[astro] 0.20210119.2.1338 u-boot source
GitOrigin-RevId: 9768d963ff46648bb8b183d8e29a7abc19f68920
Change-Id: I7546ab102cb3ee77ef262b760f9be1b9cf21536a
Reviewed-on: https://turquoise-internal-review.googlesource.com/c/third_party/u-boot/+/372314
Reviewed-by: Varun Sharma <vars@google.com>
diff --git a/board/8dtech/eco5pk/Kconfig b/board/8dtech/eco5pk/Kconfig
new file mode 100644
index 0000000..5553566
--- /dev/null
+++ b/board/8dtech/eco5pk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ECO5PK
+
+config SYS_BOARD
+ default "eco5pk"
+
+config SYS_VENDOR
+ default "8dtech"
+
+config SYS_CONFIG_NAME
+ default "eco5pk"
+
+endif
diff --git a/board/8dtech/eco5pk/MAINTAINERS b/board/8dtech/eco5pk/MAINTAINERS
new file mode 100644
index 0000000..20c1c8c
--- /dev/null
+++ b/board/8dtech/eco5pk/MAINTAINERS
@@ -0,0 +1,6 @@
+ECO5PK BOARD
+M: Raphael Assenat <raph@8d.com>
+S: Maintained
+F: board/8dtech/eco5pk/
+F: include/configs/eco5pk.h
+F: configs/eco5pk_defconfig
diff --git a/board/8dtech/eco5pk/Makefile b/board/8dtech/eco5pk/Makefile
new file mode 100644
index 0000000..3333781
--- /dev/null
+++ b/board/8dtech/eco5pk/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Adapted from ti/evm/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := eco5pk.o
diff --git a/board/8dtech/eco5pk/eco5pk.c b/board/8dtech/eco5pk/eco5pk.c
new file mode 100644
index 0000000..0f5ce7d
--- /dev/null
+++ b/board/8dtech/eco5pk/eco5pk.c
@@ -0,0 +1,49 @@
+/*
+ * eco5pk.c - board file for 8D Technology's AM3517 based eco5pk board
+ *
+ * Based on am3517evm.c
+ *
+ * Copyright (C) 2011-2012 8D Technologies inc.
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <crc.h>
+#include <asm/mach-types.h>
+#include "eco5pk.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ gpio_request(30, "RESOUT");
+ gpio_direction_output(30, 1);
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_ECO5_PK();
+}
diff --git a/board/8dtech/eco5pk/eco5pk.h b/board/8dtech/eco5pk/eco5pk.h
new file mode 100644
index 0000000..acf2b80
--- /dev/null
+++ b/board/8dtech/eco5pk/eco5pk.h
@@ -0,0 +1,392 @@
+/*
+ * eco5.h - Header file for the 8D Technologies ECO5 board.
+ *
+ * Based on am3517evm.h
+ * Based on ti/evm/evm.h
+ *
+ * Copyright (C) 2011 8D Technologies inc.
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ECO5PK_H__
+#define _ECO5PK_H__
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "ECO5 Board",
+ "NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_ECO5_PK() \
+ /* SDRC */\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_CKE0), (M0)) \
+ MUX_VAL(CP(SDRC_CKE1), (M0)) \
+ MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
+ /* GPMC */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M3)) \
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | DIS | M4)) \
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
+ /* - ETH_nRESET*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
+ /* DSS */\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA0), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA1), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA3), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA4), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA5), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA6), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA7), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | EN | M4)) \
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
+ /* CAMERA */\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ /* - CAM_RESET*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
+ /* MMC */\
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
+ \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \
+ /* McBSP */\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /* LED ACT */ \
+ \
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+ /* - LCD_INI*/\
+ MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+ /* - LCD_ENVDD */\
+ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+ /* - LCD_QVGA/nVGA */\
+ MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+ /* - LCD_RESB */\
+ /* UART */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
+ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
+ /* I2C */\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
+ /* McSPI */\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
+ /* - LAN_INTR*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \
+ \
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
+ /* LCD_EN_BACKLIGHT */\
+ MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | EN | M4)) \
+ /* CCDC */\
+ MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
+ /* RMII */\
+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
+ MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
+ MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
+ /* HECC */\
+ MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
+ /* HSUSB */\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
+ /* HDQ */\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \
+ /* Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
+ /* SYS_nRESWARM */\
+ MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
+ /* - GPIO30 */\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
+ /* - PEN_IRQ */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /* GPIO_8 */\
+ /* - VIO_1V8*/\
+ MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
+ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
+ /* JTAG */\
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
+ /* ETK (ES2 onwards) */\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \
+ /* Die to Die */\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))
+
+#endif
diff --git a/board/AndesTech/adp-ag101/Kconfig b/board/AndesTech/adp-ag101/Kconfig
new file mode 100644
index 0000000..8f0197a
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_ADP_AG101
+
+config SYS_CPU
+ default "n1213"
+
+config SYS_BOARD
+ default "adp-ag101"
+
+config SYS_VENDOR
+ default "AndesTech"
+
+config SYS_SOC
+ default "ag101"
+
+config SYS_CONFIG_NAME
+ default "adp-ag101"
+
+endif
diff --git a/board/AndesTech/adp-ag101/MAINTAINERS b/board/AndesTech/adp-ag101/MAINTAINERS
new file mode 100644
index 0000000..1f0169b
--- /dev/null
+++ b/board/AndesTech/adp-ag101/MAINTAINERS
@@ -0,0 +1,6 @@
+ADP-AG101 BOARD
+M: Andes <uboot@andestech.com>
+S: Maintained
+F: board/AndesTech/adp-ag101/
+F: include/configs/adp-ag101.h
+F: configs/adp-ag101_defconfig
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 0000000..4cc590f
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := adp-ag101.o
diff --git a/board/AndesTech/adp-ag101/README b/board/AndesTech/adp-ag101/README
new file mode 100644
index 0000000..46fc637
--- /dev/null
+++ b/board/AndesTech/adp-ag101/README
@@ -0,0 +1,74 @@
+Andes Technology SoC AG101
+==========================
+
+AG101 is the first SoC produced by Andes Technology using N1213 CPU core.
+AG101 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+ADP-AG101
+=========
+
+ADP-AG101 is the SoC with AG101 hardcore CPU.
+
+Please check http://www.andestech.com/p2-4.htm for detail of this SoC.
+
+Configurations
+==============
+
+CONFIG_MEM_REMAP:
+ Doing memory remap is essential for preparing some non-OS or RTOS
+ applications.
+
+ This is also a must on ADP-AG101 board.
+ (While other boards may not have this problem).
+
+ The reason is because the ROM/FLASH circuit on PCB board.
+ AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+ ROM/FLASH is used to boot.
+
+ When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+ and the FLASH is connected to BANK1.
+ When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+ and the FLASH is connected to BANK0.
+ It will occur problem when doing flash probing if the flash is at
+ BANK0 (0x00000000) while memory remapping was skipped.
+
+ Other board like ADP-AG101P may not enable this since there is only
+ a FLASH connected to bank0.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+ If you want to boot this system from FLASH and bypass e-bios (the
+ other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+ in "include/configs/adp-ag101.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag101` in u-boot root to build the image.
+
+burn u-boot to flash:
+1. Make sure the MA17 (J16) is Lo.
+2. Make sure the dip switch SW5 is set to "0101".
+3. Power On. Press button "S1", then press button "SW1", then you will found the
+ debug LED show 67 means the system successfully booted into e-bios.
+ Now you can control the e-bios boot loader from your console.
+4. Under "Command>>" prompt, enter "97" (CopyImageFromCard)
+5. Under "Type Dir Name of [CF/SD] =>" promtp, enter "c".
+6. Under "Enter Filename =>" prompt, enter the file name of u-boot image you
+ just build. It is usually "u-boot.bin".
+7. Under "Enter Dest. Address =>" prompt, enter the memory address where you
+ want to put the binary from SD card to RAM.
+ Address "0x500000" is our suggestion.
+8. Under "Command>>" prompt again, enter "55" (CLI) to use interactive command
+ environment.
+9. Under "CLI>" prompt, enter "burn 0x500000 0x80400000 0x30000" to burn the
+ binary from RAM to FLASH.
+10. Under "CLI>" prompt, enter "exit" to finish the burn process.
+
+boot u-boot from flash:
+1. Make sure the MA17 (J16) is Hi).
+2. Make sure the dip switch SW5 is set to "1010".
+3. Power On. Press button "S1", then you will see the debug LED count to 20.
+4. Now you can use u-boot on ADP-AG101 board.
diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 0000000..9884a5b
--- /dev/null
+++ b/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+ /*
+ * refer to BOOT_PARAMETER_PA_BASE within
+ * "linux/arch/nds32/include/asm/misc_spec.h"
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+ ftsmc020_init(); /* initialize Flash */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->ram_size = actual_size;
+
+ if (expected_size != actual_size) {
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+ }
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ ftsdc010_mmc_init(0);
+ return 0;
+}
diff --git a/board/AndesTech/adp-ag101p/Kconfig b/board/AndesTech/adp-ag101p/Kconfig
new file mode 100644
index 0000000..5e8aa22
--- /dev/null
+++ b/board/AndesTech/adp-ag101p/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_ADP_AG101P
+
+config SYS_CPU
+ default "n1213"
+
+config SYS_BOARD
+ default "adp-ag101p"
+
+config SYS_VENDOR
+ default "AndesTech"
+
+config SYS_SOC
+ default "ag101"
+
+config SYS_CONFIG_NAME
+ default "adp-ag101p"
+
+endif
diff --git a/board/AndesTech/adp-ag101p/MAINTAINERS b/board/AndesTech/adp-ag101p/MAINTAINERS
new file mode 100644
index 0000000..9a2c7a3
--- /dev/null
+++ b/board/AndesTech/adp-ag101p/MAINTAINERS
@@ -0,0 +1,6 @@
+ADP-AG101P BOARD
+M: Andes <uboot@andestech.com>
+S: Maintained
+F: board/AndesTech/adp-ag101p/
+F: include/configs/adp-ag101p.h
+F: configs/adp-ag101p_defconfig
diff --git a/board/AndesTech/adp-ag101p/Makefile b/board/AndesTech/adp-ag101p/Makefile
new file mode 100644
index 0000000..2ba7da4
--- /dev/null
+++ b/board/AndesTech/adp-ag101p/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := adp-ag101p.o
diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c
new file mode 100644
index 0000000..dd8a6653
--- /dev/null
+++ b/board/AndesTech/adp-ag101p/adp-ag101p.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+ /*
+ * refer to BOOT_PARAMETER_PA_BASE within
+ * "linux/arch/nds32/include/asm/misc_spec.h"
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+ ftsmc020_init(); /* initialize Flash */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->ram_size = actual_size;
+
+ if (expected_size != actual_size) {
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+ }
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ ftsdc010_mmc_init(0);
+ return 0;
+}
diff --git a/board/AndesTech/adp-ag102/Kconfig b/board/AndesTech/adp-ag102/Kconfig
new file mode 100644
index 0000000..fc17be3
--- /dev/null
+++ b/board/AndesTech/adp-ag102/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_ADP_AG102
+
+config SYS_CPU
+ default "n1213"
+
+config SYS_BOARD
+ default "adp-ag102"
+
+config SYS_VENDOR
+ default "AndesTech"
+
+config SYS_SOC
+ default "ag102"
+
+config SYS_CONFIG_NAME
+ default "adp-ag102"
+
+endif
diff --git a/board/AndesTech/adp-ag102/MAINTAINERS b/board/AndesTech/adp-ag102/MAINTAINERS
new file mode 100644
index 0000000..94b87c7
--- /dev/null
+++ b/board/AndesTech/adp-ag102/MAINTAINERS
@@ -0,0 +1,6 @@
+ADP-AG102 BOARD
+M: Andes <uboot@andestech.com>
+S: Maintained
+F: board/AndesTech/adp-ag102/
+F: include/configs/adp-ag102.h
+F: configs/adp-ag102_defconfig
diff --git a/board/AndesTech/adp-ag102/Makefile b/board/AndesTech/adp-ag102/Makefile
new file mode 100644
index 0000000..fc4bf88
--- /dev/null
+++ b/board/AndesTech/adp-ag102/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := adp-ag102.o
diff --git a/board/AndesTech/adp-ag102/adp-ag102.c b/board/AndesTech/adp-ag102/adp-ag102.c
new file mode 100644
index 0000000..3f879ab
--- /dev/null
+++ b/board/AndesTech/adp-ag102/adp-ag102.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftpci100.h>
+#include <faraday/ftsdc010.h>
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+ /*
+ * refer to BOOT_PARAMETER_PA_BASE within
+ * "linux/arch/nds32/include/asm/misc_spec.h"
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_ADPAG102;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+ ftsmc020_init(); /* initialize Flash */
+#endif /* CONFIG_SYS_NO_FLASH */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->ram_size = actual_size;
+
+ if (expected_size != actual_size) {
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftgmac100_initialize(bd);
+}
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+void pci_init_board(void)
+{
+ /* should be pci_ftpci100_init() */
+ pci_ftpci_init();
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ ftsdc010_mmc_init(0);
+ return 0;
+}
+#endif
diff --git a/board/Barix/ipam390/Kconfig b/board/Barix/ipam390/Kconfig
new file mode 100644
index 0000000..b85d4da
--- /dev/null
+++ b/board/Barix/ipam390/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IPAM390
+
+config SYS_BOARD
+ default "ipam390"
+
+config SYS_VENDOR
+ default "Barix"
+
+config SYS_CONFIG_NAME
+ default "ipam390"
+
+endif
diff --git a/board/Barix/ipam390/MAINTAINERS b/board/Barix/ipam390/MAINTAINERS
new file mode 100644
index 0000000..640e34f
--- /dev/null
+++ b/board/Barix/ipam390/MAINTAINERS
@@ -0,0 +1,6 @@
+IPAM390 BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: board/Barix/ipam390/
+F: include/configs/ipam390.h
+F: configs/ipam390_defconfig
diff --git a/board/Barix/ipam390/Makefile b/board/Barix/ipam390/Makefile
new file mode 100644
index 0000000..1cb4b57
--- /dev/null
+++ b/board/Barix/ipam390/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ipam390.o
diff --git a/board/Barix/ipam390/README.ipam390 b/board/Barix/ipam390/README.ipam390
new file mode 100644
index 0000000..5c45fca
--- /dev/null
+++ b/board/Barix/ipam390/README.ipam390
@@ -0,0 +1,229 @@
+Summary
+=======
+The README is for the boot procedure on the ipam390 board
+
+In the context of U-Boot, the board is booted in three stages. The initial
+bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits
+in the internal ROM. The RBL initializes the internal memory and then
+depending on the exact board and pin configurations will initialize another
+controller (such as NAND) to continue the boot process by loading
+the secondary program loader (SPL). The SPL will initialize the system
+further (some clocks, SDRAM). As on this board is used the falcon boot
+mode, now 2 ways are possible depending on the GPIO 7_14 input pin,
+connected with the "soft reset switch"
+
+If this pin is logical 1 (high level):
+spl code starts the kernel image without delay
+
+If this pin is logical 0 (low level):
+spl code starts the u-boot image
+
+AIS is an image format defined by TI for the images that are to be loaded
+to memory by the RBL. The image is divided into a series of sections and
+the image's entry point is specified. Each section comes with meta data
+like the target address the section is to be copied to and the size of the
+section, which is used by the RBL to load the image. At the end of the
+image the RBL jumps to the image entry point. The AIS format allows for
+other things such as programming the clocks and SDRAM if the header is
+programmed for it. We do not take advantage of this and instead use SPL as
+it allows for additional flexibility (run-time detect of board revision,
+loading the next image from a different media, etc).
+
+Compilation
+===========
+run "./MAKEALL ipam390" in the u-boot source tree.
+Once this build completes you will have a u-boot.ais file that needs to
+be written to the nand flash.
+
+Flashing the images to NAND
+==========================
+The AIS image can be written to NAND flash using the following commands.
+Assuming that the network is configured and enabled and the u-boot.ais file
+is tftp'able.
+
+U-Boot > print upd_uboot
+upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;nand write c0000000 20000 ${filesize}
+U-Boot >
+U-Boot > run upd_uboot
+Using DaVinci-EMAC device
+TFTP from server 192.168.1.1; our IP address is 192.168.20.71
+Filename '/tftpboot/ipam390/u-boot.ais'.
+Load address: 0xc0000000
+Loading: ##################################
+ 1.5 MiB/s
+done
+Bytes transferred = 493716 (78894 hex)
+
+NAND erase.part: device 0 offset 0x20000, size 0x160000
+Erasing at 0x160000 -- 100% complete.
+OK
+
+NAND write: device 0 offset 0x20000, size 0x78894
+ 493716 bytes written: OK
+U-Boot >
+
+Recovery
+========
+
+In the case of a "bricked" board, you need to use the TI tools found
+here[1] to create an uboot-uart-ais.bin file
+
+- cd to the u-boot source tree
+
+- compile the u-boot for the ipam390 board:
+$ ./MAKEALL ipam390
+
+ -> Now we shall have u-boot.bin
+
+- Create u-boot-uart-ais.bin
+$ mono HexAIS_OMAP-L138.exe -entrypoint 0xC1080000 -ini
+ipam390-ais-uart.cfg -o ./uboot-uart-ais.bin ./u-boot.bin@0xC1080000;
+
+Note: The ipam390-ais-uart.cfg is found in the board directory
+for the ipam390 board, u-boot:/board/Barix/ipam390/ipam390-ais-uart.cfg
+
+- We can now run bootloader on IPAM390 via UART using the command below:
+
+$ mono ./slh_OMAP-L138.exe -waitForDevice -v -p /dev/tty.UC-232AC uboot-uart-ais.bin
+NOTE: Do not cancel the command execution! The command takes 20+ seconds
+to upload u-boot over serial and run it!
+Outcome:
+Waiting for the OMAP-L138...
+(AIS Parse): Read magic word 0x41504954.
+(AIS Parse): Waiting for BOOTME... (power on or reset target now)
+(AIS Parse): BOOTME received!
+(AIS Parse): Performing Start-Word Sync...
+(AIS Parse): Performing Ping Opcode Sync...
+(AIS Parse): Processing command 0: 0x5853590D.
+(AIS Parse): Performing Opcode Sync...
+(AIS Parse): Executing function...
+(AIS Parse): Processing command 1: 0x5853590D.
+(AIS Parse): Performing Opcode Sync...
+(AIS Parse): Executing function...
+(AIS Parse): Processing command 2: 0x5853590D.
+(AIS Parse): Performing Opcode Sync...
+(AIS Parse): Executing function...
+(AIS Parse): Processing command 3: 0x5853590D.
+(AIS Parse): Performing Opcode Sync...
+(AIS Parse): Executing function...
+(AIS Parse): Processing command 4: 0x5853590D.
+(AIS Parse): Performing Opcode Sync...
+(AIS Parse): Executing function...
+(AIS Parse): Processing command 5: 0x58535901.
+(AIS Parse): Performing Opcode Sync...
+(AIS Parse): Loading section...
+(AIS Parse): Loaded 326516-Byte section to address 0xC1080000.
+(AIS Parse): Processing command 6: 0x58535906.
+(AIS Parse): Performing Opcode Sync...
+(AIS Parse): Performing jump and close...
+(AIS Parse): AIS complete. Jump to address 0xC1080000.
+(AIS Parse): Waiting for DONE...
+(AIS Parse): Boot completed successfully.
+
+Operation completed successfully.
+
+Falcon Bootmode (boot linux without booting U-Boot)
+===================================================
+
+The Falcon Mode extends this way allowing to start the Linux kernel directly
+from SPL. A new command is added to U-Boot to prepare the parameters that SPL
+must pass to the kernel, using ATAGS or Device Tree.
+
+In normal mode, these parameters are generated each time before
+loading the kernel, passing to Linux the address in memory where
+the parameters can be read.
+With Falcon Mode, this snapshot can be saved into persistent storage and SPL is
+informed to load it before running the kernel.
+
+To boot the kernel, these steps under a Falcon-aware U-Boot are required:
+
+1. Boot the board into U-Boot.
+Use the "spl export" command to generate the kernel parameters area or the DT.
+U-Boot runs as when it boots the kernel, but stops before passing the control
+to the kernel.
+
+Here the command sequence for the ipam390 board:
+- load the linux kernel image into ram:
+
+U-Boot > nand read c0100000 2 200000 400000
+
+NAND read: device 0 offset 0x200000, size 0x400000
+ 4194304 bytes read: OK
+
+- generate the bootparms image:
+
+U-Boot > spl export atags c0100000
+## Booting kernel from Legacy Image at c0100000 ...
+ Image Name: Linux-3.5.1
+ Image Type: ARM Linux Kernel Image (uncompressed)
+ Data Size: 2504280 Bytes = 2.4 MiB
+ Load Address: c0008000
+ Entry Point: c0008000
+ Verifying Checksum ... OK
+ Loading Kernel Image ... OK
+subcommand not supported
+subcommand not supported
+Argument image is now in RAM at: 0xc0000100
+
+- copy the bootparms image into nand:
+
+U-Boot > mtdparts
+
+device nand0 <davinci_nand.0>, # parts = 6
+ #: name size offset mask_flags
+ 0: u-boot-env 0x00020000 0x00000000 0
+ 1: u-boot 0x00160000 0x00020000 0
+ 2: bootparms 0x00020000 0x00180000 0
+ 3: factory-info 0x00060000 0x001a0000 0
+ 4: kernel 0x00400000 0x00200000 0
+ 5: rootfs 0x07a00000 0x00600000 0
+
+active partition: nand0,0 - (u-boot-env) 0x00020000 @ 0x00000000
+
+defaults:
+mtdids : nand0=davinci_nand.0
+mtdparts: mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs)
+U-Boot > nand erase.part bootparms
+
+NAND erase.part: device 0 offset 0x180000, size 0x20000
+Erasing at 0x180000 -- 100% complete.
+OK
+U-Boot > nand write c0000100 180000 20000
+
+NAND write: device 0 offset 0x180000, size 0x20000
+ 131072 bytes written: OK
+U-Boot >
+
+You can use also the predefined U-Boot Environment variable "setbootparms",
+which will do all the above steps in one command:
+
+U-Boot > print setbootparms
+setbootparms=nand read c0100000 200000 400000;spl export atags c0100000;nand erase.part bootparms;nand write c0000100 180000 20000
+U-Boot > run setbootparms
+
+NAND read: device 0 offset 0x200000, size 0x400000
+ 4194304 bytes read: OK
+## Booting kernel from Legacy Image at c0100000 ...
+ Image Name: Linux-3.5.1
+ Image Type: ARM Linux Kernel Image (uncompressed)
+ Data Size: 2504280 Bytes = 2.4 MiB
+ Load Address: c0008000
+ Entry Point: c0008000
+ Verifying Checksum ... OK
+ Loading Kernel Image ... OK
+subcommand not supported
+subcommand not supported
+Argument image is now in RAM at: 0xc0000100
+
+NAND erase.part: device 0 offset 0x180000, size 0x20000
+Erasing at 0x180000 -- 100% complete.
+OK
+
+NAND write: device 0 offset 0x180000, size 0x20000
+ 131072 bytes written: OK
+U-Boot >
+
+Links
+=====
+[1]
+ http://sourceforge.net/projects/dvflashutils/files/OMAP-L138/
diff --git a/board/Barix/ipam390/ipam390-ais-uart.cfg b/board/Barix/ipam390/ipam390-ais-uart.cfg
new file mode 100644
index 0000000..709cf23
--- /dev/null
+++ b/board/Barix/ipam390/ipam390-ais-uart.cfg
@@ -0,0 +1,202 @@
+; General settings that can be overwritten in the host code
+; that calls the AISGen library.
+[General]
+
+; Can be 8 or 16 - used in emifa
+busWidth=8
+
+; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW
+BootMode=UART
+
+; 8,16,24 - used for SPI,I2C
+;AddrWidth=8
+
+; NO_CRC,SECTION_CRC,SINGLE_CRC
+crcCheckType=NO_CRC
+
+; This section allows setting the PLL0 system clock with a
+; specified multiplier and divider as shown. The clock source
+; can also be chosen for internal or external.
+; |------24|------16|-------8|-------0|
+; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV|
+; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7|
+;[PLL0CONFIG]
+;PLL0CFG0 = 0x00180001
+;PLL0CFG1 = 0x00000205
+
+[PLLANDCLOCKCONFIG]
+PLL0CFG0 = 0x00180001
+PLL0CFG1 = 0x00000205
+PERIPHCLKCFG = 0x00000051
+
+; This section allows setting up the PLL1. Usually this will
+; take place as part of the EMIF3a DDR setup. The format of
+; the input args is as follows:
+; |------24|------16|-------8|-------0|
+; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
+; PLL1CFG1: | RSVD | PLLDIV3|
+[PLL1CONFIG]
+PLL1CFG0 = 0x18010001
+PLL1CFG1 = 0x00000002
+
+; This section lets us configure the peripheral interface
+; of the current booting peripheral (I2C, SPI, or UART).
+; Use with caution. The format of the PERIPHCLKCFG field
+; is as follows:
+; SPI: |------24|------16|-------8|-------0|
+; | RSVD |PRESCALE|
+;
+; I2C: |------24|------16|-------8|-------0|
+; | RSVD |PRESCALE| CLKL | CLKH |
+;
+; UART: |------24|------16|-------8|-------0|
+; | RSVD | OSR | DLH | DLL |
+[PERIPHCLKCFG]
+PERIPHCLKCFG = 0x00000051
+
+; This section can be used to configure the PLL1 and the EMIF3a registers
+; for starting the DDR2 interface.
+; See PLL1CONFIG section for the format of the PLL1CFG fields.
+; |------24|------16|-------8|-------0|
+; PLL1CFG0: | PLL1CFG |
+; PLL1CFG1: | PLL1CFG |
+; DDRPHYC1R: | DDRPHYC1R |
+; SDCR: | SDCR |
+; SDTIMR: | SDTIMR |
+; SDTIMR2: | SDTIMR2 |
+; SDRCR: | SDRCR |
+; CLK2XSRC: | CLK2XSRC |
+[EMIF3DDR]
+PLL1CFG0 = 0x18010001
+PLL1CFG1 = 0x00000002
+DDRPHYC1R = 0x000000C2
+SDCR = 0x0017C432
+SDTIMR = 0x26922A09
+SDTIMR2 = 0x4414C722
+SDRCR = 0x00000498
+CLK2XSRC = 0x00000000
+
+; This section can be used to configure the EMIFA to use
+; CS0 as an SDRAM interface. The fields required to do this
+; are given below.
+; |------24|------16|-------8|-------0|
+; SDBCR: | SDBCR |
+; SDTIMR: | SDTIMR |
+; SDRSRPDEXIT: | SDRSRPDEXIT |
+; SDRCR: | SDRCR |
+; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE |
+;[EMIF25SDRAM]
+;SDBCR = 0x00004421
+;SDTIMR = 0x42215810
+;SDRSRPDEXIT = 0x00000009
+;SDRCR = 0x00000410
+;DIV4p5_CLK_ENABLE = 0x00000001
+
+; This section can be used to configure the async chip selects
+; of the EMIFA (CS2-CS5). The fields required to do this
+; are given below.
+; |------24|------16|-------8|-------0|
+; A1CR: | A1CR |
+; A2CR: | A2CR |
+; A3CR: | A3CR |
+; A4CR: | A4CR |
+; NANDFCR: | NANDFCR |
+;[EMIF25ASYNC]
+;A1CR = 0x00000000
+;A2CR = 0x00000000
+;A3CR = 0x00000000
+;A4CR = 0x00000000
+;NANDFCR = 0x00000000
+[EMIF25ASYNC]
+A1CR = 0x00000000
+A2CR = 0x04202110
+A3CR = 0x00000000
+A4CR = 0x00000000
+NANDFCR = 0x00000012
+
+; This section should be used in place of PLL0CONFIG when
+; the I2C, SPI, or UART modes are being used. This ensures that
+; the system PLL and the peripheral's clocks are changed together.
+; See PLL0CONFIG section for the format of the PLL0CFG fields.
+; See PERIPHCLKCFG section for the format of the CLKCFG field.
+; |------24|------16|-------8|-------0|
+; PLL0CFG0: | PLL0CFG |
+; PLL0CFG1: | PLL0CFG |
+; PERIPHCLKCFG: | CLKCFG |
+;[PLLANDCLOCKCONFIG]
+;PLL0CFG0 = 0x00180001
+;PLL0CFG1 = 0x00000205
+;PERIPHCLKCFG = 0x00010032
+
+; This section should be used to setup the power state of modules
+; of the two PSCs. This section can be included multiple times to
+; allow the configuration of any or all of the device modules.
+; |------24|------16|-------8|-------0|
+; LPSCCFG: | PSCNUM | MODULE | PD | STATE |
+;[PSCCONFIG]
+;LPSCCFG=
+
+; This section allows setting of a single PINMUX register.
+; This section can be included multiple times to allow setting
+; as many PINMUX registers as needed.
+; |------24|------16|-------8|-------0|
+; REGNUM: | regNum |
+; MASK: | mask |
+; VALUE: | value |
+;[PINMUX]
+;REGNUM = 5
+;MASK = 0x00FF0000
+;VALUE = 0x00880000
+
+; No Params required - simply include this section for the fast boot
+; function to be called
+;[FASTBOOT]
+
+; This section allows setting up the PLL1. Usually this will
+; take place as part of the EMIF3a DDR setup. The format of
+; the input args is as follows:
+; |------24|------16|-------8|-------0|
+; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
+; PLL1CFG1: | RSVD | PLLDIV3|
+;[PLL1CONFIG]
+;PLL1CFG0 = 0x15010001
+;PLL1CFG1 = 0x00000002
+
+; This section can be used to configure the PLL1 and the EMIF3a registers
+; for starting the DDR2 interface on ARM-boot D800K002 devices.
+; |------24|------16|-------8|-------0|
+; DDRPHYC1R: | DDRPHYC1R |
+; SDCR: | SDCR |
+; SDTIMR: | SDTIMR |
+; SDTIMR2: | SDTIMR2 |
+; SDRCR: | SDRCR |
+; CLK2XSRC: | CLK2XSRC |
+;[ARM_EMIF3DDR_PATCHFXN]
+;DDRPHYC1R = 0x000000C2
+;SDCR = 0x0017C432
+;SDTIMR = 0x26922A09
+;SDTIMR2 = 0x4414C722
+;SDRCR = 0x00000498
+;CLK2XSRC = 0x00000000
+
+; This section can be used to configure the PLL1 and the EMIF3a registers
+; for starting the DDR2 interface on DSP-boot D800K002 devices.
+; |------24|------16|-------8|-------0|
+; DDRPHYC1R: | DDRPHYC1R |
+; SDCR: | SDCR |
+; SDTIMR: | SDTIMR |
+; SDTIMR2: | SDTIMR2 |
+; SDRCR: | SDRCR |
+; CLK2XSRC: | CLK2XSRC |
+;[DSP_EMIF3DDR_PATCHFXN]
+;DDRPHYC1R = 0x000000C4
+;SDCR = 0x08134632
+;SDTIMR = 0x26922A09
+;SDTIMR2 = 0x0014C722
+;SDRCR = 0x00000492
+;CLK2XSRC = 0x00000000
+
+;[INPUTFILE]
+;FILENAME=u-boot.bin
+;LOADADDRESS=0xC1080000
+;ENTRYPOINTADDRESS=0xC1080000
diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c
new file mode 100644
index 0000000..6ce8960
--- /dev/null
+++ b/board/Barix/ipam390/ipam390.c
@@ -0,0 +1,337 @@
+/*
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ * Based on:
+ * U-Boot:board/davinci/da8xxevm/da850evm.c
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/arch/pinmux_defs.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <hwconfig.h>
+#include <bootstage.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define HAS_RMII 1
+#else
+#define HAS_RMII 0
+#endif
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+void dsp_lpsc_on(unsigned domain, unsigned int id)
+{
+ dv_reg_p mdstat, mdctl, ptstat, ptcmd;
+ struct davinci_psc_regs *psc_regs;
+
+ psc_regs = davinci_psc0_regs;
+ mdstat = &psc_regs->psc0.mdstat[id];
+ mdctl = &psc_regs->psc0.mdctl[id];
+ ptstat = &psc_regs->ptstat;
+ ptcmd = &psc_regs->ptcmd;
+
+ while (*ptstat & (0x1 << domain))
+ ;
+
+ if ((*mdstat & 0x1f) == 0x03)
+ return; /* Already on and enabled */
+
+ *mdctl |= 0x03;
+
+ *ptcmd = 0x1 << domain;
+
+ while (*ptstat & (0x1 << domain))
+ ;
+ while ((*mdstat & 0x1f) != 0x03)
+ ; /* Probably an overkill... */
+}
+
+static void dspwake(void)
+{
+ unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
+ u32 val;
+
+ /* if the device is ARM only, return */
+ if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
+ return;
+
+ if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
+ return;
+
+ *resetvect++ = 0x1E000; /* DSP Idle */
+ /* clear out the next 10 words as NOP */
+ memset(resetvect, 0, sizeof(unsigned) * 10);
+
+ /* setup the DSP reset vector */
+ writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
+
+ dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
+ val = readl(PSC0_MDCTL + (15 * 4));
+ val |= 0x100;
+ writel(val, (PSC0_MDCTL + (15 * 4)));
+}
+
+int misc_init_r(void)
+{
+ dspwake();
+ return 0;
+}
+
+static const struct pinmux_config gpio_pins[] = {
+ /* GP7[14] selects bootmode*/
+ { pinmux(16), 8, 3 }, /* GP7[14] */
+};
+
+const struct pinmux_resource pinmuxes[] = {
+#ifdef CONFIG_DRIVER_TI_EMAC
+ PINMUX_ITEM(emac_pins_mdio),
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+ PINMUX_ITEM(emac_pins_rmii),
+#else
+ PINMUX_ITEM(emac_pins_mii),
+#endif
+#endif
+ PINMUX_ITEM(uart2_pins_txrx),
+ PINMUX_ITEM(uart2_pins_rtscts),
+ PINMUX_ITEM(uart0_pins_txrx),
+ PINMUX_ITEM(uart0_pins_rtscts),
+#ifdef CONFIG_NAND_DAVINCI
+ PINMUX_ITEM(emifa_pins_cs3),
+ PINMUX_ITEM(emifa_pins_nand),
+#endif
+ PINMUX_ITEM(gpio_pins),
+};
+
+const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
+
+const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
+ { DAVINCI_LPSC_EMAC }, /* image download */
+ { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_UART0 }, /* console */
+ { DAVINCI_LPSC_GPIO },
+};
+
+const int lpsc_size = ARRAY_SIZE(lpsc);
+
+#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
+#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
+#endif
+
+#define REV_AM18X_EVM 0x100
+
+/*
+ * get_board_rev() - setup to pass kernel board revision information
+ * Returns:
+ * bit[0-3] Maximum cpu clock rate supported by onboard SoC
+ * 0000b - 300 MHz
+ * 0001b - 372 MHz
+ * 0010b - 408 MHz
+ * 0011b - 456 MHz
+ */
+u32 get_board_rev(void)
+{
+ char *s;
+ u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
+ u32 rev = 0;
+
+ s = getenv("maxcpuclk");
+ if (s)
+ maxcpuclk = simple_strtoul(s, NULL, 10);
+
+ if (maxcpuclk >= 456000000)
+ rev = 3;
+ else if (maxcpuclk >= 408000000)
+ rev = 2;
+ else if (maxcpuclk >= 372000000)
+ rev = 1;
+#ifdef CONFIG_DA850_AM18X_EVM
+ rev |= REV_AM18X_EVM;
+#endif
+ return rev;
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * Power on required peripherals
+ * ARM does not have access by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+ return 1;
+
+ return 0;
+}
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+ irq_init();
+#endif
+
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ writel(readl(&davinci_syscfg_regs->suspsrc) &
+ ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART0),
+ &davinci_syscfg_regs->suspsrc);
+
+ /* configure pinmux settings */
+ if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
+ return 1;
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+ davinci_emac_mii_mode_sel(HAS_RMII);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+ /* enable the console UART */
+ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+ DAVINCI_UART_PWREMU_MGMT_UTRST),
+#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
+ &davinci_uart0_ctrl_regs->pwremu_mgmt);
+#else
+ &davinci_uart2_ctrl_regs->pwremu_mgmt);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+static int init_led(int gpio, char *name, int val)
+{
+ int ret;
+
+ ret = gpio_request(gpio, name);
+ if (ret)
+ return -1;
+ ret = gpio_direction_output(gpio, val);
+ if (ret)
+ return -1;
+
+ return gpio;
+}
+
+#define LED_ON 0
+#define LED_OFF 1
+
+#if !defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int status)
+{
+ static int red;
+ static int green;
+
+ if (red == 0)
+ red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
+ if (red != CONFIG_IPAM390_GPIO_LED_RED)
+ return;
+ if (green == 0)
+ green = init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green",
+ LED_OFF);
+ if (green != CONFIG_IPAM390_GPIO_LED_GREEN)
+ return;
+
+ switch (status) {
+ case BOOTSTAGE_ID_RUN_OS:
+ /*
+ * set normal state
+ * LED Red : on
+ * LED green: off
+ */
+ gpio_set_value(red, LED_ON);
+ gpio_set_value(green, LED_OFF);
+ break;
+ case BOOTSTAGE_ID_MAIN_LOOP:
+ /*
+ * U-Boot operation
+ * LED Red : on
+ * LED green: on
+ */
+ gpio_set_value(red, LED_ON);
+ gpio_set_value(green, LED_ON);
+ break;
+ }
+}
+#endif
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ int ret;
+ int bootmode = 0;
+
+ /*
+ * GP7[14] selects bootmode:
+ * 1: boot linux
+ * 0: boot u-boot
+ * if error accessing gpio boot U-Boot
+ *
+ * SPL bootmode
+ * 0: boot linux
+ * 1: boot u-boot
+ */
+ ret = gpio_request(CONFIG_IPAM390_GPIO_BOOTMODE , "bootmode");
+ if (ret)
+ bootmode = 1;
+ if (!bootmode) {
+ ret = gpio_direction_input(CONFIG_IPAM390_GPIO_BOOTMODE);
+ if (ret)
+ bootmode = 1;
+ }
+ if (!bootmode)
+ ret = gpio_get_value(CONFIG_IPAM390_GPIO_BOOTMODE);
+ if (!bootmode)
+ if (ret == 0)
+ bootmode = 1;
+ /*
+ * LED red : on
+ * LED green: off
+ */
+ init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON);
+ init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF);
+ return bootmode;
+}
+#endif
diff --git a/board/Barix/ipam390/u-boot-spl-ipam390.lds b/board/Barix/ipam390/u-boot-spl-ipam390.lds
new file mode 100644
index 0000000..5f290ec
--- /dev/null
+++ b/board/Barix/ipam390/u-boot-spl-ipam390.lds
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ __start = .;
+ *(.vectors)
+ arch/arm/cpu/arm926ejs/start.o (.text*)
+ *(.text*)
+ } >.sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ . = ALIGN(4);
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ } >.sram
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } >.sram
+
+ __image_copy_end = .;
+
+ .end :
+ {
+ *(.__end)
+ } >.sram
+}
diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h
new file mode 100644
index 0000000..15225b0
--- /dev/null
+++ b/board/BuR/common/bur_common.h
@@ -0,0 +1,22 @@
+/*
+ * bur_comon.h
+ *
+ * common board information header for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BUR_COMMON_H_
+#define _BUR_COMMON_H_
+
+void blink(u32 blinks, u32 intervall, u32 pin);
+void pmicsetup(u32 mpupll);
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+int board_eth_init(bd_t *bis);
+
+#endif
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
new file mode 100644
index 0000000..25cbe62
--- /dev/null
+++ b/board/BuR/common/common.c
@@ -0,0 +1,223 @@
+/*
+ * common.c
+ *
+ * common board functions for B&R boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include "bur_common.h"
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+/* --------------------------------------------------------------------------*/
+void blink(u32 blinks, u32 intervall, u32 pin)
+{
+ gpio_direction_output(pin, 0);
+ int val = 0;
+
+ do {
+ val ^= 0x01;
+ gpio_set_value(pin, val);
+ mdelay(intervall);
+ } while (blinks--);
+
+ gpio_set_value(pin, 0);
+}
+#ifdef CONFIG_SPL_BUILD
+void pmicsetup(u32 mpupll)
+{
+ int mpu_vdd;
+ int usb_cur_lim;
+
+ /* setup I2C */
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ if (i2c_probe(TPS65217_CHIP_PM)) {
+ puts("PMIC (0x24) not found! skip further initalization.\n");
+ return;
+ }
+
+ /* Get the frequency which is defined by device fuses */
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+ printf("detected max. frequency: %d - ", dpll_mpu_opp100.m);
+
+ if (0 != mpupll) {
+ dpll_mpu_opp100.m = MPUPLL_M_1000;
+ printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m);
+ } else {
+ puts("ok.\n");
+ }
+ /*
+ * Increase USB current limit to 1300mA or 1800mA and set
+ * the MPU voltage controller as needed.
+ */
+ if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+ } else {
+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+ }
+
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
+ usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+ puts("tps65217_reg_write failure\n");
+
+ /* Set DCDC3 (CORE) voltage to 1.125V */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+ TPS65217_DCDC_VOLT_SEL_1125MV)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set DCDC2 (MPU) voltage */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+
+ /* Set LDO3 to 1.8V */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+ TPS65217_DEFLS1,
+ TPS65217_LDO_VOLTAGE_OUT_1_8,
+ TPS65217_LDO_MASK))
+ puts("tps65217_reg_write failure\n");
+ /* Set LDO4 to 3.3V */
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+ TPS65217_DEFLS2,
+ TPS65217_LDO_VOLTAGE_OUT_3_3,
+ TPS65217_LDO_MASK))
+ puts("tps65217_reg_write failure\n");
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+#endif /* CONFIG_SPL_BUILD */
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+ return;
+}
+
+/* describing port offsets of TI's CPSW block */
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 1,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 2,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif /* CONFIG_DRIVER_TI_CPSW, ... */
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+
+int board_eth_init(bd_t *bis)
+{
+ int rv = 0;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC ... ");
+
+ if (is_valid_ether_addr(mac_addr)) {
+ printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n",
+ mac_addr[0], mac_addr[1], mac_addr[2],
+ mac_addr[3], mac_addr[4], mac_addr[5]
+ );
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+ }
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
+ cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0) {
+ printf("Error %d registering CPSW switch\n", rv);
+ return 0;
+ }
+#endif /* CONFIG_DRIVER_TI_CPSW, ... */
+ return rv;
+}
+#endif /* CONFIG_DRIVER_TI_CPSW */
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(1, 0, 0, -1, -1);
+}
+#endif
diff --git a/board/BuR/kwb/Kconfig b/board/BuR/kwb/Kconfig
new file mode 100644
index 0000000..4beefbf
--- /dev/null
+++ b/board/BuR/kwb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_KWB
+
+config SYS_BOARD
+ default "kwb"
+
+config SYS_VENDOR
+ default "BuR"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "kwb"
+
+endif
diff --git a/board/BuR/kwb/MAINTAINERS b/board/BuR/kwb/MAINTAINERS
new file mode 100644
index 0000000..c28fb49
--- /dev/null
+++ b/board/BuR/kwb/MAINTAINERS
@@ -0,0 +1,6 @@
+KWB BOARD
+M: Hannes Petermaier <hannes.petermaier@br-automation.com>
+S: Maintained
+F: board/BuR/kwb/
+F: include/configs/kwb.h
+F: configs/kwb_defconfig
diff --git a/board/BuR/kwb/Makefile b/board/BuR/kwb/Makefile
new file mode 100644
index 0000000..7b04b26
--- /dev/null
+++ b/board/BuR/kwb/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile
+#
+# Copyright (C) 2014 Hannes Petermaier <oe5hpm@oevsv.at> -
+# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) += mux.o
+obj-y += ../common/common.o
+obj-y += board.o
diff --git a/board/BuR/kwb/board.c b/board/BuR/kwb/board.c
new file mode 100644
index 0000000..804765a
--- /dev/null
+++ b/board/BuR/kwb/board.c
@@ -0,0 +1,240 @@
+/*
+ * board.c
+ *
+ * Board functions for B&R KWB Board
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+
+/* -------------------------------------------------------------------------*/
+/* -- defines for used GPIO Hardware -- */
+#define KEY (0+4)
+#define LCD_PWR (0+5)
+#define PUSH_KEY (0+31)
+#define USB2SD_NRST (32+29)
+#define USB2SD_PWR (96+13)
+/* -------------------------------------------------------------------------*/
+/* -- PSOC Resetcontroller Register defines -- */
+
+/* I2C Address of controller */
+#define RSTCTRL_ADDR 0x75
+/* Register for CTRL-word */
+#define RSTCTRL_CTRLREG 0x01
+/* Register for giving some information to VxWorks OS */
+#define RSTCTRL_SCRATCHREG 0x04
+
+/* -- defines for RSTCTRL_CTRLREG -- */
+#define RSTCTRL_FORCE_PWR_NEN 0x0404
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ unsigned int oldspeed;
+ unsigned short buf;
+
+ struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
+ struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+ /*
+ * enable additional clocks of modules which are accessed later from
+ * VxWorks OS
+ */
+ u32 *const clk_domains[] = { 0 };
+
+ u32 *const clk_modules_kwbspecific[] = {
+ &cmwkup->wkup_adctscctrl,
+ &cmper->spi1clkctrl,
+ &cmper->dcan0clkctrl,
+ &cmper->dcan1clkctrl,
+ &cmper->epwmss0clkctrl,
+ &cmper->epwmss1clkctrl,
+ &cmper->epwmss2clkctrl,
+ 0
+ };
+ do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
+
+ /* power-OFF LCD-Display */
+ gpio_direction_output(LCD_PWR, 0);
+
+ /* setup I2C */
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ /* power-ON 3V3 via Resetcontroller */
+ oldspeed = i2c_get_bus_speed();
+ if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
+ buf = RSTCTRL_FORCE_PWR_NEN;
+ i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
+ (uint8_t *)&buf, sizeof(buf));
+ i2c_set_bus_speed(oldspeed);
+ } else {
+ puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
+ }
+
+#if defined(CONFIG_AM335X_USB0)
+ /* power on USB2SD Controller */
+ gpio_direction_output(USB2SD_PWR, 1);
+ mdelay(1);
+ /* give a reset Pulse to USB2SD Controller */
+ gpio_direction_output(USB2SD_NRST, 0);
+ mdelay(1);
+ gpio_set_value(USB2SD_NRST, 1);
+#endif
+ pmicsetup(0);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+ config_ddr(400, &ddr3_ioregs,
+ &ddr3_data,
+ &ddr3_cmd_ctrl_data,
+ &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ gpmc_init();
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ const unsigned int ton = 250;
+ const unsigned int toff = 1000;
+ unsigned int cnt = 3;
+ unsigned short buf = 0xAAAA;
+ unsigned int oldspeed;
+
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */
+
+ if (gpio_get_value(KEY)) {
+ do {
+ /* turn on light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x09, 0xFF);
+ mdelay(ton);
+ /* turn off light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x01, 0xFF);
+ mdelay(toff);
+ cnt--;
+ if (!gpio_get_value(KEY) &&
+ gpio_get_value(PUSH_KEY) && 1 == cnt) {
+ puts("updating from USB ...\n");
+ setenv("bootcmd", "run usbupdate");
+ break;
+ } else if (!gpio_get_value(KEY)) {
+ break;
+ }
+ } while (cnt);
+ }
+
+ switch (cnt) {
+ case 0:
+ puts("3 blinks ... entering BOOT mode.\n");
+ buf = 0x0000;
+ break;
+ case 1:
+ puts("2 blinks ... entering DIAGNOSE mode.\n");
+ buf = 0x0F0F;
+ break;
+ case 2:
+ puts("1 blinks ... entering SERVICE mode.\n");
+ buf = 0xB4B4;
+ break;
+ case 3:
+ puts("0 blinks ... entering RUN mode.\n");
+ buf = 0x0404;
+ break;
+ }
+ mdelay(ton);
+ /* turn on light */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_WLEDCTRL1, 0x09, 0xFF);
+ /* write bootinfo into scratchregister of resetcontroller */
+ oldspeed = i2c_get_bus_speed();
+ if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
+ i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
+ (uint8_t *)&buf, sizeof(buf));
+ i2c_set_bus_speed(oldspeed);
+ } else {
+ puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
+ }
+ /*
+ * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
+ * expect that vectors are there, original u-boot moves them to _start
+ */
+ __asm__("ldr r0,=0x20000");
+ __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
+
+ return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c
new file mode 100644
index 0000000..ecb2e7a
--- /dev/null
+++ b/board/BuR/kwb/mux.c
@@ -0,0 +1,197 @@
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R LEIT Board(s)
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux usb0_pin_mux[] = {
+ {OFFSET(usb0_id), (MODE(0) | RXACTIVE)},
+ /* USB0 DrvBus Receiver disable (from romcode 0x20) */
+ {OFFSET(usb0_drvvbus), (MODE(0))},
+ /* USB1 DrvBus as GPIO due to HW-Workaround */
+ {OFFSET(usb1_drvvbus), (MODE(7))},
+ {-1},
+};
+static struct module_pin_mux spi1_pin_mux[] = {
+ /* SPI1_SCLK */
+ {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_D0 */
+ {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_D1 */
+ {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
+ /* SPI1_CS0 */
+ {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux dcan0_pin_mux[] = {
+ /* DCAN0 TX */
+ {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
+ /* DCAN0 RX */
+ {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux dcan1_pin_mux[] = {
+ /* DCAN1 TX */
+ {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
+ /* DCAN1 RX */
+ {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
+ {-1},
+};
+
+static struct module_pin_mux gpios[] = {
+ /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+ {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
+ /* GPIO0_4 (SPI D1) - TA602 */
+ {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */
+ {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},
+ /* GPIO0_7 (PWW0 OUT) - CAN TERM */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */
+ {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)},
+ /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */
+ {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)},
+ /* GPIO0_30 (GPMC_WAIT0) - TA601 */
+ {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
+ {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
+ /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */
+ {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+ /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
+ /* GPIO2_4 (GPMC_nWE) - TST_BAST */
+ {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
+ /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
+ {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
+ {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
+ /* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
+ {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
+ {-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ /* UART0_CTS */
+ {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_RXD */
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_TXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ /* I2C_DATA */
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ /* I2C_SCLK */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
+ {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+
+ {-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+ {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
+ {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
+ {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
+ {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
+ {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
+ {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
+ {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
+ {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
+ {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
+ {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
+ {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
+ {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
+ {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
+ {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
+ {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
+ {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
+
+ {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
+ {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
+ {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
+ {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
+ {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
+ {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
+ {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
+ {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
+
+ {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
+ {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
+ {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+ {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
+
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(usb0_pin_mux);
+ configure_module_pin_mux(spi1_pin_mux);
+ configure_module_pin_mux(dcan0_pin_mux);
+ configure_module_pin_mux(dcan1_pin_mux);
+ configure_module_pin_mux(mmc1_pin_mux);
+ configure_module_pin_mux(lcd_pin_mux);
+ configure_module_pin_mux(gpios);
+}
diff --git a/board/BuR/tseries/Kconfig b/board/BuR/tseries/Kconfig
new file mode 100644
index 0000000..ed48300
--- /dev/null
+++ b/board/BuR/tseries/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TSERIES
+
+config SYS_BOARD
+ default "tseries"
+
+config SYS_VENDOR
+ default "BuR"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "tseries"
+
+endif
diff --git a/board/BuR/tseries/MAINTAINERS b/board/BuR/tseries/MAINTAINERS
new file mode 100644
index 0000000..e57326a
--- /dev/null
+++ b/board/BuR/tseries/MAINTAINERS
@@ -0,0 +1,8 @@
+TSERIES BOARD
+M: Hannes Petermaier <hannes.petermaier@br-automation.com>
+S: Maintained
+F: board/BuR/tseries/
+F: include/configs/tseries.h
+F: configs/tseries_mmc_defconfig
+F: configs/tseries_nand_defconfig
+F: configs/tseries_spi_defconfig
diff --git a/board/BuR/tseries/Makefile b/board/BuR/tseries/Makefile
new file mode 100644
index 0000000..ec0d27a
--- /dev/null
+++ b/board/BuR/tseries/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+# Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y := mux.o
+endif
+obj-y += ../common/common.o
+obj-y += board.o
diff --git a/board/BuR/tseries/board.c b/board/BuR/tseries/board.c
new file mode 100644
index 0000000..c0178e7
--- /dev/null
+++ b/board/BuR/tseries/board.c
@@ -0,0 +1,149 @@
+/*
+ * board.c
+ *
+ * Board functions for B&R LEIT Board
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+#include "../common/bur_common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* --------------------------------------------------------------------------*/
+/* -- defines for GPIO -- */
+#define ETHLED_ORANGE (96+16) /* GPIO3_16 */
+#define REPSWITCH (0+20) /* GPIO0_20 */
+
+
+#if defined(CONFIG_SPL_BUILD)
+/* TODO: check ram-timing ! */
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static const struct ctrl_ioregs ddr3_ioregs = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * called from spl_nand.c
+ * return 0 for loading linux, return 1 for loading u-boot
+ */
+int spl_start_uboot(void)
+{
+ if (0 == gpio_get_value(REPSWITCH)) {
+ blink(5, 125, ETHLED_ORANGE);
+ mdelay(1000);
+ printf("SPL: entering u-boot instead kernel image.\n");
+ return 1;
+ }
+ return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#define OSC (V_OSCK/1000000)
+static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ pmicsetup(1000);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr3;
+}
+
+void sdram_init(void)
+{
+ config_ddr(400, &ddr3_ioregs,
+ &ddr3_data,
+ &ddr3_cmd_ctrl_data,
+ &ddr3_emif_reg_data, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/* Basic board specific setup. Pinmux has been handled already. */
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#ifdef CONFIG_NAND
+ gpmc_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ gpio_direction_output(ETHLED_ORANGE, 0);
+
+ if (0 == gpio_get_value(REPSWITCH)) {
+ printf("\n\n\n"
+ "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n"
+ "!!!!!!! recovery switch activated !!!!!!!\n"
+ "!!!!!!! running usbupdate !!!!!!!\n"
+ "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n\n\n");
+ setenv("bootcmd", "sleep 2; run netupdate;");
+ }
+
+ printf("turning on display power+backlight ... ");
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL1,
+ 0x09, TPS65217_MASK_ALL_BITS); /* 200 Hz, ON */
+ tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_WLEDCTRL2,
+ 0x62, TPS65217_MASK_ALL_BITS); /* 100% */
+ printf("ok.\n");
+
+ return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c
new file mode 100644
index 0000000..0ba25ee
--- /dev/null
+++ b/board/BuR/tseries/mux.c
@@ -0,0 +1,233 @@
+/*
+ * mux.c
+ *
+ * Pinmux Setting for B&R LEIT Board(s)
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ /* UART0_CTS */
+ {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_RXD */
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* UART0_TXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+ {-1},
+};
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
+
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
+ {-1},
+};
+#endif
+static struct module_pin_mux i2c0_pin_mux[] = {
+ /* I2C_DATA */
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ /* I2C_SCLK */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+ /* SPI0_SCLK */
+ {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+ /* SPI0_D0 */
+ {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+ /* SPI0_D1 */
+ {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+ /* SPI0_CS0 */
+ {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
+ {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux mii2_pin_mux[] = {
+ {OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */
+ {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */
+ {OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */
+ {OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */
+ {OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */
+ {OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */
+ {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */
+ {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */
+ {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */
+ {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */
+ {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
+ {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
+ {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
+ {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
+ /*
+ * MII2_CRS is shared with
+ * NAND_WAIT0
+ */
+ {OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
+ {-1},
+};
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+#endif
+static struct module_pin_mux gpIOs[] = {
+ /* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
+ {OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
+ {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
+ /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
+ {OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)},
+ /* GPIO2_27 (MMC0_DAT1) - MII_nNAND */
+ {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
+ /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
+ {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
+ /* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
+ {OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
+ {OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
+ {OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
+ {OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
+ {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO2_0 (GPMC_nCS3) - DCOK */
+ {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
+ /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
+ {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
+ /*
+ * GPIO0_7 (PWW0 OUT)
+ * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
+ */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
+ /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
+ {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
+ /* GPIO0_20 (DMA_INTR1) - REP-Switch */
+ {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
+ /* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
+ {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+ /* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
+ {OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
+ /* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
+ {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
+ /* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
+ {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
+
+ {-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+ {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
+ {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
+ {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
+ {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
+ {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
+ {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
+ {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
+ {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
+ {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
+ {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
+ {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
+ {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
+ {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
+ {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
+ {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
+ {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
+
+ {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
+ {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
+ {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
+ {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
+ {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
+ {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
+ {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
+ {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
+
+ {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
+ {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
+ {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
+ {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
+
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(mii2_pin_mux);
+#ifdef CONFIG_NAND
+ configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_MMC)
+ configure_module_pin_mux(mmc1_pin_mux);
+#endif
+ configure_module_pin_mux(spi0_pin_mux);
+ configure_module_pin_mux(lcd_pin_mux);
+ configure_module_pin_mux(gpIOs);
+}
diff --git a/board/BuS/eb_cpu5282/Kconfig b/board/BuS/eb_cpu5282/Kconfig
new file mode 100644
index 0000000..237dc1b
--- /dev/null
+++ b/board/BuS/eb_cpu5282/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EB_CPU5282
+
+config SYS_CPU
+ default "mcf52x2"
+
+config SYS_BOARD
+ default "eb_cpu5282"
+
+config SYS_VENDOR
+ default "BuS"
+
+config SYS_CONFIG_NAME
+ default "eb_cpu5282"
+
+endif
diff --git a/board/BuS/eb_cpu5282/MAINTAINERS b/board/BuS/eb_cpu5282/MAINTAINERS
new file mode 100644
index 0000000..87298ad
--- /dev/null
+++ b/board/BuS/eb_cpu5282/MAINTAINERS
@@ -0,0 +1,7 @@
+EB_CPU5282 BOARD
+M: Jens Scharsig <esw@bus-elektronik.de>
+S: Maintained
+F: board/BuS/eb_cpu5282/
+F: include/configs/eb_cpu5282.h
+F: configs/eb_cpu5282_defconfig
+F: configs/eb_cpu5282_internal_defconfig
diff --git a/board/BuS/eb_cpu5282/Makefile b/board/BuS/eb_cpu5282/Makefile
new file mode 100644
index 0000000..3eb7278
--- /dev/null
+++ b/board/BuS/eb_cpu5282/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = eb_cpu5282.o
diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c
new file mode 100644
index 0000000..2164b52
--- /dev/null
+++ b/board/BuS/eb_cpu5282/eb_cpu5282.c
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2005-2009
+ * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include "asm/m5282.h"
+#include <bmp_layout.h>
+#include <status_led.h>
+#include <bus_vcxk.h>
+
+/*---------------------------------------------------------------------------*/
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_VIDEO
+unsigned long display_width;
+unsigned long display_height;
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+int checkboard (void)
+{
+ puts("Board: EB+CPU5282 (BuS Elektronik GmbH & Co. KG)\n");
+#if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+ puts(" Boot from Internal FLASH\n");
+#endif
+ return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+ int size, i;
+
+ size = 0;
+ MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 |
+ MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4);
+ asm (" nop");
+#ifdef CONFIG_SYS_SDRAM_BASE0
+ MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE0)|
+ MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) |
+ MCFSDRAMC_DACR_PS_32;
+ asm (" nop");
+
+ MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
+ asm (" nop");
+
+ MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
+ asm (" nop");
+ for (i = 0; i < 10; i++)
+ asm (" nop");
+
+ *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
+ asm (" nop");
+ MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
+ asm (" nop");
+
+ for (i = 0; i < 2000; i++)
+ asm (" nop");
+
+ MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
+ asm (" nop");
+ /* write SDRAM mode register */
+ *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
+ asm (" nop");
+ size += CONFIG_SYS_SDRAM_SIZE0 * 1024 * 1024;
+#endif
+#ifdef CONFIG_SYS_SDRAM_BASE1xx
+ MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
+ | MCFSDRAMC_DACR_CASL (1)
+ | MCFSDRAMC_DACR_CBM (3)
+ | MCFSDRAMC_DACR_PS_16;
+
+ MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
+
+ MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
+
+ *(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
+ MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
+
+ for (i = 0; i < 2000; i++)
+ asm (" nop");
+
+ MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
+ *(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
+ size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
+#endif
+ return size;
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+ uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+ uint *p;
+
+ printf("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_HW_WATCHDOG)
+
+void hw_watchdog_init(void)
+{
+ char *s;
+ int enable;
+
+ enable = 1;
+ s = getenv("watchdog");
+ if (s != NULL)
+ if ((strncmp(s, "off", 3) == 0) || (strncmp(s, "0", 1) == 0))
+ enable = 0;
+ if (enable)
+ MCFGPTA_GPTDDR |= (1<<2);
+ else
+ MCFGPTA_GPTDDR &= ~(1<<2);
+}
+
+void hw_watchdog_reset(void)
+{
+ MCFGPTA_GPTPORT ^= (1<<2);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+ hw_watchdog_init();
+#endif
+ return 1;
+}
+
+void __led_toggle(led_id_t mask)
+{
+ MCFGPTA_GPTPORT ^= (1 << 3);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+ __led_set(mask, state);
+ MCFGPTA_GPTDDR |= (1 << 3);
+}
+
+void __led_set(led_id_t mask, int state)
+{
+ if (state == STATUS_LED_ON)
+ MCFGPTA_GPTPORT |= (1 << 3);
+ else
+ MCFGPTA_GPTPORT &= ~(1 << 3);
+}
+
+#if defined(CONFIG_VIDEO)
+
+int drv_video_init(void)
+{
+ char *s;
+#ifdef CONFIG_SPLASH_SCREEN
+ unsigned long splash;
+#endif
+ printf("Init Video as ");
+ s = getenv("displaywidth");
+ if (s != NULL)
+ display_width = simple_strtoul(s, NULL, 10);
+ else
+ display_width = 256;
+
+ s = getenv("displayheight");
+ if (s != NULL)
+ display_height = simple_strtoul(s, NULL, 10);
+ else
+ display_height = 256;
+
+ printf("%lu x %lu pixel matrix\n", display_width, display_height);
+
+ MCFCCM_CCR &= ~MCFCCM_CCR_SZEN;
+ MCFGPIO_PEPAR &= ~MCFGPIO_PEPAR_PEPA2;
+
+ vcxk_init(display_width, display_height);
+
+#ifdef CONFIG_SPLASH_SCREEN
+ s = getenv("splashimage");
+ if (s != NULL) {
+ splash = simple_strtoul(s, NULL, 16);
+ vcxk_acknowledge_wait();
+ video_display_bitmap(splash, 0, 0);
+ }
+#endif
+ return 0;
+}
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#ifdef CONFIG_VIDEO
+int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rcode = 0;
+ ulong side;
+ ulong bright;
+
+ switch (argc) {
+ case 3:
+ side = simple_strtoul(argv[1], NULL, 10);
+ bright = simple_strtoul(argv[2], NULL, 10);
+ if ((side >= 0) && (side <= 3) &&
+ (bright >= 0) && (bright <= 1000)) {
+ vcxk_setbrightness(side, bright);
+ rcode = 0;
+ } else {
+ printf("parameters out of range\n");
+ printf("Usage:\n%s\n", cmdtp->usage);
+ rcode = 1;
+ }
+ break;
+ default:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ rcode = 1;
+ break;
+ }
+ return rcode;
+}
+
+/*---------------------------------------------------------------------------*/
+
+U_BOOT_CMD(
+ bright, 3, 0, do_brightness,
+ "sets the display brightness\n",
+ " <side> <0..1000>\n side: 0/3=both; 1=first; 2=second\n"
+);
+
+#endif
+
+/* EOF EB+MCF-EV123.c */
diff --git a/board/BuS/eb_cpu5282/u-boot.lds b/board/BuS/eb_cpu5282/u-boot.lds
new file mode 100644
index 0000000..0df2a0a
--- /dev/null
+++ b/board/BuS/eb_cpu5282/u-boot.lds
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ .text :
+ {
+ arch/m68k/cpu/mcf52x2/start.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/BuS/eb_cpux9k2/Kconfig b/board/BuS/eb_cpux9k2/Kconfig
new file mode 100644
index 0000000..230e64d
--- /dev/null
+++ b/board/BuS/eb_cpux9k2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EB_CPUX9K2
+
+config SYS_BOARD
+ default "eb_cpux9k2"
+
+config SYS_VENDOR
+ default "BuS"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "eb_cpux9k2"
+
+endif
diff --git a/board/BuS/eb_cpux9k2/MAINTAINERS b/board/BuS/eb_cpux9k2/MAINTAINERS
new file mode 100644
index 0000000..81c4349
--- /dev/null
+++ b/board/BuS/eb_cpux9k2/MAINTAINERS
@@ -0,0 +1,7 @@
+EB_CPUX9K2 BOARD
+M: Jens Scharsig <esw@bus-elektronik.de>
+S: Maintained
+F: board/BuS/eb_cpux9k2/
+F: include/configs/eb_cpux9k2.h
+F: configs/eb_cpux9k2_defconfig
+F: configs/eb_cpux9k2_ram_defconfig
diff --git a/board/BuS/eb_cpux9k2/Makefile b/board/BuS/eb_cpux9k2/Makefile
new file mode 100644
index 0000000..b2ec389
--- /dev/null
+++ b/board/BuS/eb_cpux9k2/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cpux9k2.o
diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c
new file mode 100644
index 0000000..5e4778e
--- /dev/null
+++ b/board/BuS/eb_cpux9k2/cpux9k2.c
@@ -0,0 +1,373 @@
+/*
+ * (C) Copyright 2008-2009
+ * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
+ * Jens Scharsig <esw@bus-elektronik.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <exports.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_mc.h>
+#include <asm/arch/at91_common.h>
+
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
+
+#ifdef CONFIG_VIDEO
+#include <bus_vcxk.h>
+
+extern unsigned long display_width;
+extern unsigned long display_height;
+#endif
+
+#ifdef CONFIG_CMD_NAND
+void cpux9k2_nand_hw_init(void);
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+
+ /* Correct IRDA resistor problem / Set PA23_TXD in Output */
+ writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
+
+ gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_STATUS_LED
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+#ifdef CONFIG_CMD_NAND
+ cpux9k2_nand_hw_init();
+#endif
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ at91_seriald_hw_init();
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+
+int misc_init_r(void)
+{
+ uchar mac[8];
+ uchar tm;
+ uchar midx;
+ uchar macn6, macn7;
+
+ if (getenv("ethaddr") == NULL) {
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x00,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ (uchar *) &mac, sizeof(mac)) != 0) {
+ puts("Error reading MAC from EEPROM\n");
+ } else {
+ tm = 0;
+ macn6 = 0;
+ macn7 = 0xFF;
+ for (midx = 0; midx < 6; midx++) {
+ if ((mac[midx] != 0) && (mac[midx] != 0xFF))
+ tm++;
+ macn6 += mac[midx];
+ macn7 ^= mac[midx];
+ }
+ if ((macn6 != mac[6]) || (macn7 != mac[7]))
+ tm = 0;
+ if (tm)
+ eth_setenv_enetaddr("ethaddr", mac);
+ else
+ puts("Error: invalid MAC at EEPROM\n");
+ }
+ }
+ gd->jt[XF_do_reset] = (void *) do_reset;
+
+#ifdef CONFIG_STATUS_LED
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+ udelay(10000);
+ eth_init(gd->bd);
+}
+#endif
+
+/*
+ * DRAM initialisations
+ */
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+/*
+ * Ethernet initialisations
+ */
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+ rc = at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
+ return rc;
+}
+#endif
+
+/*
+ * Disk On Chip (NAND) Millenium initialization.
+ * The NAND lives in the CS2* space
+ */
+#if defined(CONFIG_CMD_NAND)
+
+#define MASK_ALE (1 << 22) /* our ALE is AD22 */
+#define MASK_CLE (1 << 21) /* our CLE is AD21 */
+
+void cpux9k2_nand_hw_init(void)
+{
+ unsigned long csr;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC;
+
+ /* Setup Smart Media, fitst enable the address range of CS3 */
+ writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa);
+
+ /* RWH = 1 | RWS = 0 | TDF = 1 | NWS = 3 */
+ csr = AT91_SMC_CSR_RWHOLD(1) | AT91_SMC_CSR_TDF(1) |
+ AT91_SMC_CSR_NWS(3) |
+ AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_8 |
+ AT91_SMC_CSR_WSEN;
+ writel(csr, &mc->smc.csr[3]);
+
+ writel(ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE, &pio->pioc.asr);
+ writel(ATMEL_PMX_CA_BFCK | ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE,
+ &pio->pioc.pdr);
+
+ /* Configure PC2 as input (signal Nand READY ) */
+ writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.per);
+ writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */
+ writel(ATMEL_PMX_CA_BFCK, &pio->pioc.codr);
+
+ /* PIOC clock enabling */
+ writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+}
+
+static void board_nand_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
+{
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ struct nand_chip *this = mtd->priv;
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ if ((ctrl & NAND_NCE))
+ writel(1, &pio->pioc.codr);
+ else
+ writel(1, &pio->pioc.sodr);
+
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
+ }
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+static int board_nand_dev_ready(struct mtd_info *mtd)
+{
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ cpux9k2_nand_hw_init();
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = board_nand_hwcontrol;
+ nand->dev_ready = board_nand_dev_ready;
+ nand->chip_delay = 20;
+ return 0;
+}
+
+#endif
+
+#if defined(CONFIG_VIDEO)
+/*
+ * drv_video_init
+ * FUNCTION: initialize VCxK device
+ */
+
+int drv_video_init(void)
+{
+#ifdef CONFIG_SPLASH_SCREEN
+ unsigned long splash;
+#endif
+ char *s;
+ unsigned long csr;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC;
+
+ printf("Init Video as ");
+ s = getenv("displaywidth");
+ if (s != NULL)
+ display_width = simple_strtoul(s, NULL, 10);
+ else
+ display_width = 256;
+ s = getenv("displayheight");
+ if (s != NULL)
+ display_height = simple_strtoul(s, NULL, 10);
+ else
+ display_height = 256;
+ printf("%ld x %ld pixel matrix\n", display_width, display_height);
+
+ /* RWH = 2 | RWS =2 | TDF = 4 | NWS = 0x6 */
+ csr = AT91_SMC_CSR_RWHOLD(2) | AT91_SMC_CSR_RWSETUP(2) |
+ AT91_SMC_CSR_TDF(4) | AT91_SMC_CSR_NWS(6) |
+ AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
+ AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
+ writel(csr, &mc->smc.csr[2]);
+ writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
+
+ vcxk_init(display_width, display_height);
+#ifdef CONFIG_SPLASH_SCREEN
+ s = getenv("splashimage");
+ if (s != NULL) {
+ splash = simple_strtoul(s, NULL, 16);
+ printf("use splashimage: %lx\n", splash);
+ video_display_bitmap(splash, 0, 0);
+ }
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_SOFT
+
+void i2c_init_board(void)
+{
+ u32 pin;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+
+ writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
+ pin = ATMEL_PMX_AA_TWD | ATMEL_PMX_AA_TWCK;
+ writel(pin, &pio->pioa.idr);
+ writel(pin, &pio->pioa.pudr);
+ writel(pin, &pio->pioa.per);
+ writel(pin, &pio->pioa.oer);
+ writel(pin, &pio->pioa.sodr);
+}
+
+#endif
+
+/*--------------------------------------------------------------------------*/
+
+#ifdef CONFIG_STATUS_LED
+
+void __led_toggle(led_id_t mask)
+{
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+
+ if (readl(&pio->piod.odsr) & mask)
+ writel(mask, &pio->piod.codr);
+ else
+ writel(mask, &pio->piod.codr);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+
+ writel(1 << ATMEL_ID_PIOD, &pmc->pcer); /* Enable PIOB clock */
+ /* Disable peripherals on LEDs */
+ writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per);
+ /* Enable pins as outputs */
+ writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.oer);
+ /* Turn all LEDs OFF */
+ writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.sodr);
+
+ __led_set(mask, state);
+}
+
+void __led_set(led_id_t mask, int state)
+{
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ if (state == STATUS_LED_ON)
+ writel(mask, &pio->piod.codr);
+ else
+ writel(mask, &pio->piod.sodr);
+}
+
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rcode = 0;
+ ulong side;
+ ulong bright;
+
+ switch (argc) {
+ case 3:
+ side = simple_strtoul(argv[1], NULL, 10);
+ bright = simple_strtoul(argv[2], NULL, 10);
+ if ((side >= 0) && (side <= 3) &&
+ (bright >= 0) && (bright <= 1000)) {
+ vcxk_setbrightness(side, bright);
+ rcode = 0;
+ } else {
+ printf("parameters out of range\n");
+ printf("Usage:\n%s\n", cmdtp->usage);
+ rcode = 1;
+ }
+ break;
+ default:
+ printf("Usage:\n%s\n", cmdtp->usage);
+ rcode = 1;
+ break;
+ }
+ return rcode;
+}
+
+/*---------------------------------------------------------------------------*/
+
+U_BOOT_CMD(
+ bright, 3, 0, do_brightness,
+ "bright - sets the display brightness\n",
+ " <side> <0..1000>\n side: 0/3=both; 1=first; 2=second\n"
+);
+
+/* EOF cpu9k2.c */
diff --git a/board/BuS/vl_ma2sc/Kconfig b/board/BuS/vl_ma2sc/Kconfig
new file mode 100644
index 0000000..2f43519
--- /dev/null
+++ b/board/BuS/vl_ma2sc/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_VL_MA2SC
+
+config SYS_BOARD
+ default "vl_ma2sc"
+
+config SYS_VENDOR
+ default "BuS"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "vl_ma2sc"
+
+endif
diff --git a/board/BuS/vl_ma2sc/MAINTAINERS b/board/BuS/vl_ma2sc/MAINTAINERS
new file mode 100644
index 0000000..b70104d
--- /dev/null
+++ b/board/BuS/vl_ma2sc/MAINTAINERS
@@ -0,0 +1,7 @@
+VL_MA2SC BOARD
+M: Jens Scharsig <esw@bus-elektronik.de>
+S: Maintained
+F: board/BuS/vl_ma2sc/
+F: include/configs/vl_ma2sc.h
+F: configs/vl_ma2sc_defconfig
+F: configs/vl_ma2sc_ram_defconfig
diff --git a/board/BuS/vl_ma2sc/Makefile b/board/BuS/vl_ma2sc/Makefile
new file mode 100644
index 0000000..d4b24ac
--- /dev/null
+++ b/board/BuS/vl_ma2sc/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2009-2012
+# Jens Scharsig <esw@bus-elekronik.de>
+# BuS Elektronik GmbH & Co. KG
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += vl_ma2sc.o
diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c
new file mode 100644
index 0000000..da39c86
--- /dev/null
+++ b/board/BuS/vl_ma2sc/vl_ma2sc.c
@@ -0,0 +1,519 @@
+/*
+ * (C) Copyright 2009-2012
+ * Jens Scharsig <esw@bus-elekronik.de>
+ * BuS Elektronik GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_common.h>
+#include <lcd.h>
+#include <i2c.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static void vl_ma2sc_nand_hw_init(void)
+{
+ unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
+ at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
+ at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */
+ at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */
+
+ /* Enable CS3 */
+ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa[0]);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+ writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE),
+ &pmc->pcer);
+
+ /* Configure RDY/BSY */
+#ifdef CONFIG_SYS_NAND_READY_PIN
+ gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+#endif
+ /* Enable NandFlash */
+ gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void vl_ma2sc_macb_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+ at91_phy_reset();
+
+ at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 320,
+ .vl_row = 240,
+ .vl_clk = 6500000,
+ .vl_sync = ATMEL_LCDC_INVDVAL_INVERTED |
+ ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVVD_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = (ATMEL_LCDC_PIXELSIZE_8 >> 5),
+ .vl_tft = 1,
+ .vl_hsync_len = 5, /* Horiz Sync Pulse Width */
+ .vl_left_margin = 68, /* horiz back porch */
+ .vl_right_margin = 20, /* horiz front porch */
+ .vl_vsync_len = 2, /* vert Sync Pulse Width */
+ .vl_upper_margin = 18, /* vert back porch */
+ .vl_lower_margin = 4, /* vert front porch */
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+}
+
+void lcd_disable(void)
+{
+}
+
+static void vl_ma2sc_lcd_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
+ at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
+
+ at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */
+ at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
+
+ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */
+ at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
+ at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
+
+ at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */
+ at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */
+ at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
+ at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
+
+ at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */
+
+ at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */
+ at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */
+ at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */
+ at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */
+ at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */
+ at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */
+
+ at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */
+
+ writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+ gd->fb_base = ATMEL_BASE_SRAM0;
+}
+#endif /* Config LCD */
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clocks for all PIOs */
+ writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOCDE),
+ &pmc->pcer);
+
+ at91_seriald_hw_init();
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ u32 pin;
+
+ pin = 0x1F000001;
+ writel(pin, &pio->pioa.idr);
+ writel(pin, &pio->pioa.pudr);
+ writel(pin, &pio->pioa.per);
+ writel(pin, &pio->pioa.oer);
+ writel(pin, &pio->pioa.sodr);
+ writel((1 << 25), &pio->pioa.codr);
+
+ pin = 0x1F000100;
+ writel(pin, &pio->piob.idr);
+ writel(pin, &pio->piob.pudr);
+ writel(pin, &pio->piob.per);
+ writel(pin, &pio->piob.oer);
+ writel(pin, &pio->piob.codr);
+ writel((1 << 24), &pio->piob.sodr);
+
+ pin = 0x40000000; /* Pullup DRxD enbable */
+ writel(pin, &pio->pioc.puer);
+
+ pin = 0x0000000F; /* HWversion als Input */
+ writel(pin, &pio->piod.idr);
+ writel(pin, &pio->piod.puer);
+ writel(pin, &pio->piod.per);
+ writel(pin, &pio->piod.odr);
+ writel(pin, &pio->piod.owdr);
+
+ gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup);
+ writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle);
+ writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse);
+ writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup);
+
+#ifdef CONFIG_CMD_NAND
+ vl_ma2sc_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+ vl_ma2sc_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+ at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ vl_ma2sc_lcd_hw_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ uchar buffer[8];
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ u32 pin;
+
+ buffer[0] = 0x04;
+ buffer[1] = 0x00;
+ if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0)
+ puts("error reseting rtc clock\n\0");
+
+ /* read hardware version */
+
+ pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44;
+ printf("Board: revision %c\n", pin);
+ buffer[0] = pin;
+ buffer[1] = 0;
+ setenv("revision", (char *) buffer);
+
+ pin = 0x40000000; /* Pullup DRxD enbable */
+ writel(pin, &pio->pioc.puer);
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01);
+#endif
+ return rc;
+}
+
+#ifdef CONFIG_SYS_I2C_SOFT
+void i2c_init_board(void)
+{
+ u32 pin;
+
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ u8 sda = (1<<4);
+ u8 scl = (1<<5);
+
+ writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
+ pin = sda | scl;
+ writel(pin, &pio->piob.idr); /* Disable Interupt */
+ writel(pin, &pio->piob.pudr);
+ writel(pin, &pio->piob.per);
+ writel(pin, &pio->piob.oer);
+ writel(pin, &pio->piob.sodr);
+}
+#endif
+
+void watchdog_reset(void)
+{
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ u32 pin = 0x1; /* PA0 */
+
+ if ((readl(&pio->pioa.odsr) & pin) > 0)
+ writel(pin, &pio->pioa.codr);
+ else
+ writel(pin, &pio->pioa.sodr);
+}
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+
+/*---------------------------------------------------------------------------*/
+
+int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rcode = 1;
+ int row;
+ int col;
+ u32 pinz;
+ u32 pins;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+
+ at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */
+
+ pins = 0x1F000000;
+ writel(pins, &pio->pioa.idr);
+ writel(pins, &pio->pioa.pudr);
+ writel(pins, &pio->pioa.per);
+ writel(pins, &pio->pioa.oer);
+ writel(pins, &pio->pioa.sodr);
+
+ pinz = 0x1F000000;
+ writel(pinz, &pio->piob.idr);
+ writel(pinz, &pio->piob.pudr);
+ writel(pinz, &pio->piob.per);
+ writel(pinz, &pio->piob.oer);
+ writel(pinz, &pio->piob.sodr);
+
+ for (row = 0; row < 5; row++) {
+ for (col = 0; col < 5; col++) {
+ writel((0x01000000 << col), &pio->piob.sodr);
+ writel((0x01000000 << row), &pio->pioa.codr);
+ printf("LED Test %d x %d\n", row, col);
+ udelay(1000000);
+ writel(pinz, &pio->piob.codr);
+ writel(pins, &pio->pioa.sodr);
+ }
+ }
+ return rcode;
+}
+
+void poweroff(void)
+{
+ watchdog_reset();
+ at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
+ udelay(100);
+ at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */
+ udelay(100);
+ at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */
+ udelay(100);
+ while (1)
+ watchdog_reset();
+}
+
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rcode = 1;
+ poweroff();
+ return rcode;
+}
+
+int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i;
+ u32 freq;
+ u32 durate;
+ int rcode = 1;
+
+ freq = 1000;
+ durate = 2;
+ switch (argc) {
+ case 3:
+ durate = simple_strtoul(argv[2], NULL, 10);
+ case 2:
+ freq = simple_strtoul(argv[1], NULL, 10);
+ case 1:
+ break;
+ default:
+ cmd_usage(cmdtp);
+ rcode = 1;
+ break;
+ }
+ durate = durate * freq;
+ freq = 500000 / freq;
+ for (i = 0; i < durate; i++) {
+ at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/
+ udelay(freq);
+ at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
+ udelay(freq);
+ }
+ at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
+ return rcode;
+}
+
+int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rcode = 1;
+ int row;
+ u32 col;
+ u32 pinz;
+ u32 pins;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ writel((1 << ATMEL_ID_PIOA), &pmc->pcer);
+
+ pins = 0x001F0000;
+ writel(pins, &pio->pioa.idr);
+ writel(pins, &pio->pioa.pudr);
+ writel(pins, &pio->pioa.per);
+ writel(pins, &pio->pioa.odr);
+
+ pinz = 0x000F0000;
+ writel(pinz, &pio->piob.idr);
+ writel(pinz, &pio->piob.pudr);
+ writel(pinz, &pio->piob.per);
+ writel(pinz, &pio->piob.oer);
+ writel(pinz, &pio->piob.codr);
+
+ while (1) {
+ col = 0;
+ for (row = 0; row < 4; row++) {
+ writel((0x00010000 << row), &pio->piob.sodr);
+ udelay(10000);
+ col <<= 4;
+ col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ;
+ writel(pinz, &pio->piob.codr);
+ }
+ printf("Matix: ");
+ for (row = 0; row < 16; row++) {
+ printf("%1.1d", col & 1);
+ col >>= 1;
+ }
+ printf(" SP %d\r ",
+ 1 ^ (1 & (readl(&pio->piob.pdsr) >> 20)));
+ if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) {
+ /* SHUTDOWN */
+ row = 0;
+ while (row < 1000) {
+ if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0)
+ row++;
+ udelay(100);
+ }
+ udelay(100000);
+ row = 0;
+ while (row < 1000) {
+ if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) {
+ row++;
+ udelay(1000);
+ }
+ }
+ poweroff();
+ while (1)
+ ;
+ }
+ }
+ return rcode;
+}
+
+/*****************************************************************************/
+
+U_BOOT_CMD(
+ ledtest, 1, 0, do_ledtest,
+ "test ledmatrix",
+ "\n"
+ );
+
+U_BOOT_CMD(
+ keytest, 1, 0, do_keytest,
+ "test keymatix and special keys, poweroff on pressing ON key",
+ "\n"
+ );
+
+U_BOOT_CMD(
+ poweroff, 1, 0, do_poweroff,
+ "power off",
+ "\n"
+ );
+
+U_BOOT_CMD(
+ beep, 3, 0, do_beep,
+ "[freq [duration]]",
+ "freq frequence of beep\nduration duration of beep\n"
+ );
+
+/*****************************************************************************/
diff --git a/board/CarMediaLab/flea3/Kconfig b/board/CarMediaLab/flea3/Kconfig
new file mode 100644
index 0000000..7113f2b
--- /dev/null
+++ b/board/CarMediaLab/flea3/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_FLEA3
+
+config SYS_BOARD
+ default "flea3"
+
+config SYS_VENDOR
+ default "CarMediaLab"
+
+config SYS_SOC
+ default "mx35"
+
+config SYS_CONFIG_NAME
+ default "flea3"
+
+endif
diff --git a/board/CarMediaLab/flea3/MAINTAINERS b/board/CarMediaLab/flea3/MAINTAINERS
new file mode 100644
index 0000000..c7b0df7
--- /dev/null
+++ b/board/CarMediaLab/flea3/MAINTAINERS
@@ -0,0 +1,6 @@
+FLEA3 BOARD
+M: Stefano Babic <sbabic@denx.de>
+S: Maintained
+F: board/CarMediaLab/flea3/
+F: include/configs/flea3.h
+F: configs/flea3_defconfig
diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile
new file mode 100644
index 0000000..f34be74
--- /dev/null
+++ b/board/CarMediaLab/flea3/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := flea3.o
+obj-y += lowlevel_init.o
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
new file mode 100644
index 0000000..7f5cfc8
--- /dev/null
+++ b/board/CarMediaLab/flea3/flea3.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux-mx35.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define CCM_CCMR_CONFIG 0x003F4208
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+#define ESDCTL_0x92220000 0x92220000
+#define ESDCTL_0xA2220000 0xA2220000
+#define ESDCTL_0xB2220000 0xB2220000
+#define ESDCTL_0x82228080 0x82228080
+#define ESDCTL_DDR2_EMR2 0x04000000
+#define ESDCTL_DDR2_EMR3 0x06000000
+#define ESDCTL_PRECHARGE 0x00000400
+#define ESDCTL_DDR2_EN_DLL 0x02000400
+#define ESDCTL_DDR2_RESET_DLL 0x00000333
+#define ESDCTL_DDR2_MR 0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+#define ESDCTL_DELAY_LINE5 0x00F49F00
+
+static inline void dram_wait(unsigned int count)
+{
+ volatile unsigned int wait = count;
+
+ while (wait--)
+ ;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+static void board_setup_sdram_bank(u32 start_address)
+
+{
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+ u32 *cfg_reg, *ctl_reg;
+ u32 val;
+
+ switch (start_address) {
+ case CSD0_BASE_ADDR:
+ cfg_reg = &esdc->esdcfg0;
+ ctl_reg = &esdc->esdctl0;
+ break;
+ case CSD1_BASE_ADDR:
+ cfg_reg = &esdc->esdcfg1;
+ ctl_reg = &esdc->esdctl1;
+ break;
+ default:
+ return;
+ }
+
+ /* Initialize MISC register for DDR2 */
+ val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+ ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+ writel(val, &esdc->esdmisc);
+ val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+ writel(val, &esdc->esdmisc);
+
+ /*
+ * according to DDR2 specs, wait a while before
+ * the PRECHARGE_ALL command
+ */
+ dram_wait(0x20000);
+
+ /* Load DDR2 config and timing */
+ writel(ESDCTL_DDR2_CONFIG, cfg_reg);
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ ctl_reg);
+ writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+ /* Load mode */
+ writel(ESDCTL_0xB2220000,
+ ctl_reg);
+ writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
+ writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
+ writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+ writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ ctl_reg);
+ writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+ /* Set mode auto refresh : at least two refresh are required */
+ writel(ESDCTL_0xA2220000,
+ ctl_reg);
+ writel(0xda, start_address);
+ writel(0xda, start_address);
+
+ writel(ESDCTL_0xB2220000,
+ ctl_reg);
+ writeb(0xda, start_address + ESDCTL_DDR2_MR);
+ writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
+
+ /* OCD mode exit */
+ writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+ /* Set normal mode */
+ writel(ESDCTL_0x82228080,
+ ctl_reg);
+
+ dram_wait(0x20000);
+
+ /* Do not set delay lines, only for MDDR */
+}
+
+static void board_setup_sdram(void)
+{
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /* Initialize with default values both CSD0/1 */
+ writel(0x2000, &esdc->esdctl0);
+ writel(0x2000, &esdc->esdctl1);
+
+ board_setup_sdram_bank(CSD0_BASE_ADDR);
+}
+
+static void setup_iomux_uart3(void)
+{
+ static const iomux_v3_cfg_t uart3_pads[] = {
+ MX35_PAD_RTS2__UART3_RXD_MUX,
+ MX35_PAD_CTS2__UART3_TXD_MUX,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+ static const iomux_v3_cfg_t i2c_pads[] = {
+ NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
+
+ NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
+}
+
+
+static void setup_iomux_spi(void)
+{
+ static const iomux_v3_cfg_t spi_pads[] = {
+ MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
+ MX35_PAD_CSPI1_MISO__CSPI1_MISO,
+ MX35_PAD_CSPI1_SS0__CSPI1_SS0,
+ MX35_PAD_CSPI1_SS1__CSPI1_SS1,
+ MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
+}
+
+static void setup_iomux_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+ MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX35_PAD_FEC_COL__FEC_COL,
+ MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+ MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+ MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX35_PAD_FEC_MDC__FEC_MDC,
+ MX35_PAD_FEC_MDIO__FEC_MDIO,
+ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+ MX35_PAD_FEC_CRS__FEC_CRS,
+ MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+ MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+ MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+ MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+ MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+ MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+ };
+
+ /* setup pins for FEC */
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+int board_early_init_f(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* setup GPIO3_1 to set HighVCore signal */
+ imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
+ gpio_direction_output(65, 1);
+
+ /* initialize PLL and clock configuration */
+ writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+ writel(CCM_MPLL_532_HZ, &ccm->mpctl);
+ writel(CCM_PPLL_300_HZ, &ccm->ppctl);
+
+ /* Set the core to run at 532 Mhz */
+ writel(0x00001000, &ccm->pdr0);
+
+ /* Set-up RAM */
+ board_setup_sdram();
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDIO_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_I2C3_MASK,
+ &ccm->cgr1);
+
+ /* Set-up NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ /* Set pinmux for the required peripherals */
+ setup_iomux_uart3();
+ setup_iomux_i2c();
+ setup_iomux_fec();
+ setup_iomux_spi();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ int rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
diff --git a/board/CarMediaLab/flea3/lowlevel_init.S b/board/CarMediaLab/flea3/lowlevel_init.S
new file mode 100644
index 0000000..a9b7c1b
--- /dev/null
+++ b/board/CarMediaLab/flea3/lowlevel_init.S
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ core_init
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ mov pc, lr
diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c
new file mode 100644
index 0000000..d6ffefe
--- /dev/null
+++ b/board/LaCie/common/common.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+
+#define MII_MARVELL_PHY_PAGE 22
+
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+void mv_phy_88e1116_init(const char *name, u16 phyaddr)
+{
+ u16 reg;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
+ miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
+
+ if (miiphy_reset(name, phyaddr) == 0)
+ printf("88E1116 Initialized on %s\n", name);
+}
+
+void mv_phy_88e1318_init(const char *name, u16 phyaddr)
+{
+ u16 reg;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /*
+ * Set control mode 4 for LED[0].
+ */
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
+ miiphy_read(name, phyaddr, 16, ®);
+ reg |= 0xf;
+ miiphy_write(name, phyaddr, 16, reg);
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
+ miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
+ miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
+
+ if (miiphy_reset(name, phyaddr) == 0)
+ printf("88E1318 Initialized on %s\n", name);
+}
+#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
+
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+int lacie_read_mac_address(uchar *mac_addr)
+{
+ int ret;
+ ushort version;
+
+ /* I2C-0 for on-board EEPROM */
+ i2c_set_bus_num(0);
+
+ /* Check layout version for EEPROM data */
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ (uchar *) &version, 2);
+ if (ret != 0) {
+ printf("Error: failed to read I2C EEPROM @%02x\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR);
+ return ret;
+ }
+ version = be16_to_cpu(version);
+ if (version < 1 || version > 3) {
+ printf("Error: unknown version %d for EEPROM data\n",
+ version);
+ return -1;
+ }
+
+ /* Read Ethernet MAC address from EEPROM */
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6);
+ if (ret != 0)
+ printf("Error: failed to read I2C EEPROM @%02x\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR);
+ return ret;
+}
+#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */
diff --git a/board/LaCie/common/common.h b/board/LaCie/common/common.h
new file mode 100644
index 0000000..c24e588
--- /dev/null
+++ b/board/LaCie/common/common.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _LACIE_COMMON_H
+#define _LACIE_COMMON_H
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+void mv_phy_88e1116_init(const char *name, u16 phyaddr);
+void mv_phy_88e1318_init(const char *name, u16 phyaddr);
+#endif
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+int lacie_read_mac_address(uchar *mac);
+#endif
+
+#endif /* _LACIE_COMMON_H */
diff --git a/board/LaCie/common/cpld-gpio-bus.c b/board/LaCie/common/cpld-gpio-bus.c
new file mode 100644
index 0000000..9b24dc53
--- /dev/null
+++ b/board/LaCie/common/cpld-gpio-bus.c
@@ -0,0 +1,47 @@
+/*
+ * cpld-gpio-bus.c: provides support for the CPLD GPIO bus found on some LaCie
+ * boards (as the 2Big/5Big Network v2 and the 2Big NAS). This parallel GPIO
+ * bus exposes two registers (address and data). Each of this register is made
+ * up of several dedicated GPIOs. An extra GPIO is used to notify the CPLD that
+ * the registers have been updated.
+ *
+ * Mostly this bus is used to configure the LEDs on LaCie boards.
+ *
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/gpio.h>
+#include "cpld-gpio-bus.h"
+
+static void cpld_gpio_bus_set_addr(struct cpld_gpio_bus *bus, unsigned addr)
+{
+ int pin;
+
+ for (pin = 0; pin < bus->num_addr; pin++)
+ kw_gpio_set_value(bus->addr[pin], (addr >> pin) & 1);
+}
+
+static void cpld_gpio_bus_set_data(struct cpld_gpio_bus *bus, unsigned data)
+{
+ int pin;
+
+ for (pin = 0; pin < bus->num_data; pin++)
+ kw_gpio_set_value(bus->data[pin], (data >> pin) & 1);
+}
+
+static void cpld_gpio_bus_enable_select(struct cpld_gpio_bus *bus)
+{
+ /* The transfer is enabled on the raising edge. */
+ kw_gpio_set_value(bus->enable, 0);
+ kw_gpio_set_value(bus->enable, 1);
+}
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *bus,
+ unsigned addr, unsigned value)
+{
+ cpld_gpio_bus_set_addr(bus, addr);
+ cpld_gpio_bus_set_data(bus, value);
+ cpld_gpio_bus_enable_select(bus);
+}
diff --git a/board/LaCie/common/cpld-gpio-bus.h b/board/LaCie/common/cpld-gpio-bus.h
new file mode 100644
index 0000000..3dfac0b
--- /dev/null
+++ b/board/LaCie/common/cpld-gpio-bus.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _LACIE_CPLD_GPI0_BUS_H
+#define _LACIE_CPLD_GPI0_BUS_H
+
+struct cpld_gpio_bus {
+ unsigned *addr;
+ unsigned num_addr;
+ unsigned *data;
+ unsigned num_data;
+ unsigned enable;
+};
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *cpld_gpio_bus,
+ unsigned addr, unsigned value);
+
+#endif /* _LACIE_CPLD_GPI0_BUS_H */
diff --git a/board/LaCie/edminiv2/Kconfig b/board/LaCie/edminiv2/Kconfig
new file mode 100644
index 0000000..ac3fe3f
--- /dev/null
+++ b/board/LaCie/edminiv2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_EDMINIV2
+
+config SYS_BOARD
+ default "edminiv2"
+
+config SYS_VENDOR
+ default "LaCie"
+
+config SYS_CONFIG_NAME
+ default "edminiv2"
+
+endif
diff --git a/board/LaCie/edminiv2/MAINTAINERS b/board/LaCie/edminiv2/MAINTAINERS
new file mode 100644
index 0000000..e0591f4
--- /dev/null
+++ b/board/LaCie/edminiv2/MAINTAINERS
@@ -0,0 +1,6 @@
+EDMINIV2 BOARD
+M: Albert ARIBAUD <albert.u.boot@aribaud.net>
+S: Maintained
+F: board/LaCie/edminiv2/
+F: include/configs/edminiv2.h
+F: configs/edminiv2_defconfig
diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile
new file mode 100644
index 0000000..035f686
--- /dev/null
+++ b/board/LaCie/edminiv2/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# Based on original Kirkwood support which is
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := edminiv2.o ../common/common.o
diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk
new file mode 100644
index 0000000..dfa84f0
--- /dev/null
+++ b/board/LaCie/edminiv2/config.mk
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# TEXT_BASE must equal the intended FLASH location of u-boot.
+CONFIG_SYS_TEXT_BASE = 0xfff90000
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
new file mode 100644
index 0000000..80ec7fa
--- /dev/null
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/orion5x.h>
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
+ * which CFI does not properly detect, hence the LEGACY config.
+ */
+#if defined(CONFIG_FLASH_CFI_LEGACY)
+#include <flash.h>
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
+ int sect;
+
+ if (base != CONFIG_SYS_FLASH_BASE)
+ return 0;
+
+ info->size = 0;
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ /* set each sector's start address and size based */
+ for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
+ info->start[sect] = base+info->size;
+ info->size += sectsz[sect];
+ }
+ /* This flash must be accessed in 8-bits mode, no buffer. */
+ info->flash_id = 0x01000000;
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->buffer_size = 0;
+ /* timings are derived from the Macronix datasheet. */
+ info->erase_blk_tout = 1000;
+ info->write_tout = 10;
+ info->buffer_write_tout = 300;
+ /* Commands and addresses are for AMD mode 8-bit access. */
+ info->vendor = CFI_CMDSET_AMD_LEGACY;
+ info->cmd_reset = 0xF0;
+ info->interface = FLASH_CFI_X8;
+ info->legacy_unlock = 0;
+ info->ext_addr = 0;
+ info->addr_unlock1 = 0x00000aaa;
+ info->addr_unlock2 = 0x00000555;
+ /* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */
+ info->manufacturer_id = 0x22;
+ info->device_id = 0xBA;
+ info->device_id2 = 0;
+ info->cfi_version = 0x3133;
+ info->cfi_offset = 0x0000;
+ info->name = "MX29LV400CB";
+
+ return 1;
+}
+#endif /* CONFIG_SYS_FLASH_CFI */
+
+int board_init(void)
+{
+ /* arch number of board */
+ gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
+
+ /* boot parameter start at 256th byte of RAM base */
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+ return 0;
+}
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ mv_phy_88e1116_init("egiga0", 8);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/LaCie/net2big_v2/Kconfig b/board/LaCie/net2big_v2/Kconfig
new file mode 100644
index 0000000..ba460db
--- /dev/null
+++ b/board/LaCie/net2big_v2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NET2BIG_V2
+
+config SYS_BOARD
+ default "net2big_v2"
+
+config SYS_VENDOR
+ default "LaCie"
+
+config SYS_CONFIG_NAME
+ default "lacie_kw"
+
+endif
diff --git a/board/LaCie/net2big_v2/MAINTAINERS b/board/LaCie/net2big_v2/MAINTAINERS
new file mode 100644
index 0000000..205c75e
--- /dev/null
+++ b/board/LaCie/net2big_v2/MAINTAINERS
@@ -0,0 +1,11 @@
+NET2BIG_V2 BOARD
+#M: -
+S: Maintained
+F: board/LaCie/net2big_v2/
+F: include/configs/lacie_kw.h
+F: configs/d2net_v2_defconfig
+
+NET2BIG_V2 BOARD
+M: Simon Guinot <simon.guinot@sequanux.org>
+S: Maintained
+F: configs/net2big_v2_defconfig
diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile
new file mode 100644
index 0000000..f3074af
--- /dev/null
+++ b/board/LaCie/net2big_v2/Makefile
@@ -0,0 +1,15 @@
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := net2big_v2.o ../common/common.o
+ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
+obj-y += ../common/cpld-gpio-bus.o
+endif
diff --git a/board/LaCie/net2big_v2/kwbimage.cfg b/board/LaCie/net2big_v2/kwbimage.cfg
new file mode 100644
index 0000000..453fcb2
--- /dev/null
+++ b/board/LaCie/net2big_v2/kwbimage.cfg
@@ -0,0 +1,151 @@
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000C30 # DDR Configuration register
+# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x38743000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A32 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000CCCC # DDR Address Control
+# bit1-0: 01, Cs0width=x16
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs2width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000662 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000044 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 1, DDR drive strenght reduced
+# bit2: 1, DDR ODT control lsd enabled
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, enabled
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 1 , D2P Latency enabled
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
+# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c
new file mode 100644
index 0000000..263bb54
--- /dev/null
+++ b/board/LaCie/net2big_v2/net2big_v2.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#include "net2big_v2.h"
+#include "../common/common.h"
+#include "../common/cpld-gpio-bus.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /* GPIO configuration */
+ mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
+ NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_SPI_SCn,
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO, /* Request power-off */
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP13_GPIO, /* Rear power switch (on|auto) */
+ MPP14_GPIO, /* USB fuse alarm */
+ MPP15_GPIO, /* Rear power switch (auto|off) */
+ MPP16_GPIO, /* SATA HDD1 power */
+ MPP17_GPIO, /* SATA HDD2 power */
+ MPP20_SATA1_ACTn,
+ MPP21_SATA0_ACTn,
+ MPP24_GPIO, /* USB mode select */
+ MPP26_GPIO, /* USB device vbus */
+ MPP28_GPIO, /* USB enable host vbus */
+ MPP29_GPIO, /* CPLD GPIO bus ALE */
+ MPP34_GPIO, /* Rear Push button 0=on 1=off */
+ MPP35_GPIO, /* Inhibit switch power-off */
+ MPP36_GPIO, /* SATA HDD1 presence */
+ MPP37_GPIO, /* SATA HDD2 presence */
+ MPP40_GPIO, /* eSATA presence */
+ MPP44_GPIO, /* CPLD GPIO bus (data 0) */
+ MPP45_GPIO, /* CPLD GPIO bus (data 1) */
+ MPP46_GPIO, /* CPLD GPIO bus (data 2) */
+ MPP47_GPIO, /* CPLD GPIO bus (addr 0) */
+ MPP48_GPIO, /* CPLD GPIO bus (addr 1) */
+ MPP49_GPIO, /* CPLD GPIO bus (addr 2) */
+ 0
+ };
+
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Machine number */
+ gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
+
+ /* Boot parameters address */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR)
+/*
+ * Start I2C fan (GMT G762 controller)
+ */
+static void init_fan(void)
+{
+ u8 data;
+
+ i2c_set_bus_num(0);
+
+ /* Enable open-loop and PWM modes */
+ data = 0x20;
+ if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+ G762_REG_FAN_CMD1, 1, &data, 1) != 0)
+ goto err;
+ data = 0;
+ if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+ G762_REG_SET_CNT, 1, &data, 1) != 0)
+ goto err;
+ /*
+ * RPM to PWM (set_out register) fan speed conversion array:
+ * 0 0x00
+ * 1500 0x04
+ * 2800 0x08
+ * 3400 0x0C
+ * 3700 0x10
+ * 4400 0x20
+ * 4700 0x30
+ * 4800 0x50
+ * 5200 0x80
+ * 5400 0xC0
+ * 5500 0xFF
+ *
+ * Start fan at low speed (2800 RPM):
+ */
+ data = 0x08;
+ if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+ G762_REG_SET_OUT, 1, &data, 1) != 0)
+ goto err;
+
+ return;
+err:
+ printf("Error: failed to start I2C fan @%02x\n",
+ CONFIG_SYS_I2C_G762_ADDR);
+}
+#else
+static void init_fan(void) {}
+#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */
+
+#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO)
+/*
+ * CPLD GPIO bus:
+ *
+ * - address register : bit [0-2] -> GPIO [47-49]
+ * - data register : bit [0-2] -> GPIO [44-46]
+ * - enable register : GPIO 29
+ */
+static unsigned cpld_gpio_bus_addr[] = { 47, 48, 49 };
+static unsigned cpld_gpio_bus_data[] = { 44, 45, 46 };
+
+static struct cpld_gpio_bus cpld_gpio_bus = {
+ .addr = cpld_gpio_bus_addr,
+ .num_addr = ARRAY_SIZE(cpld_gpio_bus_addr),
+ .data = cpld_gpio_bus_data,
+ .num_data = ARRAY_SIZE(cpld_gpio_bus_data),
+ .enable = 29,
+};
+
+/*
+ * LEDs configuration:
+ *
+ * The LEDs are controlled by a CPLD and can be configured through
+ * the CPLD GPIO bus.
+ *
+ * Address register selection:
+ *
+ * addr | register
+ * ----------------------------
+ * 0 | front LED
+ * 1 | front LED brightness
+ * 2 | SATA LED brightness
+ * 3 | SATA0 LED
+ * 4 | SATA1 LED
+ * 5 | SATA2 LED
+ * 6 | SATA3 LED
+ * 7 | SATA4 LED
+ *
+ * Data register configuration:
+ *
+ * data | LED brightness
+ * -------------------------------------------------
+ * 0 | min (off)
+ * - | -
+ * 7 | max
+ *
+ * data | front LED mode
+ * -------------------------------------------------
+ * 0 | fix off
+ * 1 | fix blue on
+ * 2 | fix red on
+ * 3 | blink blue on=1 sec and blue off=1 sec
+ * 4 | blink red on=1 sec and red off=1 sec
+ * 5 | blink blue on=2.5 sec and red on=0.5 sec
+ * 6 | blink blue on=1 sec and red on=1 sec
+ * 7 | blink blue on=0.5 sec and blue off=2.5 sec
+ *
+ * data | SATA LED mode
+ * -------------------------------------------------
+ * 0 | fix off
+ * 1 | SATA activity blink
+ * 2 | fix red on
+ * 3 | blink blue on=1 sec and blue off=1 sec
+ * 4 | blink red on=1 sec and red off=1 sec
+ * 5 | blink blue on=2.5 sec and red on=0.5 sec
+ * 6 | blink blue on=1 sec and red on=1 sec
+ * 7 | fix blue on
+ */
+static void init_leds(void)
+{
+ /* Enable the front blue LED */
+ cpld_gpio_bus_write(&cpld_gpio_bus, 0, 1);
+ cpld_gpio_bus_write(&cpld_gpio_bus, 1, 3);
+
+ /* Configure SATA LEDs to blink in relation with the SATA activity */
+ cpld_gpio_bus_write(&cpld_gpio_bus, 3, 1);
+ cpld_gpio_bus_write(&cpld_gpio_bus, 4, 1);
+ cpld_gpio_bus_write(&cpld_gpio_bus, 2, 3);
+}
+#else
+static void init_leds(void) {}
+#endif /* CONFIG_NET2BIG_V2 && CONFIG_KIRKWOOD_GPIO */
+
+int misc_init_r(void)
+{
+ init_fan();
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+ if (!getenv("ethaddr")) {
+ uchar mac[6];
+ if (lacie_read_mac_address(mac) == 0)
+ eth_setenv_enetaddr("ethaddr", mac);
+ }
+#endif
+ init_leds();
+
+ return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+ mv_phy_88e1116_init("egiga0", 8);
+}
+#endif
+
+#if defined(CONFIG_KIRKWOOD_GPIO)
+/* Return GPIO push button status */
+static int
+do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON);
+}
+
+U_BOOT_CMD(button, 1, 1, do_read_push_button,
+ "Return GPIO push button status 0=off 1=on", "");
+#endif
diff --git a/board/LaCie/net2big_v2/net2big_v2.h b/board/LaCie/net2big_v2/net2big_v2.h
new file mode 100644
index 0000000..8dead89
--- /dev/null
+++ b/board/LaCie/net2big_v2/net2big_v2.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef NET2BIG_V2_H
+#define NET2BIG_V2_H
+
+/* GPIO configuration */
+#define NET2BIG_V2_OE_LOW 0x0600E000
+#define NET2BIG_V2_OE_HIGH 0x00000134
+#define NET2BIG_V2_OE_VAL_LOW 0x10030000
+#define NET2BIG_V2_OE_VAL_HIGH 0x00000000
+
+/* Buttons */
+#define NET2BIG_V2_GPIO_PUSH_BUTTON 34
+
+/* GMT G762 registers (I2C fan controller) */
+#define G762_REG_SET_CNT 0x00
+#define G762_REG_SET_OUT 0x03
+#define G762_REG_FAN_CMD1 0x04
+
+#endif /* NET2BIG_V2_H */
diff --git a/board/LaCie/netspace_v2/Kconfig b/board/LaCie/netspace_v2/Kconfig
new file mode 100644
index 0000000..930b822
--- /dev/null
+++ b/board/LaCie/netspace_v2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NETSPACE_V2
+
+config SYS_BOARD
+ default "netspace_v2"
+
+config SYS_VENDOR
+ default "LaCie"
+
+config SYS_CONFIG_NAME
+ default "lacie_kw"
+
+endif
diff --git a/board/LaCie/netspace_v2/MAINTAINERS b/board/LaCie/netspace_v2/MAINTAINERS
new file mode 100644
index 0000000..55fd50d
--- /dev/null
+++ b/board/LaCie/netspace_v2/MAINTAINERS
@@ -0,0 +1,14 @@
+NETSPACE_V2 BOARD
+M: Simon Guinot <simon.guinot@sequanux.org>
+S: Maintained
+F: board/LaCie/netspace_v2/
+F: include/configs/lacie_kw.h
+F: configs/inetspace_v2_defconfig
+F: configs/netspace_max_v2_defconfig
+F: configs/netspace_v2_defconfig
+
+NETSPACE_LITE_V2 BOARD
+#M: -
+S: Maintained
+F: configs/netspace_lite_v2_defconfig
+F: configs/netspace_mini_v2_defconfig
diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile
new file mode 100644
index 0000000..47778d8
--- /dev/null
+++ b/board/LaCie/netspace_v2/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := netspace_v2.o ../common/common.o
diff --git a/board/LaCie/netspace_v2/kwbimage-is2.cfg b/board/LaCie/netspace_v2/kwbimage-is2.cfg
new file mode 100644
index 0000000..98713ea
--- /dev/null
+++ b/board/LaCie/netspace_v2/kwbimage-is2.cfg
@@ -0,0 +1,151 @@
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618 # DDR Configuration register
+# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000008 # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 10, Cs0size=512Mb
+# bit5-4: 00, Cs2width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000632 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 1, DDR drive strenght reduced
+# bit2: 1, DDR ODT control lsd enabled
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, enabled
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 1 , D2P Latency enabled
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
+# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
new file mode 100644
index 0000000..6b32193
--- /dev/null
+++ b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
@@ -0,0 +1,151 @@
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618 # DDR Configuration register
+# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x34143000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000DDDD # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 10, Cs0size=512Mb
+# bit5-4: 00, Cs2width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000632 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 1, DDR drive strenght reduced
+# bit2: 1, DDR ODT control lsd enabled
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, enabled
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 1 , D2P Latency enabled
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
+# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/LaCie/netspace_v2/kwbimage.cfg b/board/LaCie/netspace_v2/kwbimage.cfg
new file mode 100644
index 0000000..1515f81
--- /dev/null
+++ b/board/LaCie/netspace_v2/kwbimage.cfg
@@ -0,0 +1,151 @@
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618 # DDR Configuration register
+# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000C # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs2width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000632 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 1, DDR drive strenght reduced
+# bit2: 1, DDR ODT control lsd enabled
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, enabled
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 1 , D2P Latency enabled
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
+# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c
new file mode 100644
index 0000000..17e6296
--- /dev/null
+++ b/board/LaCie/netspace_v2/netspace_v2.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#include "netspace_v2.h"
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /* Gpio configuration */
+ mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
+ NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_SPI_SCn,
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO, /* Fan speed (bit 1) */
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO, /* Red led */
+ MPP14_GPIO, /* USB fuse */
+ MPP16_GPIO, /* SATA 0 power */
+ MPP17_GPIO, /* SATA 1 power */
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_SATA1_ACTn,
+ MPP21_SATA0_ACTn,
+ MPP22_GPIO, /* Fan speed (bit 0) */
+ MPP23_GPIO, /* Fan power */
+ MPP24_GPIO, /* USB mode select */
+ MPP25_GPIO, /* Fan rotation fail */
+ MPP26_GPIO, /* USB vbus-in detection */
+ MPP28_GPIO, /* USB enable vbus-out */
+ MPP29_GPIO, /* Blue led (slow register) */
+ MPP30_GPIO, /* Blue led (command register) */
+ MPP31_GPIO, /* Board power off */
+ MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */
+ MPP33_GPIO, /* Fan speed (bit 2) */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Machine number */
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+ /* Boot parameters address */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+ if (!getenv("ethaddr")) {
+ uchar mac[6];
+ if (lacie_read_mac_address(mac) == 0)
+ eth_setenv_enetaddr("ethaddr", mac);
+ }
+#endif
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+ mv_phy_88e1318_init("egiga0", 0);
+#else
+ mv_phy_88e1116_init("egiga0", 8);
+#endif
+}
+#endif
+
+#if defined(CONFIG_KIRKWOOD_GPIO)
+/* Return GPIO button status */
+static int
+do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON);
+}
+
+U_BOOT_CMD(button, 1, 1, do_read_button,
+ "Return GPIO button status 0=off 1=on", "");
+#endif
diff --git a/board/LaCie/netspace_v2/netspace_v2.h b/board/LaCie/netspace_v2/netspace_v2.h
new file mode 100644
index 0000000..cdf5238
--- /dev/null
+++ b/board/LaCie/netspace_v2/netspace_v2.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef NETSPACE_V2_H
+#define NETSPACE_V2_H
+
+/* GPIO configuration */
+#define NETSPACE_V2_OE_LOW 0x06004000
+#define NETSPACE_V2_OE_HIGH 0x00000031
+#define NETSPACE_V2_OE_VAL_LOW 0x10030000
+#define NETSPACE_V2_OE_VAL_HIGH 0x00000000
+
+#define NETSPACE_V2_GPIO_BUTTON 32
+
+#endif /* NETSPACE_V2_H */
diff --git a/board/LaCie/wireless_space/Kconfig b/board/LaCie/wireless_space/Kconfig
new file mode 100644
index 0000000..75a2fc5
--- /dev/null
+++ b/board/LaCie/wireless_space/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_WIRELESS_SPACE
+
+config SYS_BOARD
+ default "wireless_space"
+
+config SYS_VENDOR
+ default "LaCie"
+
+config SYS_CONFIG_NAME
+ default "wireless_space"
+
+endif
diff --git a/board/LaCie/wireless_space/MAINTAINERS b/board/LaCie/wireless_space/MAINTAINERS
new file mode 100644
index 0000000..c32ecb8
--- /dev/null
+++ b/board/LaCie/wireless_space/MAINTAINERS
@@ -0,0 +1,6 @@
+WIRELESS_SPACE BOARD
+M: Albert ARIBAUD <albert.u.boot@aribaud.net>
+S: Maintained
+F: board/LaCie/wireless_space/
+F: include/configs/wireless_space.h
+F: configs/wireless_space_defconfig
diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile
new file mode 100644
index 0000000..90a84f4
--- /dev/null
+++ b/board/LaCie/wireless_space/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := wireless_space.o ../common/common.o
diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg
new file mode 100644
index 0000000..037248b
--- /dev/null
+++ b/board/LaCie/wireless_space/kwbimage.cfg
@@ -0,0 +1,71 @@
+#
+# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# Based on netspace_v2 kwbimage.cfg:
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand # Boot from NAND flash
+NAND_PAGE_SIZE 800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Values taken from image original LaCie U-Boot header dump!
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+
+DATA 0xFFD01404 0x37743000 # DDR Controller Control Low
+
+DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
+
+DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
+
+DATA 0xFFD01410 0x0000CCCC # DDR Address Control
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+
+DATA 0xFFD0141C 0x00000662 # DDR Mode
+
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+
+DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
+
+DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
+
+DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x66666666
+DATA 0xFFD10000 0x01112222
+DATA 0xFFD1000C 0x00000000
+DATA 0xFFD10104 0x00000000
+DATA 0xFFD10100 0x40000000
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c
new file mode 100644
index 0000000..8620e4b
--- /dev/null
+++ b/board/LaCie/wireless_space/wireless_space.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#include "../common/common.h"
+#include "netdev.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO configuration: start FAN at low speed, USB and HDD */
+
+#define WIRELESS_SPACE_OE_LOW 0xFF006808
+#define WIRELESS_SPACE_OE_HIGH 0x0000F989
+#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080
+#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240
+
+#define WIRELESS_SPACE_REAR_BUTTON 13
+#define WIRELESS_SPACE_FRONT_BUTTON 43
+
+const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO, /* Fan speed (bit 1) */
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP13_GPIO, /* Red led */
+ MPP14_GPIO, /* USB fuse */
+ MPP15_SATA0_ACTn,
+ MPP16_GPIO, /* SATA 0 power */
+ MPP17_GPIO, /* SATA 1 power */
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0, /* Gigabit Ethernet 1 */
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GE1_8,
+ MPP29_GE1_9,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GE1_14,
+ MPP35_GE1_15,
+ MPP36_GPIO, /* Fan speed (bit 2) */
+ MPP37_GPIO, /* Fan speed (bit 0) */
+ MPP38_GPIO, /* Fan power */
+ MPP39_GPIO, /* Fan rotation fail */
+ MPP40_GPIO, /* Ethernet switch link */
+ MPP41_GPIO, /* USB enable host vbus */
+ MPP42_GPIO, /* LED clock control */
+ MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */
+ MPP44_GPIO, /* Red LED on/off */
+ MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */
+ MPP46_GPIO, /* Green LED on/off */
+ MPP47_GPIO, /* LED (blue, green) SATA activity blink */
+ MPP48_GPIO, /* Blue LED on/off */
+ 0
+};
+
+struct mv88e61xx_config swcfg = {
+ .name = "egiga0",
+ .vlancfg = MV88E61XX_VLANCFG_ROUTER,
+ .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
+ .led_init = MV88E61XX_LED_INIT_EN,
+ .mdip = MV88E61XX_MDIP_NOCHANGE,
+ .portstate = MV88E61XX_PORTSTT_FORWARDING,
+ .cpuport = 0x20,
+ .ports_enabled = 0x3F,
+};
+
+int board_early_init_f(void)
+{
+ /* Gpio configuration */
+ mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
+ WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Machine number */
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+ /* Boot parameters address */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+ if (!getenv("ethaddr")) {
+ uchar mac[6];
+ if (lacie_read_mac_address(mac) == 0)
+ eth_setenv_enetaddr("ethaddr", mac);
+ }
+#endif
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+ /* configure switch on egiga0 */
+ mv88e61xx_switch_initialize(&swcfg);
+}
+#endif
+
+#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD)
+/* Return GPIO button status */
+static int
+do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (strcmp(argv[1], "button") == 0) {
+ if (strcmp(argv[2], "rear") == 0)
+ /* invert GPIO result for intuitive while/until use */
+ return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON);
+ else if (strcmp(argv[2], "front") == 0)
+ return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON);
+ else
+ return -1;
+ } else {
+ return -1;
+ }
+}
+
+U_BOOT_CMD(ws, 3, 0, do_ws,
+ "Return GPIO button status 0=off 1=on",
+ "- ws button rear|front: test buttons' states\n"
+);
+#endif
diff --git a/board/Marvell/aspenite/Kconfig b/board/Marvell/aspenite/Kconfig
new file mode 100644
index 0000000..4dd49c4
--- /dev/null
+++ b/board/Marvell/aspenite/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ASPENITE
+
+config SYS_BOARD
+ default "aspenite"
+
+config SYS_VENDOR
+ default "Marvell"
+
+config SYS_SOC
+ default "armada100"
+
+config SYS_CONFIG_NAME
+ default "aspenite"
+
+endif
diff --git a/board/Marvell/aspenite/MAINTAINERS b/board/Marvell/aspenite/MAINTAINERS
new file mode 100644
index 0000000..a77d30e
--- /dev/null
+++ b/board/Marvell/aspenite/MAINTAINERS
@@ -0,0 +1,6 @@
+ASPENITE BOARD
+M: Prafulla Wadaskar <prafulla@marvell.com>
+S: Maintained
+F: board/Marvell/aspenite/
+F: include/configs/aspenite.h
+F: configs/aspenite_defconfig
diff --git a/board/Marvell/aspenite/Makefile b/board/Marvell/aspenite/Makefile
new file mode 100644
index 0000000..726d0e4
--- /dev/null
+++ b/board/Marvell/aspenite/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Contributor: Mahavir Jain <mjain@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := aspenite.o
diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c
new file mode 100644
index 0000000..24ee679
--- /dev/null
+++ b/board/Marvell/aspenite/aspenite.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ u32 mfp_cfg[] = {
+ /* I2C */
+ MFP105_CI2C_SDA,
+ MFP106_CI2C_SCL,
+
+ /* Enable Console on UART1 */
+ MFP107_UART1_RXD,
+ MFP108_UART1_TXD,
+
+ MFP_EOC /*End of configureation*/
+ };
+ /* configure MFP's */
+ mfp_config(mfp_cfg);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of Board */
+ gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+ return 0;
+}
diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt
new file mode 100644
index 0000000..6cae9ea
--- /dev/null
+++ b/board/Marvell/common/bootseq.txt
@@ -0,0 +1,94 @@
+(cpu/mpc7xxx/start.S)
+
+start:
+ b boot_cold
+
+start_warm:
+ b boot_warm
+
+
+boot_cold:
+boot_warm:
+ clear bats
+ init l2 (if enabled)
+ init altivec (if enabled)
+ invalidate l2 (if enabled)
+ setup bats (from defines in config_EVB)
+ enable_addr_trans: (if MMU enabled)
+ enable MSR_IR and MSR_DR
+ jump to in_flash
+
+in_flash:
+ enable l1 dcache
+ gal_low_init: (board/evb64260/sdram_init.S)
+ config SDRAM (CFG, TIMING, DECODE)
+ init scratch regs (810 + 814)
+
+ detect DIMM0 (bank 0 only)
+ config SDRAM_PARA0 to 256/512Mbit
+ bl sdram_op_mode
+ detect bank0 width
+ write scratch reg 810
+ config SDRAM_PARA0 with results
+ config SDRAM_PARA1 with results
+
+ detect DIMM1 (bank 2 only)
+ config SDRAM_PARA2 to 256/512Mbit
+ detect bank2 width
+ write scratch reg 814
+ config SDRAM_PARA2 with results
+ config SDRAM_PARA3 with results
+
+ setup device bus timings/width
+ setup boot device timings/width
+
+ setup CPU_CONF (0x0)
+ setup cpu master control register 0x160
+ setup PCI0 TIMEOUT
+ setup PCI1 TIMEOUT
+ setup PCI0 BAR
+ setup PCI1 BAR
+
+ setup MPP control 0-3
+ setup GPP level control
+ setup Serial ports multiplex
+
+ setup stack pointer (r1)
+ setup GOT
+ call cpu_init_f
+ debug leds
+ board_init_f: (common/board.c)
+ board_early_init_f:
+ remap gt regs?
+ map PCI mem/io
+ map device space
+ clear out interrupts
+ init_timebase
+ env_init
+ serial_init
+ console_init_f
+ display_options
+ initdram: (board/evb64260/evb64260.c)
+ detect memory
+ for each bank:
+ dram_size()
+ setup PCI slave memory mappings
+ setup SCS
+ setup monitor
+ alloc board info struct
+ init bd struct
+ relocate_code: (cpu/mpc7xxx/start.S)
+ copy,got,clearbss
+ board_init_r(bd, dest_addr) (common/board.c)
+ setup bd function pointers
+ trap_init
+ flash_init: (board/evb64260/flash.c)
+ setup bd flash info
+ cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
+ nothing
+ mem_malloc_init
+ malloc_bin_reloc
+ spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
+ env_relocated
+ misc_init_r(bd): (board/evb64260/evb64260.c)
+ mpsc_init2
diff --git a/board/Marvell/common/i2c.h b/board/Marvell/common/i2c.h
new file mode 100644
index 0000000..a879ea9
--- /dev/null
+++ b/board/Marvell/common/i2c.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ */
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+/* function declarations */
+uchar i2c_read(uchar, unsigned int, int, uchar*, int);
+
+#endif
diff --git a/board/Marvell/common/intel_flash.h b/board/Marvell/common/intel_flash.h
new file mode 100644
index 0000000..5531f95
--- /dev/null
+++ b/board/Marvell/common/intel_flash.h
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Hacked for the marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ */
+
+/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
+
+/*
+ * acceptable chips types are:
+ *
+ * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
+ */
+
+/* register addresses, valid only following an CHIP_CMD_RD_ID command */
+#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */
+#define CHIP_ADDR_REG_DEV 0x000001 /* device id */
+#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */
+#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */
+
+/* Commands */
+#define CHIP_CMD_RST 0xFF /* reset flash */
+#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */
+#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */
+#define CHIP_CMD_RD_STAT 0x70 /* read the status register */
+#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */
+#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */
+#define CHIP_CMD_PROG 0x40 /* program word command */
+#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */
+#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */
+#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */
+#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */
+#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */
+#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */
+#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */
+
+/* status register bits */
+#define CHIP_STAT_DPS 0x02 /* Device Protect Status */
+#define CHIP_STAT_VPPS 0x08 /* VPP Status */
+#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */
+#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */
+#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */
+#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */
+
+#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \
+ CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
+
+/* ID and Lock Configuration */
+#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */
+#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
+#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID
+
+/* dimensions */
+#define CHIP_WIDTH 2 /* chips are in 16 bit mode */
+#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */
+#define CHIP_NBLOCKS 128
+#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */
+#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS)
+
+/********************** DEFINES for Hymod Flash ******************************/
+
+/*
+ * The hymod board has 2 x 28F320J5 chips running in
+ * 16 bit mode, for a 32 bit wide bank.
+ */
+
+typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */
+typedef volatile bank_word_t *bank_addr_t;
+typedef unsigned long bank_size_t; /* want this big - >= 32 bit */
+
+#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */
+#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */
+
+#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH)
+#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT)
+#define BANK_NBLOCKS CHIP_NBLOCKS
+#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH)
+#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH)
+
+#define MAX_BANKS 1 /* only one bank possible */
+
+/* align bank addresses and sizes to bank word boundaries */
+#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
+ & ~(BANK_WIDTH - 1)))
+#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \
+ (bank_size_t)(s) + (BANK_WIDTH - 1)))
+
+/* align bank addresses and sizes to bank block boundaries */
+#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
+ & ~(BANK_BLKSZ - 1)))
+#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \
+ (bank_size_t)(s) + (BANK_BLKSZ - 1)))
+
+/* align bank addresses and sizes to bank boundaries */
+#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
+ & ~(BANK_SIZE - 1)))
+#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \
+ (bank_size_t)(s) + (BANK_SIZE - 1)))
+
+/* add an offset to a bank address */
+#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \
+ (bank_size_t)(o))
+
+/* get base address of bank b, given flash base address a */
+#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+ (bank_size_t)(b) * BANK_SIZE)
+
+/* adjust a bank address to start of next word, block or bank */
+#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
+ BANK_WIDTH)
+#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
+ BANK_BLKSZ)
+#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+ BANK_SIZE)
+
+/* get bank address of chip register r given a bank base address a */
+#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+ ((bank_size_t)(r) << BANK_WSHIFT))
+
+/* make a bank address for each chip register address */
+
+#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
+#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
+#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
+#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
+
+/*
+ * replicate a chip cmd/stat/rd value into each byte position within a word
+ * so that multiple chips are accessed in a single word i/o operation
+ *
+ * this must be as wide as the bank_word_t type, and take into account the
+ * chip width and bank layout
+ */
+
+#define BANK_FILL_WORD(o) ((bank_word_t)(o))
+
+/* make a bank word value for each chip cmd/stat/rd value */
+
+/* Commands */
+#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST)
+#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID)
+#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT)
+#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
+#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1)
+#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2)
+#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG)
+#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK)
+#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
+#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
+#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS)
+#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS)
+#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS)
+#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS)
+#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS)
+#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS)
+#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY)
+
+#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR)
+
+/* ID and Lock Configuration */
+#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK)
+#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN)
+#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV)
diff --git a/board/Marvell/common/memory.c b/board/Marvell/common/memory.c
new file mode 100644
index 0000000..610b411
--- /dev/null
+++ b/board/Marvell/common/memory.c
@@ -0,0 +1,1374 @@
+/*
+ * Copyright - Galileo technology.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ *
+ * written or collected and sometimes rewritten by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ */
+
+
+#include <common.h>
+#include "../include/core.h"
+#include "../include/memory.h"
+
+/*******************************************************************************
+* memoryGetBankBaseAddress - Returns the base address of a memory bank.
+* DESCRIPTION:
+* This function returns the base address of one of the SDRAM's memory
+* banks. There are 4 memory banks and each one represents one DIMM side.
+* INPUT:
+* MEMORY_BANK bank - Selects one of the four banks as defined in Memory.h.
+* OUTPUT:
+* None.
+* RETURN:
+* 32 bit Memory bank base address.
+*******************************************************************************/
+static unsigned long memoryGetBankRegOffset (MEMORY_BANK bank)
+{
+ switch (bank) {
+ case BANK0:
+ return SCS_0_LOW_DECODE_ADDRESS;
+ case BANK1:
+ return SCS_1_LOW_DECODE_ADDRESS;
+ case BANK2:
+ return SCS_2_LOW_DECODE_ADDRESS;
+ case BANK3:
+ return SCS_3_LOW_DECODE_ADDRESS;
+
+ }
+ return SCS_0_LOW_DECODE_ADDRESS; /* default value */
+}
+
+unsigned int memoryGetBankBaseAddress (MEMORY_BANK bank)
+{
+ unsigned int base;
+ unsigned int regOffset = memoryGetBankRegOffset (bank);
+
+ GT_REG_READ (regOffset, &base);
+ base = base << 16; /* MV6436x */
+ return base;
+}
+
+/*******************************************************************************
+* memoryGetDeviceBaseAddress - Returns the base address of a device.
+* DESCRIPTION:
+* This function returns the base address of a device on the system. There
+* are 5 possible devices (0 - 4 and one boot device) as defined in
+* gtMemory.h. Each of the device parameters is maped to one of the CS
+* (Devices chip selects) base address register.
+* INPUT:
+* device - Selects one of the five devices as defined in Memory.h.
+* OUTPUT:
+* None.
+* RETURN:
+* 32 bit Device base address.
+*
+*******************************************************************************/
+static unsigned int memoryGetDeviceRegOffset (DEVICE device)
+{
+ switch (device) {
+ case DEVICE0:
+ return CS_0_LOW_DECODE_ADDRESS;
+ case DEVICE1:
+ return CS_1_LOW_DECODE_ADDRESS;
+ case DEVICE2:
+ return CS_2_LOW_DECODE_ADDRESS;
+ case DEVICE3:
+ return CS_3_LOW_DECODE_ADDRESS;
+ case BOOT_DEVICE:
+ return BOOTCS_LOW_DECODE_ADDRESS;
+ }
+ return CS_0_LOW_DECODE_ADDRESS; /* default value */
+}
+
+unsigned int memoryGetDeviceBaseAddress (DEVICE device)
+{
+ unsigned int regBase;
+ unsigned int regOffset = memoryGetDeviceRegOffset (device);
+
+ GT_REG_READ (regOffset, ®Base);
+
+ regBase = regBase << 16; /* MV6436x */
+ return regBase;
+}
+
+/*******************************************************************************
+* MemoryGetPciBaseAddr - Returns the base address of a PCI window.
+* DESCRIPTION:
+* This function returns the base address of a PCI window. There are 5
+* possible PCI windows (memory 0 - 3 and one for I/O) for each PCI
+* interface as defined in gtMemory.h, used by the CPU's address decoding
+* mechanism.
+* New in MV6436x
+* INPUT:
+* pciWindow - Selects one of the PCI windows as defined in Memory.h.
+* OUTPUT:
+* None.
+* RETURN:
+* 32 bit PCI window base address.
+*******************************************************************************/
+unsigned int MemoryGetPciBaseAddr (PCI_MEM_WINDOW pciWindow)
+{
+ unsigned int baseAddrReg, base;
+
+ switch (pciWindow) {
+ case PCI_0_IO:
+ baseAddrReg = PCI_0I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */
+ break;
+ case PCI_0_MEM0:
+ baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */
+ break;
+ case PCI_0_MEM1:
+ baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */
+ break;
+ case PCI_0_MEM2:
+ baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */
+ break;
+ case PCI_0_MEM3:
+ baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */
+ break;
+#ifdef INCLUDE_PCI_1
+ case PCI_1_IO:
+ baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */
+ break;
+ case PCI_1_MEM0:
+ baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */
+ break;
+ case PCI_1_MEM1:
+ baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */
+ break;
+ case PCI_1_MEM2:
+ baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */
+ break;
+ case PCI_1_MEM3:
+ baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */
+ break;
+#endif /* INCLUDE_PCI_1 */
+ default:
+ return 0xffffffff;
+ }
+ GT_REG_READ (baseAddrReg, &base);
+ return (base << 16);
+}
+
+/*******************************************************************************
+* memoryGetBankSize - Returns the size of a memory bank.
+* DESCRIPTION:
+* This function returns the size of memory bank as described in
+* 'gtMemoryGetBankBaseAddress' function.
+* INPUT:
+* bank - Selects one of the four banks as defined in Memory.h.
+* OUTPUT:
+* None.
+* RETURN:
+* 32 bit size memory bank size or 0 for a closed or non populated bank.
+*
+*******************************************************************************/
+unsigned int memoryGetBankSize (MEMORY_BANK bank)
+{
+ unsigned int sizeReg, size;
+ MEMORY_WINDOW window;
+
+ switch (bank) {
+ case BANK0:
+ sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /* CS_0_SIZE; */
+ window = CS_0_WINDOW;
+ break;
+ case BANK1:
+ sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /* CS_1_SIZE; */
+ window = CS_1_WINDOW;
+ break;
+ case BANK2:
+ sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /* CS_2_SIZE; */
+ window = CS_2_WINDOW;
+ break;
+ case BANK3:
+ sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /* CS_3_SIZE; */
+ window = CS_3_WINDOW;
+ break;
+ default:
+ return 0;
+ break;
+ }
+ /* If the window is closed, a size of 0 is returned */
+ if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
+ return 0;
+ GT_REG_READ (sizeReg, &size);
+ size = ((size << 16) | 0xffff) + 1;
+ return size;
+}
+
+/*******************************************************************************
+* memoryGetDeviceSize - Returns the size of a device memory space.
+* DESCRIPTION:
+* This function returns the memory space size of a given device.
+* INPUT:
+* device - Selects one of the five devices as defined in Memory.h.
+* OUTPUT:
+* None.
+* RETURN:
+* 32 bit size of a device memory space.
+*******************************************************************************/
+unsigned int memoryGetDeviceSize (DEVICE device)
+{
+ unsigned int sizeReg, size;
+ MEMORY_WINDOW window;
+
+ switch (device) {
+ case DEVICE0:
+ sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */
+ window = DEVCS_0_WINDOW;
+ break;
+ case DEVICE1:
+ sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */
+ window = DEVCS_1_WINDOW;
+ break;
+ case DEVICE2:
+ sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */
+ window = DEVCS_2_WINDOW;
+ break;
+ case DEVICE3:
+ sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */
+ window = DEVCS_3_WINDOW;
+ break;
+ case BOOT_DEVICE:
+ sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */
+ window = BOOT_CS_WINDOW;
+ break;
+ default:
+ return 0;
+ break;
+ }
+ /* If the window is closed, a size of 0 is returned */
+ if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
+ return 0;
+ GT_REG_READ (sizeReg, &size);
+ size = ((size << 16) | 0xffff) + 1;
+ return size;
+}
+
+/*******************************************************************************
+* MemoryGetPciWindowSize - Returns the size of a PCI memory window.
+* DESCRIPTION:
+* This function returns the size of a PCI window.
+* INPUT:
+* pciWindow - Selects one of the PCI memory windows as defined in
+* Memory.h.
+* OUTPUT:
+* None.
+* RETURN:
+* 32 bit size of a PCI memory window.
+*******************************************************************************/
+unsigned int MemoryGetPciWindowSize (PCI_MEM_WINDOW pciWindow)
+{
+ unsigned int sizeReg, size;
+
+ switch (pciWindow) {
+ case PCI_0_IO:
+ sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */
+ break;
+ case PCI_0_MEM0:
+ sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */
+ break;
+ case PCI_0_MEM1:
+ sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */
+ break;
+ case PCI_0_MEM2:
+ sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */
+ break;
+ case PCI_0_MEM3:
+ sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */
+ break;
+#ifdef INCLUDE_PCI_1
+ case PCI_1_IO:
+ sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */
+ break;
+ case PCI_1_MEM0:
+ sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */
+ break;
+ case PCI_1_MEM1:
+ sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */
+ break;
+ case PCI_1_MEM2:
+ sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */
+ break;
+ case PCI_1_MEM3:
+ sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */
+ break;
+#endif /* INCLUDE_PCI_1 */
+ default:
+ return 0x0;
+ }
+ /* If the memory window is disabled, retrun size = 0 */
+ if (MemoryGetMemWindowStatus (PCI_0_IO_WINDOW << pciWindow)
+ == MEM_WINDOW_DISABLED)
+ return 0;
+ GT_REG_READ (sizeReg, &size);
+ size = ((size << 16) | 0xffff) + 1;
+ return size;
+}
+
+/*******************************************************************************
+* memoryGetDeviceWidth - Returns the width of a given device.
+* DESCRIPTION:
+* The MV's device interface supports up to 32 Bit wide devices. A device
+* can have a 1, 2, 4 or 8 Bytes data width. This function returns the
+* width of a device as defined by the user or the operating system.
+* INPUT:
+* device - Selects one of the five devices as defined in Memory.h.
+* OUTPUT:
+* None.
+* RETURN:
+* Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
+*******************************************************************************/
+unsigned int memoryGetDeviceWidth (DEVICE device)
+{
+ unsigned int width;
+ unsigned int regValue;
+
+ GT_REG_READ (DEVICE_BANK0PARAMETERS + device * 4, ®Value);
+ width = (regValue & (BIT20 | BIT21)) >> 20;
+ return (BIT0 << width);
+}
+
+/*******************************************************************************
+* memoryMapBank - Set new base address and size for one of the memory
+* banks.
+*
+* DESCRIPTION:
+* The CPU interface address decoding map consists of 21 address windows
+* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
+* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
+* space. Each address window is defined by two registers - base and size.
+* The CPU address is compared with the values in the various CPU windows
+* until a match is found and the address is than targeted to that window.
+* This function sets new base and size for one the memory banks
+* (CS0 - CS3). It is the programmer`s responsibility to make sure that
+* there are no conflicts with other memory spaces. When two memory spaces
+* overlap, the MV's behavior is not defined .If a bank needs to be closed,
+* set the 'bankLength' parameter size to 0x0.
+*
+* INPUT:
+* bank - One of the memory banks (CS0-CS3) as defined in gtMemory.h.
+* bankBase - The memory bank base address.
+* bankLength - The memory bank size. This function will decrement the
+* 'bankLength' parameter by one and then check if the size is
+* valid. A valid size must be programed from LSB to MSB as
+* sequence of '1's followed by sequence of '0's.
+* To close a memory window simply set the size to 0.
+* NOTE!!!
+* The size must be in 64Kbyte granularity.
+* The base address must be aligned to the size.
+* OUTPUT:
+* None.
+* RETURN:
+* false for invalid size, true otherwise.
+*
+* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
+*
+*******************************************************************************/
+
+bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase,
+ unsigned int bankLength)
+{
+ unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
+
+/* PCI_INTERNAL_BAR pciBAR; */
+
+ switch (bank) {
+ case BANK0:
+ baseReg = SCS_0_LOW_DECODE_ADDRESS; /*CS_0_BASE_ADDR; */
+ sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /*CS_0_SIZE; */
+/* pciBAR = PCI_CS0_BAR; */
+ break;
+ case BANK1:
+ baseReg = SCS_1_LOW_DECODE_ADDRESS; /*CS_1_BASE_ADDR; */
+ sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /*CS_1_SIZE; */
+ /* pciBAR = SCS_0_HIGH_DECODE_ADDRESS; */ /*PCI_CS1_BAR; */
+ break;
+ case BANK2:
+ baseReg = SCS_2_LOW_DECODE_ADDRESS; /*CS_2_BASE_ADDR; */
+ sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /*CS_2_SIZE; */
+/* pciBAR = PCI_CS2_BAR;*/
+ break;
+ case BANK3:
+ baseReg = SCS_3_LOW_DECODE_ADDRESS; /*CS_3_BASE_ADDR; */
+ sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /*CS_3_SIZE; */
+/* pciBAR = PCI_CS3_BAR; */
+ break;
+ default:
+ return false;
+ }
+ /* If the size is 0, the window will be disabled */
+ if (bankLength == 0) {
+ MemoryDisableWindow (CS_0_WINDOW << bank);
+ /* Disable the BAR from the PCI slave side */
+/* gtPci0DisableInternalBAR(pciBAR); */
+/* gtPci1DisableInternalBAR(pciBAR); */
+ return true;
+ }
+ /* The base address must be aligned to the size */
+ if ((bankBase % bankLength) != 0) {
+ return false;
+ }
+ if (bankLength >= MINIMUM_MEM_BANK_SIZE) {
+ newBase = bankBase >> 16;
+ newSize = bankLength >> 16;
+ /* Checking that the size is a sequence of '1' followed by a
+ sequence of '0' starting from LSB to MSB. */
+ temp = newSize - 1;
+ for (rShift = 0; rShift < 16; rShift++) {
+ temp = temp >> rShift;
+ if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
+ /* or the size is not valid */
+ if (temp > 0x0)
+ return false;
+ else
+ break;
+ }
+ }
+#ifdef DEBUG
+ {
+ unsigned int oldBase, oldSize;
+
+ GT_REG_READ (baseReg, &oldBase);
+ GT_REG_READ (sizeReg + 8, &oldSize);
+
+ printf ("b%d Base:%x Size:%x -> Base:%x Size:%x\n",
+ bank, oldBase, oldSize, newBase, newSize);
+ }
+#endif
+ /* writing the new values */
+ GT_REG_WRITE (baseReg, newBase);
+ GT_REG_WRITE (sizeReg, newSize - 1);
+ /* Enable back the window */
+ MemoryEnableWindow (CS_0_WINDOW << bank);
+ /* Enable the BAR from the PCI slave side */
+/* gtPci0EnableInternalBAR(pciBAR); */
+/* gtPci1EnableInternalBAR(pciBAR); */
+ return true;
+ }
+ return false;
+}
+
+
+/*******************************************************************************
+* memoryMapDeviceSpace - Set new base address and size for one of the device
+* windows.
+*
+* DESCRIPTION:
+* The CPU interface address decoding map consists of 21 address windows
+* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
+* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
+* space. Each address window is defined by two registers - base and size.
+* The CPU address is compared with the values in the various CPU windows
+* until a match is found and the address is than targeted to that window.
+* This function sets new base and size for one the device windows
+* (DEV_CS0 - DEV_CS3). It is the programmer`s responsibility to make sure
+* that there are no conflicts with other memory spaces. When two memory
+* spaces overlap, the MV's behavior is not defined .If a device window
+* needs to be closed, set the 'deviceLength' parameter size to 0x0.
+*
+* INPUT:
+* device - One of the device windows (DEV_CS0-DEV_CS3) as
+* defined in gtMemory.h.
+* deviceBase - The device window base address.
+* deviceLength - The device window size. This function will decrement
+* the 'deviceLength' parameter by one and then
+* check if the size is valid. A valid size must be
+* programed from LSB to MSB as sequence of '1's
+* followed by sequence of '0's.
+* To close a memory window simply set the size to 0.
+*
+* NOTE!!!
+* The size must be in 64Kbyte granularity.
+* The base address must be aligned to the size.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* false for invalid size, true otherwise.
+*
+* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
+*
+*******************************************************************************/
+
+bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase,
+ unsigned int deviceLength)
+{
+ unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
+
+/* PCI_INTERNAL_BAR pciBAR;*/
+
+ switch (device) {
+ case DEVICE0:
+ baseReg = CS_0_LOW_DECODE_ADDRESS; /*DEV_CS0_BASE_ADDR; */
+ sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */
+/* pciBAR = PCI_DEV_CS0_BAR; */
+ break;
+ case DEVICE1:
+ baseReg = CS_1_LOW_DECODE_ADDRESS; /*DEV_CS1_BASE_ADDR; */
+ sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */
+/* pciBAR = PCI_DEV_CS1_BAR; */
+ break;
+ case DEVICE2:
+ baseReg = CS_2_LOW_DECODE_ADDRESS; /*DEV_CS2_BASE_ADDR; */
+ sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */
+/* pciBAR = PCI_DEV_CS2_BAR; */
+ break;
+ case DEVICE3:
+ baseReg = CS_3_LOW_DECODE_ADDRESS; /*DEV_CS3_BASE_ADDR; */
+ sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */
+/* pciBAR = PCI_DEV_CS3_BAR; */
+ break;
+ case BOOT_DEVICE:
+ baseReg = BOOTCS_LOW_DECODE_ADDRESS; /*BOOTCS_BASE_ADDR; */
+ sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */
+/* pciBAR = PCI_BOOT_CS_BAR; */
+ break;
+ default:
+ return false;
+ }
+ if (deviceLength == 0) {
+ MemoryDisableWindow (DEVCS_0_WINDOW << device);
+ /* Disable the BAR from the PCI slave side */
+/* gtPci0DisableInternalBAR(pciBAR); */
+/* gtPci1DisableInternalBAR(pciBAR); */
+ return true;
+ }
+ /* The base address must be aligned to the size */
+ if ((deviceBase % deviceLength) != 0) {
+ return false;
+ }
+ if (deviceLength >= MINIMUM_DEVICE_WINDOW_SIZE) {
+ newBase = deviceBase >> 16;
+ newSize = deviceLength >> 16;
+ /* Checking that the size is a sequence of '1' followed by a
+ sequence of '0' starting from LSB to MSB. */
+ temp = newSize - 1;
+ for (rShift = 0; rShift < 16; rShift++) {
+ temp = temp >> rShift;
+ if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
+ /* or the size is not valid */
+ if (temp > 0x0)
+ return false;
+ else
+ break;
+ }
+ }
+ /* writing the new values */
+ GT_REG_WRITE (baseReg, newBase);
+ GT_REG_WRITE (sizeReg, newSize - 1);
+ MemoryEnableWindow (DEVCS_0_WINDOW << device);
+ /* Enable the BAR from the PCI slave side */
+/* gtPci0EnableInternalBAR(pciBAR); */
+/* gtPci1EnableInternalBAR(pciBAR); */
+ return true;
+ }
+ return false;
+}
+
+/*******************************************************************************
+* MemorySetPciWindow - Set new base address and size for one of the PCI
+* windows.
+*
+* DESCRIPTION:
+* The CPU interface address decoding map consists of 21 address windows
+* for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
+* window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
+* space. Each address window is defined by two registers - base and size.
+* The CPU address is compared with the values in the various CPU windows
+* until a match is found and the address is than targeted to that window.
+* This function sets new base and size for one the PCI windows
+* (PCI memory0/1/2..). It is the programmer`s responsibility to make sure
+* that there are no conflicts with other memory spaces. When two memory
+* spaces overlap, the MV's behavior is not defined. If a PCI window
+* needs to be closed, set the 'pciWindowSize' parameter size to 0x0.
+*
+* INPUT:
+* pciWindow - One of the PCI windows as defined in gtMemory.h.
+* pciWindowBase - The PCI window base address.
+* pciWindowSize - The PCI window size. This function will decrement the
+* 'pciWindowSize' parameter by one and then check if the
+* size is valid. A valid size must be programed from LSB
+* to MSB as sequence of '1's followed by sequence of '0's.
+* To close a memory window simply set the size to 0.
+*
+* NOTE!!!
+* The size must be in 64Kbyte granularity.
+* The base address must be aligned to the size.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* false for invalid size, true otherwise.
+*
+*******************************************************************************/
+bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
+ unsigned int pciWindowSize)
+{
+ unsigned int currentLow, baseAddrReg, sizeReg, temp, rShift;
+
+ switch (pciWindow) {
+ case PCI_0_IO:
+ baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */
+ sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */
+ break;
+ case PCI_0_MEM0:
+ baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */
+ sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */
+ break;
+ case PCI_0_MEM1:
+ baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */
+ sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */
+ break;
+ case PCI_0_MEM2:
+ baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */
+ sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */
+ break;
+ case PCI_0_MEM3:
+ baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */
+ sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */
+ break;
+#ifdef INCLUDE_PCI_1
+ case PCI_1_IO:
+ baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */
+ sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */
+ break;
+ case PCI_1_MEM0:
+ baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */
+ sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */
+ break;
+ case PCI_1_MEM1:
+ baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */
+ sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */
+ break;
+ case PCI_1_MEM2:
+ baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */
+ sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */
+ break;
+ case PCI_1_MEM3:
+ baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */
+ sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */
+ break;
+#endif /* INCLUDE_PCI_1 */
+ default:
+ return false;
+ }
+ if (pciWindowSize == 0) {
+ MemoryDisableWindow (PCI_0_IO_WINDOW << pciWindow);
+ return true;
+ }
+ /* The base address must be aligned to the size */
+ if ((pciWindowBase % pciWindowSize) != 0) {
+ return false;
+ }
+ if (pciWindowSize >= MINIMUM_PCI_WINDOW_SIZE) {
+ pciWindowBase >>= 16;
+ pciWindowSize >>= 16;
+ /* Checking that the size is a sequence of '1' followed by a
+ sequence of '0' starting from LSB to MSB. */
+ temp = pciWindowSize - 1;
+ for (rShift = 0; rShift < 16; rShift++) {
+ temp = temp >> rShift;
+ if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
+ /* or the size is not valid */
+ if (temp > 0x0)
+ return false;
+ else
+ break;
+ }
+ }
+ GT_REG_WRITE (sizeReg, pciWindowSize - 1);
+ GT_REG_READ (baseAddrReg, ¤tLow);
+ pciWindowBase =
+ (pciWindowBase & 0xfffff) | (currentLow & 0xfff00000);
+ GT_REG_WRITE (baseAddrReg, pciWindowBase);
+ MemoryEnableWindow (PCI_0_IO_WINDOW << pciWindow);
+ return true;
+ }
+ return false;
+}
+
+/*******************************************************************************
+* memoryMapInternalRegistersSpace - Sets new base address for the internal
+* registers memory space.
+*
+* DESCRIPTION:
+* This function set new base address for the internal registers memory
+* space (the size is fixed and cannot be modified). The function does not
+* handle overlapping with other memory spaces, it is the programer's
+* responsibility to ensure that overlapping does not occur.
+* When two memory spaces overlap, the MV's behavior is not defined.
+*
+* INPUT:
+* internalRegBase - new base address for the internal registers memory
+* space.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* true on success, false on failure
+*
+*******************************************************************************/
+/********************************************************************
+* memoryMapInternalRegistersSpace - Sets new base address for the internals
+* registers.
+*
+* INPUTS: unsigned int internalRegBase - The new base address.
+* RETURNS: true on success, false on failure
+*********************************************************************/
+bool memoryMapInternalRegistersSpace (unsigned int internalRegBase)
+{
+ unsigned int currentValue;
+ unsigned int internalValue = internalRegBase;
+
+ internalRegBase = (internalRegBase >> 16);
+ GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue);
+ internalRegBase = (currentValue & 0xff000000) | internalRegBase;
+ GT_REG_WRITE (INTERNAL_SPACE_DECODE, internalRegBase);
+ /* initializing also the global variable 'internalRegBaseAddr' */
+/* gtInternalRegBaseAddr = internalValue; */
+ INTERNAL_REG_BASE_ADDR = internalValue;
+ return true;
+}
+
+/*******************************************************************************
+* memoryGetInternalRegistersSpace - Returns the internal registers Base
+* address.
+*
+* DESCRIPTION:
+* This function returns the base address of the internal registers
+* memory space .
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* 32 bit base address of the internal registers memory space.
+*
+*******************************************************************************/
+unsigned int memoryGetInternalRegistersSpace (void)
+{
+ unsigned int currentValue = 0;
+
+ GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue);
+ return ((currentValue & 0x000fffff) << 16);
+}
+
+/*******************************************************************************
+* gtMemoryGetInternalSramBaseAddr - Returns the integrated SRAM base address.
+*
+* DESCRIPTION:
+* The Atlantis incorporate integrated 2Mbit SRAM for general use. This
+* funcnion return the SRAM's base address.
+* INPUT:
+* None.
+* OUTPUT:
+* None.
+* RETURN:
+* 32 bit SRAM's base address.
+*
+*******************************************************************************/
+unsigned int memoryGetInternalSramBaseAddr (void)
+{
+ return ((GTREGREAD (INTEGRATED_SRAM_BASE_ADDR) & 0xfffff) << 16);
+}
+
+/*******************************************************************************
+* gtMemorySetInternalSramBaseAddr - Set the integrated SRAM base address.
+*
+* DESCRIPTION:
+* The Atlantis incorporate integrated 2Mbit SRAM for general use. This
+* function sets a new base address to the SRAM .
+* INPUT:
+* sramBaseAddress - The SRAM's base address.
+* OUTPUT:
+* None.
+* RETURN:
+* None.
+*
+*******************************************************************************/
+void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress)
+{
+ GT_REG_WRITE (INTEGRATED_SRAM_BASE_ADDR, sramBaseAddress >> 16);
+}
+
+/*******************************************************************************
+* memorySetProtectRegion - Set protection mode for one of the 8 regions.
+*
+* DESCRIPTION:
+* The CPU interface supports configurable access protection. This includes
+* up to eight address ranges defined to a different protection type :
+* whether the address range is cacheable or not, whether it is writable or
+* not , and whether it is accessible or not. A Low and High registers
+* define each window while the minimum address range of each window is
+* 1Mbyte. An address driven by the CPU, in addition to the address
+* decoding and remapping process, is compared against the eight Access
+* Protection Low/High registers , if an address matches one of the windows
+* , the MV device checks the transaction type against the protection bits
+* defined in CPU Access Protection register, to determine if the access is
+* allowed. This function set a protection mode to one of the 8 possible
+* regions.
+* NOTE:
+* The CPU address windows are restricted to a size of 2 power n and the
+* start address must be aligned to the window size. For example, if using
+* a 16 MB window, the start address bits [23:0] must be 0.The MV's
+* internal registers space is not protected, even if the access protection
+* windows contain this space.
+*
+* INPUT:
+* region - selects which region to be configured. The values defined in
+* gtMemory.h:
+*
+* - MEM_REGION0
+* - MEM_REGION1
+* - etc.
+*
+* memAccess - Allows or forbids access (read or write ) to the region. The
+* values defined in gtMemory.h:
+*
+* - MEM_ACCESS_ALLOWED
+* - MEM_ACCESS_FORBIDEN
+*
+* memWrite - CPU write protection to the region. The values defined in
+* gtMemory.h:
+*
+* - MEM_WRITE_ALLOWED
+* - MEM_WRITE_FORBIDEN
+*
+* cacheProtection - Defines whether caching the region is allowed or not.
+* The values defined in gtMemory.h:
+*
+* - MEM_CACHE_ALLOWED
+* - MEM_CACHE_FORBIDEN
+*
+* baseAddress - the region's base Address.
+* regionSize - The region's size. This function will decrement the
+* 'regionSize' parameter by one and then check if the size
+* is valid. A valid size must be programed from LSB to MSB
+* as sequence of '1's followed by sequence of '0's.
+* To close a memory window simply set the size to 0.
+*
+* NOTE!!!
+* The size must be in 64Kbyte granularity.
+* The base address must be aligned to the size.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* false for invalid size, true otherwise.
+*
+*******************************************************************************/
+bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window,
+ MEMORY_ACCESS memAccess,
+ MEMORY_ACCESS_WRITE memWrite,
+ MEMORY_CACHE_PROTECT cacheProtection,
+ unsigned int baseAddress, unsigned int size)
+{
+ unsigned int dataForReg, temp, rShift;
+
+ if (size == 0) {
+ GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
+ 0x0);
+ return true;
+ }
+ /* The base address must be aligned to the size. */
+ if (baseAddress % size != 0) {
+ return false;
+ }
+ if (size >= MINIMUM_ACCESS_WIN_SIZE) {
+ baseAddress = ((baseAddress >> 16) & 0xfffff);
+ dataForReg = baseAddress | ((memAccess << 20) & BIT20) |
+ ((memWrite << 21) & BIT21) | ((cacheProtection << 22)
+ & BIT22) | BIT31;
+ GT_REG_WRITE (CPU_PROTECT_WINDOW_0_BASE_ADDR + 0x10 * window,
+ dataForReg);
+ size >>= 16;
+ /* Checking that the size is a sequence of '1' followed by a
+ sequence of '0' starting from LSB to MSB. */
+ temp = size - 1;
+ for (rShift = 0; rShift < 16; rShift++) {
+ temp = temp >> rShift;
+ if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
+ /* or the size is not valid */
+ if (temp > 0x0)
+ return false;
+ else
+ break;
+ }
+ }
+ GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
+ size - 1);
+ return true;
+ }
+ return false;
+}
+
+/*******************************************************************************
+* gtMemoryDisableProtectRegion - Disable a protected window.
+*
+* DESCRIPTION:
+* This function disable a protected window set by
+* 'gtMemorySetProtectRegion' function.
+*
+* INPUT:
+* window - one of the 4 windows ( defined in gtMemory.h ).
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+void memoryDisableProtectRegion (MEMORY_PROTECT_WINDOW window)
+{
+ RESET_REG_BITS (((CPU_PROTECT_WINDOW_0_BASE_ADDR) + (0x10 * window)),
+ BIT31);
+}
+
+/*******************************************************************************
+* memorySetPciRemapValue - Set a remap value to a PCI memory space target.
+*
+* DESCRIPTION:
+* In addition to the address decoding mechanism, the CPU has an address
+* remapping mechanism to be used by every PCI decoding window. Each PCI
+* window can be remaped to a desired address target according to the remap
+* value within the remap register. The address remapping is useful when a
+* CPU address range must be reallocated to a different location on the
+* PCI bus. Also, it enables CPU access to a PCI agent located above the
+* 4Gbyte space. On system boot, each of the PCI memory spaces is maped to
+* a defualt value (see CPU interface section in the MV spec for the
+* default values). The remap mechanism does not always produce the desired
+* address on the PCI bus because of the remap mechanism way of working
+* (to fully understand why, please see the 'Address Remapping' section in
+* the MV's spec). Therefor, this function sets a desired remap value to
+* one of the PCI memory windows and return the effective address that
+* should be used when exiting the PCI memory window. You should ALWAYS use
+* the returned value by this function when remapping a PCI window and
+* exiting it. If for example the base address of PCI0 memory 0 is
+* 0x90000000, the size is 0x03ffffff and the remap value is 0x11000000,
+* the function will return the value of 0x91000000 that MUST
+* be used to exit this memory window in order to achive the deisred
+* remapping.
+*
+* INPUT:
+* memoryWindow - One of the PCI memory windows as defined in Memory.h
+* remapValueLow - The low remap value.
+* remapValueHigh - The high remap value.
+* OUTPUT:
+* None.
+*
+* RETURN:
+* The effective base address to exit the PCI, or 0xffffffff if one of the
+* parameters is erroneous or the effective base address is higher the top
+* decode value.
+*
+*******************************************************************************/
+unsigned int memorySetPciRemapValue (PCI_MEM_WINDOW memoryWindow,
+ unsigned int remapValueHigh,
+ unsigned int remapValueLow)
+{
+ unsigned int pciMemWindowBaseAddrReg = 0, baseAddrValue = 0;
+ unsigned int pciMemWindowSizeReg = 0, windowSizeValue = 0;
+ unsigned int effectiveBaseAddress, remapRegLow, remapRegHigh;
+
+ /* Initializing the base and size variables of the PCI
+ memory windows */
+ switch (memoryWindow) {
+ case PCI_0_IO:
+ pciMemWindowBaseAddrReg = PCI_0_IO_BASE_ADDR;
+ pciMemWindowSizeReg = PCI_0_IO_SIZE;
+ remapRegLow = PCI_0_IO_ADDR_REMAP;
+ remapRegHigh = PCI_0_IO_ADDR_REMAP;
+ break;
+ case PCI_0_MEM0:
+ pciMemWindowBaseAddrReg = PCI_0_MEMORY0_BASE_ADDR;
+ pciMemWindowSizeReg = PCI_0_MEMORY0_SIZE;
+ remapRegLow = PCI_0_MEMORY0_LOW_ADDR_REMAP;
+ remapRegHigh = PCI_0_MEMORY0_HIGH_ADDR_REMAP;
+ break;
+ case PCI_0_MEM1:
+ pciMemWindowBaseAddrReg = PCI_0_MEMORY1_BASE_ADDR;
+ pciMemWindowSizeReg = PCI_0_MEMORY1_SIZE;
+ remapRegLow = PCI_0_MEMORY1_LOW_ADDR_REMAP;
+ remapRegHigh = PCI_0_MEMORY1_HIGH_ADDR_REMAP;
+ break;
+ case PCI_0_MEM2:
+ pciMemWindowBaseAddrReg = PCI_0_MEMORY2_BASE_ADDR;
+ pciMemWindowSizeReg = PCI_0_MEMORY2_SIZE;
+ remapRegLow = PCI_0_MEMORY2_LOW_ADDR_REMAP;
+ remapRegHigh = PCI_0_MEMORY2_HIGH_ADDR_REMAP;
+ break;
+ case PCI_0_MEM3:
+ pciMemWindowBaseAddrReg = PCI_0_MEMORY3_BASE_ADDR;
+ pciMemWindowSizeReg = PCI_0_MEMORY3_SIZE;
+ remapRegLow = PCI_0_MEMORY3_LOW_ADDR_REMAP;
+ remapRegHigh = PCI_0_MEMORY3_HIGH_ADDR_REMAP;
+ break;
+#ifdef INCLUDE_PCI_1
+ case PCI_1_IO:
+ pciMemWindowBaseAddrReg = PCI_1_IO_BASE_ADDR;
+ pciMemWindowSizeReg = PCI_1_IO_SIZE;
+ remapRegLow = PCI_1_IO_ADDR_REMAP;
+ remapRegHigh = PCI_1_IO_ADDR_REMAP;
+ break;
+ case PCI_1_MEM0:
+ pciMemWindowBaseAddrReg = PCI_1_MEMORY0_BASE_ADDR;
+ pciMemWindowSizeReg = PCI_1_MEMORY0_SIZE;
+ remapRegLow = PCI_1_MEMORY0_LOW_ADDR_REMAP;
+ remapRegHigh = PCI_1_MEMORY0_HIGH_ADDR_REMAP;
+ break;
+ case PCI_1_MEM1:
+ pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
+ pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
+ remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
+ remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
+ break;
+ case PCI_1_MEM2:
+ pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
+ pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
+ remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
+ remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
+ break;
+ case PCI_1_MEM3:
+ pciMemWindowBaseAddrReg = PCI_1_MEMORY3_BASE_ADDR;
+ pciMemWindowSizeReg = PCI_1_MEMORY3_SIZE;
+ remapRegLow = PCI_1_MEMORY3_LOW_ADDR_REMAP;
+ remapRegHigh = PCI_1_MEMORY3_HIGH_ADDR_REMAP;
+ break;
+#endif /* INCLUDE_PCI_1 */
+ default:
+ /* Retrun an invalid effective base address */
+ return 0xffffffff;
+ }
+ /* Writing the remap value to the remap regisers */
+ GT_REG_WRITE (remapRegHigh, remapValueHigh);
+ GT_REG_WRITE (remapRegLow, remapValueLow >> 16);
+ /* Reading the values from the base address and size registers */
+ baseAddrValue = GTREGREAD (pciMemWindowBaseAddrReg) & 0xfffff;
+ windowSizeValue = GTREGREAD (pciMemWindowSizeReg) & 0xffff;
+ /* Start calculating the effective Base Address */
+ effectiveBaseAddress = baseAddrValue << 16;
+ /* The effective base address will be combined from the chopped (if any)
+ remap value (according to the size value and remap mechanism) and the
+ window's base address */
+ effectiveBaseAddress |=
+ (((windowSizeValue << 16) | 0xffff) & remapValueLow);
+ /* If the effectiveBaseAddress exceed the window boundaries return an
+ invalid value. */
+ if (effectiveBaseAddress >
+ ((baseAddrValue << 16) + ((windowSizeValue << 16) | 0xffff)))
+ return 0xffffffff;
+ return effectiveBaseAddress;
+}
+
+/********************************************************************
+* memorySetRegionSnoopMode - This function modifys one of the 4 regions which
+* supports Cache Coherency.
+*
+*
+* Inputs: SNOOP_REGION region - One of the four regions.
+* SNOOP_TYPE snoopType - There is four optional Types:
+* 1. No Snoop.
+* 2. Snoop to WT region.
+* 3. Snoop to WB region.
+* 4. Snoop & Invalidate to WB region.
+* unsigned int baseAddress - Base Address of this region.
+* unsigned int topAddress - Top Address of this region.
+* Returns: false if one of the parameters is wrong and true else
+*********************************************************************/
+/* evb6260 code */
+#if 0
+bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
+ MEMORY_SNOOP_TYPE snoopType,
+ unsigned int baseAddress,
+ unsigned int regionLength)
+{
+ unsigned int snoopXbaseAddress;
+ unsigned int snoopXtopAddress;
+ unsigned int data;
+ unsigned int snoopHigh = baseAddress + regionLength;
+
+ if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
+ return false;
+ snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
+ snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
+ if(regionLength == 0) /* closing the region */
+ {
+ GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
+ GT_REG_WRITE(snoopXtopAddress,0);
+ return true;
+ }
+ baseAddress = baseAddress & 0xffff0000;
+ data = (baseAddress >> 16) | snoopType << 16;
+ GT_REG_WRITE(snoopXbaseAddress,data);
+ snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+ GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
+ return true;
+}
+#endif
+
+/********************************************************************
+* memoryRemapAddress - This fubction used for address remapping.
+*
+*
+* Inputs: regOffset: remap register
+* remapValue :
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*
+* Not needed function To_do !!!!
+*********************************************************************/
+bool memoryRemapAddress (unsigned int remapReg, unsigned int remapValue)
+{
+ unsigned int valueForReg;
+
+ valueForReg = (remapValue & 0xfff00000) >> 20;
+ GT_REG_WRITE (remapReg, valueForReg);
+ return true;
+}
+
+/*******************************************************************************
+* memoryGetDeviceParam - Extract the device parameters from the device bank
+* parameters register.
+*
+* DESCRIPTION:
+* To allow interfacing with very slow devices and fast synchronous SRAMs,
+* each device can be programed to different timing parameters. Each bank
+* has its own parameters register. Bank width can be programmed to 8, 16,
+* or 32-bits. Bank timing parameters can be programmed to support
+* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
+* Controllers). The MV allows you to set timing parameters and width for
+* each device through parameters register .
+* This function extracts the parameters described from the Device Bank
+* parameters register and fills the given 'deviceParam' (defined in
+* gtMemory.h) structure with the read data.
+*
+* INPUT:
+* deviceParam - pointer to a structure DEVICE_PARAM (defined in
+* Memory.h).For details about each structure field please
+* see the device timing parameter section in the MV
+* datasheet.
+* deviceNum - Select on of the five device banks (defined in
+* Memory.h) :
+*
+* - DEVICE0
+* - DEVICE1
+* - DEVICE2
+* - etc.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* false if one of the parameters is erroneous,true otherwise.
+*
+*******************************************************************************/
+/********************************************************************
+* memoryGetDeviceParam - This function used for getting device parameters from
+* DEVICE BANK PARAMETERS REGISTER
+*
+*
+* Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK
+* PARAMETERS REGISTER
+* - deviceNum : number of device
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+
+bool memoryGetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
+{
+ unsigned int valueOfReg;
+ unsigned int calcData;
+
+ if (deviceNum > 4)
+ return false;
+ GT_REG_READ (DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
+ calcData = (0x7 & valueOfReg) + ((BIT22 & valueOfReg) >> 19);
+ deviceParam->turnOff = calcData; /* Turn Off */
+
+ calcData = ((0x78 & valueOfReg) >> 3) + ((BIT23 & valueOfReg) >> 19);
+ deviceParam->acc2First = calcData; /* Access To First */
+
+ calcData = ((0x780 & valueOfReg) >> 7) + ((BIT24 & valueOfReg) >> 20);
+ deviceParam->acc2Next = calcData; /* Access To Next */
+
+ calcData =
+ ((0x3800 & valueOfReg) >> 11) + ((BIT25 & valueOfReg) >> 22);
+ deviceParam->ale2Wr = calcData; /* Ale To Write */
+
+ calcData = ((0x1c000 & valueOfReg) >> 14) +
+ ((BIT26 & valueOfReg) >> 23);
+ deviceParam->wrLow = calcData; /* Write Active */
+
+ calcData = ((0xe0000 & valueOfReg) >> 17) +
+ ((BIT27 & valueOfReg) >> 24);
+ deviceParam->wrHigh = calcData; /* Write High */
+
+ calcData = ((0x300000 & valueOfReg) >> 20);
+ deviceParam->deviceWidth = (BIT0 << calcData); /* In bytes */
+ calcData = ((0x30000000 & valueOfReg) >> 28);
+ deviceParam->badrSkew = calcData; /* Cycles gap between BAdr
+ toggle to read data sample. */
+ calcData = ((0x40000000 & valueOfReg) >> 30);
+ deviceParam->DPEn = calcData; /* Data Parity enable */
+ return true;
+}
+
+/*******************************************************************************
+* memorySetDeviceParam - Set new parameters for a device.
+*
+*
+* DESCRIPTION:
+* To allow interfacing with very slow devices and fast synchronous SRAMs,
+* each device can be programed to different timing parameters. Each bank
+* has its own parameters register. Bank width can be programmed to 8, 16,
+* or 32-bits. Bank timing parameters can be programmed to support
+* different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
+* Controllers). The MV allows you to set timing parameters and width for
+* each device through parameters register. This function set new
+* parameters to a device Bank from the delivered structure 'deviceParam'
+* (defined in gtMemory.h). The structure must be initialized with data
+* prior to the use of these function.
+*
+* INPUT:
+* deviceParam - pointer to a structure DEVICE_PARAM (defined in
+* Memory.h).For details about each structure field please
+* see the device timing parameter section in the MV
+* datasheet.
+* deviceNum - Select on of the five device banks (defined in
+* Memory.h) :
+*
+* - DEVICE0
+* - DEVICE1
+* - DEVICE2
+* - etc.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* false if one of the parameters is erroneous,true otherwise.
+*
+*******************************************************************************/
+/********************************************************************
+* memorySetDeviceParam - This function used for setting device parameters to
+* DEVICE BANK PARAMETERS REGISTER
+*
+*
+* Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK
+* PARAMETERS REGISTER
+* - deviceNum : number of device
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool memorySetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
+{
+ unsigned int valueForReg;
+
+ if ((deviceParam->turnOff > 0x7) || (deviceParam->acc2First > 0xf) ||
+ (deviceParam->acc2Next > 0xf) || (deviceParam->ale2Wr > 0x7) ||
+ (deviceParam->wrLow > 0x7) || (deviceParam->wrHigh > 0x7) ||
+ (deviceParam->badrSkew > 0x2) || (deviceParam->DPEn > 0x1)) {
+ return false;
+ }
+ valueForReg = (((deviceParam->turnOff) & 0x7) |
+ (((deviceParam->turnOff) & 0x8) << 19) |
+ (((deviceParam->acc2First) & 0xf) << 3) |
+ (((deviceParam->acc2First) & 0x10) << 19) |
+ (((deviceParam->acc2Next) & 0xf) << 7) |
+ (((deviceParam->acc2Next) & 0x10) << 20) |
+ (((deviceParam->ale2Wr) & 0x7) << 11) |
+ (((deviceParam->ale2Wr) & 0xf) << 22) |
+ (((deviceParam->wrLow) & 0x7) << 14) |
+ (((deviceParam->wrLow) & 0xf) << 23) |
+ (((deviceParam->wrHigh) & 0x7) << 17) |
+ (((deviceParam->wrHigh) & 0xf) << 24) |
+ (((deviceParam->badrSkew) & 0x3) << 28) |
+ (((deviceParam->DPEn) & 0x1) << 30));
+
+ /* insert the device width: */
+ switch (deviceParam->deviceWidth) {
+ case 1:
+ valueForReg = valueForReg | _8BIT;
+ break;
+ case 2:
+ valueForReg = valueForReg | _16BIT;
+ break;
+ case 4:
+ valueForReg = valueForReg | _32BIT;
+ break;
+ default:
+ valueForReg = valueForReg | _8BIT;
+ break;
+ }
+ GT_REG_WRITE (DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
+ return true;
+}
+
+/*******************************************************************************
+* MemoryDisableWindow - Disable a memory space by the disable bit.
+* DESCRIPTION:
+* This function disables one of the 21 availiable windows dedicated for
+* the CPU decoding mechanism. Its possible to combine several windows with
+* the OR command.
+* INPUT:
+* window - One or more of the memory windows (defined in gtMemory.h).
+* OUTPUT:
+* None.
+* RETURN:
+* None.
+*******************************************************************************/
+void MemoryDisableWindow (MEMORY_WINDOW window)
+{
+ SET_REG_BITS (BASE_ADDR_ENABLE, window);
+}
+
+/*******************************************************************************
+* MemoryEnableWindow - Enable a memory space that was disabled by
+* 'MemoryDisableWindow'.
+* DESCRIPTION:
+* This function enables one of the 21 availiable windows dedicated for the
+* CPU decoding mechanism. Its possible to combine several windows with the
+* OR command.
+* INPUT:
+* window - One or more of the memory windows (defined in gtMemory.h).
+* OUTPUT:
+* None.
+* RETURN:
+* None.
+*******************************************************************************/
+void MemoryEnableWindow (MEMORY_WINDOW window)
+{
+ RESET_REG_BITS (BASE_ADDR_ENABLE, window);
+}
+
+/*******************************************************************************
+* MemoryGetMemWindowStatus - This function check whether the memory window is
+* disabled or not.
+* DESCRIPTION:
+* This function checks if the given memory window is closed .
+* INPUT:
+* window - One or more of the memory windows (defined in gtMemory.h).
+* OUTPUT:
+* None.
+* RETURN:
+* true for a closed window, false otherwise .
+*******************************************************************************/
+MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window)
+{
+ if (GTREGREAD (BASE_ADDR_ENABLE) & window)
+ return MEM_WINDOW_DISABLED;
+ return MEM_WINDOW_ENABLED;
+}
diff --git a/board/Marvell/common/ns16550.c b/board/Marvell/common/ns16550.c
new file mode 100644
index 0000000..7839b68
--- /dev/null
+++ b/board/Marvell/common/ns16550.c
@@ -0,0 +1,66 @@
+/*
+ * COM1 NS16550 support
+ * originally from linux source (arch/powerpc/boot/ns16550.c)
+ * modified to use CONFIG_SYS_ISA_MEM and new defines
+ *
+ * further modified by Josh Huber <huber@mclx.com> to support
+ * the DUART on the Galileo Eval board. (db64360)
+ */
+
+#include <config.h>
+#include "ns16550.h"
+
+#ifdef ZUMA_NTL
+/* no 16550 device */
+#else
+const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0),
+ (NS16550_t) (CONFIG_SYS_DUART_IO + 0x20)
+};
+
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
+{
+ volatile struct NS16550 *com_port;
+
+ com_port = (struct NS16550 *) COM_PORTS[chan];
+ com_port->ier = 0x00;
+ com_port->lcr = LCR_BKSE; /* Access baud rate */
+ com_port->dll = baud_divisor & 0xff; /* 9600 baud */
+ com_port->dlm = (baud_divisor >> 8) & 0xff;
+ com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
+ com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */
+
+ /* Clear & enable FIFOs */
+ com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
+ return (com_port);
+}
+
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
+{
+ com_port->ier = 0x00;
+ com_port->lcr = LCR_BKSE; /* Access baud rate */
+ com_port->dll = baud_divisor & 0xff; /* 9600 baud */
+ com_port->dlm = (baud_divisor >> 8) & 0xff;
+ com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
+ com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */
+
+ /* Clear & enable FIFOs */
+ com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
+}
+
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
+{
+ while ((com_port->lsr & LSR_THRE) == 0);
+ com_port->thr = c;
+}
+
+unsigned char NS16550_getc (volatile struct NS16550 *com_port)
+{
+ while ((com_port->lsr & LSR_DR) == 0);
+ return (com_port->rbr);
+}
+
+int NS16550_tstc (volatile struct NS16550 *com_port)
+{
+ return ((com_port->lsr & LSR_DR) != 0);
+}
+#endif
diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h
new file mode 100644
index 0000000..9306381
--- /dev/null
+++ b/board/Marvell/common/ns16550.h
@@ -0,0 +1,102 @@
+/*
+ * NS16550 Serial Port
+ * originally from linux source (arch/powerpc/boot/ns16550.h)
+ * modified slightly to
+ * have addresses as offsets from CONFIG_SYS_ISA_BASE
+ * added a few more definitions
+ * added prototypes for ns16550.c
+ * reduced no of com ports to 2
+ * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
+ *
+ * further modified to support the DUART in the Galileo eval board
+ * modifications (c) Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ */
+
+#ifndef __NS16550_H__
+#define __NS16550_H__
+
+/* the padding is necessary because on the galileo board the UART is
+ wired in with the 3 address lines shifted over by 2 bits */
+struct NS16550
+{
+ unsigned char rbr; /* 0 = 0-3*/
+ int pad1:24;
+
+ unsigned char ier; /* 1 = 4-7*/
+ int pad2:24;
+
+ unsigned char fcr; /* 2 = 8-b*/
+ int pad3:24;
+
+ unsigned char lcr; /* 3 = c-f*/
+ int pad4:24;
+
+ unsigned char mcr; /* 4 = 10-13*/
+ int pad5:24;
+
+ unsigned char lsr; /* 5 = 14-17*/
+ int pad6:24;
+
+ unsigned char msr; /* 6 =18-1b*/
+ int pad7:24;
+
+ unsigned char scr; /* 7 =1c-1f*/
+ int pad8:24;
+} __attribute__ ((packed));
+
+/* aliases */
+#define thr rbr
+#define iir fcr
+#define dll rbr
+#define dlm ier
+
+#define FCR_FIFO_EN 0x01 /*fifo enable*/
+#define FCR_RXSR 0x02 /*receiver soft reset*/
+#define FCR_TXSR 0x04 /*transmitter soft reset*/
+
+
+#define MCR_DTR 0x01
+#define MCR_RTS 0x02
+#define MCR_DMA_EN 0x04
+#define MCR_TX_DFR 0x08
+
+
+#define LCR_WLS_MSK 0x03 /* character length slect mask*/
+#define LCR_WLS_5 0x00 /* 5 bit character length */
+#define LCR_WLS_6 0x01 /* 6 bit character length */
+#define LCR_WLS_7 0x02 /* 7 bit character length */
+#define LCR_WLS_8 0x03 /* 8 bit character length */
+#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define LCR_PEN 0x08 /* Parity eneble*/
+#define LCR_EPS 0x10 /* Even Parity Select*/
+#define LCR_STKP 0x20 /* Stick Parity*/
+#define LCR_SBRK 0x40 /* Set Break*/
+#define LCR_BKSE 0x80 /* Bank select enable*/
+
+#define LSR_DR 0x01 /* Data ready */
+#define LSR_OE 0x02 /* Overrun */
+#define LSR_PE 0x04 /* Parity error */
+#define LSR_FE 0x08 /* Framing error */
+#define LSR_BI 0x10 /* Break */
+#define LSR_THRE 0x20 /* Xmit holding register empty */
+#define LSR_TEMT 0x40 /* Xmitter empty */
+#define LSR_ERR 0x80 /* Error */
+
+/* useful defaults for LCR*/
+#define LCR_8N1 0x03
+
+
+#define COM1 0x03F8
+#define COM2 0x02F8
+
+volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
+void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
+unsigned char NS16550_getc(volatile struct NS16550 *com_port);
+int NS16550_tstc(volatile struct NS16550 *com_port);
+void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
+
+typedef struct NS16550 *NS16550_t;
+
+extern const NS16550_t COM_PORTS[];
+
+#endif
diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c
new file mode 100644
index 0000000..432aa06
--- /dev/null
+++ b/board/Marvell/common/serial.c
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * serial.c - serial support for the gal ev board
+ */
+
+/* supports both the 16650 duart and the MPSC */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <linux/compiler.h>
+
+#include "../include/memory.h"
+
+#include "ns16550.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_MPSC
+static int marvell_serial_init(void)
+{
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
+ int clock_divisor = 230400 / gd->baudrate;
+#endif
+
+ mpsc_init (gd->baudrate);
+
+ /* init the DUART chans so that KGDB in the kernel can use them */
+#ifdef CONFIG_SYS_INIT_CHAN1
+ NS16550_reinit (COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+ NS16550_reinit (COM_PORTS[1], clock_divisor);
+#endif
+ return (0);
+}
+
+static void marvell_serial_putc(const char c)
+{
+ if (c == '\n')
+ mpsc_putchar ('\r');
+
+ mpsc_putchar (c);
+}
+
+static int marvell_serial_getc(void)
+{
+ return mpsc_getchar ();
+}
+
+static int marvell_serial_tstc(void)
+{
+ return mpsc_test_char ();
+}
+
+static void marvell_serial_setbrg(void)
+{
+ galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
+}
+
+#else /* ! CONFIG_MPSC */
+
+static int marvell_serial_init(void)
+{
+ int clock_divisor = 230400 / gd->baudrate;
+
+#ifdef CONFIG_SYS_INIT_CHAN1
+ (void) NS16550_init (0, clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+ (void) NS16550_init (1, clock_divisor);
+#endif
+ return (0);
+}
+
+static void marvell_serial_putc(const char c)
+{
+ if (c == '\n')
+ NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
+
+ NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
+}
+
+static int marvell_serial_getc(void)
+{
+ return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
+}
+
+static int marvell_serial_tstc(void)
+{
+ return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
+}
+
+static void marvell_serial_setbrg(void)
+{
+ int clock_divisor = 230400 / gd->baudrate;
+
+#ifdef CONFIG_SYS_INIT_CHAN1
+ NS16550_reinit (COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+ NS16550_reinit (COM_PORTS[1], clock_divisor);
+#endif
+}
+
+#endif /* CONFIG_MPSC */
+
+static struct serial_device marvell_serial_drv = {
+ .name = "marvell_serial",
+ .start = marvell_serial_init,
+ .stop = NULL,
+ .setbrg = marvell_serial_setbrg,
+ .putc = marvell_serial_putc,
+ .puts = default_serial_puts,
+ .getc = marvell_serial_getc,
+ .tstc = marvell_serial_tstc,
+};
+
+void marvell_serial_initialize(void)
+{
+ serial_register(&marvell_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &marvell_serial_drv;
+}
+
+#if defined(CONFIG_CMD_KGDB)
+void kgdb_serial_init (void)
+{
+}
+
+void putDebugChar (int c)
+{
+ serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+ serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+ return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+ return;
+}
+#endif
diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig
new file mode 100644
index 0000000..98aa10a
--- /dev/null
+++ b/board/Marvell/db-mv784mp-gp/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_DB_MV784MP_GP
+
+config SYS_BOARD
+ default "db-mv784mp-gp"
+
+config SYS_VENDOR
+ default "Marvell"
+
+config SYS_SOC
+ default "armada-xp"
+
+config SYS_CONFIG_NAME
+ default "db-mv784mp-gp"
+
+endif
diff --git a/board/Marvell/db-mv784mp-gp/MAINTAINERS b/board/Marvell/db-mv784mp-gp/MAINTAINERS
new file mode 100644
index 0000000..a095f89
--- /dev/null
+++ b/board/Marvell/db-mv784mp-gp/MAINTAINERS
@@ -0,0 +1,6 @@
+DB_MV784MP_GP BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/Marvell/db-mv784mp-gp/
+F: include/configs/db-mv784mp-gp.h
+F: configs/db-mv784mp-gp_defconfig
diff --git a/board/Marvell/db-mv784mp-gp/Makefile b/board/Marvell/db-mv784mp-gp/Makefile
new file mode 100644
index 0000000..8f5a7fb
--- /dev/null
+++ b/board/Marvell/db-mv784mp-gp/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := db-mv784mp-gp.o
diff --git a/board/Marvell/db-mv784mp-gp/binary.0 b/board/Marvell/db-mv784mp-gp/binary.0
new file mode 100644
index 0000000..17bfad9
--- /dev/null
+++ b/board/Marvell/db-mv784mp-gp/binary.0
@@ -0,0 +1,17 @@
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
+
+In a few weeks, mainline U-Boot will get support to generate the
+bin_hdr with the DDR training code itself. By implementing this code
+as SPL U-Boot. Then this file will not be needed any more and will
+get removed.
+
diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
new file mode 100644
index 0000000..b3dae89
--- /dev/null
+++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BIT(nr) (1UL << (nr))
+
+#define ETH_PHY_CTRL_REG 0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
+ * "RD-AXP-GP rev 1.0".
+ *
+ * GPPs
+ * MPP# NAME IN/OUT
+ * ----------------------------------------------
+ * 21 SW_Reset_ OUT
+ * 25 Phy_Int# IN
+ * 28 SDI_WP IN
+ * 29 SDI_Status IN
+ * 54-61 On GPP Connector ?
+ * 62 Switch Interrupt IN
+ * 63-65 Reserved from SW Board ?
+ * 66 SW_BRD connected IN
+ */
+#define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20)))
+#define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27)))
+#define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0))
+
+#define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20))
+#define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
+#define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0
+
+int board_early_init_f(void)
+{
+ /* Configure MPP */
+ writel(0x00000000, MVEBU_MPP_BASE + 0x00);
+ writel(0x00000000, MVEBU_MPP_BASE + 0x04);
+ writel(0x33000000, MVEBU_MPP_BASE + 0x08);
+ writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
+ writel(0x11111111, MVEBU_MPP_BASE + 0x10);
+ writel(0x00221100, MVEBU_MPP_BASE + 0x14);
+ writel(0x00000003, MVEBU_MPP_BASE + 0x18);
+ writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
+ writel(0x00000000, MVEBU_MPP_BASE + 0x20);
+
+ /* Configure GPIO */
+ writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+ writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+ writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
+ writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Marvell DB-MV784MP-GP\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1545 PHY */
+void reset_phy(void)
+{
+ u16 devadr = CONFIG_PHY_BASE_ADDR;
+ char *name = "neta0";
+ u16 reg;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* Enable QSGMII AN */
+ /* Set page to 4 */
+ miiphy_write(name, devadr, 0x16, 4);
+ /* Enable AN */
+ miiphy_write(name, devadr, 0x0, 0x1140);
+ /* Set page to 0 */
+ miiphy_write(name, devadr, 0x16, 0);
+
+ /* Phy C_ANEG */
+ miiphy_read(name, devadr, 0x4, ®);
+ reg |= 0x1E0;
+ miiphy_write(name, devadr, 0x4, reg);
+
+ /* Soft-Reset */
+ miiphy_write(name, devadr, 22, 0x0000);
+ miiphy_write(name, devadr, 0, 0x9140);
+
+ /* Power up the phy */
+ miiphy_read(name, devadr, ETH_PHY_CTRL_REG, ®);
+ reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
+ miiphy_write(name, devadr, ETH_PHY_CTRL_REG, reg);
+
+ printf("88E1545 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/db-mv784mp-gp/kwbimage.cfg b/board/Marvell/db-mv784mp-gp/kwbimage.cfg
new file mode 100644
index 0000000..d7ef407
--- /dev/null
+++ b/board/Marvell/db-mv784mp-gp/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/Marvell/db-mv784mp-gp/binary.0 0000005b 00000068
diff --git a/board/Marvell/dkb/Kconfig b/board/Marvell/dkb/Kconfig
new file mode 100644
index 0000000..f674894
--- /dev/null
+++ b/board/Marvell/dkb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_DKB
+
+config SYS_BOARD
+ default "dkb"
+
+config SYS_VENDOR
+ default "Marvell"
+
+config SYS_SOC
+ default "pantheon"
+
+config SYS_CONFIG_NAME
+ default "dkb"
+
+endif
diff --git a/board/Marvell/dkb/MAINTAINERS b/board/Marvell/dkb/MAINTAINERS
new file mode 100644
index 0000000..c272b7a
--- /dev/null
+++ b/board/Marvell/dkb/MAINTAINERS
@@ -0,0 +1,6 @@
+DKB BOARD
+M: Lei Wen <leiwen@marvell.com>
+S: Maintained
+F: board/Marvell/dkb/
+F: include/configs/dkb.h
+F: configs/dkb_defconfig
diff --git a/board/Marvell/dkb/Makefile b/board/Marvell/dkb/Makefile
new file mode 100644
index 0000000..9d88579
--- /dev/null
+++ b/board/Marvell/dkb/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2011
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Lei Wen <leiwen@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dkb.o
diff --git a/board/Marvell/dkb/dkb.c b/board/Marvell/dkb/dkb.c
new file mode 100644
index 0000000..c0c3125
--- /dev/null
+++ b/board/Marvell/dkb/dkb.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <i2c.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/cpu.h>
+#ifdef CONFIG_GENERIC_MMC
+#include <sdhci.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ u32 mfp_cfg[] = {
+ /* Enable Console on UART2 */
+ MFP47_UART2_RXD,
+ MFP48_UART2_TXD,
+
+ /* I2C */
+ MFP53_CI2C_SCL,
+ MFP54_CI2C_SDA,
+
+ /* MMC1 */
+ MFP_MMC1_DAT7,
+ MFP_MMC1_DAT6,
+ MFP_MMC1_DAT5,
+ MFP_MMC1_DAT4,
+ MFP_MMC1_DAT3,
+ MFP_MMC1_DAT2,
+ MFP_MMC1_DAT1,
+ MFP_MMC1_DAT0,
+ MFP_MMC1_CMD,
+ MFP_MMC1_CLK,
+ MFP_MMC1_CD,
+ MFP_MMC1_WP,
+
+ MFP_EOC /*End of configureation*/
+ };
+ /* configure MFP's */
+ mfp_config(mfp_cfg);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of Board */
+ gd->bd->bi_arch_number = MACH_TYPE_TTC_DKB;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = panth_sdram_base(0) + 0x100;
+ return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+#define I2C_SLAVE_ADDR 0x34
+#define LDO13_REG 0x28
+#define LDO_V30 0x6
+#define LDO_VOLTAGE(x) ((x & 0x7) << 1)
+#define LDO_EN 0x1
+int board_mmc_init(bd_t *bd)
+{
+ ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
+ u8 i, data;
+
+ /* set LDO 13 to 3.0v */
+ data = LDO_VOLTAGE(LDO_V30) | LDO_EN;
+ i2c_write(I2C_SLAVE_ADDR, LDO13_REG, 1, &data, 1);
+
+ for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
+ if (mv_sdh_init(mmc_base_address[i], 0, 0,
+ SDHCI_QUIRK_32BIT_DMA_ADDR))
+ return 1;
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/Marvell/dreamplug/Kconfig b/board/Marvell/dreamplug/Kconfig
new file mode 100644
index 0000000..f65ff73
--- /dev/null
+++ b/board/Marvell/dreamplug/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DREAMPLUG
+
+config SYS_BOARD
+ default "dreamplug"
+
+config SYS_VENDOR
+ default "Marvell"
+
+config SYS_CONFIG_NAME
+ default "dreamplug"
+
+endif
diff --git a/board/Marvell/dreamplug/MAINTAINERS b/board/Marvell/dreamplug/MAINTAINERS
new file mode 100644
index 0000000..2561ba8
--- /dev/null
+++ b/board/Marvell/dreamplug/MAINTAINERS
@@ -0,0 +1,6 @@
+DREAMPLUG BOARD
+M: Jason Cooper <u-boot@lakedaemon.net>
+S: Maintained
+F: board/Marvell/dreamplug/
+F: include/configs/dreamplug.h
+F: configs/dreamplug_defconfig
diff --git a/board/Marvell/dreamplug/Makefile b/board/Marvell/dreamplug/Makefile
new file mode 100644
index 0000000..23e6c53
--- /dev/null
+++ b/board/Marvell/dreamplug/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2011
+# Jason Cooper <u-boot@lakedaemon.net>
+#
+# Based on work by:
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dreamplug.o
diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c
new file mode 100644
index 0000000..0887d92
--- /dev/null
+++ b/board/Marvell/dreamplug/dreamplug.c
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "dreamplug.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
+ DREAMPLUG_OE_VAL_HIGH,
+ DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_SPI_SCn, /* SPI Flash */
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD, /* Serial */
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK, /* SDIO Slot */
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0, /* Gigabit Ethernet */
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GE1_8,
+ MPP29_GE1_9,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GE1_14,
+ MPP35_GE1_15,
+ MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_TDM_SPI_SCK,
+ MPP41_TDM_SPI_MISO,
+ MPP42_TDM_SPI_MOSI,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO, /* Bluetooth LED */
+ MPP48_GPIO, /* Wifi LED */
+ MPP49_GPIO, /* Wifi AP LED */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void mv_phy_88e1116_init(char *name)
+{
+ u16 reg;
+ u16 devadr;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __func__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+ /* configure and initialize both PHY's */
+ mv_phy_88e1116_init("egiga0");
+ mv_phy_88e1116_init("egiga1");
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/dreamplug/dreamplug.h b/board/Marvell/dreamplug/dreamplug.h
new file mode 100644
index 0000000..18ea41c
--- /dev/null
+++ b/board/Marvell/dreamplug/dreamplug.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DREAMPLUG_H
+#define __DREAMPLUG_H
+
+#define DREAMPLUG_OE_LOW (~(0))
+#define DREAMPLUG_OE_HIGH (~(0))
+#define DREAMPLUG_OE_VAL_LOW 0
+#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
+
+/* PHY related */
+#define MV88E1116_MAC_CTRL2_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __DREAMPLUG_H */
diff --git a/board/Marvell/dreamplug/kwbimage.cfg b/board/Marvell/dreamplug/kwbimage.cfg
new file mode 100644
index 0000000..19d77e3
--- /dev/null
+++ b/board/Marvell/dreamplug/kwbimage.cfg
@@ -0,0 +1,147 @@
+#
+# (C) Copyright 2011
+# Jason Cooper <u-boot@lakedaemon.net>
+#
+# Based on work by:
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b9b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc # DDR Address Control
+# bit1-0: 01, Cs0width=x8
+# bit3-2: 10, Cs0size=1Gb
+# bit5-4: 01, Cs1width=x8
+# bit7-6: 10, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/Marvell/gplugd/Kconfig b/board/Marvell/gplugd/Kconfig
new file mode 100644
index 0000000..d944816
--- /dev/null
+++ b/board/Marvell/gplugd/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_GPLUGD
+
+config SYS_BOARD
+ default "gplugd"
+
+config SYS_VENDOR
+ default "Marvell"
+
+config SYS_SOC
+ default "armada100"
+
+config SYS_CONFIG_NAME
+ default "gplugd"
+
+endif
diff --git a/board/Marvell/gplugd/MAINTAINERS b/board/Marvell/gplugd/MAINTAINERS
new file mode 100644
index 0000000..320bc09
--- /dev/null
+++ b/board/Marvell/gplugd/MAINTAINERS
@@ -0,0 +1,6 @@
+GPLUGD BOARD
+M: Ajay Bhargav <ajay.bhargav@einfochips.com>
+S: Maintained
+F: board/Marvell/gplugd/
+F: include/configs/gplugd.h
+F: configs/gplugd_defconfig
diff --git a/board/Marvell/gplugd/Makefile b/board/Marvell/gplugd/Makefile
new file mode 100644
index 0000000..b384578
--- /dev/null
+++ b/board/Marvell/gplugd/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2011
+# eInfochips Ltd. <www.einfochips.com>
+# Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+#
+# Based on Aspenite:
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Contributor: Mahavir Jain <mjain@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := gplugd.o
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
new file mode 100644
index 0000000..0e8ebcc
--- /dev/null
+++ b/board/Marvell/gplugd/gplugd.c
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * Based on Aspenite:
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/armada100.h>
+#include <asm/gpio.h>
+#include <miiphy.h>
+
+#ifdef CONFIG_ARMADA100_FEC
+#include <net.h>
+#include <netdev.h>
+#endif /* CONFIG_ARMADA100_FEC */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ u32 mfp_cfg[] = {
+ /* I2C */
+ MFP105_CI2C_SDA,
+ MFP106_CI2C_SCL,
+
+ /* Enable Console on UART3 */
+ MFPO8_UART3_TXD,
+ MFPO9_UART3_RXD,
+
+ /* Ethernet PHY Interface */
+ MFP086_ETH_TXCLK,
+ MFP087_ETH_TXEN,
+ MFP088_ETH_TXDQ3,
+ MFP089_ETH_TXDQ2,
+ MFP090_ETH_TXDQ1,
+ MFP091_ETH_TXDQ0,
+ MFP092_ETH_CRS,
+ MFP093_ETH_COL,
+ MFP094_ETH_RXCLK,
+ MFP095_ETH_RXER,
+ MFP096_ETH_RXDQ3,
+ MFP097_ETH_RXDQ2,
+ MFP098_ETH_RXDQ1,
+ MFP099_ETH_RXDQ0,
+ MFP100_ETH_MDC,
+ MFP101_ETH_MDIO,
+ MFP103_ETH_RXDV,
+
+ /* SSP2 */
+ MFP107_SSP2_RXD,
+ MFP108_SSP2_TXD,
+ MFP110_SSP2_CS,
+ MFP111_SSP2_CLK,
+
+ MFP_EOC /*End of configuration*/
+ };
+ /* configure MFP's */
+ mfp_config(mfp_cfg);
+ return 0;
+}
+
+int board_init(void)
+{
+ struct armd1apb2_registers *apb2_regs =
+ (struct armd1apb2_registers *)ARMD1_APBC2_BASE;
+
+ /* arch number of Board */
+ gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+ /* Assert PHY_RST# */
+ gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
+ udelay(10);
+ /* Deassert PHY_RST# */
+ gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
+
+ /* Enable SSP2 clock */
+ writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
+ return 0;
+}
+
+#ifdef CONFIG_ARMADA100_FEC
+int board_eth_init(bd_t *bis)
+{
+ struct armd1apmu_registers *apmu_regs =
+ (struct armd1apmu_registers *)ARMD1_APMU_BASE;
+
+ /* Enable clock of ethernet controller */
+ writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc);
+
+ return armada100_fec_register(ARMD1_FEC_BASE);
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY chip 88E3015 */
+void reset_phy(void)
+{
+ u16 phy_adr;
+ const char *name = "armd-fec0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xff, 0xff, &phy_adr)) {
+ printf("Err..%s could not read PHY dev address\n", __func__);
+ return;
+ }
+
+ /* Set Ethernet LED in TX blink mode */
+ miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
+ miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
+
+ /* reset the phy */
+ miiphy_reset(name, phy_adr);
+ debug("88E3015 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+#endif /* CONFIG_ARMADA100_FEC */
diff --git a/board/Marvell/guruplug/Kconfig b/board/Marvell/guruplug/Kconfig
new file mode 100644
index 0000000..529e6e3
--- /dev/null
+++ b/board/Marvell/guruplug/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GURUPLUG
+
+config SYS_BOARD
+ default "guruplug"
+
+config SYS_VENDOR
+ default "Marvell"
+
+config SYS_CONFIG_NAME
+ default "guruplug"
+
+endif
diff --git a/board/Marvell/guruplug/MAINTAINERS b/board/Marvell/guruplug/MAINTAINERS
new file mode 100644
index 0000000..b5d0734
--- /dev/null
+++ b/board/Marvell/guruplug/MAINTAINERS
@@ -0,0 +1,6 @@
+GURUPLUG BOARD
+M: Siddarth Gore <gores@marvell.com>
+S: Maintained
+F: board/Marvell/guruplug/
+F: include/configs/guruplug.h
+F: configs/guruplug_defconfig
diff --git a/board/Marvell/guruplug/Makefile b/board/Marvell/guruplug/Makefile
new file mode 100644
index 0000000..974497a
--- /dev/null
+++ b/board/Marvell/guruplug/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := guruplug.o
diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c
new file mode 100644
index 0000000..b0d5f1e
--- /dev/null
+++ b/board/Marvell/guruplug/guruplug.c
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "guruplug.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
+ GURUPLUG_OE_VAL_HIGH,
+ GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO, /* GPIO_RST */
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GE1_8,
+ MPP29_GE1_9,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GE1_14,
+ MPP35_GE1_15,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_TDM_SPI_SCK,
+ MPP41_TDM_SPI_MISO,
+ MPP42_TDM_SPI_MOSI,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO, /* M_RLED */
+ MPP47_GPIO, /* M_GLED */
+ MPP48_GPIO, /* B_RLED */
+ MPP49_GPIO, /* B_GLED */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void mv_phy_88e1121_init(char *name)
+{
+ u16 reg;
+ u16 devadr;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, ®);
+ reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
+ miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1121 Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+ /* configure and initialize both PHY's */
+ mv_phy_88e1121_init("egiga0");
+ mv_phy_88e1121_init("egiga1");
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/guruplug/guruplug.h b/board/Marvell/guruplug/guruplug.h
new file mode 100644
index 0000000..688d950
--- /dev/null
+++ b/board/Marvell/guruplug/guruplug.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __GURUPLUG_H
+#define __GURUPLUG_H
+
+#define GURUPLUG_OE_LOW (~(0))
+#define GURUPLUG_OE_HIGH (~(0))
+#define GURUPLUG_OE_VAL_LOW 0
+#define GURUPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
+
+/* PHY related */
+#define MV88E1121_MAC_CTRL2_REG 21
+#define MV88E1121_PGADR_REG 22
+#define MV88E1121_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1121_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __GURUPLUG_H */
diff --git a/board/Marvell/guruplug/kwbimage.cfg b/board/Marvell/guruplug/kwbimage.cfg
new file mode 100644
index 0000000..865942a
--- /dev/null
+++ b/board/Marvell/guruplug/kwbimage.cfg
@@ -0,0 +1,146 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b9b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc # DDR Address Control
+# bit1-0: 01, Cs0width=x8
+# bit3-2: 10, Cs0size=1Gb
+# bit5-4: 01, Cs1width=x8
+# bit7-6: 10, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/Marvell/include/memory.h b/board/Marvell/include/memory.h
new file mode 100644
index 0000000..0947b6e
--- /dev/null
+++ b/board/Marvell/include/memory.h
@@ -0,0 +1,173 @@
+/* Memory.h - Memory mappings and remapping functions declarations */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCmemoryh
+#define __INCmemoryh
+
+/* includes */
+
+#include "core.h"
+
+/* defines */
+
+#define DONT_MODIFY 0xffffffff
+#define PARITY_SUPPORT 0x40000000
+#define MINIMUM_MEM_BANK_SIZE 0x10000
+#define MINIMUM_DEVICE_WINDOW_SIZE 0x10000
+#define MINIMUM_PCI_WINDOW_SIZE 0x10000
+#define MINIMUM_ACCESS_WIN_SIZE 0x10000
+
+#define _8BIT 0x00000000
+#define _16BIT 0x00100000
+#define _32BIT 0x00200000
+#define _64BIT 0x00300000
+
+/* typedefs */
+
+ typedef struct deviceParam
+{ /* boundary values */
+ unsigned int turnOff; /* 0x0 - 0xf */
+ unsigned int acc2First; /* 0x0 - 0x1f */
+ unsigned int acc2Next; /* 0x0 - 0x1f */
+ unsigned int ale2Wr; /* 0x0 - 0xf */
+ unsigned int wrLow; /* 0x0 - 0xf */
+ unsigned int wrHigh; /* 0x0 - 0xf */
+ unsigned int badrSkew; /* 0x0 - 0x2 */
+ unsigned int DPEn; /* 0x0 - 0x1 */
+ unsigned int deviceWidth; /* in Bytes */
+} DEVICE_PARAM;
+
+
+typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
+typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
+
+/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \
+ MEM_REGION3,MEM_REGION4,MEM_REGION5, \
+ MEM_REGION6,MEM_REGION7} \
+ MEMORY_PROTECT_REGION;*/
+/* There are four possible windows that can be defined as protected */
+typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2,
+ MEM_WINDOW3
+ } MEMORY_PROTECT_WINDOW;
+/* When defining a protected window , this paramter indicates whether it
+ is accessible or not */
+typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \
+ MEMORY_ACCESS;
+typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \
+ MEMORY_ACCESS_WRITE;
+typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \
+ MEMORY_CACHE_PROTECT;
+typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \
+ MEMORY_SNOOP_TYPE;
+typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \
+ MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \
+ MEMORY_SNOOP_REGION;
+
+/* There are 21 memory windows dedicated for the varios interfaces (PCI,
+ devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's
+ address decoding mechanism. */
+typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1,
+ CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3,
+ DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5,
+ DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7,
+ BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9,
+ PCI_0_MEM0_WINDOW = BIT10,
+ PCI_0_MEM1_WINDOW = BIT11,
+ PCI_0_MEM2_WINDOW = BIT12,
+ PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14,
+ PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16,
+ PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18,
+ INTEGRATED_SRAM_WINDOW = BIT19,
+ INTERNAL_SPACE_WINDOW = BIT20,
+ ALL_WINDOWS = 0X1FFFFF
+ } MEMORY_WINDOW;
+
+typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED
+ } MEMORY_WINDOW_STATUS;
+
+
+typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3
+#ifdef INCLUDE_PCI_1
+ ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3
+#endif /* INCLUDE_PCI_1 */
+ } PCI_MEM_WINDOW;
+
+
+/* -------------------------------------------------------------------------------------------------*/
+
+/* functions */
+unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
+unsigned int memoryGetDeviceBaseAddress(DEVICE device);
+/* New at MV6436x */
+unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow);
+unsigned int memoryGetBankSize(MEMORY_BANK bank);
+unsigned int memoryGetDeviceSize(DEVICE device);
+unsigned int memoryGetDeviceWidth(DEVICE device);
+/* New at MV6436x */
+unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow);
+
+/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
+bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
+/* Set a new base and size for one of the memory banks (CS0 - CS3) */
+bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase,
+ unsigned int bankSize);
+bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
+
+/* Change the Internal Register Base Address to a new given Address. */
+bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
+/* returns internal Register Space Base Address. */
+unsigned int memoryGetInternalRegistersSpace(void);
+
+/* Returns the integrated SRAM Base Address. */
+unsigned int memoryGetInternalSramBaseAddr(void);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Set new base address for the integrated SRAM. */
+void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Delete a protection feature to a given space. */
+void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Writes a new remap value to the remap register */
+unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow,
+ unsigned int remapValueHigh,
+ unsigned int remapValueLow);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Configurate the protection feature to a given space. */
+bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window,
+ MEMORY_ACCESS gtMemoryAccess,
+ MEMORY_ACCESS_WRITE gtMemoryWrite,
+ MEMORY_CACHE_PROTECT cacheProtection,
+ unsigned int baseAddress,
+ unsigned int size);
+
+/* Configurate the protection feature to a given space. */
+/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
+ MEMORY_ACCESS memoryAccess,
+ MEMORY_ACCESS_WRITE memoryWrite,
+ MEMORY_CACHE_PROTECT cacheProtection,
+ unsigned int baseAddress,
+ unsigned int regionLength); */
+/* Configurate the snoop feature to a given space. */
+bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
+ MEMORY_SNOOP_TYPE snoopType,
+ unsigned int baseAddress,
+ unsigned int regionLength);
+
+bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
+bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+/* Set a new base and size for one of the PCI windows. */
+bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
+ unsigned int pciWindowSize);
+
+/* Disable or enable one of the 21 windows dedicated for the CPU's
+ address decoding mechanism */
+void MemoryDisableWindow(MEMORY_WINDOW window);
+void MemoryEnableWindow (MEMORY_WINDOW window);
+MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window);
+#endif /* __INCmemoryh */
diff --git a/board/Marvell/include/pci.h b/board/Marvell/include/pci.h
new file mode 100644
index 0000000..572e0d3
--- /dev/null
+++ b/board/Marvell/include/pci.h
@@ -0,0 +1,293 @@
+/* PCI.h - PCI functions header file */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCpcih
+#define __INCpcih
+
+/* includes */
+
+#include "core.h"
+#include "memory.h"
+
+/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
+#define PCI_MAX_DEVICES 22
+
+
+/* Macros */
+
+/* The next Macros configurate the initiator board (SELF) or any any agent on
+ the PCI to become: MASTER, response to MEMORY transactions , response to
+ IO transactions or TWO both MEMORY_IO transactions. Those configuration
+ are for both PCI0 and PCI1. */
+
+#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
+ PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \
+ pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
+ PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \
+ pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \
+ PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \
+ pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host, \
+ PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \
+ pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber))
+
+#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host, \
+ PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \
+ pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host, \
+ PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \
+ pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define MASTER_ENABLE BIT2
+#define MEMORY_ENABLE BIT1
+#define I_O_ENABLE BIT0
+#define SELF 32
+
+/* Agent on the PCI bus may have up to 6 BARS. */
+#define BAR0 0x10
+#define BAR1 0x14
+#define BAR2 0x18
+#define BAR3 0x1c
+#define BAR4 0x20
+#define BAR5 0x24
+#define BAR_SEL_MEM_IO BIT0
+#define BAR_MEM_TYPE_32_BIT NO_BIT
+#define BAR_MEM_TYPE_BELOW_1M BIT1
+#define BAR_MEM_TYPE_64_BIT BIT2
+#define BAR_MEM_TYPE_RESERVED (BIT1 | BIT2)
+#define BAR_MEM_TYPE_MASK (BIT1 | BIT2)
+#define BAR_PREFETCHABLE BIT3
+#define BAR_CONFIG_MASK (BIT0 | BIT1 | BIT2 | BIT3)
+
+/* Defines for the access regions. */
+#define PREFETCH_ENABLE BIT12
+#define PREFETCH_DISABLE NO_BIT
+#define DELAYED_READ_ENABLE BIT13
+/* #define CACHING_ENABLE BIT14 */
+/* aggressive prefetch: PCI slave prefetch two burst in advance*/
+#define AGGRESSIVE_PREFETCH BIT16
+/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
+#define READ_LINE_AGGRESSIVE_PREFETCH BIT17
+/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
+#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18
+#define MAX_BURST_4 NO_BIT
+#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */
+#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */
+#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */
+#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */
+#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */
+#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */
+#define PCI_ACCESS_PROTECT BIT28
+#define PCI_WRITE_PROTECT BIT29
+
+/* typedefs */
+
+typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
+ REGION6,REGION7} PCI_ACCESS_REGIONS;
+
+typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
+typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
+
+typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
+ PCI_SNOOP_TYPE;
+typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
+ PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
+ PCI_SNOOP_REGION;
+
+typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
+typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
+ PCI_REGION2,PCI_REGION3,
+ PCI_IO}
+ PCI_REGION;
+
+/*ronen 7/Dec/03 */
+typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
+ PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
+ PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
+ PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR,
+ PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR,
+ PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR,
+ PCI_LAST_BAR} PCI_INTERNAL_BAR;
+
+typedef struct pciBar {
+ unsigned int detectBase;
+ unsigned int base;
+ unsigned int size;
+ unsigned int type;
+} PCI_BAR;
+
+typedef struct pciDevice {
+ PCI_HOST host;
+ char type[40];
+ unsigned int deviceNum;
+ unsigned int venID;
+ unsigned int deviceID;
+ PCI_BAR bar[6];
+} PCI_DEVICE;
+
+typedef struct pciSelfBars {
+ unsigned int SCS0Base;
+ unsigned int SCS0Size;
+ unsigned int SCS1Base;
+ unsigned int SCS1Size;
+ unsigned int SCS2Base;
+ unsigned int SCS2Size;
+ unsigned int SCS3Base;
+ unsigned int SCS3Size;
+ unsigned int internalMemBase;
+ unsigned int internalIOBase;
+ unsigned int CS0Base;
+ unsigned int CS0Size;
+ unsigned int CS1Base;
+ unsigned int CS1Size;
+ unsigned int CS2Base;
+ unsigned int CS2Size;
+ unsigned int CS3Base;
+ unsigned int CS3Size;
+ unsigned int CSBootBase;
+ unsigned int CSBootSize;
+ unsigned int P2PMem0Base;
+ unsigned int P2PMem0Size;
+ unsigned int P2PMem1Base;
+ unsigned int P2PMem1Size;
+ unsigned int P2PIOBase;
+ unsigned int P2PIOSize;
+ unsigned int CPUBase;
+ unsigned int CPUSize;
+} PCI_SELF_BARS;
+
+/* read/write configuration registers on local PCI bus. */
+void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
+ unsigned int pciDevNum, unsigned int data);
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+ unsigned int pciDevNum);
+
+/* read/write configuration registers on another PCI bus. */
+void pciOverBridgeWriteConfigReg(PCI_HOST host,
+ unsigned int regOffset,
+ unsigned int pciDevNum,
+ unsigned int busNum,unsigned int data);
+unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
+ unsigned int regOffset,
+ unsigned int pciDevNum,
+ unsigned int busNum);
+
+/* Performs full scane on both PCI and returns all detail possible on the
+ agents which exist on the bus. */
+void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect,
+ unsigned int numberOfElment);
+
+/* Master`s memory space */
+bool pciMapSpace(PCI_HOST host, PCI_REGION region,
+ unsigned int remapBase,
+ unsigned int deviceBase,
+ unsigned int deviceLength);
+unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
+unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
+
+/* Slave`s memory space */
+void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
+ unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
+
+#if 0 /* GARBAGE routines - dont use till they get cleaned up */
+void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
+void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
+void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
+void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
+void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
+void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
+void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
+ unsigned int pci0Dev0Length);
+void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
+ unsigned int pci1Dev0Length);
+void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
+ unsigned int pci0Dev1Length);
+void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
+ unsigned int pci1Dev1Length);
+void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
+ unsigned int pci0Dev2Length);
+void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
+ unsigned int pci1Dev2Length);
+void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
+ unsigned int pci0Dev3Length);
+void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
+ unsigned int pci1Dev3Length);
+void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
+ unsigned int pci0DevBootLength);
+void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
+ unsigned int pci1DevBootLength);
+void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base,
+ unsigned int pci0P2pMem0Length);
+void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base,
+ unsigned int pci1P2pMem0Length);
+void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base,
+ unsigned int pci0P2pMem1Length);
+void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base,
+ unsigned int pci1P2pMem1Length);
+void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase,
+ unsigned int pci0P2pIoLength);
+void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase,
+ unsigned int pci1P2pIoLength);
+
+void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
+void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);
+#endif
+
+/* PCI region options */
+
+bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
+ unsigned int features, unsigned int baseAddress,
+ unsigned int regionLength);
+
+void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
+
+/* PCI arbiter */
+
+bool pciArbiterEnable(PCI_HOST host);
+bool pciArbiterDisable(PCI_HOST host);
+bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+ PCI_AGENT_PRIO externalAgent0,
+ PCI_AGENT_PRIO externalAgent1,
+ PCI_AGENT_PRIO externalAgent2,
+ PCI_AGENT_PRIO externalAgent3,
+ PCI_AGENT_PRIO externalAgent4,
+ PCI_AGENT_PRIO externalAgent5);
+bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+ PCI_AGENT_PRIO externalAgent0,
+ PCI_AGENT_PRIO externalAgent1,
+ PCI_AGENT_PRIO externalAgent2,
+ PCI_AGENT_PRIO externalAgent3,
+ PCI_AGENT_PRIO externalAgent4,
+ PCI_AGENT_PRIO externalAgent5);
+bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
+ PCI_AGENT_PARK externalAgent0,
+ PCI_AGENT_PARK externalAgent1,
+ PCI_AGENT_PARK externalAgent2,
+ PCI_AGENT_PARK externalAgent3,
+ PCI_AGENT_PARK externalAgent4,
+ PCI_AGENT_PARK externalAgent5);
+bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
+bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
+
+/* PCI-to-PCI (P2P) */
+
+bool pciP2PConfig(PCI_HOST host,
+ unsigned int SecondBusLow,unsigned int SecondBusHigh,
+ unsigned int busNum,unsigned int devNum);
+/* PCI Cache-coherency */
+
+bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
+ PCI_SNOOP_TYPE snoopType,
+ unsigned int baseAddress,
+ unsigned int regionLength);
+
+PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
+
+#endif /* __INCpcih */
diff --git a/board/Marvell/mv88f6281gtw_ge/Kconfig b/board/Marvell/mv88f6281gtw_ge/Kconfig
new file mode 100644
index 0000000..00d7d1c
--- /dev/null
+++ b/board/Marvell/mv88f6281gtw_ge/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MV88F6281GTW_GE
+
+config SYS_BOARD
+ default "mv88f6281gtw_ge"
+
+config SYS_VENDOR
+ default "Marvell"
+
+config SYS_CONFIG_NAME
+ default "mv88f6281gtw_ge"
+
+endif
diff --git a/board/Marvell/mv88f6281gtw_ge/MAINTAINERS b/board/Marvell/mv88f6281gtw_ge/MAINTAINERS
new file mode 100644
index 0000000..9c26ca7
--- /dev/null
+++ b/board/Marvell/mv88f6281gtw_ge/MAINTAINERS
@@ -0,0 +1,6 @@
+MV88F6281GTW_GE BOARD
+M: Prafulla Wadaskar <prafulla@marvell.com>
+S: Maintained
+F: board/Marvell/mv88f6281gtw_ge/
+F: include/configs/mv88f6281gtw_ge.h
+F: configs/mv88f6281gtw_ge_defconfig
diff --git a/board/Marvell/mv88f6281gtw_ge/Makefile b/board/Marvell/mv88f6281gtw_ge/Makefile
new file mode 100644
index 0000000..e83bbf7
--- /dev/null
+++ b/board/Marvell/mv88f6281gtw_ge/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mv88f6281gtw_ge.o
diff --git a/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg b/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
new file mode 100644
index 0000000..9fa87ac
--- /dev/null
+++ b/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
@@ -0,0 +1,149 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000a00 # DDR Configuration register
+# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2202433D # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x0000002A # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000D # DDR Address Control
+# bit1-0: 01, Cs0width=x16
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs2width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000046 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 1, DDR drive strenght reduced
+# bit2: 1, DDR ODT control lsd enabled
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, enabled
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 1 , D2P Latency enabled
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
+# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E811 # CPU ODT Control
+# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
new file mode 100644
index 0000000..ef08ad8
--- /dev/null
+++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
@@ -0,0 +1,119 @@
+/*
+ * Maintainer : Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "mv88f6281gtw_ge.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(MV88F6281GTW_GE_OE_VAL_LOW,
+ MV88F6281GTW_GE_OE_VAL_HIGH,
+ MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_SPI_SCn,
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_GPIO,
+ MPP5_GPO,
+ MPP6_SYSRST_OUTn,
+ MPP7_SPI_SCn,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO,
+ MPP13_GPIO,
+ MPP14_GPIO,
+ MPP15_GPIO,
+ MPP16_GPIO,
+ MPP17_GPIO,
+ MPP18_GPO,
+ MPP19_GPO,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_MV88F6281GTW_GE;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+void reset_phy(void)
+{
+ /* configure and initialize switch */
+ struct mv88e61xx_config swcfg = {
+ .name = "egiga0",
+ .vlancfg = MV88E61XX_VLANCFG_ROUTER,
+ .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
+ .led_init = MV88E61XX_LED_INIT_EN,
+ .mdip = MV88E61XX_MDIP_REVERSE,
+ .portstate = MV88E61XX_PORTSTT_FORWARDING,
+ .cpuport = (1 << 5),
+ .ports_enabled = 0x3f
+ };
+
+ mv88e61xx_switch_initialize(&swcfg);
+}
+#endif /* CONFIG_MV88E61XX_SWITCH */
diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h
new file mode 100644
index 0000000..447e227
--- /dev/null
+++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.h
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MV88F6281GTW_GE_H
+#define __MV88F6281GTW_GE_H
+
+#define MV88F6281GTW_GE_OE_LOW (~((1 << 7) | (1 << 12) \
+ |(1 << 20) | (1 << 21))) /*enable GLED,RLED */
+#define MV88F6281GTW_GE_OE_HIGH (~((1 << 4)|(1 << 6)|(1 << 7)|(1 << 12) \
+ |(1 << 13)|(1 << 16)|(1 << 17)))
+#define MV88F6281GTW_GE_OE_VAL_LOW (1 << 20) /*make GLED on */
+#define MV88F6281GTW_GE_OE_VAL_HIGH ((1 << 6)|(1 << 13)|(1 << 16)|(1 << 17))
+
+
+#endif /* __MV88F6281GTW_GE_H */
diff --git a/board/Marvell/openrd/Kconfig b/board/Marvell/openrd/Kconfig
new file mode 100644
index 0000000..124b66d
--- /dev/null
+++ b/board/Marvell/openrd/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OPENRD
+
+config SYS_BOARD
+ default "openrd"
+
+config SYS_VENDOR
+ default "Marvell"
+
+config SYS_CONFIG_NAME
+ default "openrd"
+
+endif
diff --git a/board/Marvell/openrd/MAINTAINERS b/board/Marvell/openrd/MAINTAINERS
new file mode 100644
index 0000000..7a189ab
--- /dev/null
+++ b/board/Marvell/openrd/MAINTAINERS
@@ -0,0 +1,12 @@
+OPENRD BOARD
+M: Prafulla Wadaskar <prafulla@marvell.com>
+S: Maintained
+F: board/Marvell/openrd/
+F: include/configs/openrd.h
+F: configs/openrd_base_defconfig
+
+OPENRD_CLIENT BOARD
+#M: -
+S: Maintained
+F: configs/openrd_client_defconfig
+F: configs/openrd_ultimate_defconfig
diff --git a/board/Marvell/openrd/Makefile b/board/Marvell/openrd/Makefile
new file mode 100644
index 0000000..8f95b79
--- /dev/null
+++ b/board/Marvell/openrd/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2009
+# Net Insight <www.netinsight.net>
+# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+#
+# Based on sheevaplug:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := openrd.o
diff --git a/board/Marvell/openrd/kwbimage.cfg b/board/Marvell/openrd/kwbimage.cfg
new file mode 100644
index 0000000..8e59937
--- /dev/null
+++ b/board/Marvell/openrd/kwbimage.cfg
@@ -0,0 +1,152 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=x8
+# bit7-6: 11, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000042 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 1, DDR drive strength reduced
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
+# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
+# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
+# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
+# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+
+DATA 0xFFD0149C 0x0000E40f # CPU ODT Control
+# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
+# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
+# bit14: 1, M_STARTBURST_IN ODT: Enabled
+# bit15: 1, DDR IO ODT Unit: Use ODT block
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c
new file mode 100644
index 0000000..55cf525
--- /dev/null
+++ b/board/Marvell/openrd/openrd.c
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.c:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "openrd.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(OPENRD_OE_VAL_LOW,
+ OPENRD_OE_VAL_HIGH,
+ OPENRD_OE_LOW, OPENRD_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD, /* Alt UART1_TXD */
+ MPP14_SD_D0, /* Alt UART1_RXD */
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GPIO,
+ MPP29_TSMP9,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GPIO, /* UART1 / SD sel */
+ MPP35_TDM_CH0_TX_QL,
+ MPP36_TDM_SPI_CS1,
+ MPP37_TDM_CH2_TX_QL,
+ MPP38_TDM_CH2_RX_QL,
+ MPP39_AUDIO_I2SBCLK,
+ MPP40_AUDIO_I2SDO,
+ MPP41_AUDIO_I2SLRC,
+ MPP42_AUDIO_I2SMCLK,
+ MPP43_AUDIO_I2SDI,
+ MPP44_AUDIO_EXTCLK,
+ MPP45_TDM_PCLK,
+ MPP46_TDM_FS,
+ MPP47_TDM_DRX,
+ MPP48_TDM_DTX,
+ MPP49_TDM_CH0_RX_QL,
+ 0
+ };
+
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
+ gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
+#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
+ gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
+#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
+ gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
+#endif
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116/88E1121 PHY */
+void mv_phy_init(char *name)
+{
+ u16 reg;
+ u16 devadr;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf(PHY_NO" Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+ mv_phy_init("egiga0");
+
+#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
+ /* Kirkwood ethernet driver is written with the assumption that in case
+ * of multiple PHYs, their addresses are consecutive. But unfortunately
+ * in case of OpenRD-Client, PHY addresses are not consecutive.*/
+ miiphy_write("egiga1", 0xEE, 0xEE, 24);
+#endif
+
+#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
+ defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
+ /* configure and initialize both PHY's */
+ mv_phy_init("egiga1");
+#endif
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/openrd/openrd.h b/board/Marvell/openrd/openrd.h
new file mode 100644
index 0000000..56dfeea
--- /dev/null
+++ b/board/Marvell/openrd/openrd.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __OPENRD_BASE_H
+#define __OPENRD_BASE_H
+
+#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */
+#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */
+#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */
+#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __OPENRD_BASE_H */
diff --git a/board/Marvell/rd6281a/Kconfig b/board/Marvell/rd6281a/Kconfig
new file mode 100644
index 0000000..025ee26
--- /dev/null
+++ b/board/Marvell/rd6281a/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_RD6281A
+
+config SYS_BOARD
+ default "rd6281a"
+
+config SYS_VENDOR
+ default "Marvell"
+
+config SYS_CONFIG_NAME
+ default "rd6281a"
+
+endif
diff --git a/board/Marvell/rd6281a/MAINTAINERS b/board/Marvell/rd6281a/MAINTAINERS
new file mode 100644
index 0000000..d4ad592
--- /dev/null
+++ b/board/Marvell/rd6281a/MAINTAINERS
@@ -0,0 +1,6 @@
+RD6281A BOARD
+M: Prafulla Wadaskar <prafulla@marvell.com>
+S: Maintained
+F: board/Marvell/rd6281a/
+F: include/configs/rd6281a.h
+F: configs/rd6281a_defconfig
diff --git a/board/Marvell/rd6281a/Makefile b/board/Marvell/rd6281a/Makefile
new file mode 100644
index 0000000..cb77370
--- /dev/null
+++ b/board/Marvell/rd6281a/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := rd6281a.o
diff --git a/board/Marvell/rd6281a/kwbimage.cfg b/board/Marvell/rd6281a/kwbimage.cfg
new file mode 100644
index 0000000..f969d92
--- /dev/null
+++ b/board/Marvell/rd6281a/kwbimage.cfg
@@ -0,0 +1,151 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000099 # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=x8
+# bit7-6: 11, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 1, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 0, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
+# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c
new file mode 100644
index 0000000..b0020c9
--- /dev/null
+++ b/board/Marvell/rd6281a/rd6281a.c
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "rd6281a.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(RD6281A_OE_VAL_LOW,
+ RD6281A_OE_VAL_HIGH,
+ RD6281A_OE_LOW, RD6281A_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GE1_14,
+ MPP35_GPIO,
+ MPP36_AUDIO_SPDIFI,
+ MPP37_AUDIO_SPDIFO,
+ MPP38_GPIO,
+ MPP39_TDM_SPI_CS0,
+ MPP40_TDM_SPI_SCK,
+ MPP41_TDM_SPI_MISO,
+ MPP42_TDM_SPI_MOSI,
+ MPP43_TDM_CODEC_INTn,
+ MPP44_GPIO,
+ MPP45_TDM_PCLK,
+ MPP46_TDM_FS,
+ MPP47_TDM_DRX,
+ MPP48_TDM_DTX,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+void mv_phy_88e1116_init(char *name)
+{
+ u16 reg;
+ u16 devadr;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ if (miiphy_read (name, devadr, MII_BMCR, ®) != 0) {
+ printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
+ return;
+ }
+ if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) {
+ printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
+ return;
+ }
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+
+/* Configure and enable Switch and PHY */
+void reset_phy(void)
+{
+ /* configure and initialize switch */
+ struct mv88e61xx_config swcfg = {
+ .name = "egiga0",
+ .vlancfg = MV88E61XX_VLANCFG_ROUTER,
+ .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
+ .led_init = MV88E61XX_LED_INIT_EN,
+ .portstate = MV88E61XX_PORTSTT_FORWARDING,
+ .cpuport = (1 << 5),
+ .ports_enabled = 0x3f,
+ };
+
+ mv88e61xx_switch_initialize(&swcfg);
+
+ /* configure and initialize PHY */
+ mv_phy_88e1116_init("egiga1");
+}
diff --git a/board/Marvell/rd6281a/rd6281a.h b/board/Marvell/rd6281a/rd6281a.h
new file mode 100644
index 0000000..5e1f6a8
--- /dev/null
+++ b/board/Marvell/rd6281a/rd6281a.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __RD6281A_H
+#define __RD6281A_H
+
+#define RD6281A_OE_LOW (~(1 << 7))
+#define RD6281A_OE_HIGH (~(1 << 2 | 1 << 12))
+#define RD6281A_OE_VAL_LOW (0)
+#define RD6281A_OE_VAL_HIGH (1 << 12)
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __RD6281A_H */
diff --git a/board/Marvell/sheevaplug/Kconfig b/board/Marvell/sheevaplug/Kconfig
new file mode 100644
index 0000000..e5f9284
--- /dev/null
+++ b/board/Marvell/sheevaplug/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SHEEVAPLUG
+
+config SYS_BOARD
+ default "sheevaplug"
+
+config SYS_VENDOR
+ default "Marvell"
+
+config SYS_CONFIG_NAME
+ default "sheevaplug"
+
+endif
diff --git a/board/Marvell/sheevaplug/MAINTAINERS b/board/Marvell/sheevaplug/MAINTAINERS
new file mode 100644
index 0000000..2b0103d
--- /dev/null
+++ b/board/Marvell/sheevaplug/MAINTAINERS
@@ -0,0 +1,6 @@
+SHEEVAPLUG BOARD
+M: Prafulla Wadaskar <prafulla@marvell.com>
+S: Maintained
+F: board/Marvell/sheevaplug/
+F: include/configs/sheevaplug.h
+F: configs/sheevaplug_defconfig
diff --git a/board/Marvell/sheevaplug/Makefile b/board/Marvell/sheevaplug/Makefile
new file mode 100644
index 0000000..e812545
--- /dev/null
+++ b/board/Marvell/sheevaplug/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := sheevaplug.o
diff --git a/board/Marvell/sheevaplug/kwbimage.cfg b/board/Marvell/sheevaplug/kwbimage.cfg
new file mode 100644
index 0000000..76b7528
--- /dev/null
+++ b/board/Marvell/sheevaplug/kwbimage.cfg
@@ -0,0 +1,146 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer to doc/README.kwbimage for more details about how-to
+# configure and create kirkwood boot images.
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=x8
+# bit7-6: 11, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c
new file mode 100644
index 0000000..8907fb5
--- /dev/null
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "sheevaplug.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
+ SHEEVAPLUG_OE_VAL_HIGH,
+ SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_UART0_RTS,
+ MPP9_UART0_CTS,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_TSMP9,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/sheevaplug/sheevaplug.h b/board/Marvell/sheevaplug/sheevaplug.h
new file mode 100644
index 0000000..8517b99
--- /dev/null
+++ b/board/Marvell/sheevaplug/sheevaplug.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SHEEVAPLUG_H
+#define __SHEEVAPLUG_H
+
+#define SHEEVAPLUG_OE_LOW (~(0))
+#define SHEEVAPLUG_OE_HIGH (~(0))
+#define SHEEVAPLUG_OE_VAL_LOW (1 << 29) /* USB_PWEN low */
+#define SHEEVAPLUG_OE_VAL_HIGH (1 << 17) /* LED pin high */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __SHEEVAPLUG_H */
diff --git a/board/Seagate/dockstar/Kconfig b/board/Seagate/dockstar/Kconfig
new file mode 100644
index 0000000..b50cd3b
--- /dev/null
+++ b/board/Seagate/dockstar/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DOCKSTAR
+
+config SYS_BOARD
+ default "dockstar"
+
+config SYS_VENDOR
+ default "Seagate"
+
+config SYS_CONFIG_NAME
+ default "dockstar"
+
+endif
diff --git a/board/Seagate/dockstar/MAINTAINERS b/board/Seagate/dockstar/MAINTAINERS
new file mode 100644
index 0000000..f259e58
--- /dev/null
+++ b/board/Seagate/dockstar/MAINTAINERS
@@ -0,0 +1,6 @@
+DOCKSTAR BOARD
+M: Eric Cooper <ecc@cmu.edu>
+S: Maintained
+F: board/Seagate/dockstar/
+F: include/configs/dockstar.h
+F: configs/dockstar_defconfig
diff --git a/board/Seagate/dockstar/Makefile b/board/Seagate/dockstar/Makefile
new file mode 100644
index 0000000..2ef5093
--- /dev/null
+++ b/board/Seagate/dockstar/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/Makefile originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dockstar.o
diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c
new file mode 100644
index 0000000..83ab1bc
--- /dev/null
+++ b/board/Seagate/dockstar/dockstar.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.c originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include "dockstar.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(DOCKSTAR_OE_VAL_LOW,
+ DOCKSTAR_OE_VAL_HIGH,
+ DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_UART0_RTS,
+ MPP9_UART0_CTS,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_TSMP9,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_DOCKSTAR;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#define GREEN_LED (1 << 14)
+#define ORANGE_LED (1 << 15)
+#define BOTH_LEDS (GREEN_LED | ORANGE_LED)
+#define NEITHER_LED 0
+
+static void set_leds(u32 leds, u32 blinking)
+{
+ struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
+ u32 oe = readl(&r->oe) | BOTH_LEDS;
+ writel(oe & ~leds, &r->oe); /* active low */
+ u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
+ writel(bl | blinking, &r->blink_en);
+}
+
+void show_boot_progress(int val)
+{
+ switch (val) {
+ case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
+ set_leds(BOTH_LEDS, NEITHER_LED);
+ break;
+ case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
+ set_leds(GREEN_LED, GREEN_LED);
+ break;
+ default:
+ if (val < 0) /* error */
+ set_leds(ORANGE_LED, ORANGE_LED);
+ break;
+ }
+}
diff --git a/board/Seagate/dockstar/dockstar.h b/board/Seagate/dockstar/dockstar.h
new file mode 100644
index 0000000..ec6fa25
--- /dev/null
+++ b/board/Seagate/dockstar/dockstar.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.h originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DOCKSTAR_H
+#define __DOCKSTAR_H
+
+#define DOCKSTAR_OE_LOW (~(0))
+#define DOCKSTAR_OE_HIGH (~(0))
+#define DOCKSTAR_OE_VAL_LOW (1 << 29) /* USB_PWEN low */
+#define DOCKSTAR_OE_VAL_HIGH (1 << 17) /* LED pin high */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __DOCKSTAR_H */
diff --git a/board/Seagate/dockstar/kwbimage.cfg b/board/Seagate/dockstar/kwbimage.cfg
new file mode 100644
index 0000000..e68ce64
--- /dev/null
+++ b/board/Seagate/dockstar/kwbimage.cfg
@@ -0,0 +1,149 @@
+#
+# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/kwbimage.cfg originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000d # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/Seagate/goflexhome/Kconfig b/board/Seagate/goflexhome/Kconfig
new file mode 100644
index 0000000..0cbeaf7
--- /dev/null
+++ b/board/Seagate/goflexhome/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GOFLEXHOME
+
+config SYS_BOARD
+ default "goflexhome"
+
+config SYS_VENDOR
+ default "Seagate"
+
+config SYS_CONFIG_NAME
+ default "goflexhome"
+
+endif
diff --git a/board/Seagate/goflexhome/MAINTAINERS b/board/Seagate/goflexhome/MAINTAINERS
new file mode 100644
index 0000000..6d6a1ff
--- /dev/null
+++ b/board/Seagate/goflexhome/MAINTAINERS
@@ -0,0 +1,6 @@
+GOFLEXHOME BOARD
+M: Suriyan Ramasami <suriyan.r@gmail.com>
+S: Maintained
+F: board/Seagate/goflexhome/
+F: include/configs/goflexhome.h
+F: configs/goflexhome_defconfig
diff --git a/board/Seagate/goflexhome/Makefile b/board/Seagate/goflexhome/Makefile
new file mode 100644
index 0000000..e56230c
--- /dev/null
+++ b/board/Seagate/goflexhome/Makefile
@@ -0,0 +1,15 @@
+#
+# Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+#
+# Based on dockstar/Makefile originally written by
+# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/Makefile originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := goflexhome.o
diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c
new file mode 100644
index 0000000..1f4fb92
--- /dev/null
+++ b/board/Seagate/goflexhome/goflexhome.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+ *
+ * Based on dockstar.c originally written by
+ * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.c originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_UART0_RTS,
+ MPP9_UART0_CTS,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_TSMP9,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW,
+ GOFLEXHOME_OE_VAL_HIGH,
+ GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __func__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#define GREEN_LED (1 << 14)
+#define ORANGE_LED (1 << 15)
+#define BOTH_LEDS (GREEN_LED | ORANGE_LED)
+#define NEITHER_LED 0
+
+static void set_leds(u32 leds, u32 blinking)
+{
+ struct kwgpio_registers *r;
+ u32 oe;
+ u32 bl;
+
+ r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
+ oe = readl(&r->oe) | BOTH_LEDS;
+ writel(oe & ~leds, &r->oe); /* active low */
+ bl = readl(&r->blink_en) & ~BOTH_LEDS;
+ writel(bl | blinking, &r->blink_en);
+}
+
+void show_boot_progress(int val)
+{
+ switch (val) {
+ case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
+ set_leds(BOTH_LEDS, NEITHER_LED);
+ break;
+ case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
+ set_leds(GREEN_LED, GREEN_LED);
+ break;
+ default:
+ if (val < 0) /* error */
+ set_leds(ORANGE_LED, ORANGE_LED);
+ break;
+ }
+}
diff --git a/board/Seagate/goflexhome/kwbimage.cfg b/board/Seagate/goflexhome/kwbimage.cfg
new file mode 100644
index 0000000..9d147ea
--- /dev/null
+++ b/board/Seagate/goflexhome/kwbimage.cfg
@@ -0,0 +1,152 @@
+#
+# Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+#
+# Based on dockstar/kwbimage.cfg originally written by
+# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/kwbimage.cfg originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000d # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/a3m071/Kconfig b/board/a3m071/Kconfig
new file mode 100644
index 0000000..444c450
--- /dev/null
+++ b/board/a3m071/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_A3M071
+
+config SYS_BOARD
+ default "a3m071"
+
+config SYS_CONFIG_NAME
+ default "a3m071"
+
+endif
diff --git a/board/a3m071/MAINTAINERS b/board/a3m071/MAINTAINERS
new file mode 100644
index 0000000..975107d
--- /dev/null
+++ b/board/a3m071/MAINTAINERS
@@ -0,0 +1,7 @@
+A3M071 BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/a3m071/
+F: include/configs/a3m071.h
+F: configs/a3m071_defconfig
+F: configs/a4m2k_defconfig
diff --git a/board/a3m071/Makefile b/board/a3m071/Makefile
new file mode 100644
index 0000000..4e31e33
--- /dev/null
+++ b/board/a3m071/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := a3m071.o
diff --git a/board/a3m071/README b/board/a3m071/README
new file mode 100644
index 0000000..112c47b
--- /dev/null
+++ b/board/a3m071/README
@@ -0,0 +1,80 @@
+------------------------------------------------------------------------
+A3M071 board support
+------------------------------------------------------------------------
+
+
+SPL NOR flash support:
+----------------------
+To boot fast into the OS (Linux), this board port integrates the SPL
+framework. This means, that a special, stripped-down version of
+U-Boot runs in the beginning. In the case of the A3M071 board, this
+SPL U-Boot version is less than 16 KiB big. This SPL U-Boot can either
+boot the OS (Linux) or a "real", full-blown U-Boot. This detection
+on whether to boot Linux or U-Boot is done by using the "boot_os"
+environment variable. If "boot_os" is set to "yes", Linux will be
+loaded and booted from the SPL U-Boot version. Otherwise, the
+full-blown U-Boot version will be loaded and run.
+
+Enabling Linux booting:
+-----------------------
+From U-Boot:
+=> setenv boot_os yes
+=> saveenv
+
+From Linux:
+$ fw_setenv boot_os yes
+
+Enabling U-Boot booting:
+------------------------
+From U-Boot:
+=> setenv boot_os no
+=> saveenv
+
+From Linux:
+$ fw_setenv boot_os no
+
+
+Preparing Linux image(s) for booting from SPL U-Boot:
+-----------------------------------------------------
+To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
+prepard/patched first. U-Boot usually inserts some dynamic values into
+the DT binary (blob), e.g. autodetected memory size, MAC addresses,
+clocks speeds etc. To generate this patched DT blob, you can use
+the following command:
+
+1. Load fdt blob to SDRAM:
+=> tftp 1800000 a3m071/a3m071.dtb
+
+2. Set bootargs as desired for Linux booting (e.g. flash_mtd):
+=> run mtdargs addip2 addtty
+
+3. Use "fdt" commands to patch the DT blob:
+=> fdt addr 1800000
+=> fdt boardsetup
+=> fdt chosen
+
+4. Display patched DT blob (optional):
+=> fdt print
+
+5. Save fdt to NOR flash:
+=> erase fc180000 fc07ffff
+=> cp.b 1800000 fc180000 10000
+
+All this can be integrated into an environment command:
+=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip addtty; \
+ fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc180000 fc07ffff; \
+ cp.b 1800000 fc180000 10000'
+=> saveenv
+
+After this, only "run upd_fdt" needs to get called to load, patch
+and save the DT blob into NOR flash.
+
+Additionally, the Linux kernel image has to be saved uncompressed in
+its uImage file (and not gzip compressed). This can be done with this
+command:
+
+$ mkimage -A ppc -O linux -T kernel -C none -a 0 -e 0 \
+ -n "Linux Kernel Image" -d vmlinux.bin uImage.uncompressed
+
+------------------------------------------------------------------------
+Stefan Roese, 2012-08-23
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
new file mode 100644
index 0000000..ee1681b
--- /dev/null
+++ b/board/a3m071/a3m071.c
@@ -0,0 +1,477 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2006
+ * MicroSys GmbH
+ *
+ * Copyright 2012-2013 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <miiphy.h>
+#include <linux/compiler.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_A4M2K
+#include "is46r16320d.h"
+#else
+#include "mt46v16m16-75.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_SYS_RAMBOOT) && \
+ (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
+static void sdram_start(int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+ long control = SDRAM_CONTROL | hi_addr_bit;
+
+ /* unlock mode register */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
+
+ /* precharge all banks */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+
+#ifdef SDRAM_DDR
+ /* set mode register: extended mode */
+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+
+ /* set mode register: reset DLL */
+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+#endif
+
+ /* precharge all banks */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+
+ /* auto refresh */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
+
+ /* set mode register */
+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+ /* normal operation */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
+
+ /*
+ * Wait a short while for the DLL to lock before accessing
+ * the SDRAM
+ */
+ udelay(100);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+phys_size_t initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ uint svr, pvr;
+#if !defined(CONFIG_SYS_RAMBOOT) && \
+ (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
+ out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
+
+ /* setup config registers */
+ out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+ out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+#ifdef SDRAM_DDR
+ /* set tap delay */
+ out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
+ 0x13 + __builtin_ffs(dramsize >> 20) - 1);
+ } else {
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
+ }
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
+ if (dramsize >= 0x13)
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ else
+ dramsize = 0;
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
+ if (dramsize2 >= 0x13)
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ else
+ dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
+ out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
+
+ return dramsize + dramsize2;
+}
+
+static void get_revisions(int *failsavelevel, int *digiboardversion,
+ int *fpgaversion)
+{
+ struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+ u8 val;
+
+ /* read digitalboard-version from TMR[2..4] */
+ val = 0;
+ val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
+ val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
+ val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
+ *digiboardversion = val;
+
+ /*
+ * A4M2K only supports digiboardversion. No failsavelevel and
+ * fpgaversion here.
+ */
+#if !defined(CONFIG_A4M2K)
+ /*
+ * Figure out failsavelevel
+ * see ticket dsvk#59
+ */
+ *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */
+
+ if (*digiboardversion == 0) {
+ *failsavelevel = 1; /* digiboard-version ok */
+
+ /* read fpga-version from TMR[5..7] */
+ val = 0;
+ val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0;
+ val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
+ val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
+ *fpgaversion = val;
+
+ if (*fpgaversion == 1)
+ *failsavelevel = 2; /* fpga-version ok */
+ }
+#endif
+}
+
+/*
+ * This function is called from the SPL U-Boot version for
+ * early init stuff, that needs to be done for OS (e.g. Linux)
+ * booting. Doing it later in the real U-Boot would not work
+ * in case that the SPL U-Boot boots Linux directly.
+ */
+void spl_board_init(void)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_mmap_ctl *mm =
+ (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+
+#if defined(CONFIG_A4M2K)
+ /* enable CS3 and CS5 (FPGA) */
+ setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21));
+#else
+ int digiboardversion;
+ int failsavelevel;
+ int fpgaversion;
+ u32 val;
+
+ get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
+
+ val = in_be32(&mm->ipbi_ws_ctrl);
+
+ /* first clear bits 19..21 (CS3...5) */
+ val &= ~((1 << 19) | (1 << 20) | (1 << 21));
+ if (failsavelevel == 2) {
+ /* FPGA ok */
+ val |= (1 << 19) | (1 << 21);
+ }
+
+ if (failsavelevel >= 1) {
+ /* at least digiboard-version ok */
+ val |= (1 << 20);
+ }
+
+ /* And write new value back to register */
+ out_be32(&mm->ipbi_ws_ctrl, val);
+
+
+ /* Setup pin multiplexing */
+ if (failsavelevel == 2) {
+ /* fpga-version ok */
+#if defined(CONFIG_SYS_GPS_PORT_CONFIG_2)
+ out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_2);
+#endif
+ } else if (failsavelevel == 1) {
+ /* digiboard-version ok - fpga not */
+#if defined(CONFIG_SYS_GPS_PORT_CONFIG_1)
+ out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_1);
+#endif
+ } else {
+ /* full failsave-mode */
+#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
+ out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
+#endif
+ }
+#endif
+
+ /*
+ * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
+ * ticket #60
+ *
+ * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
+ * set bit 0(msb) to 1
+ */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN);
+
+#if defined(CONFIG_A4M2K)
+ /* Setup USB[x] as MPCDiag[0..3] GPIO outputs */
+
+ /* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */
+ gpio->simple_ddr |= 1 << (31 - 15);
+ gpio->simple_ddr |= 1 << (31 - 14);
+ gpio->simple_ddr |= 1 << (31 - 13);
+ gpio->simple_ddr |= 1 << (31 - 12);
+
+ /* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */
+ gpio->simple_gpioe |= 1 << (31 - 15);
+ gpio->simple_gpioe |= 1 << (31 - 14);
+ gpio->simple_gpioe |= 1 << (31 - 13);
+ gpio->simple_gpioe |= 1 << (31 - 12);
+
+ /* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */
+
+ /* set PSC2[0..2] (STSLED[0..2]) direction to output */
+ gpio->simple_ddr |= 1 << (31 - 27);
+ gpio->simple_ddr |= 1 << (31 - 26);
+ gpio->simple_ddr |= 1 << (31 - 25);
+
+ /* enable PSC2[0..2] (STSLED[0..2]) as GPIO */
+ gpio->simple_gpioe |= 1 << (31 - 27);
+ gpio->simple_gpioe |= 1 << (31 - 26);
+ gpio->simple_gpioe |= 1 << (31 - 25);
+
+ /* Setup PSC6[2] as MRST2 self reset GPIO output */
+
+ /* set PSC6[2]/IRDA_TX (MRST2) direction to output */
+ gpio->simple_ddr |= 1 << (31 - 3);
+
+ /* set PSC6[2]/IRDA_TX (MRST2) output as open drain */
+ gpio->simple_ode |= 1 << (31 - 3);
+
+ /* set PSC6[2]/IRDA_TX (MRST2) output as default high */
+ gpio->simple_dvo |= 1 << (31 - 3);
+
+ /* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */
+ gpio->simple_gpioe |= 1 << (31 - 3);
+
+ /* Setup PSC6[3] as HARNSSCD harness code GPIO input */
+
+ /* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */
+ gpio->simple_ddr |= 0 << (31 - 2);
+
+ /* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */
+ gpio->simple_gpioe |= 1 << (31 - 2);
+#else
+ /* setup GPIOs for status-leds if needed - see ticket #57 */
+ if (failsavelevel > 0) {
+ /* digiboard-version is OK */
+ /* LED is LOW ACTIVE - so deactivate by set output to 1 */
+ gpio->simple_dvo |= 1 << (31 - 12);
+ gpio->simple_dvo |= 1 << (31 - 13);
+ /* set GPIO direction to output */
+ gpio->simple_ddr |= 1 << (31 - 12);
+ gpio->simple_ddr |= 1 << (31 - 13);
+ /* open drain config is set to "normal output" at reset */
+ /* gpio->simple_ode &=~ ( 1 << (31-12) ); */
+ /* gpio->simple_ode &=~ ( 1 << (31-13) ); */
+ /* enable as GPIO */
+ gpio->simple_gpioe |= 1 << (31 - 12);
+ gpio->simple_gpioe |= 1 << (31 - 13);
+ }
+
+ /* setup fpga irq - see ticket #65 */
+ if (failsavelevel > 1) {
+ /*
+ * The main irq initialisation is done in interrupts.c
+ * mpc5xxx_init_irq
+ */
+ struct mpc5xxx_intr *intr =
+ (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
+
+ setbits_be32(&intr->ctrl, 0x08C01801);
+
+ /*
+ * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
+ * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
+ */
+ }
+#endif
+}
+
+int checkboard(void)
+{
+ int digiboardversion;
+ int failsavelevel;
+ int fpgaversion;
+
+ get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
+
+#ifdef CONFIG_A4M2K
+ puts("Board: A4M2K\n");
+ printf(" digiboard IO version %u\n", digiboardversion);
+#else
+ puts("Board: A3M071\n");
+ printf("Rev: failsave level %u\n", failsavelevel);
+ printf(" digiboard IO version %u\n", digiboardversion);
+ if (failsavelevel > 0) /* only if fpga-version red */
+ printf(" fpga IO version %u\n", fpgaversion);
+#endif
+
+ return 0;
+}
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+ /* adjust flash start and offset to detected values */
+ gd->bd->bi_flashstart = flash_info[0].start[0];
+ gd->bd->bi_flashoffset = 0;
+
+ /* adjust mapping */
+ out_be32((void *)MPC5XXX_BOOTCS_START,
+ START_REG(gd->bd->bi_flashstart));
+ out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart));
+ out_be32((void *)MPC5XXX_BOOTCS_STOP,
+ STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
+ out_be32((void *)MPC5XXX_CS0_STOP,
+ STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * A3M071 specific implementation of spl_start_uboot()
+ *
+ * RETURN
+ * 0 if booting into OS is selected (default)
+ * 1 if booting into U-Boot is selected
+ */
+int spl_start_uboot(void)
+{
+ char s[8];
+
+ env_init();
+ getenv_f("boot_os", s, sizeof(s));
+ if ((s != NULL) && (*s == '1' || *s == 'y' || *s == 'Y' ||
+ *s == 't' || *s == 'T'))
+ return 0;
+
+ return 1;
+}
+#endif
+
+#if defined(CONFIG_HW_WATCHDOG)
+static int watchdog_toggle;
+
+void hw_watchdog_reset(void)
+{
+ int val;
+
+ /*
+ * Check if watchdog is enabled via user command
+ */
+ if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) {
+ /* Set direction to output */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN);
+
+ /*
+ * Toggle watchdog output
+ */
+ val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
+ CONFIG_WDOG_GPIO_PIN);
+ if (val) {
+ clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
+ CONFIG_WDOG_GPIO_PIN);
+ } else {
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
+ CONFIG_WDOG_GPIO_PIN);
+ }
+ }
+}
+
+int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc != 2)
+ goto usage;
+
+ if (strncmp(argv[1], "on", 2) == 0)
+ watchdog_toggle = 1;
+ else if (strncmp(argv[1], "off", 3) == 0)
+ watchdog_toggle = 0;
+ else
+ goto usage;
+
+ return 0;
+usage:
+ printf("Usage: wdogtoggle %s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle,
+ "toggle GPIO pin to service watchdog",
+ "[on/off] - Switch watchdog toggling via GPIO pin on/off"
+);
+#endif
diff --git a/board/a3m071/is46r16320d.h b/board/a3m071/is46r16320d.h
new file mode 100644
index 0000000..981359f
--- /dev/null
+++ b/board/a3m071/is46r16320d.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR /* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */
+
+/* SDRAM Config Standard timing */
+#define SDRAM_MODE 0x008d0000
+#define SDRAM_EMODE 0x40010000
+#define SDRAM_CONTROL 0x70430f00
+#define SDRAM_CONFIG1 0x33622930
+#define SDRAM_CONFIG2 0x46670000
+#define SDRAM_TAPDELAY 0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/a3m071/mt46v16m16-75.h b/board/a3m071/mt46v16m16-75.h
new file mode 100644
index 0000000..8f42830
--- /dev/null
+++ b/board/a3m071/mt46v16m16-75.h
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR /* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x704f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/a4m072/Kconfig b/board/a4m072/Kconfig
new file mode 100644
index 0000000..ba5447f
--- /dev/null
+++ b/board/a4m072/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_A4M072
+
+config SYS_BOARD
+ default "a4m072"
+
+config SYS_CONFIG_NAME
+ default "a4m072"
+
+endif
diff --git a/board/a4m072/MAINTAINERS b/board/a4m072/MAINTAINERS
new file mode 100644
index 0000000..83dc59e
--- /dev/null
+++ b/board/a4m072/MAINTAINERS
@@ -0,0 +1,6 @@
+A4M072 BOARD
+M: Sergei Poselenov <sposelenov@emcraft.com>
+S: Maintained
+F: board/a4m072/
+F: include/configs/a4m072.h
+F: configs/a4m072_defconfig
diff --git a/board/a4m072/Makefile b/board/a4m072/Makefile
new file mode 100644
index 0000000..2a40e57
--- /dev/null
+++ b/board/a4m072/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := a4m072.o
diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c
new file mode 100644
index 0000000..c5d161b
--- /dev/null
+++ b/board/a4m072/a4m072.c
@@ -0,0 +1,475 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2010
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <netdev.h>
+#include <led-display.h>
+#include <linux/err.h>
+
+#include "mt46v32m16.h"
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+ long control = SDRAM_CONTROL | hi_addr_bit;
+
+ /* unlock mode register */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+ __asm__ volatile ("sync");
+#endif
+
+ /* precharge all banks */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
+ __asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+ ulong dramsize = 0;
+ uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
+ out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+ out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set tap delay */
+ out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
+ __asm__ volatile ("sync");
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
+ 0x13 + __builtin_ffs(dramsize >> 20) - 1);
+ } else {
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
+ if (dramsize >= 0x13) {
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ } else {
+ dramsize = 0;
+ }
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
+ __asm__ volatile ("sync");
+ }
+
+ return dramsize;
+}
+
+int checkboard (void)
+{
+ puts ("Board: A4M072\n");
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, num_if = 0;
+
+ /* Initialize TSECs first */
+ if ((rv = cpu_eth_init(bis)) >= 0)
+ num_if += rv;
+ else
+ printf("ERROR: failed to initialize FEC.\n");
+
+ if ((rv = pci_eth_init(bis)) >= 0)
+ num_if += rv;
+ else
+ printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+ return num_if;
+}
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * Initialize EEPROM write-protect GPIO pin.
+ */
+int misc_init_r(void)
+{
+#if defined(CONFIG_SYS_EEPROM_WREN)
+ /* Enable GPIO pin */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
+ /* Set direction, output */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
+ /* De-assert write enable */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+#endif
+ return 0;
+}
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access */
+ clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
+ CONFIG_SYS_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+#endif
+
+#ifdef CONFIG_CMD_DISPLAY
+#define DISPLAY_BUF_SIZE 2
+static u8 display_buf[DISPLAY_BUF_SIZE];
+static u8 display_putc_pos;
+static u8 display_out_pos;
+
+void display_set(int cmd) {
+
+ if (cmd & DISPLAY_CLEAR) {
+ display_buf[0] = display_buf[1] = 0;
+ }
+
+ if (cmd & DISPLAY_HOME) {
+ display_putc_pos = 0;
+ }
+}
+
+#define SEG_A (1<<0)
+#define SEG_B (1<<1)
+#define SEG_C (1<<2)
+#define SEG_D (1<<3)
+#define SEG_E (1<<4)
+#define SEG_F (1<<5)
+#define SEG_G (1<<6)
+#define SEG_P (1<<7)
+#define SEG__ 0
+
+/*
+ * +- A -+
+ * | |
+ * F B
+ * | |
+ * +- G -+
+ * | |
+ * E C
+ * | |
+ * +- D -+ P
+ *
+ * 0..9 index 0..9
+ * A..Z index 10..35
+ * - index 36
+ * _ index 37
+ * . index 38
+ */
+
+#define SYMBOL_DASH (36)
+#define SYMBOL_UNDERLINE (37)
+#define SYMBOL_DOT (38)
+
+static u8 display_char2seg7_tbl[]=
+{
+ SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* 0 */
+ SEG_B | SEG_C, /* 1 */
+ SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* 2 */
+ SEG_A | SEG_B | SEG_C | SEG_D | SEG_G, /* 3 */
+ SEG_B | SEG_C | SEG_F | SEG_G, /* 4 */
+ SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* 5 */
+ SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 6 */
+ SEG_A | SEG_B | SEG_C, /* 7 */
+ SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 8 */
+ SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* 9 */
+ SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* A */
+ SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* b */
+ SEG_A | SEG_D | SEG_E | SEG_F, /* C */
+ SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */
+ SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */
+ SEG_A | SEG_E | SEG_F | SEG_G, /* F */
+ 0, /* g - not displayed */
+ SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */
+ SEG_B | SEG_C, /* I */
+ 0, /* J - not displayed */
+ 0, /* K - not displayed */
+ SEG_D | SEG_E | SEG_F, /* L */
+ 0, /* m - not displayed */
+ 0, /* n - not displayed */
+ SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* O */
+ SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */
+ 0, /* q - not displayed */
+ 0, /* r - not displayed */
+ SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */
+ SEG_D | SEG_E | SEG_F | SEG_G, /* t */
+ SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */
+ 0, /* V - not displayed */
+ 0, /* w - not displayed */
+ 0, /* X - not displayed */
+ SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */
+ 0, /* Z - not displayed */
+ SEG_G, /* - */
+ SEG_D, /* _ */
+ SEG_P /* . */
+};
+
+/* Convert char to the LED segments representation */
+static u8 display_char2seg7(char c)
+{
+ u8 val = 0;
+
+ if (c >= '0' && c <= '9')
+ c -= '0';
+ else if (c >= 'a' && c <= 'z')
+ c -= 'a' - 10;
+ else if (c >= 'A' && c <= 'Z')
+ c -= 'A' - 10;
+ else if (c == '-')
+ c = SYMBOL_DASH;
+ else if (c == '_')
+ c = SYMBOL_UNDERLINE;
+ else if (c == '.')
+ c = SYMBOL_DOT;
+ else
+ c = ' '; /* display unsupported symbols as space */
+
+ if (c != ' ')
+ val = display_char2seg7_tbl[(int)c];
+
+ return val;
+}
+
+int display_putc(char c)
+{
+ if (display_putc_pos >= DISPLAY_BUF_SIZE)
+ return -1;
+
+ display_buf[display_putc_pos++] = display_char2seg7(c);
+ /* one-symbol message should be steady */
+ if (display_putc_pos == 1)
+ display_buf[display_putc_pos] = display_char2seg7(c);
+
+ return c;
+}
+
+/*
+ * Flush current symbol to the LED display hardware
+ */
+static inline void display_flush(void)
+{
+ u32 val = display_buf[display_out_pos];
+
+ val |= (val << 8) | (val << 16) | (val << 24);
+ out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
+}
+
+/*
+ * Output contents of the software display buffer to the LED display every 0.5s
+ */
+void board_show_activity(ulong timestamp)
+{
+ static ulong last;
+ static u8 once;
+
+ if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
+ display_flush();
+ display_out_pos ^= 1;
+ last = timestamp;
+ once = 1;
+ }
+}
+
+/*
+ * Empty fake function
+ */
+void show_activity(int arg)
+{
+}
+#endif
+#if defined (CONFIG_SHOW_BOOT_PROGRESS)
+static int a4m072_status2code(int status, char *buf)
+{
+ char c = 0;
+
+ if (((status > 0) && (status <= 8)) ||
+ ((status >= 100) && (status <= 108)) ||
+ ((status < 0) && (status >= -9)) ||
+ (status == -100) || (status == -101) ||
+ ((status <= -103) && (status >= -113))) {
+ c = '5';
+ } else if (((status >= 9) && (status <= 14)) ||
+ ((status >= 120) && (status <= 123)) ||
+ ((status >= 125) && (status <= 129)) ||
+ ((status >= -13) && (status <= -10)) ||
+ (status == -120) || (status == -122) ||
+ ((status <= -124) && (status >= -127)) ||
+ (status == -129)) {
+ c = '8';
+ } else if (status == 15) {
+ c = '9';
+ } else if ((status <= -30) && (status >= -32)) {
+ c = 'A';
+ } else if (((status <= -35) && (status >= -40)) ||
+ ((status <= -42) && (status >= -51)) ||
+ ((status <= -53) && (status >= -58)) ||
+ (status == -64) ||
+ ((status <= -80) && (status >= -83)) ||
+ (status == -130) || (status == -140) ||
+ (status == -150)) {
+ c = 'B';
+ }
+
+ if (c == 0)
+ return -EINVAL;
+
+ buf[0] = (status < 0) ? '-' : c;
+ buf[1] = c;
+
+ return 0;
+}
+
+void show_boot_progress(int status)
+{
+ char buf[2];
+
+ if (a4m072_status2code(status, buf) < 0)
+ return;
+
+ display_putc(buf[0]);
+ display_putc(buf[1]);
+ display_set(DISPLAY_HOME);
+ display_out_pos = 0; /* reset output position */
+
+ /* we want to flush status 15 now */
+ if (status == BOOTSTAGE_ID_RUN_OS)
+ display_flush();
+}
+#endif
diff --git a/board/a4m072/mt46v32m16.h b/board/a4m072/mt46v32m16.h
new file mode 100644
index 0000000..c0a08a8
--- /dev/null
+++ b/board/a4m072/mt46v32m16.h
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40010000
+#define SDRAM_CONTROL 0x704f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/abilis/tb100/Kconfig b/board/abilis/tb100/Kconfig
new file mode 100644
index 0000000..904a92c
--- /dev/null
+++ b/board/abilis/tb100/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TB100
+
+config SYS_CPU
+ default "arc700"
+
+config SYS_BOARD
+ default "tb100"
+
+config SYS_VENDOR
+ default "abilis"
+
+config SYS_CONFIG_NAME
+ default "tb100"
+
+endif
diff --git a/board/abilis/tb100/MAINTAINERS b/board/abilis/tb100/MAINTAINERS
new file mode 100644
index 0000000..f08c3fe
--- /dev/null
+++ b/board/abilis/tb100/MAINTAINERS
@@ -0,0 +1,6 @@
+TB100 BOARD
+M: Alexey Brodkin <abrodkin@synopsys.com>
+S: Maintained
+F: board/abilis/tb100/
+F: include/configs/tb100.h
+F: configs/tb100_defconfig
diff --git a/board/abilis/tb100/Makefile b/board/abilis/tb100/Makefile
new file mode 100644
index 0000000..4f273b3
--- /dev/null
+++ b/board/abilis/tb100/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2014 Pierrick Hascoet, Abilis Systems
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += tb100.o
diff --git a/board/abilis/tb100/tb100.c b/board/abilis/tb100/tb100.c
new file mode 100644
index 0000000..ff3632f
--- /dev/null
+++ b/board/abilis/tb100/tb100.c
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2014 Pierrick Hascoet, Abilis Systems
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+void reset_cpu(ulong addr)
+{
+#define CRM_SWRESET 0xff101044
+ writel(0x1, (void *)CRM_SWRESET);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ if (designware_initialize(ETH0_BASE_ADDRESS, 0) >= 0)
+ return 1;
+
+ return 0;
+}
diff --git a/board/afeb9260/Kconfig b/board/afeb9260/Kconfig
new file mode 100644
index 0000000..6a5a931
--- /dev/null
+++ b/board/afeb9260/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AFEB9260
+
+config SYS_BOARD
+ default "afeb9260"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "afeb9260"
+
+endif
diff --git a/board/afeb9260/MAINTAINERS b/board/afeb9260/MAINTAINERS
new file mode 100644
index 0000000..337f302
--- /dev/null
+++ b/board/afeb9260/MAINTAINERS
@@ -0,0 +1,6 @@
+AFEB9260 BOARD
+M: Sergey Lapin <slapin@ossfans.org>
+S: Maintained
+F: board/afeb9260/
+F: include/configs/afeb9260.h
+F: configs/afeb9260_defconfig
diff --git a/board/afeb9260/Makefile b/board/afeb9260/Makefile
new file mode 100644
index 0000000..e0c3cd5
--- /dev/null
+++ b/board/afeb9260/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += afeb9260.o
+obj-y += partition.o
diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c
new file mode 100644
index 0000000..ea9575d
--- /dev/null
+++ b/board/afeb9260/afeb9260.c
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <netdev.h>
+#include <net.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void afeb9260_nand_hw_init(void)
+{
+ unsigned long csa;
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+ /* Assign CS3 to NAND/SmartMedia Interface */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+#ifdef CONFIG_MACB
+static void afeb9260_macb_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+
+ /* Enable EMAC clock */
+ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA17) => PHY normal mode (not Test mode)
+ * ERX0 (PA14) => PHY ADDR0
+ * ERX1 (PA15) => PHY ADDR1
+ * ERX2 (PA25) => PHY ADDR2
+ * ERX3 (PA26) => PHY ADDR3
+ * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ &pioa->pudr);
+
+ at91_phy_reset();
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ &pioa->puer);
+
+ at91_macb_hw_init();
+}
+#endif
+int board_early_init_f(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ /* Enable clocks for all PIOs */
+ writel((1 << ATMEL_ID_PIOA) |
+ (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOC),
+ &pmc->pcer);
+ return 0;
+}
+int board_init(void)
+{
+ /* arch number of AT91SAM9260EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ at91_seriald_hw_init();
+#ifdef CONFIG_CMD_NAND
+ afeb9260_nand_hw_init();
+#endif
+ at91_spi0_hw_init((1 << 0) | (1 << 1));
+#ifdef CONFIG_MACB
+ afeb9260_macb_hw_init();
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x01);
+#endif
+ return rc;
+}
diff --git a/board/afeb9260/config.mk b/board/afeb9260/config.mk
new file mode 100644
index 0000000..2077692
--- /dev/null
+++ b/board/afeb9260/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x21f00000
diff --git a/board/afeb9260/partition.c b/board/afeb9260/partition.c
new file mode 100644
index 0000000..6b71477
--- /dev/null
+++ b/board/afeb9260/partition.c
@@ -0,0 +1,21 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_CLEAR, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00041FFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
+};
diff --git a/board/ait/cam_enc_4xx/Kconfig b/board/ait/cam_enc_4xx/Kconfig
new file mode 100644
index 0000000..64e18f4
--- /dev/null
+++ b/board/ait/cam_enc_4xx/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CAM_ENC_4XX
+
+config SYS_BOARD
+ default "cam_enc_4xx"
+
+config SYS_VENDOR
+ default "ait"
+
+config SYS_CONFIG_NAME
+ default "cam_enc_4xx"
+
+endif
diff --git a/board/ait/cam_enc_4xx/MAINTAINERS b/board/ait/cam_enc_4xx/MAINTAINERS
new file mode 100644
index 0000000..d6477c6
--- /dev/null
+++ b/board/ait/cam_enc_4xx/MAINTAINERS
@@ -0,0 +1,6 @@
+CAM_ENC_4XX BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: board/ait/cam_enc_4xx/
+F: include/configs/cam_enc_4xx.h
+F: configs/cam_enc_4xx_defconfig
diff --git a/board/ait/cam_enc_4xx/Makefile b/board/ait/cam_enc_4xx/Makefile
new file mode 100644
index 0000000..0d03ce0
--- /dev/null
+++ b/board/ait/cam_enc_4xx/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cam_enc_4xx.o
diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c
new file mode 100644
index 0000000..290dc19
--- /dev/null
+++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c
@@ -0,0 +1,1106 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cli.h>
+#include <errno.h>
+#include <linux/mtd/nand.h>
+#include <nand.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/davinci_misc.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SPL_BUILD
+static struct davinci_timer *timer =
+ (struct davinci_timer *)DAVINCI_TIMER3_BASE;
+
+static unsigned long get_timer_val(void)
+{
+ unsigned long now = readl(&timer->tim34);
+
+ return now;
+}
+
+static int timer_running(void)
+{
+ return readl(&timer->tcr) &
+ (DV_TIMER_TCR_ENAMODE_MASK << DV_TIMER_TCR_ENAMODE34_SHIFT);
+}
+
+static void stop_timer(void)
+{
+ writel(0x0, &timer->tcr);
+ return;
+}
+
+int checkboard(void)
+{
+ printf("Board: AIT CAM ENC 4XX\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+static int cam_enc_4xx_check_network(void)
+{
+ char *s;
+
+ s = getenv("ethaddr");
+ if (!s)
+ return -EINVAL;
+
+ if (!is_valid_ether_addr((const u8 *)s))
+ return -EINVAL;
+
+ s = getenv("ipaddr");
+ if (!s)
+ return -EINVAL;
+
+ s = getenv("netmask");
+ if (!s)
+ return -EINVAL;
+
+ s = getenv("serverip");
+ if (!s)
+ return -EINVAL;
+
+ s = getenv("gatewayip");
+ if (!s)
+ return -EINVAL;
+
+ return 0;
+}
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ ret = cam_enc_4xx_check_network();
+ if (ret)
+ return ret;
+
+ davinci_emac_initialize();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+static int
+davinci_std_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ struct nand_chip *this = mtd->priv;
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ uint8_t *p = buf;
+ uint8_t *oob = chip->oob_poi;
+
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
+
+ chip->read_buf(mtd, oob, mtd->oobsize);
+
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page & this->pagemask);
+
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ int stat;
+
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ chip->read_buf(mtd, p, eccsize);
+ chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
+
+ if (chip->ecc.prepad)
+ oob += chip->ecc.prepad;
+
+ stat = chip->ecc.correct(mtd, p, oob, NULL);
+
+ if (stat == -1)
+ mtd->ecc_stats.failed++;
+ else
+ mtd->ecc_stats.corrected += stat;
+
+ oob += eccbytes;
+
+ if (chip->ecc.postpad)
+ oob += chip->ecc.postpad;
+ }
+
+ /* Calculate remaining oob bytes */
+ i = mtd->oobsize - (oob - chip->oob_poi);
+ if (i)
+ chip->read_buf(mtd, oob, i);
+
+ return 0;
+}
+
+static int davinci_std_write_page_syndrome(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf,
+ int oob_required)
+{
+ unsigned char davinci_ecc_buf[NAND_MAX_OOBSIZE];
+ struct nand_chip *this = mtd->priv;
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+ int offset = 0;
+ const uint8_t *p = buf;
+ uint8_t *oob = chip->oob_poi;
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+ chip->write_buf(mtd, p, eccsize);
+
+ /* Calculate ECC without prepad */
+ chip->ecc.calculate(mtd, p, oob + chip->ecc.prepad);
+
+ if (chip->ecc.prepad) {
+ offset = (chip->ecc.steps - eccsteps) * chunk;
+ memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.prepad);
+ oob += chip->ecc.prepad;
+ }
+
+ offset = ((chip->ecc.steps - eccsteps) * chunk) +
+ chip->ecc.prepad;
+ memcpy(&davinci_ecc_buf[offset], oob, eccbytes);
+ oob += eccbytes;
+
+ if (chip->ecc.postpad) {
+ offset = ((chip->ecc.steps - eccsteps) * chunk) +
+ chip->ecc.prepad + eccbytes;
+ memcpy(&davinci_ecc_buf[offset], oob,
+ chip->ecc.postpad);
+ oob += chip->ecc.postpad;
+ }
+ }
+
+ /*
+ * Write the sparebytes into the page once
+ * all eccsteps have been covered
+ */
+ for (i = 0; i < mtd->oobsize; i++)
+ writeb(davinci_ecc_buf[i], this->IO_ADDR_W);
+
+ /* Calculate remaining oob bytes */
+ i = mtd->oobsize - (oob - chip->oob_poi);
+ if (i)
+ chip->write_buf(mtd, oob, i);
+ return 0;
+}
+
+static int davinci_std_write_oob_syndrome(struct mtd_info *mtd,
+ struct nand_chip *chip, int page)
+{
+ int pos, status = 0;
+ const uint8_t *bufpoi = chip->oob_poi;
+
+ pos = mtd->writesize;
+
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
+
+ chip->write_buf(mtd, bufpoi, mtd->oobsize);
+
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+ status = chip->waitfunc(mtd, chip);
+
+ return status & NAND_STATUS_FAIL ? -1 : 0;
+}
+
+static int davinci_std_read_oob_syndrome(struct mtd_info *mtd,
+ struct nand_chip *chip, int page)
+{
+ struct nand_chip *this = mtd->priv;
+ uint8_t *buf = chip->oob_poi;
+ uint8_t *bufpoi = buf;
+
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
+
+ chip->read_buf(mtd, bufpoi, mtd->oobsize);
+
+ return 0;
+}
+
+static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *this = mtd->priv;
+ unsigned long wbase = (unsigned long) this->IO_ADDR_W;
+ unsigned long rbase = (unsigned long) this->IO_ADDR_R;
+
+ if (chip == 1) {
+ __set_bit(14, &wbase);
+ __set_bit(14, &rbase);
+ } else {
+ __clear_bit(14, &wbase);
+ __clear_bit(14, &rbase);
+ }
+ this->IO_ADDR_W = (void *)wbase;
+ this->IO_ADDR_R = (void *)rbase;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+ nand->select_chip = nand_dm365evm_select_chip;
+
+ return 0;
+}
+
+struct nand_ecc_ctrl org_ecc;
+static int notsaved = 1;
+
+static int nand_switch_hw_func(int mode)
+{
+ struct nand_chip *nand;
+ struct mtd_info *mtd;
+
+ if (nand_curr_device < 0 ||
+ nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
+ !nand_info[nand_curr_device].name) {
+ printf("Error: Can't switch hw functions," \
+ " no devices available\n");
+ return -1;
+ }
+
+ mtd = &nand_info[nand_curr_device];
+ nand = mtd->priv;
+
+ if (mode == 0) {
+ if (notsaved == 0) {
+ printf("switching to uboot hw functions.\n");
+ memcpy(&nand->ecc, &org_ecc,
+ sizeof(struct nand_ecc_ctrl));
+ }
+ } else {
+ /* RBL */
+ printf("switching to RBL hw functions.\n");
+ if (notsaved == 1) {
+ memcpy(&org_ecc, &nand->ecc,
+ sizeof(struct nand_ecc_ctrl));
+ notsaved = 0;
+ }
+ nand->ecc.mode = NAND_ECC_HW_SYNDROME;
+ nand->ecc.prepad = 6;
+ nand->ecc.read_page = davinci_std_read_page_syndrome;
+ nand->ecc.write_page = davinci_std_write_page_syndrome;
+ nand->ecc.read_oob = davinci_std_read_oob_syndrome;
+ nand->ecc.write_oob = davinci_std_write_oob_syndrome;
+ }
+ return mode;
+}
+
+static int hwmode;
+
+static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (argc != 2)
+ goto usage;
+ if (strncmp(argv[1], "rbl", 2) == 0)
+ hwmode = nand_switch_hw_func(1);
+ else if (strncmp(argv[1], "uboot", 2) == 0)
+ hwmode = nand_switch_hw_func(0);
+ else
+ goto usage;
+
+ return 0;
+
+usage:
+ printf("Usage: nandrbl %s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ nandrbl, 2, 1, do_switch_ecc,
+ "switch between rbl/uboot NAND ECC calculation algorithm",
+ "[rbl/uboot] - Switch between rbl/uboot NAND ECC algorithm"
+);
+
+
+#endif /* #ifdef CONFIG_NAND_DAVINCI */
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .input_clk = 121500000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int err;
+
+ /* Add slot-0 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd0);
+
+ return err;
+}
+#endif
+
+int board_late_init(void)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank45;
+
+ /* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running */
+ while ((get_timer_val() < CONFIG_AIT_TIMER_TIMEOUT) &&
+ timer_running())
+ ;
+
+ /* 1 sec reached -> stop timer, clear all LED */
+ stop_timer();
+ clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+ return 0;
+}
+
+void reset_phy(void)
+{
+ char *name = "GENERIC @ 0x00";
+
+ /* reset the phy */
+ miiphy_reset(name, 0x0);
+}
+
+#else /* #ifndef CONFIG_SPL_BUILD */
+static void cam_enc_4xx_set_all_led(void)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank45;
+
+ setbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+}
+
+/*
+ * TIMER 0 is used for tick
+ */
+static struct davinci_timer *timer =
+ (struct davinci_timer *)DAVINCI_TIMER3_BASE;
+
+#define TIMER_LOAD_VAL 0xffffffff
+#define TIM_CLK_DIV 16
+
+static int cam_enc_4xx_timer_init(void)
+{
+ /* We are using timer34 in unchained 32-bit mode, full speed */
+ writel(0x0, &timer->tcr);
+ writel(0x0, &timer->tgcr);
+ writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
+ writel(0x0, &timer->tim34);
+ writel(TIMER_LOAD_VAL, &timer->prd34);
+ writel(2 << 22, &timer->tcr);
+ return 0;
+}
+
+void board_gpio_init(void)
+{
+ struct davinci_gpio *gpio;
+
+ cam_enc_4xx_set_all_led();
+ cam_enc_4xx_timer_init();
+ gpio = davinci_gpio_bank01;
+ clrbits_le32(&gpio->dir, ~0xfdfffffe);
+ /* clear LED D14 = GPIO25 */
+ clrbits_le32(&gpio->out_data, 0x02000000);
+ gpio = davinci_gpio_bank23;
+ clrbits_le32(&gpio->dir, ~0x5ff0afef);
+ /* set GPIO61 to 1 -> intern UART0 as Console */
+ setbits_le32(&gpio->out_data, 0x20000000);
+ /*
+ * PHY out of reset GIO 50 = 1
+ * NAND WP off GIO 51 = 1
+ */
+ setbits_le32(&gpio->out_data, 0x000c0004);
+ gpio = davinci_gpio_bank45;
+ clrbits_le32(&gpio->dir, ~(0xdb2fffff) | CONFIG_CAM_ENC_LED_MASK);
+ /*
+ * clear LED:
+ * D17 = GPIO86
+ * D11 = GPIO87
+ * GPIO88
+ * GPIO89
+ * D13 = GPIO90
+ * GPIO91
+ */
+ clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
+ gpio = davinci_gpio_bank67;
+ clrbits_le32(&gpio->dir, ~0x000007ff);
+}
+
+/*
+ * functions for the post memory test.
+ */
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ *vstart = CONFIG_SYS_SDRAM_BASE;
+ *size = PHYS_SDRAM_1_SIZE;
+ *phys_offset = 0;
+ return 0;
+}
+
+void arch_memory_failure_handle(void)
+{
+ cam_enc_4xx_set_all_led();
+ puts("mem failure\n");
+ while (1)
+ ;
+}
+#endif
+#if defined(CONFIG_MENU)
+#include "menu.h"
+
+#define MENU_EXIT -1
+#define MENU_EXIT_BOOTCMD -2
+#define MENU_STAY 0
+#define MENU_MAIN 1
+#define MENU_UPDATE 2
+#define MENU_NETWORK 3
+#define MENU_LOAD 4
+
+static int menu_start;
+
+#define FIT_SUBTYPE_UNKNOWN 0
+#define FIT_SUBTYPE_UBL_HEADER 1
+#define FIT_SUBTYPE_SPL_IMAGE 2
+#define FIT_SUBTYPE_UBOOT_IMAGE 3
+#define FIT_SUBTYPE_DF_ENV_IMAGE 4
+#define FIT_SUBTYPE_RAMDISK_IMAGE 5
+
+struct fit_images_info {
+ u_int8_t type;
+ int subtype;
+ char desc[200];
+ const void *data;
+ size_t size;
+};
+
+static struct fit_images_info imgs[10];
+
+struct menu_display {
+ char title[50];
+ int timeout; /* in sec */
+ int id; /* MENU_* */
+ char **menulist;
+ int (*menu_evaluate)(char *choice);
+};
+
+char *menu_main[] = {
+ "(1) Boot",
+ "(2) Update Software",
+ "(3) Reset to default setting and boot",
+ "(4) Enter U-Boot console",
+ NULL
+};
+
+char *menu_update[] = {
+ "(1) Network settings",
+ "(2) load image",
+ "(3) back to main",
+ NULL
+};
+
+char *menu_load[] = {
+ "(1) install image",
+ "(2) cancel",
+ NULL
+};
+
+char *menu_network[] = {
+ "(1) ipaddr ",
+ "(2) netmask ",
+ "(3) serverip ",
+ "(4) gatewayip",
+ "(5) tftp image name",
+ "(6) back to update software",
+ NULL
+};
+
+static void ait_menu_print(void *data)
+{
+ printf("%s\n", (char *)data);
+ return;
+}
+
+static char *menu_handle(struct menu_display *display)
+{
+ struct menu *m;
+ int i;
+ void *choice = NULL;
+ char key[2];
+ int ret;
+ char *s;
+ char temp[6][200];
+
+ m = menu_create(display->title, display->timeout, 1, ait_menu_print,
+ NULL, NULL);
+
+ for (i = 0; display->menulist[i]; i++) {
+ sprintf(key, "%d", i + 1);
+ if (display->id == MENU_NETWORK) {
+ switch (i) {
+ case 0:
+ s = getenv("ipaddr");
+ break;
+ case 1:
+ s = getenv("netmask");
+ break;
+ case 2:
+ s = getenv("serverip");
+ break;
+ case 3:
+ s = getenv("gatewayip");
+ break;
+ case 4:
+ s = getenv("img_file");
+ break;
+ default:
+ s = NULL;
+ break;
+ }
+ if (s) {
+ sprintf(temp[i], "%s: %s",
+ display->menulist[i], s);
+ ret = menu_item_add(m, key, temp[i]);
+ } else {
+ ret = menu_item_add(m, key,
+ display->menulist[i]);
+ }
+ } else {
+ ret = menu_item_add(m, key, display->menulist[i]);
+ }
+
+ if (ret != 1) {
+ printf("failed to add item!");
+ menu_destroy(m);
+ return NULL;
+ }
+ }
+ sprintf(key, "%d", 1);
+ menu_default_set(m, key);
+
+ if (menu_get_choice(m, &choice) != 1)
+ debug("Problem picking a choice!\n");
+
+ menu_destroy(m);
+
+ return choice;
+}
+
+static int ait_menu_show(struct menu_display *display, int bootdelay)
+{
+ int end = MENU_STAY;
+ char *choice;
+
+ if ((menu_start == 0) && (display->id == MENU_MAIN))
+ display->timeout = bootdelay;
+ else
+ display->timeout = 0;
+
+ while (end == MENU_STAY) {
+ choice = menu_handle(display);
+ if (choice)
+ end = display->menu_evaluate(choice);
+
+ if (end == display->id)
+ end = MENU_STAY;
+ if (display->id == MENU_MAIN) {
+ if (menu_start == 0)
+ end = MENU_EXIT_BOOTCMD;
+ else
+ display->timeout = 0;
+ }
+ }
+ return end;
+}
+
+static int ait_writeublheader(void)
+{
+ char s[20];
+ unsigned long i;
+ int ret;
+
+ for (i = CONFIG_SYS_NAND_BLOCK_SIZE;
+ i < CONFIG_SYS_NAND_U_BOOT_OFFS;
+ i += CONFIG_SYS_NAND_BLOCK_SIZE) {
+ sprintf(s, "%lx", i);
+ ret = setenv("header_addr", s);
+ if (ret == 0)
+ ret = run_command("run img_writeheader", 0);
+ if (ret != 0)
+ break;
+ }
+ return ret;
+}
+
+static int ait_menu_install_images(void)
+{
+ int ret = 0;
+ int count = 0;
+ char s[100];
+ char *t;
+
+ /*
+ * possible image types:
+ * FIT_SUBTYPE_UNKNOWN
+ * FIT_SUBTYPE_UBL_HEADER
+ * FIT_SUBTYPE_SPL_IMAGE
+ * FIT_SUBTYPE_UBOOT_IMAGE
+ * FIT_SUBTYPE_DF_ENV_IMAGE
+ * FIT_SUBTYPE_RAMDISK_IMAGE
+ *
+ * use Envvariables:
+ * img_addr_r: image start addr
+ * header_addr: addr where to write to UBL header
+ * img_writeheader: write ubl header to nand
+ * img_writespl: write spl to nand
+ * img_writeuboot: write uboot to nand
+ * img_writedfenv: write default environment to ubi volume
+ * img_volume: which ubi volume should be updated with img_writeramdisk
+ * filesize: size of data for updating ubi volume
+ * img_writeramdisk: write ramdisk to ubi volume
+ */
+
+ while (imgs[count].type != IH_TYPE_INVALID) {
+ printf("Installing %s\n",
+ genimg_get_type_name(imgs[count].type));
+ sprintf(s, "%p", imgs[count].data);
+ setenv("img_addr_r", s);
+ sprintf(s, "%lx", (unsigned long)imgs[count].size);
+ setenv("filesize", s);
+ switch (imgs[count].subtype) {
+ case FIT_SUBTYPE_DF_ENV_IMAGE:
+ ret = run_command("run img_writedfenv", 0);
+ break;
+ case FIT_SUBTYPE_RAMDISK_IMAGE:
+ t = getenv("img_volume");
+ if (!t) {
+ ret = setenv("img_volume", "rootfs1");
+ } else {
+ /* switch to other volume */
+ if (strncmp(t, "rootfs1", 7) == 0)
+ ret = setenv("img_volume", "rootfs2");
+ else
+ ret = setenv("img_volume", "rootfs1");
+ }
+ if (ret != 0)
+ break;
+
+ ret = run_command("run img_writeramdisk", 0);
+ break;
+ case FIT_SUBTYPE_SPL_IMAGE:
+ ret = run_command("run img_writespl", 0);
+ break;
+ case FIT_SUBTYPE_UBL_HEADER:
+ ret = ait_writeublheader();
+ break;
+ case FIT_SUBTYPE_UBOOT_IMAGE:
+ ret = run_command("run img_writeuboot", 0);
+ break;
+ default:
+ /* not supported type */
+ break;
+ }
+ count++;
+ }
+ /* now save dvn_* and img_volume env vars to new values */
+ if (ret == 0) {
+ t = getenv("x_dvn_boot_vers");
+ if (t)
+ setenv("dvn_boot_vers", t);
+
+ t = getenv("x_dvn_app_vers");
+ if (t)
+ setenv("dvn_boot_vers", t);
+
+ setenv("x_dvn_boot_vers", NULL);
+ setenv("x_dvn_app_vers", NULL);
+ ret = run_command("run savenewvers", 0);
+ }
+
+ return ret;
+}
+
+static int ait_menu_evaluate_load(char *choice)
+{
+ if (!choice)
+ return -1;
+
+ switch (choice[1]) {
+ case '1':
+ /* install image */
+ ait_menu_install_images();
+ break;
+ case '2':
+ /* cancel, back to main */
+ setenv("x_dvn_boot_vers", NULL);
+ setenv("x_dvn_app_vers", NULL);
+ break;
+ }
+
+ return MENU_MAIN;
+}
+
+struct menu_display ait_load = {
+ .title = "AIT load image",
+ .timeout = 0,
+ .id = MENU_LOAD,
+ .menulist = menu_load,
+ .menu_evaluate = ait_menu_evaluate_load,
+};
+
+static void ait_menu_read_env(char *name)
+{
+ char output[CONFIG_SYS_CBSIZE];
+ char cbuf[CONFIG_SYS_CBSIZE];
+ int readret;
+ int ret;
+
+ sprintf(output, "%s old: %s value: ", name, getenv(name));
+ memset(cbuf, 0, CONFIG_SYS_CBSIZE);
+ readret = cli_readline_into_buffer(output, cbuf, 0);
+
+ if (readret >= 0) {
+ ret = setenv(name, cbuf);
+ if (ret) {
+ printf("Error setting %s\n", name);
+ return;
+ }
+ }
+ return;
+}
+
+static int ait_menu_evaluate_network(char *choice)
+{
+ if (!choice)
+ return MENU_MAIN;
+
+ switch (choice[1]) {
+ case '1':
+ ait_menu_read_env("ipaddr");
+ break;
+ case '2':
+ ait_menu_read_env("netmask");
+ break;
+ case '3':
+ ait_menu_read_env("serverip");
+ break;
+ case '4':
+ ait_menu_read_env("gatewayip");
+ break;
+ case '5':
+ ait_menu_read_env("img_file");
+ break;
+ case '6':
+ return MENU_UPDATE;
+ break;
+ }
+
+ return MENU_STAY;
+}
+
+struct menu_display ait_network = {
+ .title = "AIT network settings",
+ .timeout = 0,
+ .id = MENU_NETWORK,
+ .menulist = menu_network,
+ .menu_evaluate = ait_menu_evaluate_network,
+};
+
+static int fit_get_subtype(const void *fit, int noffset, char **subtype)
+{
+ int len;
+
+ *subtype = (char *)fdt_getprop(fit, noffset, "subtype", &len);
+ if (*subtype == NULL)
+ return -1;
+
+ return 0;
+}
+
+static int ait_subtype_nr(char *subtype)
+{
+ int ret = FIT_SUBTYPE_UNKNOWN;
+
+ if (!strncmp("ublheader", subtype, strlen("ublheader")))
+ return FIT_SUBTYPE_UBL_HEADER;
+ if (!strncmp("splimage", subtype, strlen("splimage")))
+ return FIT_SUBTYPE_SPL_IMAGE;
+ if (!strncmp("ubootimage", subtype, strlen("ubootimage")))
+ return FIT_SUBTYPE_UBOOT_IMAGE;
+ if (!strncmp("dfenvimage", subtype, strlen("dfenvimage")))
+ return FIT_SUBTYPE_DF_ENV_IMAGE;
+
+ return ret;
+}
+
+static int ait_menu_check_image(void)
+{
+ char *s;
+ unsigned long fit_addr;
+ void *addr;
+ int format;
+ char *desc;
+ char *subtype;
+ int images_noffset;
+ int noffset;
+ int ndepth;
+ int count = 0;
+ int ret;
+ int i;
+ int found_uboot = -1;
+ int found_ramdisk = -1;
+
+ memset(imgs, 0, sizeof(imgs));
+ s = getenv("fit_addr_r");
+ fit_addr = s ? (unsigned long)simple_strtol(s, NULL, 16) : \
+ CONFIG_BOARD_IMG_ADDR_R;
+
+ addr = (void *)fit_addr;
+ /* check if it is a FIT image */
+ format = genimg_get_format(addr);
+ if (format != IMAGE_FORMAT_FIT)
+ return -EINVAL;
+
+ if (!fit_check_format(addr))
+ return -EINVAL;
+
+ /* print the FIT description */
+ ret = fit_get_desc(addr, 0, &desc);
+ printf("FIT description: ");
+ if (ret)
+ printf("unavailable\n");
+ else
+ printf("%s\n", desc);
+
+ /* find images */
+ images_noffset = fdt_path_offset(addr, FIT_IMAGES_PATH);
+ if (images_noffset < 0) {
+ printf("Can't find images parent node '%s' (%s)\n",
+ FIT_IMAGES_PATH, fdt_strerror(images_noffset));
+ return -EINVAL;
+ }
+
+ /* Process its subnodes, print out component images details */
+ for (ndepth = 0, count = 0,
+ noffset = fdt_next_node(addr, images_noffset, &ndepth);
+ (noffset >= 0) && (ndepth > 0);
+ noffset = fdt_next_node(addr, noffset, &ndepth)) {
+ if (ndepth == 1) {
+ /*
+ * Direct child node of the images parent node,
+ * i.e. component image node.
+ */
+ printf("Image %u (%s)\n", count,
+ fit_get_name(addr, noffset, NULL));
+
+ fit_image_print(addr, noffset, "");
+
+ fit_image_get_type(addr, noffset,
+ &imgs[count].type);
+ /* Mandatory properties */
+ ret = fit_get_desc(addr, noffset, &desc);
+ printf("Description: ");
+ if (ret)
+ printf("unavailable\n");
+ else
+ printf("%s\n", desc);
+
+ ret = fit_get_subtype(addr, noffset, &subtype);
+ printf("Subtype: ");
+ if (ret) {
+ printf("unavailable\n");
+ } else {
+ imgs[count].subtype = ait_subtype_nr(subtype);
+ printf("%s %d\n", subtype,
+ imgs[count].subtype);
+ }
+
+ sprintf(imgs[count].desc, "%s", desc);
+
+ ret = fit_image_get_data(addr, noffset,
+ &imgs[count].data,
+ &imgs[count].size);
+
+ printf("Data Size: ");
+ if (ret)
+ printf("unavailable\n");
+ else
+ genimg_print_size(imgs[count].size);
+ printf("Data @ %p\n", imgs[count].data);
+ count++;
+ }
+ }
+
+ for (i = 0; i < count; i++) {
+ if (imgs[i].subtype == FIT_SUBTYPE_UBOOT_IMAGE)
+ found_uboot = i;
+ if (imgs[i].type == IH_TYPE_RAMDISK) {
+ found_ramdisk = i;
+ imgs[i].subtype = FIT_SUBTYPE_RAMDISK_IMAGE;
+ }
+ }
+
+ /* dvn_* env var update, if the FIT descriptors are different */
+ if (found_uboot >= 0) {
+ s = getenv("dvn_boot_vers");
+ if (s) {
+ ret = strcmp(s, imgs[found_uboot].desc);
+ if (ret != 0) {
+ setenv("x_dvn_boot_vers",
+ imgs[found_uboot].desc);
+ } else {
+ found_uboot = -1;
+ printf("no new uboot version\n");
+ }
+ } else {
+ setenv("dvn_boot_vers", imgs[found_uboot].desc);
+ }
+ }
+ if (found_ramdisk >= 0) {
+ s = getenv("dvn_app_vers");
+ if (s) {
+ ret = strcmp(s, imgs[found_ramdisk].desc);
+ if (ret != 0) {
+ setenv("x_dvn_app_vers",
+ imgs[found_ramdisk].desc);
+ } else {
+ found_ramdisk = -1;
+ printf("no new ramdisk version\n");
+ }
+ } else {
+ setenv("dvn_app_vers", imgs[found_ramdisk].desc);
+ }
+ }
+ if ((found_uboot == -1) && (found_ramdisk == -1))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int ait_menu_evaluate_update(char *choice)
+{
+ int ret;
+
+ if (!choice)
+ return MENU_MAIN;
+
+ switch (choice[1]) {
+ case '1':
+ return ait_menu_show(&ait_network, 0);
+ break;
+ case '2':
+ /* load image */
+ ret = run_command("run load_img", 0);
+ printf("ret: %d\n", ret);
+ if (ret)
+ return MENU_UPDATE;
+
+ ret = ait_menu_check_image();
+ if (ret)
+ return MENU_UPDATE;
+
+ return ait_menu_show(&ait_load, 0);
+ break;
+ case '3':
+ return MENU_MAIN;
+ break;
+
+ }
+
+ return MENU_MAIN;
+}
+
+struct menu_display ait_update = {
+ .title = "AIT Update Software",
+ .timeout = 0,
+ .id = MENU_UPDATE,
+ .menulist = menu_update,
+ .menu_evaluate = ait_menu_evaluate_update,
+};
+
+static int ait_menu_evaluate_main(char *choice)
+{
+ if (!choice)
+ return MENU_STAY;
+
+ menu_start = 1;
+ switch (choice[1]) {
+ case '1':
+ /* run bootcmd */
+ return MENU_EXIT_BOOTCMD;
+ break;
+ case '2':
+ return ait_menu_show(&ait_update, 0);
+ break;
+ case '3':
+ /* reset to default settings */
+ setenv("app_reset", "yes");
+ return MENU_EXIT_BOOTCMD;
+ break;
+ case '4':
+ /* u-boot shell */
+ return MENU_EXIT;
+ break;
+ }
+
+ return MENU_EXIT;
+}
+
+struct menu_display ait_main = {
+ .title = "AIT Main",
+ .timeout = CONFIG_BOOTDELAY,
+ .id = MENU_MAIN,
+ .menulist = menu_main,
+ .menu_evaluate = ait_menu_evaluate_main,
+};
+
+int menu_show(int bootdelay)
+{
+ int ret;
+
+ run_command("run saveparms", 0);
+ ret = ait_menu_show(&ait_main, bootdelay);
+ run_command("run restoreparms", 0);
+
+ if (ret == MENU_EXIT_BOOTCMD)
+ return 0;
+
+ return MENU_EXIT;
+}
+
+void menu_display_statusline(struct menu *m)
+{
+ char *s1, *s2;
+
+ s1 = getenv("x_dvn_boot_vers");
+ if (!s1)
+ s1 = getenv("dvn_boot_vers");
+
+ s2 = getenv("x_dvn_app_vers");
+ if (!s2)
+ s2 = getenv("dvn_app_vers");
+
+ printf("State: dvn_boot_vers: %s dvn_app_vers: %s\n", s1, s2);
+ return;
+}
+#endif
diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk
new file mode 100644
index 0000000..2022151
--- /dev/null
+++ b/board/ait/cam_enc_4xx/config.mk
@@ -0,0 +1,20 @@
+#
+# AIT cam_enc_4xx board
+# cam_enc_4xx board has 1 bank of 256 MB DDR RAM
+# Physical Address: 8000'0000 to 9000'0000
+#
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+UBL_CONFIG = $(srctree)/board/$(BOARDDIR)/ublimage.cfg
+ifndef CONFIG_SPL_BUILD
+ALL-y += u-boot.ubl
+else
+# as SPL_TEXT_BASE is not page-aligned, we need for some
+# linkers the -n flag (Do not page align data), to prevent
+# the following error message:
+# arm-linux-ld: u-boot-spl: Not enough room for program headers, try linking
+# with -N
+LDFLAGS_u-boot-spl += -n
+endif
diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds
new file mode 100644
index 0000000..f5c19df
--- /dev/null
+++ b/board/ait/cam_enc_4xx/u-boot-spl.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = CONFIG_SPL_TEXT_BASE;
+
+ . = ALIGN(4);
+ .text :
+ {
+ __start = .;
+ *(.vectors)
+ arch/arm/cpu/arm926ejs/start.o (.text*)
+ *(.text*)
+ } >.sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+ . = ALIGN(4);
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ } >.sram
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } >.sram
+
+ __image_copy_end = .;
+
+ .end :
+ {
+ *(.__end)
+ }
+}
diff --git a/board/ait/cam_enc_4xx/ublimage.cfg b/board/ait/cam_enc_4xx/ublimage.cfg
new file mode 100644
index 0000000..d4fe705
--- /dev/null
+++ b/board/ait/cam_enc_4xx/ublimage.cfg
@@ -0,0 +1,31 @@
+#
+# (C Copyright 2011
+# Heiko Schocher DENX Software Engineering hs@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.ublimage for more details about how-to configure
+# and create ublimage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# UBL special mode : one of
+# safe (the board has no nand neither onenand)
+MODE safe
+
+# Entry point address for the user bootloader (absolute address)
+# nand spl TEXT_BASE = 0x20 !!
+ENTRY 0x00000020
+
+# Number of pages (size of user bootloader in number of pages)
+# @ nand spl 6 pages
+PAGES 6
+
+# Block number where user bootloader is present
+START_BLOCK 0
+
+# Page number where user bootloader is present
+# Page 0 is always UBL header
+START_PAGE 0
+
+LD_ADDR 0x20
diff --git a/board/alphaproject/ap_sh4a_4a/Kconfig b/board/alphaproject/ap_sh4a_4a/Kconfig
new file mode 100644
index 0000000..4692851
--- /dev/null
+++ b/board/alphaproject/ap_sh4a_4a/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AP_SH4A_4A
+
+config SYS_BOARD
+ default "ap_sh4a_4a"
+
+config SYS_VENDOR
+ default "alphaproject"
+
+config SYS_CONFIG_NAME
+ default "ap_sh4a_4a"
+
+endif
diff --git a/board/alphaproject/ap_sh4a_4a/MAINTAINERS b/board/alphaproject/ap_sh4a_4a/MAINTAINERS
new file mode 100644
index 0000000..f24489d
--- /dev/null
+++ b/board/alphaproject/ap_sh4a_4a/MAINTAINERS
@@ -0,0 +1,7 @@
+AP_SH4A_4A BOARD
+M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S: Maintained
+F: board/alphaproject/ap_sh4a_4a/
+F: include/configs/ap_sh4a_4a.h
+F: configs/ap_sh4a_4a_defconfig
diff --git a/board/alphaproject/ap_sh4a_4a/Makefile b/board/alphaproject/ap_sh4a_4a/Makefile
new file mode 100644
index 0000000..486d0ac
--- /dev/null
+++ b/board/alphaproject/ap_sh4a_4a/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := ap_sh4a_4a.o
+obj-y += lowlevel_init.o
diff --git a/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c
new file mode 100644
index 0000000..b81a68d
--- /dev/null
+++ b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <netdev.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MODEMR (0xFFCC0020)
+#define MODEMR_MASK (0x6)
+#define MODEMR_533MHZ (0x2)
+
+int checkboard(void)
+{
+ u32 r = readl(MODEMR);
+ if ((r & MODEMR_MASK) & MODEMR_533MHZ)
+ puts("CPU Clock: 533MHz\n");
+ else
+ puts("CPU Clock: 400MHz\n");
+
+ puts("BOARD: Alpha Project. AP-SH4A-4A\n");
+ return 0;
+}
+
+#define MSTPSR1 (0xFFC80044)
+#define MSTPCR1 (0xFFC80034)
+#define MSTPSR1_GETHER (1 << 14)
+
+/* IPSR3 */
+#define ET0_ETXD0 (0x4 << 3)
+#define ET0_GTX_CLK_A (0x4 << 6)
+#define ET0_ETXD1_A (0x4 << 9)
+#define ET0_ETXD2_A (0x4 << 12)
+#define ET0_ETXD3_A (0x4 << 15)
+#define ET0_ETXD4 (0x3 << 18)
+#define ET0_ETXD5_A (0x5 << 21)
+#define ET0_ETXD6_A (0x5 << 24)
+#define ET0_ETXD7 (0x4 << 27)
+#define IPSR3_ETH_ENABLE \
+ (ET0_ETXD0 | ET0_GTX_CLK_A | ET0_ETXD1_A | ET0_ETXD2_A | \
+ ET0_ETXD3_A | ET0_ETXD4 | ET0_ETXD5_A | ET0_ETXD6_A | ET0_ETXD7)
+
+/* IPSR4 */
+#define ET0_ERXD7 (0x4)
+#define ET0_RX_DV (0x4 << 3)
+#define ET0_RX_ER (0x4 << 6)
+#define ET0_CRS (0x4 << 9)
+#define ET0_COL (0x4 << 12)
+#define ET0_MDC (0x4 << 15)
+#define ET0_MDIO_A (0x3 << 18)
+#define ET0_LINK_A (0x3 << 20)
+#define ET0_PHY_INT_A (0x3 << 24)
+
+#define IPSR4_ETH_ENABLE \
+ (ET0_ERXD7 | ET0_RX_DV | ET0_RX_ER | ET0_CRS | ET0_COL | \
+ ET0_MDC | ET0_MDIO_A | ET0_LINK_A | ET0_PHY_INT_A)
+
+/* IPSR8 */
+#define ET0_ERXD0 (0x4 << 20)
+#define ET0_ERXD1 (0x4 << 23)
+#define ET0_ERXD2_A (0x3 << 26)
+#define ET0_ERXD3_A (0x3 << 28)
+#define IPSR8_ETH_ENABLE \
+ (ET0_ERXD0 | ET0_ERXD1 | ET0_ERXD2_A | ET0_ERXD3_A)
+
+/* IPSR10 */
+#define RX4_D (0x1 << 22)
+#define TX4_D (0x1 << 23)
+#define IPSR10_SCIF_ENABLE (RX4_D | TX4_D)
+
+/* IPSR11 */
+#define ET0_ERXD4 (0x4 << 4)
+#define ET0_ERXD5 (0x4 << 7)
+#define ET0_ERXD6 (0x3 << 10)
+#define ET0_TX_EN (0x2 << 19)
+#define ET0_TX_ER (0x2 << 21)
+#define ET0_TX_CLK_A (0x4 << 23)
+#define ET0_RX_CLK_A (0x3 << 26)
+#define IPSR11_ETH_ENABLE \
+ (ET0_ERXD4 | ET0_ERXD5 | ET0_ERXD6 | ET0_TX_EN | ET0_TX_ER | \
+ ET0_TX_CLK_A | ET0_RX_CLK_A)
+
+#define GPSR1_INIT (0xFFFF7FFF)
+#define GPSR2_INIT (0x4005FEFF)
+#define GPSR3_INIT (0x2EFFFFFF)
+#define GPSR4_INIT (0xC7000000)
+
+int board_init(void)
+{
+ u32 data;
+
+ /* Set IPSR register */
+ data = readl(IPSR3);
+ data |= IPSR3_ETH_ENABLE;
+ writel(~data, PMMR);
+ writel(data, IPSR3);
+
+ data = readl(IPSR4);
+ data |= IPSR4_ETH_ENABLE;
+ writel(~data, PMMR);
+ writel(data, IPSR4);
+
+ data = readl(IPSR8);
+ data |= IPSR8_ETH_ENABLE;
+ writel(~data, PMMR);
+ writel(data, IPSR8);
+
+ data = readl(IPSR10);
+ data |= IPSR10_SCIF_ENABLE;
+ writel(~data, PMMR);
+ writel(data, IPSR10);
+
+ data = readl(IPSR11);
+ data |= IPSR11_ETH_ENABLE;
+ writel(~data, PMMR);
+ writel(data, IPSR11);
+
+ /* GPIO select */
+ data = GPSR1_INIT;
+ writel(~data, PMMR);
+ writel(data, GPSR1);
+
+ data = GPSR2_INIT;
+ writel(~data, PMMR);
+ writel(data, GPSR2);
+
+ data = GPSR3_INIT;
+ writel(~data, PMMR);
+ writel(data, GPSR3);
+
+ data = GPSR4_INIT;
+ writel(~data, PMMR);
+ writel(data, GPSR4);
+
+ data = 0x0;
+ writel(~data, PMMR);
+ writel(data, GPSR5);
+
+ /* mode select */
+ data = MODESEL2_INIT;
+ writel(~data, PMMR);
+ writel(data, MODESEL2);
+
+#if defined(CONFIG_SH_ETHER)
+ u32 r = readl(MSTPSR1);
+ if (r & MSTPSR1_GETHER)
+ writel((r & ~MSTPSR1_GETHER), MSTPCR1);
+#endif
+ return 0;
+}
+
+int board_late_init(void)
+{
+ u8 mac[6];
+
+ /* Read Mac Address and set*/
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
+
+ /* Read MAC address */
+ i2c_read(0x50, 0x0, 0, mac, 6);
+
+ if (is_valid_ether_addr(mac))
+ eth_setenv_enetaddr("ethaddr", mac);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+
+ return 0;
+}
diff --git a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
new file mode 100644
index 0000000..d5900a8
--- /dev/null
+++ b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
@@ -0,0 +1,450 @@
+/*
+ * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2011, 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+#include <asm/processor.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ /* WDT */
+ write32 WDTCSR_A, WDTCSR_D
+
+ /* MMU */
+ write32 MMUCR_A, MMUCR_D
+
+ write32 FRQCR2_A, FRQCR2_D
+ write32 FRQCR0_A, FRQCR0_D
+
+ write32 CS0CTRL_A, CS0CTRL_D
+ write32 CS1CTRL_A, CS1CTRL_D
+ write32 CS0CTRL2_A, CS0CTRL2_D
+
+ write32 CSPWCR0_A, CSPWCR0_D
+ write32 CSPWCR1_A, CSPWCR1_D
+ write32 CS1GDST_A, CS1GDST_D
+
+ # clock mode check
+ mov.l MODEMR, r1
+ mov.l @r1, r0
+ and #6, r0 /* Check 1 and 2 bit.*/
+ cmp/eq #2, r0 /* 0x02 is 533Mhz mode */
+ bt init_lbsc_533
+
+init_lbsc_400:
+
+ write32 CSWCR0_A, CSWCR0_D_400
+ write32 CSWCR1_A, CSWCR1_D
+
+ bra init_dbsc3_400_pad
+ nop
+
+ .align 2
+
+MODEMR: .long 0xFFCC0020
+WDTCSR_A: .long 0xFFCC0004
+WDTCSR_D: .long 0xA5000000
+MMUCR_A: .long 0xFF000010
+MMUCR_D: .long 0x00000004
+
+FRQCR2_A: .long 0xFFC80008
+FRQCR2_D: .long 0x00000000
+FRQCR0_A: .long 0xFFC80000
+FRQCR0_D: .long 0xCF000001
+
+CS0CTRL_A: .long 0xFF800200
+CS0CTRL_D: .long 0x00000020
+CS1CTRL_A: .long 0xFF800204
+CS1CTRL_D: .long 0x00000020
+
+CS0CTRL2_A: .long 0xFF800220
+CS0CTRL2_D: .long 0x00004000
+
+CSPWCR0_A: .long 0xFF800280
+CSPWCR0_D: .long 0x00000000
+CSPWCR1_A: .long 0xFF800284
+CSPWCR1_D: .long 0x00000000
+CS1GDST_A: .long 0xFF8002C0
+CS1GDST_D: .long 0x00000011
+
+init_lbsc_533:
+
+ write32 CSWCR0_A, CSWCR0_D_533
+ write32 CSWCR1_A, CSWCR1_D
+
+ bra init_dbsc3_533_pad
+ nop
+
+ .align 2
+
+CSWCR0_A: .long 0xFF800230
+CSWCR0_D_533: .long 0x01120104
+CSWCR0_D_400: .long 0x02120114
+CSWCR1_A: .long 0xFF800234
+CSWCR1_D: .long 0x077F077F
+
+init_dbsc3_400_pad:
+
+ write32 DBPDCNT3_A, DBPDCNT3_D
+ wait_timer WAIT_200US_400
+
+ write32 DBPDCNT0_A, DBPDCNT0_D_400
+ write32 DBPDCNT3_A, DBPDCNT3_D0
+ write32 DBPDCNT1_A, DBPDCNT1_D
+
+ write32 DBPDCNT3_A, DBPDCNT3_D1
+ wait_timer WAIT_32MCLK
+
+ write32 DBPDCNT3_A, DBPDCNT3_D2
+ wait_timer WAIT_100US_400
+
+ write32 DBPDCNT3_A, DBPDCNT3_D3
+ wait_timer WAIT_16MCLK
+
+ write32 DBPDCNT3_A, DBPDCNT3_D4
+ wait_timer WAIT_200US_400
+
+ write32 DBPDCNT3_A, DBPDCNT3_D5
+ wait_timer WAIT_1MCLK
+
+ write32 DBPDCNT3_A, DBPDCNT3_D6
+ wait_timer WAIT_10KMCLK
+
+ bra init_dbsc3_ctrl_400
+ nop
+
+ .align 2
+
+init_dbsc3_533_pad:
+
+ write32 DBPDCNT3_A, DBPDCNT3_D
+ wait_timer WAIT_200US_533
+
+ write32 DBPDCNT0_A, DBPDCNT0_D_533
+ write32 DBPDCNT3_A, DBPDCNT3_D0
+ write32 DBPDCNT1_A, DBPDCNT1_D
+
+ write32 DBPDCNT3_A, DBPDCNT3_D1
+ wait_timer WAIT_32MCLK
+
+ write32 DBPDCNT3_A, DBPDCNT3_D2
+ wait_timer WAIT_100US_533
+
+ write32 DBPDCNT3_A, DBPDCNT3_D3
+ wait_timer WAIT_16MCLK
+
+ write32 DBPDCNT3_A, DBPDCNT3_D4
+ wait_timer WAIT_200US_533
+
+ write32 DBPDCNT3_A, DBPDCNT3_D5
+ wait_timer WAIT_1MCLK
+
+ write32 DBPDCNT3_A, DBPDCNT3_D6
+ wait_timer WAIT_10KMCLK
+
+ bra init_dbsc3_ctrl_533
+ nop
+
+ .align 2
+
+WAIT_200US_400: .long 40000
+WAIT_200US_533: .long 53300
+WAIT_100US_400: .long 20000
+WAIT_100US_533: .long 26650
+WAIT_32MCLK: .long 32
+WAIT_16MCLK: .long 16
+WAIT_1MCLK: .long 1
+WAIT_10KMCLK: .long 10000
+
+DBPDCNT0_A: .long 0xFE800200
+DBPDCNT0_D_533: .long 0x00010245
+DBPDCNT0_D_400: .long 0x00010235
+DBPDCNT1_A: .long 0xFE800204
+DBPDCNT1_D: .long 0x00000014
+DBPDCNT3_A: .long 0xFE80020C
+DBPDCNT3_D: .long 0x80000000
+DBPDCNT3_D0: .long 0x800F0000
+DBPDCNT3_D1: .long 0x800F1000
+DBPDCNT3_D2: .long 0x820F1000
+DBPDCNT3_D3: .long 0x860F1000
+DBPDCNT3_D4: .long 0x870F1000
+DBPDCNT3_D5: .long 0x870F3000
+DBPDCNT3_D6: .long 0x870F7000
+
+init_dbsc3_ctrl_400:
+
+ write32 DBKIND_A, DBKIND_D
+ write32 DBCONF_A, DBCONF_D
+
+ write32 DBTR0_A, DBTR0_D_400
+ write32 DBTR1_A, DBTR1_D_400
+ write32 DBTR2_A, DBTR2_D
+ write32 DBTR3_A, DBTR3_D_400
+ write32 DBTR4_A, DBTR4_D_400
+ write32 DBTR5_A, DBTR5_D_400
+ write32 DBTR6_A, DBTR6_D_400
+ write32 DBTR7_A, DBTR7_D
+ write32 DBTR8_A, DBTR8_D_400
+ write32 DBTR9_A, DBTR9_D
+ write32 DBTR10_A, DBTR10_D_400
+ write32 DBTR11_A, DBTR11_D
+ write32 DBTR12_A, DBTR12_D_400
+ write32 DBTR13_A, DBTR13_D_400
+ write32 DBTR14_A, DBTR14_D
+ write32 DBTR15_A, DBTR15_D
+ write32 DBTR16_A, DBTR16_D_400
+ write32 DBTR17_A, DBTR17_D_400
+ write32 DBTR18_A, DBTR18_D_400
+
+ write32 DBBL_A, DBBL_D
+ write32 DBRNK0_A, DBRNK0_D
+
+ write32 DBCMD_A, DBCMD_D0_400
+ write32 DBCMD_A, DBCMD_D1
+ write32 DBCMD_A, DBCMD_D2
+ write32 DBCMD_A, DBCMD_D3
+ write32 DBCMD_A, DBCMD_D4
+ write32 DBCMD_A, DBCMD_D5_400
+ write32 DBCMD_A, DBCMD_D6
+ write32 DBCMD_A, DBCMD_D7
+ write32 DBCMD_A, DBCMD_D8
+ write32 DBCMD_A, DBCMD_D9_400
+ write32 DBCMD_A, DBCMD_D10
+ write32 DBCMD_A, DBCMD_D11
+ write32 DBCMD_A, DBCMD_D12
+
+ write32 DBRFCNF0_A, DBRFCNF0_D
+ write32 DBRFCNF1_A, DBRFCNF1_D_400
+ write32 DBRFCNF2_A, DBRFCNF2_D
+ write32 DBRFEN_A, DBRFEN_D
+ write32 DBACEN_A, DBACEN_D
+ write32 DBACEN_A, DBACEN_D
+
+ /* Dummy read */
+ mov.l DBWAIT_A, r1
+ synco
+ mov.l @r1, r0
+ synco
+
+ /* Dummy read */
+ mov.l SDRAM_A, r1
+ synco
+ mov.l @r1, r0
+ synco
+
+ /* need sleep 186A0 */
+
+ bra finish_init_sh7734
+ nop
+
+ .align 2
+
+init_dbsc3_ctrl_533:
+
+ write32 DBKIND_A, DBKIND_D
+ write32 DBCONF_A, DBCONF_D
+
+ write32 DBTR0_A, DBTR0_D_533
+ write32 DBTR1_A, DBTR1_D_533
+ write32 DBTR2_A, DBTR2_D
+ write32 DBTR3_A, DBTR3_D_533
+ write32 DBTR4_A, DBTR4_D_533
+ write32 DBTR5_A, DBTR5_D_533
+ write32 DBTR6_A, DBTR6_D_533
+ write32 DBTR7_A, DBTR7_D
+ write32 DBTR8_A, DBTR8_D_533
+ write32 DBTR9_A, DBTR9_D
+ write32 DBTR10_A, DBTR10_D_533
+ write32 DBTR11_A, DBTR11_D
+ write32 DBTR12_A, DBTR12_D_533
+ write32 DBTR13_A, DBTR13_D_533
+ write32 DBTR14_A, DBTR14_D
+ write32 DBTR15_A, DBTR15_D
+ write32 DBTR16_A, DBTR16_D_533
+ write32 DBTR17_A, DBTR17_D_533
+ write32 DBTR18_A, DBTR18_D_533
+
+ write32 DBBL_A, DBBL_D
+ write32 DBRNK0_A, DBRNK0_D
+
+ write32 DBCMD_A, DBCMD_D0_533
+ write32 DBCMD_A, DBCMD_D1
+ write32 DBCMD_A, DBCMD_D2
+ write32 DBCMD_A, DBCMD_D3
+ write32 DBCMD_A, DBCMD_D4
+ write32 DBCMD_A, DBCMD_D5_533
+ write32 DBCMD_A, DBCMD_D6
+ write32 DBCMD_A, DBCMD_D7
+ write32 DBCMD_A, DBCMD_D8
+ write32 DBCMD_A, DBCMD_D9_533
+ write32 DBCMD_A, DBCMD_D10
+ write32 DBCMD_A, DBCMD_D11
+ write32 DBCMD_A, DBCMD_D12
+
+ write32 DBRFCNF0_A, DBRFCNF0_D
+ write32 DBRFCNF1_A, DBRFCNF1_D_533
+ write32 DBRFCNF2_A, DBRFCNF2_D
+ write32 DBRFEN_A, DBRFEN_D
+ write32 DBACEN_A, DBACEN_D
+ write32 DBACEN_A, DBACEN_D
+
+ /* Dummy read */
+ mov.l DBWAIT_A, r1
+ synco
+ mov.l @r1, r0
+ synco
+
+ /* Dummy read */
+ mov.l SDRAM_A, r1
+ synco
+ mov.l @r1, r0
+ synco
+
+ /* need sleep 186A0 */
+
+ bra finish_init_sh7734
+ nop
+
+ .align 2
+
+DBKIND_A: .long 0xFE800020
+DBKIND_D: .long 0x00000005
+DBCONF_A: .long 0xFE800024
+DBCONF_D: .long 0x0D020A01
+
+DBTR0_A: .long 0xFE800040
+DBTR0_D_533:.long 0x00000004
+DBTR0_D_400:.long 0x00000003
+DBTR1_A: .long 0xFE800044
+DBTR1_D_533:.long 0x00000003
+DBTR1_D_400:.long 0x00000002
+DBTR2_A: .long 0xFE800048
+DBTR2_D: .long 0x00000000
+DBTR3_A: .long 0xFE800050
+DBTR3_D_533:.long 0x00000004
+DBTR3_D_400:.long 0x00000003
+
+DBTR4_A: .long 0xFE800054
+DBTR4_D_533:.long 0x00050004
+DBTR4_D_400:.long 0x00050003
+
+DBTR5_A: .long 0xFE800058
+DBTR5_D_533:.long 0x0000000F
+DBTR5_D_400:.long 0x0000000B
+
+DBTR6_A: .long 0xFE80005C
+DBTR6_D_533:.long 0x0000000B
+DBTR6_D_400:.long 0x00000008
+
+DBTR7_A: .long 0xFE800060
+DBTR7_D: .long 0x00000002
+
+DBTR8_A: .long 0xFE800064
+DBTR8_D_533:.long 0x0000000D
+DBTR8_D_400:.long 0x0000000A
+
+DBTR9_A: .long 0xFE800068
+DBTR9_D: .long 0x00000002
+
+DBTR10_A: .long 0xFE80006C
+DBTR10_D_533:.long 0x00000004
+DBTR10_D_400:.long 0x00000003
+
+DBTR11_A: .long 0xFE800070
+DBTR11_D: .long 0x00000008
+
+DBTR12_A: .long 0xFE800074
+DBTR12_D_533:.long 0x00000009
+DBTR12_D_400:.long 0x00000008
+
+DBTR13_A: .long 0xFE800078
+DBTR13_D_533:.long 0x00000022
+DBTR13_D_400:.long 0x0000001A
+
+DBTR14_A: .long 0xFE80007C
+DBTR14_D: .long 0x00070002
+
+DBTR15_A: .long 0xFE800080
+DBTR15_D: .long 0x00000003
+
+DBTR16_A: .long 0xFE800084
+DBTR16_D_533:.long 0x120A1001
+DBTR16_D_400:.long 0x12091001
+
+DBTR17_A: .long 0xFE800088
+DBTR17_D_533:.long 0x00040000
+DBTR17_D_400:.long 0x00030000
+
+DBTR18_A: .long 0xFE80008C
+DBTR18_D_533:.long 0x02010200
+DBTR18_D_400:.long 0x02000207
+
+DBBL_A: .long 0xFE8000B0
+DBBL_D: .long 0x00000000
+
+DBRNK0_A: .long 0xFE800100
+DBRNK0_D: .long 0x00000001
+
+DBCMD_A: .long 0xFE800018
+DBCMD_D0_533: .long 0x1100006B
+DBCMD_D0_400: .long 0x11000050
+DBCMD_D1: .long 0x0B000000
+DBCMD_D2: .long 0x2A004000
+DBCMD_D3: .long 0x2B006000
+DBCMD_D4: .long 0x29002044
+DBCMD_D5_533: .long 0x28000743
+DBCMD_D5_400: .long 0x28000533
+DBCMD_D6: .long 0x0B000000
+DBCMD_D7: .long 0x0C000000
+DBCMD_D8: .long 0x0C000000
+DBCMD_D9_533: .long 0x28000643
+DBCMD_D9_400: .long 0x28000433
+DBCMD_D10: .long 0x000000C8
+DBCMD_D11: .long 0x290023C4
+DBCMD_D12: .long 0x29002004
+
+DBRFCNF0_A: .long 0xFE8000E0
+DBRFCNF0_D: .long 0x000001FF
+DBRFCNF1_A: .long 0xFE8000E4
+DBRFCNF1_D_533: .long 0x00000805
+DBRFCNF1_D_400: .long 0x00000618
+
+DBRFCNF2_A: .long 0xFE8000E8
+DBRFCNF2_D: .long 0x00000000
+
+DBRFEN_A: .long 0xFE800014
+DBRFEN_D: .long 0x00000001
+
+DBACEN_A: .long 0xFE800010
+DBACEN_D: .long 0x00000001
+
+DBWAIT_A: .long 0xFE80001C
+SDRAM_A: .long 0x0C000000
+
+finish_init_sh7734:
+ write32 CCR_A, CCR_D
+
+ stc sr, r0
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+ nop
+
+ .align 2
+
+CCR_A: .long 0xFF00001C
+CCR_D: .long 0x0000090B
+SR_MASK_D: .long 0xEFFFFF0F
diff --git a/board/altera/common/cfide.c b/board/altera/common/cfide.c
new file mode 100644
index 0000000..40d6a12
--- /dev/null
+++ b/board/altera/common/cfide.c
@@ -0,0 +1,33 @@
+/*
+ * Altera CF drvier
+ *
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_IDE_RESET) && defined(CONFIG_SYS_CF_CTL_BASE)
+/* ide_set_reset for Altera CF interface */
+#define ALTERA_CF_CTL_STATUS 0
+#define ALTERA_CF_IDE_CTL 4
+#define ALTERA_CF_CTL_STATUS_PRESENT_MSK (0x1)
+#define ALTERA_CF_CTL_STATUS_POWER_MSK (0x2)
+#define ALTERA_CF_CTL_STATUS_RESET_MSK (0x4)
+#define ALTERA_CF_CTL_STATUS_IRQ_EN_MSK (0x8)
+#define ALTERA_CF_IDE_CTL_IRQ_EN_MSK (0x1)
+
+void ide_set_reset(int idereset)
+{
+ int i;
+ writel(idereset ? ALTERA_CF_CTL_STATUS_RESET_MSK :
+ ALTERA_CF_CTL_STATUS_POWER_MSK,
+ CONFIG_SYS_CF_CTL_BASE + ALTERA_CF_CTL_STATUS);
+ /* wait 500 ms for power to stabilize */
+ for (i = 0; i < 500; i++)
+ udelay(1000);
+}
+#endif
diff --git a/board/altera/nios2-generic/Kconfig b/board/altera/nios2-generic/Kconfig
new file mode 100644
index 0000000..cd3d098
--- /dev/null
+++ b/board/altera/nios2-generic/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NIOS2_GENERIC
+
+config SYS_BOARD
+ default "nios2-generic"
+
+config SYS_VENDOR
+ default "altera"
+
+config SYS_CONFIG_NAME
+ default "nios2-generic"
+
+endif
diff --git a/board/altera/nios2-generic/MAINTAINERS b/board/altera/nios2-generic/MAINTAINERS
new file mode 100644
index 0000000..9cbcba9
--- /dev/null
+++ b/board/altera/nios2-generic/MAINTAINERS
@@ -0,0 +1,6 @@
+NIOS2-GENERIC BOARD
+M: Scott McNutt <smcnutt@psyent.com>
+S: Maintained
+F: board/altera/nios2-generic/
+F: include/configs/nios2-generic.h
+F: configs/nios2-generic_defconfig
diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile
new file mode 100644
index 0000000..5e4192c
--- /dev/null
+++ b/board/altera/nios2-generic/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nios2-generic.o
+obj-$(CONFIG_CMD_IDE) += ../common/cfide.o
diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk
new file mode 100644
index 0000000..a673525
--- /dev/null
+++ b/board/altera/nios2-generic/config.mk
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h
new file mode 100644
index 0000000..cf75d35
--- /dev/null
+++ b/board/altera/nios2-generic/custom_fpga.h
@@ -0,0 +1,89 @@
+/*
+ * This header is generated by sopc2dts
+ * Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
+ * in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _CUSTOM_FPGA_H_
+#define _CUSTOM_FPGA_H_
+
+/* generated from qsys_ghrd_3c120.sopcinfo */
+
+/* Dumping slaves of cpu.data_master */
+
+/* cpu.jtag_debug_module is a altera_nios2_qsys */
+#define CONFIG_SYS_CLK_FREQ 125000000
+#define CONFIG_SYS_DCACHE_SIZE 32768
+#define CONFIG_SYS_DCACHELINE_SIZE 32
+#define CONFIG_SYS_ICACHELINE_SIZE 32
+#define CONFIG_SYS_EXCEPTION_ADDR 0xd0000020
+#define CONFIG_SYS_ICACHE_SIZE 32768
+#define CONFIG_SYS_RESET_ADDR 0xc2800000
+#define IO_REGION_BASE 0xE0000000
+
+/* pb_cpu_to_ddr2_bot.s0 is a altera_avalon_mm_bridge */
+/* Dumping slaves of pb_cpu_to_ddr2_bot.m0 */
+
+/* ddr2_bot.s1 is a altmemddr2 */
+#define CONFIG_SYS_SDRAM_BASE 0xD0000000
+#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+
+/* pb_cpu_to_io.s0 is a altera_avalon_mm_bridge */
+/* Dumping slaves of pb_cpu_to_io.m0 */
+
+/* timer_1ms.s1 is a altera_avalon_timer */
+#define CONFIG_SYS_TIMER_IRQ 11
+#define CONFIG_SYS_TIMER_FREQ 125000000
+#define CONFIG_SYS_TIMER_BASE 0xE8400000
+
+/* sysid.control_slave is a altera_avalon_sysid_qsys */
+#define CONFIG_SYS_SYSID_BASE 0xE8004D40
+
+/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
+#define CONFIG_SYS_JTAG_UART_BASE 0xE8004D50
+
+/* tse_mac.control_port is a triple_speed_ethernet */
+#define CONFIG_SYS_ALTERA_TSE_RX_FIFO 2048
+#define CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE 0xE8004800
+#define CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE 0xE8004400
+#define CONFIG_SYS_ALTERA_TSE_TX_FIFO 2048
+#define CONFIG_SYS_ALTERA_TSE_DESC_SIZE 0x00002000
+#define CONFIG_SYS_ALTERA_TSE_MAC_BASE 0xE8004000
+#define CONFIG_SYS_ALTERA_TSE_DESC_BASE 0xE8002000
+#define CONFIG_ALTERA_TSE
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_SYS_ALTERA_TSE_PHY_ADDR 18
+#define CONFIG_SYS_ALTERA_TSE_FLAGS 1
+
+/* uart.s1 is a altera_avalon_uart */
+#define CONFIG_SYS_UART_BAUD 115200
+#define CONFIG_SYS_UART_BASE 0xE8004C80
+#define CONFIG_SYS_UART_FREQ 62500000
+
+/* user_led_pio_8out.s1 is a altera_avalon_pio */
+#define USER_LED_PIO_8OUT_BASE 0xE8004CC0
+
+/* user_dipsw_pio_8in.s1 is a altera_avalon_pio */
+#define USER_DIPSW_PIO_8IN_BASE 0xE8004CE0
+#define USER_DIPSW_PIO_8IN_IRQ 8
+
+/* user_pb_pio_4in.s1 is a altera_avalon_pio */
+#define USER_PB_PIO_4IN_BASE 0xE8004D00
+#define USER_PB_PIO_4IN_IRQ 9
+
+/* cfi_flash_64m.uas is a altera_generic_tristate_controller */
+#define CFI_FLASH_64M_BASE 0xE0000000
+
+/* ext_flash.s1 is a altera_avalon_cfi_flash */
+#define CONFIG_SYS_FLASH_BASE CFI_FLASH_64M_BASE
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+
+#endif /* _CUSTOM_FPGA_H_ */
diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c
new file mode 100644
index 0000000..834cbeb
--- /dev/null
+++ b/board/altera/nios2-generic/nios2-generic.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#if defined(CONFIG_CFI_FLASH_MTD)
+#include <mtd/cfi_flash.h>
+#endif
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \
+ defined(CONFIG_CFI_FLASH_MTD)
+static void __early_flash_cmd_reset(void)
+{
+ /* reset flash before we read env */
+ writeb(AMD_CMD_RESET, CONFIG_ENV_ADDR);
+ writeb(FLASH_CMD_RESET, CONFIG_ENV_ADDR);
+}
+void early_flash_cmd_reset(void)
+ __attribute__((weak,alias("__early_flash_cmd_reset")));
+#endif
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_ALTERA_PIO
+#ifdef LED_PIO_BASE
+ altera_pio_init(LED_PIO_BASE, LED_PIO_WIDTH, 'o',
+ LED_PIO_RSTVAL, (1 << LED_PIO_WIDTH) - 1,
+ "led");
+#endif
+#endif
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \
+ defined(CONFIG_CFI_FLASH_MTD)
+ early_flash_cmd_reset();
+#endif
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("BOARD : %s\n", CONFIG_BOARD_NAME);
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc += smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+ rc += dm9000_initialize(bis);
+#endif
+#ifdef CONFIG_ALTERA_TSE
+ rc += altera_tse_initialize(0,
+ CONFIG_SYS_ALTERA_TSE_MAC_BASE,
+ CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE,
+ CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE,
+#if defined(CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_BASE) && \
+ (CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_SIZE > 0)
+ CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_BASE,
+ CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_SIZE);
+#else
+ 0,
+ 0);
+#endif
+#endif
+#ifdef CONFIG_ETHOC
+ rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/altera/socfpga/Kconfig b/board/altera/socfpga/Kconfig
new file mode 100644
index 0000000..fc42185
--- /dev/null
+++ b/board/altera/socfpga/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SOCFPGA_CYCLONE5
+
+config SYS_BOARD
+ default "socfpga"
+
+config SYS_VENDOR
+ default "altera"
+
+config SYS_SOC
+ default "socfpga"
+
+config SYS_CONFIG_NAME
+ default "socfpga_cyclone5"
+
+endif
diff --git a/board/altera/socfpga/MAINTAINERS b/board/altera/socfpga/MAINTAINERS
new file mode 100644
index 0000000..0482581
--- /dev/null
+++ b/board/altera/socfpga/MAINTAINERS
@@ -0,0 +1,12 @@
+SOCFPGA BOARD
+M: Dinh Nguyen <dinguyen@altera.com>
+M: Chin-Liang See <clsee@altera.com>
+S: Maintained
+F: board/altera/socfpga/
+F: include/configs/socfpga_cyclone5.h
+F: configs/socfpga_cyclone5_defconfig
+
+SOCRATES BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: configs/socfpga_socrates_defconfig
diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile
new file mode 100644
index 0000000..44baa00
--- /dev/null
+++ b/board/altera/socfpga/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := socfpga_cyclone5.o
+obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o
diff --git a/board/altera/socfpga/iocsr_config.c b/board/altera/socfpga/iocsr_config.c
new file mode 100644
index 0000000..b4b5ff8
--- /dev/null
+++ b/board/altera/socfpga/iocsr_config.c
@@ -0,0 +1,657 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* This file is generated by Preloader Generator */
+
+#include <iocsr_config.h>
+
+const unsigned long iocsr_scan_chain0_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
+ 0x00000000,
+ 0x00000000,
+ 0x0FF00000,
+ 0xC0000000,
+ 0x0000003F,
+ 0x00008000,
+ 0x00020080,
+ 0x08020000,
+ 0x08000000,
+ 0x00018020,
+ 0x00000000,
+ 0x00004000,
+ 0x00010040,
+ 0x04010000,
+ 0x04000000,
+ 0x00000010,
+ 0x00004010,
+ 0x00002000,
+ 0x00020000,
+ 0x02008000,
+ 0x02000000,
+ 0x00000008,
+ 0x00002008,
+ 0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
+ 0x000C0300,
+ 0x10040000,
+ 0x100000C0,
+ 0x00000040,
+ 0x00010040,
+ 0x00008000,
+ 0x00080000,
+ 0x18060000,
+ 0x18000000,
+ 0x00000060,
+ 0x00018060,
+ 0x00004000,
+ 0x00010040,
+ 0x10000000,
+ 0x04000000,
+ 0x00000010,
+ 0x00004010,
+ 0x00002000,
+ 0x06008020,
+ 0x02008000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x00004010,
+ 0x01004000,
+ 0x01000000,
+ 0x00003004,
+ 0x00001004,
+ 0x00000800,
+ 0x00000000,
+ 0x00000000,
+ 0x00800000,
+ 0x00000002,
+ 0x00002000,
+ 0x00000400,
+ 0x00000000,
+ 0x00401000,
+ 0x00000003,
+ 0x00000000,
+ 0x00000000,
+ 0x00000200,
+ 0x00600802,
+ 0x00000000,
+ 0x80200000,
+ 0x80000600,
+ 0x00000200,
+ 0x00000100,
+ 0x00300401,
+ 0xC0100400,
+ 0x40100000,
+ 0x40000300,
+ 0x000C0100,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
+ 0x80040100,
+ 0x00000000,
+ 0x0FF00000,
+ 0x00000000,
+ 0x0C010040,
+ 0x00008000,
+ 0x18020080,
+ 0x00000000,
+ 0x08000000,
+ 0x00040020,
+ 0x06018060,
+ 0x00004000,
+ 0x0C010040,
+ 0x04010000,
+ 0x00000030,
+ 0x00000000,
+ 0x03004010,
+ 0x00002000,
+ 0x06008020,
+ 0x02008000,
+ 0x02000018,
+ 0x00006008,
+ 0x01802008,
+ 0x00001000,
+ 0x03004010,
+ 0x01004000,
+ 0x0100000C,
+ 0x00003004,
+ 0x00C01004,
+ 0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[((
+ CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
+ 0x2C420D80,
+ 0x082000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0xE4400000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000070,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00A28,
+ 0xA20D0000,
+ 0x24906808,
+ 0x00A28340,
+ 0xD000001A,
+ 0x06808A20,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000FF0,
+ 0x72200000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x6A1C0000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x1A870001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000070,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00040,
+ 0xA20D0002,
+ 0x24906808,
+ 0x00A28340,
+ 0xD005141A,
+ 0x06808A20,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x000001C1,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC255F80,
+ 0xF1C71C71,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x04510680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00600391,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC255F80,
+ 0xF1C71C71,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x8341D348,
+ 0x821A0124,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC255F80,
+ 0xF1C71C71,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x40120800,
+ 0x00000070,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC255F80,
+ 0xF1C71C71,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0x00489800,
+ 0x001A1A1A,
+ 0x085506A0,
+ 0x0000E1D4,
+ 0x045506A0,
+ 0x0000E1D4,
+ 0x085506A0,
+ 0x8000E1D4,
+ 0x00000200,
+ 0x00000004,
+ 0x04000000,
+ 0x00000009,
+ 0x00002410,
+ 0x00000040,
+ 0x41000000,
+ 0x00002082,
+ 0x00000350,
+ 0x000000DA,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x022A8350,
+ 0x000070EA,
+ 0x86000000,
+ 0x08000004,
+ 0x00000000,
+ 0x00482000,
+ 0x21800000,
+ 0x00101061,
+ 0x021541A8,
+ 0x00003875,
+ 0x011541A8,
+ 0x00003875,
+ 0x021541A8,
+ 0x20003875,
+ 0x00000080,
+ 0x00000001,
+ 0x41000000,
+ 0x00000002,
+ 0x00FF0904,
+ 0x00000000,
+ 0x90400000,
+ 0x00000820,
+ 0xC0000001,
+ 0x38D612AF,
+ 0x86F8E38E,
+ 0x0A0A78B4,
+ 0x000D020A,
+ 0x00006800,
+ 0x028A4320,
+ 0xEC2CB23D,
+ 0x8F5D1451,
+ 0xA47A88A2,
+ 0x0001A0E9,
+ 0x00410D00,
+ 0x40000068,
+ 0x3D000003,
+ 0x51EC2CB2,
+ 0xA28F5D14,
+ 0xE9A47A88,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000540,
+ 0x000003A8,
+ 0x08AA0D40,
+ 0x8001C3A8,
+ 0x0000007F,
+ 0x00000000,
+ 0x00004060,
+ 0xE1208000,
+ 0x0000001F,
+ 0x00004100,
+};
diff --git a/board/altera/socfpga/iocsr_config.h b/board/altera/socfpga/iocsr_config.h
new file mode 100644
index 0000000..490f109
--- /dev/null
+++ b/board/altera/socfpga/iocsr_config.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* This file is generated by Preloader Generator */
+
+#ifndef _PRELOADER_IOCSR_CONFIG_H_
+#define _PRELOADER_IOCSR_CONFIG_H_
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
+
+#endif /*_PRELOADER_IOCSR_CONFIG_H_*/
diff --git a/board/altera/socfpga/pinmux_config.c b/board/altera/socfpga/pinmux_config.c
new file mode 100644
index 0000000..8b09005
--- /dev/null
+++ b/board/altera/socfpga/pinmux_config.c
@@ -0,0 +1,214 @@
+/* This file is generated by Preloader Generator */
+
+#include "pinmux_config.h"
+
+/* pin mux configuration data */
+unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
+ 0, /* EMACIO0 - Unused */
+ 2, /* EMACIO1 - USB */
+ 2, /* EMACIO2 - USB */
+ 2, /* EMACIO3 - USB */
+ 2, /* EMACIO4 - USB */
+ 2, /* EMACIO5 - USB */
+ 2, /* EMACIO6 - USB */
+ 2, /* EMACIO7 - USB */
+ 2, /* EMACIO8 - USB */
+ 0, /* EMACIO9 - Unused */
+ 2, /* EMACIO10 - USB */
+ 2, /* EMACIO11 - USB */
+ 2, /* EMACIO12 - USB */
+ 2, /* EMACIO13 - USB */
+ 0, /* EMACIO14 - N/A */
+ 0, /* EMACIO15 - N/A */
+ 0, /* EMACIO16 - N/A */
+ 0, /* EMACIO17 - N/A */
+ 0, /* EMACIO18 - N/A */
+ 0, /* EMACIO19 - N/A */
+ 3, /* FLASHIO0 - SDMMC */
+ 3, /* FLASHIO1 - SDMMC */
+ 3, /* FLASHIO2 - SDMMC */
+ 3, /* FLASHIO3 - SDMMC */
+ 0, /* FLASHIO4 - SDMMC */
+ 0, /* FLASHIO5 - SDMMC */
+ 0, /* FLASHIO6 - SDMMC */
+ 0, /* FLASHIO7 - SDMMC */
+ 0, /* FLASHIO8 - SDMMC */
+ 3, /* FLASHIO9 - SDMMC */
+ 3, /* FLASHIO10 - SDMMC */
+ 3, /* FLASHIO11 - SDMMC */
+ 3, /* GENERALIO0 - TRACE */
+ 3, /* GENERALIO1 - TRACE */
+ 3, /* GENERALIO2 - TRACE */
+ 3, /* GENERALIO3 - TRACE */
+ 3, /* GENERALIO4 - TRACE */
+ 3, /* GENERALIO5 - TRACE */
+ 3, /* GENERALIO6 - TRACE */
+ 3, /* GENERALIO7 - TRACE */
+ 3, /* GENERALIO8 - TRACE */
+ 3, /* GENERALIO9 - SPIM0 */
+ 3, /* GENERALIO10 - SPIM0 */
+ 3, /* GENERALIO11 - SPIM0 */
+ 3, /* GENERALIO12 - SPIM0 */
+ 2, /* GENERALIO13 - CAN0 */
+ 2, /* GENERALIO14 - CAN0 */
+ 3, /* GENERALIO15 - I2C0 */
+ 3, /* GENERALIO16 - I2C0 */
+ 2, /* GENERALIO17 - UART0 */
+ 2, /* GENERALIO18 - UART0 */
+ 0, /* GENERALIO19 - N/A */
+ 0, /* GENERALIO20 - N/A */
+ 0, /* GENERALIO21 - N/A */
+ 0, /* GENERALIO22 - N/A */
+ 0, /* GENERALIO23 - N/A */
+ 0, /* GENERALIO24 - N/A */
+ 0, /* GENERALIO25 - N/A */
+ 0, /* GENERALIO26 - N/A */
+ 0, /* GENERALIO27 - N/A */
+ 0, /* GENERALIO28 - N/A */
+ 0, /* GENERALIO29 - N/A */
+ 0, /* GENERALIO30 - N/A */
+ 0, /* GENERALIO31 - N/A */
+ 2, /* MIXED1IO0 - EMAC */
+ 2, /* MIXED1IO1 - EMAC */
+ 2, /* MIXED1IO2 - EMAC */
+ 2, /* MIXED1IO3 - EMAC */
+ 2, /* MIXED1IO4 - EMAC */
+ 2, /* MIXED1IO5 - EMAC */
+ 2, /* MIXED1IO6 - EMAC */
+ 2, /* MIXED1IO7 - EMAC */
+ 2, /* MIXED1IO8 - EMAC */
+ 2, /* MIXED1IO9 - EMAC */
+ 2, /* MIXED1IO10 - EMAC */
+ 2, /* MIXED1IO11 - EMAC */
+ 2, /* MIXED1IO12 - EMAC */
+ 2, /* MIXED1IO13 - EMAC */
+ 0, /* MIXED1IO14 - Unused */
+ 3, /* MIXED1IO15 - QSPI */
+ 3, /* MIXED1IO16 - QSPI */
+ 3, /* MIXED1IO17 - QSPI */
+ 3, /* MIXED1IO18 - QSPI */
+ 3, /* MIXED1IO19 - QSPI */
+ 3, /* MIXED1IO20 - QSPI */
+ 0, /* MIXED1IO21 - GPIO */
+ 0, /* MIXED2IO0 - N/A */
+ 0, /* MIXED2IO1 - N/A */
+ 0, /* MIXED2IO2 - N/A */
+ 0, /* MIXED2IO3 - N/A */
+ 0, /* MIXED2IO4 - N/A */
+ 0, /* MIXED2IO5 - N/A */
+ 0, /* MIXED2IO6 - N/A */
+ 0, /* MIXED2IO7 - N/A */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
diff --git a/board/altera/socfpga/pinmux_config.h b/board/altera/socfpga/pinmux_config.h
new file mode 100644
index 0000000..f278f2b
--- /dev/null
+++ b/board/altera/socfpga/pinmux_config.h
@@ -0,0 +1,54 @@
+/* This file is generated by Preloader Generator */
+
+#ifndef _PRELOADER_PINMUX_CONFIG_H_
+#define _PRELOADER_PINMUX_CONFIG_H_
+
+/*
+ * State of enabling for which IP connected out through the muxing.
+ * Value 1 mean the IP connection is muxed out
+ */
+#define CONFIG_HPS_EMAC0 (0)
+#define CONFIG_HPS_EMAC1 (1)
+#define CONFIG_HPS_USB0 (0)
+#define CONFIG_HPS_USB1 (1)
+#define CONFIG_HPS_NAND (0)
+#define CONFIG_HPS_SDMMC (1)
+#define CONFIG_HPS_QSPI (1)
+#define CONFIG_HPS_UART0 (1)
+#define CONFIG_HPS_UART1 (0)
+#define CONFIG_HPS_TRACE (1)
+#define CONFIG_HPS_I2C0 (1)
+#define CONFIG_HPS_I2C1 (0)
+#define CONFIG_HPS_I2C2 (0)
+#define CONFIG_HPS_I2C3 (0)
+#define CONFIG_HPS_SPIM0 (1)
+#define CONFIG_HPS_SPIM1 (0)
+#define CONFIG_HPS_SPIS0 (0)
+#define CONFIG_HPS_SPIS1 (0)
+#define CONFIG_HPS_CAN0 (1)
+#define CONFIG_HPS_CAN1 (0)
+
+/* IP attribute value (which affected by pin muxing configuration) */
+#define CONFIG_HPS_SDMMC_BUSWIDTH (4)
+
+/* 1 if the pins are connected out */
+#define CONFIG_HPS_QSPI_CS0 (1)
+#define CONFIG_HPS_QSPI_CS1 (0)
+#define CONFIG_HPS_QSPI_CS2 (0)
+#define CONFIG_HPS_QSPI_CS3 (0)
+
+/* UART */
+/* 1 means the pin is mux out or available */
+#define CONFIG_HPS_UART0_TX (1)
+#define CONFIG_HPS_UART0_RX (1)
+#define CONFIG_HPS_UART0_CTS (0)
+#define CONFIG_HPS_UART0_RTS (0)
+#define CONFIG_HPS_UART1_TX (0)
+#define CONFIG_HPS_UART1_RX (0)
+#define CONFIG_HPS_UART1_CTS (0)
+#define CONFIG_HPS_UART1_RTS (0)
+
+/* Pin mux data */
+#define CONFIG_HPS_PINMUX_NUM (207)
+
+#endif /* _PRELOADER_PINMUX_CONFIG_H_ */
diff --git a/board/altera/socfpga/pll_config.h b/board/altera/socfpga/pll_config.h
new file mode 100644
index 0000000..f0f59a9
--- /dev/null
+++ b/board/altera/socfpga/pll_config.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2014. All rights reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* This file is generated by Preloader Generator */
+
+#ifndef _PRELOADER_PLL_CONFIG_H_
+#define _PRELOADER_PLL_CONFIG_H_
+
+/* PLL configuration data */
+/* Main PLL */
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
+/*
+ * To tell where is the clock source:
+ * 0 = MAINPLL
+ * 1 = PERIPHPLL
+ */
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
+
+/* Peripheral PLL */
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1)
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9)
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1)
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
+/*
+ * To tell where is the clock source:
+ * 0 = F2S_PERIPH_REF_CLK
+ * 1 = MAIN_CLK
+ * 2 = PERIPH_CLK
+ */
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
+
+/* SDRAM PLL */
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz
+ * This if..else... is not required if generated by tools */
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127)
+#else
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31)
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
+
+/* Info for driver */
+#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
+#define CONFIG_HPS_CLK_OSC2_HZ 0
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
+#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000)
+#else
+#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000)
+#endif
+#define CONFIG_HPS_CLK_EMAC0_HZ (250000000)
+#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
+#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
+#define CONFIG_HPS_CLK_NAND_HZ (50000000)
+#define CONFIG_HPS_CLK_SDMMC_HZ (200000000)
+#define CONFIG_HPS_CLK_QSPI_HZ (400000000)
+#define CONFIG_HPS_CLK_SPIM_HZ (200000000)
+#define CONFIG_HPS_CLK_CAN0_HZ (100000000)
+#define CONFIG_HPS_CLK_CAN1_HZ (100000000)
+#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
+#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
+#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
+
+#endif /* _PRELOADER_PLL_CONFIG_H_ */
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
new file mode 100644
index 0000000..459d82f
--- /dev/null
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <usb_mass_storage.h>
+
+#include <micrel.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Print Board information
+ */
+int checkboard(void)
+{
+ puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
+ return 0;
+}
+
+/*
+ * Initialization function which happen at early stage of c code
+ */
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+/*
+ * PHY configuration
+ */
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret;
+ /*
+ * These skew settings for the KSZ9021 ethernet phy is required for ethernet
+ * to work reliably on most flavors of cyclone5 boards.
+ */
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf0f0);
+ if (ret)
+ return ret;
+
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET
+struct s3c_plat_otg_data socfpga_otg_data = {
+ .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
+ .usb_gusbcfg = 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return s3c_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+ return 1;
+}
+#endif
diff --git a/board/amcc/acadia/Kconfig b/board/amcc/acadia/Kconfig
new file mode 100644
index 0000000..033deaf
--- /dev/null
+++ b/board/amcc/acadia/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ACADIA
+
+config SYS_BOARD
+ default "acadia"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "acadia"
+
+endif
diff --git a/board/amcc/acadia/MAINTAINERS b/board/amcc/acadia/MAINTAINERS
new file mode 100644
index 0000000..c16961f
--- /dev/null
+++ b/board/amcc/acadia/MAINTAINERS
@@ -0,0 +1,6 @@
+ACADIA BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/amcc/acadia/
+F: include/configs/acadia.h
+F: configs/acadia_defconfig
diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile
new file mode 100644
index 0000000..035f407
--- /dev/null
+++ b/board/amcc/acadia/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = acadia.o cmd_acadia.o memory.o pll.o
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
new file mode 100644
index 0000000..2eb18df
--- /dev/null
+++ b/board/amcc/acadia/acadia.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+extern void board_pll_init_f(void);
+
+static void acadia_gpio_init(void)
+{
+ /*
+ * GPIO0 setup (select GPIO or alternate function)
+ */
+ out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
+ out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
+ out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
+ out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
+ out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
+ out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
+ out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
+
+ /*
+ * Ultra (405EZ) was nice enough to add another GPIO controller
+ */
+ out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH); /* output select */
+ out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL);
+ out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H); /* input select */
+ out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L);
+ out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH); /* three-state select */
+ out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL);
+ out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR); /* enable output driver for outputs */
+}
+
+int board_early_init_f(void)
+{
+ unsigned int reg;
+
+ /* don't reinit PLL when booting via I2C bootstrap option */
+ mfsdr(SDR0_PINSTP, reg);
+ if (reg != 0xf0000000)
+ board_pll_init_f();
+
+ acadia_gpio_init();
+
+ /* Configure 405EZ for NAND usage */
+ mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
+ mfsdr(SDR0_ULTRA0, reg);
+ reg &= ~SDR_ULTRA0_CSN_MASK;
+ reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
+ SDR_ULTRA0_NDGPIOBP |
+ SDR_ULTRA0_EBCRDYEN |
+ SDR_ULTRA0_NFSRSTEN;
+ mtsdr(SDR0_ULTRA0, reg);
+
+ /* USB Host core needs this bit set */
+ mfsdr(SDR0_ULTRA1, reg);
+ mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
+
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000010);
+ mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */
+ mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ return 0;
+}
+
+int misc_init_f(void)
+{
+ /* Set EPLD to take PHY out of reset */
+ out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00);
+ udelay(100000);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+ u8 rev;
+
+ rev = in8(CONFIG_SYS_CPLD_BASE + 0);
+ printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return (0);
+}
diff --git a/board/amcc/acadia/cmd_acadia.c b/board/amcc/acadia/cmd_acadia.c
new file mode 100644
index 0000000..e9df61b
--- /dev/null
+++ b/board/amcc/acadia/cmd_acadia.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+static u8 boot_267_nor[] = {
+ 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00,
+ 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+};
+
+static u8 boot_267_nand[] = {
+ 0xd0, 0x38, 0xc3, 0x50, 0x13, 0x88, 0x8e, 0x00,
+ 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+};
+
+static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u8 chip;
+ u8 *buf;
+ int cpu_freq;
+
+ if (argc < 3)
+ return cmd_usage(cmdtp);
+
+ cpu_freq = simple_strtol(argv[1], NULL, 10);
+ if (cpu_freq != 267) {
+ printf("Unsupported cpu-frequency - only 267 supported\n");
+ return 1;
+ }
+
+ /* use 0x50 as I2C EEPROM address for now */
+ chip = 0x50;
+
+ if ((strcmp(argv[2], "nor") != 0) &&
+ (strcmp(argv[2], "nand") != 0)) {
+ printf("Unsupported boot-device - only nor|nand support\n");
+ return 1;
+ }
+
+ if (strcmp(argv[2], "nand") == 0) {
+ switch (cpu_freq) {
+ case 267:
+ buf = boot_267_nand;
+ break;
+ default:
+ break;
+ }
+ } else {
+ switch (cpu_freq) {
+ case 267:
+ buf = boot_267_nor;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (i2c_write(chip, 0, 1, buf, 16) != 0)
+ printf("Error writing to EEPROM at address 0x%x\n", chip);
+ udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+ if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0)
+ printf("Error2 writing to EEPROM at address 0x%x\n", chip);
+
+ printf("Done\n");
+ printf("Please power-cycle the board for the changes to take effect\n");
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ bootstrap, 3, 0, do_bootstrap,
+ "program the I2C bootstrap EEPROM",
+ "<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM"
+);
diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk
new file mode 100644
index 0000000..5350ec0
--- /dev/null
+++ b/board/amcc/acadia/config.mk
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2007-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#
+# AMCC 405EZ Reference Platform (Acadia) board
+#
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
new file mode 100644
index 0000000..9673118
--- /dev/null
+++ b/board/amcc/acadia/memory.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+extern void board_pll_init_f(void);
+
+static void cram_bcr_write(u32 wr_val)
+{
+ wr_val <<= 2;
+
+ /* set CRAM_CRE to 1 */
+ gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
+
+ /* Write BCR to CRAM on CS1 */
+ out32(wr_val + 0x00200000, 0);
+ debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
+
+ /* Write BCR to CRAM on CS2 */
+ out32(wr_val + 0x02200000, 0);
+ debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
+
+ sync();
+ eieio();
+
+ /* set CRAM_CRE back to 0 (normal operation) */
+ gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
+
+ return;
+}
+
+phys_size_t initdram(int board_type)
+{
+ int i;
+ u32 val;
+
+ /* 1. EBC need to program READY, CLK, ADV for ASync mode */
+ gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+ gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+ gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+ gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
+
+ /* 2. EBC in Async mode */
+ mtebc(PB1AP, 0x078F1EC0);
+ mtebc(PB2AP, 0x078F1EC0);
+ mtebc(PB1CR, 0x000BC000);
+ mtebc(PB2CR, 0x020BC000);
+
+ /* 3. Set CRAM in Sync mode */
+ cram_bcr_write(0x7012); /* CRAM burst setting */
+
+ /* 4. EBC in Sync mode */
+ mtebc(PB1AP, 0x9C0201C0);
+ mtebc(PB2AP, 0x9C0201C0);
+
+ /* Set GPIO pins back to alternate function */
+ gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+ gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+
+ /* Config EBC to use RDY */
+ mfsdr(SDR0_ULTRA0, val);
+ mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
+
+ /* Wait a short while, since for NAND booting this is too fast */
+ for (i=0; i<200000; i++)
+ ;
+
+ return (CONFIG_SYS_MBYTES_RAM << 20);
+}
diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c
new file mode 100644
index 0000000..d868582
--- /dev/null
+++ b/board/amcc/acadia/pll.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/ppc405.h>
+
+/* test-only: move into cpu directory!!! */
+
+#if defined(PLLMR0_200_133_66)
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------------------
+ * | CLK | FREQ (MHz) | DIV RATIO |
+ * ----------------------------------
+ * | CPU | 200.0 | 4 (0x02)|
+ * | PLB | 133.3 | 6 (0x06)|
+ * | OPB | 66.6 | 12 (0x0C)|
+ * | EBC | 66.6 | 12 (0x0C)|
+ * | SPI | 66.6 | 12 (0x0C)|
+ * | UART0 | 10.0 | 40 (0x28)|
+ * | UART1 | 10.0 | 40 (0x28)|
+ * | DAC | 2.0 | 200 (0xC8)|
+ * | ADC | 2.0 | 200 (0xC8)|
+ * | PWM | 100.0 | 4 (0x04)|
+ * | EMAC | 25.0 | 16 (0x10)|
+ * -----------------------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(CPR0_PLLC, 0x0000033c);
+ mtcpr(CPR0_PLLD, 0x0c010200);
+ mtcpr(CPR0_PRIMAD, 0x04060c0c);
+ mtcpr(CPR0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(CPR0_CLKUPD, 0x40000000);
+}
+
+#elif defined(PLLMR0_266_160_80)
+
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------------------
+ * | CLK | FREQ (MHz) | DIV RATIO |
+ * ----------------------------------
+ * | CPU | 266.64 | 3 |
+ * | PLB | 159.98 | 5 (0x05)|
+ * | OPB | 79.99 | 10 (0x0A)|
+ * | EBC | 79.99 | 10 (0x0A)|
+ * | SPI | 79.99 | 10 (0x0A)|
+ * | UART0 | 28.57 | 7 (0x07)|
+ * | UART1 | 28.57 | 7 (0x07)|
+ * | DAC | 28.57 | 7 (0xA7)|
+ * | ADC | 4 | 50 (0x32)|
+ * | PWM | 28.57 | 7 (0x07)|
+ * | EMAC | 4 | 50 (0x32)|
+ * -----------------------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(CPR0_PLLC, 0x20000238);
+ mtcpr(CPR0_PLLD, 0x03010400);
+ mtcpr(CPR0_PRIMAD, 0x03050a0a);
+ mtcpr(CPR0_PERC0, 0x00000000);
+ mtcpr(CPR0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(CPR0_PERD1, 0x07323200);
+ mtcpr(CPR0_CLKUP, 0x40000000);
+}
+
+#elif defined(PLLMR0_333_166_83)
+
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------------------
+ * | CLK | FREQ (MHz) | DIV RATIO |
+ * ----------------------------------
+ * | CPU | 333.33 | 2 |
+ * | PLB | 166.66 | 4 (0x04)|
+ * | OPB | 83.33 | 8 (0x08)|
+ * | EBC | 83.33 | 8 (0x08)|
+ * | SPI | 83.33 | 8 (0x08)|
+ * | UART0 | 16.66 | 5 (0x05)|
+ * | UART1 | 16.66 | 5 (0x05)|
+ * | DAC | ???? | 166 (0xA6)|
+ * | ADC | ???? | 166 (0xA6)|
+ * | PWM | 41.66 | 3 (0x03)|
+ * | EMAC | ???? | 3 (0x03)|
+ * -----------------------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(CPR0_PLLC, 0x0000033C);
+ mtcpr(CPR0_PLLD, 0x0a010000);
+ mtcpr(CPR0_PRIMAD, 0x02040808);
+ mtcpr(CPR0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(CPR0_PERD1, 0xA6A60300);
+ mtcpr(CPR0_CLKUP, 0x40000000);
+}
+
+#elif defined(PLLMR0_100_100_12)
+
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------
+ * | CLK | FREQ (MHz) |
+ * ----------------------
+ * | CPU | 100.00 |
+ * | PLB | 100.00 |
+ * | OPB | 12.00 |
+ * | EBC | 49.00 |
+ * ----------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(CPR0_PLLC, 0x000003BC);
+ mtcpr(CPR0_PLLD, 0x06060600);
+ mtcpr(CPR0_PRIMAD, 0x02020004);
+ mtcpr(CPR0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(CPR0_PERD1, 0xC8C81600);
+ mtcpr(CPR0_CLKUP, 0x40000000);
+}
+#endif /* CPU_<speed>_405EZ */
diff --git a/board/amcc/bamboo/Kconfig b/board/amcc/bamboo/Kconfig
new file mode 100644
index 0000000..c0bd40a
--- /dev/null
+++ b/board/amcc/bamboo/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BAMBOO
+
+config SYS_BOARD
+ default "bamboo"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "bamboo"
+
+endif
diff --git a/board/amcc/bamboo/MAINTAINERS b/board/amcc/bamboo/MAINTAINERS
new file mode 100644
index 0000000..4c8929e
--- /dev/null
+++ b/board/amcc/bamboo/MAINTAINERS
@@ -0,0 +1,6 @@
+BAMBOO BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/amcc/bamboo/
+F: include/configs/bamboo.h
+F: configs/bamboo_defconfig
diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile
new file mode 100644
index 0000000..4c0a125
--- /dev/null
+++ b/board/amcc/bamboo/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = bamboo.o flash.o
+extra-y += init.o
diff --git a/board/amcc/bamboo/README b/board/amcc/bamboo/README
new file mode 100644
index 0000000..e139c6d
--- /dev/null
+++ b/board/amcc/bamboo/README
@@ -0,0 +1,77 @@
+The 2 important dipswitches are configured as shown below:
+
+SW1 (for 33MHz SysClk)
+----------------------
+S1 S2 S3 S4 S5 S6 S7 S8
+OFF OFF OFF OFF OFF OFF OFF ON
+
+SW7 (for Op-Code Flash and Boot Option H)
+-----------------------------------------
+S1 S2 S3 S4 S5 S6 S7 S8
+OFF OFF OFF ON OFF OFF OFF OFF
+
+The EEPROM at location 0x52 is loaded with these 16 bytes:
+C47042A6 05D7A190 40082350 0d050000
+
+SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors
+SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB
+SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output
+SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz
+SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor
+SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A
+SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B
+SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B
+SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor
+SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor
+SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0
+SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0
+SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0
+SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer
+SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit
+SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC
+SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled
+SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled
+SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100
+SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled
+SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1
+SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled
+SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC
+SDR0_SDSTP0[NE]: 0 : NDFC: disabled
+SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit
+SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection
+SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size)
+SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled
+SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready
+SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter
+SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC
+SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC
+SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC
+SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC
+SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count
+
+PPC440EP Clocking Configuration
+
+SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz
+OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz
+
+The above information is reported by Eugene O'Brien
+<Eugene.O'Brien@advantechamt.com>. Thanks a lot.
+
+2007-08-06, Stefan Roese <sr@denx.de>
+---------------------------------------------------------------------
+
+The configuration for the AMCC 440EP eval board "Bamboo" was changed
+to only use 384 kbytes of FLASH for the U-Boot image. This way the
+redundant environment can be saved in the remaining 2 sectors of the
+same flash chip.
+
+Caution: With an upgrade from an earlier U-Boot version the current
+environment will be erased since the environment is now saved in
+different sectors. By using the following command the environment can
+be saved after upgrading the U-Boot image and *before* resetting the
+board:
+
+setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \
+ 'cp.b FFF60000 FFF80000 20000'
+
+2006-07-27, Stefan Roese <sr@denx.de>
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
new file mode 100644
index 0000000..c8d0963
--- /dev/null
+++ b/board/amcc/bamboo/bamboo.c
@@ -0,0 +1,1896 @@
+/*
+ * (C) Copyright 2005-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-gpio.h>
+#include <spd_sdram.h>
+#include <asm/ppc440.h>
+#include "bamboo.h"
+
+void ext_bus_cntlr_init(void);
+void configure_ppc440ep_pins(void);
+int is_nand_selected(void);
+
+/*************************************************************************
+ *
+ * Bamboo has one bank onboard sdram (plus DIMM)
+ *
+ * Fixed memory is composed of :
+ * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
+ * 13 row add bits, 10 column add bits (but 12 row used only).
+ * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
+ * 12 row add bits, 10 column add bits.
+ * Prepare a subset (only the used ones) of SPD data
+ *
+ * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
+ * the corresponding bank is divided by 2 due to number of Row addresses
+ * 12 in the ECC module
+ *
+ * Assumes: 64 MB, ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+const unsigned char cfg_simulate_spd_eeprom[128] = {
+ 0x80, /* number of SPD bytes used: 128 */
+ 0x08, /* total number bytes in SPD device = 256 */
+ 0x07, /* DDR ram */
+#ifdef CONFIG_DDR_ECC
+ 0x0C, /* num Row Addr: 12 */
+#else
+ 0x0D, /* num Row Addr: 13 */
+#endif
+ 0x09, /* numColAddr: 9 */
+ 0x01, /* numBanks: 1 */
+ 0x20, /* Module data width: 32 bits */
+ 0x00, /* Module data width continued: +0 */
+ 0x04, /* 2.5 Volt */
+ 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
+ 0x00, /* SDRAM Access from clock */
+#ifdef CONFIG_DDR_ECC
+ 0x02, /* ECC ON : 02 OFF : 00 */
+#else
+ 0x00, /* ECC ON : 02 OFF : 00 */
+#endif
+ 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
+ 0,
+ 0,
+ 0x01, /* wcsbc = 1 */
+ 0,
+ 0,
+ 0x0C, /* casBit (2,2.5) */
+ 0,
+ 0,
+ 0x00, /* not registered: 0 registered : 0x02*/
+ 0,
+ 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
+ 0,
+ 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
+ 0,
+ 0x50, /* tRpNs = 20 ns */
+ 0,
+ 0x50, /* tRcdNs = 20 ns */
+ 45, /* tRasNs */
+#ifdef CONFIG_DDR_ECC
+ 0x08, /* bankSizeID: 32MB */
+#else
+ 0x10, /* bankSizeID: 64MB */
+#endif
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+};
+
+#if 0
+{ /* GPIO Alternate1 Alternate2 Alternate3 */
+ {
+ /* GPIO Core 0 */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
+ { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
+ { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
+ },
+ {
+ /* GPIO Core 1 */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
+ { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
+ }
+};
+#endif
+
+/*----------------------------------------------------------------------------+
+ | EBC Devices Characteristics
+ | Peripheral Bank Access Parameters - EBC0_BnAP
+ | Peripheral Bank Configuration Register - EBC0_BnCR
+ +----------------------------------------------------------------------------*/
+/* Small Flash */
+#define EBC0_BNAP_SMALL_FLASH \
+ EBC0_BNAP_BME_DISABLED | \
+ EBC0_BNAP_TWT_ENCODE(6) | \
+ EBC0_BNAP_CSN_ENCODE(0) | \
+ EBC0_BNAP_OEN_ENCODE(1) | \
+ EBC0_BNAP_WBN_ENCODE(1) | \
+ EBC0_BNAP_WBF_ENCODE(3) | \
+ EBC0_BNAP_TH_ENCODE(1) | \
+ EBC0_BNAP_RE_ENABLED | \
+ EBC0_BNAP_SOR_DELAYED | \
+ EBC0_BNAP_BEM_WRITEONLY | \
+ EBC0_BNAP_PEN_DISABLED
+
+#define EBC0_BNCR_SMALL_FLASH_CS0 \
+ EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_8BIT
+
+#define EBC0_BNCR_SMALL_FLASH_CS4 \
+ EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_8BIT
+
+/* Large Flash or SRAM */
+#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
+ EBC0_BNAP_BME_DISABLED | \
+ EBC0_BNAP_TWT_ENCODE(8) | \
+ EBC0_BNAP_CSN_ENCODE(0) | \
+ EBC0_BNAP_OEN_ENCODE(1) | \
+ EBC0_BNAP_WBN_ENCODE(1) | \
+ EBC0_BNAP_WBF_ENCODE(1) | \
+ EBC0_BNAP_TH_ENCODE(2) | \
+ EBC0_BNAP_SOR_DELAYED | \
+ EBC0_BNAP_BEM_RW | \
+ EBC0_BNAP_PEN_DISABLED
+
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
+ EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
+ EBC0_BNCR_BS_8MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_16BIT
+
+
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
+ EBC0_BNCR_BAS_ENCODE(0x87800000) | \
+ EBC0_BNCR_BS_8MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_16BIT
+
+/* NVRAM - FPGA */
+#define EBC0_BNAP_NVRAM_FPGA \
+ EBC0_BNAP_BME_DISABLED | \
+ EBC0_BNAP_TWT_ENCODE(9) | \
+ EBC0_BNAP_CSN_ENCODE(0) | \
+ EBC0_BNAP_OEN_ENCODE(1) | \
+ EBC0_BNAP_WBN_ENCODE(1) | \
+ EBC0_BNAP_WBF_ENCODE(0) | \
+ EBC0_BNAP_TH_ENCODE(2) | \
+ EBC0_BNAP_RE_ENABLED | \
+ EBC0_BNAP_SOR_DELAYED | \
+ EBC0_BNAP_BEM_WRITEONLY | \
+ EBC0_BNAP_PEN_DISABLED
+
+#define EBC0_BNCR_NVRAM_FPGA_CS5 \
+ EBC0_BNCR_BAS_ENCODE(0x80000000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_8BIT
+
+/* Nand Flash */
+#define EBC0_BNAP_NAND_FLASH \
+ EBC0_BNAP_BME_DISABLED | \
+ EBC0_BNAP_TWT_ENCODE(3) | \
+ EBC0_BNAP_CSN_ENCODE(0) | \
+ EBC0_BNAP_OEN_ENCODE(0) | \
+ EBC0_BNAP_WBN_ENCODE(0) | \
+ EBC0_BNAP_WBF_ENCODE(0) | \
+ EBC0_BNAP_TH_ENCODE(1) | \
+ EBC0_BNAP_RE_ENABLED | \
+ EBC0_BNAP_SOR_NOT_DELAYED | \
+ EBC0_BNAP_BEM_RW | \
+ EBC0_BNAP_PEN_DISABLED
+
+
+#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
+
+/* NAND0 */
+#define EBC0_BNCR_NAND_FLASH_CS1 \
+ EBC0_BNCR_BAS_ENCODE(0x90000000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_32BIT
+/* NAND1 - Bank2 */
+#define EBC0_BNCR_NAND_FLASH_CS2 \
+ EBC0_BNCR_BAS_ENCODE(0x94000000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_32BIT
+
+/* NAND1 - Bank3 */
+#define EBC0_BNCR_NAND_FLASH_CS3 \
+ EBC0_BNCR_BAS_ENCODE(0x94000000) | \
+ EBC0_BNCR_BS_1MB | \
+ EBC0_BNCR_BU_RW | \
+ EBC0_BNCR_BW_32BIT
+
+int board_early_init_f(void)
+{
+ ext_bus_cntlr_init();
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ /*--------------------------------------------------------------------
+ * Setup the GPIO pins
+ *-------------------------------------------------------------------*/
+ out32(GPIO0_OSRL, 0x00000400);
+ out32(GPIO0_OSRH, 0x00000000);
+ out32(GPIO0_TSRL, 0x00000400);
+ out32(GPIO0_TSRH, 0x00000000);
+ out32(GPIO0_ISR1L, 0x00000000);
+ out32(GPIO0_ISR1H, 0x00000000);
+ out32(GPIO0_ISR2L, 0x00000000);
+ out32(GPIO0_ISR2H, 0x00000000);
+ out32(GPIO0_ISR3L, 0x00000000);
+ out32(GPIO0_ISR3H, 0x00000000);
+
+ out32(GPIO1_OSRL, 0x0C380000);
+ out32(GPIO1_OSRH, 0x00000000);
+ out32(GPIO1_TSRL, 0x0C380000);
+ out32(GPIO1_TSRH, 0x00000000);
+ out32(GPIO1_ISR1L, 0x0FC30000);
+ out32(GPIO1_ISR1H, 0x00000000);
+ out32(GPIO1_ISR2L, 0x0C010000);
+ out32(GPIO1_ISR2H, 0x00000000);
+ out32(GPIO1_ISR3L, 0x01400000);
+ out32(GPIO1_ISR3H, 0x00000000);
+
+ configure_ppc440ep_pins();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+
+phys_size_t initdram (int board_type)
+{
+ long dram_size;
+
+ dram_size = spd_sdram();
+
+ return dram_size;
+}
+
+/*----------------------------------------------------------------------------+
+ | is_powerpc440ep_pass1.
+ +----------------------------------------------------------------------------*/
+int is_powerpc440ep_pass1(void)
+{
+ unsigned long pvr;
+
+ pvr = get_pvr();
+
+ if (pvr == PVR_POWERPC_440EP_PASS1)
+ return true;
+ else if (pvr == PVR_POWERPC_440EP_PASS2)
+ return false;
+ else {
+ printf("brdutil error 3\n");
+ for (;;)
+ ;
+ }
+
+ return false;
+}
+
+/*----------------------------------------------------------------------------+
+ | is_nand_selected.
+ +----------------------------------------------------------------------------*/
+int is_nand_selected(void)
+{
+#ifdef CONFIG_BAMBOO_NAND
+ return true;
+#else
+ return false;
+#endif
+}
+
+/*----------------------------------------------------------------------------+
+ | config_on_ebc_cs4_is_small_flash => from EPLD
+ +----------------------------------------------------------------------------*/
+unsigned char config_on_ebc_cs4_is_small_flash(void)
+{
+ /* Not implemented yet => returns constant value */
+ return true;
+}
+
+/*----------------------------------------------------------------------------+
+ | Ext_bus_cntlr_init.
+ | Initialize the external bus controller
+ +----------------------------------------------------------------------------*/
+void ext_bus_cntlr_init(void)
+{
+ unsigned long sdr0_pstrp0, sdr0_sdstp1;
+ unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
+ int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+ unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
+ unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
+ unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
+ unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
+ unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
+
+
+ /*-------------------------------------------------------------------------+
+ |
+ | PART 1 : Initialize EBC Bank 5
+ | ==============================
+ | Bank5 is always associated to the NVRAM/EPLD.
+ | It has to be initialized prior to other banks settings computation since
+ | some board registers values may be needed
+ |
+ +-------------------------------------------------------------------------*/
+ /* NVRAM - FPGA */
+ mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
+ mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
+
+ /*-------------------------------------------------------------------------+
+ |
+ | PART 2 : Determine which boot device was selected
+ | =========================================
+ |
+ | Read Pin Strap Register in PPC440EP
+ | In case of boot from IIC, read Serial Device Strap Register1
+ |
+ | Result can either be :
+ | - Boot from EBC 8bits => SMALL FLASH
+ | - Boot from EBC 16bits => Large Flash or SRAM
+ | - Boot from NAND Flash
+ | - Boot from PCI
+ |
+ +-------------------------------------------------------------------------*/
+ /* Read Pin Strap Register in PPC440EP */
+ mfsdr(SDR0_PINSTP, sdr0_pstrp0);
+ bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
+
+ /*-------------------------------------------------------------------------+
+ | PPC440EP Pass1
+ +-------------------------------------------------------------------------*/
+ if (is_powerpc440ep_pass1() == true) {
+ switch(bootstrap_settings) {
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+ /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
+ /* Boot from Small Flash */
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+ /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
+ /* Boot from PCI */
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+ /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
+ /* Boot from Nand Flash */
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
+ /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
+ /* Boot from Small Flash */
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
+ /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
+ /* Read Serial Device Strap Register1 in PPC440EP */
+ mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
+ boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
+ ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+ switch(boot_selection) {
+ case SDR0_SDSTP1_BOOT_SEL_EBC:
+ switch(ebc_boot_size) {
+ case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+ break;
+ case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ }
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_PCI:
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_NDFC:
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
+ break;
+ }
+ break;
+ }
+ }
+
+ /*-------------------------------------------------------------------------+
+ | PPC440EP Pass2
+ +-------------------------------------------------------------------------*/
+ else {
+ switch(bootstrap_settings) {
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+ /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
+ /* Boot from Small Flash */
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+ /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
+ /* Boot from PCI */
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+ /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
+ /* Boot from Nand Flash */
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
+ /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
+ /* Boot from Large Flash or SRAM */
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
+ /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
+ /* Boot from Large Flash or SRAM */
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
+ /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
+ /* Boot from PCI */
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
+ case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
+ /* Default Strap Settings 5-7 */
+ /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
+ /* Read Serial Device Strap Register1 in PPC440EP */
+ mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
+ boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
+ ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+ switch(boot_selection) {
+ case SDR0_SDSTP1_BOOT_SEL_EBC:
+ switch(ebc_boot_size) {
+ case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+ computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+ break;
+ case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ }
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_PCI:
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_NDFC:
+ computed_boot_device = BOOT_FROM_NAND_FLASH0;
+ break;
+ }
+ break;
+ }
+ }
+
+ /*-------------------------------------------------------------------------+
+ |
+ | PART 3 : Compute EBC settings depending on selected boot device
+ | ====== ======================================================
+ |
+ | Resulting EBC init will be among following configurations :
+ |
+ | - Boot from EBC 8bits => boot from SMALL FLASH selected
+ | EBC-CS0 = Small Flash
+ | EBC-CS1,2,3 = NAND Flash or
+ | Exp.Slot depending on Soft Config
+ | EBC-CS4 = SRAM/Large Flash or
+ | Large Flash/SRAM depending on jumpers
+ | EBC-CS5 = NVRAM / EPLD
+ |
+ | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
+ | EBC-CS0 = SRAM/Large Flash or
+ | Large Flash/SRAM depending on jumpers
+ | EBC-CS1,2,3 = NAND Flash or
+ | Exp.Slot depending on Software Configuration
+ | EBC-CS4 = Small Flash
+ | EBC-CS5 = NVRAM / EPLD
+ |
+ | - Boot from NAND Flash
+ | EBC-CS0 = NAND Flash0
+ | EBC-CS1,2,3 = NAND Flash1
+ | EBC-CS4 = SRAM/Large Flash or
+ | Large Flash/SRAM depending on jumpers
+ | EBC-CS5 = NVRAM / EPLD
+ |
+ | - Boot from PCI
+ | EBC-CS0 = ...
+ | EBC-CS1,2,3 = NAND Flash or
+ | Exp.Slot depending on Software Configuration
+ | EBC-CS4 = SRAM/Large Flash or
+ | Large Flash/SRAM or
+ | Small Flash depending on jumpers
+ | EBC-CS5 = NVRAM / EPLD
+ |
+ +-------------------------------------------------------------------------*/
+
+ switch(computed_boot_device) {
+ /*------------------------------------------------------------------------- */
+ case BOOT_FROM_SMALL_FLASH:
+ /*------------------------------------------------------------------------- */
+ ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
+ ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
+ if ((is_nand_selected()) == true) {
+ /* NAND Flash */
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+ ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ } else {
+ /* Expansion Slot */
+ ebc0_cs1_bnap_value = 0;
+ ebc0_cs1_bncr_value = 0;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ }
+ ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+ ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+
+ break;
+
+ /*------------------------------------------------------------------------- */
+ case BOOT_FROM_LARGE_FLASH_OR_SRAM:
+ /*------------------------------------------------------------------------- */
+ ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+ ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
+ if ((is_nand_selected()) == true) {
+ /* NAND Flash */
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ } else {
+ /* Expansion Slot */
+ ebc0_cs1_bnap_value = 0;
+ ebc0_cs1_bncr_value = 0;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ }
+ ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
+ ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
+
+ break;
+
+ /*------------------------------------------------------------------------- */
+ case BOOT_FROM_NAND_FLASH0:
+ /*------------------------------------------------------------------------- */
+ ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+
+ ebc0_cs1_bnap_value = 0;
+ ebc0_cs1_bncr_value = 0;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+
+ /* Large Flash or SRAM */
+ ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+ ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+
+ break;
+
+ /*------------------------------------------------------------------------- */
+ case BOOT_FROM_PCI:
+ /*------------------------------------------------------------------------- */
+ ebc0_cs0_bnap_value = 0;
+ ebc0_cs0_bncr_value = 0;
+
+ if ((is_nand_selected()) == true) {
+ /* NAND Flash */
+ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+ ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ } else {
+ /* Expansion Slot */
+ ebc0_cs1_bnap_value = 0;
+ ebc0_cs1_bncr_value = 0;
+ ebc0_cs2_bnap_value = 0;
+ ebc0_cs2_bncr_value = 0;
+ ebc0_cs3_bnap_value = 0;
+ ebc0_cs3_bncr_value = 0;
+ }
+
+ if ((config_on_ebc_cs4_is_small_flash()) == true) {
+ /* Small Flash */
+ ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
+ ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
+ } else {
+ /* Large Flash or SRAM */
+ ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+ ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+ }
+
+ break;
+
+ /*------------------------------------------------------------------------- */
+ case BOOT_DEVICE_UNKNOWN:
+ /*------------------------------------------------------------------------- */
+ /* Error */
+ break;
+
+ }
+
+
+ /*-------------------------------------------------------------------------+
+ | Initialize EBC CONFIG
+ +-------------------------------------------------------------------------*/
+ mtdcr(EBC0_CFGADDR, EBC0_CFG);
+ mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN |
+ EBC0_CFG_PTD_ENABLED |
+ EBC0_CFG_RTC_2048PERCLK |
+ EBC0_CFG_EMPL_LOW |
+ EBC0_CFG_EMPH_LOW |
+ EBC0_CFG_CSTC_DRIVEN |
+ EBC0_CFG_BPF_ONEDW |
+ EBC0_CFG_EMS_8BIT |
+ EBC0_CFG_PME_DISABLED |
+ EBC0_CFG_PMT_ENCODE(0) );
+
+ /*-------------------------------------------------------------------------+
+ | Initialize EBC Bank 0-4
+ +-------------------------------------------------------------------------*/
+ /* EBC Bank0 */
+ mtebc(PB0AP, ebc0_cs0_bnap_value);
+ mtebc(PB0CR, ebc0_cs0_bncr_value);
+ /* EBC Bank1 */
+ mtebc(PB1AP, ebc0_cs1_bnap_value);
+ mtebc(PB1CR, ebc0_cs1_bncr_value);
+ /* EBC Bank2 */
+ mtebc(PB2AP, ebc0_cs2_bnap_value);
+ mtebc(PB2CR, ebc0_cs2_bncr_value);
+ /* EBC Bank3 */
+ mtebc(PB3AP, ebc0_cs3_bnap_value);
+ mtebc(PB3CR, ebc0_cs3_bncr_value);
+ /* EBC Bank4 */
+ mtebc(PB4AP, ebc0_cs4_bnap_value);
+ mtebc(PB4CR, ebc0_cs4_bncr_value);
+
+ return;
+}
+
+
+/*----------------------------------------------------------------------------+
+ | get_uart_configuration.
+ +----------------------------------------------------------------------------*/
+uart_config_nb_t get_uart_configuration(void)
+{
+ return (L4);
+}
+
+/*----------------------------------------------------------------------------+
+ | set_phy_configuration_through_fpga => to EPLD
+ +----------------------------------------------------------------------------*/
+void set_phy_configuration_through_fpga(zmii_config_t config)
+{
+
+ unsigned long fpga_selection_reg;
+
+ fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
+
+ switch(config)
+ {
+ case ZMII_CONFIGURATION_IS_MII:
+ fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
+ break;
+ case ZMII_CONFIGURATION_IS_RMII:
+ fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
+ break;
+ case ZMII_CONFIGURATION_IS_SMII:
+ fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
+ break;
+ case ZMII_CONFIGURATION_UNKNOWN:
+ default:
+ break;
+ }
+ out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
+
+}
+
+/*----------------------------------------------------------------------------+
+ | scp_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void scp_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
+ fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | iic1_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void iic1_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
+ fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | dma_a_b_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void dma_a_b_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | dma_a_b_unselect_in_fpga.
+ +----------------------------------------------------------------------------*/
+void dma_a_b_unselect_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | dma_c_d_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void dma_c_d_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | dma_c_d_unselect_in_fpga.
+ +----------------------------------------------------------------------------*/
+void dma_c_d_unselect_in_fpga(void)
+{
+ unsigned long fpga_selection_2_reg;
+
+ fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
+ out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | usb2_device_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void usb2_device_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_1_reg;
+
+ fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
+ out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | usb2_device_reset_through_fpga.
+ +----------------------------------------------------------------------------*/
+void usb2_device_reset_through_fpga(void)
+{
+ /* Perform soft Reset pulse */
+ unsigned long fpga_reset_reg;
+ int i;
+
+ fpga_reset_reg = in8(FPGA_RESET_REG);
+ out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
+ for (i=0; i<500; i++)
+ udelay(1000);
+ out8(FPGA_RESET_REG,fpga_reset_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | usb2_host_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void usb2_host_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_1_reg;
+
+ fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
+ out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | ndfc_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void ndfc_selection_in_fpga(void)
+{
+ unsigned long fpga_selection_1_reg;
+
+ fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
+ fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
+ fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
+ out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+ | uart_selection_in_fpga.
+ +----------------------------------------------------------------------------*/
+void uart_selection_in_fpga(uart_config_nb_t uart_config)
+{
+ /* FPGA register */
+ unsigned char fpga_selection_3_reg;
+
+ /* Read FPGA Reagister */
+ fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
+
+ switch (uart_config)
+ {
+ case L1:
+ /* ----------------------------------------------------------------------- */
+ /* L1 configuration: UART0 = 8 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Configure FPGA */
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+ break;
+
+ case L2:
+ /* ----------------------------------------------------------------------- */
+ /* L2 configuration: UART0 = 4 pins */
+ /* UART1 = 4 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Configure FPGA */
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+ break;
+
+ case L3:
+ /* ----------------------------------------------------------------------- */
+ /* L3 configuration: UART0 = 4 pins */
+ /* UART1 = 2 pins */
+ /* UART2 = 2 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Configure FPGA */
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+ break;
+
+ case L4:
+ /* Configure FPGA */
+ fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+ fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
+ out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+ break;
+
+ default:
+ /* Unsupported UART configuration number */
+ for (;;)
+ ;
+ break;
+
+ }
+}
+
+
+/*----------------------------------------------------------------------------+
+ | init_default_gpio
+ +----------------------------------------------------------------------------*/
+void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+ int i;
+
+ /* Init GPIO0 */
+ for(i=0; i<GPIO_MAX; i++)
+ {
+ gpio_tab[GPIO0][i].add = GPIO0_BASE;
+ gpio_tab[GPIO0][i].in_out = GPIO_DIS;
+ gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
+ }
+
+ /* Init GPIO1 */
+ for(i=0; i<GPIO_MAX; i++)
+ {
+ gpio_tab[GPIO1][i].add = GPIO1_BASE;
+ gpio_tab[GPIO1][i].in_out = GPIO_DIS;
+ gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
+ }
+
+ /* EBC_CS_N(5) - GPIO0_10 */
+ gpio_tab[GPIO0][10].in_out = GPIO_OUT;
+ gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
+
+ /* EBC_CS_N(4) - GPIO0_9 */
+ gpio_tab[GPIO0][9].in_out = GPIO_OUT;
+ gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_uart_ios
+ +------------------------------------------------------------------------------
+ |
+ | Set UART Configuration in PowerPC440EP
+ |
+ | +---------------------------------------------------------------------+
+ | | Configuartion | Connector | Nb of pins | Pins | Associated |
+ | | Number | Port Name | available | naming | CORE |
+ | +-----------------+---------------+------------+--------+-------------+
+ | | L1 | Port_A | 8 | UART | UART core 0 |
+ | +-----------------+---------------+------------+--------+-------------+
+ | | L2 | Port_A | 4 | UART1 | UART core 0 |
+ | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
+ | +-----------------+---------------+------------+--------+-------------+
+ | | L3 | Port_A | 4 | UART1 | UART core 0 |
+ | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
+ | | | Port_C | 2 | UART3 | UART core 2 |
+ | +-----------------+---------------+------------+--------+-------------+
+ | | | Port_A | 2 | UART1 | UART core 0 |
+ | | L4 | Port_B | 2 | UART2 | UART core 1 |
+ | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
+ | | | Port_D | 2 | UART4 | UART core 3 |
+ | +-----------------+---------------+------------+--------+-------------+
+ |
+ | Involved GPIOs
+ |
+ | +------------------------------------------------------------------------------+
+ | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
+ | +---------+------------------+-----+-----------------+-----+-------------+-----+
+ | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
+ | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
+ | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
+ | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
+ | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
+ | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
+ | +------------------------------------------------------------------------------+
+ |
+ |
+ +----------------------------------------------------------------------------*/
+
+void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+ switch (uart_config)
+ {
+ case L1:
+ /* ----------------------------------------------------------------------- */
+ /* L1 configuration: UART0 = 8 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO1][2].in_out = GPIO_IN;
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][3].in_out = GPIO_IN;
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
+
+ break;
+
+ case L2:
+ /* ----------------------------------------------------------------------- */
+ /* L2 configuration: UART0 = 4 pins */
+ /* UART1 = 4 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO1][2].in_out = GPIO_IN;
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][3].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+ break;
+
+ case L3:
+ /* ----------------------------------------------------------------------- */
+ /* L3 configuration: UART0 = 4 pins */
+ /* UART1 = 2 pins */
+ /* UART2 = 2 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO1][2].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][3].in_out = GPIO_IN;
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+ break;
+
+ case L4:
+ /* ----------------------------------------------------------------------- */
+ /* L4 configuration: UART0 = 2 pins */
+ /* UART1 = 2 pins */
+ /* UART2 = 2 pins */
+ /* UART3 = 2 pins */
+ /* ----------------------------------------------------------------------- */
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO1][2].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][3].in_out = GPIO_IN;
+ gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][4].in_out = GPIO_IN;
+ gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
+
+ gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+ gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][7].in_out = GPIO_IN;
+ gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+ break;
+
+ default:
+ /* Unsupported UART configuration number */
+ printf("ERROR - Unsupported UART configuration number.\n\n");
+ for (;;)
+ ;
+ break;
+
+ }
+
+ /* Set input Selection Register on Alt_Receive for UART Input Core */
+ out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
+ out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
+ out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
+}
+
+/*----------------------------------------------------------------------------+
+ | update_ndfc_ios(void).
+ +----------------------------------------------------------------------------*/
+void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
+ gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
+ gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
+
+#if 0
+ gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
+ gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
+#endif
+}
+
+/*----------------------------------------------------------------------------+
+ | update_zii_ios(void).
+ +----------------------------------------------------------------------------*/
+void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+ /* Update GPIO Configuration Table */
+ gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
+ gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
+ gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
+ gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
+ gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
+ gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
+ gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
+ gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
+ gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
+ gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
+ gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
+ gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
+ gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
+ gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
+ gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | update_uic_0_3_irq_ios().
+ +----------------------------------------------------------------------------*/
+void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+ gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
+ gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
+ gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
+ gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
+ gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_uic_4_9_irq_ios().
+ +----------------------------------------------------------------------------*/
+void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+ gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
+ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
+ gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
+ gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
+ gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
+ gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_dma_a_b_ios().
+ +----------------------------------------------------------------------------*/
+void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+ gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
+ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
+ gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
+ gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
+ gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
+ gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_dma_c_d_ios().
+ +----------------------------------------------------------------------------*/
+void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+ gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
+ gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
+ gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
+ gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
+ gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
+ gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
+ gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | update_ebc_master_ios().
+ +----------------------------------------------------------------------------*/
+void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+ gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
+ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
+ gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
+ gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | update_usb2_device_ios().
+ +----------------------------------------------------------------------------*/
+void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+ gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
+ gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
+ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
+ gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
+ gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
+ gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
+
+ gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
+ gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
+
+ gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
+ gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | update_pci_patch_ios().
+ +----------------------------------------------------------------------------*/
+void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+ gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
+ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+ | set_chip_gpio_configuration(unsigned char gpio_core,
+ | gpio_param_s (*gpio_tab)[GPIO_MAX])
+ | Put the core impacted by clock modification and sharing in reset.
+ | Config the select registers to resolve the sharing depending of the config.
+ | Configure the GPIO registers.
+ |
+ +----------------------------------------------------------------------------*/
+void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
+{
+ unsigned char i=0, j=0, reg_offset = 0;
+ unsigned long gpio_reg, gpio_core_add;
+
+ /* GPIO config of the GPIOs 0 to 31 */
+ for (i=0; i<GPIO_MAX; i++, j++)
+ {
+ if (i == GPIO_MAX/2)
+ {
+ reg_offset = 4;
+ j = i-16;
+ }
+
+ gpio_core_add = gpio_tab[gpio_core][i].add;
+
+ if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
+ (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
+ {
+ switch (gpio_tab[gpio_core][i].alt_nb)
+ {
+ case GPIO_SEL:
+ break;
+
+ case GPIO_ALT1:
+ gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+ out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
+ break;
+
+ case GPIO_ALT2:
+ gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+ out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
+ break;
+
+ case GPIO_ALT3:
+ gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+ out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ }
+ }
+ if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
+ (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
+ {
+
+ switch (gpio_tab[gpio_core][i].alt_nb)
+ {
+ case GPIO_SEL:
+ break;
+ case GPIO_ALT1:
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ case GPIO_ALT2:
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ case GPIO_ALT3:
+ gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+ out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+ gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+ gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+ out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+ break;
+ }
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------+
+ | force_bup_core_selection.
+ +----------------------------------------------------------------------------*/
+void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
+{
+ /* Pointer invalid */
+ if (core_select_P == NULL)
+ {
+ printf("Configuration invalid pointer 1\n");
+ for (;;)
+ ;
+ }
+
+ /* L4 Selection */
+ *(core_select_P+UART_CORE0) = CORE_SELECTED;
+ *(core_select_P+UART_CORE1) = CORE_SELECTED;
+ *(core_select_P+UART_CORE2) = CORE_SELECTED;
+ *(core_select_P+UART_CORE3) = CORE_SELECTED;
+
+ /* RMII Selection */
+ *(core_select_P+RMII_SEL) = CORE_SELECTED;
+
+ /* External Interrupt 0-9 selection */
+ *(core_select_P+UIC_0_3) = CORE_SELECTED;
+ *(core_select_P+UIC_4_9) = CORE_SELECTED;
+
+ *(core_select_P+SCP_CORE) = CORE_SELECTED;
+ *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
+ *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
+ *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
+
+ if (is_nand_selected()) {
+ *(core_select_P+NAND_FLASH) = CORE_SELECTED;
+ }
+
+ *config_val_P = CONFIG_IS_VALID;
+
+}
+
+/*----------------------------------------------------------------------------+
+ | configure_ppc440ep_pins.
+ +----------------------------------------------------------------------------*/
+void configure_ppc440ep_pins(void)
+{
+ uart_config_nb_t uart_configuration;
+ config_validity_t config_val = CONFIG_IS_INVALID;
+
+ /* Create Core Selection Table */
+ core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
+ {
+ CORE_NOT_SELECTED, /* IIC_CORE, */
+ CORE_NOT_SELECTED, /* SPC_CORE, */
+ CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
+ CORE_NOT_SELECTED, /* UIC_4_9, */
+ CORE_NOT_SELECTED, /* USB2_HOST, */
+ CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
+ CORE_NOT_SELECTED, /* USB2_DEVICE, */
+ CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
+ CORE_NOT_SELECTED, /* USB1_DEVICE, */
+ CORE_NOT_SELECTED, /* EBC_MASTER, */
+ CORE_NOT_SELECTED, /* NAND_FLASH, */
+ CORE_NOT_SELECTED, /* UART_CORE0, */
+ CORE_NOT_SELECTED, /* UART_CORE1, */
+ CORE_NOT_SELECTED, /* UART_CORE2, */
+ CORE_NOT_SELECTED, /* UART_CORE3, */
+ CORE_NOT_SELECTED, /* MII_SEL, */
+ CORE_NOT_SELECTED, /* RMII_SEL, */
+ CORE_NOT_SELECTED, /* SMII_SEL, */
+ CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
+ CORE_NOT_SELECTED, /* UIC_0_3 */
+ CORE_NOT_SELECTED, /* USB1_HOST */
+ CORE_NOT_SELECTED /* PCI_PATCH */
+ };
+
+ gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
+
+ /* Table Default Initialisation + FPGA Access */
+ init_default_gpio(gpio_tab);
+ set_chip_gpio_configuration(GPIO0, gpio_tab);
+ set_chip_gpio_configuration(GPIO1, gpio_tab);
+
+ /* Update Table */
+ force_bup_core_selection(ppc440ep_core_selection, &config_val);
+#if 0 /* test-only */
+ /* If we are running PIBS 1, force known configuration */
+ update_core_selection_table(ppc440ep_core_selection, &config_val);
+#endif
+
+ /*----------------------------------------------------------------------------+
+ | SDR + ios table update + fpga initialization
+ +----------------------------------------------------------------------------*/
+ unsigned long sdr0_pfc1 = 0;
+ unsigned long sdr0_usb0 = 0;
+ unsigned long sdr0_mfr = 0;
+
+ /* PCI Always selected */
+
+ /* I2C Selection */
+ if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+ iic1_selection_in_fpga();
+ }
+
+ /* SCP Selection */
+ if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
+ scp_selection_in_fpga();
+ }
+
+ /* UIC 0:3 Selection */
+ if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
+ {
+ update_uic_0_3_irq_ios(gpio_tab);
+ dma_a_b_unselect_in_fpga();
+ }
+
+ /* UIC 4:9 Selection */
+ if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
+ update_uic_4_9_irq_ios(gpio_tab);
+ }
+
+ /* DMA AB Selection */
+ if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
+ update_dma_a_b_ios(gpio_tab);
+ dma_a_b_selection_in_fpga();
+ }
+
+ /* DMA CD Selection */
+ if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
+ {
+ update_dma_c_d_ios(gpio_tab);
+ dma_c_d_selection_in_fpga();
+ }
+
+ /* EBC Master Selection */
+ if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
+ update_ebc_master_ios(gpio_tab);
+ }
+
+ /* PCI Patch Enable */
+ if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
+ {
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
+ update_pci_patch_ios(gpio_tab);
+ }
+
+ /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
+ if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
+ {
+ /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
+ printf("Invalid configuration => USB2 Host selected\n");
+ for (;;)
+ ;
+ /*usb2_host_selection_in_fpga(); */
+ }
+
+ /* USB2.0 Device Selection */
+ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
+ {
+ update_usb2_device_ios(gpio_tab);
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
+
+ mfsdr(SDR0_USB0, sdr0_usb0);
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
+ mtsdr(SDR0_USB0, sdr0_usb0);
+
+ usb2_device_selection_in_fpga();
+ }
+
+ /* USB1.1 Device Selection */
+ if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
+ {
+ mfsdr(SDR0_USB0, sdr0_usb0);
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
+ mtsdr(SDR0_USB0, sdr0_usb0);
+ }
+
+ /* USB1.1 Host Selection */
+ if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
+ {
+ mfsdr(SDR0_USB0, sdr0_usb0);
+ sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
+ sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
+ mtsdr(SDR0_USB0, sdr0_usb0);
+ }
+
+ /* NAND Flash Selection */
+ if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
+ {
+ update_ndfc_ios(gpio_tab);
+ mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ SDR0_CUST0_CHIPSELGAT_EN1 |
+ SDR0_CUST0_CHIPSELGAT_EN2);
+ ndfc_selection_in_fpga();
+ }
+ else
+ {
+ /* Set Mux on EMAC */
+ mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
+ }
+
+ /* MII Selection */
+ if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
+ {
+ update_zii_ios(gpio_tab);
+ mfsdr(SDR0_MFR, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
+ mtsdr(SDR0_MFR, sdr0_mfr);
+
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
+ }
+
+ /* RMII Selection */
+ if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
+ {
+ update_zii_ios(gpio_tab);
+ mfsdr(SDR0_MFR, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
+ mtsdr(SDR0_MFR, sdr0_mfr);
+
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
+ }
+
+ /* SMII Selection */
+ if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
+ {
+ update_zii_ios(gpio_tab);
+ mfsdr(SDR0_MFR, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
+ mtsdr(SDR0_MFR, sdr0_mfr);
+
+ set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
+ }
+
+ /* UART Selection */
+ uart_configuration = get_uart_configuration();
+ switch (uart_configuration)
+ {
+ case L1: /* L1 Selection */
+ /* UART0 8 pins Only */
+ /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
+ break;
+ case L2: /* L2 Selection */
+ /* UART0 and UART1 4 pins */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ break;
+ case L3: /* L3 Selection */
+ /* UART0 4 pins, UART1 and UART2 2 pins */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ break;
+ case L4: /* L4 Selection */
+ /* UART0, UART1, UART2 and UART3 2 pins */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+ break;
+ }
+ update_uart_ios(uart_configuration, gpio_tab);
+
+ /* UART Selection in all cases */
+ uart_selection_in_fpga(uart_configuration);
+
+ /* Packet Reject Function Available */
+ if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
+ {
+ /* Set UPR Bit in SDR0_PFC1 Register */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
+ }
+
+ /* Packet Reject Function Enable */
+ if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
+ {
+ mfsdr(SDR0_MFR, sdr0_mfr);
+ sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
+ mtsdr(SDR0_MFR, sdr0_mfr);
+ }
+
+ /* Perform effective access to hardware */
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ set_chip_gpio_configuration(GPIO0, gpio_tab);
+ set_chip_gpio_configuration(GPIO1, gpio_tab);
+
+ /* USB2.0 Device Reset must be done after GPIO setting */
+ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
+ usb2_device_reset_through_fpga();
+
+}
diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h
new file mode 100644
index 0000000..49f200a
--- /dev/null
+++ b/board/amcc/bamboo/bamboo.h
@@ -0,0 +1,348 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*----------------------------------------------------------------------------+
+ | FPGA registers and bit definitions
+ +----------------------------------------------------------------------------*/
+/*
+ * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
+ * TLB initialization makes it correspond to logical address 0x80001FF0.
+ * => Done init_chip.s in bootlib
+ */
+#define FPGA_BASE_ADDR 0x80002000
+
+/*----------------------------------------------------------------------------+
+ | Board Jumpers Setting Register
+ | Board Settings provided by jumpers
+ +----------------------------------------------------------------------------*/
+#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3)
+/* Boot from small flash */
+#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80
+/* Operational Flash versus SRAM position in Memory Map */
+#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40
+#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40
+#define FPGA_SET_REG_SRAM_ABOVE 0x00
+/* Boot From NAND Flash */
+#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40
+#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00
+/* On Board PCI Arbiter Select */
+#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10
+#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00
+
+/*----------------------------------------------------------------------------+
+ | Functions Selection Register 1
+ +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4)
+#define FPGA_SEL_1_REG_PHY_MASK 0xE0
+#define FPGA_SEL_1_REG_MII 0x80
+#define FPGA_SEL_1_REG_RMII 0x40
+#define FPGA_SEL_1_REG_SMII 0x20
+#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */
+#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */
+#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */
+#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */
+#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */
+#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */
+
+/*----------------------------------------------------------------------------+
+ | Functions Selection Register 2
+ +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5)
+#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */
+#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */
+#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */
+#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */
+#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */
+#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */
+#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */
+ /* 1 = TC - output from 440EP */
+#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */
+ /* 1 = TC (output from 440EP) */
+#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */
+#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */
+#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */
+
+/*----------------------------------------------------------------------------+
+ | Functions Selection Register 3
+ +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6)
+#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */
+#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70
+#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */
+#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */
+#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */
+#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */
+#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */
+#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */
+
+/*----------------------------------------------------------------------------+
+ | Soft Reset Register
+ +----------------------------------------------------------------------------*/
+#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7)
+#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */
+#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */
+#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */
+#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */
+#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */
+#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */
+
+
+/*----------------------------------------------------------------------------+
+| SDR Configuration registers
++----------------------------------------------------------------------------*/
+#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */
+#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */
+#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */
+#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
+
+#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */
+#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
+#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */
+#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */
+
+/* Serial Device Enabled - Addr = 0xA8 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
+/* Serial Device Enabled - Addr = 0xA4 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
+
+/* Pin Straps Reg */
+#define SDR0_PSTRP0 0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
+
+/*----------------------------------------------------------------------------+
+| EBC Configuration Register - EBC0_CFG
++----------------------------------------------------------------------------*/
+/* External Bus Three-State Control */
+#define EBC0_CFG_EBTC_DRIVEN 0x80000000
+/* Device-Paced Time-out Disable */
+#define EBC0_CFG_PTD_ENABLED 0x00000000
+/* Ready Timeout Count */
+#define EBC0_CFG_RTC_MASK 0x38000000
+#define EBC0_CFG_RTC_16PERCLK 0x00000000
+#define EBC0_CFG_RTC_32PERCLK 0x08000000
+#define EBC0_CFG_RTC_64PERCLK 0x10000000
+#define EBC0_CFG_RTC_128PERCLK 0x18000000
+#define EBC0_CFG_RTC_256PERCLK 0x20000000
+#define EBC0_CFG_RTC_512PERCLK 0x28000000
+#define EBC0_CFG_RTC_1024PERCLK 0x30000000
+#define EBC0_CFG_RTC_2048PERCLK 0x38000000
+/* External Master Priority Low */
+#define EBC0_CFG_EMPL_LOW 0x00000000
+#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
+#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
+#define EBC0_CFG_EMPL_HIGH 0x06000000
+/* External Master Priority High */
+#define EBC0_CFG_EMPH_LOW 0x00000000
+#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
+#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
+#define EBC0_CFG_EMPH_HIGH 0x01800000
+/* Chip Select Three-State Control */
+#define EBC0_CFG_CSTC_DRIVEN 0x00400000
+/* Burst Prefetch */
+#define EBC0_CFG_BPF_ONEDW 0x00000000
+#define EBC0_CFG_BPF_TWODW 0x00100000
+#define EBC0_CFG_BPF_FOURDW 0x00200000
+/* External Master Size */
+#define EBC0_CFG_EMS_8BIT 0x00000000
+/* Power Management Enable */
+#define EBC0_CFG_PME_DISABLED 0x00000000
+#define EBC0_CFG_PME_ENABLED 0x00020000
+/* Power Management Timer */
+#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
+
+/*----------------------------------------------------------------------------+
+| Peripheral Bank Configuration Register - EBC0_BnCR
++----------------------------------------------------------------------------*/
+/* BAS - Base Address Select */
+#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
+/* BS - Bank Size */
+#define EBC0_BNCR_BS_MASK 0x000E0000
+#define EBC0_BNCR_BS_1MB 0x00000000
+#define EBC0_BNCR_BS_2MB 0x00020000
+#define EBC0_BNCR_BS_4MB 0x00040000
+#define EBC0_BNCR_BS_8MB 0x00060000
+#define EBC0_BNCR_BS_16MB 0x00080000
+#define EBC0_BNCR_BS_32MB 0x000A0000
+#define EBC0_BNCR_BS_64MB 0x000C0000
+#define EBC0_BNCR_BS_128MB 0x000E0000
+/* BU - Bank Usage */
+#define EBC0_BNCR_BU_MASK 0x00018000
+#define EBC0_BNCR_BU_RO 0x00008000
+#define EBC0_BNCR_BU_WO 0x00010000
+#define EBC0_BNCR_BU_RW 0x00018000
+/* BW - Bus Width */
+#define EBC0_BNCR_BW_MASK 0x00006000
+#define EBC0_BNCR_BW_8BIT 0x00000000
+#define EBC0_BNCR_BW_16BIT 0x00002000
+#define EBC0_BNCR_BW_32BIT 0x00004000
+
+/*----------------------------------------------------------------------------+
+| Peripheral Bank Access Parameters - EBC0_BnAP
++----------------------------------------------------------------------------*/
+/* Burst Mode Enable */
+#define EBC0_BNAP_BME_ENABLED 0x80000000
+#define EBC0_BNAP_BME_DISABLED 0x00000000
+/* Transfert Wait */
+#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */
+/* Chip Select On Timing */
+#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */
+/* Output Enable On Timing */
+#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */
+/* Write Back Enable On Timing */
+#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */
+/* Write Back Enable Off Timing */
+#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */
+/* Transfert Hold */
+#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */
+/* PerReady Enable */
+#define EBC0_BNAP_RE_ENABLED 0x00000100
+#define EBC0_BNAP_RE_DISABLED 0x00000000
+/* Sample On Ready */
+#define EBC0_BNAP_SOR_DELAYED 0x00000000
+#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080
+/* Byte Enable Mode */
+#define EBC0_BNAP_BEM_WRITEONLY 0x00000000
+#define EBC0_BNAP_BEM_RW 0x00000040
+/* Parity Enable */
+#define EBC0_BNAP_PEN_DISABLED 0x00000000
+#define EBC0_BNAP_PEN_ENABLED 0x00000020
+
+/*----------------------------------------------------------------------------+
+| Define Boot devices
++----------------------------------------------------------------------------*/
+/* */
+#define BOOT_FROM_SMALL_FLASH 0x00
+#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
+#define BOOT_FROM_NAND_FLASH0 0x02
+#define BOOT_FROM_PCI 0x03
+#define BOOT_DEVICE_UNKNOWN 0x04
+
+
+#define PVR_POWERPC_440EP_PASS1 0x42221850
+#define PVR_POWERPC_440EP_PASS2 0x422218D3
+
+#define GPIO0 0
+#define GPIO1 1
+
+/*#define MAX_SELECTION_NB CORE_NB */
+#define MAX_CORE_SELECT_NB 22
+
+/*----------------------------------------------------------------------------+
+ | PPC440EP GPIOs addresses.
+ +----------------------------------------------------------------------------*/
+#define GPIO0_REAL 0xEF600B00
+
+#define GPIO1_REAL 0xEF600C00
+
+/* Offsets */
+#define GPIOx_OR 0x00 /* GPIO Output Register */
+#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
+#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
+#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
+#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
+#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
+#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
+#define GPIOx_IR 0x1C /* GPIO Input Register */
+#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
+#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
+#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
+#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
+#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
+#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
+#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
+#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
+#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
+
+/* GPIO0 */
+#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L)
+#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H)
+#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L)
+#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H)
+#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L)
+#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L)
+
+/* GPIO1 */
+#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L)
+#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H)
+#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L)
+#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H)
+#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L)
+#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L)
+
+#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
+#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
+#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
+#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
+#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
+
+
+/*----------------------------------------------------------------------------+
+ | XX XX
+ |
+ | XXXXXX XXX XX XXX XXX
+ | XX XX X XX XX XX
+ | XX XX X XX XX XX
+ | XX XX XX XX XX
+ | XXXXXX XXX XXX XXXX XXXX
+ +----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+ | Defines
+ +----------------------------------------------------------------------------*/
+typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
+ ZMII_CONFIGURATION_IS_MII,
+ ZMII_CONFIGURATION_IS_RMII,
+ ZMII_CONFIGURATION_IS_SMII
+} zmii_config_t;
+
+/*----------------------------------------------------------------------------+
+ | Declare Configuration values
+ +----------------------------------------------------------------------------*/
+typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
+typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
+typedef enum config_list { IIC_CORE,
+ SCP_CORE,
+ DMA_CHANNEL_AB,
+ UIC_4_9,
+ USB2_HOST,
+ DMA_CHANNEL_CD,
+ USB2_DEVICE,
+ PACKET_REJ_FUNC_AVAIL,
+ USB1_DEVICE,
+ EBC_MASTER,
+ NAND_FLASH,
+ UART_CORE0,
+ UART_CORE1,
+ UART_CORE2,
+ UART_CORE3,
+ MII_SEL,
+ RMII_SEL,
+ SMII_SEL,
+ PACKET_REJ_FUNC_EN,
+ UIC_0_3,
+ USB1_HOST,
+ PCI_PATCH,
+ CORE_NB
+} core_list_t;
+
+typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5,
+ B3_V6, B3_V7, B3_V8, B3_V9, B3_V10,
+ B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
+ B3_V16, B3_VALUE_UNKNOWN
+} block3_value_t;
+
+typedef enum config_validity { CONFIG_IS_VALID,
+ CONFIG_IS_INVALID
+} config_validity_t;
diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk
new file mode 100644
index 0000000..9cb071e
--- /dev/null
+++ b/board/amcc/bamboo/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2002-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c
new file mode 100644
index 0000000..6dbe09f
--- /dev/null
+++ b/board/amcc/bamboo/flash.c
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/ppc440.h>
+#include "bamboo.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
+ */
+static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
+ {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
+ {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
+ {0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash */
+ {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
+ {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
+ {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
+ {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */
+ {0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+ unsigned short index = 0;
+ int i;
+ unsigned long val;
+ unsigned long ebc_boot_size;
+ unsigned long boot_selection;
+
+ mfsdr(SDR0_PINSTP, val);
+ index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29;
+
+ if ((index == 5) || (index == 7)) {
+ /*
+ * Boot Settings in IIC EEprom address 0xA8 or 0xA4
+ * Read Serial Device Strap Register1 in PPC440EP
+ */
+ mfsdr(SDR0_SDSTP1, val);
+ boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
+ ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+ switch(boot_selection) {
+ case SDR0_SDSTP1_BOOT_SEL_EBC:
+ switch(ebc_boot_size) {
+ case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+ index = 3;
+ break;
+ case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+ index = 0;
+ break;
+ }
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_PCI:
+ index = 1;
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_NDFC:
+ index = 2;
+ break;
+ }
+ } else if (index == 0) {
+ if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) {
+ index = 8; /* sram below op code flash -> new index 8 */
+ }
+ }
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0)
+ continue;
+
+ DEBUGF("Detection bank %d...\n", i);
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+ &flash_info[i]);
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR_REDUND)
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#endif
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
new file mode 100644
index 0000000..5c7c839
--- /dev/null
+++ b/board/amcc/bamboo/init.S
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
+
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
+
+ /* PCI base & peripherals */
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I)
+ tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I)
+
+ /* PCI */
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG)
+
+ /* USB 2.0 Device */
+ tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
+
+ tlbtab_end
diff --git a/board/amcc/bubinga/Kconfig b/board/amcc/bubinga/Kconfig
new file mode 100644
index 0000000..540d9b6
--- /dev/null
+++ b/board/amcc/bubinga/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BUBINGA
+
+config SYS_BOARD
+ default "bubinga"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "bubinga"
+
+endif
diff --git a/board/amcc/bubinga/MAINTAINERS b/board/amcc/bubinga/MAINTAINERS
new file mode 100644
index 0000000..3299cc3
--- /dev/null
+++ b/board/amcc/bubinga/MAINTAINERS
@@ -0,0 +1,6 @@
+BUBINGA BOARD
+#M: -
+S: Maintained
+F: board/amcc/bubinga/
+F: include/configs/bubinga.h
+F: configs/bubinga_defconfig
diff --git a/board/amcc/bubinga/Makefile b/board/amcc/bubinga/Makefile
new file mode 100644
index 0000000..0e7ebca
--- /dev/null
+++ b/board/amcc/bubinga/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = bubinga.o flash.o
diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c
new file mode 100644
index 0000000..5c1e071
--- /dev/null
+++ b/board/amcc/bubinga/bubinga.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+long int spd_sdram(void);
+
+int board_early_init_f(void)
+{
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000010);
+ mtdcr(UIC0PR, 0xFFFF7FF0); /* set int polarities */
+ mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * Configure CPC0_PCI to enable PerWE as output
+ * and enable the internal PCI arbiter if selected
+ */
+ if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
+ mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
+ else
+ mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ puts("Board: Bubinga - AMCC PPC405EP Evaluation Board");
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+/* -------------------------------------------------------------------------
+ initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ the necessary info for SDRAM controller configuration
+ ------------------------------------------------------------------------- */
+phys_size_t initdram(int board_type)
+{
+ long int ret;
+
+ ret = spd_sdram();
+ return ret;
+}
diff --git a/board/amcc/bubinga/flash.c b/board/amcc/bubinga/flash.c
new file mode 100644
index 0000000..a9d0ed8
--- /dev/null
+++ b/board/amcc/bubinga/flash.c
@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+ uint pbcr;
+ unsigned long base_b0, base_b1;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 =
+ flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ /* Only one bank */
+ if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
+ /* Setup offsets */
+ flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+ &flash_info[0]);
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ size_b1 = 0;
+ flash_info[0].size = size_b0;
+ }
+
+ /* 2 banks */
+ else {
+ size_b1 =
+ flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
+ &flash_info[1]);
+
+ /* Re-do sizing to get full correct info */
+
+ if (size_b1) {
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b1 = -size_b1;
+ pbcr = (pbcr & 0x0001ffff) | base_b1 |
+ (((size_b1 / 1024 / 1024) - 1) << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+ /* printf("PB1CR = %x\n", pbcr); */
+ }
+
+ if (size_b0) {
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ base_b0 = base_b1 - size_b0;
+ pbcr = (pbcr & 0x0001ffff) | base_b0 |
+ (((size_b0 / 1024 / 1024) - 1) << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+ /* printf("PB0CR = %x\n", pbcr); */
+ }
+
+ size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
+
+ flash_get_offsets(base_b0, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+ /* Also protect sector containing initial power-up instruction */
+ /* (flash_protect() checks address range - other call ignored) */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET,
+ 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
+
+ if (size_b1) {
+ /* Re-do sizing to get full correct info */
+ size_b1 =
+ flash_get_size((vu_long *) base_b1, &flash_info[1]);
+
+ flash_get_offsets(base_b1, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ base_b1 + size_b1 - CONFIG_SYS_MONITOR_LEN,
+ base_b1 + size_b1 - 1,
+ &flash_info[1]);
+ /* monitor protection OFF by default (one is enough) */
+ (void)flash_protect(FLAG_PROTECT_CLEAR,
+ base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN,
+ base_b0 + size_b0 - 1,
+ &flash_info[0]);
+ } else {
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+ } /* else 2 banks */
+ return (size_b0 + size_b1);
+}
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ (info->flash_id == FLASH_AM040)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+}
diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig
new file mode 100644
index 0000000..530a6ef
--- /dev/null
+++ b/board/amcc/canyonlands/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CANYONLANDS
+
+config SYS_BOARD
+ default "canyonlands"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "canyonlands"
+
+endif
diff --git a/board/amcc/canyonlands/MAINTAINERS b/board/amcc/canyonlands/MAINTAINERS
new file mode 100644
index 0000000..52bf004
--- /dev/null
+++ b/board/amcc/canyonlands/MAINTAINERS
@@ -0,0 +1,8 @@
+CANYONLANDS BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/amcc/canyonlands/
+F: include/configs/canyonlands.h
+F: configs/arches_defconfig
+F: configs/canyonlands_defconfig
+F: configs/glacier_defconfig
diff --git a/board/amcc/canyonlands/Makefile b/board/amcc/canyonlands/Makefile
new file mode 100644
index 0000000..ba0765f
--- /dev/null
+++ b/board/amcc/canyonlands/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2008
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := canyonlands.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+extra-y += init.o
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
new file mode 100644
index 0000000..c5cc4ff
--- /dev/null
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -0,0 +1,521 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc440.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/4xx_pcie.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/errno.h>
+#include <usb.h>
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct board_bcsr {
+ u8 board_id;
+ u8 cpld_rev;
+ u8 led_user;
+ u8 board_status;
+ u8 reset_ctrl;
+ u8 flash_ctrl;
+ u8 eth_ctrl;
+ u8 usb_ctrl;
+ u8 irq_ctrl;
+};
+
+#define BOARD_CANYONLANDS_PCIE 1
+#define BOARD_CANYONLANDS_SATA 2
+#define BOARD_GLACIER 3
+#define BOARD_ARCHES 4
+
+/*
+ * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+#if defined(CONFIG_ARCHES)
+u32 ddr_wrdtr(u32 default_val) {
+ return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
+}
+#else
+u32 ddr_wrdtr(u32 default_val) {
+ return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
+}
+
+u32 ddr_clktr(u32 default_val) {
+ return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
+}
+#endif
+
+#if defined(CONFIG_ARCHES)
+/*
+ * FPGA read/write helper macros
+ */
+static inline int board_fpga_read(int offset)
+{
+ int data;
+
+ data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
+
+ return data;
+}
+
+static inline void board_fpga_write(int offset, int data)
+{
+ out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
+}
+
+/*
+ * CPLD read/write helper macros
+ */
+static inline int board_cpld_read(int offset)
+{
+ int data;
+
+ out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
+ data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
+
+ return data;
+}
+
+static inline void board_cpld_write(int offset, int data)
+{
+ out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
+ out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
+}
+#else
+static int pvr_460ex(void)
+{
+ u32 pvr = get_pvr();
+
+ if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
+ (pvr == PVR_460EX_RB))
+ return 1;
+
+ return 0;
+}
+#endif /* defined(CONFIG_ARCHES) */
+
+int board_early_init_f(void)
+{
+#if !defined(CONFIG_ARCHES)
+ u32 sdr0_cust0;
+ struct board_bcsr *bcsr_data =
+ (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+
+#endif
+
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC3SR, 0xffffffff); /* clear all */
+ mtdcr(UIC3ER, 0x00000000); /* disable all */
+ mtdcr(UIC3CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC3SR, 0xffffffff); /* clear all */
+
+#if !defined(CONFIG_ARCHES)
+ /* SDR Setting - enable NDFC */
+ mfsdr(SDR0_CUST0, sdr0_cust0);
+ sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ SDR0_CUST0_NDFC_BAC_ENCODE(3) |
+ (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
+ mtsdr(SDR0_CUST0, sdr0_cust0);
+#endif
+
+ /*
+ * Configure PFC (Pin Function Control) registers
+ * UART0: 4 pins
+ */
+ mtsdr(SDR0_PFC1, 0x00040000);
+
+ /* Enable PCI host functionality in SDR0_PCI0 */
+ mtsdr(SDR0_PCI0, 0xe0000000);
+
+#if !defined(CONFIG_ARCHES)
+ /* Enable ethernet and take out of reset */
+ out_8(&bcsr_data->eth_ctrl, 0) ;
+
+ /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
+ out_8(&bcsr_data->flash_ctrl, 0) ;
+ mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
+
+ /* Setup PLB4-AHB bridge based on the system address map */
+ mtdcr(AHB_TOP, 0x8000004B);
+ mtdcr(AHB_BOT, 0x8000004B);
+
+#endif
+
+ return 0;
+}
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
+int board_usb_init(int index, enum usb_init_type init)
+{
+ struct board_bcsr *bcsr_data =
+ (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+ u8 val;
+
+ /* Enable USB host & USB-OTG */
+ val = in_8(&bcsr_data->usb_ctrl);
+ val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
+ out_8(&bcsr_data->usb_ctrl, val);
+
+ /*
+ * Configure USB-STP pins as alternate and not GPIO
+ * It seems to be neccessary to configure the STP pins as GPIO
+ * input at powerup (perhaps while USB reset is asserted). So
+ * we configure those pins to their "real" function now.
+ */
+ gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+ gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+
+ return 0;
+}
+
+int usb_board_stop(void)
+{
+ struct board_bcsr *bcsr_data =
+ (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+ u8 val;
+
+ /* Disable USB host & USB-OTG */
+ val = in_8(&bcsr_data->usb_ctrl);
+ val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
+ out_8(&bcsr_data->usb_ctrl, val);
+
+ /* Reconfigure USB-STP pins as input */
+ gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
+ gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return usb_board_stop();
+}
+#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
+
+#if !defined(CONFIG_ARCHES)
+static void canyonlands_sata_init(int board_type)
+{
+ u32 reg;
+
+ if (board_type == BOARD_CANYONLANDS_SATA) {
+ /* Put SATA in reset */
+ SDR_WRITE(SDR0_SRST1, 0x00020001);
+
+ /* Set the phy for SATA, not PCI-E port 0 */
+ reg = SDR_READ(PESDR0_PHY_CTL_RST);
+ SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
+ reg = SDR_READ(PESDR0_L0CLK);
+ SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
+ SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
+ SDR_WRITE(PESDR0_L0DRV, 0x00000104);
+
+ /* Bring SATA out of reset */
+ SDR_WRITE(SDR0_SRST1, 0x00000000);
+ }
+}
+#endif /* !defined(CONFIG_ARCHES) */
+
+int get_cpu_num(void)
+{
+ int cpu = NA_OR_UNKNOWN_CPU;
+
+#if defined(CONFIG_ARCHES)
+ int cpu_num;
+
+ cpu_num = board_fpga_read(0x3);
+
+ /* sanity check; assume cpu numbering starts and increments from 0 */
+ if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
+ cpu = cpu_num;
+#endif
+
+ return cpu;
+}
+
+#if !defined(CONFIG_ARCHES)
+int checkboard(void)
+{
+ struct board_bcsr *bcsr_data =
+ (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ if (pvr_460ex()) {
+ printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
+ if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
+ gd->board_type = BOARD_CANYONLANDS_PCIE;
+ else
+ gd->board_type = BOARD_CANYONLANDS_SATA;
+ } else {
+ printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
+ gd->board_type = BOARD_GLACIER;
+ }
+
+ switch (gd->board_type) {
+ case BOARD_CANYONLANDS_PCIE:
+ case BOARD_GLACIER:
+ puts(", 2*PCIe");
+ break;
+
+ case BOARD_CANYONLANDS_SATA:
+ puts(", 1*PCIe/1*SATA");
+ break;
+ }
+
+ printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ canyonlands_sata_init(gd->board_type);
+
+ return (0);
+}
+
+#else /* defined(CONFIG_ARCHES) */
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
+ printf(" Revision %02x.%02x ",
+ board_fpga_read(0x0), board_fpga_read(0x1));
+
+ gd->board_type = BOARD_ARCHES;
+
+ /* Only CPU0 has access to CPLD registers */
+ if (get_cpu_num() == 0) {
+ u8 cfg_sw = board_cpld_read(0x1);
+ printf("(FPGA=%02x, CPLD=%02x)\n",
+ board_fpga_read(0x2), board_cpld_read(0x0));
+ printf(" Configuration Switch %d%d%d%d\n",
+ ((cfg_sw >> 3) & 0x01),
+ ((cfg_sw >> 2) & 0x01),
+ ((cfg_sw >> 1) & 0x01),
+ ((cfg_sw >> 0) & 0x01));
+ } else
+ printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
+
+
+ if (s != NULL)
+ printf(" Serial# %s\n", s);
+
+ return 0;
+}
+#endif /* !defined(CONFIG_ARCHES) */
+
+#if defined(CONFIG_PCI)
+int board_pcie_first(void)
+{
+ /*
+ * Canyonlands with SATA enabled has only one PCIe slot
+ * (2nd one).
+ */
+ if (gd->board_type == BOARD_CANYONLANDS_SATA)
+ return 1;
+
+ return 0;
+}
+#endif /* CONFIG_PCI */
+
+int board_early_init_r (void)
+{
+ /*
+ * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
+ * boot EBC mapping only supports a maximum of 16MBytes
+ * (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the FLASH has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfc00.0000 -> 4.cc00.0000
+ */
+
+ /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
+ mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
+
+ /* Remove TLB entry of boot EBC mapping */
+ remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
+
+ /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
+ program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
+ TLB_WORD2_I_ENABLE);
+
+ /*
+ * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
+ * 0xfc00.0000 is possible
+ */
+
+ /*
+ * Clear potential errors resulting from auto-calibration.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
+ return 0;
+}
+
+#if !defined(CONFIG_ARCHES)
+int misc_init_r(void)
+{
+ u32 sdr0_srst1 = 0;
+ u32 eth_cfg;
+ u8 val;
+
+ /*
+ * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+ * This is board specific, so let's do it here.
+ */
+ mfsdr(SDR0_ETH_CFG, eth_cfg);
+ /* disable SGMII mode */
+ eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
+ SDR0_ETH_CFG_SGMII1_ENABLE |
+ SDR0_ETH_CFG_SGMII0_ENABLE);
+ /* Set the for 2 RGMII mode */
+ /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
+ eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
+ if (pvr_460ex())
+ eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+ else
+ eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+ mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+ /*
+ * The AHB Bridge core is held in reset after power-on or reset
+ * so enable it now
+ */
+ mfsdr(SDR0_SRST1, sdr0_srst1);
+ sdr0_srst1 &= ~SDR0_SRST1_AHB;
+ mtsdr(SDR0_SRST1, sdr0_srst1);
+
+ /*
+ * RTC/M41T62:
+ * Disable square wave output: Batterie will be drained
+ * quickly, when this output is not disabled
+ */
+ val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
+ val &= ~0x40;
+ i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
+
+ return 0;
+}
+
+#else /* defined(CONFIG_ARCHES) */
+
+int misc_init_r(void)
+{
+ u32 eth_cfg = 0;
+ u32 eth_pll;
+ u32 reg;
+
+ /*
+ * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+ * This is board specific, so let's do it here.
+ */
+
+ /* enable SGMII mode */
+ eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
+ SDR0_ETH_CFG_SGMII1_ENABLE |
+ SDR0_ETH_CFG_SGMII2_ENABLE);
+
+ /* Set EMAC for MDIO */
+ eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
+
+ /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
+ eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
+
+ mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+ /* reset all SGMII interfaces */
+ mfsdr(SDR0_SRST1, reg);
+ reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
+ mtsdr(SDR0_SRST1, reg);
+ mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
+ mtsdr(SDR0_SRST1, 0x00000000);
+
+ do {
+ mfsdr(SDR0_ETH_PLL, eth_pll);
+ } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
+
+ return 0;
+}
+#endif /* !defined(CONFIG_ARCHES) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+extern int __ft_board_setup(void *blob, bd_t *bd);
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ __ft_board_setup(blob, bd);
+
+ if (gd->board_type == BOARD_CANYONLANDS_SATA) {
+ /*
+ * When SATA is selected we need to disable the first PCIe
+ * node in the device tree, so that Linux doesn't initialize
+ * it.
+ */
+ fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
+ "disabled", sizeof("disabled"), 1);
+ }
+
+ if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
+ /*
+ * When PCIe is selected we need to disable the SATA
+ * node in the device tree, so that Linux doesn't initialize
+ * it.
+ */
+ fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
+ "disabled", sizeof("disabled"), 1);
+ }
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/amcc/canyonlands/chip_config.c b/board/amcc/canyonlands/chip_config.c
new file mode 100644
index 0000000..e485570
--- /dev/null
+++ b/board/amcc/canyonlands/chip_config.c
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88",
+ {
+ 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+#if !defined(CONFIG_ARCHES)
+ {
+ "600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1066-nand", "NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88",
+ {
+ 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+#endif
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/amcc/canyonlands/config.mk b/board/amcc/canyonlands/config.mk
new file mode 100644
index 0000000..63b8973
--- /dev/null
+++ b/board/amcc/canyonlands/config.mk
@@ -0,0 +1,19 @@
+#
+# (C) Copyright 2008-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+#
+# AMCC 460EX/460GT Evaluation Board (Canyonlands) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
new file mode 100644
index 0000000..bf00bd6
--- /dev/null
+++ b/board/amcc/canyonlands/init.S
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+ * use the speed up boot process. It is patched after relocation to
+ * enable SA_I
+ */
+ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
+#endif
+
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
+
+ /* PCIe UTL register */
+ tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_RW | SA_IG)
+
+#if !defined(CONFIG_ARCHES)
+ /* TLB-entry for NAND */
+ tlbentry(CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG)
+
+ /* TLB-entry for CPLD */
+ tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG)
+#else
+ /* TLB-entry for FPGA */
+ tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_RW | SA_IG)
+#endif
+
+ /* TLB-entry for OCM */
+ tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_RWX | SA_I)
+
+ /* TLB-entry for Local Configuration registers => peripherals */
+ tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
+
+ /* AHB: Internal USB Peripherals (USB, SATA) */
+ tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_RWX | SA_IG)
+
+#if defined(CONFIG_RAPIDIO)
+ /* TLB-entries for RapidIO (SRIO) */
+ tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
+ 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
+ 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
+ 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K, 0x00100000,
+ 0x4, AC_RW | SA_IG)
+#endif
+
+ tlbtab_end
diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c
new file mode 100644
index 0000000..4b2300b
--- /dev/null
+++ b/board/amcc/common/flash.c
@@ -0,0 +1,934 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_STM:
+ printf("STM ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf("SST ");
+ break;
+ case FLASH_MAN_MX:
+ printf ("MACRONIX ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ printf("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AMD016:
+ printf("AM29F016D (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM033C:
+ printf("AM29LV033C (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_SST800A:
+ printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST160A:
+ printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_STMW320DT:
+ printf ("M29W320DT (32 M, top sector)\n");
+ break;
+ case FLASH_MXLV320T:
+ printf ("MXLV320T (32 Mbit, top sector)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
+ }
+
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ", info->protect[i] ? "RO " : " ");
+ }
+ printf("\n");
+ return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+ /* bit 0 used for big flash marking */
+ if ((ulong)addr & 0x1) {
+ return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
+ } else {
+ return flash_get_size_1(addr, info);
+ }
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+ short i;
+ CONFIG_SYS_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 KiB */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 KiB */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 KiB */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
+ info->flash_id += FLASH_AMD016;
+ info->sector_count = 32;
+ info->size = 0x00200000; /* => 2 MiB */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
+ info->flash_id += FLASH_AMDLV033C;
+ info->sector_count = 64;
+ info->size = 0x00400000; /* => 4 MiB */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000; /* => 512 KiB */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000; /* => 512 KiB */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000; /* => 1 MiB */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000; /* => 1 MiB */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000; /* => 2 MiB */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000; /* => 2 MiB */
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+ (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+ (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+ return flash_erase_2(info, s_first, s_last);
+ } else {
+ return flash_erase_1(info, s_first, s_last);
+ }
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_1(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+ return write_word_2(info, dest, data);
+ } else {
+ return write_word_1(info, dest, data);
+ }
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+
+#undef CONFIG_SYS_FLASH_WORD_SIZE
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+ short i;
+ int n;
+ CONFIG_SYS_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT:
+ info->flash_id = FLASH_MAN_MX;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MiB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MiB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
+ info->flash_id += FLASH_STMW320DT;
+ info->sector_count = 67;
+ info->size = 0x00400000; break; /* => 4 MiB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T:
+ info->flash_id += FLASH_MXLV320T;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ /* 1 x 16k boot sector */
+ base -= 16 << 10;
+ --i;
+ info->start[i] = base;
+ /* 2 x 8k boot sectors */
+ for (n=0; n<2; ++n) {
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ /* 1 x 32k boot sector */
+ base -= 32 << 10;
+ --i;
+ info->start[i] = base;
+
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) {
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00002000;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000a000;
+ info->start[i--] = base + info->size - 0x0000c000;
+ info->start[i--] = base + info->size - 0x0000e000;
+ info->start[i--] = base + info->size - 0x00010000;
+
+ for (; i >= 0; i--)
+ info->start[i] = base + i * 0x00010000;
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00002000;
+ info->start[2] = base + 0x00004000;
+ info->start[3] = base + 0x00006000;
+ info->start[4] = base + 0x00008000;
+ info->start[5] = base + 0x0000a000;
+ info->start[6] = base + 0x0000c000;
+ info->start[7] = base + 0x0000e000;
+ for (i = 8; i < info->sector_count; i++) {
+ info->start[i] =
+ base + ((i-7) * 0x00010000);
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00002000;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000a000;
+ info->start[i--] = base + info->size - 0x0000c000;
+ info->start[i--] = base + info->size - 0x0000e000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+ (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+ (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_2(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+ ulong *data_ptr = &data;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
diff --git a/board/amcc/ebony/Kconfig b/board/amcc/ebony/Kconfig
new file mode 100644
index 0000000..62394b6
--- /dev/null
+++ b/board/amcc/ebony/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_EBONY
+
+config SYS_BOARD
+ default "ebony"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "ebony"
+
+endif
diff --git a/board/amcc/ebony/MAINTAINERS b/board/amcc/ebony/MAINTAINERS
new file mode 100644
index 0000000..bc62851
--- /dev/null
+++ b/board/amcc/ebony/MAINTAINERS
@@ -0,0 +1,6 @@
+EBONY BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/amcc/ebony/
+F: include/configs/ebony.h
+F: configs/ebony_defconfig
diff --git a/board/amcc/ebony/Makefile b/board/amcc/ebony/Makefile
new file mode 100644
index 0000000..5876486
--- /dev/null
+++ b/board/amcc/ebony/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ebony.o flash.o
+extra-y += init.o
diff --git a/board/amcc/ebony/README b/board/amcc/ebony/README
new file mode 100644
index 0000000..4df00b3
--- /dev/null
+++ b/board/amcc/ebony/README
@@ -0,0 +1,136 @@
+ AMCC Ebony Board
+
+ Last Update: September 12, 2002
+=======================================================================
+
+This file contains some handy info regarding U-Boot and the AMCC
+Ebony evaluation board. See the README.ppc440 for additional
+information.
+
+
+SWITCH SETTINGS & JUMPERS
+==========================
+
+Here's what I've been using successfully. If you feel inclined to
+change things ... please read the docs!
+
+DIPSW U46 U80
+------------------------
+SW 1 off on
+SW 2 on on
+SW 3 on on
+SW 4 off on
+SW 5 on off
+SW 6 on on
+SW 7 on off
+SW 8 on off
+
+J41: strapped
+J42: open
+
+All others are factory default.
+
+
+I2C probe
+=====================
+
+The i2c utilities have been tested on both Rev B. and Rev C. and
+look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent
+probing the CDCV850 clock controller at address 0x69 (since reading
+it causes the i2c implementation to misbehave. The output of
+'i2c probe' should look like this (assuming you are only using a single
+SO-DIMM:
+
+=> i2c probe
+Valid chip addresses: 50 53 54
+Excluded chip addresses: 69
+
+
+GETTING OUT OF I2C TROUBLE
+===========================
+
+If you're like me ... you may have screwed up your bootstrap serial
+eeprom ... or worse, your SPD eeprom when experimenting with the
+i2c commands. If so, here are some ideas on how to get out of
+trouble:
+
+Serial bootstrap eeprom corruption:
+-----------------------------------
+Power down the board and set the following straps:
+
+J41 - open
+J42 - strapped
+
+This will select the default sys0 and sys1 settings (the serial
+eeproms are not used). Then power up the board and fix the serial
+eeprom using the 'i2c mm' command. Here are the values I currently
+use:
+
+=> i2c md 50 0 10
+0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................
+
+=> i2c md 54 0 10
+0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M...........
+
+Once you have the eeproms set correctly change the
+J41/J42 straps as you desire.
+
+SPD eeprom corruption:
+------------------------
+I've corrupted the SPD eeprom several times ... perhaps too much coffee
+and not enough presence of mind ;-). By default, the ebony code uses
+the SPD to initialize the DDR SDRAM control registers. So if the SPD
+eeprom is corrupted, U-Boot will never get into ram. Here's how I got
+out of this situation:
+
+0. First, _before_ playing with the i2c utilities, do an 'i2c probe', then
+use 'i2c md' to capture the various device contents to a file. Some day
+you may be glad you did this ... trust me :-). Otherwise try the
+following:
+
+1. In the include/configs/EBONY.h file find the line that defines
+the CONFIG_SPD_EEPROM macro and undefine it. E.g:
+
+#undef CONFIG_SPD_EEPROM
+
+This will make the code use default SDRAM control register
+settings without using the SPD eeprom.
+
+2. Rebuild U-Boot
+
+3. Load the new U-Boot image and reboot ebony.
+
+4. Repair the SPD eeprom using the 'i2c mm' command. Here's the eeprom
+contents that work with the default SO-DIMM that comes with the
+ebony board (micron 8VDDT164AG-265A1). Note: these are probably
+_not_ the factory settings ... but they work.
+
+=> i2c md 53 0 10 80
+0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ......@..uu.....
+0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P<P-
+0020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00 ..PP.....AK42u..
+0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c ................
+0040: 2c 00 00 00 00 00 00 00 08 38 56 44 44 54 31 36 ,........8VDDT16
+0050: 36 34 41 47 2d 32 36 35 41 31 20 01 00 01 2c 63 64AG-265A1 ...,c
+0060: 22 25 ab 00 00 00 00 00 00 00 00 00 00 00 00 00 "%..............
+0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
+
+
+PCI DOUBLE-ENUMERATION WOES
+===========================
+
+If you're not using PCI-X cards and are simply using 32-bit and/or
+33 MHz cards via extenders and the like, you may notice that the
+initial pci scan reports various devices twice ... and configuration
+does not succeed (one or more devices are enumerated twice). To correct
+this we replaced the 2K ohm resistor on the IDSEL line(s) with a
+22 ohm resistor and the problem went away. This change hasn't broken
+anything yet -- use at your own risk.
+
+We never tested anything other than 33 MHz/32-bit cards. If you have
+the chance to do this, please let me know how things turn out :-)
+
+
+Regards,
+--Scott
+<smcnutt@artesyncp.com>
diff --git a/board/amcc/ebony/config.mk b/board/amcc/ebony/config.mk
new file mode 100644
index 0000000..f18b097
--- /dev/null
+++ b/board/amcc/ebony/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
new file mode 100644
index 0000000..eb42448
--- /dev/null
+++ b/board/amcc/ebony/ebony.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+#define BOOT_SMALL_FLASH 32 /* 00100000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+long int fixed_sdram(void);
+
+int board_early_init_f(void)
+{
+ uint reg;
+ unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
+ unsigned char status;
+
+ /*--------------------------------------------------------------------
+ * Setup the external bus controller/chip selects
+ *-------------------------------------------------------------------*/
+ mtdcr(EBC0_CFGADDR, EBC0_CFG);
+ reg = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
+
+ mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */
+ mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
+ mtebc(PB7AP, 0x01015280); /* FPGA registers */
+ mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
+
+ /* read FPGA_REG0 and set the bus controller */
+ status = *fpga_base;
+ if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
+ mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */
+ mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
+ mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */
+ mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
+ } else {
+ mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */
+ mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
+
+ /* set CS2 if FLASH_ONBD_N == 0 */
+ if (!(status & FLASH_ONBD_N)) {
+ mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */
+ mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
+ }
+ }
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+phys_size_t initdram(int board_type)
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+ return dram_size;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ *
+ * Assumes: 128 MB, non-ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram(void)
+{
+ uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup some default
+ *------------------------------------------------------------------*/
+ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
+ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+
+ /*--------------------------------------------------------------------
+ * Setup for board-specific specific mem
+ *------------------------------------------------------------------*/
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ /* RA=10 RD=3 */
+ mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
+ mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
+ udelay(400); /* Delay 200 usecs (min) */
+
+ /*--------------------------------------------------------------------
+ * Enable the controller, then wait for DCEN to complete
+ *------------------------------------------------------------------*/
+ mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ for (;;) {
+ mfsdram(SDRAM0_MCSTS, reg);
+ if (reg & 0x80000000)
+ break;
+ }
+
+ return (128 * 1024 * 1024); /* 128 MB */
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
diff --git a/board/amcc/ebony/flash.c b/board/amcc/ebony/flash.c
new file mode 100644
index 0000000..5740a56
--- /dev/null
+++ b/board/amcc/ebony/flash.c
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+#define BOOT_SMALL_FLASH 32 /* 00100000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+
+#define BOOT_SMALL_FLASH_VAL 4
+#define FLASH_ONBD_N_VAL 2
+#define FLASH_SRAM_SEL_VAL 1
+
+static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
+ {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */
+ {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */
+ {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */
+ {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */
+ {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */
+ {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */
+ {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */
+ {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+
+/*
+ * Override the weak default mapping function with a board specific one
+ */
+u32 flash_get_bank_size(int cs, int idx)
+{
+ u8 reg = in_8((void *)CONFIG_SYS_FPGA_BASE);
+
+ if ((reg & BOOT_SMALL_FLASH) && !(reg & FLASH_ONBD_N)) {
+ /*
+ * cs0: small flash (512KiB)
+ * cs2: 2 * big flash (2 * 2MiB)
+ */
+ if (cs == 0)
+ return flash_info[2].size;
+ if (cs == 2)
+ return flash_info[0].size + flash_info[1].size;
+ } else {
+ /*
+ * cs0: 2 * big flash (2 * 2MiB)
+ * cs2: small flash (512KiB)
+ */
+ if (cs == 0)
+ return flash_info[0].size + flash_info[1].size;
+ if (cs == 2)
+ return flash_info[2].size;
+ }
+
+ return 0;
+}
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+ unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
+ unsigned char switch_status;
+ unsigned short index = 0;
+ int i;
+
+ /* read FPGA base register FPGA_REG0 */
+ switch_status = *fpga_base;
+
+ /* check the bitmap of switch status */
+ if (switch_status & BOOT_SMALL_FLASH) {
+ index += BOOT_SMALL_FLASH_VAL;
+ }
+ if (switch_status & FLASH_ONBD_N) {
+ index += FLASH_ONBD_N_VAL;
+ }
+ if (switch_status & FLASH_SRAM_SEL) {
+ index += FLASH_SRAM_SEL_VAL;
+ }
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *)
+ flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+ &flash_info[2]);
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[2]);
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[2]);
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S
new file mode 100644
index 0000000..904e648
--- /dev/null
+++ b/board/amcc/ebony/init.S
@@ -0,0 +1,41 @@
+/*
+* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
+ tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
+ tlbtab_end
diff --git a/board/amcc/katmai/Kconfig b/board/amcc/katmai/Kconfig
new file mode 100644
index 0000000..fc606cf
--- /dev/null
+++ b/board/amcc/katmai/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_KATMAI
+
+config SYS_BOARD
+ default "katmai"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "katmai"
+
+endif
diff --git a/board/amcc/katmai/MAINTAINERS b/board/amcc/katmai/MAINTAINERS
new file mode 100644
index 0000000..f089352
--- /dev/null
+++ b/board/amcc/katmai/MAINTAINERS
@@ -0,0 +1,6 @@
+KATMAI BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/amcc/katmai/
+F: include/configs/katmai.h
+F: configs/katmai_defconfig
diff --git a/board/amcc/katmai/Makefile b/board/amcc/katmai/Makefile
new file mode 100644
index 0000000..b738def
--- /dev/null
+++ b/board/amcc/katmai/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := katmai.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+extra-y += init.o
diff --git a/board/amcc/katmai/chip_config.c b/board/amcc/katmai/chip_config.c
new file mode 100644
index 0000000..5e711c4
--- /dev/null
+++ b/board/amcc/katmai/chip_config.c
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "400-133","CPU: 400 PLB: 133 OPB: 66 EBC: 66",
+ { 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "500-166","CPU: 500 PLB: 166 OPB: 83 EBC: 83",
+ { 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "533-133","CPU: 533 PLB: 133 OPB: 66 EBC: 66",
+ { 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "667-133","CPU: 667 PLB: 133 OPB: 66 EBC: 66",
+ { 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "667-166","CPU: 667 PLB: 166 OPB: 83 EBC: 83",
+ { 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "800-160","CPU: 800 PLB: 160 OPB: 53 EBC: 17",
+ { 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/amcc/katmai/config.mk b/board/amcc/katmai/config.mk
new file mode 100644
index 0000000..6108f79
--- /dev/null
+++ b/board/amcc/katmai/config.mk
@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#
+# AMCC 440SPe Evaluation (Katmai) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S
new file mode 100644
index 0000000..32f2667
--- /dev/null
+++ b/board/amcc/katmai/init.S
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+
+/**************************************************************************
+ * TLB table for revA
+ *************************************************************************/
+ .globl tlbtabA
+tlbtabA:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
+ tlbtab_end
+
+/**************************************************************************
+ * TLB table for revB
+ *
+ * Notice: revB of the 440SPe chip is very strict about PLB real addresses
+ * and ranges to be mapped for config space: it seems to only work with
+ * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
+ * set otherwise) while revA uses c_nnnn_nnnn.
+ *************************************************************************/
+ .globl tlbtabB
+tlbtabB:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
+ tlbtab_end
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
new file mode 100644
index 0000000..6ae340b
--- /dev/null
+++ b/board/amcc/katmai/katmai.c
@@ -0,0 +1,270 @@
+/*
+ * (C) Copyright 2007-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/4xx_pcie.h>
+#include <asm/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f (void)
+{
+ unsigned long mfr;
+
+ /*----------------------------------------------------------------------+
+ * Interrupt controller setup for the Katmai 440SPe Evaluation board.
+ *-----------------------------------------------------------------------+
+ *-----------------------------------------------------------------------+
+ * Interrupt | Source | Pol. | Sensi.| Crit. |
+ *-----------+-----------------------------------+-------+-------+-------+
+ * IRQ 00 | UART0 | High | Level | Non |
+ * IRQ 01 | UART1 | High | Level | Non |
+ * IRQ 02 | IIC0 | High | Level | Non |
+ * IRQ 03 | IIC1 | High | Level | Non |
+ * IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
+ * IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
+ * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
+ * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
+ * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
+ * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
+ * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
+ * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
+ * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
+ * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
+ * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
+ * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
+ * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
+ * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
+ * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
+ * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
+ * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
+ * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
+ * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
+ * IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
+ * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
+ * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
+ * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
+ * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
+ * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
+ * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
+ * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
+ * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
+ *------------------------------------------------------------------------
+ * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
+ * IRQ 33 | MAL Serr | High | Level | Non |
+ * IRQ 34 | MAL Txde | High | Level | Non |
+ * IRQ 35 | MAL Rxde | High | Level | Non |
+ * IRQ 36 | DMC CE or DMC UE | High | Level | Non |
+ * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
+ * IRQ 38 | MAL TX EOB | High | Level | Non |
+ * IRQ 39 | MAL RX EOB | High | Level | Non |
+ * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
+ * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
+ * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
+ * IRQ 43 | L2 Cache | Risin | Edge | Non |
+ * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
+ * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
+ * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
+ * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
+ * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
+ * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
+ * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
+ * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
+ * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
+ * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
+ * IRQ 54 | DMA Error | High | Level | Non |
+ * IRQ 55 | DMA I2O Error | High | Level | Non |
+ * IRQ 56 | Serial ROM | High | Level | Non |
+ * IRQ 57 | PCIX0 Error | High | Edge | Non |
+ * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
+ * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
+ * IRQ 60 | EMAC0 Interrupt | High | Level | Non |
+ * IRQ 61 | EMAC0 Wake-up | High | Level | Non |
+ * IRQ 62 | Reserved | High | Level | Non |
+ * IRQ 63 | XOR | High | Level | Non |
+ *-----------------------------------------------------------------------
+ * IRQ 64 | PE0 AL | High | Level | Non |
+ * IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
+ * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
+ * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
+ * IRQ 68 | PE0 TCR | High | Level | Non |
+ * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
+ * IRQ 70 | PE0 DCR Error | High | Level | Non |
+ * IRQ 71 | Reserved | N/A | N/A | Non |
+ * IRQ 72 | PE1 AL | High | Level | Non |
+ * IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
+ * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
+ * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
+ * IRQ 76 | PE1 TCR | High | Level | Non |
+ * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
+ * IRQ 78 | PE1 DCR Error | High | Level | Non |
+ * IRQ 79 | Reserved | N/A | N/A | Non |
+ * IRQ 80 | PE2 AL | High | Level | Non |
+ * IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
+ * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
+ * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
+ * IRQ 84 | PE2 TCR | High | Level | Non |
+ * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
+ * IRQ 86 | PE2 DCR Error | High | Level | Non |
+ * IRQ 87 | Reserved | N/A | N/A | Non |
+ * IRQ 88 | External IRQ(5) | Progr | Progr | Non |
+ * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
+ * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
+ * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
+ * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
+ * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
+ * IRQ 94 | Reserved | N/A | N/A | Non |
+ * IRQ 95 | Reserved | N/A | N/A | Non |
+ *-----------------------------------------------------------------------
+ * IRQ 96 | PE0 INTA | High | Level | Non |
+ * IRQ 97 | PE0 INTB | High | Level | Non |
+ * IRQ 98 | PE0 INTC | High | Level | Non |
+ * IRQ 99 | PE0 INTD | High | Level | Non |
+ * IRQ 100 | PE1 INTA | High | Level | Non |
+ * IRQ 101 | PE1 INTB | High | Level | Non |
+ * IRQ 102 | PE1 INTC | High | Level | Non |
+ * IRQ 103 | PE1 INTD | High | Level | Non |
+ * IRQ 104 | PE2 INTA | High | Level | Non |
+ * IRQ 105 | PE2 INTB | High | Level | Non |
+ * IRQ 106 | PE2 INTC | High | Level | Non |
+ * IRQ 107 | PE2 INTD | Risin | Edge | Non |
+ * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
+ * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
+ * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
+ * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
+ * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
+ * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
+ * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
+ * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
+ * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
+ * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
+ * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
+ * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
+ * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
+ * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
+ * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
+ * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
+ * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
+ * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
+ * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
+ * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
+ *-----------+-----------------------------------+-------+-------+-------+ */
+ /*-------------------------------------------------------------------------+
+ * Put UICs in PowerPC440SPemode.
+ * Initialise UIC registers. Clear all interrupts. Disable all interrupts.
+ * Set critical interrupt values. Set interrupt polarities. Set interrupt
+ * trigger levels. Make bit 0 High priority. Clear all interrupts again.
+ *------------------------------------------------------------------------*/
+ mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */
+ mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/
+ mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/
+ mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/
+
+
+ mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/
+ mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
+ mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/
+ mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/
+ mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/
+ mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/
+ mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/
+ mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/
+ mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/
+
+ mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */
+ mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/
+ mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/
+ mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/
+ mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/
+
+ mfsdr(SDR0_MFR, mfr);
+ mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
+ mtsdr(SDR0_MFR, mfr);
+
+ mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
+
+ out32(GPIO0_OR, CONFIG_SYS_GPIO_OR);
+ out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
+ out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: Katmai - AMCC 440SPe Evaluation Board");
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+/*
+ * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+u32 ddr_wrdtr(u32 default_val) {
+ return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
+}
+
+u32 ddr_clktr(u32 default_val) {
+ return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
+}
+
+#if defined(CONFIG_PCI)
+int board_pcie_card_present(int port)
+{
+ u32 val;
+
+ val = in32(GPIO0_IR);
+ switch (port) {
+ case 0:
+ return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0));
+ case 1:
+ return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1));
+ case 2:
+ return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2));
+ default:
+ return 0;
+ }
+}
+#endif /* defined(CONFIG_PCI) */
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis);
+ return pci_eth_init(bis);
+}
diff --git a/board/amcc/kilauea/Kconfig b/board/amcc/kilauea/Kconfig
new file mode 100644
index 0000000..3f2f434
--- /dev/null
+++ b/board/amcc/kilauea/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_KILAUEA
+
+config SYS_BOARD
+ default "kilauea"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "kilauea"
+
+endif
diff --git a/board/amcc/kilauea/MAINTAINERS b/board/amcc/kilauea/MAINTAINERS
new file mode 100644
index 0000000..12bbcb1
--- /dev/null
+++ b/board/amcc/kilauea/MAINTAINERS
@@ -0,0 +1,7 @@
+KILAUEA BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/amcc/kilauea/
+F: include/configs/kilauea.h
+F: configs/haleakala_defconfig
+F: configs/kilauea_defconfig
diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile
new file mode 100644
index 0000000..754dadc
--- /dev/null
+++ b/board/amcc/kilauea/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := kilauea.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
diff --git a/board/amcc/kilauea/chip_config.c b/board/amcc/kilauea/chip_config.c
new file mode 100644
index 0000000..7e9dd3b
--- /dev/null
+++ b/board/amcc/kilauea/chip_config.c
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "333-nor","NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83",
+ {
+ 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
+ {
+ 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
+ {
+ 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
+ {
+ 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111",
+ {
+ 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/amcc/kilauea/config.mk b/board/amcc/kilauea/config.mk
new file mode 100644
index 0000000..0dc15c1
--- /dev/null
+++ b/board/amcc/kilauea/config.mk
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2007-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
new file mode 100644
index 0000000..abfaa1e
--- /dev/null
+++ b/board/amcc/kilauea/kilauea.c
@@ -0,0 +1,309 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc405.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#include <asm/4xx_pcie.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+static int board_cpld_version(void)
+{
+ u32 cpld;
+
+ cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE);
+ if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) {
+ /*
+ * Magic not found -> "old" CPLD revision which needs
+ * the "old" EBC configuration
+ */
+ mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) |
+ EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE |
+ EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) |
+ EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) |
+ EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED |
+ EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED);
+
+ /*
+ * Return 0 for "old" CPLD version
+ */
+ return 0;
+ }
+
+ /*
+ * Magic found -> "new" CPLD revision which needs no new
+ * EBC configuration
+ */
+ return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8;
+}
+
+/*
+ * Board early initialization function
+ */
+int board_early_init_f (void)
+{
+ u32 val;
+
+ /*--------------------------------------------------------------------+
+ | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
+ +--------------------------------------------------------------------+
+ +---------------------------------------------------------------------+
+ |Interrupt| Source | Pol. | Sensi.| Crit. |
+ +---------+-----------------------------------+-------+-------+-------+
+ | IRQ 00 | UART0 | High | Level | Non |
+ | IRQ 01 | UART1 | High | Level | Non |
+ | IRQ 02 | IIC0 | High | Level | Non |
+ | IRQ 03 | TBD | High | Level | Non |
+ | IRQ 04 | TBD | High | Level | Non |
+ | IRQ 05 | EBM | High | Level | Non |
+ | IRQ 06 | BGI | High | Level | Non |
+ | IRQ 07 | IIC1 | Rising| Edge | Non |
+ | IRQ 08 | SPI | High | Lvl/ed| Non |
+ | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
+ | IRQ 10 | MAL TX EOB | High | Level | Non |
+ | IRQ 11 | MAL RX EOB | High | Level | Non |
+ | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
+ | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
+ | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
+ | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
+ | IRQ 16 | PCIE0 AL | high | Level | Non |
+ | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
+ | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
+ | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
+ | IRQ 20 | PCIE0 TCR | High | Level | Non |
+ | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
+ | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
+ | IRQ 23 | Security EIP-94 | High | Level | Non |
+ | IRQ 24 | EMAC0 interrupt | High | Level | Non |
+ | IRQ 25 | EMAC1 interrupt | High | Level | Non |
+ | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
+ | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
+ | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
+ | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
+ | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
+ | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
+ |----------------------------------------------------------------------
+ | IRQ 32 | MAL Serr | High | Level | Non |
+ | IRQ 33 | MAL Txde | High | Level | Non |
+ | IRQ 34 | MAL Rxde | High | Level | Non |
+ | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
+ | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
+ | IRQ 37 | EBC | High |Lvl Edg| Non |
+ | IRQ 38 | NDFC | High | Level | Non |
+ | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
+ | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
+ | IRQ 41 | PCIE1 AL | high | Level | Non |
+ | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
+ | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
+ | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
+ | IRQ 45 | PCIE1 TCR | High | Level | Non |
+ | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
+ | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
+ | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
+ | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
+ | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
+ | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
+ | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
+ | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
+ | IRQ 55 | Serial ROM | High | Level | Non |
+ | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
+ | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
+ | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
+ |----------------------------------------------------------------------
+ | IRQ 64 | PE0 AL | High | Level | Non |
+ | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
+ | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 68 | PE0 TCR | High | Level | Non |
+ | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 70 | PE0 DCR Error | High | Level | Non |
+ | IRQ 71 | Reserved | N/A | N/A | Non |
+ | IRQ 72 | PE1 AL | High | Level | Non |
+ | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
+ | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 76 | PE1 TCR | High | Level | Non |
+ | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 78 | PE1 DCR Error | High | Level | Non |
+ | IRQ 79 | Reserved | N/A | N/A | Non |
+ | IRQ 80 | PE2 AL | High | Level | Non |
+ | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
+ | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 84 | PE2 TCR | High | Level | Non |
+ | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 86 | PE2 DCR Error | High | Level | Non |
+ | IRQ 87 | Reserved | N/A | N/A | Non |
+ | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
+ | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
+ | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
+ | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
+ | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
+ | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
+ | IRQ 94 | Reserved | N/A | N/A | Non |
+ | IRQ 95 | Reserved | N/A | N/A | Non |
+ |---------------------------------------------------------------------
+ +---------+-----------------------------------+-------+-------+------*/
+ /*--------------------------------------------------------------------+
+ | Initialise UIC registers. Clear all interrupts. Disable all
+ | interrupts.
+ | Set critical interrupt values. Set interrupt polarities. Set
+ | interrupt trigger levels. Make bit 0 High priority. Clear all
+ | interrupts again.
+ +-------------------------------------------------------------------*/
+
+ mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
+ mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
+ /* Except cascade UIC0 and UIC1 */
+ mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
+ mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
+
+ /*
+ * Note: Some cores are still in reset when the chip starts, so
+ * take them out of reset
+ */
+ mtsdr(SDR0_SRST, 0);
+
+ /* Configure 405EX for NAND usage */
+ val = SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NRB_BUSY |
+ (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
+ mtsdr(SDR0_CUST0, val);
+
+ /*
+ * Configure PFC (Pin Function Control) registers
+ * -> Enable USB
+ */
+ val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
+ mtsdr(SDR0_PFC1, val);
+
+ /*
+ * The CPLD version detection has to be the first access to
+ * the CPLD, so we need to make this access this early and
+ * save the CPLD version for later.
+ */
+ gd->board_type = board_cpld_version();
+
+ /*
+ * Configure FPGA register with PCIe reset
+ */
+ out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */
+ mdelay(50);
+ out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ /* Monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+#endif
+
+ return 0;
+}
+
+static int is_405exr(void)
+{
+ u32 pvr = get_pvr();
+
+ if (pvr & 0x00000004)
+ return 0; /* bit 2 set -> 405EX */
+
+ return 1; /* bit 2 cleared -> 405EXr */
+}
+
+int board_emac_count(void)
+{
+ /*
+ * 405EXr only has one EMAC interface, 405EX has two
+ */
+ if (is_405exr())
+ return 1;
+ else
+ return 2;
+}
+
+/*
+ * Override the weak default implementation and return the
+ * last PCIe slot number (max number - 1).
+ */
+int board_pcie_last(void)
+{
+ /*
+ * 405EXr only has one EMAC interface, 405EX has two
+ */
+ if (is_405exr())
+ return 1 - 1;
+ else
+ return 2 - 1;
+}
+
+int checkboard (void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ if (is_405exr())
+ printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
+ else
+ printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ printf(" (CPLD rev. %ld)\n", gd->board_type);
+
+ return (0);
+}
diff --git a/board/amcc/luan/Kconfig b/board/amcc/luan/Kconfig
new file mode 100644
index 0000000..3df90af
--- /dev/null
+++ b/board/amcc/luan/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_LUAN
+
+config SYS_BOARD
+ default "luan"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "luan"
+
+endif
diff --git a/board/amcc/luan/MAINTAINERS b/board/amcc/luan/MAINTAINERS
new file mode 100644
index 0000000..a23296d
--- /dev/null
+++ b/board/amcc/luan/MAINTAINERS
@@ -0,0 +1,6 @@
+LUAN BOARD
+M: John Otken <jotken@softadvances.com>
+S: Maintained
+F: board/amcc/luan/
+F: include/configs/luan.h
+F: configs/luan_defconfig
diff --git a/board/amcc/luan/Makefile b/board/amcc/luan/Makefile
new file mode 100644
index 0000000..345ad56
--- /dev/null
+++ b/board/amcc/luan/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = luan.o flash.o
+extra-y += init.o
diff --git a/board/amcc/luan/config.mk b/board/amcc/luan/config.mk
new file mode 100644
index 0000000..f18b097
--- /dev/null
+++ b/board/amcc/luan/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/luan/epld.h b/board/amcc/luan/epld.h
new file mode 100644
index 0000000..569d78c
--- /dev/null
+++ b/board/amcc/luan/epld.h
@@ -0,0 +1,85 @@
+#define EPLD0_FSEL_FB2 0x80
+#define EPLD0_BOOT_SMALL_FLASH 0x40 /* 0 boot from large flash, 1 from small flash */
+#define EPLD0_RAW_CARD_BIT0 0x20 /* raw card EC level */
+#define EPLD0_RAW_CARD_BIT1 0x10
+#define EPLD0_RAW_CARD_BIT2 0x08
+#define EPLD0_EXT_ARB_SEL_N 0x04 /* 0 select on-board ext PCI-X, 1 internal arbiter */
+#define EPLD0_FLASH_ONBRD_N 0x02 /* 0 small flash/SRAM active, 1 block access */
+#define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */
+
+#define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */
+#define EPLD1_PCIL0_CNTL1 0x40 /* S*0 of 9531 */
+#define EPLD1_PCIL0_CNTL2 0x20 /* S*1 of 9531 */
+#define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */
+#define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */
+#define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */
+#define EPLD1_MASTER_CLOCK7 0x02 /* clock source select 7 */
+#define EPLD1_MASTER_CLOCK8 0x01 /* clock source select 8 */
+
+#define EPLD2_ETH_MODE_10 0x80 /* Ethernet mode 10 (default = 1) */
+#define EPLD2_ETH_MODE_100 0x40 /* Ethernet mode 100 (default = 1) */
+#define EPLD2_ETH_MODE_1000 0x20 /* Ethernet mode 1000 (default = 1) */
+#define EPLD2_ETH_DUPLEX_MODE 0x10 /* Ethernet force full duplex mode */
+#define EPLD2_RESET_ETH_N 0x08 /* Ethernet reset (default = 1) */
+#define EPLD2_ETH_AUTO_NEGO 0x04 /* Ethernet auto negotiation */
+#define EPLD2_DEFAULT_UART_N 0x01 /* 0 select DSR DTR for UART1 */
+
+#define EPLD3_STATUS_LED4 0x08 /* status LED 8 (1 = LED on) */
+#define EPLD3_STATUS_LED3 0x04 /* status LED 4 (1 = LED on) */
+#define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */
+#define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */
+
+#define EPLD4_PCIL0_VTH1 0x80 /* PCI-X 0 VTH1 status */
+#define EPLD4_PCIL0_VTH2 0x40 /* PCI-X 0 VTH2 status */
+#define EPLD4_PCIL0_VTH3 0x20 /* PCI-X 0 VTH3 status */
+#define EPLD4_PCIL0_VTH4 0x10 /* PCI-X 0 VTH4 status */
+#define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */
+#define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */
+#define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */
+#define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */
+
+#define EPLD5_PCIL0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */
+#define EPLD5_PCIL0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */
+#define EPLD5_PCIL0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */
+#define EPLD5_PCIL0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */
+#define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */
+#define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */
+#define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */
+#define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */
+
+#define EPLD6_PCIL0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */
+#define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCI1_CLKCNTL1 0x80 /* PCI1 clock control S*0 of 9531 */
+#define EPLD6_PCI1_CLKCNTL2 0x40 /* PCI1 clock control S*1 of 9531 */
+#define EPLD6_PCI2_CLKCNTL1 0x20 /* PCI2 clock control S*0 of 9531 */
+#define EPLD6_PCI2_CLKCNTL2 0x10 /* PCI2 clock control S*1 of 9531 */
+
+#define EPLD7_VTH1 0x80 /* PCI2 VTH1 status */
+#define EPLD7_VTH2 0x40 /* PCI2 VTH2 status */
+#define EPLD7_VTH3 0x20 /* PCI2 VTH3 status */
+#define EPLD7_VTH4 0x10 /* PCI2 VTH4 status */
+#define EPLD7_INTA_MODE 0x80 /* see S5 on SW2 for details */
+#define EPLD7_PCI_INT_MODE_N 0x40 /* see S1 on SW2 for details */
+#define EPLD7_WRITE_ENABLE_GPIO 0x20 /* see S2 on SW2 for details */
+#define EPLD7_WRITE_ENABLE_INT 0x10 /* see S3 on SW2 for details */
+
+
+typedef struct {
+ unsigned char status; /* misc status */
+ unsigned char clock; /* clock status, PCI-X clock control */
+ unsigned char ethuart; /* Ethernet, UART status */
+ unsigned char leds; /* LED register */
+ unsigned char vth01; /* PCI0, PCI1 VTH register */
+ unsigned char pciints; /* PCI0, PCI1 interrupts */
+ unsigned char pci2; /* PCI2 interrupts, clock control */
+ unsigned char vth2; /* PCI2 VTH register */
+ unsigned char filler1[4096-8];
+ unsigned char gpio00; /* GPIO bits 0-7 */
+ unsigned char gpio08; /* GPIO bits 8-15 */
+ unsigned char gpio16; /* GPIO bits 16-23 */
+ unsigned char gpio24; /* GPIO bits 24-31 */
+ unsigned char filler2[4096-4];
+ unsigned char version; /* EPLD version */
+} epld_t;
diff --git a/board/amcc/luan/flash.c b/board/amcc/luan/flash.c
new file mode 100644
index 0000000..a242bef
--- /dev/null
+++ b/board/amcc/luan/flash.c
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+static unsigned long flash_addr_table[1][CONFIG_SYS_MAX_FLASH_BANKS] = {
+ {0xff900000, 0xff980000, 0xffc00000}, /* 0:000: configuraton 3 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+ unsigned short index = 0;
+ int i;
+
+ /* read FPGA base register FPGA_REG0 */
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *)
+ flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+ &flash_info[2]);
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[2]);
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[2]);
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S
new file mode 100644
index 0000000..0f4a78e
--- /dev/null
+++ b/board/amcc/luan/init.S
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G)
+
+ tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG)
+ tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG)
+ tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG)
+ tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG)
+ tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ /* internal ram (l2 cache) */
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I)
+
+ /* peripherals at f0000000 */
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG)
+
+ /* PCI */
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG)
+ tlbtab_end
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
new file mode 100644
index 0000000..774671d
--- /dev/null
+++ b/board/amcc/luan/luan.c
@@ -0,0 +1,223 @@
+/*
+ * (C) Copyright 2005
+ * John Otken, jotken@softadvances.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-isram.h>
+#include <spd_sdram.h>
+#include "epld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+
+/*************************************************************************
+ * int board_early_init_f()
+ *
+ ************************************************************************/
+int board_early_init_f(void)
+{
+ u32 mfr;
+
+ mtebc( PB0AP, 0x03800000 ); /* set chip selects */
+ mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
+ mtebc( PB1AP, 0x03800000 );
+ mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
+ mtebc( PB2AP, 0x03800000 );
+ mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
+
+ mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */
+ mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */
+ mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */
+ mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */
+ mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */
+ mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */
+ mtdcr( UIC1SR, 0xffffffff );
+
+ mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */
+ mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */
+ mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */
+ mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */
+ mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */
+ mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */
+ mtdcr( UIC0SR, 0xffffffff );
+
+ mfsdr(SDR0_MFR, mfr);
+ mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
+ mtsdr(SDR0_MFR, mfr);
+
+ return 0;
+}
+
+
+/*************************************************************************
+ * int misc_init_r()
+ *
+ ************************************************************************/
+int misc_init_r(void)
+{
+ volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE;
+
+ /* set modes of operation */
+ x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
+ EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
+ /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
+ x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
+
+ /* put Ethernet+PHY in reset */
+ x->ethuart &= ~EPLD2_RESET_ETH_N;
+ udelay(10000);
+ /* take Ethernet+PHY out of reset */
+ x->ethuart |= EPLD2_RESET_ETH_N;
+
+ return 0;
+}
+
+
+/*************************************************************************
+ * int checkboard()
+ *
+ ************************************************************************/
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: Luan - AMCC PPC440SP Evaluation Board");
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+/*
+ * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+u32 ddr_clktr(u32 default_val) {
+ return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+}
+
+/*************************************************************************
+ * hw_watchdog_reset
+ *
+ * This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+}
+#endif
+
+
+/*************************************************************************
+ * int on_off()
+ *
+ ************************************************************************/
+static int on_off( const char *s )
+{
+ if (strcmp(s, "on") == 0) {
+ return 1;
+ } else if (strcmp(s, "off") == 0) {
+ return 0;
+ }
+ return -1;
+}
+
+
+/*************************************************************************
+ * void l2cache_disable()
+ *
+ ************************************************************************/
+static void l2cache_disable(void)
+{
+ mtdcr( L2_CACHE_CFG, 0 );
+}
+
+
+/*************************************************************************
+ * void l2cache_enable()
+ *
+ ************************************************************************/
+static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
+{
+ mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
+
+ mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */
+
+ mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
+
+ while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ;; /* poll L2_SR for completion */
+
+ mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
+
+ mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
+
+ mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */
+ mtdcr( L2_CACHE_SNP1, 0 );
+
+ __asm__ volatile ("sync"); /* msync */
+
+ mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */
+
+ __asm__ volatile ("sync");
+}
+
+
+/*************************************************************************
+ * int l2cache_status()
+ *
+ ************************************************************************/
+static int l2cache_status(void)
+{
+ return (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
+}
+
+
+/*************************************************************************
+ * int do_l2cache()
+ *
+ ************************************************************************/
+int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] )
+{
+ switch (argc) {
+ case 2: /* on / off */
+ switch (on_off(argv[1])) {
+ case 0: l2cache_disable();
+ break;
+ case 1: l2cache_enable();
+ break;
+ }
+ /* FALL TROUGH */
+ case 1: /* get status */
+ printf ("L2 Cache is %s\n",
+ l2cache_status() ? "ON" : "OFF");
+ return 0;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+
+U_BOOT_CMD(
+ l2cache, 2, 1, do_l2cache,
+ "enable or disable L2 cache",
+ "[on, off]\n"
+ " - enable or disable L2 cache"
+);
diff --git a/board/amcc/makalu/Kconfig b/board/amcc/makalu/Kconfig
new file mode 100644
index 0000000..31ce5f1
--- /dev/null
+++ b/board/amcc/makalu/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MAKALU
+
+config SYS_BOARD
+ default "makalu"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "makalu"
+
+endif
diff --git a/board/amcc/makalu/MAINTAINERS b/board/amcc/makalu/MAINTAINERS
new file mode 100644
index 0000000..ecd5e19
--- /dev/null
+++ b/board/amcc/makalu/MAINTAINERS
@@ -0,0 +1,6 @@
+MAKALU BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/amcc/makalu/
+F: include/configs/makalu.h
+F: configs/makalu_defconfig
diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile
new file mode 100644
index 0000000..dcf162c
--- /dev/null
+++ b/board/amcc/makalu/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = makalu.o cmd_pll.o
+obj-y += init.o
diff --git a/board/amcc/makalu/cmd_pll.c b/board/amcc/makalu/cmd_pll.c
new file mode 100644
index 0000000..f12655b
--- /dev/null
+++ b/board/amcc/makalu/cmd_pll.c
@@ -0,0 +1,279 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * ehnus: change pll frequency.
+ * Wed Sep 5 11:45:17 CST 2007
+ * hsun@udtech.com.cn
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <i2c.h>
+
+#ifdef CONFIG_CMD_EEPROM
+
+#define EEPROM_CONF_OFFSET 0
+#define EEPROM_TEST_OFFSET 16
+#define EEPROM_SDSTP_PARAM 16
+
+#define PLL_NAME_MAX 12
+#define BUF_STEP 8
+
+/* eeprom_wirtes 8Byte per op. */
+#define EEPROM_ALTER_FREQ(freq) \
+ do { \
+ int __i; \
+ for (__i = 0; __i < 2; __i++) \
+ eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, \
+ EEPROM_CONF_OFFSET + __i*BUF_STEP, \
+ pll_select[freq], \
+ BUF_STEP + __i*BUF_STEP); \
+ } while (0)
+
+#define PDEBUG
+#ifdef PDEBUG
+#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET)
+#else
+#define PLL_DEBUG
+#endif
+
+typedef enum {
+ PLL_ebc20,
+ PLL_333,
+ PLL_4001,
+ PLL_4002,
+ PLL_533,
+ PLL_600,
+ PLL_666, /* For now, kilauea can't support */
+ RCONF,
+ WTEST,
+ PLL_TOTAL
+} pll_freq_t;
+
+static const char
+pll_name[][PLL_NAME_MAX] = {
+ "PLL_ebc20",
+ "PLL_333",
+ "PLL_400@1",
+ "PLL_400@2",
+ "PLL_533",
+ "PLL_600",
+ "PLL_666",
+ "RCONF",
+ "WTEST",
+ ""
+};
+
+/*
+ * ehnus:
+ */
+static uchar
+pll_select[][EEPROM_SDSTP_PARAM] = {
+ /* 0: CPU 333MHz EBC 20MHz, for test only */
+ {
+ 0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 0: 333 */
+ {
+ 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 1: 400_266 */
+ {
+ 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 2: 400 */
+ {
+ 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 3: 533 */
+ {
+ 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 4: 600 */
+ {
+ 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ /* 5: 666 */
+ {
+ 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ },
+
+ {}
+};
+
+static uchar
+testbuf[EEPROM_SDSTP_PARAM] = {
+ 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+ 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
+};
+
+static void
+pll_debug(int off)
+{
+ int i;
+ uchar buffer[EEPROM_SDSTP_PARAM];
+
+ memset(buffer, 0, sizeof(buffer));
+ eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off,
+ buffer, EEPROM_SDSTP_PARAM);
+
+ printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
+ for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
+ printf("%02x ", buffer[i]);
+ printf("\n");
+}
+
+static void
+test_write(void)
+{
+ printf("Debug: test eeprom_write ... ");
+
+ /*
+ * Write twice, 8 bytes per write
+ */
+ eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
+ testbuf, 8);
+ eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
+ testbuf, 16);
+ printf("done\n");
+
+ pll_debug(EEPROM_TEST_OFFSET);
+}
+
+int
+do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char c = '\0';
+ pll_freq_t pll_freq;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) {
+ if (!strcmp(pll_name[pll_freq], argv[1]))
+ break;
+ }
+
+ switch (pll_freq) {
+ case PLL_ebc20:
+ case PLL_333:
+ case PLL_4001:
+ case PLL_4002:
+ case PLL_533:
+ case PLL_600:
+ EEPROM_ALTER_FREQ(pll_freq);
+ break;
+
+ case PLL_666: /* not support */
+ printf("Choose this option will result in a boot failure."
+ "\nContinue? (Y/N): ");
+
+ c = getc(); putc('\n');
+
+ if ((c == 'y') || (c == 'Y')) {
+ EEPROM_ALTER_FREQ(pll_freq);
+ break;
+ }
+ goto ret;
+
+ case RCONF:
+ pll_debug(EEPROM_CONF_OFFSET);
+ goto ret;
+ case WTEST:
+ printf("DEBUG: write test\n");
+ test_write();
+ goto ret;
+
+ default:
+ printf("Invalid options\n\n");
+ return cmd_usage(cmdtp);
+ }
+
+ printf("PLL set to %s, "
+ "reset the board to take effect\n", pll_name[pll_freq]);
+
+ PLL_DEBUG;
+ret:
+ return 0;
+}
+
+U_BOOT_CMD(
+ pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter,
+ "change pll frequence",
+ "pllalter <selection> - change pll frequence \n\n\
+ ** New freq take effect after reset. ** \n\
+ ----------------------------------------------\n\
+ PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t Same as PLL_333 \n\
+ \t except \n\
+ \t EBC: 20 MHz \n\
+ ----------------------------------------------\n\
+ PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 666 MHz \n\
+ \t CPU: 333 MHz \n\
+ \t PLB: 166 MHz \n\
+ \t OPB: 83 MHz \n\
+ \t DDR: 83 MHz \n\
+ ------------------------------------------------\n\
+ PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 800 MHz \n\
+ \t CPU: 400 MHz \n\
+ \t PLB: 133 MHz \n\
+ \t OPB: 66 MHz \n\
+ \t DDR: 133 MHz \n\
+ ------------------------------------------------\n\
+ PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 800 MHz \n\
+ \t CPU: 400 MHz \n\
+ \t PLB: 200 MHz \n\
+ \t OPB: 100 MHz \n\
+ \t DDR: 200 MHz \n\
+ ----------------------------------------------\n\
+ PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 1066 MHz \n\
+ \t CPU: 533 MHz \n\
+ \t PLB: 177 MHz \n\
+ \t OPB: 88 MHz \n\
+ \t DDR: 177 MHz \n\
+ ----------------------------------------------\n\
+ PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 1200 MHz \n\
+ \t CPU: 600 MHz \n\
+ \t PLB: 200 MHz \n\
+ \t OPB: 100 MHz \n\
+ \t DDR: 200 MHz \n\
+ ----------------------------------------------\n\
+ PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
+ \t VCO: 1333 MHz \n\
+ \t CPU: 666 MHz \n\
+ \t PLB: 166 MHz \n\
+ \t OPB: 83 MHz \n\
+ \t DDR: 166 MHz \n\
+ -----------------------------------------------\n\
+ RCONF: Read current eeprom configuration. \n\
+ -----------------------------------------------\n\
+ WTEST: Test EEPROM write with predefined values\n\
+ -----------------------------------------------"
+);
+
+#endif /* CONFIG_CMD_EEPROM */
diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S
new file mode 100644
index 0000000..e15c622
--- /dev/null
+++ b/board/amcc/makalu/init.S
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ * Grant Erickson <gerickson@nuovations.com>
+ *
+ * (C) Copyright 2007-2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Originally based on code provided from Senao and AMCC
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+ .globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+ blr
diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
new file mode 100644
index 0000000..a6ad2a1
--- /dev/null
+++ b/board/amcc/makalu/makalu.c
@@ -0,0 +1,223 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc405.h>
+#include <libfdt.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <asm/errno.h>
+
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#include <asm/4xx_pcie.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * Board early initialization function
+ */
+int board_early_init_f (void)
+{
+ u32 val;
+
+ /*--------------------------------------------------------------------+
+ | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
+ +--------------------------------------------------------------------+
+ +---------------------------------------------------------------------+
+ |Interrupt| Source | Pol. | Sensi.| Crit. |
+ +---------+-----------------------------------+-------+-------+-------+
+ | IRQ 00 | UART0 | High | Level | Non |
+ | IRQ 01 | UART1 | High | Level | Non |
+ | IRQ 02 | IIC0 | High | Level | Non |
+ | IRQ 03 | TBD | High | Level | Non |
+ | IRQ 04 | TBD | High | Level | Non |
+ | IRQ 05 | EBM | High | Level | Non |
+ | IRQ 06 | BGI | High | Level | Non |
+ | IRQ 07 | IIC1 | Rising| Edge | Non |
+ | IRQ 08 | SPI | High | Lvl/ed| Non |
+ | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
+ | IRQ 10 | MAL TX EOB | High | Level | Non |
+ | IRQ 11 | MAL RX EOB | High | Level | Non |
+ | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
+ | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
+ | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
+ | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
+ | IRQ 16 | PCIE0 AL | high | Level | Non |
+ | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
+ | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
+ | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
+ | IRQ 20 | PCIE0 TCR | High | Level | Non |
+ | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
+ | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
+ | IRQ 23 | Security EIP-94 | High | Level | Non |
+ | IRQ 24 | EMAC0 interrupt | High | Level | Non |
+ | IRQ 25 | EMAC1 interrupt | High | Level | Non |
+ | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
+ | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
+ | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
+ | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
+ | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
+ | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
+ |----------------------------------------------------------------------
+ | IRQ 32 | MAL Serr | High | Level | Non |
+ | IRQ 33 | MAL Txde | High | Level | Non |
+ | IRQ 34 | MAL Rxde | High | Level | Non |
+ | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
+ | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
+ | IRQ 37 | EBC | High |Lvl Edg| Non |
+ | IRQ 38 | NDFC | High | Level | Non |
+ | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
+ | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
+ | IRQ 41 | PCIE1 AL | high | Level | Non |
+ | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
+ | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
+ | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
+ | IRQ 45 | PCIE1 TCR | High | Level | Non |
+ | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
+ | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
+ | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
+ | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
+ | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
+ | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
+ | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
+ | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
+ | IRQ 55 | Serial ROM | High | Level | Non |
+ | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
+ | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
+ | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
+ |----------------------------------------------------------------------
+ | IRQ 64 | PE0 AL | High | Level | Non |
+ | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
+ | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 68 | PE0 TCR | High | Level | Non |
+ | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 70 | PE0 DCR Error | High | Level | Non |
+ | IRQ 71 | Reserved | N/A | N/A | Non |
+ | IRQ 72 | PE1 AL | High | Level | Non |
+ | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
+ | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 76 | PE1 TCR | High | Level | Non |
+ | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 78 | PE1 DCR Error | High | Level | Non |
+ | IRQ 79 | Reserved | N/A | N/A | Non |
+ | IRQ 80 | PE2 AL | High | Level | Non |
+ | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
+ | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 84 | PE2 TCR | High | Level | Non |
+ | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 86 | PE2 DCR Error | High | Level | Non |
+ | IRQ 87 | Reserved | N/A | N/A | Non |
+ | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
+ | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
+ | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
+ | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
+ | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
+ | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
+ | IRQ 94 | Reserved | N/A | N/A | Non |
+ | IRQ 95 | Reserved | N/A | N/A | Non |
+ |---------------------------------------------------------------------
+ +---------+-----------------------------------+-------+-------+------*/
+ /*--------------------------------------------------------------------+
+ | Initialise UIC registers. Clear all interrupts. Disable all
+ | interrupts.
+ | Set critical interrupt values. Set interrupt polarities. Set
+ | interrupt trigger levels. Make bit 0 High priority. Clear all
+ | interrupts again.
+ +-------------------------------------------------------------------*/
+
+ mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
+ mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
+ /* Except cascade UIC0 and UIC1 */
+ mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
+ mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
+
+ /*
+ * Note: Some cores are still in reset when the chip starts, so
+ * take them out of reset
+ */
+ mtsdr(SDR0_SRST, 0);
+
+ /* Reset PCIe slots */
+ gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0);
+ udelay(100);
+ gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1);
+
+ /*
+ * Configure PFC (Pin Function Control) registers
+ * -> Enable USB
+ */
+ val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
+ mtsdr(SDR0_PFC1, val);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ /* Monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+#endif
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: Makalu - AMCC PPC405EX Evaluation Board");
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return (0);
+}
diff --git a/board/amcc/ocotea/Kconfig b/board/amcc/ocotea/Kconfig
new file mode 100644
index 0000000..18c1a15
--- /dev/null
+++ b/board/amcc/ocotea/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OCOTEA
+
+config SYS_BOARD
+ default "ocotea"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "ocotea"
+
+endif
diff --git a/board/amcc/ocotea/MAINTAINERS b/board/amcc/ocotea/MAINTAINERS
new file mode 100644
index 0000000..34634a2
--- /dev/null
+++ b/board/amcc/ocotea/MAINTAINERS
@@ -0,0 +1,6 @@
+OCOTEA BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/amcc/ocotea/
+F: include/configs/ocotea.h
+F: configs/ocotea_defconfig
diff --git a/board/amcc/ocotea/Makefile b/board/amcc/ocotea/Makefile
new file mode 100644
index 0000000..7646bbb
--- /dev/null
+++ b/board/amcc/ocotea/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ocotea.o flash.o
+extra-y += init.o
diff --git a/board/amcc/ocotea/README.ocotea b/board/amcc/ocotea/README.ocotea
new file mode 100644
index 0000000..be79b03
--- /dev/null
+++ b/board/amcc/ocotea/README.ocotea
@@ -0,0 +1,73 @@
+ AMCC Ocotea Board
+
+ Last Update: March 2, 2004
+=======================================================================
+
+This file contains some handy info regarding U-Boot and the AMCC
+Ocotea 440gx evaluation board. See the README.ppc440 for additional
+information.
+
+
+SWITCH SETTINGS & JUMPERS
+==========================
+
+Here's what I've been using successfully. If you feel inclined to
+change things ... please read the docs!
+
+DIPSW U46 U80
+------------------------
+SW 1 off off
+SW 2 on off
+SW 3 off off
+SW 4 off off
+SW 5 off off
+SW 6 on on
+SW 7 on off
+SW 8 on off
+
+J41: strapped
+J42: open
+
+All others are factory default.
+
+
+I2C Information
+=====================
+
+See README.ebony for information.
+
+PCI
+===========================
+
+Untested at the time of writing.
+
+PPC440GX Ethernet EMACs
+===========================
+
+All EMAC ports have been tested and are known to work
+with EPS Group 4.
+
+Special note about the Cicada CIS8201:
+ The CIS8201 Gigabit PHY comes up in GMII mode by default.
+ One must hit an extended register to allow use of RGMII mode.
+ This has been done in the 440gx_enet.c file with a #ifdef/endif
+ pair.
+
+AMCC does not store the EMAC ethernet addresses within their PIBS bootloader.
+The addresses contained in the config header file are from my particular
+board and you _*should*_ change them to reflect your board either in the
+config file and/or in your environment variables. I found the addresses on
+labels on the bottom side of the board.
+
+
+BDI2k or JTAG Debugging
+===========================
+
+For ease of debugging you can swap the small boot flash and external SRAM
+by changing U46:3 to on. You can then use the sram as your boot flash by
+loading the sram via the jtag debugger.
+
+
+Regards,
+--Travis
+<tsawyer@sandburst.com>
diff --git a/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot b/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot
new file mode 100644
index 0000000..25dd2a2
--- /dev/null
+++ b/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot
@@ -0,0 +1,99 @@
+------------------------------------------
+Installation of U-Boot using PIBS firmware
+------------------------------------------
+
+This document describes how to install U-Boot on the Ocotea PPC440GX
+Evaluation Board. We do not erase the PIBS firmware but install U-Boot in the
+soldered FLASH. After this you should be able to switch between PIBS and
+U-Boot via the switch U46 SW1. Please check that SW1 is off (= open) before
+continuing.
+
+Connect to the serial port 0 (J11 lower) of the Ocotea board using the cu
+program. See the hints for configuring cu above. Make sure you can
+communicate with the PIBS firmware: reset the board and hit ENTER a couple of
+times until you see the PIBS prompt (PIBS $). Then proceed as follows:
+
+
+Read MAC Addresses from PIBS
+----------------------------
+
+To read the configured MAC addresses available on your Ocotea board please use
+the following commands:
+
+PIBS $ echo $hwdaddr0
+000173017FE3
+PIBS $ echo $hwdaddr1
+000173017FE4
+PIBS $ echo $hwdaddr2
+000173017FE1
+PIBS $ echo $hwdaddr3
+000173017FE2
+
+In U-Boot this is stored in the following environment variables:
+
+* Ethernet Address 0: ethaddr = 000173017FE3 (==> 00:01:73:01:7F:E3)
+* Ethernet Address 1: eth1addr = 000173017FE4 (==> 00:01:73:01:7F:E4)
+* Ethernet Address 2: eth2addr = 000173017FE1 (==> 00:01:73:01:7F:E1)
+* Ethernet Address 3: eth3addr = 000173017FE2 (==> 00:01:73:01:7F:E2)
+
+
+Configure the network interface (ent0 == emac0)
+-----------------------------------------------
+
+To download the U-Boot image we need to configure the ethernet interface with
+the following commands:
+
+PIBS $ ifconfig ent0 192.168.160.142 netmask 255.255.0.0 up
+PIBS $ set ipdstaddr0=192.168.1.1
+status: writing PIBS variable value to FLASH
+PIBS $ set bootfilename=/tftpboot/ocotea/u-boot.bin
+status: writing PIBS variable value to FLASH
+
+Please insert correct parameters for your configuration (ip-addresses and
+file-location).
+
+
+Program U-Boot into soldered User-FLASH
+---------------------------------------
+
+Please make sure to use a newer version of U-Boot (at least 1.1.3), since
+older versions don't support running from user-FLASH.
+
+To program U-Boot into the soldered user-FLASH use the following command:
+
+PIBS $ storefile bin eth 0xffbc0000
+
+This commands loads the file vis ethernet into ram and copies it into the
+user-FLASH.
+
+
+Switch to U-Boot
+----------------
+
+Now you can turn your board off and switch SW1 (U46) to on (= closed). After
+powering the board you should see the following message:
+
+U-Boot 1.1.3 (Apr 5 2005 - 22:59:57)
+
+AMCC PowerPC 440 GX Rev. C
+Board: AMCC 440GX Evaluation Board
+ VCO: 1066 MHz
+ CPU: 533 MHz
+ PLB: 152 MHz
+ OPB: 76 MHz
+ EPB: 76 MHz
+I2C: ready
+DRAM: 256 MB
+FLASH: 5 MB
+PCI: Bus Dev VenId DevId Class Int
+In: serial
+Out: serial
+Err: serial
+KGDB: kgdb ready
+ready
+Net: ppc_440x_eth0, ppc_440x_eth1, ppc_440x_eth2, ppc_440x_eth3
+BEDBUG:ready
+=>
+
+
+April 06 2005, Stefan Roese <sr@denx.de>
diff --git a/board/amcc/ocotea/config.mk b/board/amcc/ocotea/config.mk
new file mode 100644
index 0000000..e19b561
--- /dev/null
+++ b/board/amcc/ocotea/config.mk
@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#
+# AMCC 440GX Reference Platform (Ocotea) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/ocotea/flash.c b/board/amcc/ocotea/flash.c
new file mode 100644
index 0000000..a9bbf04
--- /dev/null
+++ b/board/amcc/ocotea/flash.c
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+#define BOOT_SMALL_FLASH 0x40 /* 01000000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+
+#define BOOT_SMALL_FLASH_VAL 4
+#define FLASH_ONBD_N_VAL 2
+#define FLASH_SRAM_SEL_VAL 1
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
+ {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */
+ {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */
+ {0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */
+ {0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */
+ {0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+ unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
+ unsigned char switch_status;
+ unsigned short index = 0;
+ int i;
+
+ /* read FPGA base register FPGA_REG0 */
+ switch_status = *fpga_base;
+
+ /* check the bitmap of switch status */
+ if (switch_status & BOOT_SMALL_FLASH) {
+ index += BOOT_SMALL_FLASH_VAL;
+ }
+ if (switch_status & FLASH_ONBD_N) {
+ index += FLASH_ONBD_N_VAL;
+ }
+ if (switch_status & FLASH_SRAM_SEL) {
+ index += FLASH_SRAM_SEL_VAL;
+ }
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0) {
+ continue;
+ }
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] =
+ flash_get_size((vu_long *) flash_addr_table[index][i],
+ &flash_info[i]);
+ flash_info[i].size = size_b[i];
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf
+ ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+ &flash_info[i]);
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#endif
+
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S
new file mode 100644
index 0000000..35085f0
--- /dev/null
+++ b/board/amcc/ocotea/init.S
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
+ tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
+ tlbtab_end
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
new file mode 100644
index 0000000..5f11f19
--- /dev/null
+++ b/board/amcc/ocotea/ocotea.c
@@ -0,0 +1,387 @@
+/*
+ * Copyright (C) 2004 PaulReynolds@lhsolutions.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include "ocotea.h"
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <asm/ppc4xx-emac.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BOOT_SMALL_FLASH 32 /* 00100000 */
+#define FLASH_ONBD_N 2 /* 00000010 */
+#define FLASH_SRAM_SEL 1 /* 00000001 */
+
+long int fixed_sdram (void);
+void fpga_init (void);
+
+int board_early_init_f (void)
+{
+ unsigned long mfr;
+ unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE;
+ unsigned char switch_status;
+ unsigned long cs0_base;
+ unsigned long cs0_size;
+ unsigned long cs0_twt;
+ unsigned long cs2_base;
+ unsigned long cs2_size;
+ unsigned long cs2_twt;
+
+ /*-------------------------------------------------------------------------+
+ | Initialize EBC CONFIG
+ +-------------------------------------------------------------------------*/
+ mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
+ EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
+ EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
+ EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
+ EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
+
+ /*-------------------------------------------------------------------------+
+ | FPGA. Initialize bank 7 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
+ EBC_BXAP_BCE_DISABLE|
+ EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+ EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+ EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+ EBC_BXAP_BEM_WRITEONLY|
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
+ EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+ /* read FPGA base register FPGA_REG0 */
+ switch_status = *fpga_base;
+
+ if (switch_status & 0x40) {
+ cs0_base = 0xFFE00000;
+ cs0_size = EBC_BXCR_BS_2MB;
+ cs0_twt = 8;
+ cs2_base = 0xFF800000;
+ cs2_size = EBC_BXCR_BS_4MB;
+ cs2_twt = 10;
+ } else {
+ cs0_base = 0xFFC00000;
+ cs0_size = EBC_BXCR_BS_4MB;
+ cs0_twt = 10;
+ cs2_base = 0xFF800000;
+ cs2_size = EBC_BXCR_BS_2MB;
+ cs2_twt = 8;
+ }
+
+ /*-------------------------------------------------------------------------+
+ | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
+ EBC_BXAP_BCE_DISABLE|
+ EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+ EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+ EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+ EBC_BXAP_BEM_WRITEONLY|
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)|
+ cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+ /*-------------------------------------------------------------------------+
+ | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
+ EBC_BXAP_BCE_DISABLE|
+ EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+ EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+ EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+ EBC_BXAP_BEM_WRITEONLY|
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)|
+ EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+ /*-------------------------------------------------------------------------+
+ | 4 MB FLASH. Initialize bank 2 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
+ EBC_BXAP_BCE_DISABLE|
+ EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+ EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+ EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+ EBC_BXAP_BEM_WRITEONLY|
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)|
+ cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+ /*-------------------------------------------------------------------------+
+ | FPGA. Initialize bank 7 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
+ EBC_BXAP_BCE_DISABLE|
+ EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+ EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+ EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+ EBC_BXAP_BEM_WRITEONLY|
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
+ EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ /*
+ * Because of the interrupt handling rework to handle 440GX interrupts
+ * with the common code, we needed to change names of the UIC registers.
+ * Here the new relationship:
+ *
+ * U-Boot name 440GX name
+ * -----------------------
+ * UIC0 UICB0
+ * UIC1 UIC0
+ * UIC2 UIC1
+ * UIC3 UIC2
+ */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+ mtdcr (UIC1ER, 0x00000000); /* disable all */
+ mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
+ mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
+ mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+ mtdcr (UIC2ER, 0x00000000); /* disable all */
+ mtdcr (UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+ mtdcr (UIC3ER, 0x00000000); /* disable all */
+ mtdcr (UIC3CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
+ mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC0SR, 0xfc000000); /* clear all */
+ mtdcr (UIC0ER, 0x00000000); /* disable all */
+ mtdcr (UIC0CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC0PR, 0xfc000000); /* */
+ mtdcr (UIC0TR, 0x00000000); /* */
+ mtdcr (UIC0VR, 0x00000001); /* */
+ mfsdr (SDR0_MFR, mfr);
+ mfr &= ~SDR0_MFR_ECS_MASK;
+/* mtsdr(SDR0_MFR, mfr); */
+ fpga_init();
+
+ return 0;
+}
+
+
+int checkboard (void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc ('\n');
+
+ return (0);
+}
+
+
+phys_size_t initdram (int board_type)
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram ();
+#else
+ dram_size = fixed_sdram ();
+#endif
+ return dram_size;
+}
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ *
+ * Assumes: 128 MB, non-ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup some default
+ *------------------------------------------------------------------*/
+ mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
+ mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+
+ /*--------------------------------------------------------------------
+ * Setup for board-specific specific mem
+ *------------------------------------------------------------------*/
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+ /* RA=10 RD=3 */
+ mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
+ mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
+ mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
+ udelay (400); /* Delay 200 usecs (min) */
+
+ /*--------------------------------------------------------------------
+ * Enable the controller, then wait for DCEN to complete
+ *------------------------------------------------------------------*/
+ mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
+ for (;;) {
+ mfsdram (SDRAM0_MCSTS, reg);
+ if (reg & 0x80000000)
+ break;
+ }
+
+ return (128 * 1024 * 1024); /* 128 MB */
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+void fpga_init(void)
+{
+ unsigned long group;
+ unsigned long sdr0_pfc0;
+ unsigned long sdr0_pfc1;
+ unsigned long sdr0_cust0;
+ unsigned long pvr;
+
+ mfsdr (SDR0_PFC0, sdr0_pfc0);
+ mfsdr (SDR0_PFC1, sdr0_pfc1);
+ group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
+ pvr = get_pvr ();
+
+ sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
+ if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
+ sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
+ out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+ FPGA_REG2_EXT_INTFACE_ENABLE);
+ mtsdr (SDR0_PFC0, sdr0_pfc0);
+ mtsdr (SDR0_PFC1, sdr0_pfc1);
+ } else {
+ sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
+ switch (group)
+ {
+ case 0:
+ case 1:
+ case 2:
+ /* CPU trace A */
+ out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+ FPGA_REG2_EXT_INTFACE_ENABLE);
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
+ mtsdr (SDR0_PFC0, sdr0_pfc0);
+ mtsdr (SDR0_PFC1, sdr0_pfc1);
+ break;
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ /* CPU trace B - Over EBMI */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
+ mtsdr (SDR0_PFC0, sdr0_pfc0);
+ mtsdr (SDR0_PFC1, sdr0_pfc1);
+ out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+ FPGA_REG2_EXT_INTFACE_DISABLE);
+ break;
+ }
+ }
+
+ /* Initialize the ethernet specific functions in the fpga */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_CUST0, sdr0_cust0);
+ if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
+ ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
+ (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
+ {
+ if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+ {
+ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
+ FPGA_REG3_ENET_GROUP7);
+ }
+ else
+ {
+ if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
+ {
+ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+ FPGA_REG3_ENET_GROUP7);
+ }
+ else
+ {
+ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+ FPGA_REG3_ENET_GROUP8);
+ }
+ }
+ }
+ else
+ {
+ if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+ {
+ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
+ FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
+ }
+ else
+ {
+ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+ FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
+ }
+ }
+ out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
+ FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
+ FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
+
+ /* reset the gigabyte phy if necessary */
+ if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
+ {
+ if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+ {
+ out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
+ udelay(10000);
+ out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
+ }
+ else
+ {
+ out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
+ udelay(10000);
+ out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
+ }
+ }
+
+ /*
+ * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
+ */
+ if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
+ out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
+ udelay(10000);
+ out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
+ }
+
+ /* Turn off the LED's */
+ out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
+ FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
+ FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
+
+ return;
+}
diff --git a/board/amcc/ocotea/ocotea.h b/board/amcc/ocotea/ocotea.h
new file mode 100644
index 0000000..853002f
--- /dev/null
+++ b/board/amcc/ocotea/ocotea.h
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Board specific FPGA stuff ... */
+#define FPGA_REG0 (CONFIG_SYS_FPGA_BASE + 0x00)
+#define FPGA_REG0_SSCG_MASK 0x80
+#define FPGA_REG0_SSCG_DISABLE 0x00
+#define FPGA_REG0_SSCG_ENABLE 0x80
+#define FPGA_REG0_BOOT_MASK 0x40
+#define FPGA_REG0_BOOT_LARGE_FLASH 0x00
+#define FPGA_REG0_BOOT_SMALL_FLASH 0x40
+#define FPGA_REG0_ECLS_MASK 0x38 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_0 0x20 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_1 0x10 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_2 0x08 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER1 0x00 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER3 0x08 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER4 0x10 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER5 0x18 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER2 0x20 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER6 0x28 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER7 0x30 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ECLS_VER8 0x38 /* New for Ocotea Rev 2 */
+#define FPGA_REG0_ARBITER_MASK 0x04
+#define FPGA_REG0_ARBITER_EXT 0x00
+#define FPGA_REG0_ARBITER_INT 0x04
+#define FPGA_REG0_ONBOARD_FLASH_MASK 0x02
+#define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00
+#define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02
+#define FPGA_REG0_FLASH 0x01
+#define FPGA_REG1 (CONFIG_SYS_FPGA_BASE + 0x01)
+#define FPGA_REG1_9772_FSELFBX_MASK 0x80
+#define FPGA_REG1_9772_FSELFBX_6 0x00
+#define FPGA_REG1_9772_FSELFBX_10 0x80
+#define FPGA_REG1_9531_SX_MASK 0x60
+#define FPGA_REG1_9531_SX_33MHZ 0x00
+#define FPGA_REG1_9531_SX_100MHZ 0x20
+#define FPGA_REG1_9531_SX_66MHZ 0x40
+#define FPGA_REG1_9531_SX_133MHZ 0x60
+#define FPGA_REG1_9772_FSELBX_MASK 0x18
+#define FPGA_REG1_9772_FSELBX_4 0x00
+#define FPGA_REG1_9772_FSELBX_6 0x08
+#define FPGA_REG1_9772_FSELBX_8 0x10
+#define FPGA_REG1_9772_FSELBX_10 0x18
+#define FPGA_REG1_SOURCE_MASK 0x07
+#define FPGA_REG1_SOURCE_TC 0x00
+#define FPGA_REG1_SOURCE_66MHZ 0x01
+#define FPGA_REG1_SOURCE_50MHZ 0x02
+#define FPGA_REG1_SOURCE_33MHZ 0x03
+#define FPGA_REG1_SOURCE_25MHZ 0x04
+#define FPGA_REG1_SOURCE_SSDIV1 0x05
+#define FPGA_REG1_SOURCE_SSDIV2 0x06
+#define FPGA_REG1_SOURCE_SSDIV4 0x07
+#define FPGA_REG2 (CONFIG_SYS_FPGA_BASE + 0x02)
+#define FPGA_REG2_TC0 0x80
+#define FPGA_REG2_TC1 0x40
+#define FPGA_REG2_TC2 0x20
+#define FPGA_REG2_TC3 0x10
+#define FPGA_REG2_GIGABIT_RESET_DISABLE 0x08 /*Use on Ocotea pass 2 boards*/
+#define FPGA_REG2_EXT_INTFACE_MASK 0x04
+#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00
+#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04
+#define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/
+#define FPGA_REG2_DEFAULT_UART1_N 0x01
+#define FPGA_REG3 (CONFIG_SYS_FPGA_BASE + 0x03)
+#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/
+#define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/
+#define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/
+#define FPGA_REG3_ENET_GROUP0 0x00
+#define FPGA_REG3_ENET_GROUP1 0x10
+#define FPGA_REG3_ENET_GROUP2 0x20
+#define FPGA_REG3_ENET_GROUP3 0x30
+#define FPGA_REG3_ENET_GROUP4 0x40
+#define FPGA_REG3_ENET_GROUP5 0x50
+#define FPGA_REG3_ENET_GROUP6 0x60
+#define FPGA_REG3_ENET_GROUP7 0x70
+#define FPGA_REG3_ENET_GROUP8 0x80 /*Use on Ocotea pass 2 boards*/
+#define FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/
+#define FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/
+#define FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/
+#define FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/
+#define FPGA_REG3_STAT_MASK 0x0F
+#define FPGA_REG3_STAT_LED8_ENAB 0x08
+#define FPGA_REG3_STAT_LED4_ENAB 0x04
+#define FPGA_REG3_STAT_LED2_ENAB 0x02
+#define FPGA_REG3_STAT_LED1_ENAB 0x01
+#define FPGA_REG3_STAT_LED8_DISAB 0x00
+#define FPGA_REG3_STAT_LED4_DISAB 0x00
+#define FPGA_REG3_STAT_LED2_DISAB 0x00
+#define FPGA_REG3_STAT_LED1_DISAB 0x00
+#define FPGA_REG4 (CONFIG_SYS_FPGA_BASE + 0x04)
+#define FPGA_REG4_GPHY_MODE10 0x80
+#define FPGA_REG4_GPHY_MODE100 0x40
+#define FPGA_REG4_GPHY_MODE1000 0x20
+#define FPGA_REG4_GPHY_FRC_DPLX 0x10
+#define FPGA_REG4_GPHY_ANEG_DIS 0x08
+#define FPGA_REG4_CONNECT_PHYS 0x04
+
+
+#define SDR0_CUST0_ENET3_MASK 0x00000080
+#define SDR0_CUST0_ENET3_COPPER 0x00000000
+#define SDR0_CUST0_ENET3_FIBER 0x00000080
+#define SDR0_CUST0_RGMII3_MASK 0x00000070
+#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
+#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
+#define SDR0_CUST0_RGMII3_DISAB 0x00000000
+#define SDR0_CUST0_RGMII3_RTBI 0x00000040
+#define SDR0_CUST0_RGMII3_RGMII 0x00000050
+#define SDR0_CUST0_RGMII3_TBI 0x00000060
+#define SDR0_CUST0_RGMII3_GMII 0x00000070
+#define SDR0_CUST0_ENET2_MASK 0x00000008
+#define SDR0_CUST0_ENET2_COPPER 0x00000000
+#define SDR0_CUST0_ENET2_FIBER 0x00000008
+#define SDR0_CUST0_RGMII2_MASK 0x00000007
+#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
+#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
+#define SDR0_CUST0_RGMII2_DISAB 0x00000000
+#define SDR0_CUST0_RGMII2_RTBI 0x00000004
+#define SDR0_CUST0_RGMII2_RGMII 0x00000005
+#define SDR0_CUST0_RGMII2_TBI 0x00000006
+#define SDR0_CUST0_RGMII2_GMII 0x00000007
diff --git a/board/amcc/redwood/Kconfig b/board/amcc/redwood/Kconfig
new file mode 100644
index 0000000..d710590
--- /dev/null
+++ b/board/amcc/redwood/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_REDWOOD
+
+config SYS_BOARD
+ default "redwood"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "redwood"
+
+endif
diff --git a/board/amcc/redwood/MAINTAINERS b/board/amcc/redwood/MAINTAINERS
new file mode 100644
index 0000000..756b301
--- /dev/null
+++ b/board/amcc/redwood/MAINTAINERS
@@ -0,0 +1,6 @@
+REDWOOD BOARD
+M: Feng Kan <fkan@amcc.com>
+S: Maintained
+F: board/amcc/redwood/
+F: include/configs/redwood.h
+F: configs/redwood_defconfig
diff --git a/board/amcc/redwood/Makefile b/board/amcc/redwood/Makefile
new file mode 100644
index 0000000..2bc632b
--- /dev/null
+++ b/board/amcc/redwood/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2008
+# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = redwood.o
+extra-y += init.o
diff --git a/board/amcc/redwood/config.mk b/board/amcc/redwood/config.mk
new file mode 100644
index 0000000..42b3e5f
--- /dev/null
+++ b/board/amcc/redwood/config.mk
@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2008
+# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#
+# AMCC 460SX Reference Platform (redwood) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/redwood/init.S b/board/amcc/redwood/init.S
new file mode 100644
index 0000000..fd05130
--- /dev/null
+++ b/board/amcc/redwood/init.S
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ /* Although 512 KB, map 256k at a time */
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+ tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_RWX | SA_I)
+
+ tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
+
+ /*
+ * Peripheral base
+ */
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_RW | SA_IG)
+ tlbtab_end
diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c
new file mode 100644
index 0000000..15c3884
--- /dev/null
+++ b/board/amcc/redwood/redwood.c
@@ -0,0 +1,440 @@
+/*
+ * This is the main board level file for the Redwood AMCC board.
+ *
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "redwood.h"
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+int compare_to_true(char *str);
+char *remove_l_w_space(char *in_str);
+char *remove_t_w_space(char *in_str);
+int get_console_port(void);
+
+static void early_init_EBC(void);
+static int bootdevice_selected(void);
+static void early_reinit_EBC(int);
+static void early_init_UIC(void);
+
+/*
+ * Define Boot devices
+ */
+#define BOOT_FROM_8BIT_SRAM 0x00
+#define BOOT_FROM_16BIT_SRAM 0x01
+#define BOOT_FROM_32BIT_SRAM 0x02
+#define BOOT_FROM_8BIT_NAND 0x03
+#define BOOT_FROM_16BIT_NOR 0x04
+#define BOOT_DEVICE_UNKNOWN 0xff
+
+/*
+ * EBC Devices Characteristics
+ * Peripheral Bank Access Parameters - EBC_BxAP
+ * Peripheral Bank Configuration Register - EBC_BxCR
+ */
+
+/*
+ * 8 bit width SRAM
+ * BU Value
+ * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
+ * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
+ */
+#define EBC_BXAP_8BIT_SRAM \
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
+ EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXAP_16BIT_SRAM EBC_BXAP_8BIT_SRAM
+#define EBC_BXAP_32BIT_SRAM EBC_BXAP_8BIT_SRAM
+
+/*
+ * NAND flash
+ * BU Value
+ * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_NAND \
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
+ EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED
+
+/*
+ * NOR flash
+ * BU Value
+ * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_NOR \
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \
+ EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED
+
+/*
+ * FPGA
+ * BU value :
+ * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
+ * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
+ */
+#define EBC_BXAP_FPGA \
+ EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(11) | \
+ EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1) | \
+ EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_RW | \
+ EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_8BIT_SRAM_CS0 \
+ EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_32BIT_SRAM_CS0 \
+ EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT
+
+#define EBC_BXCR_NAND_CS0 \
+ EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_16BIT_SRAM_CS0 \
+ EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NOR_CS0 \
+ EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NOR_CS1 \
+ EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_NAND_CS1 \
+ EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_NAND_CS2 \
+ EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_SRAM_CS2 \
+ EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT
+
+#define EBC_BXCR_LARGE_FLASH_CS2 \
+ EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_FPGA_CS3 \
+ EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT
+
+/*****************************************************************************
+ * UBOOT initiated board specific function calls
+ ****************************************************************************/
+
+int board_early_init_f(void)
+{
+ int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+ /*
+ * Initialise EBC
+ */
+ early_init_EBC();
+
+ /*
+ * Determine which boot device was selected
+ */
+ computed_boot_device = bootdevice_selected();
+
+ /*
+ * Reinit EBC based on selected boot device
+ */
+ early_reinit_EBC(computed_boot_device);
+
+ /*
+ * Setup for UIC on 460SX redwood board
+ */
+ early_init_UIC();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: Redwood - AMCC 460SX Reference Board");
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+static void early_init_EBC(void)
+{
+ /*
+ * Initialize EBC CONFIG -
+ * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+ * default value :
+ * 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+ */
+ mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
+ EBC_CFG_PTD_ENABLE |
+ EBC_CFG_RTC_16PERCLK |
+ EBC_CFG_ATC_PREVIOUS |
+ EBC_CFG_DTC_PREVIOUS |
+ EBC_CFG_CTC_PREVIOUS |
+ EBC_CFG_OEO_PREVIOUS |
+ EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16);
+
+ /*
+ * PART 1 : Initialize EBC Bank 3
+ * ==============================
+ * Bank1 is always associated to the EPLD.
+ * It has to be initialized prior to other banks settings computation
+ * since some board registers values may be needed to determine the
+ * boot type
+ */
+ mtebc(PB1AP, EBC_BXAP_FPGA);
+ mtebc(PB1CR, EBC_BXCR_FPGA_CS3);
+
+}
+
+static int bootdevice_selected(void)
+{
+ unsigned long sdr0_pinstp;
+ unsigned long bootstrap_settings;
+ int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+ /*
+ * Determine which boot device was selected
+ * =================================================
+ *
+ * Read Pin Strap Register in PPC460SX
+ * Result can either be :
+ * - Boot strap = boot from EBC 8bits => Small Flash
+ * - Boot strap = boot from PCI
+ * - Boot strap = IIC
+ * In case of boot from IIC, read Serial Device Strap Register1
+ *
+ * Result can either be :
+ * - Boot from EBC - EBC Bus Width = 8bits => Small Flash
+ * - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
+ * - Boot from PCI
+ */
+
+ /* Read Pin Strap Register in PPC460SX */
+ mfsdr(SDR0_PINSTP, sdr0_pinstp);
+ bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK;
+
+ switch (bootstrap_settings) {
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+ /*
+ * Boot from SRAM, 8bit width
+ */
+ computed_boot_device = BOOT_FROM_8BIT_SRAM;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+ /*
+ * Boot from SRAM, 32bit width
+ */
+ computed_boot_device = BOOT_FROM_32BIT_SRAM;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+ /*
+ * Boot from NAND, 8bit width
+ */
+ computed_boot_device = BOOT_FROM_8BIT_NAND;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
+ /*
+ * Boot from SRAM, 16bit width
+ * Boot setting in IIC EEPROM 0x50
+ */
+ computed_boot_device = BOOT_FROM_16BIT_SRAM;
+ break;
+ case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5:
+ /*
+ * Boot from NOR, 16bit width
+ * Boot setting in IIC EEPROM 0x54
+ */
+ computed_boot_device = BOOT_FROM_16BIT_NOR;
+ break;
+ default:
+ /* should not be */
+ computed_boot_device = BOOT_DEVICE_UNKNOWN;
+ break;
+ }
+
+ return computed_boot_device;
+}
+
+static void early_reinit_EBC(int computed_boot_device)
+{
+ /*
+ * Compute EBC settings depending on selected boot device
+ * ======================================================
+ *
+ * Resulting EBC init will be among following configurations :
+ *
+ * - Boot from EBC 8bits => boot from Small Flash selected
+ * EBC-CS0 = Small Flash
+ * EBC-CS2 = Large Flash and SRAM
+ *
+ * - Boot from EBC 16bits => boot from Large Flash or SRAM
+ * EBC-CS0 = Large Flash or SRAM
+ * EBC-CS2 = Small Flash
+ *
+ * - Boot from PCI
+ * EBC-CS0 = not initialized to avoid address contention
+ * EBC-CS2 = same as boot from Small Flash selected
+ */
+
+ unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
+ unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0;
+ unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
+
+ switch (computed_boot_device) {
+ /*-------------------------------------------------------------------*/
+ case BOOT_FROM_8BIT_SRAM:
+ /*-------------------------------------------------------------------*/
+ ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM;
+ ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0;
+ ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+ ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+ ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+ ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+ break;
+
+ /*-------------------------------------------------------------------*/
+ case BOOT_FROM_16BIT_SRAM:
+ /*-------------------------------------------------------------------*/
+ ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM;
+ ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0;
+ ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+ ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+ ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+ ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+ break;
+
+ /*-------------------------------------------------------------------*/
+ case BOOT_FROM_32BIT_SRAM:
+ /*-------------------------------------------------------------------*/
+ ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM;
+ ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0;
+ ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+ ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+ ebc0_cs2_bxap_value = EBC_BXAP_NAND;
+ ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
+ break;
+
+ /*-------------------------------------------------------------------*/
+ case BOOT_FROM_16BIT_NOR:
+ /*-------------------------------------------------------------------*/
+ ebc0_cs0_bxap_value = EBC_BXAP_NOR;
+ ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0;
+ ebc0_cs1_bxap_value = EBC_BXAP_NAND;
+ ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1;
+ ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
+ ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
+ break;
+
+ /*-------------------------------------------------------------------*/
+ case BOOT_FROM_8BIT_NAND:
+ /*-------------------------------------------------------------------*/
+ ebc0_cs0_bxap_value = EBC_BXAP_NAND;
+ ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0;
+ ebc0_cs1_bxap_value = EBC_BXAP_NOR;
+ ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
+ ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
+ ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
+ break;
+
+ /*-------------------------------------------------------------------*/
+ default:
+ /*-------------------------------------------------------------------*/
+ /* BOOT_DEVICE_UNKNOWN */
+ break;
+ }
+
+ mtebc(PB0AP, ebc0_cs0_bxap_value);
+ mtebc(PB0CR, ebc0_cs0_bxcr_value);
+ mtebc(PB1AP, ebc0_cs1_bxap_value);
+ mtebc(PB1CR, ebc0_cs1_bxcr_value);
+ mtebc(PB2AP, ebc0_cs2_bxap_value);
+ mtebc(PB2CR, ebc0_cs2_bxcr_value);
+}
+
+static void early_init_UIC(void)
+{
+ /*
+ * Initialise UIC registers. Clear all interrupts. Disable all
+ * interrupts.
+ * Set critical interrupt values. Set interrupt polarities. Set
+ * interrupt trigger levels. Make bit 0 High priority. Clear all
+ * interrupts again.
+ */
+ mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */
+ mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical
+ * interrupts */
+ mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
+ mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical
+ * interrupts */
+ mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
+ mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
+ mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical
+ * interrupts */
+ mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted
+ * cascade to be checked */
+ mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical
+ * interrupts */
+ mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
+
+}
diff --git a/board/amcc/redwood/redwood.h b/board/amcc/redwood/redwood.h
new file mode 100644
index 0000000..9c36073
--- /dev/null
+++ b/board/amcc/redwood/redwood.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuit Corp., fkan@amcc.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __REDWOOD_H_
+#define __REDWOOD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------+
+| Defines
++----------------------------------------------------------------------------*/
+/* Pin Straps Reg */
+#define SDR0_PSTRP0 0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __REDWOOD_H_ */
diff --git a/board/amcc/sequoia/Kconfig b/board/amcc/sequoia/Kconfig
new file mode 100644
index 0000000..67ee3ca
--- /dev/null
+++ b/board/amcc/sequoia/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SEQUOIA
+
+config SYS_BOARD
+ default "sequoia"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "sequoia"
+
+endif
diff --git a/board/amcc/sequoia/MAINTAINERS b/board/amcc/sequoia/MAINTAINERS
new file mode 100644
index 0000000..6c28a37
--- /dev/null
+++ b/board/amcc/sequoia/MAINTAINERS
@@ -0,0 +1,9 @@
+SEQUOIA BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/amcc/sequoia/
+F: include/configs/sequoia.h
+F: configs/rainier_defconfig
+F: configs/rainier_ramboot_defconfig
+F: configs/sequoia_defconfig
+F: configs/sequoia_ramboot_defconfig
diff --git a/board/amcc/sequoia/Makefile b/board/amcc/sequoia/Makefile
new file mode 100644
index 0000000..b4ab5da
--- /dev/null
+++ b/board/amcc/sequoia/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = sequoia.o sdram.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+extra-y += init.o
diff --git a/board/amcc/sequoia/chip_config.c b/board/amcc/sequoia/chip_config.c
new file mode 100644
index 0000000..eef9316
--- /dev/null
+++ b/board/amcc/sequoia/chip_config.c
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "333-133-nor", "NOR CPU: 333 PLB: 133 OPB: 66 EBC: 66",
+ {
+ 0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "333-166-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 55",
+ {
+ 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "333-166-nand", "NAND CPU: 333 PLB: 166 OPB: 83 EBC: 55",
+ {
+ 0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
+ {
+ 0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-160-nor", "NOR CPU: 400 PLB: 160 OPB: 80 EBC: 53",
+ {
+ 0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "416-166-nor", "NOR CPU: 416 PLB: 166 OPB: 83 EBC: 55",
+ {
+ 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "416-166-nand", "NAND CPU: 416 PLB: 166 OPB: 83 EBC: 55",
+ {
+ 0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "500-166-nor", "NOR CPU: 500 PLB: 166 OPB: 83 EBC: 55",
+ {
+ 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "500-166-nand", "NAND CPU: 500 PLB: 166 OPB: 83 EBC: 55",
+ {
+ 0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "533-133-nor", "NOR CPU: 533 PLB: 133 OPB: 66 EBC: 66",
+ {
+ 0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "667-133-nor", "NOR CPU: 667 PLB: 133 OPB: 66 EBC: 66",
+ {
+ 0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "667-166-nor", "NOR CPU: 667 PLB: 166 OPB: 83 EBC: 55",
+ {
+ 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "667-166-nand", "NAND CPU: 667 PLB: 166 OPB: 83 EBC: 55",
+ {
+ 0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk
new file mode 100644
index 0000000..824e78f
--- /dev/null
+++ b/board/amcc/sequoia/config.mk
@@ -0,0 +1,19 @@
+#
+# (C) Copyright 2002-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+#
+# AMCC 440EPx Reference Platform (Sequoia) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
new file mode 100644
index 0000000..f876639
--- /dev/null
+++ b/board/amcc/sequoia/init.S
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ */
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /* vxWorks needs this as first entry for the Machine Check interrupt */
+ tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
+
+ /*
+ * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
+ * entry is already configured for SDRAM via the JTAG debugger and mustn't
+ * be re-initialized by this RAM-booting U-Boot version.
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+ /* TLB-entry for DDR SDRAM (Up to 2GB) */
+#ifdef CONFIG_4xx_DCACHE
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G)
+#else
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
+#endif
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ /* TLB-entry for EBC */
+ tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG )
+
+ /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
+
+ /* TLB-entry for NAND */
+ tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
+
+ /*TLB-entry PCI registers*/
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
+
+ /* TLB-entry for peripherals */
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
+
+ /* TLB-entry PCI IO Space - from sr@denx.de */
+ tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
+
+ tlbtab_end
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
new file mode 100644
index 0000000..67640d7
--- /dev/null
+++ b/board/amcc/sequoia/sdram.c
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* define DEBUG for debug output */
+#undef DEBUG
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc440.h>
+
+/*-----------------------------------------------------------------------------+
+ * Prototypes
+ *-----------------------------------------------------------------------------*/
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
+
+/*************************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+phys_size_t initdram (int board_type)
+{
+#if !defined(CONFIG_SYS_RAMBOOT)
+ ulong speed = get_bus_freq(0);
+
+ mtsdram(DDR0_02, 0x00000000);
+
+ mtsdram(DDR0_00, 0x0000190A);
+ mtsdram(DDR0_01, 0x01000000);
+ mtsdram(DDR0_03, 0x02030602);
+ mtsdram(DDR0_04, 0x0A020200);
+ mtsdram(DDR0_05, 0x02020308);
+ mtsdram(DDR0_06, 0x0102C812);
+ mtsdram(DDR0_07, 0x000D0100);
+ mtsdram(DDR0_08, 0x02430001);
+ mtsdram(DDR0_09, 0x00011D5F);
+ mtsdram(DDR0_10, 0x00000100);
+ mtsdram(DDR0_11, 0x0027C800);
+ mtsdram(DDR0_12, 0x00000003);
+ mtsdram(DDR0_14, 0x00000000);
+ mtsdram(DDR0_17, 0x19000000);
+ mtsdram(DDR0_18, 0x19191919);
+ mtsdram(DDR0_19, 0x19191919);
+ mtsdram(DDR0_20, 0x0B0B0B0B);
+ mtsdram(DDR0_21, 0x0B0B0B0B);
+ mtsdram(DDR0_22, 0x00267F0B);
+ mtsdram(DDR0_23, 0x00000000);
+ mtsdram(DDR0_24, 0x01010002);
+ if (speed > 133333334)
+ mtsdram(DDR0_26, 0x5B26050C);
+ else
+ mtsdram(DDR0_26, 0x5B260408);
+ mtsdram(DDR0_27, 0x0000682B);
+ mtsdram(DDR0_28, 0x00000000);
+ mtsdram(DDR0_31, 0x00000000);
+ mtsdram(DDR0_42, 0x01000006);
+ mtsdram(DDR0_43, 0x030A0200);
+ mtsdram(DDR0_44, 0x00000003);
+ mtsdram(DDR0_02, 0x00000001);
+
+ denali_wait_for_dlllock();
+#endif /* #ifndef CONFIG_SYS_RAMBOOT */
+
+#ifdef CONFIG_DDR_DATA_EYE
+ /* -----------------------------------------------------------+
+ * Perform data eye search if requested.
+ * ----------------------------------------------------------*/
+ denali_core_search_data_eye();
+#endif
+
+ /*
+ * Clear possible errors resulting from data-eye-search.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
+ return (CONFIG_SYS_MBYTES_SDRAM << 20);
+}
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
new file mode 100644
index 0000000..91c6cbf
--- /dev/null
+++ b/board/amcc/sequoia/sequoia.c
@@ -0,0 +1,413 @@
+/*
+ * (C) Copyright 2006-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+#endif
+
+extern void __ft_board_setup(void *blob, bd_t *bd);
+ulong flash_get_size(ulong base, int banknum);
+
+static inline u32 get_async_pci_freq(void)
+{
+ if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
+ CONFIG_SYS_BCSR5_PCI66EN)
+ return 66666666;
+ else
+ return 33333333;
+}
+
+int board_early_init_f(void)
+{
+ u32 sdr0_cust0;
+ u32 sdr0_pfc1, sdr0_pfc2;
+ u32 reg;
+
+ mtdcr(EBC0_CFGADDR, EBC0_CFG);
+ mtdcr(EBC0_CFGDATA, 0xb8400000);
+
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ /* Check and reconfigure the PCI sync clock if necessary */
+ ppc4xx_pci_sync_clock_config(get_async_pci_freq());
+
+ /* 50MHz tmrclk */
+ out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
+
+ /* clear write protects */
+ out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
+
+ /* enable Ethernet */
+ out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
+
+ /* enable USB device */
+ out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
+
+ /* select Ethernet (and optionally IIC1) pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_4;
+#ifdef CONFIG_I2C_MULTI_BUS
+ sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
+#endif
+ /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
+
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_4;
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /* PCI arbiter enabled */
+ mfsdr(SDR0_PCI0, reg);
+ mtsdr(SDR0_PCI0, 0x80000000 | reg);
+
+ /* setup NAND FLASH */
+ mfsdr(SDR0_CUST0, sdr0_cust0);
+ sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
+ mtsdr(SDR0_CUST0, sdr0_cust0);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+#if !defined(CONFIG_SYS_NO_FLASH)
+ uint pbcr;
+ int size_val = 0;
+#endif
+#ifdef CONFIG_440EPX
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1;
+ char *act = getenv("usbact");
+#endif
+ u32 reg;
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+ /* Re-do flash sizing to get full correct info */
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+#if defined(CONFIG_SYS_RAMBOOT)
+ mtdcr(EBC0_CFGADDR, PB3CR);
+#else
+ mtdcr(EBC0_CFGADDR, PB0CR);
+#endif
+ pbcr = mfdcr(EBC0_CFGDATA);
+ size_val = ffs(gd->bd->bi_flashsize) - 21;
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+#if defined(CONFIG_SYS_RAMBOOT)
+ mtdcr(EBC0_CFGADDR, PB3CR);
+#else
+ mtdcr(EBC0_CFGADDR, PB0CR);
+#endif
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ /* Env protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+#endif /* CONFIG_SYS_NO_FLASH */
+
+ /*
+ * USB suff...
+ */
+#ifdef CONFIG_440EPX
+ if (act == NULL || strcmp(act, "hostdev") == 0) {
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+
+ /*
+ * An 8-bit/60MHz interface is the only possible alternative
+ * when connecting the Device to the PHY
+ */
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
+
+ /*
+ * To enable the USB 2.0 Device function
+ * through the UTMI interface
+ */
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /*clear resets*/
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay (1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host(int phy) Device(ext phy)\n");
+
+ } else if (strcmp(act, "dev") == 0) {
+ /*-------------------PATCH-------------------------------*/
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x672c6000);
+
+ udelay (1000);
+ mtsdr(SDR0_SRST0, 0x00000080);
+
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x60206000);
+
+ *(unsigned int *)(0xe0000350) = 0x00000001;
+
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x60306000);
+ /*-------------------PATCH-------------------------------*/
+
+ /* SDR Setting */
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
+
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
+
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
+
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /* clear resets */
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay (1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Device(int phy)\n");
+ }
+#endif /* CONFIG_440EPX */
+
+ mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
+ reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
+ mtsdr(SDR0_SRST1, reg);
+
+ /*
+ * Clear PLB4A0_ACR[WRP]
+ * This fix will make the MAL burst disabling patch for the Linux
+ * EMAC driver obsolete.
+ */
+ reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+ mtdcr(PLB4A0_ACR, reg);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+ u8 rev;
+ u32 clock = get_async_pci_freq();
+
+#ifdef CONFIG_440EPX
+ printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
+#else
+ printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
+#endif
+
+ rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
+ printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ /*
+ * Reconfiguration of the PCI sync clock is already done,
+ * now check again if everything is in range:
+ */
+ if (ppc4xx_pci_sync_clock_config(clock)) {
+ printf("ERROR: PCI clocking incorrect (async=%d "
+ "sync=%ld)!\n", clock, get_PCI_freq());
+ }
+
+ return (0);
+}
+
+#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
+/*
+ * Assign interrupts to PCI devices.
+ */
+void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
+}
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+/*
+ * On NAND-booting sequoia, we need to patch the chips select numbers
+ * in the dtb (CS0 - NAND, CS3 - NOR)
+ */
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int rc;
+ int len;
+ int nodeoffset;
+ struct fdt_property *prop;
+ u32 *reg;
+ char path[32];
+
+ /* First do common fdt setup */
+ __ft_board_setup(blob, bd);
+
+ /* And now configure NOR chip select to 3 instead of 0 */
+ strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
+ nodeoffset = fdt_path_offset(blob, path);
+ prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
+ if (prop == NULL) {
+ printf("Unable to update NOR chip select for NAND booting\n");
+ return -FDT_ERR_NOTFOUND;
+ }
+ reg = (u32 *)&prop->data[0];
+ reg[0] = 3;
+ rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
+ if (rc) {
+ printf("Unable to update property NOR mappings\n");
+ return rc;
+ }
+
+ /* And now configure NAND chip select to 0 instead of 3 */
+ strcpy(path, "/plb/opb/ebc/ndfc@3,0");
+ nodeoffset = fdt_path_offset(blob, path);
+ prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
+ if (prop == NULL) {
+ printf("Unable to update NDFC chip select for NAND booting\n");
+ return len;
+ }
+ reg = (u32 *)&prop->data[0];
+ reg[0] = 0;
+ rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
+ if (rc) {
+ printf("Unable to update property NDFC mapping\n");
+ return rc;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_SYS_RAMBOOT */
diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds
new file mode 100644
index 0000000..ef08be8
--- /dev/null
+++ b/board/amcc/sequoia/u-boot-ram.lds
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .text :
+ {
+ arch/powerpc/cpu/ppc4xx/start.o (.text*)
+ board/amcc/sequoia/init.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ KEEP(*(.got))
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/amcc/taihu/Kconfig b/board/amcc/taihu/Kconfig
new file mode 100644
index 0000000..fc5cb1d
--- /dev/null
+++ b/board/amcc/taihu/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TAIHU
+
+config SYS_BOARD
+ default "taihu"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "taihu"
+
+endif
diff --git a/board/amcc/taihu/MAINTAINERS b/board/amcc/taihu/MAINTAINERS
new file mode 100644
index 0000000..2efc254
--- /dev/null
+++ b/board/amcc/taihu/MAINTAINERS
@@ -0,0 +1,6 @@
+TAIHU BOARD
+M: John Otken <jotken@softadvances.com>
+S: Maintained
+F: board/amcc/taihu/
+F: include/configs/taihu.h
+F: configs/taihu_defconfig
diff --git a/board/amcc/taihu/Makefile b/board/amcc/taihu/Makefile
new file mode 100644
index 0000000..65606fe
--- /dev/null
+++ b/board/amcc/taihu/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = taihu.o flash.o lcd.o update.o
diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c
new file mode 100644
index 0000000..0780488
--- /dev/null
+++ b/board/amcc/taihu/flash.c
@@ -0,0 +1,1063 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+#define CONFIG_SYS_FLASH_CHAR_SIZE unsigned char
+#define CONFIG_SYS_FLASH_CHAR_ADDR0 (0x0aaa)
+#define CONFIG_SYS_FLASH_CHAR_ADDR1 (0x0555)
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef FLASH_BASE1_PRELIM
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+unsigned long flash_init(void)
+{
+ unsigned long size_b0, size_b1=0;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 =
+ flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ if (size_b0) {
+ /* Setup offsets */
+ flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+ &flash_info[0]);
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+ /* Also protect sector containing initial power-up instruction */
+ /* (flash_protect() checks address range - other call ignored) */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+ }
+#ifdef FLASH_BASE1_PRELIM
+ size_b1 =
+ flash_get_size((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1])*2;
+
+ if (flash_info[1].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+ size_b1, size_b1 << 20);
+ }
+
+ if (size_b1) {
+ /* Setup offsets */
+ flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]);
+ flash_info[1].size = size_b1;
+ }
+#endif
+ return (size_b0 + size_b1);
+}
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ (info->flash_id == FLASH_AM040)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000*2);
+ }
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000*2);
+ }
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+}
+
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_STM:
+ printf("STM ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf("SST ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ printf("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AMD016:
+ printf("AM29F016D (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM033C:
+ printf("AM29LV033C (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AMLV128U:
+ printf("AM29LV128U (128 Mbit * 2, top boot sector)\n");
+ break;
+ case FLASH_SST800A:
+ printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST160A:
+ printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_STMW320DT:
+ printf ("M29W320DT (32 M, top sector)\n");
+ break;
+ case FLASH_S29GL128N:
+ printf ("S29GL128N (256 Mbit, uniform sector size)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
+ }
+
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ", info->protect[i] ? "RO " : " ");
+ }
+ printf("\n");
+ return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef FLASH_BASE1_PRELIM
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+ if ((ulong)addr == FLASH_BASE1_PRELIM) {
+ return flash_get_size_2(addr, info);
+ } else {
+ return flash_get_size_1(addr, info);
+ }
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+ short i;
+ CONFIG_SYS_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return 0; /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
+ info->flash_id += FLASH_AMD016;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
+ info->flash_id += FLASH_AMDLV033C;
+ info->sector_count = 64;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return 0; /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ }
+ else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000 * 2);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return info->size;
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+ (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+ (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+#ifdef FLASH_BASE1_PRELIM
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+ return flash_erase_2(info, s_first, s_last);
+ } else {
+ return flash_erase_1(info, s_first, s_last);
+ }
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_1(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return rc;
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return rc;
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return 0;
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef FLASH_BASE1_PRELIM
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+ return write_word_2(info, dest, data);
+ } else {
+ return write_word_1(info, dest, data);
+ }
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+ ulong *data_ptr = &data;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return 2;
+ }
+
+ for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return 1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+#ifdef FLASH_BASE1_PRELIM
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+ short i;
+ CONFIG_SYS_FLASH_CHAR_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+ udelay(1000);
+
+ value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return 0; /* no or unknown flash */
+ }
+
+ value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[2]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F016D:
+ info->flash_id += FLASH_AMD016;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV033C:
+ info->flash_id += FLASH_AMDLV033C;
+ info->sector_count = 64;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+ case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_MIRROR:
+ if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_2
+ && (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) {
+ info->flash_id += FLASH_AMLV128U;
+ info->sector_count = 256;
+ info->size = 0x01000000;
+ } else if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_2
+ && (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) {
+ info->flash_id += FLASH_S29GL128N;
+ info->sector_count = 128;
+ info->size = 0x01000000;
+ }
+ else
+ info->flash_id = FLASH_UNKNOWN;
+ break; /* => 2 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return 0; /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMLV128U) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_S29GL128N ) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00020000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[4] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0;
+ return info->size;
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+ (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while (((CONFIG_SYS_FLASH_WORD_SIZE)addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) !=
+ (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+ addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080;
+ addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x50505050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+ addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080;
+ addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30303030; /* sector erase */
+ }
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_2(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+ ulong *data_ptr = &data;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return 2;
+ }
+
+ for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA0A0A0A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) !=
+ (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080)) {
+
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return 1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+#endif /* FLASH_BASE1_PRELIM */
diff --git a/board/amcc/taihu/lcd.c b/board/amcc/taihu/lcd.c
new file mode 100644
index 0000000..c7c7fa4
--- /dev/null
+++ b/board/amcc/taihu/lcd.c
@@ -0,0 +1,237 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#define LCD_CMD_ADDR 0x50100002
+#define LCD_DATA_ADDR 0x50100003
+#define LCD_BLK_CTRL CPLD_REG1_ADDR
+
+static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT";
+static int addr_flag = 0x80;
+
+static void lcd_bl_ctrl(char val)
+{
+ out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val);
+}
+
+static void lcd_putc(int val)
+{
+ int i = 100;
+ char addr;
+
+ while (i--) {
+ if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+ udelay(50);
+ break;
+ }
+ udelay(50);
+ }
+
+ if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+ printf("LCD is busy\n");
+ return;
+ }
+
+ addr = in_8((u8 *) LCD_CMD_ADDR);
+ udelay(50);
+ if ((addr != 0) && (addr % 0x10 == 0)) {
+ addr_flag ^= 0x40;
+ out_8((u8 *) LCD_CMD_ADDR, addr_flag);
+ }
+
+ udelay(50);
+ out_8((u8 *) LCD_DATA_ADDR, val);
+ udelay(50);
+}
+
+static void lcd_puts(char *s)
+{
+ char *p = s;
+ int i = 100;
+
+ while (i--) {
+ if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+ udelay(50);
+ break;
+ }
+ udelay(50);
+ }
+
+ if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+ printf("LCD is busy\n");
+ return;
+ }
+
+ while (*p)
+ lcd_putc(*p++);
+}
+
+static void lcd_put_logo(void)
+{
+ int i = 100;
+ char *p = amcc_logo;
+
+ while (i--) {
+ if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
+ udelay(50);
+ break;
+ }
+ udelay(50);
+ }
+
+ if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
+ printf("LCD is busy\n");
+ return;
+ }
+
+ out_8((u8 *) LCD_CMD_ADDR, 0x80);
+ while (*p)
+ lcd_putc(*p++);
+}
+
+int lcd_init(void)
+{
+ puts("LCD: ");
+ out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */
+ udelay(50);
+ out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */
+ udelay(50);
+ out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */
+ udelay(2000);
+ out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */
+ udelay(50);
+ lcd_bl_ctrl(0x02); /* set backlight on */
+ lcd_put_logo();
+ puts("ready\n");
+
+ return 0;
+}
+
+static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ out_8((u8 *) LCD_CMD_ADDR, 0x01);
+ udelay(2000);
+
+ return 0;
+}
+
+static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ lcd_puts(argv[1]);
+
+ return 0;
+}
+
+static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ lcd_putc((char)argv[1][0]);
+
+ return 0;
+}
+
+static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong count;
+ ulong dir;
+ char cur_addr;
+
+ if (argc < 3)
+ return cmd_usage(cmdtp);
+
+ count = simple_strtoul(argv[1], NULL, 16);
+ if (count > 31) {
+ printf("unable to shift > 0x20\n");
+ count = 0;
+ }
+
+ dir = simple_strtoul(argv[2], NULL, 16);
+ cur_addr = in_8((u8 *) LCD_CMD_ADDR);
+ udelay(50);
+
+ if (dir == 0x0) {
+ if (addr_flag == 0x80) {
+ if (count >= (cur_addr & 0xf)) {
+ out_8((u8 *) LCD_CMD_ADDR, 0x80);
+ udelay(50);
+ count = 0;
+ }
+ } else {
+ if (count >= ((cur_addr & 0x0f) + 0x0f)) {
+ out_8((u8 *) LCD_CMD_ADDR, 0x80);
+ addr_flag = 0x80;
+ udelay(50);
+ count = 0x0;
+ } else if (count >= ( cur_addr & 0xf)) {
+ count -= cur_addr & 0xf ;
+ out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf);
+ addr_flag = 0x80;
+ udelay(50);
+ }
+ }
+ } else {
+ if (addr_flag == 0x80) {
+ if (count >= (0x1f - (cur_addr & 0xf))) {
+ count = 0x0;
+ addr_flag = 0xc0;
+ out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf);
+ udelay(50);
+ } else if ((count + (cur_addr & 0xf ))>= 0x0f) {
+ count = count + (cur_addr & 0xf) - 0x0f;
+ addr_flag = 0xc0;
+ out_8((u8 *) LCD_CMD_ADDR, 0xc0);
+ udelay(50);
+ }
+ } else if ((count + (cur_addr & 0xf )) >= 0x0f) {
+ count = 0x0;
+ out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F);
+ udelay(50);
+ }
+ }
+ while (count--) {
+ if (dir == 0)
+ out_8((u8 *) LCD_CMD_ADDR, 0x10);
+ else
+ out_8((u8 *) LCD_CMD_ADDR, 0x14);
+ udelay(50);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ lcd_cls, 1, 1, do_lcd_clear,
+ "lcd clear display",
+ ""
+);
+
+U_BOOT_CMD(
+ lcd_puts, 2, 1, do_lcd_puts,
+ "display string on lcd",
+ "<string> - <string> to be displayed"
+);
+
+U_BOOT_CMD(
+ lcd_putc, 2, 1, do_lcd_putc,
+ "display char on lcd",
+ "<char> - <char> to be displayed"
+);
+
+U_BOOT_CMD(
+ lcd_cur, 3, 1, do_lcd_cur,
+ "shift cursor on lcd",
+ "<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n"
+ " <count> - 0..31\n"
+ " <dir> - 0=backward 1=forward"
+);
diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c
new file mode 100644
index 0000000..fcb8936
--- /dev/null
+++ b/board/amcc/taihu/taihu.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005-2007
+ * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <netdev.h>
+#include <asm/ppc4xx-gpio.h>
+
+extern int lcd_init(void);
+
+/*
+ * board_early_init_f
+ */
+int board_early_init_f(void)
+{
+ lcd_init();
+
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000);
+ mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
+ mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+
+ mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
+ mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
+
+ /*
+ * Configure CPC0_PCI to enable PerWE as output
+ * and enable the internal PCI arbiter
+ */
+ mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[])
+{
+ char stat;
+ int i;
+
+ stat = in_8((u8 *) CPLD_REG0_ADDR);
+ printf("SW2 status: ");
+ for (i=0; i<4; i++) /* 4-position */
+ printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
+ printf("\n");
+ return 0;
+}
+
+U_BOOT_CMD (
+ sw2_stat, 1, 1, do_sw_stat,
+ "show status of switch 2",
+ ""
+);
+
+static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[])
+{
+ int led_no;
+
+ if (argc != 3)
+ return cmd_usage(cmd_tp);
+
+ led_no = simple_strtoul(argv[1], NULL, 16);
+ if (led_no != 1 && led_no != 2)
+ return cmd_usage(cmd_tp);
+
+ if (strcmp(argv[2],"off") == 0x0) {
+ if (led_no == 1)
+ gpio_write_bit(30, 1);
+ else
+ gpio_write_bit(31, 1);
+ } else if (strcmp(argv[2],"on") == 0x0) {
+ if (led_no == 1)
+ gpio_write_bit(30, 0);
+ else
+ gpio_write_bit(31, 0);
+ } else {
+ return cmd_usage(cmd_tp);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD (
+ led_ctl, 3, 1, do_led_ctl,
+ "make led 1 or 2 on or off",
+ "<led_no> <on/off> - make led <led_no> on/off,\n"
+ "\tled_no is 1 or 2"
+);
+
+#define SPI_CS_GPIO0 0
+#define SPI_SCLK_GPIO14 14
+#define SPI_DIN_GPIO15 15
+#define SPI_DOUT_GPIO16 16
+
+void spi_scl(int bit)
+{
+ gpio_write_bit(SPI_SCLK_GPIO14, bit);
+}
+
+void spi_sda(int bit)
+{
+ gpio_write_bit(SPI_DOUT_GPIO16, bit);
+}
+
+unsigned char spi_read(void)
+{
+ return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ gpio_write_bit(SPI_CS_GPIO0, 1);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ gpio_write_bit(SPI_CS_GPIO0, 0);
+}
+
+#ifdef CONFIG_PCI
+static unsigned char int_lines[32] = {
+ 29, 30, 27, 28, 29, 30, 25, 27,
+ 29, 30, 27, 28, 29, 30, 27, 28,
+ 29, 30, 27, 28, 29, 30, 27, 28,
+ 29, 30, 27, 28, 29, 30, 27, 28};
+
+static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
+
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+int pci_pre_init(struct pci_controller *hose)
+{
+ hose->fixup_irq = taihu_pci_fixup_irq;
+ return 1;
+}
+#endif /* CONFIG_PCI */
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis);
+ return pci_eth_init(bis);
+}
diff --git a/board/amcc/taihu/update.c b/board/amcc/taihu/update.c
new file mode 100644
index 0000000..ace217d
--- /dev/null
+++ b/board/amcc/taihu/update.c
@@ -0,0 +1,116 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <i2c.h>
+
+#define PCI_M66EN 0x10
+
+static uchar buf_33[] =
+{
+ 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
+ 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x10, /* 0x0d~0x0e:vendor id 0x1014*/
+ 0x14,
+ 0x00, /* 0x0f~0x10:device id 0x0000*/
+ 0x00,
+ 0x00, /* 0x11:revision 0x00 */
+ 0x00, /* 0x12~0x14:class 0x000000 */
+ 0x00,
+ 0x00,
+ 0x10, /* 0x15~0x16:subsystem vendor id */
+ 0xe8,
+ 0x00, /* 0x17~0x18:subsystem device id */
+ 0x00,
+ 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
+ 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
+ 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
+ 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
+ 0xbe, /* 0x1d: tun[24-31]=0xbe */
+ 0x00,
+ 0x00
+};
+
+static uchar buf_66[] =
+{
+ 0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
+ 0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
+ 0x00,
+ 0x00,
+ 0x10, /* 0x0d~0x0e:vendor id 0x1014*/
+ 0x14,
+ 0x00, /* 0x0f~0x10:device id 0x0000*/
+ 0x00,
+ 0x00, /* 0x11:revision 0x00 */
+ 0x00, /* 0x12~0x14:class 0x000000 */
+ 0x00,
+ 0x00,
+ 0x10, /* 0x15~0x16:subsystem vendor id */
+ 0xe8,
+ 0x00, /* 0x17~0x18:subsystem device id */
+ 0x00,
+ 0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
+ 0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
+ 0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
+ 0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
+ 0xbe, /* 0x1d: tun[24-31]=0xbe */
+ 0x00,
+ 0x00
+};
+
+static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong len = 0x20;
+ uchar chip = CONFIG_SYS_I2C_EEPROM_ADDR;
+ uchar *pbuf;
+ uchar base;
+ int i;
+
+ if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) {
+ pbuf = buf_33;
+ base = 0x00;
+ } else {
+ pbuf = buf_66;
+ base = 0x40;
+ }
+
+ for (i = 0; i< len; i++, base++) {
+ if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) {
+ printf("i2c_write fail\n");
+ return 1;
+ }
+ udelay(11000);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD (
+ update_boot_eeprom, 1, 1, update_boot_eeprom,
+ "update boot eeprom content",
+ ""
+);
diff --git a/board/amcc/taishan/Kconfig b/board/amcc/taishan/Kconfig
new file mode 100644
index 0000000..abd07f5
--- /dev/null
+++ b/board/amcc/taishan/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TAISHAN
+
+config SYS_BOARD
+ default "taishan"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "taishan"
+
+endif
diff --git a/board/amcc/taishan/MAINTAINERS b/board/amcc/taishan/MAINTAINERS
new file mode 100644
index 0000000..d9d80bf
--- /dev/null
+++ b/board/amcc/taishan/MAINTAINERS
@@ -0,0 +1,6 @@
+TAISHAN BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/amcc/taishan/
+F: include/configs/taishan.h
+F: configs/taishan_defconfig
diff --git a/board/amcc/taishan/Makefile b/board/amcc/taishan/Makefile
new file mode 100644
index 0000000..04e93cc
--- /dev/null
+++ b/board/amcc/taishan/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = taishan.o lcd.o update.o showinfo.o
+extra-y += init.o
diff --git a/board/amcc/taishan/config.mk b/board/amcc/taishan/config.mk
new file mode 100644
index 0000000..6de8b59
--- /dev/null
+++ b/board/amcc/taishan/config.mk
@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#
+# AMCC 440GX Reference Platform (Taishan) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/taishan/init.S b/board/amcc/taishan/init.S
new file mode 100644
index 0000000..ab1bb34
--- /dev/null
+++ b/board/amcc/taishan/init.S
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+ tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX )
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
+ tlbtab_end
diff --git a/board/amcc/taishan/lcd.c b/board/amcc/taishan/lcd.c
new file mode 100644
index 0000000..124b81e
--- /dev/null
+++ b/board/amcc/taishan/lcd.c
@@ -0,0 +1,358 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <miiphy.h>
+
+#ifdef CONFIG_TAISHAN
+
+#define LCD_DELAY_NORMAL_US 100
+#define LCD_DELAY_NORMAL_MS 2
+#define LCD_CMD_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE))
+#define LCD_DATA_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE+1))
+#define LCD_BLK_CTRL ((volatile char *)(CONFIG_SYS_EBC1_FPGA_BASE+0x2))
+
+static int g_lcd_init_b = 0;
+static char *amcc_logo = " AMCC TAISHAN 440GX EvalBoard";
+static char addr_flag = 0x80;
+
+static void lcd_bl_ctrl(char val)
+{
+ char cpld_val;
+
+ cpld_val = *LCD_BLK_CTRL;
+ *LCD_BLK_CTRL = val | cpld_val;
+}
+
+static void lcd_putc(char val)
+{
+ int i = 100;
+ char addr;
+
+ while (i--) {
+ if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
+ udelay(LCD_DELAY_NORMAL_US);
+ break;
+ }
+ udelay(LCD_DELAY_NORMAL_US);
+ }
+
+ if (*LCD_CMD_ADDR & 0x80) {
+ printf("LCD is busy\n");
+ return;
+ }
+
+ addr = *LCD_CMD_ADDR;
+ udelay(LCD_DELAY_NORMAL_US);
+ if ((addr != 0) && (addr % 0x10 == 0)) {
+ addr_flag ^= 0x40;
+ *LCD_CMD_ADDR = addr_flag;
+ }
+
+ udelay(LCD_DELAY_NORMAL_US);
+ *LCD_DATA_ADDR = val;
+ udelay(LCD_DELAY_NORMAL_US);
+}
+
+static void lcd_puts(char *s)
+{
+ char *p = s;
+ int i = 100;
+
+ while (i--) {
+ if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
+ udelay(LCD_DELAY_NORMAL_US);
+ break;
+ }
+ udelay(LCD_DELAY_NORMAL_US);
+ }
+
+ if (*LCD_CMD_ADDR & 0x80) {
+ printf("LCD is busy\n");
+ return;
+ }
+
+ while (*p)
+ lcd_putc(*p++);
+}
+
+static void lcd_put_logo(void)
+{
+ int i = 100;
+ char *p = amcc_logo;
+
+ while (i--) {
+ if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
+ udelay(LCD_DELAY_NORMAL_US);
+ break;
+ }
+ udelay(LCD_DELAY_NORMAL_US);
+ }
+
+ if (*LCD_CMD_ADDR & 0x80) {
+ printf("LCD is busy\n");
+ return;
+ }
+
+ *LCD_CMD_ADDR = 0x80;
+ while (*p)
+ lcd_putc(*p++);
+}
+
+int lcd_init(void)
+{
+ if (g_lcd_init_b == 0) {
+ puts("LCD: ");
+ mdelay(100); /* Waiting for the LCD initialize */
+
+ *LCD_CMD_ADDR = 0x38; /*set function:8-bit,2-line,5x7 font type */
+ udelay(LCD_DELAY_NORMAL_US);
+
+ *LCD_CMD_ADDR = 0x0f; /*set display on,cursor on,blink on */
+ udelay(LCD_DELAY_NORMAL_US);
+
+ *LCD_CMD_ADDR = 0x01; /*display clear */
+ mdelay(LCD_DELAY_NORMAL_MS);
+
+ *LCD_CMD_ADDR = 0x06; /*set entry */
+ udelay(LCD_DELAY_NORMAL_US);
+
+ lcd_bl_ctrl(0x02);
+ lcd_put_logo();
+
+ puts(" ready\n");
+ g_lcd_init_b = 1;
+ }
+
+ return 0;
+}
+
+static int do_lcd_test(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ lcd_init();
+ return 0;
+}
+
+static int do_lcd_clear(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ *LCD_CMD_ADDR = 0x01;
+ mdelay(LCD_DELAY_NORMAL_MS);
+ return 0;
+}
+static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ lcd_puts(argv[1]);
+ return 0;
+}
+static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ lcd_putc((char)argv[1][0]);
+ return 0;
+}
+static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong count;
+ ulong dir;
+ char cur_addr;
+
+ if (argc < 3)
+ return cmd_usage(cmdtp);
+
+ count = simple_strtoul(argv[1], NULL, 16);
+ if (count > 31) {
+ printf("unable to shift > 0x20\n");
+ count = 0;
+ }
+
+ dir = simple_strtoul(argv[2], NULL, 16);
+ cur_addr = *LCD_CMD_ADDR;
+ udelay(LCD_DELAY_NORMAL_US);
+ if (dir == 0x0) {
+ if (addr_flag == 0x80) {
+ if (count >= (cur_addr & 0xf)) {
+ *LCD_CMD_ADDR = 0x80;
+ udelay(LCD_DELAY_NORMAL_US);
+ count = 0;
+ }
+ } else {
+ if (count >= ((cur_addr & 0x0f) + 0x0f)) {
+ *LCD_CMD_ADDR = 0x80;
+ addr_flag = 0x80;
+ udelay(LCD_DELAY_NORMAL_US);
+ count = 0x0;
+ } else if (count >= (cur_addr & 0xf)) {
+ count -= cur_addr & 0xf;
+ *LCD_CMD_ADDR = 0x80 | 0xf;
+ addr_flag = 0x80;
+ udelay(LCD_DELAY_NORMAL_US);
+ }
+ }
+ } else {
+ if (addr_flag == 0x80) {
+ if (count >= (0x1f - (cur_addr & 0xf))) {
+ count = 0x0;
+ addr_flag = 0xc0;
+ *LCD_CMD_ADDR = 0xc0 | 0xf;
+ udelay(LCD_DELAY_NORMAL_US);
+ } else if ((count + (cur_addr & 0xf)) >= 0x0f) {
+ count = count + (cur_addr & 0xf) - 0x0f;
+ addr_flag = 0xc0;
+ *LCD_CMD_ADDR = 0xc0;
+ udelay(LCD_DELAY_NORMAL_US);
+ }
+ } else if ((count + (cur_addr & 0xf)) >= 0x0f) {
+ count = 0x0;
+ *LCD_CMD_ADDR = 0xc0 | 0xf;
+ udelay(LCD_DELAY_NORMAL_US);
+ }
+ }
+
+ while (count--) {
+ if (dir == 0) {
+ *LCD_CMD_ADDR = 0x10;
+ } else {
+ *LCD_CMD_ADDR = 0x14;
+ }
+ udelay(LCD_DELAY_NORMAL_US);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd test display", "");
+U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd clear display", "");
+U_BOOT_CMD(lcd_puts, 2, 1, do_lcd_puts,
+ "display string on lcd",
+ "<string> - <string> to be displayed");
+U_BOOT_CMD(lcd_putc, 2, 1, do_lcd_putc,
+ "display char on lcd",
+ "<char> - <char> to be displayed");
+U_BOOT_CMD(lcd_cur, 3, 1, do_lcd_cur,
+ "shift cursor on lcd",
+ "<count> <dir>- shift cursor on lcd <count> times, direction is <dir> \n"
+ " <count> - 0~31\n" " <dir> - 0,backward; 1, forward");
+
+#if 0 /* test-only */
+void set_phy_loopback_mode(void)
+{
+ char devemac2[32];
+ char devemac3[32];
+
+ sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
+ sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
+
+#if 0
+ unsigned short reg_short;
+
+ miiphy_read(devemac2, 0x1, 1, ®_short);
+ if (reg_short & 0x04) {
+ /*
+ * printf("EMAC2 link up,do nothing\n");
+ */
+ } else {
+ udelay(1000);
+ miiphy_write(devemac2, 0x1, 0, 0x6000);
+ udelay(1000);
+ miiphy_read(devemac2, 0x1, 0, ®_short);
+ if (reg_short != 0x6000) {
+ printf
+ ("\nEMAC2 error set LOOPBACK mode error,reg2[0]=%x\n",
+ reg_short);
+ }
+ }
+
+ miiphy_read(devemac3, 0x3, 1, ®_short);
+ if (reg_short & 0x04) {
+ /*
+ * printf("EMAC3 link up,do nothing\n");
+ */
+ } else {
+ udelay(1000);
+ miiphy_write(devemac3, 0x3, 0, 0x6000);
+ udelay(1000);
+ miiphy_read(devemac3, 0x3, 0, ®_short);
+ if (reg_short != 0x6000) {
+ printf
+ ("\nEMAC3 error set LOOPBACK mode error,reg2[0]=%x\n",
+ reg_short);
+ }
+ }
+#else
+ /* Set PHY as LOOPBACK MODE, for Linux emac initializing */
+ miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0, 0x6000);
+ udelay(1000);
+ miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0, 0x6000);
+ udelay(1000);
+#endif /* 0 */
+}
+
+void set_phy_normal_mode(void)
+{
+ char devemac2[32];
+ char devemac3[32];
+ unsigned short reg_short;
+
+ sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
+ sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
+
+ /* Set phy of EMAC2 */
+ miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x16, ®_short);
+ reg_short &= ~(0x7);
+ reg_short |= 0x6; /* RGMII DLL Delay */
+ miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x16, reg_short);
+
+ miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x17, ®_short);
+ reg_short &= ~(0x40);
+ miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x17, reg_short);
+
+ miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x1c, 0x74f0);
+
+ /* Set phy of EMAC3 */
+ miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x16, ®_short);
+ reg_short &= ~(0x7);
+ reg_short |= 0x6; /* RGMII DLL Delay */
+ miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x16, reg_short);
+
+ miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x17, ®_short);
+ reg_short &= ~(0x40);
+ miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x17, reg_short);
+
+ miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x1c, 0x74f0);
+}
+#endif /* 0 - test only */
+
+static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ volatile unsigned int *GpioOr =
+ (volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700);
+ *GpioOr |= 0x00300000;
+ return 0;
+}
+
+static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ volatile unsigned int *GpioOr =
+ (volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700);
+ *GpioOr &= ~0x00300000;
+ return 0;
+}
+
+U_BOOT_CMD(ledon, 1, 1, do_led_test_on,
+ "led test light on", "");
+
+U_BOOT_CMD(ledoff, 1, 1, do_led_test_off,
+ "led test light off", "");
+#endif
diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c
new file mode 100644
index 0000000..53bfdf7
--- /dev/null
+++ b/board/amcc/taishan/showinfo.c
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+void show_reset_reg(void)
+{
+ unsigned long reg;
+
+ /* read clock regsiter */
+ printf("===== Display reset and initialize register Start =========\n");
+ mfcpr(CPR0_PLLC,reg);
+ printf("cpr_pllc = %#010lx\n",reg);
+
+ mfcpr(CPR0_PLLD,reg);
+ printf("cpr_plld = %#010lx\n",reg);
+
+ mfcpr(CPR0_PRIMAD0,reg);
+ printf("cpr_primad = %#010lx\n",reg);
+
+ mfcpr(CPR0_PRIMBD0,reg);
+ printf("cpr_primbd = %#010lx\n",reg);
+
+ mfcpr(CPR0_OPBD0,reg);
+ printf("cpr_opbd = %#010lx\n",reg);
+
+ mfcpr(CPR0_PERD,reg);
+ printf("cpr_perd = %#010lx\n",reg);
+
+ mfcpr(CPR0_MALD,reg);
+ printf("cpr_mald = %#010lx\n",reg);
+
+ /* read sdr register */
+ mfsdr(SDR0_EBC,reg);
+ printf("SDR0_EBC = %#010lx\n",reg);
+
+ mfsdr(SDR0_CP440,reg);
+ printf("SDR0_CP440 = %#010lx\n",reg);
+
+ mfsdr(SDR0_XCR,reg);
+ printf("SDR0_XCR = %#010lx\n",reg);
+
+ mfsdr(SDR0_XPLLC,reg);
+ printf("SDR0_XPLLC = %#010lx\n",reg);
+
+ mfsdr(SDR0_XPLLD,reg);
+ printf("SDR0_XPLLD = %#010lx\n",reg);
+
+ mfsdr(SDR0_PFC0,reg);
+ printf("SDR0_PFC0 = %#010lx\n",reg);
+
+ mfsdr(SDR0_PFC1,reg);
+ printf("SDR0_PFC1 = %#010lx\n",reg);
+
+ mfsdr(SDR0_CUST0,reg);
+ printf("SDR0_CUST0 = %#010lx\n",reg);
+
+ mfsdr(SDR0_CUST1,reg);
+ printf("SDR0_CUST1 = %#010lx\n",reg);
+
+ mfsdr(SDR0_UART0,reg);
+ printf("SDR0_UART0 = %#010lx\n",reg);
+
+ mfsdr(SDR0_UART1,reg);
+ printf("SDR0_UART1 = %#010lx\n",reg);
+
+ printf("===== Display reset and initialize register End =========\n");
+}
+
+void show_xbridge_info(void)
+{
+ unsigned long reg;
+
+ printf("PCI-X chip control registers\n");
+ mfsdr(SDR0_XCR, reg);
+ printf("SDR0_XCR = %#010lx\n", reg);
+
+ mfsdr(SDR0_XPLLC, reg);
+ printf("SDR0_XPLLC = %#010lx\n", reg);
+
+ mfsdr(SDR0_XPLLD, reg);
+ printf("SDR0_XPLLD = %#010lx\n", reg);
+
+ printf("PCI-X Bridge Configure registers\n");
+ printf("PCIL0_VENDID = %#06x\n", in16r(PCIL0_VENDID));
+ printf("PCIL0_DEVID = %#06x\n", in16r(PCIL0_DEVID));
+ printf("PCIL0_CMD = %#06x\n", in16r(PCIL0_CMD));
+ printf("PCIL0_STATUS = %#06x\n", in16r(PCIL0_STATUS));
+ printf("PCIL0_REVID = %#04x\n", in8(PCIL0_REVID));
+ printf("PCIL0_CACHELS = %#04x\n", in8(PCIL0_CACHELS));
+ printf("PCIL0_LATTIM = %#04x\n", in8(PCIL0_LATTIM));
+ printf("PCIL0_HDTYPE = %#04x\n", in8(PCIL0_HDTYPE));
+ printf("PCIL0_BIST = %#04x\n", in8(PCIL0_BIST));
+
+ printf("PCIL0_BAR0 = %#010lx\n", in32r(PCIL0_BAR0));
+ printf("PCIL0_BAR1 = %#010lx\n", in32r(PCIL0_BAR1));
+ printf("PCIL0_BAR2 = %#010lx\n", in32r(PCIL0_BAR2));
+ printf("PCIL0_BAR3 = %#010lx\n", in32r(PCIL0_BAR3));
+ printf("PCIL0_BAR4 = %#010lx\n", in32r(PCIL0_BAR4));
+ printf("PCIL0_BAR5 = %#010lx\n", in32r(PCIL0_BAR5));
+
+ printf("PCIL0_CISPTR = %#010lx\n", in32r(PCIL0_CISPTR));
+ printf("PCIL0_SBSSYSVID = %#010x\n", in16r(PCIL0_SBSYSVID));
+ printf("PCIL0_SBSSYSID = %#010x\n", in16r(PCIL0_SBSYSID));
+ printf("PCIL0_EROMBA = %#010lx\n", in32r(PCIL0_EROMBA));
+ printf("PCIL0_CAP = %#04x\n", in8(PCIL0_CAP));
+ printf("PCIL0_INTLN = %#04x\n", in8(PCIL0_INTLN));
+ printf("PCIL0_INTPN = %#04x\n", in8(PCIL0_INTPN));
+ printf("PCIL0_MINGNT = %#04x\n", in8(PCIL0_MINGNT));
+ printf("PCIL0_MAXLTNCY = %#04x\n", in8(PCIL0_MAXLTNCY));
+
+ printf("PCIL0_BRDGOPT1 = %#010lx\n", in32r(PCIL0_BRDGOPT1));
+ printf("PCIL0_BRDGOPT2 = %#010lx\n", in32r(PCIL0_BRDGOPT2));
+
+ printf("PCIL0_POM0LAL = %#010lx\n", in32r(PCIL0_POM0LAL));
+ printf("PCIL0_POM0LAH = %#010lx\n", in32r(PCIL0_POM0LAH));
+ printf("PCIL0_POM0SA = %#010lx\n", in32r(PCIL0_POM0SA));
+ printf("PCIL0_POM0PCILAL = %#010lx\n", in32r(PCIL0_POM0PCIAL));
+ printf("PCIL0_POM0PCILAH = %#010lx\n", in32r(PCIL0_POM0PCIAH));
+ printf("PCIL0_POM1LAL = %#010lx\n", in32r(PCIL0_POM1LAL));
+ printf("PCIL0_POM1LAH = %#010lx\n", in32r(PCIL0_POM1LAH));
+ printf("PCIL0_POM1SA = %#010lx\n", in32r(PCIL0_POM1SA));
+ printf("PCIL0_POM1PCILAL = %#010lx\n", in32r(PCIL0_POM1PCIAL));
+ printf("PCIL0_POM1PCILAH = %#010lx\n", in32r(PCIL0_POM1PCIAH));
+ printf("PCIL0_POM2SA = %#010lx\n", in32r(PCIL0_POM2SA));
+
+ printf("PCIL0_PIM0SA = %#010lx\n", in32r(PCIL0_PIM0SA));
+ printf("PCIL0_PIM0LAL = %#010lx\n", in32r(PCIL0_PIM0LAL));
+ printf("PCIL0_PIM0LAH = %#010lx\n", in32r(PCIL0_PIM0LAH));
+ printf("PCIL0_PIM1SA = %#010lx\n", in32r(PCIL0_PIM1SA));
+ printf("PCIL0_PIM1LAL = %#010lx\n", in32r(PCIL0_PIM1LAL));
+ printf("PCIL0_PIM1LAH = %#010lx\n", in32r(PCIL0_PIM1LAH));
+ printf("PCIL0_PIM2SA = %#010lx\n", in32r(PCIL0_PIM1SA));
+ printf("PCIL0_PIM2LAL = %#010lx\n", in32r(PCIL0_PIM1LAL));
+ printf("PCIL0_PIM2LAH = %#010lx\n", in32r(PCIL0_PIM1LAH));
+
+ printf("PCIL0_XSTS = %#010lx\n", in32r(PCIL0_STS));
+}
+
+int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ show_xbridge_info();
+ return 0;
+}
+
+U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info,
+ "Show PCIX bridge info", "");
+
+#define TAISHAN_PCI_DEV_ID0 0x800
+#define TAISHAN_PCI_DEV_ID1 0x1000
+
+void show_pcix_device_info(void)
+{
+ int ii;
+ int dev;
+ u8 capp;
+ u8 xcapid;
+ u16 status;
+ u16 xcommand;
+ u32 xstatus;
+
+ for (ii = 0; ii < 2; ii++) {
+ if (ii == 0)
+ dev = TAISHAN_PCI_DEV_ID0;
+ else
+ dev = TAISHAN_PCI_DEV_ID1;
+
+ pci_read_config_word(dev, PCI_STATUS, &status);
+ if (status & PCI_STATUS_CAP_LIST) {
+ pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp);
+
+ pci_read_config_byte(dev, (int)(capp), &xcapid);
+ if (xcapid == 0x07) {
+ pci_read_config_word(dev, (int)(capp + 2),
+ &xcommand);
+ pci_read_config_dword(dev, (int)(capp + 4),
+ &xstatus);
+ printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n",
+ (ii + 1), xcommand, xstatus);
+ } else {
+ printf("BUS0 dev%d PCI-X CAP ID error,"
+ "CAP=%#04x,XCAPID=%#04x\n",
+ (ii + 1), capp, xcapid);
+ }
+ } else {
+ printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n",
+ ii + 1);
+ }
+ }
+
+}
+
+int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ show_pcix_device_info();
+ return 0;
+}
+
+U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info,
+ "Show PCIX Device info", "");
+
+extern void show_reset_reg(void);
+
+int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ show_reset_reg();
+ return 0;
+}
+
+U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info,
+ "Show Reset REG info", "");
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
new file mode 100644
index 0000000..5c8d9ec
--- /dev/null
+++ b/board/amcc/taishan/taishan.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2004 PaulReynolds@lhsolutions.com
+ *
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <asm/ppc4xx-emac.h>
+#include <netdev.h>
+
+#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
+void show_reset_reg(void);
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int lcd_init(void);
+
+int board_early_init_f (void)
+{
+ unsigned long reg;
+ volatile unsigned int *GpioOdr;
+ volatile unsigned int *GpioTcr;
+ volatile unsigned int *GpioOr;
+
+ /*-------------------------------------------------------------------------+
+ | Initialize EBC CONFIG
+ +-------------------------------------------------------------------------*/
+ mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
+ EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
+ EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
+ EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
+ EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
+
+ /*-------------------------------------------------------------------------+
+ | 64MB FLASH. Initialize bank 0 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
+ EBC_BXAP_BCE_DISABLE |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
+ EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
+ EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
+ EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
+ EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
+
+ /*-------------------------------------------------------------------------+
+ | FPGA. Initialize bank 1 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
+ EBC_BXAP_BCE_DISABLE |
+ EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
+ EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
+ EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
+ EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+
+ /*-------------------------------------------------------------------------+
+ | LCM. Initialize bank 2 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
+ EBC_BXAP_BCE_DISABLE |
+ EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
+ EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
+ EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) |
+ EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+ /*-------------------------------------------------------------------------+
+ | TMP. Initialize bank 3 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
+ EBC_BXAP_BCE_DISABLE |
+ EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
+ EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
+ EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
+ EBC_BXAP_BEM_WRITEONLY |
+ EBC_BXAP_PEN_DISABLED);
+ mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
+ EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+ /*-------------------------------------------------------------------------+
+ | Connector 4~7. Initialize bank 3~ 7 with default values.
+ +-------------------------------------------------------------------------*/
+ mtebc(PB4AP,0);
+ mtebc(PB4CR,0);
+ mtebc(PB5AP,0);
+ mtebc(PB5CR,0);
+ mtebc(PB6AP,0);
+ mtebc(PB6CR,0);
+ mtebc(PB7AP,0);
+ mtebc(PB7CR,0);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ /*
+ * Because of the interrupt handling rework to handle 440GX interrupts
+ * with the common code, we needed to change names of the UIC registers.
+ * Here the new relationship:
+ *
+ * U-Boot name 440GX name
+ * -----------------------
+ * UIC0 UICB0
+ * UIC1 UIC0
+ * UIC2 UIC1
+ * UIC3 UIC2
+ */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+ mtdcr (UIC1ER, 0x00000000); /* disable all */
+ mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
+ mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
+ mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+ mtdcr (UIC2ER, 0x00000000); /* disable all */
+ mtdcr (UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+ mtdcr (UIC3ER, 0x00000000); /* disable all */
+ mtdcr (UIC3CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
+ mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC0SR, 0xfc000000); /* clear all */
+ mtdcr (UIC0ER, 0x00000000); /* disable all */
+ mtdcr (UIC0CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC0PR, 0xfc000000); /* */
+ mtdcr (UIC0TR, 0x00000000); /* */
+ mtdcr (UIC0VR, 0x00000001); /* */
+
+ /* Enable two GPIO 10~11 and TraceA signal */
+ mfsdr(SDR0_PFC0,reg);
+ reg |= 0x00300000;
+ mtsdr(SDR0_PFC0,reg);
+
+ mfsdr(SDR0_PFC1,reg);
+ reg |= 0x00100000;
+ mtsdr(SDR0_PFC1,reg);
+
+ /* Set GPIO 10 and 11 as output */
+ GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718);
+ GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704);
+ GpioOr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700);
+
+ *GpioOdr &= ~(0x00300000);
+ *GpioTcr |= 0x00300000;
+ *GpioOr |= 0x00300000;
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ lcd_init();
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc ('\n');
+
+#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
+ show_reset_reg();
+#endif
+
+ return (0);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis);
+ return pci_eth_init(bis);
+}
diff --git a/board/amcc/taishan/update.c b/board/amcc/taishan/update.c
new file mode 100644
index 0000000..2738989
--- /dev/null
+++ b/board/amcc/taishan/update.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <i2c.h>
+
+#if defined(CONFIG_TAISHAN)
+
+const uchar bootstrap_buf[16] = {
+ 0x86,
+ 0x78,
+ 0xc1,
+ 0xa6,
+ 0x09,
+ 0x67,
+ 0x04,
+ 0x63,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00
+};
+
+static int update_boot_eeprom(void)
+{
+ ulong len = 0x10;
+ uchar chip = CONFIG_SYS_BOOTSTRAP_IIC_ADDR;
+ uchar *pbuf = (uchar *)bootstrap_buf;
+ int ii, jj;
+
+ for (ii = 0; ii < len; ii++) {
+ if (i2c_write(chip, ii, 1, &pbuf[ii], 1) != 0) {
+ printf("i2c_write failed\n");
+ return -1;
+ }
+
+ /* wait 10ms */
+ for (jj = 0; jj < 10; jj++)
+ udelay(1000);
+ }
+ return 0;
+}
+
+int do_update_boot_eeprom(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ return update_boot_eeprom();
+}
+
+U_BOOT_CMD(update_boot_eeprom, 1, 1, do_update_boot_eeprom,
+ "update bootstrap eeprom content", "");
+#endif
diff --git a/board/amcc/walnut/Kconfig b/board/amcc/walnut/Kconfig
new file mode 100644
index 0000000..94e3dc9
--- /dev/null
+++ b/board/amcc/walnut/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_WALNUT
+
+config SYS_BOARD
+ default "walnut"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "walnut"
+
+endif
diff --git a/board/amcc/walnut/MAINTAINERS b/board/amcc/walnut/MAINTAINERS
new file mode 100644
index 0000000..2a98c85
--- /dev/null
+++ b/board/amcc/walnut/MAINTAINERS
@@ -0,0 +1,7 @@
+WALNUT BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/amcc/walnut/
+F: include/configs/walnut.h
+F: configs/sycamore_defconfig
+F: configs/walnut_defconfig
diff --git a/board/amcc/walnut/Makefile b/board/amcc/walnut/Makefile
new file mode 100644
index 0000000..9228170
--- /dev/null
+++ b/board/amcc/walnut/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = walnut.o flash.o
diff --git a/board/amcc/walnut/flash.c b/board/amcc/walnut/flash.c
new file mode 100644
index 0000000..cc0f425
--- /dev/null
+++ b/board/amcc/walnut/flash.c
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+ uint pbcr;
+ unsigned long base_b0, base_b1;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 =
+ flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ /* Only one bank */
+ if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
+ /* Setup offsets */
+ flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+ &flash_info[0]);
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ size_b1 = 0;
+ flash_info[0].size = size_b0;
+ } else {
+ /* 2 banks */
+ size_b1 =
+ flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
+ &flash_info[1]);
+
+ /* Re-do sizing to get full correct info */
+
+ if (size_b1) {
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b1 = -size_b1;
+ pbcr =
+ (pbcr & 0x0001ffff) | base_b1 |
+ (((size_b1 / 1024 / 1024) - 1) << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+ /* printf("PB1CR = %x\n", pbcr); */
+ }
+
+ if (size_b0) {
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ base_b0 = base_b1 - size_b0;
+ pbcr =
+ (pbcr & 0x0001ffff) | base_b0 |
+ (((size_b0 / 1024 / 1024) - 1) << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+ /* printf("PB0CR = %x\n", pbcr); */
+ }
+
+ size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
+
+ flash_get_offsets(base_b0, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ base_b0 + size_b0 - monitor_flash_len,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+
+ if (size_b1) {
+ /* Re-do sizing to get full correct info */
+ size_b1 =
+ flash_get_size((vu_long *) base_b1, &flash_info[1]);
+
+ flash_get_offsets(base_b1, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ base_b1 + size_b1 -
+ monitor_flash_len,
+ base_b1 + size_b1 - 1,
+ &flash_info[1]);
+ /* monitor protection OFF by default (one is enough) */
+ (void)flash_protect(FLAG_PROTECT_CLEAR,
+ base_b0 + size_b0 -
+ monitor_flash_len,
+ base_b0 + size_b0 - 1,
+ &flash_info[0]);
+ } else {
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+ } /* else 2 banks */
+ return (size_b0 + size_b1);
+}
+
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ (info->flash_id == FLASH_AM040)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+}
diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c
new file mode 100644
index 0000000..c948209
--- /dev/null
+++ b/board/amcc/walnut/walnut.c
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+int board_early_init_f(void)
+{
+ /*-------------------------------------------------------------------------+
+ | Interrupt controller setup for the Walnut/Sycamore board.
+ | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
+ | IRQ 16 405GP internally generated; active low; level sensitive
+ | IRQ 17-24 RESERVED
+ | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+ | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+ | IRQ 27 (EXT IRQ 2) Not Used
+ | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+ | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+ | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+ | Note for Walnut board:
+ | An interrupt taken for the FPGA (IRQ 25) indicates that either
+ | the Mouse, Keyboard, IRDA, or External Expansion caused the
+ | interrupt. The FPGA must be read to determine which device
+ | caused the interrupt. The default setting of the FPGA clears
+ |
+ +-------------------------------------------------------------------------*/
+
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */
+ mtdcr(UIC0PR, 0xFFFFFFE0); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /* set UART1 control to select CTS/RTS */
+#define FPGA_BRDC 0xF0300004
+ *(volatile char *)(FPGA_BRDC) |= 0x1;
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+ uint pvr = get_pvr();
+
+ if (pvr == PVR_405GPR_RB) {
+ puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board");
+ } else {
+ puts("Board: Walnut - AMCC PPC405GP Evaluation Board");
+ }
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+/*
+ * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ * the necessary info for SDRAM controller configuration
+ */
+phys_size_t initdram(int board_type)
+{
+ return spd_sdram();
+}
diff --git a/board/amcc/yosemite/Kconfig b/board/amcc/yosemite/Kconfig
new file mode 100644
index 0000000..dfa1068
--- /dev/null
+++ b/board/amcc/yosemite/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_YOSEMITE
+
+config SYS_BOARD
+ default "yosemite"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "yosemite"
+
+endif
diff --git a/board/amcc/yosemite/MAINTAINERS b/board/amcc/yosemite/MAINTAINERS
new file mode 100644
index 0000000..3f553e1
--- /dev/null
+++ b/board/amcc/yosemite/MAINTAINERS
@@ -0,0 +1,7 @@
+YOSEMITE BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/amcc/yosemite/
+F: include/configs/yosemite.h
+F: configs/yellowstone_defconfig
+F: configs/yosemite_defconfig
diff --git a/board/amcc/yosemite/Makefile b/board/amcc/yosemite/Makefile
new file mode 100644
index 0000000..daf020a
--- /dev/null
+++ b/board/amcc/yosemite/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = yosemite.o
+extra-y += init.o
diff --git a/board/amcc/yosemite/config.mk b/board/amcc/yosemite/config.mk
new file mode 100644
index 0000000..f18b097
--- /dev/null
+++ b/board/amcc/yosemite/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/yosemite/init.S b/board/amcc/yosemite/init.S
new file mode 100644
index 0000000..529cc65
--- /dev/null
+++ b/board/amcc/yosemite/init.S
@@ -0,0 +1,49 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
+
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
+
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I )
+
+ /* PCI */
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
+
+ /* USB 2.0 Device */
+ tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
+
+ tlbtab_end
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
new file mode 100644
index 0000000..56b5191
--- /dev/null
+++ b/board/amcc/yosemite/yosemite.c
@@ -0,0 +1,357 @@
+/*
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+static inline u32 get_async_pci_freq(void)
+{
+ if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
+ CONFIG_SYS_BCSR5_PCI66EN)
+ return 66666666;
+ else
+ return 33333333;
+}
+
+int board_early_init_f(void)
+{
+ register uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup the external bus controller/chip selects
+ *-------------------------------------------------------------------*/
+ mtdcr(EBC0_CFGADDR, EBC0_CFG);
+ reg = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
+
+ /*--------------------------------------------------------------------
+ * Setup the GPIO pins
+ *-------------------------------------------------------------------*/
+ /*CPLD cs */
+ /*setup Address lines for flash size 64Meg. */
+ out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
+
+ /*setup emac */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
+ out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
+ out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
+
+ /*UART1 */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
+ out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
+ out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
+
+ /* external interrupts IRQ0...3 */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
+ out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
+ out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
+
+#ifdef CONFIG_440EP
+ /*setup USB 2.0 */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
+ out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
+ out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
+ out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
+ out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
+#endif
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ /*--------------------------------------------------------------------
+ * Setup other serial configuration
+ *-------------------------------------------------------------------*/
+ mfsdr(SDR0_PCI0, reg);
+ mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
+ mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
+ mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
+
+ /* Check and reconfigure the PCI sync clock if necessary */
+ ppc4xx_pci_sync_clock_config(get_async_pci_freq());
+
+ /*clear tmrclk divisor */
+ *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
+
+ /*enable ethernet */
+ *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;
+
+#ifdef CONFIG_440EP
+ /*enable usb 1.1 fs device and remove usb 2.0 reset */
+ *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
+#endif
+
+ /*get rid of flash write protect */
+ *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ uint pbcr;
+ int size_val = 0;
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ switch (gd->bd->bi_flashsize) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ case 32 << 20:
+ size_val = 5;
+ break;
+ case 64 << 20:
+ size_val = 6;
+ break;
+ case 128 << 20:
+ size_val = 7;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+ u8 rev;
+ u32 clock = get_async_pci_freq();
+
+#ifdef CONFIG_440EP
+ printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
+#else
+ printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
+#endif
+
+ rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
+ printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ /*
+ * Reconfiguration of the PCI sync clock is already done,
+ * now check again if everything is in range:
+ */
+ if (ppc4xx_pci_sync_clock_config(clock)) {
+ printf("ERROR: PCI clocking incorrect (async=%d "
+ "sync=%ld)!\n", clock, get_PCI_freq());
+ }
+
+ return (0);
+}
+
+/*************************************************************************
+ * initdram -- doesn't use serial presence detect.
+ *
+ * Assumes: 256 MB, ECC, non-registered
+ * PLB @ 133 MHz
+ *
+ ************************************************************************/
+#define NUM_TRIES 64
+#define NUM_READS 10
+
+void sdram_tr1_set(int ram_address, int* tr1_value)
+{
+ int i;
+ int j, k;
+ volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
+ int first_good = -1, last_bad = 0x1ff;
+
+ unsigned long test[NUM_TRIES] = {
+ 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+ 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+ 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+ 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+ 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+ 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+ 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+ 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
+
+ /* go through all possible SDRAM0_TR1[RDCT] values */
+ for (i=0; i<=0x1ff; i++) {
+ /* set the current value for TR1 */
+ mtsdram(SDRAM0_TR1, (0x80800800 | i));
+
+ /* write values */
+ for (j=0; j<NUM_TRIES; j++) {
+ ram_pointer[j] = test[j];
+
+ /* clear any cache at ram location */
+ __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+ }
+
+ /* read values back */
+ for (j=0; j<NUM_TRIES; j++) {
+ for (k=0; k<NUM_READS; k++) {
+ /* clear any cache at ram location */
+ __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+
+ if (ram_pointer[j] != test[j])
+ break;
+ }
+
+ /* read error */
+ if (k != NUM_READS) {
+ break;
+ }
+ }
+
+ /* we have a SDRAM0_TR1[RDCT] that is part of the window */
+ if (j == NUM_TRIES) {
+ if (first_good == -1)
+ first_good = i; /* found beginning of window */
+ } else { /* bad read */
+ /* if we have not had a good read then don't care */
+ if(first_good != -1) {
+ /* first failure after a good read */
+ last_bad = i-1;
+ break;
+ }
+ }
+ }
+
+ /* return the current value for TR1 */
+ *tr1_value = (first_good + last_bad) / 2;
+}
+
+phys_size_t initdram(int board)
+{
+ register uint reg;
+ int tr1_bank1, tr1_bank2;
+
+ /*--------------------------------------------------------------------
+ * Setup some default
+ *------------------------------------------------------------------*/
+ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
+ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(SDRAM0_CLKTR, 0x40000000); /* ?? */
+ mtsdram(SDRAM0_WDDCTR, 0x40000000); /* ?? */
+
+ /*clear this first, if the DDR is enabled by a debugger
+ then you can not make changes. */
+ mtsdram(SDRAM0_CFG0, 0x00000000); /* Disable EEC */
+
+ /*--------------------------------------------------------------------
+ * Setup for board-specific specific mem
+ *------------------------------------------------------------------*/
+ /*
+ * Following for CAS Latency = 2.5 @ 133 MHz PLB
+ */
+ mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+ mtsdram(SDRAM0_B1CR, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
+
+ mtsdram(SDRAM0_TR0, 0x410a4012); /* ?? */
+ mtsdram(SDRAM0_RTR, 0x04080000); /* ?? */
+ mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
+ mtsdram(SDRAM0_CFG0, 0x30000000); /* Disable EEC */
+ udelay(400); /* Delay 200 usecs (min) */
+
+ /*--------------------------------------------------------------------
+ * Enable the controller, then wait for DCEN to complete
+ *------------------------------------------------------------------*/
+ mtsdram(SDRAM0_CFG0, 0x80000000); /* Enable */
+
+ for (;;) {
+ mfsdram(SDRAM0_MCSTS, reg);
+ if (reg & 0x80000000)
+ break;
+ }
+
+ sdram_tr1_set(0x00000000, &tr1_bank1);
+ sdram_tr1_set(0x08000000, &tr1_bank2);
+ mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
+
+ return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */
+}
+
+/*************************************************************************
+ * hw_watchdog_reset
+ *
+ * This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+
+}
+#endif
+
+void board_reset(void)
+{
+ /* give reset to BCSR */
+ *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;
+}
diff --git a/board/amcc/yucca/Kconfig b/board/amcc/yucca/Kconfig
new file mode 100644
index 0000000..61d9589
--- /dev/null
+++ b/board/amcc/yucca/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_YUCCA
+
+config SYS_BOARD
+ default "yucca"
+
+config SYS_VENDOR
+ default "amcc"
+
+config SYS_CONFIG_NAME
+ default "yucca"
+
+endif
diff --git a/board/amcc/yucca/MAINTAINERS b/board/amcc/yucca/MAINTAINERS
new file mode 100644
index 0000000..1cbdb0e
--- /dev/null
+++ b/board/amcc/yucca/MAINTAINERS
@@ -0,0 +1,6 @@
+YUCCA BOARD
+#M: -
+S: Maintained
+F: board/amcc/yucca/
+F: include/configs/yucca.h
+F: configs/yucca_defconfig
diff --git a/board/amcc/yucca/Makefile b/board/amcc/yucca/Makefile
new file mode 100644
index 0000000..5b1af32
--- /dev/null
+++ b/board/amcc/yucca/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = yucca.o flash.o cmd_yucca.o
+extra-y += init.o
diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c
new file mode 100644
index 0000000..c1724bf
--- /dev/null
+++ b/board/amcc/yucca/cmd_yucca.c
@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * hacked for evb440spe
+ */
+
+#include <common.h>
+#include <cli.h>
+#include <command.h>
+#include "yucca.h"
+#include <i2c.h>
+#include <asm/byteorder.h>
+
+extern void print_evb440spe_info(void);
+static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
+ int flag, int argc, char * const argv[]);
+
+/* ------------------------------------------------------------------------- */
+int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ return setBootStrapClock (cmdtp, 1, flag, argc, argv);
+}
+
+/* ------------------------------------------------------------------------- */
+/* Modify memory.
+ *
+ * Syntax:
+ * evb440spe wrclk prom0,prom1
+ */
+static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
+ int argc, char * const argv[])
+{
+ uchar chip;
+ ulong data;
+ int nbytes;
+
+ char sysClock[4];
+ char cpuClock[4];
+ char plbClock[4];
+ char pcixClock[4];
+
+ if (argc < 3)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[2], "prom0") == 0)
+ chip = IIC0_BOOTPROM_ADDR;
+ else
+ chip = IIC0_ALT_BOOTPROM_ADDR;
+
+ do {
+ printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n");
+ nbytes = cli_readline(" ? ");
+
+ if (strcmp(console_buffer, "quit") == 0)
+ return 0;
+
+ if ((strcmp(console_buffer, "33") != 0) &
+ (strcmp(console_buffer, "66") != 0))
+ nbytes=0;
+
+ strcpy(sysClock, console_buffer);
+
+ } while (nbytes == 0);
+
+ do {
+ if (strcmp(sysClock, "66") == 0) {
+ printf("enter cpu clock frequency 400, 533 MHz or quit to abort\n");
+ } else {
+#ifdef CONFIG_STRESS
+ printf("enter cpu clock frequency 400, 500, 533, 667 MHz or quit to abort\n");
+#else
+ printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n");
+#endif
+ }
+ nbytes = cli_readline(" ? ");
+
+ if (strcmp(console_buffer, "quit") == 0)
+ return 0;
+
+ if (strcmp(sysClock, "66") == 0) {
+ if ((strcmp(console_buffer, "400") != 0) &
+ (strcmp(console_buffer, "533") != 0)
+#ifdef CONFIG_STRESS
+ & (strcmp(console_buffer, "667") != 0)
+#endif
+ ) {
+ nbytes = 0;
+ }
+ } else {
+ if ((strcmp(console_buffer, "400") != 0) &
+ (strcmp(console_buffer, "500") != 0) &
+ (strcmp(console_buffer, "533") != 0)
+#ifdef CONFIG_STRESS
+ & (strcmp(console_buffer, "667") != 0)
+#endif
+ ) {
+ nbytes = 0;
+ }
+ }
+
+ strcpy(cpuClock, console_buffer);
+
+ } while (nbytes == 0);
+
+ if (strcmp(cpuClock, "500") == 0){
+ strcpy(plbClock, "166");
+ } else if (strcmp(cpuClock, "533") == 0){
+ strcpy(plbClock, "133");
+ } else {
+ do {
+ if (strcmp(cpuClock, "400") == 0)
+ printf("enter plb clock frequency 100, 133 MHz or quit to abort\n");
+
+#ifdef CONFIG_STRESS
+ if (strcmp(cpuClock, "667") == 0)
+ printf("enter plb clock frequency 133, 166 MHz or quit to abort\n");
+
+#endif
+ nbytes = cli_readline(" ? ");
+
+ if (strcmp(console_buffer, "quit") == 0)
+ return 0;
+
+ if (strcmp(cpuClock, "400") == 0) {
+ if ((strcmp(console_buffer, "100") != 0) &
+ (strcmp(console_buffer, "133") != 0))
+ nbytes = 0;
+ }
+#ifdef CONFIG_STRESS
+ if (strcmp(cpuClock, "667") == 0) {
+ if ((strcmp(console_buffer, "133") != 0) &
+ (strcmp(console_buffer, "166") != 0))
+ nbytes = 0;
+ }
+#endif
+ strcpy(plbClock, console_buffer);
+
+ } while (nbytes == 0);
+ }
+
+ do {
+ printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n");
+ nbytes = cli_readline(" ? ");
+
+ if (strcmp(console_buffer, "quit") == 0)
+ return 0;
+
+ if ((strcmp(console_buffer, "33") != 0) &
+ (strcmp(console_buffer, "66") != 0) &
+ (strcmp(console_buffer, "100") != 0) &
+ (strcmp(console_buffer, "133") != 0)) {
+ nbytes = 0;
+ }
+ strcpy(pcixClock, console_buffer);
+
+ } while (nbytes == 0);
+
+ printf("\nsys clk = %s MHz\n", sysClock);
+ printf("cpu clk = %s MHz\n", cpuClock);
+ printf("plb clk = %s MHz\n", plbClock);
+ printf("Pci-X clk = %s MHz\n", pcixClock);
+
+ do {
+ printf("\npress [y] to write I2C bootstrap\n");
+ printf("or [n] to abort.\n");
+ printf("Don't forget to set board switches\n");
+ printf("according to your choice before re-starting\n");
+ printf("(refer to 440spe_uboot_kit_um_1_01.pdf)\n");
+
+ nbytes = cli_readline(" ? ");
+ if (strcmp(console_buffer, "n") == 0)
+ return 0;
+
+ } while (nbytes == 0);
+
+ if (strcmp(sysClock, "33") == 0) {
+ if ((strcmp(cpuClock, "400") == 0) &
+ (strcmp(plbClock, "100") == 0))
+ data = 0x8678c206;
+
+ if ((strcmp(cpuClock, "400") == 0) &
+ (strcmp(plbClock, "133") == 0))
+ data = 0x8678c2c6;
+
+ if ((strcmp(cpuClock, "500") == 0))
+ data = 0x8778f2c6;
+
+ if ((strcmp(cpuClock, "533") == 0))
+ data = 0x87790252;
+
+#ifdef CONFIG_STRESS
+ if ((strcmp(cpuClock, "667") == 0) &
+ (strcmp(plbClock, "133") == 0))
+ data = 0x87794256;
+
+ if ((strcmp(cpuClock, "667") == 0) &
+ (strcmp(plbClock, "166") == 0))
+ data = 0x87794206;
+
+#endif
+ }
+ if (strcmp(sysClock, "66") == 0) {
+ if ((strcmp(cpuClock, "400") == 0) &
+ (strcmp(plbClock, "100") == 0))
+ data = 0x84706206;
+
+ if ((strcmp(cpuClock, "400") == 0) &
+ (strcmp(plbClock, "133") == 0))
+ data = 0x847062c6;
+
+ if ((strcmp(cpuClock, "533") == 0))
+ data = 0x85708206;
+
+#ifdef CONFIG_STRESS
+ if ((strcmp(cpuClock, "667") == 0) &
+ (strcmp(plbClock, "133") == 0))
+ data = 0x8570a256;
+
+ if ((strcmp(cpuClock, "667") == 0) &
+ (strcmp(plbClock, "166") == 0))
+ data = 0x8570a206;
+
+#endif
+ }
+
+#ifdef DEBUG
+ printf(" pin strap0 to write in i2c = %x\n", data);
+#endif /* DEBUG */
+
+ if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0)
+ printf("Error writing strap0 in %s\n", argv[2]);
+
+ if (strcmp(pcixClock, "33") == 0)
+ data = 0x00000701;
+
+ if (strcmp(pcixClock, "66") == 0)
+ data = 0x00000601;
+
+ if (strcmp(pcixClock, "100") == 0)
+ data = 0x00000501;
+
+ if (strcmp(pcixClock, "133") == 0)
+ data = 0x00000401;
+
+ if (strcmp(plbClock, "166") == 0)
+ data = data | 0x05950000;
+ else
+ data = data | 0x05A50000;
+
+#ifdef DEBUG
+ printf(" pin strap1 to write in i2c = %x\n", data);
+#endif /* DEBUG */
+
+ udelay(1000);
+ if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0)
+ printf("Error writing strap1 in %s\n", argv[2]);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ evb440spe, 3, 1, do_evb440spe,
+ "program the serial device strap",
+ "wrclk [prom0|prom1] - program the serial device strap"
+);
diff --git a/board/amcc/yucca/config.mk b/board/amcc/yucca/config.mk
new file mode 100644
index 0000000..05a4162
--- /dev/null
+++ b/board/amcc/yucca/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#
+# AMCC 440SPe Reference Platform (yucca) board
+#
+
+ifeq ($(ramsym),1)
+CONFIG_SYS_TEXT_BASE = 0x07FD0000
+else
+CONFIG_SYS_TEXT_BASE = 0xfffb0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c
new file mode 100644
index 0000000..b1fd657
--- /dev/null
+++ b/board/amcc/yucca/flash.c
@@ -0,0 +1,1033 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/ppc440.h>
+#include "yucca.h"
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
+ */
+static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
+ {0xfff00000, 0xfff80000, 0xe7c00001}, /* 0:boot from small flash */
+ {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */
+ {0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
+ {0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
+ {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
+ {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */
+ {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */
+ {0xfff00000, 0xfff80000, 0xe7c00001}, /* 8:boot from small flash */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_STM:
+ printf("STM ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf("SST ");
+ break;
+ case FLASH_MAN_MX:
+ printf("MIXC ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ printf("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_AM400B:
+ printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AMD016:
+ printf("AM29F016D (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_AM160B:
+ printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM033C:
+ printf("AM29LV033C (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_SST800A:
+ printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST160A:
+ printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_STMW320DT:
+ printf ("M29W320DT (32 M, top sector)\n");
+ break;
+ case FLASH_MXLV320T:
+ printf ("MXLV320T (32 Mbit, top sector)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
+ }
+
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " ");
+ }
+ printf("\n");
+ return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+ /* bit 0 used for big flash marking */
+ if ((ulong)addr & 0x1)
+ return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
+ else
+ return flash_get_size_1(addr, info);
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+ short i;
+ CONFIG_SYS_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
+ info->flash_id += FLASH_AMD016;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
+ info->flash_id += FLASH_AMDLV033C;
+ info->sector_count = 64;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] =
+ base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+ (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+ (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+ return flash_erase_2(info, s_first, s_last);
+ } else {
+ return flash_erase_1(info, s_first, s_last);
+ }
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!", prot);
+
+ printf("\n");
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_1(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+
+ for (; cnt == 0 && i < 4; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ if ((rc = write_word(info, wp, data)) != 0)
+ return (rc);
+
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i)
+ data = (data << 8) | *src++;
+
+ if ((rc = write_word(info, wp, data)) != 0)
+ return (rc);
+
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0)
+ return (0);
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+ if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
+ return write_word_2(info, dest, data);
+ } else {
+ return write_word_1(info, dest, data);
+ }
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i, flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data)
+ return (2);
+
+ for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+ return (1);
+ }
+ }
+
+ return (0);
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+
+#undef CONFIG_SYS_FLASH_WORD_SIZE
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+ short i;
+ int n;
+ CONFIG_SYS_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT:
+ info->flash_id = FLASH_MAN_MX;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+ case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
+ info->flash_id += FLASH_STMW320DT;
+ info->sector_count = 67;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+ case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T:
+ info->flash_id += FLASH_MXLV320T;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ /* 1 x 16k boot sector */
+ base -= 16 << 10;
+ --i;
+ info->start[i] = base;
+ /* 2 x 8k boot sectors */
+ for (n = 0; n < 2; ++n) {
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ /* 1 x 32k boot sector */
+ base -= 32 << 10;
+ --i;
+ info->start[i] = base;
+
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) {
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00002000;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000a000;
+ info->start[i--] = base + info->size - 0x0000c000;
+ info->start[i--] = base + info->size - 0x0000e000;
+ info->start[i--] = base + info->size - 0x00010000;
+
+ for (; i >= 0; i--)
+ info->start[i] = base + i * 0x00010000;
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+
+ for (i = 4; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+
+ for (; i >= 0; i--)
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+ /* For AMD29033C flash we need to resend the command of *
+ * reading flash protection for upper 8 Mb of flash */
+ if (i == 32) {
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+ (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+ (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!", prot);
+
+ printf("\n");
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_2(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+ ulong *data_ptr = &data;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data)
+ return (2);
+
+ for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+ return (1);
+ }
+ }
+
+ return (0);
+}
+#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+ unsigned short index = 0;
+ int i;
+ unsigned long val;
+ unsigned long ebc_boot_size;
+ unsigned long boot_selection;
+
+ mfsdr(sdr_pstrp0, val);
+ index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 28;
+
+ if ((index == 0xc) || (index == 8)) {
+ /*
+ * Boot Settings in IIC EEprom address 0xA8 or 0xA0
+ * Read Serial Device Strap Register1 in PPC440SPe
+ */
+ mfsdr(SDR0_SDSTP1, val);
+ boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
+ ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+ switch(boot_selection) {
+ case SDR0_SDSTP1_BOOT_SEL_EBC:
+ switch(ebc_boot_size) {
+ case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+ index = 3;
+ break;
+ case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+ index = 0;
+ break;
+ }
+ break;
+
+ case SDR0_SDSTP1_BOOT_SEL_PCI:
+ index = 1;
+ break;
+
+ }
+ } /*else if (index == 0) {*/
+/* if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/
+/* index = 8;*/ /* sram below op code flash -> new index 8*/
+/* }*/
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0)
+ continue;
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+ &flash_info[i]);
+
+ flash_info[i].size = size_b[i];
+
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+ &flash_info[i]);
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#if defined(CONFIG_ENV_ADDR_REDUND)
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#endif
+#endif
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
new file mode 100644
index 0000000..7da5c0d
--- /dev/null
+++ b/board/amcc/yucca/init.S
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+
+/**************************************************************************
+ * TLB table for revA
+ *************************************************************************/
+ .globl tlbtabA
+tlbtabA:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+ tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
+
+ tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
+ tlbtab_end
+
+/**************************************************************************
+ * TLB table for revB
+ *
+ * Notice: revB of the 440SPe chip is very strict about PLB real addresses
+ * and ranges to be mapped for config space: it seems to only work with
+ * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
+ * set otherwise) while revA uses c_nnnn_nnnn.
+ *************************************************************************/
+ .globl tlbtabB
+tlbtabB:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+ tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
+
+ tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
+ tlbtab_end
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
new file mode 100644
index 0000000..c0445ef
--- /dev/null
+++ b/board/amcc/yucca/yucca.c
@@ -0,0 +1,714 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Port to AMCC-440SPE Evaluation Board SOP - April 2005
+ *
+ * PCIe supporting routines derived from Linux 440SPe PCIe driver.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/4xx_pcie.h>
+#include <asm/errno.h>
+
+#include "yucca.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fpga_init (void);
+
+#define DEBUG_ENV
+#ifdef DEBUG_ENV
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+
+int board_early_init_f (void)
+{
+/*----------------------------------------------------------------------------+
+| Define Boot devices
++----------------------------------------------------------------------------*/
+#define BOOT_FROM_SMALL_FLASH 0x00
+#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
+#define BOOT_FROM_PCI 0x02
+#define BOOT_DEVICE_UNKNOWN 0x03
+
+/*----------------------------------------------------------------------------+
+| EBC Devices Characteristics
+| Peripheral Bank Access Parameters - EBC_BxAP
+| Peripheral Bank Configuration Register - EBC_BxCR
++----------------------------------------------------------------------------*/
+
+/*
+ * Small Flash and FRAM
+ * BU Value
+ * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
+ * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
+ */
+#define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(7) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(0) | \
+ EBC_BXAP_WBF_ENCODE(0) | \
+ EBC_BXAP_TH_ENCODE(0) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_DELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
+ EBC_BXCR_BS_16MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_8BIT
+
+#define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \
+ EBC_BXCR_BS_16MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_8BIT
+
+/*
+ * Large Flash and SRAM
+ * BU Value
+ * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
+ * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
+ * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
+*/
+#define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(7) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(0) | \
+ EBC_BXAP_WBN_ENCODE(0) | \
+ EBC_BXAP_WBF_ENCODE(0) | \
+ EBC_BXAP_TH_ENCODE(0) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_DELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
+ EBC_BXCR_BS_16MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT
+
+#define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \
+ EBC_BXCR_BS_16MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT
+
+/*
+ * FPGA
+ * BU value :
+ * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
+ * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
+ */
+#define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(11) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(10) | \
+ EBC_BXAP_OEN_ENCODE(1) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(1) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_DELAYED | \
+ EBC_BXAP_BEM_RW | \
+ EBC_BXAP_PEN_DISABLED
+
+#define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT
+
+ unsigned long mfr;
+ /*
+ * Define Variables for EBC initialization depending on BOOTSTRAP option
+ */
+ unsigned long sdr0_pinstp, sdr0_sdstp1 ;
+ unsigned long bootstrap_settings, ebc_data_width, boot_selection;
+ int computed_boot_device = BOOT_DEVICE_UNKNOWN;
+
+ /*-------------------------------------------------------------------+
+ | Initialize EBC CONFIG -
+ | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+ | default value :
+ | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+ |
+ +-------------------------------------------------------------------*/
+ mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
+ EBC_CFG_PTD_ENABLE |
+ EBC_CFG_RTC_16PERCLK |
+ EBC_CFG_ATC_PREVIOUS |
+ EBC_CFG_DTC_PREVIOUS |
+ EBC_CFG_CTC_PREVIOUS |
+ EBC_CFG_OEO_PREVIOUS |
+ EBC_CFG_EMC_DEFAULT |
+ EBC_CFG_PME_DISABLE |
+ EBC_CFG_PR_16);
+
+ /*-------------------------------------------------------------------+
+ |
+ | PART 1 : Initialize EBC Bank 1
+ | ==============================
+ | Bank1 is always associated to the EPLD.
+ | It has to be initialized prior to other banks settings computation
+ | since some board registers values may be needed to determine the
+ | boot type
+ |
+ +-------------------------------------------------------------------*/
+ mtebc(PB1AP, EBC_BXAP_FPGA);
+ mtebc(PB1CR, EBC_BXCR_FPGA_CS1);
+
+ /*-------------------------------------------------------------------+
+ |
+ | PART 2 : Determine which boot device was selected
+ | =================================================
+ |
+ | Read Pin Strap Register in PPC440SPe
+ | Result can either be :
+ | - Boot strap = boot from EBC 8bits => Small Flash
+ | - Boot strap = boot from PCI
+ | - Boot strap = IIC
+ | In case of boot from IIC, read Serial Device Strap Register1
+ |
+ | Result can either be :
+ | - Boot from EBC - EBC Bus Width = 8bits => Small Flash
+ | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
+ | - Boot from PCI
+ |
+ +-------------------------------------------------------------------*/
+ /* Read Pin Strap Register in PPC440SP */
+ mfsdr(SDR0_PINSTP, sdr0_pinstp);
+ bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
+
+ switch (bootstrap_settings) {
+ case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
+ /*
+ * Strapping Option A
+ * Boot from EBC - 8 bits , Small Flash
+ */
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
+ /*
+ * Strappping Option B
+ * Boot from PCI
+ */
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+ case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
+ case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
+ /*
+ * Strapping Option C or D
+ * Boot Settings in IIC EEprom address 0x50 or 0x54
+ * Read Serial Device Strap Register1 in PPC440SPe
+ */
+ mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
+ boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
+ ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
+
+ switch (boot_selection) {
+ case SDR0_SDSTP1_ERPN_EBC:
+ switch (ebc_data_width) {
+ case SDR0_SDSTP1_EBCW_16_BITS:
+ computed_boot_device =
+ BOOT_FROM_LARGE_FLASH_OR_SRAM;
+ break;
+ case SDR0_SDSTP1_EBCW_8_BITS :
+ computed_boot_device = BOOT_FROM_SMALL_FLASH;
+ break;
+ }
+ break;
+
+ case SDR0_SDSTP1_ERPN_PCI:
+ computed_boot_device = BOOT_FROM_PCI;
+ break;
+ default:
+ /* should not occure */
+ computed_boot_device = BOOT_DEVICE_UNKNOWN;
+ }
+ break;
+ default:
+ /* should not be */
+ computed_boot_device = BOOT_DEVICE_UNKNOWN;
+ break;
+ }
+
+ /*-------------------------------------------------------------------+
+ |
+ | PART 3 : Compute EBC settings depending on selected boot device
+ | ====== ======================================================
+ |
+ | Resulting EBC init will be among following configurations :
+ |
+ | - Boot from EBC 8bits => boot from Small Flash selected
+ | EBC-CS0 = Small Flash
+ | EBC-CS2 = Large Flash and SRAM
+ |
+ | - Boot from EBC 16bits => boot from Large Flash or SRAM
+ | EBC-CS0 = Large Flash or SRAM
+ | EBC-CS2 = Small Flash
+ |
+ | - Boot from PCI
+ | EBC-CS0 = not initialized to avoid address contention
+ | EBC-CS2 = same as boot from Small Flash selected
+ |
+ +-------------------------------------------------------------------*/
+ unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
+ unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
+
+ switch (computed_boot_device) {
+ /*-------------------------------------------------------------------*/
+ case BOOT_FROM_PCI:
+ /*-------------------------------------------------------------------*/
+ /*
+ * By Default CS2 is affected to LARGE Flash
+ * do not initialize SMALL FLASH to avoid address contention
+ * Large Flash
+ */
+ ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
+ ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
+ break;
+
+ /*-------------------------------------------------------------------*/
+ case BOOT_FROM_SMALL_FLASH:
+ /*-------------------------------------------------------------------*/
+ ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
+ ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
+
+ /*
+ * Large Flash or SRAM
+ */
+ /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
+ ebc0_cs2_bxap_value = 0x048ff240;
+ ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
+ break;
+
+ /*-------------------------------------------------------------------*/
+ case BOOT_FROM_LARGE_FLASH_OR_SRAM:
+ /*-------------------------------------------------------------------*/
+ ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
+ ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
+
+ /* Small flash */
+ ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
+ ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
+ break;
+
+ /*-------------------------------------------------------------------*/
+ default:
+ /*-------------------------------------------------------------------*/
+ /* BOOT_DEVICE_UNKNOWN */
+ break;
+ }
+
+ mtebc(PB0AP, ebc0_cs0_bxap_value);
+ mtebc(PB0CR, ebc0_cs0_bxcr_value);
+ mtebc(PB2AP, ebc0_cs2_bxap_value);
+ mtebc(PB2CR, ebc0_cs2_bxcr_value);
+
+ /*--------------------------------------------------------------------+
+ | Interrupt controller setup for the AMCC 440SPe Evaluation board.
+ +--------------------------------------------------------------------+
+ +---------------------------------------------------------------------+
+ |Interrupt| Source | Pol. | Sensi.| Crit. |
+ +---------+-----------------------------------+-------+-------+-------+
+ | IRQ 00 | UART0 | High | Level | Non |
+ | IRQ 01 | UART1 | High | Level | Non |
+ | IRQ 02 | IIC0 | High | Level | Non |
+ | IRQ 03 | IIC1 | High | Level | Non |
+ | IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
+ | IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
+ | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
+ | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
+ | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
+ | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
+ | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
+ | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
+ | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
+ | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
+ | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
+ | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
+ | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
+ | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
+ | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
+ | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
+ | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
+ | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
+ | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
+ | IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
+ | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
+ | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
+ | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
+ | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
+ | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
+ | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
+ | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
+ | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
+ |----------------------------------------------------------------------
+ | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
+ | IRQ 33 | MAL Serr | High | Level | Non |
+ | IRQ 34 | MAL Txde | High | Level | Non |
+ | IRQ 35 | MAL Rxde | High | Level | Non |
+ | IRQ 36 | DMC CE or DMC UE | High | Level | Non |
+ | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
+ | IRQ 38 | MAL TX EOB | High | Level | Non |
+ | IRQ 39 | MAL RX EOB | High | Level | Non |
+ | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
+ | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
+ | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
+ | IRQ 43 | L2 Cache | Risin | Edge | Non |
+ | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
+ | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
+ | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
+ | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
+ | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
+ | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
+ | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
+ | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
+ | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
+ | IRQ 54 | DMA Error | High | Level | Non |
+ | IRQ 55 | DMA I2O Error | High | Level | Non |
+ | IRQ 56 | Serial ROM | High | Level | Non |
+ | IRQ 57 | PCIX0 Error | High | Edge | Non |
+ | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
+ | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
+ | IRQ 60 | EMAC0 Interrupt | High | Level | Non |
+ | IRQ 61 | EMAC0 Wake-up | High | Level | Non |
+ | IRQ 62 | Reserved | High | Level | Non |
+ | IRQ 63 | XOR | High | Level | Non |
+ |----------------------------------------------------------------------
+ | IRQ 64 | PE0 AL | High | Level | Non |
+ | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
+ | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 68 | PE0 TCR | High | Level | Non |
+ | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 70 | PE0 DCR Error | High | Level | Non |
+ | IRQ 71 | Reserved | N/A | N/A | Non |
+ | IRQ 72 | PE1 AL | High | Level | Non |
+ | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
+ | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 76 | PE1 TCR | High | Level | Non |
+ | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 78 | PE1 DCR Error | High | Level | Non |
+ | IRQ 79 | Reserved | N/A | N/A | Non |
+ | IRQ 80 | PE2 AL | High | Level | Non |
+ | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
+ | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 84 | PE2 TCR | High | Level | Non |
+ | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 86 | PE2 DCR Error | High | Level | Non |
+ | IRQ 87 | Reserved | N/A | N/A | Non |
+ | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
+ | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
+ | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
+ | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
+ | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
+ | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
+ | IRQ 94 | Reserved | N/A | N/A | Non |
+ | IRQ 95 | Reserved | N/A | N/A | Non |
+ |---------------------------------------------------------------------
+ | IRQ 96 | PE0 INTA | High | Level | Non |
+ | IRQ 97 | PE0 INTB | High | Level | Non |
+ | IRQ 98 | PE0 INTC | High | Level | Non |
+ | IRQ 99 | PE0 INTD | High | Level | Non |
+ | IRQ 100 | PE1 INTA | High | Level | Non |
+ | IRQ 101 | PE1 INTB | High | Level | Non |
+ | IRQ 102 | PE1 INTC | High | Level | Non |
+ | IRQ 103 | PE1 INTD | High | Level | Non |
+ | IRQ 104 | PE2 INTA | High | Level | Non |
+ | IRQ 105 | PE2 INTB | High | Level | Non |
+ | IRQ 106 | PE2 INTC | High | Level | Non |
+ | IRQ 107 | PE2 INTD | Risin | Edge | Non |
+ | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
+ | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
+ | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
+ | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
+ | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
+ | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
+ | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
+ | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
+ | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
+ | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
+ | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
+ | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
+ | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
+ | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
+ | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
+ | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
+ | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
+ | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
+ | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
+ | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
+ +---------+-----------------------------------+-------+-------+------*/
+ /*--------------------------------------------------------------------+
+ | Put UICs in PowerPC440SPemode.
+ | Initialise UIC registers. Clear all interrupts. Disable all
+ | interrupts.
+ | Set critical interrupt values. Set interrupt polarities. Set
+ | interrupt trigger levels. Make bit 0 High priority. Clear all
+ | interrupts again.
+ +-------------------------------------------------------------------*/
+ mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical
+ * interrupts */
+ mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest
+ * priority */
+ mtdcr (UIC3SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical
+ * interrupts */
+ mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities */
+ mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest
+ * priority */
+ mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical
+ * interrupts */
+ mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest
+ * priority */
+ mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted
+ * cascade to be checked */
+ mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical
+ * interrupts */
+ mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest
+ * priority */
+ mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
+
+ mfsdr(SDR0_MFR, mfr);
+ mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
+ mtsdr(SDR0_MFR, mfr);
+
+ fpga_init();
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: Yucca - AMCC 440SPe Evaluation Board");
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+/*
+ * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+static int ppc440spe_rev_a(void)
+{
+ if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
+ return 1;
+ else
+ return 0;
+}
+
+u32 ddr_wrdtr(u32 default_val) {
+ /*
+ * Yucca boards with 440SPe rev. A need a slightly different setup
+ * for the MCIF0_WRDTR register.
+ */
+ if (ppc440spe_rev_a())
+ return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
+
+ return default_val;
+}
+
+u32 ddr_clktr(u32 default_val) {
+ /*
+ * Yucca boards with 440SPe rev. A need a slightly different setup
+ * for the MCIF0_CLKTR register.
+ */
+ if (ppc440spe_rev_a())
+ return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+
+ return default_val;
+}
+
+#if defined(CONFIG_PCI)
+int board_pcie_card_present(int port)
+{
+ u16 reg;
+
+ reg = in_be16((u16 *)FPGA_REG1C);
+ switch(port) {
+ case 0:
+ return !(reg & FPGA_REG1C_PE0_PRSNT);
+ case 1:
+ return !(reg & FPGA_REG1C_PE1_PRSNT);
+ case 2:
+ return !(reg & FPGA_REG1C_PE2_PRSNT);
+ default:
+ return 0;
+ }
+}
+
+/*
+ * For the given slot, set endpoint mode, send power to the slot,
+ * turn on the green LED and turn off the yellow LED, enable the
+ * clock. In endpoint mode reset bit is read only.
+ */
+void board_pcie_setup_port(int port, int rootpoint)
+{
+ u16 power, clock, green_led, yellow_led,
+ reset_off, rp, ep;
+
+ switch (port) {
+ case 0:
+ rp = FPGA_REG1C_PE0_ROOTPOINT;
+ ep = 0;
+ break;
+ case 1:
+ rp = 0;
+ ep = FPGA_REG1C_PE1_ENDPOINT;
+ break;
+ case 2:
+ rp = 0;
+ ep = FPGA_REG1C_PE2_ENDPOINT;
+ break;
+
+ default:
+ return;
+ }
+
+ power = FPGA_REG1A_PWRON_ENCODE(port);
+ green_led = FPGA_REG1A_GLED_ENCODE(port);
+ clock = FPGA_REG1A_REFCLK_ENCODE(port);
+ yellow_led = FPGA_REG1A_YLED_ENCODE(port);
+ reset_off = FPGA_REG1C_PERST_ENCODE(port);
+
+ out_be16((u16 *)FPGA_REG1A, ~(power | clock | green_led) &
+ (yellow_led | in_be16((u16 *)FPGA_REG1A)));
+
+ out_be16((u16 *)FPGA_REG1C, ~(ep | reset_off) &
+ (rp | in_be16((u16 *)FPGA_REG1C)));
+
+ if (rootpoint) {
+ /*
+ * Leave device in reset for a while after powering on the
+ * slot to give it a chance to initialize.
+ */
+ udelay(250 * 1000);
+
+ out_be16((u16 *)FPGA_REG1C,
+ reset_off | in_be16((u16 *)FPGA_REG1C));
+ }
+}
+#endif /* defined(CONFIG_PCI) */
+
+int misc_init_f (void)
+{
+ uint reg;
+
+ out16(FPGA_REG10, (in16(FPGA_REG10) &
+ ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
+ FPGA_REG10_10MHZ_ENABLE |
+ FPGA_REG10_100MHZ_ENABLE |
+ FPGA_REG10_GIGABIT_ENABLE |
+ FPGA_REG10_FULL_DUPLEX );
+
+ udelay(10000); /* wait 10ms */
+
+ out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
+
+ /* minimal init for PCIe */
+ /* pci express 0 Endpoint Mode */
+ mfsdr(SDRN_PESDR_DLPSET(0), reg);
+ reg &= (~0x00400000);
+ mtsdr(SDRN_PESDR_DLPSET(0), reg);
+ /* pci express 1 Rootpoint Mode */
+ mfsdr(SDRN_PESDR_DLPSET(1), reg);
+ reg |= 0x00400000;
+ mtsdr(SDRN_PESDR_DLPSET(1), reg);
+ /* pci express 2 Rootpoint Mode */
+ mfsdr(SDRN_PESDR_DLPSET(2), reg);
+ reg |= 0x00400000;
+ mtsdr(SDRN_PESDR_DLPSET(2), reg);
+
+ out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
+ ~FPGA_REG1C_PE0_ROOTPOINT &
+ ~FPGA_REG1C_PE1_ENDPOINT &
+ ~FPGA_REG1C_PE2_ENDPOINT));
+
+ return 0;
+}
+
+void fpga_init(void)
+{
+ /*
+ * by default sdram access is disabled by fpga
+ */
+ out16(FPGA_REG10, (in16 (FPGA_REG10) |
+ FPGA_REG10_SDRAM_ENABLE |
+ FPGA_REG10_ENABLE_DISPLAY ));
+
+ return;
+}
+
+/*---------------------------------------------------------------------------+
+ | onboard_pci_arbiter_selected => from EPLD
+ +---------------------------------------------------------------------------*/
+int onboard_pci_arbiter_selected(int core_pci)
+{
+#if 0
+ unsigned long onboard_pci_arbiter_sel;
+
+ onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
+
+ if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
+ return (BOARD_OPTION_SELECTED);
+ else
+#endif
+ return (BOARD_OPTION_NOT_SELECTED);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis);
+ return pci_eth_init(bis);
+}
diff --git a/board/amcc/yucca/yucca.h b/board/amcc/yucca/yucca.h
new file mode 100644
index 0000000..ac9e5ae
--- /dev/null
+++ b/board/amcc/yucca/yucca.h
@@ -0,0 +1,350 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __YUCCA_H_
+#define __YUCCA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------+
+| Defines
++----------------------------------------------------------------------------*/
+
+#define TMR_FREQ_EXT 25000000
+#define BOARD_UART_CLOCK 11059200
+
+#define BOARD_OPTION_SELECTED 1
+#define BOARD_OPTION_NOT_SELECTED 0
+
+#define ENGINEERING_CLOCK_CHECKING "clk_chk"
+#define ENGINEERING_EXTERNAL_CLOCK "ext_clk"
+
+#define ENGINEERING_CLOCK_CHECKING_DATA 1
+#define ENGINEERING_EXTERNAL_CLOCK_DATA 2
+
+/* ethernet definition */
+#define MAX_ENETMODE_PARM 3
+#define ENETMODE_NEG 0
+#define ENETMODE_SPEED 1
+#define ENETMODE_DUPLEX 2
+
+#define ENETMODE_AUTONEG 0
+#define ENETMODE_NO_AUTONEG 1
+#define ENETMODE_10 2
+#define ENETMODE_100 3
+#define ENETMODE_1000 4
+#define ENETMODE_HALF 5
+#define ENETMODE_FULL 6
+
+#define NUM_TLB_ENTRIES 64
+
+/* MICRON SPD JEDEC ID Code (first byte) - SPD data byte [64] */
+#define MICRON_SPD_JEDEC_ID 0x2c
+
+/*----------------------------------------------------------------------------+
+| TLB specific defines.
++----------------------------------------------------------------------------*/
+#define TLB_256MB_ALIGN_MASK 0xF0000000
+#define TLB_16MB_ALIGN_MASK 0xFF000000
+#define TLB_1MB_ALIGN_MASK 0xFFF00000
+#define TLB_256KB_ALIGN_MASK 0xFFFC0000
+#define TLB_64KB_ALIGN_MASK 0xFFFF0000
+#define TLB_16KB_ALIGN_MASK 0xFFFFC000
+#define TLB_4KB_ALIGN_MASK 0xFFFFF000
+#define TLB_1KB_ALIGN_MASK 0xFFFFFC00
+#define TLB_256MB_SIZE 0x10000000
+#define TLB_16MB_SIZE 0x01000000
+#define TLB_1MB_SIZE 0x00100000
+#define TLB_256KB_SIZE 0x00040000
+#define TLB_64KB_SIZE 0x00010000
+#define TLB_16KB_SIZE 0x00004000
+#define TLB_4KB_SIZE 0x00001000
+#define TLB_1KB_SIZE 0x00000400
+
+#define TLB_WORD0_EPN_MASK 0xFFFFFC00
+#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD0_V_MASK 0x00000200
+#define TLB_WORD0_V_ENABLE 0x00000200
+#define TLB_WORD0_V_DISABLE 0x00000000
+#define TLB_WORD0_TS_MASK 0x00000100
+#define TLB_WORD0_TS_1 0x00000100
+#define TLB_WORD0_TS_0 0x00000000
+#define TLB_WORD0_SIZE_MASK 0x000000F0
+#define TLB_WORD0_SIZE_1KB 0x00000000
+#define TLB_WORD0_SIZE_4KB 0x00000010
+#define TLB_WORD0_SIZE_16KB 0x00000020
+#define TLB_WORD0_SIZE_64KB 0x00000030
+#define TLB_WORD0_SIZE_256KB 0x00000040
+#define TLB_WORD0_SIZE_1MB 0x00000050
+#define TLB_WORD0_SIZE_16MB 0x00000070
+#define TLB_WORD0_SIZE_256MB 0x00000090
+#define TLB_WORD0_TPAR_MASK 0x0000000F
+#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+#define TLB_WORD1_RPN_MASK 0xFFFFFC00
+#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
+#define TLB_WORD1_PAR1_MASK 0x00000300
+#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
+#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
+#define TLB_WORD1_PAR1_0 0x00000000
+#define TLB_WORD1_PAR1_1 0x00000100
+#define TLB_WORD1_PAR1_2 0x00000200
+#define TLB_WORD1_PAR1_3 0x00000300
+#define TLB_WORD1_ERPN_MASK 0x0000000F
+#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
+#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
+
+#define TLB_WORD2_PAR2_MASK 0xC0000000
+#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
+#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
+#define TLB_WORD2_PAR2_0 0x00000000
+#define TLB_WORD2_PAR2_1 0x40000000
+#define TLB_WORD2_PAR2_2 0x80000000
+#define TLB_WORD2_PAR2_3 0xC0000000
+#define TLB_WORD2_U0_MASK 0x00008000
+#define TLB_WORD2_U0_ENABLE 0x00008000
+#define TLB_WORD2_U0_DISABLE 0x00000000
+#define TLB_WORD2_U1_MASK 0x00004000
+#define TLB_WORD2_U1_ENABLE 0x00004000
+#define TLB_WORD2_U1_DISABLE 0x00000000
+#define TLB_WORD2_U2_MASK 0x00002000
+#define TLB_WORD2_U2_ENABLE 0x00002000
+#define TLB_WORD2_U2_DISABLE 0x00000000
+#define TLB_WORD2_U3_MASK 0x00001000
+#define TLB_WORD2_U3_ENABLE 0x00001000
+#define TLB_WORD2_U3_DISABLE 0x00000000
+#define TLB_WORD2_W_MASK 0x00000800
+#define TLB_WORD2_W_ENABLE 0x00000800
+#define TLB_WORD2_W_DISABLE 0x00000000
+#define TLB_WORD2_I_MASK 0x00000400
+#define TLB_WORD2_I_ENABLE 0x00000400
+#define TLB_WORD2_I_DISABLE 0x00000000
+#define TLB_WORD2_M_MASK 0x00000200
+#define TLB_WORD2_M_ENABLE 0x00000200
+#define TLB_WORD2_M_DISABLE 0x00000000
+#define TLB_WORD2_G_MASK 0x00000100
+#define TLB_WORD2_G_ENABLE 0x00000100
+#define TLB_WORD2_G_DISABLE 0x00000000
+#define TLB_WORD2_E_MASK 0x00000080
+#define TLB_WORD2_E_ENABLE 0x00000080
+#define TLB_WORD2_E_DISABLE 0x00000000
+#define TLB_WORD2_UX_MASK 0x00000020
+#define TLB_WORD2_UX_ENABLE 0x00000020
+#define TLB_WORD2_UX_DISABLE 0x00000000
+#define TLB_WORD2_UW_MASK 0x00000010
+#define TLB_WORD2_UW_ENABLE 0x00000010
+#define TLB_WORD2_UW_DISABLE 0x00000000
+#define TLB_WORD2_UR_MASK 0x00000008
+#define TLB_WORD2_UR_ENABLE 0x00000008
+#define TLB_WORD2_UR_DISABLE 0x00000000
+#define TLB_WORD2_SX_MASK 0x00000004
+#define TLB_WORD2_SX_ENABLE 0x00000004
+#define TLB_WORD2_SX_DISABLE 0x00000000
+#define TLB_WORD2_SW_MASK 0x00000002
+#define TLB_WORD2_SW_ENABLE 0x00000002
+#define TLB_WORD2_SW_DISABLE 0x00000000
+#define TLB_WORD2_SR_MASK 0x00000001
+#define TLB_WORD2_SR_ENABLE 0x00000001
+#define TLB_WORD2_SR_DISABLE 0x00000000
+
+/*----------------------------------------------------------------------------+
+| Board specific defines.
++----------------------------------------------------------------------------*/
+#define NONCACHE_MEMORY_SIZE (64*1024)
+#define NONCACHE_AREA0_ENDOFFSET (64*1024)
+#define NONCACHE_AREA1_ENDOFFSET (32*1024)
+
+#define FLASH_SECTORSIZE 0x00010000
+
+/* SDRAM MICRON */
+#define SDRAM_MICRON 0x2C
+
+#define SDRAM_TRUE 1
+#define SDRAM_FALSE 0
+#define SDRAM_DDR1 1
+#define SDRAM_DDR2 2
+#define SDRAM_NONE 0
+#define MAXDIMMS 2 /* Changes le 12/01/05 pour 1.6 */
+#define MAXRANKS 4 /* Changes le 12/01/05 pour 1.6 */
+#define MAXBANKSPERDIMM 2
+#define MAXRANKSPERDIMM 2
+#define MAXBXCF 4 /* Changes le 12/01/05 pour 1.6 */
+#define MAXSDRAMMEMORY 0xFFFFFFFF /* 4GB */
+#define ERROR_STR_LENGTH 256
+#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
+
+/*----------------------------------------------------------------------------+
+| SDR Configuration registers
++----------------------------------------------------------------------------*/
+/* Serial Device Strap Reg 0 */
+#define sdr_pstrp0 0x0040
+
+#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00000080 /* EBC Boot bus width Mask */
+#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00000080 /* EBC 16 Bits */
+#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */
+
+#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00080000 /* Boot device Selection Mask */
+#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */
+#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00080000 /* PCI */
+
+#define SDR0_SDSTP1_EBC_SIZE_MASK 0x00000060 /* Boot rom size Mask */
+#define SDR0_SDSTP1_BOOT_SIZE_16MB 0x00000060 /* 16 MB */
+#define SDR0_SDSTP1_BOOT_SIZE_8MB 0x00000040 /* 8 MB */
+#define SDR0_SDSTP1_BOOT_SIZE_4MB 0x00000020 /* 4 MB */
+#define SDR0_SDSTP1_BOOT_SIZE_2MB 0x00000000 /* 2 MB */
+
+/* Serial Device Enabled - Addr = 0xA8 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
+/* Serial Device Enabled - Addr = 0xA4 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
+
+/* Pin Straps Reg */
+#define SDR0_PSTRP0 0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */
+
+/* fpgareg - defines are in include/config/YUCCA.h */
+
+#define SDR0_CUST0_ENET3_MASK 0x00000080
+#define SDR0_CUST0_ENET3_COPPER 0x00000000
+#define SDR0_CUST0_ENET3_FIBER 0x00000080
+#define SDR0_CUST0_RGMII3_MASK 0x00000070
+#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
+#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
+#define SDR0_CUST0_RGMII3_DISAB 0x00000000
+#define SDR0_CUST0_RGMII3_RTBI 0x00000040
+#define SDR0_CUST0_RGMII3_RGMII 0x00000050
+#define SDR0_CUST0_RGMII3_TBI 0x00000060
+#define SDR0_CUST0_RGMII3_GMII 0x00000070
+#define SDR0_CUST0_ENET2_MASK 0x00000008
+#define SDR0_CUST0_ENET2_COPPER 0x00000000
+#define SDR0_CUST0_ENET2_FIBER 0x00000008
+#define SDR0_CUST0_RGMII2_MASK 0x00000007
+#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
+#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
+#define SDR0_CUST0_RGMII2_DISAB 0x00000000
+#define SDR0_CUST0_RGMII2_RTBI 0x00000004
+#define SDR0_CUST0_RGMII2_RGMII 0x00000005
+#define SDR0_CUST0_RGMII2_TBI 0x00000006
+#define SDR0_CUST0_RGMII2_GMII 0x00000007
+
+#define ONE_MILLION 1000000
+#define ONE_BILLION 1000000000
+
+/*----------------------------------------------------------------------------+
+| X
+| XX
+| XX XXX XXXXX XX XXX XXXXX
+| XX XX X XXX XX XX
+| XX XX XXXXXX XX XX
+| XX XX X XX XX XX XX
+| XXX XX XXXXX X XXXX XXX
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+| Declare Configuration values
++----------------------------------------------------------------------------*/
+
+typedef enum config_selection {
+ CONFIG_NOT_SELECTED,
+ CONFIG_SELECTED
+} config_selection_t;
+
+typedef enum config_list {
+ UART2_IN_SERVICE_MODE,
+ CPU_TRACE_MODE,
+ UART1_CTS_RTS,
+ CONFIG_NB
+} config_list_t;
+
+#define MAX_CONFIG_SELECT_NB 3
+
+#define BOARD_INFO_UART2_IN_SERVICE_MODE 1
+#define BOARD_INFO_CPU_TRACE_MODE 2
+#define BOARD_INFO_UART1_CTS_RTS_MODE 4
+
+void force_bup_config_selection(config_selection_t *confgi_select_P);
+void update_config_selection_table(config_selection_t *config_select_P);
+void display_config_selection(config_selection_t *config_select_P);
+
+/*----------------------------------------------------------------------------+
+| XX
+|
+| XXXX XX XXX XXX XXXX
+| XX XX XX XX XX XX
+| XX XXX XX XX XX XX XX
+| XX XX XXXXX XX XX XX
+| XXXX XX XXXX XXXX
+| XXXX
+|
+|
+|
+| +------------------------------------------------------------------+
+| | GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O |
+| +----------------------+------------------+-----+------------+-----+
+| | | | | | |
+| | GPIO0_0 | PCIX0REQ2_N | I/O | TRCCLK | |
+| | GPIO0_1 | PCIX0REQ3_N | I/O | TRCBS0 | |
+| | GPIO0_2 | PCIX0GNT2_N | I/O | TRCBS1 | |
+| | GPIO0_3 | PCIX0GNT3_N | I/O | TRCBS2 | |
+| | GPIO0_4 | PCIX1REQ2_N | I/O | TRCES0 | |
+| | GPIO0_5 | PCIX1REQ3_N | I/O | TRCES1 | |
+| | GPIO0_6 | PCIX1GNT2_N | I/O | TRCES2 | NA |
+| | GPIO0_7 | PCIX1GNT3_N | I/O | TRCES3 | NA |
+| | GPIO0_8 | PERREADY | I | TRCES4 | NA |
+| | GPIO0_9 | PERCS1_N | O | TRCTS0 | NA |
+| | GPIO0_10 | PERCS2_N | O | TRCTS1 | NA |
+| | GPIO0_11 | IRQ0 | I | TRCTS2 | NA |
+| | GPIO0_12 | IRQ1 | I | TRCTS3 | NA |
+| | GPIO0_13 | IRQ2 | I | TRCTS4 | NA |
+| | GPIO0_14 | IRQ3 | I | TRCTS5 | NA |
+| | GPIO0_15 | IRQ4 | I | TRCTS6 | NA |
+| | GPIO0_16 | IRQ5 | I | UART2RX | I |
+| | GPIO0_17 | PERBE0_N | O | UART2TX | O |
+| | GPIO0_18 | PCI0GNT0_N | I/O | NA | NA |
+| | GPIO0_19 | PCI0GNT1_N | I/O | NA | NA |
+| | GPIO0_20 | PCI0REQ0_N | I/O | NA | NA |
+| | GPIO0_21 | PCI0REQ1_N | I/O | NA | NA |
+| | GPIO0_22 | PCI1GNT0_N | I/O | NA | NA |
+| | GPIO0_23 | PCI1GNT1_N | I/O | NA | NA |
+| | GPIO0_24 | PCI1REQ0_N | I/O | NA | NA |
+| | GPIO0_25 | PCI1REQ1_N | I/O | NA | NA |
+| | GPIO0_26 | PCI2GNT0_N | I/O | NA | NA |
+| | GPIO0_27 | PCI2GNT1_N | I/O | NA | NA |
+| | GPIO0_28 | PCI2REQ0_N | I/O | NA | NA |
+| | GPIO0_29 | PCI2REQ1_N | I/O | NA | NA |
+| | GPIO0_30 | UART1RX | I | NA | NA |
+| | GPIO0_31 | UART1TX | O | NA | NA |
+| | | | | | |
+| +----------------------+------------------+-----+------------+-----+
+|
++----------------------------------------------------------------------------*/
+
+unsigned long auto_calc_speed(void);
+/*----------------------------------------------------------------------------+
+| Prototypes
++----------------------------------------------------------------------------*/
+void print_evb440spe_info(void);
+
+int onboard_pci_arbiter_selected(int core_pci);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __YUCCA_H_ */
diff --git a/board/amlogic/Kconfig b/board/amlogic/Kconfig
new file mode 100755
index 0000000..decb872
--- /dev/null
+++ b/board/amlogic/Kconfig
@@ -0,0 +1,399 @@
+
+config GXB_SKT_V1
+ bool "Support amlogic gxbaby skt v1 board"
+ default n
+
+config GXB_P200_V1
+ bool "Support amlogic gxbaby p200(develop) v1 board"
+ default n
+
+config GXB_P201_V1
+ bool "Support amlogic gxbaby p200(reference) v1 board"
+ default n
+
+config GXTVBB_SKT_V1
+ bool "Support amlogic gxtv baby socket v1 board"
+ default n
+
+config GXTVBB_P301_V1
+ bool "Support amlogic gxtv baby p301(reference) v1 board"
+ default n
+
+config GXTVBB_P300_V1
+ bool "Support amlogic gxtv baby p300(develop) v1 board"
+ default n
+
+config GXTVBB_P310_V1
+ bool "Support amlogic gxtv baby P310 socket v1 board"
+ default n
+
+config GXTVBB_P311_V1
+ bool "Support amlogic gxtv baby P311 socket v1 board"
+ default n
+
+config GXTVBB_9023_SKT_V1
+ bool "Support amlogic gxtv baby 9023 socket v1 board"
+ default n
+
+config GXTVBB_T966_SKT_V1
+ bool "Support amlogic gxtv baby 9023 socket v1 board"
+ default n
+
+config GXL_SKT_V1
+ bool "Support amlogic gxl socket v1 board"
+ default n
+
+config GXL_P212_V1
+ bool "Support amlogic gxl p212 board"
+ default n
+
+config GXL_ESTELLE_P0
+ bool "Support amlogic gxl estelle p0 board"
+ default n
+
+config GXL_S905X_P0
+ bool "Support amlogic gxl s905x p0 board"
+ default n
+
+config GXL_P281_V1
+ bool "Support amlogic gxl p281 board"
+ default n
+
+config GXL_P271_V1
+ bool "Support amlogic gxl p271 board"
+ default n
+
+config GXL_P241_V1
+ bool "Support amlogic gxl p241 board"
+ default n
+
+config GXL_P230_V1
+ bool "Support amlogic gxm/gxl p230 board"
+ default n
+
+config GXL_P231_V1
+ bool "Support amlogic gxm/gxl p231 board"
+ default n
+
+config GXL_P400_V1
+ bool "Support amlogic gxl p400 board"
+ default n
+
+config GXL_P401_V1
+ bool "Support amlogic gxl p401 board"
+ default n
+
+config GXM_SKT_V1
+ bool "Support amlogic gxm/gxl skt board"
+ default n
+
+config GXM_Q201_V1
+ bool "Support amlogic gxm/gxl q201 board"
+ default n
+
+config GXM_Q200_V1
+ bool "Support amlogic gxm/gxl q200 board"
+ default n
+
+config TXL_SKT_V1
+ bool "Support amlogic txl socket v1 board"
+ default n
+
+config TXL_P320_V1
+ bool "Support amlogic txl p320 board"
+ default n
+
+config TXL_P321_V1
+ bool "Support amlogic txl p321 board"
+ default n
+
+config TXL_T950_SKT_V1
+ bool "Support amlogic txl t950 socket board"
+ default n
+
+config TXL_P341_V1
+ bool "Support amlogic txl t950 p341 board"
+ default n
+
+config TXL_P341_V2
+ bool "Support amlogic txl t950 p341 v2 board"
+ default n
+
+config TXL_P346_V1
+ bool "Support amlogic txl t960 p346 v1 board"
+ default n
+
+config TXLX_T962X_SKT_V1
+ bool "Support amlogic txlx t962x skt v1 board"
+ default n
+
+config TXLX_T962E_SKT_V1
+ bool "Support amlogic txlx t962e skt v1 board"
+ default n
+
+config TXLX_T962X_R311_V1
+ bool "Support amlogic txlx t962x r311 v1 board"
+ default n
+
+config TXLX_T962E_R321_V1
+ bool "Support amlogic txlx t962e r321 v1 board"
+ default n
+
+config AXG_SKT_V1
+ bool "Support amlogic axg skt v1 board"
+ default n
+
+config AXG_S400_V1
+ bool "Support amlogic axg s400 v1 board"
+ default n
+
+config AXG_S420_V1
+ bool "Support amlogic axg s420 v1 board"
+ default n
+
+config TXHD_SKT_V1
+ bool "Support amlogic txhd socket v1 board"
+ default n
+
+config TXHD_R341_V1
+ bool "Support amlogic txhd r341 v1 board"
+ default n
+
+config G12A_SKT_V1
+ bool "Support amlogic g12a skt v1 board"
+ default n
+
+config G12A_ESTELLE_P2
+ bool "Support google estelle p2 board"
+ default n
+
+config G12A_ESTELLE_BX
+ bool "Support google estelle bx board"
+ default n
+
+config G12A_NEWMAN_P0
+ bool "Support google newman p0 board"
+ default n
+
+config G12A_U200_V1
+ bool "Support amlogic g12a u200 v1 board"
+ default n
+
+config G12A_U211_V1
+ bool "Support amlogic g12a u211 v1 board"
+ default n
+
+config G12A_U220_V1
+ bool "Support amlogic g12a u220 v1 board"
+ default n
+
+config G12A_U221_V1
+ bool "Support amlogic g12a u221 v1 board"
+ default n
+
+config PXP_EMULATOR
+ bool "Support pxp environment"
+ default n
+
+config SUPPORT_CUSOTMER_BOARD
+ bool "Customer board support"
+
+config ODROID_C2
+ bool "Support Hardkernel ODROID-C2 board"
+ default n
+
+if GXB_SKT_V1
+source "board/amlogic/gxb_skt_v1/Kconfig"
+endif
+
+if GXB_P200_V1
+source "board/amlogic/gxb_p200_v1/Kconfig"
+endif
+
+if GXB_P201_V1
+source "board/amlogic/gxb_p201_v1/Kconfig"
+endif
+
+if GXTVBB_SKT_V1
+source "board/amlogic/gxtvbb_skt_v1/Kconfig"
+endif
+
+if GXTVBB_P301_V1
+source "board/amlogic/gxtvbb_p301_v1/Kconfig"
+endif
+
+if GXTVBB_P300_V1
+source "board/amlogic/gxtvbb_p300_v1/Kconfig"
+endif
+
+if GXTVBB_P310_V1
+source "board/amlogic/gxtvbb_p310_v1/Kconfig"
+endif
+
+if GXTVBB_P311_V1
+source "board/amlogic/gxtvbb_p311_v1/Kconfig"
+endif
+
+if GXTVBB_9023_SKT_V1
+source "board/amlogic/gxtvbb_9023_skt_v1/Kconfig"
+endif
+
+if GXTVBB_T966_SKT_V1
+source "board/amlogic/gxtvbb_t966_skt_v1/Kconfig"
+endif
+
+if GXL_SKT_V1
+source "board/amlogic/gxl_skt_v1/Kconfig"
+endif
+
+if GXL_P212_V1
+source "board/amlogic/gxl_p212_v1/Kconfig"
+endif
+
+if GXL_ESTELLE_P0
+source "board/amlogic/gxl_estelle_p0/Kconfig"
+endif
+
+if GXL_S905X_P0
+source "board/amlogic/gxl_s905x_p0/Kconfig"
+endif
+
+if GXL_P281_V1
+source "board/amlogic/gxl_p281_v1/Kconfig"
+endif
+
+if GXL_P271_V1
+source "board/amlogic/gxl_p271_v1/Kconfig"
+endif
+
+if GXL_P241_V1
+source "board/amlogic/gxl_p241_v1/Kconfig"
+endif
+
+if GXL_P230_V1
+source "board/amlogic/gxl_p230_v1/Kconfig"
+endif
+
+if GXL_P231_V1
+source "board/amlogic/gxl_p231_v1/Kconfig"
+endif
+
+if GXL_P400_V1
+source "board/amlogic/gxl_p400_v1/Kconfig"
+endif
+
+if GXL_P401_V1
+source "board/amlogic/gxl_p401_v1/Kconfig"
+endif
+
+if GXM_SKT_V1
+source "board/amlogic/gxm_skt_v1/Kconfig"
+endif
+
+if GXM_Q201_V1
+source "board/amlogic/gxm_q201_v1/Kconfig"
+endif
+
+if GXM_Q200_V1
+source "board/amlogic/gxm_q200_v1/Kconfig"
+endif
+
+if TXL_SKT_V1
+source "board/amlogic/txl_skt_v1/Kconfig"
+endif
+
+if TXL_P320_V1
+source "board/amlogic/txl_p320_v1/Kconfig"
+endif
+
+if TXL_P321_V1
+source "board/amlogic/txl_p321_v1/Kconfig"
+endif
+
+if TXL_T950_SKT_V1
+source "board/amlogic/txl_t950_skt_v1/Kconfig"
+endif
+
+if TXL_P341_V1
+source "board/amlogic/txl_p341_v1/Kconfig"
+endif
+
+if TXL_P341_V2
+source "board/amlogic/txl_p341_v2/Kconfig"
+endif
+
+if TXL_P346_V1
+source "board/amlogic/txl_p346_v1/Kconfig"
+endif
+
+if TXLX_T962X_SKT_V1
+source "board/amlogic/txlx_t962x_skt_v1/Kconfig"
+endif
+
+if TXLX_T962E_SKT_V1
+source "board/amlogic/txlx_t962e_skt_v1/Kconfig"
+endif
+
+if TXLX_T962X_R311_V1
+source "board/amlogic/txlx_t962x_r311_v1/Kconfig"
+endif
+
+if TXLX_T962E_R321_V1
+source "board/amlogic/txlx_t962e_r321_v1/Kconfig"
+endif
+
+if AXG_SKT_V1
+source "board/amlogic/axg_skt_v1/Kconfig"
+endif
+
+if AXG_S400_V1
+source "board/amlogic/axg_s400_v1/Kconfig"
+endif
+
+if AXG_S420_V1
+source "board/amlogic/axg_s420_v1/Kconfig"
+endif
+
+if TXHD_SKT_V1
+source "board/amlogic/txhd_skt_v1/Kconfig"
+endif
+
+if TXHD_R341_V1
+source "board/amlogic/txhd_r341_v1/Kconfig"
+endif
+
+if G12A_SKT_V1
+source "board/amlogic/g12a_skt_v1/Kconfig"
+endif
+
+if G12A_ESTELLE_P2
+source "board/amlogic/g12a_estelle_p2/Kconfig"
+endif
+
+if G12A_ESTELLE_BX
+source "board/amlogic/g12a_estelle_bx/Kconfig"
+endif
+
+if G12A_NEWMAN_P0
+source "board/amlogic/g12a_newman_p0/Kconfig"
+endif
+
+if G12A_U200_V1
+source "board/amlogic/g12a_u200_v1/Kconfig"
+endif
+
+if G12A_U211_V1
+source "board/amlogic/g12a_u211_v1/Kconfig"
+endif
+
+if G12A_U220_V1
+source "board/amlogic/g12a_u220_v1/Kconfig"
+endif
+
+if G12A_U221_V1
+source "board/amlogic/g12a_u221_v1/Kconfig"
+endif
+
+if ODROID_C2
+source "board/hardkernel/odroidc2/Kconfig"
+endif
diff --git a/board/amlogic/axg_s400_v1/Kconfig b/board/amlogic/axg_s400_v1/Kconfig
new file mode 100644
index 0000000..00da0b2
--- /dev/null
+++ b/board/amlogic/axg_s400_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_AXG
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "axg_s400_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "axg"
+
+config SYS_CONFIG_NAME
+ default "axg_s400_v1"
+
+endif
diff --git a/board/amlogic/axg_s400_v1/Makefile b/board/amlogic/axg_s400_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/axg_s400_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/axg_s400_v1/aml-user-key.sig b/board/amlogic/axg_s400_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/axg_s400_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/axg_s400_v1/axg_s400_v1.c b/board/amlogic/axg_s400_v1/axg_s400_v1.c
new file mode 100755
index 0000000..d7fe13b
--- /dev/null
+++ b/board/amlogic/axg_s400_v1/axg_s400_v1.c
@@ -0,0 +1,715 @@
+
+/*
+ * board/amlogic/axg_s400_v1/axg_s400_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/secure_apb.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm/arch/clock.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/board_id.h>
+#ifdef CONFIG_SYS_I2C_AML_IS31F123XX
+#include <amlogic/aml_is31fl32xx.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+#ifdef CONFIG_CMD_NET
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+ writel(0x11111111, P_PERIPHS_PIN_MUX_8);
+ writel(0x111111, P_PERIPHS_PIN_MUX_9);
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+ /* hardware reset ethernet phy : gpioY15 connect phyreset pin*/
+ udelay(1000);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 15);
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+#endif
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ /*axg skt using GPIOX_6 as CD, no debug board anymore*/
+ clrbits_le32(P_PERIPHS_PIN_MUX_4, 0xF000000);
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 6);
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 6) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ #if 0 /* no default card on board. */
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ #endif
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_AML
+struct aml_i2c_platform g_aml_i2c_plat = {
+};
+/* multi i2c bus */
+struct aml_i2c_platform g_aml_i2c_ports[] = {
+ {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = CONFIG_SYS_I2C_SPEED,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_10_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_10_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_11_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_11_BIT,
+ }
+ },
+ {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_B,
+ .use_pio = 0,
+ .master_i2c_speed = CONFIG_SYS_I2C_SPEED,
+ .master_b_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOZ_8_REG,
+ .scl_bit = MESON_I2C_MASTER_B_GPIOZ_8_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOZ_9_REG,
+ .sda_bit = MESON_I2C_MASTER_B_GPIOZ_9_BIT,
+ }
+ },
+ /* sign of end */
+ {.master_i2c_speed=0},
+};
+
+static void board_i2c_init(void)
+{
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ extern void aml_i2c_set_ports(struct aml_i2c_platform *i2c_plat);
+ aml_i2c_set_ports(g_aml_i2c_ports);
+
+ udelay(10);
+}
+
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ if (is_power_on) {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<5));
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<21));
+ } else {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<5));
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<21));
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_PCIE
+#include <asm/arch-axg/pci.h>
+
+static void pcie_init_reset_pin(void)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_AML_PCIEA_GPIO_RESET,
+ CONFIG_AML_PCIEA_GPIO_RESET_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n", CONFIG_AML_PCIEA_GPIO_RESET);
+ return;
+ }
+ gpio_direction_output(CONFIG_AML_PCIEA_GPIO_RESET, 0);
+
+ ret = gpio_request(CONFIG_AML_PCIEB_GPIO_RESET,
+ CONFIG_AML_PCIEB_GPIO_RESET_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n", CONFIG_AML_PCIEB_GPIO_RESET);
+ return;
+ }
+ gpio_direction_output(CONFIG_AML_PCIEB_GPIO_RESET, 0);
+}
+
+void amlogic_pcie_init_reset_pin(int pcie_dev)
+{
+ int ret;
+
+ if (pcie_dev == 0) {
+ mdelay(5);
+ ret = gpio_request(CONFIG_AML_PCIEA_GPIO_RESET,
+ CONFIG_AML_PCIEA_GPIO_RESET_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_AML_PCIEA_GPIO_RESET);
+ return;
+ }
+ gpio_direction_output(CONFIG_AML_PCIEA_GPIO_RESET, 1);
+ } else {
+ mdelay(5);
+ ret = gpio_request(CONFIG_AML_PCIEB_GPIO_RESET,
+ CONFIG_AML_PCIEB_GPIO_RESET_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_AML_PCIEB_GPIO_RESET);
+ return;
+ }
+ gpio_direction_input(CONFIG_AML_PCIEB_GPIO_RESET);
+ }
+}
+
+void amlogic_pcie_disable(void)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_AML_PCIEA_GPIO_RESET,
+ CONFIG_AML_PCIEA_GPIO_RESET_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_AML_PCIEA_GPIO_RESET);
+ return;
+ }
+ gpio_direction_output(CONFIG_AML_PCIEA_GPIO_RESET, 0);
+
+ ret = gpio_request(CONFIG_AML_PCIEB_GPIO_RESET,
+ CONFIG_AML_PCIEB_GPIO_RESET_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_AML_PCIEB_GPIO_RESET);
+ return;
+ }
+ gpio_direction_output(CONFIG_AML_PCIEB_GPIO_RESET, 0);
+}
+#endif
+
+#ifdef CONFIG_AML_WIFI_EN_INIT
+static void wifi_init_enable_pin(void)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_AML_GPIO_WIFI_EN_1,
+ CONFIG_AML_GPIO_WIFI_EN_1_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n", CONFIG_AML_GPIO_WIFI_EN_1);
+ return;
+ }
+ gpio_direction_output(CONFIG_AML_GPIO_WIFI_EN_1, 1);
+
+ ret = gpio_request(CONFIG_AML_GPIO_WIFI_EN_2,
+ CONFIG_AML_GPIO_WIFI_EN_2_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n", CONFIG_AML_GPIO_WIFI_EN_2);
+ return;
+ }
+ gpio_direction_output(CONFIG_AML_GPIO_WIFI_EN_2, 1);
+}
+#endif
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "misc",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+#ifdef CONFIG_AB_SYSTEM
+ {
+ .name = "boot_a",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "boot_b",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system_a",
+ .offset = 0,
+ .size = 150*SZ_1M,
+ },
+ {
+ .name = "system_b",
+ .offset = 0,
+ .size = 150*SZ_1M,
+ },
+ #else
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 280*SZ_1M,
+ },
+#endif
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+void power_save_pre(void)
+{
+ /*Close MIPI clock*/
+ clrbits_le32(P_HHI_MIPI_CNTL0, 0xffffffff);
+ clrbits_le32(P_HHI_MIPI_CNTL1, 0xffffffff);
+ clrbits_le32(P_HHI_MIPI_CNTL2, 0xffdfffff);
+}
+int board_init(void)
+{
+#ifdef CONFIG_AML_PCIE
+ pcie_init_reset_pin();
+#endif
+
+#ifdef CONFIG_AML_WIFI_EN_INIT
+ wifi_init_enable_pin();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+#ifdef CONFIG_SYS_I2C_AML
+ board_i2c_init();
+#endif
+#ifdef CONFIG_SYS_I2C_AML_IS31F123XX
+ board_is31fl32xx_init();
+ board_is31fl32xx_light_on();
+#endif
+ if (get_cpu_id().package_id == MESON_CPU_PACKAGE_ID_A113X)
+ power_save_pre();
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ //run_command("keyunify init 0x1234", 0);
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ //vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int b_id = 0;
+ char loc_name[64] = {0};
+
+ b_id = get_board_id();
+
+ printf("%s board adc:%d\n", __func__, b_id);
+
+ switch (b_id) {
+ case 0:
+ case 1:
+ case 2:
+ strcpy(loc_name, "axg_s400_1g\0");
+ break;
+ case 3:
+ strcpy(loc_name, "axg_s400_v03\0");
+ break;
+ default:
+ strcpy(loc_name, "axg_s400_1g");
+ break;
+ }
+ if (name != NULL)
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/axg_s400_v1/eth_setup.c b/board/amlogic/axg_s400_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/axg_s400_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/axg_s400_v1/firmware/board_init.c b/board/amlogic/axg_s400_v1/firmware/board_init.c
new file mode 100644
index 0000000..8e72364
--- /dev/null
+++ b/board/amlogic/axg_s400_v1/firmware/board_init.c
@@ -0,0 +1,49 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+
+#define PNL_PREG_PAD_GPIO3_EN_N 0x15
+#define PNL_PREG_PAD_GPIO3_O 0x16
+#define PNL_PREG_PAD_GPIO3_I 0x17
+
+#define PNL_REG_BASE (0xff634400L)
+#define PNL_REG(reg) (PNL_REG_BASE + (reg << 2))
+#define PNL_REG_R(_reg) (*(volatile unsigned int *)PNL_REG(_reg))
+#define PNL_REG_W(_reg, _value) *(volatile unsigned int *)PNL_REG(_reg) = (_value);
+static void panel_power_init(void)
+{
+ serial_puts("init panel power\n");
+ /* GPIOZ_4/5/6 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_O) & ~((1 << 4) | (1 << 5) | (1 << 6))));
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_EN_N) & ~((1 << 4) | (1 << 5) | (1 << 6))));
+}
+
+void board_init(void)
+{
+ power_init(0);
+
+ panel_power_init();
+}
\ No newline at end of file
diff --git a/board/amlogic/axg_s400_v1/firmware/power.c b/board/amlogic/axg_s400_v1/firmware/power.c
new file mode 100644
index 0000000..c032e9e
--- /dev/null
+++ b/board/amlogic/axg_s400_v1/firmware/power.c
@@ -0,0 +1,207 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+enum pwm_id {
+ pwm_ao_b=0,
+ pwm_ao_d,
+};
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ */
+
+ switch (id) {
+ case pwm_ao_d:
+ reg = readl(AO_PWM_MISC_REG_CD);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_CD);
+ /*
+ * default set to max voltage
+ */
+ reg = readl(AO_RTI_PINMUX_REG1);
+ reg &= ~(0xf << 4);
+ writel(reg | (0x3 << 4), AO_RTI_PINMUX_REG1);
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ reg = readl(AO_RTI_PINMUX_REG0);
+ reg &= ~(0xf << 8);
+ writel(reg | (0x3 << 8), AO_RTI_PINMUX_REG0);
+ break;
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ switch (id) {
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ writel(pwm_voltage_table[to][0],AO_PWM_PWM_B);
+ break;
+ case pwm_ao_d:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_D);
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void gpio_set_vcc5v_power(char is_power_on)
+{
+ if (is_power_on) {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<13));
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<29));
+ } else {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<13));
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<29));
+ }
+}
+
+static void gpio_set_vcc3_3_power(char is_power_on)
+{
+ if (is_power_on) {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<12));
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<28));
+ } else {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<12));
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<28));
+ }
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_d, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_ao_b);
+ pwm_init(pwm_ao_d);
+ gpio_set_vcc5v_power(1);
+ gpio_set_vcc3_3_power(1);
+}
diff --git a/board/amlogic/axg_s400_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/axg_s400_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..5d52f34
--- /dev/null
+++ b/board/amlogic/axg_s400_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,141 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860),
+ DVFS( 250000000, 860+CHIP_ADJUST),
+ DVFS( 500000000, 860+RIPPLE_ADJUST),
+ DVFS( 667000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+void pwm_init(void)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ */
+
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ reg = readl(AO_RTI_PINMUX_REG0);
+ reg &= ~(0xf << 8);
+ writel(reg | (0x3 << 8), AO_RTI_PINMUX_REG0);
+
+ _udelay(200);
+}
+
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = readl(AO_PWM_PWM_B);
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init();
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ writel(pwm_voltage_table[cur][0], AO_PWM_PWM_B);
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/axg_s400_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/axg_s400_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..6d4109e
--- /dev/null
+++ b/board/amlogic/axg_s400_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,39 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#endif //__PWM_CTRL_H__
\ No newline at end of file
diff --git a/board/amlogic/axg_s400_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/axg_s400_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..7eb45fa
--- /dev/null
+++ b/board/amlogic/axg_s400_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,373 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#if 0
+
+#define ON 1
+#define OFF 0
+
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+
+#endif
+
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_D);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ /*set gpioao_13 low to power off vcc 5v*/
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 13)) & (~(1 << 29)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PINMUX_REG1) & (~(0xf << 20)), AO_RTI_PINMUX_REG1);
+
+ /*set gpioao_12 high to power off vcc 3.3v*/
+ writel((readl(AO_GPIO_O_EN_N) & (~(1 << 12))) | (1 << 28), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PINMUX_REG1) & (~(0xf << 16)), AO_RTI_PINMUX_REG1);
+
+ /*power off VDDCPU*/
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+
+ /*step down ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+
+/*
+ uart_puts("81gate = 0x");
+ uart_put_hex(readl(0xff63c140),32);
+ uart_puts("\n");
+ uart_puts("81gate = 0x");
+ uart_put_hex(readl(0xff63c144),32);
+ uart_puts("\n");
+ uart_puts("81gate = 0x");
+ uart_put_hex(readl(0xff63c148),32);
+ uart_puts("\n");
+
+ writel(0,0xff63c000);
+ writel(0,0xff63c004);
+ writel(0,0xff63c008);
+
+ uart_puts("mipi = 0x");
+ uart_put_hex(readl(0xff63c000),32);
+ uart_puts("\n");
+ uart_put_hex(readl(0xff63c004),32);
+ uart_puts("\n");
+ uart_put_hex(readl(0xff63c008),32);
+ uart_puts("\n");
+
+ uart_puts("PCIE_CML = 0x");
+ uart_put_hex(readl(0xff63c0f0),32);
+ uart_puts("\n");
+
+ uart_puts("PCIE_PLL = 0x");
+ uart_put_hex(readl(0xff63c0d8),32);
+ uart_puts("\n");
+
+ uart_puts("AO_SAR_CLK = 0x");
+ uart_put_hex(readl(0xFF800090),32);
+ uart_puts("\n");
+
+ uart_puts("GP0_PLL = 0x");
+ uart_put_hex(readl(HHI_GP0_PLL_CNTL),32);
+ uart_puts("\n");
+ uart_puts("MPLL = 0x");
+ uart_put_hex(readl(HHI_MPLL_CNTL),32);
+ uart_puts("\n");
+ uart_puts("HIFI_PLL = 0x");
+ uart_put_hex(readl(HHI_HIFI_PLL_CNTL),32);
+ uart_puts("\n");
+ writel(0,HHI_HIFI_PLL_CNTL2);
+ writel(0,HHI_HIFI_PLL_CNTL);
+
+ uart_puts("HHI_PLL6 = 0x");
+ uart_put_hex(readl(HHI_MPLL_CNTL6),32);
+ uart_puts("\n");
+
+ uart_puts("SYS_PLL = 0x");
+ uart_put_hex(readl(HHI_SYS_PLL_CNTL),32);
+ uart_puts("\n");
+
+ writel(0,0xff637000);
+ writel(0,0xff637004);
+ writel(0,0xff637008);
+ writel(0,0xff63700c);
+ writel(0,0xff637010);
+ writel(0,0xff637014);
+ writel(0,0xff637018);
+
+ writel(0, HHI_MPLL_CNTL);
+ writel(0, HHI_MPLL_CNTL2);
+ writel(0, HHI_MPLL_CNTL3);
+ writel(0, HHI_MPLL_CNTL4);
+ writel(0, HHI_MPLL_CNTL5);
+ writel(0, HHI_MPLL_CNTL6);
+ writel(0, HHI_MPLL_CNTL7);
+ writel(0, HHI_MPLL_CNTL8);
+ writel(0, HHI_MPLL_CNTL9);
+ writel(0, HHI_MPLL_CNTL10);
+ writel(0, HHI_MPLL3_CNTL0);
+ writel(0, HHI_MPLL3_CNTL1);
+
+ writel(0, HHI_SYS_PLL_CNTL);
+ writel(0, HHI_SYS_PLL_CNTL1);
+ writel(0, HHI_SYS_PLL_CNTL2);
+ writel(0, HHI_SYS_PLL_CNTL3);
+ writel(0, HHI_SYS_PLL_CNTL4);
+ writel(0, HHI_SYS_PLL_CNTL5);
+
+ writel(0x088800e1,0xff63c140);
+ writel(0xe0800000,0xff63c144);
+ writel(0x44000006,0xff63c148);
+*/
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ /*step up ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+ /*power on VDDCPU*/
+ writel(readl(AO_GPIO_O_EN_N) | (1 << 31), AO_GPIO_O_EN_N);
+ _udelay(100);
+
+ /*set gpioao_12 low to power om vcc 3.3v*/
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 12)) & (~(1 << 28)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PINMUX_REG1) & (~(0xf << 16)), AO_RTI_PINMUX_REG1);
+ _udelay(200);
+
+ /*set gpioao_13 high to power on vcc 5v*/
+ writel((readl(AO_GPIO_O_EN_N) & (~(1 << 13))) | (1 << 29), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PINMUX_REG1) & (~(0xf << 20)), AO_RTI_PINMUX_REG1);
+ _udelay(10000);
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC | ETH_PHY_GPIO_SRC | WIFI_WAKEUP_SRC);
+
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+
+#ifdef CONFIG_BT_WAKEUP
+ gpio = &(p->gpio_info[0]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_22;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ /*WIFI Wakeup: IN: GPIOX[7], OUT: GPIOX[6]*/
+ gpio = &(p->gpio_info[1]);
+ gpio->wakeup_id = WIFI_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_6;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO1_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+#endif
+ p->sources = val;
+}
+/*
+static unsigned int mpeg_clk;
+void clk81_switch_to_24M(int flag)//for 1M
+{
+ unsigned int val;
+ if (flag) {
+ //val = readl(HHI_MPEG_CLK_CNTL);
+ //val = val | (0x1 << 8);
+ uart_puts("val3 = 0x");
+ uart_put_hex(mpeg_clk,32);
+ uart_puts("ddddd\n");
+ writel(mpeg_clk, HHI_MPEG_CLK_CNTL);
+ uart_puts("val4 = 0x");
+ uart_put_hex(readl(HHI_MPEG_CLK_CNTL),32);
+ _udelay(100);
+ uart_puts("val5 = 0x");
+ } else{
+ val = readl(HHI_MPEG_CLK_CNTL);
+ mpeg_clk = val;
+ uart_puts("val = 0x");
+ uart_put_hex(val,32);
+ // val = (val & (~(1<<9)) & (~(0x7<<12)) & (~(1<<31)) & (~(0x7f<<0))) | (3<<7) | (0x0<<0);//1M
+ val = (val & (~((1<<9) | (0x7<<12) | (1<<31) | (0x7f<<0)))) | (3<<7) | (0x17<<0);//12M
+ uart_puts("val2 = 0x");
+ uart_put_hex(val,32);
+ // val = val & (~(0x3<<8)) ;
+ writel(val, HHI_MPEG_CLK_CNTL);
+ // writel(readl(HHI_MPEG_CLK_CNTL) | (1<<8), HHI_MPEG_CLK_CNTL);
+ _udelay(100);
+ }
+}
+*/
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ unsigned char adc_key_cnt = 0;
+
+ init_remote();
+ saradc_enable();
+
+ do {
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+
+ if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
+ irq[IRQ_VRTC] = 0xFFFFFFFF;
+ exit_reason = RTC_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+
+#ifdef CONFIG_BT_WAKEUP
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 21))
+ && (readl(PREG_PAD_GPIO2_O) & (0x01 << 21))
+ && !(readl(PREG_PAD_GPIO2_I) & (0x01 << 22)))
+ exit_reason = BT_WAKEUP;
+ }
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
+ irq[IRQ_GPIO1] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 7))
+ && (readl(PREG_PAD_GPIO2_O) & (0x01 << 7))
+ && !(readl(PREG_PAD_GPIO2_I) & (0x01 << 6)))
+ exit_reason = WIFI_WAKEUP;
+ }
+#endif
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/axg_s400_v1/firmware/timing.c b/board/amlogic/axg_s400_v1/firmware/timing.c
new file mode 100644
index 0000000..e0f7775
--- /dev/null
+++ b/board/amlogic/axg_s400_v1/firmware/timing.c
@@ -0,0 +1,569 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 20
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_60OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x59959, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0x10,
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/axg_s400_v1/lcd.c b/board/amlogic/axg_s400_v1/lcd.c
new file mode 100755
index 0000000..dbe0f47
--- /dev/null
+++ b/board/amlogic/axg_s400_v1/lcd.c
@@ -0,0 +1,465 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_6",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_dft[] = {
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_dft[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+#if 0 /* reset in init_cmd */
+ {LCD_POWER_TYPE_CPU, 0,1,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,100,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_4",
+ "GPIOZ_5",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,
+ /* custome */
+ Rsv_val,Rsv_val,Rsv_val,
+ /* MIPI_attr: lane_num, bit_rate_max, factor, operation_mode_init, operation_mode_display, video_mode_type, clk_always_hs, phy_switch */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_dft, lcd_power_off_step_dft,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_A,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_A,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,3,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_A,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOZ_5
+ .pinmux_set = {{2, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x00d00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xff, 20,
+ 0x05, 1, 0x29,
+ 0xff, 20,
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xff, 10,
+ 0x05, 1, 0x10,
+ 0xff, 10,
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xff, 100, /* delay */
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0xff, //ending flag
+};
+
+static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff,0xff, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 4,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .cmd_size = 9,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 1,
+ .name = "mipi_KD080D13",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 2,
+ .name = "mipi_TV070WSM",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 3,
+ .name = "mipi_P070ACB",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{2, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x00d00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "none",
+ .type = BL_EXTERN_MAX,
+ .i2c_addr = 0xff,
+ .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+ .dim_min = 10,
+ .dim_max = 255,
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/axg_s420_v1/Kconfig b/board/amlogic/axg_s420_v1/Kconfig
new file mode 100644
index 0000000..95c3548
--- /dev/null
+++ b/board/amlogic/axg_s420_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_AXG
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "axg_s420_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "axg"
+
+config SYS_CONFIG_NAME
+ default "axg_s420_v1"
+
+endif
diff --git a/board/amlogic/axg_s420_v1/Makefile b/board/amlogic/axg_s420_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/axg_s420_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/axg_s420_v1/README b/board/amlogic/axg_s420_v1/README
new file mode 100644
index 0000000..cb4a921
--- /dev/null
+++ b/board/amlogic/axg_s420_v1/README
@@ -0,0 +1 @@
+s420 config use independent files now.
diff --git a/board/amlogic/axg_s420_v1/aml-user-key.sig b/board/amlogic/axg_s420_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/axg_s420_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/axg_s420_v1/axg_s420_v1.c b/board/amlogic/axg_s420_v1/axg_s420_v1.c
new file mode 100755
index 0000000..e0ef370
--- /dev/null
+++ b/board/amlogic/axg_s420_v1/axg_s420_v1.c
@@ -0,0 +1,634 @@
+
+/*
+ * board/amlogic/axg_s400_v1/axg_s400_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/secure_apb.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/board_id.h>
+#ifdef CONFIG_SYS_I2C_AML_IS31F123XX
+#include <amlogic/aml_is31fl32xx.h>
+#endif
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+#ifdef CONFIG_CMD_NET
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+ writel(0x11111111, P_PERIPHS_PIN_MUX_8);
+ writel(0x111111, P_PERIPHS_PIN_MUX_9);
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+ /* hardware reset ethernet phy : gpioY15 connect phyreset pin*/
+ udelay(1000);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 15);
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+#endif
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ /*axg skt using GPIOX_6 as CD, no debug board anymore*/
+ clrbits_le32(P_PERIPHS_PIN_MUX_4, 0xF000000);
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 6);
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 6) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ #if 0 /* no default card on board. */
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ #endif
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_AML
+struct aml_i2c_platform g_aml_i2c_plat = {
+};
+/* multi i2c bus */
+struct aml_i2c_platform g_aml_i2c_ports[] = {
+ {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = CONFIG_SYS_I2C_SPEED,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_10_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_10_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_11_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_11_BIT,
+ }
+ },
+};
+
+
+static void board_i2c_init(void)
+{
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ //aml_i2c_init();
+ extern void aml_i2c_set_ports(struct aml_i2c_platform *i2c_plat);
+ aml_i2c_set_ports(g_aml_i2c_ports);
+
+ udelay(10);
+}
+
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ if (is_power_on) {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<5));
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<21));
+ } else {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<5));
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<21));
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+#ifdef CONFIG_ENV_IS_IN_NAND
+ {
+ .name = "environment",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+#endif
+ {
+ .name = "misc",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+#ifdef CONFIG_AB_SYSTEM
+ {
+ .name = "boot_a",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "boot_b",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system_a",
+ .offset = 0,
+ .size = 150*SZ_1M,
+ },
+ {
+ .name = "system_b",
+ .offset = 0,
+ .size = 150*SZ_1M,
+ },
+ #else
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 280*SZ_1M,
+ },
+#endif
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+void power_save_pre(void)
+{
+ /*Close MIPI clock*/
+ clrbits_le32(P_HHI_MIPI_CNTL0, 0xffffffff);
+ clrbits_le32(P_HHI_MIPI_CNTL1, 0xffffffff);
+ clrbits_le32(P_HHI_MIPI_CNTL2, 0xffdfffff);
+}
+
+#if 0
+static int led_extern_change_i2c_bus(unsigned aml_i2c_bus)
+{
+ int ret = 0;
+ extern struct aml_i2c_platform g_aml_i2c_plat;
+
+ g_aml_i2c_plat.master_no = aml_i2c_bus;
+ ret = aml_i2c_init();
+
+ return ret;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+
+#ifdef CONFIG_SYS_I2C_AML
+ board_i2c_init();
+ //led_extern_change_i2c_bus(g_aml_i2c_ports[0].master_no);
+#endif
+#ifdef CONFIG_SYS_I2C_AML_IS31F123XX
+ board_is31fl32xx_init();
+ board_is31fl32xx_light_on();
+#endif
+ if (get_cpu_id().package_id == MESON_CPU_PACKAGE_ID_A113X)
+ power_save_pre();
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ //run_command("keyunify init 0x1234", 0);
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ //vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int ddr_size = 0;
+ unsigned int b_id = 0;
+ char loc_name[64] = {0};
+ int i;
+
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+ printf("debug ddr size: 0x%x\n", ddr_size);
+
+ b_id = get_board_id();
+
+ printf("%s board adc:%d\n", __func__, b_id);
+
+ switch (b_id) {
+ case 0:
+ case 1:
+ case 2:
+ strcpy(loc_name, "axg_s420_512m\0");
+ break;
+ case 3:
+ strcpy(loc_name, "axg_s420_v03\0");
+ break;
+ default:
+ //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "axg_s420_v03");
+ break;
+ }
+
+ switch (ddr_size) {
+ case 0x8000000:
+ strcpy(loc_name, "axg_s420_128m\0");
+ break;
+ default:
+ printf("dts ,it's up to board id\n");
+ break;
+ }
+
+ if (name != NULL)
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/axg_s420_v1/eth_setup.c b/board/amlogic/axg_s420_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/axg_s420_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/axg_s420_v1/firmware/board_init.c b/board/amlogic/axg_s420_v1/firmware/board_init.c
new file mode 100644
index 0000000..2771433
--- /dev/null
+++ b/board/amlogic/axg_s420_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/axg_s420_v1/firmware/power.c b/board/amlogic/axg_s420_v1/firmware/power.c
new file mode 100644
index 0000000..c032e9e
--- /dev/null
+++ b/board/amlogic/axg_s420_v1/firmware/power.c
@@ -0,0 +1,207 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+enum pwm_id {
+ pwm_ao_b=0,
+ pwm_ao_d,
+};
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ */
+
+ switch (id) {
+ case pwm_ao_d:
+ reg = readl(AO_PWM_MISC_REG_CD);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_CD);
+ /*
+ * default set to max voltage
+ */
+ reg = readl(AO_RTI_PINMUX_REG1);
+ reg &= ~(0xf << 4);
+ writel(reg | (0x3 << 4), AO_RTI_PINMUX_REG1);
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ reg = readl(AO_RTI_PINMUX_REG0);
+ reg &= ~(0xf << 8);
+ writel(reg | (0x3 << 8), AO_RTI_PINMUX_REG0);
+ break;
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ switch (id) {
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ writel(pwm_voltage_table[to][0],AO_PWM_PWM_B);
+ break;
+ case pwm_ao_d:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_D);
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void gpio_set_vcc5v_power(char is_power_on)
+{
+ if (is_power_on) {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<13));
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<29));
+ } else {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<13));
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<29));
+ }
+}
+
+static void gpio_set_vcc3_3_power(char is_power_on)
+{
+ if (is_power_on) {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<12));
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<28));
+ } else {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<12));
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<28));
+ }
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_d, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_ao_b);
+ pwm_init(pwm_ao_d);
+ gpio_set_vcc5v_power(1);
+ gpio_set_vcc3_3_power(1);
+}
diff --git a/board/amlogic/axg_s420_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/axg_s420_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..5d52f34
--- /dev/null
+++ b/board/amlogic/axg_s420_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,141 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860),
+ DVFS( 250000000, 860+CHIP_ADJUST),
+ DVFS( 500000000, 860+RIPPLE_ADJUST),
+ DVFS( 667000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+void pwm_init(void)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ */
+
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ reg = readl(AO_RTI_PINMUX_REG0);
+ reg &= ~(0xf << 8);
+ writel(reg | (0x3 << 8), AO_RTI_PINMUX_REG0);
+
+ _udelay(200);
+}
+
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = readl(AO_PWM_PWM_B);
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init();
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ writel(pwm_voltage_table[cur][0], AO_PWM_PWM_B);
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/axg_s420_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/axg_s420_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..6d4109e
--- /dev/null
+++ b/board/amlogic/axg_s420_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,39 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#endif //__PWM_CTRL_H__
\ No newline at end of file
diff --git a/board/amlogic/axg_s420_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/axg_s420_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..3f2bb97
--- /dev/null
+++ b/board/amlogic/axg_s420_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,368 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#if 0
+
+#define ON 1
+#define OFF 0
+
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+
+#endif
+
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_D);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ /*set gpioao_13 low to power off vcc 5v*/
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 13)) & (~(1 << 29)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PINMUX_REG1) & (~(0xf << 20)), AO_RTI_PINMUX_REG1);
+
+ /*set gpioao_12 high to power off vcc 3.3v*/
+ writel((readl(AO_GPIO_O_EN_N) & (~(1 << 12))) | (1 << 28), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PINMUX_REG1) & (~(0xf << 16)), AO_RTI_PINMUX_REG1);
+
+ /*power off VDDCPU*/
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+
+ /*step down ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+
+/*
+ uart_puts("81gate = 0x");
+ uart_put_hex(readl(0xff63c140),32);
+ uart_puts("\n");
+ uart_puts("81gate = 0x");
+ uart_put_hex(readl(0xff63c144),32);
+ uart_puts("\n");
+ uart_puts("81gate = 0x");
+ uart_put_hex(readl(0xff63c148),32);
+ uart_puts("\n");
+
+ writel(0,0xff63c000);
+ writel(0,0xff63c004);
+ writel(0,0xff63c008);
+
+ uart_puts("mipi = 0x");
+ uart_put_hex(readl(0xff63c000),32);
+ uart_puts("\n");
+ uart_put_hex(readl(0xff63c004),32);
+ uart_puts("\n");
+ uart_put_hex(readl(0xff63c008),32);
+ uart_puts("\n");
+
+ uart_puts("PCIE_CML = 0x");
+ uart_put_hex(readl(0xff63c0f0),32);
+ uart_puts("\n");
+
+ uart_puts("PCIE_PLL = 0x");
+ uart_put_hex(readl(0xff63c0d8),32);
+ uart_puts("\n");
+
+ uart_puts("AO_SAR_CLK = 0x");
+ uart_put_hex(readl(0xFF800090),32);
+ uart_puts("\n");
+
+ uart_puts("GP0_PLL = 0x");
+ uart_put_hex(readl(HHI_GP0_PLL_CNTL),32);
+ uart_puts("\n");
+ uart_puts("MPLL = 0x");
+ uart_put_hex(readl(HHI_MPLL_CNTL),32);
+ uart_puts("\n");
+ uart_puts("HIFI_PLL = 0x");
+ uart_put_hex(readl(HHI_HIFI_PLL_CNTL),32);
+ uart_puts("\n");
+ writel(0,HHI_HIFI_PLL_CNTL2);
+ writel(0,HHI_HIFI_PLL_CNTL);
+
+ uart_puts("HHI_PLL6 = 0x");
+ uart_put_hex(readl(HHI_MPLL_CNTL6),32);
+ uart_puts("\n");
+
+ uart_puts("SYS_PLL = 0x");
+ uart_put_hex(readl(HHI_SYS_PLL_CNTL),32);
+ uart_puts("\n");
+
+ writel(0,0xff637000);
+ writel(0,0xff637004);
+ writel(0,0xff637008);
+ writel(0,0xff63700c);
+ writel(0,0xff637010);
+ writel(0,0xff637014);
+ writel(0,0xff637018);
+
+ writel(0, HHI_MPLL_CNTL);
+ writel(0, HHI_MPLL_CNTL2);
+ writel(0, HHI_MPLL_CNTL3);
+ writel(0, HHI_MPLL_CNTL4);
+ writel(0, HHI_MPLL_CNTL5);
+ writel(0, HHI_MPLL_CNTL6);
+ writel(0, HHI_MPLL_CNTL7);
+ writel(0, HHI_MPLL_CNTL8);
+ writel(0, HHI_MPLL_CNTL9);
+ writel(0, HHI_MPLL_CNTL10);
+ writel(0, HHI_MPLL3_CNTL0);
+ writel(0, HHI_MPLL3_CNTL1);
+
+ writel(0, HHI_SYS_PLL_CNTL);
+ writel(0, HHI_SYS_PLL_CNTL1);
+ writel(0, HHI_SYS_PLL_CNTL2);
+ writel(0, HHI_SYS_PLL_CNTL3);
+ writel(0, HHI_SYS_PLL_CNTL4);
+ writel(0, HHI_SYS_PLL_CNTL5);
+
+ writel(0x088800e1,0xff63c140);
+ writel(0xe0800000,0xff63c144);
+ writel(0x44000006,0xff63c148);
+*/
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ /*step up ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+ /*power on VDDCPU*/
+ writel(readl(AO_GPIO_O_EN_N) | (1 << 31), AO_GPIO_O_EN_N);
+ _udelay(100);
+
+ /*set gpioao_12 low to power om vcc 3.3v*/
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 12)) & (~(1 << 28)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PINMUX_REG1) & (~(0xf << 16)), AO_RTI_PINMUX_REG1);
+ _udelay(200);
+
+ /*set gpioao_13 high to power on vcc 5v*/
+ writel((readl(AO_GPIO_O_EN_N) & (~(1 << 13))) | (1 << 29), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PINMUX_REG1) & (~(0xf << 20)), AO_RTI_PINMUX_REG1);
+ _udelay(10000);
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC | WIFI_WAKEUP_SRC);
+
+#ifdef CONFIG_BT_WAKEUP
+ gpio = &(p->gpio_info[0]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_22;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ /*WIFI Wakeup: IN: GPIOX[7], OUT: GPIOX[6]*/
+ gpio = &(p->gpio_info[1]);
+ gpio->wakeup_id = WIFI_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_6;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO1_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+#endif
+ p->sources = val;
+}
+/*
+static unsigned int mpeg_clk;
+void clk81_switch_to_24M(int flag)//for 1M
+{
+ unsigned int val;
+ if (flag) {
+ //val = readl(HHI_MPEG_CLK_CNTL);
+ //val = val | (0x1 << 8);
+ uart_puts("val3 = 0x");
+ uart_put_hex(mpeg_clk,32);
+ uart_puts("ddddd\n");
+ writel(mpeg_clk, HHI_MPEG_CLK_CNTL);
+ uart_puts("val4 = 0x");
+ uart_put_hex(readl(HHI_MPEG_CLK_CNTL),32);
+ _udelay(100);
+ uart_puts("val5 = 0x");
+ } else{
+ val = readl(HHI_MPEG_CLK_CNTL);
+ mpeg_clk = val;
+ uart_puts("val = 0x");
+ uart_put_hex(val,32);
+ // val = (val & (~(1<<9)) & (~(0x7<<12)) & (~(1<<31)) & (~(0x7f<<0))) | (3<<7) | (0x0<<0);//1M
+ val = (val & (~((1<<9) | (0x7<<12) | (1<<31) | (0x7f<<0)))) | (3<<7) | (0x17<<0);//12M
+ uart_puts("val2 = 0x");
+ uart_put_hex(val,32);
+ // val = val & (~(0x3<<8)) ;
+ writel(val, HHI_MPEG_CLK_CNTL);
+ // writel(readl(HHI_MPEG_CLK_CNTL) | (1<<8), HHI_MPEG_CLK_CNTL);
+ _udelay(100);
+ }
+}
+*/
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ unsigned char adc_key_cnt = 0;
+
+ init_remote();
+ saradc_enable();
+
+ do {
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+
+ if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
+ irq[IRQ_VRTC] = 0xFFFFFFFF;
+ exit_reason = RTC_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+
+#ifdef CONFIG_BT_WAKEUP
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 21))
+ && (readl(PREG_PAD_GPIO2_O) & (0x01 << 21))
+ && !(readl(PREG_PAD_GPIO2_I) & (0x01 << 22)))
+ exit_reason = BT_WAKEUP;
+ }
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
+ irq[IRQ_GPIO1] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 7))
+ && (readl(PREG_PAD_GPIO2_O) & (0x01 << 7))
+ && !(readl(PREG_PAD_GPIO2_I) & (0x01 << 6)))
+ exit_reason = WIFI_WAKEUP;
+ }
+#endif
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/axg_s420_v1/firmware/timing.c b/board/amlogic/axg_s420_v1/firmware/timing.c
new file mode 100644
index 0000000..e0f7775
--- /dev/null
+++ b/board/amlogic/axg_s420_v1/firmware/timing.c
@@ -0,0 +1,569 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 20
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_60OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x59959, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0x10,
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/axg_s420_v1/lcd.c b/board/amlogic/axg_s420_v1/lcd.c
new file mode 100755
index 0000000..75b8268
--- /dev/null
+++ b/board/amlogic/axg_s420_v1/lcd.c
@@ -0,0 +1,468 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+
+
+
+//Rsv_val = 0xffffffff
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_6",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_dft[] = {
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_dft[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+#if 0 /* reset in init_cmd */
+ {LCD_POWER_TYPE_CPU, 0,1,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,100,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_4",
+ "GPIOZ_5",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,
+ /* custome */
+ Rsv_val,Rsv_val,Rsv_val,
+ /* MIPI_attr: lane_num, bit_rate_max, factor, operation_mode_init, operation_mode_display, video_mode_type, clk_always_hs, phy_stop_wait */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_dft, lcd_power_off_step_dft,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_A,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_A,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,3,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_A,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOZ_5
+ .pinmux_set = {{2, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x00d00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xff, 20,
+ 0x05, 1, 0x29,
+ 0xff, 20,
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xff, 10,
+ 0x05, 1, 0x10,
+ 0xff, 10,
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xff, 100, /* delay */
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0xff, //ending flag
+};
+
+static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff,0xff, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 4,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .cmd_size = 9,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 1,
+ .name = "mipi_KD080D13",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 2,
+ .name = "mipi_TV070WSM",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 3,
+ .name = "mipi_P070ACB",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{2, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x00d00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "none",
+ .type = BL_EXTERN_MAX,
+ .i2c_addr = 0xff,
+ .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+ .dim_min = 10,
+ .dim_max = 255,
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/axg_skt_v1/Kconfig b/board/amlogic/axg_skt_v1/Kconfig
new file mode 100644
index 0000000..9532808
--- /dev/null
+++ b/board/amlogic/axg_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_AXG
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "axg_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "axg"
+
+config SYS_CONFIG_NAME
+ default "axg_skt_v1"
+
+endif
diff --git a/board/amlogic/axg_skt_v1/Makefile b/board/amlogic/axg_skt_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/axg_skt_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/axg_skt_v1/aml-user-key.sig b/board/amlogic/axg_skt_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/axg_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/axg_skt_v1/axg_skt_v1.c b/board/amlogic/axg_skt_v1/axg_skt_v1.c
new file mode 100644
index 0000000..6dfbcf5
--- /dev/null
+++ b/board/amlogic/axg_skt_v1/axg_skt_v1.c
@@ -0,0 +1,666 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/secure_apb.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm/arch/clock.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#ifdef CONFIG_AML_SPIFC
+#include <amlogic/spifc.h>
+#endif
+#ifdef CONFIG_AML_SPICC
+#include <amlogic/spicc.h>
+#endif
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+#ifdef CONFIG_CMD_NET
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+ writel(0x11111111, P_PERIPHS_PIN_MUX_8);
+ writel(0x111111, P_PERIPHS_PIN_MUX_9);
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+ /* hardware reset ethernet phy : gpioY15 connect phyreset pin*/
+ udelay(1000);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 15);
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+#endif
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ /*axg skt using GPIOX_6 as CD, no debug board anymore*/
+ clrbits_le32(P_PERIPHS_PIN_MUX_4, 0xF000000);
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 6);
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 6) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ setbits_le32(P_PAD_PULL_UP_REG2, 0x3F);
+ setbits_le32(P_PAD_PULL_UP_EN_REG2, 0x3F);
+ #if 0 /* no default card on board. */
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ #endif
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ if (is_power_on) {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<5));
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<21));
+ } else {
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<5));
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<21));
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_PCIE
+#include <asm/arch-axg/pci.h>
+
+static void pcie_init_reset_pin(void)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_AML_PCIEA_GPIO_RESET,
+ CONFIG_AML_PCIEA_GPIO_RESET_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n", CONFIG_AML_PCIEA_GPIO_RESET);
+ return;
+ }
+ gpio_direction_output(CONFIG_AML_PCIEA_GPIO_RESET, 0);
+}
+
+void amlogic_pcie_init_reset_pin(int pcie_dev)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_AML_PCIEA_GPIO_RESET,
+ CONFIG_AML_PCIEA_GPIO_RESET_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_AML_PCIEA_GPIO_RESET);
+ return;
+ }
+ gpio_direction_output(CONFIG_AML_PCIEA_GPIO_RESET, 1);
+}
+
+void amlogic_pcie_disable(void)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_AML_PCIEA_GPIO_RESET,
+ CONFIG_AML_PCIEA_GPIO_RESET_NAME);
+
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_AML_PCIEA_GPIO_RESET);
+ return;
+ }
+ gpio_direction_output(CONFIG_AML_PCIEA_GPIO_RESET, 0);
+}
+
+#endif
+
+
+#ifdef CONFIG_AML_WIFI_EN_INIT
+static void wifi_init_enable_pin(void)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_AML_GPIO_WIFI_EN,
+ CONFIG_AML_GPIO_WIFI_EN_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n", CONFIG_AML_GPIO_WIFI_EN);
+ return;
+ }
+ gpio_direction_output(CONFIG_AML_GPIO_WIFI_EN, 1);
+}
+#endif
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 220*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_9: NOR_WPn:reg1[7:4]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {PIN_BOOT_14};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xffff << 12);
+ if (enable)
+ val |= 0x3333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~((0xf << 4) | (0xf << 24));
+ if (enable)
+ val |= 0x3 << 4;
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xfb000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+#ifdef CONFIG_AML_SPICC
+/* generic config in arch gpio/clock.c */
+extern int spicc0_clk_enable(bool enable);
+extern int spicc0_pinctrl_enable(bool enable);
+
+static const struct spicc_platdata spicc0_platdata = {
+ .compatible = "amlogic,meson-axg-spicc",
+ .reg = (void __iomem *)0xffd13000,
+ .clk_rate = 166666666,
+ .clk_enable = spicc0_clk_enable,
+ .pinctrl_enable = spicc0_pinctrl_enable,
+ /* case one slave without cs: {"no_cs", 0} */
+ .cs_gpio_names = {"GPIOZ_3", 0},
+};
+
+U_BOOT_DEVICE(spicc0) = {
+ .name = "spicc",
+ .platdata = &spicc0_platdata,
+};
+#endif /* CONFIG_AML_SPICC */
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_PCIE
+ pcie_init_reset_pin();
+#endif
+
+#ifdef CONFIG_AML_WIFI_EN_INIT
+ wifi_init_enable_pin();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ //vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
diff --git a/board/amlogic/axg_skt_v1/eth_setup.c b/board/amlogic/axg_skt_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/axg_skt_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/axg_skt_v1/firmware/board_init.c b/board/amlogic/axg_skt_v1/firmware/board_init.c
new file mode 100644
index 0000000..2771433
--- /dev/null
+++ b/board/amlogic/axg_skt_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/axg_skt_v1/firmware/power.c b/board/amlogic/axg_skt_v1/firmware/power.c
new file mode 100644
index 0000000..f2139fd
--- /dev/null
+++ b/board/amlogic/axg_skt_v1/firmware/power.c
@@ -0,0 +1,183 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+enum pwm_id {
+ pwm_ao_b=0,
+ pwm_ao_d,
+};
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ */
+
+ switch (id) {
+ case pwm_ao_d:
+ reg = readl(AO_PWM_MISC_REG_CD);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_CD);
+ /*
+ * default set to max voltage
+ */
+ reg = readl(AO_RTI_PINMUX_REG1);
+ reg &= ~(0xf << 4);
+ writel(reg | (0x3 << 4), AO_RTI_PINMUX_REG1);
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ reg = readl(AO_RTI_PINMUX_REG0);
+ reg &= ~(0xf << 8);
+ writel(reg | (0x3 << 8), AO_RTI_PINMUX_REG0);
+ break;
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ switch (id) {
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ writel(pwm_voltage_table[to][0],AO_PWM_PWM_B);
+ break;
+ case pwm_ao_d:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_D);
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_d, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_ao_b);
+ pwm_init(pwm_ao_d);
+}
diff --git a/board/amlogic/axg_skt_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/axg_skt_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..5d52f34
--- /dev/null
+++ b/board/amlogic/axg_skt_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,141 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860),
+ DVFS( 250000000, 860+CHIP_ADJUST),
+ DVFS( 500000000, 860+RIPPLE_ADJUST),
+ DVFS( 667000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+void pwm_init(void)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ */
+
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ reg = readl(AO_RTI_PINMUX_REG0);
+ reg &= ~(0xf << 8);
+ writel(reg | (0x3 << 8), AO_RTI_PINMUX_REG0);
+
+ _udelay(200);
+}
+
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = readl(AO_PWM_PWM_B);
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init();
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ writel(pwm_voltage_table[cur][0], AO_PWM_PWM_B);
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/axg_skt_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/axg_skt_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..6d4109e
--- /dev/null
+++ b/board/amlogic/axg_skt_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,39 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#endif //__PWM_CTRL_H__
\ No newline at end of file
diff --git a/board/amlogic/axg_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/axg_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..26e7b17
--- /dev/null
+++ b/board/amlogic/axg_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,181 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+//#include "pwm_ctrl.h"
+
+#if 0
+
+#define ON 1
+#define OFF 0
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ switch (id) {
+ case pwm_a:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table_ee[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+#endif
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ return;
+}
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ return;
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+
+ p->sources = val;
+ p->gpio_info_count = 0;
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ unsigned char adc_key_cnt = 0;
+
+ init_remote();
+ saradc_enable();
+
+ do {
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+
+ if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
+ irq[IRQ_VRTC] = 0xFFFFFFFF;
+ exit_reason = RTC_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/axg_skt_v1/firmware/timing.c b/board/amlogic/axg_skt_v1/firmware/timing.c
new file mode 100644
index 0000000..e0f7775
--- /dev/null
+++ b/board/amlogic/axg_skt_v1/firmware/timing.c
@@ -0,0 +1,569 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 20
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_60OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x59959, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0x10,
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/axg_skt_v1/lcd.c b/board/amlogic/axg_skt_v1/lcd.c
new file mode 100755
index 0000000..54e606b
--- /dev/null
+++ b/board/amlogic/axg_skt_v1/lcd.c
@@ -0,0 +1,467 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+
+
+
+//Rsv_val = 0xffffffff
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_6",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_dft[] = {
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_dft[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+#if 0 /* reset in init_cmd */
+ {LCD_POWER_TYPE_CPU, 0,1,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,100,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_4",
+ "GPIOZ_5",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,
+ /* custome */
+ Rsv_val,Rsv_val,Rsv_val,
+ /* MIPI_attr: lane_num, bit_rate_max, factor, operation_mode_init, operation_mode_display, video_mode_type, clk_always_hs, phy_stop_wait */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_dft, lcd_power_off_step_dft,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_A,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_A,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,3,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_A,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOZ_5
+ .pinmux_set = {{2, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x00d00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xff, 20,
+ 0x05, 1, 0x29,
+ 0xff, 20,
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xff, 10,
+ 0x05, 1, 0x10,
+ 0xff, 10,
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xff, 100, /* delay */
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0xff, //ending flag
+};
+
+static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff,0xff, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 4,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .cmd_size = 9,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 1,
+ .name = "mipi_KD080D13",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 2,
+ .name = "mipi_TV070WSM",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 3,
+ .name = "mipi_P070ACB",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{2, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x00d00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "none",
+ .type = BL_EXTERN_MAX,
+ .i2c_addr = 0xff,
+ .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+ .dim_min = 10,
+ .dim_max = 255,
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/configs/axg_s400_v1.h b/board/amlogic/configs/axg_s400_v1.h
new file mode 100755
index 0000000..27b4ff5
--- /dev/null
+++ b/board/amlogic/configs/axg_s400_v1.h
@@ -0,0 +1,597 @@
+
+/*
+ * board/amlogic/configs/axg_s400_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __AXG_S400_V1_H__
+#define __AXG_S400_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 950 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 810 // voltage for suspend
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* command watchdog */
+#define CONFIG_CMD_WATCHDOG 1
+
+/*config irblaster*/
+#define CONFIG_CMD_IRBLASTER 1
+
+/*config a/b system*/
+//#define CONFIG_AB_SYSTEM 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+#define CONFIG_BT_WAKEUP
+//#define CONFIG_WIFI_WAKEUP
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 5
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 0 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lcd_0\0" \
+ "outputmode=panel\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=768\0" \
+ "fb_height=1024\0" \
+ "lock=10001000\0"\
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlycon=aml_uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "setenv bootargs ${bootargs} slot_suffix=${active_slot};"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "i2c mw 1f 3.1 0 2;i2c mw 1f 1.1 fc 2;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+
+/* IMPORTANT
+ * DDR clk <= 400MHz, please enable CONFIG_DDR_PLL_BYPASS blow
+ * DDR clk > 400MHz, please disable CONFIG_DDR_PLL_BYPASS blow
+ */
+#define CONFIG_DDR_CLK 912 //MHz, Range: 200-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 912 //MHz, this is for same board with DDR4 chip
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_16BIT
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 1 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+#define CONFIG_BL2_COPY_NUM 8
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+/* storage macro checks */
+#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND)
+#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled.
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 3
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+//#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 0
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+//#define CONFIG_AML_CVBS 1
+#endif
+
+#define CONFIG_AML_LCD 1
+/*#define CONFIG_AML_LCD_TV 1*/
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_TV070WSM 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_ST7701 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_P070ACB 1
+#define CONFIG_AML_BL_EXTERN 1
+#define CONFIG_AML_BL_EXTERN_MIPI_IT070ME05 1
+
+#define CONFIG_AML_WIFI_EN_INIT
+#define CONFIG_AML_GPIO_WIFI_EN_1 PIN_GPIOX_7
+#define CONFIG_AML_GPIO_WIFI_EN_2 PIN_GPIOX_16
+#define CONFIG_AML_GPIO_WIFI_EN_1_NAME "GPIOX_7"
+#define CONFIG_AML_GPIO_WIFI_EN_2_NAME "GPIOX_16"
+
+#define CONFIG_AML_PCIE
+#define CONFIG_AML_PCIEA_GPIO_RESET PIN_GPIOX_19
+#define CONFIG_AML_PCIEB_GPIO_RESET PIN_GPIOZ_10
+#define CONFIG_AML_PCIEA_GPIO_RESET_NAME "GPIOX_19"
+#define CONFIG_AML_PCIEB_GPIO_RESET_NAME "GPIOZ_10"
+
+#define CONFIG_PCI 1
+#define CONFIG_CMD_PCI 1
+#define CONFIG_CMD_PCI_ENUM 1
+#define CONFIG_PCIE_AMLOGIC 1
+#define CONFIG_PCI_SCAN_SHOW 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_AML_MTD
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1
+#endif
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0xA000000
+#define CONFIG_DEVICE_PRODUCT "axg_s400"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+/* #define CONFIG_SYS_I2C_AML_IS31F123XX 1 */
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0
+#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//2017.04.26
+//data compress for BL30,BL32,BL33
+//compress ratio is about 50%, BL31 will take the decompress
+//profit :
+// size : u-boot.bin 1.2MB -> 780KB
+// boot time : 140ms decrease
+//default: enable the data compress feature
+//to disable the data compress please just define followings
+//#define CONFIG_AML_BL30_COMPRESS_DISABLE 1
+//#define CONFIG_AML_BL32_COMPRESS_DISABLE 1
+//#define CONFIG_AML_BL33_COMPRESS_DISABLE 1
+
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/axg_s400_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define ETHERNET_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/axg_s420_v1.h b/board/amlogic/configs/axg_s420_v1.h
new file mode 100755
index 0000000..77b7e67
--- /dev/null
+++ b/board/amlogic/configs/axg_s420_v1.h
@@ -0,0 +1,569 @@
+
+/*
+ * board/amlogic/configs/axg_s400_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __AXG_S400_V1_H__
+#define __AXG_S400_V1_H__
+
+#include <asm/arch/cpu.h>
+
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 950 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 810 // voltage for suspend
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* command watchdog */
+#define CONFIG_CMD_WATCHDOG 1
+
+/*config a/b system*/
+//#define CONFIG_AB_SYSTEM 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+#define CONFIG_BT_WAKEUP
+//#define CONFIG_WIFI_WAKEUP
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 5
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 0 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "dtb_mem_addr=0x1000000\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "lock=10001000\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlycon=aml_uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "setenv bootargs ${bootargs} slot_suffix=${active_slot};"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "i2c mw 1f 3.1 0 2;i2c mw 1f 1.1 fc 2;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+
+/* IMPORTANT
+ * DDR clk <= 400MHz, please enable CONFIG_DDR_PLL_BYPASS blow
+ * DDR clk > 400MHz, please disable CONFIG_DDR_PLL_BYPASS blow
+ */
+#define CONFIG_DDR_CLK 912 //MHz, Range: 200-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 912 //MHz, this is for same board with DDR4 chip
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_16BIT
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 1 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* #define CONFIG_ENV_IS_IN_NAND 1 */
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0
+#ifdef CONFIG_ENV_SIZE
+#undef CONFIG_ENV_SIZE
+/*
+ *The env size must be an integer
+ *multiple of the block size
+ */
+#define CONFIG_ENV_SIZE (128*1024)
+#endif
+#endif
+
+
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+#define CONFIG_BL2_COPY_NUM 8
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+/* storage macro checks */
+#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND)
+#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled.
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_AMLNAND) && defined(CONFIG_ENV_IS_IN_NAND)
+#error CONFIG_ENV_IS_IN_AMLNAND and CONFIG_ENV_IS_IN_NAND are not compatibility
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+
+/* vpu */
+//#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 3
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+//#define CONFIG_AML_CANVAS 1
+//#define CONFIG_AML_VOUT 1
+//#define CONFIG_AML_OSD 1
+//#define CONFIG_OSD_SCALE_ENABLE 0
+//#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+//#define CONFIG_AML_CVBS 1
+#endif
+
+//#define CONFIG_AML_LCD 1
+
+/*#define CONFIG_AML_LCD_TV 1*/
+//#define CONFIG_AML_LCD_TABLET 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_AML_MTD
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1
+#endif
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0xA000000
+#define CONFIG_DEVICE_PRODUCT "axg_s400"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+/* #define CONFIG_SYS_I2C_AML_IS31F123XX 1 */
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0
+#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//2017.04.26
+//data compress for BL30,BL32,BL33
+//compress ratio is about 50%, BL31 will take the decompress
+//profit :
+// size : u-boot.bin 1.2MB -> 780KB
+// boot time : 140ms decrease
+//default: enable the data compress feature
+//to disable the data compress please just define followings
+//#define CONFIG_AML_BL30_COMPRESS_DISABLE 1
+//#define CONFIG_AML_BL32_COMPRESS_DISABLE 1
+//#define CONFIG_AML_BL33_COMPRESS_DISABLE 1
+
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/axg_s400_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define ETHERNET_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/axg_skt_v1.h b/board/amlogic/configs/axg_skt_v1.h
new file mode 100755
index 0000000..caac81c
--- /dev/null
+++ b/board/amlogic/configs/axg_skt_v1.h
@@ -0,0 +1,592 @@
+
+/*
+ * board/amlogic/configs/axg_skt_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __AXG_SKT_V1_H__
+#define __AXG_SKT_V1_H__
+
+#include <asm/arch/cpu.h>
+
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+//#define CONFIG_AML_RPMB_DISABLE
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 950 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* command watchdog */
+#define CONFIG_CMD_WATCHDOG 1
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 5
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 0 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "i2c_auto_test=disable\0" \
+ "loadaddr=1080000\0"\
+ "panel_type=lcd_0\0" \
+ "outputmode=panel\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=768\0" \
+ "fb_height=1024\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "lock=10001000\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlycon=aml_uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag} i2c_auto_test=${i2c_auto_test}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel boot ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+
+/* IMPORTANT
+ * DDR clk <= 400MHz, please enable CONFIG_DDR_PLL_BYPASS blow
+ * DDR clk > 400MHz, please disable CONFIG_DDR_PLL_BYPASS blow
+ */
+#define CONFIG_DDR_CLK 912 //MHz, Range: 200-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 912 //MHz, this is for same board with DDR4 chip
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_16BIT
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 1 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 1 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+#define CONFIG_BL2_COPY_NUM 8
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+/* storage macro checks */
+#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND)
+#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled.
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL // to test
+ #define CONFIG_SPI_FLASH_EON // to test
+ #define CONFIG_SPI_FLASH_GIGADEVICE // to test
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION // to test
+ #define CONFIG_SPI_FLASH_STMICRO // to test
+ #define CONFIG_SPI_FLASH_SST // to test
+ #define CONFIG_SPI_FLASH_WINBOND // to test
+ #define CONFIG_SPI_FRAM_RAMTRON // to add & test
+ #define CONFIG_SPI_M95XXX // to add & test
+ #define CONFIG_SPI_FLASH_ESMT // to add & test
+ #define CONFIG_SPI_NAND
+#endif
+
+
+/* vpu */
+//#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 3
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+//#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+//#define CONFIG_AML_OSD 1
+//#define CONFIG_OSD_SCALE_ENABLE 0
+//#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+//#define CONFIG_AML_CVBS 1
+#endif
+
+#define CONFIG_AML_WIFI_EN_INIT
+#define CONFIG_AML_GPIO_WIFI_EN PIN_GPIOX_16
+#define CONFIG_AML_GPIO_WIFI_EN_NAME "GPIOX_16"
+
+#define CONFIG_AML_PCIE
+#define CONFIG_AML_PCIEA_GPIO_RESET PIN_GPIOX_19
+#define CONFIG_AML_PCIEA_GPIO_RESET_NAME "GPIOX_19"
+
+#define CONFIG_PCI 1
+#define CONFIG_CMD_PCI 1
+#define CONFIG_CMD_PCI_ENUM 1
+#define CONFIG_PCIE_AMLOGIC 1
+#define CONFIG_PCI_SCAN_SHOW 1
+
+//#define CONFIG_AML_LCD 1
+//#define CONFIG_AML_LCD_TV 1
+//#define CONFIG_AML_LCD_TABLET 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_AML_MTD
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1
+#endif
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0xA000000
+#define CONFIG_DEVICE_PRODUCT "axg_skt"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_CHIPID 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//2017.04.26
+//data compress for BL30,BL32,BL33
+//compress ratio is about 50%, BL31 will take the decompress
+//profit :
+// size : u-boot.bin 1.2MB -> 780KB
+// boot time : 140ms decrease
+//default: enable the data compress feature
+//to disable the data compress please just define followings
+//#define CONFIG_AML_BL30_COMPRESS_DISABLE 1
+//#define CONFIG_AML_BL32_COMPRESS_DISABLE 1
+//#define CONFIG_AML_BL33_COMPRESS_DISABLE 1
+
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define ETHERNET_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/g12a_estelle_bx.h b/board/amlogic/configs/g12a_estelle_bx.h
new file mode 100755
index 0000000..62fb29b
--- /dev/null
+++ b/board/amlogic/configs/g12a_estelle_bx.h
@@ -0,0 +1,566 @@
+
+/*
+ * board/amlogic/configs/g12a_estelle_bx.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __G12A_S905D2_ESTELLE_BX_V1_H__
+#define __G12A_S905D2_ESTELLE_BX_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+#define CONFIG_ABR_WEAR_LEVELING
+#define CONFIG_ZIRCON_BOOT_IMAGE
+#define CONFIG_ZIRCON_VBOOT
+#define CONFIG_LIBAVB
+#define CONFIG_USE_ROLLBACK_IN_FUSE
+#define CONFIG_WDT
+
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_DEVICE_PRODUCT "Google Home Hub"
+
+/* Timeout of 0 will only check any buffered keys, but will then continue
+ immediately. This turns out to be sufficient for us, since a user can hit
+ the fastboot key any time prior to this during boot and we'll still see it
+ when flushing the buffer. */
+#define CONFIG_FORCE_FASTBOOT_TIMEOUT_MS 0
+
+#define CONFIG_G_DNL_MANUFACTURER "Google"
+#define CONFIG_G_DNL_VENDOR_NUM 0x18d1
+#define CONFIG_G_DNL_PRODUCT_NUM 0x4ee0
+
+/* DRAM Layout
+ * 0x00000000 -----------------------------------------
+ * RSV (16 MiB) (Usable by kernel)
+ * 0x01000000 -----------------------------------------
+ * Device Tree (512 KiB) (Unused)
+ * 0x01080000 -----------------------------------------
+ * Default Kernel Location (63.5 MiB)
+ * 0x05000000 -----------------------------------------
+ * BL31/32 Reserved (35 MiB)
+ * 0x07300000 -----------------------------------------
+ * LastKmsg (Unused)
+ * 0x07400000 -----------------------------------------
+ * Fastboot Buffer Location (512 MiB)
+ * 0x27400000 -----------------------------------------
+ * Unused (512 MiB)
+ * 0x47400000 -----------------------------------------
+ * U-Boot Code + Stack + Heap (268 MiB)
+ * 0x58000000 -----------------------------------------
+ * RSV (128 MiB)
+ * - board cfg file?
+ * 0x5f7fe000 - 0x5f800000 (8 KiB)
+ * - NVRAM region
+ * 0x5f800000 - 0x60000000 (8 MiB)
+ * - marked as reserved to zircon
+ * 0x60000000 -----------------------------------------
+ */
+#define CONFIG_DEFAULT_KERNEL_ADDR 0x01080000
+#define CONFIG_DEFAULT_KERNEL_SIZE 0x03f80000
+#define CONFIG_USB_FASTBOOT_BUF_ADDR 0x07400000
+#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x20000000
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr="__stringify(CONFIG_DEFAULT_KERNEL_ADDR)"\0" \
+ "loadsize="__stringify(CONFIG_DEFAULT_KERNEL_SIZE)"\0" \
+ "outputmode=panel\0" \
+ "hdmimode=1080p60hz\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x5f800000\0" \
+ "fb_width=608\0" \
+ "fb_height=1024\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0" \
+ "try_auto_burn=update 700 750;\0" \
+ "sdcburncfg=aml_sdc_burn.ini\0" \
+ "sdc_burning=sdc_burn ${sdcburncfg}\0" \
+ "wipe_data=successful\0" \
+ "wipe_cache=successful\0" \
+ "EnableSelinux=enforcing\0" \
+ "storeargs=" \
+ "get_rebootmode;" \
+ "setenv bootargs " \
+ "logo=${display_layer},loaded,${fb_addr} " \
+ "vout=${outputmode},enable " \
+ "panel_type=${panel_type} " \
+ "test_mode=${test_mode} " \
+ "androidboot.reboot_mode=${reboot_mode} " \
+ "ramoops.mem_address=0x20000000 ramoops.mem_size=0x100000 ramoops.record_size=0x8000 ramoops.console_size=0x8000 " \
+ "hw_id=${hw_id};" \
+ "setenv bootargs ${bootargs} " \
+ "androidboot.hardware="__stringify(BOARD_NAME)";" \
+ "\0" \
+ "switch_bootmode=" \
+ "get_rebootmode;" \
+ "if test ${reboot_mode} = factory_reset; then " \
+ "run recovery_from_flash;" \
+ "else if test ${reboot_mode} = update; then " \
+ "run update;" \
+ "else if test ${reboot_mode} = cold_boot; then " \
+ /* "run try_auto_burn;" */ \
+ "else if test ${reboot_mode} = fastboot; then " \
+ "fastboot;" \
+ "fi;fi;fi;fi;" \
+ "\0" \
+ "storeboot=" \
+ /* zvb_load_and_boot doesn't return on success */ \
+ "zvb_load_and_boot kernel ${loadaddr} ${loadsize};" \
+ "run update;" \
+ "\0" \
+ "factory_reset_poweroff_protect=" \
+ "echo wipe_data=${wipe_data};" \
+ "echo wipe_cache=${wipe_cache};" \
+ "if test ${wipe_data} = failed; then " \
+ "run init_display;" \
+ "run get_hw_id;" \
+ "run storeargs;" \
+ "run recovery_from_flash;" \
+ "fi;" \
+ "if test ${wipe_cache} = failed; then " \
+ "run init_display;" \
+ "run get_hw_id;" \
+ "run storeargs;" \
+ "run recovery_from_flash;" \
+ "fi;" \
+ "\0" \
+ "update=" \
+ "run usb_burning;" \
+ "run recovery_from_flash;" \
+ "\0" \
+ /* load and boot an image from 'recovery' partition to restore the device. */ \
+ "recovery_from_flash=" \
+ "zvb_load_and_boot recovery ${loadaddr} ${loadsize};" \
+ "\0" \
+ "reset_ddic=" \
+ "gpio clear GPIOH_6" \
+ "\0" \
+ "detect_panel=" \
+ "if gpio input GPIOH_5; then " \
+ "setenv panel_type lcd_3;" \
+ "else " \
+ "setenv panel_type lcd_4;" \
+ "fi;" \
+ "\0" \
+ "start_backlight=" \
+ "if ubifsload 0x8000000 bl_calibration.txt; then " \
+ "configure_backlight 0x8000000;" \
+ "else " \
+ "configure_backlight;" \
+ "fi;" \
+ "\0"\
+ "init_display=" \
+ "run reset_ddic;" \
+ "check_fdr_for_backlight_brightness;" \
+ "run detect_panel;" \
+ "osd open;" \
+ "osd clear;" \
+ "osd setcolor 0x5b0d5b0d;" \
+ "ubi part factory;" \
+ "ubifsmount ubi0:factory;" \
+ /* do this sequentially so we could reuse the address and do
+ * not need to know the size of the images */ \
+ "mw 0x8000000 0 1;" \
+ "ubifsload 0x8000000 logo.bmp;" \
+ "bmp display 0x8000000;" \
+ "mw 0x8000000 0 1;" \
+ "ubifsload 0x8000000 corner_BL.bmp;" \
+ "bmp display 0x8000000 0 1008;" \
+ "mw 0x8000000 0 1;" \
+ "ubifsload 0x8000000 corner_BR.bmp;" \
+ "bmp display 0x8000000 592 1008;" \
+ "mw 0x8000000 0 1;" \
+ "ubifsload 0x8000000 corner_TL.bmp;" \
+ "bmp display 0x8000000 0 0;" \
+ "mw 0x8000000 0 1;" \
+ "ubifsload 0x8000000 corner_TR.bmp;" \
+ "bmp display 0x8000000 592 0;" \
+ "bmp scale;" \
+ "vout output ${outputmode};" \
+ "run start_backlight;" \
+ "ubifsumount;" \
+ "\0" \
+ "get_hw_id=" \
+ "get_estelle_hw_id;" \
+ "\0" \
+ "upgrade_key=" \
+ "setenv boot_external_image 0;" \
+ "if gpio input GPIOZ_6; then " \
+ "echo detect VOL_DN pressed;" \
+ "run recovery_from_flash;" \
+ "else " \
+ "if gpio input GPIOZ_5; then " \
+ "echo detect VOL_UP pressed;" \
+ "if gpio input GPIOZ_2; then " \
+ "echo MUTE not engaged, starting fastboot;" \
+ "fastboot;" \
+ "else " \
+ "echo MUTE engaged, skipping fastboot;" \
+ "fi;" \
+ "else " \
+ "echo upgrade key not pressed;" \
+ "fi;" \
+ "fi;" \
+ "if force_fastboot_mode; then " \
+ "echo fastboot mode was requested;" \
+ "fastboot;" \
+ "fi;" \
+ "\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run factory_reset_poweroff_protect;" \
+ "run init_display;" \
+ "run get_hw_id;" \
+ "run storeargs;" \
+ "run upgrade_key;" \
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot;"
+
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_SHORT_RSV 1
+#define RESERVED_BLOCK_NUM 8
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+#define CONFIG_NOT_SKIP_BAD_BLOCK 1
+
+/* support nand fts*/
+#define CONFIG_NAND_FTS 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+#define CONFIG_BL2_COPY_NUM 8
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE y
+ #define CONFIG_RBTREE
+ #define CONFIG_CMD_NAND_TORTURE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+ #define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_CANVAS 1 // required for showing the logo during uboot
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_TV070WSM 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_P070ACB 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_TV070WSM_FT 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_P070ACB_FT 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_PHY_20 0xff636000
+ #define CONFIG_USB_PHY_21 0xff63A000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_V2 1
+ #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6)
+ #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6"
+ //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+#define CONFIG_USB_DEVICE_V2 1
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+//UBOOT Facotry usb/sdcard burning config
+#ifndef CONFIG_AML_DISABLE_UPDATE_MODE
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#endif
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_AML_HAS_MASK 1
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_FACTORY_BOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY -2 // autoboot with no delay and not check for abort
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_LOADB 1
+
+//#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+// Check size of boot image before load. See doc:
+// https://docs.google.com/document/d/1YrW2yBzCbMrQfBR2n56aUPZPg_0waxveOH-E0NU07OM/edit?usp=sharing
+#define CONFIG_IMG_SECURE_CHECK_SZ 0x3f00000
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+#endif
+
diff --git a/board/amlogic/configs/g12a_estelle_p2.h b/board/amlogic/configs/g12a_estelle_p2.h
new file mode 100755
index 0000000..041a048
--- /dev/null
+++ b/board/amlogic/configs/g12a_estelle_p2.h
@@ -0,0 +1,544 @@
+
+/*
+ * board/amlogic/configs/g12a_estelle_p2.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __G12A_S905D2_ESTELLE_P2_V1_H__
+#define __G12A_S905D2_ESTELLE_P2_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+#define CONFIG_ZIRCON_BOOT_IMAGE
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0" \
+ "loadaddr=1080000\0" \
+ "outputmode=panel\0" \
+ "hdmimode=1080p60hz\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x5f800000\0" \
+ "fb_width=608\0" \
+ "fb_height=1024\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0" \
+ "try_auto_burn=update 700 750;\0" \
+ "sdcburncfg=aml_sdc_burn.ini\0" \
+ "sdc_burning=sdc_burn ${sdcburncfg}\0" \
+ "wipe_data=successful\0" \
+ "wipe_cache=successful\0" \
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0" \
+ "recovery_offset=0\0" \
+ "active_slot=_a\0" \
+ "boot_part=boot\0" \
+ "storeargs=" \
+ "get_rebootmode;" \
+ "setenv bootargs " \
+ "logo=${display_layer},loaded,${fb_addr} " \
+ "vout=${outputmode},enable " \
+ "panel_type=${panel_type} " \
+ "androidboot.selinux=${EnableSelinux} " \
+ "androidboot.firstboot=${firstboot} " \
+ "test_mode=${test_mode} " \
+ "androidboot.reboot_mode=${reboot_mode} " \
+ "hw_id=${hw_id};" \
+ "setenv bootargs ${bootargs} " \
+ "androidboot.hardware=estelle-p2;" \
+ "setenv bootargs ${bootargs} " \
+ "androidboot.slot_suffix=${active_slot};" \
+ "\0" \
+ "switch_bootmode=" \
+ "get_rebootmode;" \
+ "if test ${reboot_mode} = factory_reset; then " \
+ "run recovery_from_flash;" \
+ "else if test ${reboot_mode} = update; then " \
+ "run update;" \
+ "else if test ${reboot_mode} = cold_boot; then " \
+ /* "run try_auto_burn;" */ \
+ "else if test ${reboot_mode} = fastboot; then " \
+ "fastboot;" \
+ "else if test ${reboot_mode} = factory_boot; then " \
+ "if imgread kernel cache ${loadaddr}; then " \
+ "bootm ${loadaddr};" \
+ "fi;" \
+ "fi;fi;fi;fi;fi;" \
+ "\0" \
+ "storeboot=" \
+ "if imgread kernel ${boot_part} ${loadaddr}; then " \
+ "bootm ${loadaddr};" \
+ "fi;" \
+ "run update;" \
+ "\0" \
+ "factory_reset_poweroff_protect=" \
+ "echo wipe_data=${wipe_data};" \
+ "echo wipe_cache=${wipe_cache};" \
+ "if test ${wipe_data} = failed; then " \
+ "run init_display;" \
+ "run get_hw_id;" \
+ "run storeargs;" \
+ "if usb start 0; then " \
+ "run recovery_from_udisk;" \
+ "fi;" \
+ "run recovery_from_flash;" \
+ "fi;" \
+ "if test ${wipe_cache} = failed; then " \
+ "run init_display;" \
+ "run get_hw_id;" \
+ "run storeargs;" \
+ "if usb start 0; then " \
+ "run recovery_from_udisk;" \
+ "fi;" \
+ "run recovery_from_flash;" \
+ "fi;" \
+ "\0" \
+ "update=" \
+ "run usb_burning;" \
+ "run recovery_from_flash;" \
+ "\0" \
+ "recovery_from_udisk=" \
+ "while true ;do " \
+ "usb start 0;fatls usb 0; " \
+ "if fatload usb 0 ${loadaddr} recovery.img; then " \
+ "bootm ${loadaddr};" \
+ "fi;" \
+ "done;" \
+ "\0" \
+ "recovery_from_flash=" \
+ "setenv bootargs ${bootargs} " \
+ "aml_dt=${aml_dt} " \
+ "recovery_part=${recovery_part} " \
+ "recovery_offset=${recovery_offset};" \
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then " \
+ "wipeisb;" \
+ "bootm ${loadaddr};" \
+ "fi" \
+ "\0" \
+ "reset_ddic=" \
+ "gpio clear GPIOH_6" \
+ "\0" \
+ "detect_panel=" \
+ "get_ddictype;" \
+ "if test $ddic_type = FITI; then " \
+ "if gpio input GPIOH_5; then " \
+ "setenv panel_type lcd_3;" \
+ "else " \
+ "setenv panel_type lcd_4;" \
+ "fi;" \
+ "else " \
+ "if gpio input GPIOH_5; then " \
+ "setenv panel_type lcd_1;" \
+ "else " \
+ "setenv panel_type lcd_2;" \
+ "fi;" \
+ "fi;" \
+ "\0" \
+ "start_backlight=" \
+ "if ubifsload 0x8000000 bl_calibration.txt; then " \
+ "configure_backlight 0x8000000;" \
+ "else " \
+ "configure_backlight;" \
+ "fi;" \
+ "\0"\
+ "init_display=" \
+ "run reset_ddic;" \
+ "check_fdr_for_backlight_brightness;" \
+ "run detect_panel;" \
+ "osd open;" \
+ "osd clear;" \
+ "osd setcolor 0x5b0d5b0d;" \
+ "ubi part factory;" \
+ "ubifsmount ubi0:factory;" \
+ "ubifsload 0x8000000 logo.bmp;" \
+ "bmp display 0x8000000;" \
+ "bmp scale;" \
+ "vout output ${outputmode};" \
+ "run start_backlight;" \
+ "ubifsumount;" \
+ "\0" \
+ "get_hw_id=" \
+ "get_estelle_hw_id;" \
+ "\0" \
+ "upgrade_key=" \
+ "if gpio input GPIOZ_5; then " \
+ "echo detect VOL_UP pressed;" \
+ "if gpio input GPIOZ_6; then " \
+ "echo VOL_DN pressed;" \
+ "setenv boot_external_image 1;" \
+ "run recovery_from_udisk;" \
+ "fi;" \
+ "else " \
+ "echo upgrade key not pressed;" \
+ "setenv boot_external_image 0;" \
+ "fi;" \
+ "\0" \
+ "test_mode_check=" \
+ "setenv test_mode false;" \
+ "if gpio input GPIOZ_2; then " \
+ "echo MUTE not engaged;" \
+ "else " \
+ "echo MUTE engaged;" \
+ "if gpio input GPIOZ_5; then " \
+ "echo VOL_UP pressed;" \
+ "if gpio input GPIOZ_6; then " \
+ "echo VOL_DN pressed;" \
+ "else " \
+ "echo VOL_DN not pressed;" \
+ "setenv test_mode true;" \
+ "fi;" \
+ "else " \
+ "echo VOL_UP not pressed;" \
+ "fi;" \
+ "fi;" \
+ "\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run factory_reset_poweroff_protect;" \
+ "run init_display;" \
+ "run get_hw_id;" \
+ "run test_mode_check;" \
+ "run storeargs;" \
+ "run upgrade_key;" \
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_SHORT_RSV 1
+#define RESERVED_BLOCK_NUM 8
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+/* support nand fts*/
+#define CONFIG_NAND_FTS 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+#define CONFIG_BL2_COPY_NUM 8
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE y
+ #define CONFIG_RBTREE
+ #define CONFIG_CMD_NAND_TORTURE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+ #define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_CANVAS 1 // required for showing the logo during uboot
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_TV070WSM 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_P070ACB 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_TV070WSM_FT 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_P070ACB_FT 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_PHY_20 0xff636000
+ #define CONFIG_USB_PHY_21 0xff63A000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_V2 1
+ #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6)
+ #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6"
+ //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+#define CONFIG_USB_DEVICE_V2 1
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+//UBOOT Facotry usb/sdcard burning config
+#ifndef CONFIG_AML_DISABLE_UPDATE_MODE
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#endif
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_AML_HAS_MASK 1
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_FACTORY_BOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 // delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_LOADB 1
+
+//#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+#endif
+
diff --git a/board/amlogic/configs/g12a_newman_p0.h b/board/amlogic/configs/g12a_newman_p0.h
new file mode 100755
index 0000000..eb22fdc
--- /dev/null
+++ b/board/amlogic/configs/g12a_newman_p0.h
@@ -0,0 +1,598 @@
+
+/*
+ * board/amlogic/configs/g12a_newman_p0.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __G12A_S905D2_NEWMAN_P2_V1_H__
+#define __G12A_S905D2_NEWMAN_P2_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 800 // VDDEE suspend voltage
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=panel\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x5f800000\0" \
+ "fb_width=608\0" \
+ "fb_height=1024\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=newman-p0;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "else if test ${reboot_mode} = factory_boot; then "\
+ "if imgread kernel cache ${loadaddr}; then "\
+ "bootm ${loadaddr}; fi;"\
+ "fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "reset_ddic="\
+ "gpio clear GPIOH_6"\
+ "\0"\
+ "detect_panel="\
+ "get_ddictype; "\
+ "if test $ddic_type = FITI; then "\
+ "if gpio input GPIOH_5; then "\
+ "setenv panel_type lcd_3;" \
+ "else "\
+ "setenv panel_type lcd_4;"\
+ "fi;"\
+ "else "\
+ "if gpio input GPIOH_5; then "\
+ "setenv panel_type lcd_1;" \
+ "else "\
+ "setenv panel_type lcd_2;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "run reset_ddic; run detect_panel; osd open; osd clear; ubi part factory; ubifsmount ubi0:factory; ubifsload 0x8000000 logo.bmp; bmp display 0x8000000; bmp scale; vout output ${outputmode}; ubifsumount"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOZ_5; then "\
+ "echo detect VOL_UP pressed;"\
+ "if gpio input GPIOZ_6; then "\
+ "echo VOL_DN pressed; setenv boot_external_image 1; run update;"\
+ "fi;"\
+ "else "\
+ "echo upgrade key not pressed; setenv boot_external_image 0;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;"\
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_SHORT_RSV 1
+#define RESERVED_BLOCK_NUM 8
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+//#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+#define CONFIG_BL2_COPY_NUM 8
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ /* support mmc fts*/
+ #define CONFIG_MMC_FTS 1
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL
+ #define CONFIG_SPI_FLASH_EON
+ #define CONFIG_SPI_FLASH_GIGADEVICE
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION
+ #define CONFIG_SPI_FLASH_STMICRO
+ #define CONFIG_SPI_FLASH_SST
+ #define CONFIG_SPI_FLASH_WINBOND
+ #define CONFIG_SPI_FRAM_RAMTRON
+ #define CONFIG_SPI_M95XXX
+ #define CONFIG_SPI_FLASH_ESMT
+ /* SPI nand flash support */
+ #define CONFIG_SPI_NAND
+ #define CONFIG_BL2_SIZE (64 * 1024)
+#endif
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE y
+ #define CONFIG_RBTREE
+ #define CONFIG_CMD_NAND_TORTURE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+ #define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+//#define CONFIG_AML_CVBS 1
+#endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_TV070WSM 1
+#define CONFIG_AML_LCD_EXTERN_MIPI_P070ACB 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_PHY_20 0xff636000
+ #define CONFIG_USB_PHY_21 0xff63A000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_V2 1
+ #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6)
+ #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6"
+ //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+#define CONFIG_USB_DEVICE_V2 1
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "newman_p0"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#undef CONFIG_CMD_NET
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_AML_HAS_MASK 1
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_FACTORY_BOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_LOADB 1
+
+//#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+#endif
+
diff --git a/board/amlogic/configs/g12a_skt_v1.h b/board/amlogic/configs/g12a_skt_v1.h
new file mode 100644
index 0000000..5a08395
--- /dev/null
+++ b/board/amlogic/configs/g12a_skt_v1.h
@@ -0,0 +1,581 @@
+
+/*
+ * board/amlogic/configs/txlx_t962x_r311_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __TXLX_T962E_R321_V1_H__
+#define __TXLX_T962E_R321_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+#define CONFIG_SARADC_CH 2
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "lock=10001000\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "forceupdate;" \
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+//SKT 1024 pages only support 4 block, so 4 copies
+#define CONFIG_BL2_COPY_NUM 4
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL
+ #define CONFIG_SPI_FLASH_EON
+ #define CONFIG_SPI_FLASH_GIGADEVICE
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION
+ #define CONFIG_SPI_FLASH_STMICRO
+ #define CONFIG_SPI_FLASH_SST
+ #define CONFIG_SPI_FLASH_WINBOND
+ #define CONFIG_SPI_FRAM_RAMTRON
+ #define CONFIG_SPI_M95XXX
+ #define CONFIG_SPI_FLASH_ESMT
+ /* SPI nand flash support */
+ #define CONFIG_SPI_NAND
+ #define CONFIG_BL2_SIZE (64 * 1024)
+#endif
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE y
+ #define CONFIG_RBTREE
+ #define CONFIG_CMD_NAND_TORTURE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+ #define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+// #define CONFIG_AML_LCD 1
+// #define CONFIG_AML_LCD_TABLET 1
+// #define CONFIG_AML_LCD_EXTERN 1
+// #define CONFIG_AML_LCD_EXTERN_MIPI_TV070WSM 1
+// #define CONFIG_AML_LCD_EXTERN_MIPI_P070ACB 1
+// #define CONFIG_AML_LCD_EXTERN_MIPI_TL050FHV02CT 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_PHY_20 0xff636000
+ #define CONFIG_USB_PHY_21 0xff63A000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_V2 1
+ #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6)
+ #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6"
+ //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+#define CONFIG_USB_DEVICE_V2 1
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "g12a_skt"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_PLLTEST 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_LOADB 1
+
+//#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+/* Choose One of Ethernet Type */
+#undef CONFIG_ETHERNET_NONE
+#define ETHERNET_INTERNAL_PHY
+#undef ETHERNET_EXTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/g12a_u200_v1.h b/board/amlogic/configs/g12a_u200_v1.h
new file mode 100755
index 0000000..454f401
--- /dev/null
+++ b/board/amlogic/configs/g12a_u200_v1.h
@@ -0,0 +1,577 @@
+
+/*
+ * board/amlogic/configs/g12a_u200_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __G12A_U200_V1_H__
+#define __G12A_U200_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+#define CONFIG_SARADC_CH 2
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "lock=10001000\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "forceupdate;" \
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+//SKT 1024 pages only support 4 block, so 4 copies
+#define CONFIG_BL2_COPY_NUM 4
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL
+ #define CONFIG_SPI_FLASH_EON
+ #define CONFIG_SPI_FLASH_GIGADEVICE
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION
+ #define CONFIG_SPI_FLASH_STMICRO
+ #define CONFIG_SPI_FLASH_SST
+ #define CONFIG_SPI_FLASH_WINBOND
+ #define CONFIG_SPI_FRAM_RAMTRON
+ #define CONFIG_SPI_M95XXX
+ #define CONFIG_SPI_FLASH_ESMT
+ /* SPI nand flash support */
+ #define CONFIG_SPI_NAND
+ #define CONFIG_BL2_SIZE (64 * 1024)
+#endif
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE y
+ #define CONFIG_RBTREE
+ #define CONFIG_CMD_NAND_TORTURE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+ #define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+// #define CONFIG_AML_LCD 1
+// #define CONFIG_AML_LCD_TABLET 1
+// #define CONFIG_AML_LCD_EXTERN 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_PHY_20 0xff636000
+ #define CONFIG_USB_PHY_21 0xff63A000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_V2 1
+ #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6)
+ #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6"
+ //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+#define CONFIG_USB_DEVICE_V2 1
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "u200"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_LOADB 1
+
+//#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+/* Choose One of Ethernet Type */
+#undef CONFIG_ETHERNET_NONE
+#define ETHERNET_INTERNAL_PHY
+#undef ETHERNET_EXTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/g12a_u211_v1.h b/board/amlogic/configs/g12a_u211_v1.h
new file mode 100755
index 0000000..785afbd
--- /dev/null
+++ b/board/amlogic/configs/g12a_u211_v1.h
@@ -0,0 +1,576 @@
+
+/*
+ * board/amlogic/configs/g12a_u211_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __G12A_U211_V1_H__
+#define __G12A_U211_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "lock=10001000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmimode=${hdmimode} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+//SKT 1024 pages only support 4 block, so 4 copies
+#define CONFIG_BL2_COPY_NUM 4
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL
+ #define CONFIG_SPI_FLASH_EON
+ #define CONFIG_SPI_FLASH_GIGADEVICE
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION
+ #define CONFIG_SPI_FLASH_STMICRO
+ #define CONFIG_SPI_FLASH_SST
+ #define CONFIG_SPI_FLASH_WINBOND
+ #define CONFIG_SPI_FRAM_RAMTRON
+ #define CONFIG_SPI_M95XXX
+ #define CONFIG_SPI_FLASH_ESMT
+ /* SPI nand flash support */
+ #define CONFIG_SPI_NAND
+ #define CONFIG_BL2_SIZE (64 * 1024)
+#endif
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE y
+ #define CONFIG_RBTREE
+ #define CONFIG_CMD_NAND_TORTURE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+ #define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+// #define CONFIG_AML_LCD 1
+// #define CONFIG_AML_LCD_TABLET 1
+// #define CONFIG_AML_LCD_EXTERN 1
+
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_PHY_20 0xff636000
+ #define CONFIG_USB_PHY_21 0xff63A000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_V2 1
+ #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6)
+ #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6"
+ //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+#define CONFIG_USB_DEVICE_V2 1
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "u211"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_LOADB 1
+
+//#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+/* Choose One of Ethernet Type */
+#undef CONFIG_ETHERNET_NONE
+#define ETHERNET_INTERNAL_PHY
+#undef ETHERNET_EXTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/g12a_u212_v1.h b/board/amlogic/configs/g12a_u212_v1.h
new file mode 100755
index 0000000..f6dd1d6
--- /dev/null
+++ b/board/amlogic/configs/g12a_u212_v1.h
@@ -0,0 +1,604 @@
+
+/*
+ * board/amlogic/configs/g12a_u212_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __G12A_U212_V1_H__
+#define __G12A_U212_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 772 // VDDEE suspend voltage
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#define CONFIG_CMD_BOOTCTOL_AVB
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "lock=10001000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} ${fs_type} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "boot_cooling;"\
+ "get_system_as_root_mode;"\
+ "echo system_mode: ${system_mode};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv fs_type ""ro rootwait skip_initramfs"";"\
+ "run storeargs;"\
+ "fi;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "hdmitx hpd;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+//SKT 1024 pages only support 4 block, so 4 copies
+#define CONFIG_BL2_COPY_NUM 4
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+//#define CONFIG_AML_GPT
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL
+ #define CONFIG_SPI_FLASH_EON
+ #define CONFIG_SPI_FLASH_GIGADEVICE
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION
+ #define CONFIG_SPI_FLASH_STMICRO
+ #define CONFIG_SPI_FLASH_SST
+ #define CONFIG_SPI_FLASH_WINBOND
+ #define CONFIG_SPI_FRAM_RAMTRON
+ #define CONFIG_SPI_M95XXX
+ #define CONFIG_SPI_FLASH_ESMT
+ /* SPI nand flash support */
+ #define CONFIG_SPI_NAND
+ #define CONFIG_BL2_SIZE (64 * 1024)
+#endif
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE y
+ #define CONFIG_RBTREE
+ #define CONFIG_CMD_NAND_TORTURE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+ #define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+// #define CONFIG_AML_LCD 1
+// #define CONFIG_AML_LCD_TABLET 1
+// #define CONFIG_AML_LCD_EXTERN 1
+
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_PHY_20 0xff636000
+ #define CONFIG_USB_PHY_21 0xff63A000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_V2 1
+ #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6)
+ #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6"
+ //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+#define CONFIG_USB_DEVICE_V2 1
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "u212"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+/* I2C DM driver*/
+//#define CONFIG_DM_I2C
+
+#if defined(CONFIG_DM_I2C)
+#define CONFIG_SYS_I2C_MESON 1
+#else
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+#endif
+
+#define CONFIG_EFUSE 1
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_LOADB 1
+
+//#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+/* Choose One of Ethernet Type */
+#undef CONFIG_ETHERNET_NONE
+#define ETHERNET_INTERNAL_PHY
+#undef ETHERNET_EXTERNAL_PHY
+
+#define CONFIG_HIGH_TEMP_COOL 90
+#endif
+
diff --git a/board/amlogic/configs/g12a_u220_v1.h b/board/amlogic/configs/g12a_u220_v1.h
new file mode 100755
index 0000000..ecd4ce1
--- /dev/null
+++ b/board/amlogic/configs/g12a_u220_v1.h
@@ -0,0 +1,601 @@
+
+/*
+ * board/amlogic/configs/g12a_u220_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __G12A_U220_V1_H__
+#define __G12A_U220_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 772 // VDDEE suspend voltage
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#define CONFIG_CMD_BOOTCTOL_AVB
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} ${fs_type} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "boot_cooling;"\
+ "get_system_as_root_mode;"\
+ "echo system_mode: ${system_mode};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv fs_type ""ro rootwait skip_initramfs"";"\
+ "run storeargs;"\
+ "fi;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "hdmitx hpd;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+//SKT 1024 pages only support 4 block, so 4 copies
+#define CONFIG_BL2_COPY_NUM 4
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+//#define CONFIG_AML_GPT
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL
+ #define CONFIG_SPI_FLASH_EON
+ #define CONFIG_SPI_FLASH_GIGADEVICE
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION
+ #define CONFIG_SPI_FLASH_STMICRO
+ #define CONFIG_SPI_FLASH_SST
+ #define CONFIG_SPI_FLASH_WINBOND
+ #define CONFIG_SPI_FRAM_RAMTRON
+ #define CONFIG_SPI_M95XXX
+ #define CONFIG_SPI_FLASH_ESMT
+ /* SPI nand flash support */
+ #define CONFIG_SPI_NAND
+ #define CONFIG_BL2_SIZE (64 * 1024)
+#endif
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE y
+ #define CONFIG_RBTREE
+ #define CONFIG_CMD_NAND_TORTURE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+ #define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+// #define CONFIG_AML_LCD 1
+// #define CONFIG_AML_LCD_TABLET 1
+// #define CONFIG_AML_LCD_EXTERN 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_PHY_20 0xff636000
+ #define CONFIG_USB_PHY_21 0xff63A000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_V2 1
+ #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6)
+ #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6"
+ //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+#define CONFIG_USB_DEVICE_V2 1
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "u220"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+/* I2C DM driver*/
+//#define CONFIG_DM_I2C
+
+#if defined(CONFIG_DM_I2C)
+#define CONFIG_SYS_I2C_MESON 1
+#else
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+#endif
+
+#define CONFIG_EFUSE 1
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_LOADB 1
+
+//#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+/* Choose One of Ethernet Type */
+#undef CONFIG_ETHERNET_NONE
+#undef ETHERNET_INTERNAL_PHY
+#define ETHERNET_EXTERNAL_PHY
+
+#define CONFIG_HIGH_TEMP_COOL 90
+#endif
+
diff --git a/board/amlogic/configs/g12a_u221_v1.h b/board/amlogic/configs/g12a_u221_v1.h
new file mode 100755
index 0000000..6266e4c
--- /dev/null
+++ b/board/amlogic/configs/g12a_u221_v1.h
@@ -0,0 +1,602 @@
+
+/*
+ * board/amlogic/configs/g12a_u221_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __G12A_U221_V1_H__
+#define __G12A_U221_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 772 // VDDEE suspend voltage
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#define CONFIG_CMD_BOOTCTOL_AVB
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "lock=10001000\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} ${fs_type} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "boot_cooling;"\
+ "get_system_as_root_mode;"\
+ "echo system_mode: ${system_mode};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv fs_type ""ro rootwait skip_initramfs"";"\
+ "run storeargs;"\
+ "fi;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "hdmitx hpd;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+//SKT 1024 pages only support 4 block, so 4 copies
+#define CONFIG_BL2_COPY_NUM 4
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+//#define CONFIG_AML_GPT
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL
+ #define CONFIG_SPI_FLASH_EON
+ #define CONFIG_SPI_FLASH_GIGADEVICE
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION
+ #define CONFIG_SPI_FLASH_STMICRO
+ #define CONFIG_SPI_FLASH_SST
+ #define CONFIG_SPI_FLASH_WINBOND
+ #define CONFIG_SPI_FRAM_RAMTRON
+ #define CONFIG_SPI_M95XXX
+ #define CONFIG_SPI_FLASH_ESMT
+ /* SPI nand flash support */
+ #define CONFIG_SPI_NAND
+ #define CONFIG_BL2_SIZE (64 * 1024)
+#endif
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE y
+ #define CONFIG_RBTREE
+ #define CONFIG_CMD_NAND_TORTURE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+ #define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+//#define CONFIG_AML_CVBS 1
+#endif
+
+// #define CONFIG_AML_LCD 1
+// #define CONFIG_AML_LCD_TABLET 1
+// #define CONFIG_AML_LCD_EXTERN 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_PHY_20 0xff636000
+ #define CONFIG_USB_PHY_21 0xff63A000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_V2 1
+ #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6)
+ #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6"
+ //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+#define CONFIG_USB_DEVICE_V2 1
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "u221"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+/* I2C DM driver*/
+//#define CONFIG_DM_I2C
+
+#if defined(CONFIG_DM_I2C)
+#define CONFIG_SYS_I2C_MESON 1
+#else
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+#endif
+
+#define CONFIG_EFUSE 1
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_LOADB 1
+
+//#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+/* Choose One of Ethernet Type */
+#define CONFIG_ETHERNET_NONE
+#undef ETHERNET_INTERNAL_PHY
+#undef ETHERNET_EXTERNAL_PHY
+
+#define CONFIG_HIGH_TEMP_COOL 90
+#endif
+
diff --git a/board/amlogic/configs/g12b_skt_v1.h b/board/amlogic/configs/g12b_skt_v1.h
new file mode 100755
index 0000000..cfab14e
--- /dev/null
+++ b/board/amlogic/configs/g12b_skt_v1.h
@@ -0,0 +1,601 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __G12B_SKT_V1_H__
+#define __G12B_SKT_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 772 // VDDEE suspend voltage
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+#define CONFIG_SARADC_CH 2
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "lock=10001000\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} ${fs_type} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "boot_cooling;"\
+ "get_system_as_root_mode;"\
+ "echo system_mode: ${system_mode};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv fs_type ""ro rootwait skip_initramfs"";"\
+ "run storeargs;"\
+ "fi;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "hdmitx hpd;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+//SKT 1024 pages only support 4 block, so 4 copies
+#define CONFIG_BL2_COPY_NUM 4
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+//#define CONFIG_AML_GPT
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL
+ #define CONFIG_SPI_FLASH_EON
+ #define CONFIG_SPI_FLASH_GIGADEVICE
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION
+ #define CONFIG_SPI_FLASH_STMICRO
+ #define CONFIG_SPI_FLASH_SST
+ #define CONFIG_SPI_FLASH_WINBOND
+ #define CONFIG_SPI_FRAM_RAMTRON
+ #define CONFIG_SPI_M95XXX
+ #define CONFIG_SPI_FLASH_ESMT
+ /* SPI nand flash support */
+ #define CONFIG_SPI_NAND
+ #define CONFIG_BL2_SIZE (64 * 1024)
+#endif
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE y
+ #define CONFIG_RBTREE
+ #define CONFIG_CMD_NAND_TORTURE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+ #define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN 1
+
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_PHY_20 0xff636000
+ #define CONFIG_USB_PHY_21 0xff63A000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_V2 1
+ #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6)
+ #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6"
+ //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+#define CONFIG_USB_DEVICE_V2 1
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F69E5
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "g12b_skt"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+/* I2C DM driver*/
+//#define CONFIG_DM_I2C
+#if defined(CONFIG_DM_I2C)
+#define CONFIG_SYS_I2C_MESON 1
+#else
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+#endif
+#define CONFIG_EFUSE 1
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_PLLTEST 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_LOADB 1
+
+//#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+/* Choose One of Ethernet Type */
+#undef CONFIG_ETHERNET_NONE
+#define ETHERNET_INTERNAL_PHY
+#undef ETHERNET_EXTERNAL_PHY
+
+#define CONFIG_HIGH_TEMP_COOL 90
+#endif
+
diff --git a/board/amlogic/configs/g12b_w400_v1.h b/board/amlogic/configs/g12b_w400_v1.h
new file mode 100755
index 0000000..bdcf4b8
--- /dev/null
+++ b/board/amlogic/configs/g12b_w400_v1.h
@@ -0,0 +1,602 @@
+
+/*
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __G12B_W400_V1_H__
+#define __G12B_W400_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 772 // VDDEE suspend voltage
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+#define CONFIG_SARADC_CH 2
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "lock=10001000\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} ${fs_type} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "boot_cooling;"\
+ "get_system_as_root_mode;"\
+ "echo system_mode: ${system_mode};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv fs_type ""ro rootwait skip_initramfs"";"\
+ "run storeargs;"\
+ "fi;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "hdmitx hpd;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "forceupdate;" \
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+//SKT 1024 pages only support 4 block, so 4 copies
+#define CONFIG_BL2_COPY_NUM 4
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+//#define CONFIG_AML_GPT
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL
+ #define CONFIG_SPI_FLASH_EON
+ #define CONFIG_SPI_FLASH_GIGADEVICE
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION
+ #define CONFIG_SPI_FLASH_STMICRO
+ #define CONFIG_SPI_FLASH_SST
+ #define CONFIG_SPI_FLASH_WINBOND
+ #define CONFIG_SPI_FRAM_RAMTRON
+ #define CONFIG_SPI_M95XXX
+ #define CONFIG_SPI_FLASH_ESMT
+ /* SPI nand flash support */
+ #define CONFIG_SPI_NAND
+ #define CONFIG_BL2_SIZE (64 * 1024)
+#endif
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE y
+ #define CONFIG_RBTREE
+ #define CONFIG_CMD_NAND_TORTURE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+ #define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+//#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN 1
+
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_PHY_20 0xff636000
+ #define CONFIG_USB_PHY_21 0xff63A000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_V2 1
+ #define CONFIG_USB_GPIO_PWR GPIOEE(GPIOH_6)
+ #define CONFIG_USB_GPIO_PWR_NAME "GPIOH_6"
+ //#define CONFIG_USB_XHCI_AMLOGIC_USB3_V2 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+#define CONFIG_USB_DEVICE_V2 1
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F69E5
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "g12b_w400"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+/* I2C DM driver*/
+//#define CONFIG_DM_I2C
+#if defined(CONFIG_DM_I2C)
+#define CONFIG_SYS_I2C_MESON 1
+#else
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+#endif
+#define CONFIG_EFUSE 1
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_PLLTEST 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_LOADB 1
+
+//#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+/* Choose One of Ethernet Type */
+#undef CONFIG_ETHERNET_NONE
+#define ETHERNET_INTERNAL_PHY
+#undef ETHERNET_EXTERNAL_PHY
+
+#define CONFIG_HIGH_TEMP_COOL 90
+#endif
+
diff --git a/board/amlogic/configs/gxb_p200_v1.h b/board/amlogic/configs/gxb_p200_v1.h
new file mode 100644
index 0000000..377ca7f
--- /dev/null
+++ b/board/amlogic/configs/gxb_p200_v1.h
@@ -0,0 +1,458 @@
+
+/*
+ * board/amlogic/configs/gxb_p200_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXB_P200_V1_H__
+#define __GXB_P200_V1_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+/* bt wake up */
+#define CONFIG_BT_WAKEUP
+/* wifi wake up */
+#define CONFIG_WIFI_WAKEUP
+
+#define CONFIG_INSTABOOT
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+//for detect remote key
+#define CONFIG_IR_REMOTE 1
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0x3ac5bd02
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0"\
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "lock=10001000\0"\
+ "cvbs_drv=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} vout=${outputmode},enable hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "run try_auto_burn; "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1536 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 1024 //MB
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR3
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0_ONLY : one channel
+ * CONFIG_DDR0_RANK01_SAME : one channel use two rank with same setting
+ * CONFIG_DDR0_RANK01_DIFF : one channel use two rank with diff setting
+ * CONFIG_DDR01_SHARE_AC : two channels */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK01_SAME
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr power saving */
+#define CONFIG_DDR_ZQ_POWER_DOWN
+#define CONFIG_DDR_POWER_DOWN_PHY_VREF
+/* ddr detection */
+#define CONFIG_DDR_SIZE_AUTO_DETECT 1 //0:disable, 1:enable
+/* ddr functions */
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_AML_NAND 1
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 52000000
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_M8_USBPORT_BASE_A 0xC9000000
+ #define CONFIG_M8_USBPORT_BASE_B 0xC9100000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_DWC_OTG_HCD 1
+ #define CONFIG_USB_DWC_OTG_294 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p200"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_MULTI_DTB 1
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+#endif
+
diff --git a/board/amlogic/configs/gxb_p201_v1.h b/board/amlogic/configs/gxb_p201_v1.h
new file mode 100644
index 0000000..b007bb6
--- /dev/null
+++ b/board/amlogic/configs/gxb_p201_v1.h
@@ -0,0 +1,443 @@
+
+/*
+ * board/amlogic/configs/gxb_p201_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXB_P201_V1_H__
+#define __GXB_P201_V1_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#define CONFIG_INSTABOOT
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+//#define CONFIG_IR_REMOTE
+//#define CONFIG_AML_IRDETECT_EARLY
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0x3ac5bd02
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=apee\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0"\
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "lock=10001000\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} vout=${outputmode},enable hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "run try_auto_burn; "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; sleep 5; run update;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1536 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 1024 //MB
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR3
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0_ONLY : one channel
+ * CONFIG_DDR0_RANK01_SAME : one channel use two rank with same setting
+ * CONFIG_DDR0_RANK01_DIFF : one channel use two rank with diff setting
+ * CONFIG_DDR01_SHARE_AC : two channels */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK01_SAME
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr power saving */
+#define CONFIG_DDR_ZQ_POWER_DOWN
+#define CONFIG_DDR_POWER_DOWN_PHY_VREF
+/* ddr detection */
+#define CONFIG_DDR_SIZE_AUTO_DETECT 0 //0:disable, 1:enable
+/* ddr functions */
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_AML_NAND 1
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 52000000
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_M8_USBPORT_BASE_A 0xC9000000
+ #define CONFIG_M8_USBPORT_BASE_B 0xC9100000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_DWC_OTG_HCD 1
+ #define CONFIG_USB_DWC_OTG_294 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p201"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+#endif
+
diff --git a/board/amlogic/configs/gxb_skt_v1.h b/board/amlogic/configs/gxb_skt_v1.h
new file mode 100644
index 0000000..6e4f7bb
--- /dev/null
+++ b/board/amlogic/configs/gxb_skt_v1.h
@@ -0,0 +1,286 @@
+
+/*
+ * board/amlogic/configs/gxb_skt_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXB_SKT_V1_H__
+#define __GXB_SKT_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 3
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0x3ac5bd02
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "storeboot=\0"
+#define CONFIG_BOOTARGS "init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1536 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 1024 //MB
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR3
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0_ONLY : one channel
+ * CONFIG_DDR0_RANK01_SAME : one channel use two rank with same setting
+ * CONFIG_DDR0_RANK01_DIFF : one channel use two rank with diff setting
+ * CONFIG_DDR01_SHARE_AC : two channels */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK01_SAME
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr power saving */
+#define CONFIG_DDR_ZQ_POWER_DOWN
+#define CONFIG_DDR_POWER_DOWN_PHY_VREF
+/* ddr detection */
+#define CONFIG_DDR_SIZE_AUTO_DETECT 0 //0:disable, 1:enable
+/* ddr functions */
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_AML_NAND 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 52000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL // to test
+ #define CONFIG_SPI_FLASH_EON // to test
+ #define CONFIG_SPI_FLASH_GIGADEVICE // to test
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION // to test
+ #define CONFIG_SPI_FLASH_STMICRO // to test
+ #define CONFIG_SPI_FLASH_SST // to test
+ #define CONFIG_SPI_FLASH_WINBOND // to test
+ #define CONFIG_SPI_FRAM_RAMTRON // to add & test
+ #define CONFIG_SPI_M95XXX // to add & test
+ #define CONFIG_SPI_FLASH_ESMT // to add & test
+#endif
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_M8_USBPORT_BASE_A 0xC9000000
+ #define CONFIG_M8_USBPORT_BASE_B 0xC9100000
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_DWC_OTG_HCD 1
+ #define CONFIG_USB_DWC_OTG_294 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "gxbb_skt"
+#define CONFIG_AML_V2_FACTORY_BURN 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_JTAG 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+/* ddr dump function defines */
+//#define CONFIG_SPL_DDR_DUMP 1
+#ifdef CONFIG_SPL_DDR_DUMP
+ #define CONFIG_SPL_DDR_DUMP_ADDR 0x01000000
+ #define CONFIG_SPL_DDR_DUMP_SIZE 0x00200000
+ #define CONFIG_SPL_DDR_DUMP_DEV_TYPE 0x4 //device type, 1:emmc, 4:sd
+ #define CONFIG_SPL_DDR_DUMP_DEV_OFFSET 0x40000000 //offset of store device
+ #define CONFIG_SPL_DDR_DUMP_FLAG 0x1 //flag write in sticky reg
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+
+#endif
+
diff --git a/board/amlogic/configs/gxl_estelle_p0.h b/board/amlogic/configs/gxl_estelle_p0.h
new file mode 100644
index 0000000..1a53e5a
--- /dev/null
+++ b/board/amlogic/configs/gxl_estelle_p0.h
@@ -0,0 +1,556 @@
+
+/*
+ * board/amlogic/configs/gxl_estelle_p0.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXL_ESTELLE_P0_H__
+#define __GXL_ESTELLE_P0_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1120
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+/* configs for dtb in boot.img */
+//#define DTB_BIND_KERNEL
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/*config irblaster*/
+#define CONFIG_CMD_IRBLASTER 1
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/*a/b update */
+#define CONFIG_CMD_BOOTCTOL_AVB
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+//#define CONFIG_IR_REMOTE
+//#define CONFIG_AML_IRDETECT_EARLY
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0"\
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "rpmb_state=0\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyUSB0,115200 console=ttyS0,115200 no_console_suspend earlycon=aml_uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 mtdblock.ro_fspart=\"system\" "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.veritymode=enforcing androidboot.hardware=estelle-p0;"\
+ "setenv bootargs ${bootargs} androidboot.rpmb_state=${rpmb_state};"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "else if test ${reboot_mode} = factory_boot; then "\
+ "if imgread kernel cache ${loadaddr}; then "\
+ "bootm ${loadaddr}; fi;"\
+ "fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_2; then "\
+ "echo detect upgrade key; sleep 3;"\
+ "if gpio input GPIOAO_2; then run update; fi;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_SHORT_RSV 1
+#define RESERVED_BLOCK_NUM 48
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR_CHL_AUTO
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+#define CONFIG_BL2_COPY_NUM 8
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+
+
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+ /*
+ flash/erase operation region on boot1
+ in bytes, 2M by default
+ */
+ //#define CONFIG_EMMC_BOOT1_TOUCH_REGION (0x200000)
+
+#endif
+/* storage macro checks */
+#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND)
+#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled.
+#endif
+
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+
+
+/* env checks */
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_AML_MTD
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1
+#endif
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "estelle"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#ifndef DTB_BIND_KERNEL
+#define CONFIG_UNIFY_KEY_MANAGE 1
+#endif
+
+/* net */
+#undef CONFIG_CMD_NET
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_FACTORY_BOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_MULTI_DTB 1
+
+#define CONFIG_CMD_CHIPID 1
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#undef CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/gxl_p212_v1.h b/board/amlogic/configs/gxl_p212_v1.h
new file mode 100755
index 0000000..e95fdba
--- /dev/null
+++ b/board/amlogic/configs/gxl_p212_v1.h
@@ -0,0 +1,538 @@
+
+/*
+ * board/amlogic/configs/gxl_p212_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXL_P212_V1_H__
+#define __GXL_P212_V1_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1120
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+//#define CONFIG_BT_WAKEUP
+#define CONFIG_INSTABOOT
+/* configs for dtb in boot.img */
+//#define DTB_BIND_KERNEL
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/*config irblaster*/
+#define CONFIG_CMD_IRBLASTER 1
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/*a/b update */
+#define CONFIG_CMD_BOOTCTOL_AVB
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+//#define CONFIG_IR_REMOTE
+//#define CONFIG_AML_IRDETECT_EARLY
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "lock=10001000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0"\
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "active_slot=_a\0"\
+ "page_trace=on\0"\
+ "boot_part=boot\0"\
+ "rpmb_state=0\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlycon=aml_uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.veritymode=enforcing androidboot.hardware=amlogic;"\
+ "setenv bootargs ${bootargs} page_trace=${page_trace};" \
+ "setenv bootargs ${bootargs} androidboot.rpmb_state=${rpmb_state};"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_2; then "\
+ "echo detect upgrade key; sleep 3;"\
+ "if gpio input GPIOAO_2; then run update; fi;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR_CHL_AUTO
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+//#define CONFIG_AML_MTD 1
+/* support for nftl */
+#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+
+
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+ /*
+ flash/erase operation region on boot1
+ in bytes, 2M by default
+ */
+ //#define CONFIG_EMMC_BOOT1_TOUCH_REGION (0x200000)
+
+#endif
+/* storage macro checks */
+#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND)
+#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled.
+#endif
+
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+
+
+/* env checks */
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_AML_MTD
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1
+#endif
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p212"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#ifndef DTB_BIND_KERNEL
+#define CONFIG_UNIFY_KEY_MANAGE 1
+#endif
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_MULTI_DTB 1
+
+#define CONFIG_CMD_CHIPID 1
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/gxl_p241_v1.h b/board/amlogic/configs/gxl_p241_v1.h
new file mode 100755
index 0000000..36daff8
--- /dev/null
+++ b/board/amlogic/configs/gxl_p241_v1.h
@@ -0,0 +1,526 @@
+
+/*
+ * board/amlogic/configs/gxl_p241_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXL_P241_V1_H__
+#define __GXL_P241_V1_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1120
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+/* configs for dtb in boot.img */
+//#define DTB_BIND_KERNEL
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+//#define CONFIG_IR_REMOTE
+//#define CONFIG_AML_IRDETECT_EARLY
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "lock=10001000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0"\
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "active_slot=_a\0"\
+ "page_trace=on\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "setenv bootargs ${bootargs} page_trace=${page_trace};" \
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel boot ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_2; then "\
+ "echo detect upgrade key; sleep 3;"\
+ "if gpio input GPIOAO_2; then run update; fi;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1000 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 1024 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 792 //MHz, for boards which use different ddr chip
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR4//CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_16BIT //CONFIG_DDR_CHL_AUTO
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_RDBI 1 //0:disable, 1:enable. low power consumption and upgrade stability
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+//#define CONFIG_AML_MTD 1
+/* support for nftl */
+#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+
+
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+/* storage macro checks */
+#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND)
+#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled.
+#endif
+
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+
+
+/* env checks */
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 2
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_AML_MTD
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1
+#endif
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p241"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#ifndef DTB_BIND_KERNEL
+#define CONFIG_UNIFY_KEY_MANAGE 1
+#endif
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_MULTI_DTB 1
+
+#define CONFIG_CMD_CHIPID 1
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/gxl_p271_v1.h b/board/amlogic/configs/gxl_p271_v1.h
new file mode 100755
index 0000000..d21445c
--- /dev/null
+++ b/board/amlogic/configs/gxl_p271_v1.h
@@ -0,0 +1,526 @@
+
+/*
+ * board/amlogic/configs/gxl_p271_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXL_P271_V1_H__
+#define __GXL_P271_V1_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1120
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+/* configs for dtb in boot.img */
+//#define DTB_BIND_KERNEL
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/*config irblaster*/
+#define CONFIG_CMD_IRBLASTER 1
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+//#define CONFIG_IR_REMOTE
+//#define CONFIG_AML_IRDETECT_EARLY
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "lock=10001000\0"\
+ "EnableSelinux=enforcing\0"\
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlycon=aml_uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_2; then "\
+ "echo detect upgrade key; sleep 3;"\
+ "if gpio input GPIOAO_2; then run update; fi;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 792 //MHz, for boards which use different ddr chip
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR_CHL_AUTO
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+//#define CONFIG_AML_MTD 1
+/* support for nftl */
+#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+
+
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+/* storage macro checks */
+#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND)
+#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled.
+#endif
+
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+
+
+/* env checks */
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_AML_MTD
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1
+#endif
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p271"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#ifndef DTB_BIND_KERNEL
+#define CONFIG_UNIFY_KEY_MANAGE 1
+#endif
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_MULTI_DTB 1
+
+#define CONFIG_CMD_CHIPID 1
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/gxl_p281_v1.h b/board/amlogic/configs/gxl_p281_v1.h
new file mode 100755
index 0000000..3e58899
--- /dev/null
+++ b/board/amlogic/configs/gxl_p281_v1.h
@@ -0,0 +1,526 @@
+
+/*
+ * board/amlogic/configs/gxl_p281_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXL_P281_V1_H__
+#define __GXL_P281_V1_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1120
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+/* configs for dtb in boot.img */
+//#define DTB_BIND_KERNEL
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/*config irblaster*/
+#define CONFIG_CMD_IRBLASTER 1
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+//#define CONFIG_IR_REMOTE
+//#define CONFIG_AML_IRDETECT_EARLY
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0"\
+ "recovery_part=recovery\0"\
+ "lock=10001000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_2; then "\
+ "echo detect upgrade key; sleep 3;"\
+ "if gpio input GPIOAO_2; then run update; fi;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 1024 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR3//CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_16BIT//CONFIG_DDR_CHL_AUTO
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+
+#define X4_DDR3 2
+#define CONFIG_DDR_REMAP_SET X4_DDR3
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+//#define CONFIG_AML_MTD 1
+/* support for nftl */
+#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+
+
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+/* storage macro checks */
+#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND)
+#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled.
+#endif
+
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+
+
+/* env checks */
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_AML_MTD
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1
+#endif
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p281"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#ifndef DTB_BIND_KERNEL
+#define CONFIG_UNIFY_KEY_MANAGE 1
+#endif
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_MULTI_DTB 1
+
+#define CONFIG_CMD_CHIPID 1
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/gxl_p400_v1.h b/board/amlogic/configs/gxl_p400_v1.h
new file mode 100755
index 0000000..617da8e
--- /dev/null
+++ b/board/amlogic/configs/gxl_p400_v1.h
@@ -0,0 +1,520 @@
+
+/*
+ * board/amlogic/configs/gxl_p400_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXM_Q200_V1_H__
+#define __GXM_Q200_V1_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCKA_INIT_VOLTAGE 1120 // cluster_0 Big cpu
+#define CONFIG_VCCKB_INIT_VOLTAGE 1050 // cluster_1 Little cpu
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#define CONFIG_CMD_SARADC 1
+#define CONFIG_SARADC_CH 0
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+//#define CONFIG_IR_REMOTE
+//#define CONFIG_AML_IRDETECT_EARLY
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "lock=10001000\0"\
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0"\
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "root=/dev/system rw rootfstype=ext4 rootwait init=/sbin/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} androidboot.selinux=${EnableSelinux} maxcpus=${maxcpus} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_2; then "\
+ "echo detect upgrade key; sleep 3;"\
+ "if gpio input GPIOAO_2; then run update; fi;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "forceupdate;" \
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK01
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+//#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+/* storage macro checks */
+#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND)
+#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled.
+#endif
+
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+
+
+/* env checks */
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_AML_MTD
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1
+#endif
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "q200"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_CHIPID 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+//#define CONFIG_INTERNAL_PHY
+#define CONFIG_EXTERNAL_PHY
+#endif
+
diff --git a/board/amlogic/configs/gxl_p401_v1.h b/board/amlogic/configs/gxl_p401_v1.h
new file mode 100755
index 0000000..9467c43
--- /dev/null
+++ b/board/amlogic/configs/gxl_p401_v1.h
@@ -0,0 +1,537 @@
+
+/*
+ * board/amlogic/configs/gxm_q200_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXM_Q200_V1_H__
+#define __GXM_Q200_V1_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCKA_INIT_VOLTAGE 1120 // cluster_0 Big cpu
+#define CONFIG_VCCKB_INIT_VOLTAGE 1050 // cluster_1 Little cpu
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#define CONFIG_CMD_SARADC 1
+#define CONFIG_SARADC_CH 0
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+//#define CONFIG_IR_REMOTE
+//#define CONFIG_AML_IRDETECT_EARLY
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "lock=10001000\0"\
+ "EnableSelinux=enforcing\0"\
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlycon=aml_uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} pq=${pq} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_2; then "\
+ "echo detect upgrade key; sleep 3;"\
+ "if gpio input GPIOAO_2; then run update; fi;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "forceupdate;" \
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK01
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+/* storage macro checks */
+#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND)
+#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled.
+#endif
+
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+
+
+/* env checks */
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#define CONFIG_DISCRETE_BOOTLOADER
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+#define CONFIG_BL2_COPY_NUM 8
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1
+#endif
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "q200"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_CHIPID 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+//#define CONFIG_INTERNAL_PHY
+#define CONFIG_EXTERNAL_PHY
+#endif
+
diff --git a/board/amlogic/configs/gxl_s905x_p0.h b/board/amlogic/configs/gxl_s905x_p0.h
new file mode 100644
index 0000000..c0d7fb3
--- /dev/null
+++ b/board/amlogic/configs/gxl_s905x_p0.h
@@ -0,0 +1,542 @@
+
+/*
+ * board/amlogic/configs/gxl_s905x_p0.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXL_S905X_P0_H__
+#define __GXL_S905X_P0_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1120
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+/* configs for dtb in boot.img */
+//#define DTB_BIND_KERNEL
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/*config irblaster*/
+#define CONFIG_CMD_IRBLASTER 1
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/*a/b update */
+#define CONFIG_CMD_BOOTCTOL_AVB
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+//#define CONFIG_IR_REMOTE
+//#define CONFIG_AML_IRDETECT_EARLY
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0"\
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "rpmb_state=0\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyUSB0,115200 console=ttyS0,115200 no_console_suspend earlycon=aml_uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.veritymode=enforcing androidboot.hardware=s905x-p0;"\
+ "setenv bootargs ${bootargs} androidboot.rpmb_state=${rpmb_state};"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "switch_bootpart="\
+ "mmc dev 1;"\
+ "if ext4ls mmc 1:c /recovery_mode; then "\
+ "setenv boot_part recovery;"\
+ "else "\
+ "setenv boot_part boot;"\
+ "fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_2; then "\
+ "echo detect upgrade key; sleep 3;"\
+ "if gpio input GPIOAO_2; then run update; fi;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "run switch_bootmode;" \
+ "run switch_bootpart;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR_CHL_AUTO
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+//#define CONFIG_AML_MTD 1
+/* support for nftl */
+#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+
+
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+ /*
+ flash/erase operation region on boot1
+ in bytes, 2M by default
+ */
+ //#define CONFIG_EMMC_BOOT1_TOUCH_REGION (0x200000)
+
+#endif
+/* storage macro checks */
+#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND)
+#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled.
+#endif
+
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+
+
+/* env checks */
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_AML_MTD
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1
+#endif
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "s905x"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#ifndef DTB_BIND_KERNEL
+#define CONFIG_UNIFY_KEY_MANAGE 1
+#endif
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_MULTI_DTB 1
+
+#define CONFIG_CMD_CHIPID 1
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/gxl_skt_v1.h b/board/amlogic/configs/gxl_skt_v1.h
new file mode 100644
index 0000000..38ec5b9
--- /dev/null
+++ b/board/amlogic/configs/gxl_skt_v1.h
@@ -0,0 +1,505 @@
+
+/*
+ * board/amlogic/configs/gxl_skt_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXL_SKT_V1_H__
+#define __GXL_SKT_V1_H__
+
+#include <asm/arch/cpu.h>
+
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1100 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 4 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rc5
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 3
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0"\
+ "lock=10001000\0"\
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "active_slot=_a\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel boot ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1024 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 792 //MHz, for boards which use different ddr chip
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR_CHL_AUTO
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 1 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_AML_NAND 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL // to test
+ #define CONFIG_SPI_FLASH_EON // to test
+ #define CONFIG_SPI_FLASH_GIGADEVICE // to test
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION // to test
+ #define CONFIG_SPI_FLASH_STMICRO // to test
+ #define CONFIG_SPI_FLASH_SST // to test
+ #define CONFIG_SPI_FLASH_WINBOND // to test
+ #define CONFIG_SPI_FRAM_RAMTRON // to add & test
+ #define CONFIG_SPI_M95XXX // to add & test
+ #define CONFIG_SPI_FLASH_ESMT // to add & test
+#endif
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "gxl_skt"
+
+/* To support eMMC booting */
+#define CONFIG_FASTBOOT_FLASH 1
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+/* ddr dump function defines */
+//#define CONFIG_SPL_DDR_DUMP 1
+#ifdef CONFIG_SPL_DDR_DUMP
+ #define CONFIG_SPL_DDR_DUMP_ADDR 0x01000000
+ #define CONFIG_SPL_DDR_DUMP_SIZE 0x00200000
+ #define CONFIG_SPL_DDR_DUMP_DEV_TYPE 0x4 //device type, 1:emmc, 4:sd
+ #define CONFIG_SPL_DDR_DUMP_DEV_OFFSET 0x40000000 //offset of store device
+ #define CONFIG_SPL_DDR_DUMP_FLAG 0x1 //flag write in sticky reg
+#endif
+
+//2017.05.11 new compress solution, only support BL33 LZ4 compress
+//compress ratio is about 50%, BL31 will take the decompress
+//profit :
+// size : u-boot.bin 1.2MB -> 913KB
+// boot time decrease: SD boot: ~100ms ; eMMC boot: 50ms
+//default: enable the data compress feature
+//to disable the data compress please just define followings
+//#undef CONFIG_AML_BL33_COMPRESS_ENABLE
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+//#define CONFIG_AML_SECURE_BOOT_V3 1
+
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/gxm_q200_v1.h b/board/amlogic/configs/gxm_q200_v1.h
new file mode 100644
index 0000000..53ce022
--- /dev/null
+++ b/board/amlogic/configs/gxm_q200_v1.h
@@ -0,0 +1,523 @@
+
+/*
+ * board/amlogic/configs/gxm_q200_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXM_Q200_V1_H__
+#define __GXM_Q200_V1_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCKA_INIT_VOLTAGE 1120 // cluster_0 Big cpu
+#define CONFIG_VCCKB_INIT_VOLTAGE 1050 // cluster_1 Little cpu
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#define CONFIG_CMD_SARADC 1
+#define CONFIG_SARADC_CH 0
+
+/*a/b update */
+/*#define CONFIG_CMD_BOOTCTOL_DEFAULT 1*/
+#define CONFIG_CMD_BOOTCTOL_AVB
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+//#define CONFIG_IR_REMOTE
+//#define CONFIG_AML_IRDETECT_EARLY
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0"\
+ "recovery_part=recovery\0"\
+ "lock=10001000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} pq=${pq} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.veritymode=enforcing androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_2; then "\
+ "echo detect upgrade key; sleep 3;"\
+ "if gpio input GPIOAO_2; then run update; fi;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "forceupdate;" \
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK01
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+//#define CONFIG_AML_MTD 1
+/* support for nftl */
+//#define CONFIG_AML_NAND 1
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
+#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIFG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_MTD_PARTITIONS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+/* storage macro checks */
+#if defined(CONFIG_AML_MTD) && defined(CONFIG_AML_NAND)
+#error mtd/nftl are mutually-exclusive, only 1 nand driver can be enabled.
+#endif
+
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+
+
+/* env checks */
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#ifdef CONFIG_AML_MTD
+#define CONFIG_FASTBOOT_FLASH_NAND_DEV 1
+#endif
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_CMD_CHIPID 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+//#define CONFIG_INTERNAL_PHY
+#define CONFIG_EXTERNAL_PHY
+#endif
+
diff --git a/board/amlogic/configs/gxm_q201_v1.h b/board/amlogic/configs/gxm_q201_v1.h
new file mode 100644
index 0000000..34ac1a4
--- /dev/null
+++ b/board/amlogic/configs/gxm_q201_v1.h
@@ -0,0 +1,464 @@
+
+/*
+ * board/amlogic/configs/gxm_q201_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXM_Q201_V1_H__
+#define __GXM_Q201_V1_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCKA_INIT_VOLTAGE 1120 // cluster_0 Big cpu
+#define CONFIG_VCCKB_INIT_VOLTAGE 1050 // cluster_1 Little cpu
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#define CONFIG_CMD_SARADC 1
+#define CONFIG_SARADC_CH 0
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+//#define CONFIG_IR_REMOTE
+//#define CONFIG_AML_IRDETECT_EARLY
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0"\
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "active_slot=_a\0"\
+ "lock=10001000\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} androidboot.selinux=${EnableSelinux} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} pq=${pq} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_2; then "\
+ "echo detect upgrade key; sleep 3;"\
+ "if gpio input GPIOAO_2; then run update; fi;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "forceupdate;" \
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR_CHL_AUTO
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_AML_NAND 1
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/gxm_skt_v1.h b/board/amlogic/configs/gxm_skt_v1.h
new file mode 100644
index 0000000..6f3e7f9
--- /dev/null
+++ b/board/amlogic/configs/gxm_skt_v1.h
@@ -0,0 +1,492 @@
+
+/*
+ * board/amlogic/configs/gxm_skt_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXM_SKT_V1_H__
+#define __GXM_SKT_V1_H__
+
+#ifndef __SUSPEND_FIRMWARE__
+#include <asm/arch/cpu.h>
+#endif /* for compile problem of A53 and m3 */
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef __SUSPEND_FIRMWARE__
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+#endif /* for compile problem of A53 and m3 */
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCKA_INIT_VOLTAGE 1120 // cluster_0 Big cpu
+#define CONFIG_VCCKB_INIT_VOLTAGE 1050 // cluster_1 Little cpu
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+//#define CONFIG_IR_REMOTE
+//#define CONFIG_AML_IRDETECT_EARLY
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 4
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:rcmm
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0XE51AFB04 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0Xffffffff //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xffffffff //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xBA45BD02
+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xffffffff
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "jtag=apee\0"\
+ "loadaddr=1080000\0"\
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "lock=10001000\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 androidboot.selinux=enforcing"\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr},${outputmode} maxcpus=${maxcpus} vout=${outputmode},enable hdmimode=${hdmimode} cvbsmode=${cvbsmode} hdmitx=${cecconfig} cvbsdrv=${cvbs_drv} pq=${pq} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_2; then "\
+ "echo detect upgrade key; sleep 3;"\
+ "if gpio input GPIOAO_2; then run update; fi;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK0
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_AML_NAND 1
+/* env */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL // to test
+ #define CONFIG_SPI_FLASH_EON // to test
+ #define CONFIG_SPI_FLASH_GIGADEVICE // to test
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION // to test
+ #define CONFIG_SPI_FLASH_STMICRO // to test
+ #define CONFIG_SPI_FLASH_SST // to test
+ #define CONFIG_SPI_FLASH_WINBOND // to test
+ #define CONFIG_SPI_FRAM_RAMTRON // to add & test
+ #define CONFIG_SPI_M95XXX // to add & test
+ #define CONFIG_SPI_FLASH_ESMT // to add & test
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "gxm_skt"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+//use hardware sha2
+//#define CONFIG_AML_HW_SHA2
+
+//use sha2 command
+//#define CONFIG_CMD_SHA2
+
+//add hardware aes
+//#define CONFIG_AML_HW_AES
+
+#endif
+
diff --git a/board/amlogic/configs/gxtvbb_9023_skt_v1.h b/board/amlogic/configs/gxtvbb_9023_skt_v1.h
new file mode 100644
index 0000000..aa635cd
--- /dev/null
+++ b/board/amlogic/configs/gxtvbb_9023_skt_v1.h
@@ -0,0 +1,310 @@
+
+/*
+ * board/amlogic/configs/gxtvbb_9023_skt_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXTVBB_9023_SKT_V1_H__
+#define __GXTVBB_9023_SKT_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1100 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_IR_REMOTE 1
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 8
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec,toshiba 1:duokan 2:Toshiba 3:rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic nec tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0xf30cfe01 //amlogic nec tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xf20dfe01 //amlogic nec tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xe51afb04 //amlogic nec box ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xFFFFFFFF //amlogic nec tv ir --- right
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0x00f2a0d5 //tcl rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xf40b1818 //hair toshiba
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xf30c0e0e //skyworth
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=1080000\0"\
+ "dtb_mem_addr=0x1000000\0" \
+ "outputmode=1080p60hz\0" \
+ "panel_reverse=0\0" \
+ "osd_reverse=n\0" \
+ "video_reverse=n\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "fb_addr=0x3b000000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "storeargs="\
+ "setenv bootargs rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 androidboot.selinux=disabled logo=osd1,loaded,0x3b000000 vout=1080p60hz,enable hdmitx= osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.firstboot=0"\
+ "\0"\
+ "storeboot="\
+ "if imgread kernel boot ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;vout output ${outputmode};imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale"\
+ "\0"
+
+#define CONFIG_BOOTARGS "init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "
+#define CONFIG_PREBOOT \
+ "hdmitx output 1080p60hz;" \
+ "run init_display;" \
+ "run storeargs;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1536 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 2048 //MB
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR3
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_ONLY_32BIT : one channel 32bit
+ * CONFIG_DDR0_ONLY_16BIT : one channel 16bit
+ * CONFIG_DDR01_TWO_CHANNEL : two channels 32bit
+ * CONFIG_DDR01_TWO_CHANNEL_16BIT : two channels 16bit */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR01_TWO_CHANNEL
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr power saving */
+#define CONFIG_DDR_ZQ_POWER_DOWN
+#define CONFIG_DDR_POWER_DOWN_PHY_VREF
+/* ddr detection */
+#define CONFIG_DDR_SIZE_AUTO_DETECT 0 //0:disable, 1:enable
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_AML_NAND 1
+#ifdef CONFIG_AML_NAND
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL // to test
+ #define CONFIG_SPI_FLASH_EON // to test
+ #define CONFIG_SPI_FLASH_GIGADEVICE // to test
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION // to test
+ #define CONFIG_SPI_FLASH_STMICRO // to test
+ #define CONFIG_SPI_FLASH_SST // to test
+ #define CONFIG_SPI_FLASH_WINBOND // to test
+ #define CONFIG_SPI_FRAM_RAMTRON // to add & test
+ #define CONFIG_SPI_M95XXX // to add & test
+ #define CONFIG_SPI_FLASH_ESMT // to add & test
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+//#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+/* #define CONFIG_AML_LCD_TABLET 1 */
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXTVBB_XHCI_BASE 0xc9000000
+ #define CONFIG_GXTVBB_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXTVBB_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC 1
+#endif //#if defined(CONFIG_CMD_USB)
+//#define CONFIG_AML_TINY_USBTOOL 1
+#define CONFIG_AML_V2_FACTORY_BURN 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_AML_PMU4 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxtvbb
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_JTAG 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+#define CONFIG_MULTI_DTB 1
+
+/* ddr dump function defines */
+//#define CONFIG_SPL_DDR_DUMP 1
+#ifdef CONFIG_SPL_DDR_DUMP
+ #define CONFIG_SPL_DDR_DUMP_ADDR 0x01000000
+ #define CONFIG_SPL_DDR_DUMP_SIZE 0x00200000
+ #define CONFIG_SPL_DDR_DUMP_DEV_TYPE 0x4 //device type, 1:emmc, 4:sd
+ #define CONFIG_SPL_DDR_DUMP_DEV_OFFSET 0x40000000 //offset of store device
+ #define CONFIG_SPL_DDR_DUMP_FLAG 0x1 //flag write in sticky reg
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+#endif
+
diff --git a/board/amlogic/configs/gxtvbb_p300_v1.h b/board/amlogic/configs/gxtvbb_p300_v1.h
new file mode 100644
index 0000000..ce9cdaf
--- /dev/null
+++ b/board/amlogic/configs/gxtvbb_p300_v1.h
@@ -0,0 +1,487 @@
+
+/*
+ * board/amlogic/configs/gxtvbb_p300_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXTVBB_P300_V1_H__
+#define __GXTVBB_P300_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1100 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* meson SPI */
+//#define CONFIG_AML_SPIFC
+#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/*#define CONFIG_AML_LOCAL_DIMMING*/
+/*#define CONFIG_AML_LOCAL_DIMMING_IW7019*/
+/*#define CONFIG_AML_LOCAL_DIMMING_OB3350*/
+/*#define CONFIG_AML_LOCAL_DIMMING_IW7027*/
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_IR_REMOTE 1
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 8
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec,toshiba 1:duokan 2:Toshiba 3:rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic nec tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0xf30cfe01 //amlogic nec tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xf20dfe01 //amlogic nec tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xe51afb04 //amlogic nec box ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xFFFFFFFF //amlogic nec tv ir --- right
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0x00f2a0d5 //tcl rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xf40b1818 //hair toshiba
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xf30c0e0e //skyworth
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_2\0" \
+ "outputmode=1080p60hz\0" \
+ "panel_reverse=0\0" \
+ "osd_reverse=n\0" \
+ "video_reverse=n\0" \
+ "bl_off=none\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3b000000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "jtag=apao\0"\
+ "lock=10001000\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update; "\
+ "else fi; "\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs rootfstype=ramfs init=/init "\
+ "console=ttyS0,115200 no_console_suspend "\
+ "earlyprintk=aml-uart,0xc81004c0 "\
+ "androidboot.selinux=${EnableSelinux} "\
+ "logo=${display_layer},loaded,${fb_addr} "\
+ "vout=${outputmode},enable "\
+ "panel_type=${panel_type} hdmitx= "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} "\
+ "bl_off=${bl_off} "\
+ "jtag=${jtag} "\
+ "androidboot.firstboot=${firstboot}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys; "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash; "\
+ "else if test ${reboot_mode} = update; then "\
+ "run update; "\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "run try_auto_burn; "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "run update; "\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache}; "\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "fi; "\
+ "\0" \
+ "update="\
+ /*first usb burning,
+ second sdc_burn,
+ third ext-sd autoscr/recovery,
+ last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then "\
+ "autoscr ${loadaddr}; "\
+ "fi; "\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then "\
+ "echo sd dtb.img loaded; "\
+ "fi; "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then "\
+ "autoscr ${loadaddr}; "\
+ "fi; "\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then "\
+ "echo udisk dtb.img loaded; "\
+ "fi; "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if imgread kernel recovery ${loadaddr}; then "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi"\
+ "\0"\
+ "init_display="\
+ "osd open; osd clear; "\
+ "vout output ${outputmode}; "\
+ "imgread pic logo bootup $loadaddr; "\
+ "bmp display $bootup_offset; bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "androidboot.serialno=${usid}; "\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi; "\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "mac=${mac} androidboot.mac=${mac}; "\
+ "fi; "\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "androidboot.deviceid=${deviceid}; "\
+ "fi; "\
+ "fi; "\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; sleep 5; run update; "\
+ "fi; "\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect; "\
+ "run upgrade_check; "\
+ "run init_display; "\
+ "run storeargs; "\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1536 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 2048 //MB
+#define CONFIG_DDR_CLK 720 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR3
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_ONLY_32BIT : one channel 32bit
+ * CONFIG_DDR0_ONLY_16BIT : one channel 16bit
+ * CONFIG_DDR01_TWO_CHANNEL : two channels 32bit
+ * CONFIG_DDR01_TWO_CHANNEL_16BIT : two channels 16bit */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR01_TWO_CHANNEL
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_CMD_DDR_TEST 0
+#define CONFIG_DDR_CMD_BDL_TUNE
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr power saving */
+#define CONFIG_DDR_ZQ_POWER_DOWN
+#define CONFIG_DDR_POWER_DOWN_PHY_VREF
+/* ddr detection */
+#define CONFIG_DDR_SIZE_AUTO_DETECT 0 //0:disable, 1:enable
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 52000000
+#endif
+//#define CONFIG_AML_NAND 1
+#ifdef CONFIG_AML_NAND
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+// #if defined(CONFIG_AML_VOUT)
+// #define CONFIG_AML_CVBS 1
+// #endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN
+#define CONFIG_AML_LCD_EXTERN_I2C_T5800Q
+#define CONFIG_AML_LCD_EXTERN_I2C_DLPC3439
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXTVBB_XHCI_BASE 0xc9000000
+ #define CONFIG_GXTVBB_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXTVBB_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p300"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_AML_PMU4 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxtvbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+#define CONFIG_MULTI_DTB 1
+
+/* ddr dump function defines */
+//#define CONFIG_SPL_DDR_DUMP 1
+#ifdef CONFIG_SPL_DDR_DUMP
+ #define CONFIG_SPL_DDR_DUMP_ADDR 0x01000000
+ #define CONFIG_SPL_DDR_DUMP_SIZE 0x00200000
+ #define CONFIG_SPL_DDR_DUMP_DEV_TYPE 0x4 //device type, 1:emmc, 4:sd
+ #define CONFIG_SPL_DDR_DUMP_DEV_OFFSET 0x40000000 //offset of store device
+ #define CONFIG_SPL_DDR_DUMP_FLAG 0x1 //flag write in sticky reg
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+#endif
+
diff --git a/board/amlogic/configs/gxtvbb_p301_v1.h b/board/amlogic/configs/gxtvbb_p301_v1.h
new file mode 100644
index 0000000..3d7c464
--- /dev/null
+++ b/board/amlogic/configs/gxtvbb_p301_v1.h
@@ -0,0 +1,503 @@
+
+/*
+ * board/amlogic/configs/gxtvbb_p301_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXTVBB_P301_V1_H__
+#define __GXTVBB_P301_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1100 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/*#define CONFIG_AML_LOCAL_DIMMING*/
+/*#define CONFIG_AML_LOCAL_DIMMING_IW7019*/
+/*#define CONFIG_AML_LOCAL_DIMMING_OB3350*/
+/*#define CONFIG_AML_LOCAL_DIMMING_IW7027*/
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_IR_REMOTE 1
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 8
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca 4:nec||toshiba 5:nec||rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic nec tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0xf30cfe01 //amlogic nec tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xf20dfe01 //amlogic nec tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xe51afb04 //amlogic nec box ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xFFFFFFFF //amlogic nec tv ir --- right
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0x00f2a0d5 //tcl rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xf40b1818 //hair toshiba
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xf30c0e0e //skyworth
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_AML_LED
+//#define CONFIG_LED_PWM_INVERT
+#define CONFIG_CMD_LED
+#define CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+
+/* meson SPI */
+//#define CONFIG_AML_SPIFC
+#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_2\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmiuart_mode=close\0"\
+ "panel_reverse=0\0" \
+ "osd_reverse=n\0" \
+ "video_reverse=n\0" \
+ "bl_off=none\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3b000000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "jtag=apao\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "lock=10001000\0"\
+ "ledmode=standby:breath,booting:on,working:on\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update; "\
+ "else fi; "\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs rootfstype=ramfs init=/init "\
+ "console=ttyS0,115200 no_console_suspend "\
+ "earlyprintk=aml-uart,0xc81004c0 "\
+ "androidboot.selinux=${EnableSelinux} "\
+ "logo=${display_layer},loaded,${fb_addr} "\
+ "vout=${outputmode},enable "\
+ "panel_type=${panel_type} hdmitx= "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} "\
+ "bl_off=${bl_off} "\
+ "jtag=${jtag} "\
+ "ledmode=${ledmode} "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "androidboot.firstboot=${firstboot}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys; "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash; "\
+ "else if test ${reboot_mode} = update; then "\
+ "run update; "\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "run try_auto_burn; "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "run update; "\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache}; "\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "fi; "\
+ "\0" \
+ "update="\
+ /*first usb burning,
+ second sdc_burn,
+ third ext-sd autoscr/recovery,
+ last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "led 0 toggle; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then "\
+ "autoscr ${loadaddr}; "\
+ "fi; "\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then "\
+ "echo sd dtb.img loaded; "\
+ "fi; "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then "\
+ "autoscr ${loadaddr}; "\
+ "fi; "\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then "\
+ "echo udisk dtb.img loaded; "\
+ "fi; "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if imgread kernel recovery ${loadaddr}; then "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi"\
+ "\0"\
+ "init_display="\
+ "osd open; osd clear; "\
+ "vout output ${outputmode}; "\
+ "imgread pic logo bootup $loadaddr; "\
+ "bmp display $bootup_offset; bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "androidboot.serialno=${usid}; "\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi; "\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "mac=${mac} androidboot.mac=${mac}; "\
+ "fi; "\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "androidboot.deviceid=${deviceid}; "\
+ "fi; "\
+ "fi; "\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; sleep 5; run update; "\
+ "fi; "\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect; "\
+ "run upgrade_check; "\
+ "run init_display; "\
+ "run storeargs; "\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1536 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 1024 //MB
+#define CONFIG_DDR_CLK 720 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR3
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_ONLY_32BIT : one channel 32bit
+ * CONFIG_DDR0_ONLY_16BIT : one channel 16bit
+ * CONFIG_DDR01_TWO_CHANNEL : two channels 32bit
+ * CONFIG_DDR01_TWO_CHANNEL_16BIT : two channels 16bit */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR01_TWO_CHANNEL
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_CMD_DDR_TEST 0
+#define CONFIG_DDR_CMD_BDL_TUNE
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr power saving */
+#define CONFIG_DDR_ZQ_POWER_DOWN
+#define CONFIG_DDR_POWER_DOWN_PHY_VREF
+/* ddr detection */
+#define CONFIG_DDR_SIZE_AUTO_DETECT 0 //0:disable, 1:enable
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 52000000
+#endif
+//#define CONFIG_AML_NAND 1
+#ifdef CONFIG_AML_NAND
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+// #if defined(CONFIG_AML_VOUT)
+// #define CONFIG_AML_CVBS 1
+// #endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN
+#define CONFIG_AML_LCD_EXTERN_I2C_T5800Q
+#define CONFIG_AML_LCD_EXTERN_I2C_DLPC3439
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXTVBB_XHCI_BASE 0xc9000000
+ #define CONFIG_GXTVBB_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXTVBB_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p301"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_AML_PMU4 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxtvbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_HDMI_UART_BOARD 1
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+#define CONFIG_MULTI_DTB 1
+
+/* ddr dump function defines */
+//#define CONFIG_SPL_DDR_DUMP 1
+#ifdef CONFIG_SPL_DDR_DUMP
+ #define CONFIG_SPL_DDR_DUMP_ADDR 0x01000000
+ #define CONFIG_SPL_DDR_DUMP_SIZE 0x00200000
+ #define CONFIG_SPL_DDR_DUMP_DEV_TYPE 0x4 //device type, 1:emmc, 4:sd
+ #define CONFIG_SPL_DDR_DUMP_DEV_OFFSET 0x40000000 //offset of store device
+ #define CONFIG_SPL_DDR_DUMP_FLAG 0x1 //flag write in sticky reg
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+#endif
+
diff --git a/board/amlogic/configs/gxtvbb_p310_v1.h b/board/amlogic/configs/gxtvbb_p310_v1.h
new file mode 100644
index 0000000..3884696
--- /dev/null
+++ b/board/amlogic/configs/gxtvbb_p310_v1.h
@@ -0,0 +1,456 @@
+
+/*
+ * board/amlogic/configs/gxtvbb_p310_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXTVBB_P310_V1_H__
+#define __GXTVBB_P310_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1100 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_IR_REMOTE 1
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 8
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic nec tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0xf30cfe01 //amlogic nec tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xf20dfe01 //amlogic nec tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xe51afb04 //amlogic nec box ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xFFFFFFFF //amlogic nec tv ir --- right
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0x00f2a0d5 //tcl rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xf40b1818 //hair toshiba
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xf30c0e0e //skyworth
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "loadaddr=1080000\0"\
+ "dtb_mem_addr=0x1000000\0" \
+ "outputmode=1080p60hz\0" \
+ "panel_reverse=0\0" \
+ "osd_reverse=n\0" \
+ "video_reverse=n\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "fb_addr=0x3b000000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "lock=10001000\0"\
+ "EnableSelinux=enforcing\0" \
+ "jtag=apao\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update; "\
+ "else fi; "\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs rootfstype=ramfs init=/init "\
+ "console=ttyS0,115200 no_console_suspend "\
+ "earlyprintk=aml-uart,0xc81004c0 "\
+ "androidboot.selinux=${EnableSelinux} "\
+ "logo=${display_layer},loaded,${fb_addr} "\
+ "vout=${outputmode},enable "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} "\
+ "jtag=${jtag} "\
+ "androidboot.firstboot=${firstboot}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys; "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash; "\
+ "else if test ${reboot_mode} = update; then "\
+ "run update; "\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "run try_auto_burn; "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "run update; "\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache}; "\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "fi; "\
+ "\0" \
+ "update="\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then "\
+ "autoscr ${loadaddr}; "\
+ "fi; "\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then "\
+ "echo sd dtb.img loaded; "\
+ "fi; "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then "\
+ "autoscr ${loadaddr}; "\
+ "fi; "\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then "\
+ "echo udisk dtb.img loaded; "\
+ "fi; "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if imgread kernel recovery ${loadaddr}; then "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi"\
+ "\0"\
+ "init_display="\
+ "osd open; osd clear; "\
+ "vout output ${outputmode}; "\
+ "imgread pic logo bootup $loadaddr; "\
+ "bmp display $bootup_offset; bmp scale"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "androidboot.serialno=${usid}; "\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi; "\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "mac=${mac} androidboot.mac=${mac}; "\
+ "fi; "\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "androidboot.deviceid=${deviceid}; "\
+ "fi; "\
+ "fi; "\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect; "\
+ "run upgrade_check; "\
+ "run init_display; "\
+ "run storeargs; "\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1536 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 1024 //MB
+#define CONFIG_DDR_CLK 720 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR3
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_ONLY_32BIT : one channel 32bit
+ * CONFIG_DDR0_ONLY_16BIT : one channel 16bit
+ * CONFIG_DDR01_TWO_CHANNEL : two channels 32bit
+ * CONFIG_DDR01_TWO_CHANNEL_16BIT : two channels 16bit */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR01_TWO_CHANNEL
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr power saving */
+#define CONFIG_DDR_ZQ_POWER_DOWN
+#define CONFIG_DDR_POWER_DOWN_PHY_VREF
+/* ddr detection */
+#define CONFIG_DDR_SIZE_AUTO_DETECT 0 //0:disable, 1:enable
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 52000000
+#endif
+//#define CONFIG_AML_NAND 1
+#ifdef CONFIG_AML_NAND
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+//#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+/* #define CONFIG_AML_LCD_TABLET 1 */
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXTVBB_XHCI_BASE 0xc9000000
+ #define CONFIG_GXTVBB_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXTVBB_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p310"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxtvbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+#define CONFIG_MULTI_DTB 1
+
+/* ddr dump function defines */
+//#define CONFIG_SPL_DDR_DUMP 1
+#ifdef CONFIG_SPL_DDR_DUMP
+ #define CONFIG_SPL_DDR_DUMP_ADDR 0x01000000
+ #define CONFIG_SPL_DDR_DUMP_SIZE 0x00200000
+ #define CONFIG_SPL_DDR_DUMP_DEV_TYPE 0x4 //device type, 1:emmc, 4:sd
+ #define CONFIG_SPL_DDR_DUMP_DEV_OFFSET 0x40000000 //offset of store device
+ #define CONFIG_SPL_DDR_DUMP_FLAG 0x1 //flag write in sticky reg
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+#endif
+
diff --git a/board/amlogic/configs/gxtvbb_p311_v1.h b/board/amlogic/configs/gxtvbb_p311_v1.h
new file mode 100644
index 0000000..590a68c
--- /dev/null
+++ b/board/amlogic/configs/gxtvbb_p311_v1.h
@@ -0,0 +1,456 @@
+
+/*
+ * board/amlogic/configs/gxtvbb_p311_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXTVBB_P311_V1_H__
+#define __GXTVBB_P311_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1100 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_IR_REMOTE 1
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 8
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic nec tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0xf30cfe01 //amlogic nec tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xf20dfe01 //amlogic nec tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xe51afb04 //amlogic nec box ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xFFFFFFFF //amlogic nec tv ir --- right
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0x00f2a0d5 //tcl rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xf40b1818 //hair toshiba
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xf30c0e0e //skyworth
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "loadaddr=1080000\0"\
+ "dtb_mem_addr=0x1000000\0" \
+ "outputmode=1080p60hz\0" \
+ "panel_reverse=0\0" \
+ "osd_reverse=n\0" \
+ "video_reverse=n\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "fb_addr=0x3b000000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "jtag=apao\0"\
+ "active_slot=_a\0"\
+ "lock=10001000\0"\
+ "boot_part=boot\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update; "\
+ "else fi; "\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs rootfstype=ramfs init=/init "\
+ "console=ttyS0,115200 no_console_suspend "\
+ "earlyprintk=aml-uart,0xc81004c0 "\
+ "androidboot.selinux=${EnableSelinux} "\
+ "logo=${display_layer},loaded,${fb_addr} "\
+ "vout=${outputmode},enable "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} "\
+ "jtag=${jtag} "\
+ "androidboot.firstboot=${firstboot}; "\
+ "run cmdline_keys; "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash; "\
+ "else if test ${reboot_mode} = update; then "\
+ "run update; "\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "run try_auto_burn; "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "run update; "\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache}; "\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "fi; "\
+ "\0" \
+ "update="\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then "\
+ "autoscr ${loadaddr}; "\
+ "fi; "\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then "\
+ "echo sd dtb.img loaded; "\
+ "fi; "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then "\
+ "autoscr ${loadaddr}; "\
+ "fi; "\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then "\
+ "echo udisk dtb.img loaded; "\
+ "fi; "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if imgread kernel recovery ${loadaddr}; then "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi"\
+ "\0"\
+ "init_display="\
+ "osd open; osd clear; "\
+ "vout output ${outputmode}; "\
+ "imgread pic logo bootup $loadaddr; "\
+ "bmp display $bootup_offset; bmp scale"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "androidboot.serialno=${usid}; "\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi; "\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "mac=${mac} androidboot.mac=${mac}; "\
+ "fi; "\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "androidboot.deviceid=${deviceid}; "\
+ "fi; "\
+ "fi; "\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect; "\
+ "run upgrade_check; "\
+ "run init_display; "\
+ "run storeargs; "\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1536 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 1024 //MB
+#define CONFIG_DDR_CLK 720 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR3
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_ONLY_32BIT : one channel 32bit
+ * CONFIG_DDR0_ONLY_16BIT : one channel 16bit
+ * CONFIG_DDR01_TWO_CHANNEL : two channels 32bit
+ * CONFIG_DDR01_TWO_CHANNEL_16BIT : two channels 16bit */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR01_TWO_CHANNEL
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr power saving */
+#define CONFIG_DDR_ZQ_POWER_DOWN
+#define CONFIG_DDR_POWER_DOWN_PHY_VREF
+/* ddr detection */
+#define CONFIG_DDR_SIZE_AUTO_DETECT 0 //0:disable, 1:enable
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 52000000
+#endif
+//#define CONFIG_AML_NAND 1
+#ifdef CONFIG_AML_NAND
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+//#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+/* #define CONFIG_AML_LCD_TABLET 1 */
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXTVBB_XHCI_BASE 0xc9000000
+ #define CONFIG_GXTVBB_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXTVBB_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p311"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_AML_PMU4 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxtvbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+#define CONFIG_MULTI_DTB 1
+
+/* ddr dump function defines */
+//#define CONFIG_SPL_DDR_DUMP 1
+#ifdef CONFIG_SPL_DDR_DUMP
+ #define CONFIG_SPL_DDR_DUMP_ADDR 0x01000000
+ #define CONFIG_SPL_DDR_DUMP_SIZE 0x00200000
+ #define CONFIG_SPL_DDR_DUMP_DEV_TYPE 0x4 //device type, 1:emmc, 4:sd
+ #define CONFIG_SPL_DDR_DUMP_DEV_OFFSET 0x40000000 //offset of store device
+ #define CONFIG_SPL_DDR_DUMP_FLAG 0x1 //flag write in sticky reg
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+#endif
+
diff --git a/board/amlogic/configs/gxtvbb_skt_v1.h b/board/amlogic/configs/gxtvbb_skt_v1.h
new file mode 100644
index 0000000..e728473
--- /dev/null
+++ b/board/amlogic/configs/gxtvbb_skt_v1.h
@@ -0,0 +1,469 @@
+
+/*
+ * board/amlogic/configs/gxtvbb_skt_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXTVBB_SKT_V1_H__
+#define __GXTVBB_SKT_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+#define CONFIG_INSTABOOT
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_IR_REMOTE 1
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 8
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic nec tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0xf30cfe01 //amlogic nec tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xf20dfe01 //amlogic nec tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xe51afb04 //amlogic nec box ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xFFFFFFFF //amlogic nec tv ir --- right
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0x00f2a0d5 //tcl rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xf40b1818 //hair toshiba
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xf30c0e0e //skyworth
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "loadaddr=1080000\0"\
+ "dtb_mem_addr=0x1000000\0" \
+ "fdt_high=0x20000000\0" \
+ "panel_type=lvds_0\0" \
+ "outputmode=1080p60hz\0" \
+ "panel_reverse=0\0" \
+ "osd_reverse=n\0" \
+ "video_reverse=n\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "fb_addr=0x3b000000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "lock=10001000\0"\
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "jtag=apao\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update; "\
+ "else if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; "\
+ "fi; fi; "\
+ "\0"\
+ "bootmode_check="\
+ "get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; "\
+ "fi; "\
+ "\0"\
+ "storeargs=setenv bootargs "\
+ "rootfstype=ramfs init=/init "\
+ "console=ttyS0,115200 no_console_suspend "\
+ "earlyprintk=aml-uart,0xc81004c0 "\
+ "androidboot.selinux=disabled "\
+ "logo=${display_layer},loaded,${fb_addr} "\
+ "vout=${outputmode},enable "\
+ "panel_type=${panel_type} hdmitx= "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} "\
+ "jtag=${jtag} "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "androidboot.firstboot=${firstboot}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys; "\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash; "\
+ "else if test ${reboot_mode} = update; then "\
+ "run update; "\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "run try_auto_burn; "\
+ "fi; fi; fi; "\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel boot ${loadaddr}; then "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "run update; "\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache}; "\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "fi; "\
+ "\0" \
+ "update="\
+ /*first usb burning,
+ second sdc_burn,
+ third ext-sd autoscr/recovery,
+ last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "led 0 toggle; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then "\
+ "autoscr ${loadaddr}; "\
+ "fi; "\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then "\
+ "echo sd dtb.img loaded; "\
+ "fi; "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then "\
+ "autoscr ${loadaddr}; "\
+ "fi; "\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then "\
+ "echo udisk dtb.img loaded; "\
+ "fi; "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if imgread kernel recovery ${loadaddr}; then "\
+ "wipeisb; "\
+ "bootm ${loadaddr}; "\
+ "fi"\
+ "\0"\
+ "init_display="\
+ "osd open; osd clear; "\
+ "vout output ${outputmode}; "\
+ "imgread pic logo bootup $loadaddr; "\
+ "bmp display $bootup_offset; bmp scale"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "androidboot.serialno=${usid}; "\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi; "\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "mac=${mac} androidboot.mac=${mac}; "\
+ "fi; "\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "androidboot.deviceid=${deviceid}; "\
+ "fi; "\
+ "fi; "\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; sleep 5; run update; "\
+ "fi; "\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run factory_reset_poweroff_protect; "\
+ "run upgrade_check; "\
+ "run bootmode_check; "\
+ "run init_display; "\
+ "run storeargs; "\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1536 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 2048 //MB
+#define CONFIG_DDR_CLK 720 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR3
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_ONLY_32BIT : one channel 32bit
+ * CONFIG_DDR0_ONLY_16BIT : one channel 16bit
+ * CONFIG_DDR01_TWO_CHANNEL : two channels 32bit
+ * CONFIG_DDR01_TWO_CHANNEL_16BIT : two channels 16bit */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR01_TWO_CHANNEL
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr power saving */
+#define CONFIG_DDR_ZQ_POWER_DOWN
+#define CONFIG_DDR_POWER_DOWN_PHY_VREF
+/* ddr detection */
+#define CONFIG_DDR_SIZE_AUTO_DETECT 1 //0:disable, 1:enable
+/* ddr functions */
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 52000000
+#endif
+#define CONFIG_AML_NAND 1
+#ifdef CONFIG_AML_NAND
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL // to test
+ #define CONFIG_SPI_FLASH_EON // to test
+ #define CONFIG_SPI_FLASH_GIGADEVICE // to test
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION // to test
+ #define CONFIG_SPI_FLASH_STMICRO // to test
+ #define CONFIG_SPI_FLASH_SST // to test
+ #define CONFIG_SPI_FLASH_WINBOND // to test
+ #define CONFIG_SPI_FRAM_RAMTRON // to add & test
+ #define CONFIG_SPI_M95XXX // to add & test
+ #define CONFIG_SPI_FLASH_ESMT // to add & test
+#endif
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+// #if defined(CONFIG_AML_VOUT)
+// #define CONFIG_AML_CVBS 1
+// #endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXTVBB_XHCI_BASE 0xc9000000
+ #define CONFIG_GXTVBB_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXTVBB_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC 1
+#endif //#if defined(CONFIG_CMD_USB)
+//#define CONFIG_AML_TINY_USBTOOL 1
+#define CONFIG_AML_V2_FACTORY_BURN 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_AML_PMU4 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxtvbb
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_PLLTEST 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+#define CONFIG_MULTI_DTB 1
+
+/* ddr dump function defines */
+//#define CONFIG_SPL_DDR_DUMP 1
+#ifdef CONFIG_SPL_DDR_DUMP
+ #define CONFIG_SPL_DDR_DUMP_ADDR 0x01000000
+ #define CONFIG_SPL_DDR_DUMP_SIZE 0x00200000
+ #define CONFIG_SPL_DDR_DUMP_DEV_TYPE 0x4 //device type, 1:emmc, 4:sd
+ #define CONFIG_SPL_DDR_DUMP_DEV_OFFSET 0x40000000 //offset of store device
+ #define CONFIG_SPL_DDR_DUMP_FLAG 0x1 //flag write in sticky reg
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+#endif
+
diff --git a/board/amlogic/configs/gxtvbb_t966_skt_v1.h b/board/amlogic/configs/gxtvbb_t966_skt_v1.h
new file mode 100644
index 0000000..8a8a776
--- /dev/null
+++ b/board/amlogic/configs/gxtvbb_t966_skt_v1.h
@@ -0,0 +1,440 @@
+
+/*
+ * board/amlogic/configs/gxtvbb_t966_skt_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __GXTVBB_T966_SKT_V1_H__
+#define __GXTVBB_T966_SKT_V1_H__
+
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1100 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "Mbox"
+#define CONFIG_CEC_WAKEUP
+
+#define CONFIG_INSTABOOT
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_IR_REMOTE 1
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 8
+#define CONFIG_IR_REMOTE_USE_PROTOCOL 0 // 0:nec 1:duokan 2:Toshiba 3:rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic nec tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0xf30cfe01 //amlogic nec tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xf20dfe01 //amlogic nec tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xe51afb04 //amlogic nec box ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xFFFFFFFF //amlogic nec tv ir --- right
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0x00f2a0d5 //tcl rca
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xf40b1818 //hair toshiba
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xf30c0e0e //skyworth
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=0\0"\
+ "upgrade_step=0\0"\
+ "loadaddr=1080000\0"\
+ "dtb_mem_addr=0x1000000\0" \
+ "outputmode=1080p60hz\0" \
+ "panel_reverse=0\0" \
+ "osd_reverse=n\0" \
+ "video_reverse=n\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "fb_addr=0x3b000000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "lock=10001000\0"\
+ "jtag=apao\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update; "\
+ "else if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; "\
+ "fi; fi; "\
+ "\0"\
+ "bootmode_check="\
+ "get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; "\
+ "fi; "\
+ "\0" \
+ "storeargs="\
+ "setenv bootargs rootfstype=ramfs init=/init "\
+ "console=ttyS0,115200 no_console_suspend "\
+ "earlyprintk=aml-uart,0xc81004c0 "\
+ "androidboot.selinux=disabled "\
+ "logo=${display_layer},loaded,${fb_addr} "\
+ "vout=${outputmode},enable "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} "\
+ "jtag=${jtag} "\
+ "androidboot.firstboot=${firstboot}; "\
+ "run cmdline_keys; "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash; "\
+ "else if test ${reboot_mode} = update; then "\
+ "run update; "\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "run try_auto_burn; "\
+ "fi; fi; fi; "\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "run update; "\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache}; "\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "fi; "\
+ "\0" \
+ "update="\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard; "\
+ "fi; "\
+ "if usb start 0; then "\
+ "run recovery_from_udisk; "\
+ "fi; "\
+ "run recovery_from_flash; "\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then "\
+ "autoscr ${loadaddr}; "\
+ "fi; "\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then "\
+ "echo sd dtb.img loaded; "\
+ "fi; "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then "\
+ "autoscr ${loadaddr}; "\
+ "fi; "\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then "\
+ "echo udisk dtb.img loaded; "\
+ "fi; "\
+ "bootm ${loadaddr}; "\
+ "fi; "\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt};"\
+ "if imgread kernel recovery ${loadaddr}; then "\
+ "bootm ${loadaddr}; "\
+ "fi"\
+ "\0"\
+ "init_display="\
+ "osd open; osd clear; "\
+ "vout output ${outputmode}; "\
+ "imgread pic logo bootup $loadaddr; "\
+ "bmp display $bootup_offset; bmp scale"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "androidboot.serialno=${usid}; "\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi; "\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "mac=${mac} androidboot.mac=${mac}; "\
+ "fi; "\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} "\
+ "androidboot.deviceid=${deviceid}; "\
+ "fi; "\
+ "fi; "\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect; "\
+ "run upgrade_check; "\
+ "run bootmode_check; "\
+ "run init_display; "\
+ "run storeargs; "\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1536 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 2048//1024 //MB
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR3
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_ONLY_32BIT : one channel 32bit
+ * CONFIG_DDR0_ONLY_16BIT : one channel 16bit
+ * CONFIG_DDR01_TWO_CHANNEL : two channels 32bit
+ * CONFIG_DDR01_TWO_CHANNEL_16BIT : two channels 16bit */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR01_TWO_CHANNEL
+#define CONFIG_DDR_FULL_TEST 0 //1 for ddr full test
+#define CONFIG_NR_DRAM_BANKS 1
+/* ddr power saving */
+#define CONFIG_DDR_ZQ_POWER_DOWN
+#define CONFIG_DDR_POWER_DOWN_PHY_VREF
+/* ddr detection */
+#define CONFIG_DDR_SIZE_AUTO_DETECT 0 //0:disable, 1:enable
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 52000000
+#endif
+#define CONFIG_AML_NAND 1
+#ifdef CONFIG_AML_NAND
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+//#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+/* #define CONFIG_AML_LCD_TABLET 1 */
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXTVBB_XHCI_BASE 0xc9000000
+ #define CONFIG_GXTVBB_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXTVBB_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC 1
+#endif //#if defined(CONFIG_CMD_USB)
+//#define CONFIG_AML_TINY_USBTOOL 1
+#define CONFIG_AML_V2_FACTORY_BURN 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_AML_PMU4 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxtvbb
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1 //delay 1s
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+#define CONFIG_MULTI_DTB 1
+
+/* ddr dump function defines */
+//#define CONFIG_SPL_DDR_DUMP 1
+#ifdef CONFIG_SPL_DDR_DUMP
+ #define CONFIG_SPL_DDR_DUMP_ADDR 0x01000000
+ #define CONFIG_SPL_DDR_DUMP_SIZE 0x00200000
+ #define CONFIG_SPL_DDR_DUMP_DEV_TYPE 0x4 //device type, 1:emmc, 4:sd
+ #define CONFIG_SPL_DDR_DUMP_DEV_OFFSET 0x40000000 //offset of store device
+ #define CONFIG_SPL_DDR_DUMP_FLAG 0x1 //flag write in sticky reg
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+#endif
+
diff --git a/board/amlogic/configs/txhd_r341_v1.h b/board/amlogic/configs/txhd_r341_v1.h
new file mode 100755
index 0000000..eda54a8
--- /dev/null
+++ b/board/amlogic/configs/txhd_r341_v1.h
@@ -0,0 +1,486 @@
+
+/*
+ * board/amlogic/configs/txhd_skt_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __TXHD_R341_V1_H__
+#define __TXHD_R341_V1_H__
+
+#include <asm/arch/cpu.h>
+
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1050
+#define CONFIG_VDDEE_INIT_VOLTAGE 1050 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 3
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_0\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "lock=10001000\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 1024 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 912 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR3
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_16BIT_2
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 5
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+//#define CONFIG_AML_CVBS 1
+#endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN 1
+#define CONFIG_AML_LCD_EXTERN_I2C_RT6947 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "txhd_r341"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//2017.05.11 new compress solution, only support BL33 LZ4 compress
+//compress ratio is about 50%, BL31 will take the decompress
+//profit :
+// size : u-boot.bin 880KB -> 577KB
+// boot time decrease: SD boot: ~100ms ; eMMC boot: 47ms
+//default: enable the data compress feature
+//to disable the data compress please just define followings
+//#undef CONFIG_AML_BL33_COMPRESS_ENABLE
+
+
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define ETHERNET_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/txhd_skt_v1.h b/board/amlogic/configs/txhd_skt_v1.h
new file mode 100755
index 0000000..ba5530e
--- /dev/null
+++ b/board/amlogic/configs/txhd_skt_v1.h
@@ -0,0 +1,595 @@
+
+/*
+ * board/amlogic/configs/txhd_skt_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __TXHD_SKT_V1_H__
+#define __TXHD_SKT_V1_H__
+
+#include <asm/arch/cpu.h>
+
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1050
+#define CONFIG_VDDEE_INIT_VOLTAGE 1050 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 3
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+
+
+
+#ifdef CONFIG_PXP_EMULATOR
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_0\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "tcon_fb_addr=0x3de05c00\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x6000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=permissive\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "lock=10001000\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs=rootfstype=ramfs "\
+ "init=/init console=ttyS0,115200 no_console_suspend "\
+ "earlyprintk=aml-uart,0xff803000 "\
+ "ramoops.pstore_en=1 "\
+ "ramoops.record_size=0x8000 "\
+ "ramoops.console_size=0x4000 "\
+ "\0"\
+ "storeargs=setenv bootargs ${initargs} "\
+ "logo=${display_layer},loaded,${fb_addr} "\
+ "vout=${outputmode},enable "\
+ "panel_type=${panel_type} "\
+ "osd_reverse=${osd_reverse} "\
+ "video_reverse=${video_reverse} "\
+ "jtag=${jtag} "\
+ "androidboot.selinux=${EnableSelinux} "\
+ "androidboot.firstboot=${firstboot} "\
+ "androidboot.slot_suffix=${active_slot} "\
+ "androidboot.hardware=amlogic "\
+ "\0"\
+ "boot_kernel_from_ddr=fdt addr ${dtb_mem_addr}; "\
+ "booti 0x8000000 - 0x6000000; "\
+ "\0"\
+ "storeboot=run boot_kernel_from_ddr;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run storeargs;"\
+
+#else
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_0\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+
+#endif
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 1024 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR3
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_16BIT_2
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL
+ #define CONFIG_SPI_FLASH_EON
+ #define CONFIG_SPI_FLASH_GIGADEVICE
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION
+ #define CONFIG_SPI_FLASH_STMICRO
+ #define CONFIG_SPI_FLASH_SST
+ #define CONFIG_SPI_FLASH_WINBOND
+ #define CONFIG_SPI_FRAM_RAMTRON
+ #define CONFIG_SPI_M95XXX
+ #define CONFIG_SPI_FLASH_ESMT
+ /* SPI nand flash support */
+ #define CONFIG_SPI_NAND
+#endif
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE y
+ #define CONFIG_RBTREE
+ #define CONFIG_CMD_NAND_TORTURE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+ #define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 5
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+//#define CONFIG_AML_CVBS 1
+#endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "txhd_skt"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//2017.05.11 new compress solution, only support BL33 LZ4 compress
+//compress ratio is about 50%, BL31 will take the decompress
+//profit :
+// size : u-boot.bin 880KB -> 577KB
+// boot time decrease: SD boot: ~100ms ; eMMC boot: 47ms
+//default: enable the data compress feature
+//to disable the data compress please just define followings
+//#undef CONFIG_AML_BL33_COMPRESS_ENABLE
+
+
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define ETHERNET_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/txl_p320_v1.h b/board/amlogic/configs/txl_p320_v1.h
new file mode 100644
index 0000000..8c0683b
--- /dev/null
+++ b/board/amlogic/configs/txl_p320_v1.h
@@ -0,0 +1,479 @@
+
+/*
+ * board/amlogic/configs/txl_p320_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __TXL_P320_V1_H__
+#define __TXL_P320_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 900 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 3
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "ir_power_key=0xffffffff\0"\
+ "adc_ch_power_key=0xffff,137\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "lock=10001000\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 792 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR4
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK0
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_RDBI 1 //0:disable, 1:enable. low power consumption and upgrade stability
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+// #if defined(CONFIG_AML_VOUT)
+// #define CONFIG_AML_CVBS 1
+// #endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN
+#define CONFIG_AML_LCD_EXTERN_I2C_T5800Q
+#define CONFIG_AML_LCD_EXTERN_I2C_DLPC3439
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p320"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+//#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/txl_p321_v1.h b/board/amlogic/configs/txl_p321_v1.h
new file mode 100644
index 0000000..93a3952
--- /dev/null
+++ b/board/amlogic/configs/txl_p321_v1.h
@@ -0,0 +1,480 @@
+
+/*
+ * board/amlogic/configs/txl_p321_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __TXL_P321_V1_H__
+#define __TXL_P321_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 900 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 3
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=apee\0"\
+ "hdmiuart_mode=close\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "lock=10001000\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 792 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK0
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_RDBI 1 //0:disable, 1:enable. low power consumption and upgrade stability
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+// #if defined(CONFIG_AML_VOUT)
+// #define CONFIG_AML_CVBS 1
+// #endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN
+#define CONFIG_AML_LCD_EXTERN_I2C_T5800Q
+#define CONFIG_AML_LCD_EXTERN_I2C_DLPC3439
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p321"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+//#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/txl_p341_v1.h b/board/amlogic/configs/txl_p341_v1.h
new file mode 100644
index 0000000..eb9d554
--- /dev/null
+++ b/board/amlogic/configs/txl_p341_v1.h
@@ -0,0 +1,477 @@
+
+/*
+ * board/amlogic/configs/txl_p341_v1.h
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __TXL_P341_V1_H__
+#define __TXL_P341_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1000
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000//1070 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 900//900 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 3
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "hdmiuart_mode=close\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=disabled\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "lock=10001000\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 792 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_16BIT
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_RDBI 1 //0:disable, 1:enable. low power consumption and upgrade stability
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+// #if defined(CONFIG_AML_VOUT)
+// #define CONFIG_AML_CVBS 1
+// #endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p341"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/txl_p341_v2.h b/board/amlogic/configs/txl_p341_v2.h
new file mode 100644
index 0000000..7ecb512
--- /dev/null
+++ b/board/amlogic/configs/txl_p341_v2.h
@@ -0,0 +1,477 @@
+
+/*
+ * board/amlogic/configs/txl_p341_v2.h
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __TXL_P341_V1_H__
+#define __TXL_P341_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 900 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 3
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0x3ac5bd02
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "hdmiuart_mode=close\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1280\0" \
+ "display_height=720\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x6000000\0" \
+ "fb_width=1280\0" \
+ "fb_height=720\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=disabled\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "lock=10001000\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 512 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 792 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_16BIT
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_RDBI 1 //0:disable, 1:enable. low power consumption and upgrade stability
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+// #if defined(CONFIG_AML_VOUT)
+// #define CONFIG_AML_CVBS 1
+// #endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p341"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+//#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/txl_p346_v1.h b/board/amlogic/configs/txl_p346_v1.h
new file mode 100755
index 0000000..6a793a7
--- /dev/null
+++ b/board/amlogic/configs/txl_p346_v1.h
@@ -0,0 +1,471 @@
+/*
+ * board/amlogic/configs/txl_p346_v1.h
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __TXL_P346_V1_H__
+#define __TXL_P346_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 900 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 3
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=apee\0"\
+ "hdmiuart_mode=close\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=disabled\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "lock=10001000\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 1024 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 792 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR4
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK0
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_RDBI 1 //0:disable, 1:enable. low power consumption and upgrade stability
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+// #if defined(CONFIG_AML_VOUT)
+// #define CONFIG_AML_CVBS 1
+// #endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN
+#define CONFIG_AML_LCD_EXTERN_I2C_T5800Q
+#define CONFIG_AML_LCD_EXTERN_I2C_DLPC3439
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "p346"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+//#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/txl_skt_v1.h b/board/amlogic/configs/txl_skt_v1.h
new file mode 100755
index 0000000..9d57ef9
--- /dev/null
+++ b/board/amlogic/configs/txl_skt_v1.h
@@ -0,0 +1,514 @@
+
+/*
+ * board/amlogic/configs/txl_skt_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __TXL_SKT_V1_H__
+#define __TXL_SKT_V1_H__
+
+#include <asm/arch/cpu.h>
+
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1100 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 3
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_0\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "lock=10001000\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK0
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 1 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL // to test
+ #define CONFIG_SPI_FLASH_EON // to test
+ #define CONFIG_SPI_FLASH_GIGADEVICE // to test
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION // to test
+ #define CONFIG_SPI_FLASH_STMICRO // to test
+ #define CONFIG_SPI_FLASH_SST // to test
+ #define CONFIG_SPI_FLASH_WINBOND // to test
+ #define CONFIG_SPI_FRAM_RAMTRON // to add & test
+ #define CONFIG_SPI_M95XXX // to add & test
+ #define CONFIG_SPI_FLASH_ESMT // to add & test
+#endif
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+//#define CONFIG_AML_CVBS 1
+#endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "txl_skt"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_PLLTEST 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+//#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//2017.05.11 new compress solution, only support BL33 LZ4 compress
+//compress ratio is about 50%, BL31 will take the decompress
+//profit :
+// size : u-boot.bin 1.2MB -> 913KB
+// boot time decrease: SD boot: ~100ms ; eMMC boot: 50ms
+//default: enable the data compress feature
+//to disable the data compress please just define followings
+//#undef CONFIG_AML_BL33_COMPRESS_ENABLE
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/txl_t950_skt_v1.h b/board/amlogic/configs/txl_t950_skt_v1.h
new file mode 100644
index 0000000..14a8024
--- /dev/null
+++ b/board/amlogic/configs/txl_t950_skt_v1.h
@@ -0,0 +1,506 @@
+
+/*
+ * board/amlogic/configs/txl_t950_skt_v1.h
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __TXL_T950_SKT_V1_H__
+#define __TXL_T950_SKT_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 1000//1070 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 860//900 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* support ext4*/
+#define CONFIG_CMD_EXT4 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_CNT 3
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "hdmiuart_mode=close\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1280\0" \
+ "display_height=720\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x6000000\0" \
+ "fb_width=1280\0" \
+ "fb_height=720\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "lock=10001000\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xc81004c0 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if itest ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 512 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 792 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_16BIT
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_RDBI 1 //0:disable, 1:enable. low power consumption and upgrade stability
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL // to test
+ #define CONFIG_SPI_FLASH_EON // to test
+ #define CONFIG_SPI_FLASH_GIGADEVICE // to test
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION // to test
+ #define CONFIG_SPI_FLASH_STMICRO // to test
+ #define CONFIG_SPI_FLASH_SST // to test
+ #define CONFIG_SPI_FLASH_WINBOND // to test
+ #define CONFIG_SPI_FRAM_RAMTRON // to add & test
+ #define CONFIG_SPI_M95XXX // to add & test
+ #define CONFIG_SPI_FLASH_ESMT // to add & test
+#endif
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+#define CONFIG_VPU_CLK_LEVEL_DFT 7
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+// #if defined(CONFIG_AML_VOUT)
+// #define CONFIG_AML_CVBS 1
+// #endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xc9000000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xd0078000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xd0078080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+//#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//2017.05.11 new compress solution, only support BL33 LZ4 compress
+//compress ratio is about 50%, BL31 will take the decompress
+//profit :
+// size : u-boot.bin 1.2MB -> 913KB
+// boot time decrease: SD boot: ~100ms ; eMMC boot: 50ms
+//default: enable the data compress feature
+//to disable the data compress please just define followings
+//#undef CONFIG_AML_BL33_COMPRESS_ENABLE
+
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define CONFIG_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/txlx_t962e_r321_v1.h b/board/amlogic/configs/txlx_t962e_r321_v1.h
new file mode 100755
index 0000000..18721d9
--- /dev/null
+++ b/board/amlogic/configs/txlx_t962e_r321_v1.h
@@ -0,0 +1,478 @@
+
+/*
+ * board/amlogic/configs/txlx_t962x_r311_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __TXLX_T962E_R321_V1_H__
+#define __TXLX_T962E_R321_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1050//1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 950 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 900 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "page_trace=on\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "lock=10001000\0"\
+ "boot_part=boot\0"\
+ "model_name=t962e_r321_hdmitx\0" \
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} hdmimode=${hdmimode} cvbsmode=${cvbsmode} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} page_trace=${page_trace};" \
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK0
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+//#define CONFIG_AML_SPIFC
+#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+
+/* DISPLAY & HDMITX */
+#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+#define CONFIG_AML_CVBS 1
+#endif
+
+//#define CONFIG_AML_LCD 1
+//#define CONFIG_AML_LCD_TV 1
+//#define CONFIG_AML_LCD_TABLET 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "t962e_r321"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+//#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define ETHERNET_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/txlx_t962e_skt_v1.h b/board/amlogic/configs/txlx_t962e_skt_v1.h
new file mode 100755
index 0000000..06b7799
--- /dev/null
+++ b/board/amlogic/configs/txlx_t962e_skt_v1.h
@@ -0,0 +1,504 @@
+
+/*
+ * board/amlogic/configs/txlx_t962e_skt_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+#ifndef __TXLX_T962E_SKT_V1_H__
+#define __TXLX_T962E_SKT_V1_H__
+
+#include <asm/arch/cpu.h>
+
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 950 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "lock=10001000\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 1024 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 1008 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK0
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 1 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL // to test
+ #define CONFIG_SPI_FLASH_EON // to test
+ #define CONFIG_SPI_FLASH_GIGADEVICE // to test
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION // to test
+ #define CONFIG_SPI_FLASH_STMICRO // to test
+ #define CONFIG_SPI_FLASH_SST // to test
+ #define CONFIG_SPI_FLASH_WINBOND // to test
+ #define CONFIG_SPI_FRAM_RAMTRON // to add & test
+ #define CONFIG_SPI_M95XXX // to add & test
+ #define CONFIG_SPI_FLASH_ESMT // to add & test
+#endif
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+//#define CONFIG_AML_CVBS 1
+#endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "t962e_skt"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//2017.05.11 new compress solution, only support BL33 LZ4 compress
+//compress ratio is about 50%, BL31 will take the decompress
+//profit :
+// size : u-boot.bin 880KB -> 577KB
+// boot time decrease: SD boot: ~100ms ; eMMC boot: 47ms
+//default: enable the data compress feature
+//to disable the data compress please just define followings
+//#undef CONFIG_AML_BL33_COMPRESS_ENABLE
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define ETHERNET_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/txlx_t962x_r311_v1.h b/board/amlogic/configs/txlx_t962x_r311_v1.h
new file mode 100755
index 0000000..2524384
--- /dev/null
+++ b/board/amlogic/configs/txlx_t962x_r311_v1.h
@@ -0,0 +1,489 @@
+
+/*
+ * board/amlogic/configs/txlx_t962x_r311_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __TXLX_T962X_R311_V1_H__
+#define __TXLX_T962X_R311_V1_H__
+
+#include <asm/arch/cpu.h>
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1050//1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 950 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 900 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+#define CONFIG_BT_WAKEUP
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=apee\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "page_trace=on\0"\
+ "osd_reverse=0\0"\
+ "lock=10001000\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "boot_part=boot\0"\
+ "model_name=t962x_r311_FHD\0" \
+ "ui_mode=720p\0" \
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag} ui_mode=${ui_mode}; "\
+ "setenv bootargs ${bootargs} page_trace=${page_trace};" \
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 0 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 792 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_DDR4
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK0
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_RDBI 1 //0:disable, 1:enable. low power consumption and upgrade stability
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+//#define CONFIG_AML_SPIFC
+#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+//#define CONFIG_AML_CVBS 1
+#endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+#define CONFIG_AML_LCD_EXTERN 1
+
+#define CONFIG_AML_LOCAL_DIMMING
+#define CONFIG_AML_LOCAL_DIMMING_GLOBAL
+#define CONFIG_AML_LOCAL_DIMMING_IW7027
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "t962x_r311"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+// #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_INI 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+#define CONFIG_CMD_EXT4 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+#define CONFIG_MULTI_DTB 1
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//support secure boot
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/(board)/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define ETHERNET_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/configs/txlx_t962x_skt_v1.h b/board/amlogic/configs/txlx_t962x_skt_v1.h
new file mode 100755
index 0000000..f104519
--- /dev/null
+++ b/board/amlogic/configs/txlx_t962x_skt_v1.h
@@ -0,0 +1,504 @@
+
+/*
+ * board/amlogic/configs/txl_skt_v1.h
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifndef __TXL_SKT_V1_H__
+#define __TXL_SKT_V1_H__
+
+#include <asm/arch/cpu.h>
+
+
+#define CONFIG_SYS_GENERIC_BOARD 1
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+
+/*
+ * platform power init config
+ */
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 1100
+#define CONFIG_VDDEE_INIT_VOLTAGE 950 // voltage for power up
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 850 // voltage for suspend
+
+/* configs for CEC */
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#define CONFIG_CMD_SARADC 1
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_AML_MESON_SERIAL 1
+#define CONFIG_SERIAL_MULTI 1
+
+//Enable ir remote wake up for bl30
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=apao\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lvds_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd1\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=permissive\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=_a\0"\
+ "lock=10001000\0"\
+ "boot_part=boot\0"\
+ "initargs="\
+ "rootfstype=ramfs init=/init console=ttyS0,115200 no_console_suspend earlyprintk=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "setenv bootargs ${initargs} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} osd_reverse=${osd_reverse} video_reverse=${video_reverse} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ /*"run try_auto_burn; "*/\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "hdmitx output 1080p60hz;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run switch_bootmode;"
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+//#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_ANDROID_IMG 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1200 //MHz. Range: 600-1800, should be multiple of 24
+
+/* ddr */
+#define CONFIG_DDR_SIZE 1024 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK 792 //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR4_CLK 792 //MHz, for boards which use different ddr chip
+#define CONFIG_NR_DRAM_BANKS 1
+/* DDR type setting
+ * CONFIG_DDR_TYPE_LPDDR3 : LPDDR3
+ * CONFIG_DDR_TYPE_DDR3 : DDR3
+ * CONFIG_DDR_TYPE_DDR4 : DDR4
+ * CONFIG_DDR_TYPE_AUTO : DDR3/DDR4 auto detect */
+#define CONFIG_DDR_TYPE CONFIG_DDR_TYPE_AUTO
+/* DDR channel setting, please refer hardware design.
+ * CONFIG_DDR0_RANK0 : DDR0 rank0
+ * CONFIG_DDR0_RANK01 : DDR0 rank0+1
+ * CONFIG_DDR0_16BIT : DDR0 16bit mode
+ * CONFIG_DDR0_16BIT_2 : DDR0 16bit mode, 2ranks
+ * CONFIG_DDR_CHL_AUTO : auto detect RANK0 / RANK0+1 */
+#define CONFIG_DDR_CHANNEL_SET CONFIG_DDR0_RANK0
+/* ddr functions */
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 1 //0:disable, 1:enable. print ddr training window
+
+/* storage: emmc/nand/sd */
+#define CONFIG_STORE_COMPATIBLE 1
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CMD_SAVEENV
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+#define CONFIG_AML_SD_EMMC 1
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#define CONFIG_SYS_NO_FLASH 1
+
+/* meson SPI */
+#define CONFIG_AML_SPIFC
+//#define CONFIG_AML_SPICC
+#if defined CONFIG_AML_SPIFC || defined CONFIG_AML_SPICC
+ #define CONFIG_OF_SPI
+ #define CONFIG_DM_SPI
+ #define CONFIG_CMD_SPI
+#endif
+/* SPI flash config */
+#ifdef CONFIG_AML_SPIFC
+ #define CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
+ #define CONFIG_SPI_FLASH
+ #define CONFIG_DM_SPI_FLASH
+ #define CONFIG_CMD_SF
+ /* SPI flash surpport list */
+ #define CONFIG_SPI_FLASH_ATMEL // to test
+ #define CONFIG_SPI_FLASH_EON // to test
+ #define CONFIG_SPI_FLASH_GIGADEVICE // to test
+ #define CONFIG_SPI_FLASH_MACRONIX
+ #define CONFIG_SPI_FLASH_SPANSION // to test
+ #define CONFIG_SPI_FLASH_STMICRO // to test
+ #define CONFIG_SPI_FLASH_SST // to test
+ #define CONFIG_SPI_FLASH_WINBOND // to test
+ #define CONFIG_SPI_FRAM_RAMTRON // to add & test
+ #define CONFIG_SPI_M95XXX // to add & test
+ #define CONFIG_SPI_FLASH_ESMT // to add & test
+#endif
+
+
+/* vpu */
+#define CONFIG_AML_VPU 1
+
+/* DISPLAY & HDMITX */
+//#define CONFIG_AML_HDMITX20 1
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_VOUT 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+#define CONFIG_CMD_BMP 1
+
+#if defined(CONFIG_AML_VOUT)
+//#define CONFIG_AML_CVBS 1
+#endif
+
+#define CONFIG_AML_LCD 1
+#define CONFIG_AML_LCD_TV 1
+#define CONFIG_AML_LCD_TABLET 1
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+#define CONFIG_CMD_USB 1
+#if defined(CONFIG_CMD_USB)
+ #define CONFIG_GXL_XHCI_BASE 0xff500000
+ #define CONFIG_GXL_USB_PHY2_BASE 0xffe09000
+ #define CONFIG_GXL_USB_PHY3_BASE 0xffe09080
+ #define CONFIG_USB_STORAGE 1
+ #define CONFIG_USB_XHCI 1
+ #define CONFIG_USB_XHCI_AMLOGIC_GXL 1
+#endif //#if defined(CONFIG_CMD_USB)
+
+#define CONFIG_TXLX_USB 1
+
+//UBOOT fastboot config
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "t962x_skt"
+
+//UBOOT Facotry usb/sdcard burning config
+#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isn't power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+
+/* net */
+#define CONFIG_CMD_NET 1
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME arm_gxbb
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#define CONFIG_EFUSE 1
+#define CONFIG_SYS_I2C_AML 1
+#define CONFIG_SYS_I2C_SPEED 400000
+
+/* commands */
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_I2C 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#define CONFIG_AML_PARTITION 1
+#define CONFIG_MMC 1
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+//#define CONFIG_SYS_DCACHE_OFF
+//#define CONFIG_SYS_ICACHE_OFF
+
+/* other functions */
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 //hide 128MB for kernel reserve
+
+/* debug mode defines */
+//#define CONFIG_DEBUG_MODE 1
+#ifdef CONFIG_DEBUG_MODE
+#define CONFIG_DDR_CLK_DEBUG 636
+#define CONFIG_CPU_CLK_DEBUG 600
+#endif
+
+//2017.05.11 new compress solution, only support BL33 LZ4 compress
+//compress ratio is about 50%, BL31 will take the decompress
+//profit :
+// size : u-boot.bin 880KB -> 577KB
+// boot time decrease: SD boot: ~100ms ; eMMC boot: 47ms
+//default: enable the data compress feature
+//to disable the data compress please just define followings
+//#undef CONFIG_AML_BL33_COMPRESS_ENABLE
+
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+//for GXBB SRAM size limitation just disable NAND
+//as the socket board default has no NAND
+//#undef CONFIG_AML_NAND
+
+//unify build for generate encrypted bootloader "u-boot.bin.encrypt"
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+//unify build for generate encrypted kernel image
+//SRC : "board/amlogic/gxb_skt_v1/boot.img"
+//DST : "fip/boot.img.encrypt"
+//#define CONFIG_AML_CRYPTO_IMG 1
+
+#endif //CONFIG_AML_SECURE_UBOOT
+
+#define CONFIG_SECURE_STORAGE 1
+
+//build with uboot auto test
+//#define CONFIG_AML_UBOOT_AUTO_TEST 1
+
+//board customer ID
+//#define CONFIG_CUSTOMER_ID (0x6472616F624C4D41)
+
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#define ETHERNET_INTERNAL_PHY
+
+#endif
+
diff --git a/board/amlogic/defconfigs/axg_pxp_defconfig b/board/amlogic/defconfigs/axg_pxp_defconfig
new file mode 100644
index 0000000..851e92d
--- /dev/null
+++ b/board/amlogic/defconfigs/axg_pxp_defconfig
@@ -0,0 +1,8 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_AXG=y
+CONFIG_AXG_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
+CONFIG_PXP_EMULATOR=y
+
diff --git a/board/amlogic/defconfigs/axg_s400_v1_defconfig b/board/amlogic/defconfigs/axg_s400_v1_defconfig
new file mode 100644
index 0000000..065d8da
--- /dev/null
+++ b/board/amlogic/defconfigs/axg_s400_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_AXG=y
+CONFIG_AXG_S400_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/axg_s420_v1_defconfig b/board/amlogic/defconfigs/axg_s420_v1_defconfig
new file mode 100644
index 0000000..d00a90a
--- /dev/null
+++ b/board/amlogic/defconfigs/axg_s420_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_AXG=y
+CONFIG_AXG_S420_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/axg_skt_v1_defconfig b/board/amlogic/defconfigs/axg_skt_v1_defconfig
new file mode 100644
index 0000000..33efad2
--- /dev/null
+++ b/board/amlogic/defconfigs/axg_skt_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_AXG=y
+CONFIG_AXG_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/g12a_estelle_bx_defconfig b/board/amlogic/defconfigs/g12a_estelle_bx_defconfig
new file mode 100755
index 0000000..2a41216
--- /dev/null
+++ b/board/amlogic/defconfigs/g12a_estelle_bx_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_G12A=y
+CONFIG_G12A_ESTELLE_BX=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/g12a_estelle_p2_defconfig b/board/amlogic/defconfigs/g12a_estelle_p2_defconfig
new file mode 100755
index 0000000..1b7398e
--- /dev/null
+++ b/board/amlogic/defconfigs/g12a_estelle_p2_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_G12A=y
+CONFIG_G12A_ESTELLE_P2=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/g12a_newman_p0_defconfig b/board/amlogic/defconfigs/g12a_newman_p0_defconfig
new file mode 100755
index 0000000..ac1600a
--- /dev/null
+++ b/board/amlogic/defconfigs/g12a_newman_p0_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_G12A=y
+CONFIG_G12A_NEWMAN_P0=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/g12a_pxp_defconfig b/board/amlogic/defconfigs/g12a_pxp_defconfig
new file mode 100644
index 0000000..d231a9c
--- /dev/null
+++ b/board/amlogic/defconfigs/g12a_pxp_defconfig
@@ -0,0 +1,7 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_G12A=y
+CONFIG_g12a_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
+CONFIG_PXP_EMULATOR=y
diff --git a/board/amlogic/defconfigs/g12a_skt_v1_defconfig b/board/amlogic/defconfigs/g12a_skt_v1_defconfig
new file mode 100644
index 0000000..9d2885d
--- /dev/null
+++ b/board/amlogic/defconfigs/g12a_skt_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_G12A=y
+CONFIG_G12A_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/g12a_u200_v1_defconfig b/board/amlogic/defconfigs/g12a_u200_v1_defconfig
new file mode 100644
index 0000000..00177f1
--- /dev/null
+++ b/board/amlogic/defconfigs/g12a_u200_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_G12A=y
+CONFIG_G12A_U200_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/g12a_u211_v1_defconfig b/board/amlogic/defconfigs/g12a_u211_v1_defconfig
new file mode 100644
index 0000000..cdbfbfe
--- /dev/null
+++ b/board/amlogic/defconfigs/g12a_u211_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_G12A=y
+CONFIG_G12A_U211_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/g12a_u220_v1_defconfig b/board/amlogic/defconfigs/g12a_u220_v1_defconfig
new file mode 100644
index 0000000..354c7b2
--- /dev/null
+++ b/board/amlogic/defconfigs/g12a_u220_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_G12A=y
+CONFIG_G12A_U220_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/g12a_u221_v1_defconfig b/board/amlogic/defconfigs/g12a_u221_v1_defconfig
new file mode 100644
index 0000000..5aa540e
--- /dev/null
+++ b/board/amlogic/defconfigs/g12a_u221_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_G12A=y
+CONFIG_G12A_U221_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gl2a_legion_p1_defconfig b/board/amlogic/defconfigs/gl2a_legion_p1_defconfig
new file mode 100755
index 0000000..af85139
--- /dev/null
+++ b/board/amlogic/defconfigs/gl2a_legion_p1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_G12A=y
+CONFIG_G12A_ESTELLE_P1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxb_p200_v1_defconfig b/board/amlogic/defconfigs/gxb_p200_v1_defconfig
new file mode 100644
index 0000000..e614a34
--- /dev/null
+++ b/board/amlogic/defconfigs/gxb_p200_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXB_P200_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxb_p201_v1_defconfig b/board/amlogic/defconfigs/gxb_p201_v1_defconfig
new file mode 100644
index 0000000..f5f4aec
--- /dev/null
+++ b/board/amlogic/defconfigs/gxb_p201_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXB_P201_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxb_pxp_defconfig b/board/amlogic/defconfigs/gxb_pxp_defconfig
new file mode 100644
index 0000000..db96c0f
--- /dev/null
+++ b/board/amlogic/defconfigs/gxb_pxp_defconfig
@@ -0,0 +1,7 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXB_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
+CONFIG_PXP_EMULATOR=y
diff --git a/board/amlogic/defconfigs/gxb_skt_v1_defconfig b/board/amlogic/defconfigs/gxb_skt_v1_defconfig
new file mode 100644
index 0000000..1e15c03
--- /dev/null
+++ b/board/amlogic/defconfigs/gxb_skt_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXB_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxl_estelle_p0_defconfig b/board/amlogic/defconfigs/gxl_estelle_p0_defconfig
new file mode 100644
index 0000000..ce9cc56
--- /dev/null
+++ b/board/amlogic/defconfigs/gxl_estelle_p0_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_ESTELLE_P0=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxl_p211_v1_defconfig b/board/amlogic/defconfigs/gxl_p211_v1_defconfig
new file mode 100644
index 0000000..c8896d5
--- /dev/null
+++ b/board/amlogic/defconfigs/gxl_p211_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_P211_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxl_p212_v1_defconfig b/board/amlogic/defconfigs/gxl_p212_v1_defconfig
new file mode 100644
index 0000000..871fecb
--- /dev/null
+++ b/board/amlogic/defconfigs/gxl_p212_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_P212_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxl_p230_v1_defconfig b/board/amlogic/defconfigs/gxl_p230_v1_defconfig
new file mode 100644
index 0000000..c4b95a1
--- /dev/null
+++ b/board/amlogic/defconfigs/gxl_p230_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_P230_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxl_p231_v1_defconfig b/board/amlogic/defconfigs/gxl_p231_v1_defconfig
new file mode 100644
index 0000000..b5a480e
--- /dev/null
+++ b/board/amlogic/defconfigs/gxl_p231_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_P231_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxl_p241_v1_defconfig b/board/amlogic/defconfigs/gxl_p241_v1_defconfig
new file mode 100644
index 0000000..d8a95d3
--- /dev/null
+++ b/board/amlogic/defconfigs/gxl_p241_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_P241_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxl_p271_v1_defconfig b/board/amlogic/defconfigs/gxl_p271_v1_defconfig
new file mode 100644
index 0000000..2b7fb25
--- /dev/null
+++ b/board/amlogic/defconfigs/gxl_p271_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_P271_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxl_p281_v1_defconfig b/board/amlogic/defconfigs/gxl_p281_v1_defconfig
new file mode 100644
index 0000000..1ee1ada
--- /dev/null
+++ b/board/amlogic/defconfigs/gxl_p281_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_P281_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxl_p400_v1_defconfig b/board/amlogic/defconfigs/gxl_p400_v1_defconfig
new file mode 100644
index 0000000..f83831e
--- /dev/null
+++ b/board/amlogic/defconfigs/gxl_p400_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_P400_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxl_p401_v1_defconfig b/board/amlogic/defconfigs/gxl_p401_v1_defconfig
new file mode 100644
index 0000000..be3e96f
--- /dev/null
+++ b/board/amlogic/defconfigs/gxl_p401_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_P401_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxl_pxp_defconfig b/board/amlogic/defconfigs/gxl_pxp_defconfig
new file mode 100644
index 0000000..09ae7aa
--- /dev/null
+++ b/board/amlogic/defconfigs/gxl_pxp_defconfig
@@ -0,0 +1,7 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
+CONFIG_PXP_EMULATOR=y
diff --git a/board/amlogic/defconfigs/gxl_s905x_p0_defconfig b/board/amlogic/defconfigs/gxl_s905x_p0_defconfig
new file mode 100644
index 0000000..32e178c
--- /dev/null
+++ b/board/amlogic/defconfigs/gxl_s905x_p0_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_S905X_P0=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxl_skt_v1_defconfig b/board/amlogic/defconfigs/gxl_skt_v1_defconfig
new file mode 100644
index 0000000..c2bc0a5
--- /dev/null
+++ b/board/amlogic/defconfigs/gxl_skt_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXL_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxm_pxp_defconfig b/board/amlogic/defconfigs/gxm_pxp_defconfig
new file mode 100644
index 0000000..9cbd300
--- /dev/null
+++ b/board/amlogic/defconfigs/gxm_pxp_defconfig
@@ -0,0 +1,7 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXM_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
+CONFIG_PXP_EMULATOR=y
diff --git a/board/amlogic/defconfigs/gxm_q200_v1_defconfig b/board/amlogic/defconfigs/gxm_q200_v1_defconfig
new file mode 100644
index 0000000..1829ef0
--- /dev/null
+++ b/board/amlogic/defconfigs/gxm_q200_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXM_Q200_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxm_q201_v1_defconfig b/board/amlogic/defconfigs/gxm_q201_v1_defconfig
new file mode 100644
index 0000000..3e1a114
--- /dev/null
+++ b/board/amlogic/defconfigs/gxm_q201_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXM_Q201_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxm_skt_v1_defconfig b/board/amlogic/defconfigs/gxm_skt_v1_defconfig
new file mode 100644
index 0000000..c66607b
--- /dev/null
+++ b/board/amlogic/defconfigs/gxm_skt_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_GXM_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxtvbb_9023_skt_v1_defconfig b/board/amlogic/defconfigs/gxtvbb_9023_skt_v1_defconfig
new file mode 100644
index 0000000..6a666ce
--- /dev/null
+++ b/board/amlogic/defconfigs/gxtvbb_9023_skt_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GXTV=y
+CONFIG_GXTVBB_9023_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxtvbb_p300_v1_defconfig b/board/amlogic/defconfigs/gxtvbb_p300_v1_defconfig
new file mode 100644
index 0000000..c9fdfcf
--- /dev/null
+++ b/board/amlogic/defconfigs/gxtvbb_p300_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GXTV=y
+CONFIG_GXTVBB_P300_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxtvbb_p301_v1_defconfig b/board/amlogic/defconfigs/gxtvbb_p301_v1_defconfig
new file mode 100644
index 0000000..d0b5938
--- /dev/null
+++ b/board/amlogic/defconfigs/gxtvbb_p301_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GXTV=y
+CONFIG_GXTVBB_P301_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxtvbb_p310_v1_defconfig b/board/amlogic/defconfigs/gxtvbb_p310_v1_defconfig
new file mode 100644
index 0000000..b2e85fc
--- /dev/null
+++ b/board/amlogic/defconfigs/gxtvbb_p310_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GXTV=y
+CONFIG_GXTVBB_P310_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxtvbb_p311_v1_defconfig b/board/amlogic/defconfigs/gxtvbb_p311_v1_defconfig
new file mode 100644
index 0000000..750d2a9
--- /dev/null
+++ b/board/amlogic/defconfigs/gxtvbb_p311_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GXTV=y
+CONFIG_GXTVBB_P311_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxtvbb_pxp_defconfig b/board/amlogic/defconfigs/gxtvbb_pxp_defconfig
new file mode 100644
index 0000000..b2e8529
--- /dev/null
+++ b/board/amlogic/defconfigs/gxtvbb_pxp_defconfig
@@ -0,0 +1,7 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GXTV=y
+CONFIG_GXTVBB_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
+CONFIG_PXP_EMULATOR=y
diff --git a/board/amlogic/defconfigs/gxtvbb_skt_v1_defconfig b/board/amlogic/defconfigs/gxtvbb_skt_v1_defconfig
new file mode 100644
index 0000000..ae11d9b
--- /dev/null
+++ b/board/amlogic/defconfigs/gxtvbb_skt_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GXTV=y
+CONFIG_GXTVBB_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/gxtvbb_t966_skt_v1_defconfig b/board/amlogic/defconfigs/gxtvbb_t966_skt_v1_defconfig
new file mode 100644
index 0000000..651f622
--- /dev/null
+++ b/board/amlogic/defconfigs/gxtvbb_t966_skt_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GXTV=y
+CONFIG_GXTVBB_T966_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/txhd_pxp_defconfig b/board/amlogic/defconfigs/txhd_pxp_defconfig
new file mode 100644
index 0000000..2dc0802
--- /dev/null
+++ b/board/amlogic/defconfigs/txhd_pxp_defconfig
@@ -0,0 +1,7 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_TXHD=y
+CONFIG_TXHD_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
+CONFIG_PXP_EMULATOR=y
diff --git a/board/amlogic/defconfigs/txhd_r341_v1_defconfig b/board/amlogic/defconfigs/txhd_r341_v1_defconfig
new file mode 100644
index 0000000..f94990c
--- /dev/null
+++ b/board/amlogic/defconfigs/txhd_r341_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_TXHD=y
+CONFIG_TXHD_R341_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/txhd_skt_v1_defconfig b/board/amlogic/defconfigs/txhd_skt_v1_defconfig
new file mode 100644
index 0000000..0fe3289
--- /dev/null
+++ b/board/amlogic/defconfigs/txhd_skt_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_TXHD=y
+CONFIG_TXHD_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/txl_p320_v1_defconfig b/board/amlogic/defconfigs/txl_p320_v1_defconfig
new file mode 100644
index 0000000..06f7915
--- /dev/null
+++ b/board/amlogic/defconfigs/txl_p320_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GXTV=y
+CONFIG_TXL_P320_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/txl_p321_v1_defconfig b/board/amlogic/defconfigs/txl_p321_v1_defconfig
new file mode 100644
index 0000000..d307aaf
--- /dev/null
+++ b/board/amlogic/defconfigs/txl_p321_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GXTV=y
+CONFIG_TXL_P321_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/txl_p341_v1_defconfig b/board/amlogic/defconfigs/txl_p341_v1_defconfig
new file mode 100644
index 0000000..056d782
--- /dev/null
+++ b/board/amlogic/defconfigs/txl_p341_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_TXL=y
+CONFIG_TXL_P341_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/txl_p341_v2_defconfig b/board/amlogic/defconfigs/txl_p341_v2_defconfig
new file mode 100644
index 0000000..09a3f2e
--- /dev/null
+++ b/board/amlogic/defconfigs/txl_p341_v2_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_TXL=y
+CONFIG_TXL_P341_V2=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/txl_p346_v1_defconfig b/board/amlogic/defconfigs/txl_p346_v1_defconfig
new file mode 100644
index 0000000..8bbc150
--- /dev/null
+++ b/board/amlogic/defconfigs/txl_p346_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_TXL=y
+CONFIG_TXL_P346_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/txl_pxp_defconfig b/board/amlogic/defconfigs/txl_pxp_defconfig
new file mode 100644
index 0000000..d811065
--- /dev/null
+++ b/board/amlogic/defconfigs/txl_pxp_defconfig
@@ -0,0 +1,7 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GX=y
+CONFIG_TXL_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
+CONFIG_PXP_EMULATOR=y
diff --git a/board/amlogic/defconfigs/txl_skt_v1_defconfig b/board/amlogic/defconfigs/txl_skt_v1_defconfig
new file mode 100644
index 0000000..0c01c3ea
--- /dev/null
+++ b/board/amlogic/defconfigs/txl_skt_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_GXTV=y
+CONFIG_TXL_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/txl_t950_skt_v1_defconfig b/board/amlogic/defconfigs/txl_t950_skt_v1_defconfig
new file mode 100644
index 0000000..79abf77
--- /dev/null
+++ b/board/amlogic/defconfigs/txl_t950_skt_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_TXL=y
+CONFIG_TXL_T950_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/txlx_pxp_defconfig b/board/amlogic/defconfigs/txlx_pxp_defconfig
new file mode 100644
index 0000000..f48eab3
--- /dev/null
+++ b/board/amlogic/defconfigs/txlx_pxp_defconfig
@@ -0,0 +1,7 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_TXLX=y
+CONFIG_TXLX_T962X_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
+CONFIG_PXP_EMULATOR=y
diff --git a/board/amlogic/defconfigs/txlx_t962e_r321_v1_defconfig b/board/amlogic/defconfigs/txlx_t962e_r321_v1_defconfig
new file mode 100644
index 0000000..9af0676
--- /dev/null
+++ b/board/amlogic/defconfigs/txlx_t962e_r321_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_TXLX=y
+CONFIG_TXLX_T962E_R321_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/txlx_t962e_skt_v1_defconfig b/board/amlogic/defconfigs/txlx_t962e_skt_v1_defconfig
new file mode 100644
index 0000000..f4415ca
--- /dev/null
+++ b/board/amlogic/defconfigs/txlx_t962e_skt_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_TXLX=y
+CONFIG_TXLX_T962E_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/txlx_t962x_r311_v1_defconfig b/board/amlogic/defconfigs/txlx_t962x_r311_v1_defconfig
new file mode 100644
index 0000000..b6a2104
--- /dev/null
+++ b/board/amlogic/defconfigs/txlx_t962x_r311_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_TXLX=y
+CONFIG_TXLX_T962X_R311_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/defconfigs/txlx_t962x_skt_v1_defconfig b/board/amlogic/defconfigs/txlx_t962x_skt_v1_defconfig
new file mode 100644
index 0000000..3a6aac2
--- /dev/null
+++ b/board/amlogic/defconfigs/txlx_t962x_skt_v1_defconfig
@@ -0,0 +1,6 @@
+CONFIG_ARM=y
+CONFIG_TARGET_MESON_TXLX=y
+CONFIG_TXLX_T962X_SKT_V1=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_AML_GPIO=y
diff --git a/board/amlogic/g12a_estelle_bx/Kconfig b/board/amlogic/g12a_estelle_bx/Kconfig
new file mode 100755
index 0000000..1537e16
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_G12A
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "g12a_estelle_bx"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "g12a"
+
+config SYS_CONFIG_NAME
+ default "g12a_estelle_bx"
+
+endif
diff --git a/board/amlogic/g12a_estelle_bx/Makefile b/board/amlogic/g12a_estelle_bx/Makefile
new file mode 100755
index 0000000..c9fe5f6
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/Makefile
@@ -0,0 +1,6 @@
+
+obj-y += $(BOARD).o
+obj-$(CONFIG_AML_LCD) += lcd.o
+obj-y += pwm_table.o
+obj-$(CONFIG_ZIRCON_BOOT_IMAGE) += zircon.o zircon_partition.o sysconfig-header.o abr-wear-leveling.o
+obj-$(CONFIG_ZIRCON_VBOOT) += avb.o
diff --git a/board/amlogic/g12a_estelle_bx/abr-wear-leveling.c b/board/amlogic/g12a_estelle_bx/abr-wear-leveling.c
new file mode 100644
index 0000000..0d4cab4
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/abr-wear-leveling.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2020 The Fuchsia Authors
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "abr-wear-leveling.h"
+
+#if defined(ABR_WEAR_LEVELING_DEBUG)
+#define abrwlP(fmt...) \
+ printf("[abr-wear-leveling]%s:%d:", __func__, __LINE__), printf(fmt)
+#else
+#define abrwlP(fmt...)
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void set_abr_metadata_ext_magic(struct abr_metadata_ext *data)
+{
+ data->magic[0] = ABR_WEAR_LEVELING_MAGIC_BYTE_0;
+ data->magic[1] = ABR_WEAR_LEVELING_MAGIC_BYTE_1;
+ data->magic[2] = ABR_WEAR_LEVELING_MAGIC_BYTE_2;
+ data->magic[3] = ABR_WEAR_LEVELING_MAGIC_BYTE_3;
+}
+
+bool abr_metadata_ext_valid(const void *abr_data)
+{
+ const uint8_t *start = (const uint8_t *)abr_data;
+ return start[ABR_WEAR_LEVELING_MAGIC_OFFSET] ==
+ ABR_WEAR_LEVELING_MAGIC_BYTE_0 &&
+ start[ABR_WEAR_LEVELING_MAGIC_OFFSET + 1] ==
+ ABR_WEAR_LEVELING_MAGIC_BYTE_1 &&
+ start[ABR_WEAR_LEVELING_MAGIC_OFFSET + 2] ==
+ ABR_WEAR_LEVELING_MAGIC_BYTE_2 &&
+ start[ABR_WEAR_LEVELING_MAGIC_OFFSET + 3] ==
+ ABR_WEAR_LEVELING_MAGIC_BYTE_3;
+}
+
+bool layout_support_wear_leveling(const struct sysconfig_header *header,
+ size_t page_size)
+{
+ // Abr metadata sub-partition needs to be at the end.
+ return header->abr_metadata.size > page_size &&
+ header->abr_metadata.offset >= header->sysconfig_data.offset &&
+ header->abr_metadata.offset >= header->vb_metadata_a.offset &&
+ header->abr_metadata.offset >= header->vb_metadata_b.offset &&
+ header->abr_metadata.offset >= header->vb_metadata_r.offset;
+}
+
+int find_latest_abr_metadata_page(const struct sysconfig_header *header,
+ const void *abr_subpart, uint64_t page_size,
+ struct abr_metadata_ext *out)
+{
+ // Abr metadatas are appended from the first to the last page in the
+ // sub-partition. Thus, we scan backward and find the first valid
+ // page.
+ int i, num_pages = header->abr_metadata.size / page_size;
+ const uint8_t *start = (const uint8_t *)abr_subpart;
+ abrwlP("Finding page with latest abr metadata\n");
+ for (i = num_pages - 1; i >= 0; i--) {
+ if (abr_metadata_ext_valid(start + i * page_size)) {
+ abrwlP("page %d has valid abr metadata\n", i);
+ memcpy(out, start + i * page_size,
+ sizeof(struct abr_metadata_ext));
+ return i;
+ }
+ }
+ // Default to the first page if there is no page with valid magic,
+ abrwlP("no page with valid magic found. use page 0 as default\n");
+ memcpy(out, start, sizeof(struct abr_metadata_ext));
+ return 0;
+}
+
+bool find_empty_page_for_wear_leveling(const struct sysconfig_header *header,
+ const uint8_t *abr_subpart,
+ uint64_t page_size, int64_t *out)
+{
+ // NAND page programming has to be consecutive from the first to last
+ // within a block. Thus we find the first empty page such that all pages
+ // behind it are also empty, or in other work, the immediate empty page
+ // after the last non-empty page in the sub-partition;
+ int64_t i, j, num_pages = header->abr_metadata.size / page_size;
+
+ const uint8_t *page;
+ abrwlP("Finding empty page, total pages: %lld\n", num_pages);
+ for (i = 1; i <= num_pages; i++) {
+ page = abr_subpart + (num_pages - i) * page_size;
+ bool page_empty = true;
+ // Check whether the page is empty.
+ for (j = 0; j < (int64_t)page_size; j++) {
+ if (page[j] != 0xff) {
+ abrwlP("page %lld, offset %lld = 0x%x != 0xff\n",
+ (num_pages - i), j, page[j]);
+ page_empty = false;
+ break;
+ }
+ }
+
+ if (!page_empty) {
+ abrwlP("page %lld non-empty\n", (num_pages - i));
+ break;
+ }
+
+ abrwlP("page %lld empty\n", (num_pages - i));
+ }
+ *out = num_pages - i + 1;
+ abrwlP("using empty page %lld\n", *out);
+ // If no page is empty, *out will be equal to num_pages.
+ return *out < num_pages;
+}
diff --git a/board/amlogic/g12a_estelle_bx/abr-wear-leveling.h b/board/amlogic/g12a_estelle_bx/abr-wear-leveling.h
new file mode 100644
index 0000000..380a69f
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/abr-wear-leveling.h
@@ -0,0 +1,89 @@
+/**
+ * Copyright (c) 2020 The Fuchsia Authors.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * The header file defines structures and functions for supporting abr wear-leveling
+ * algorithm. The logic are written in C as it needs to be used in both OS
+ * and bootloader.
+ */
+
+#ifndef ABR_WEAR_LEVELING_H_
+#define ABR_WEAR_LEVELING_H_
+
+#include <common.h>
+
+#include "sysconfig-header.h"
+
+#define ABR_WEAR_LEVELING_ABR_DATA_SIZE 32
+#define ABR_WEAR_LEVELING_MAGIC_OFFSET ABR_WEAR_LEVELING_ABR_DATA_SIZE
+#define ABR_WEAR_LEVELING_MAGIC_LEN 4
+#define ABR_WEAR_LEVELING_MAGIC_BYTE_0 0xaa
+#define ABR_WEAR_LEVELING_MAGIC_BYTE_1 0x55
+#define ABR_WEAR_LEVELING_MAGIC_BYTE_2 0x11
+#define ABR_WEAR_LEVELING_MAGIC_BYTE_3 0x22
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Abr metadata extended with a magic for wear-leveling.
+ * Though abr metadata itself comes with a magic. Here we use a separate magic
+ * to avoid exposing internal detail of abr logic to wear-leveling algorithm.
+ */
+struct abr_metadata_ext {
+ uint8_t abr_data[ABR_WEAR_LEVELING_ABR_DATA_SIZE];
+ uint8_t magic[ABR_WEAR_LEVELING_MAGIC_LEN];
+} __attribute__((packed));
+
+/**
+ * Checks whether an abr metadata page is valid in the context of wear-levelingn
+ * It simply checks the magic in abr_metadata_ext.
+ *
+ * Return true if valid, false otherwise.
+ */
+bool abr_metadata_page_valid(const struct abr_metadata_ext *abr_data);
+
+/**
+ * Checks whether the sysconfig layout specified by <header> supports abr wear-leveling.
+ *
+ * Returns true if it supports, false otherwise.
+ */
+bool layout_support_wear_leveling(const struct sysconfig_header *header,
+ size_t page_size);
+
+/**
+ * Finds the latest abr metadata in abr sub-partition given as a memory buffer.
+ * Copies the new data into <out>. The function will check the magic in each page.
+ * If no page contains valid magic, it copies from the first page.
+ *
+ * Returns the page index where the latest page resides.
+ *
+ */
+int find_latest_abr_metadata_page(const struct sysconfig_header *header,
+ const void *abr_subpart, uint64_t page_size,
+ struct abr_metadata_ext *out);
+/**
+ * Finds an valid empty page for appending new abr metadata.
+ * The requirement of consecutive page programming is met by trying to find the
+ * immediate empty page after the last non-empty page in the sub-partition.
+ *
+ * Returns true if there is an empty page to write. The page index will be assigned
+ * to <out>. Returns false otherwise.
+ */
+bool find_empty_page_for_wear_leveling(const struct sysconfig_header *header,
+ const uint8_t *abr_subpart,
+ uint64_t page_size, int64_t *out);
+
+/**
+ * Set the magic field of the given abr_metadata_ext struct.
+ *
+ */
+void set_abr_metadata_ext_magic(struct abr_metadata_ext *data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // LIB_SYSCONFIG_ABR_WEAR_LEVELING_H_
diff --git a/board/amlogic/g12a_estelle_bx/aml-user-key.sig b/board/amlogic/g12a_estelle_bx/aml-user-key.sig
new file mode 100755
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/g12a_estelle_bx/avb.c b/board/amlogic/g12a_estelle_bx/avb.c
new file mode 100644
index 0000000..479468b
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/avb.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2019 The Fuchsia Authors
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm/arch/bl31_apis.h>
+#include <asm/arch/efuse.h>
+#include <common.h>
+#include <libavb/libavb.h>
+#include <libavb_atx/libavb_atx.h>
+#include <u-boot/sha256.h>
+
+#ifdef CONFIG_DEV_BUILD
+#include "avb_dev_attrs/atx_permanent_attrs.h"
+#elif defined(CONFIG_DOGFOOD_BUILD)
+#include "avb_dogfood_attrs/atx_permanent_attrs.h"
+#elif defined(CONFIG_PROD_BUILD)
+#include "avb_prod_attrs/atx_permanent_attrs.h"
+#else
+#error "Unknown build config"
+#endif
+
+#define ROLLBACK_INDEX_BYTES 8
+#define MAX_ROLLBACK_INDEX 8 * ROLLBACK_INDEX_BYTES
+
+#define AVB_ATX_PIK_VERSION_LOCATION_MAX 63
+#define AVB_ATX_PIK_VERSION_LOCATION_MASK \
+ ((1ULL << AVB_ATX_PIK_VERSION_LOCATION_MAX) - 1)
+
+/* Make sure we agree with BL31 on the sizes of the perm attrs and hashes. */
+_Static_assert(sizeof(AvbAtxPermanentAttributes) == PERMANENT_ATTRIBUTES_SIZE,
+ "Permanent attribute size mismatch");
+_Static_assert(sizeof(avb_atx_permanent_attributes_hash) ==
+ PERMANENT_ATTRIBUTES_HASH_SIZE,
+ "Permanent attribute hash size mismatch");
+_Static_assert(sizeof(avb_atx_permanent_attributes_hash) ==
+ AVB_SHA256_DIGEST_SIZE,
+ "AVB digest size mismatch");
+
+AvbIOResult avb_read_permanent_attributes(AvbAtxOps *atx_ops,
+ AvbAtxPermanentAttributes *attributes)
+{
+ int result = bl31_get_permanent_attributes(
+ avb_atx_permanent_attributes_hash, attributes);
+ return (result == 0) ? AVB_IO_RESULT_OK : AVB_IO_RESULT_ERROR_IO;
+}
+
+AvbIOResult
+avb_read_permanent_attributes_hash(AvbAtxOps *atx_ops,
+ uint8_t hash[AVB_SHA256_DIGEST_SIZE])
+{
+ memcpy(hash, avb_atx_permanent_attributes_hash, AVB_SHA256_DIGEST_SIZE);
+ return AVB_IO_RESULT_OK;
+}
+
+/* Reads rollback index from user data area of OTP. */
+AvbIOResult avb_read_rollback_index(AvbOps *ops, size_t rollback_index_location,
+ uint64_t *out_rollback_index)
+{
+#ifdef CONFIG_USE_ROLLBACK_IN_FUSE
+ char buf[ROLLBACK_INDEX_BYTES];
+ uint64_t *fuse_bits;
+ ssize_t ret;
+
+ if ((rollback_index_location >
+ AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS) &&
+ (rollback_index_location != AVB_ATX_PIK_VERSION_LOCATION) &&
+ (rollback_index_location != AVB_ATX_PSK_VERSION_LOCATION)) {
+ return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION;
+ }
+
+ loff_t offset = rollback_index_location * ROLLBACK_INDEX_BYTES;
+
+ ret = efuse_read_usr(buf, ROLLBACK_INDEX_BYTES, &offset);
+ if (ret != ROLLBACK_INDEX_BYTES) {
+ return AVB_SLOT_VERIFY_RESULT_ERROR_IO;
+ }
+ fuse_bits = (uint64_t *)buf;
+
+ if (rollback_index_location == AVB_ATX_PIK_VERSION_LOCATION) {
+ *fuse_bits &= AVB_ATX_PIK_VERSION_LOCATION_MASK;
+ }
+
+ *out_rollback_index = __builtin_popcountl(*fuse_bits);
+#else
+ *out_rollback_index = 0;
+#endif
+ return AVB_IO_RESULT_OK;
+}
+
+/* Writes rollback index to user data area of OTP. If the rollback_index is
+ * less than the current rollback index, the function does nothing and
+ * returns with no error.
+ */
+AvbIOResult avb_write_rollback_index(AvbOps *ops,
+ size_t rollback_index_location,
+ uint64_t rollback_index)
+{
+#ifdef CONFIG_USE_ROLLBACK_IN_FUSE
+ uint64_t cur_index;
+
+ if (rollback_index > MAX_ROLLBACK_INDEX) {
+ return AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE;
+ }
+ // read_rollback_index() performs bounds check on the index location.
+ AvbIOResult ret = avb_read_rollback_index(ops, rollback_index_location,
+ &cur_index);
+ if (ret != AVB_IO_RESULT_OK) {
+ return ret;
+ }
+ if (rollback_index <= cur_index) {
+ return AVB_IO_RESULT_OK;
+ }
+
+ if ((rollback_index_location == AVB_ATX_PIK_VERSION_LOCATION) &&
+ (rollback_index > AVB_ATX_PIK_VERSION_LOCATION_MAX)) {
+ return AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX;
+ }
+
+ loff_t offset = rollback_index_location * ROLLBACK_INDEX_BYTES;
+ uint64_t fuse_bits = (1 << rollback_index) - 1;
+ ssize_t bytes_written = efuse_write_usr((char *)&fuse_bits,
+ ROLLBACK_INDEX_BYTES, &offset);
+ if (bytes_written != ROLLBACK_INDEX_BYTES) {
+ return AVB_SLOT_VERIFY_RESULT_ERROR_IO;
+ }
+#endif
+ return AVB_IO_RESULT_OK;
+}
diff --git a/board/amlogic/g12a_estelle_bx/avb_dev_attrs/atx_permanent_attrs.h b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/atx_permanent_attrs.h
new file mode 100644
index 0000000..467ba32
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/atx_permanent_attrs.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2019 The Fuchsia Authors
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if !defined(CONFIG_DEV_BUILD) || defined(CONFIG_DOGFOOD_BUILD) || \
+ defined(CONFIG_PROD_BUILD)
+#error "Dev permanent attributes can only be used on a dev build"
+#endif
+
+static const uint8_t avb_atx_permanent_attributes_hash[] = {
+ 0xE4, 0xE9, 0x41, 0x69, 0x21, 0x75, 0x10, 0x4D, 0x2B, 0xED, 0xA3,
+ 0x92, 0xBC, 0xA1, 0x61, 0x4A, 0xE0, 0xD6, 0x79, 0x7B, 0x3B, 0xC9,
+ 0x92, 0x56, 0xC7, 0x0F, 0xB3, 0x94, 0x94, 0x31, 0xE7, 0xC3
+};
diff --git a/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_metadata.bin b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_metadata.bin
new file mode 100644
index 0000000..31cf48c
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_metadata.bin
Binary files differ
diff --git a/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_permanent_attributes.bin b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_permanent_attributes.bin
new file mode 100644
index 0000000..ca1fe4f
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_permanent_attributes.bin
Binary files differ
diff --git a/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_pik_certificate.bin b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_pik_certificate.bin
new file mode 100644
index 0000000..b95cc77
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_pik_certificate.bin
Binary files differ
diff --git a/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_psk_certificate.bin b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_psk_certificate.bin
new file mode 100644
index 0000000..84e910b
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_psk_certificate.bin
Binary files differ
diff --git a/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_puk_certificate.bin b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_puk_certificate.bin
new file mode 100644
index 0000000..7fc6232
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_atx_puk_certificate.bin
Binary files differ
diff --git a/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_product_id.bin b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_product_id.bin
new file mode 100644
index 0000000..0fef3c3
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/avb_dev_attrs/estelle_dev_product_id.bin
@@ -0,0 +1 @@
+”3u›¸ë©ä 83ïS,
\ No newline at end of file
diff --git a/board/amlogic/g12a_estelle_bx/avb_dogfood_attrs/atx_permanent_attrs.h b/board/amlogic/g12a_estelle_bx/avb_dogfood_attrs/atx_permanent_attrs.h
new file mode 100644
index 0000000..b776f71
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/avb_dogfood_attrs/atx_permanent_attrs.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2019 The Fuchsia Authors
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if defined(CONFIG_DEV_BUILD) || !defined(CONFIG_DOGFOOD_BUILD) || \
+ defined(CONFIG_PROD_BUILD)
+#error "Dogfood permanent attributes can only be used on a dogfood build"
+#endif
+
+static const uint8_t avb_atx_permanent_attributes_hash[] = {
+ 0xEA, 0x4F, 0x0E, 0x7A, 0xEC, 0x51, 0xCE, 0x37, 0xA6, 0x1C, 0xAC,
+ 0x3F, 0x83, 0xC8, 0x74, 0xB8, 0x4F, 0x04, 0x76, 0xFB, 0xBF, 0x9E,
+ 0x1E, 0xCD, 0xC3, 0x27, 0xBA, 0xD1, 0xDF, 0x98, 0x06, 0x9A
+};
diff --git a/board/amlogic/g12a_estelle_bx/avb_prod_attrs/atx_permanent_attrs.h b/board/amlogic/g12a_estelle_bx/avb_prod_attrs/atx_permanent_attrs.h
new file mode 100644
index 0000000..d097c51
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/avb_prod_attrs/atx_permanent_attrs.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2019 The Fuchsia Authors
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if defined(CONFIG_DEV_BUILD) || defined(CONFIG_DOGFOOD_BUILD) || \
+ !defined(CONFIG_PROD_BUILD)
+#error "Prod permanent attributes can only be used on a prod build"
+#endif
+
+static const uint8_t avb_atx_permanent_attributes_hash[] = {
+ 0xD5, 0x49, 0x6B, 0x9F, 0xEB, 0xEC, 0x71, 0x94, 0x09, 0x35, 0x96,
+ 0xB3, 0x0E, 0xFA, 0x38, 0x95, 0x56, 0x71, 0x63, 0x41, 0x5B, 0x16,
+ 0xC7, 0xDE, 0x45, 0xBE, 0x1E, 0x19, 0xDA, 0x4A, 0x0D, 0x48
+};
diff --git a/board/amlogic/g12a_estelle_bx/firmware/scp_task/dvfs_board.c b/board/amlogic/g12a_estelle_bx/firmware/scp_task/dvfs_board.c
new file mode 100755
index 0000000..2016d3f
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,194 @@
+
+/*
+ * board/amlogic/g12a_estelle_bx/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+/*
+int pwm_voltage_table[ ][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+*/
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~((1 << 21) | 1 << 12);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(1 << 16);
+ P_PIN_MUX_REG10 = reg;//clear reg10
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/g12a_estelle_bx/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12a_estelle_bx/firmware/scp_task/pwm_ctrl.h
new file mode 100755
index 0000000..367eb01
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,40 @@
+/*
+*board/amlogic/g12a_estelle_bx/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 681},
+ { 0x1b0001, 691},
+ { 0x1a0002, 701},
+ { 0x190003, 711},
+ { 0x180004, 721},
+ { 0x170005, 731},
+ { 0x160006, 741},
+ { 0x150007, 751},
+ { 0x140008, 761},
+ { 0x130009, 772},
+ { 0x12000a, 782},
+ { 0x11000b, 792},
+ { 0x10000c, 802},
+ { 0x0f000d, 812},
+ { 0x0e000e, 822},
+ { 0x0d000f, 832},
+ { 0x0c0010, 842},
+ { 0x0b0011, 852},
+ { 0x0a0012, 862},
+ { 0x090013, 872},
+ { 0x080014, 882},
+ { 0x070015, 892},
+ { 0x060016, 902},
+ { 0x050017, 912},
+ { 0x040018, 922},
+ { 0x030019, 932},
+ { 0x02001a, 942},
+ { 0x01001b, 952},
+ { 0x00001c, 962}
+};
+
+#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12a_estelle_bx/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12a_estelle_bx/firmware/scp_task/pwr_ctrl.c
new file mode 100755
index 0000000..c580b64
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,153 @@
+
+/*
+ * board/amlogic/g12a_estelle_bx/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ /*set gpioH_8 low to power off vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+
+ /*set test_n low to power off vcck & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+
+ /*step down ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ /*step up ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+ /*set test_n low to power on vcck & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+ _udelay(100);
+
+ /*set gpioH_8 low to power on vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+ _udelay(10000);
+
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+
+ p->sources = val;
+ p->gpio_info_count = i;
+
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ unsigned char adc_key_cnt = 0;
+ init_remote();
+ saradc_enable();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ do {
+ #ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+ if (cec_power_on_check())
+ exit_reason = CEC_WAKEUP;
+ }
+ #endif
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/g12a_estelle_bx/firmware/timing.c b/board/amlogic/g12a_estelle_bx/firmware/timing.c
new file mode 100755
index 0000000..f519b82
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/firmware/timing.c
@@ -0,0 +1,463 @@
+
+/*
+ * board/amlogic/g12a_estelle_p2/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+
+#ifdef CONFIG_DDR_LOGS_ENABLED
+#define LOG_FLAG 0x9
+#else
+#define LOG_FLAG 0xA
+#endif
+
+ddr_set_t __ddr_setting[] = {
+ {
+ /* g12a skt (u209) ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 1024,
+ .dram_cs1_size_MB = 512,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0c0c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+// .vref_reverse = 0,
+ .ac_trace_delay ={32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = 0,
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = LOG_FLAG,
+ .dram_cs0_size_MB = 1024,
+ .dram_cs1_size_MB = 512,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0c0c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = 0,
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function = {DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING, 0},
+ .dfi_hwtmrl = 4,
+
+ .ac_trace_delay = {
+ 32, 32, 32, 32,
+ 32, 32, 32, 32,
+ 32, 32,
+ },
+
+ .write_dqs_delay = {
+ 163, 163, 163, 163,
+ 167, 167, 165, 165,
+ 159, 159, 163, 163,
+ 165, 165, 161, 161,
+ },
+
+ .read_dqs_delay = {
+ 13, 13, 14, 14,
+ 14, 14, 15, 14,
+ 14, 14, 14, 15,
+ 14, 13, 14, 14,
+ },
+
+ .write_dq_bit_delay = {
+ 20, 21, 19, 21,
+ 21, 21, 22, 20,
+ 22, 21, 20, 20,
+ 19, 21, 18, 21,
+ 20, 20, 24, 20,
+ 22, 25, 24, 25,
+ 26, 26, 23, 20,
+ 21, 20, 23, 21,
+ 21, 23, 23, 20,
+ 48, 49, 48, 50,
+ 50, 50, 51, 49,
+ 49, 21, 21, 19,
+ 20, 21, 19, 20,
+ 21, 20, 22, 18,
+ 20, 23, 23, 24,
+ 24, 24, 22, 17,
+ 18, 17, 20, 18,
+ 18, 21, 20, 19,
+ },
+
+ .read_dq_bit_delay = {
+ 15, 15, 15, 23,
+ 31, 31, 31, 29,
+ 0 , 23, 19, 11,
+ 17, 35, 23, 31,
+ 31, 0 , 15, 3 ,
+ 9 , 15, 27, 27,
+ 35, 35, 0 , 13,
+ 15, 11, 19, 25,
+ 19, 31, 31, 0 ,
+ 15, 17, 15, 19,
+ 31, 33, 31, 27,
+ 0 , 19, 19, 15,
+ 13, 31, 23, 27,
+ 31, 0 , 13, 3 ,
+ 5 , 11, 23, 27,
+ 31, 27, 0 , 13,
+ 13, 9 , 19, 23,
+ 23, 27, 27, 0 ,
+ },
+
+ .read_dqs_gate_delay = {
+ 225, 227, 223, 225,
+ 223, 225, 223, 227,
+ 223, 225, 223, 225,
+ 225, 227, 227, 229,
+ },
+
+ .dq_dqs_delay_flag = DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS|DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ|
+ DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS|DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0000001c
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE PWM table */
+#if (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x0010000c
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x000f000d
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x000e000e
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x000d000f
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x000c0010
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x000b0011
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x000a0012
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x00090013
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x00080014
+#elif (VDDEE_VAL == 890)
+ #define VDDEE_VAL_REG 0x00070015
+#elif (VDDEE_VAL == 900)
+ #define VDDEE_VAL_REG 0x00060016
+#elif (VDDEE_VAL == 910)
+ #define VDDEE_VAL_REG 0x00050017
+#elif (VDDEE_VAL == 920)
+ #define VDDEE_VAL_REG 0x00040018
+#elif (VDDEE_VAL == 930)
+ #define VDDEE_VAL_REG 0x00030019
+#elif (VDDEE_VAL == 940)
+ #define VDDEE_VAL_REG 0x0002001a
+#elif (VDDEE_VAL == 950)
+ #define VDDEE_VAL_REG 0x0001001b
+#elif (VDDEE_VAL == 960)
+ #define VDDEE_VAL_REG 0x0000001c
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ /* eg: PWM init */
+
+ /* PWM_AO_D */
+ /* VCCK_VAL_REG: check PWM table */
+ {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
+ /* PWM_AO_B */
+ /* VDDEE_VAL_REG: check PWM table */
+ {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable 5V_EN */
+ {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Enable VCCK */
+ {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 31), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/g12a_estelle_bx/fvm_ftl_image.h b/board/amlogic/g12a_estelle_bx/fvm_ftl_image.h
new file mode 100644
index 0000000..955a730
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/fvm_ftl_image.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020 The Fuchsia Authors
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * The file should be kept in sync with
+ * src/storage/volume_image/ftl/raw_nand_image.h in the
+ * fuchsia repo
+ */
+
+#define FVM_FTL_IMAGE_REQUIRE_WIPE 1
+#define FVM_FTL_IMAGE_RAW 0
+#define FVM_FTL_IMAGE_ANDROID_SPARSE 1
+
+// Identifies this header.
+#define FVM_FTL_IMAGE_MAGIC 0x12A17178711A711D
+
+// Current major version.
+#define FVM_FTL_IMAGE_MAJOR 1
+
+// Current minor version.
+#define FVM_FTL_IMAGE_MANIOR 1
+
+// Header that precedes a block image, whose block data is being
+// augmented with Out Of Band(OOB) or Spare Area bytes.
+struct RawNandImageHeader {
+ // 64 bits reserved as an indicator of this prelude.
+ uint64_t magic;
+
+ // Major version number for the format.
+ // Crossing this version may break backwards compatibility.
+ uint32_t version_major;
+
+ // Min version number for the format.
+ // Crossing this version will not break backwards compatibility.
+ uint32_t version_minor;
+
+ // Set of blacks to tweak behaviour during the flashing process.
+ // Values must match |RawNandSparseImageFlag| enum.
+ uint32_t flags;
+
+ // Format of the content following the RawNandImageHeader.
+ uint32_t format;
+
+ // Page size used for the data written in the chosen image format.
+ // Must be equal to the target device page size.
+ uint32_t page_size;
+
+ // Out of band bytes used in data written in the chosen image format.
+ // Must be small or equal to the target device OOB byte size.
+ uint8_t oob_size;
+
+ // Reserved
+ uint8_t reserved[3];
+} __attribute__((packed));
diff --git a/board/amlogic/g12a_estelle_bx/g12a_estelle_bx.c b/board/amlogic/g12a_estelle_bx/g12a_estelle_bx.c
new file mode 100644
index 0000000..9885cca
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/g12a_estelle_bx.c
@@ -0,0 +1,1180 @@
+
+/*
+ * board/amlogic/g12a_estelle_bx/g12a_estelle_bx.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <flash_ts.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#ifdef CONFIG_AML_SPIFC
+#include <amlogic/spifc.h>
+#endif
+#ifdef CONFIG_AML_SPICC
+#include <amlogic/spicc.h>
+#endif
+
+#include <linux/mtd/mtd.h>
+/* for reading factory partition */
+#include <../../../fs/ubifs/ubifs.h>
+
+#include <asm/arch/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_check_fdr_for_backlight_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_CMD_NAND
+ extern bool amlnf_is_inited(void);
+ if(!amlnf_is_inited()) {
+ return 0;
+ }
+ flash_ts_init();
+
+ static const char *fts_key = "bootloader.recovery";
+ static const char *fdr = "--wipe_data";
+ static const int fdr_len = sizeof(fdr) - 1;
+ int i;
+
+ char fts_value[256] = { 0 };
+ flash_ts_get(fts_key, fts_value, sizeof(fts_value));
+ int fts_len = strnlen(fts_value, sizeof(fts_value));
+ for (i = 0; i <= fts_len - fdr_len; i++) {
+ if (0 == strncmp(fts_value+i, fdr, fdr_len)) {
+ printf("Reset persistent brightness.\n");
+ writel(0, AO_RTI_STICKY_REG2);
+ break;
+ }
+ }
+#endif /* CONFIG_CMD_NAND */
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ check_fdr_for_backlight_brightness, 1, 0, do_check_fdr_for_backlight_brightness,
+ "check FDR for backlight brightness",
+ " This command will clear backlight brightness level stored in the sticky register when doing FDR\n"
+);
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+//SOC_VDDCPU_DVFS0
+#define VDD_CPU_DVFS0_EN_1 GPIOEE(GPIOZ_13)
+#define VDD_CPU_DVFS0_EN_1_NAME "GPIOZ_13"
+
+//SOC_VDDEE_DVFS0
+#define VDD_GPU_DVFS0_EN_1 GPIOEE(GPIOA_13)
+#define VDD_GPU_DVFS0_EN_1_NAME "GPIOA_13"
+
+//SOC_VDDEE_DVFS1
+#define VDD_GPU_DVFS1_EN_1 GPIOEE(GPIOZ_0)
+#define VDD_GPU_DVFS1_EN_1_NAME "GPIOZ_0"
+
+static void CPU_GPU_Voltage_init(void)
+{
+ int ret;
+
+ ret = gpio_request(VDD_CPU_DVFS0_EN_1,
+ VDD_CPU_DVFS0_EN_1_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", VDD_CPU_DVFS0_EN_1_NAME);
+ return;
+ }
+ gpio_direction_output(VDD_CPU_DVFS0_EN_1, 1);
+
+ //GPU
+ ret = gpio_request(VDD_GPU_DVFS0_EN_1,
+ VDD_GPU_DVFS0_EN_1_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", VDD_GPU_DVFS0_EN_1_NAME);
+ return;
+ }
+ gpio_direction_output(VDD_GPU_DVFS0_EN_1, 0);
+
+ ret = gpio_request(VDD_GPU_DVFS1_EN_1,
+ VDD_GPU_DVFS1_EN_1_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", VDD_GPU_DVFS1_EN_1_NAME);
+ return;
+ }
+ gpio_direction_output(VDD_GPU_DVFS1_EN_1, 1);
+}
+
+// Disable GPIOZ_2, GPIOZ_3, GPIOZ_7, GPIOZ_8, GPIOC_7, GPIOH_8's pull-up
+// so the mute switch and HW id can be read.
+static void gpio_disable_pull(void)
+{
+ int ret;
+
+ ret = readl(PAD_PULL_UP_EN_REG4);
+ writel(ret & (~(1 << 2)), PAD_PULL_UP_EN_REG4);
+
+ ret = readl(PAD_PULL_UP_EN_REG4);
+ writel(ret & (~(1 << 7)), PAD_PULL_UP_EN_REG4);
+
+ ret = readl(PAD_PULL_UP_EN_REG4);
+ writel(ret & (~(1 << 8)), PAD_PULL_UP_EN_REG4);
+
+ ret = readl(PAD_PULL_UP_EN_REG4);
+ writel(ret & (~(1 << 3)), PAD_PULL_UP_EN_REG4);
+
+ ret = readl(PAD_PULL_UP_EN_REG1);
+ writel(ret & (~(1 << 7)), PAD_PULL_UP_EN_REG1);
+
+ ret = readl(PAD_PULL_UP_EN_REG3);
+ writel(ret & (~(1 << 8)), PAD_PULL_UP_EN_REG3);
+}
+
+int do_get_estelle_hw_id(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ unsigned int hw_id = 0, ret = 0;
+ char hw_id_str[8] = {0}; // eg: 0x0A
+
+ // Reading from highest bit to lowest bit
+ // HW_ID_4: GPIOH_8
+ ret = readl(P_PREG_PAD_GPIO3_I);
+ hw_id |= (ret & (1<<8)) >> 8;
+ hw_id = hw_id << 1;
+
+ // HW_ID_3: GPIOC_7
+ ret = readl(P_PREG_PAD_GPIO1_I);
+ hw_id |= (ret & (1<<7)) >> 7;
+ hw_id = hw_id << 1;
+
+ // HW_ID_2: GPIOZ_3
+ ret = readl(P_PREG_PAD_GPIO4_I);
+ hw_id |= (ret & (1<<3)) >> 3;
+ hw_id = hw_id << 1;
+
+ // HW_ID_1: GPIOZ_8
+ ret = readl(P_PREG_PAD_GPIO4_I);
+ hw_id |= (ret & (1<<8)) >> 8;
+ hw_id = hw_id << 1;
+
+ // HW_ID_0: GPIOZ_7
+ ret = readl(P_PREG_PAD_GPIO4_I);
+ hw_id |= (ret & (1<<7)) >> 7;
+
+ snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id);
+ setenv("hw_id", hw_id_str);
+ return 0;
+}
+
+U_BOOT_CMD(
+ get_estelle_hw_id, 1, 0, do_get_estelle_hw_id,
+ "get estelle's HW_ID and setenv 'hw_id'\n",
+ "get_estelle_hw_id"
+);
+
+//SOC_DISP_ID
+#define DISP_ID_PIN GPIOEE(GPIOH_5)
+#define DISP_ID_PIN_NAME "GPIOH_5"
+
+static void panel_detect_init(void)
+{
+ int ret;
+
+ ret = gpio_request(DISP_ID_PIN, DISP_ID_PIN_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", DISP_ID_PIN_NAME);
+ return;
+ }
+ gpio_direction_input(DISP_ID_PIN);
+}
+
+//SOC_BL_ENABLE
+#define BL_ENABLE_PIN GPIOEE(GPIOA_10)
+#define BL_ENABLE_PIN_NAME "GPIOA_10"
+
+static void enable_backlight(bool enable)
+{
+ int ret;
+
+ ret = gpio_request(BL_ENABLE_PIN, BL_ENABLE_PIN_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", BL_ENABLE_PIN_NAME);
+ return;
+ }
+ gpio_direction_output(BL_ENABLE_PIN, enable ? 1 : 0);
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ /* check card detect */
+ clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_AML
+int i2c_set_bus_num(unsigned int busnum);
+int i2c_write(unsigned char chip, unsigned int addr, int alen,
+ unsigned char *buffer, int len);
+struct aml_i2c_platform g_aml_i2c_plat[] = {
+ {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+
+ /* i2c_ao */
+ .master_ao_pinmux = {
+ .sda_reg = (unsigned long)MESON_I2C_AO_M0_SDA_GPIOAO_2_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .sda_mask = MESON_I2C_AO_M0_SDA_GPIOAO_2_MASK,
+#endif
+ .sda_bit = MESON_I2C_AO_M0_SDA_GPIOAO_2_BIT,
+
+ .scl_reg = (unsigned long)MESON_I2C_AO_M0_SCL_GPIOAO_3_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .scl_mask = MESON_I2C_AO_M0_SCL_GPIOAO_3_MASK,
+#endif
+ .scl_bit = MESON_I2C_AO_M0_SCL_GPIOAO_3_BIT,
+ },
+ },
+ {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_A,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+
+ /* i2c0 */
+ .master_a_pinmux = {
+ .sda_reg = (unsigned long)MESON_I2C_EE_M0_SDA_GPIOZ_7_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .sda_mask = MESON_I2C_EE_M0_SDA_GPIOZ_7_MASK,
+#endif
+ .sda_bit = MESON_I2C_EE_M0_SDA_GPIOZ_7_BIT,
+
+ .scl_reg = (unsigned long)MESON_I2C_EE_M0_SCL_GPIOZ_8_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .scl_mask = MESON_I2C_EE_M0_SCL_GPIOZ_8_MASK,
+#endif
+ .scl_bit = MESON_I2C_EE_M0_SCL_GPIOZ_8_BIT,
+ },
+ },
+ {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_D,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ /* i2c3 */
+ .master_d_pinmux = {
+ .sda_reg = (unsigned long)MESON_I2C_EE_M3_SDA_GPIOA_14_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .sda_mask = MESON_I2C_EE_M3_SDA_GPIOA_14_MASK,
+#endif
+ .sda_bit = MESON_I2C_EE_M3_SDA_GPIOA_14_BIT,
+
+ .scl_reg = (unsigned long)MESON_I2C_EE_M3_SCL_GPIOA_15_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .scl_mask = MESON_I2C_EE_M3_SCL_GPIOA_15_MASK,
+#endif
+ .scl_bit = MESON_I2C_EE_M3_SCL_GPIOA_15_BIT,
+ },
+ },
+ /* sign of end */
+ {.master_i2c_speed=0},
+};
+
+static void board_i2c_init(void)
+{
+ extern void aml_i2c_set_ports(struct aml_i2c_platform *i2c_plat);
+ aml_i2c_set_ports(g_aml_i2c_plat);
+
+ udelay(10);
+}
+#endif /* CONFIG_SYS_I2C_AML */
+
+/* Skip the first line and parse one uint
+ * Return negative if not found */
+int parse_calibration_file_string(const char *str)
+{
+ if (str == NULL)
+ return -EINVAL;
+
+ str = strchr(str, '\n');
+ if (str == NULL)
+ return -EINVAL;
+ ++str;
+
+ return simple_strtoul(str, NULL, 10);
+}
+
+/* If zero, this value has not been set and the default brightness should not be
+ * overwritten. To store zero, store a non-zero value with its bottom 12 bits
+ * all zero, like 0x1000.
+ */
+int get_persistent_brightness(void)
+{
+ u32 brightness_sticky_val = readl(AO_RTI_STICKY_REG2);
+ if (brightness_sticky_val != 0)
+ return (brightness_sticky_val & 0x0fff) >> 1;
+ return -1;
+}
+
+int do_configure_backlight(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+#ifdef CONFIG_SYS_I2C_AML
+ int ret, i, attempt;
+ const int retries = 3;
+ char *addr_cal;
+ int calibrated_current, persistent_brightness;
+
+ /* Values to write:
+ * [0]: Brightness register control only, backlight enabled
+ * [1-2]: Standby disabled, 20mA MAX_CURRENT, CURRENT scale 1/2
+ * [3]: Enable undervoltage protection at 5.2 V, "disable" backlight
+ * (i2c only), disable set resistors
+ * [4]: 9.6kHz PWM rate, 3 phase drivers
+ * [5]: EN_DRV3, EN_DRV2, boost inductor current limit = 1.6 A
+ * [6]: VBOOST_MAX = 25 V, JUMP_EN = 0
+ * [7]: STEP_UP = 105 mV, STEP_DN = 105 mV, LED_FAULT_TH = 3V,
+ * LED_COMP_HYST = DRIVER_HEADROOM + 750 mV
+ * [8-9]: 12-bit brightness (default: 100%)
+ * Important: Write brightness last to apply current calibration */
+ const __u8 addrs[] = {0x01, 0xa0, 0xa1, 0xa2, 0xa5, 0xa7, 0xa9, 0xae,
+ 0x10, 0x11};
+ __u8 values[] = {0x85, 0xff, 0x37, 0x30, 0x54, 0xf4, 0x60, 0x09, 0xff,
+ 0x0f};
+ const int n_bytes = sizeof(values)/sizeof(values[0]);
+
+ if (argc > 2) {
+ printf("%s: Too many args: %d\n", __func__, argc);
+ return CMD_RET_USAGE;
+ }
+
+ if (argc == 2) {
+ addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
+ calibrated_current = parse_calibration_file_string(addr_cal);
+ if (calibrated_current >= 0 && calibrated_current <= 4095) {
+ /* CURRENT_LSB */
+ values[1] = 0xff & calibrated_current;
+ /* CURRENT_MSB */
+ values[2] = (values[2] & 0xf0) |
+ (0x0f & (calibrated_current >> 8));
+ }
+ }
+
+ // Apply persistent brightness if found
+ persistent_brightness = get_persistent_brightness();
+ if (persistent_brightness >= 0) {
+ printf("Applying persistent_brightness=%d\n", persistent_brightness);
+ /* Get LSB and MSB */
+ values[n_bytes - 2] = persistent_brightness & 0xff;
+ values[n_bytes - 1] = persistent_brightness >> 8 & 0x0f;
+ } else {
+ printf("Persistent_brightness not set\n");
+ }
+
+ enable_backlight(true);
+
+ i2c_set_bus_num(AML_I2C_MASTER_D);
+ for (i = 0; i < n_bytes; ++i) {
+ for (attempt = 0; attempt < retries; ++attempt) {
+ ret = i2c_write(0x2c, addrs[i], 1, &values[i], 1);
+ if (ret)
+ printf("%s: Attempt=%d to write byte=0x%02x to reg=0x%02x of backlight failed\n",
+ __func__, attempt, values[i], addrs[i]);
+ else
+ break;
+ }
+ }
+
+ return ret;
+#else
+ enable_backlight(true);
+
+ return 0;
+#endif /* CONFIG_SYS_I2C_AML */
+}
+
+U_BOOT_CMD(
+ configure_backlight, 2, 0, do_configure_backlight,
+ "configures the lp8556 backlight",
+ "Usage: configure_backlight [calibration_string_addr]\n"\
+ " Sets up required parameters of the backlight.\n"\
+ " Default calibration is 100%.\n"\
+ " calibration_str_addr (optional):\n"\
+ " Address of calibration file string to parse.\n"
+);
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM 1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_USB_GPIO_PWR,
+ CONFIG_USB_GPIO_PWR_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_USB_GPIO_PWR);
+ return;
+ }
+
+ if (is_power_on) {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
+ } else {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+ .usb_phy2_pll_base_addr = {
+ CONFIG_USB_PHY_20,
+ CONFIG_USB_PHY_21,
+ }
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "fts",
+ .offset = 0,
+ .size = 1*SZ_1M,
+ },
+ {
+ .name = "factory",
+ .offset = 0,
+ .size = 8*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 216*SZ_1M,
+ },
+ {
+ .name = "cache",
+ .offset = 0,
+ .size = 237*SZ_1M,
+ },
+ {
+ .name = "sys-config",
+ .offset = 0,
+ .size = 1*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "migration",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ * This is the partition table used for estelle b3 and b4.
+ * Please check go/estelle-partition
+ */
+static struct mtd_partition normal_partition_info_dvt_pvt[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "fts",
+ .offset = 0,
+ .size = 1*SZ_1M,
+ },
+ {
+ .name = "factory",
+ .offset = 0,
+ .size = 8*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 24*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 208*SZ_1M,
+ },
+ {
+ .name = "cache",
+ .offset = 0,
+ .size = 237*SZ_1M,
+ },
+ {
+ .name = "sys-config",
+ .offset = 0,
+ .size = 1*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "migration",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ if(!strncmp(BOARD_NAME, "estelle-b3", sizeof(BOARD_NAME)) ||
+ !strncmp(BOARD_NAME, "estelle-b4", sizeof(BOARD_NAME)))
+ return normal_partition_info_dvt_pvt;
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ if(!strncmp(BOARD_NAME, "estelle-b3", sizeof(BOARD_NAME)) ||
+ !strncmp(BOARD_NAME, "estelle-b4", sizeof(BOARD_NAME)))
+ return ARRAY_SIZE(normal_partition_info_dvt_pvt);
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xfffff << 12);
+ if (enable)
+ val |= 0x33333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~(0xf << 24);
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xf6000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+#ifdef CONFIG_AML_SPICC
+/* generic config in arch gpio/clock.c */
+extern int spicc1_clk_set_rate(int rate);
+extern int spicc1_clk_enable(bool enable);
+extern int spicc1_pinctrl_enable(bool enable);
+
+static const struct spicc_platdata spicc1_platdata = {
+ .compatible = "amlogic,meson-g12a-spicc",
+ .reg = (void __iomem *)0xffd15000,
+ .clk_rate = 666666666,
+ .clk_set_rate = spicc1_clk_set_rate,
+ .clk_enable = spicc1_clk_enable,
+ .pinctrl_enable = spicc1_pinctrl_enable,
+ /* case one slave without cs: {"no_cs", 0} */
+ .cs_gpio_names = {"GPIOH_6", 0},
+};
+
+U_BOOT_DEVICE(spicc1) = {
+ .name = "spicc",
+ .platdata = &spicc1_platdata,
+};
+#endif /* CONFIG_AML_SPICC */
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+ CPU_GPU_Voltage_init();
+ enable_backlight(false);
+ panel_detect_init();
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+ //As NOT NEED other board init If USB BOOT MODE
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+ board_usb_pll_disable(&g_usb_config_GXL_skt);
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_SYS_I2C_AML
+ board_i2c_init();
+#endif
+
+ /* TODO(b/110040521): This is the earliest the backlight can be started,
+ * but the LCD is not running yet. */
+
+#if 0
+ aml_pwm_cal_init(0);
+#endif//
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ gpio_disable_pull();
+
+ return 0;
+}
+
+/* Estelle device SN is 12 symbols */
+#define SN_SIZE 12
+
+/*
+ * Set serial number from ubi:factory partition into
+ * "serial" environment
+ */
+static int set_serial_number(void)
+{
+ char sn[SN_SIZE + 1];
+ int ret;
+
+ ret = ubi_mtd_param_parse("factory", NULL);
+ if (ret) {
+ printf("%s: ERROR: ubi_mtd_param_parse() failed\n", __func__);
+ return ret;
+ }
+
+ ret = ubi_init();
+ if (ret) {
+ printf("%s: ERROR: ubi_init() failed\n", __func__);
+ return ret;
+ }
+
+ ret = ubifs_init();
+ if (ret < 0) {
+ printf("%s: ERROR: ubifs_init() failed\n", __func__);
+ goto fail_init;
+ }
+
+ ret = uboot_ubifs_mount("ubi:factory");
+ if (ret < 0) {
+ printf("%s: ERROR: uboot_ubifs_mount() failed\n", __func__);
+ goto fail;
+ }
+
+ ret = ubifs_load("serial.txt", (u32) (uintptr_t) sn, SN_SIZE);
+ if (ret < 0) {
+ printf("%s: ERROR: ubifs_load() failed\n", __func__);
+ goto fail;
+ }
+
+ sn[SN_SIZE] = '\0';
+
+ ret = setenv("serial", sn);
+ if (ret) {
+ printf("%s: ERROR: setenv() failed\n", __func__);
+ }
+
+fail:
+ if (ubifs_sb) {
+ ubifs_umount(ubifs_sb->s_fs_info);
+ }
+
+fail_init:
+ ubi_exit();
+
+ return ret;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ run_command("defenv", 0);
+ run_command("run detect_panel", 0);
+#if 0
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+#ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+#endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#endif
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ if (set_serial_number()) {
+ printf("%s: Warning: failed to set serial number.\n", __func__);
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 1 p321 v1
+ * hwid = 2 p321 v2
+ */
+ unsigned int hwid = 1;
+ char loc_name[64] = {0};
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+
+ switch (hwid) {
+ case 1:
+ strcpy(loc_name, "txl_p321_v1\0");
+ break;
+ case 2:
+ strcpy(loc_name, "txl_p321_v2\0");
+ break;
+ default:
+ strcpy(loc_name, "txl_p321_v1");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+/* workaround for VDDEE issue */
+/* VCCK PWM table */
+#define VCCK_VAL_REG_800 0x00150007
+#define VCCK_VAL_REG_810 0x00140008
+#define VCCK_VAL_REG_820 0x00130009
+#define VCCK_VAL_REG_830 0x0012000a
+#define VCCK_VAL_REG_840 0x0011000b
+#define VCCK_VAL_REG_850 0x0010000c
+#define VCCK_VAL_REG_860 0x000f000d
+#define VCCK_VAL_REG_870 0x000e000e
+#define VCCK_VAL_REG_880 0x000d000f
+#define VCCK_VAL_REG_890 0x000c0010
+#define VCCK_VAL_REG_900 0x000b0011
+#define VCCK_VAL_REG_910 0x000a0012
+#define VCCK_VAL_REG_920 0x00090013
+#define VCCK_VAL_REG_930 0x00080014
+#define VCCK_VAL_REG_940 0x00070015
+#define VCCK_VAL_REG_950 0x00060016
+#define VCCK_VAL_REG_960 0x00050017
+#define VCCK_VAL_REG_970 0x00040018
+#define VCCK_VAL_REG_980 0x00030019
+#define VCCK_VAL_REG_990 0x0002001a
+#define VCCK_VAL_REG_1000 0x0001001b
+#define VCCK_VAL_REG_1010 0x0000001c
+#define VCCK_VAL_REG_DEFAULT 0x00500008
+
+/* VDDEE PWM table */
+#define VDDEE_VAL_REG_800 0x0010000c
+#define VDDEE_VAL_REG_810 0x000f000d
+#define VDDEE_VAL_REG_820 0x000e000e
+#define VDDEE_VAL_REG_830 0x000d000f
+#define VDDEE_VAL_REG_840 0x000c0010
+#define VDDEE_VAL_REG_850 0x000b0011
+#define VDDEE_VAL_REG_860 0x000a0012
+#define VDDEE_VAL_REG_870 0x00090013
+#define VDDEE_VAL_REG_880 0x00080014
+#define VDDEE_VAL_REG_890 0x00070015
+#define VDDEE_VAL_REG_900 0x00060016
+#define VDDEE_VAL_REG_910 0x00050017
+#define VDDEE_VAL_REG_920 0x00040018
+#define VDDEE_VAL_REG_930 0x00030019
+#define VDDEE_VAL_REG_940 0x0002001a
+#define VDDEE_VAL_REG_950 0x0001001b
+#define VDDEE_VAL_REG_960 0x0000001c
+#define VDDEE_VAL_REG_DEFAULT 0x00500008
+
+void reset_misc(void)
+{
+ unsigned int value;
+
+ /* adjust VDDCPU to Hiz value step by step */
+ writel(VCCK_VAL_REG_830, AO_PWM_PWM_D);
+ udelay(1);
+ writel(VCCK_VAL_REG_860, AO_PWM_PWM_D);
+ udelay(1);
+
+ /* GPIOE_0 & GPIOE_1 to gpio pin */
+ value = readl(AO_RTI_PINMUX_REG1);
+ value &= ~(0xff << 16);
+ writel(value, AO_RTI_PINMUX_REG1);
+
+ /* disable pwm_ao_b - VDDEE */
+ value = readl(AO_PWM_MISC_REG_AB);
+ value &= ~((0x1 << 1) | (0x1 << 23));
+ writel(value, AO_PWM_MISC_REG_AB);
+ writel(VDDEE_VAL_REG_DEFAULT, AO_PWM_PWM_B);
+
+ /* disable pwm_ao_d - VDDCPU_B*/
+ value = readl(AO_PWM_MISC_REG_CD);
+ value &= ~((0x1 << 1) | (0x1 << 23));
+ writel(value, AO_PWM_MISC_REG_CD);
+ writel(VCCK_VAL_REG_DEFAULT, AO_PWM_PWM_D);
+}
+
+#ifdef CONFIG_FORCE_FASTBOOT_TIMEOUT_MS
+
+/* 2^5 = 32 samples during CONFIG_FORCE_FASTBOOT_TIMEOUT_MS period */
+#define FORCE_FASTBOOT_SAMPLING_RATE 5
+#define FORCE_FASTBOOT_LISTEN_KEY 'f'
+
+/*
+ * Fastboot mode is triggered during boot time when the UART serial interface receives a
+ * FORCE_FASTBOOT_LISTEN_KEY character during the listen window.
+ */
+bool force_fastboot_mode(void)
+{
+ uint64_t start_ticks = get_ticks();
+ uint64_t threshold = CONFIG_FORCE_FASTBOOT_TIMEOUT_MS * (get_tbclk() / 1000);
+ uint64_t wait_delay = CONFIG_FORCE_FASTBOOT_TIMEOUT_MS >> FORCE_FASTBOOT_SAMPLING_RATE;
+
+ do {
+ /* Flush the entire key buffer on each loop so that timeout==0 will
+ still check all buffered keys. */
+ while (tstc()) {
+ if (getc() == FORCE_FASTBOOT_LISTEN_KEY) {
+ return true;
+ }
+ }
+
+ __udelay(wait_delay);
+ } while ((get_ticks() - start_ticks) < threshold);
+
+ return false;
+}
+#endif /* CONFIG_FORCE_FASTBOOT_TIMEOUT_MS */
diff --git a/board/amlogic/g12a_estelle_bx/lcd.c b/board/amlogic/g12a_estelle_bx/lcd.c
new file mode 100755
index 0000000..8d836aa
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/lcd.c
@@ -0,0 +1,527 @@
+/*
+ * AMLOGIC TV LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_6", /* panel rst */
+ "GPIOZ_8", /* panel power */
+ "invalid", /* ending flag */
+};
+
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd power */
+#if 1
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,
+ /* custome */
+ Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,1,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_EXTERN,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_EXTERN,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM_FT*/
+ "lcd_3",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,3,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB_FT*/
+ "lcd_4",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,770,1070,10,80,0,6,20,0,
+ /* clk_attr */
+ 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,4,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOH_5
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+static unsigned char mipi_init_on_table[] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xff, 20,
+ 0x05, 1, 0x29,
+ 0xff, 20,
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table[] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xff, 10,
+ 0x05, 1, 0x10,
+ 0xff, 10,
+ 0xff,0xff, //ending flag
+};
+static unsigned char mipi_init_on_table_TV070WSM[] = {//table size < 100
+ 0xff, 10,
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
+ 0xff, 10, /* delay */
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TV070WSM[] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+static unsigned char mipi_init_on_table_P070ACB[] = {//table size < 100
+ 0xff, 10,
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
+ 0xff, 10, /* delay */
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_P070ACB[] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 2, /* ext_index if needed, must match ext_config_dtf.index;*/
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_clk_path = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0xff, //ending flag
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff,0xff, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 5,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = 1,
+ .name = "mipi_TV070WSM",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = 2,
+ .name = "mipi_P070ACB",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = 3,
+ .name = "mipi_TV070WSM_FT",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = 4,
+ .name = "mipi_P070ACB_FT",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_EXTERN,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "i2c_lp8556",
+ .type = BL_EXTERN_I2C,
+ .i2c_addr = 0x2c,
+ .i2c_bus = BL_EXTERN_I2C_BUS_D,
+ .dim_min = 10,
+ .dim_max = 255,
+};
+#endif
+
+extern int i2c_set_bus_num(unsigned int busnum);
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 3:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 4:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_BL_EXTERN
+ i2c_set_bus_num(BL_EXTERN_I2C_BUS_D);
+#endif
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/g12a_estelle_bx/pwm_table.c b/board/amlogic/g12a_estelle_bx/pwm_table.c
new file mode 100755
index 0000000..18dc638
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/pwm_table.c
@@ -0,0 +1,71 @@
+#include <common.h>
+
+const int pwm_cal_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+const int pwm_cal_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
+int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
+
+
diff --git a/board/amlogic/g12a_estelle_bx/sysconfig-header.c b/board/amlogic/g12a_estelle_bx/sysconfig-header.c
new file mode 100644
index 0000000..ba7376f
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/sysconfig-header.c
@@ -0,0 +1,121 @@
+#include "sysconfig-header.h"
+
+static bool subpartition_page_aligned(const struct sysconfig_subpartition *part,
+ uint64_t page_size)
+{
+ // It shall be page-aligned.
+ if (part->size % page_size || part->offset % page_size) {
+ return false;
+ }
+
+ return true;
+}
+
+static bool subpartition_not_on_page0(const struct sysconfig_subpartition *part,
+ uint64_t page_size)
+{
+ return part->offset >= page_size;
+}
+
+static bool subpartition_out_of_range(const struct sysconfig_subpartition *part,
+ uint64_t page_size,
+ uint64_t partition_size)
+{
+ // It shall fit into sysconfig partition size.
+ if (part->size > partition_size ||
+ part->offset > partition_size - part->size) {
+ return false;
+ }
+
+ return true;
+}
+
+static bool subpartition_disjoint(const struct sysconfig_subpartition *part_a,
+ const struct sysconfig_subpartition *part_b)
+{
+ return part_a->offset + part_a->size <= part_b->offset ||
+ part_b->offset + part_b->size <= part_a->offset;
+}
+
+bool
+sysconfig_header_valid(const struct sysconfig_header *header,
+ uint64_t page_size, uint64_t partition_size)
+{
+ // Conditions:
+ // 1. valid magic.
+ // 2. valid crc.
+ // 3. sub-partition fits into partition.
+ // 4. sub-partitions do not overlap.
+ // 5. the first page is reserved for header.
+
+ if (memcmp(header->magic, SYSCONFIG_HEADER_MAGIC_STR,
+ sizeof(header->magic))) {
+ syshdrP("Header has invalid magic.\n");
+ return false;
+ }
+
+ if (header->crc_value !=
+ sysconfig_header_crc32(0, (const uint8_t *)header,
+ offsetof(struct sysconfig_header,
+ crc_value))) {
+ syshdrP("Header has invalid crc.\n");
+ return false;
+ }
+
+ struct sysconfig_subpartition all_parts[] = { header->abr_metadata,
+ header->sysconfig_data,
+ header->vb_metadata_a,
+ header->vb_metadata_b,
+ header->vb_metadata_r };
+
+ int i, j;
+ int num_subparts =
+ sizeof(all_parts) / sizeof(struct sysconfig_subpartition);
+ for (i = 0; i < num_subparts; i++) {
+ if (!subpartition_page_aligned(&all_parts[i], page_size)) {
+ syshdrP("sub-partition %d is not page-aligned\n", i);
+ return false;
+ }
+
+ if (!subpartition_out_of_range(&all_parts[i], page_size,
+ partition_size)) {
+ syshdrP("sub-partition %d is out-of-range\n", i);
+ return false;
+ }
+
+ if (!subpartition_not_on_page0(&all_parts[i], page_size)) {
+ syshdrP("sub-partition %d occupies page0 reserved for header\n",
+ i);
+ return false;
+ }
+
+ for (j = i + 1; j < num_subparts; j++) {
+ if (!subpartition_disjoint(&all_parts[i],
+ &all_parts[j])) {
+ syshdrP("sub-partition %d and %d overlap\n", i,
+ j);
+ return false;
+ }
+ }
+ }
+
+ return true;
+}
+
+bool sysconfig_header_equal(const struct sysconfig_header *lhs,
+ const struct sysconfig_header *rhs)
+{
+ return memcmp(lhs, rhs, offsetof(struct sysconfig_header, crc_value)) ==
+ 0;
+}
+
+void update_sysconfig_header_magic_and_crc(struct sysconfig_header *header)
+{
+ memcpy(header->magic, SYSCONFIG_HEADER_MAGIC_STR,
+ sizeof(header->magic));
+ memset(header->reserved, 0, 4);
+ header->crc_value = sysconfig_header_crc32(
+ 0, (const uint8_t *)header,
+ offsetof(struct sysconfig_header, crc_value));
+}
+
diff --git a/board/amlogic/g12a_estelle_bx/sysconfig-header.h b/board/amlogic/g12a_estelle_bx/sysconfig-header.h
new file mode 100644
index 0000000..72d2272
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/sysconfig-header.h
@@ -0,0 +1,93 @@
+// Copyright 2019 The Fuchsia Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE file.
+
+// The header defines structures and functions for supporting header-based
+// reconfigurable sysconfig partition layout. The logic are written in C
+// as it needs to be used in both OS and bootloader.
+#ifndef LIB_SYSCONFIG_SYSCONFIG_HEADER_H_
+#define LIB_SYSCONFIG_SYSCONFIG_HEADER_H_
+
+#include <common.h>
+
+#define SYSCONFIG_HEADER_MAGIC_ARRAY \
+ { \
+ 'S', 'C', 'F', 'G' \
+ }
+#define SYSCONFIG_HEADER_MAGIC_STR "SCFG"
+
+#if defined(SYSCONFIG_HEADER_DEBUG)
+#define syshdrP(fmt...) \
+ printf("[sysconfig-header]%s:%d:", __func__, __LINE__), printf(fmt)
+#else
+#define syshdrP(fmt...)
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// The following structures model header based sysconfig partition layout.
+struct sysconfig_subpartition {
+ uint64_t offset;
+ uint64_t size;
+} __attribute__((packed));
+
+struct sysconfig_header {
+ uint8_t magic[4];
+ uint8_t reserved[4];
+ struct sysconfig_subpartition sysconfig_data;
+ struct sysconfig_subpartition abr_metadata;
+ struct sysconfig_subpartition vb_metadata_a;
+ struct sysconfig_subpartition vb_metadata_b;
+ struct sysconfig_subpartition vb_metadata_r;
+ uint32_t crc_value;
+} __attribute__((packed));
+
+_Static_assert(sizeof(struct sysconfig_header) == 92,
+ "Unexpected size of sysconfig_header.");
+
+#define SYSCONFIG_HEADER_SIZE sizeof(struct sysconfig_header)
+
+/**
+ * Check whether two sysconfig_header, represented by <lhs> and <rhs> are
+ * equal. It will not take into consideration of <crc_value> field.
+ *
+ * Return true if equal, false if not equal
+ */
+bool sysconfig_header_equal(const struct sysconfig_header *lhs,
+ const struct sysconfig_header *rhs);
+
+/**
+ * Forward declaration of crc32 function. It is provided by the system and
+ * will be used in update_sysconfig_header_magic_and_crc.
+ *
+ */
+uint32_t sysconfig_header_crc32(uint32_t crc, const uint8_t *buf, size_t len);
+
+/**
+ * Check whether a given sysconfig_header is valid w.r.t the page size and
+ * total sysconfig partition size. Conditions to check include:
+ * 1. valid magic.
+ * 2. valid crc.
+ * 3. sub-partition fits into partition.
+ * 4. sub-partitions do not overlap.
+ * 5. the first page is reserved for header.
+ *
+ * Return true if valid, false if not valid.
+ */
+bool
+sysconfig_header_valid(const struct sysconfig_header *header,
+ uint64_t page_size, uint64_t partition_size);
+
+/**
+ * Compute and set the crc_value field and the magic array of the given header.
+ *
+ */
+void update_sysconfig_header_magic_and_crc(struct sysconfig_header *header);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // LIB_SYSCONFIG_SYSCONFIG_HEADER_H_
diff --git a/board/amlogic/g12a_estelle_bx/zircon.c b/board/amlogic/g12a_estelle_bx/zircon.c
new file mode 100644
index 0000000..654aa43
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/zircon.c
@@ -0,0 +1,937 @@
+/*
+ * Copyright (c) 2018 The Fuchsia Authors
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <aml_i2c.h>
+#include <asm/arch/efuse.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/reboot.h>
+#include <command.h>
+#include <common.h>
+#include <storage.h>
+#include <version.h>
+#include <wdt.h>
+#include <zbi/zbi.h>
+#include <zircon/boot/bootfs.h>
+#include <zircon/boot/image.h>
+#include <zircon-estelle/fw-testing.h>
+#include <zircon-estelle/partition.h>
+#include <zircon-estelle/vboot.h>
+#include <zircon-estelle/zircon.h>
+
+// for reading factory partition
+#include <../../../fs/ubifs/ubifs.h>
+
+// bitmask for determining whether the RNG_USR_DATA register is ready.
+// This mask should be applied to the RNG_USR_STS register.
+// 0: The RNG_USR_DATA register is not ready to be read from.
+// 1: The RNG_USR_DATA register is ready to be read from.
+#define USR_RAND32_RDY 0x1
+
+#define PDEV_VID_GOOGLE 3
+#define PDEV_PID_ASTRO 3
+
+#define NVRAM_LENGTH (8 * 1024)
+
+// Size of the CMDLINE entropy string.
+#define CMDLINE_ENTROPY_SIZE 1024
+
+// Random bits to pass to zircon.
+#define CMDLINE_ENTROPY_BITS 256
+
+// Deadline for time waiting for the RNG_USR_STS register to be ready.
+// This is a very generous value, given that after reading from
+// the hw rng, we should expect it to be available after
+// HW_RNG_RESEEDING_INTERVAL_MICROS.
+#define ENTROPY_COLLECTION_DEADLINE_MICROS 100000
+
+// HW RNG is reseeded every 40 microseconds.
+#define HW_RNG_RESEEDING_INTERVAL_MICROS 40
+
+#define ENTROPY_BITS_PER_CHAR 4
+
+#ifdef DEBUG
+#define debugP(fmt...) printf("[Dbg %s]L%d:", __func__, __LINE__), printf(fmt)
+#else
+#define debugP(fmt...)
+#endif
+
+static const char zircon_entropy_arg[] = "kernel.entropy-mixin=";
+static char entropy_cmdline[CMDLINE_ENTROPY_SIZE] = { 0 };
+
+_Static_assert(CMDLINE_ENTROPY_BITS % 32 == 0,
+ "Requested entropy must be a multiple of 32");
+
+_Static_assert((CMDLINE_ENTROPY_BITS / ENTROPY_BITS_PER_CHAR) +
+ sizeof(zircon_entropy_arg) <
+ CMDLINE_ENTROPY_SIZE,
+ "Requested entropy doesn't fit in cmdline.");
+
+static const zbi_cpu_config_t cpu_config = {
+ .cluster_count = 1,
+ .clusters = {
+ {
+ .cpu_count = 4,
+ },
+ },
+};
+
+static const zbi_mem_range_t mem_config[] = {
+ {
+ .type = ZBI_MEM_RANGE_RAM,
+ .length = 0x60000000, // 1.5 GB
+ },
+ {
+ .type = ZBI_MEM_RANGE_PERIPHERAL,
+ .paddr = 0xf5800000,
+ .length = 0x0a800000,
+ },
+ // secmon_reserved:linux,secmon
+ {
+ .type = ZBI_MEM_RANGE_RESERVED,
+ .paddr = 0x05000000,
+ .length = 0x2400000,
+ },
+ // logo_reserved:linux,meson-fb
+ {
+ .type = ZBI_MEM_RANGE_RESERVED,
+ .paddr = 0x5f800000,
+ .length = 0x800000,
+ },
+};
+
+static const dcfg_simple_t uart_driver = {
+ .mmio_phys = 0xff803000,
+ .irq = 225,
+};
+
+static const dcfg_arm_gicv2_driver_t gicv2_driver = {
+ .mmio_phys = 0xffc00000,
+ .gicd_offset = 0x1000,
+ .gicc_offset = 0x2000,
+ .gich_offset = 0x4000,
+ .gicv_offset = 0x6000,
+ .ipi_base = 5,
+};
+
+static const dcfg_arm_psci_driver_t psci_driver = {
+ .use_hvc = false,
+ .reboot_args = { 1, 0, 0 },
+ .reboot_bootloader_args = { 4, 0, 0 },
+ .reboot_recovery_args = { 2, 0, 0 },
+};
+
+static const dcfg_arm_generic_timer_driver_t timer_driver = {
+ .irq_phys = 30,
+};
+
+static const dcfg_amlogic_rng_driver_t rng_driver = {
+ .rng_data_phys = (uint64_t)P_RNG_USR_DATA,
+ .rng_status_phys = (uint64_t)P_RNG_USR_STS,
+ .rng_refresh_interval_usec = HW_RNG_RESEEDING_INTERVAL_MICROS,
+};
+
+#define WDT_CTRL 0xffd0f0d0
+#define WDT_PET 0xffd0f0dc
+
+#define WATCHDOG_TIMEOUT_SECONDS 5
+#define SECONDS_TO_NANOSECONDS 1000000000LL
+
+#ifdef CONFIG_FIRMWARE_TESTING_DEV_BUILD
+static dcfg_generic_32bit_watchdog_t watchdog_driver = {
+#else
+static const dcfg_generic_32bit_watchdog_t watchdog_driver = {
+#endif
+ .pet_action = {
+ .addr = WDT_PET,
+ .clr_mask = 0xffffffff,
+ .set_mask = 0x00000000,
+ },
+ .enable_action = {
+ .addr = WDT_CTRL,
+ .clr_mask = 0x00000000,
+ .set_mask = 0x00040000,
+ },
+ .disable_action = {
+ .addr = WDT_CTRL,
+ .clr_mask = 0x00040000,
+ .set_mask = 0x00000000,
+ },
+ .watchdog_period_nsec =
+ WATCHDOG_TIMEOUT_SECONDS * SECONDS_TO_NANOSECONDS,
+ .flags = KDRV_GENERIC_32BIT_WATCHDOG_FLAG_ENABLED,
+};
+
+#ifdef CONFIG_FIRMWARE_TESTING_DEV_BUILD
+/**
+ * disable_watchdog_petting() - disable petting of watchdog
+ *
+ * The function disables the petting function of watchdog driver by
+ * faking a pet_action.addr and setting the set_mask anc clr_mask
+ * field to be 0.
+ *
+ * It is mainly used for testing watchdog after booting into zircon.
+ * i.e., whether it triggers a reboot if zircon is not able to pet it in time
+ */
+void disable_watchdog_petting(void)
+{
+ watchdog_driver.pet_action.addr = watchdog_driver.enable_action.addr;
+ watchdog_driver.pet_action.set_mask = 0; // no set
+ watchdog_driver.pet_action.clr_mask = 0; // no clear
+}
+#endif
+
+static const zbi_platform_id_t platform_id = {
+ .vid = PDEV_VID_GOOGLE,
+ .pid = PDEV_PID_ASTRO,
+ .board_name = "astro",
+};
+
+// Factory file list. Only files listed here will be supplied to Zircon as metadata.
+static const char *const factory_file_list[] = {
+ "amp_calibration.txt",
+ "bl_calibration.txt",
+ "checksum.sha1",
+ "client.crt",
+ "client.key",
+ "clm_bcmdhd.blob",
+ "corner_BL.bmp",
+ "corner_BR.bmp",
+ "corner_TL.bmp",
+ "corner_TR.bmp",
+ "hw.txt",
+ "locale_list.txt",
+ "logo.bmp",
+ "mac_addr",
+ "mlb_sn.txt",
+ "nf.key",
+ "partitions.sha1",
+ "pr3.crt",
+ "pr3.key",
+ "rgb_b_led_cal.txt",
+ "rgb_b_off_cal.txt",
+ "rgb_b_on_cal.txt",
+ "rgb_c_led_cal.txt",
+ "rgb_c_off_cal.txt",
+ "rgb_c_on_cal.txt",
+ "rgb_g_led_cal.txt",
+ "rgb_g_off_cal.txt",
+ "rgb_g_on_cal.txt",
+ "rgb_r_led_cal.txt",
+ "rgb_r_off_cal.txt",
+ "rgb_r_on_cal.txt",
+ "serial.txt",
+ "sounds/checksum.sha1",
+ "sounds/err_no_lang_pack.opus",
+ "sounds/error.opus",
+ "sounds/fdr.opus",
+ "sounds/meta.txt",
+ "sounds/mic_muted_warning.opus",
+ "sounds/mute.opus",
+ "sounds/unmute.opus",
+ "sounds/welcome.opus",
+ "ultrasound.txt",
+ "weave.crt",
+ "weave.key",
+ "weave_device_id",
+ "weave_pairing_code",
+ "wip_sn.txt",
+ "wv.key",
+};
+
+static void *mandatory_memset(void *dst, int c, size_t n)
+{
+ volatile unsigned char *out = dst;
+ size_t i = 0;
+
+ for (i = 0; i < n; ++i) {
+ out[i] = (unsigned char)c;
+ }
+ return dst;
+}
+
+static bool s_vboot_enabled = true;
+bool zircon_is_vboot_enabled(void)
+{
+ return s_vboot_enabled;
+}
+
+#if defined(CONFIG_ZIRCON_VBOOT_UNLOCK)
+/* 511th bit of user area */
+#define FUSE_UNLOCK_DISABLE_FLAG 511
+#define FUSE_UNLOCK_DISABLE_FLAG_BYTE_OFFSET (FUSE_UNLOCK_DISABLE_FLAG / 8)
+#define FUSE_UNLOCK_DISABLE_FLAG_MASK (1 << (FUSE_UNLOCK_DISABLE_FLAG % 8))
+
+bool zircon_is_vboot_unlock_enabled(void)
+{
+ char unlock_disable = 0;
+
+ loff_t offset = FUSE_UNLOCK_DISABLE_FLAG_BYTE_OFFSET;
+ ssize_t ret = efuse_read_usr(&unlock_disable, 1, &offset);
+ if (ret != 1) {
+ /* unlock is disabled by default */
+ return false;
+ }
+
+ debugP("UNLOCK disable flag %d\n", unlock_disable);
+
+ return !(unlock_disable & FUSE_UNLOCK_DISABLE_FLAG_MASK);
+}
+
+int zircon_vboot_disable_vboot_unlock(void)
+{
+ char unlock_disable = FUSE_UNLOCK_DISABLE_FLAG_MASK;
+
+ if (!s_vboot_enabled) {
+ /* device has to be locked first */
+ printf("error: the device has to be locked first\n");
+ return -1;
+ }
+
+ loff_t offset = FUSE_UNLOCK_DISABLE_FLAG_BYTE_OFFSET;
+ ssize_t ret = efuse_write_usr(&unlock_disable, 1, &offset);
+ if (ret != 1) {
+ return -1;
+ }
+
+ return 0;
+}
+
+int zircon_vboot_set_unlock(bool unlock)
+{
+ if (!unlock) {
+ s_vboot_enabled = true;
+ return 0;
+ }
+
+ if (!zircon_is_vboot_unlock_enabled()) {
+ debugP("Unlock feature is permanently disabled.\n");
+ return -1;
+ }
+
+ s_vboot_enabled = false;
+ return 0;
+}
+#endif /* CONFIG_ZIRCON_VBOOT_UNLOCK */
+
+/* Helper to add a ZBI item. Returns 0 on success, -1 and logs on failure.*/
+int append_zbi_item_or_log(void *zbi, size_t capacity, uint32_t type,
+ uint32_t extra, const void *payload, size_t size)
+{
+ if (size > 0xFFFFFFFFU) {
+ printf("Error: ZBI item 0x%08X/0x%X is too large (%zu bytes)\n",
+ type, extra, size);
+ return -1;
+ }
+
+ zbi_result_t result = zbi_create_entry_with_payload(
+ zbi, capacity, type, extra, 0 /*flags*/, payload, size);
+ if (result != ZBI_RESULT_OK) {
+ printf("Error: Failed to add ZBI item 0x%08X/0x%X (code %d)\n",
+ type, extra, result);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int add_partition_map(zbi_header_t *zbi, size_t capacity)
+{
+ const zbi_partition_map_t *partition_map = zircon_get_partition_map();
+ if (partition_map == NULL) {
+ printf("WARNING: zircon partition map is not defined.\n");
+ return -1;
+ }
+ return append_zbi_item_or_log(
+ zbi, capacity, ZBI_TYPE_DRV_PARTITION_MAP, 0, partition_map,
+ sizeof(zbi_partition_map_t) + partition_map->partition_count *
+ sizeof(zbi_partition_t));
+}
+
+// I wish u-boot had sscanf()...
+static int hex_to_int(char ch)
+{
+ if (ch >= '0' && ch <= '9') {
+ return ch - '0';
+ } else if (ch >= 'a' && ch <= 'f') {
+ return ch - 'a' + 0xA;
+ } else if (ch >= 'A' && ch <= 'F') {
+ return ch - 'A' + 0xA;
+ } else {
+ return -1;
+ }
+}
+
+static int add_mac_address(zbi_header_t *zbi, size_t capacity, uint32_t index,
+ const char *str)
+{
+ uint8_t mac_addr[6];
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ int hi = hex_to_int(*str++);
+ int lo = hex_to_int(*str++);
+ if (hi < 0 || lo < 0) {
+ return -1;
+ }
+ mac_addr[i] = ((hi << 4) | lo);
+ }
+
+ return append_zbi_item_or_log(zbi, capacity, ZBI_TYPE_DRV_MAC_ADDRESS,
+ index, mac_addr, sizeof(mac_addr));
+}
+
+static int add_mac_addresses(zbi_header_t *zbi, size_t capacity)
+{
+ char buffer[100];
+ int ret;
+
+ memset(buffer, 0, sizeof(buffer));
+ ret = ubifs_load("mac_addr", (u32)(uintptr_t)buffer, sizeof(buffer));
+ if (ret < 0) {
+ printf("ERROR: ubifs_load() failed\n");
+ return ret;
+ }
+ // "buffer" should now contain two hex strings separated by \n, for a total of 25 bytes.
+ // Unfortunately we have no sscanf() to use here, so we parse the hex strings manually.
+ ret = add_mac_address(zbi, capacity, 0, buffer);
+ if (ret < 0) {
+ printf("ERROR: could not add MAC address from %s\n", buffer);
+ return ret;
+ }
+ ret = add_mac_address(zbi, capacity, 1, buffer + 13);
+ if (ret < 0) {
+ printf("ERROR: could not add MAC address from %s\n",
+ buffer + 13);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int add_board_info(zbi_header_t *zbi, size_t capacity)
+{
+ zbi_board_info_t board_info = {};
+ char *s;
+ if (((s = getenv("hw_id")) != NULL) && (*s != '\0')) {
+ uint32_t hw_id = simple_strtoul(s, NULL, 16);
+ board_info.revision = hw_id;
+ } else {
+ printf("Failed to retrieve Board Revision\n");
+ }
+
+ return append_zbi_item_or_log(zbi, capacity, ZBI_TYPE_DRV_BOARD_INFO, 0,
+ &board_info, sizeof(board_info));
+}
+
+// fills an 8 char buffer with the lowercase hex representation of the given
+// value.
+// WARNING this does not add a '\0' to the end of the buffer.
+static inline void uint32_to_hex(uint32_t val, char buf[static 8])
+{
+ static const char hex[] = "0123456789abcdef";
+ int i = 0;
+
+ for (i = 7; i >= 0; i--) {
+ buf[i] = hex[val & 0xF];
+ val >>= 4;
+ }
+}
+
+// Reads a value from the userspace hardware random number generator.
+//
+// This assumes that the drng has been previously seeded. Callers should
+// poll P_RNG_USR_STS beforehand to make sure that a reseed occurred.
+static inline uint32_t read_hw_rng(void)
+{
+ return readl(P_RNG_USR_DATA);
+}
+
+// Gathers CMDLINE_ENTROPY_BITS bits of entropy from the hardware random
+// number generator and appends it as a ZBI_TYPE_CMDLINE for zircon to seed
+// its cprng.
+//
+// This function will sleep a maximum of HW_RNG_RESEEDING_INTERVAL_MICROS *
+// (CMDLINE_ENTROPY_BITS / 32) + ENTROPY_COLLECTION_DEADLINE_MICROS.
+// If the function can't gather enough entropy after after exceeding
+// the deadline, it will return -1 and the cmdline zbi will not be added.
+static int add_cmdline_entropy(zbi_header_t *zbi, size_t capacity)
+{
+ strcpy(entropy_cmdline, zircon_entropy_arg);
+ char *entropy = entropy_cmdline + strlen(zircon_entropy_arg);
+ uint32_t elapsed_time_us = 0;
+ int i = 0;
+
+ for (i = 0; i < CMDLINE_ENTROPY_BITS; i += 32) {
+ // Reading a 1 in the RNG_USR_STS means that the
+ // hw rng has been reseeded. Wait until we see a 1,
+ // without exceeding the global deadline.
+ while ((readl(P_RNG_USR_STS) & USR_RAND32_RDY) != 1) {
+ udelay(1);
+ elapsed_time_us++;
+ if (elapsed_time_us >
+ ENTROPY_COLLECTION_DEADLINE_MICROS) {
+ return -1;
+ }
+ }
+
+ uint32_to_hex(read_hw_rng(), entropy);
+ entropy += 8;
+
+ // According to the docs, this should guarantee a reseed.
+ udelay(HW_RNG_RESEEDING_INTERVAL_MICROS);
+ }
+ *entropy = '\0';
+
+ int ret = append_zbi_item_or_log(zbi, capacity, ZBI_TYPE_CMDLINE, 0,
+ entropy_cmdline,
+ sizeof(entropy_cmdline));
+
+ mandatory_memset(entropy_cmdline, '\0', sizeof(entropy_cmdline));
+ return ret;
+}
+
+/* Adds a single bootfs factory file to the ZBI payload.
+ *
+ * @filename: UBIFS filename.
+ * @data_off: offset from the payload start to this file's data.
+ * @max_bootfs_size: maximum payload size.
+ * @direntry_start: pointer to this file's zbi_bootfs_dirent_t in the payload
+ * buffer. Will be advanced past this entry on success,
+ * including padding.
+ * @payload_start: pointer to this file's data in the payload buffer. Will be
+ * advanced past this data on success, including padding.
+ * @data_len: will be filled with the file's data length.
+ *
+ * Returns 0 on success, nonzero on failure.
+ */
+static int add_factory_file(const char *filename, uint32_t data_off,
+ uint32_t max_bootfs_size, uint8_t **direntry_start,
+ uint8_t **payload_start, uint32_t *data_len)
+{
+ const uint32_t name_len = strlen(filename) + 1;
+ const uint32_t max_data_size =
+ (max_bootfs_size - data_off) & ~(ZBI_BOOTFS_PAGE_SIZE - 1);
+
+ int ret = ubifs_load((char *)filename, (u32)(uintptr_t)*payload_start,
+ max_data_size);
+ if (ret < 0) {
+ printf("ERROR: ubifs_load() failed\n");
+ return ret;
+ }
+ // At this point, $filesize contains the actual size of the file. This
+ // value will not be larger than |max_data_size| due to ubifs_load()
+ // picking the min of |max_data_size| and the real file size.
+ *data_len = (uint32_t)getenv_hex("filesize", 0);
+ *payload_start += *data_len;
+
+ uint32_t data_pad_size = ZBI_BOOTFS_PAGE_ALIGN(*data_len) - *data_len;
+ memset(*payload_start, 0, data_pad_size);
+ *payload_start += data_pad_size;
+
+ // The caller has already reserved space for the dirent structures and
+ // filenames in the buffer, so we don't need to check for overflow here.
+ zbi_bootfs_dirent_t *entry_hdr =
+ (zbi_bootfs_dirent_t *)(*direntry_start);
+ entry_hdr->name_len = name_len;
+ entry_hdr->data_len = *data_len;
+ entry_hdr->data_off = data_off;
+
+ *direntry_start += offsetof(zbi_bootfs_dirent_t, name);
+ memcpy(*direntry_start, filename, name_len);
+ *direntry_start += name_len;
+
+ uint32_t full_dirent_size = ZBI_BOOTFS_DIRENT_SIZE(name_len);
+ uint32_t after_name_offset =
+ offsetof(zbi_bootfs_dirent_t, name[name_len]);
+ uint32_t dirent_pad_size = full_dirent_size - after_name_offset;
+ memset(*direntry_start, 0, dirent_pad_size);
+ *direntry_start += dirent_pad_size;
+
+ return 0;
+}
+
+/* Loads factory files into a BOOTFS ZBI payload.
+ *
+ * @bootfs_header: start of the payload buffer to fill.
+ * @max_bootfs_size: maximum payload size.
+ * @file_count: number of files in the ZBI item.
+ * @dirsize: size in bytes of the zbi_bootfs_dirent_t array.
+ * @bootfs_size: set to the actual payload size.
+ *
+ * Returns 0 on success, nonzero on failure.
+ */
+static int add_bootfs_factory_files(zbi_bootfs_header_t *bootfs_header,
+ uint32_t max_bootfs_size,
+ uint32_t file_count, uint32_t dirsize,
+ uint32_t *bootfs_size)
+{
+ if (sizeof(*bootfs_header) > max_bootfs_size) {
+ printf("ERROR: can't fit bootfs header in ZBI payload (%zu > %u)\n",
+ sizeof(*bootfs_header), max_bootfs_size);
+ return 1;
+ }
+ bootfs_header->magic = ZBI_BOOTFS_MAGIC;
+ bootfs_header->dirsize = dirsize;
+ bootfs_header->reserved0 = 0;
+ bootfs_header->reserved1 = 0;
+
+ uint32_t dir_entries_end_offset = dirsize + sizeof(zbi_bootfs_header_t);
+ uint32_t data_off = ZBI_BOOTFS_PAGE_ALIGN(dir_entries_end_offset);
+ if (data_off < dirsize) {
+ printf("ERROR: bootfs dirsize overflow (dirsize = %u, data_off = %u)\n",
+ dirsize, data_off);
+ return 1;
+ }
+ if (data_off > max_bootfs_size) {
+ printf("ERROR: can't fit bootfs dir entries in ZBI payload (%u > %u)\n",
+ data_off, max_bootfs_size);
+ return 1;
+ }
+
+ uint8_t *header_start = (uint8_t *)bootfs_header;
+ uint8_t *entry_ptr = header_start + sizeof(zbi_bootfs_header_t);
+ uint8_t *payload_padding_start = header_start + dir_entries_end_offset;
+ uint8_t *payload_start = header_start + data_off;
+
+ memset(payload_padding_start, 0,
+ (size_t)(payload_start - payload_padding_start));
+
+ uint32_t i;
+ for (i = 0; i < file_count; i++) {
+ const char *const filename = factory_file_list[i];
+ uint32_t data_len = 0;
+
+ payload_padding_start = payload_start;
+ int ret =
+ add_factory_file(filename, data_off, max_bootfs_size,
+ &entry_ptr, &payload_start, &data_len);
+ if (ret != 0) {
+ // Log the error, but try to keep going and add the rest of the
+ // factory files.
+ printf("ERROR: failed to add factory file %s\n",
+ filename);
+ }
+ payload_padding_start += data_len;
+
+ data_off += ZBI_BOOTFS_PAGE_ALIGN(data_len);
+ memset(payload_padding_start, 0,
+ (size_t)(payload_start - payload_padding_start));
+ }
+
+ *bootfs_size = data_off;
+ return 0;
+}
+
+/* Adds a ZBI item containing the factory files to the given container.
+ *
+ * On Estelle, factory files are stored in a UBIFS partition. Fuchsia doesn't
+ * have a UBIFS driver, so we load the files from the bootloader and pass them
+ * as a ZBI item that Fuchsia understands.
+ *
+ * Note also that ZBI_TYPE_STORAGE_BOOTFS_FACTORY wasn't really meant to be
+ * ABI-stable, so the definitions aren't part of the Firmware SDK. In the future
+ * we may want to formalize this as a stable ABI e.g. ZBI_TYPE_ASTRO_FACTORY_FS.
+ *
+ * @zbi: ZBI container to add the factory files to.
+ * @capacity: ZBI container max capacity.
+ *
+ * Returns 0 on success, nonzero on failure.
+ */
+static int add_factory_data(zbi_header_t *zbi, size_t capacity)
+{
+ int ret = ubifs_init();
+ if (ret < 0) {
+ printf("ERROR: ubifs_init() failed\n");
+ return ret;
+ }
+
+ ret = uboot_ubifs_mount("ubi:factory");
+ if (ret < 0) {
+ printf("ERROR: uboot_ubifs_mount() failed\n");
+ return ret;
+ }
+
+ // MAC addresses are a special case of factory files which are put in their
+ // own ZBI items.
+ ret = add_mac_addresses(zbi, capacity);
+ if (ret < 0) {
+ printf("ERROR: add_mac_addresses() failed\n");
+ return ret;
+ }
+
+ // Add an empty ZBI header for factory data. Factory data is formated as BOOTFS.
+ // BOOTFS is a trivial "filesystem" format.
+ //
+ // It consists of a zbi_bootfs_header_t followed by a series of zbi_bootfs_dirent_t structs.
+ // After the zbi_bootfs_dirent_t structs, file data is placed.
+ // File data offsets are page aligned (multiple of 4096).
+ // zbi_bootfs_dirent_t structs start on uint32 boundaries.
+ void *payload = NULL;
+ uint32_t max_payload_size = 0;
+ zbi_result_t result = zbi_get_next_entry_payload(
+ zbi, capacity, &payload, &max_payload_size);
+ if (result != ZBI_RESULT_OK) {
+ printf("ERROR: zbi_get_next_entry_payload() failed: %d\n",
+ result);
+ return 1;
+ }
+
+ // Determine how much space is needed to store all of the directory entries.
+ uint32_t dirsize = 0;
+ uint32_t file_count = (uint32_t)(sizeof(factory_file_list) /
+ sizeof(*factory_file_list));
+
+ uint32_t i;
+ for (i = 0; i < file_count; i++) {
+ const char *const filename = factory_file_list[i];
+ dirsize += ZBI_BOOTFS_DIRENT_SIZE(strlen(filename) + 1);
+ }
+
+ // Mark the start of the zbi_bootfs_header_t. This header is bootfs-specific and stores
+ // data related to the number of directory entries.
+ uint32_t bootfs_size = 0;
+ ret = add_bootfs_factory_files((zbi_bootfs_header_t *)payload,
+ max_payload_size, file_count, dirsize,
+ &bootfs_size);
+ if (ret != 0) {
+ printf("ERROR: add_bootfs_factory_files() failed\n");
+ return ret;
+ }
+
+ // Finally, add the ZBI item using the newly created payload.
+ result =
+ zbi_create_entry(zbi, capacity, ZBI_TYPE_STORAGE_BOOTFS_FACTORY,
+ 0, 0, bootfs_size, NULL);
+ if (result != ZBI_RESULT_OK) {
+ printf("ERROR: zbi_create_entry() failed: %d\n", result);
+ return 1;
+ }
+ return 0;
+}
+
+static int add_reboot_reason(zbi_header_t *zbi, size_t capacity)
+{
+ // See cmd/amlogic/cmd_reboot.c
+ const uint32_t reboot_mode_val = ((readl(AO_SEC_SD_CFG15) >> 12) & 0xf);
+
+ zbi_hw_reboot_reason_t reboot_reason;
+ switch (reboot_mode_val) {
+ case AMLOGIC_COLD_BOOT:
+ reboot_reason = ZBI_HW_REBOOT_COLD;
+ break;
+ case AMLOGIC_NORMAL_BOOT:
+ case AMLOGIC_FACTORY_RESET_REBOOT:
+ case AMLOGIC_UPDATE_REBOOT:
+ case AMLOGIC_FASTBOOT_REBOOT:
+ case AMLOGIC_SUSPEND_REBOOT:
+ case AMLOGIC_HIBERNATE_REBOOT:
+ case AMLOGIC_BOOTLOADER_REBOOT:
+ case AMLOGIC_SHUTDOWN_REBOOT:
+ case AMLOGIC_RPMBP_REBOOT:
+ case AMLOGIC_FACTORY_BOOT:
+ case AMLOGIC_CRASH_REBOOT:
+ case AMLOGIC_KERNEL_PANIC:
+ reboot_reason = ZBI_HW_REBOOT_WARM;
+ break;
+ case AMLOGIC_WATCHDOG_REBOOT:
+ reboot_reason = ZBI_HW_REBOOT_WATCHDOG;
+ break;
+ default:
+ reboot_reason = ZBI_HW_REBOOT_UNDEFINED;
+ break;
+ }
+
+ return append_zbi_item_or_log(zbi, capacity, ZBI_TYPE_HW_REBOOT_REASON,
+ 0, &reboot_reason, sizeof(reboot_reason));
+}
+
+// Buffer to keep staged ZBI files.
+// We store these in their own ZBI container, which takes up a little extra
+// space due to ZBI headers, but makes copying them over to the actual ZBI
+// trivial.
+//
+// The test team needs to be able to put up to 3 SSH keys on a single device
+// so make sure it's at least big enough for that.
+static uint8_t zbi_files[4096] __attribute__((aligned(ZBI_ALIGNMENT)));
+static bool zbi_files_initialized = false;
+
+int zircon_stage_zbi_file(const char *name, const uint8_t *data,
+ size_t data_len)
+{
+ size_t name_len = strlen(name);
+ if (name_len > U8_MAX) {
+ printf("ZBI filename too long");
+ return -1;
+ }
+
+ // Payload = (name_length_byte + name + data), size must fit in a uint32_t.
+ size_t payload_length = 1 + name_len + data_len;
+ if (payload_length > U32_MAX || payload_length < data_len) {
+ printf("ZBI file data too large");
+ return -1;
+ }
+
+ if (!zbi_files_initialized) {
+ zbi_result_t result = zbi_init(zbi_files, sizeof(zbi_files));
+ if (result != ZBI_RESULT_OK) {
+ printf("Failed to initialize zbi_files: %d\n", result);
+ return -1;
+ }
+ zbi_files_initialized = true;
+ }
+
+ uint8_t *payload = NULL;
+ zbi_result_t result =
+ zbi_create_entry(zbi_files, sizeof(zbi_files),
+ ZBI_TYPE_BOOTLOADER_FILE, 0, 0, payload_length,
+ (void **)&payload);
+ if (result != ZBI_RESULT_OK) {
+ printf("Failed to create ZBI file entry: %d\n", result);
+ return -1;
+ }
+
+ payload[0] = name_len;
+ memcpy(&payload[1], name, name_len);
+ memcpy(&payload[1 + name_len], data, data_len);
+
+ return 0;
+}
+
+static int add_staged_zbi_files(zbi_header_t *zbi, size_t capacity)
+{
+ if (!zbi_files_initialized) {
+ return 0;
+ }
+
+ zbi_result_t result = zbi_extend(zbi, capacity, zbi_files);
+ if (result != ZBI_RESULT_OK) {
+ printf("Failed to add staged ZBI files: %d\n", result);
+ return -1;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_WDT
+static void start_watchdog(void)
+{
+ printf("starting watchdog\n");
+ wdt_init();
+ wdt_start(WATCHDOG_TIMEOUT_SECONDS);
+ wdt_reset();
+}
+#endif
+
+/* We do this a lot in zircon_preboot(), a macro helps with boilerplate.
+ * Generally it's best to fail loudly if we can't add a ZBI item; we want to
+ * know immediately if ZBI items are missing, not later when random things
+ * stop working in the OS. */
+#define RETURN_IF_NONZERO(val) \
+ do { \
+ int ret = (val); \
+ if (ret != 0) { \
+ return ret; \
+ } \
+ } while (0)
+
+int zircon_fixup_zbi(zbi_header_t *zbi, size_t capacity)
+{
+ // add CPU configuration
+ RETURN_IF_NONZERO(append_zbi_item_or_log(
+ zbi, capacity, ZBI_TYPE_CPU_CONFIG, 0, &cpu_config,
+ sizeof(zbi_cpu_config_t) +
+ sizeof(zbi_cpu_cluster_t) * cpu_config.cluster_count));
+
+ // allocate crashlog save area before 0x5f800000-0x60000000 reserved area
+ zbi_nvram_t nvram;
+ nvram.base = 0x5f800000 - NVRAM_LENGTH;
+ nvram.length = NVRAM_LENGTH;
+ RETURN_IF_NONZERO(append_zbi_item_or_log(zbi, capacity, ZBI_TYPE_NVRAM,
+ 0, &nvram, sizeof(nvram)));
+
+ // add memory configuration
+ RETURN_IF_NONZERO(
+ append_zbi_item_or_log(zbi, capacity, ZBI_TYPE_MEM_CONFIG, 0,
+ &mem_config, sizeof(mem_config)));
+
+ // add kernel drivers
+ RETURN_IF_NONZERO(append_zbi_item_or_log(
+ zbi, capacity, ZBI_TYPE_KERNEL_DRIVER, KDRV_AMLOGIC_UART,
+ &uart_driver, sizeof(uart_driver)));
+ RETURN_IF_NONZERO(append_zbi_item_or_log(
+ zbi, capacity, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GIC_V2,
+ &gicv2_driver, sizeof(gicv2_driver)));
+ RETURN_IF_NONZERO(append_zbi_item_or_log(
+ zbi, capacity, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_PSCI,
+ &psci_driver, sizeof(psci_driver)));
+ RETURN_IF_NONZERO(append_zbi_item_or_log(
+ zbi, capacity, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GENERIC_TIMER,
+ &timer_driver, sizeof(timer_driver)));
+ RETURN_IF_NONZERO(append_zbi_item_or_log(
+ zbi, capacity, ZBI_TYPE_KERNEL_DRIVER, KDRV_AMLOGIC_RNG,
+ &rng_driver, sizeof(rng_driver)));
+
+ char uboot_ver[] = "bootloader.name=" U_BOOT_VERSION_STRING;
+ // Zircon's cmdline parameters cannot contain spaces so
+ // convert spaces in autogenerated U-boot version string
+ // to underscores.
+ // See zircon/docs/kernel_cmdline.md
+ int i;
+ int len = strlen(uboot_ver);
+ for (i = 0; i < len; i++) {
+ if (uboot_ver[i] == ' ') {
+ uboot_ver[i] = '_';
+ }
+ }
+
+ RETURN_IF_NONZERO(append_zbi_item_or_log(
+ zbi, capacity, ZBI_TYPE_CMDLINE, 0, uboot_ver, len + 1));
+
+ RETURN_IF_NONZERO(add_board_info(zbi, capacity));
+
+ // add platform ID
+ RETURN_IF_NONZERO(
+ append_zbi_item_or_log(zbi, capacity, ZBI_TYPE_PLATFORM_ID, 0,
+ &platform_id, sizeof(platform_id)));
+
+ RETURN_IF_NONZERO(add_partition_map(zbi, capacity));
+ RETURN_IF_NONZERO(add_cmdline_entropy(zbi, capacity));
+ RETURN_IF_NONZERO(add_factory_data(zbi, capacity));
+
+#ifdef CONFIG_ABR_WEAR_LEVELING
+ // The following option enables abr wear-leveling technique.
+ const char abr_wear_leveling_opt[] =
+ "astro.sysconfig.abr-wear-leveling=1";
+ RETURN_IF_NONZERO(append_zbi_item_or_log(
+ zbi, capacity, ZBI_TYPE_CMDLINE, 0, abr_wear_leveling_opt,
+ sizeof(abr_wear_leveling_opt)));
+#endif
+
+ RETURN_IF_NONZERO(add_reboot_reason(zbi, capacity));
+
+ RETURN_IF_NONZERO(add_staged_zbi_files(zbi, capacity));
+
+#if defined(CONFIG_ZIRCON_VBOOT)
+ RETURN_IF_NONZERO(zircon_vboot_add_extra_zbi_items(zbi, capacity));
+#endif
+
+#ifdef CONFIG_FIRMWARE_TESTING_DEV_BUILD
+ RETURN_IF_NONZERO(zircon_fw_testing_add_extra_zbi_items(zbi, capacity));
+#endif
+
+#ifdef CONFIG_WDT
+ RETURN_IF_NONZERO(append_zbi_item_or_log(
+ zbi, capacity, ZBI_TYPE_KERNEL_DRIVER,
+ KDRV_GENERIC_32BIT_WATCHDOG, &watchdog_driver,
+ sizeof(watchdog_driver)));
+
+ if (watchdog_driver.flags & KDRV_GENERIC_32BIT_WATCHDOG_FLAG_ENABLED) {
+ start_watchdog();
+ }
+#endif
+
+ return 0;
+}
diff --git a/board/amlogic/g12a_estelle_bx/zircon_partition.c b/board/amlogic/g12a_estelle_bx/zircon_partition.c
new file mode 100644
index 0000000..0d43c54
--- /dev/null
+++ b/board/amlogic/g12a_estelle_bx/zircon_partition.c
@@ -0,0 +1,1390 @@
+/*
+ * Copyright (c) 2019 The Fuchsia Authors
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <config.h>
+#include <common.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <aboot.h>
+#include <abr/abr.h>
+#include <abr/ops.h>
+#include <amlogic/storage_if.h>
+#include <libavb/libavb.h>
+#include <nand.h>
+#include <partition_table.h>
+
+#include <zircon/boot/image.h>
+#include <zircon-estelle/partition.h>
+#include <zircon-estelle/zircon.h>
+
+#include "sysconfig-header.h"
+#include "abr-wear-leveling.h"
+#include "fvm_ftl_image.h"
+
+/* most NANDs have ERASE GRP which does not exceed 256K */
+#define ERASE_GRP_SIZE_MAX (256 * 1024)
+
+#if defined(ZPARTITION_DEBUG)
+#define debugP(fmt...) \
+ printf("[Dbg zircon partition]%s:%d:", __func__, __LINE__), printf(fmt)
+#else
+#define debugP(fmt...)
+#endif
+
+extern struct mtd_partition *get_aml_mtd_partition(void);
+extern int get_aml_partition_count(void);
+
+enum {
+ PART_BL2,
+ PART_TPL,
+ PART_FTS,
+ PART_FACTORY,
+ PART_ZIRCON_R,
+ PART_ZIRCON_A,
+ PART_ZIRCON_B,
+ PART_FVM,
+ PART_SYS_CONFIG,
+ PART_MIGRATION,
+ PART_COUNT,
+};
+
+static zbi_partition_map_t partition_map = {
+ // .block_count filled in below
+ // .block_size filled in below
+ .guid = {},
+ .partition_count = PART_COUNT,
+ .partitions = {
+ {
+ .type_guid = GUID_BL2_VALUE,
+ .name = "bl2",
+ },
+ {
+ .type_guid = GUID_BOOTLOADER_VALUE,
+ .name = "tpl",
+ },
+ {
+ .name = "fts",
+ },
+ {
+ .name = "factory",
+ },
+ {
+ .type_guid = GUID_ZIRCON_R_VALUE,
+ .name = ZIRCON_PARTITION_PREFIX"r",
+ },
+ {
+ .type_guid = GUID_ZIRCON_A_VALUE,
+ .name = ZIRCON_PARTITION_PREFIX"a",
+ },
+ {
+ .type_guid = GUID_ZIRCON_B_VALUE,
+ .name = ZIRCON_PARTITION_PREFIX"b",
+ },
+ {
+ .type_guid = GUID_FVM_VALUE,
+ .name = "fvm",
+ },
+ {
+ .type_guid = GUID_SYS_CONFIG_VALUE,
+ .name = "sys-config",
+ },
+ {
+ .name = "migration",
+ },
+ },
+};
+
+// This is the partition map passed to the ZBI.
+// It is copied from partition_map below and modified to
+// match the zircon partition naming scheme.
+// The number of partitions must match PART_COUNT.
+static zbi_partition_map_t zbi_partition_map = {
+ .partitions = { {}, {}, {}, {}, {}, {}, {}, {}, {}, {} }
+};
+
+static nand_info_t *bl2_nand_info = &nand_info[0];
+static nand_info_t *data_nand_info = &nand_info[1];
+
+#define SYS_CFG_NUM_OF_COPIES 4
+
+static void init_partition_map(void)
+{
+ struct mtd_partition *tpl_part = NULL;
+ struct mtd_partition *fts_part = NULL;
+ struct mtd_partition *factory_part = NULL;
+ struct mtd_partition *recovery_part = NULL;
+ struct mtd_partition *boot_part = NULL;
+ struct mtd_partition *system_part = NULL;
+ struct mtd_partition *sys_config_part = NULL;
+ struct mtd_partition *migration_part = NULL;
+ struct mtd_partition *partitions = get_aml_mtd_partition();
+ int partition_count = get_aml_partition_count();
+ int i;
+ static int init_done = 0;
+
+ if (init_done) {
+ return;
+ }
+
+ for (i = 0; i < partition_count; i++) {
+ struct mtd_partition *part = &partitions[i];
+ if (!strcmp("tpl", part->name)) {
+ tpl_part = part;
+ } else if (!strcmp("fts", part->name)) {
+ fts_part = part;
+ } else if (!strcmp("factory", part->name)) {
+ factory_part = part;
+ } else if (!strcmp("recovery", part->name)) {
+ recovery_part = part;
+ } else if (!strcmp("boot", part->name)) {
+ boot_part = part;
+ } else if (!strcmp("system", part->name)) {
+ system_part = part;
+ } else if (!strcmp("sys-config", part->name)) {
+ sys_config_part = part;
+ } else if (!strcmp("migration", part->name)) {
+ migration_part = part;
+ }
+ }
+
+ if (!tpl_part) {
+ printf("could not find tpl partition\n");
+ return;
+ }
+ if (!fts_part) {
+ printf("could not find fts partition\n");
+ return;
+ }
+ if (!factory_part) {
+ printf("could not find factory partition\n");
+ return;
+ }
+ if (!recovery_part) {
+ printf("could not find recovery partition\n");
+ return;
+ }
+ if (!boot_part) {
+ printf("could not find boot partition\n");
+ return;
+ }
+ if (!system_part) {
+ printf("could not find system partition\n");
+ return;
+ }
+ if (!sys_config_part) {
+ printf("could not find sys-config partition\n");
+ return;
+ }
+ if (!migration_part) {
+ printf("could not find migration partition\n");
+ return;
+ }
+
+ uint32_t bl2_block_size = bl2_nand_info->writesize;
+ uint64_t bl2_size = bl2_nand_info->size;
+
+ partition_map.partitions[PART_BL2].first_block = 0;
+ partition_map.partitions[PART_BL2].last_block =
+ (bl2_size / bl2_block_size) - 1;
+
+ uint32_t block_size = data_nand_info->writesize;
+ uint64_t total_size = data_nand_info->size;
+
+ partition_map.block_size = block_size;
+ partition_map.block_count = total_size / block_size;
+
+ /* map tpl partition to BOOTLOADER */
+ partition_map.partitions[PART_TPL].first_block =
+ tpl_part->offset / block_size;
+ partition_map.partitions[PART_TPL].last_block =
+ ((tpl_part->offset + tpl_part->size) / block_size) - 1;
+ /* map fts partition to "fts" */
+ partition_map.partitions[PART_FTS].first_block =
+ fts_part->offset / block_size;
+ partition_map.partitions[PART_FTS].last_block =
+ ((fts_part->offset + fts_part->size) / block_size) - 1;
+ /* map factory partition to "factory" */
+ partition_map.partitions[PART_FACTORY].first_block =
+ factory_part->offset / block_size;
+ partition_map.partitions[PART_FACTORY].last_block =
+ ((factory_part->offset + factory_part->size) / block_size) - 1;
+ /* map recovery partition to ZIRCON_R */
+ partition_map.partitions[PART_ZIRCON_R].first_block =
+ recovery_part->offset / block_size;
+ partition_map.partitions[PART_ZIRCON_R].last_block =
+ ((recovery_part->offset + recovery_part->size) / block_size) -
+ 1;
+ /* map boot partition to ZIRCON_A */
+ partition_map.partitions[PART_ZIRCON_A].first_block =
+ boot_part->offset / block_size;
+ partition_map.partitions[PART_ZIRCON_A].last_block =
+ ((boot_part->offset + boot_part->size) / block_size) - 1;
+ /* ZIRCON_B partition at start of system */
+ partition_map.partitions[PART_ZIRCON_B].first_block =
+ system_part->offset / block_size;
+ partition_map.partitions[PART_ZIRCON_B].last_block =
+ partition_map.partitions[PART_ZIRCON_B].first_block +
+ (boot_part->size / block_size) - 1;
+ /* FVM follows ZIRCON_B and extends to SYS_CONFIG */
+ partition_map.partitions[PART_FVM].first_block =
+ partition_map.partitions[PART_ZIRCON_B].last_block + 1;
+ partition_map.partitions[PART_FVM].last_block =
+ sys_config_part->offset / block_size - 1;
+ /* map sys-config partition to SYS_CONFIG */
+ partition_map.partitions[PART_SYS_CONFIG].first_block =
+ sys_config_part->offset / block_size;
+ partition_map.partitions[PART_SYS_CONFIG].last_block =
+ ((sys_config_part->offset + sys_config_part->size) /
+ block_size) -
+ 1;
+ /* map migration partition to MIGRATION */
+ partition_map.partitions[PART_MIGRATION].first_block =
+ migration_part->offset / block_size;
+ partition_map.partitions[PART_MIGRATION].last_block =
+ ((migration_part->offset + migration_part->size) / block_size) -
+ 1;
+
+ assert(sys_config_part->size ==
+ SYS_CFG_NUM_OF_COPIES * data_nand_info->erasesize);
+
+ assert(data_nand_info->erasesize <= ERASE_GRP_SIZE_MAX);
+
+ uint64_t partition_map_size =
+ sizeof(zbi_partition_map_t) +
+ partition_map.partition_count * sizeof(zbi_partition_t);
+
+ memcpy(&zbi_partition_map, &partition_map, partition_map_size);
+
+ // Replace first underscore in each partition name with a dash.
+ for (i = 0; i < zbi_partition_map.partition_count; i++) {
+ char *underscore =
+ strchr(zbi_partition_map.partitions[i].name, '_');
+ if (underscore) {
+ *underscore = '-';
+ }
+ }
+
+ printf("Zircon partitions:\n");
+ for (i = 0; i < PART_COUNT; i++) {
+ printf(" 0x%016llx - 0x%016llx : %s\n",
+ zbi_partition_map.partitions[i].first_block * block_size,
+ (zbi_partition_map.partitions[i].last_block + 1) *
+ block_size,
+ zbi_partition_map.partitions[i].name);
+ }
+
+ init_done = 1;
+ return;
+}
+
+/**
+ * Defines image types, which specify the expected contents of the partition.
+ */
+enum sys_config_img_type {
+ IMG_TYPE_ANY, // Expected data is not erased (all 0xff)
+ IMG_TYPE_VBMETA, // Expected data is a valid vbmeta image
+ IMG_TYPE_ABR_META, // Expected data is valid ABR metadata
+ IMG_TYPE_HEADER, // Expected data is syconfig header.
+ IMG_TYPE_ABR_META_WEAR_LEVELING // Expected data is Abr metadata in wear-leveling.
+};
+
+const struct sysconfig_header *get_sysconfig_header(void);
+
+/**
+ * If a previous erase / write was interrupted by for ex. a power failure,
+ * sys-config might be in an inconsistent state. For example, the first copy
+ * could be erased, but with nothing written. This function provides a heuristic
+ * to check if it is likely that the image is valid.
+ *
+ * For unknown image types, it checks if there is non-erased data in the region.
+ * For VBMeta and A/B/R metadata, it verifies that the image is valid,
+ * but not necessarily correct.
+ */
+static bool is_sys_config_img_likely_valid(const unsigned char *data,
+ size_t size,
+ enum sys_config_img_type img_type)
+{
+ switch (img_type) {
+ case IMG_TYPE_ANY: {
+ size_t i;
+ for (i = 0; i < size; i++) {
+ if (data[i] != 0xFF) {
+ return true;
+ }
+ }
+ return false;
+ }
+
+ case IMG_TYPE_VBMETA: {
+ AvbVBMetaVerifyResult avb_res = avb_vbmeta_image_verify(
+ data, size, /*out_public_key_data =*/NULL,
+ /*out_public_key_length =*/NULL);
+ return (avb_res == AVB_VBMETA_VERIFY_RESULT_OK);
+ }
+
+ case IMG_TYPE_ABR_META: {
+ return AbrIsValidMetadata(data, size);
+ }
+
+ case IMG_TYPE_HEADER: {
+ return sysconfig_header_valid(
+ (const struct sysconfig_header *)data, PAGE_SIZE,
+ ERASE_GRP_SIZE_MAX);
+ }
+
+ case IMG_TYPE_ABR_META_WEAR_LEVELING: {
+ struct abr_metadata_ext latest;
+ find_latest_abr_metadata_page(get_sysconfig_header(), data,
+ PAGE_SIZE, &latest);
+ return AbrIsValidMetadata(latest.abr_data,
+ sizeof(latest.abr_data));
+ }
+ }
+ return false;
+}
+
+static unsigned char sys_cfg_read_buf[ERASE_GRP_SIZE_MAX];
+static unsigned char sys_cfg_write_buf[ERASE_GRP_SIZE_MAX];
+static unsigned char sys_cfg_erase_buf[ERASE_GRP_SIZE_MAX];
+
+#define SYS_CFG_NUM_READ_RETRIES 3
+/**
+ * The sys-config partition contains 4 replicated copies, each of which are the
+ * size of an erase block. This tries to read each copy 3 times until a read
+ * succeeds. This mitigates transient read failures.
+ *
+ * offset and size must be multiples of the NAND page size (normally 4096)
+ */
+static int read_from_sys_config(uint64_t offset, unsigned char *data,
+ size_t size, enum sys_config_img_type img_type)
+{
+ init_partition_map();
+
+ if (offset % data_nand_info->writesize ||
+ size % data_nand_info->writesize) {
+ fprintf(stderr, "sys_config: ERROR: unaligned size / offset\n");
+ return -1;
+ }
+
+ if ((offset + size) > data_nand_info->erasesize) {
+ fprintf(stderr,
+ "sys_config: ERROR: read overflows partition\n");
+ return -1;
+ }
+
+ uint64_t sys_cfg_offset =
+ partition_map.partitions[PART_SYS_CONFIG].first_block *
+ partition_map.block_size;
+
+ int ret = -1;
+
+ int copy, retry;
+
+ // at least one copy has to be read without error
+ for (copy = 0; copy < SYS_CFG_NUM_OF_COPIES; copy++) {
+ uint64_t copy_offset =
+ sys_cfg_offset + (copy * data_nand_info->erasesize);
+ uint64_t read_offset = copy_offset + offset;
+
+ if (nand_block_isbad(data_nand_info, copy_offset)) {
+ printf("sys_config: bad block @ 0x%llx, ignored for reading\n",
+ copy_offset);
+ continue;
+ }
+
+ bool read_succeeded = false;
+
+ for (retry = 0; retry < SYS_CFG_NUM_READ_RETRIES; retry++) {
+ size_t len = size;
+
+ if (!nand_read(data_nand_info, read_offset, &len,
+ sys_cfg_read_buf) &&
+ len == size) {
+ read_succeeded = true;
+ break;
+ }
+
+ fprintf(stderr,
+ "sys_config: failed to read %zu bytes @ %llu (copy: %d, try: %d)\n",
+ size, read_offset, copy, retry);
+ } // Retry for loop
+
+ if (!read_succeeded) {
+ fprintf(stderr, "sys_config: failed to read copy %d\n",
+ copy);
+ continue;
+ }
+
+ // Return 0 if any read succeeds.
+ ret = 0;
+ memcpy(data, sys_cfg_read_buf, size);
+
+ // Return if the contents look valid. If not, read the backup
+ // copies. The copies should only differ in contents if a failure
+ // occurs while writing.
+ if (is_sys_config_img_likely_valid(data, size, img_type)) {
+ return 0;
+ }
+ fprintf(stderr,
+ "sys_config: Read copy %d, but contents look invalid (type: %d).\n",
+ copy, img_type);
+
+ } // Copies for loop
+
+ if (ret) {
+ fprintf(stderr, "sys_config: ERROR failed to read any copy!\n");
+ }
+
+ return ret;
+}
+
+typedef enum nand_block_write_result {
+ NAND_BLOCK_WRITE_SUCCESS,
+ NAND_BLOCK_WRITE_ERROR,
+ NAND_BLOCK_WRITE_MARKBAD
+} nand_block_write_result_t;
+
+/**
+ * The function support two modes for writing to sys-config.
+ *
+ * SYSCONFIG_READ_UPDATE_ERASE_WRITE:
+ * Existing data is first read into a buffer. New data is updated in the
+ * buffer. Last, the buffer is written to storage using normal erase-write
+ * flow. This mode only changes |size| of data on storage from |offset|.
+ * Otherdata remains the same.
+ *
+ * SYSCONFIG_ERASE_WRITE:
+ * Erase sysconfig and write |size| of data from |offset|. Memory space
+ * not in the specified range remains in an erased state.
+ *
+ * offset must be a multiple of writesize (normally 4096)
+ *
+ * size can be unaligned.
+ */
+typedef enum write_to_sys_config_mode {
+ SYSCONFIG_READ_UPDATE_ERASE_WRITE,
+ SYSCONFIG_ERASE_WRITE,
+} write_to_sys_config_mode_t;
+
+static nand_block_write_result_t sys_config_mark_copy_bad(uint64_t copy_offset)
+{
+ // Block will be marked bad.
+ printf("sys_config: copy @ %llx will be marked bad.\n", copy_offset);
+ if (mtd_block_markbad(data_nand_info, copy_offset)) {
+ fprintf(stderr, "sys_config: Failed to mark copy bad");
+ return NAND_BLOCK_WRITE_ERROR;
+ }
+ return NAND_BLOCK_WRITE_MARKBAD;
+}
+
+static nand_block_write_result_t
+sys_config_write_copy(uint64_t sys_cfg_offset, int copy,
+ const unsigned char *data, size_t size,
+ uint64_t in_copy_offset)
+{
+ uint64_t copy_offset =
+ sys_cfg_offset + (copy * data_nand_info->erasesize);
+ if (nand_erase(data_nand_info, copy_offset,
+ data_nand_info->erasesize)) {
+ printf("sys_config: Failed to erase copy @ 0x%llx\n",
+ copy_offset);
+ return sys_config_mark_copy_bad(copy_offset);
+ }
+ printf("sys_config: Erased copy %d\n", copy);
+
+ size_t written = size;
+ if (nand_write(data_nand_info, copy_offset + in_copy_offset, &written,
+ (unsigned char *)data) ||
+ written != size) {
+ printf("sys_config: Failed to write copy @ 0x%llx\n",
+ copy_offset);
+ return sys_config_mark_copy_bad(copy_offset);
+ }
+ return NAND_BLOCK_WRITE_SUCCESS;
+}
+
+static int write_to_sys_config_mode_opt(uint64_t offset,
+ const unsigned char *data, size_t size,
+ write_to_sys_config_mode_t mode)
+{
+ int ret = -1;
+
+ init_partition_map();
+
+ if (offset % data_nand_info->writesize) {
+ fprintf(stderr, "sys_config: ERROR: unaligned offset\n");
+ return -1;
+ }
+
+ if (size == 0) {
+ return 0;
+ }
+
+ if ((offset + size) > data_nand_info->erasesize) {
+ fprintf(stderr,
+ "sys_config: ERROR: write overflows partition\n");
+ return -1;
+ }
+
+ uint64_t sys_cfg_offset =
+ partition_map.partitions[PART_SYS_CONFIG].first_block *
+ partition_map.block_size;
+
+ // Skip reading existing data if overwriting the entire partition
+ if (!(offset == 0 && size == data_nand_info->erasesize) &&
+ mode == SYSCONFIG_READ_UPDATE_ERASE_WRITE) {
+ if (read_from_sys_config(0, sys_cfg_write_buf,
+ data_nand_info->erasesize,
+ IMG_TYPE_ANY)) {
+ fprintf(stderr, "sys_config: read failed\n");
+ return -1;
+ }
+ }
+
+ // Update buffer with new data.
+ memcpy(sys_cfg_write_buf + offset, data, size);
+
+ uint64_t write_offset = 0;
+ size_t write_len, expected_write_len;
+ if (mode == SYSCONFIG_READ_UPDATE_ERASE_WRITE) {
+ expected_write_len = data_nand_info->erasesize;
+ write_offset = 0;
+ } else if (mode == SYSCONFIG_ERASE_WRITE) {
+ expected_write_len = size;
+ write_offset = offset;
+ } else {
+ fprintf(stderr, "sys_config: Unknown mode: %d\n", (int)mode);
+ return -1;
+ }
+ write_len = expected_write_len;
+
+ int copy;
+ for (copy = 0; copy < SYS_CFG_NUM_OF_COPIES; copy++) {
+ uint64_t copy_offset =
+ sys_cfg_offset + (copy * data_nand_info->erasesize);
+
+ if (nand_block_isbad(data_nand_info, copy_offset)) {
+ printf("sysconfig: Bad block @ %llx, skipping\n",
+ copy_offset);
+ continue;
+ }
+
+ size_t read_len = data_nand_info->erasesize;
+
+ // Read contents of this specific copy for the following optimizations.
+ // - Skip erase/write if the contents are the same.
+ // If read fails, continue with erase/write.
+ if (!nand_read(data_nand_info, copy_offset, &read_len,
+ sys_cfg_read_buf) &&
+ read_len == data_nand_info->erasesize) {
+ if (!memcmp(sys_cfg_read_buf, sys_cfg_write_buf,
+ read_len)) {
+ printf("sys_config: Skipping write to copy %d - same data as already exists\n",
+ copy);
+ ret = 0;
+ continue;
+ }
+ }
+
+ if (sys_config_write_copy(
+ sys_cfg_offset, copy, sys_cfg_write_buf, write_len,
+ write_offset) == NAND_BLOCK_WRITE_SUCCESS) {
+ ret = 0;
+ }
+ }
+
+ if (ret) {
+ fprintf(stderr,
+ "sys_config: ERROR: Failed to write any copies!\n");
+ }
+
+ return ret;
+}
+
+static int write_to_sys_config(uint64_t offset, const unsigned char *data,
+ size_t size)
+{
+ return write_to_sys_config_mode_opt(offset, data, size,
+ SYSCONFIG_READ_UPDATE_ERASE_WRITE);
+}
+
+/**
+ * erases subset of sys-config.
+ *
+ * offset and size must be multiples of writesize (normally 4096)
+ */
+static int erase_at_sys_config(uint64_t offset, size_t size)
+{
+ if ((offset + size) > data_nand_info->erasesize) {
+ fprintf(stderr,
+ "sys_config: ERROR: erase overflows partition\n");
+ return -1;
+ }
+
+ if (offset % data_nand_info->writesize ||
+ size % data_nand_info->writesize) {
+ fprintf(stderr, "sys_config: ERROR: unaligned offset\n");
+ return -1;
+ }
+
+ // erase writes 0xff to the specified region.
+ memset(sys_cfg_erase_buf, 0xff, size);
+
+ return write_to_sys_config(offset, sys_cfg_erase_buf, size);
+}
+
+const zbi_partition_t *get_partition_by_name(const char *name)
+{
+ int i;
+ if (name == NULL)
+ return NULL;
+
+ /* init partition layout in case it was not initialized already */
+ init_partition_map();
+ for (i = 0; i < PART_COUNT; i++) {
+ if (!strncmp(partition_map.partitions[i].name, name,
+ ZBI_PARTITION_NAME_LEN)) {
+ return &partition_map.partitions[i];
+ }
+ }
+
+ return NULL;
+}
+
+/* === public API === */
+
+const zbi_partition_map_t *zircon_get_partition_map(void)
+{
+ /* init partition layout in case it was not initialized already */
+ init_partition_map();
+ return &zbi_partition_map;
+}
+
+/*
+ * ABR and AVBs metadatas are located on 'sys-config' partition.
+ * 'sys-config' partition has following layout:
+ * 00000 - 0EFFF (60K) sys-config data
+ * 0F000 - 0FFFF (4K) A/B/R metadata
+ * 10000 - 1FFFF (64K) AVB -a metadata
+ * 20000 - 2FFFF (64K) AVB -b metadata
+ * 30000 - 3FFFF (64K) AVB -r metadata
+ */
+#define ABR_OFFSET 0x0F000
+#define AVB_A_OFFSET 0x10000
+#define AVB_B_OFFSET 0x20000
+#define AVB_R_OFFSET 0x30000
+#define SYSCONFIG_DATA_SIZE (60 * 1024)
+#define ABR_SIZE (4 * 1024)
+#define AVB_SIZE (64 * 1024)
+
+static const struct sysconfig_header legacy_sysconfig_layout = {
+ .magic = SYSCONFIG_HEADER_MAGIC_ARRAY,
+ .sysconfig_data = { 0, SYSCONFIG_DATA_SIZE },
+ .abr_metadata = { ABR_OFFSET, ABR_SIZE },
+ .vb_metadata_a = { AVB_A_OFFSET, AVB_SIZE },
+ .vb_metadata_b = { AVB_B_OFFSET, AVB_SIZE },
+ .vb_metadata_r = { AVB_R_OFFSET, AVB_SIZE },
+ .crc_value = 2716817057, // the value is precomputed
+};
+
+/*
+ * Used for storing header loaded from storage.
+ * It will only be loaded once, assuming that header from storage won't change.
+ */
+static struct sysconfig_header sysconfig_header_from_storage = {
+ .magic = { 0 },
+};
+
+/*
+ * A pointer for current header in use. If valid, it is returned by
+ * get_sysconfig_header
+ */
+static const struct sysconfig_header *sysconfig_header_in_use = NULL;
+
+const struct sysconfig_header *get_sysconfig_header(void)
+{
+ if (sysconfig_header_in_use) {
+ return sysconfig_header_in_use;
+ }
+
+ uint8_t buf[PAGE_SIZE];
+ int status;
+
+ if ((status = read_from_sys_config(0, buf, PAGE_SIZE,
+ IMG_TYPE_HEADER))) {
+ // When fail to read from storage, i.e. due to ecc error, default
+ // to legacy header to try our best to boot into OS and also allow
+ // partition writing to proceed for recovery.
+ debugP("Failed to read sysconfig header from storage. "
+ "Default to legacy layout. %d\n",
+ status);
+ return sysconfig_header_in_use = &legacy_sysconfig_layout;
+ }
+
+ struct sysconfig_header *header = (struct sysconfig_header *)buf;
+ if (!sysconfig_header_valid(header, PAGE_SIZE, ERASE_GRP_SIZE_MAX)) {
+ printf("Sysconfig does not contain a valid header. Default to legacy layout\n");
+ return sysconfig_header_in_use = &legacy_sysconfig_layout;
+ }
+
+ sysconfig_header_from_storage = *header;
+ return sysconfig_header_in_use = &sysconfig_header_from_storage;
+}
+
+uint32_t sysconfig_header_crc32(uint32_t crc, const uint8_t *buf, size_t len)
+{
+ return crc32(crc, buf, len);
+}
+
+static int abr_wear_leveling_read(uint64_t offset, unsigned char *data,
+ size_t size, int *page_index)
+{
+ int read_status;
+
+ const struct sysconfig_header *header = get_sysconfig_header();
+ offset += header->abr_metadata.offset;
+
+ // If the layout have not been organized to support wear-leveling,
+ // fall back to normal read.
+ if (!layout_support_wear_leveling(header, PAGE_SIZE)) {
+ if (page_index) {
+ *page_index = -1;
+ }
+ return read_from_sys_config(offset, data, size,
+ IMG_TYPE_ABR_META);
+ }
+
+ // read entire abr sub-partition
+ if ((read_status = read_from_sys_config(
+ offset, sys_cfg_read_buf, header->abr_metadata.size,
+ IMG_TYPE_ABR_META_WEAR_LEVELING))) {
+ return read_status;
+ }
+
+ struct abr_metadata_ext latest;
+ int idx = find_latest_abr_metadata_page(header, sys_cfg_read_buf,
+ PAGE_SIZE, &latest);
+ if (page_index) {
+ *page_index = idx;
+ }
+ memcpy(data, &latest, min(size, sizeof(latest)));
+ return 0;
+}
+
+/*
+ * Writes new abr metadata while resetting the other pages in the sub-partition
+ * to be empty. Specifically, it write the new data at the first page and reset
+ * all other pages to empty. This is used when there are no empty page to write
+ * or abr_wear_leveling_write_append fails.
+ */
+static int abr_wear_leveling_write_reset(uint64_t offset,
+ const uint8_t *new_abr_data,
+ size_t size,
+ const struct sysconfig_header *header,
+ uint8_t *data_on_storage);
+
+/*
+ * The function find a write new abr metadata to an empty page.
+ */
+static int abr_wear_leveling_write_append(uint64_t offset,
+ const uint8_t *new_abr_data,
+ size_t size,
+ const struct sysconfig_header *header,
+ const uint8_t *data_on_storage);
+
+static int abr_wear_leveling_write(uint64_t offset, const unsigned char *data,
+ size_t size, bool force_reset)
+{
+ int read_status;
+
+ const struct sysconfig_header *header = get_sysconfig_header();
+ if (!layout_support_wear_leveling(header, PAGE_SIZE)) {
+ return write_to_sys_config(offset + header->abr_metadata.offset,
+ data, size);
+ }
+
+ // Read current data from storage.
+ if ((read_status =
+ read_from_sys_config(offset, sys_cfg_write_buf,
+ ERASE_GRP_SIZE_MAX, IMG_TYPE_ANY))) {
+ return read_status;
+ }
+
+ // Always try append first. Unless |force_reset| is set.
+ // But if any of the following happens:
+ // 1) no empty page is found
+ // 2) write append fails
+ // fall back to normal write-flow (erase + write)
+ if (force_reset ||
+ abr_wear_leveling_write_append(offset, data, size, header,
+ sys_cfg_write_buf)) {
+ debugP("Abr metadata append fails. Fall back to erase + write flow\n");
+ return abr_wear_leveling_write_reset(offset, data, size, header,
+ sys_cfg_write_buf);
+ }
+ return 0;
+}
+
+static int abr_wear_leveling_write_reset(uint64_t offset,
+ const uint8_t *new_abr_data,
+ size_t size,
+ const struct sysconfig_header *header,
+ uint8_t *data_on_storage)
+{
+ // 1. write the new abr data at the 1st page.
+ // 2. set the rest of pages allocated to abr sub-partition as empty (0xff).
+ int status = 0;
+ size_t start_abr = header->abr_metadata.offset;
+ // Put the new abr metadata at the first page.
+ struct abr_metadata_ext copy;
+ memcpy(©, new_abr_data, sizeof(copy));
+ set_abr_metadata_ext_magic(©);
+ // Copy the new data to the first page.
+ memcpy(&data_on_storage[start_abr], ©, sizeof(copy));
+
+ size_t write_len =
+ ERASE_GRP_SIZE_MAX - header->abr_metadata.size + PAGE_SIZE;
+ // Use mode SYSCONFIG_ERASE_WRITE for two reason:
+ // 1. Avoid writing trailing empty pages (even 0xff) so that they are
+ // truly safe for write later.
+ // 2. It's possible that this call is due to a fall back from
+ // abr_wear_leveling_write_append, in which case the storage may have
+ // already been compromised and unreadable. Thus, it is necessary to
+ // directly go into erase + write and avoid any read.
+ if ((status = write_to_sys_config_mode_opt(
+ 0, data_on_storage, write_len, SYSCONFIG_ERASE_WRITE))) {
+ debugP("Failed to write to sys-config partition. %d\n", status);
+ return status;
+ }
+ return 0;
+}
+
+static int abr_wear_leveling_write_append(uint64_t offset,
+ const uint8_t *new_abr_data,
+ size_t size,
+ const struct sysconfig_header *header,
+ const uint8_t *data_on_storage)
+{
+ int ret = 0;
+ int64_t candidate;
+ // Find an empty page to write.
+ if (!find_empty_page_for_wear_leveling(
+ header, &data_on_storage[header->abr_metadata.offset],
+ PAGE_SIZE, &candidate)) {
+ debugP("Cannot find an empty page to write\n");
+ return -1;
+ }
+
+ // Prepare the new abr metadata
+ uint8_t write_buf[PAGE_SIZE] = { 0 };
+ struct abr_metadata_ext copy;
+ memcpy(©, new_abr_data, sizeof(copy));
+ set_abr_metadata_ext_magic(©);
+ memcpy(write_buf, ©, sizeof(copy));
+
+ nand_info_t *nand = &nand_info[nand_curr_device];
+ assert(nand->erasesize <= ERASE_GRP_SIZE_MAX);
+ assert((offset + size) <= nand->erasesize);
+
+ // Write new abr metadata at <page_index> offset in abr for each copy.
+ debugP("Attempt to append new abr metadata at page %lld\n", candidate);
+
+ uint64_t start_abr = header->abr_metadata.offset;
+ int i;
+ for (i = 0; i < SYS_CFG_NUM_OF_COPIES; i++) {
+ debugP("Append new abr metadata for copy %d\n", i);
+ if (store_write_ops((unsigned char *)"sys-config", write_buf,
+ i * nand->erasesize + start_abr +
+ (uint64_t)candidate * PAGE_SIZE,
+ PAGE_SIZE)) {
+ return __LINE__;
+ }
+ }
+
+ // The following double-checks that the written data can be correctly read
+ // back without failures. Returns error if not. It will lead the caller to
+ // fall back to abr_wear_leveling_write_reset.
+ uint8_t read_back_buffer[PAGE_SIZE];
+ if ((ret = abr_wear_leveling_read(offset, read_back_buffer, PAGE_SIZE,
+ NULL))) {
+ debugP("Failed while reading back for validation. %d\n", ret);
+ return ret;
+ }
+
+ if (memcmp(©, read_back_buffer, sizeof(struct abr_metadata_ext))) {
+ debugP("Validation failed. Read is different from write\n");
+ return -1;
+ }
+
+ debugP("Successfully write abr metadata at page %zu without erase.\n",
+ candidate);
+ return 0;
+}
+
+int abr_wear_leveling_reset_pages(void)
+{
+ uint8_t buffer[PAGE_SIZE];
+ int page_idx;
+ int status = abr_wear_leveling_read(0, buffer, PAGE_SIZE, &page_idx);
+ if (status) {
+ debugP("Failed to read from abr wear-leveling\n");
+ return status;
+ }
+
+ if (page_idx == -1 || page_idx == 0) {
+ return 0;
+ }
+
+ status = abr_wear_leveling_write(0, buffer, PAGE_SIZE, true);
+ if (status) {
+ debugP("Failed to write abr wear-leveling page\n");
+ return status;
+ }
+
+ return 0;
+}
+
+#define OOB_SIZE 8
+#define PAGE_PLUS_OOB_SIZE (PAGE_SIZE + OOB_SIZE)
+#define BLOCK_WITH_OOB_SIZE \
+ ((ERASE_GRP_SIZE_MAX / PAGE_SIZE) * PAGE_PLUS_OOB_SIZE)
+
+// Assume that the layout of data is:
+// page->oob->page->oob->.....
+static nand_block_write_result_t
+raw_nand_write_block(size_t offset, const uint8_t *data, size_t size)
+{
+ if (size > BLOCK_WITH_OOB_SIZE) {
+ printf("Cannot write more than one block of raw nand data\n");
+ return -1;
+ }
+
+ // Allocate a dedicated buffer to make sure its DMA aligned.
+ uint8_t *page_buffer = (uint8_t *)memalign(
+ ARCH_DMA_MINALIGN, ROUNDUP(PAGE_SIZE, ARCH_DMA_MINALIGN));
+ if (!page_buffer) {
+ printf("Failed to allocate page buffer.\n");
+ return -1;
+ }
+
+ const size_t pages = size / (PAGE_PLUS_OOB_SIZE);
+ int ret = NAND_BLOCK_WRITE_SUCCESS;
+ size_t i = 0;
+ for (; i < pages; i++) {
+ const uint8_t *page_data = data + i * PAGE_PLUS_OOB_SIZE;
+ const uint8_t *oob = page_data + PAGE_SIZE;
+ memcpy(page_buffer, page_data, PAGE_SIZE);
+ size_t physical_offset = offset + i * PAGE_SIZE;
+ struct mtd_oob_ops ops = {
+ .mode = MTD_OPS_AUTO_OOB,
+ .len = PAGE_SIZE,
+ .ooblen = OOB_SIZE,
+ .ooboffs = 0,
+ .datbuf = page_buffer,
+ .oobbuf = (uint8_t *)oob,
+ };
+ int result =
+ mtd_write_oob(data_nand_info, physical_offset, &ops);
+ if (result) {
+ printf("Fail to write page @ %lx\n", physical_offset);
+ ret = NAND_BLOCK_WRITE_ERROR;
+ break;
+ }
+
+ if (ops.retlen != ops.len || ops.oobretlen != ops.ooblen) {
+ printf("@ address %lx. Expect to write %zu of data, %zu of obb. "
+ "Actually write %zu of data, %zu of oob\n",
+ physical_offset, ops.len, ops.ooblen, ops.retlen,
+ ops.oobretlen);
+ ret = NAND_BLOCK_WRITE_ERROR;
+ break;
+ }
+ }
+
+ free(page_buffer);
+ return ret;
+}
+
+// Setting data = NULL equivalently performs an erase or mark bad operation.
+static nand_block_write_result_t
+raw_nand_write_block_or_mark_bad(size_t offset, const uint8_t *data,
+ size_t size, int retry)
+{
+ int attempt = 0;
+ for (; attempt < retry; attempt++) {
+ // We are not sure if previous attempt has written any data,
+ // so erase the block first.
+ int ret = nand_erase(data_nand_info, offset,
+ data_nand_info->erasesize);
+ if (ret) {
+ continue;
+ }
+
+ if (!data || raw_nand_write_block(offset, data, size) ==
+ NAND_BLOCK_WRITE_SUCCESS) {
+ return NAND_BLOCK_WRITE_SUCCESS;
+ }
+ }
+
+ // Mark the block bad
+ printf("failed %d times erasing/writing @ %lx. block will be marked bad.\n",
+ attempt, offset);
+ int ret = mtd_block_markbad(data_nand_info, offset);
+ if (ret) {
+ printf("failed to mark block @ %lx bad.\n", offset);
+ return NAND_BLOCK_WRITE_ERROR;
+ }
+ return NAND_BLOCK_WRITE_MARKBAD;
+}
+
+#define RAW_NAND_RETRIES_BEFORE_MARKBAD 3
+
+/**
+ * Erase all blocks in memory space from |offset| to |offset + size|,
+ * marking blocks as bad if necessary.
+ */
+static int raw_nand_erase_or_markbad(size_t offset, size_t size)
+{
+ size_t curr = offset, end = offset + size;
+ for (; curr < end; curr += data_nand_info->erasesize) {
+ if (nand_block_isbad(data_nand_info, curr)) {
+ printf("skipping erasing bad block @ %lx\n", curr);
+ continue;
+ }
+
+ nand_block_write_result_t ret =
+ raw_nand_write_block_or_mark_bad(
+ curr, NULL, 0, RAW_NAND_RETRIES_BEFORE_MARKBAD);
+ if (ret == NAND_BLOCK_WRITE_ERROR) {
+ return -1;
+ }
+ }
+ return 0;
+}
+
+int write_fvm_ftl_raw_image(size_t ptn_offset, size_t ptn_size,
+ const uint8_t *data, size_t size)
+{
+ const uint8_t *block_start = data;
+ const uint8_t *end = data + size;
+
+ if (size % PAGE_PLUS_OOB_SIZE) {
+ printf("Image size is not a multiple of page + oob size.\n");
+ return -1;
+ }
+
+ size_t write_offset = ptn_offset;
+ while (block_start < end) {
+ size_t write_size = min((size_t)BLOCK_WITH_OOB_SIZE,
+ (size_t)(end - block_start));
+
+ if (write_offset + write_size > ptn_offset + ptn_size) {
+ printf("FVM partition write overflow\n");
+ return -1;
+ }
+
+ // Skip known bad blocks.
+ if (nand_block_isbad(data_nand_info, write_offset)) {
+ printf("skipping writing bad block @ %lx\n",
+ write_offset);
+ write_offset += data_nand_info->erasesize;
+ continue;
+ }
+ // Assume that block starts in an erased state.
+ nand_block_write_result_t ret = raw_nand_write_block(
+ write_offset, block_start, write_size);
+ if (ret != NAND_BLOCK_WRITE_SUCCESS) {
+ ret = raw_nand_write_block_or_mark_bad(
+ write_offset, block_start, write_size,
+ RAW_NAND_RETRIES_BEFORE_MARKBAD);
+ if (ret == NAND_BLOCK_WRITE_ERROR) {
+ return -1;
+ }
+ }
+ // Succeed or markbad, |write_offset| needs to move to the next block.
+ write_offset += data_nand_info->erasesize;
+ if (ret == NAND_BLOCK_WRITE_SUCCESS) {
+ block_start += write_size;
+ }
+ }
+ return 0;
+}
+
+int validate_fvm_ftl_image_header(const struct RawNandImageHeader *header)
+{
+ if (header->magic != FVM_FTL_IMAGE_MAGIC) {
+ printf("Incorrect magic for fvm ftl image\n");
+ return -1;
+ }
+
+ if (header->version_major != FVM_FTL_IMAGE_MAJOR) {
+ printf("Major version is not supported");
+ return -1;
+ }
+
+ if (header->page_size != PAGE_SIZE) {
+ printf("Image page size %d does not match device (%d)\n",
+ header->page_size, PAGE_SIZE);
+ return -1;
+ }
+
+ if (header->oob_size != OOB_SIZE) {
+ printf("Image oob size %d does not match device (%d)\n",
+ header->oob_size, OOB_SIZE);
+ return -1;
+ }
+
+ return 0;
+}
+
+int write_fvm_ftl_image(const uint8_t *data, size_t size)
+{
+ const zbi_partition_t *ptn = get_partition_by_name("fvm");
+ // Notes: the |block_size| here is not the erase block size, but
+ // rather the minimum write size.
+ uint32_t block_size = partition_map.block_size;
+ if (!ptn) {
+ return -1;
+ }
+
+ uint64_t ptn_offset = ptn->first_block * block_size;
+ uint64_t ptn_size =
+ (ptn->last_block - ptn->first_block + 1) * block_size;
+
+ struct RawNandImageHeader header;
+ memcpy(&header, data, sizeof(header));
+ if (validate_fvm_ftl_image_header(&header)) {
+ return -1;
+ }
+
+ if (raw_nand_erase_or_markbad(ptn_offset, ptn_size)) {
+ printf("Failed to erase fvm partition\n");
+ return -1;
+ }
+
+ data += sizeof(header);
+ size -= sizeof(header);
+ if (header.format == FVM_FTL_IMAGE_RAW) {
+ return write_fvm_ftl_raw_image(ptn_offset, ptn_size, data,
+ size);
+ } else {
+ printf("Unsupported fvm ftl image format\n");
+ return -1;
+ }
+}
+
+int zircon_partition_write(const char *name, uint64_t offset,
+ const unsigned char *data, size_t size)
+{
+ size_t sub_off;
+ /* size has to be multiple of page size. Otherwise low level API will crash */
+ assert((size % PAGE_SIZE) == 0);
+
+ /* TODO (dmitryya@) move partition boundary check for offset + size here. */
+ if (!strcmp(name, "sys-config")) {
+ return write_to_sys_config(offset, data, size);
+ } else if (!strcmp(name, "sysconfig-data")) {
+ sub_off = get_sysconfig_header()->sysconfig_data.offset;
+ return write_to_sys_config(offset + sub_off, data, size);
+ } else if (!strcmp(name, "misc")) {
+ sub_off = get_sysconfig_header()->abr_metadata.offset;
+ return write_to_sys_config(offset + sub_off, data, size);
+ } else if (!strcmp(name, "abr-wear-leveling")) {
+ return abr_wear_leveling_write(offset, data, size, false);
+ } else if (!strcmp(name, "vbmeta_a")) {
+ sub_off = get_sysconfig_header()->vb_metadata_a.offset;
+ return write_to_sys_config(offset + sub_off, data, size);
+ } else if (!strcmp(name, "vbmeta_b")) {
+ sub_off = get_sysconfig_header()->vb_metadata_b.offset;
+ return write_to_sys_config(offset + sub_off, data, size);
+ } else if (!strcmp(name, "vbmeta_r")) {
+ sub_off = get_sysconfig_header()->vb_metadata_r.offset;
+ return write_to_sys_config(offset + sub_off, data, size);
+ } else if (!strcmp(name, "fvm")) {
+ return write_fvm_ftl_image(data, size);
+ } else { /* access to general partition */
+ /* erase whole partition if not in sys-config. */
+ if (zircon_partition_erase(name)) {
+ fprintf(stderr, "erase failed\n");
+ return -1;
+ }
+
+ const zbi_partition_t *ptn = get_partition_by_name(name);
+ uint32_t block_size = partition_map.block_size;
+
+ if (ptn != NULL) {
+ int flags = 0;
+ size_t len = size;
+ uint64_t ptn_size =
+ (ptn->last_block - ptn->first_block + 1) *
+ block_size;
+ loff_t flash_offset =
+ ptn->first_block * block_size + offset;
+
+ if (flash_offset > ptn->last_block * block_size) {
+ return -1;
+ }
+
+ return nand_write_skip_bad(data_nand_info, flash_offset,
+ &len, NULL,
+ ptn_size - offset,
+ (u_char *)data, flags);
+ }
+ }
+
+ return -1;
+}
+
+int zircon_partition_read(const char *name, uint64_t offset,
+ unsigned char *data, size_t size)
+{
+ size_t sub_off;
+ /* size has to be multiple of page size. Otherwise low level API will crash */
+ assert((size % PAGE_SIZE) == 0);
+
+ /* TODO (dmitryya@) move partition boundary check for offset + size here. */
+ if (!strcmp(name, "sys-config")) {
+ return read_from_sys_config(offset, data, size, IMG_TYPE_ANY);
+ } else if (!strcmp(name, "sysconfig-data")) {
+ sub_off = get_sysconfig_header()->sysconfig_data.offset;
+ return read_from_sys_config(offset + sub_off, data, size,
+ IMG_TYPE_ANY);
+ } else if (!strcmp(name, "misc")) {
+ sub_off = get_sysconfig_header()->abr_metadata.offset;
+ return read_from_sys_config(offset + sub_off, data, size,
+ IMG_TYPE_ABR_META);
+ } else if (!strcmp(name, "abr-wear-leveling")) {
+ return abr_wear_leveling_read(offset, data, size, NULL);
+ } else if (!strcmp(name, "vbmeta_a")) {
+ sub_off = get_sysconfig_header()->vb_metadata_a.offset;
+ return read_from_sys_config(offset + sub_off, data, size,
+ IMG_TYPE_VBMETA);
+ } else if (!strcmp(name, "vbmeta_b")) {
+ sub_off = get_sysconfig_header()->vb_metadata_b.offset;
+ return read_from_sys_config(offset + sub_off, data, size,
+ IMG_TYPE_VBMETA);
+ } else if (!strcmp(name, "vbmeta_r")) {
+ sub_off = get_sysconfig_header()->vb_metadata_r.offset;
+ return read_from_sys_config(offset + sub_off, data, size,
+ IMG_TYPE_VBMETA);
+ } else { /* access to general partition */
+ const zbi_partition_t *ptn = get_partition_by_name(name);
+ uint32_t block_size = partition_map.block_size;
+
+ if (ptn != NULL) {
+ size_t len = size;
+ uint64_t ptn_size =
+ (ptn->last_block - ptn->first_block + 1) *
+ block_size;
+ loff_t flash_offset =
+ ptn->first_block * block_size + offset;
+
+ if (flash_offset > ptn->last_block * block_size) {
+ return -1;
+ }
+
+ return nand_read_skip_bad(data_nand_info, flash_offset,
+ &len, NULL, ptn_size - offset,
+ data);
+ }
+ }
+
+ return -1;
+}
+
+int zircon_get_partititon_size(const char *name, uint64_t *size)
+{
+ assert(size != NULL);
+
+ /* virtual partitions */
+ if (!strcmp(name, "sys-config")) {
+ *size = data_nand_info->erasesize;
+ return 0;
+ } else if (!strcmp(name, "sysconfig-data")) {
+ *size = get_sysconfig_header()->sysconfig_data.size;
+ return 0;
+ } else if (!strcmp(name, "misc")) {
+ *size = get_sysconfig_header()->abr_metadata.size;
+ return 0;
+ } else if (!strcmp(name, "abr-wear-leveling")) {
+ *size = PAGE_SIZE;
+ return 0;
+ } else if (!strcmp(name, "vbmeta_a")) {
+ *size = get_sysconfig_header()->vb_metadata_a.size;
+ return 0;
+ } else if (!strcmp(name, "vbmeta_b")) {
+ *size = get_sysconfig_header()->vb_metadata_b.size;
+ return 0;
+ } else if (!strcmp(name, "vbmeta_r")) {
+ *size = get_sysconfig_header()->vb_metadata_r.size;
+ return 0;
+ } else {
+ /* general partition */
+ /* init partition layout in case it was not initialized already */
+ init_partition_map();
+ uint32_t block_size = partition_map.block_size;
+ const zbi_partition_t *ptn = get_partition_by_name(name);
+ if (ptn != NULL) {
+ *size = (ptn->last_block - ptn->first_block + 1) *
+ block_size;
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+int zircon_partition_erase(const char *name)
+{
+ struct sysconfig_subpartition subpart;
+ if (!strcmp(name, "misc")) {
+ subpart = get_sysconfig_header()->abr_metadata;
+ return erase_at_sys_config(subpart.offset, subpart.size);
+ } else if (!strcmp(name, "vbmeta_a")) {
+ subpart = get_sysconfig_header()->vb_metadata_a;
+ return erase_at_sys_config(subpart.offset, subpart.size);
+ } else if (!strcmp(name, "vbmeta_b")) {
+ subpart = get_sysconfig_header()->vb_metadata_b;
+ return erase_at_sys_config(subpart.offset, subpart.size);
+ } else if (!strcmp(name, "vbmeta_r")) {
+ subpart = get_sysconfig_header()->vb_metadata_r;
+ return erase_at_sys_config(subpart.offset, subpart.size);
+ } else { /* access to general partition */
+ /* general partition */
+ uint32_t block_size;
+
+ /* init partition layout in case it was not initialized already */
+ init_partition_map();
+ block_size = partition_map.block_size;
+ const zbi_partition_t *ptn = get_partition_by_name(name);
+ if (ptn != NULL) {
+ nand_erase_options_t opts;
+ int ret;
+
+ memset(&opts, 0, sizeof(opts));
+ opts.length = (ptn->last_block - ptn->first_block + 1) *
+ block_size;
+ opts.offset = ptn->first_block * block_size;
+ opts.quiet = 1;
+
+ printf("Erasing blocks 0x%llx to 0x%llx\n", opts.offset,
+ opts.length);
+
+ ret = nand_erase_opts(data_nand_info, &opts);
+ if (ret)
+ return -1;
+
+ printf("........ erased 0x%llx bytes from '%s'\n",
+ opts.length, name);
+
+ return 0;
+ }
+ }
+
+ return -1;
+}
diff --git a/board/amlogic/g12a_estelle_p2/Kconfig b/board/amlogic/g12a_estelle_p2/Kconfig
new file mode 100755
index 0000000..6358b9e
--- /dev/null
+++ b/board/amlogic/g12a_estelle_p2/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_G12A
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "g12a_estelle_p2"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "g12a"
+
+config SYS_CONFIG_NAME
+ default "g12a_estelle_p2"
+
+endif
diff --git a/board/amlogic/g12a_estelle_p2/Makefile b/board/amlogic/g12a_estelle_p2/Makefile
new file mode 100755
index 0000000..458100f
--- /dev/null
+++ b/board/amlogic/g12a_estelle_p2/Makefile
@@ -0,0 +1,5 @@
+
+obj-y += $(BOARD).o
+obj-$(CONFIG_AML_LCD) += lcd.o
+obj-y += pwm_table.o
+obj-$(CONFIG_ZIRCON_BOOT_IMAGE) += zircon.o zircon_partition.o
diff --git a/board/amlogic/g12a_estelle_p2/aml-user-key.sig b/board/amlogic/g12a_estelle_p2/aml-user-key.sig
new file mode 100755
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/g12a_estelle_p2/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/g12a_estelle_p2/firmware/scp_task/dvfs_board.c b/board/amlogic/g12a_estelle_p2/firmware/scp_task/dvfs_board.c
new file mode 100755
index 0000000..c42779b
--- /dev/null
+++ b/board/amlogic/g12a_estelle_p2/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,194 @@
+
+/*
+ * board/amlogic/g12a_estelle_p2/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+/*
+int pwm_voltage_table[ ][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+*/
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~((1 << 21) | 1 << 12);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(1 << 16);
+ P_PIN_MUX_REG10 = reg;//clear reg10
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/g12a_estelle_p2/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12a_estelle_p2/firmware/scp_task/pwm_ctrl.h
new file mode 100755
index 0000000..507d90b
--- /dev/null
+++ b/board/amlogic/g12a_estelle_p2/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,40 @@
+/*
+*board/amlogic/g12a_estelle_p2/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 681},
+ { 0x1b0001, 691},
+ { 0x1a0002, 701},
+ { 0x190003, 711},
+ { 0x180004, 721},
+ { 0x170005, 731},
+ { 0x160006, 741},
+ { 0x150007, 751},
+ { 0x140008, 761},
+ { 0x130009, 772},
+ { 0x12000a, 782},
+ { 0x11000b, 792},
+ { 0x10000c, 802},
+ { 0x0f000d, 812},
+ { 0x0e000e, 822},
+ { 0x0d000f, 832},
+ { 0x0c0010, 842},
+ { 0x0b0011, 852},
+ { 0x0a0012, 862},
+ { 0x090013, 872},
+ { 0x080014, 882},
+ { 0x070015, 892},
+ { 0x060016, 902},
+ { 0x050017, 912},
+ { 0x040018, 922},
+ { 0x030019, 932},
+ { 0x02001a, 942},
+ { 0x01001b, 952},
+ { 0x00001c, 962}
+};
+
+#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12a_estelle_p2/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12a_estelle_p2/firmware/scp_task/pwr_ctrl.c
new file mode 100755
index 0000000..3a51a0f
--- /dev/null
+++ b/board/amlogic/g12a_estelle_p2/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,153 @@
+
+/*
+ * board/amlogic/g12a_estelle_p2/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ /*set gpioH_8 low to power off vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+
+ /*set test_n low to power off vcck & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+
+ /*step down ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ /*step up ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+ /*set test_n low to power on vcck & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+ _udelay(100);
+
+ /*set gpioH_8 low to power on vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+ _udelay(10000);
+
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+
+ p->sources = val;
+ p->gpio_info_count = i;
+
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ unsigned char adc_key_cnt = 0;
+ init_remote();
+ saradc_enable();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ do {
+ #ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+ if (cec_power_on_check())
+ exit_reason = CEC_WAKEUP;
+ }
+ #endif
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/g12a_estelle_p2/firmware/timing.c b/board/amlogic/g12a_estelle_p2/firmware/timing.c
new file mode 100755
index 0000000..f519b82
--- /dev/null
+++ b/board/amlogic/g12a_estelle_p2/firmware/timing.c
@@ -0,0 +1,463 @@
+
+/*
+ * board/amlogic/g12a_estelle_p2/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+
+#ifdef CONFIG_DDR_LOGS_ENABLED
+#define LOG_FLAG 0x9
+#else
+#define LOG_FLAG 0xA
+#endif
+
+ddr_set_t __ddr_setting[] = {
+ {
+ /* g12a skt (u209) ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 1024,
+ .dram_cs1_size_MB = 512,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0c0c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+// .vref_reverse = 0,
+ .ac_trace_delay ={32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = 0,
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = LOG_FLAG,
+ .dram_cs0_size_MB = 1024,
+ .dram_cs1_size_MB = 512,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0c0c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = 0,
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function = {DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING, 0},
+ .dfi_hwtmrl = 4,
+
+ .ac_trace_delay = {
+ 32, 32, 32, 32,
+ 32, 32, 32, 32,
+ 32, 32,
+ },
+
+ .write_dqs_delay = {
+ 163, 163, 163, 163,
+ 167, 167, 165, 165,
+ 159, 159, 163, 163,
+ 165, 165, 161, 161,
+ },
+
+ .read_dqs_delay = {
+ 13, 13, 14, 14,
+ 14, 14, 15, 14,
+ 14, 14, 14, 15,
+ 14, 13, 14, 14,
+ },
+
+ .write_dq_bit_delay = {
+ 20, 21, 19, 21,
+ 21, 21, 22, 20,
+ 22, 21, 20, 20,
+ 19, 21, 18, 21,
+ 20, 20, 24, 20,
+ 22, 25, 24, 25,
+ 26, 26, 23, 20,
+ 21, 20, 23, 21,
+ 21, 23, 23, 20,
+ 48, 49, 48, 50,
+ 50, 50, 51, 49,
+ 49, 21, 21, 19,
+ 20, 21, 19, 20,
+ 21, 20, 22, 18,
+ 20, 23, 23, 24,
+ 24, 24, 22, 17,
+ 18, 17, 20, 18,
+ 18, 21, 20, 19,
+ },
+
+ .read_dq_bit_delay = {
+ 15, 15, 15, 23,
+ 31, 31, 31, 29,
+ 0 , 23, 19, 11,
+ 17, 35, 23, 31,
+ 31, 0 , 15, 3 ,
+ 9 , 15, 27, 27,
+ 35, 35, 0 , 13,
+ 15, 11, 19, 25,
+ 19, 31, 31, 0 ,
+ 15, 17, 15, 19,
+ 31, 33, 31, 27,
+ 0 , 19, 19, 15,
+ 13, 31, 23, 27,
+ 31, 0 , 13, 3 ,
+ 5 , 11, 23, 27,
+ 31, 27, 0 , 13,
+ 13, 9 , 19, 23,
+ 23, 27, 27, 0 ,
+ },
+
+ .read_dqs_gate_delay = {
+ 225, 227, 223, 225,
+ 223, 225, 223, 227,
+ 223, 225, 223, 225,
+ 225, 227, 227, 229,
+ },
+
+ .dq_dqs_delay_flag = DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS|DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ|
+ DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS|DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0000001c
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE PWM table */
+#if (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x0010000c
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x000f000d
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x000e000e
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x000d000f
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x000c0010
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x000b0011
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x000a0012
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x00090013
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x00080014
+#elif (VDDEE_VAL == 890)
+ #define VDDEE_VAL_REG 0x00070015
+#elif (VDDEE_VAL == 900)
+ #define VDDEE_VAL_REG 0x00060016
+#elif (VDDEE_VAL == 910)
+ #define VDDEE_VAL_REG 0x00050017
+#elif (VDDEE_VAL == 920)
+ #define VDDEE_VAL_REG 0x00040018
+#elif (VDDEE_VAL == 930)
+ #define VDDEE_VAL_REG 0x00030019
+#elif (VDDEE_VAL == 940)
+ #define VDDEE_VAL_REG 0x0002001a
+#elif (VDDEE_VAL == 950)
+ #define VDDEE_VAL_REG 0x0001001b
+#elif (VDDEE_VAL == 960)
+ #define VDDEE_VAL_REG 0x0000001c
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ /* eg: PWM init */
+
+ /* PWM_AO_D */
+ /* VCCK_VAL_REG: check PWM table */
+ {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
+ /* PWM_AO_B */
+ /* VDDEE_VAL_REG: check PWM table */
+ {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable 5V_EN */
+ {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Enable VCCK */
+ {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 31), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/g12a_estelle_p2/g12a_estelle_p2.c b/board/amlogic/g12a_estelle_p2/g12a_estelle_p2.c
new file mode 100755
index 0000000..2257d6c
--- /dev/null
+++ b/board/amlogic/g12a_estelle_p2/g12a_estelle_p2.c
@@ -0,0 +1,1036 @@
+
+/*
+ * board/amlogic/g12a_estelle_p2/g12a_estelle_p2.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <flash_ts.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#ifdef CONFIG_AML_SPIFC
+#include <amlogic/spifc.h>
+#endif
+#ifdef CONFIG_AML_SPICC
+#include <amlogic/spicc.h>
+#endif
+
+
+#include <asm/arch/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+int do_get_ddictype (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_CMD_NAND
+ extern bool amlnf_is_inited(void);
+ if(!amlnf_is_inited()) {
+ setenv("ddic_type", "NOVATEK");
+ return 0;
+ }
+ flash_ts_init();
+
+ const char *fts_key = "ddic.type";
+
+ char fts_value[256] = { 0 };
+ flash_ts_get(fts_key, fts_value, sizeof(fts_value));
+ printf("FTS read: ddic.type -> %s\n", fts_value);
+
+ if (strncmp(fts_value, "FITI", sizeof(fts_value)) == 0) {
+ setenv("ddic_type", "FITI");
+ } else {
+ setenv("ddic_type", "NOVATEK");
+ }
+#endif /* CONFIG_CMD_NAND */
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ get_ddictype, 1, 0, do_get_ddictype,
+ "get ddic type",
+ " This command will get and setenv 'ddic_type'\n"
+);
+
+int do_check_fdr_for_backlight_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_CMD_NAND
+ extern bool amlnf_is_inited(void);
+ if(!amlnf_is_inited()) {
+ return 0;
+ }
+ flash_ts_init();
+
+ static const char *fts_key = "bootloader.recovery";
+ static const char *fdr = "--wipe_data";
+ static const int fdr_len = sizeof(fdr) - 1;
+ int i;
+
+ char fts_value[256] = { 0 };
+ flash_ts_get(fts_key, fts_value, sizeof(fts_value));
+ int fts_len = strnlen(fts_value, sizeof(fts_value));
+ for (i = 0; i <= fts_len - fdr_len; i++) {
+ if (0 == strncmp(fts_value+i, fdr, fdr_len)) {
+ printf("Reset persistent brightness.\n");
+ writel(0, AO_RTI_STICKY_REG2);
+ break;
+ }
+ }
+#endif /* CONFIG_CMD_NAND */
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ check_fdr_for_backlight_brightness, 1, 0, do_check_fdr_for_backlight_brightness,
+ "check FDR for backlight brightness",
+ " This command will clear backlight brightness level stored in the sticky register when doing FDR\n"
+);
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+//SOC_VDDCPU_DVFS0
+#define VDD_CPU_DVFS0_EN_1 GPIOEE(GPIOZ_13)
+#define VDD_CPU_DVFS0_EN_1_NAME "GPIOZ_13"
+
+//SOC_VDDEE_DVFS0
+#define VDD_GPU_DVFS0_EN_1 GPIOEE(GPIOA_13)
+#define VDD_GPU_DVFS0_EN_1_NAME "GPIOA_13"
+
+//SOC_VDDEE_DVFS1
+#define VDD_GPU_DVFS1_EN_1 GPIOEE(GPIOZ_0)
+#define VDD_GPU_DVFS1_EN_1_NAME "GPIOZ_0"
+
+static void CPU_GPU_Voltage_init(void)
+{
+ int ret;
+
+ ret = gpio_request(VDD_CPU_DVFS0_EN_1,
+ VDD_CPU_DVFS0_EN_1_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", VDD_CPU_DVFS0_EN_1_NAME);
+ return;
+ }
+ gpio_direction_output(VDD_CPU_DVFS0_EN_1, 1);
+
+ //GPU
+ ret = gpio_request(VDD_GPU_DVFS0_EN_1,
+ VDD_GPU_DVFS0_EN_1_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", VDD_GPU_DVFS0_EN_1_NAME);
+ return;
+ }
+ gpio_direction_output(VDD_GPU_DVFS0_EN_1, 0);
+
+ ret = gpio_request(VDD_GPU_DVFS1_EN_1,
+ VDD_GPU_DVFS1_EN_1_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", VDD_GPU_DVFS1_EN_1_NAME);
+ return;
+ }
+ gpio_direction_output(VDD_GPU_DVFS1_EN_1, 1);
+}
+
+// Disable GPIOZ_2, GPIOZ_3, GPIOZ_7, GPIOZ_8, GPIOC_7, GPIOH_8's pull-up
+// so the mute switch and HW id can be read.
+static void gpio_disable_pull(void)
+{
+ int ret;
+
+ ret = readl(PAD_PULL_UP_EN_REG4);
+ writel(ret & (~(1 << 2)), PAD_PULL_UP_EN_REG4);
+
+ ret = readl(PAD_PULL_UP_EN_REG4);
+ writel(ret & (~(1 << 7)), PAD_PULL_UP_EN_REG4);
+
+ ret = readl(PAD_PULL_UP_EN_REG4);
+ writel(ret & (~(1 << 8)), PAD_PULL_UP_EN_REG4);
+
+ ret = readl(PAD_PULL_UP_EN_REG4);
+ writel(ret & (~(1 << 3)), PAD_PULL_UP_EN_REG4);
+
+ ret = readl(PAD_PULL_UP_EN_REG1);
+ writel(ret & (~(1 << 7)), PAD_PULL_UP_EN_REG1);
+
+ ret = readl(PAD_PULL_UP_EN_REG3);
+ writel(ret & (~(1 << 8)), PAD_PULL_UP_EN_REG3);
+}
+
+int do_get_estelle_hw_id(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ unsigned int hw_id = 0, ret = 0;
+ char hw_id_str[8] = {0}; // eg: 0x0A
+
+ // Reading from highest bit to lowest bit
+ // HW_ID_4: GPIOH_8
+ ret = readl(P_PREG_PAD_GPIO3_I);
+ hw_id |= (ret & (1<<8)) >> 8;
+ hw_id = hw_id << 1;
+
+ // HW_ID_3: GPIOC_7
+ ret = readl(P_PREG_PAD_GPIO1_I);
+ hw_id |= (ret & (1<<7)) >> 7;
+ hw_id = hw_id << 1;
+
+ // HW_ID_2: GPIOZ_3
+ ret = readl(P_PREG_PAD_GPIO4_I);
+ hw_id |= (ret & (1<<3)) >> 3;
+ hw_id = hw_id << 1;
+
+ // HW_ID_1: GPIOZ_8
+ ret = readl(P_PREG_PAD_GPIO4_I);
+ hw_id |= (ret & (1<<8)) >> 8;
+ hw_id = hw_id << 1;
+
+ // HW_ID_0: GPIOZ_7
+ ret = readl(P_PREG_PAD_GPIO4_I);
+ hw_id |= (ret & (1<<7)) >> 7;
+
+ snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id);
+ setenv("hw_id", hw_id_str);
+ return 0;
+}
+
+U_BOOT_CMD(
+ get_estelle_hw_id, 1, 0, do_get_estelle_hw_id,
+ "get estelle's HW_ID and setenv 'hw_id'\n",
+ "get_estelle_hw_id"
+);
+
+
+
+//SOC_DISP_ID
+#define DISP_ID_PIN GPIOEE(GPIOH_5)
+#define DISP_ID_PIN_NAME "GPIOH_5"
+
+static void panel_detect_init(void)
+{
+ int ret;
+
+ ret = gpio_request(DISP_ID_PIN, DISP_ID_PIN_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", DISP_ID_PIN_NAME);
+ return;
+ }
+ gpio_direction_input(DISP_ID_PIN);
+}
+
+//SOC_BL_ENABLE
+#define BL_ENABLE_PIN GPIOEE(GPIOA_10)
+#define BL_ENABLE_PIN_NAME "GPIOA_10"
+
+static void enable_backlight(bool enable)
+{
+ int ret;
+
+ ret = gpio_request(BL_ENABLE_PIN, BL_ENABLE_PIN_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", BL_ENABLE_PIN_NAME);
+ return;
+ }
+ gpio_direction_output(BL_ENABLE_PIN, enable ? 1 : 0);
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ /* check card detect */
+ clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_AML
+int i2c_set_bus_num(unsigned int busnum);
+int i2c_write(unsigned char chip, unsigned int addr, int alen,
+ unsigned char *buffer, int len);
+struct aml_i2c_platform g_aml_i2c_plat[] = {
+ {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+
+ /* i2c_ao */
+ .master_ao_pinmux = {
+ .sda_reg = (unsigned long)MESON_I2C_AO_M0_SDA_GPIOAO_2_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .sda_mask = MESON_I2C_AO_M0_SDA_GPIOAO_2_MASK,
+#endif
+ .sda_bit = MESON_I2C_AO_M0_SDA_GPIOAO_2_BIT,
+
+ .scl_reg = (unsigned long)MESON_I2C_AO_M0_SCL_GPIOAO_3_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .scl_mask = MESON_I2C_AO_M0_SCL_GPIOAO_3_MASK,
+#endif
+ .scl_bit = MESON_I2C_AO_M0_SCL_GPIOAO_3_BIT,
+ },
+ },
+ {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_A,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+
+ /* i2c0 */
+ .master_a_pinmux = {
+ .sda_reg = (unsigned long)MESON_I2C_EE_M0_SDA_GPIOZ_7_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .sda_mask = MESON_I2C_EE_M0_SDA_GPIOZ_7_MASK,
+#endif
+ .sda_bit = MESON_I2C_EE_M0_SDA_GPIOZ_7_BIT,
+
+ .scl_reg = (unsigned long)MESON_I2C_EE_M0_SCL_GPIOZ_8_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .scl_mask = MESON_I2C_EE_M0_SCL_GPIOZ_8_MASK,
+#endif
+ .scl_bit = MESON_I2C_EE_M0_SCL_GPIOZ_8_BIT,
+ },
+ },
+ {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_D,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ /* i2c3 */
+ .master_d_pinmux = {
+ .sda_reg = (unsigned long)MESON_I2C_EE_M3_SDA_GPIOA_14_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .sda_mask = MESON_I2C_EE_M3_SDA_GPIOA_14_MASK,
+#endif
+ .sda_bit = MESON_I2C_EE_M3_SDA_GPIOA_14_BIT,
+
+ .scl_reg = (unsigned long)MESON_I2C_EE_M3_SCL_GPIOA_15_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .scl_mask = MESON_I2C_EE_M3_SCL_GPIOA_15_MASK,
+#endif
+ .scl_bit = MESON_I2C_EE_M3_SCL_GPIOA_15_BIT,
+ },
+ },
+ /* sign of end */
+ {.master_i2c_speed=0},
+};
+
+static void board_i2c_init(void)
+{
+ extern void aml_i2c_set_ports(struct aml_i2c_platform *i2c_plat);
+ aml_i2c_set_ports(g_aml_i2c_plat);
+
+ udelay(10);
+}
+#endif /* CONFIG_SYS_I2C_AML */
+
+/* Skip the first line and parse one uint
+ * Return negative if not found */
+int parse_calibration_file_string(const char *str)
+{
+ if (str == NULL)
+ return -EINVAL;
+
+ str = strchr(str, '\n');
+ if (str == NULL)
+ return -EINVAL;
+ ++str;
+
+ return simple_strtoul(str, NULL, 10);
+}
+
+/* If zero, this value has not been set and the default brightness should not be
+ * overwritten. To store zero, store a non-zero value with its bottom 12 bits
+ * all zero, like 0x1000.
+ */
+int get_persistent_brightness(void)
+{
+ u32 brightness_sticky_val = readl(AO_RTI_STICKY_REG2);
+ if (brightness_sticky_val != 0)
+ return (brightness_sticky_val & 0x0fff) >> 1;
+ return -1;
+}
+
+int do_configure_backlight(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+#ifdef CONFIG_SYS_I2C_AML
+ int ret, i, attempt;
+ const int retries = 3;
+ char *addr_cal;
+ int calibrated_current, persistent_brightness;
+
+ /* Values to write:
+ * [0]: Brightness register control only, backlight enabled
+ * [1-2]: Standby disabled, 20mA MAX_CURRENT, CURRENT scale 1/2
+ * [3]: Enable undervoltage protection at 5.2 V, "disable" backlight
+ * (i2c only), disable set resistors
+ * [4]: 9.6kHz PWM rate, 3 phase drivers
+ * [5]: EN_DRV3, EN_DRV2, boost inductor current limit = 1.6 A
+ * [6]: VBOOST_MAX = 25 V, JUMP_EN = 0
+ * [7]: STEP_UP = 105 mV, STEP_DN = 105 mV, LED_FAULT_TH = 3V,
+ * LED_COMP_HYST = DRIVER_HEADROOM + 750 mV
+ * [8-9]: 12-bit brightness (default: 100%)
+ * Important: Write brightness last to apply current calibration */
+ const __u8 addrs[] = {0x01, 0xa0, 0xa1, 0xa2, 0xa5, 0xa7, 0xa9, 0xae,
+ 0x10, 0x11};
+ __u8 values[] = {0x85, 0xff, 0x37, 0x30, 0x54, 0xf4, 0x60, 0x09, 0xff,
+ 0x0f};
+ const int n_bytes = sizeof(values)/sizeof(values[0]);
+
+ if (argc > 2) {
+ printf("%s: Too many args: %d\n", __func__, argc);
+ return CMD_RET_USAGE;
+ }
+
+ if (argc == 2) {
+ addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
+ calibrated_current = parse_calibration_file_string(addr_cal);
+ if (calibrated_current >= 0 && calibrated_current <= 4095) {
+ /* CURRENT_LSB */
+ values[1] = 0xff & calibrated_current;
+ /* CURRENT_MSB */
+ values[2] = (values[2] & 0xf0) |
+ (0x0f & (calibrated_current >> 8));
+ }
+ }
+
+ // Apply persistent brightness if found
+ persistent_brightness = get_persistent_brightness();
+ if (persistent_brightness >= 0) {
+ printf("Applying persistent_brightness=%d\n", persistent_brightness);
+ /* Get LSB and MSB */
+ values[n_bytes - 2] = persistent_brightness & 0xff;
+ values[n_bytes - 1] = persistent_brightness >> 8 & 0x0f;
+ } else {
+ printf("Persistent_brightness not set\n");
+ }
+
+ enable_backlight(true);
+
+ i2c_set_bus_num(AML_I2C_MASTER_D);
+ for (i = 0; i < n_bytes; ++i) {
+ for (attempt = 0; attempt < retries; ++attempt) {
+ ret = i2c_write(0x2c, addrs[i], 1, &values[i], 1);
+ if (ret)
+ printf("%s: Attempt=%d to write byte=0x%02x to reg=0x%02x of backlight failed\n",
+ __func__, attempt, values[i], addrs[i]);
+ else
+ break;
+ }
+ }
+
+ return ret;
+#else
+ enable_backlight(true);
+
+ return 0;
+#endif /* CONFIG_SYS_I2C_AML */
+}
+
+U_BOOT_CMD(
+ configure_backlight, 2, 0, do_configure_backlight,
+ "configures the lp8556 backlight",
+ "Usage: configure_backlight [calibration_string_addr]\n"\
+ " Sets up required parameters of the backlight.\n"\
+ " Default calibration is 100%.\n"\
+ " calibration_str_addr (optional):\n"\
+ " Address of calibration file string to parse.\n"
+);
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM 1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_USB_GPIO_PWR,
+ CONFIG_USB_GPIO_PWR_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_USB_GPIO_PWR);
+ return;
+ }
+
+ if (is_power_on) {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
+ } else {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+ .usb_phy2_pll_base_addr = {
+ CONFIG_USB_PHY_20,
+ CONFIG_USB_PHY_21,
+ }
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "fts",
+ .offset = 0,
+ .size = 1*SZ_1M,
+ },
+ {
+ .name = "factory",
+ .offset = 0,
+ .size = 8*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 220*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "cache",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xfffff << 12);
+ if (enable)
+ val |= 0x33333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~(0xf << 24);
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xf6000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+#ifdef CONFIG_AML_SPICC
+/* generic config in arch gpio/clock.c */
+extern int spicc1_clk_set_rate(int rate);
+extern int spicc1_clk_enable(bool enable);
+extern int spicc1_pinctrl_enable(bool enable);
+
+static const struct spicc_platdata spicc1_platdata = {
+ .compatible = "amlogic,meson-g12a-spicc",
+ .reg = (void __iomem *)0xffd15000,
+ .clk_rate = 666666666,
+ .clk_set_rate = spicc1_clk_set_rate,
+ .clk_enable = spicc1_clk_enable,
+ .pinctrl_enable = spicc1_pinctrl_enable,
+ /* case one slave without cs: {"no_cs", 0} */
+ .cs_gpio_names = {"GPIOH_6", 0},
+};
+
+U_BOOT_DEVICE(spicc1) = {
+ .name = "spicc",
+ .platdata = &spicc1_platdata,
+};
+#endif /* CONFIG_AML_SPICC */
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+ CPU_GPU_Voltage_init();
+ enable_backlight(false);
+ panel_detect_init();
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+ //As NOT NEED other board init If USB BOOT MODE
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+ board_usb_pll_disable(&g_usb_config_GXL_skt);
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_SYS_I2C_AML
+ board_i2c_init();
+#endif
+
+ /* TODO(b/110040521): This is the earliest the backlight can be started,
+ * but the LCD is not running yet. */
+
+#if 0
+ aml_pwm_cal_init(0);
+#endif//
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ gpio_disable_pull();
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ run_command("defenv", 0);
+ run_command("run detect_panel", 0);
+#if 0
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+#ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+#endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#endif
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 1 p321 v1
+ * hwid = 2 p321 v2
+ */
+ unsigned int hwid = 1;
+ char loc_name[64] = {0};
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+
+ switch (hwid) {
+ case 1:
+ strcpy(loc_name, "txl_p321_v1\0");
+ break;
+ case 2:
+ strcpy(loc_name, "txl_p321_v2\0");
+ break;
+ default:
+ strcpy(loc_name, "txl_p321_v1");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+/* workaround for VDDEE issue */
+/* VCCK PWM table */
+#define VCCK_VAL_REG_800 0x00150007
+#define VCCK_VAL_REG_810 0x00140008
+#define VCCK_VAL_REG_820 0x00130009
+#define VCCK_VAL_REG_830 0x0012000a
+#define VCCK_VAL_REG_840 0x0011000b
+#define VCCK_VAL_REG_850 0x0010000c
+#define VCCK_VAL_REG_860 0x000f000d
+#define VCCK_VAL_REG_870 0x000e000e
+#define VCCK_VAL_REG_880 0x000d000f
+#define VCCK_VAL_REG_890 0x000c0010
+#define VCCK_VAL_REG_900 0x000b0011
+#define VCCK_VAL_REG_910 0x000a0012
+#define VCCK_VAL_REG_920 0x00090013
+#define VCCK_VAL_REG_930 0x00080014
+#define VCCK_VAL_REG_940 0x00070015
+#define VCCK_VAL_REG_950 0x00060016
+#define VCCK_VAL_REG_960 0x00050017
+#define VCCK_VAL_REG_970 0x00040018
+#define VCCK_VAL_REG_980 0x00030019
+#define VCCK_VAL_REG_990 0x0002001a
+#define VCCK_VAL_REG_1000 0x0001001b
+#define VCCK_VAL_REG_1010 0x0000001c
+#define VCCK_VAL_REG_DEFAULT 0x00500008
+
+/* VDDEE PWM table */
+#define VDDEE_VAL_REG_800 0x0010000c
+#define VDDEE_VAL_REG_810 0x000f000d
+#define VDDEE_VAL_REG_820 0x000e000e
+#define VDDEE_VAL_REG_830 0x000d000f
+#define VDDEE_VAL_REG_840 0x000c0010
+#define VDDEE_VAL_REG_850 0x000b0011
+#define VDDEE_VAL_REG_860 0x000a0012
+#define VDDEE_VAL_REG_870 0x00090013
+#define VDDEE_VAL_REG_880 0x00080014
+#define VDDEE_VAL_REG_890 0x00070015
+#define VDDEE_VAL_REG_900 0x00060016
+#define VDDEE_VAL_REG_910 0x00050017
+#define VDDEE_VAL_REG_920 0x00040018
+#define VDDEE_VAL_REG_930 0x00030019
+#define VDDEE_VAL_REG_940 0x0002001a
+#define VDDEE_VAL_REG_950 0x0001001b
+#define VDDEE_VAL_REG_960 0x0000001c
+#define VDDEE_VAL_REG_DEFAULT 0x00500008
+
+void reset_misc(void)
+{
+ unsigned int value;
+
+ /* adjust VDDCPU to Hiz value step by step */
+ writel(VCCK_VAL_REG_830, AO_PWM_PWM_D);
+ udelay(1);
+ writel(VCCK_VAL_REG_860, AO_PWM_PWM_D);
+ udelay(1);
+
+ /* GPIOE_0 & GPIOE_1 to gpio pin */
+ value = readl(AO_RTI_PINMUX_REG1);
+ value &= ~(0xff << 16);
+ writel(value, AO_RTI_PINMUX_REG1);
+
+ /* disable pwm_ao_b - VDDEE */
+ value = readl(AO_PWM_MISC_REG_AB);
+ value &= ~((0x1 << 1) | (0x1 << 23));
+ writel(value, AO_PWM_MISC_REG_AB);
+ writel(VDDEE_VAL_REG_DEFAULT, AO_PWM_PWM_B);
+
+ /* disable pwm_ao_d - VDDCPU_B*/
+ value = readl(AO_PWM_MISC_REG_CD);
+ value &= ~((0x1 << 1) | (0x1 << 23));
+ writel(value, AO_PWM_MISC_REG_CD);
+ writel(VCCK_VAL_REG_DEFAULT, AO_PWM_PWM_D);
+}
diff --git a/board/amlogic/g12a_estelle_p2/lcd.c b/board/amlogic/g12a_estelle_p2/lcd.c
new file mode 100755
index 0000000..8d836aa
--- /dev/null
+++ b/board/amlogic/g12a_estelle_p2/lcd.c
@@ -0,0 +1,527 @@
+/*
+ * AMLOGIC TV LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_6", /* panel rst */
+ "GPIOZ_8", /* panel power */
+ "invalid", /* ending flag */
+};
+
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd power */
+#if 1
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,
+ /* custome */
+ Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,1,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_EXTERN,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_EXTERN,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM_FT*/
+ "lcd_3",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,3,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB_FT*/
+ "lcd_4",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,770,1070,10,80,0,6,20,0,
+ /* clk_attr */
+ 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,4,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOH_5
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+static unsigned char mipi_init_on_table[] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xff, 20,
+ 0x05, 1, 0x29,
+ 0xff, 20,
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table[] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xff, 10,
+ 0x05, 1, 0x10,
+ 0xff, 10,
+ 0xff,0xff, //ending flag
+};
+static unsigned char mipi_init_on_table_TV070WSM[] = {//table size < 100
+ 0xff, 10,
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
+ 0xff, 10, /* delay */
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TV070WSM[] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+static unsigned char mipi_init_on_table_P070ACB[] = {//table size < 100
+ 0xff, 10,
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
+ 0xff, 10, /* delay */
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_P070ACB[] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 2, /* ext_index if needed, must match ext_config_dtf.index;*/
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_clk_path = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0xff, //ending flag
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff,0xff, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 5,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = 1,
+ .name = "mipi_TV070WSM",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = 2,
+ .name = "mipi_P070ACB",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = 3,
+ .name = "mipi_TV070WSM_FT",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = 4,
+ .name = "mipi_P070ACB_FT",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_EXTERN,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "i2c_lp8556",
+ .type = BL_EXTERN_I2C,
+ .i2c_addr = 0x2c,
+ .i2c_bus = BL_EXTERN_I2C_BUS_D,
+ .dim_min = 10,
+ .dim_max = 255,
+};
+#endif
+
+extern int i2c_set_bus_num(unsigned int busnum);
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 3:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 4:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_BL_EXTERN
+ i2c_set_bus_num(BL_EXTERN_I2C_BUS_D);
+#endif
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/g12a_estelle_p2/pwm_table.c b/board/amlogic/g12a_estelle_p2/pwm_table.c
new file mode 100755
index 0000000..18dc638
--- /dev/null
+++ b/board/amlogic/g12a_estelle_p2/pwm_table.c
@@ -0,0 +1,71 @@
+#include <common.h>
+
+const int pwm_cal_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+const int pwm_cal_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
+int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
+
+
diff --git a/board/amlogic/g12a_estelle_p2/zircon.c b/board/amlogic/g12a_estelle_p2/zircon.c
new file mode 100644
index 0000000..81b83f3
--- /dev/null
+++ b/board/amlogic/g12a_estelle_p2/zircon.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2018 The Fuchsia Authors
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common.h>
+#include <storage.h>
+#include <version.h>
+#include <zircon-estelle/zircon.h>
+#include <zircon-estelle/partition.h>
+
+#define PDEV_VID_GOOGLE 3
+#define PDEV_PID_ASTRO 3
+
+#define NVRAM_LENGTH (8 * 1024)
+
+static const zbi_cpu_config_t cpu_config = {
+ .cluster_count = 1,
+ .clusters = {
+ {
+ .cpu_count = 4,
+ },
+ },
+};
+
+static const zbi_mem_range_t mem_config[] = {
+ {
+ .type = ZBI_MEM_RANGE_RAM,
+ .length = 0x60000000, // 1.5 GB
+ },
+ {
+ .type = ZBI_MEM_RANGE_PERIPHERAL,
+ .paddr = 0xf5800000,
+ .length = 0x0a800000,
+ },
+ // secmon_reserved:linux,secmon
+ {
+ .type = ZBI_MEM_RANGE_RESERVED,
+ .paddr = 0x05000000,
+ .length = 0x2400000,
+ },
+ // logo_reserved:linux,meson-fb
+ {
+ .type = ZBI_MEM_RANGE_RESERVED,
+ .paddr = 0x5f800000,
+ .length = 0x800000,
+ },
+};
+
+static const dcfg_simple_t uart_driver = {
+ .mmio_phys = 0xff803000,
+ .irq = 225,
+};
+
+static const dcfg_arm_gicv2_driver_t gicv2_driver = {
+ .mmio_phys = 0xffc00000,
+ .gicd_offset = 0x1000,
+ .gicc_offset = 0x2000,
+ .gich_offset = 0x4000,
+ .gicv_offset = 0x6000,
+ .ipi_base = 5,
+};
+
+static const dcfg_arm_psci_driver_t psci_driver = {
+ .use_hvc = false,
+ .reboot_args = {1, 0, 0},
+ .reboot_bootloader_args = {4, 0, 0},
+ .reboot_recovery_args = {2, 0, 0},
+};
+
+static const dcfg_arm_generic_timer_driver_t timer_driver = {
+ .irq_phys = 30,
+};
+
+static const zbi_platform_id_t platform_id = {
+ .vid = PDEV_VID_GOOGLE,
+ .pid = PDEV_PID_ASTRO,
+ .board_name = "astro",
+};
+
+bool zircon_is_vboot_enabled(void)
+{
+ return true;
+}
+
+bool zircon_is_vboot_unlock_enabled(void)
+{
+ return false;
+}
+
+int zircon_vboot_disable_vboot_unlock(void)
+{
+ return -1;
+}
+
+int zircon_vboot_set_unlock(bool unlock)
+{
+ return -1;
+}
+
+static void add_partition_map(zbi_header_t * zbi)
+{
+ const zbi_partition_map_t *partition_map = zircon_get_partition_map();
+ if (partition_map == NULL) {
+ printf("WARNING: zircon partition map is not defined.\n");
+ return;
+ }
+ zircon_append_boot_item(zbi, ZBI_TYPE_DRV_PARTITION_MAP, 0,
+ partition_map,
+ sizeof(zbi_partition_map_t) +
+ partition_map->partition_count *
+ sizeof(zbi_partition_t));
+}
+
+int zircon_preboot(zbi_header_t * zbi)
+{
+ // add CPU configuration
+ zircon_append_boot_item(zbi, ZBI_TYPE_CPU_CONFIG, 0, &cpu_config,
+ sizeof(zbi_cpu_config_t) +
+ sizeof(zbi_cpu_cluster_t) *
+ cpu_config.cluster_count);
+
+ // allocate crashlog save area before 0x5f800000-0x60000000 reserved area
+ zbi_nvram_t nvram;
+ nvram.base = 0x5f800000 - NVRAM_LENGTH;
+ nvram.length = NVRAM_LENGTH;
+ zircon_append_boot_item(zbi, ZBI_TYPE_NVRAM, 0, &nvram, sizeof(nvram));
+
+ // add memory configuration
+ zircon_append_boot_item(zbi, ZBI_TYPE_MEM_CONFIG, 0, &mem_config,
+ sizeof(mem_config));
+
+ // add kernel drivers
+ zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_AMLOGIC_UART,
+ &uart_driver, sizeof(uart_driver));
+ zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GIC_V2,
+ &gicv2_driver, sizeof(gicv2_driver));
+ zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_PSCI,
+ &psci_driver, sizeof(psci_driver));
+ zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER,
+ KDRV_ARM_GENERIC_TIMER, &timer_driver,
+ sizeof(timer_driver));
+
+ char uboot_ver[] = "bootloader.name=" U_BOOT_VERSION_STRING;
+ // Zircon's cmdline parameters cannot contain spaces so
+ // convert spaces in autogenerated U-boot version string
+ // to underscores.
+ // See zircon/docs/kernel_cmdline.md
+ int i;
+ int len = strlen(uboot_ver);
+ for (i = 0; i < len; i++) {
+ if (uboot_ver[i] == ' ') {
+ uboot_ver[i] = '_';
+ }
+ }
+
+ zircon_append_boot_item(zbi, ZBI_TYPE_CMDLINE, 0, uboot_ver, len + 1);
+
+ // add platform ID
+ zircon_append_boot_item(zbi, ZBI_TYPE_PLATFORM_ID, 0, &platform_id,
+ sizeof(platform_id));
+
+ add_partition_map(zbi);
+
+ return 0;
+}
diff --git a/board/amlogic/g12a_estelle_p2/zircon_partition.c b/board/amlogic/g12a_estelle_p2/zircon_partition.c
new file mode 100644
index 0000000..bf892ac
--- /dev/null
+++ b/board/amlogic/g12a_estelle_p2/zircon_partition.c
@@ -0,0 +1,591 @@
+/*
+ * Copyright (c) 2019 The Fuchsia Authors
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <config.h>
+#include <common.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <nand.h>
+
+#include <partition_table.h>
+#include <amlogic/storage_if.h>
+
+#include <zircon/boot/image.h>
+#include <zircon-estelle/partition.h>
+#include <zircon-estelle/zircon.h>
+
+/* most NANDs have ERASE GRP which does not exceed 256K */
+#define ERASE_GRP_SIZE_MAX (256*1024)
+
+#if defined(ZPARTITION_DEBUG)
+#define debugP(fmt...) \
+ printf("[Dbg zircon partition]%s:%d:", __func__, __LINE__),printf(fmt)
+#else
+#define debugP(fmt...)
+#endif
+
+#define RECOVERY_SIZE (16 * 1024 * 1024)
+#define SYS_CONFIG_SIZE (1 * 1024 * 1024)
+#define MIGRATION_SIZE (3 * 1024 * 1024)
+
+extern struct mtd_partition *get_aml_mtd_partition(void);
+extern int get_aml_partition_count(void);
+
+enum {
+ PART_TPL,
+ PART_FTS,
+ PART_FACTORY,
+ PART_ZIRCON_R,
+ PART_ZIRCON_A,
+ PART_ZIRCON_B,
+ PART_FVM,
+ PART_SYS_CONFIG,
+ PART_MIGRATION,
+ PART_COUNT,
+};
+
+static zbi_partition_map_t partition_map = {
+ // .block_count filled in below
+ // .block_size filled in below
+ .guid = {},
+ .partition_count = PART_COUNT,
+ .partitions = {
+ {
+ .type_guid = GUID_BOOTLOADER_VALUE,
+ .name = "tpl",
+ },
+ {
+ .name = "fts",
+ },
+ {
+ .name = "factory",
+ },
+ {
+ .type_guid = GUID_ZIRCON_R_VALUE,
+ .name = ZIRCON_PARTITION_PREFIX"r",
+ },
+ {
+ .type_guid = GUID_ZIRCON_A_VALUE,
+ .name = ZIRCON_PARTITION_PREFIX"a",
+ },
+ {
+ .type_guid = GUID_ZIRCON_B_VALUE,
+ .name = ZIRCON_PARTITION_PREFIX"b",
+ },
+ {
+ .type_guid = GUID_FVM_VALUE,
+ .name = "fvm",
+ },
+ {
+ .type_guid = GUID_SYS_CONFIG_VALUE,
+ .name = "sys-config",
+ },
+ {
+ .name = "migration",
+ },
+ },
+};
+
+static void init_partition_map(void)
+{
+ struct mtd_partition *tpl_part = NULL;
+ struct mtd_partition *fts_part = NULL;
+ struct mtd_partition *factory_part = NULL;
+ struct mtd_partition *recovery_part = NULL;
+ struct mtd_partition *boot_part = NULL;
+ struct mtd_partition *system_part = NULL;
+ struct mtd_partition *partitions = get_aml_mtd_partition();
+ int partition_count = get_aml_partition_count();
+ int i;
+ static int init_done = 0;
+
+ if (init_done) {
+ return;
+ }
+
+ for (i = 0; i < partition_count; i++) {
+ struct mtd_partition *part = &partitions[i];
+ if (!strcmp("tpl", part->name)) {
+ tpl_part = part;
+ } else if (!strcmp("fts", part->name)) {
+ fts_part = part;
+ } else if (!strcmp("factory", part->name)) {
+ factory_part = part;
+ } else if (!strcmp("recovery", part->name)) {
+ recovery_part = part;
+ } else if (!strcmp("boot", part->name)) {
+ boot_part = part;
+ } else if (!strcmp("system", part->name)) {
+ system_part = part;
+ }
+ }
+
+ if (!tpl_part) {
+ printf("could not find tpl partition\n");
+ return;
+ }
+ if (!fts_part) {
+ printf("could not find fts partition\n");
+ return;
+ }
+ if (!factory_part) {
+ printf("could not find factory partition\n");
+ return;
+ }
+ if (!recovery_part) {
+ printf("could not find recovery partition\n");
+ return;
+ }
+ if (!boot_part) {
+ printf("could not find boot partition\n");
+ return;
+ }
+ if (!system_part) {
+ printf("could not find system partition\n");
+ return;
+ }
+
+ uint32_t block_size = nand_info[1].writesize;
+ uint64_t total_size = nand_info[1].size;
+
+ partition_map.block_size = block_size;
+ partition_map.block_count = total_size / block_size;
+
+ /* map tpl partition to BOOTLOADER */
+ partition_map.partitions[PART_TPL].first_block =
+ tpl_part->offset / block_size;
+ partition_map.partitions[PART_TPL].last_block =
+ ((tpl_part->offset + tpl_part->size) / block_size) - 1;
+ /* map fts partition to "fts" */
+ partition_map.partitions[PART_FTS].first_block =
+ fts_part->offset / block_size;
+ partition_map.partitions[PART_FTS].last_block =
+ ((fts_part->offset + fts_part->size) / block_size) - 1;
+ /* map factory partition to "factory" */
+ partition_map.partitions[PART_FACTORY].first_block =
+ factory_part->offset / block_size;
+ partition_map.partitions[PART_FACTORY].last_block =
+ ((factory_part->offset + factory_part->size) / block_size) - 1;
+ /* map recovery partition to ZIRCON_R */
+ partition_map.partitions[PART_ZIRCON_R].first_block =
+ recovery_part->offset / block_size;
+ partition_map.partitions[PART_ZIRCON_R].last_block =
+ ((recovery_part->offset + recovery_part->size) / block_size) - 1;
+ /* map boot partition to ZIRCON_A */
+ partition_map.partitions[PART_ZIRCON_A].first_block =
+ boot_part->offset / block_size;
+ partition_map.partitions[PART_ZIRCON_A].last_block =
+ ((boot_part->offset + boot_part->size) / block_size) - 1;
+ /* ZIRCON_B partition at start of system */
+ partition_map.partitions[PART_ZIRCON_B].first_block =
+ system_part->offset / block_size;
+ partition_map.partitions[PART_ZIRCON_B].last_block =
+ partition_map.partitions[PART_ZIRCON_B].first_block +
+ (boot_part->size / block_size) - 1;
+ /* FVM follows ZIRCON_B */
+ partition_map.partitions[PART_FVM].first_block =
+ partition_map.partitions[PART_ZIRCON_B].last_block + 1;
+ partition_map.partitions[PART_FVM].last_block =
+ ((total_size - SYS_CONFIG_SIZE - MIGRATION_SIZE) / block_size) - 1;
+ /* SYS_CONFIG follows FVM */
+ partition_map.partitions[PART_SYS_CONFIG].first_block =
+ partition_map.partitions[PART_FVM].last_block + 1;
+ partition_map.partitions[PART_SYS_CONFIG].last_block =
+ partition_map.partitions[PART_SYS_CONFIG].first_block +
+ (SYS_CONFIG_SIZE / block_size) - 1;
+ /* MIGRATION follows SYS_CONFIG */
+ partition_map.partitions[PART_MIGRATION].first_block =
+ partition_map.partitions[PART_SYS_CONFIG].last_block + 1;
+ partition_map.partitions[PART_MIGRATION].last_block =
+ partition_map.partitions[PART_MIGRATION].first_block +
+ (MIGRATION_SIZE / block_size) - 1;
+
+ printf("Zircon partitions:\n");
+ for (i = 0; i < PART_COUNT; i++) {
+ printf(" 0x%016llx - 0x%016llx : %s\n",
+ partition_map.partitions[i].first_block * block_size,
+ (partition_map.partitions[i].last_block +
+ 1) * block_size, partition_map.partitions[i].name);
+ }
+
+ init_done = 1;
+ return;
+}
+
+/*
+ * It is bad idea to write to NAND without erasing data first.
+ * NAND can be erased only by NAND ERASE GROUP size.
+ * So, need todo following:
+ * 1. read existing data
+ * 2. update data
+ * 3. erase NAND region
+ * 4. write modified data back to NANS
+ */
+static int update_sys_cfg_copy(uint8_t grp_idx,
+ uint64_t off,
+ const unsigned char *data, size_t size)
+{
+ int ret = 0;
+ char str[128];
+ uint64_t sys_cfg_offset;
+ nand_info_t *nand = &nand_info[nand_curr_device];
+ unsigned char buf[ERASE_GRP_SIZE_MAX];
+
+ assert(nand->erasesize <= ERASE_GRP_SIZE_MAX);
+ assert((off + size) <= nand->erasesize);
+
+ /* init partition layout in case it was not initialized already */
+ init_partition_map();
+
+ sys_cfg_offset = partition_map.partitions[PART_SYS_CONFIG].first_block
+ * partition_map.block_size;
+
+ debugP("Update %d copy of sys-config on NAND\n", grp_idx);
+
+ /* 1. read existing data */
+ debugP(" 1. reading existing data from NAND (%u, %u)\n",
+ nand->erasesize * grp_idx, nand->erasesize);
+ if (store_read_ops((unsigned char *)"sys-config",
+ buf,
+ nand->erasesize * grp_idx, nand->erasesize) < 0) {
+ printf
+ ("ERROR(%s:L%d) failed to read data from %s partition (off %u size %u)\n",
+ __func__, __LINE__, "sys-config",
+ nand->erasesize * grp_idx, nand->erasesize);
+ return __LINE__;
+ }
+
+ /* 2. update data */
+ debugP(" 2. updating data with new info\n");
+ memcpy(buf + off, data, size);
+
+ /* 3. erase NAND region */
+ /* TODO (dmitryya@): optimization: check if a region is already erased */
+ /* wipe one ERASE BLOCK */
+ debugP(" 3. erasing NAND (%lld, %u)\n",
+ sys_cfg_offset + nand->erasesize * grp_idx, nand->erasesize);
+ snprintf(str, 128, "nand erase 0x%08llX 0x%04X",
+ sys_cfg_offset + nand->erasesize * grp_idx, nand->erasesize);
+ ret = run_command(str, 0);
+ if (ret != 0) {
+ printf("ERROR(%s:L%d) erase failed!\n", __func__, __LINE__);
+ return -1;
+ }
+
+ /* 4. write data back */
+ debugP(" 4. writing updated data back to NAND(%u, %u)\n",
+ nand->erasesize * grp_idx, nand->erasesize);
+ if (store_write_ops((unsigned char *)"sys-config",
+ (unsigned char *)buf,
+ nand->erasesize * grp_idx, nand->erasesize) < 0) {
+ printf
+ ("ERROR(%s:L%d) failed to write data to %s partition (off %u size %u).\n",
+ __func__, __LINE__, "sys-config",
+ nand->erasesize * grp_idx, nand->erasesize);
+ return __LINE__;
+ }
+
+ return 0;
+}
+
+#define SYS_CFG_NUM_OF_COPIES 4
+static int write_to_sys_config(uint64_t offset, const unsigned char *data,
+ size_t size)
+{
+ int ret = -1;
+
+ if (NAND_BOOT_FLAG == device_boot_flag) {
+ int i;
+
+ debugP("Update all copies of 'sys-config'\n");
+ for (i = 0; i < SYS_CFG_NUM_OF_COPIES; ++i) {
+ int r = update_sys_cfg_copy(i, offset, data, size);
+ /* at least one copy has to be written without error */
+ if (r == 0) {
+ ret = 0;
+ }
+ }
+ } else {
+ if (store_write_ops((unsigned char *)"sys-config",
+ (unsigned char *)data, offset, size) == 0) {
+ ret = 0;
+ }
+ }
+
+ return ret;
+}
+
+static int read_from_sys_config(uint64_t offset, unsigned char *data,
+ size_t size)
+{
+ int ret = -1;
+
+ debugP("Reading data from sys-config: 0x%llX offset, %zd size\n",
+ offset, size);
+ if (NAND_BOOT_FLAG == device_boot_flag) {
+ int i;
+ /* at least one copy has to be read without error */
+ for (i = 0; i < SYS_CFG_NUM_OF_COPIES; ++i) {
+ if (store_read_ops((unsigned char *)"sys-config",
+ data,
+ i * ERASE_GRP_SIZE_MAX + offset,
+ size) == 0) {
+ return 0;
+ }
+ }
+ } else {
+ if (store_read_ops((unsigned char *)"sys-config",
+ data, offset, size) == 0) {
+ ret = 0;
+ }
+ }
+
+ return ret;
+}
+
+static int erase_at_sys_config(uint64_t offset, size_t size)
+{
+ int ret = -1;
+ unsigned char buf[ERASE_GRP_SIZE_MAX] = { 0 };
+
+ /*
+ * max 'logic' partition size inside sys-config parition has to be
+ * less then ERASE GROUP SIZE
+ */
+ assert(size < ERASE_GRP_SIZE_MAX);
+
+ if (NAND_BOOT_FLAG == device_boot_flag) {
+ int i;
+
+ debugP("Update all copies of 'sys-config'\n");
+ for (i = 0; i < 4; ++i) {
+ int r = update_sys_cfg_copy(i, offset, buf, size);
+ /* at least one copy has to be written without error */
+ if (r == 0) {
+ ret = 0;
+ }
+ }
+ } else {
+ if (store_write_ops((unsigned char *)"sys-config",
+ (unsigned char *)buf, offset, size) == 0) {
+ ret = 0;
+ }
+ }
+
+ return ret;
+}
+
+const zbi_partition_t *get_partition_by_name(const char *name)
+{
+ int i;
+ if (name == NULL)
+ return NULL;
+
+ /* init partition layout in case it was not initialized already */
+ init_partition_map();
+ for (i = 0; i < PART_COUNT; i++) {
+ if (!strncmp(partition_map.partitions[i].name, name,
+ ZBI_PARTITION_NAME_LEN)) {
+ return &partition_map.partitions[i];
+ }
+ }
+
+ return NULL;
+}
+
+/* === public API === */
+
+const zbi_partition_map_t *zircon_get_partition_map(void)
+{
+ /* init partition layout in case it was not initialized already */
+ init_partition_map();
+ return &partition_map;
+}
+
+/*
+ * ABR and AVBs metadatas are located on 'sys-config' partition.
+ * 'sys-config' partition has following layout:
+ * 00000 - 0EFFF (60K) sys-config data
+ * 0F000 - 0FFFF (4K) A/B/R metadata
+ * 10000 - 1FFFF (64K) AVB -a metadata
+ * 20000 - 2FFFF (64K) AVB -b metadata
+ * 30000 - 3FFFF (64K) AVB -r metadata
+ */
+#define ABR_OFFSET 0x0F000
+#define AVB_A_OFFSET 0x10000
+#define AVB_B_OFFSET 0x20000
+#define AVB_R_OFFSET 0x30000
+#define ABR_SIZE (4*1024)
+#define AVB_SIZE (64*1024)
+
+int zircon_partition_write(const char *name, uint64_t offset,
+ const unsigned char *data, size_t size)
+{
+ /* size has to be multiple of page size. Otherwise low level API will crash */
+ assert((size % PAGE_SIZE) == 0);
+
+ /* TODO (dmitryya@) move partition boundary check for offset + size here. */
+ if (!strcmp(name, "sys-config")) {
+ return write_to_sys_config(offset, data, size);
+ } else if (!strcmp(name, "misc")) {
+ return write_to_sys_config(offset + ABR_OFFSET, data, size);
+ } else if (!strcmp(name, "vbmeta-a")) {
+ return write_to_sys_config(offset + AVB_A_OFFSET, data, size);
+ } else if (!strcmp(name, "vbmeta-b")) {
+ return write_to_sys_config(offset + AVB_B_OFFSET, data, size);
+ } else if (!strcmp(name, "vbmeta-r")) {
+ return write_to_sys_config(offset + AVB_R_OFFSET, data, size);
+ } else { /* access to general partition */
+ nand_info_t *nand = &nand_info[nand_curr_device];
+
+ const zbi_partition_t *ptn = get_partition_by_name(name);
+ uint32_t block_size = partition_map.block_size;
+
+ if (ptn != NULL) {
+ int flags = 0;
+ size_t len = size;
+ uint64_t ptn_size =
+ (ptn->last_block - ptn->first_block +
+ 1) * block_size;
+ loff_t flash_offset =
+ ptn->first_block * block_size + offset;
+
+ if (flash_offset > ptn->last_block * block_size) {
+ return -1;
+ }
+
+ return nand_write_skip_bad(nand, flash_offset, &len,
+ NULL, ptn_size - offset,
+ (u_char *) data, flags);
+ }
+ }
+
+ return -1;
+}
+
+int zircon_partition_read(const char *name, uint64_t offset,
+ unsigned char *data, size_t size)
+{
+ /* size has to be multiple of page size. Otherwise low level API will crash */
+ assert((size % PAGE_SIZE) == 0);
+
+ /* TODO (dmitryya@) move partition boundary check for offset + size here. */
+ if (!strcmp(name, "sys-config")) {
+ return read_from_sys_config(offset, data, size);
+ } else if (!strcmp(name, "misc")) {
+ return read_from_sys_config(offset + ABR_OFFSET, data, size);
+ } else if (!strcmp(name, "vbmeta-a")) {
+ return read_from_sys_config(offset + AVB_A_OFFSET, data, size);
+ } else if (!strcmp(name, "vbmeta-b")) {
+ return read_from_sys_config(offset + AVB_B_OFFSET, data, size);
+ } else if (!strcmp(name, "vbmeta-r")) {
+ return read_from_sys_config(offset + AVB_R_OFFSET, data, size);
+ } else { /* access to general partition */
+ nand_info_t *nand = &nand_info[nand_curr_device];
+
+ const zbi_partition_t *ptn = get_partition_by_name(name);
+ uint32_t block_size = partition_map.block_size;
+
+ if (ptn != NULL) {
+ size_t len = size;
+ uint64_t ptn_size =
+ (ptn->last_block - ptn->first_block +
+ 1) * block_size;
+ loff_t flash_offset =
+ ptn->first_block * block_size + offset;
+
+ if (flash_offset > ptn->last_block * block_size) {
+ return -1;
+ }
+
+ return nand_read_skip_bad(nand, flash_offset, &len,
+ NULL, ptn_size - offset,
+ data);
+ }
+ }
+
+ return -1;
+}
+
+int zircon_get_partititon_size(const char *name, uint64_t * size)
+{
+ assert(size != NULL);
+
+ /* virtual partitions */
+ if (!strcmp(name, "misc")) {
+ *size = ABR_SIZE;
+ return 0;
+ } else if (!strcmp(name, "vbmeta-a")) {
+ *size = AVB_SIZE;
+ return 0;
+ } else if (!strcmp(name, "vbmeta-b")) {
+ *size = AVB_SIZE;
+ return 0;
+ } else if (!strcmp(name, "vbmeta-r")) {
+ *size = AVB_SIZE;
+ return 0;
+ } else {
+ /* general partition */
+ uint32_t block_size = partition_map.block_size;
+ const zbi_partition_t *ptn = get_partition_by_name(name);
+ if (ptn != NULL) {
+ *size =
+ (ptn->last_block - ptn->first_block +
+ 1) * block_size;
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+int zircon_partition_erase(const char *name)
+{
+ if (!strcmp(name, "misc")) {
+ return erase_at_sys_config(ABR_OFFSET, ABR_SIZE);
+ } else if (!strcmp(name, "vbmeta-a")) {
+ return erase_at_sys_config(AVB_A_OFFSET, AVB_SIZE);
+ } else if (!strcmp(name, "vbmeta-b")) {
+ return erase_at_sys_config(AVB_B_OFFSET, AVB_SIZE);
+ } else if (!strcmp(name, "vbmeta-r")) {
+ return erase_at_sys_config(AVB_R_OFFSET, AVB_SIZE);
+ } else { /* access to general partition */
+ /* general partition */
+ uint32_t block_size;
+
+ /* init partition layout in case it was not initialized already */
+ init_partition_map();
+ block_size = partition_map.block_size;
+ const zbi_partition_t *ptn = get_partition_by_name(name);
+ if (ptn != NULL) {
+ nand_erase_options_t opts;
+ int ret;
+ nand_info_t *nand = &nand_info[nand_curr_device];
+
+ memset(&opts, 0, sizeof(opts));
+ opts.length =
+ (ptn->last_block - ptn->first_block +
+ 1) * block_size;
+ opts.offset = ptn->first_block * block_size;
+ opts.quiet = 1;
+
+ printf("Erasing blocks 0x%llx to 0x%llx\n",
+ opts.offset, opts.length);
+
+ ret = nand_erase_opts(nand, &opts);
+ if (ret)
+ return -1;
+
+ printf("........ erased 0x%llx bytes from '%s'\n",
+ opts.length, name);
+
+ return 0;
+ }
+ }
+
+ return -1;
+}
diff --git a/board/amlogic/g12a_newman_p0/Kconfig b/board/amlogic/g12a_newman_p0/Kconfig
new file mode 100755
index 0000000..4553294
--- /dev/null
+++ b/board/amlogic/g12a_newman_p0/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_G12A
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "g12a_newman_p0"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "g12a"
+
+config SYS_CONFIG_NAME
+ default "g12a_newman_p0"
+
+endif
diff --git a/board/amlogic/g12a_newman_p0/Makefile b/board/amlogic/g12a_newman_p0/Makefile
new file mode 100755
index 0000000..9ae0b2c
--- /dev/null
+++ b/board/amlogic/g12a_newman_p0/Makefile
@@ -0,0 +1,4 @@
+
+obj-y += $(BOARD).o
+obj-$(CONFIG_AML_LCD) += lcd.o
+obj-y += pwm_table.o
diff --git a/board/amlogic/g12a_newman_p0/aml-user-key.sig b/board/amlogic/g12a_newman_p0/aml-user-key.sig
new file mode 100755
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/g12a_newman_p0/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/g12a_newman_p0/firmware/scp_task/dvfs_board.c b/board/amlogic/g12a_newman_p0/firmware/scp_task/dvfs_board.c
new file mode 100755
index 0000000..b2f0670
--- /dev/null
+++ b/board/amlogic/g12a_newman_p0/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,194 @@
+
+/*
+ * board/amlogic/g12a_newman_p0/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+/*
+int pwm_voltage_table[ ][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+*/
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~((1 << 21) | 1 << 12);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(1 << 16);
+ P_PIN_MUX_REG10 = reg;//clear reg10
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/g12a_newman_p0/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12a_newman_p0/firmware/scp_task/pwm_ctrl.h
new file mode 100755
index 0000000..0b30066
--- /dev/null
+++ b/board/amlogic/g12a_newman_p0/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,40 @@
+/*
+*board/amlogic/g12a_newman_p0/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 681},
+ { 0x1b0001, 691},
+ { 0x1a0002, 701},
+ { 0x190003, 711},
+ { 0x180004, 721},
+ { 0x170005, 731},
+ { 0x160006, 741},
+ { 0x150007, 751},
+ { 0x140008, 761},
+ { 0x130009, 772},
+ { 0x12000a, 782},
+ { 0x11000b, 792},
+ { 0x10000c, 802},
+ { 0x0f000d, 812},
+ { 0x0e000e, 822},
+ { 0x0d000f, 832},
+ { 0x0c0010, 842},
+ { 0x0b0011, 852},
+ { 0x0a0012, 862},
+ { 0x090013, 872},
+ { 0x080014, 882},
+ { 0x070015, 892},
+ { 0x060016, 902},
+ { 0x050017, 912},
+ { 0x040018, 922},
+ { 0x030019, 932},
+ { 0x02001a, 942},
+ { 0x01001b, 952},
+ { 0x00001c, 962}
+};
+
+#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12a_newman_p0/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12a_newman_p0/firmware/scp_task/pwr_ctrl.c
new file mode 100755
index 0000000..452b3df
--- /dev/null
+++ b/board/amlogic/g12a_newman_p0/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,136 @@
+
+/*
+ * board/amlogic/g12a_newman_p0/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ /*set gpioH_8 low to power off vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+
+ /*set test_n low to power off vcck & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0x3 << 28)), AO_RTI_PIN_MUX_REG1);
+
+ /*step down ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ /*step up ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+ /*set test_n low to power on vcck & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0x3 << 28)), AO_RTI_PIN_MUX_REG1);
+ _udelay(100);
+
+ /*set gpioH_8 low to power on vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+ _udelay(10000);
+
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+
+ p->sources = val;
+ p->gpio_info_count = i;
+
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ unsigned char adc_key_cnt = 0;
+ init_remote();
+ saradc_enable();
+
+ do {
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/g12a_newman_p0/firmware/timing.c b/board/amlogic/g12a_newman_p0/firmware/timing.c
new file mode 100755
index 0000000..90a10d8
--- /dev/null
+++ b/board/amlogic/g12a_newman_p0/firmware/timing.c
@@ -0,0 +1,453 @@
+
+/*
+ * board/amlogic/g12a_newman_p0/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+
+ddr_set_t __ddr_setting[] = {
+{
+ /* g12a skt (u209) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 700,
+ .vref_dram_permil = 700,
+ .vref_reverse = 0,
+ .ac_trace_delay = {00,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function={0x0,0x0}, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+},
+{
+ /* g12a skt (u209) ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_16BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xA,
+ .dram_cs0_size_MB = 1024,
+ .dram_cs1_size_MB = 512,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {30,30,30,30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ .vref_reverse = 0,
+ .ac_trace_delay = {00,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) lpddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 1024,//1024,
+ .dram_cs1_size_MB = 1024,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 200,
+ .vref_dram_permil = 350,
+ .vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a Y2 dongle */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 1536,//1024,
+ .dram_cs1_size_MB = 0,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 200,
+ .vref_dram_permil = 350,
+ .vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0000001c
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE PWM table */
+#if (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x0010000c
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x000f000d
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x000e000e
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x000d000f
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x000c0010
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x000b0011
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x000a0012
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x00090013
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x00080014
+#elif (VDDEE_VAL == 890)
+ #define VDDEE_VAL_REG 0x00070015
+#elif (VDDEE_VAL == 900)
+ #define VDDEE_VAL_REG 0x00060016
+#elif (VDDEE_VAL == 910)
+ #define VDDEE_VAL_REG 0x00050017
+#elif (VDDEE_VAL == 920)
+ #define VDDEE_VAL_REG 0x00040018
+#elif (VDDEE_VAL == 930)
+ #define VDDEE_VAL_REG 0x00030019
+#elif (VDDEE_VAL == 940)
+ #define VDDEE_VAL_REG 0x0002001a
+#elif (VDDEE_VAL == 950)
+ #define VDDEE_VAL_REG 0x0001001b
+#elif (VDDEE_VAL == 960)
+ #define VDDEE_VAL_REG 0x0000001c
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ /* eg: PWM init */
+
+ /* PWM_AO_D */
+ /* VCCK_VAL_REG: check PWM table */
+ {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
+ /* PWM_AO_B */
+ /* VDDEE_VAL_REG: check PWM table */
+ {AO_PWM_PWM_B, VDDEE_VAL_REG, (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable VDDEE */
+ {GPIO_O_EN_N_REG3, 0, (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Enable VCCK */
+ {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 31), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/g12a_newman_p0/g12a_newman_p0.c b/board/amlogic/g12a_newman_p0/g12a_newman_p0.c
new file mode 100755
index 0000000..6e51227
--- /dev/null
+++ b/board/amlogic/g12a_newman_p0/g12a_newman_p0.c
@@ -0,0 +1,744 @@
+
+/*
+ * board/amlogic/g12a_newman_p0/g12a_newman_p0.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <flash_ts.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#ifdef CONFIG_AML_SPIFC
+#include <dm.h>
+#include <amlogic/spifc.h>
+#endif
+
+#include <asm/arch/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+int do_get_ddictype (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+#if defined(CONFIG_AML_MTD) || defined(CONFIG_AML_MMC)
+#if defined(CONFIG_AML_MTD)
+ extern bool amlnf_is_inited(void);
+ if(!amlnf_is_inited()) {
+#endif
+
+#if defined(CONFIG_AML_MMC)
+ extern bool amlmmc_is_inited(void);
+ if(!amlmmc_is_inited()) {
+#endif
+ setenv("ddic_type", "NOVATEK");
+ return 0;
+ }
+
+ flash_ts_init();
+
+ const char *fts_key = "ddic.type";
+
+ char fts_value[256] = { 0 };
+ flash_ts_get(fts_key, fts_value, sizeof(fts_value));
+
+ printf("FTS read: ddic.type -> %s\n", fts_value);
+
+ if (strncmp(fts_value, "FITI", sizeof(fts_value)) == 0) {
+ setenv("ddic_type", "FITI");
+ } else {
+ setenv("ddic_type", "NOVATEK");
+ }
+#endif
+ return 0;
+}
+
+U_BOOT_CMD(
+ get_ddictype, 1, 0, do_get_ddictype,
+ "get ddic type",
+ " This command will get and setenv 'ddic_type'\n"
+);
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+//SOC_VDDCPU_DVFS0
+#define VDD_CPU_DVFS0_EN_1 GPIOEE(GPIOZ_13)
+#define VDD_CPU_DVFS0_EN_1_NAME "GPIOZ_13"
+
+//SOC_VDDCPU_DVFS1
+#define VDD_CPU_DVFS1_EN_1 GPIOEE(GPIOZ_2)
+#define VDD_CPU_DVFS1_EN_1_NAME "GPIOZ_2"
+
+//SOC_VDDEE_DVFS0
+#define VDD_GPU_DVFS0_EN_1 GPIOEE(GPIOA_13)
+#define VDD_GPU_DVFS0_EN_1_NAME "GPIOA_13"
+
+//SOC_VDDEE_DVFS1
+#define VDD_GPU_DVFS1_EN_1 GPIOEE(GPIOZ_0)
+#define VDD_GPU_DVFS1_EN_1_NAME "GPIOZ_0"
+
+static void CPU_GPU_Voltage_init(void)
+{
+ int ret;
+
+ ret = gpio_request(VDD_CPU_DVFS0_EN_1,
+ VDD_CPU_DVFS0_EN_1_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", VDD_CPU_DVFS0_EN_1_NAME);
+ return;
+ }
+ gpio_direction_output(VDD_CPU_DVFS0_EN_1, 1);
+
+ ret = gpio_request(VDD_CPU_DVFS1_EN_1,
+ VDD_CPU_DVFS1_EN_1_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", VDD_CPU_DVFS1_EN_1_NAME);
+ return;
+ }
+ gpio_direction_output(VDD_CPU_DVFS1_EN_1, 1);
+
+ //GPU
+ ret = gpio_request(VDD_GPU_DVFS0_EN_1,
+ VDD_GPU_DVFS0_EN_1_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", VDD_GPU_DVFS0_EN_1_NAME);
+ return;
+ }
+ gpio_direction_output(VDD_GPU_DVFS0_EN_1, 0);
+
+ ret = gpio_request(VDD_GPU_DVFS1_EN_1,
+ VDD_GPU_DVFS1_EN_1_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", VDD_GPU_DVFS1_EN_1_NAME);
+ return;
+ }
+ gpio_direction_output(VDD_GPU_DVFS1_EN_1, 1);
+}
+
+//SOC_DISP_ID
+#define DISP_ID_PIN GPIOEE(GPIOH_5)
+#define DISP_ID_PIN_NAME "GPIOH_5"
+
+static void panel_detect_init(void)
+{
+ int ret;
+
+ ret = gpio_request(DISP_ID_PIN, DISP_ID_PIN_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", DISP_ID_PIN_NAME);
+ return;
+ }
+ gpio_direction_input(DISP_ID_PIN);
+}
+
+//SOC_BL_ENABLE
+#define BL_ENABLE_PIN GPIOEE(GPIOA_10)
+#define BL_ENABLE_PIN_NAME "GPIOA_10"
+
+static void enable_backlight(void)
+{
+ int ret;
+
+ ret = gpio_request(BL_ENABLE_PIN, BL_ENABLE_PIN_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %s failed\n", BL_ENABLE_PIN_NAME);
+ return;
+ }
+ gpio_direction_output(BL_ENABLE_PIN, 1);
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ /* check card detect */
+ clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#if defined(CONFIG_ENV_IS_NOWHERE) && defined(CONFIG_AML_SD_EMMC)
+ struct mmc *mmc;
+#endif
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+
+#if defined(CONFIG_ENV_IS_NOWHERE) && defined(CONFIG_AML_SD_EMMC)
+ /* try emmc here. */
+ mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ if (!mmc)
+ printf("%s() %d: No MMC found\n", __func__, __LINE__);
+ else if (mmc_init(mmc))
+ printf("%s() %d: MMC init failed\n", __func__, __LINE__);
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_AML
+struct aml_i2c_platform g_aml_i2c_plat[] = {
+ {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+
+ /* i2c_ao */
+ .master_ao_pinmux = {
+ .sda_reg = (unsigned long)MESON_I2C_AO_M0_SDA_GPIOAO_2_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .sda_mask = MESON_I2C_AO_M0_SDA_GPIOAO_2_MASK,
+#endif
+ .sda_bit = MESON_I2C_AO_M0_SDA_GPIOAO_2_BIT,
+
+ .scl_reg = (unsigned long)MESON_I2C_AO_M0_SCL_GPIOAO_3_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .scl_mask = MESON_I2C_AO_M0_SCL_GPIOAO_3_MASK,
+#endif
+ .scl_bit = MESON_I2C_AO_M0_SCL_GPIOAO_3_BIT,
+ },
+ },
+ {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_A,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+
+ /* i2c0 */
+ .master_a_pinmux = {
+ .sda_reg = (unsigned long)MESON_I2C_EE_M0_SDA_GPIOZ_7_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .sda_mask = MESON_I2C_EE_M0_SDA_GPIOZ_7_MASK,
+#endif
+ .sda_bit = MESON_I2C_EE_M0_SDA_GPIOZ_7_BIT,
+
+ .scl_reg = (unsigned long)MESON_I2C_EE_M0_SCL_GPIOZ_8_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .scl_mask = MESON_I2C_EE_M0_SCL_GPIOZ_8_MASK,
+#endif
+ .scl_bit = MESON_I2C_EE_M0_SCL_GPIOZ_8_BIT,
+ },
+ },
+ {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_D,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ /* i2c3 */
+ .master_d_pinmux = {
+ .sda_reg = (unsigned long)MESON_I2C_EE_M3_SDA_GPIOA_14_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .sda_mask = MESON_I2C_EE_M3_SDA_GPIOA_14_MASK,
+#endif
+ .sda_bit = MESON_I2C_EE_M3_SDA_GPIOA_14_BIT,
+
+ .scl_reg = (unsigned long)MESON_I2C_EE_M3_SCL_GPIOA_15_REG,
+#ifdef CONFIG_SYS_I2C_AML_HAS_MASK
+ .scl_mask = MESON_I2C_EE_M3_SCL_GPIOA_15_MASK,
+#endif
+ .scl_bit = MESON_I2C_EE_M3_SCL_GPIOA_15_BIT,
+ },
+ },
+ /* sign of end */
+ {.master_i2c_speed=0},
+};
+
+static void board_i2c_init(void)
+{
+ extern void aml_i2c_set_ports(struct aml_i2c_platform *i2c_plat);
+ aml_i2c_set_ports(g_aml_i2c_plat);
+
+ udelay(10);
+}
+
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM 1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_USB_GPIO_PWR,
+ CONFIG_USB_GPIO_PWR_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_USB_GPIO_PWR);
+ return;
+ }
+
+ if (is_power_on) {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
+ } else {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+ .usb_phy2_pll_base_addr = {
+ CONFIG_USB_PHY_20,
+ CONFIG_USB_PHY_21,
+ }
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "fts",
+ .offset = 0,
+ .size = 1*SZ_1M,
+ },
+ {
+ .name = "factory",
+ .offset = 0,
+ .size = 8*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 220*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "cache",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xfffff << 12);
+ if (enable)
+ val |= 0x33333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~(0xf << 24);
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xf6000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+ CPU_GPU_Voltage_init();
+ panel_detect_init();
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+ //As NOT NEED other board init If USB BOOT MODE
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+ board_usb_pll_disable(&g_usb_config_GXL_skt);
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_SYS_I2C_AML
+ board_i2c_init();
+#endif
+
+#if 0
+ aml_pwm_cal_init(0);
+#endif//
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+
+ enable_backlight();
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ run_command("defenv", 0);
+ run_command("run detect_panel", 0);
+#if 0
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+#ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+#endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#endif
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 1 p321 v1
+ * hwid = 2 p321 v2
+ */
+ unsigned int hwid = 1;
+ char loc_name[64] = {0};
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+
+ switch (hwid) {
+ case 1:
+ strcpy(loc_name, "txl_p321_v1\0");
+ break;
+ case 2:
+ strcpy(loc_name, "txl_p321_v2\0");
+ break;
+ default:
+ strcpy(loc_name, "txl_p321_v1");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/g12a_newman_p0/lcd.c b/board/amlogic/g12a_newman_p0/lcd.c
new file mode 100755
index 0000000..59f2018
--- /dev/null
+++ b/board/amlogic/g12a_newman_p0/lcd.c
@@ -0,0 +1,466 @@
+/*
+ * AMLOGIC TV LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_6", /* panel rst */
+ "GPIOZ_8", /* panel power */
+ "invalid", /* ending flag */
+};
+
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd power */
+#if 1
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOA_10", /* BL_EN */
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,
+ /* custome */
+ Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,1,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_EXTERN,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_EXTERN,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOH_5
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+static unsigned char mipi_init_on_table[] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xff, 20,
+ 0x05, 1, 0x29,
+ 0xff, 20,
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table[] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xff, 10,
+ 0x05, 1, 0x10,
+ 0xff, 10,
+ 0xff,0xff, //ending flag
+};
+static unsigned char mipi_init_on_table_TV070WSM[] = {//table size < 100
+ 0xff, 10,
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
+ 0xff, 10, /* delay */
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TV070WSM[] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+static unsigned char mipi_init_on_table_P070ACB[] = {//table size < 100
+ 0xff, 10,
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
+ 0xff, 10, /* delay */
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_P070ACB[] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 2, /* ext_index if needed, must match ext_config_dtf.index;*/
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_clk_path = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0xff, //ending flag
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff,0xff, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 3,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = 1,
+ .name = "mipi_TV070WSM",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = 2,
+ .name = "mipi_P070ACB",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_EXTERN,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "i2c_lp8556",
+ .type = BL_EXTERN_I2C,
+ .i2c_addr = 0x2c,
+ .i2c_bus = BL_EXTERN_I2C_BUS_D,
+ .dim_min = 10,
+ .dim_max = 255,
+};
+#endif
+
+extern int i2c_set_bus_num(unsigned int busnum);
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_BL_EXTERN
+ i2c_set_bus_num(BL_EXTERN_I2C_BUS_D);
+#endif
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/g12a_newman_p0/pwm_table.c b/board/amlogic/g12a_newman_p0/pwm_table.c
new file mode 100755
index 0000000..18dc638
--- /dev/null
+++ b/board/amlogic/g12a_newman_p0/pwm_table.c
@@ -0,0 +1,71 @@
+#include <common.h>
+
+const int pwm_cal_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+const int pwm_cal_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
+int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
+
+
diff --git a/board/amlogic/g12a_skt_v1/Kconfig b/board/amlogic/g12a_skt_v1/Kconfig
new file mode 100644
index 0000000..491bb0f
--- /dev/null
+++ b/board/amlogic/g12a_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_G12A
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "g12a_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "g12a"
+
+config SYS_CONFIG_NAME
+ default "g12a_skt_v1"
+
+endif
diff --git a/board/amlogic/g12a_skt_v1/Makefile b/board/amlogic/g12a_skt_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/g12a_skt_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/g12a_skt_v1/aml-user-key.sig b/board/amlogic/g12a_skt_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/g12a_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/g12a_skt_v1/eth_setup.c b/board/amlogic/g12a_skt_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/g12a_skt_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/g12a_skt_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12a_skt_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..93b0335
--- /dev/null
+++ b/board/amlogic/g12a_skt_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,40 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 681},
+ { 0x1b0001, 691},
+ { 0x1a0002, 701},
+ { 0x190003, 711},
+ { 0x180004, 721},
+ { 0x170005, 731},
+ { 0x160006, 741},
+ { 0x150007, 751},
+ { 0x140008, 761},
+ { 0x130009, 772},
+ { 0x12000a, 782},
+ { 0x11000b, 792},
+ { 0x10000c, 802},
+ { 0x0f000d, 812},
+ { 0x0e000e, 822},
+ { 0x0d000f, 832},
+ { 0x0c0010, 842},
+ { 0x0b0011, 852},
+ { 0x0a0012, 862},
+ { 0x090013, 872},
+ { 0x080014, 882},
+ { 0x070015, 892},
+ { 0x060016, 902},
+ { 0x050017, 912},
+ { 0x040018, 922},
+ { 0x030019, 932},
+ { 0x02001a, 942},
+ { 0x01001b, 952},
+ { 0x00001c, 962}
+};
+
+#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12a_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12a_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..02773d1
--- /dev/null
+++ b/board/amlogic/g12a_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,153 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ /*set gpioH_8 low to power off vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+
+ /*set test_n low to power off vcck & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+
+ /*step down ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ /*step up ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+ /*set test_n low to power on vcck & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+ _udelay(100);
+
+ /*set gpioH_8 low to power on vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+ _udelay(10000);
+
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+
+ p->sources = val;
+ p->gpio_info_count = i;
+
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ unsigned char adc_key_cnt = 0;
+ init_remote();
+ saradc_enable();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ do {
+ #ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+ if (cec_power_on_check())
+ exit_reason = CEC_WAKEUP;
+ }
+ #endif
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/g12a_skt_v1/firmware/timing.c b/board/amlogic/g12a_skt_v1/firmware/timing.c
new file mode 100755
index 0000000..e99f6d9
--- /dev/null
+++ b/board/amlogic/g12a_skt_v1/firmware/timing.c
@@ -0,0 +1,779 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] = {
+{
+ /* g12a skt (u209) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1200, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 48,
+ .soc_data_drv_ohm_n = 48,
+ .soc_data_odt_ohm_p = 48,//60,//60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 48,//60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ //.ac_trace_delay = {32,42,42,42,32,32,42,42,42,42},
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function={0x0,0x0}, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .read_dq_bit_delay={
+6 ,
+4 ,
+7 ,
+8 ,
+21 ,
+23 ,
+23 ,
+26 ,
+0 ,
+8 ,
+17 ,
+21 ,
+12 ,
+16 ,
+21 ,
+27 ,
+23 ,
+0 ,
+7 ,
+6 ,
+6 ,
+8 ,
+27 ,
+21 ,
+19 ,
+19 ,
+0 ,
+9 ,
+10 ,
+12 ,
+11 ,
+20 ,
+22 ,
+23 ,
+20 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+0 ,
+},
+ .read_dqs_delay={
+0x83,
+0x83,
+0x83,
+0x82,
+0x82,
+0x83,
+0x83,
+0x83,
+0x0 ,
+0x0 ,
+0x0 ,
+0x0 ,
+0x0 ,
+0x0 ,
+0x0 ,
+0x0 ,
+ },//DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS|DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ
+ .dq_dqs_delay_flag = DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS,
+ .bitTimeControl_2d=6,
+},
+
+{
+ /* g12a skt (u209) ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,//4096,
+ .dram_cs1_size_MB = 0xffff,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0c0c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) lpddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,//48,
+ .ac_drv_ohm = 40,//48,
+
+ /*
+ .soc_data_drv_ohm_p = 40,//30,//30,
+ .soc_data_drv_ohm_n = 40,//30,//30,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,//40,//60,// 120,//120,
+ .dram_data_drv_ohm = 40,// 48, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,// 48,//48,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 0,///1, 1/3vddq 0 2/5 vddq
+ */
+ ///*
+ .soc_data_drv_ohm_p = 48,//30,//30,
+ .soc_data_drv_ohm_n = 48,//30,//30,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 48,//40,//60,// 120,//120,
+ .dram_data_drv_ohm = 48,// 48, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 48,// 48,//48,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ //*/
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 14,13,12,15,8,9,11,10, 20,21,22,23,16,17,19,18, 24,25,28,26,31,30,27,29},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+ .bitTimeControl_2d=7,
+ //.slt_test_function = { DMC_TEST_SLT_SCAN_FREQUENCY|DMC_TEST_SLT_OFFSET_DELAY , 5},
+ .write_dq_bit_delay={
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+0x8002 ,
+} ,
+ .dq_dqs_delay_flag = DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ,
+ //.dq_dqs_delay_flag = DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS|DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ|
+ //DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS|DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ
+},
+{
+ /* g12a Y2 dongle */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .bitTimeControl_2d=7,
+},
+{
+ /* lpddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR3,
+ .DRAMFreq = {600, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,//0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x00c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 30, //
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x3ff,//0x253,
+ .soc_ac_slew_rate = 0x3ff,//0x253,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 800,//200,
+ .vref_receiver_permil = 700,//875, //700 for drv 40 odt 60 is better ,why?
+ .vref_dram_permil = 500,//875,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {0x10,0x0,0x10-6,0x10-6,0x10-6,0x0,0x0,0x0,0x0,0x0},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 29 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ),
+ [4] = ( 31| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8},
+ .ddr_lpddr34_dq_remap = {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24},
+ //{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6},
+ .dram_rtt_nom_wr_park = {00,00},
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+
+#ifdef CONFIG_AML_SUPPORT_TLV
+ .nCFGTAddr = AML_BL2_TMASTER_DDR_ADDR,
+#endif
+
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0000001c
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE PWM table */
+#if (VDDEE_VAL == 680)
+ #define VDDEE_VAL_REG 0x001c0000
+#elif (VDDEE_VAL == 690)
+ #define VDDEE_VAL_REG 0x001b0001
+#elif (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x001a0002
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x00190003
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x00180004
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0x00170005
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0x00160006
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0x00150007
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0x00140008
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0x00130009
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0x0012000a
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x0011000b
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x0010000c
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x000f000d
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x000e000e
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x000d000f
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x000c0010
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x000b0011
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x000a0012
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x00090013
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x00080014
+#elif (VDDEE_VAL == 890)
+ #define VDDEE_VAL_REG 0x00070015
+#elif (VDDEE_VAL == 900)
+ #define VDDEE_VAL_REG 0x00060016
+#elif (VDDEE_VAL == 910)
+ #define VDDEE_VAL_REG 0x00050017
+#elif (VDDEE_VAL == 920)
+ #define VDDEE_VAL_REG 0x00040018
+#elif (VDDEE_VAL == 930)
+ #define VDDEE_VAL_REG 0x00030019
+#elif (VDDEE_VAL == 940)
+ #define VDDEE_VAL_REG 0x0002001a
+#elif (VDDEE_VAL == 950)
+ #define VDDEE_VAL_REG 0x0001001b
+#elif (VDDEE_VAL == 960)
+ #define VDDEE_VAL_REG 0x0000001c
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ /* eg: PWM init */
+
+ /* PWM_AO_D */
+ /* VCCK_VAL_REG: check PWM table */
+ {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
+ /* PWM_AO_B */
+ /* VDDEE_VAL_REG: check PWM table */
+ {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable 5V_EN */
+ {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Enable VCCK */
+ {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 31), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/g12a_skt_v1/g12a_skt_v1.c b/board/amlogic/g12a_skt_v1/g12a_skt_v1.c
new file mode 100644
index 0000000..a1b438f
--- /dev/null
+++ b/board/amlogic/g12a_skt_v1/g12a_skt_v1.c
@@ -0,0 +1,770 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#ifdef CONFIG_AML_SPIFC
+#include <amlogic/spifc.h>
+#endif
+#ifdef CONFIG_AML_SPICC
+#include <amlogic/spicc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+#ifdef ETHERNET_INTERNAL_PHY
+void internalPhyConfig(struct phy_device *phydev)
+{
+}
+
+static int dwmac_meson_cfg_pll(void)
+{
+ writel(0x39C0040A, P_ETH_PLL_CTL0);
+ writel(0x927E0000, P_ETH_PLL_CTL1);
+ writel(0xAC5F49E5, P_ETH_PLL_CTL2);
+ writel(0x00000000, P_ETH_PLL_CTL3);
+ udelay(200);
+ writel(0x19C0040A, P_ETH_PLL_CTL0);
+ return 0;
+}
+
+static int dwmac_meson_cfg_analog(void)
+{
+ /*Analog*/
+ writel(0x20200000, P_ETH_PLL_CTL5);
+ writel(0x0000c002, P_ETH_PLL_CTL6);
+ writel(0x00000023, P_ETH_PLL_CTL7);
+
+ return 0;
+}
+
+static int dwmac_meson_cfg_ctrl(void)
+{
+ /*config phyid should between a 0~0xffffffff*/
+ /*please don't use 44000181, this has been used by internal phy*/
+ writel(0x33000180, P_ETH_PHY_CNTL0);
+
+ /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
+ writel(0x260, P_ETH_PHY_CNTL2);
+
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ writel(0x34043, P_ETH_PHY_CNTL1);
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ return 0;
+}
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 1;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 9;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ dwmac_meson_cfg_pll();
+ dwmac_meson_cfg_analog();
+ dwmac_meson_cfg_ctrl();
+
+ /* eth core clock */
+ setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
+ /* eth phy clock */
+ setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
+
+ /* eth phy pll, clk50m */
+ setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+
+static int dwmac_meson_cfg_drive_strength(void)
+{
+ writel(0xaaaaaaa5, P_PAD_DS_REG4A);
+ return 0;
+}
+
+static void setup_net_chip_ext(void)
+{
+ eth_aml_reg0_t eth_reg0;
+ writel(0x11111111, P_PERIPHS_PIN_MUX_6);
+ writel(0x111111, P_PERIPHS_PIN_MUX_7);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_ETHERNET_NONE
+ return 0;
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+ dwmac_meson_cfg_drive_strength();
+ setup_net_chip_ext();
+#endif
+#ifdef ETHERNET_INTERNAL_PHY
+ setup_net_chip();
+#endif
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ /* check card detect */
+ clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM 1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_USB_GPIO_PWR,
+ CONFIG_USB_GPIO_PWR_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_USB_GPIO_PWR);
+ return;
+ }
+
+ if (is_power_on) {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
+ } else {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+ .usb_phy2_pll_base_addr = {
+ CONFIG_USB_PHY_20,
+ CONFIG_USB_PHY_21,
+ }
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 280*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xfffff << 12);
+ if (enable)
+ val |= 0x33333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~(0xf << 24);
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xf6000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+#ifdef CONFIG_AML_SPICC
+/* generic config in arch gpio/clock.c */
+extern int spicc1_clk_set_rate(int rate);
+extern int spicc1_clk_enable(bool enable);
+extern int spicc1_pinctrl_enable(bool enable);
+
+static const struct spicc_platdata spicc1_platdata = {
+ .compatible = "amlogic,meson-g12a-spicc",
+ .reg = (void __iomem *)0xffd15000,
+ .clk_rate = 666666666,
+ .clk_set_rate = spicc1_clk_set_rate,
+ .clk_enable = spicc1_clk_enable,
+ .pinctrl_enable = spicc1_pinctrl_enable,
+ /* case one slave without cs: {"no_cs", 0} */
+ .cs_gpio_names = {"GPIOH_6", 0},
+};
+
+U_BOOT_DEVICE(spicc1) = {
+ .name = "spicc",
+ .platdata = &spicc1_platdata,
+};
+#endif /* CONFIG_AML_SPICC */
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+ //As NOT NEED other board init If USB BOOT MODE
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+ board_usb_pll_disable(&g_usb_config_GXL_skt);
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#if 0
+ aml_pwm_cal_init(0);
+#endif//
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+/* set dts props */
+void aml_config_dtb(void)
+{
+ cpu_id_t cpuid = get_cpu_id();
+
+ run_command("fdt address $dtb_mem_addr", 0);
+ printf("%s %d\n", __func__, __LINE__);
+ if (cpuid.chip_rev == 0xA) {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /emmc/emmc co_phase <0x2>", 0);
+ run_command("fdt set /sdio status okay", 0);
+ run_command("fdt set /sd1 status okay", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux1 drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength <2>", 0);
+ run_command("fdt set /pinctrl@ff634480/sdio_all_pins/mux drive-strength <1>", 0);
+ /* debug */
+ run_command("fdt print /emmc/emmc co_phase", 0);
+ run_command("fdt print /sdio status", 0);
+ run_command("fdt print /sd1 status ", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux1 drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sdio_all_pins/mux drive-strength", 0);
+ } else {
+
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /emmc/emmc co_phase <0x3>", 0);
+ run_command("fdt set /sdio status disabled", 0);
+ run_command("fdt set /sd2 status okay", 0);
+ /* debug */
+ run_command("fdt print /emmc/emmc co_phase", 0);
+ run_command("fdt print /sdio status", 0);
+ run_command("fdt print /sd2 status", 0);
+ }
+
+ return;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+#ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+#endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ /**/
+ aml_config_dtb();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 1 p321 v1
+ * hwid = 2 p321 v2
+ */
+ unsigned int hwid = 1;
+ char loc_name[64] = {0};
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+
+ switch (hwid) {
+ case 1:
+ strcpy(loc_name, "txl_p321_v1\0");
+ break;
+ case 2:
+ strcpy(loc_name, "txl_p321_v2\0");
+ break;
+ default:
+ strcpy(loc_name, "txl_p321_v1");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/g12a_skt_v1/lcd.c b/board/amlogic/g12a_skt_v1/lcd.c
new file mode 100755
index 0000000..8005199
--- /dev/null
+++ b/board/amlogic/g12a_skt_v1/lcd.c
@@ -0,0 +1,576 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+#ifdef CONFIG_AML_LCD_EXTERN
+#include "lcd_extern.h"
+#endif
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_9", /* panel rst */
+ "GPIOZ_8", /* panel power */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+#if 0
+ {LCD_POWER_TYPE_CPU, 0,1,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TL050FHV02CT[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TL050FHV02CT[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TL070WSH27[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TL070WSH27[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,10,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_4", /* BL_EN */
+ "GPIOH_5", /* BL_PWM */
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,1,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TL050FHV02CT*/
+ "lcd_3",LCD_MIPI,8,
+ /* basic timing */
+ 1080,1920,1125,2100,5,30,0,44,108,0,
+ /* clk_attr */
+ 0,0,1,118125000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,960,0,1,0,2,1,0,Rsv_val,3,
+ /* power step */
+ lcd_power_on_step_TL050FHV02CT, lcd_power_off_step_TL050FHV02CT,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TL070WSH27*/
+ "lcd_4",LCD_MIPI,8,
+ /* basic timing */
+ 1024,600,1250,630,80,100,0,5,20,0,
+ /* clk_attr */
+ 0,0,1,47250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,300,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_TL070WSH27, lcd_power_off_step_TL070WSH27,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOH_5
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xff, 20,
+ 0x05, 1, 0x29,
+ 0xff, 20,
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xff, 10,
+ 0x05, 1, 0x10,
+ 0xff, 10,
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 10,
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
+ 0xff, 100, /* delay */
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 10,
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_TL050FHV02CT[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff,0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TL050FHV02CT[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_TL070WSH27[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xff, 100,
+ 0x05, 1, 0x29,
+ 0xff, 20,
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TL070WSH27[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xff, 100,
+ 0x05, 1, 0x10,
+ 0xff, 10,
+ 0xff, 0xff, //ending flag
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_clk_path = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0xff, //ending flag
+};
+
+static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff,0xff, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 4,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .cmd_size = 9,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 1,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_TV070WSM,
+ .table_init_off = ext_init_off_table_TV070WSM,
+ },
+ {
+ .index = 2,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_P070ACB,
+ .table_init_off = ext_init_off_table_P070ACB,
+ },
+ {
+ .index = 3,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_TL050FHV02CT,
+ .table_init_off = ext_init_off_table_TL050FHV02CT,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "none",
+ .type = BL_EXTERN_MAX,
+ .i2c_addr = 0xff,
+ .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+ .dim_min = 10,
+ .dim_max = 255,
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 3:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TL050FHV02CT;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TL050FHV02CT;
+ break;
+ case 4:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TL070WSH27;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TL070WSH27;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/g12a_skt_v1/lcd_extern.h b/board/amlogic/g12a_skt_v1/lcd_extern.h
new file mode 100644
index 0000000..b5bdb7a
--- /dev/null
+++ b/board/amlogic/g12a_skt_v1/lcd_extern.h
@@ -0,0 +1,389 @@
+/*
+ * board/amlogic/g12a_u200_v1/lcd_extern.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DFT_LCD_EXTERN_H_
+#define _DFT_LCD_EXTERN_H_
+
+static unsigned char ext_init_on_table_TV070WSM[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 100, /* delay */
+ 0x15, 2, 0x62, 0x01,
+ 0x39, 5, 0xff, 0xaa, 0x55, 0x25, 0x01,
+ 0x15, 2, 0xfc, 0x08,
+ 0xff, 1, /* delay */
+ 0x15, 2, 0xfc, 0x00,
+ 0x39, 5, 0xff, 0xaa, 0x55, 0x25, 0x00,
+ 0xff, 20, /* delay */
+ 0x39, 6, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00,
+ 0x39, 3, 0xb1, 0x68, 0x41,
+ 0x15, 2, 0xb5, 0x88,
+ 0x15, 2, 0xb6, 0x0f,
+ 0x39, 5, 0xb8, 0x01, 0x01, 0x12, 0x01,
+ 0x39, 3, 0xbb, 0x11, 0x11,
+ 0x39, 3, 0xbc, 0x05, 0x05,
+ 0x15, 2, 0xc7, 0x03,
+ 0x39, 6, 0xbd, 0x03, 0x02, 0x19, 0x17, 0x00,
+ 0x15, 2, 0xc8, 0x80,
+ 0x39, 6, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x01,
+ 0x39, 3, 0xB2, 0x01, 0x01,
+ 0x39, 3, 0xB3, 0x28, 0x28,
+ 0x39, 3, 0xB4, 0x14, 0x14,
+ 0x39, 3, 0xB8, 0x05, 0x05,
+ 0x39, 3, 0xB9, 0x45, 0x45,
+ 0x39, 3, 0xBA, 0x25, 0x25,
+ 0x39, 3, 0xBC, 0x88, 0x00,
+ 0x39, 3, 0xBD, 0x88, 0x00,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02,
+ 0x15, 2, 0xEE, 0x00,
+ 0x39, 17, 0xB0, 0x00, 0x4B, 0x00, 0x5C, 0x00, 0x79, 0x00, 0x94, 0x00, 0xA6, 0x00, 0xD8, 0x00, 0xF2, 0x01, 0x19,
+ 0x39, 17, 0xB1, 0x01, 0x39, 0x01, 0x77, 0x01, 0xA2, 0x01, 0xF2, 0x02, 0x32, 0x02, 0x34, 0x02, 0x6D, 0x02, 0xA2,
+ 0x39, 17, 0xB2, 0x02, 0xC7, 0x02, 0xF2, 0x03, 0x18, 0x03, 0x43, 0x03, 0x65, 0x03, 0x86, 0x03, 0x8F, 0x03, 0x94,
+ 0x39, 5, 0xB3, 0x03, 0x96, 0x03, 0x98,
+ 0x39, 17, 0xB4, 0x00, 0x84, 0x00, 0x91, 0x00, 0xA4, 0x00, 0xB6, 0x00, 0xCA, 0x00, 0xE9, 0x01, 0x02, 0x01, 0x2A,
+ 0x39, 17, 0xB5, 0x01, 0x49, 0x01, 0x82, 0x01, 0xAF, 0x01, 0xF7, 0x02, 0x36, 0x02, 0x38, 0x02, 0x70, 0x02, 0xA6,
+ 0x39, 17, 0xB6, 0x02, 0xC8, 0x02, 0xF5, 0x03, 0x1A, 0x03, 0x43, 0x03, 0x62, 0x03, 0x82, 0x03, 0x8F, 0x03, 0x94,
+ 0x39, 5, 0xB7, 0x03, 0x96, 0x03, 0x98,
+ 0x39, 17, 0xB8, 0x01, 0x22, 0x01, 0x27, 0x01, 0x2E, 0x01, 0x38, 0x01, 0x40, 0x01, 0x53, 0x01, 0x60, 0x01, 0x7B,
+ 0x39, 17, 0xB9, 0x01, 0x8C, 0x01, 0xB5, 0x01, 0xD3, 0x02, 0x11, 0x02, 0x49, 0x02, 0x4A, 0x02, 0x7F, 0x02, 0xB1,
+ 0x39, 17, 0xBA, 0x02, 0xD1, 0x03, 0x00, 0x03, 0x22, 0x03, 0x49, 0x03, 0x60, 0x03, 0x7A, 0x03, 0x8B, 0x03, 0x8F,
+ 0x39, 5, 0xBB, 0x03, 0x93, 0x03, 0x9A,
+ 0x39, 17, 0xBC, 0x00, 0x37, 0x00, 0x48, 0x00, 0x65, 0x00, 0x80, 0x00, 0x92, 0x00, 0xC4, 0x00, 0xDE, 0x01, 0x05,
+ 0x39, 17, 0xBD, 0x01, 0x31, 0x01, 0x6F, 0x01, 0x9E, 0x01, 0xEE, 0x02, 0x32, 0x02, 0x34, 0x02, 0x71, 0x02, 0xA7,
+ 0x39, 17, 0xBE, 0x02, 0xD3, 0x02, 0xFE, 0x03, 0x24, 0x03, 0x4F, 0x03, 0x71, 0x03, 0x92, 0x03, 0x9B, 0x03, 0xA0,
+ 0x39, 5, 0xBF, 0x03, 0xA6, 0x03, 0xA8,
+ 0x39, 17, 0xC0, 0x00, 0x70, 0x00, 0x7D, 0x00, 0x90, 0x00, 0xA4, 0x00, 0xB6, 0x00, 0xD5, 0x00, 0xEE, 0x01, 0x16,
+ 0x39, 17, 0xC1, 0x01, 0x41, 0x01, 0x7A, 0x01, 0xAB, 0x01, 0xF3, 0x02, 0x36, 0x02, 0x38, 0x02, 0x74, 0x02, 0xAA,
+ 0x39, 17, 0xC2, 0x02, 0xD4, 0x03, 0x01, 0x03, 0x26, 0x03, 0x4F, 0x03, 0x6E, 0x03, 0x8E, 0x03, 0x9B, 0x03, 0xA0,
+ 0x39, 5, 0xC3, 0x03, 0xA6, 0x03, 0xA8,
+ 0x39, 17, 0xC4, 0x01, 0x0E, 0x01, 0x13, 0x01, 0x1A, 0x01, 0x24, 0x01, 0x2C, 0x01, 0x3F, 0x01, 0x4C, 0x01, 0x67,
+ 0x39, 17, 0xC5, 0x01, 0x84, 0x01, 0xAD, 0x01, 0xCF, 0x02, 0x0D, 0x02, 0x49, 0x02, 0x4A, 0x02, 0x83, 0x02, 0xB5,
+ 0x39, 17, 0xC6, 0x02, 0xDD, 0x03, 0x0C, 0x03, 0x2E, 0x03, 0x55, 0x03, 0x6B, 0x03, 0x86, 0x03, 0x97, 0x03, 0x9B,
+ 0x39, 5, 0xC7, 0x03, 0xA1, 0x03, 0xA8,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x04,
+ 0x39, 6, 0xB1, 0x03, 0x02, 0x02, 0x02, 0x00,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06,
+ 0x39, 3, 0xB0, 0x11, 0x11,
+ 0x39, 3, 0xB1, 0x13, 0x13,
+ 0x39, 3, 0xB2, 0x03, 0x03,
+ 0x39, 3, 0xB3, 0x34, 0x34,
+ 0x39, 3, 0xB4, 0x34, 0x34,
+ 0x39, 3, 0xB5, 0x34, 0x34,
+ 0x39, 3, 0xB6, 0x34, 0x34,
+ 0x39, 3, 0xB7, 0x34, 0x34,
+ 0x39, 3, 0xB8, 0x34, 0x34,
+ 0x39, 3, 0xB9, 0x34, 0x34,
+ 0x39, 3, 0xBA, 0x34, 0x34,
+ 0x39, 3, 0xBB, 0x34, 0x34,
+ 0x39, 3, 0xBC, 0x34, 0x34,
+ 0x39, 3, 0xBD, 0x34, 0x34,
+ 0x39, 3, 0xBE, 0x34, 0x34,
+ 0x39, 3, 0xBF, 0x34, 0x34,
+ 0x39, 3, 0xC0, 0x34, 0x34,
+ 0x39, 3, 0xC1, 0x02, 0x02,
+ 0x39, 3, 0xC2, 0x12, 0x12,
+ 0x39, 3, 0xC3, 0x10, 0x10,
+ 0x39, 3, 0xE5, 0x34, 0x34,
+ 0x39, 6, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x39, 6, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05,
+ 0x15, 2, 0xC0, 0x03,
+ 0x15, 2, 0xC1, 0x02,
+ 0x39, 3, 0xC8, 0x01, 0x20,
+ 0x15, 2, 0xE5, 0x03,
+ 0x15, 2, 0xE6, 0x03,
+ 0x15, 2, 0xE7, 0x03,
+ 0x15, 2, 0xE8, 0x03,
+ 0x15, 2, 0xE9, 0x03,
+ 0x39, 5, 0xD1, 0x03, 0x00, 0x3D, 0x00,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03,
+ 0x39, 3, 0xB0, 0x11, 0x00,
+ 0x39, 3, 0xB1, 0x11, 0x00,
+ 0x39, 6, 0xB2, 0x03, 0x00, 0x00, 0x00, 0x00,
+ 0x39, 6, 0xB3, 0x03, 0x00, 0x00, 0x00, 0x00,
+ 0x39, 6, 0xBA, 0x31, 0x00, 0x00, 0x00, 0x00,
+ 0x15, 2, 0x35, 0x00,
+ 0x15, 2, 0x51, 0xFF,
+ 0x15, 2, 0x53, 0x2C,
+ 0x15, 2, 0x55, 0x03,
+ 0x05, 1, 0x11,
+ 0xff, 120, /* delay 120ms */
+ 0x05, 1, 0x29,
+ 0xff, 0xff, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_TV070WSM[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xff, 30, /* delay 30ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xff, 10,
+ 0xff, 0xff, /* ending flag */
+};
+
+static unsigned char ext_init_on_table_P070ACB[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 100, /* delay */
+ 0x15, 2, 0x62, 0x01,
+ 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x01,
+ 0x23, 2, 0xFC, 0x08,
+ 0xFF, 1, /* delay(ms) */
+ 0x23, 2, 0xFC, 0x00,
+
+ 0xFF, 1, /* delay(ms) */
+ 0x23, 2, 0x6F, 0x21,
+ 0x23, 2, 0xF7, 0x01,
+ 0xFF, 1, /* delay(ms) */
+ 0x23, 2, 0x6F, 0x21,
+ 0x23, 2, 0xF7, 0x00,
+ 0xFF, 1, /* delay(ms) */
+
+ 0x23, 2, 0x6F, 0x1A,
+ 0x23, 2, 0xF7, 0x05,
+ 0xFF, 1, /* delay(ms) */
+
+ 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x00,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00,
+ 0x29, 3, 0xB1, 0x68, 0x41,
+ 0x23, 2, 0xB5, 0x88,
+ 0x29, 6, 0xBD, 0x02, 0xB0, 0x0C, 0x14, 0x00,
+ 0x23, 2, 0xC8, 0x80,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01,
+ 0x29, 3, 0xB3, 0x2D, 0x2D,
+ 0x29, 3, 0xB4, 0x19, 0x19,
+ 0x23, 2, 0xB5, 0x06,
+
+ 0x29, 3, 0xB9, 0x36, 0x36,
+ 0x29, 3, 0xBA, 0x26, 0x26,
+ 0x29, 3, 0xBC, 0xA8, 0x01,
+ 0x29, 3, 0xBD, 0xAB, 0x01,
+ 0x23, 2, 0xC0, 0x0C,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02,
+ 0x23, 2, 0xEE, 0x02,
+ 0x29, 7, 0xB0, 0x00, 0x50, 0x00, 0x52, 0x00, 0x73,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xB0, 0x00, 0x8F, 0x00, 0xA5, 0x00, 0xCA,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xB0, 0x00, 0xEA, 0x01, 0x1B,
+ 0x29, 7, 0xB1, 0x01, 0x42, 0x01, 0x82, 0x01, 0xB3,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xB1, 0x02, 0x00, 0x02, 0x41, 0x02, 0x42,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xB1, 0x02, 0x78, 0x02, 0xB5,
+ 0x29, 7, 0xB2, 0x02, 0xDA, 0x03, 0x12, 0x03, 0x3A,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xB2, 0x03, 0x6E, 0x03, 0x8D, 0x03, 0xB1,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xB2, 0x03, 0xCA, 0x03, 0xE8,
+ 0x29, 5, 0xB3, 0x03, 0xF4, 0x03, 0xFF,
+
+ 0x29, 7, 0xBC, 0x00, 0x05, 0x00, 0x52, 0x00, 0x73,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xBC, 0x00, 0x8F, 0x00, 0xA5, 0x00, 0xCA,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xBC, 0x00, 0xEA, 0x01, 0x1B,
+ 0x29, 7, 0xBD, 0x01, 0x42, 0x01, 0x82, 0x01, 0xB3,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xBD, 0x02, 0x00, 0x02, 0x41, 0x02, 0x42,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xBD, 0x02, 0x78, 0x02, 0xB5,
+ 0x29, 7, 0xBE, 0x02, 0xDA, 0x03, 0x12, 0x03, 0x3A,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xBE, 0x03, 0x6E, 0x03, 0x8D, 0x03, 0xB1,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xBE, 0x03, 0xCA, 0x03, 0xE8,
+ 0x29, 5, 0xBF, 0x03, 0xF4, 0x03, 0xFF,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03,
+ 0x29, 6, 0xB2, 0x05, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xB6, 0x05, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xB7, 0x05, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xBA, 0x57, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xBB, 0x57, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 5, 0xC0, 0x00, 0x34, 0x00, 0x00,
+ 0x29, 5, 0xC1, 0x00, 0x00, 0x34, 0x00,
+ 0x23, 2, 0xC4, 0x40,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05,
+ 0x29, 3, 0xB0, 0x17, 0x06,
+ 0x29, 3, 0xB1, 0x17, 0x06,
+ 0x29, 3, 0xB2, 0x17, 0x06,
+ 0x29, 3, 0xB3, 0x17, 0x06,
+ 0x29, 3, 0xB4, 0x17, 0x06,
+
+ 0x29, 6, 0xBD, 0x03, 0x01, 0x03, 0x03, 0x01,
+ 0x23, 2, 0xC0, 0x05,
+ 0x23, 2, 0xC4, 0x82,
+ 0x23, 2, 0xC5, 0xA2,
+ 0x29, 3, 0xC8, 0x03, 0x30,
+ 0x29, 3, 0xC9, 0x03, 0x31,
+ 0x29, 4, 0xCC, 0x00, 0x00, 0x3C,
+ 0x29, 4, 0xCD, 0x00, 0x00, 0x3C,
+ 0x29, 6, 0xD1, 0x00, 0x44, 0x09, 0x00, 0x00,
+ 0x29, 6, 0xD2, 0x00, 0x04, 0x0B, 0x00, 0x00,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06,
+ 0x29, 3, 0xB0, 0x0B, 0x2D,
+ 0x29, 3, 0xB1, 0x2D, 0x09,
+ 0x29, 3, 0xB2, 0x2A, 0x29,
+ 0x29, 3, 0xB3, 0x34, 0x1B,
+ 0x29, 3, 0xB4, 0x19, 0x17,
+ 0x29, 3, 0xB5, 0x15, 0x13,
+ 0x29, 3, 0xB6, 0x11, 0x01,
+ 0x29, 3, 0xB7, 0x34, 0x34,
+ 0x29, 3, 0xB8, 0x34, 0x2D,
+ 0x29, 3, 0xB9, 0x2D, 0x34,
+ 0x29, 3, 0xBA, 0x2D, 0x2D,
+ 0x29, 3, 0xBB, 0x34, 0x34,
+ 0x29, 3, 0xBC, 0x34, 0x34,
+ 0x29, 3, 0xBD, 0x00, 0x10,
+ 0x29, 3, 0xBE, 0x12, 0x14,
+ 0x29, 3, 0xBF, 0x16, 0x18,
+
+ 0x29, 3, 0xC0, 0x1A, 0x34,
+ 0x29, 3, 0xC1, 0x29, 0x2A,
+ 0x29, 3, 0xC2, 0x08, 0x2D,
+ 0x29, 3, 0xC3, 0x2D, 0x0A,
+ 0x29, 3, 0xC4, 0x0A, 0x2D,
+ 0x29, 3, 0xC5, 0x2D, 0x00,
+ 0x29, 3, 0xC6, 0x2A, 0x29,
+ 0x29, 3, 0xC7, 0x34, 0x14,
+ 0x29, 3, 0xC8, 0x16, 0x18,
+ 0x29, 3, 0xC9, 0x1A, 0x10,
+ 0x29, 3, 0xCA, 0x12, 0x08,
+ 0x29, 3, 0xCB, 0x34, 0x34,
+ 0x29, 3, 0xCC, 0x34, 0x2D,
+ 0x29, 3, 0xCD, 0x2D, 0x34,
+ 0x29, 3, 0xCE, 0x2D, 0x2D,
+ 0x29, 3, 0xCF, 0x34, 0x34,
+
+ 0x29, 3, 0xD0, 0x34, 0x34,
+ 0x29, 3, 0xD1, 0x09, 0x13,
+ 0x29, 3, 0xD2, 0x11, 0x1B,
+ 0x29, 3, 0xD3, 0x19, 0x17,
+ 0x29, 3, 0xD4, 0x15, 0x34,
+ 0x29, 3, 0xD5, 0x29, 0x2A,
+ 0x29, 3, 0xD6, 0x01, 0x2D,
+ 0x29, 3, 0xD7, 0x2D, 0x0B,
+ 0x29, 6, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ 0x29, 3, 0xE5, 0x34, 0x34,
+ 0x29, 3, 0xE6, 0x34, 0x34,
+ 0x23, 2, 0xE7, 0x00,
+ 0x29, 3, 0xE8, 0x34, 0x34,
+ 0x29, 3, 0xE9, 0x34, 0x34,
+ 0x23, 2, 0xEA, 0x00,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x00, 0x00,
+
+ 0x13, 1, 0x35,
+ 0x13, 1, 0x11,
+ 0xFF, 120, /* delay(ms) */
+ 0x13, 1, 0x29,
+ 0xFF, 20, /* delay(ms) */
+ 0xFF, 0xFF, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_P070ACB[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xFF, 10, /* delay 10ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xFF, 150, /* delay 150ms */
+ 0xFF, 0xFF, /* ending flag */
+};
+
+static unsigned char ext_init_on_table_TL050FHV02CT[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03,
+ 0x29, 10, 0x90, 0x03, 0x14, 0x09, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00,
+ 0x29, 10, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 12, 0x92, 0x40, 0x0B, 0x0C, 0x0D, 0x0E, 0x00, 0x38, 0x00, 0x10, 0x03, 0x04,
+ 0x29, 9, 0x94, 0x00, 0x08, 0x0B, 0x03, 0xD2, 0x03, 0xD3, 0x0C,
+ 0x29, 17, 0x95, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 3, 0x99, 0x00, 0x00,
+ 0x29, 12, 0x9A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 7, 0x9B, 0x01, 0x38, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 3, 0x9C, 0x00, 0x00,
+ 0x29, 9, 0x9D, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00,
+ 0x29, 3, 0x9E, 0x00, 0x00,
+ 0x29, 11, 0xA0, 0x9F, 0x1F, 0x08, 0x1F, 0x0A, 0x1F, 0x00, 0x1F, 0x14, 0x1F,
+ 0x29, 11, 0xA1, 0x15, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x29, 11, 0xA2, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x29, 11, 0xA4, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x29, 11, 0xA5, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x15,
+ 0x29, 11, 0xA6, 0x1F, 0x14, 0x1F, 0x01, 0x1F, 0x0B, 0x1F, 0x09, 0x1F, 0x1F,
+ 0x29, 11, 0xA7, 0x1F, 0x1F, 0x0B, 0x1F, 0x09, 0x1F, 0x01, 0x1F, 0x15, 0x1F,
+ 0x29, 11, 0xA8, 0x14, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x29, 11, 0xA9, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x29, 11, 0xAB, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x29, 11, 0xAC, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x14,
+ 0x29, 11, 0xAD, 0x1F, 0x15, 0x1F, 0x00, 0x1F, 0x08, 0x1F, 0x0A, 0x1F, 0x1F,
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00,
+ 0x29, 4, 0xBC, 0x00, 0x00, 0x00,
+ 0x29, 5, 0xB8, 0x01, 0xAF, 0x8F, 0x8F,
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01,
+ 0x29, 17, 0xD1, 0x00, 0x00, 0x00, 0x09, 0x00, 0x1F, 0x00, 0x30, 0x00, 0x3F, 0x00, 0x5D, 0x00, 0x79, 0x00, 0xA7,
+ 0x29, 17, 0xD2, 0x00, 0xCF, 0x01, 0x12, 0x01, 0x49, 0x01, 0xA1, 0x01, 0xEB, 0x01, 0xED, 0x02, 0x2F, 0x02, 0x74,
+ 0x29, 17, 0xD3, 0x02, 0x9F, 0x02, 0xD5, 0x02, 0xFB, 0x03, 0x2C, 0x03, 0x4B, 0x03, 0x73, 0x03, 0x8C, 0x03, 0xA5,
+ 0x29, 5, 0xD4, 0x03, 0xC5, 0x03, 0xFF,
+ 0x29, 17, 0xD5, 0x00, 0x00, 0x00, 0x09, 0x00, 0x1F, 0x00, 0x30, 0x00, 0x3F, 0x00, 0x5D, 0x00, 0x79, 0x00, 0xA7,
+ 0x29, 17, 0xD6, 0x00, 0xCF, 0x01, 0x12, 0x01, 0x49, 0x01, 0xA1, 0x01, 0xEB, 0x01, 0xED, 0x02, 0x2F, 0x02, 0x74,
+ 0x29, 17, 0xD7, 0x02, 0x9F, 0x02, 0xD5, 0x02, 0xFB, 0x03, 0x2C, 0x03, 0x4B, 0x03, 0x73, 0x03, 0x8C, 0x03, 0xA5,
+ 0x29, 5, 0xD8, 0x03, 0xC5, 0x03, 0xFF,
+ 0x29, 17, 0xD9, 0x00, 0x00, 0x00, 0x09, 0x00, 0x1F, 0x00, 0x30, 0x00, 0x3F, 0x00, 0x5D, 0x00, 0x79, 0x00, 0xA7,
+ 0x29, 17, 0xDD, 0x00, 0xCF, 0x01, 0x12, 0x01, 0x49, 0x01, 0xA1, 0x01, 0xEB, 0x01, 0xED, 0x02, 0x2F, 0x02, 0x74,
+ 0x29, 17, 0xDE, 0x02, 0x9F, 0x02, 0xD5, 0x02, 0xFB, 0x03, 0x2C, 0x03, 0x4B, 0x03, 0x73, 0x03, 0x8C, 0x03, 0xA5,
+ 0x29, 5, 0xDF, 0x03, 0xC5, 0x03, 0xFF,
+ 0x29, 17, 0xE0, 0x00, 0x00, 0x00, 0x09, 0x00, 0x1F, 0x00, 0x30, 0x00, 0x3F, 0x00, 0x5D, 0x00, 0x79, 0x00, 0xA7,
+ 0x29, 17, 0xE1, 0x00, 0xCF, 0x01, 0x12, 0x01, 0x49, 0x01, 0xA1, 0x01, 0xEB, 0x01, 0xED, 0x02, 0x2F, 0x02, 0x74,
+ 0x29, 17, 0xE2, 0x02, 0x9F, 0x02, 0xD5, 0x02, 0xFB, 0x03, 0x2C, 0x03, 0x4B, 0x03, 0x73, 0x03, 0x8C, 0x03, 0xA5,
+ 0x29, 5, 0xE3, 0x03, 0xC5, 0x03, 0xFF,
+ 0x29, 17, 0xE4, 0x00, 0x00, 0x00, 0x09, 0x00, 0x1F, 0x00, 0x30, 0x00, 0x3F, 0x00, 0x5D, 0x00, 0x79, 0x00, 0xA7,
+ 0x29, 17, 0xE5, 0x00, 0xCF, 0x01, 0x12, 0x01, 0x49, 0x01, 0xA1, 0x01, 0xEB, 0x01, 0xED, 0x02, 0x2F, 0x02, 0x74,
+ 0x29, 17, 0xE6, 0x02, 0x9F, 0x02, 0xD5, 0x02, 0xFB, 0x03, 0x2C, 0x03, 0x4B, 0x03, 0x73, 0x03, 0x8C, 0x03, 0xA5,
+ 0x29, 5, 0xE7, 0x03, 0xC5, 0x03, 0xFF,
+ 0x29, 17, 0xE8, 0x00, 0x00, 0x00, 0x09, 0x00, 0x1F, 0x00, 0x30, 0x00, 0x3F, 0x00, 0x5D, 0x00, 0x79, 0x00, 0xA7,
+ 0x29, 17, 0xE9, 0x00, 0xCF, 0x01, 0x12, 0x01, 0x49, 0x01, 0xA1, 0x01, 0xEB, 0x01, 0xED, 0x02, 0x2F, 0x02, 0x74,
+ 0x29, 17, 0xEA, 0x02, 0x9F, 0x02, 0xD5, 0x02, 0xFB, 0x03, 0x2C, 0x03, 0x4B, 0x03, 0x73, 0x03, 0x8C, 0x03, 0xA5,
+ 0x29, 5, 0xEB, 0x03, 0xC5, 0x03, 0xFF,
+ 0x29, 4, 0xB0, 0x05, 0x05, 0x05,
+ 0x29, 4, 0xB1, 0x05, 0x05, 0x05,
+ 0x29, 4, 0xB3, 0x10, 0x10, 0x10,
+ 0x29, 4, 0xB4, 0x06, 0x06, 0x06,
+ 0x29, 4, 0xB6, 0x44, 0x44, 0x44,
+ 0x29, 4, 0xB7, 0x34, 0x34, 0x34,
+ 0x29, 4, 0xB8, 0x34, 0x34, 0x34,
+ 0x29, 4, 0xB9, 0x24, 0x24, 0x24,
+ 0x29, 4, 0xBA, 0x24, 0x24, 0x24,
+ 0x29, 4, 0xBC, 0x00, 0x70, 0x00,
+ 0x29, 4, 0xBD, 0x00, 0x70, 0x00,
+ 0x23, 2, 0xBE, 0x50,
+ 0x23, 2, 0x35, 0x00,
+ 0x13, 1, 0x11,
+ 0xff, 200,
+ 0x13, 1, 0x29,
+ 0xff, 200,
+ 0xFF, 0xFF, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_TL050FHV02CT[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xFF, 10, /* delay 10ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xFF, 150, /* delay 150ms */
+ 0xFF, 0xFF, /* ending flag */
+};
+
+#endif
+
diff --git a/board/amlogic/g12a_u200_v1/Kconfig b/board/amlogic/g12a_u200_v1/Kconfig
new file mode 100644
index 0000000..98e605d
--- /dev/null
+++ b/board/amlogic/g12a_u200_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_G12A
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "g12a_u200_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "g12a"
+
+config SYS_CONFIG_NAME
+ default "g12a_u200_v1"
+
+endif
diff --git a/board/amlogic/g12a_u200_v1/Makefile b/board/amlogic/g12a_u200_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/g12a_u200_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/g12a_u200_v1/aml-user-key.sig b/board/amlogic/g12a_u200_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/g12a_u200_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/g12a_u200_v1/eth_setup.c b/board/amlogic/g12a_u200_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/g12a_u200_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/g12a_u200_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12a_u200_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..93b0335
--- /dev/null
+++ b/board/amlogic/g12a_u200_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,40 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 681},
+ { 0x1b0001, 691},
+ { 0x1a0002, 701},
+ { 0x190003, 711},
+ { 0x180004, 721},
+ { 0x170005, 731},
+ { 0x160006, 741},
+ { 0x150007, 751},
+ { 0x140008, 761},
+ { 0x130009, 772},
+ { 0x12000a, 782},
+ { 0x11000b, 792},
+ { 0x10000c, 802},
+ { 0x0f000d, 812},
+ { 0x0e000e, 822},
+ { 0x0d000f, 832},
+ { 0x0c0010, 842},
+ { 0x0b0011, 852},
+ { 0x0a0012, 862},
+ { 0x090013, 872},
+ { 0x080014, 882},
+ { 0x070015, 892},
+ { 0x060016, 902},
+ { 0x050017, 912},
+ { 0x040018, 922},
+ { 0x030019, 932},
+ { 0x02001a, 942},
+ { 0x01001b, 952},
+ { 0x00001c, 962}
+};
+
+#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12a_u200_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12a_u200_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..b99260e
--- /dev/null
+++ b/board/amlogic/g12a_u200_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,210 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ /*set gpioH_8 low to power off vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+
+ /*set test_n low to power off vcck & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+
+ /*step down ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ /*step up ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+ /*set test_n low to power on vcck & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+ _udelay(100);
+
+ /*set gpioH_8 low to power on vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+ _udelay(10000);
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ struct wakeup_gpio_info *gpio;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC | ETH_PHY_GPIO_SRC);
+
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_3;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+ /*Eth:GPIOZ_14*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = ETH_PHY_GPIO_SRC;
+ gpio->gpio_in_idx = GPIOZ_14;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO1_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+ /*bt wake host*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_18;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ unsigned char adc_key_cnt = 0;
+ init_remote();
+ saradc_enable();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ do {
+ #ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+ if (cec_power_on_check())
+ exit_reason = CEC_WAKEUP;
+ }
+ #endif
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
+ irq[IRQ_VRTC] = 0xFFFFFFFF;
+ exit_reason = RTC_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<3)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+#if 0
+ if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
+ irq[IRQ_GPIO1] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 14))
+ && (readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 14)))
+ exit_reason = ETH_PHY_GPIO;
+ }
+#endif
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO2_I) & (0x01 << 18))
+ && (readl(PREG_PAD_GPIO2_O) & (0x01 << 17))
+ && !(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 17)))
+ exit_reason = BT_WAKEUP;
+ }
+
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/g12a_u200_v1/firmware/timing.c b/board/amlogic/g12a_u200_v1/firmware/timing.c
new file mode 100755
index 0000000..3f79234
--- /dev/null
+++ b/board/amlogic/g12a_u200_v1/firmware/timing.c
@@ -0,0 +1,588 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] = {
+{
+ /* g12a skt (u209) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1200, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0xffff,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0c0c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) lpddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+{
+ /* g12a Y2 dongle */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
+ .dram_rtt_nom_wr_park = {00,00},
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* lpddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR3,
+ .DRAMFreq = {600, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,//0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x00c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 30, //
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x3ff,//0x253,
+ .soc_ac_slew_rate = 0x3ff,//0x253,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 800,//200,
+ .vref_receiver_permil = 700,//875, //700 for drv 40 odt 60 is better ,why?
+ .vref_dram_permil = 500,//875,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {0x10,0x0,0x10-6,0x10-6,0x10-6,0x0,0x0,0x0,0x0,0x0},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 29 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ),
+ [4] = ( 31| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8},
+ .ddr_lpddr34_dq_remap = {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24},
+ //{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6},
+ .dram_rtt_nom_wr_park = {00,00},
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0000001c
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE PWM table */
+#if (VDDEE_VAL == 680)
+ #define VDDEE_VAL_REG 0x001c0000
+#elif (VDDEE_VAL == 690)
+ #define VDDEE_VAL_REG 0x001b0001
+#elif (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x001a0002
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x00190003
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x00180004
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0x00170005
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0x00160006
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0x00150007
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0x00140008
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0x00130009
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0x0012000a
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x0011000b
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x0010000c
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x000f000d
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x000e000e
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x000d000f
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x000c0010
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x000b0011
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x000a0012
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x00090013
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x00080014
+#elif (VDDEE_VAL == 890)
+ #define VDDEE_VAL_REG 0x00070015
+#elif (VDDEE_VAL == 900)
+ #define VDDEE_VAL_REG 0x00060016
+#elif (VDDEE_VAL == 910)
+ #define VDDEE_VAL_REG 0x00050017
+#elif (VDDEE_VAL == 920)
+ #define VDDEE_VAL_REG 0x00040018
+#elif (VDDEE_VAL == 930)
+ #define VDDEE_VAL_REG 0x00030019
+#elif (VDDEE_VAL == 940)
+ #define VDDEE_VAL_REG 0x0002001a
+#elif (VDDEE_VAL == 950)
+ #define VDDEE_VAL_REG 0x0001001b
+#elif (VDDEE_VAL == 960)
+ #define VDDEE_VAL_REG 0x0000001c
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ /* eg: PWM init */
+
+ /* PWM_AO_D */
+ /* VCCK_VAL_REG: check PWM table */
+ {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
+ /* PWM_AO_B */
+ /* VDDEE_VAL_REG: check PWM table */
+ {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable 5V_EN */
+ {GPIO_O_EN_N_REG3, (1 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Enable VCCK */
+ {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 31), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Init sys led*/
+ {AO_GPIO_O_EN_N, (0 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/g12a_u200_v1/g12a_u200_v1.c b/board/amlogic/g12a_u200_v1/g12a_u200_v1.c
new file mode 100644
index 0000000..ff4d97c
--- /dev/null
+++ b/board/amlogic/g12a_u200_v1/g12a_u200_v1.c
@@ -0,0 +1,752 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#ifdef CONFIG_AML_SPIFC
+#include <dm.h>
+#include <amlogic/spifc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+#ifdef ETHERNET_INTERNAL_PHY
+void internalPhyConfig(struct phy_device *phydev)
+{
+}
+
+static int dwmac_meson_cfg_pll(void)
+{
+ writel(0x39C0040A, P_ETH_PLL_CTL0);
+ writel(0x927E0000, P_ETH_PLL_CTL1);
+ writel(0xAC5F49E5, P_ETH_PLL_CTL2);
+ writel(0x00000000, P_ETH_PLL_CTL3);
+ udelay(200);
+ writel(0x19C0040A, P_ETH_PLL_CTL0);
+ return 0;
+}
+
+static int dwmac_meson_cfg_analog(void)
+{
+ /*Analog*/
+ writel(0x20200000, P_ETH_PLL_CTL5);
+ writel(0x0000c002, P_ETH_PLL_CTL6);
+ writel(0x00000023, P_ETH_PLL_CTL7);
+
+ return 0;
+}
+
+static int dwmac_meson_cfg_ctrl(void)
+{
+ /*config phyid should between a 0~0xffffffff*/
+ /*please don't use 44000181, this has been used by internal phy*/
+ writel(0x33000180, P_ETH_PHY_CNTL0);
+
+ /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
+ writel(0x260, P_ETH_PHY_CNTL2);
+
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ writel(0x34043, P_ETH_PHY_CNTL1);
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ return 0;
+}
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 1;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 9;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ dwmac_meson_cfg_pll();
+ dwmac_meson_cfg_analog();
+ dwmac_meson_cfg_ctrl();
+
+ /* eth core clock */
+ setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
+ /* eth phy clock */
+ setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
+
+ /* eth phy pll, clk50m */
+ setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+
+static int dwmac_meson_cfg_drive_strength(void)
+{
+ writel(0xaaaaaaa5, P_PAD_DS_REG4A);
+ return 0;
+}
+
+static void setup_net_chip_ext(void)
+{
+ eth_aml_reg0_t eth_reg0;
+ writel(0x11111111, P_PERIPHS_PIN_MUX_6);
+ writel(0x111111, P_PERIPHS_PIN_MUX_7);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_ETHERNET_NONE
+ return 0;
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+ dwmac_meson_cfg_drive_strength();
+ setup_net_chip_ext();
+#endif
+#ifdef ETHERNET_INTERNAL_PHY
+ setup_net_chip();
+#endif
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ /* check card detect */
+ clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM 1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_USB_GPIO_PWR,
+ CONFIG_USB_GPIO_PWR_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_USB_GPIO_PWR);
+ return;
+ }
+
+ if (is_power_on) {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
+ } else {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+ .usb_phy2_pll_base_addr = {
+ CONFIG_USB_PHY_20,
+ CONFIG_USB_PHY_21,
+ }
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 280*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xfffff << 12);
+ if (enable)
+ val |= 0x33333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~(0xf << 24);
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xf6000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+ //As NOT NEED other board init If USB BOOT MODE
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+ board_usb_pll_disable(&g_usb_config_GXL_skt);
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#if 0
+ aml_pwm_cal_init(0);
+#endif//
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+/* set dts props */
+void aml_config_dtb(void)
+{
+ cpu_id_t cpuid = get_cpu_id();
+
+ run_command("fdt address $dtb_mem_addr", 0);
+ printf("%s %d\n", __func__, __LINE__);
+ if (cpuid.chip_rev == 0xA) {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /emmc/emmc co_phase <0x2>", 0);
+ run_command("fdt rm /emmc/emmc caps2", 0);
+ run_command("fdt set /emmc/emmc f_max <0x02625a00>", 0);
+
+ run_command("fdt set /sdio status okay", 0);
+ run_command("fdt set /sd1 status okay", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux1 drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength <2>", 0);
+ run_command("fdt set /pinctrl@ff634480/sdio_all_pins/mux drive-strength <1>", 0);
+ /* debug */
+ run_command("fdt print /emmc/emmc co_phase", 0);
+ run_command("fdt print /emmc/emmc caps2", 0);
+ run_command("fdt print /emmc/emmc f_max", 0);
+
+ run_command("fdt print /sdio status", 0);
+ run_command("fdt print /sd1 status ", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux1 drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sdio_all_pins/mux drive-strength", 0);
+ } else {
+
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /emmc/emmc co_phase <0x3>", 0);
+ run_command("fdt set /sdio status disabled", 0);
+ run_command("fdt set /sd2 status okay", 0);
+ /* debug */
+ run_command("fdt print /emmc/emmc co_phase", 0);
+ run_command("fdt print /emmc/emmc caps2", 0);
+ run_command("fdt print /emmc/emmc f_max", 0);
+ run_command("fdt print /sdio status", 0);
+ run_command("fdt print /sd2 status", 0);
+ }
+
+ return;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+#ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+#endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ /**/
+ aml_config_dtb();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 1 p321 v1
+ * hwid = 2 p321 v2
+ */
+ unsigned int hwid = 1;
+ char loc_name[64] = {0};
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+
+ switch (hwid) {
+ case 1:
+ strcpy(loc_name, "txl_p321_v1\0");
+ break;
+ case 2:
+ strcpy(loc_name, "txl_p321_v2\0");
+ break;
+ default:
+ strcpy(loc_name, "txl_p321_v1");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/g12a_u200_v1/lcd.c b/board/amlogic/g12a_u200_v1/lcd.c
new file mode 100755
index 0000000..6873421
--- /dev/null
+++ b/board/amlogic/g12a_u200_v1/lcd.c
@@ -0,0 +1,631 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+#ifdef CONFIG_AML_LCD_EXTERN
+#include "lcd_extern.h"
+#endif
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_9", /* panel rst */
+ "GPIOZ_8", /* panel power */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+#if 0
+ {LCD_POWER_TYPE_CPU, 0,1,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TL050FHV02CT[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TL050FHV02CT[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TL070WSH27[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TL070WSH27[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,10,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_4", /* BL_EN */
+ "GPIOH_5", /* BL_PWM */
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,1,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TL050FHV02CT*/
+ "lcd_3",LCD_MIPI,8,
+ /* basic timing */
+ 1080,1920,1125,2100,5,30,0,44,108,0,
+ /* clk_attr */
+ 0,0,1,118125000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,960,0,1,0,2,1,0,Rsv_val,3,
+ /* power step */
+ lcd_power_on_step_TL050FHV02CT, lcd_power_off_step_TL050FHV02CT,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TL070WSH27*/
+ "lcd_4",LCD_MIPI,8,
+ /* basic timing */
+ 1024,600,1250,630,80,100,0,5,20,0,
+ /* clk_attr */
+ 0,0,1,47250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,300,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_TL070WSH27, lcd_power_off_step_TL070WSH27,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM_FT*/
+ "lcd_5",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,4,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB_FT*/
+ "lcd_6",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,770,1070,10,80,0,6,20,0,
+ /* clk_attr */
+ 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,5,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOH_5
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xff, 20,
+ 0x05, 1, 0x29,
+ 0xff, 20,
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xff, 10,
+ 0x05, 1, 0x10,
+ 0xff, 10,
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 10,
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 10,
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_TL050FHV02CT[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff,0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TL050FHV02CT[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_TL070WSH27[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xff, 100,
+ 0x05, 1, 0x29,
+ 0xff, 20,
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TL070WSH27[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xff, 100,
+ 0x05, 1, 0x10,
+ 0xff, 10,
+ 0xff, 0xff, //ending flag
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_clk_path = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0xff, //ending flag
+};
+
+static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff,0xff, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 6,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .cmd_size = 9,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ { /* TV070WSM */
+ .index = 1,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_TV070WSM,
+ .table_init_off = ext_init_off_table_TV070WSM,
+ },
+ { /* P070ACB */
+ .index = 2,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_P070ACB,
+ .table_init_off = ext_init_off_table_P070ACB,
+ },
+ { /* TL050FHV02CT */
+ .index = 3,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_TL050FHV02CT,
+ .table_init_off = ext_init_off_table_TL050FHV02CT,
+ },
+ { /* TV070WSM_FT */
+ .index = 4,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_TV070WSM_FT,
+ .table_init_off = ext_init_off_table_TV070WSM_FT,
+ },
+ { /* P070ACB_FT */
+ .index = 5,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_P070ACB_FT,
+ .table_init_off = ext_init_off_table_P070ACB_FT,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "none",
+ .type = BL_EXTERN_MAX,
+ .i2c_addr = 0xff,
+ .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+ .dim_min = 10,
+ .dim_max = 255,
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:/* TV070WSM*/
+ case 5:/* TV070WSM_FT*/
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:/* P070ACB*/
+ case 6:/* P070ACB_FT*/
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 3:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TL050FHV02CT;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TL050FHV02CT;
+ break;
+ case 4:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TL070WSH27;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TL070WSH27;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/g12a_u200_v1/lcd_extern.h b/board/amlogic/g12a_u200_v1/lcd_extern.h
new file mode 100644
index 0000000..fbcf179
--- /dev/null
+++ b/board/amlogic/g12a_u200_v1/lcd_extern.h
@@ -0,0 +1,919 @@
+/*
+ * board/amlogic/g12a_u200_v1/lcd_extern.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DFT_LCD_EXTERN_H_
+#define _DFT_LCD_EXTERN_H_
+
+static unsigned char ext_init_on_table_TV070WSM[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 100, /* delay */
+ 0x15, 2, 0x62, 0x01,
+ 0x39, 5, 0xff, 0xaa, 0x55, 0x25, 0x01,
+ 0x15, 2, 0xfc, 0x08,
+ 0xff, 1, /* delay */
+ 0x15, 2, 0xfc, 0x00,
+ 0x39, 5, 0xff, 0xaa, 0x55, 0x25, 0x00,
+ 0xff, 20, /* delay */
+ 0x39, 6, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00,
+ 0x39, 3, 0xb1, 0x68, 0x41,
+ 0x15, 2, 0xb5, 0x88,
+ 0x15, 2, 0xb6, 0x0f,
+ 0x39, 5, 0xb8, 0x01, 0x01, 0x12, 0x01,
+ 0x39, 3, 0xbb, 0x11, 0x11,
+ 0x39, 3, 0xbc, 0x05, 0x05,
+ 0x15, 2, 0xc7, 0x03,
+ 0x39, 6, 0xbd, 0x03, 0x02, 0x19, 0x17, 0x00,
+ 0x15, 2, 0xc8, 0x80,
+ 0x39, 6, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x01,
+ 0x39, 3, 0xB2, 0x01, 0x01,
+ 0x39, 3, 0xB3, 0x28, 0x28,
+ 0x39, 3, 0xB4, 0x14, 0x14,
+ 0x39, 3, 0xB8, 0x05, 0x05,
+ 0x39, 3, 0xB9, 0x45, 0x45,
+ 0x39, 3, 0xBA, 0x25, 0x25,
+ 0x39, 3, 0xBC, 0x88, 0x00,
+ 0x39, 3, 0xBD, 0x88, 0x00,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02,
+ 0x15, 2, 0xEE, 0x00,
+ 0x39, 17, 0xB0, 0x00, 0x4B, 0x00, 0x5C, 0x00, 0x79, 0x00, 0x94, 0x00, 0xA6, 0x00, 0xD8, 0x00, 0xF2, 0x01, 0x19,
+ 0x39, 17, 0xB1, 0x01, 0x39, 0x01, 0x77, 0x01, 0xA2, 0x01, 0xF2, 0x02, 0x32, 0x02, 0x34, 0x02, 0x6D, 0x02, 0xA2,
+ 0x39, 17, 0xB2, 0x02, 0xC7, 0x02, 0xF2, 0x03, 0x18, 0x03, 0x43, 0x03, 0x65, 0x03, 0x86, 0x03, 0x8F, 0x03, 0x94,
+ 0x39, 5, 0xB3, 0x03, 0x96, 0x03, 0x98,
+ 0x39, 17, 0xB4, 0x00, 0x84, 0x00, 0x91, 0x00, 0xA4, 0x00, 0xB6, 0x00, 0xCA, 0x00, 0xE9, 0x01, 0x02, 0x01, 0x2A,
+ 0x39, 17, 0xB5, 0x01, 0x49, 0x01, 0x82, 0x01, 0xAF, 0x01, 0xF7, 0x02, 0x36, 0x02, 0x38, 0x02, 0x70, 0x02, 0xA6,
+ 0x39, 17, 0xB6, 0x02, 0xC8, 0x02, 0xF5, 0x03, 0x1A, 0x03, 0x43, 0x03, 0x62, 0x03, 0x82, 0x03, 0x8F, 0x03, 0x94,
+ 0x39, 5, 0xB7, 0x03, 0x96, 0x03, 0x98,
+ 0x39, 17, 0xB8, 0x01, 0x22, 0x01, 0x27, 0x01, 0x2E, 0x01, 0x38, 0x01, 0x40, 0x01, 0x53, 0x01, 0x60, 0x01, 0x7B,
+ 0x39, 17, 0xB9, 0x01, 0x8C, 0x01, 0xB5, 0x01, 0xD3, 0x02, 0x11, 0x02, 0x49, 0x02, 0x4A, 0x02, 0x7F, 0x02, 0xB1,
+ 0x39, 17, 0xBA, 0x02, 0xD1, 0x03, 0x00, 0x03, 0x22, 0x03, 0x49, 0x03, 0x60, 0x03, 0x7A, 0x03, 0x8B, 0x03, 0x8F,
+ 0x39, 5, 0xBB, 0x03, 0x93, 0x03, 0x9A,
+ 0x39, 17, 0xBC, 0x00, 0x37, 0x00, 0x48, 0x00, 0x65, 0x00, 0x80, 0x00, 0x92, 0x00, 0xC4, 0x00, 0xDE, 0x01, 0x05,
+ 0x39, 17, 0xBD, 0x01, 0x31, 0x01, 0x6F, 0x01, 0x9E, 0x01, 0xEE, 0x02, 0x32, 0x02, 0x34, 0x02, 0x71, 0x02, 0xA7,
+ 0x39, 17, 0xBE, 0x02, 0xD3, 0x02, 0xFE, 0x03, 0x24, 0x03, 0x4F, 0x03, 0x71, 0x03, 0x92, 0x03, 0x9B, 0x03, 0xA0,
+ 0x39, 5, 0xBF, 0x03, 0xA6, 0x03, 0xA8,
+ 0x39, 17, 0xC0, 0x00, 0x70, 0x00, 0x7D, 0x00, 0x90, 0x00, 0xA4, 0x00, 0xB6, 0x00, 0xD5, 0x00, 0xEE, 0x01, 0x16,
+ 0x39, 17, 0xC1, 0x01, 0x41, 0x01, 0x7A, 0x01, 0xAB, 0x01, 0xF3, 0x02, 0x36, 0x02, 0x38, 0x02, 0x74, 0x02, 0xAA,
+ 0x39, 17, 0xC2, 0x02, 0xD4, 0x03, 0x01, 0x03, 0x26, 0x03, 0x4F, 0x03, 0x6E, 0x03, 0x8E, 0x03, 0x9B, 0x03, 0xA0,
+ 0x39, 5, 0xC3, 0x03, 0xA6, 0x03, 0xA8,
+ 0x39, 17, 0xC4, 0x01, 0x0E, 0x01, 0x13, 0x01, 0x1A, 0x01, 0x24, 0x01, 0x2C, 0x01, 0x3F, 0x01, 0x4C, 0x01, 0x67,
+ 0x39, 17, 0xC5, 0x01, 0x84, 0x01, 0xAD, 0x01, 0xCF, 0x02, 0x0D, 0x02, 0x49, 0x02, 0x4A, 0x02, 0x83, 0x02, 0xB5,
+ 0x39, 17, 0xC6, 0x02, 0xDD, 0x03, 0x0C, 0x03, 0x2E, 0x03, 0x55, 0x03, 0x6B, 0x03, 0x86, 0x03, 0x97, 0x03, 0x9B,
+ 0x39, 5, 0xC7, 0x03, 0xA1, 0x03, 0xA8,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x04,
+ 0x39, 6, 0xB1, 0x03, 0x02, 0x02, 0x02, 0x00,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06,
+ 0x39, 3, 0xB0, 0x11, 0x11,
+ 0x39, 3, 0xB1, 0x13, 0x13,
+ 0x39, 3, 0xB2, 0x03, 0x03,
+ 0x39, 3, 0xB3, 0x34, 0x34,
+ 0x39, 3, 0xB4, 0x34, 0x34,
+ 0x39, 3, 0xB5, 0x34, 0x34,
+ 0x39, 3, 0xB6, 0x34, 0x34,
+ 0x39, 3, 0xB7, 0x34, 0x34,
+ 0x39, 3, 0xB8, 0x34, 0x34,
+ 0x39, 3, 0xB9, 0x34, 0x34,
+ 0x39, 3, 0xBA, 0x34, 0x34,
+ 0x39, 3, 0xBB, 0x34, 0x34,
+ 0x39, 3, 0xBC, 0x34, 0x34,
+ 0x39, 3, 0xBD, 0x34, 0x34,
+ 0x39, 3, 0xBE, 0x34, 0x34,
+ 0x39, 3, 0xBF, 0x34, 0x34,
+ 0x39, 3, 0xC0, 0x34, 0x34,
+ 0x39, 3, 0xC1, 0x02, 0x02,
+ 0x39, 3, 0xC2, 0x12, 0x12,
+ 0x39, 3, 0xC3, 0x10, 0x10,
+ 0x39, 3, 0xE5, 0x34, 0x34,
+ 0x39, 6, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x39, 6, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05,
+ 0x15, 2, 0xC0, 0x03,
+ 0x15, 2, 0xC1, 0x02,
+ 0x39, 3, 0xC8, 0x01, 0x20,
+ 0x15, 2, 0xE5, 0x03,
+ 0x15, 2, 0xE6, 0x03,
+ 0x15, 2, 0xE7, 0x03,
+ 0x15, 2, 0xE8, 0x03,
+ 0x15, 2, 0xE9, 0x03,
+ 0x39, 5, 0xD1, 0x03, 0x00, 0x3D, 0x00,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03,
+ 0x39, 3, 0xB0, 0x11, 0x00,
+ 0x39, 3, 0xB1, 0x11, 0x00,
+ 0x39, 6, 0xB2, 0x03, 0x00, 0x00, 0x00, 0x00,
+ 0x39, 6, 0xB3, 0x03, 0x00, 0x00, 0x00, 0x00,
+ 0x39, 6, 0xBA, 0x31, 0x00, 0x00, 0x00, 0x00,
+ 0x15, 2, 0x35, 0x00,
+ 0x15, 2, 0x51, 0xFF,
+ 0x15, 2, 0x53, 0x2C,
+ 0x15, 2, 0x55, 0x03,
+ 0x05, 1, 0x11,
+ 0xff, 120, /* delay 120ms */
+ 0x05, 1, 0x29,
+ 0xff, 0xff, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_TV070WSM[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xff, 30, /* delay 30ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xff, 10,
+ 0xff, 0xff, /* ending flag */
+};
+
+static unsigned char ext_init_on_table_P070ACB[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 100, /* delay */
+ 0x15, 2, 0x62, 0x01,
+ 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x01,
+ 0x23, 2, 0xFC, 0x08,
+ 0xFF, 1, /* delay(ms) */
+ 0x23, 2, 0xFC, 0x00,
+
+ 0xFF, 1, /* delay(ms) */
+ 0x23, 2, 0x6F, 0x21,
+ 0x23, 2, 0xF7, 0x01,
+ 0xFF, 1, /* delay(ms) */
+ 0x23, 2, 0x6F, 0x21,
+ 0x23, 2, 0xF7, 0x00,
+ 0xFF, 1, /* delay(ms) */
+
+ 0x23, 2, 0x6F, 0x1A,
+ 0x23, 2, 0xF7, 0x05,
+ 0xFF, 1, /* delay(ms) */
+
+ 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x00,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00,
+ 0x29, 3, 0xB1, 0x68, 0x41,
+ 0x23, 2, 0xB5, 0x88,
+ 0x29, 6, 0xBD, 0x02, 0xB0, 0x0C, 0x14, 0x00,
+ 0x23, 2, 0xC8, 0x80,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01,
+ 0x29, 3, 0xB3, 0x2D, 0x2D,
+ 0x29, 3, 0xB4, 0x19, 0x19,
+ 0x23, 2, 0xB5, 0x06,
+
+ 0x29, 3, 0xB9, 0x36, 0x36,
+ 0x29, 3, 0xBA, 0x26, 0x26,
+ 0x29, 3, 0xBC, 0xA8, 0x01,
+ 0x29, 3, 0xBD, 0xAB, 0x01,
+ 0x23, 2, 0xC0, 0x0C,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02,
+ 0x23, 2, 0xEE, 0x02,
+ 0x29, 7, 0xB0, 0x00, 0x50, 0x00, 0x52, 0x00, 0x73,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xB0, 0x00, 0x8F, 0x00, 0xA5, 0x00, 0xCA,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xB0, 0x00, 0xEA, 0x01, 0x1B,
+ 0x29, 7, 0xB1, 0x01, 0x42, 0x01, 0x82, 0x01, 0xB3,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xB1, 0x02, 0x00, 0x02, 0x41, 0x02, 0x42,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xB1, 0x02, 0x78, 0x02, 0xB5,
+ 0x29, 7, 0xB2, 0x02, 0xDA, 0x03, 0x12, 0x03, 0x3A,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xB2, 0x03, 0x6E, 0x03, 0x8D, 0x03, 0xB1,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xB2, 0x03, 0xCA, 0x03, 0xE8,
+ 0x29, 5, 0xB3, 0x03, 0xF4, 0x03, 0xFF,
+
+ 0x29, 7, 0xBC, 0x00, 0x05, 0x00, 0x52, 0x00, 0x73,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xBC, 0x00, 0x8F, 0x00, 0xA5, 0x00, 0xCA,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xBC, 0x00, 0xEA, 0x01, 0x1B,
+ 0x29, 7, 0xBD, 0x01, 0x42, 0x01, 0x82, 0x01, 0xB3,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xBD, 0x02, 0x00, 0x02, 0x41, 0x02, 0x42,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xBD, 0x02, 0x78, 0x02, 0xB5,
+ 0x29, 7, 0xBE, 0x02, 0xDA, 0x03, 0x12, 0x03, 0x3A,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xBE, 0x03, 0x6E, 0x03, 0x8D, 0x03, 0xB1,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xBE, 0x03, 0xCA, 0x03, 0xE8,
+ 0x29, 5, 0xBF, 0x03, 0xF4, 0x03, 0xFF,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03,
+ 0x29, 6, 0xB2, 0x05, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xB6, 0x05, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xB7, 0x05, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xBA, 0x57, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xBB, 0x57, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 5, 0xC0, 0x00, 0x34, 0x00, 0x00,
+ 0x29, 5, 0xC1, 0x00, 0x00, 0x34, 0x00,
+ 0x23, 2, 0xC4, 0x40,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05,
+ 0x29, 3, 0xB0, 0x17, 0x06,
+ 0x29, 3, 0xB1, 0x17, 0x06,
+ 0x29, 3, 0xB2, 0x17, 0x06,
+ 0x29, 3, 0xB3, 0x17, 0x06,
+ 0x29, 3, 0xB4, 0x17, 0x06,
+
+ 0x29, 6, 0xBD, 0x03, 0x01, 0x03, 0x03, 0x01,
+ 0x23, 2, 0xC0, 0x05,
+ 0x23, 2, 0xC4, 0x82,
+ 0x23, 2, 0xC5, 0xA2,
+ 0x29, 3, 0xC8, 0x03, 0x30,
+ 0x29, 3, 0xC9, 0x03, 0x31,
+ 0x29, 4, 0xCC, 0x00, 0x00, 0x3C,
+ 0x29, 4, 0xCD, 0x00, 0x00, 0x3C,
+ 0x29, 6, 0xD1, 0x00, 0x44, 0x09, 0x00, 0x00,
+ 0x29, 6, 0xD2, 0x00, 0x04, 0x0B, 0x00, 0x00,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06,
+ 0x29, 3, 0xB0, 0x0B, 0x2D,
+ 0x29, 3, 0xB1, 0x2D, 0x09,
+ 0x29, 3, 0xB2, 0x2A, 0x29,
+ 0x29, 3, 0xB3, 0x34, 0x1B,
+ 0x29, 3, 0xB4, 0x19, 0x17,
+ 0x29, 3, 0xB5, 0x15, 0x13,
+ 0x29, 3, 0xB6, 0x11, 0x01,
+ 0x29, 3, 0xB7, 0x34, 0x34,
+ 0x29, 3, 0xB8, 0x34, 0x2D,
+ 0x29, 3, 0xB9, 0x2D, 0x34,
+ 0x29, 3, 0xBA, 0x2D, 0x2D,
+ 0x29, 3, 0xBB, 0x34, 0x34,
+ 0x29, 3, 0xBC, 0x34, 0x34,
+ 0x29, 3, 0xBD, 0x00, 0x10,
+ 0x29, 3, 0xBE, 0x12, 0x14,
+ 0x29, 3, 0xBF, 0x16, 0x18,
+
+ 0x29, 3, 0xC0, 0x1A, 0x34,
+ 0x29, 3, 0xC1, 0x29, 0x2A,
+ 0x29, 3, 0xC2, 0x08, 0x2D,
+ 0x29, 3, 0xC3, 0x2D, 0x0A,
+ 0x29, 3, 0xC4, 0x0A, 0x2D,
+ 0x29, 3, 0xC5, 0x2D, 0x00,
+ 0x29, 3, 0xC6, 0x2A, 0x29,
+ 0x29, 3, 0xC7, 0x34, 0x14,
+ 0x29, 3, 0xC8, 0x16, 0x18,
+ 0x29, 3, 0xC9, 0x1A, 0x10,
+ 0x29, 3, 0xCA, 0x12, 0x08,
+ 0x29, 3, 0xCB, 0x34, 0x34,
+ 0x29, 3, 0xCC, 0x34, 0x2D,
+ 0x29, 3, 0xCD, 0x2D, 0x34,
+ 0x29, 3, 0xCE, 0x2D, 0x2D,
+ 0x29, 3, 0xCF, 0x34, 0x34,
+
+ 0x29, 3, 0xD0, 0x34, 0x34,
+ 0x29, 3, 0xD1, 0x09, 0x13,
+ 0x29, 3, 0xD2, 0x11, 0x1B,
+ 0x29, 3, 0xD3, 0x19, 0x17,
+ 0x29, 3, 0xD4, 0x15, 0x34,
+ 0x29, 3, 0xD5, 0x29, 0x2A,
+ 0x29, 3, 0xD6, 0x01, 0x2D,
+ 0x29, 3, 0xD7, 0x2D, 0x0B,
+ 0x29, 6, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ 0x29, 3, 0xE5, 0x34, 0x34,
+ 0x29, 3, 0xE6, 0x34, 0x34,
+ 0x23, 2, 0xE7, 0x00,
+ 0x29, 3, 0xE8, 0x34, 0x34,
+ 0x29, 3, 0xE9, 0x34, 0x34,
+ 0x23, 2, 0xEA, 0x00,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x00, 0x00,
+
+ 0x13, 1, 0x35,
+ 0x13, 1, 0x11,
+ 0xFF, 120, /* delay(ms) */
+ 0x13, 1, 0x29,
+ 0xFF, 20, /* delay(ms) */
+ 0xFF, 0xFF, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_P070ACB[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xFF, 10, /* delay 10ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xFF, 150, /* delay 150ms */
+ 0xFF, 0xFF, /* ending flag */
+};
+
+static unsigned char ext_init_on_table_TV070WSM_FT[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x23,2,0xE0,0x00,
+ 0x23,2,0xE1,0x93,
+ 0x23,2,0xE2,0x65,
+ 0x23,2,0xE3,0xF8,
+ 0x23,2,0xE0,0x01,
+ 0x23,2,0x00,0x00,
+ 0x23,2,0x01,0x90,
+ 0x23,2,0x03,0x00,
+ 0x23,2,0x04,0x90,
+ 0x23,2,0x17,0x00,
+ 0x23,2,0x18,0xB0,
+ 0x23,2,0x19,0x01,
+ 0x23,2,0x1A,0x00,
+ 0x23,2,0x1B,0xB0,
+ 0x23,2,0x1C,0x01,
+ 0x23,2,0x1F,0x3E,
+ 0x23,2,0x20,0x2F,
+ 0x23,2,0x21,0x2F,
+ 0x23,2,0x22,0x0E,
+ 0x23,2,0x37,0x69,
+ 0x23,2,0x38,0x05,
+ 0x23,2,0x39,0x00,
+ 0x23,2,0x3A,0x01,
+ 0x23,2,0x3C,0x90,
+ 0x23,2,0x3D,0xFF,
+ 0x23,2,0x3E,0xFF,
+ 0x23,2,0x3F,0xFF,
+ 0x23,2,0x40,0x02,
+ 0x23,2,0x41,0x80,
+ 0x23,2,0x42,0x99,
+ 0x23,2,0x43,0x06,
+ 0x23,2,0x44,0x09,
+ 0x23,2,0x45,0x3C,
+ 0x23,2,0x4B,0x04,
+ 0x23,2,0x55,0x0F,
+ 0x23,2,0x56,0x01,
+ 0x23,2,0x57,0x89,
+ 0x23,2,0x58,0x0A,
+ 0x23,2,0x59,0x0A,
+ 0x23,2,0x5A,0x27,
+ 0x23,2,0x5B,0x15,
+ 0x23,2,0x5D,0x7C,
+ 0x23,2,0x5E,0x67,
+ 0x23,2,0x5F,0x58,
+ 0x23,2,0x60,0x4C,
+ 0x23,2,0x61,0x48,
+ 0x23,2,0x62,0x38,
+ 0x23,2,0x63,0x3C,
+ 0x23,2,0x64,0x24,
+ 0x23,2,0x65,0x3B,
+ 0x23,2,0x66,0x38,
+ 0x23,2,0x67,0x36,
+ 0x23,2,0x68,0x53,
+ 0x23,2,0x69,0x3F,
+ 0x23,2,0x6A,0x44,
+ 0x23,2,0x6B,0x35,
+ 0x23,2,0x6C,0x2E,
+ 0x23,2,0x6D,0x1F,
+ 0x23,2,0x6E,0x0C,
+ 0x23,2,0x6F,0x00,
+ 0x23,2,0x70,0x7C,
+ 0x23,2,0x71,0x67,
+ 0x23,2,0x72,0x58,
+ 0x23,2,0x73,0x4C,
+ 0x23,2,0x74,0x48,
+ 0x23,2,0x75,0x38,
+ 0x23,2,0x76,0x3C,
+ 0x23,2,0x77,0x24,
+ 0x23,2,0x78,0x3B,
+ 0x23,2,0x79,0x38,
+ 0x23,2,0x7A,0x36,
+ 0x23,2,0x7B,0x53,
+ 0x23,2,0x7C,0x3F,
+ 0x23,2,0x7D,0x44,
+ 0x23,2,0x7E,0x35,
+ 0x23,2,0x7F,0x2E,
+ 0x23,2,0x80,0x1F,
+ 0x23,2,0x81,0x0C,
+ 0x23,2,0x82,0x00,
+ 0x23,2,0xE0,0x02,
+ 0x23,2,0x00,0x45,
+ 0x23,2,0x01,0x45,
+ 0x23,2,0x02,0x47,
+ 0x23,2,0x03,0x47,
+ 0x23,2,0x04,0x41,
+ 0x23,2,0x05,0x41,
+ 0x23,2,0x06,0x1F,
+ 0x23,2,0x07,0x1F,
+ 0x23,2,0x08,0x1F,
+ 0x23,2,0x09,0x1F,
+ 0x23,2,0x0A,0x1F,
+ 0x23,2,0x0B,0x1F,
+ 0x23,2,0x0C,0x1F,
+ 0x23,2,0x0D,0x1D,
+ 0x23,2,0x0E,0x1D,
+ 0x23,2,0x0F,0x1D,
+ 0x23,2,0x10,0x1F,
+ 0x23,2,0x11,0x1F,
+ 0x23,2,0x12,0x1F,
+ 0x23,2,0x13,0x1F,
+ 0x23,2,0x14,0x1F,
+ 0x23,2,0x15,0x1F,
+ 0x23,2,0x16,0x44,
+ 0x23,2,0x17,0x44,
+ 0x23,2,0x18,0x46,
+ 0x23,2,0x19,0x46,
+ 0x23,2,0x1A,0x40,
+ 0x23,2,0x1B,0x40,
+ 0x23,2,0x1C,0x1F,
+ 0x23,2,0x1D,0x1F,
+ 0x23,2,0x1E,0x1F,
+ 0x23,2,0x1F,0x1F,
+ 0x23,2,0x20,0x1F,
+ 0x23,2,0x21,0x1F,
+ 0x23,2,0x22,0x1F,
+ 0x23,2,0x23,0x1D,
+ 0x23,2,0x24,0x1D,
+ 0x23,2,0x25,0x1D,
+ 0x23,2,0x26,0x1F,
+ 0x23,2,0x27,0x1F,
+ 0x23,2,0x28,0x1F,
+ 0x23,2,0x29,0x1F,
+ 0x23,2,0x2A,0x1F,
+ 0x23,2,0x2B,0x1F,
+ 0x23,2,0x58,0x40,
+ 0x23,2,0x59,0x00,
+ 0x23,2,0x5A,0x00,
+ 0x23,2,0x5B,0x10,
+ 0x23,2,0x5C,0x06,
+ 0x23,2,0x5D,0x20,
+ 0x23,2,0x5E,0x00,
+ 0x23,2,0x5F,0x00,
+ 0x23,2,0x61,0x00,
+ 0x23,2,0x62,0x00,
+ 0x23,2,0x63,0x7A,
+ 0x23,2,0x64,0x7A,
+ 0x23,2,0x65,0x00,
+ 0x23,2,0x66,0x00,
+ 0x23,2,0x67,0x32,
+ 0x23,2,0x68,0x08,
+ 0x23,2,0x69,0x7A,
+ 0x23,2,0x6A,0x7A,
+ 0x23,2,0x6B,0x00,
+ 0x23,2,0x6C,0x00,
+ 0x23,2,0x6D,0x04,
+ 0x23,2,0x6E,0x04,
+ 0x23,2,0x6F,0x88,
+ 0x23,2,0x70,0x00,
+ 0x23,2,0x71,0x00,
+ 0x23,2,0x72,0x06,
+ 0x23,2,0x73,0x7B,
+ 0x23,2,0x74,0x00,
+ 0x23,2,0x75,0x07,
+ 0x23,2,0x76,0x00,
+ 0x23,2,0x77,0x5D,
+ 0x23,2,0x78,0x17,
+ 0x23,2,0x79,0x1F,
+ 0x23,2,0x7A,0x00,
+ 0x23,2,0x7B,0x00,
+ 0x23,2,0x7C,0x00,
+ 0x23,2,0x7D,0x03,
+ 0x23,2,0x7E,0x7B,
+ 0x23,2,0xE0,0x03,
+ 0x23,2,0xAF,0x20,
+ 0x23,2,0xE0,0x04,
+ 0x23,2,0x09,0x11,
+ 0x23,2,0x0E,0x48,
+ 0x23,2,0x2B,0x2B,
+ 0x23,2,0x2E,0x44,
+ 0x23,2,0x41,0xFF,
+ 0x23,2,0xE0,0x00,
+ 0x23,2,0xE6,0x02,
+ 0x23,2,0xE7,0x0C,
+ 0x05,1,0x11,
+ 0xff,120,/* delay 120ms */
+
+ 0x23,2,0xE0,0x03,
+ 0x23,2,0x2B,0x01,
+ 0x23,2,0x2C,0x00,
+ 0x23,2,0x30,0x03,
+ 0x23,2,0x31,0xCC,
+ 0x23,2,0x32,0x03,
+ 0x23,2,0x33,0xC9,
+ 0x23,2,0x34,0x03,
+ 0x23,2,0x35,0xC0,
+ 0x23,2,0x36,0x03,
+ 0x23,2,0x37,0xB3,
+ 0x23,2,0x38,0x03,
+ 0x23,2,0x39,0xAB,
+ 0x23,2,0x3A,0x03,
+ 0x23,2,0x3B,0x9D,
+ 0x23,2,0x3C,0x03,
+ 0x23,2,0x3D,0x8F,
+ 0x23,2,0x3E,0x03,
+ 0x23,2,0x3F,0x6D,
+ 0x23,2,0x40,0x03,
+ 0x23,2,0x41,0x51,
+ 0x23,2,0x42,0x03,
+ 0x23,2,0x43,0x17,
+ 0x23,2,0x44,0x02,
+ 0x23,2,0x45,0xD8,
+ 0x23,2,0x46,0x02,
+ 0x23,2,0x47,0x60,
+ 0x23,2,0x48,0x01,
+ 0x23,2,0x49,0xEB,
+ 0x23,2,0x4A,0x01,
+ 0x23,2,0x4B,0xE5,
+ 0x23,2,0x4C,0x01,
+ 0x23,2,0x4D,0x6C,
+ 0x23,2,0x4E,0x00,
+ 0x23,2,0x4F,0xF2,
+ 0x23,2,0x50,0x00,
+ 0x23,2,0x51,0xB4,
+ 0x23,2,0x52,0x00,
+ 0x23,2,0x53,0x74,
+ 0x23,2,0x54,0x00,
+ 0x23,2,0x55,0x54,
+ 0x23,2,0x56,0x00,
+ 0x23,2,0x57,0x34,
+ 0x23,2,0x58,0x00,
+ 0x23,2,0x59,0x26,
+ 0x23,2,0x5A,0x00,
+ 0x23,2,0x5B,0x18,
+ 0x23,2,0x5C,0x00,
+ 0x23,2,0x5D,0x11,
+ 0x23,2,0x5E,0x00,
+ 0x23,2,0x5F,0x0A,
+ 0x23,2,0x60,0x00,
+ 0x23,2,0x61,0x03,
+ 0x23,2,0x62,0x00,
+ 0x23,2,0x63,0x00,
+ 0x23,2,0x64,0x03,
+ 0x23,2,0x65,0x9E,
+ 0x23,2,0x66,0x03,
+ 0x23,2,0x67,0x9B,
+ 0x23,2,0x68,0x03,
+ 0x23,2,0x69,0x94,
+ 0x23,2,0x6A,0x03,
+ 0x23,2,0x6B,0x8C,
+ 0x23,2,0x6C,0x03,
+ 0x23,2,0x6D,0x85,
+ 0x23,2,0x6E,0x03,
+ 0x23,2,0x6F,0x76,
+ 0x23,2,0x70,0x03,
+ 0x23,2,0x71,0x67,
+ 0x23,2,0x72,0x03,
+ 0x23,2,0x73,0x4B,
+ 0x23,2,0x74,0x03,
+ 0x23,2,0x75,0x2E,
+ 0x23,2,0x76,0x02,
+ 0x23,2,0x77,0xF7,
+ 0x23,2,0x78,0x02,
+ 0x23,2,0x79,0xB8,
+ 0x23,2,0x7A,0x02,
+ 0x23,2,0x7B,0x46,
+ 0x23,2,0x7C,0x01,
+ 0x23,2,0x7D,0xD6,
+ 0x23,2,0x7E,0x01,
+ 0x23,2,0x7F,0xD0,
+ 0x23,2,0x80,0x01,
+ 0x23,2,0x81,0x5C,
+ 0x23,2,0x82,0x00,
+ 0x23,2,0x83,0xE7,
+ 0x23,2,0x84,0x00,
+ 0x23,2,0x85,0xAA,
+ 0x23,2,0x86,0x00,
+ 0x23,2,0x87,0x74,
+ 0x23,2,0x88,0x00,
+ 0x23,2,0x89,0x5A,
+ 0x23,2,0x8A,0x00,
+ 0x23,2,0x8B,0x3C,
+ 0x23,2,0x8C,0x00,
+ 0x23,2,0x8D,0x2C,
+ 0x23,2,0x8E,0x00,
+ 0x23,2,0x8F,0x1C,
+ 0x23,2,0x90,0x00,
+ 0x23,2,0x91,0x14,
+ 0x23,2,0x92,0x00,
+ 0x23,2,0x93,0x0C,
+ 0x23,2,0x94,0x00,
+ 0x23,2,0x95,0x04,
+ 0x23,2,0x96,0x00,
+ 0x23,2,0x97,0x00,
+ 0x23,2,0xE0,0x00,
+ 0x05,1,0x29,
+ 0xff,5,
+ 0xff, 0xff, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_TV070WSM_FT[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xff, 30, /* delay 30ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xff, 10,
+ 0xff, 0xff, /* ending flag */
+};
+
+static unsigned char ext_init_on_table_P070ACB_FT[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x23,2,0xE0,0x00,//Page 0
+ 0x23,2,0xE1,0x93,// PASSWORD
+ 0x23,2,0xE2,0x65,
+ 0x23,2,0xE3,0xF8,
+ 0x23,2,0x80,0x03,
+ 0x23,2,0xE0,0x01,//Page 01
+ 0x23,2,0x0C,0x74,//Set PWRIC
+ 0x23,2,0x17,0x00,//Set Gamma Power
+ 0x23,2,0x18,0xEF,//VGMP=5.1V
+ 0x23,2,0x19,0x00,
+ 0x23,2,0x1A,0x00,
+ 0x23,2,0x1B,0xEF,//VGMN=-5.1V
+ 0x23,2,0x1C,0x00,
+ 0x23,2,0x1F,0x70,//Set Gate Power
+ 0x23,2,0x20,0x2D,
+ 0x23,2,0x21,0x2D,
+ 0x23,2,0x22,0x7E,
+ 0x23,2,0x26,0xF3,//VDDD from IOVCC
+ 0x23,2,0x37,0x09,//SetPanel
+ 0x23,2,0x38,0x04,//SET RGBCYC
+ 0x23,2,0x39,0x00,
+ 0x23,2,0x3A,0x01,
+ 0x23,2,0x3C,0x90,
+ 0x23,2,0x3D,0xFF,
+ 0x23,2,0x3E,0xFF,
+ 0x23,2,0x3F,0xFF,
+ 0x23,2,0x40,0x02,//Set TCON
+ 0x23,2,0x41,0x80,
+ 0x23,2,0x42,0x99,
+ 0x23,2,0x43,0x14,
+ 0x23,2,0x44,0x19,
+ 0x23,2,0x45,0x5A,
+ 0x23,2,0x4B,0x04,
+ 0x23,2,0x55,0x02,//power voltage
+ 0x23,2,0x56,0x01,
+ 0x23,2,0x57,0x69,
+ 0x23,2,0x58,0x0A,
+ 0x23,2,0x59,0x0A,
+ 0x23,2,0x5A,0x2E,//VGH = 16.2V
+ 0x23,2,0x5B,0x19,//VGL = -12V
+ 0x23,2,0x5C,0x15,
+ 0x23,2,0x5D,0x77,//Gamma
+ 0x23,2,0x5E,0x56,
+ 0x23,2,0x5F,0x45,
+ 0x23,2,0x60,0x38,
+ 0x23,2,0x61,0x35,
+ 0x23,2,0x62,0x27,
+ 0x23,2,0x63,0x2D,
+ 0x23,2,0x64,0x18,
+ 0x23,2,0x65,0x33,
+ 0x23,2,0x66,0x34,
+ 0x23,2,0x67,0x35,
+ 0x23,2,0x68,0x56,
+ 0x23,2,0x69,0x45,
+ 0x23,2,0x6A,0x4F,
+ 0x23,2,0x6B,0x42,
+ 0x23,2,0x6C,0x40,
+ 0x23,2,0x6D,0x34,
+ 0x23,2,0x6E,0x25,
+ 0x23,2,0x6F,0x02,
+ 0x23,2,0x70,0x77,
+ 0x23,2,0x71,0x56,
+ 0x23,2,0x72,0x45,
+ 0x23,2,0x73,0x38,
+ 0x23,2,0x74,0x35,
+ 0x23,2,0x75,0x27,
+ 0x23,2,0x76,0x2D,
+ 0x23,2,0x77,0x18,
+ 0x23,2,0x78,0x33,
+ 0x23,2,0x79,0x34,
+ 0x23,2,0x7A,0x35,
+ 0x23,2,0x7B,0x56,
+ 0x23,2,0x7C,0x45,
+ 0x23,2,0x7D,0x4F,
+ 0x23,2,0x7E,0x42,
+ 0x23,2,0x7F,0x40,
+ 0x23,2,0x80,0x34,
+ 0x23,2,0x81,0x25,
+ 0x23,2,0x82,0x02,
+ 0x23,2,0xE0,0x02,//Page2
+ 0x23,2,0x00,0x53,//GIP_L Pin mapping RESET_EVEN
+ 0x23,2,0x01,0x55,//VSSG_EVEN
+ 0x23,2,0x02,0x55,//VSSA_EVEN
+ 0x23,2,0x03,0x51,//STV2_EVEN
+ 0x23,2,0x04,0x77,//VDD2_EVEN
+ 0x23,2,0x05,0x57,//VDD1_EVEN
+ 0x23,2,0x06,0x1F,
+ 0x23,2,0x07,0x4F, //CK12
+ 0x23,2,0x08,0x4D, //CK10
+ 0x23,2,0x09,0x1F,
+ 0x23,2,0x0A,0x4B, //CK8
+ 0x23,2,0x0B,0x49, //CK6
+ 0x23,2,0x0C,0x1F,
+ 0x23,2,0x0D,0x47, //CK4
+ 0x23,2,0x0E,0x45, //CK2
+ 0x23,2,0x0F,0x41, //STV1_EVEN
+ 0x23,2,0x10,0x1F,
+ 0x23,2,0x11,0x1F,
+ 0x23,2,0x12,0x1F,
+ 0x23,2,0x13,0x55, //VGG
+ 0x23,2,0x14,0x1F,
+ 0x23,2,0x15,0x1F,
+ 0x23,2,0x16,0x52,//GIP_R Pin mapping RESET_ODD
+ 0x23,2,0x17,0x55, //VSSG_ODD
+ 0x23,2,0x18,0x55, //VSSA_ODD
+ 0x23,2,0x19,0x50, //STV2_ODD
+ 0x23,2,0x1A,0x77,//VDD2_ODD
+ 0x23,2,0x1B,0x57,//VDD1_ODD
+ 0x23,2,0x1C,0x1F,
+ 0x23,2,0x1D,0x4E, //CK11
+ 0x23,2,0x1E,0x4C, //CK9
+ 0x23,2,0x1F,0x1F,
+ 0x23,2,0x20,0x4A, //CK7
+ 0x23,2,0x21,0x48, //CK5
+ 0x23,2,0x22,0x1F,
+ 0x23,2,0x23,0x46, //CK3
+ 0x23,2,0x24,0x44, //CK1
+ 0x23,2,0x25,0x40,//STV1_ODD
+ 0x23,2,0x26,0x1F,
+ 0x23,2,0x27,0x1F,
+ 0x23,2,0x28,0x1F,
+ 0x23,2,0x29,0x1F,
+ 0x23,2,0x2A,0x1F,
+ 0x23,2,0x2B,0x55, //VGG
+ 0x23,2,0x2C,0x12,//GIP_L_GS Pin mapping
+ 0x23,2,0x2D,0x15,
+ 0x23,2,0x2E,0x15,
+ 0x23,2,0x2F,0x00,
+ 0x23,2,0x30,0x37,
+ 0x23,2,0x31,0x17,
+ 0x23,2,0x32,0x1F,
+ 0x23,2,0x33,0x08,
+ 0x23,2,0x34,0x0A,
+ 0x23,2,0x35,0x1F,
+ 0x23,2,0x36,0x0C,
+ 0x23,2,0x37,0x0E,
+ 0x23,2,0x38,0x1F,
+ 0x23,2,0x39,0x04,
+ 0x23,2,0x3A,0x06,
+ 0x23,2,0x3B,0x10,
+ 0x23,2,0x3C,0x1F,
+ 0x23,2,0x3D,0x1F,
+ 0x23,2,0x3E,0x1F,
+ 0x23,2,0x3F,0x15,
+ 0x23,2,0x40,0x1F,
+ 0x23,2,0x41,0x1F,
+ 0x23,2,0x42,0x13,//GIP_R_GS Pin mapping
+ 0x23,2,0x43,0x15,
+ 0x23,2,0x44,0x15,
+ 0x23,2,0x45,0x01,
+ 0x23,2,0x46,0x37,
+ 0x23,2,0x47,0x17,
+ 0x23,2,0x48,0x1F,
+ 0x23,2,0x49,0x09,
+ 0x23,2,0x4A,0x0B,
+ 0x23,2,0x4B,0x1F,
+ 0x23,2,0x4C,0x0D,
+ 0x23,2,0x4D,0x0F,
+ 0x23,2,0x4E,0x1F,
+ 0x23,2,0x4F,0x05,
+ 0x23,2,0x50,0x07,
+ 0x23,2,0x51,0x11,
+ 0x23,2,0x52,0x1F,
+ 0x23,2,0x53,0x1F,
+ 0x23,2,0x54,0x1F,
+ 0x23,2,0x55,0x1F,
+ 0x23,2,0x56,0x1F,
+ 0x23,2,0x57,0x15,
+ 0x23,2,0x58,0x40,//GIP Timing
+ 0x23,2,0x59,0x00,
+ 0x23,2,0x5A,0x00,
+ 0x23,2,0x5B,0x10,
+ 0x23,2,0x5C,0x14,
+ 0x23,2,0x5D,0x40,
+ 0x23,2,0x5E,0x01,
+ 0x23,2,0x5F,0x02,
+ 0x23,2,0x60,0x40,
+ 0x23,2,0x61,0x03,
+ 0x23,2,0x62,0x04,
+ 0x23,2,0x63,0x7A,
+ 0x23,2,0x64,0x7A,
+ 0x23,2,0x65,0x74,
+ 0x23,2,0x66,0x16,
+ 0x23,2,0x67,0xB4,
+ 0x23,2,0x68,0x16,
+ 0x23,2,0x69,0x7A,
+ 0x23,2,0x6A,0x7A,
+ 0x23,2,0x6B,0x0C,
+ 0x23,2,0x6C,0x00,
+ 0x23,2,0x6D,0x04,
+ 0x23,2,0x6E,0x04,
+ 0x23,2,0x6F,0x88,
+ 0x23,2,0x70,0x00,
+ 0x23,2,0x71,0x00,
+ 0x23,2,0x72,0x06,
+ 0x23,2,0x73,0x7B,
+ 0x23,2,0x74,0x00,
+ 0x23,2,0x75,0xBC,
+ 0x23,2,0x76,0x00,
+ 0x23,2,0x77,0x04,
+ 0x23,2,0x78,0x2C,
+ 0x23,2,0x79,0x00,
+ 0x23,2,0x7A,0x00,
+ 0x23,2,0x7B,0x00,
+ 0x23,2,0x7C,0x00,
+ 0x23,2,0x7D,0x03,
+ 0x23,2,0x7E,0x7B,
+ 0x23,2,0xE0,0x04,//Page4
+ 0x23,2,0x09,0x11,//Set RGBCYC2
+ 0x23,2,0x0E,0x48,
+ 0x23,2,0x2B,0x2B,//ESD Protect
+ 0x23,2,0x2E,0x44,
+ 0x23,2,0xE0,0x00,//Page0
+ 0x23,2,0xE6,0x02,//Watch dog
+ 0x23,2,0xE7,0x0C,
+ 0x05,1,0x11,//sleep out
+ 0xff,120,
+ 0x05,1,0x29,//display on
+ 0x05,1,0x35,
+ 0xFF, 20, /* delay(ms) */
+ 0xFF, 0xFF, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_P070ACB_FT[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xFF, 10, /* delay 10ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xFF, 150, /* delay 150ms */
+ 0xFF, 0xFF, /* ending flag */
+};
+
+static unsigned char ext_init_on_table_TL050FHV02CT[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03,
+ 0x29, 10, 0x90, 0x03, 0x14, 0x09, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00,
+ 0x29, 10, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 12, 0x92, 0x40, 0x0B, 0x0C, 0x0D, 0x0E, 0x00, 0x38, 0x00, 0x10, 0x03, 0x04,
+ 0x29, 9, 0x94, 0x00, 0x08, 0x0B, 0x03, 0xD2, 0x03, 0xD3, 0x0C,
+ 0x29, 17, 0x95, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 3, 0x99, 0x00, 0x00,
+ 0x29, 12, 0x9A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 7, 0x9B, 0x01, 0x38, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 3, 0x9C, 0x00, 0x00,
+ 0x29, 9, 0x9D, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00,
+ 0x29, 3, 0x9E, 0x00, 0x00,
+ 0x29, 11, 0xA0, 0x9F, 0x1F, 0x08, 0x1F, 0x0A, 0x1F, 0x00, 0x1F, 0x14, 0x1F,
+ 0x29, 11, 0xA1, 0x15, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x29, 11, 0xA2, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x29, 11, 0xA4, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x29, 11, 0xA5, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x15,
+ 0x29, 11, 0xA6, 0x1F, 0x14, 0x1F, 0x01, 0x1F, 0x0B, 0x1F, 0x09, 0x1F, 0x1F,
+ 0x29, 11, 0xA7, 0x1F, 0x1F, 0x0B, 0x1F, 0x09, 0x1F, 0x01, 0x1F, 0x15, 0x1F,
+ 0x29, 11, 0xA8, 0x14, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x29, 11, 0xA9, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x29, 11, 0xAB, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+ 0x29, 11, 0xAC, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x14,
+ 0x29, 11, 0xAD, 0x1F, 0x15, 0x1F, 0x00, 0x1F, 0x08, 0x1F, 0x0A, 0x1F, 0x1F,
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00,
+ 0x29, 4, 0xBC, 0x00, 0x00, 0x00,
+ 0x29, 5, 0xB8, 0x01, 0xAF, 0x8F, 0x8F,
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01,
+ 0x29, 17, 0xD1, 0x00, 0x00, 0x00, 0x09, 0x00, 0x1F, 0x00, 0x30, 0x00, 0x3F, 0x00, 0x5D, 0x00, 0x79, 0x00, 0xA7,
+ 0x29, 17, 0xD2, 0x00, 0xCF, 0x01, 0x12, 0x01, 0x49, 0x01, 0xA1, 0x01, 0xEB, 0x01, 0xED, 0x02, 0x2F, 0x02, 0x74,
+ 0x29, 17, 0xD3, 0x02, 0x9F, 0x02, 0xD5, 0x02, 0xFB, 0x03, 0x2C, 0x03, 0x4B, 0x03, 0x73, 0x03, 0x8C, 0x03, 0xA5,
+ 0x29, 5, 0xD4, 0x03, 0xC5, 0x03, 0xFF,
+ 0x29, 17, 0xD5, 0x00, 0x00, 0x00, 0x09, 0x00, 0x1F, 0x00, 0x30, 0x00, 0x3F, 0x00, 0x5D, 0x00, 0x79, 0x00, 0xA7,
+ 0x29, 17, 0xD6, 0x00, 0xCF, 0x01, 0x12, 0x01, 0x49, 0x01, 0xA1, 0x01, 0xEB, 0x01, 0xED, 0x02, 0x2F, 0x02, 0x74,
+ 0x29, 17, 0xD7, 0x02, 0x9F, 0x02, 0xD5, 0x02, 0xFB, 0x03, 0x2C, 0x03, 0x4B, 0x03, 0x73, 0x03, 0x8C, 0x03, 0xA5,
+ 0x29, 5, 0xD8, 0x03, 0xC5, 0x03, 0xFF,
+ 0x29, 17, 0xD9, 0x00, 0x00, 0x00, 0x09, 0x00, 0x1F, 0x00, 0x30, 0x00, 0x3F, 0x00, 0x5D, 0x00, 0x79, 0x00, 0xA7,
+ 0x29, 17, 0xDD, 0x00, 0xCF, 0x01, 0x12, 0x01, 0x49, 0x01, 0xA1, 0x01, 0xEB, 0x01, 0xED, 0x02, 0x2F, 0x02, 0x74,
+ 0x29, 17, 0xDE, 0x02, 0x9F, 0x02, 0xD5, 0x02, 0xFB, 0x03, 0x2C, 0x03, 0x4B, 0x03, 0x73, 0x03, 0x8C, 0x03, 0xA5,
+ 0x29, 5, 0xDF, 0x03, 0xC5, 0x03, 0xFF,
+ 0x29, 17, 0xE0, 0x00, 0x00, 0x00, 0x09, 0x00, 0x1F, 0x00, 0x30, 0x00, 0x3F, 0x00, 0x5D, 0x00, 0x79, 0x00, 0xA7,
+ 0x29, 17, 0xE1, 0x00, 0xCF, 0x01, 0x12, 0x01, 0x49, 0x01, 0xA1, 0x01, 0xEB, 0x01, 0xED, 0x02, 0x2F, 0x02, 0x74,
+ 0x29, 17, 0xE2, 0x02, 0x9F, 0x02, 0xD5, 0x02, 0xFB, 0x03, 0x2C, 0x03, 0x4B, 0x03, 0x73, 0x03, 0x8C, 0x03, 0xA5,
+ 0x29, 5, 0xE3, 0x03, 0xC5, 0x03, 0xFF,
+ 0x29, 17, 0xE4, 0x00, 0x00, 0x00, 0x09, 0x00, 0x1F, 0x00, 0x30, 0x00, 0x3F, 0x00, 0x5D, 0x00, 0x79, 0x00, 0xA7,
+ 0x29, 17, 0xE5, 0x00, 0xCF, 0x01, 0x12, 0x01, 0x49, 0x01, 0xA1, 0x01, 0xEB, 0x01, 0xED, 0x02, 0x2F, 0x02, 0x74,
+ 0x29, 17, 0xE6, 0x02, 0x9F, 0x02, 0xD5, 0x02, 0xFB, 0x03, 0x2C, 0x03, 0x4B, 0x03, 0x73, 0x03, 0x8C, 0x03, 0xA5,
+ 0x29, 5, 0xE7, 0x03, 0xC5, 0x03, 0xFF,
+ 0x29, 17, 0xE8, 0x00, 0x00, 0x00, 0x09, 0x00, 0x1F, 0x00, 0x30, 0x00, 0x3F, 0x00, 0x5D, 0x00, 0x79, 0x00, 0xA7,
+ 0x29, 17, 0xE9, 0x00, 0xCF, 0x01, 0x12, 0x01, 0x49, 0x01, 0xA1, 0x01, 0xEB, 0x01, 0xED, 0x02, 0x2F, 0x02, 0x74,
+ 0x29, 17, 0xEA, 0x02, 0x9F, 0x02, 0xD5, 0x02, 0xFB, 0x03, 0x2C, 0x03, 0x4B, 0x03, 0x73, 0x03, 0x8C, 0x03, 0xA5,
+ 0x29, 5, 0xEB, 0x03, 0xC5, 0x03, 0xFF,
+ 0x29, 4, 0xB0, 0x05, 0x05, 0x05,
+ 0x29, 4, 0xB1, 0x05, 0x05, 0x05,
+ 0x29, 4, 0xB3, 0x10, 0x10, 0x10,
+ 0x29, 4, 0xB4, 0x06, 0x06, 0x06,
+ 0x29, 4, 0xB6, 0x44, 0x44, 0x44,
+ 0x29, 4, 0xB7, 0x34, 0x34, 0x34,
+ 0x29, 4, 0xB8, 0x34, 0x34, 0x34,
+ 0x29, 4, 0xB9, 0x24, 0x24, 0x24,
+ 0x29, 4, 0xBA, 0x24, 0x24, 0x24,
+ 0x29, 4, 0xBC, 0x00, 0x70, 0x00,
+ 0x29, 4, 0xBD, 0x00, 0x70, 0x00,
+ 0x23, 2, 0xBE, 0x50,
+ 0x23, 2, 0x35, 0x00,
+ 0x13, 1, 0x11,
+ 0xff, 200,
+ 0x13, 1, 0x29,
+ 0xff, 200,
+ 0xFF, 0xFF, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_TL050FHV02CT[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xFF, 10, /* delay 10ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xFF, 150, /* delay 150ms */
+ 0xFF, 0xFF, /* ending flag */
+};
+
+#endif
+
diff --git a/board/amlogic/g12a_u211_v1/Kconfig b/board/amlogic/g12a_u211_v1/Kconfig
new file mode 100644
index 0000000..9c38a0d
--- /dev/null
+++ b/board/amlogic/g12a_u211_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_G12A
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "g12a_u211_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "g12a"
+
+config SYS_CONFIG_NAME
+ default "g12a_u211_v1"
+
+endif
diff --git a/board/amlogic/g12a_u211_v1/Makefile b/board/amlogic/g12a_u211_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/g12a_u211_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/g12a_u211_v1/aml-user-key.sig b/board/amlogic/g12a_u211_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/g12a_u211_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/g12a_u211_v1/eth_setup.c b/board/amlogic/g12a_u211_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/g12a_u211_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/g12a_u211_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12a_u211_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..93b0335
--- /dev/null
+++ b/board/amlogic/g12a_u211_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,40 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 681},
+ { 0x1b0001, 691},
+ { 0x1a0002, 701},
+ { 0x190003, 711},
+ { 0x180004, 721},
+ { 0x170005, 731},
+ { 0x160006, 741},
+ { 0x150007, 751},
+ { 0x140008, 761},
+ { 0x130009, 772},
+ { 0x12000a, 782},
+ { 0x11000b, 792},
+ { 0x10000c, 802},
+ { 0x0f000d, 812},
+ { 0x0e000e, 822},
+ { 0x0d000f, 832},
+ { 0x0c0010, 842},
+ { 0x0b0011, 852},
+ { 0x0a0012, 862},
+ { 0x090013, 872},
+ { 0x080014, 882},
+ { 0x070015, 892},
+ { 0x060016, 902},
+ { 0x050017, 912},
+ { 0x040018, 922},
+ { 0x030019, 932},
+ { 0x02001a, 942},
+ { 0x01001b, 952},
+ { 0x00001c, 962}
+};
+
+#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12a_u211_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12a_u211_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..b95d542
--- /dev/null
+++ b/board/amlogic/g12a_u211_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,175 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ /*set gpioH_8 high to power off vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+
+ /*set test_n low to power off vcck*/
+ writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+
+ /*step down ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ /*step up ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+ /*set test_n low to power on vcck*/
+ writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+ _udelay(100);
+
+ /*set gpioH_8 low to power on vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+ _udelay(10000);
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ struct wakeup_gpio_info *gpio;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+
+ p->sources = val;
+ p->gpio_info_count = i;
+
+/*bt wake host*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_18;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ unsigned char adc_key_cnt = 0;
+ init_remote();
+ saradc_enable();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ do {
+ #ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+ if (cec_power_on_check())
+ exit_reason = CEC_WAKEUP;
+ }
+ #endif
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
+ irq[IRQ_VRTC] = 0xFFFFFFFF;
+ exit_reason = RTC_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO2_I) & (0x01 << 18))
+ && (readl(PREG_PAD_GPIO2_O) & (0x01 << 17))
+ && !(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 17)))
+ exit_reason = BT_WAKEUP;
+ }
+
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/g12a_u211_v1/firmware/timing.c b/board/amlogic/g12a_u211_v1/firmware/timing.c
new file mode 100755
index 0000000..4b70ba9
--- /dev/null
+++ b/board/amlogic/g12a_u211_v1/firmware/timing.c
@@ -0,0 +1,587 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] = {
+{
+ /* g12a skt (u209) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1200, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0xffff,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0c0c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) lpddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+{
+ /* g12a Y2 dongle */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28},
+ .dram_rtt_nom_wr_park = {00,00},
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* lpddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR3,
+ .DRAMFreq = {600, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,//0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x00c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 30, //
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x3ff,//0x253,
+ .soc_ac_slew_rate = 0x3ff,//0x253,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 800,//200,
+ .vref_receiver_permil = 700,//875, //700 for drv 40 odt 60 is better ,why?
+ .vref_dram_permil = 500,//875,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {0x10,0x0,0x10-6,0x10-6,0x10-6,0x0,0x0,0x0,0x0,0x0},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 29 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ),
+ [4] = ( 31| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8},
+ .ddr_lpddr34_dq_remap = {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24},
+ //{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6},
+ .dram_rtt_nom_wr_park = {00,00},
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0000001c
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE PWM table */
+#if (VDDEE_VAL == 680)
+ #define VDDEE_VAL_REG 0x001c0000
+#elif (VDDEE_VAL == 690)
+ #define VDDEE_VAL_REG 0x001b0001
+#elif (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x001a0002
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x00190003
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x00180004
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0x00170005
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0x00160006
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0x00150007
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0x00140008
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0x00130009
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0x0012000a
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x0011000b
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x0010000c
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x000f000d
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x000e000e
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x000d000f
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x000c0010
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x000b0011
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x000a0012
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x00090013
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x00080014
+#elif (VDDEE_VAL == 890)
+ #define VDDEE_VAL_REG 0x00070015
+#elif (VDDEE_VAL == 900)
+ #define VDDEE_VAL_REG 0x00060016
+#elif (VDDEE_VAL == 910)
+ #define VDDEE_VAL_REG 0x00050017
+#elif (VDDEE_VAL == 920)
+ #define VDDEE_VAL_REG 0x00040018
+#elif (VDDEE_VAL == 930)
+ #define VDDEE_VAL_REG 0x00030019
+#elif (VDDEE_VAL == 940)
+ #define VDDEE_VAL_REG 0x0002001a
+#elif (VDDEE_VAL == 950)
+ #define VDDEE_VAL_REG 0x0001001b
+#elif (VDDEE_VAL == 960)
+ #define VDDEE_VAL_REG 0x0000001c
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ /* eg: PWM init */
+
+ /* PWM_AO_D */
+ /* VCCK_VAL_REG: check PWM table */
+ {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
+ /* PWM_AO_B */
+ /* VDDEE_VAL_REG: check PWM table */
+ {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable 5V_EN */
+ {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Enable VCCK */
+ {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 31), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Init sys led*/
+ {AO_GPIO_O_EN_N, (0 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (0 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/g12a_u211_v1/g12a_u211_v1.c b/board/amlogic/g12a_u211_v1/g12a_u211_v1.c
new file mode 100644
index 0000000..ff4d97c
--- /dev/null
+++ b/board/amlogic/g12a_u211_v1/g12a_u211_v1.c
@@ -0,0 +1,752 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#ifdef CONFIG_AML_SPIFC
+#include <dm.h>
+#include <amlogic/spifc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+#ifdef ETHERNET_INTERNAL_PHY
+void internalPhyConfig(struct phy_device *phydev)
+{
+}
+
+static int dwmac_meson_cfg_pll(void)
+{
+ writel(0x39C0040A, P_ETH_PLL_CTL0);
+ writel(0x927E0000, P_ETH_PLL_CTL1);
+ writel(0xAC5F49E5, P_ETH_PLL_CTL2);
+ writel(0x00000000, P_ETH_PLL_CTL3);
+ udelay(200);
+ writel(0x19C0040A, P_ETH_PLL_CTL0);
+ return 0;
+}
+
+static int dwmac_meson_cfg_analog(void)
+{
+ /*Analog*/
+ writel(0x20200000, P_ETH_PLL_CTL5);
+ writel(0x0000c002, P_ETH_PLL_CTL6);
+ writel(0x00000023, P_ETH_PLL_CTL7);
+
+ return 0;
+}
+
+static int dwmac_meson_cfg_ctrl(void)
+{
+ /*config phyid should between a 0~0xffffffff*/
+ /*please don't use 44000181, this has been used by internal phy*/
+ writel(0x33000180, P_ETH_PHY_CNTL0);
+
+ /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
+ writel(0x260, P_ETH_PHY_CNTL2);
+
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ writel(0x34043, P_ETH_PHY_CNTL1);
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ return 0;
+}
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 1;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 9;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ dwmac_meson_cfg_pll();
+ dwmac_meson_cfg_analog();
+ dwmac_meson_cfg_ctrl();
+
+ /* eth core clock */
+ setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
+ /* eth phy clock */
+ setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
+
+ /* eth phy pll, clk50m */
+ setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+
+static int dwmac_meson_cfg_drive_strength(void)
+{
+ writel(0xaaaaaaa5, P_PAD_DS_REG4A);
+ return 0;
+}
+
+static void setup_net_chip_ext(void)
+{
+ eth_aml_reg0_t eth_reg0;
+ writel(0x11111111, P_PERIPHS_PIN_MUX_6);
+ writel(0x111111, P_PERIPHS_PIN_MUX_7);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_ETHERNET_NONE
+ return 0;
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+ dwmac_meson_cfg_drive_strength();
+ setup_net_chip_ext();
+#endif
+#ifdef ETHERNET_INTERNAL_PHY
+ setup_net_chip();
+#endif
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ /* check card detect */
+ clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM 1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_USB_GPIO_PWR,
+ CONFIG_USB_GPIO_PWR_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_USB_GPIO_PWR);
+ return;
+ }
+
+ if (is_power_on) {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
+ } else {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+ .usb_phy2_pll_base_addr = {
+ CONFIG_USB_PHY_20,
+ CONFIG_USB_PHY_21,
+ }
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 280*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xfffff << 12);
+ if (enable)
+ val |= 0x33333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~(0xf << 24);
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xf6000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+ //As NOT NEED other board init If USB BOOT MODE
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+ board_usb_pll_disable(&g_usb_config_GXL_skt);
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#if 0
+ aml_pwm_cal_init(0);
+#endif//
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+/* set dts props */
+void aml_config_dtb(void)
+{
+ cpu_id_t cpuid = get_cpu_id();
+
+ run_command("fdt address $dtb_mem_addr", 0);
+ printf("%s %d\n", __func__, __LINE__);
+ if (cpuid.chip_rev == 0xA) {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /emmc/emmc co_phase <0x2>", 0);
+ run_command("fdt rm /emmc/emmc caps2", 0);
+ run_command("fdt set /emmc/emmc f_max <0x02625a00>", 0);
+
+ run_command("fdt set /sdio status okay", 0);
+ run_command("fdt set /sd1 status okay", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux1 drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength <2>", 0);
+ run_command("fdt set /pinctrl@ff634480/sdio_all_pins/mux drive-strength <1>", 0);
+ /* debug */
+ run_command("fdt print /emmc/emmc co_phase", 0);
+ run_command("fdt print /emmc/emmc caps2", 0);
+ run_command("fdt print /emmc/emmc f_max", 0);
+
+ run_command("fdt print /sdio status", 0);
+ run_command("fdt print /sd1 status ", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux1 drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sdio_all_pins/mux drive-strength", 0);
+ } else {
+
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /emmc/emmc co_phase <0x3>", 0);
+ run_command("fdt set /sdio status disabled", 0);
+ run_command("fdt set /sd2 status okay", 0);
+ /* debug */
+ run_command("fdt print /emmc/emmc co_phase", 0);
+ run_command("fdt print /emmc/emmc caps2", 0);
+ run_command("fdt print /emmc/emmc f_max", 0);
+ run_command("fdt print /sdio status", 0);
+ run_command("fdt print /sd2 status", 0);
+ }
+
+ return;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+#ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+#endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ /**/
+ aml_config_dtb();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 1 p321 v1
+ * hwid = 2 p321 v2
+ */
+ unsigned int hwid = 1;
+ char loc_name[64] = {0};
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+
+ switch (hwid) {
+ case 1:
+ strcpy(loc_name, "txl_p321_v1\0");
+ break;
+ case 2:
+ strcpy(loc_name, "txl_p321_v2\0");
+ break;
+ default:
+ strcpy(loc_name, "txl_p321_v1");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/g12a_u211_v1/lcd.c b/board/amlogic/g12a_u211_v1/lcd.c
new file mode 100755
index 0000000..4a32602
--- /dev/null
+++ b/board/amlogic/g12a_u211_v1/lcd.c
@@ -0,0 +1,460 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_9", /* panel rst */
+ "GPIOZ_8", /* panel power */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+#if 1
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_4", /* BL_EN */
+ "GPIOH_5", /* BL_PWM */
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,1,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOH_5
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xff, 20,
+ 0x05, 1, 0x29,
+ 0xff, 20,
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xff, 10,
+ 0x05, 1, 0x10,
+ 0xff, 10,
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_clk_path = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0xff, //ending flag
+};
+
+static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff,0xff, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 3,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .cmd_size = 9,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 1,
+ .name = "mipi_TV070WSM",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 2,
+ .name = "mipi_P070ACB",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "none",
+ .type = BL_EXTERN_MAX,
+ .i2c_addr = 0xff,
+ .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+ .dim_min = 10,
+ .dim_max = 255,
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/g12a_u212_v1/Kconfig b/board/amlogic/g12a_u212_v1/Kconfig
new file mode 100755
index 0000000..b2df95c
--- /dev/null
+++ b/board/amlogic/g12a_u212_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_G12A
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "g12a_u212_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "g12a"
+
+config SYS_CONFIG_NAME
+ default "g12a_u212_v1"
+
+endif
diff --git a/board/amlogic/g12a_u212_v1/Makefile b/board/amlogic/g12a_u212_v1/Makefile
new file mode 100755
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/g12a_u212_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/g12a_u212_v1/aml-user-key.sig b/board/amlogic/g12a_u212_v1/aml-user-key.sig
new file mode 100755
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/g12a_u212_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/g12a_u212_v1/eth_setup.c b/board/amlogic/g12a_u212_v1/eth_setup.c
new file mode 100755
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/g12a_u212_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/g12a_u212_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12a_u212_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100755
index 0000000..93b0335
--- /dev/null
+++ b/board/amlogic/g12a_u212_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,40 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 681},
+ { 0x1b0001, 691},
+ { 0x1a0002, 701},
+ { 0x190003, 711},
+ { 0x180004, 721},
+ { 0x170005, 731},
+ { 0x160006, 741},
+ { 0x150007, 751},
+ { 0x140008, 761},
+ { 0x130009, 772},
+ { 0x12000a, 782},
+ { 0x11000b, 792},
+ { 0x10000c, 802},
+ { 0x0f000d, 812},
+ { 0x0e000e, 822},
+ { 0x0d000f, 832},
+ { 0x0c0010, 842},
+ { 0x0b0011, 852},
+ { 0x0a0012, 862},
+ { 0x090013, 872},
+ { 0x080014, 882},
+ { 0x070015, 892},
+ { 0x060016, 902},
+ { 0x050017, 912},
+ { 0x040018, 922},
+ { 0x030019, 932},
+ { 0x02001a, 942},
+ { 0x01001b, 952},
+ { 0x00001c, 962}
+};
+
+#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12a_u212_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12a_u212_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100755
index 0000000..e3918ab
--- /dev/null
+++ b/board/amlogic/g12a_u212_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,165 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ /*set gpioH_8 high to power off vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+
+ /*set test_n low to power off vcck*/
+ writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+
+ /*step down ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ /*step up ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+ /*set test_n low to power on vcck*/
+ writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+ _udelay(100);
+
+ /*set gpioH_8 low to power on vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+ _udelay(10000);
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ struct wakeup_gpio_info *gpio;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ BT_WAKEUP_SRC | CECB_WAKEUP_SRC);
+
+ p->sources = val;
+ p->gpio_info_count = i;
+
+/*bt wake host*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_18;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO1_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ do {
+ #ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+ if (cec_power_on_check())
+ exit_reason = CEC_WAKEUP;
+ }
+ #endif
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
+ irq[IRQ_VRTC] = 0xFFFFFFFF;
+ exit_reason = RTC_WAKEUP;
+ }
+
+ if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
+ irq[IRQ_GPIO1] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO2_I) & (0x01 << 18))
+ && (readl(PREG_PAD_GPIO2_O) & (0x01 << 17))
+ && !(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 17)))
+ exit_reason = BT_WAKEUP;
+ }
+
+ if (irq[IRQ_ETH_PTM] == IRQ_ETH_PMT_NUM) {
+ irq[IRQ_ETH_PTM]= 0xFFFFFFFF;
+ exit_reason = ETH_PMT_WAKEUP;
+ }
+
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/g12a_u212_v1/firmware/timing.c b/board/amlogic/g12a_u212_v1/firmware/timing.c
new file mode 100755
index 0000000..4b70ba9
--- /dev/null
+++ b/board/amlogic/g12a_u212_v1/firmware/timing.c
@@ -0,0 +1,587 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] = {
+{
+ /* g12a skt (u209) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1200, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0xffff,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0c0c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) lpddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+{
+ /* g12a Y2 dongle */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28},
+ .dram_rtt_nom_wr_park = {00,00},
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* lpddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR3,
+ .DRAMFreq = {600, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,//0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x00c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 30, //
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x3ff,//0x253,
+ .soc_ac_slew_rate = 0x3ff,//0x253,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 800,//200,
+ .vref_receiver_permil = 700,//875, //700 for drv 40 odt 60 is better ,why?
+ .vref_dram_permil = 500,//875,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {0x10,0x0,0x10-6,0x10-6,0x10-6,0x0,0x0,0x0,0x0,0x0},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 29 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ),
+ [4] = ( 31| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8},
+ .ddr_lpddr34_dq_remap = {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24},
+ //{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6},
+ .dram_rtt_nom_wr_park = {00,00},
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0000001c
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE PWM table */
+#if (VDDEE_VAL == 680)
+ #define VDDEE_VAL_REG 0x001c0000
+#elif (VDDEE_VAL == 690)
+ #define VDDEE_VAL_REG 0x001b0001
+#elif (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x001a0002
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x00190003
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x00180004
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0x00170005
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0x00160006
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0x00150007
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0x00140008
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0x00130009
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0x0012000a
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x0011000b
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x0010000c
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x000f000d
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x000e000e
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x000d000f
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x000c0010
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x000b0011
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x000a0012
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x00090013
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x00080014
+#elif (VDDEE_VAL == 890)
+ #define VDDEE_VAL_REG 0x00070015
+#elif (VDDEE_VAL == 900)
+ #define VDDEE_VAL_REG 0x00060016
+#elif (VDDEE_VAL == 910)
+ #define VDDEE_VAL_REG 0x00050017
+#elif (VDDEE_VAL == 920)
+ #define VDDEE_VAL_REG 0x00040018
+#elif (VDDEE_VAL == 930)
+ #define VDDEE_VAL_REG 0x00030019
+#elif (VDDEE_VAL == 940)
+ #define VDDEE_VAL_REG 0x0002001a
+#elif (VDDEE_VAL == 950)
+ #define VDDEE_VAL_REG 0x0001001b
+#elif (VDDEE_VAL == 960)
+ #define VDDEE_VAL_REG 0x0000001c
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ /* eg: PWM init */
+
+ /* PWM_AO_D */
+ /* VCCK_VAL_REG: check PWM table */
+ {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
+ /* PWM_AO_B */
+ /* VDDEE_VAL_REG: check PWM table */
+ {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable 5V_EN */
+ {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Enable VCCK */
+ {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 31), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Init sys led*/
+ {AO_GPIO_O_EN_N, (0 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (0 << 11), (1 << 11), 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/g12a_u212_v1/g12a_u212_v1.c b/board/amlogic/g12a_u212_v1/g12a_u212_v1.c
new file mode 100755
index 0000000..3d6c4f5
--- /dev/null
+++ b/board/amlogic/g12a_u212_v1/g12a_u212_v1.c
@@ -0,0 +1,796 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#endif
+#ifdef CONFIG_SYS_I2C_MESON
+#include <amlogic/i2c.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#ifdef CONFIG_AML_SPIFC
+#include <amlogic/spifc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+#ifdef ETHERNET_INTERNAL_PHY
+void internalPhyConfig(struct phy_device *phydev)
+{
+}
+
+static int dwmac_meson_cfg_pll(void)
+{
+ writel(0x39C0040A, P_ETH_PLL_CTL0);
+ writel(0x927E0000, P_ETH_PLL_CTL1);
+ writel(0xAC5F49E5, P_ETH_PLL_CTL2);
+ writel(0x00000000, P_ETH_PLL_CTL3);
+ udelay(200);
+ writel(0x19C0040A, P_ETH_PLL_CTL0);
+ return 0;
+}
+
+static int dwmac_meson_cfg_analog(void)
+{
+ /*Analog*/
+ writel(0x20200000, P_ETH_PLL_CTL5);
+ writel(0x0000c002, P_ETH_PLL_CTL6);
+ writel(0x00000023, P_ETH_PLL_CTL7);
+
+ return 0;
+}
+
+static int dwmac_meson_cfg_ctrl(void)
+{
+ /*config phyid should between a 0~0xffffffff*/
+ /*please don't use 44000181, this has been used by internal phy*/
+ writel(0x33000180, P_ETH_PHY_CNTL0);
+
+ /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
+ writel(0x260, P_ETH_PHY_CNTL2);
+
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ writel(0x34043, P_ETH_PHY_CNTL1);
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ return 0;
+}
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 1;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 9;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ dwmac_meson_cfg_pll();
+ dwmac_meson_cfg_analog();
+ dwmac_meson_cfg_ctrl();
+
+ /* eth core clock */
+ setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
+ /* eth phy clock */
+ setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
+
+ /* eth phy pll, clk50m */
+ setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+
+static int dwmac_meson_cfg_drive_strength(void)
+{
+ writel(0xaaaaaaa5, P_PAD_DS_REG4A);
+ return 0;
+}
+
+static void setup_net_chip_ext(void)
+{
+ eth_aml_reg0_t eth_reg0;
+ writel(0x11111111, P_PERIPHS_PIN_MUX_6);
+ writel(0x111111, P_PERIPHS_PIN_MUX_7);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_ETHERNET_NONE
+ return 0;
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+ dwmac_meson_cfg_drive_strength();
+ setup_net_chip_ext();
+#endif
+#ifdef ETHERNET_INTERNAL_PHY
+ setup_net_chip();
+#endif
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ /* check card detect */
+ clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM 1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_USB_GPIO_PWR,
+ CONFIG_USB_GPIO_PWR_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_USB_GPIO_PWR);
+ return;
+ }
+
+ if (is_power_on) {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
+ } else {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+ .usb_phy2_pll_base_addr = {
+ CONFIG_USB_PHY_20,
+ CONFIG_USB_PHY_21,
+ }
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 280*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xfffff << 12);
+ if (enable)
+ val |= 0x33333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~(0xf << 24);
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xf6000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+extern void aml_pwm_cal_init(int mode);
+
+#ifdef CONFIG_SYS_I2C_MESON
+static const struct meson_i2c_platdata i2c_data[] = {
+ { 0, 0xffd1f000, 166666666, 3, 15, 100000 },
+ { 1, 0xffd1e000, 166666666, 3, 15, 100000 },
+ { 2, 0xffd1d000, 166666666, 3, 15, 100000 },
+ { 3, 0xffd1c000, 166666666, 3, 15, 100000 },
+ { 4, 0xff805000, 166666666, 3, 15, 100000 },
+};
+
+U_BOOT_DEVICES(meson_i2cs) = {
+ { "i2c_meson", &i2c_data[0] },
+ { "i2c_meson", &i2c_data[1] },
+ { "i2c_meson", &i2c_data[2] },
+ { "i2c_meson", &i2c_data[3] },
+ { "i2c_meson", &i2c_data[4] },
+};
+
+/*
+ *GPIOAO_10//I2C_SDA_AO
+ *GPIOAO_11//I2C_SCK_AO
+ *pinmux configuration seperated with i2c controller configuration
+ * config it when you use
+ */
+void set_i2c_ao_pinmux(void)
+{
+ return;
+}
+#endif /*end CONFIG_SYS_I2C_MESON*/
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+ //As NOT NEED other board init If USB BOOT MODE
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+ board_usb_pll_disable(&g_usb_config_GXL_skt);
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#if 0
+ aml_pwm_cal_init(0);
+#endif//
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+#ifdef CONFIG_SYS_I2C_MESON
+ set_i2c_ao_pinmux();
+#endif
+
+ return 0;
+}
+
+/* set dts props */
+void aml_config_dtb(void)
+{
+ cpu_id_t cpuid = get_cpu_id();
+
+ run_command("fdt address $dtb_mem_addr", 0);
+ printf("%s %d\n", __func__, __LINE__);
+ if (cpuid.chip_rev == 0xA) {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /emmc/emmc co_phase <0x2>", 0);
+ run_command("fdt rm /emmc/emmc caps2", 0);
+ run_command("fdt set /emmc/emmc f_max <0x02625a00>", 0);
+
+ run_command("fdt set /sdio status okay", 0);
+ run_command("fdt set /sd1 status okay", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sd_all_pins/mux1 drive-strength <1>", 0);
+ run_command("fdt set /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength <2>", 0);
+ run_command("fdt set /pinctrl@ff634480/sdio_all_pins/mux drive-strength <1>", 0);
+ /* debug */
+ run_command("fdt print /emmc/emmc co_phase", 0);
+ run_command("fdt print /emmc/emmc caps2", 0);
+ run_command("fdt print /emmc/emmc f_max", 0);
+
+ run_command("fdt print /sdio status", 0);
+ run_command("fdt print /sd1 status ", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_clk_cmd_pins/mux1 drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sd_all_pins/mux1 drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sdio_clk_cmd_pins/mux drive-strength", 0);
+ run_command("fdt print /pinctrl@ff634480/sdio_all_pins/mux drive-strength", 0);
+ } else {
+
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /emmc/emmc co_phase <0x3>", 0);
+ run_command("fdt set /sdio status disabled", 0);
+ run_command("fdt set /sd2 status okay", 0);
+ /* debug */
+ run_command("fdt print /emmc/emmc co_phase", 0);
+ run_command("fdt print /emmc/emmc caps2", 0);
+ run_command("fdt print /emmc/emmc f_max", 0);
+ run_command("fdt print /sdio status", 0);
+ run_command("fdt print /sd2 status", 0);
+ }
+
+ return;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+#ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+#endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ /**/
+ aml_config_dtb();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 1 p321 v1
+ * hwid = 2 p321 v2
+ */
+ unsigned int hwid = 1;
+ char loc_name[64] = {0};
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+
+ switch (hwid) {
+ case 1:
+ strcpy(loc_name, "txl_p321_v1\0");
+ break;
+ case 2:
+ strcpy(loc_name, "txl_p321_v2\0");
+ break;
+ default:
+ strcpy(loc_name, "txl_p321_v1");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+ "lock",
+
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/g12a_u212_v1/lcd.c b/board/amlogic/g12a_u212_v1/lcd.c
new file mode 100755
index 0000000..2f352f6
--- /dev/null
+++ b/board/amlogic/g12a_u212_v1/lcd.c
@@ -0,0 +1,475 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_9", /* panel rst */
+ "GPIOZ_8", /* panel power */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+#if 1
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_4", /* BL_EN */
+ "GPIOH_5", /* BL_PWM */
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,1,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOH_5
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xfd, 1, 20,
+ 0x05, 1, 0x29,
+ 0xfd, 1, 20,
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xfd, 1, 10,
+ 0x05, 1, 0x10,
+ 0xfd, 1, 10,
+ 0xff, 0, //ending
+};
+
+static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff, 0, //ending
+};
+
+static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff, 0, //ending
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_clk_path = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0, //ending flag
+};
+
+static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 3,
+ .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_on_cnt = sizeof(ext_init_on_table),
+ .table_init_off = ext_init_off_table,
+ .table_init_off_cnt = sizeof(ext_init_off_table),
+ },
+ {
+ .index = 1,
+ .name = "mipi_TV070WSM",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_on_cnt = sizeof(ext_init_on_table),
+ .table_init_off = ext_init_off_table,
+ .table_init_off_cnt = sizeof(ext_init_off_table),
+ },
+ {
+ .index = 2,
+ .name = "mipi_P070ACB",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_on_cnt = sizeof(ext_init_on_table),
+ .table_init_off = ext_init_off_table,
+ .table_init_off_cnt = sizeof(ext_init_off_table),
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX];
+static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX];
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "none",
+ .type = BL_EXTERN_MAX,
+ .i2c_addr = 0xff,
+ .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+ .dim_min = 10,
+ .dim_max = 255,
+
+ .init_loaded = 0,
+ .cmd_size = 0xff,
+ .init_on = bl_ext_init_on,
+ .init_off = bl_ext_init_off,
+ .init_on_cnt = sizeof(bl_ext_init_on),
+ .init_off_cnt = sizeof(bl_ext_init_off),
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/g12a_u220_v1/Kconfig b/board/amlogic/g12a_u220_v1/Kconfig
new file mode 100644
index 0000000..2c2046a
--- /dev/null
+++ b/board/amlogic/g12a_u220_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_G12A
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "g12a_u220_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "g12a"
+
+config SYS_CONFIG_NAME
+ default "g12a_u220_v1"
+
+endif
diff --git a/board/amlogic/g12a_u220_v1/Makefile b/board/amlogic/g12a_u220_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/g12a_u220_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/g12a_u220_v1/aml-user-key.sig b/board/amlogic/g12a_u220_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/g12a_u220_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/g12a_u220_v1/eth_setup.c b/board/amlogic/g12a_u220_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/g12a_u220_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/g12a_u220_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12a_u220_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..93b0335
--- /dev/null
+++ b/board/amlogic/g12a_u220_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,40 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 681},
+ { 0x1b0001, 691},
+ { 0x1a0002, 701},
+ { 0x190003, 711},
+ { 0x180004, 721},
+ { 0x170005, 731},
+ { 0x160006, 741},
+ { 0x150007, 751},
+ { 0x140008, 761},
+ { 0x130009, 772},
+ { 0x12000a, 782},
+ { 0x11000b, 792},
+ { 0x10000c, 802},
+ { 0x0f000d, 812},
+ { 0x0e000e, 822},
+ { 0x0d000f, 832},
+ { 0x0c0010, 842},
+ { 0x0b0011, 852},
+ { 0x0a0012, 862},
+ { 0x090013, 872},
+ { 0x080014, 882},
+ { 0x070015, 892},
+ { 0x060016, 902},
+ { 0x050017, 912},
+ { 0x040018, 922},
+ { 0x030019, 932},
+ { 0x02001a, 942},
+ { 0x01001b, 952},
+ { 0x00001c, 962}
+};
+
+#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12a_u220_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12a_u220_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..08d4649
--- /dev/null
+++ b/board/amlogic/g12a_u220_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,192 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ /*set gpioH_8 low to power off vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+
+ /*set test_n low to power off vcck & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+
+ /*step down ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ /*step up ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+ /*set test_n low to power on vcck & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+ _udelay(100);
+
+ /*set gpioH_8 low to power on vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+ _udelay(10000);
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ struct wakeup_gpio_info *gpio;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC | ETH_PHY_GPIO_SRC);
+
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_3;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+ /*Eth:GPIOZ_14*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = ETH_PHY_GPIO_SRC;
+ gpio->gpio_in_idx = GPIOZ_14;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ unsigned char adc_key_cnt = 0;
+ init_remote();
+ saradc_enable();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ do {
+ #ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+ if (cec_power_on_check())
+ exit_reason = CEC_WAKEUP;
+ }
+ #endif
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
+ irq[IRQ_VRTC] = 0xFFFFFFFF;
+ exit_reason = RTC_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<3)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 14))
+ && (readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 14)))
+ exit_reason = ETH_PHY_GPIO;
+ }
+
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/g12a_u220_v1/firmware/timing.c b/board/amlogic/g12a_u220_v1/firmware/timing.c
new file mode 100755
index 0000000..40d6a33
--- /dev/null
+++ b/board/amlogic/g12a_u220_v1/firmware/timing.c
@@ -0,0 +1,1008 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] = {
+{
+ /* g12a skt (u209) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1200, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0xffff,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0c0c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a u220 lpddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1200, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 48,//40,
+ .cs_drv_ohm = 48,//40,
+ .ac_drv_ohm = 48,//40,
+
+ /*
+ .soc_data_drv_ohm_p = 40,//30,//30,
+ .soc_data_drv_ohm_n = 40,//30,//30,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,//40,//60,// 120,//120,
+ .dram_data_drv_ohm = 40,// 48, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,// 48,//48,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 0,///1, 1/3vddq 0 2/5 vddq
+ */
+ ///*
+ .soc_data_drv_ohm_p = 48,//30,//30,
+ .soc_data_drv_ohm_n = 48,//30,//30,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 48,//40,//60,// 120,//120,
+ .dram_data_drv_ohm = 48,// 48, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 48,// 48,//48,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ //*/
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 14,13,12,15,8,9,11,10, 20,21,22,23,16,17,19,18, 24,25,28,26,31,30,27,29},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+{
+ /* g12a u220 lpddr4 repair mode */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1200, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 48,//40,
+ .cs_drv_ohm = 48,//40,
+ .ac_drv_ohm = 48,//40,
+
+ /*
+ .soc_data_drv_ohm_p = 40,//30,//30,
+ .soc_data_drv_ohm_n = 40,//30,//30,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,//40,//60,// 120,//120,
+ .dram_data_drv_ohm = 40,// 48, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,// 48,//48,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 0,///1, 1/3vddq 0 2/5 vddq
+ */
+ ///*
+ .soc_data_drv_ohm_p = 48,//30,//30,
+ .soc_data_drv_ohm_n = 48,//30,//30,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 48,//40,//60,// 120,//120,
+ .dram_data_drv_ohm = 48,// 48, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 48,// 48,//48,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ //*/
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 14,13,12,15,8,9,11,10, 20,21,22,23,16,17,19,18, 24,25,28,26,31,30,27,29},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+/*
+ .slt_test_function = { DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING, 0},
+ .dfi_hwtmrl = 7 ,
+
+ .ac_trace_delay = {
+ 32 ,
+ 32 ,
+ 30 ,
+ 29 ,
+ 0 ,
+ 32 ,
+ 32 ,
+ 29 ,
+ 27 ,
+ 0 ,
+ } ,
+
+ .write_dqs_delay = {
+ 144 ,
+ 144 ,
+ 160 ,
+ 160 ,
+ 160 ,
+ 160 ,
+ 140 ,
+ 140 ,
+ 142 ,
+ 142 ,
+ 160 ,
+ 160 ,
+ 160 ,
+ 160 ,
+ 142 ,
+ 142 ,
+ } ,
+
+ .read_dqs_delay = {
+ 11 ,
+ 2 ,
+ 11 ,
+ 0 ,
+ 13 ,
+ 1 ,
+ 13 ,
+ 5 ,
+ 13 ,
+ 3 ,
+ 10 ,
+ 2 ,
+ 11 ,
+ 1 ,
+ 10 ,
+ 5 ,
+ } ,
+
+ .write_dq_bit_delay = {
+ 77 ,
+ 75 ,
+ 80 ,
+ 79 ,
+ 84 ,
+ 84 ,
+ 84 ,
+ 83 ,
+ 79 ,
+ 60 ,
+ 62 ,
+ 67 ,
+ 65 ,
+ 69 ,
+ 69 ,
+ 70 ,
+ 70 ,
+ 65 ,
+ 60 ,
+ 61 ,
+ 67 ,
+ 65 ,
+ 69 ,
+ 69 ,
+ 69 ,
+ 69 ,
+ 65 ,
+ 75 ,
+ 74 ,
+ 72 ,
+ 79 ,
+ 74 ,
+ 80 ,
+ 79 ,
+ 79 ,
+ 76 ,
+ 76 ,
+ 73 ,
+ 79 ,
+ 77 ,
+ 82 ,
+ 82 ,
+ 82 ,
+ 82 ,
+ 78 ,
+ 61 ,
+ 63 ,
+ 67 ,
+ 65 ,
+ 70 ,
+ 70 ,
+ 71 ,
+ 70 ,
+ 66 ,
+ 61 ,
+ 63 ,
+ 68 ,
+ 66 ,
+ 71 ,
+ 71 ,
+ 70 ,
+ 70 ,
+ 66 ,
+ 80 ,
+ 78 ,
+ 77 ,
+ 82 ,
+ 78 ,
+ 84 ,
+ 84 ,
+ 84 ,
+ 80 ,
+ } ,
+
+ .read_dq_bit_delay = {
+ 4 ,
+ 0 ,
+ 18 ,
+ 12 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 10 ,
+ 8 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 4 ,
+ 14 ,
+ 12 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 10 ,
+ 2 ,
+ 0 ,
+ 18 ,
+ 0 ,
+ 10 ,
+ 10 ,
+ 10 ,
+ 0 ,
+ 6 ,
+ 0 ,
+ 16 ,
+ 14 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 2 ,
+ 0 ,
+ 10 ,
+ 10 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 2 ,
+ 12 ,
+ 12 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 10 ,
+ 4 ,
+ 0 ,
+ 16 ,
+ 0 ,
+ 10 ,
+ 10 ,
+ 10 ,
+ 0 ,
+ } ,
+
+ .read_dqs_gate_delay = {
+ 375 ,
+ 375 ,
+ 367 ,
+ 367 ,
+ 363 ,
+ 363 ,
+ 371 ,
+ 371 ,
+ 379 ,
+ 379 ,
+ 371 ,
+ 371 ,
+ 371 ,
+ 371 ,
+ 381 ,
+ 381 ,
+ } ,
+
+ .dq_dqs_delay_flag = DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS|DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ|
+ DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS|DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ
+ ,
+ */
+///*
+ .read_dqs_delay = {
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ 0x82 ,
+ },
+ .write_dq_bit_delay = {
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ 0x8002 ,
+ } ,
+
+ .dq_dqs_delay_flag = DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS | DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ,
+ //*/
+},
+
+{
+ /* g12a Y2 dongle */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 14,13,12,15,8,9,11,10, 20,21,22,23,16,17,19,18, 24,25,28,26,31,30,27,29},
+ .dram_rtt_nom_wr_park = {00,00},
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* lpddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR3,
+ .DRAMFreq = {600, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,//0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x00c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 30, //
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x3ff,//0x253,
+ .soc_ac_slew_rate = 0x3ff,//0x253,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 800,//200,
+ .vref_receiver_permil = 700,//875, //700 for drv 40 odt 60 is better ,why?
+ .vref_dram_permil = 500,//875,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {0x10,0x0,0x10-6,0x10-6,0x10-6,0x0,0x0,0x0,0x0,0x0},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 29 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ),
+ [4] = ( 31| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8},
+ .ddr_lpddr34_dq_remap = {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24},
+ //{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6},
+ .dram_rtt_nom_wr_park = {00,00},
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0000001c
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE PWM table */
+#if (VDDEE_VAL == 680)
+ #define VDDEE_VAL_REG 0x001c0000
+#elif (VDDEE_VAL == 690)
+ #define VDDEE_VAL_REG 0x001b0001
+#elif (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x001a0002
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x00190003
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x00180004
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0x00170005
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0x00160006
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0x00150007
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0x00140008
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0x00130009
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0x0012000a
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x0011000b
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x0010000c
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x000f000d
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x000e000e
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x000d000f
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x000c0010
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x000b0011
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x000a0012
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x00090013
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x00080014
+#elif (VDDEE_VAL == 890)
+ #define VDDEE_VAL_REG 0x00070015
+#elif (VDDEE_VAL == 900)
+ #define VDDEE_VAL_REG 0x00060016
+#elif (VDDEE_VAL == 910)
+ #define VDDEE_VAL_REG 0x00050017
+#elif (VDDEE_VAL == 920)
+ #define VDDEE_VAL_REG 0x00040018
+#elif (VDDEE_VAL == 930)
+ #define VDDEE_VAL_REG 0x00030019
+#elif (VDDEE_VAL == 940)
+ #define VDDEE_VAL_REG 0x0002001a
+#elif (VDDEE_VAL == 950)
+ #define VDDEE_VAL_REG 0x0001001b
+#elif (VDDEE_VAL == 960)
+ #define VDDEE_VAL_REG 0x0000001c
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ /* eg: PWM init */
+
+ /* PWM_AO_D */
+ /* VCCK_VAL_REG: check PWM table */
+ {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
+ /* PWM_AO_B */
+ /* VDDEE_VAL_REG: check PWM table */
+ {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable 5V_EN */
+ {GPIO_O_EN_N_REG3, (1 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Enable VCCK */
+ {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 31), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/g12a_u220_v1/g12a_u220_v1.c b/board/amlogic/g12a_u220_v1/g12a_u220_v1.c
new file mode 100644
index 0000000..b21bd7f
--- /dev/null
+++ b/board/amlogic/g12a_u220_v1/g12a_u220_v1.c
@@ -0,0 +1,698 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#ifdef CONFIG_AML_SPIFC
+#include <dm.h>
+#include <amlogic/spifc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+#ifdef ETHERNET_INTERNAL_PHY
+void internalPhyConfig(struct phy_device *phydev)
+{
+}
+
+static int dwmac_meson_cfg_pll(void)
+{
+ writel(0x39C0040A, P_ETH_PLL_CTL0);
+ writel(0x927E0000, P_ETH_PLL_CTL1);
+ writel(0xAC5F49E5, P_ETH_PLL_CTL2);
+ writel(0x00000000, P_ETH_PLL_CTL3);
+ udelay(200);
+ writel(0x19C0040A, P_ETH_PLL_CTL0);
+ return 0;
+}
+
+static int dwmac_meson_cfg_analog(void)
+{
+ /*Analog*/
+ writel(0x20200000, P_ETH_PLL_CTL5);
+ writel(0x0000c002, P_ETH_PLL_CTL6);
+ writel(0x00000023, P_ETH_PLL_CTL7);
+
+ return 0;
+}
+
+static int dwmac_meson_cfg_ctrl(void)
+{
+ /*config phyid should between a 0~0xffffffff*/
+ /*please don't use 44000181, this has been used by internal phy*/
+ writel(0x33000180, P_ETH_PHY_CNTL0);
+
+ /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
+ writel(0x260, P_ETH_PHY_CNTL2);
+
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ writel(0x34043, P_ETH_PHY_CNTL1);
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ return 0;
+}
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 1;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 9;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ dwmac_meson_cfg_pll();
+ dwmac_meson_cfg_analog();
+ dwmac_meson_cfg_ctrl();
+
+ /* eth core clock */
+ setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
+ /* eth phy clock */
+ setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
+
+ /* eth phy pll, clk50m */
+ setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+
+static int dwmac_meson_cfg_drive_strength(void)
+{
+ writel(0xaaaaaaa5, P_PAD_DS_REG4A);
+ return 0;
+}
+
+static void setup_net_chip_ext(void)
+{
+ eth_aml_reg0_t eth_reg0;
+ writel(0x11111111, P_PERIPHS_PIN_MUX_6);
+ writel(0x111111, P_PERIPHS_PIN_MUX_7);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_ETHERNET_NONE
+ return 0;
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+ dwmac_meson_cfg_drive_strength();
+ setup_net_chip_ext();
+#endif
+#ifdef ETHERNET_INTERNAL_PHY
+ setup_net_chip();
+#endif
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ /* check card detect */
+ clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM 1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_USB_GPIO_PWR,
+ CONFIG_USB_GPIO_PWR_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_USB_GPIO_PWR);
+ return;
+ }
+
+ if (is_power_on) {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
+ } else {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+ .usb_phy2_pll_base_addr = {
+ CONFIG_USB_PHY_20,
+ CONFIG_USB_PHY_21,
+ }
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 280*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xfffff << 12);
+ if (enable)
+ val |= 0x33333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~(0xf << 24);
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xf6000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+ //As NOT NEED other board init If USB BOOT MODE
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+ board_usb_pll_disable(&g_usb_config_GXL_skt);
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#if 0
+ aml_pwm_cal_init(0);
+#endif//
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+#ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+#endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 1 p321 v1
+ * hwid = 2 p321 v2
+ */
+ unsigned int hwid = 1;
+ char loc_name[64] = {0};
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+
+ switch (hwid) {
+ case 1:
+ strcpy(loc_name, "txl_p321_v1\0");
+ break;
+ case 2:
+ strcpy(loc_name, "txl_p321_v2\0");
+ break;
+ default:
+ strcpy(loc_name, "txl_p321_v1");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/g12a_u220_v1/lcd.c b/board/amlogic/g12a_u220_v1/lcd.c
new file mode 100644
index 0000000..4a32602
--- /dev/null
+++ b/board/amlogic/g12a_u220_v1/lcd.c
@@ -0,0 +1,460 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_9", /* panel rst */
+ "GPIOZ_8", /* panel power */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+#if 1
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_4", /* BL_EN */
+ "GPIOH_5", /* BL_PWM */
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,1,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOH_5
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xff, 20,
+ 0x05, 1, 0x29,
+ 0xff, 20,
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xff, 10,
+ 0x05, 1, 0x10,
+ 0xff, 10,
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_clk_path = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0xff, //ending flag
+};
+
+static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff,0xff, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 3,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .cmd_size = 9,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 1,
+ .name = "mipi_TV070WSM",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 2,
+ .name = "mipi_P070ACB",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "none",
+ .type = BL_EXTERN_MAX,
+ .i2c_addr = 0xff,
+ .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+ .dim_min = 10,
+ .dim_max = 255,
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/g12a_u221_v1/Kconfig b/board/amlogic/g12a_u221_v1/Kconfig
new file mode 100644
index 0000000..07af633
--- /dev/null
+++ b/board/amlogic/g12a_u221_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_G12A
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "g12a_u221_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "g12a"
+
+config SYS_CONFIG_NAME
+ default "g12a_u221_v1"
+
+endif
diff --git a/board/amlogic/g12a_u221_v1/Makefile b/board/amlogic/g12a_u221_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/g12a_u221_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/g12a_u221_v1/aml-user-key.sig b/board/amlogic/g12a_u221_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/g12a_u221_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/g12a_u221_v1/eth_setup.c b/board/amlogic/g12a_u221_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/g12a_u221_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/g12a_u221_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12a_u221_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..93b0335
--- /dev/null
+++ b/board/amlogic/g12a_u221_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,40 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 681},
+ { 0x1b0001, 691},
+ { 0x1a0002, 701},
+ { 0x190003, 711},
+ { 0x180004, 721},
+ { 0x170005, 731},
+ { 0x160006, 741},
+ { 0x150007, 751},
+ { 0x140008, 761},
+ { 0x130009, 772},
+ { 0x12000a, 782},
+ { 0x11000b, 792},
+ { 0x10000c, 802},
+ { 0x0f000d, 812},
+ { 0x0e000e, 822},
+ { 0x0d000f, 832},
+ { 0x0c0010, 842},
+ { 0x0b0011, 852},
+ { 0x0a0012, 862},
+ { 0x090013, 872},
+ { 0x080014, 882},
+ { 0x070015, 892},
+ { 0x060016, 902},
+ { 0x050017, 912},
+ { 0x040018, 922},
+ { 0x030019, 932},
+ { 0x02001a, 942},
+ { 0x01001b, 952},
+ { 0x00001c, 962}
+};
+
+#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12a_u221_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12a_u221_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..e6e3db8
--- /dev/null
+++ b/board/amlogic/g12a_u221_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,139 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#define ON 1
+#define OFF 0
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_D);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ return;
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ return;
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+
+ p->sources = val;
+ p->gpio_info_count = i;
+
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ unsigned char adc_key_cnt = 0;
+ init_remote();
+ saradc_enable();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ do {
+ #ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+ if (cec_power_on_check())
+ exit_reason = CEC_WAKEUP;
+ }
+ #endif
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
+ irq[IRQ_VRTC] = 0xFFFFFFFF;
+ exit_reason = RTC_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/g12a_u221_v1/firmware/timing.c b/board/amlogic/g12a_u221_v1/firmware/timing.c
new file mode 100755
index 0000000..b3d38eb
--- /dev/null
+++ b/board/amlogic/g12a_u221_v1/firmware/timing.c
@@ -0,0 +1,584 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] = {
+{
+ /* g12a skt (u209) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1200, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0xffff,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0c0c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* g12a skt (u209) lpddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 14,13,12,15,8,9,11,10, 20,21,22,23,16,17,19,18, 24,25,28,26,31,30,27,29},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+{
+ /* g12a Y2 dongle */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 14,13,12,15,8,9,11,10, 20,21,22,23,16,17,19,18, 24,25,28,26,31,30,27,29},
+ .dram_rtt_nom_wr_park = {00,00},
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* lpddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR3,
+ .DRAMFreq = {600, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,//0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x00c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 30, //
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x3ff,//0x253,
+ .soc_ac_slew_rate = 0x3ff,//0x253,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 800,//200,
+ .vref_receiver_permil = 700,//875, //700 for drv 40 odt 60 is better ,why?
+ .vref_dram_permil = 500,//875,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {0x10,0x0,0x10-6,0x10-6,0x10-6,0x0,0x0,0x0,0x0,0x0},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 29 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ),
+ [4] = ( 31| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8},
+ .ddr_lpddr34_dq_remap = {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24},
+ //{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6},
+ .dram_rtt_nom_wr_park = {00,00},
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0000001c
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE PWM table */
+#if (VDDEE_VAL == 680)
+ #define VDDEE_VAL_REG 0x001c0000
+#elif (VDDEE_VAL == 690)
+ #define VDDEE_VAL_REG 0x001b0001
+#elif (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x001a0002
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x00190003
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x00180004
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0x00170005
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0x00160006
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0x00150007
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0x00140008
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0x00130009
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0x0012000a
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x0011000b
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x0010000c
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x000f000d
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x000e000e
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x000d000f
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x000c0010
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x000b0011
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x000a0012
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x00090013
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x00080014
+#elif (VDDEE_VAL == 890)
+ #define VDDEE_VAL_REG 0x00070015
+#elif (VDDEE_VAL == 900)
+ #define VDDEE_VAL_REG 0x00060016
+#elif (VDDEE_VAL == 910)
+ #define VDDEE_VAL_REG 0x00050017
+#elif (VDDEE_VAL == 920)
+ #define VDDEE_VAL_REG 0x00040018
+#elif (VDDEE_VAL == 930)
+ #define VDDEE_VAL_REG 0x00030019
+#elif (VDDEE_VAL == 940)
+ #define VDDEE_VAL_REG 0x0002001a
+#elif (VDDEE_VAL == 950)
+ #define VDDEE_VAL_REG 0x0001001b
+#elif (VDDEE_VAL == 960)
+ #define VDDEE_VAL_REG 0x0000001c
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ /* eg: PWM init */
+
+ /* PWM_AO_D */
+ /* VCCK_VAL_REG: check PWM table */
+ {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
+ /* PWM_AO_B */
+ /* VDDEE_VAL_REG: check PWM table */
+ {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable 5V_EN */
+ {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* Enable VCCK */
+ {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 31), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/g12a_u221_v1/g12a_u221_v1.c b/board/amlogic/g12a_u221_v1/g12a_u221_v1.c
new file mode 100644
index 0000000..b21bd7f
--- /dev/null
+++ b/board/amlogic/g12a_u221_v1/g12a_u221_v1.c
@@ -0,0 +1,698 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#ifdef CONFIG_AML_SPIFC
+#include <dm.h>
+#include <amlogic/spifc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+#ifdef ETHERNET_INTERNAL_PHY
+void internalPhyConfig(struct phy_device *phydev)
+{
+}
+
+static int dwmac_meson_cfg_pll(void)
+{
+ writel(0x39C0040A, P_ETH_PLL_CTL0);
+ writel(0x927E0000, P_ETH_PLL_CTL1);
+ writel(0xAC5F49E5, P_ETH_PLL_CTL2);
+ writel(0x00000000, P_ETH_PLL_CTL3);
+ udelay(200);
+ writel(0x19C0040A, P_ETH_PLL_CTL0);
+ return 0;
+}
+
+static int dwmac_meson_cfg_analog(void)
+{
+ /*Analog*/
+ writel(0x20200000, P_ETH_PLL_CTL5);
+ writel(0x0000c002, P_ETH_PLL_CTL6);
+ writel(0x00000023, P_ETH_PLL_CTL7);
+
+ return 0;
+}
+
+static int dwmac_meson_cfg_ctrl(void)
+{
+ /*config phyid should between a 0~0xffffffff*/
+ /*please don't use 44000181, this has been used by internal phy*/
+ writel(0x33000180, P_ETH_PHY_CNTL0);
+
+ /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
+ writel(0x260, P_ETH_PHY_CNTL2);
+
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ writel(0x34043, P_ETH_PHY_CNTL1);
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ return 0;
+}
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 1;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 9;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ dwmac_meson_cfg_pll();
+ dwmac_meson_cfg_analog();
+ dwmac_meson_cfg_ctrl();
+
+ /* eth core clock */
+ setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
+ /* eth phy clock */
+ setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
+
+ /* eth phy pll, clk50m */
+ setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+
+static int dwmac_meson_cfg_drive_strength(void)
+{
+ writel(0xaaaaaaa5, P_PAD_DS_REG4A);
+ return 0;
+}
+
+static void setup_net_chip_ext(void)
+{
+ eth_aml_reg0_t eth_reg0;
+ writel(0x11111111, P_PERIPHS_PIN_MUX_6);
+ writel(0x111111, P_PERIPHS_PIN_MUX_7);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_ETHERNET_NONE
+ return 0;
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+ dwmac_meson_cfg_drive_strength();
+ setup_net_chip_ext();
+#endif
+#ifdef ETHERNET_INTERNAL_PHY
+ setup_net_chip();
+#endif
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ /* check card detect */
+ clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM 1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_USB_GPIO_PWR,
+ CONFIG_USB_GPIO_PWR_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_USB_GPIO_PWR);
+ return;
+ }
+
+ if (is_power_on) {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
+ } else {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+ .usb_phy2_pll_base_addr = {
+ CONFIG_USB_PHY_20,
+ CONFIG_USB_PHY_21,
+ }
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 280*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xfffff << 12);
+ if (enable)
+ val |= 0x33333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~(0xf << 24);
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xf6000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+ //As NOT NEED other board init If USB BOOT MODE
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+ board_usb_pll_disable(&g_usb_config_GXL_skt);
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#if 0
+ aml_pwm_cal_init(0);
+#endif//
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+#ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+#endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 1 p321 v1
+ * hwid = 2 p321 v2
+ */
+ unsigned int hwid = 1;
+ char loc_name[64] = {0};
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+
+ switch (hwid) {
+ case 1:
+ strcpy(loc_name, "txl_p321_v1\0");
+ break;
+ case 2:
+ strcpy(loc_name, "txl_p321_v2\0");
+ break;
+ default:
+ strcpy(loc_name, "txl_p321_v1");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/g12a_u221_v1/lcd.c b/board/amlogic/g12a_u221_v1/lcd.c
new file mode 100755
index 0000000..4a32602
--- /dev/null
+++ b/board/amlogic/g12a_u221_v1/lcd.c
@@ -0,0 +1,460 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_9", /* panel rst */
+ "GPIOZ_8", /* panel power */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+#if 1
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,30,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_4", /* BL_EN */
+ "GPIOH_5", /* BL_PWM */
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,1,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOH_5
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xff, 20,
+ 0x05, 1, 0x29,
+ 0xff, 20,
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xff, 10,
+ 0x05, 1, 0x10,
+ 0xff, 10,
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0xff, //ending flag
+};
+static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff,0xff, //ending flag
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_clk_path = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0xff, //ending flag
+};
+
+static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff,0xff, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 3,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .cmd_size = 9,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 1,
+ .name = "mipi_TV070WSM",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = 2,
+ .name = "mipi_P070ACB",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_off = ext_init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "none",
+ .type = BL_EXTERN_MAX,
+ .i2c_addr = 0xff,
+ .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+ .dim_min = 10,
+ .dim_max = 255,
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/g12b_skt_v1/Kconfig b/board/amlogic/g12b_skt_v1/Kconfig
new file mode 100755
index 0000000..0e406f7
--- /dev/null
+++ b/board/amlogic/g12b_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_G12B
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "g12b_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "g12b"
+
+config SYS_CONFIG_NAME
+ default "g12b_skt_v1"
+
+endif
diff --git a/board/amlogic/g12b_skt_v1/Makefile b/board/amlogic/g12b_skt_v1/Makefile
new file mode 100755
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/g12b_skt_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/g12b_skt_v1/aml-user-key.sig b/board/amlogic/g12b_skt_v1/aml-user-key.sig
new file mode 100755
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/g12b_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/g12b_skt_v1/eth_setup.c b/board/amlogic/g12b_skt_v1/eth_setup.c
new file mode 100755
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/g12b_skt_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/g12b_skt_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12b_skt_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100755
index 0000000..93b0335
--- /dev/null
+++ b/board/amlogic/g12b_skt_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,40 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 681},
+ { 0x1b0001, 691},
+ { 0x1a0002, 701},
+ { 0x190003, 711},
+ { 0x180004, 721},
+ { 0x170005, 731},
+ { 0x160006, 741},
+ { 0x150007, 751},
+ { 0x140008, 761},
+ { 0x130009, 772},
+ { 0x12000a, 782},
+ { 0x11000b, 792},
+ { 0x10000c, 802},
+ { 0x0f000d, 812},
+ { 0x0e000e, 822},
+ { 0x0d000f, 832},
+ { 0x0c0010, 842},
+ { 0x0b0011, 852},
+ { 0x0a0012, 862},
+ { 0x090013, 872},
+ { 0x080014, 882},
+ { 0x070015, 892},
+ { 0x060016, 902},
+ { 0x050017, 912},
+ { 0x040018, 922},
+ { 0x030019, 932},
+ { 0x02001a, 942},
+ { 0x01001b, 952},
+ { 0x00001c, 962}
+};
+
+#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12b_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12b_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100755
index 0000000..962940b
--- /dev/null
+++ b/board/amlogic/g12b_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,173 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ /*set gpioH_8 low to power off vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+
+ /*set gpioao_4 low to power off vcck_a*/
+ writel(readl(AO_GPIO_O) & (~(1 << 4)), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 4)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG) & (~(0xf << 16)), AO_RTI_PIN_MUX_REG);
+
+ /*set test_n low to power off vcck_b & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+
+ /*step down ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ /*step up ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+ /*set test_n low to power on vcck_b & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+ _udelay(100);
+
+ /*set gpioao_4 high to power on vcck_a*/
+ writel(readl(AO_GPIO_O) | (1 << 4), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 4)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG) & (~(0xf << 16)), AO_RTI_PIN_MUX_REG);
+ _udelay(100);
+
+ /*set gpioH_8 low to power on vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+ _udelay(10000);
+
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ BT_WAKEUP_SRC);
+
+ p->sources = val;
+ p->gpio_info_count = i;
+
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ unsigned char adc_key_cnt = 0;
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ do {
+ #ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+ if (cec_power_on_check())
+ exit_reason = CEC_WAKEUP;
+ }
+ #endif
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
+ irq[IRQ_VRTC] = 0xFFFFFFFF;
+ exit_reason = RTC_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+
+ if (irq[IRQ_ETH_PTM] == IRQ_ETH_PMT_NUM) {
+ irq[IRQ_ETH_PTM]= 0xFFFFFFFF;
+ exit_reason = ETH_PMT_WAKEUP;
+ }
+
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/g12b_skt_v1/firmware/timing.c b/board/amlogic/g12b_skt_v1/firmware/timing.c
new file mode 100755
index 0000000..ff09383
--- /dev/null
+++ b/board/amlogic/g12b_skt_v1/firmware/timing.c
@@ -0,0 +1,753 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] = {
+{
+ /* ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1200, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ //.slt_test_function={0x0,0x0}, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ ///*
+ .slt_test_function = { DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING , 0},
+ .dfi_hwtmrl = 6,
+ .ac_trace_delay = {
+ 32 ,
+ 32 ,
+ 32 ,
+ 32 ,
+ 32 ,
+ 32 ,
+ 32 ,
+ 32 ,
+ 32 ,
+ 32 ,
+ } ,
+
+ .write_dqs_delay = {
+ 173 ,
+ 173 ,
+ 171 ,
+ 171 ,
+ 165 ,
+ 165 ,
+ 163 ,
+ 163 ,
+ 128 ,
+ 128 ,
+ 128 ,
+ 128 ,
+ 128 ,
+ 128 ,
+ 128 ,
+ 128 ,
+ } ,
+
+ .read_dqs_delay = {
+ 14 ,
+ 12 ,
+ 12 ,
+ 12 ,
+ 11 ,
+ 13 ,
+ 11 ,
+ 11 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ } ,
+
+ .write_dq_bit_delay = {
+ 30 ,
+ 30 ,
+ 30 ,
+ 32 ,
+ 32 ,
+ 35 ,
+ 35 ,
+ 34 ,
+ 31 ,
+ 30 ,
+ 34 ,
+ 33 ,
+ 32 ,
+ 31 ,
+ 30 ,
+ 34 ,
+ 30 ,
+ 30 ,
+ 25 ,
+ 24 ,
+ 26 ,
+ 25 ,
+ 27 ,
+ 26 ,
+ 25 ,
+ 28 ,
+ 24 ,
+ 21 ,
+ 23 ,
+ 24 ,
+ 23 ,
+ 22 ,
+ 25 ,
+ 25 ,
+ 26 ,
+ 20 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ 16 ,
+ } ,
+
+ .read_dq_bit_delay = {
+ 7 ,
+ 1 ,
+ 7 ,
+ 7 ,
+ 19 ,
+ 19 ,
+ 23 ,
+ 23 ,
+ 0 ,
+ 3 ,
+ 19 ,
+ 19 ,
+ 15 ,
+ 15 ,
+ 15 ,
+ 23 ,
+ 19 ,
+ 0 ,
+ 7 ,
+ 5 ,
+ 11 ,
+ 7 ,
+ 23 ,
+ 23 ,
+ 19 ,
+ 23 ,
+ 0 ,
+ 3 ,
+ 11 ,
+ 11 ,
+ 11 ,
+ 15 ,
+ 23 ,
+ 23 ,
+ 23 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ 0 ,
+ } ,
+
+ .read_dqs_gate_delay = {
+ 233 ,
+ 237 ,
+ 237 ,
+ 241 ,
+ 231 ,
+ 235 ,
+ 231 ,
+ 235 ,
+ 128 ,
+ 128 ,
+ 128 ,
+ 128 ,
+ 128 ,
+ 128 ,
+ 128 ,
+ 128 ,
+ } ,
+
+ .dq_dqs_delay_flag = DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS | DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ | DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS | DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ,
+ //*/
+},
+{
+ /* ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0xffff,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0c0c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* lpddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 14,13,12,15,8,9,11,10, 20,21,22,23,16,17,19,18, 24,25,28,26,31,30,27,29},
+ .dram_rtt_nom_wr_park = {00,00},
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+{
+ /* Y2 dongle */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0000001c
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE PWM table */
+#if (VDDEE_VAL == 680)
+ #define VDDEE_VAL_REG 0x001c0000
+#elif (VDDEE_VAL == 690)
+ #define VDDEE_VAL_REG 0x001b0001
+#elif (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x001a0002
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x00190003
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x00180004
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0x00170005
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0x00160006
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0x00150007
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0x00140008
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0x00130009
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0x0012000a
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x0011000b
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x0010000c
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x000f000d
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x000e000e
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x000d000f
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x000c0010
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x000b0011
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x000a0012
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x00090013
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x00080014
+#elif (VDDEE_VAL == 890)
+ #define VDDEE_VAL_REG 0x00070015
+#elif (VDDEE_VAL == 900)
+ #define VDDEE_VAL_REG 0x00060016
+#elif (VDDEE_VAL == 910)
+ #define VDDEE_VAL_REG 0x00050017
+#elif (VDDEE_VAL == 920)
+ #define VDDEE_VAL_REG 0x00040018
+#elif (VDDEE_VAL == 930)
+ #define VDDEE_VAL_REG 0x00030019
+#elif (VDDEE_VAL == 940)
+ #define VDDEE_VAL_REG 0x0002001a
+#elif (VDDEE_VAL == 950)
+ #define VDDEE_VAL_REG 0x0001001b
+#elif (VDDEE_VAL == 960)
+ #define VDDEE_VAL_REG 0x0000001c
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ /* eg: PWM init */
+
+ /* PWM_AO_D */
+ /* VCCK_VAL_REG: check PWM table */
+ {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
+ /* PWM_AO_B */
+ /* VDDEE_VAL_REG: check PWM table */
+ {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable 5V_EN */
+ {GPIO_O_EN_N_REG3, (1 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ {GPIO_O_REG3, (1 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable CPUA ,control by GPIOAO_4 */
+ {AO_GPIO_O_EN_N, (0 << 4), (1 << 4), 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 4), (1 << 4), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable VCCK */
+ {AO_SEC_REG0, (1 << 0), (1 << 0), 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 31), (1 << 31), 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/g12b_skt_v1/g12b_skt_v1.c b/board/amlogic/g12b_skt_v1/g12b_skt_v1.c
new file mode 100755
index 0000000..a26173b
--- /dev/null
+++ b/board/amlogic/g12b_skt_v1/g12b_skt_v1.c
@@ -0,0 +1,774 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#endif
+#ifdef CONFIG_SYS_I2C_MESON
+#include <amlogic/i2c.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#ifdef CONFIG_AML_SPIFC
+#include <amlogic/spifc.h>
+#endif
+#ifdef CONFIG_AML_SPICC
+#include <amlogic/spicc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+#ifdef ETHERNET_INTERNAL_PHY
+void internalPhyConfig(struct phy_device *phydev)
+{
+}
+
+static int dwmac_meson_cfg_pll(void)
+{
+ writel(0x39C0040A, P_ETH_PLL_CTL0);
+ writel(0x927E0000, P_ETH_PLL_CTL1);
+ writel(0xAC5F49E5, P_ETH_PLL_CTL2);
+ writel(0x00000000, P_ETH_PLL_CTL3);
+ udelay(200);
+ writel(0x19C0040A, P_ETH_PLL_CTL0);
+ return 0;
+}
+
+static int dwmac_meson_cfg_analog(void)
+{
+ /*Analog*/
+ writel(0x20200000, P_ETH_PLL_CTL5);
+ writel(0x0000c002, P_ETH_PLL_CTL6);
+ writel(0x00000023, P_ETH_PLL_CTL7);
+
+ return 0;
+}
+
+static int dwmac_meson_cfg_ctrl(void)
+{
+ /*config phyid should between a 0~0xffffffff*/
+ /*please don't use 44000181, this has been used by internal phy*/
+ writel(0x33000180, P_ETH_PHY_CNTL0);
+
+ /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
+ writel(0x260, P_ETH_PHY_CNTL2);
+
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ writel(0x34043, P_ETH_PHY_CNTL1);
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ return 0;
+}
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 1;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 9;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ dwmac_meson_cfg_pll();
+ dwmac_meson_cfg_analog();
+ dwmac_meson_cfg_ctrl();
+
+ /* eth core clock */
+ setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
+ /* eth phy clock */
+ setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
+
+ /* eth phy pll, clk50m */
+ setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+
+static int dwmac_meson_cfg_drive_strength(void)
+{
+ writel(0xaaaaaaa5, P_PAD_DS_REG4A);
+ return 0;
+}
+
+static void setup_net_chip_ext(void)
+{
+ eth_aml_reg0_t eth_reg0;
+ writel(0x11111111, P_PERIPHS_PIN_MUX_6);
+ writel(0x111111, P_PERIPHS_PIN_MUX_7);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_ETHERNET_NONE
+ return 0;
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+ dwmac_meson_cfg_drive_strength();
+ setup_net_chip_ext();
+#endif
+#ifdef ETHERNET_INTERNAL_PHY
+ setup_net_chip();
+#endif
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ /* check card detect */
+ clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM 1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_USB_GPIO_PWR,
+ CONFIG_USB_GPIO_PWR_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_USB_GPIO_PWR);
+ return;
+ }
+
+ if (is_power_on) {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
+ } else {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+ .usb_phy2_pll_base_addr = {
+ CONFIG_USB_PHY_20,
+ CONFIG_USB_PHY_21,
+ }
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 280*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xfffff << 12);
+ if (enable)
+ val |= 0x33333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~(0xf << 24);
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xf6000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+#ifdef CONFIG_AML_SPICC
+/* generic config in arch gpio/clock.c */
+extern int spicc1_clk_set_rate(int rate);
+extern int spicc1_clk_enable(bool enable);
+extern int spicc1_pinctrl_enable(bool enable);
+
+static const struct spicc_platdata spicc1_platdata = {
+ .compatible = "amlogic,meson-g12a-spicc",
+ .reg = (void __iomem *)0xffd15000,
+ .clk_rate = 666666666,
+ .clk_set_rate = spicc1_clk_set_rate,
+ .clk_enable = spicc1_clk_enable,
+ .pinctrl_enable = spicc1_pinctrl_enable,
+ /* case one slave without cs: {"no_cs", 0} */
+ .cs_gpio_names = {"GPIOH_6", 0},
+};
+
+U_BOOT_DEVICE(spicc1) = {
+ .name = "spicc",
+ .platdata = &spicc1_platdata,
+};
+#endif /* CONFIG_AML_SPICC */
+
+#ifdef CONFIG_SYS_I2C_MESON
+static const struct meson_i2c_platdata i2c_data[] = {
+ { 0, 0xffd1f000, 166666666, 3, 15, 100000 },
+ { 1, 0xffd1e000, 166666666, 3, 15, 100000 },
+ { 2, 0xffd1d000, 166666666, 3, 15, 100000 },
+ { 3, 0xffd1c000, 166666666, 3, 15, 100000 },
+ { 4, 0xff805000, 166666666, 3, 15, 100000 },
+};
+
+U_BOOT_DEVICES(meson_i2cs) = {
+ { "i2c_meson", &i2c_data[0] },
+ { "i2c_meson", &i2c_data[1] },
+ { "i2c_meson", &i2c_data[2] },
+ { "i2c_meson", &i2c_data[3] },
+ { "i2c_meson", &i2c_data[4] },
+};
+
+/*
+ *GPIOH_6 I2C_SDA_M1
+ *GPIOH_7 I2C_SCK_M1
+ *pinmux configuration seperated with i2c controller configuration
+ * config it when you use
+ */
+void set_i2c_m1_pinmux(void)
+{
+ /*ds =3 */
+ clrbits_le32(PAD_DS_REG3A, 0xf << 12);
+ setbits_le32(PAD_DS_REG3A, 0x3 << 12 | 0x3 << 14);
+ /*pull up en*/
+ clrbits_le32(PAD_PULL_UP_EN_REG3, 0x3 << 6);
+ setbits_le32(PAD_PULL_UP_EN_REG3, 0x3 << 6 );
+ /*pull up*/
+ clrbits_le32(PAD_PULL_UP_REG3, 0x3 << 6);
+ setbits_le32(PAD_PULL_UP_REG3, 0x3 << 6 );
+ /*pin mux to i2cm1*/
+ clrbits_le32(PERIPHS_PIN_MUX_B, 0xff << 24);
+ setbits_le32(PERIPHS_PIN_MUX_B, 0x4 << 24 | 0x4 << 28);
+
+ return;
+}
+#endif /*end CONFIG_SYS_I2C_MESON*/
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+ //As NOT NEED other board init If USB BOOT MODE
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+ board_usb_pll_disable(&g_usb_config_GXL_skt);
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#if 0
+ aml_pwm_cal_init(0);
+#endif//
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+#ifdef CONFIG_SYS_I2C_MESON
+ set_i2c_m1_pinmux();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+#ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+#endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 1 p321 v1
+ * hwid = 2 p321 v2
+ */
+ unsigned int hwid = 1;
+ char loc_name[64] = {0};
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+
+ switch (hwid) {
+ case 1:
+ strcpy(loc_name, "txl_p321_v1\0");
+ break;
+ case 2:
+ strcpy(loc_name, "txl_p321_v2\0");
+ break;
+ default:
+ strcpy(loc_name, "txl_p321_v1");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/g12b_skt_v1/lcd.c b/board/amlogic/g12b_skt_v1/lcd.c
new file mode 100755
index 0000000..6c35291
--- /dev/null
+++ b/board/amlogic/g12b_skt_v1/lcd.c
@@ -0,0 +1,592 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+#ifdef CONFIG_AML_LCD_EXTERN
+#include "lcd_extern.h"
+#endif
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_9", /* panel rst */
+ "GPIOZ_8", /* panel power */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+#if 0
+ {LCD_POWER_TYPE_CPU, 0,1,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+#endif
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TL050FHV02CT[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TL050FHV02CT[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_TL070WSH27[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_TL070WSH27[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,10,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_4", /* BL_EN */
+ "GPIOH_5", /* BL_PWM */
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TV070WSM*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,700,1053,24,36,0,2,8,0,
+ /* clk_attr */
+ 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,360,0,1,0,2,0,0,Rsv_val,1,
+ /* power step */
+ lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TL050FHV02CT*/
+ "lcd_3",LCD_MIPI,8,
+ /* basic timing */
+ 1080,1920,1125,2100,5,30,0,44,108,0,
+ /* clk_attr */
+ 0,0,1,118125000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,960,0,1,0,2,1,0,Rsv_val,3,
+ /* power step */
+ lcd_power_on_step_TL050FHV02CT, lcd_power_off_step_TL050FHV02CT,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TL070WSH27*/
+ "lcd_4",LCD_MIPI,8,
+ /* basic timing */
+ 1024,600,1250,630,80,100,0,5,20,0,
+ /* clk_attr */
+ 0,0,1,47250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,300,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_TL070WSH27, lcd_power_off_step_TL070WSH27,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOH_5
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xfd, 1, 20,
+ 0x05, 1, 0x29,
+ 0xfd, 1, 20,
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xfd, 1, 10,
+ 0x05, 1, 0x10,
+ 0xfd, 1, 10,
+ 0xff, 0, //ending
+};
+
+static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xfd, 1, 10,
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff, 0, //ending
+};
+
+static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xfd, 1, 10,
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff, 0, //ending
+};
+
+static unsigned char mipi_init_on_table_TL050FHV02CT[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_TL050FHV02CT[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff, 0, //ending
+};
+
+static unsigned char mipi_init_on_table_TL070WSH27[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x29,
+ 0xfd, 1, 20,
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_TL070WSH27[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x10,
+ 0xfd, 1, 10,
+ 0xff, 0, //ending
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_clk_path = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0, //ending flag
+};
+
+static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 4,
+ .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_on_cnt = sizeof(ext_init_on_table),
+ .table_init_off = ext_init_off_table,
+ .table_init_off_cnt = sizeof(ext_init_off_table),
+ },
+ { /* TV070WSM */
+ .index = 1,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_TV070WSM,
+ .table_init_on_cnt = sizeof(ext_init_on_table_TV070WSM),
+ .table_init_off = ext_init_off_table_TV070WSM,
+ .table_init_off_cnt = sizeof(ext_init_off_table_TV070WSM),
+ },
+ { /* P070ACB */
+ .index = 2,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_P070ACB,
+ .table_init_on_cnt = sizeof(ext_init_on_table_P070ACB),
+ .table_init_off = ext_init_off_table_P070ACB,
+ .table_init_off_cnt = sizeof(ext_init_off_table_P070ACB),
+ },
+ { /* TL050FHV02CT */
+ .index = 3,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_TL050FHV02CT,
+ .table_init_on_cnt = sizeof(ext_init_on_table_TL050FHV02CT),
+ .table_init_off = ext_init_off_table_TL050FHV02CT,
+ .table_init_off_cnt = sizeof(ext_init_off_table_TL050FHV02CT),
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX];
+static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX];
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "none",
+ .type = BL_EXTERN_MAX,
+ .i2c_addr = 0xff,
+ .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+ .dim_min = 10,
+ .dim_max = 255,
+
+ .init_loaded = 0,
+ .cmd_size = 0xff,
+ .init_on = bl_ext_init_on,
+ .init_off = bl_ext_init_off,
+ .init_on_cnt = sizeof(bl_ext_init_on),
+ .init_off_cnt = sizeof(bl_ext_init_off),
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1:/* TV070WSM*/
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TV070WSM;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TV070WSM;
+ break;
+ case 2:/* P070ACB*/
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 3:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TL050FHV02CT;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TL050FHV02CT;
+ break;
+ case 4:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TL070WSH27;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TL070WSH27;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/g12b_skt_v1/lcd_extern.h b/board/amlogic/g12b_skt_v1/lcd_extern.h
new file mode 100755
index 0000000..ba680a0
--- /dev/null
+++ b/board/amlogic/g12b_skt_v1/lcd_extern.h
@@ -0,0 +1,862 @@
+/*
+ * board/amlogic/g12a_u200_v1/lcd_extern.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DFT_LCD_EXTERN_H_
+#define _DFT_LCD_EXTERN_H_
+
+static unsigned char ext_init_on_table_TV070WSM[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xfd, 1, 100, /* delay */
+ 0x15, 2, 0x62, 0x01,
+ 0x39, 5, 0xff, 0xaa, 0x55, 0x25, 0x01,
+ 0x15, 2, 0xfc, 0x08,
+ 0xfd, 1, 1, /* delay */
+ 0x15, 2, 0xfc, 0x00,
+ 0x39, 5, 0xff, 0xaa, 0x55, 0x25, 0x00,
+ 0xfd, 1, 20, /* delay */
+ 0x39, 6, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00,
+ 0x39, 3, 0xb1, 0x68, 0x41,
+ 0x15, 2, 0xb5, 0x88,
+ 0x15, 2, 0xb6, 0x0f,
+ 0x39, 5, 0xb8, 0x01, 0x01, 0x12, 0x01,
+ 0x39, 3, 0xbb, 0x11, 0x11,
+ 0x39, 3, 0xbc, 0x05, 0x05,
+ 0x15, 2, 0xc7, 0x03,
+ 0x39, 6, 0xbd, 0x03, 0x02, 0x19, 0x17, 0x00,
+ 0x15, 2, 0xc8, 0x80,
+ 0x39, 6, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x01,
+ 0x39, 3, 0xB2, 0x01, 0x01,
+ 0x39, 3, 0xB3, 0x28, 0x28,
+ 0x39, 3, 0xB4, 0x14, 0x14,
+ 0x39, 3, 0xB8, 0x05, 0x05,
+ 0x39, 3, 0xB9, 0x45, 0x45,
+ 0x39, 3, 0xBA, 0x25, 0x25,
+ 0x39, 3, 0xBC, 0x88, 0x00,
+ 0x39, 3, 0xBD, 0x88, 0x00,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02,
+ 0x15, 2, 0xEE, 0x00,
+ 0x39, 17, 0xB0, 0x00, 0x4B, 0x00, 0x5C, 0x00, 0x79, 0x00, 0x94, 0x00, 0xA6, 0x00, 0xD8, 0x00, 0xF2, 0x01, 0x19,
+ 0x39, 17, 0xB1, 0x01, 0x39, 0x01, 0x77, 0x01, 0xA2, 0x01, 0xF2, 0x02, 0x32, 0x02, 0x34, 0x02, 0x6D, 0x02, 0xA2,
+ 0x39, 17, 0xB2, 0x02, 0xC7, 0x02, 0xF2, 0x03, 0x18, 0x03, 0x43, 0x03, 0x65, 0x03, 0x86, 0x03, 0x8F, 0x03, 0x94,
+ 0x39, 5, 0xB3, 0x03, 0x96, 0x03, 0x98,
+ 0x39, 17, 0xB4, 0x00, 0x84, 0x00, 0x91, 0x00, 0xA4, 0x00, 0xB6, 0x00, 0xCA, 0x00, 0xE9, 0x01, 0x02, 0x01, 0x2A,
+ 0x39, 17, 0xB5, 0x01, 0x49, 0x01, 0x82, 0x01, 0xAF, 0x01, 0xF7, 0x02, 0x36, 0x02, 0x38, 0x02, 0x70, 0x02, 0xA6,
+ 0x39, 17, 0xB6, 0x02, 0xC8, 0x02, 0xF5, 0x03, 0x1A, 0x03, 0x43, 0x03, 0x62, 0x03, 0x82, 0x03, 0x8F, 0x03, 0x94,
+ 0x39, 5, 0xB7, 0x03, 0x96, 0x03, 0x98,
+ 0x39, 17, 0xB8, 0x01, 0x22, 0x01, 0x27, 0x01, 0x2E, 0x01, 0x38, 0x01, 0x40, 0x01, 0x53, 0x01, 0x60, 0x01, 0x7B,
+ 0x39, 17, 0xB9, 0x01, 0x8C, 0x01, 0xB5, 0x01, 0xD3, 0x02, 0x11, 0x02, 0x49, 0x02, 0x4A, 0x02, 0x7F, 0x02, 0xB1,
+ 0x39, 17, 0xBA, 0x02, 0xD1, 0x03, 0x00, 0x03, 0x22, 0x03, 0x49, 0x03, 0x60, 0x03, 0x7A, 0x03, 0x8B, 0x03, 0x8F,
+ 0x39, 5, 0xBB, 0x03, 0x93, 0x03, 0x9A,
+ 0x39, 17, 0xBC, 0x00, 0x37, 0x00, 0x48, 0x00, 0x65, 0x00, 0x80, 0x00, 0x92, 0x00, 0xC4, 0x00, 0xDE, 0x01, 0x05,
+ 0x39, 17, 0xBD, 0x01, 0x31, 0x01, 0x6F, 0x01, 0x9E, 0x01, 0xEE, 0x02, 0x32, 0x02, 0x34, 0x02, 0x71, 0x02, 0xA7,
+ 0x39, 17, 0xBE, 0x02, 0xD3, 0x02, 0xFE, 0x03, 0x24, 0x03, 0x4F, 0x03, 0x71, 0x03, 0x92, 0x03, 0x9B, 0x03, 0xA0,
+ 0x39, 5, 0xBF, 0x03, 0xA6, 0x03, 0xA8,
+ 0x39, 17, 0xC0, 0x00, 0x70, 0x00, 0x7D, 0x00, 0x90, 0x00, 0xA4, 0x00, 0xB6, 0x00, 0xD5, 0x00, 0xEE, 0x01, 0x16,
+ 0x39, 17, 0xC1, 0x01, 0x41, 0x01, 0x7A, 0x01, 0xAB, 0x01, 0xF3, 0x02, 0x36, 0x02, 0x38, 0x02, 0x74, 0x02, 0xAA,
+ 0x39, 17, 0xC2, 0x02, 0xD4, 0x03, 0x01, 0x03, 0x26, 0x03, 0x4F, 0x03, 0x6E, 0x03, 0x8E, 0x03, 0x9B, 0x03, 0xA0,
+ 0x39, 5, 0xC3, 0x03, 0xA6, 0x03, 0xA8,
+ 0x39, 17, 0xC4, 0x01, 0x0E, 0x01, 0x13, 0x01, 0x1A, 0x01, 0x24, 0x01, 0x2C, 0x01, 0x3F, 0x01, 0x4C, 0x01, 0x67,
+ 0x39, 17, 0xC5, 0x01, 0x84, 0x01, 0xAD, 0x01, 0xCF, 0x02, 0x0D, 0x02, 0x49, 0x02, 0x4A, 0x02, 0x83, 0x02, 0xB5,
+ 0x39, 17, 0xC6, 0x02, 0xDD, 0x03, 0x0C, 0x03, 0x2E, 0x03, 0x55, 0x03, 0x6B, 0x03, 0x86, 0x03, 0x97, 0x03, 0x9B,
+ 0x39, 5, 0xC7, 0x03, 0xA1, 0x03, 0xA8,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x04,
+ 0x39, 6, 0xB1, 0x03, 0x02, 0x02, 0x02, 0x00,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06,
+ 0x39, 3, 0xB0, 0x11, 0x11,
+ 0x39, 3, 0xB1, 0x13, 0x13,
+ 0x39, 3, 0xB2, 0x03, 0x03,
+ 0x39, 3, 0xB3, 0x34, 0x34,
+ 0x39, 3, 0xB4, 0x34, 0x34,
+ 0x39, 3, 0xB5, 0x34, 0x34,
+ 0x39, 3, 0xB6, 0x34, 0x34,
+ 0x39, 3, 0xB7, 0x34, 0x34,
+ 0x39, 3, 0xB8, 0x34, 0x34,
+ 0x39, 3, 0xB9, 0x34, 0x34,
+ 0x39, 3, 0xBA, 0x34, 0x34,
+ 0x39, 3, 0xBB, 0x34, 0x34,
+ 0x39, 3, 0xBC, 0x34, 0x34,
+ 0x39, 3, 0xBD, 0x34, 0x34,
+ 0x39, 3, 0xBE, 0x34, 0x34,
+ 0x39, 3, 0xBF, 0x34, 0x34,
+ 0x39, 3, 0xC0, 0x34, 0x34,
+ 0x39, 3, 0xC1, 0x02, 0x02,
+ 0x39, 3, 0xC2, 0x12, 0x12,
+ 0x39, 3, 0xC3, 0x10, 0x10,
+ 0x39, 3, 0xE5, 0x34, 0x34,
+ 0x39, 6, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x39, 6, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05,
+ 0x15, 2, 0xC0, 0x03,
+ 0x15, 2, 0xC1, 0x02,
+ 0x39, 3, 0xC8, 0x01, 0x20,
+ 0x15, 2, 0xE5, 0x03,
+ 0x15, 2, 0xE6, 0x03,
+ 0x15, 2, 0xE7, 0x03,
+ 0x15, 2, 0xE8, 0x03,
+ 0x15, 2, 0xE9, 0x03,
+ 0x39, 5, 0xD1, 0x03, 0x00, 0x3D, 0x00,
+ 0x39, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03,
+ 0x39, 3, 0xB0, 0x11, 0x00,
+ 0x39, 3, 0xB1, 0x11, 0x00,
+ 0x39, 6, 0xB2, 0x03, 0x00, 0x00, 0x00, 0x00,
+ 0x39, 6, 0xB3, 0x03, 0x00, 0x00, 0x00, 0x00,
+ 0x39, 6, 0xBA, 0x31, 0x00, 0x00, 0x00, 0x00,
+ 0x15, 2, 0x35, 0x00,
+ 0x15, 2, 0x51, 0xFF,
+ 0x15, 2, 0x53, 0x2C,
+ 0x15, 2, 0x55, 0x03,
+ 0x05, 1, 0x11,
+ 0xfd, 1, 120, /* delay 120ms */
+ 0x05, 1, 0x29,
+ 0xff, 0, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_TV070WSM[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xfd, 1, 30, /* delay 30ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xfd, 1, 10,
+ 0xff, 0, /* ending flag */
+};
+
+static unsigned char ext_init_on_table_P070ACB[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xfd, 1, 100, /* delay */
+ 0x15, 2, 0x62, 0x01,
+ 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x01,
+ 0x23, 2, 0xFC, 0x08,
+ 0xfd, 1, 1, /* delay(ms) */
+ 0x23, 2, 0xFC, 0x00,
+
+ 0xfd, 1, 1, /* delay(ms) */
+ 0x23, 2, 0x6F, 0x21,
+ 0x23, 2, 0xF7, 0x01,
+ 0xfd, 1, 1, /* delay(ms) */
+ 0x23, 2, 0x6F, 0x21,
+ 0x23, 2, 0xF7, 0x00,
+ 0xfd, 1, 1, /* delay(ms) */
+
+ 0x23, 2, 0x6F, 0x1A,
+ 0x23, 2, 0xF7, 0x05,
+ 0xfd, 1, 1, /* delay(ms) */
+
+ 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x00,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00,
+ 0x29, 3, 0xB1, 0x68, 0x41,
+ 0x23, 2, 0xB5, 0x88,
+ 0x29, 6, 0xBD, 0x02, 0xB0, 0x0C, 0x14, 0x00,
+ 0x23, 2, 0xC8, 0x80,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01,
+ 0x29, 3, 0xB3, 0x2D, 0x2D,
+ 0x29, 3, 0xB4, 0x19, 0x19,
+ 0x23, 2, 0xB5, 0x06,
+
+ 0x29, 3, 0xB9, 0x36, 0x36,
+ 0x29, 3, 0xBA, 0x26, 0x26,
+ 0x29, 3, 0xBC, 0xA8, 0x01,
+ 0x29, 3, 0xBD, 0xAB, 0x01,
+ 0x23, 2, 0xC0, 0x0C,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02,
+ 0x23, 2, 0xEE, 0x02,
+ 0x29, 7, 0xB0, 0x00, 0x50, 0x00, 0x52, 0x00, 0x73,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xB0, 0x00, 0x8F, 0x00, 0xA5, 0x00, 0xCA,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xB0, 0x00, 0xEA, 0x01, 0x1B,
+ 0x29, 7, 0xB1, 0x01, 0x42, 0x01, 0x82, 0x01, 0xB3,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xB1, 0x02, 0x00, 0x02, 0x41, 0x02, 0x42,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xB1, 0x02, 0x78, 0x02, 0xB5,
+ 0x29, 7, 0xB2, 0x02, 0xDA, 0x03, 0x12, 0x03, 0x3A,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xB2, 0x03, 0x6E, 0x03, 0x8D, 0x03, 0xB1,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xB2, 0x03, 0xCA, 0x03, 0xE8,
+ 0x29, 5, 0xB3, 0x03, 0xF4, 0x03, 0xFF,
+
+ 0x29, 7, 0xBC, 0x00, 0x05, 0x00, 0x52, 0x00, 0x73,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xBC, 0x00, 0x8F, 0x00, 0xA5, 0x00, 0xCA,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xBC, 0x00, 0xEA, 0x01, 0x1B,
+ 0x29, 7, 0xBD, 0x01, 0x42, 0x01, 0x82, 0x01, 0xB3,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xBD, 0x02, 0x00, 0x02, 0x41, 0x02, 0x42,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xBD, 0x02, 0x78, 0x02, 0xB5,
+ 0x29, 7, 0xBE, 0x02, 0xDA, 0x03, 0x12, 0x03, 0x3A,
+ 0x23, 2, 0x6F, 0x06,
+ 0x29, 7, 0xBE, 0x03, 0x6E, 0x03, 0x8D, 0x03, 0xB1,
+ 0x23, 2, 0x6F, 0x0C,
+ 0x29, 5, 0xBE, 0x03, 0xCA, 0x03, 0xE8,
+ 0x29, 5, 0xBF, 0x03, 0xF4, 0x03, 0xFF,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03,
+ 0x29, 6, 0xB2, 0x05, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xB6, 0x05, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xB7, 0x05, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xBA, 0x57, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xBB, 0x57, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 5, 0xC0, 0x00, 0x34, 0x00, 0x00,
+ 0x29, 5, 0xC1, 0x00, 0x00, 0x34, 0x00,
+ 0x23, 2, 0xC4, 0x40,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05,
+ 0x29, 3, 0xB0, 0x17, 0x06,
+ 0x29, 3, 0xB1, 0x17, 0x06,
+ 0x29, 3, 0xB2, 0x17, 0x06,
+ 0x29, 3, 0xB3, 0x17, 0x06,
+ 0x29, 3, 0xB4, 0x17, 0x06,
+
+ 0x29, 6, 0xBD, 0x03, 0x01, 0x03, 0x03, 0x01,
+ 0x23, 2, 0xC0, 0x05,
+ 0x23, 2, 0xC4, 0x82,
+ 0x23, 2, 0xC5, 0xA2,
+ 0x29, 3, 0xC8, 0x03, 0x30,
+ 0x29, 3, 0xC9, 0x03, 0x31,
+ 0x29, 4, 0xCC, 0x00, 0x00, 0x3C,
+ 0x29, 4, 0xCD, 0x00, 0x00, 0x3C,
+ 0x29, 6, 0xD1, 0x00, 0x44, 0x09, 0x00, 0x00,
+ 0x29, 6, 0xD2, 0x00, 0x04, 0x0B, 0x00, 0x00,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06,
+ 0x29, 3, 0xB0, 0x0B, 0x2D,
+ 0x29, 3, 0xB1, 0x2D, 0x09,
+ 0x29, 3, 0xB2, 0x2A, 0x29,
+ 0x29, 3, 0xB3, 0x34, 0x1B,
+ 0x29, 3, 0xB4, 0x19, 0x17,
+ 0x29, 3, 0xB5, 0x15, 0x13,
+ 0x29, 3, 0xB6, 0x11, 0x01,
+ 0x29, 3, 0xB7, 0x34, 0x34,
+ 0x29, 3, 0xB8, 0x34, 0x2D,
+ 0x29, 3, 0xB9, 0x2D, 0x34,
+ 0x29, 3, 0xBA, 0x2D, 0x2D,
+ 0x29, 3, 0xBB, 0x34, 0x34,
+ 0x29, 3, 0xBC, 0x34, 0x34,
+ 0x29, 3, 0xBD, 0x00, 0x10,
+ 0x29, 3, 0xBE, 0x12, 0x14,
+ 0x29, 3, 0xBF, 0x16, 0x18,
+
+ 0x29, 3, 0xC0, 0x1A, 0x34,
+ 0x29, 3, 0xC1, 0x29, 0x2A,
+ 0x29, 3, 0xC2, 0x08, 0x2D,
+ 0x29, 3, 0xC3, 0x2D, 0x0A,
+ 0x29, 3, 0xC4, 0x0A, 0x2D,
+ 0x29, 3, 0xC5, 0x2D, 0x00,
+ 0x29, 3, 0xC6, 0x2A, 0x29,
+ 0x29, 3, 0xC7, 0x34, 0x14,
+ 0x29, 3, 0xC8, 0x16, 0x18,
+ 0x29, 3, 0xC9, 0x1A, 0x10,
+ 0x29, 3, 0xCA, 0x12, 0x08,
+ 0x29, 3, 0xCB, 0x34, 0x34,
+ 0x29, 3, 0xCC, 0x34, 0x2D,
+ 0x29, 3, 0xCD, 0x2D, 0x34,
+ 0x29, 3, 0xCE, 0x2D, 0x2D,
+ 0x29, 3, 0xCF, 0x34, 0x34,
+
+ 0x29, 3, 0xD0, 0x34, 0x34,
+ 0x29, 3, 0xD1, 0x09, 0x13,
+ 0x29, 3, 0xD2, 0x11, 0x1B,
+ 0x29, 3, 0xD3, 0x19, 0x17,
+ 0x29, 3, 0xD4, 0x15, 0x34,
+ 0x29, 3, 0xD5, 0x29, 0x2A,
+ 0x29, 3, 0xD6, 0x01, 0x2D,
+ 0x29, 3, 0xD7, 0x2D, 0x0B,
+ 0x29, 6, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x29, 6, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+ 0x29, 3, 0xE5, 0x34, 0x34,
+ 0x29, 3, 0xE6, 0x34, 0x34,
+ 0x23, 2, 0xE7, 0x00,
+ 0x29, 3, 0xE8, 0x34, 0x34,
+ 0x29, 3, 0xE9, 0x34, 0x34,
+ 0x23, 2, 0xEA, 0x00,
+
+ 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x00, 0x00,
+
+ 0x13, 1, 0x35,
+ 0x13, 1, 0x11,
+ 0xfd, 1, 120, /* delay(ms) */
+ 0x13, 1, 0x29,
+ 0xfd, 1, 20, /* delay(ms) */
+ 0xFF, 0, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_P070ACB[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xfd, 1, 10, /* delay 10ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xfd, 1, 150, /* delay 150ms */
+ 0xFF, 0, /* ending flag */
+};
+
+static unsigned char ext_init_on_table_TL050FHV02CT[LCD_EXTERN_INIT_ON_MAX] = {
+ //LCD driver initialization
+ 0x23, 2, 0XFF, 0X05,
+ 0x23, 2, 0XFB, 0X01,
+ 0x23, 2, 0XC5, 0X01, //TURN ON
+ 0xfd, 1, 100,
+
+ //AUO4.97+NT35596_intial
+ 0x23, 2, 0XFF, 0XEE, //CMD page select
+ 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
+ 0x23, 2, 0X1F, 0X45,
+ 0x23, 2, 0X24, 0X4F,
+ 0x23, 2, 0X38, 0XC8,
+ 0x23, 2, 0X39, 0X2C,
+ 0x23, 2, 0X1E, 0XBB,
+ 0x23, 2, 0X1D, 0X0F,
+ 0x23, 2, 0X7E, 0XB1,
+
+ 0x23, 2, 0XFF, 0X00, //CMD page select
+ 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
+ 0x23, 2, 0X35, 0X01,
+
+ 0x23, 2, 0XFF, 0X01, //CMD page select
+ 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
+ 0x23, 2, 0X00, 0X01,
+ 0x23, 2, 0X01, 0X55,
+ 0x23, 2, 0X02, 0X40,
+ 0x23, 2, 0X05, 0X40,
+ 0x23, 2, 0X06, 0X4A,
+ 0x23, 2, 0X07, 0X24,
+ 0x23, 2, 0X08, 0X0C,
+ 0x23, 2, 0X0B, 0X87,
+ 0x23, 2, 0X0C, 0X87,
+ 0x23, 2, 0X0E, 0XB0,
+ 0x23, 2, 0X0F, 0XB3,
+ 0x23, 2, 0X11, 0X10,
+ 0x23, 2, 0X12, 0X10,
+ 0x23, 2, 0X13, 0X05,
+ 0x23, 2, 0X14, 0X4A,
+ 0x23, 2, 0X15, 0X18,
+ 0x23, 2, 0X16, 0X18,
+ 0x23, 2, 0X18, 0X00,
+ 0x23, 2, 0X19, 0X77,
+ 0x23, 2, 0X1A, 0X55,
+ 0x23, 2, 0X1B, 0X13,
+ 0x23, 2, 0X1C, 0X00,
+ 0x23, 2, 0X1D, 0X00,
+ 0x23, 2, 0X1E, 0X13,
+ 0x23, 2, 0X1F, 0X00,
+ 0x23, 2, 0X23, 0X00,
+ 0x23, 2, 0X24, 0X00,
+ 0x23, 2, 0X25, 0X00,
+ 0x23, 2, 0X26, 0X00,
+ 0x23, 2, 0X27, 0X00,
+ 0x23, 2, 0X28, 0X00,
+ 0x23, 2, 0X35, 0X00,
+ 0x23, 2, 0X66, 0X00,
+ 0x23, 2, 0X58, 0X82,
+ 0x23, 2, 0X59, 0X02,
+ 0x23, 2, 0X5A, 0X02,
+ 0x23, 2, 0X5B, 0X02,
+ 0x23, 2, 0X5C, 0X82,
+ 0x23, 2, 0X5D, 0X82,
+ 0x23, 2, 0X5E, 0X02,
+ 0x23, 2, 0X5F, 0X02,
+ 0x23, 2, 0X72, 0X31,
+
+ 0x23, 2, 0XFF, 0X05, //CMD page select
+ 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
+ 0x23, 2, 0X00, 0X01,
+ 0x23, 2, 0X01, 0X0B,
+ 0x23, 2, 0X02, 0X0C,
+ 0x23, 2, 0X03, 0X09,
+ 0x23, 2, 0X04, 0X0A,
+ 0x23, 2, 0X05, 0X00,
+ 0x23, 2, 0X06, 0X0F,
+ 0x23, 2, 0X07, 0X10,
+ 0x23, 2, 0X08, 0X00,
+ 0x23, 2, 0X09, 0X00,
+ 0x23, 2, 0X0A, 0X00,
+ 0x23, 2, 0X0B, 0X00,
+ 0x23, 2, 0X0C, 0X00,
+ 0x23, 2, 0X0D, 0X13,
+ 0x23, 2, 0X0E, 0X15,
+ 0x23, 2, 0X0F, 0X17,
+ 0x23, 2, 0X10, 0X01,
+ 0x23, 2, 0X11, 0X0B,
+ 0x23, 2, 0X12, 0X0C,
+ 0x23, 2, 0X13, 0X09,
+ 0x23, 2, 0X14, 0X0A,
+ 0x23, 2, 0X15, 0X00,
+ 0x23, 2, 0X16, 0X0F,
+ 0x23, 2, 0X17, 0X10,
+ 0x23, 2, 0X18, 0X00,
+ 0x23, 2, 0X19, 0X00,
+ 0x23, 2, 0X1A, 0X00,
+ 0x23, 2, 0X1B, 0X00,
+ 0x23, 2, 0X1C, 0X00,
+ 0x23, 2, 0X1D, 0X13,
+ 0x23, 2, 0X1E, 0X15,
+ 0x23, 2, 0X1F, 0X17,
+ 0x23, 2, 0X20, 0X00,
+ 0x23, 2, 0X21, 0X03,
+ 0x23, 2, 0X22, 0X01,
+ 0x23, 2, 0X23, 0X40,
+ 0x23, 2, 0X24, 0X40,
+ 0x23, 2, 0X25, 0XED,
+ 0x23, 2, 0X29, 0X58,
+ 0x23, 2, 0X2A, 0X12,
+ 0x23, 2, 0X2B, 0X01,
+ 0x23, 2, 0X4B, 0X06,
+ 0x23, 2, 0X4C, 0X11,
+ 0x23, 2, 0X4D, 0X20,
+ 0x23, 2, 0X4E, 0X02,
+ 0x23, 2, 0X4F, 0X02,
+ 0x23, 2, 0X50, 0X20,
+ 0x23, 2, 0X51, 0X61,
+ 0x23, 2, 0X52, 0X01,
+ 0x23, 2, 0X53, 0X63,
+ 0x23, 2, 0X54, 0X77,
+ 0x23, 2, 0X55, 0XED,
+ 0x23, 2, 0X5B, 0X00,
+ 0x23, 2, 0X5C, 0X00,
+ 0x23, 2, 0X5D, 0X00,
+ 0x23, 2, 0X5E, 0X00,
+ 0x23, 2, 0X5F, 0X15,
+ 0x23, 2, 0X60, 0X75,
+ 0x23, 2, 0X61, 0X00,
+ 0x23, 2, 0X62, 0X00,
+ 0x23, 2, 0X63, 0X00,
+ 0x23, 2, 0X64, 0X00,
+ 0x23, 2, 0X65, 0X00,
+ 0x23, 2, 0X66, 0X00,
+ 0x23, 2, 0X67, 0X00,
+ 0x23, 2, 0X68, 0X04,
+ 0x23, 2, 0X69, 0X00,
+ 0x23, 2, 0X6A, 0X00,
+ 0x23, 2, 0X6C, 0X40,
+ 0x23, 2, 0X75, 0X01,
+ 0x23, 2, 0X76, 0X01,
+ 0x23, 2, 0X7A, 0X80,
+ 0x23, 2, 0X7B, 0XC5,
+ 0x23, 2, 0X7C, 0XD8,
+ 0x23, 2, 0X7D, 0X60,
+ 0x23, 2, 0X7F, 0X15,
+ 0x23, 2, 0X80, 0X81,
+ 0x23, 2, 0X83, 0X05,
+ 0x23, 2, 0X93, 0X08,
+ 0x23, 2, 0X94, 0X10,
+ 0x23, 2, 0X8A, 0X00,
+ 0x23, 2, 0X9B, 0X0F,
+ 0x23, 2, 0XEA, 0XFF,
+ 0x23, 2, 0XEC, 0X00,
+
+ 0x23, 2, 0XFF, 0X01, //CMD page select
+ 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
+ 0x23, 2, 0X75, 0X00, //Gamma R+
+ 0x23, 2, 0X76, 0X18,
+ 0x23, 2, 0X77, 0X00,
+ 0x23, 2, 0X78, 0X38,
+ 0x23, 2, 0X79, 0X00,
+ 0x23, 2, 0X7A, 0X65,
+ 0x23, 2, 0X7B, 0X00,
+ 0x23, 2, 0X7C, 0X84,
+ 0x23, 2, 0X7D, 0X00,
+ 0x23, 2, 0X7E, 0X9B,
+ 0x23, 2, 0X7F, 0X00,
+ 0x23, 2, 0X80, 0XAF,
+ 0x23, 2, 0X81, 0X00,
+ 0x23, 2, 0X82, 0XC1,
+ 0x23, 2, 0X83, 0X00,
+ 0x23, 2, 0X84, 0XD2,
+ 0x23, 2, 0X85, 0X00,
+ 0x23, 2, 0X86, 0XDF,
+ 0x23, 2, 0X87, 0X01,
+ 0x23, 2, 0X88, 0X11,
+ 0x23, 2, 0X89, 0X01,
+ 0x23, 2, 0X8A, 0X38,
+ 0x23, 2, 0X8B, 0X01,
+ 0x23, 2, 0X8C, 0X76,
+ 0x23, 2, 0X8D, 0X01,
+ 0x23, 2, 0X8E, 0XA7,
+ 0x23, 2, 0X8F, 0X01,
+ 0x23, 2, 0X90, 0XF3,
+ 0x23, 2, 0X91, 0X02,
+ 0x23, 2, 0X92, 0X2F,
+ 0x23, 2, 0X93, 0X02,
+ 0x23, 2, 0X94, 0X30,
+ 0x23, 2, 0X95, 0X02,
+ 0x23, 2, 0X96, 0X66,
+ 0x23, 2, 0X97, 0X02,
+ 0x23, 2, 0X98, 0XA0,
+ 0x23, 2, 0X99, 0X02,
+ 0x23, 2, 0X9A, 0XC5,
+ 0x23, 2, 0X9B, 0X02,
+ 0x23, 2, 0X9C, 0XF8,
+ 0x23, 2, 0X9D, 0X03,
+ 0x23, 2, 0X9E, 0X1B,
+ 0x23, 2, 0X9F, 0X03,
+ 0x23, 2, 0XA0, 0X46,
+ 0x23, 2, 0XA2, 0X03,
+ 0x23, 2, 0XA3, 0X52,
+ 0x23, 2, 0XA4, 0X03,
+ 0x23, 2, 0XA5, 0X62,
+ 0x23, 2, 0XA6, 0X03,
+ 0x23, 2, 0XA7, 0X71,
+ 0x23, 2, 0XA9, 0X03,
+ 0x23, 2, 0XAA, 0X83,
+ 0x23, 2, 0XAB, 0X03,
+ 0x23, 2, 0XAC, 0X94,
+ 0x23, 2, 0XAD, 0X03,
+ 0x23, 2, 0XAE, 0XA3,
+ 0x23, 2, 0XAF, 0X03,
+ 0x23, 2, 0XB0, 0XAD,
+ 0x23, 2, 0XB1, 0X03,
+ 0x23, 2, 0XB2, 0XCC,
+
+ 0x23, 2, 0XB3, 0X00, //Gamma R-
+ 0x23, 2, 0XB4, 0X18,
+ 0x23, 2, 0XB5, 0X00,
+ 0x23, 2, 0XB6, 0X38,
+ 0x23, 2, 0XB7, 0X00,
+ 0x23, 2, 0XB8, 0X65,
+ 0x23, 2, 0XB9, 0X00,
+ 0x23, 2, 0XBA, 0X84,
+ 0x23, 2, 0XBB, 0X00,
+ 0x23, 2, 0XBC, 0X9B,
+ 0x23, 2, 0XBD, 0X00,
+ 0x23, 2, 0XBE, 0XAF,
+ 0x23, 2, 0XBF, 0X00,
+ 0x23, 2, 0XC0, 0XC1,
+ 0x23, 2, 0XC1, 0X00,
+ 0x23, 2, 0XC2, 0XD2,
+ 0x23, 2, 0XC3, 0X00,
+ 0x23, 2, 0XC4, 0XDF,
+ 0x23, 2, 0XC5, 0X01,
+ 0x23, 2, 0XC6, 0X11,
+ 0x23, 2, 0XC7, 0X01,
+ 0x23, 2, 0XC8, 0X38,
+ 0x23, 2, 0XC9, 0X01,
+ 0x23, 2, 0XCA, 0X76,
+ 0x23, 2, 0XCB, 0X01,
+ 0x23, 2, 0XCC, 0XA7,
+ 0x23, 2, 0XCD, 0X01,
+ 0x23, 2, 0XCE, 0XF3,
+ 0x23, 2, 0XCF, 0X02,
+ 0x23, 2, 0XD0, 0X2F,
+ 0x23, 2, 0XD1, 0X02,
+ 0x23, 2, 0XD2, 0X30,
+ 0x23, 2, 0XD3, 0X02,
+ 0x23, 2, 0XD4, 0X66,
+ 0x23, 2, 0XD5, 0X02,
+ 0x23, 2, 0XD6, 0XA0,
+ 0x23, 2, 0XD7, 0X02,
+ 0x23, 2, 0XD8, 0XC5,
+ 0x23, 2, 0XD9, 0X02,
+ 0x23, 2, 0XDA, 0XF8,
+ 0x23, 2, 0XDB, 0X03,
+ 0x23, 2, 0XDC, 0X1B,
+ 0x23, 2, 0XDD, 0X03,
+ 0x23, 2, 0XDE, 0X46,
+ 0x23, 2, 0XDF, 0X03,
+ 0x23, 2, 0XE0, 0X52,
+ 0x23, 2, 0XE1, 0X03,
+ 0x23, 2, 0XE2, 0X62,
+ 0x23, 2, 0XE3, 0X03,
+ 0x23, 2, 0XE4, 0X71,
+ 0x23, 2, 0XE5, 0X03,
+ 0x23, 2, 0XE6, 0X83,
+ 0x23, 2, 0XE7, 0X03,
+ 0x23, 2, 0XE8, 0X94,
+ 0x23, 2, 0XE9, 0X03,
+ 0x23, 2, 0XEA, 0XA3,
+ 0x23, 2, 0XEB, 0X03,
+ 0x23, 2, 0XEC, 0XAD,
+ 0x23, 2, 0XED, 0X03,
+ 0x23, 2, 0XEE, 0XCC,
+
+ 0x23, 2, 0XEF, 0X00, //Gamma G+
+ 0x23, 2, 0XF0, 0X18,
+ 0x23, 2, 0XF1, 0X00,
+ 0x23, 2, 0XF2, 0X38,
+ 0x23, 2, 0XF3, 0X00,
+ 0x23, 2, 0XF4, 0X65,
+ 0x23, 2, 0XF5, 0X00,
+ 0x23, 2, 0XF6, 0X84,
+ 0x23, 2, 0XF7, 0X00,
+ 0x23, 2, 0XF8, 0X9B,
+ 0x23, 2, 0XF9, 0X00,
+ 0x23, 2, 0XFA, 0XAF,
+ 0x23, 2, 0XFF, 0X02, //CMD page select
+ 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
+ 0x23, 2, 0X00, 0X00,
+ 0x23, 2, 0X01, 0XC1,
+ 0x23, 2, 0X02, 0X00,
+ 0x23, 2, 0X03, 0XD2,
+ 0x23, 2, 0X04, 0X00,
+ 0x23, 2, 0X05, 0XDF,
+ 0x23, 2, 0X06, 0X01,
+ 0x23, 2, 0X07, 0X11,
+ 0x23, 2, 0X08, 0X01,
+ 0x23, 2, 0X09, 0X38,
+ 0x23, 2, 0X0A, 0X01,
+ 0x23, 2, 0X0B, 0X76,
+ 0x23, 2, 0X0C, 0X01,
+ 0x23, 2, 0X0D, 0XA7,
+ 0x23, 2, 0X0E, 0X01,
+ 0x23, 2, 0X0F, 0XF3,
+ 0x23, 2, 0X10, 0X02,
+ 0x23, 2, 0X11, 0X2F,
+ 0x23, 2, 0X12, 0X02,
+ 0x23, 2, 0X13, 0X30,
+ 0x23, 2, 0X14, 0X02,
+ 0x23, 2, 0X15, 0X66,
+ 0x23, 2, 0X16, 0X02,
+ 0x23, 2, 0X17, 0XA0,
+ 0x23, 2, 0X18, 0X02,
+ 0x23, 2, 0X19, 0XC5,
+ 0x23, 2, 0X1A, 0X02,
+ 0x23, 2, 0X1B, 0XF8,
+ 0x23, 2, 0X1C, 0X03,
+ 0x23, 2, 0X1D, 0X1B,
+ 0x23, 2, 0X1E, 0X03,
+ 0x23, 2, 0X1F, 0X46,
+ 0x23, 2, 0X20, 0X03,
+ 0x23, 2, 0X21, 0X52,
+ 0x23, 2, 0X22, 0X03,
+ 0x23, 2, 0X23, 0X62,
+ 0x23, 2, 0X24, 0X03,
+ 0x23, 2, 0X25, 0X71,
+ 0x23, 2, 0X26, 0X03,
+ 0x23, 2, 0X27, 0X83,
+ 0x23, 2, 0X28, 0X03,
+ 0x23, 2, 0X29, 0X94,
+ 0x23, 2, 0X2A, 0X03,
+ 0x23, 2, 0X2B, 0XA3,
+ 0x23, 2, 0X2D, 0X03,
+ 0x23, 2, 0X2F, 0XAD,
+ 0x23, 2, 0X30, 0X03,
+ 0x23, 2, 0X31, 0XCC,
+
+ 0x23, 2, 0X32, 0X00, //Gamma G-
+ 0x23, 2, 0X33, 0X18,
+ 0x23, 2, 0X34, 0X00,
+ 0x23, 2, 0X35, 0X38,
+ 0x23, 2, 0X36, 0X00,
+ 0x23, 2, 0X37, 0X65,
+ 0x23, 2, 0X38, 0X00,
+ 0x23, 2, 0X39, 0X84,
+ 0x23, 2, 0X3A, 0X00,
+ 0x23, 2, 0X3B, 0X9B,
+ 0x23, 2, 0X3D, 0X00,
+ 0x23, 2, 0X3F, 0XAF,
+ 0x23, 2, 0X40, 0X00,
+ 0x23, 2, 0X41, 0XC1,
+ 0x23, 2, 0X42, 0X00,
+ 0x23, 2, 0X43, 0XD2,
+ 0x23, 2, 0X44, 0X00,
+ 0x23, 2, 0X45, 0XDF,
+ 0x23, 2, 0X46, 0X01,
+ 0x23, 2, 0X47, 0X11,
+ 0x23, 2, 0X48, 0X01,
+ 0x23, 2, 0X49, 0X38,
+ 0x23, 2, 0X4A, 0X01,
+ 0x23, 2, 0X4B, 0X76,
+ 0x23, 2, 0X4C, 0X01,
+ 0x23, 2, 0X4D, 0XA7,
+ 0x23, 2, 0X4E, 0X01,
+ 0x23, 2, 0X4F, 0XF3,
+ 0x23, 2, 0X50, 0X02,
+ 0x23, 2, 0X51, 0X2F,
+ 0x23, 2, 0X52, 0X02,
+ 0x23, 2, 0X53, 0X30,
+ 0x23, 2, 0X54, 0X02,
+ 0x23, 2, 0X55, 0X66,
+ 0x23, 2, 0X56, 0X02,
+ 0x23, 2, 0X58, 0XA0,
+ 0x23, 2, 0X59, 0X02,
+ 0x23, 2, 0X5A, 0XC5,
+ 0x23, 2, 0X5B, 0X02,
+ 0x23, 2, 0X5C, 0XF8,
+ 0x23, 2, 0X5D, 0X03,
+ 0x23, 2, 0X5E, 0X1B,
+ 0x23, 2, 0X5F, 0X03,
+ 0x23, 2, 0X60, 0X46,
+ 0x23, 2, 0X61, 0X03,
+ 0x23, 2, 0X62, 0X52,
+ 0x23, 2, 0X63, 0X03,
+ 0x23, 2, 0X64, 0X62,
+ 0x23, 2, 0X65, 0X03,
+ 0x23, 2, 0X66, 0X71,
+ 0x23, 2, 0X67, 0X03,
+ 0x23, 2, 0X68, 0X83,
+ 0x23, 2, 0X69, 0X03,
+ 0x23, 2, 0X6A, 0X94,
+ 0x23, 2, 0X6B, 0X03,
+ 0x23, 2, 0X6C, 0XA3,
+ 0x23, 2, 0X6D, 0X03,
+ 0x23, 2, 0X6E, 0XAD,
+ 0x23, 2, 0X6F, 0X03,
+ 0x23, 2, 0X70, 0XCC,
+
+ 0x23, 2, 0X71, 0X00, //Gamma B+
+ 0x23, 2, 0X72, 0X18,
+ 0x23, 2, 0X73, 0X00,
+ 0x23, 2, 0X74, 0X38,
+ 0x23, 2, 0X75, 0X00,
+ 0x23, 2, 0X76, 0X65,
+ 0x23, 2, 0X77, 0X00,
+ 0x23, 2, 0X78, 0X84,
+ 0x23, 2, 0X79, 0X00,
+ 0x23, 2, 0X7A, 0X9B,
+ 0x23, 2, 0X7B, 0X00,
+ 0x23, 2, 0X7C, 0XAF,
+ 0x23, 2, 0X7D, 0X00,
+ 0x23, 2, 0X7E, 0XC1,
+ 0x23, 2, 0X7F, 0X00,
+ 0x23, 2, 0X80, 0XD2,
+ 0x23, 2, 0X81, 0X00,
+ 0x23, 2, 0X82, 0XDF,
+ 0x23, 2, 0X83, 0X01,
+ 0x23, 2, 0X84, 0X11,
+ 0x23, 2, 0X85, 0X01,
+ 0x23, 2, 0X86, 0X38,
+ 0x23, 2, 0X87, 0X01,
+ 0x23, 2, 0X88, 0X76,
+ 0x23, 2, 0X89, 0X01,
+ 0x23, 2, 0X8A, 0XA7,
+ 0x23, 2, 0X8B, 0X01,
+ 0x23, 2, 0X8C, 0XF3,
+ 0x23, 2, 0X8D, 0X02,
+ 0x23, 2, 0X8E, 0X2F,
+ 0x23, 2, 0X8F, 0X02,
+ 0x23, 2, 0X90, 0X30,
+ 0x23, 2, 0X91, 0X02,
+ 0x23, 2, 0X92, 0X66,
+ 0x23, 2, 0X93, 0X02,
+ 0x23, 2, 0X94, 0XA0,
+ 0x23, 2, 0X95, 0X02,
+ 0x23, 2, 0X96, 0XC5,
+ 0x23, 2, 0X97, 0X02,
+ 0x23, 2, 0X98, 0XF8,
+ 0x23, 2, 0X99, 0X03,
+ 0x23, 2, 0X9A, 0X1B,
+ 0x23, 2, 0X9B, 0X03,
+ 0x23, 2, 0X9C, 0X46,
+ 0x23, 2, 0X9D, 0X03,
+ 0x23, 2, 0X9E, 0X52,
+ 0x23, 2, 0X9F, 0X03,
+ 0x23, 2, 0XA0, 0X62,
+ 0x23, 2, 0XA2, 0X03,
+ 0x23, 2, 0XA3, 0X71,
+ 0x23, 2, 0XA4, 0X03,
+ 0x23, 2, 0XA5, 0X83,
+ 0x23, 2, 0XA6, 0X03,
+ 0x23, 2, 0XA7, 0X94,
+ 0x23, 2, 0XA9, 0X03,
+ 0x23, 2, 0XAA, 0XA3,
+ 0x23, 2, 0XAB, 0X03,
+ 0x23, 2, 0XAC, 0XAD,
+ 0x23, 2, 0XAD, 0X03,
+ 0x23, 2, 0XAE, 0XCC,
+
+ 0x23, 2, 0XAF, 0X00, //Gamma B-
+ 0x23, 2, 0XB0, 0X18,
+ 0x23, 2, 0XB1, 0X00,
+ 0x23, 2, 0XB2, 0X38,
+ 0x23, 2, 0XB3, 0X00,
+ 0x23, 2, 0XB4, 0X65,
+ 0x23, 2, 0XB5, 0X00,
+ 0x23, 2, 0XB6, 0X84,
+ 0x23, 2, 0XB7, 0X00,
+ 0x23, 2, 0XB8, 0X9B,
+ 0x23, 2, 0XB9, 0X00,
+ 0x23, 2, 0XBA, 0XAF,
+ 0x23, 2, 0XBB, 0X00,
+ 0x23, 2, 0XBC, 0XC1,
+ 0x23, 2, 0XBD, 0X00,
+ 0x23, 2, 0XBE, 0XD2,
+ 0x23, 2, 0XBF, 0X00,
+ 0x23, 2, 0XC0, 0XDF,
+ 0x23, 2, 0XC1, 0X01,
+ 0x23, 2, 0XC2, 0X11,
+ 0x23, 2, 0XC3, 0X01,
+ 0x23, 2, 0XC4, 0X38,
+ 0x23, 2, 0XC5, 0X01,
+ 0x23, 2, 0XC6, 0X76,
+ 0x23, 2, 0XC7, 0X01,
+ 0x23, 2, 0XC8, 0XA7,
+ 0x23, 2, 0XC9, 0X01,
+ 0x23, 2, 0XCA, 0XF3,
+ 0x23, 2, 0XCB, 0X02,
+ 0x23, 2, 0XCC, 0X2F,
+ 0x23, 2, 0XCD, 0X02,
+ 0x23, 2, 0XCE, 0X30,
+ 0x23, 2, 0XCF, 0X02,
+ 0x23, 2, 0XD0, 0X66,
+ 0x23, 2, 0XD1, 0X02,
+ 0x23, 2, 0XD2, 0XA0,
+ 0x23, 2, 0XD3, 0X02,
+ 0x23, 2, 0XD4, 0XC5,
+ 0x23, 2, 0XD5, 0X02,
+ 0x23, 2, 0XD6, 0XF8,
+ 0x23, 2, 0XD7, 0X03,
+ 0x23, 2, 0XD8, 0X1B,
+ 0x23, 2, 0XD9, 0X03,
+ 0x23, 2, 0XDA, 0X46,
+ 0x23, 2, 0XDB, 0X03,
+ 0x23, 2, 0XDC, 0X52,
+ 0x23, 2, 0XDD, 0X03,
+ 0x23, 2, 0XDE, 0X62,
+ 0x23, 2, 0XDF, 0X03,
+ 0x23, 2, 0XE0, 0X71,
+ 0x23, 2, 0XE1, 0X03,
+ 0x23, 2, 0XE2, 0X83,
+ 0x23, 2, 0XE3, 0X03,
+ 0x23, 2, 0XE4, 0X94,
+ 0x23, 2, 0XE5, 0X03,
+ 0x23, 2, 0XE6, 0XA3,
+ 0x23, 2, 0XE7, 0X03,
+ 0x23, 2, 0XE8, 0XAD,
+ 0x23, 2, 0XE9, 0X03,
+ 0x23, 2, 0XEA, 0XCC,
+
+ 0x23, 2, 0XFF, 0X01, //CMD page select
+ 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
+ 0x23, 2, 0XFF, 0X02, //CMD page select
+ 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
+ 0x23, 2, 0XFF, 0X04, //CMD page select
+ 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
+ 0x23, 2, 0XFF, 0X00, //CMD page select
+
+ 0x23, 2, 0XD3, 0X05,
+ 0x23, 2, 0XD4, 0X04,
+
+ 0x23, 2, 0X11, 0X00, //Sleep out
+ 0xfd, 1, 100, //delay 100ms
+ 0x23, 2, 0XFF, 0X00,
+
+ 0x23, 2, 0X35, 0X00, //TE on
+
+ 0x23, 2, 0X29, 0X00, //Display on
+ 0xfd, 1, 100, //delay 100ms
+ 0xff, 0, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_TL050FHV02CT[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xfd, 1, 10, /* delay 10ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xfd, 1, 150, /* delay 150ms */
+ 0xFF, 0, /* ending flag */
+};
+
+#endif
+
diff --git a/board/amlogic/g12b_w400_v1/Kconfig b/board/amlogic/g12b_w400_v1/Kconfig
new file mode 100755
index 0000000..e596a47
--- /dev/null
+++ b/board/amlogic/g12b_w400_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_G12B
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "g12b_w400_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "g12b"
+
+config SYS_CONFIG_NAME
+ default "g12b_w400_v1"
+
+endif
diff --git a/board/amlogic/g12b_w400_v1/Makefile b/board/amlogic/g12b_w400_v1/Makefile
new file mode 100755
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/g12b_w400_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/g12b_w400_v1/aml-user-key.sig b/board/amlogic/g12b_w400_v1/aml-user-key.sig
new file mode 100755
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/g12b_w400_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/g12b_w400_v1/eth_setup.c b/board/amlogic/g12b_w400_v1/eth_setup.c
new file mode 100755
index 0000000..3935a1e
--- /dev/null
+++ b/board/amlogic/g12b_w400_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/g12b_w400_v1/eth_setup.c
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/g12b_w400_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12b_w400_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100755
index 0000000..35f79c4
--- /dev/null
+++ b/board/amlogic/g12b_w400_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,40 @@
+/*
+*board/amlogic/g12b_w400_v1/firmware/scp_task/pwm_ctrl.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+#ifndef __PWM_CTRL_H__
+#define __PWM_CTRL_H__
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 681},
+ { 0x1b0001, 691},
+ { 0x1a0002, 701},
+ { 0x190003, 711},
+ { 0x180004, 721},
+ { 0x170005, 731},
+ { 0x160006, 741},
+ { 0x150007, 751},
+ { 0x140008, 761},
+ { 0x130009, 772},
+ { 0x12000a, 782},
+ { 0x11000b, 792},
+ { 0x10000c, 802},
+ { 0x0f000d, 812},
+ { 0x0e000e, 822},
+ { 0x0d000f, 832},
+ { 0x0c0010, 842},
+ { 0x0b0011, 852},
+ { 0x0a0012, 862},
+ { 0x090013, 872},
+ { 0x080014, 882},
+ { 0x070015, 892},
+ { 0x060016, 902},
+ { 0x050017, 912},
+ { 0x040018, 922},
+ { 0x030019, 932},
+ { 0x02001a, 942},
+ { 0x01001b, 952},
+ { 0x00001c, 962}
+};
+
+#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12b_w400_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12b_w400_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100755
index 0000000..60e2f44
--- /dev/null
+++ b/board/amlogic/g12b_w400_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,174 @@
+
+/*
+ * board/amlogic/g12b_w400_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <gpio.h>
+#include "pwm_ctrl.h"
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void set_vddee_voltage(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage) {
+ break;
+ }
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+}
+
+static void power_off_at_24M(unsigned int suspend_from)
+{
+ /*set gpioH_8 low to power off vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+
+ /*set gpioao_4 low to power off vcck_a*/
+ writel(readl(AO_GPIO_O) & (~(1 << 4)), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 4)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG) & (~(0xf << 16)), AO_RTI_PIN_MUX_REG);
+ /*set test_n low to power off vcck_b & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+
+ /*step down ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_SLEEP_VOLTAGE);
+}
+
+static void power_on_at_24M(unsigned int suspend_from)
+{
+ /*step up ee voltage*/
+ set_vddee_voltage(CONFIG_VDDEE_INIT_VOLTAGE);
+
+ /*set test_n high to power on vcck_b & vcc 3.3v*/
+ writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
+ _udelay(100);
+ /*set gpioao_4 high to power on vcck_a*/
+ writel(readl(AO_GPIO_O) | (1 << 4), AO_GPIO_O);
+ writel(readl(AO_GPIO_O_EN_N) & (~(1 << 4)), AO_GPIO_O_EN_N);
+ writel(readl(AO_RTI_PIN_MUX_REG) & (~(0xf << 16)), AO_RTI_PIN_MUX_REG);
+ _udelay(100);
+ /*set gpioH_8 low to power on vcc 5v*/
+ writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
+ writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
+ _udelay(10000);
+
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ struct wakeup_gpio_info *gpio;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ BT_WAKEUP_SRC);
+
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_3;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+}
+extern void __switch_idle_task(void);
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ do {
+ #ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+ if (cec_power_on_check())
+ exit_reason = CEC_WAKEUP;
+ }
+ #endif
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+ if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
+ irq[IRQ_VRTC] = 0xFFFFFFFF;
+ exit_reason = RTC_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<3)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+
+ if (irq[IRQ_ETH_PTM] == IRQ_ETH_PMT_NUM) {
+ irq[IRQ_ETH_PTM]= 0xFFFFFFFF;
+ exit_reason = ETH_PMT_WAKEUP;
+ }
+
+ if (exit_reason)
+ break;
+ else
+ __switch_idle_task();
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/g12b_w400_v1/firmware/timing.c b/board/amlogic/g12b_w400_v1/firmware/timing.c
new file mode 100755
index 0000000..d4eb351
--- /dev/null
+++ b/board/amlogic/g12b_w400_v1/firmware/timing.c
@@ -0,0 +1,518 @@
+
+/*
+ * board/amlogic/g12b_w400_v1/firmware/timing.c
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] = {
+{
+ /* ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1200, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0xffff,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0c0c,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* lpddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+{
+ /* Y2 dongle */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1392, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0808,
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
+ .dram_rtt_nom_wr_park = {00,00},
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL CONFIG_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL CONFIG_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0000001c
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG0: VDDEE PWM table 0.67v-0.97v*/
+/* VDDEE_VAL_REG1: VDDEE PWM table 0.69v-0.89v*/
+#if (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG0 0x0010000c
+ #define VDDEE_VAL_REG1 0x0008000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG0 0x000f000d
+ #define VDDEE_VAL_REG1 0x0007000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG0 0x000e000e
+ #define VDDEE_VAL_REG1 0x0006000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG0 0x000d000f
+ #define VDDEE_VAL_REG1 0x0005000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG0 0x000c0010
+ #define VDDEE_VAL_REG1 0x0004000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG0 0x000b0011
+ #define VDDEE_VAL_REG1 0x00030019
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG0 0x000a0012
+ #define VDDEE_VAL_REG1 0x00020010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG0 0x00090013
+ #define VDDEE_VAL_REG1 0x00010011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG0 0x00080014
+ #define VDDEE_VAL_REG1 0x00000012
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ /* eg: PWM init */
+
+ /* PWM_AO_D */
+ /* VCCK_VAL_REG: check PWM table */
+ {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
+
+ /* set BOOT_9 input */
+ //{PAD_PULL_UP_EN_REG0, 1 << 9, 1 << 9, 0, BL2_INIT_STAGE_1, 0},
+
+ /* PWM_AO_B */
+ /* VDDEE init start */
+ /* step1: CHK HW */
+ {(uint64_t)P_ASSIST_POR_CONFIG, 7, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
+
+ /* step2: match PWM config */
+ /* GPIO9[BIT7]=H use PWM_CFG0(0.67v-0.97v), =L use PWM_CFG1(0.69v-0.89v) */
+ {0x1, PWM_CFG0, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
+ {0x0, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
+
+ /* step3: config PWM */
+ /* VDDEE_VAL_REG0: VDDEE PWM table 0.67v-0.97v*/
+ {AO_PWM_PWM_B, VDDEE_VAL_REG0, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
+ /* VDDEE_VAL_REG1: VDDEE PWM table 0.69v-0.89v*/
+ {AO_PWM_PWM_B, VDDEE_VAL_REG1, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
+ {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
+ {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
+ /* VDDEE init done */
+
+ /* Enable 5V_EN */
+ {GPIO_O_EN_N_REG3, (1 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ {GPIO_O_REG3, (1 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable CPUA ,control by GPIOAO_4 */
+ {AO_GPIO_O_EN_N, (0 << 4), (1 << 4), 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 4), (1 << 4), 0, BL2_INIT_STAGE_1, 0},
+ /* Enable VCCK */
+ {AO_SEC_REG0, (1 << 0), (1 << 0), 0, BL2_INIT_STAGE_1, 0},
+ {AO_GPIO_O, (1 << 31), (1 << 31), 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/g12b_w400_v1/g12b_w400_v1.c b/board/amlogic/g12b_w400_v1/g12b_w400_v1.c
new file mode 100755
index 0000000..37edd5f
--- /dev/null
+++ b/board/amlogic/g12b_w400_v1/g12b_w400_v1.c
@@ -0,0 +1,783 @@
+
+/*
+ * board/amlogic/g12b_w400_v1/g12b_w400_v1.c
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#endif
+#ifdef CONFIG_SYS_I2C_MESON
+#include <amlogic/i2c.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#ifdef CONFIG_AML_SPIFC
+#include <amlogic/spifc.h>
+#endif
+#ifdef CONFIG_AML_SPICC
+#include <amlogic/spicc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+#ifdef ETHERNET_INTERNAL_PHY
+void internalPhyConfig(struct phy_device *phydev)
+{
+}
+
+static int dwmac_meson_cfg_pll(void)
+{
+ writel(0x39C0040A, P_ETH_PLL_CTL0);
+ writel(0x927E0000, P_ETH_PLL_CTL1);
+ writel(0xAC5F49E5, P_ETH_PLL_CTL2);
+ writel(0x00000000, P_ETH_PLL_CTL3);
+ udelay(200);
+ writel(0x19C0040A, P_ETH_PLL_CTL0);
+ return 0;
+}
+
+static int dwmac_meson_cfg_analog(void)
+{
+ /*Analog*/
+ writel(0x20200000, P_ETH_PLL_CTL5);
+ writel(0x0000c002, P_ETH_PLL_CTL6);
+ writel(0x00000023, P_ETH_PLL_CTL7);
+
+ return 0;
+}
+
+static int dwmac_meson_cfg_ctrl(void)
+{
+ /*config phyid should between a 0~0xffffffff*/
+ /*please don't use 44000181, this has been used by internal phy*/
+ writel(0x33000180, P_ETH_PHY_CNTL0);
+
+ /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
+ writel(0x260, P_ETH_PHY_CNTL2);
+
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ writel(0x34043, P_ETH_PHY_CNTL1);
+ writel(0x74043, P_ETH_PHY_CNTL1);
+ return 0;
+}
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 1;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 9;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ dwmac_meson_cfg_pll();
+ dwmac_meson_cfg_analog();
+ dwmac_meson_cfg_ctrl();
+
+ /* eth core clock */
+ setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
+ /* eth phy clock */
+ setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
+
+ /* eth phy pll, clk50m */
+ setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+
+static int dwmac_meson_cfg_drive_strength(void)
+{
+ writel(0xaaaaaaa5, P_PAD_DS_REG4A);
+ return 0;
+}
+
+static void setup_net_chip_ext(void)
+{
+ eth_aml_reg0_t eth_reg0;
+ writel(0x11111111, P_PERIPHS_PIN_MUX_6);
+ writel(0x111111, P_PERIPHS_PIN_MUX_7);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+}
+#endif
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_ETHERNET_NONE
+ return 0;
+#endif
+
+#ifdef ETHERNET_EXTERNAL_PHY
+ dwmac_meson_cfg_drive_strength();
+ setup_net_chip_ext();
+#endif
+#ifdef ETHERNET_INTERNAL_PHY
+ setup_net_chip();
+#endif
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ /* check card detect */
+ clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
+ setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
+ setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+#include <asm/arch/usb-v2.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
+#define CONFIG_GXL_USB_U3_PORT_NUM 1
+#else
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+#endif
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ int ret;
+
+ ret = gpio_request(CONFIG_USB_GPIO_PWR,
+ CONFIG_USB_GPIO_PWR_NAME);
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n",
+ CONFIG_USB_GPIO_PWR);
+ return;
+ }
+
+ if (is_power_on) {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
+ } else {
+ gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
+ }
+}
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+ .usb_phy2_pll_base_addr = {
+ CONFIG_USB_PHY_20,
+ CONFIG_USB_PHY_21,
+ }
+};
+
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 280*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_7: NOR_WPn:reg0[31:28]=3
+ * BOOT_14: NOR_CS:reg1[27:24]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xfffff << 12);
+ if (enable)
+ val |= 0x33333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~(0xf << 24);
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xf6000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+#ifdef CONFIG_AML_SPICC
+/* generic config in arch gpio/clock.c */
+extern int spicc1_clk_set_rate(int rate);
+extern int spicc1_clk_enable(bool enable);
+extern int spicc1_pinctrl_enable(bool enable);
+
+static const struct spicc_platdata spicc1_platdata = {
+ .compatible = "amlogic,meson-g12a-spicc",
+ .reg = (void __iomem *)0xffd15000,
+ .clk_rate = 666666666,
+ .clk_set_rate = spicc1_clk_set_rate,
+ .clk_enable = spicc1_clk_enable,
+ .pinctrl_enable = spicc1_pinctrl_enable,
+ /* case one slave without cs: {"no_cs", 0} */
+ .cs_gpio_names = {"GPIOH_6", 0},
+};
+
+U_BOOT_DEVICE(spicc1) = {
+ .name = "spicc",
+ .platdata = &spicc1_platdata,
+};
+#endif /* CONFIG_AML_SPICC */
+
+#ifdef CONFIG_SYS_I2C_MESON
+static const struct meson_i2c_platdata i2c_data[] = {
+ { 0, 0xffd1f000, 166666666, 3, 15, 100000 },
+ { 1, 0xffd1e000, 166666666, 3, 15, 100000 },
+ { 2, 0xffd1d000, 166666666, 3, 15, 100000 },
+ { 3, 0xffd1c000, 166666666, 3, 15, 100000 },
+ { 4, 0xff805000, 166666666, 3, 15, 100000 },
+};
+
+U_BOOT_DEVICES(meson_i2cs) = {
+ { "i2c_meson", &i2c_data[0] },
+ { "i2c_meson", &i2c_data[1] },
+ { "i2c_meson", &i2c_data[2] },
+ { "i2c_meson", &i2c_data[3] },
+ { "i2c_meson", &i2c_data[4] },
+};
+
+/*
+ *GPIOH_6 I2C_SDA_M1
+ *GPIOH_7 I2C_SCK_M1
+ *pinmux configuration seperated with i2c controller configuration
+ * config it when you use
+ */
+void set_i2c_m1_pinmux(void)
+{
+ /*ds =3 */
+ clrbits_le32(PAD_DS_REG3A, 0xf << 12);
+ setbits_le32(PAD_DS_REG3A, 0x3 << 12 | 0x3 << 14);
+ /*pull up en*/
+ clrbits_le32(PAD_PULL_UP_EN_REG3, 0x3 << 6);
+ setbits_le32(PAD_PULL_UP_EN_REG3, 0x3 << 6 );
+ /*pull up*/
+ clrbits_le32(PAD_PULL_UP_REG3, 0x3 << 6);
+ setbits_le32(PAD_PULL_UP_REG3, 0x3 << 6 );
+ /*pin mux to i2cm1*/
+ clrbits_le32(PERIPHS_PIN_MUX_B, 0xff << 24);
+ setbits_le32(PERIPHS_PIN_MUX_B, 0x4 << 24 | 0x4 << 28);
+
+ return;
+}
+
+#endif /*end CONFIG_SYS_I2C_MESON*/
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+ //As NOT NEED other board init If USB BOOT MODE
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
+ board_usb_pll_disable(&g_usb_config_GXL_skt);
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#if 0
+ aml_pwm_cal_init(0);
+#endif//
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+#ifdef CONFIG_SYS_I2C_MESON
+ set_i2c_m1_pinmux();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+#ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+#endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 1 p321 v1
+ * hwid = 2 p321 v2
+ */
+ unsigned int hwid = 1;
+ char loc_name[64] = {0};
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+
+ switch (hwid) {
+ case 1:
+ strcpy(loc_name, "g12b_w400_v1\0");
+ break;
+ case 2:
+ strcpy(loc_name, "g12b_w400_v2\0");
+ break;
+ default:
+ strcpy(loc_name, "g12b_w400_v1");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+ "lock",
+
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/g12b_w400_v1/lcd.c b/board/amlogic/g12b_w400_v1/lcd.c
new file mode 100755
index 0000000..96bde4d
--- /dev/null
+++ b/board/amlogic/g12b_w400_v1/lcd.c
@@ -0,0 +1,512 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+#ifdef CONFIG_AML_LCD_EXTERN
+#include "lcd_extern.h"
+#endif
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_9", /* panel rst */
+ "GPIOZ_8", /* panel power */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
+ {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
+ {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_4", /* BL_EN */
+ "GPIOH_5", /* BL_PWM */
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* B080XAN01*/
+ "lcd_0",LCD_MIPI,8,
+ /* basic timing */
+ 768,1024,948,1140,64,56,0,50,30,0,
+ /* clk_attr */
+ 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TL070WSH27*/
+ "lcd_1",LCD_MIPI,8,
+ /* basic timing */
+ 1024,600,1250,630,80,100,0,5,20,0,
+ /* clk_attr */
+ 0,0,1,47250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,300,0,1,0,2,1,0,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* TL070HDV03CT*/
+ "lcd_2",LCD_MIPI,8,
+ /* basic timing */
+ 720,1280,970,1364,10,120,0,4,40,0,
+ /* clk_attr */
+ 0,0,1,79385000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,500,0,1,0,2,1,0,Rsv_val,2,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* P070ACB_FT*/
+ "lcd_3",LCD_MIPI,8,
+ /* basic timing */
+ 600,1024,680,1194,24,36,0,10,80,0,
+ /* clk_attr */
+ 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* mipi_attr */
+ 4,400,0,1,0,2,0,0,Rsv_val,3,
+ /* power step */
+ lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
+ /* backlight */
+ 100,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_pin",
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOH_5
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xfd, 1, 20,
+ 0x05, 1, 0x29,
+ 0xfd, 1, 20,
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xfd, 1, 10,
+ 0x05, 1, 0x10,
+ 0xfd, 1, 10,
+ 0xff, 0, //ending
+};
+
+static unsigned char mipi_init_on_table_TL070WSH27[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xfd, 1, 200,
+ 0x05, 1, 0x29,
+ 0xfd, 1, 20,
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_TL070WSH27[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xfd, 1, 10,
+ 0x05, 1, 0x10,
+ 0xfd, 1, 10,
+ 0xff, 0, //ending
+};
+
+static unsigned char mipi_init_on_table_TL070HDV03CT[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_TL070HDV03CT[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff, 0, //ending
+};
+
+static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
+ 0xfd, 1, 10,
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
+ 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
+ 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0xff, 0, //ending
+};
+
+static struct dsi_config_s lcd_mipi_config = {
+ .lane_num = 4,
+ .bit_rate_max = 550, /* MHz */
+ .factor_numerator = 0,
+ .factor_denominator = 100,
+ .operation_mode_init = 1, /* 0=video mode, 1=command mode */
+ .operation_mode_display = 0, /* 0=video mode, 1=command mode */
+ .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
+ .clk_always_hs = 1, /* 0=disable, 1=enable */
+ .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
+
+ .dsi_init_on = &mipi_init_on_table[0],
+ .dsi_init_off = &mipi_init_off_table[0],
+ .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
+ .check_en = 0,
+ .check_state = 0,
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 10, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_clk_path = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX,
+ .lcd_bits = 8,
+ .h_active = 768,
+ .v_active = 1024,
+ .h_period = 948,
+ .v_period = 1140,
+
+ .screen_width = 119,
+ .screen_height = 159,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 64843200,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 64,
+ .hsync_bp = 56,
+ .hsync_pol = 0,
+ .vsync_width = 50,
+ .vsync_bp = 30,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .mipi_config= &lcd_mipi_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0, //ending flag
+};
+
+static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, //ending flag
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 4,
+ .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table,
+ .table_init_on_cnt = sizeof(ext_init_on_table),
+ .table_init_off = ext_init_off_table,
+ .table_init_off_cnt = sizeof(ext_init_off_table),
+ },
+ { /* TL070WSH27 */
+ .index = 1,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_TL070WSH27,
+ .table_init_on_cnt = sizeof(ext_init_on_table_TL070WSH27),
+ .table_init_off = ext_init_off_table_TL070WSH27,
+ .table_init_off_cnt = sizeof(ext_init_off_table_TL070WSH27),
+ },
+ { /* TL070HDV03CT */
+ .index = 2,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_TL070HDV03CT,
+ .table_init_on_cnt = sizeof(ext_init_on_table_TL070HDV03CT),
+ .table_init_off = ext_init_off_table_TL070HDV03CT,
+ .table_init_off_cnt = sizeof(ext_init_off_table_TL070HDV03CT),
+ },
+ { /* P070ACB_FT */
+ .index = 3,
+ .name = "mipi_default",
+ .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
+ .table_init_on = ext_init_on_table_P070ACB_FT,
+ .table_init_on_cnt = sizeof(ext_init_on_table_P070ACB_FT),
+ .table_init_off = ext_init_off_table_P070ACB_FT,
+ .table_init_off_cnt = sizeof(ext_init_off_table_P070ACB_FT),
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .bl_extern_index = 0xff,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_BL_EXTERN
+static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX];
+static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX];
+struct bl_extern_config_s bl_extern_config_dtf = {
+ .index = BL_EXTERN_INDEX_INVALID,
+ .name = "none",
+ .type = BL_EXTERN_MAX,
+ .i2c_addr = 0xff,
+ .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
+ .dim_min = 10,
+ .dim_max = 255,
+
+ .init_loaded = 0,
+ .cmd_size = 0xff,
+ .init_on = bl_ext_init_on,
+ .init_off = bl_ext_init_off,
+ .init_on_cnt = sizeof(bl_ext_init_on),
+ .init_off_cnt = sizeof(bl_ext_init_off),
+};
+#endif
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+ char *str;
+ struct ext_lcd_config_s *ext_lcd = NULL;
+
+ str = getenv("panel_type");
+ if (str) {
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ ext_lcd = &ext_lcd_config[i];
+ if (strcmp(ext_lcd->panel_type, str) == 0) {
+ switch (i) {
+ case 1: /* TL070WSH27 */
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TL070WSH27;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TL070WSH27;
+ break;
+ case 2: /* TL070HDV03CT */
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_TL070HDV03CT;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_TL070HDV03CT;
+ break;
+ case 3:/* P070ACB_FT*/
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table_P070ACB;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table_P070ACB;
+ break;
+ case 0:
+ default:
+ lcd_mipi_config.dsi_init_on = mipi_init_on_table;
+ lcd_mipi_config.dsi_init_off = mipi_init_off_table;
+ break;
+ }
+ break;
+ }
+ }
+ }
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/g12b_w400_v1/lcd_extern.h b/board/amlogic/g12b_w400_v1/lcd_extern.h
new file mode 100755
index 0000000..d5f7ddc
--- /dev/null
+++ b/board/amlogic/g12b_w400_v1/lcd_extern.h
@@ -0,0 +1,504 @@
+/*
+ * board/amlogic/g12b_w400_v1/lcd_extern.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _DFT_LCD_EXTERN_H_
+#define _DFT_LCD_EXTERN_H_
+
+static unsigned char ext_init_on_table_TL070WSH27[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x15, 2, 0x25, 0x55,
+ 0x15, 2, 0x36, 0x01,
+ //0x15, 2, 0x25, 0x00,
+
+ 0x15, 2, 0xB1, 0x30,
+ 0x15, 2, 0xB2, 0x10,
+ 0x15, 2, 0x80, 0x58,
+ 0x15, 2, 0x81, 0x47,
+ 0x15, 2, 0x82, 0xD4,
+ 0x15, 2, 0x83, 0x88,
+ 0x15, 2, 0x84, 0xA9,
+ 0x15, 2, 0x85, 0xC3,
+ 0x15, 2, 0x86, 0x82,
+ 0xfd, 1, 150, /* delay 150ms */
+
+ 0x05, 1, 0x11,
+ 0xfd, 1, 200, /* delay 120ms */
+ 0x05, 1, 0x29,
+ 0xff, 0, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_TL070WSH27[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xfd, 1, 30, /* delay 30ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xfd, 1, 10,
+ 0xff, 0, /* ending flag */
+};
+
+static unsigned char ext_init_on_table_TL070HDV03CT[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x39, 4, 0xFF, 0x98, 0x81, 0x03,
+ 0x15, 2, 0x01, 0x00,
+ 0x15, 2, 0x02, 0x00,
+ 0x15, 2, 0x03, 0x72,
+ 0x15, 2, 0x04, 0x00,
+ 0x15, 2, 0x05, 0x00,
+ 0x15, 2, 0x06, 0x09,
+ 0x15, 2, 0x07, 0x00,
+ 0x15, 2, 0x08, 0x00,
+ 0x15, 2, 0x09, 0x01,
+ 0x15, 2, 0x0A, 0x00,
+ 0x15, 2, 0x0B, 0x00,
+ 0x15, 2, 0x0C, 0x01,
+ 0x15, 2, 0x0D, 0x00,
+ 0x15, 2, 0x0E, 0x00,
+ 0x15, 2, 0x0F, 0x14,
+ 0x15, 2, 0x10, 0x14,
+ 0x15, 2, 0x11, 0x00,
+ 0x15, 2, 0x12, 0x00,
+ 0x15, 2, 0x13, 0x00,
+ 0x15, 2, 0x14, 0x00,
+ 0x15, 2, 0x15, 0x00,
+ 0x15, 2, 0x16, 0x00,
+ 0x15, 2, 0x17, 0x00,
+ 0x15, 2, 0x18, 0x00,
+ 0x15, 2, 0x19, 0x00,
+ 0x15, 2, 0x1A, 0x00,
+ 0x15, 2, 0x1B, 0x00,
+ 0x15, 2, 0x1C, 0x00,
+ 0x15, 2, 0x1D, 0x00,
+ 0x15, 2, 0x1E, 0x40,
+ 0x15, 2, 0x1F, 0x80,
+ 0x15, 2, 0x20, 0x05,
+ 0x15, 2, 0x21, 0x02,
+ 0x15, 2, 0x22, 0x00,
+ 0x15, 2, 0x23, 0x00,
+ 0x15, 2, 0x24, 0x00,
+ 0x15, 2, 0x25, 0x00,
+ 0x15, 2, 0x26, 0x00,
+ 0x15, 2, 0x27, 0x00,
+ 0x15, 2, 0x28, 0x33,
+ 0x15, 2, 0x29, 0x02,
+ 0x15, 2, 0x2A, 0x00,
+ 0x15, 2, 0x2B, 0x00,
+ 0x15, 2, 0x2C, 0x00,
+ 0x15, 2, 0x2D, 0x00,
+ 0x15, 2, 0x2E, 0x00,
+ 0x15, 2, 0x2F, 0x00,
+ 0x15, 2, 0x30, 0x00,
+ 0x15, 2, 0x31, 0x00,
+ 0x15, 2, 0x32, 0x00,
+ 0x15, 2, 0x33, 0x00,
+ 0x15, 2, 0x34, 0x04,
+ 0x15, 2, 0x35, 0x00,
+ 0x15, 2, 0x36, 0x00,
+ 0x15, 2, 0x37, 0x00,
+ 0x15, 2, 0x38, 0x3C,
+ 0x15, 2, 0x39, 0x00,
+ 0x15, 2, 0x3A, 0x00,
+ 0x15, 2, 0x3B, 0x00,
+ 0x15, 2, 0x3C, 0x00,
+ 0x15, 2, 0x3D, 0x00,
+ 0x15, 2, 0x3E, 0x00,
+ 0x15, 2, 0x3F, 0x00,
+ 0x15, 2, 0x40, 0x00,
+ 0x15, 2, 0x41, 0x00,
+ 0x15, 2, 0x42, 0x00,
+ 0x15, 2, 0x43, 0x00,
+ 0x15, 2, 0x44, 0x00,
+
+ 0x15, 2, 0x50, 0x10,
+ 0x15, 2, 0x51, 0x32,
+ 0x15, 2, 0x52, 0x54,
+ 0x15, 2, 0x53, 0x76,
+ 0x15, 2, 0x54, 0x98,
+ 0x15, 2, 0x55, 0xBA,
+ 0x15, 2, 0x56, 0x10,
+ 0x15, 2, 0x57, 0x32,
+ 0x15, 2, 0x58, 0x54,
+ 0x15, 2, 0x59, 0x76,
+ 0x15, 2, 0x5A, 0x98,
+ 0x15, 2, 0x5B, 0xBA,
+ 0x15, 2, 0x5C, 0xDC,
+ 0x15, 2, 0x5D, 0xFE,
+ 0x15, 2, 0x5E, 0x00,
+ 0x15, 2, 0x5F, 0x0E,
+ 0x15, 2, 0x60, 0x0F,
+ 0x15, 2, 0x61, 0x0C,
+ 0x15, 2, 0x62, 0x0D,
+ 0x15, 2, 0x63, 0x06,
+ 0x15, 2, 0x64, 0x07,
+ 0x15, 2, 0x65, 0x02,
+ 0x15, 2, 0x66, 0x02,
+ 0x15, 2, 0x67, 0x02,
+ 0x15, 2, 0x68, 0x02,
+ 0x15, 2, 0x69, 0x01,
+ 0x15, 2, 0x6A, 0x00,
+ 0x15, 2, 0x6B, 0x02,
+ 0x15, 2, 0x6C, 0x15,
+ 0x15, 2, 0x6D, 0x14,
+ 0x15, 2, 0x6E, 0x02,
+ 0x15, 2, 0x6F, 0x02,
+ 0x15, 2, 0x70, 0x02,
+ 0x15, 2, 0x71, 0x02,
+ 0x15, 2, 0x72, 0x02,
+ 0x15, 2, 0x73, 0x02,
+ 0x15, 2, 0x74, 0x02,
+ 0x15, 2, 0x75, 0x0E,
+ 0x15, 2, 0x76, 0x0F,
+ 0x15, 2, 0x77, 0x0C,
+ 0x15, 2, 0x78, 0x0D,
+ 0x15, 2, 0x79, 0x06,
+ 0x15, 2, 0x7A, 0x07,
+ 0x15, 2, 0x7B, 0x02,
+ 0x15, 2, 0x7C, 0x02,
+ 0x15, 2, 0x7D, 0x02,
+ 0x15, 2, 0x7E, 0x02,
+ 0x15, 2, 0x7F, 0x01,
+ 0x15, 2, 0x80, 0x00,
+ 0x15, 2, 0x81, 0x02,
+ 0x15, 2, 0x82, 0x14,
+ 0x15, 2, 0x83, 0x15,
+ 0x15, 2, 0x84, 0x02,
+ 0x15, 2, 0x85, 0x02,
+ 0x15, 2, 0x86, 0x02,
+ 0x15, 2, 0x87, 0x02,
+ 0x15, 2, 0x88, 0x02,
+ 0x15, 2, 0x89, 0x02,
+ 0x15, 2, 0x8A, 0x02,
+
+ 0x39, 4, 0xFF, 0x98, 0x81, 0x04,
+ 0x15, 2, 0x6C, 0x15,
+ 0x15, 2, 0x6E, 0x2A,
+ 0x15, 2, 0x6F, 0x33, //33
+ 0x15, 2, 0x3A, 0x94,
+ 0x15, 2, 0x8D, 0x14,
+ 0x15, 2, 0x87, 0xBA,
+ 0x15, 2, 0x26, 0x76,
+ 0x15, 2, 0xB2, 0xD1,
+ 0x15, 2, 0xB5, 0x06,
+
+ 0x39, 4, 0xFF, 0x98, 0x81, 0x01,
+ 0x15, 2, 0x22, 0x02, //xiugai RGB
+ 0x15, 2, 0x31, 0x00, //dot inv
+ //0x15, 2, 0x52, 0x00,
+ 0x15, 2, 0x53, 0x72, //vcom
+ //0x15, 2, 0x54, 0x00, //vcom
+ 0x15, 2, 0x55, 0x88,
+
+ 0x15, 2, 0x40, 0x33,
+
+ 0x15, 2, 0x50, 0x96,
+ 0x15, 2, 0x51, 0x96,
+
+ 0x15, 2, 0x60, 0x08,
+
+ 0x15, 2, 0xA0, 0x08, //GAMMA P
+ 0x15, 2, 0xA1, 0x1D,
+ 0x15, 2, 0xA2, 0x2A,
+ 0x15, 2, 0xA3, 0x10,
+ 0x15, 2, 0xA4, 0x15,
+ 0x15, 2, 0xA5, 0x28,
+ 0x15, 2, 0xA6, 0x1C,
+ 0x15, 2, 0xA7, 0x1D,
+ 0x15, 2, 0xA8, 0x7E,
+ 0x15, 2, 0xA9, 0x1D,
+ 0x15, 2, 0xAA, 0x29,
+ 0x15, 2, 0xAB, 0x6B,
+ 0x15, 2, 0xAC, 0x1A,
+ 0x15, 2, 0xAD, 0x18,
+ 0x15, 2, 0xAE, 0x4B,
+ 0x15, 2, 0xAF, 0x20,
+ 0x15, 2, 0xB0, 0x27,
+ 0x15, 2, 0xB1, 0x50,
+ 0x15, 2, 0xB2, 0x64,
+ 0x15, 2, 0xB3, 0x39,
+
+ 0x15, 2, 0xC0, 0x08, //GAMMA N
+ 0x15, 2, 0xC1, 0x1D,
+ 0x15, 2, 0xC2, 0x2A,
+ 0x15, 2, 0xC3, 0x10,
+ 0x15, 2, 0xC4, 0x15,
+ 0x15, 2, 0xC5, 0x28,
+ 0x15, 2, 0xC6, 0x1C,
+ 0x15, 2, 0xC7, 0x1D,
+ 0x15, 2, 0xC8, 0x7E,
+ 0x15, 2, 0xC9, 0x1D,
+ 0x15, 2, 0xCA, 0x29,
+ 0x15, 2, 0xCB, 0x6B,
+ 0x15, 2, 0xCC, 0x1A,
+ 0x15, 2, 0xCD, 0x18,
+ 0x15, 2, 0xCE, 0x4B,
+ 0x15, 2, 0xCF, 0x20,
+ 0x15, 2, 0xD0, 0x27,
+ 0x15, 2, 0xD1, 0x50,
+ 0x15, 2, 0xD2, 0x64,
+ 0x15, 2, 0xD3, 0x39,
+
+ 0x39, 4, 0xFF, 0x98, 0x81, 0x00,
+
+ 0x15, 2, 0x3A, 0x77,
+ 0xfd, 1, 2,
+
+ 0x15, 2, 0x36, 0x08,
+
+ 0x05, 1, 0x11, //display on
+ 0xfd, 1, 200,
+
+ 0x05, 1, 0x29, //display on
+ 0xfd, 1, 200,
+ 0xFF, 0, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_TL070HDV03CT[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xfd, 1, 10, /* delay 10ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xfd, 1, 150, /* delay 150ms */
+ 0xFF, 0, /* ending flag */
+};
+
+static unsigned char ext_init_on_table_P070ACB_FT[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x23,2,0xE0,0x00,//Page 0
+ 0x23,2,0xE1,0x93,// PASSWORD
+ 0x23,2,0xE2,0x65,
+ 0x23,2,0xE3,0xF8,
+ 0x23,2,0x80,0x03,
+ 0x23,2,0xE0,0x01,//Page 01
+ 0x23,2,0x0C,0x74,//Set PWRIC
+ 0x23,2,0x17,0x00,//Set Gamma Power
+ 0x23,2,0x18,0xEF,//VGMP=5.1V
+ 0x23,2,0x19,0x00,
+ 0x23,2,0x1A,0x00,
+ 0x23,2,0x1B,0xEF,//VGMN=-5.1V
+ 0x23,2,0x1C,0x00,
+ 0x23,2,0x1F,0x70,//Set Gate Power
+ 0x23,2,0x20,0x2D,
+ 0x23,2,0x21,0x2D,
+ 0x23,2,0x22,0x7E,
+ 0x23,2,0x26,0xF3,//VDDD from IOVCC
+ 0x23,2,0x37,0x09,//SetPanel
+ 0x23,2,0x38,0x04,//SET RGBCYC
+ 0x23,2,0x39,0x00,
+ 0x23,2,0x3A,0x01,
+ 0x23,2,0x3C,0x90,
+ 0x23,2,0x3D,0xFF,
+ 0x23,2,0x3E,0xFF,
+ 0x23,2,0x3F,0xFF,
+ 0x23,2,0x40,0x02,//Set TCON
+ 0x23,2,0x41,0x80,
+ 0x23,2,0x42,0x99,
+ 0x23,2,0x43,0x14,
+ 0x23,2,0x44,0x19,
+ 0x23,2,0x45,0x5A,
+ 0x23,2,0x4B,0x04,
+ 0x23,2,0x55,0x02,//power voltage
+ 0x23,2,0x56,0x01,
+ 0x23,2,0x57,0x69,
+ 0x23,2,0x58,0x0A,
+ 0x23,2,0x59,0x0A,
+ 0x23,2,0x5A,0x2E,//VGH = 16.2V
+ 0x23,2,0x5B,0x19,//VGL = -12V
+ 0x23,2,0x5C,0x15,
+ 0x23,2,0x5D,0x77,//Gamma
+ 0x23,2,0x5E,0x56,
+ 0x23,2,0x5F,0x45,
+ 0x23,2,0x60,0x38,
+ 0x23,2,0x61,0x35,
+ 0x23,2,0x62,0x27,
+ 0x23,2,0x63,0x2D,
+ 0x23,2,0x64,0x18,
+ 0x23,2,0x65,0x33,
+ 0x23,2,0x66,0x34,
+ 0x23,2,0x67,0x35,
+ 0x23,2,0x68,0x56,
+ 0x23,2,0x69,0x45,
+ 0x23,2,0x6A,0x4F,
+ 0x23,2,0x6B,0x42,
+ 0x23,2,0x6C,0x40,
+ 0x23,2,0x6D,0x34,
+ 0x23,2,0x6E,0x25,
+ 0x23,2,0x6F,0x02,
+ 0x23,2,0x70,0x77,
+ 0x23,2,0x71,0x56,
+ 0x23,2,0x72,0x45,
+ 0x23,2,0x73,0x38,
+ 0x23,2,0x74,0x35,
+ 0x23,2,0x75,0x27,
+ 0x23,2,0x76,0x2D,
+ 0x23,2,0x77,0x18,
+ 0x23,2,0x78,0x33,
+ 0x23,2,0x79,0x34,
+ 0x23,2,0x7A,0x35,
+ 0x23,2,0x7B,0x56,
+ 0x23,2,0x7C,0x45,
+ 0x23,2,0x7D,0x4F,
+ 0x23,2,0x7E,0x42,
+ 0x23,2,0x7F,0x40,
+ 0x23,2,0x80,0x34,
+ 0x23,2,0x81,0x25,
+ 0x23,2,0x82,0x02,
+ 0x23,2,0xE0,0x02,//Page2
+ 0x23,2,0x00,0x53,//GIP_L Pin mapping RESET_EVEN
+ 0x23,2,0x01,0x55,//VSSG_EVEN
+ 0x23,2,0x02,0x55,//VSSA_EVEN
+ 0x23,2,0x03,0x51,//STV2_EVEN
+ 0x23,2,0x04,0x77,//VDD2_EVEN
+ 0x23,2,0x05,0x57,//VDD1_EVEN
+ 0x23,2,0x06,0x1F,
+ 0x23,2,0x07,0x4F, //CK12
+ 0x23,2,0x08,0x4D, //CK10
+ 0x23,2,0x09,0x1F,
+ 0x23,2,0x0A,0x4B, //CK8
+ 0x23,2,0x0B,0x49, //CK6
+ 0x23,2,0x0C,0x1F,
+ 0x23,2,0x0D,0x47, //CK4
+ 0x23,2,0x0E,0x45, //CK2
+ 0x23,2,0x0F,0x41, //STV1_EVEN
+ 0x23,2,0x10,0x1F,
+ 0x23,2,0x11,0x1F,
+ 0x23,2,0x12,0x1F,
+ 0x23,2,0x13,0x55, //VGG
+ 0x23,2,0x14,0x1F,
+ 0x23,2,0x15,0x1F,
+ 0x23,2,0x16,0x52,//GIP_R Pin mapping RESET_ODD
+ 0x23,2,0x17,0x55, //VSSG_ODD
+ 0x23,2,0x18,0x55, //VSSA_ODD
+ 0x23,2,0x19,0x50, //STV2_ODD
+ 0x23,2,0x1A,0x77,//VDD2_ODD
+ 0x23,2,0x1B,0x57,//VDD1_ODD
+ 0x23,2,0x1C,0x1F,
+ 0x23,2,0x1D,0x4E, //CK11
+ 0x23,2,0x1E,0x4C, //CK9
+ 0x23,2,0x1F,0x1F,
+ 0x23,2,0x20,0x4A, //CK7
+ 0x23,2,0x21,0x48, //CK5
+ 0x23,2,0x22,0x1F,
+ 0x23,2,0x23,0x46, //CK3
+ 0x23,2,0x24,0x44, //CK1
+ 0x23,2,0x25,0x40,//STV1_ODD
+ 0x23,2,0x26,0x1F,
+ 0x23,2,0x27,0x1F,
+ 0x23,2,0x28,0x1F,
+ 0x23,2,0x29,0x1F,
+ 0x23,2,0x2A,0x1F,
+ 0x23,2,0x2B,0x55, //VGG
+ 0x23,2,0x2C,0x12,//GIP_L_GS Pin mapping
+ 0x23,2,0x2D,0x15,
+ 0x23,2,0x2E,0x15,
+ 0x23,2,0x2F,0x00,
+ 0x23,2,0x30,0x37,
+ 0x23,2,0x31,0x17,
+ 0x23,2,0x32,0x1F,
+ 0x23,2,0x33,0x08,
+ 0x23,2,0x34,0x0A,
+ 0x23,2,0x35,0x1F,
+ 0x23,2,0x36,0x0C,
+ 0x23,2,0x37,0x0E,
+ 0x23,2,0x38,0x1F,
+ 0x23,2,0x39,0x04,
+ 0x23,2,0x3A,0x06,
+ 0x23,2,0x3B,0x10,
+ 0x23,2,0x3C,0x1F,
+ 0x23,2,0x3D,0x1F,
+ 0x23,2,0x3E,0x1F,
+ 0x23,2,0x3F,0x15,
+ 0x23,2,0x40,0x1F,
+ 0x23,2,0x41,0x1F,
+ 0x23,2,0x42,0x13,//GIP_R_GS Pin mapping
+ 0x23,2,0x43,0x15,
+ 0x23,2,0x44,0x15,
+ 0x23,2,0x45,0x01,
+ 0x23,2,0x46,0x37,
+ 0x23,2,0x47,0x17,
+ 0x23,2,0x48,0x1F,
+ 0x23,2,0x49,0x09,
+ 0x23,2,0x4A,0x0B,
+ 0x23,2,0x4B,0x1F,
+ 0x23,2,0x4C,0x0D,
+ 0x23,2,0x4D,0x0F,
+ 0x23,2,0x4E,0x1F,
+ 0x23,2,0x4F,0x05,
+ 0x23,2,0x50,0x07,
+ 0x23,2,0x51,0x11,
+ 0x23,2,0x52,0x1F,
+ 0x23,2,0x53,0x1F,
+ 0x23,2,0x54,0x1F,
+ 0x23,2,0x55,0x1F,
+ 0x23,2,0x56,0x1F,
+ 0x23,2,0x57,0x15,
+ 0x23,2,0x58,0x40,//GIP Timing
+ 0x23,2,0x59,0x00,
+ 0x23,2,0x5A,0x00,
+ 0x23,2,0x5B,0x10,
+ 0x23,2,0x5C,0x14,
+ 0x23,2,0x5D,0x40,
+ 0x23,2,0x5E,0x01,
+ 0x23,2,0x5F,0x02,
+ 0x23,2,0x60,0x40,
+ 0x23,2,0x61,0x03,
+ 0x23,2,0x62,0x04,
+ 0x23,2,0x63,0x7A,
+ 0x23,2,0x64,0x7A,
+ 0x23,2,0x65,0x74,
+ 0x23,2,0x66,0x16,
+ 0x23,2,0x67,0xB4,
+ 0x23,2,0x68,0x16,
+ 0x23,2,0x69,0x7A,
+ 0x23,2,0x6A,0x7A,
+ 0x23,2,0x6B,0x0C,
+ 0x23,2,0x6C,0x00,
+ 0x23,2,0x6D,0x04,
+ 0x23,2,0x6E,0x04,
+ 0x23,2,0x6F,0x88,
+ 0x23,2,0x70,0x00,
+ 0x23,2,0x71,0x00,
+ 0x23,2,0x72,0x06,
+ 0x23,2,0x73,0x7B,
+ 0x23,2,0x74,0x00,
+ 0x23,2,0x75,0xBC,
+ 0x23,2,0x76,0x00,
+ 0x23,2,0x77,0x04,
+ 0x23,2,0x78,0x2C,
+ 0x23,2,0x79,0x00,
+ 0x23,2,0x7A,0x00,
+ 0x23,2,0x7B,0x00,
+ 0x23,2,0x7C,0x00,
+ 0x23,2,0x7D,0x03,
+ 0x23,2,0x7E,0x7B,
+ 0x23,2,0xE0,0x04,//Page4
+ 0x23,2,0x09,0x11,//Set RGBCYC2
+ 0x23,2,0x0E,0x48,
+ 0x23,2,0x2B,0x2B,//ESD Protect
+ 0x23,2,0x2E,0x44,
+ 0x23,2,0xE0,0x00,//Page0
+ 0x23,2,0xE6,0x02,//Watch dog
+ 0x23,2,0xE7,0x0C,
+ 0x05,1,0x11,//sleep out
+ 0xfd, 1,120,
+ 0x05,1,0x29,//display on
+ 0x05,1,0x35,
+ 0xfd, 1, 20, /* delay(ms) */
+ 0xFF, 0, /* ending flag */
+};
+
+static unsigned char ext_init_off_table_P070ACB_FT[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0x05, 1, 0x28, /* display off */
+ 0xfd, 1, 10, /* delay 10ms */
+ 0x05, 1, 0x10, /* sleep in */
+ 0xfd, 1, 150, /* delay 150ms */
+ 0xFF, 0, /* ending flag */
+};
+
+#endif
+
diff --git a/board/amlogic/gxb_p200_v1/Kconfig b/board/amlogic/gxb_p200_v1/Kconfig
new file mode 100644
index 0000000..832fd04
--- /dev/null
+++ b/board/amlogic/gxb_p200_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxb_p200_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxb"
+
+config SYS_CONFIG_NAME
+ default "gxb_p200_v1"
+
+endif
diff --git a/board/amlogic/gxb_p200_v1/Makefile b/board/amlogic/gxb_p200_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxb_p200_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxb_p200_v1/aml-user-key.sig b/board/amlogic/gxb_p200_v1/aml-user-key.sig
new file mode 100755
index 0000000..6b51b19
--- /dev/null
+++ b/board/amlogic/gxb_p200_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxb_p200_v1/eth_setup.c b/board/amlogic/gxb_p200_v1/eth_setup.c
new file mode 100644
index 0000000..33b5db1
--- /dev/null
+++ b/board/amlogic/gxb_p200_v1/eth_setup.c
@@ -0,0 +1,50 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxb_p200_v1/firmware/board_init.c b/board/amlogic/gxb_p200_v1/firmware/board_init.c
new file mode 100644
index 0000000..46838d8
--- /dev/null
+++ b/board/amlogic/gxb_p200_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxb_p200_v1/firmware/power.c b/board/amlogic/gxb_p200_v1/firmware/power.c
new file mode 100644
index 0000000..f3cc7ae
--- /dev/null
+++ b/board/amlogic/gxb_p200_v1/firmware/power.c
@@ -0,0 +1,183 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 22);
+ reg |= (1 << 21); // enable PWM_B
+ P_PIN_MUX_REG3 = reg;
+ break;
+
+ case pwm_d:
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 23);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg |= (1 << 20); // enable PWM_D
+ P_PIN_MUX_REG3 = reg;
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_d);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxb_p200_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxb_p200_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..191c865
--- /dev/null
+++ b/board/amlogic/gxb_p200_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,157 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860),
+ DVFS( 250000000, 860),
+ DVFS( 500000000, 860),
+ DVFS( 667000000, 900),
+ DVFS(1000000000, 940),
+ DVFS(1200000000, 980),
+ DVFS(1296000000, 1000),
+ DVFS(1416000000, 1020),
+ DVFS(1536000000, 1050),
+ DVFS(1752000000, 1050),
+ DVFS(2016000000, 1050)
+};
+
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 22);
+ reg |= (1 << 21); // enable PWM_B
+ P_PIN_MUX_REG3 = reg;
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_B;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_B = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+
diff --git a/board/amlogic/gxb_p200_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxb_p200_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..c5fbeb7
--- /dev/null
+++ b/board/amlogic/gxb_p200_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,312 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#include <gpio-gxbb.h>
+
+extern int pwm_voltage_table[31][2];
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ uart_puts("set vddee to 0x");
+ uart_put_hex(voltage, 16);
+ uart_puts("mv\n");
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<18, 1<<18);
+}
+static void power_on_3v3(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<18, 0);
+}
+
+/*p200/201 GPIOAO_4 powr on :1, power_off :0*/
+static void power_off_vcck(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<20, 0);
+}
+static void power_on_vcck(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<20, 1<<20);
+}
+
+static void power_off_at_clk81(void)
+{
+ power_off_3v3();
+ power_off_vcck();
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_SLEEP_VOLTAGE); // reduce power
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_INIT_VOLTAGE);
+ power_on_vcck();
+ power_on_3v3();
+}
+
+static void power_off_at_24M(void)
+{
+ //LED gpioao_13
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<29, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<29, 1<<29);
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC);
+#ifdef CONFIG_BT_WAKEUP
+ val |= BT_WAKEUP_SRC;
+#endif
+
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= WIFI_WAKEUP_SRC;
+#endif
+
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_3;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+ /* BT Wakeup: IN: GPIOX[21], OUT: GPIOX[20]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP;
+ gpio->gpio_in_idx = GPIOX_21;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = GPIOX_20;
+ gpio->gpio_out_ao = 0;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+#ifdef CONFIG_WIFI_WAKEUP
+ if (suspend_from != SYS_POWEROFF) {
+ /*WIFI Wakeup: IN: GPIOX[7], OUT: GPIOX[6]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = WIFI_WAKEUP;
+ gpio->gpio_in_idx = GPIOX_7;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = GPIOX_6;
+ gpio->gpio_out_ao = 0;
+ gpio->irq = IRQ_GPIO1_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+ }
+#endif
+}
+
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned *irq = (unsigned *)SECURE_TASK_SHARE_IRQ;
+ unsigned int ret;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+ switch (*irq) {
+#ifdef CONFIG_CEC_WAKEUP
+ case IRQ_AO_CEC_NUM:
+ if (suspend_from == SYS_POWEROFF)
+ break;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ break;
+#endif
+ case IRQ_TIMERA_NUM:
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ break;
+
+ case IRQ_AO_IR_DEC_NUM:
+ ret = remote_detect_key();
+ if (ret == 1)
+ exit_reason = REMOTE_WAKEUP;
+ if (ret == 2)
+ exit_reason = REMOTE_CUS_WAKEUP;
+ break;
+
+ case IRQ_AO_GPIO0_NUM:
+ if ((readl(AO_GPIO_I) & (1<<3)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ break;
+
+#ifdef CONFIG_BT_WAKEUP
+ case IRQ_GPIO0_NUM:
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ &(0x01 << 20)) &&
+ (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 20)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 21)))
+ exit_reason = BT_WAKEUP;
+ break;
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ case IRQ_GPIO1_NUM:
+ if (suspend_from) {
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ & (0x01 << 6)) &&
+ (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 6)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 7)))
+ exit_reason = WIFI_WAKEUP;
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+ *irq = 0xffffffff;
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/gxb_p200_v1/firmware/timing.c b/board/amlogic/gxb_p200_v1/firmware/timing.c
new file mode 100644
index 0000000..fac90c9
--- /dev/null
+++ b/board/amlogic/gxb_p200_v1/firmware/timing.c
@@ -0,0 +1,511 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+#define CFG_DDR_DRV DDR3_DRV_40OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#endif
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_14,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (14),
+ .cfg_ddr_rcd = (14),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (14),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (10),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* lpddr2 */
+ {
+ .identifier = CONFIG_LPDDR2_TIMMING_DDR1066,
+ .cfg_ddr_rtp = 4,//(4),0
+ .cfg_ddr_wtr = (4),
+ .cfg_ddr_rp = (12),
+ .cfg_ddr_rcd = (10),
+ .cfg_ddr_ras = (23),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (36),
+ .cfg_ddr_mrd = (5),
+ .cfg_ddr_mod = (0),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (70),
+ .cfg_ddr_wlmrd = (0),
+ .cfg_ddr_wlo = (0),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (4),
+ .cfg_ddr_cke = (3),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (39),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (8),
+ .cfg_ddr_wr = (8),
+ .cfg_ddr_cwl = (4),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (76),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (0),
+ .cfg_ddr_cksrx = (2),
+ .cfg_ddr_zqcs = (48),
+ .cfg_ddr_zqcl = (192),
+ .cfg_ddr_xpdll = (0),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_rpab = (12),
+ .cfg_ddr_rppb = (10),
+ .cfg_ddr_tdqsck = (1),
+ .cfg_ddr_tdqsckmax = (2),
+ .cfg_ddr_tckesr = (8),
+ .cfg_ddr_tdpd = (500),
+ .cfg_ddr_taond_aofd = 2,
+ },
+ /* lpddr3 */
+ {
+ .identifier = CONFIG_LPDDR3_TIMMING_DDR1600,
+ .cfg_ddr_rtp =6,// (6),0
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (0),
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (128),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (39),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = 2,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 2,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (72),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (0),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_rpab = (17),
+ .cfg_ddr_rppb = (15),
+ .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ .cfg_ddr_tdqsckmax = (5),
+ .cfg_ddr_tckesr = (12),
+ .cfg_ddr_tdpd = (500),
+ .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+ .ddr_size_detect = CONFIG_DDR_SIZE_AUTO_DETECT,
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00210000,
+ .t_pub_mr = {0},
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x0380c6a0, //PUB PGCR1
+ //.t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ .t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aafe60, //PUB PGCR3
+ .t_pub_dxccr = 0x00181884, //PUB DXCCR
+ .t_pub_dtcr = 0x43003087, //PUB DTCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ .t_pub_dsgcr = 0x020645a,
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x69, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x69, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x69, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x69, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F21, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = (1<<31)|(0x20<<16)|(0x0<<0)//[B31]hw_exit_idle_en
+ |( 0<<8), //[B10,B9,B8] tfaw_cfg_offset:
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ //.t_pctl0_ppcfg = (0xF0 << 1),
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 1,
+ .t_pctl0_dfitphywrlta = 2,
+ .t_pctl0_dfitrddataen = 3,
+ .t_pctl0_dfitphyrdlat = 16,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype1 = 0x200,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (3 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+ .t_pub_acbdlr0 = 0x10, //2015.09.21 add for CK0 delay fine tune
+
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ /* v3 added, lpddr3 support */
+ .t_pub_mr11 = CFG_DDR_ODT,
+ .t_lpddr3_ca0 = CONFIG_LPDDR3_CA_TRAINING_CA0,
+ .t_lpddr3_ca1 = CONFIG_LPDDR3_CA_TRAINING_CA1,
+ .t_lpddr3_remap = CONFIG_LPDDR_REMAP_SET,
+ .t_lpddr3_wl = CONFIG_LPDDR3_WRITE_LEVELING,
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+};
diff --git a/board/amlogic/gxb_p200_v1/gxb_p200_v1.c b/board/amlogic/gxb_p200_v1/gxb_p200_v1.c
new file mode 100644
index 0000000..c5c94c1
--- /dev/null
+++ b/board/amlogic/gxb_p200_v1/gxb_p200_v1.c
@@ -0,0 +1,509 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/io.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ //setup ethernet clk need calibrate to configre
+ setbits_le32(P_PERIPHS_PIN_MUX_6, 0x3fff);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rgmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+ /* hardware reset ethernet phy : gpioz14 connect phyreset pin*/
+ clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 14);
+ clrbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+ udelay(10000);
+ setbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RGMII);
+
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ ret=readl(P_PREG_PAD_GPIO5_I)&(1<<29)?0:1;
+ printf("ret = %d .",ret);
+ if ((readl(P_PERIPHS_PIN_MUX_8)&(3<<9))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I)&(1<<24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_B |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIODV_26 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIODV_27 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_B & I2C_SCK_B
+ clrbits_le32(P_PERIPHS_PIN_MUX_0, ((1<<9)|(1<<10)));
+ clrbits_le32(P_PERIPHS_PIN_MUX_2, ((1<<26)|(1<<27)));
+ clrbits_le32(P_PERIPHS_PIN_MUX_5, ((1<<8)|(1<<9)|(1<<10)));
+ //enable I2C MASTER B pins
+ setbits_le32(P_PERIPHS_PIN_MUX_7,
+ (MESON_I2C_MASTER_B_GPIODV_26_BIT | MESON_I2C_MASTER_B_GPIODV_27_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_B,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_b_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_B_GPIODV_27_REG,
+ .scl_bit = MESON_I2C_MASTER_B_GPIODV_27_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_B_GPIODV_26_REG,
+ .sda_bit = MESON_I2C_MASTER_B_GPIODV_26_BIT,
+}
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_DWC_OTG_HCD
+#include <asm/arch/usb.h>
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ if (is_power_on) {
+ setbits_le32(PREG_PAD_GPIO0_EN_N, 1<<24);
+ setbits_le32(PREG_PAD_GPIO0_O, 1<<24);
+ } else {
+ }
+}
+
+static int usb_charging_detect_call_back(char bc_mode)
+{
+ switch (bc_mode) {
+ case BC_MODE_DCP:
+ case BC_MODE_CDP:
+ //Pull up chargging current > 500mA
+ break;
+
+ case BC_MODE_UNKNOWN:
+ case BC_MODE_SDP:
+ default:
+ //Limit chargging current <= 500mA
+ //Or detet dec-charger
+ break;
+ }
+ return 0;
+}
+//note: try with some M3 pll but only following can work
+//USB_PHY_CLOCK_SEL_M3_XTAL @ 1 (24MHz)
+//USB_PHY_CLOCK_SEL_M3_XTAL_DIV2 @ 0 (12MHz)
+//USB_PHY_CLOCK_SEL_M3_DDR_PLL @ 27(336MHz); @Rev2663 M3 SKT board DDR is 336MHz
+// 43 (528MHz); M3 SKT board DDR not stable for 528MHz
+
+struct amlogic_usb_config g_usb_config_gx_skt_a={
+ USB_PHY_CLK_SEL_XTAL,
+ 1, //PLL divider: (clock/12 -1)
+ CONFIG_M8_USBPORT_BASE_A,
+ USB_ID_MODE_SW_HOST,
+ gpio_set_vbus_power, //set_vbus_power
+ NULL,
+};
+struct amlogic_usb_config g_usb_config_gx_skt_b={
+ USB_PHY_CLK_SEL_XTAL,
+ 1, //PLL divider: (clock/12 -1)
+ CONFIG_M8_USBPORT_BASE_B,
+ USB_ID_MODE_SW_HOST,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ NULL,
+};
+struct amlogic_usb_config g_usb_config_gx_skt_h={
+ USB_PHY_CLK_SEL_XTAL,
+ 1, //PLL divider: (clock/12 -1)
+ CONFIG_M8_USBPORT_BASE_A,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ usb_charging_detect_call_back,
+};
+#endif /*CONFIG_USB_DWC_OTG_HCD*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+}
+#endif
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<13));
+ //set output 1
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<29));
+ /*Power on GPIOAO_2 for VCC_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+ #ifdef CONFIG_USB_DWC_OTG_HCD
+ board_usb_init(&g_usb_config_gx_skt_a,BOARD_USB_MODE_HOST);
+ board_usb_init(&g_usb_config_gx_skt_b,BOARD_USB_MODE_HOST);
+ board_usb_init(&g_usb_config_gx_skt_h,BOARD_USB_MODE_CHARGER);
+#endif /*CONFIG_USB_DWC_OTG_HCD*/
+ canvas_init();
+
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int ddr_size=0;
+ char loc_name[64] = {0};
+ int i;
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+ switch (ddr_size) {
+ case 0x80000000:
+ strcpy(loc_name, "gxb_p200_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "gxb_p200_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "gxb_p200_512m\0");
+ break;
+ default:
+ //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "gxb_p200_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
+
diff --git a/board/amlogic/gxb_p201_v1/Kconfig b/board/amlogic/gxb_p201_v1/Kconfig
new file mode 100644
index 0000000..450f350
--- /dev/null
+++ b/board/amlogic/gxb_p201_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxb_p201_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxb"
+
+config SYS_CONFIG_NAME
+ default "gxb_p201_v1"
+
+endif
diff --git a/board/amlogic/gxb_p201_v1/Makefile b/board/amlogic/gxb_p201_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxb_p201_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxb_p201_v1/aml-user-key.sig b/board/amlogic/gxb_p201_v1/aml-user-key.sig
new file mode 100755
index 0000000..6b51b19
--- /dev/null
+++ b/board/amlogic/gxb_p201_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxb_p201_v1/eth_setup.c b/board/amlogic/gxb_p201_v1/eth_setup.c
new file mode 100644
index 0000000..33b5db1
--- /dev/null
+++ b/board/amlogic/gxb_p201_v1/eth_setup.c
@@ -0,0 +1,50 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxb_p201_v1/firmware/board_init.c b/board/amlogic/gxb_p201_v1/firmware/board_init.c
new file mode 100644
index 0000000..22c36d1
--- /dev/null
+++ b/board/amlogic/gxb_p201_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxb_p201_v1/firmware/power.c b/board/amlogic/gxb_p201_v1/firmware/power.c
new file mode 100644
index 0000000..4923273
--- /dev/null
+++ b/board/amlogic/gxb_p201_v1/firmware/power.c
@@ -0,0 +1,183 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 22);
+ reg |= (1 << 21); // enable PWM_B
+ P_PIN_MUX_REG3 = reg;
+ break;
+
+ case pwm_d:
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 23);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg |= (1 << 20); // enable PWM_D
+ P_PIN_MUX_REG3 = reg;
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_d);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxb_p201_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxb_p201_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..191c865
--- /dev/null
+++ b/board/amlogic/gxb_p201_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,157 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860),
+ DVFS( 250000000, 860),
+ DVFS( 500000000, 860),
+ DVFS( 667000000, 900),
+ DVFS(1000000000, 940),
+ DVFS(1200000000, 980),
+ DVFS(1296000000, 1000),
+ DVFS(1416000000, 1020),
+ DVFS(1536000000, 1050),
+ DVFS(1752000000, 1050),
+ DVFS(2016000000, 1050)
+};
+
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 22);
+ reg |= (1 << 21); // enable PWM_B
+ P_PIN_MUX_REG3 = reg;
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_B;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_B = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+
diff --git a/board/amlogic/gxb_p201_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxb_p201_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..2cf730c
--- /dev/null
+++ b/board/amlogic/gxb_p201_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,250 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+
+extern int pwm_voltage_table[31][2];
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ uart_puts("set vddee to 0x");
+ uart_put_hex(voltage, 16);
+ uart_puts("mv\n");
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<18, 1<<18);
+}
+static void power_on_3v3(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<18, 0);
+}
+
+/*p200/201 GPIOAO_4 powr on :1, power_off :0*/
+static void power_off_vcck(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<20, 0);
+}
+static void power_on_vcck(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<20, 1<<20);
+}
+
+static void power_off_at_clk81(void)
+{
+ power_off_3v3();
+ power_off_vcck();
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_SLEEP_VOLTAGE); // reduce power
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_INIT_VOLTAGE);
+ power_on_vcck();
+ power_on_3v3();
+}
+
+static void power_off_at_24M(void)
+{
+ //LED gpioao_13
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<29, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<29, 1<<29);
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_3;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+
+ p->gpio_info_count = ++i;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned *irq = (unsigned *)SECURE_TASK_SHARE_IRQ;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+ switch (*irq) {
+#ifdef CONFIG_CEC_WAKEUP
+ case IRQ_AO_CEC_NUM:
+ if (suspend_from == SYS_POWEROFF)
+ break;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ break;
+#endif
+ case IRQ_TIMERA_NUM:
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ break;
+
+ case IRQ_AO_IR_DEC_NUM:
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ break;
+
+ case IRQ_AO_GPIO0_NUM:
+ if ((readl(AO_GPIO_I) & (1<<3)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ break;
+
+ default:
+ break;
+ }
+ *irq = 0xffffffff;
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
+
diff --git a/board/amlogic/gxb_p201_v1/firmware/timing.c b/board/amlogic/gxb_p201_v1/firmware/timing.c
new file mode 100644
index 0000000..3f8af13
--- /dev/null
+++ b/board/amlogic/gxb_p201_v1/firmware/timing.c
@@ -0,0 +1,510 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+#define CFG_DDR_DRV DDR3_DRV_40OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#endif
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_14,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (14),
+ .cfg_ddr_rcd = (14),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (14),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (10),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* lpddr2 */
+ {
+ .identifier = CONFIG_LPDDR2_TIMMING_DDR1066,
+ .cfg_ddr_rtp = 4,//(4),0
+ .cfg_ddr_wtr = (4),
+ .cfg_ddr_rp = (12),
+ .cfg_ddr_rcd = (10),
+ .cfg_ddr_ras = (23),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (36),
+ .cfg_ddr_mrd = (5),
+ .cfg_ddr_mod = (0),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (70),
+ .cfg_ddr_wlmrd = (0),
+ .cfg_ddr_wlo = (0),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (4),
+ .cfg_ddr_cke = (3),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (39),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (8),
+ .cfg_ddr_wr = (8),
+ .cfg_ddr_cwl = (4),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (76),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (0),
+ .cfg_ddr_cksrx = (2),
+ .cfg_ddr_zqcs = (48),
+ .cfg_ddr_zqcl = (192),
+ .cfg_ddr_xpdll = (0),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_rpab = (12),
+ .cfg_ddr_rppb = (10),
+ .cfg_ddr_tdqsck = (1),
+ .cfg_ddr_tdqsckmax = (2),
+ .cfg_ddr_tckesr = (8),
+ .cfg_ddr_tdpd = (500),
+ .cfg_ddr_taond_aofd = 2,
+ },
+ /* lpddr3 */
+ {
+ .identifier = CONFIG_LPDDR3_TIMMING_DDR1600,
+ .cfg_ddr_rtp =6,// (6),0
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (0),
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (128),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (39),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = 2,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 2,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (72),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (0),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_rpab = (17),
+ .cfg_ddr_rppb = (15),
+ .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ .cfg_ddr_tdqsckmax = (5),
+ .cfg_ddr_tckesr = (12),
+ .cfg_ddr_tdpd = (500),
+ .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+ .ddr_size_detect = CONFIG_DDR_SIZE_AUTO_DETECT,
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00210000,
+ .t_pub_mr = {0},
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x0380c6a0, //PUB PGCR1
+ //.t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ .t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aafe60, //PUB PGCR3
+ .t_pub_dxccr = 0x00181884, //PUB DXCCR
+ .t_pub_dtcr = 0x43003087, //PUB DTCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+ .t_pub_dcr = 0X8B, //PUB DCR
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ .t_pub_dsgcr = 0x020645a, //0x020641a, 2015.09.21, shift DQS gate 1/2 earlier and 1/2 later
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x1d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x19, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x19, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x19, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F21, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = (1<<31)|(0x20<<16)|(0x0<<0)//[B31]hw_exit_idle_en
+ |( 0<<8), //[B10,B9,B8] tfaw_cfg_offset:
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ //.t_pctl0_ppcfg = (0xF0 << 1),
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 1,
+ .t_pctl0_dfitphywrlta = 2,
+ .t_pctl0_dfitrddataen = 3,
+ .t_pctl0_dfitphyrdlat = 16,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype1 = 0x200,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (3 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0x10, //2015.09.21 CK0 delay 16 cycles
+
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ /* v3 added, lpddr3 support */
+ .t_pub_mr11 = CFG_DDR_ODT,
+ .t_lpddr3_ca0 = CONFIG_LPDDR3_CA_TRAINING_CA0,
+ .t_lpddr3_ca1 = CONFIG_LPDDR3_CA_TRAINING_CA1,
+ .t_lpddr3_remap = CONFIG_LPDDR_REMAP_SET,
+ .t_lpddr3_wl = CONFIG_LPDDR3_WRITE_LEVELING,
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+};
diff --git a/board/amlogic/gxb_p201_v1/gxb_p201_v1.c b/board/amlogic/gxb_p201_v1/gxb_p201_v1.c
new file mode 100644
index 0000000..2ec961a
--- /dev/null
+++ b/board/amlogic/gxb_p201_v1/gxb_p201_v1.c
@@ -0,0 +1,492 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ //setup ethernet clk need calibrate to configre
+ setbits_le32(P_PERIPHS_PIN_MUX_6, 0x3c73);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+ /* hardware reset ethernet phy : gpioz14 connect phyreset pin*/
+ clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 14);
+ clrbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+ udelay(10000);
+ setbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ ret=readl(P_PREG_PAD_GPIO5_I)&(1<<29)?0:1;
+ printf("ret = %d .",ret);
+ if ((readl(P_PERIPHS_PIN_MUX_8)&(3<<9))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I)&(1<<24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_DWC_OTG_HCD
+#include <asm/arch/usb.h>
+/*
+static void gpio_set_vbus_power(char is_power_on)
+{
+ if (is_power_on) {
+ setbits_le32(PREG_PAD_GPIO0_EN_N, 1<<24);
+ setbits_le32(PREG_PAD_GPIO0_O, 1<<24);
+ } else {
+ }
+}
+*/
+static int usb_charging_detect_call_back(char bc_mode)
+{
+ switch (bc_mode) {
+ case BC_MODE_DCP:
+ case BC_MODE_CDP:
+ //Pull up chargging current > 500mA
+ break;
+
+ case BC_MODE_UNKNOWN:
+ case BC_MODE_SDP:
+ default:
+ //Limit chargging current <= 500mA
+ //Or detet dec-charger
+ break;
+ }
+ return 0;
+}
+//note: try with some M3 pll but only following can work
+//USB_PHY_CLOCK_SEL_M3_XTAL @ 1 (24MHz)
+//USB_PHY_CLOCK_SEL_M3_XTAL_DIV2 @ 0 (12MHz)
+//USB_PHY_CLOCK_SEL_M3_DDR_PLL @ 27(336MHz); @Rev2663 M3 SKT board DDR is 336MHz
+// 43 (528MHz); M3 SKT board DDR not stable for 528MHz
+
+struct amlogic_usb_config g_usb_config_gx_skt_a={
+ USB_PHY_CLK_SEL_XTAL,
+ 1, //PLL divider: (clock/12 -1)
+ CONFIG_M8_USBPORT_BASE_A,
+ USB_ID_MODE_SW_HOST,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ NULL,
+};
+struct amlogic_usb_config g_usb_config_gx_skt_b={
+ USB_PHY_CLK_SEL_XTAL,
+ 1, //PLL divider: (clock/12 -1)
+ CONFIG_M8_USBPORT_BASE_B,
+ USB_ID_MODE_SW_HOST,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ NULL,
+};
+struct amlogic_usb_config g_usb_config_gx_skt_h={
+ USB_PHY_CLK_SEL_XTAL,
+ 1, //PLL divider: (clock/12 -1)
+ CONFIG_M8_USBPORT_BASE_A,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ usb_charging_detect_call_back,
+};
+#endif /*CONFIG_USB_DWC_OTG_HCD*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+}
+#endif
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<13));
+ //set output 1
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<29));
+
+
+ /*Power on GPIOAO_2 for VCC_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+ #ifdef CONFIG_USB_DWC_OTG_HCD
+ board_usb_init(&g_usb_config_gx_skt_a,BOARD_USB_MODE_HOST);
+ board_usb_init(&g_usb_config_gx_skt_b,BOARD_USB_MODE_HOST);
+ board_usb_init(&g_usb_config_gx_skt_h,BOARD_USB_MODE_CHARGER);
+ #endif /*CONFIG_USB_DWC_OTG_HCD*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
+
diff --git a/board/amlogic/gxb_skt_v1/Kconfig b/board/amlogic/gxb_skt_v1/Kconfig
new file mode 100644
index 0000000..8544f4d
--- /dev/null
+++ b/board/amlogic/gxb_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxb_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxb"
+
+config SYS_CONFIG_NAME
+ default "gxb_skt_v1"
+
+endif
diff --git a/board/amlogic/gxb_skt_v1/Makefile b/board/amlogic/gxb_skt_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxb_skt_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxb_skt_v1/aml-user-key.sig b/board/amlogic/gxb_skt_v1/aml-user-key.sig
new file mode 100644
index 0000000..6b51b19
--- /dev/null
+++ b/board/amlogic/gxb_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxb_skt_v1/eth_setup.c b/board/amlogic/gxb_skt_v1/eth_setup.c
new file mode 100644
index 0000000..f7aff48
--- /dev/null
+++ b/board/amlogic/gxb_skt_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/gxb_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxb_skt_v1/firmware/board_init.c b/board/amlogic/gxb_skt_v1/firmware/board_init.c
new file mode 100644
index 0000000..107f13e
--- /dev/null
+++ b/board/amlogic/gxb_skt_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxb_skt_v1/firmware/power.c b/board/amlogic/gxb_skt_v1/firmware/power.c
new file mode 100644
index 0000000..f3cc7ae
--- /dev/null
+++ b/board/amlogic/gxb_skt_v1/firmware/power.c
@@ -0,0 +1,183 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 22);
+ reg |= (1 << 21); // enable PWM_B
+ P_PIN_MUX_REG3 = reg;
+ break;
+
+ case pwm_d:
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 23);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg |= (1 << 20); // enable PWM_D
+ P_PIN_MUX_REG3 = reg;
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_d);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxb_skt_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxb_skt_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..191c865
--- /dev/null
+++ b/board/amlogic/gxb_skt_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,157 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860),
+ DVFS( 250000000, 860),
+ DVFS( 500000000, 860),
+ DVFS( 667000000, 900),
+ DVFS(1000000000, 940),
+ DVFS(1200000000, 980),
+ DVFS(1296000000, 1000),
+ DVFS(1416000000, 1020),
+ DVFS(1536000000, 1050),
+ DVFS(1752000000, 1050),
+ DVFS(2016000000, 1050)
+};
+
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 22);
+ reg |= (1 << 21); // enable PWM_B
+ P_PIN_MUX_REG3 = reg;
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_B;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_B = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+
diff --git a/board/amlogic/gxb_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxb_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..a4aeb81
--- /dev/null
+++ b/board/amlogic/gxb_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,304 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#include <gpio-gxbb.h>
+
+extern int pwm_voltage_table[31][2];
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ uart_puts("set vddee to 0x");
+ uart_put_hex(voltage, 16);
+ uart_puts("mv\n");
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<18, 1<<18);
+}
+static void power_on_3v3(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<18, 0);
+}
+
+/*p200/201 GPIOAO_4 powr on :1, power_off :0*/
+static void power_off_vcck(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<20, 0);
+}
+static void power_on_vcck(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<20, 1<<20);
+}
+
+static void power_off_at_clk81(void)
+{
+ power_off_3v3();
+ power_off_vcck();
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_SLEEP_VOLTAGE); // reduce power
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_INIT_VOLTAGE);
+ power_on_vcck();
+ power_on_3v3();
+}
+
+static void power_off_at_24M(void)
+{
+ //LED gpioao_13
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<29, 0);
+}
+static void power_on_at_24M(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<29, 1<<29);
+}
+
+static void power_off_at_32k(void)
+{
+}
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC);
+#ifdef CONFIG_BT_WAKEUP
+ val |= BT_WAKEUP_SRC;
+#endif
+
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= WIFI_WAKEUP_SRC;
+#endif
+
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_3;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+ /* BT Wakeup: IN: GPIOX[21], OUT: GPIOX[20]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP;
+ gpio->gpio_in_idx = GPIOX_21;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = GPIOX_20;
+ gpio->gpio_out_ao = 0;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+#ifdef CONFIG_WIFI_WAKEUP
+ if (suspend_from != SYS_POWEROFF) {
+ /*WIFI Wakeup: IN: GPIOX[7], OUT: GPIOX[6]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = WIFI_WAKEUP;
+ gpio->gpio_in_idx = GPIOX_7;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = GPIOX_6;
+ gpio->gpio_out_ao = 0;
+ gpio->irq = IRQ_GPIO1_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+ }
+#endif
+}
+
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned *irq = (unsigned *)SECURE_TASK_SHARE_IRQ;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+ switch (*irq) {
+#ifdef CONFIG_CEC_WAKEUP
+ case IRQ_AO_CEC_NUM:
+ if (suspend_from == SYS_POWEROFF)
+ break;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ break;
+#endif
+ case IRQ_TIMERA_NUM:
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ break;
+
+ case IRQ_AO_IR_DEC_NUM:
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ break;
+ case IRQ_AO_GPIO0_NUM:
+ if ((readl(AO_GPIO_I) & (1<<3)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ break;
+#ifdef CONFIG_BT_WAKEUP
+ case IRQ_GPIO0_NUM:
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ &(0x01 << 20)) &&
+ (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 20)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 21)))
+ exit_reason = BT_WAKEUP;
+ break;
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ case IRQ_GPIO1_NUM:
+ if (suspend_from) {
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ & (0x01 << 6)) &&
+ (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 6)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 7)))
+ exit_reason = WIFI_WAKEUP;
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+ *irq = 0xffffffff;
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/gxb_skt_v1/firmware/timing.c b/board/amlogic/gxb_skt_v1/firmware/timing.c
new file mode 100644
index 0000000..549324f
--- /dev/null
+++ b/board/amlogic/gxb_skt_v1/firmware/timing.c
@@ -0,0 +1,404 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+#define CFG_DDR3_DRV DDR3_DRV_40OHM
+#define CFG_DDR3_ODT DDR3_ODT_120OHM
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_14,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (14),
+ .cfg_ddr_rcd = (14),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (14),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (10),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+ .ddr_size_detect = CONFIG_DDR_SIZE_AUTO_DETECT,
+ .ddr_drv = CFG_DDR3_DRV,
+ .ddr_odt = CFG_DDR3_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00210000,
+ .t_pub_mr = {0},
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x0380c6a0, //PUB PGCR1
+ //.t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ .t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aafe60, //PUB PGCR3
+ .t_pub_dxccr = 0x00181884, //PUB DXCCR
+ .t_pub_dtcr = 0x43003087, //PUB DTCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+ .t_pub_dcr = 0X8B, //PUB DCR
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ .t_pub_dsgcr = 0x020641a,
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x1d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x19, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x19, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x19, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F21, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = (1<<31)|(0x20<<16)|(0x80<<0)//[B31]hw_exit_idle_en
+ |( 0<<8), //[B10,B9,B8] tfaw_cfg_offset:
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ //.t_pctl0_ppcfg = (0xF0 << 1),
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 1,
+ .t_pctl0_dfitphywrlta = 2,
+ .t_pctl0_dfitrddataen = 3,
+ .t_pctl0_dfitphyrdlat = 16,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype1 = 0x200,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (3 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+ .t_pub_acbdlr0 = 0, //2015.09.21 add for CK0 delay fine tune
+
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+ .wr_adj_per = { /* dqs tuning demo 2016.01.26 */
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+};
diff --git a/board/amlogic/gxb_skt_v1/gxb_skt_v1.c b/board/amlogic/gxb_skt_v1/gxb_skt_v1.c
new file mode 100644
index 0000000..66fa18f
--- /dev/null
+++ b/board/amlogic/gxb_skt_v1/gxb_skt_v1.c
@@ -0,0 +1,464 @@
+
+/*
+ * board/amlogic/gxb_skt_v1/gxb_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <amlogic/spifc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+ eth_board_setup("g9bb");
+ return rc;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ ret=readl(P_PREG_PAD_GPIO5_I)&(1<<29)?0:1;
+ printf("ret = %d .",ret);
+ if ((readl(P_PERIPHS_PIN_MUX_8)&(3<<9))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I)&(1<<24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_DWC_OTG_HCD
+#include <asm/arch/usb.h>
+
+static void gpio_set_vbus_power(char is_power_on)
+{
+ if (is_power_on) {
+ setbits_le32(PREG_PAD_GPIO0_EN_N, 1<<24);
+ setbits_le32(PREG_PAD_GPIO0_O, 1<<24);
+ } else {
+ }
+}
+
+static int usb_charging_detect_call_back(char bc_mode)
+{
+ switch (bc_mode) {
+ case BC_MODE_DCP:
+ case BC_MODE_CDP:
+ //Pull up chargging current > 500mA
+ break;
+
+ case BC_MODE_UNKNOWN:
+ case BC_MODE_SDP:
+ default:
+ //Limit chargging current <= 500mA
+ //Or detet dec-charger
+ break;
+ }
+ return 0;
+}
+//note: try with some M3 pll but only following can work
+//USB_PHY_CLOCK_SEL_M3_XTAL @ 1 (24MHz)
+//USB_PHY_CLOCK_SEL_M3_XTAL_DIV2 @ 0 (12MHz)
+//USB_PHY_CLOCK_SEL_M3_DDR_PLL @ 27(336MHz); @Rev2663 M3 SKT board DDR is 336MHz
+// 43 (528MHz); M3 SKT board DDR not stable for 528MHz
+
+struct amlogic_usb_config g_usb_config_gx_skt_a={
+ USB_PHY_CLK_SEL_XTAL,
+ 1, //PLL divider: (clock/12 -1)
+ CONFIG_M8_USBPORT_BASE_A,
+ USB_ID_MODE_SW_HOST,
+ gpio_set_vbus_power, //set_vbus_power
+ NULL,
+};
+struct amlogic_usb_config g_usb_config_gx_skt_b={
+ USB_PHY_CLK_SEL_XTAL,
+ 1, //PLL divider: (clock/12 -1)
+ CONFIG_M8_USBPORT_BASE_B,
+ USB_ID_MODE_SW_HOST,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ NULL,
+};
+struct amlogic_usb_config g_usb_config_gx_skt_h={
+ USB_PHY_CLK_SEL_XTAL,
+ 1, //PLL divider: (clock/12 -1)
+ CONFIG_M8_USBPORT_BASE_A,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ usb_charging_detect_call_back,
+};
+#endif /*CONFIG_USB_DWC_OTG_HCD*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_11: NOR_D:reg5[1], clr reg4[24]
+ * BOOT_12: NOR_Q:reg5[3], clr reg4[23]
+ * BOOT_13: NOR_C:reg5[2], clr reg4[22]
+ * BOOT_15: NOR_CS:reg5[0],clr reg4[20] + reg4[31]
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {112/*PIN_BOOT_15*/};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_5);
+ val &= ~((1<<3)|(1<<2)|(1<<1)|(1<<0));
+ if (enable) {
+ val |= (1<<3)|(1<<2)|(1<<1);
+ writel(val, P_PERIPHS_PIN_MUX_5);
+ val = readl(P_PERIPHS_PIN_MUX_4);
+ val &= ~((1<<31)|(1<<24)|(1<<23)|(1<<22)|(1<<20));
+ writel(val, P_PERIPHS_PIN_MUX_4);
+ }
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xc1108c80,
+ .mem_map = 0xcc000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_DWC_OTG_HCD
+ //setbits_le32(PREG_PAD_GPIO0_EN_N, 1<<24);
+ //setbits_le32(PREG_PAD_GPIO0_O, 1<<24);
+ board_usb_init(&g_usb_config_gx_skt_a,BOARD_USB_MODE_HOST);
+ board_usb_init(&g_usb_config_gx_skt_b,BOARD_USB_MODE_HOST);
+ board_usb_init(&g_usb_config_gx_skt_h,BOARD_USB_MODE_CHARGER);
+#endif /*CONFIG_USB_DWC_OTG_HCD*/
+ canvas_init();
+
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+ /*add board late init function here*/
+ run_command("setenv fdt_high 0x20000000", 1);
+ run_command("setenv dtb_mem_addr 0x1000000", 1);
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
diff --git a/board/amlogic/gxl_estelle_p0/Kconfig b/board/amlogic/gxl_estelle_p0/Kconfig
new file mode 100644
index 0000000..9c44d5b
--- /dev/null
+++ b/board/amlogic/gxl_estelle_p0/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxl_estelle_p0"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxl_estelle_p0"
+
+endif
diff --git a/board/amlogic/gxl_estelle_p0/Makefile b/board/amlogic/gxl_estelle_p0/Makefile
new file mode 100644
index 0000000..12be299
--- /dev/null
+++ b/board/amlogic/gxl_estelle_p0/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o
diff --git a/board/amlogic/gxl_estelle_p0/aml-user-key.sig b/board/amlogic/gxl_estelle_p0/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/gxl_estelle_p0/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxl_estelle_p0/firmware/board_init.c b/board/amlogic/gxl_estelle_p0/firmware/board_init.c
new file mode 100644
index 0000000..22c36d1
--- /dev/null
+++ b/board/amlogic/gxl_estelle_p0/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxl_estelle_p0/firmware/power.c b/board/amlogic/gxl_estelle_p0/firmware/power.c
new file mode 100644
index 0000000..fce6e3c
--- /dev/null
+++ b/board/amlogic/gxl_estelle_p0/firmware/power.c
@@ -0,0 +1,185 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5);
+ reg |= (1 << 11); // enable PWM_B
+ P_PIN_MUX_REG2 = reg;
+ break;
+
+ case pwm_d:
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_d);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxl_estelle_p0/firmware/scp_task/dvfs_board.c b/board/amlogic/gxl_estelle_p0/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..f15c3e4
--- /dev/null
+++ b/board/amlogic/gxl_estelle_p0/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,171 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+ DVFS(1200000000, 1020+50),
+ DVFS(1512000000, 1110+30),
+};
+
+
+
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_D;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_D = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/gxl_estelle_p0/firmware/scp_task/dvfs_board.h b/board/amlogic/gxl_estelle_p0/firmware/scp_task/dvfs_board.h
new file mode 100644
index 0000000..ceede58
--- /dev/null
+++ b/board/amlogic/gxl_estelle_p0/firmware/scp_task/dvfs_board.h
@@ -0,0 +1,3 @@
+#ifndef __DVFS_BOARD_H__
+extern int pwm_voltage_table[31][2];
+#endif
diff --git a/board/amlogic/gxl_estelle_p0/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxl_estelle_p0/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..6e75686
--- /dev/null
+++ b/board/amlogic/gxl_estelle_p0/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,287 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "dvfs_board.h"
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB \
+ (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD \
+ (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+#define ON 1
+#define OFF 0
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+static struct pwr_op *g_pwr_op;
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage)
+ break;
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table))
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+
+ switch (id) {
+ case pwm_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+/*GPIOH_3*/
+static void hdmi_5v_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* VCC5V ON GPIOH_3 output mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 0);
+ } else {
+ /* VCC5V OFF GPIOH_3 input mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 1 << 23);
+ }
+}
+/*GPIODV_25*/
+static void vcck_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 1 << 25);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ } else {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 0);
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+ hdmi_5v_ctrl(OFF);
+ vcck_ctrl(OFF);
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_SLEEP_VOLTAGE);
+ /* reduce power */
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ vcck_ctrl(ON);
+ hdmi_5v_ctrl(ON);
+}
+
+static void power_off_at_24M(void)
+{
+ /* LED GPIODV_24*/
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ if (g_pwr_op->exit_reason != 4) {
+ /* bluetooth wakeup */
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 1 << 24);
+ }
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_2;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_18;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(10, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned int ret;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1) {
+ cec_node_init();
+ }
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ ret = remote_detect_key();
+ if (ret == 1)
+ exit_reason = REMOTE_WAKEUP;
+ if (ret == 2)
+ exit_reason = REMOTE_CUS_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<2)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 18))
+ && (readl(PREG_PAD_GPIO4_O) & (0x01 << 17))
+ && !(readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 17)))
+ exit_reason = BT_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+ pwr_op->exit_reason = 0;
+ g_pwr_op = pwr_op;
+}
+
diff --git a/board/amlogic/gxl_estelle_p0/firmware/timing.c b/board/amlogic/gxl_estelle_p0/firmware/timing.c
new file mode 100644
index 0000000..a2f4892
--- /dev/null
+++ b/board/amlogic/gxl_estelle_p0/firmware/timing.c
@@ -0,0 +1,694 @@
+
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_120OHM 2
+#define LPDDR3_ODT_240OHM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_40OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_0OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_34OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+//#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+//#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CONFIG_SOC_VREF 1+ (50+((50*48)/(48+480/(6+1)))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF 1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#else
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#endif
+
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (9),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = 9,//12,//(23), //6 7 8 9 10 11 ok ,bit0-3 max is 15 ,why use 15 is bad 2016_11_10 jiaxing ,test should change with ddr frequency ?
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = 6,// (6),0
+ .cfg_ddr_wtr = (6+2),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (12),//12-17
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (168),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (39-2),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = 9,//9,// (4),//rank0 rank1 turn aroud time jiaxing modify should big for 2rank lpddr3
+ .cfg_ddr_cksre = 12,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 12,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (100),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (12),
+ .cfg_ddr_zqcsi = (1000),
+ // .cfg_ddr_rpab = (17),
+ // .cfg_ddr_rppb = (15),
+ // .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ // .cfg_ddr_tdqsckmax = (5),
+ // .cfg_ddr_tckesr = (12),
+ // .cfg_ddr_tdpd = (500),
+ // .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#if (CONFIG_LPDDR_REMAP_SET == LPDDR_DIE_ROW_COL_R14_C9)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#elif (CONFIG_LPDDR_REMAP_SET== LPDDR_DIE_ROW_COL_R13_C10)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#endif /*CONFIG_LPDDR_REMAP_SET*/
+#else
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+#endif /*CONFIG_DDR_TYPE_LPDDR3*/
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+//lpddr3
+ .t_pub_zq0pr = 0x0ca1c, //0x0ca1c, //PUB ZQ0PR //lpddr3
+ .t_pub_zq1pr = 0x1cf3c, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x1cf3c, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+/* 2layer board
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+*/
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+/* 4layer ddr4 */
+ .t_pub_zq0pr = 0x0995d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#else // ddr3 and auto
+/* p212 4layer board ddr3 */
+ .t_pub_zq0pr = 0x5d95d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x5d95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x5d95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#endif
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+///*lpddr3
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune TAKE CARE LPDDR3 ADD/CMD DELAY
+ .t_pub_aclcdlr = 0,
+ .t_pub_acbdlr3 = 0x2020,//0, //CK0 delay fine tune b-3f //lpddr3 tianhe 2016-10-13
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+//2layer board DDR4
+ .t_pub_acbdlr0 = 0, //0x3f,
+ .t_pub_aclcdlr = 0, //0x28,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0, //0x10,// 0x10,//0xa, //cs add 22ohm 08 0ohm 0x10
+#else // ddr3 and auto
+//4layer ddr3
+ .t_pub_acbdlr0 = 0,
+ .t_pub_aclcdlr = 0,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0,//0xa, //cs
+#endif
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ //tianhe lpddr3 20161013
+ .wr_adj_per = {
+ [0] = 90, //aclcdlr
+ [1] = 100,
+ [2] = 120,
+ [3] = 110,
+ [4] = 120,
+ [5] = 105,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 110,
+ [3] = 110,
+ [4] = 110,
+ [5] = 110,},
+#else
+ /* P212 */
+ .wr_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=95,
+ [3]=95,
+ [4]=95,
+ [5]=95,
+ },
+ .rd_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=88,
+ [3]=95,
+ [4]=95,
+ [5]=100,
+ },
+#endif
+
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+ /* pll ssc setting:
+
+ .ddr_pll_ssc = 0x00120000, ppm1000 center SS, boot log show: Set ddr ssc: ppm1000
+ .ddr_pll_ssc = 0x00124000, ppm1000 up SS, boot log show: Set ddr ssc: ppm1000+
+ .ddr_pll_ssc = 0x00128000, ppm1000 down SS, boot log show: Set ddr ssc: ppm1000-
+
+ .ddr_pll_ssc = 0x00140000, ppm2000 center SS, boot log show: Set ddr ssc: ppm2000
+ .ddr_pll_ssc = 0x00144000, ppm2000 up SS, boot log show: Set ddr ssc: ppm2000+
+ .ddr_pll_ssc = 0x00148000, ppm2000 down SS, boot log show: Set ddr ssc: ppm2000-
+
+ .ddr_pll_ssc = 0x00160000, ppm3000 center SS, boot log show: Set ddr ssc: ppm3000
+ .ddr_pll_ssc = 0x00164000, ppm3000 up SS, boot log show: Set ddr ssc: ppm3000+
+ .ddr_pll_ssc = 0x00168000, ppm3000 down SS, boot log show: Set ddr ssc: ppm3000-
+ */
+ .ddr_pll_ssc = 0,
+};
diff --git a/board/amlogic/gxl_estelle_p0/gxl_estelle_p0.c b/board/amlogic/gxl_estelle_p0/gxl_estelle_p0.c
new file mode 100644
index 0000000..19451f0
--- /dev/null
+++ b/board/amlogic/gxl_estelle_p0/gxl_estelle_p0.c
@@ -0,0 +1,644 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+#include <asm/arch/mailbox.h>
+#ifdef DTB_BIND_KERNEL
+#include "storage.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ } else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+ __maybe_unused struct mmc *mmc;
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+#if defined(CONFIG_ENV_IS_NOWHERE) && !defined(CONFIG_AML_MTD)
+ /* try emmc here. */
+ mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ if (!mmc)
+ printf("%s() %d: No MMC found\n", __func__, __LINE__);
+ else if (mmc_init(mmc))
+ printf("%s() %d: MMC init failed\n", __func__, __LINE__);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23);
+ clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23);
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "fts",
+ .offset = 0,
+ .size = 1*SZ_1M,
+ },
+ {
+ .name = "factory",
+ .offset = 0,
+ .size = 8*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 12*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 220*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "cache",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24));
+ //set output 1
+ setbits_le32(PREG_PAD_GPIO0_O, (1 << 24));
+
+ /*increase cpu core voltage to 1.15 V*/
+ //clear pinmux
+ clrbits_le32(P_PERIPHS_PIN_MUX_6, (1<<1)|(1<<7)|(1<<9)|(1<<11));
+ clrbits_le32(P_PERIPHS_PIN_MUX_6, (1<<0)|(1<<6)|(1<<8)|(1<<10));
+ //set output mode
+ clrbits_le32(P_PREG_PAD_GPIO2_EN_N, (1 << 24));
+ clrbits_le32(P_PREG_PAD_GPIO2_EN_N, (1 << 25));
+ //set output 1
+ setbits_le32(P_PREG_PAD_GPIO2_O, 1 << 24);
+ setbits_le32(P_PREG_PAD_GPIO2_O, 1 << 25);
+
+ /*Power on GPIOAO_2 for VCC_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+#define SAMPLE_BIT_MASK 0xfff
+#define NUM 50
+#define BASE_CH7 1843
+#define P_SAR_ADC_REG0 (volatile unsigned int *)0xc1108680
+#define P_SAR_ADC_CHAN_LIST (volatile unsigned int *)0xc1108684
+#define P_SAR_ADC_REG3 (volatile unsigned int *)0xc110868c
+#define P_SAR_ADC_FIFO_RD (volatile unsigned int *)0xc1108698
+#define P_SAR_ADC_DETECT_IDLE_SW (volatile unsigned int *)0xc11086a4
+#define P_SAR_ADC_REG13 (volatile unsigned int *)0xc11086b4
+#if 0
+#define dbgv(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define dbgv(fmt, ...)
+#endif
+void quicksort1(unsigned int a[], int numsize)
+{
+ int i = 0, j = numsize-1;
+ int val = a[0];
+ if (numsize > 1) {
+ while (i < j) {
+ for (; j > i; j--)
+ if (a[j] < val) {
+ a[i] = a[j];
+ break;
+ }
+ for (; i < j; i++)
+ if (a[i] > val) {
+ a[j] = a[i];
+ break;
+ }
+ }
+ a[i] = val;
+ quicksort1(a, i);
+ quicksort1(a+i+1, numsize-1-i);
+}
+}
+int check_vref(void)
+{
+ int i,count;
+ unsigned int value[50];
+ unsigned int value7=0;
+ unsigned int bak, bak_reg3;
+ unsigned int vref_efuse = (readl(SEC_AO_SEC_SD_CFG12)>>19)&(0x1f);
+
+ if (!vref_efuse) {
+ dbgv("This chip has no FT vref, no need to check, PASS\n");
+ return 0;
+ }
+ //run_command("md 0xc1108680 0x10", 0);
+ dbgv("SEC_AO_SEC_SD_CFG12: 0x%x\n",readl(SEC_AO_SEC_SD_CFG12));
+ dbgv("vref_efuse: %d\n",vref_efuse);
+
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ bak = (readl(P_SAR_ADC_REG13)>>8)&0x3f; /*back up SAR_ADC_REG13[13:8]*/
+ writel((readl(P_SAR_ADC_REG13)&(~(0x3f<<8)))|(vref_efuse<<9), P_SAR_ADC_REG13);
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ writel(0x00000007, P_SAR_ADC_CHAN_LIST);/*ch7*/
+ //writel(0xc000c|(0x7<<23)|(0x7<<7), P_SAR_ADC_DETECT_IDLE_SW);/*channel 7*/
+ bak_reg3 = readl(P_SAR_ADC_REG3);
+ writel((readl(P_SAR_ADC_REG3)&(~(0x7<<23)))|(0x2<<23), P_SAR_ADC_REG3);/*AVDD18/2*/
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ //run_command("md 0xc1108680 0x10", 0);
+ for (i=0;i<NUM;i++) {
+ writel((readl(P_SAR_ADC_REG0)&(~(1<<0))), P_SAR_ADC_REG0);
+ writel((readl(P_SAR_ADC_REG0)|(1<<0)), P_SAR_ADC_REG0);
+ writel((readl(P_SAR_ADC_REG0)|(1<<2)), P_SAR_ADC_REG0);/*start sample*/
+ count = 0;
+ do {
+ udelay(20);
+ count++;
+ } while ((readl(P_SAR_ADC_REG0) & (0x7<<28))
+ && (count < 100));/*finish sample?*/
+ if (count == 100) {
+ printf("%s : ch7 wait finish sample timeout!\n",__func__);
+ return -1;
+ }
+ value[i] = readl(P_SAR_ADC_FIFO_RD); /*read saradc*/
+ if (((value[i]>>12) & 0x7) == 0x7)
+ value[i] = value[i]&SAMPLE_BIT_MASK;
+ else {
+ printf("%s : not ch7! sample err!\n",__func__);
+ return -1;
+ }
+ }
+ quicksort1(value, NUM);
+ for (i = 0; i < NUM; i++)
+ dbgv("%d ", value[i]);
+ dbgv("\n");
+ for (i = 2; i < NUM-2; i++)
+ value7 += value[i];
+ value7 = value7/(NUM-4);
+ dbgv("the average ch7 adc=%d\n", value7);
+ dbgv("vref_efuse: %d\n",vref_efuse);
+ if ((value7 < (BASE_CH7*94/100)) || (value7 > (BASE_CH7*106/100))) { //1843
+ printf("the average ch7 : %d out of range: %d ~ %d\n",
+ value7, (BASE_CH7*94/100), (BASE_CH7*106/100));
+ printf("replace FT vref...\n");
+ thermal_calibration(4, bak>>1); /*[13:9]*/
+ }
+ /*write back SAR_ADC_REG13[13:8]*/
+ writel(((readl(P_SAR_ADC_REG13))&(~(0x3f<<8)))|
+ ((bak & 0x3f)<<8),
+ P_SAR_ADC_REG13);
+ writel(bak_reg3, P_SAR_ADC_REG3);
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ dbgv("SEC_AO_SEC_SD_CFG12: 0x%x\n",readl(SEC_AO_SEC_SD_CFG12));
+ //run_command("md 0xc1108680 0x10", 0);
+ return 0;
+}
+
+int board_late_init(void){
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ ret = check_vref();
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) {
+ setenv("maxcpus","4");
+ }
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int ddr_size=0;
+ char loc_name[64] = {0};
+ int i;
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+ switch (ddr_size) {
+ case 0x80000000:
+ strcpy(loc_name, "gxl_p212_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "gxl_p212_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "gxl_p212_512m\0");
+ break;
+ default:
+ //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "gxl_p212_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/gxl_estelle_p0/lcd.c b/board/amlogic/gxl_estelle_p0/lcd.c
new file mode 100644
index 0000000..24dae0f
--- /dev/null
+++ b/board/amlogic/gxl_estelle_p0/lcd.c
@@ -0,0 +1,236 @@
+/*
+ * AMLOGIC TV LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {
+ "lcd_0",LCD_TTL,6,
+ /* basic timing */
+ 1280,720,1650,750,40,220,1,5,20,1,
+ /* clk_attr */
+ 0,0,1,74250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* ttl_attr */
+ 0,1,1,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ 0xff,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+};
+
+//**** Special parameters just for ttl ***//
+static struct ttl_config_s lcd_ttl_config = {
+ .clk_pol = 0,
+ .sync_valid = (1 << 1) | (1 << 0), /* [1]DE, [0]hvsync */
+ .swap_ctrl = (0 << 1) | (0 << 0), /* [1]rb swap, [0]bit swap */
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .ttl_config = &lcd_ttl_config,
+ .lvds_config = &lcd_lvds_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{3, 0x000002a0}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{1, 0xfa030000}, {2, 0xf9fe0409}, {3, 0x00000001}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+#define LCD_EXTERN_NAME "ext_default"
+#define LCD_EXTERN_CMD_SIZE 9
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_config_s ext_config_dtf = {
+ .lcd_ext_key_valid = 0,
+ .index = LCD_EXTERN_INDEX_INVALID,
+ .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_D, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = LCD_EXTERN_CMD_SIZE,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{2, 0x00000800}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{1, 0x00000400}, {2, 0x00000020}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_config_dtf.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_config_dtf.gpio_name[j], "invalid");
+
+ strcpy(ext_config_dtf.name, LCD_EXTERN_NAME);
+#endif
+}
diff --git a/board/amlogic/gxl_p212_v1/Kconfig b/board/amlogic/gxl_p212_v1/Kconfig
new file mode 100644
index 0000000..3caff24
--- /dev/null
+++ b/board/amlogic/gxl_p212_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxl_p212_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxl_p212_v1"
+
+endif
diff --git a/board/amlogic/gxl_p212_v1/Makefile b/board/amlogic/gxl_p212_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxl_p212_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxl_p212_v1/aml-user-key.sig b/board/amlogic/gxl_p212_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/gxl_p212_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxl_p212_v1/eth_setup.c b/board/amlogic/gxl_p212_v1/eth_setup.c
new file mode 100644
index 0000000..33b5db1
--- /dev/null
+++ b/board/amlogic/gxl_p212_v1/eth_setup.c
@@ -0,0 +1,50 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxl_p212_v1/firmware/board_init.c b/board/amlogic/gxl_p212_v1/firmware/board_init.c
new file mode 100644
index 0000000..22c36d1
--- /dev/null
+++ b/board/amlogic/gxl_p212_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxl_p212_v1/firmware/power.c b/board/amlogic/gxl_p212_v1/firmware/power.c
new file mode 100644
index 0000000..fce6e3c
--- /dev/null
+++ b/board/amlogic/gxl_p212_v1/firmware/power.c
@@ -0,0 +1,185 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5);
+ reg |= (1 << 11); // enable PWM_B
+ P_PIN_MUX_REG2 = reg;
+ break;
+
+ case pwm_d:
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_d);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxl_p212_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxl_p212_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..f15c3e4
--- /dev/null
+++ b/board/amlogic/gxl_p212_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,171 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+ DVFS(1200000000, 1020+50),
+ DVFS(1512000000, 1110+30),
+};
+
+
+
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_D;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_D = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/gxl_p212_v1/firmware/scp_task/dvfs_board.h b/board/amlogic/gxl_p212_v1/firmware/scp_task/dvfs_board.h
new file mode 100644
index 0000000..ceede58
--- /dev/null
+++ b/board/amlogic/gxl_p212_v1/firmware/scp_task/dvfs_board.h
@@ -0,0 +1,3 @@
+#ifndef __DVFS_BOARD_H__
+extern int pwm_voltage_table[31][2];
+#endif
diff --git a/board/amlogic/gxl_p212_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxl_p212_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100755
index 0000000..8481308
--- /dev/null
+++ b/board/amlogic/gxl_p212_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,290 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "dvfs_board.h"
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB \
+ (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD \
+ (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+#define ON 1
+#define OFF 0
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+static struct pwr_op *g_pwr_op;
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage)
+ break;
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table))
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+
+ switch (id) {
+ case pwm_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+/*GPIOH_3*/
+static void hdmi_5v_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* VCC5V ON GPIOH_3 output mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 0);
+ } else {
+ /* VCC5V OFF GPIOH_3 input mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 1 << 23);
+ }
+}
+/*GPIODV_25*/
+static void vcck_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 1 << 25);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ } else {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 0);
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+ hdmi_5v_ctrl(OFF);
+ vcck_ctrl(OFF);
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_SLEEP_VOLTAGE);
+ /* reduce power */
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ vcck_ctrl(ON);
+ hdmi_5v_ctrl(ON);
+}
+
+static void power_off_at_24M(void)
+{
+ /* LED GPIODV_24*/
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ if (g_pwr_op->exit_reason != 4) {
+ /* bluetooth wakeup */
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 1 << 24);
+ }
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_2;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+#ifdef CONFIG_BT_WAKEUP
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_18;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+#endif
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned int ret;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1) {
+ cec_node_init();
+ }
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ ret = remote_detect_key();
+ if (ret == 1)
+ exit_reason = REMOTE_WAKEUP;
+ if (ret == 2)
+ exit_reason = REMOTE_CUS_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<2)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+#ifdef CONFIG_BT_WAKEUP
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 18))
+ && (readl(PREG_PAD_GPIO4_O) & (0x01 << 17))
+ && !(readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 17)))
+ exit_reason = BT_WAKEUP;
+ }
+#endif
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+ pwr_op->exit_reason = 0;
+ g_pwr_op = pwr_op;
+}
+
diff --git a/board/amlogic/gxl_p212_v1/firmware/timing.c b/board/amlogic/gxl_p212_v1/firmware/timing.c
new file mode 100644
index 0000000..a2f4892
--- /dev/null
+++ b/board/amlogic/gxl_p212_v1/firmware/timing.c
@@ -0,0 +1,694 @@
+
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_120OHM 2
+#define LPDDR3_ODT_240OHM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_40OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_0OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_34OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+//#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+//#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CONFIG_SOC_VREF 1+ (50+((50*48)/(48+480/(6+1)))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF 1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#else
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#endif
+
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (9),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = 9,//12,//(23), //6 7 8 9 10 11 ok ,bit0-3 max is 15 ,why use 15 is bad 2016_11_10 jiaxing ,test should change with ddr frequency ?
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = 6,// (6),0
+ .cfg_ddr_wtr = (6+2),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (12),//12-17
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (168),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (39-2),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = 9,//9,// (4),//rank0 rank1 turn aroud time jiaxing modify should big for 2rank lpddr3
+ .cfg_ddr_cksre = 12,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 12,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (100),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (12),
+ .cfg_ddr_zqcsi = (1000),
+ // .cfg_ddr_rpab = (17),
+ // .cfg_ddr_rppb = (15),
+ // .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ // .cfg_ddr_tdqsckmax = (5),
+ // .cfg_ddr_tckesr = (12),
+ // .cfg_ddr_tdpd = (500),
+ // .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#if (CONFIG_LPDDR_REMAP_SET == LPDDR_DIE_ROW_COL_R14_C9)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#elif (CONFIG_LPDDR_REMAP_SET== LPDDR_DIE_ROW_COL_R13_C10)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#endif /*CONFIG_LPDDR_REMAP_SET*/
+#else
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+#endif /*CONFIG_DDR_TYPE_LPDDR3*/
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+//lpddr3
+ .t_pub_zq0pr = 0x0ca1c, //0x0ca1c, //PUB ZQ0PR //lpddr3
+ .t_pub_zq1pr = 0x1cf3c, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x1cf3c, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+/* 2layer board
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+*/
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+/* 4layer ddr4 */
+ .t_pub_zq0pr = 0x0995d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#else // ddr3 and auto
+/* p212 4layer board ddr3 */
+ .t_pub_zq0pr = 0x5d95d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x5d95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x5d95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#endif
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+///*lpddr3
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune TAKE CARE LPDDR3 ADD/CMD DELAY
+ .t_pub_aclcdlr = 0,
+ .t_pub_acbdlr3 = 0x2020,//0, //CK0 delay fine tune b-3f //lpddr3 tianhe 2016-10-13
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+//2layer board DDR4
+ .t_pub_acbdlr0 = 0, //0x3f,
+ .t_pub_aclcdlr = 0, //0x28,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0, //0x10,// 0x10,//0xa, //cs add 22ohm 08 0ohm 0x10
+#else // ddr3 and auto
+//4layer ddr3
+ .t_pub_acbdlr0 = 0,
+ .t_pub_aclcdlr = 0,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0,//0xa, //cs
+#endif
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ //tianhe lpddr3 20161013
+ .wr_adj_per = {
+ [0] = 90, //aclcdlr
+ [1] = 100,
+ [2] = 120,
+ [3] = 110,
+ [4] = 120,
+ [5] = 105,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 110,
+ [3] = 110,
+ [4] = 110,
+ [5] = 110,},
+#else
+ /* P212 */
+ .wr_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=95,
+ [3]=95,
+ [4]=95,
+ [5]=95,
+ },
+ .rd_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=88,
+ [3]=95,
+ [4]=95,
+ [5]=100,
+ },
+#endif
+
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+ /* pll ssc setting:
+
+ .ddr_pll_ssc = 0x00120000, ppm1000 center SS, boot log show: Set ddr ssc: ppm1000
+ .ddr_pll_ssc = 0x00124000, ppm1000 up SS, boot log show: Set ddr ssc: ppm1000+
+ .ddr_pll_ssc = 0x00128000, ppm1000 down SS, boot log show: Set ddr ssc: ppm1000-
+
+ .ddr_pll_ssc = 0x00140000, ppm2000 center SS, boot log show: Set ddr ssc: ppm2000
+ .ddr_pll_ssc = 0x00144000, ppm2000 up SS, boot log show: Set ddr ssc: ppm2000+
+ .ddr_pll_ssc = 0x00148000, ppm2000 down SS, boot log show: Set ddr ssc: ppm2000-
+
+ .ddr_pll_ssc = 0x00160000, ppm3000 center SS, boot log show: Set ddr ssc: ppm3000
+ .ddr_pll_ssc = 0x00164000, ppm3000 up SS, boot log show: Set ddr ssc: ppm3000+
+ .ddr_pll_ssc = 0x00168000, ppm3000 down SS, boot log show: Set ddr ssc: ppm3000-
+ */
+ .ddr_pll_ssc = 0,
+};
diff --git a/board/amlogic/gxl_p212_v1/gxl_p212_v1.c b/board/amlogic/gxl_p212_v1/gxl_p212_v1.c
new file mode 100644
index 0000000..e46e589
--- /dev/null
+++ b/board/amlogic/gxl_p212_v1/gxl_p212_v1.c
@@ -0,0 +1,641 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+#include <asm/arch/mailbox.h>
+#ifdef DTB_BIND_KERNEL
+#include "storage.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ } else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+ __maybe_unused struct mmc *mmc;
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+#if defined(CONFIG_ENV_IS_NOWHERE) && defined(CONFIG_AML_SD_EMMC)
+ /* try emmc here. */
+ mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ if (!mmc)
+ printf("%s() %d: No MMC found\n", __func__, __LINE__);
+ else if (mmc_init(mmc))
+ printf("%s() %d: MMC init failed\n", __func__, __LINE__);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23);
+ clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23);
+}
+#endif
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24));
+ //set output 1
+ setbits_le32(PREG_PAD_GPIO0_O, (1 << 24));
+
+ /*Power on GPIOAO_2 for VCC_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+#define SAMPLE_BIT_MASK 0xfff
+#define NUM 50
+#define BASE_CH7 1843
+#define P_SAR_ADC_REG0 (volatile unsigned int *)0xc1108680
+#define P_SAR_ADC_CHAN_LIST (volatile unsigned int *)0xc1108684
+#define P_SAR_ADC_REG3 (volatile unsigned int *)0xc110868c
+#define P_SAR_ADC_FIFO_RD (volatile unsigned int *)0xc1108698
+#define P_SAR_ADC_DETECT_IDLE_SW (volatile unsigned int *)0xc11086a4
+#define P_SAR_ADC_REG13 (volatile unsigned int *)0xc11086b4
+#if 0
+#define dbgv(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define dbgv(fmt, ...)
+#endif
+void quicksort1(unsigned int a[], int numsize)
+{
+ int i = 0, j = numsize-1;
+ int val = a[0];
+ if (numsize > 1) {
+ while (i < j) {
+ for (; j > i; j--)
+ if (a[j] < val) {
+ a[i] = a[j];
+ break;
+ }
+ for (; i < j; i++)
+ if (a[i] > val) {
+ a[j] = a[i];
+ break;
+ }
+ }
+ a[i] = val;
+ quicksort1(a, i);
+ quicksort1(a+i+1, numsize-1-i);
+}
+}
+int check_vref(void)
+{
+ int i,count;
+ unsigned int value[50];
+ unsigned int value7=0;
+ unsigned int bak, bak_reg3;
+ unsigned int vref_efuse = (readl(SEC_AO_SEC_SD_CFG12)>>19)&(0x1f);
+
+ if (!vref_efuse) {
+ dbgv("This chip has no FT vref, no need to check, PASS\n");
+ return 0;
+ }
+ //run_command("md 0xc1108680 0x10", 0);
+ dbgv("SEC_AO_SEC_SD_CFG12: 0x%x\n",readl(SEC_AO_SEC_SD_CFG12));
+ dbgv("vref_efuse: %d\n",vref_efuse);
+
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ bak = (readl(P_SAR_ADC_REG13)>>8)&0x3f; /*back up SAR_ADC_REG13[13:8]*/
+ writel((readl(P_SAR_ADC_REG13)&(~(0x3f<<8)))|(vref_efuse<<9), P_SAR_ADC_REG13);
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ writel(0x00000007, P_SAR_ADC_CHAN_LIST);/*ch7*/
+ //writel(0xc000c|(0x7<<23)|(0x7<<7), P_SAR_ADC_DETECT_IDLE_SW);/*channel 7*/
+ bak_reg3 = readl(P_SAR_ADC_REG3);
+ writel((readl(P_SAR_ADC_REG3)&(~(0x7<<23)))|(0x2<<23), P_SAR_ADC_REG3);/*AVDD18/2*/
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ //run_command("md 0xc1108680 0x10", 0);
+ for (i=0;i<NUM;i++) {
+ writel((readl(P_SAR_ADC_REG0)&(~(1<<0))), P_SAR_ADC_REG0);
+ writel((readl(P_SAR_ADC_REG0)|(1<<0)), P_SAR_ADC_REG0);
+ writel((readl(P_SAR_ADC_REG0)|(1<<2)), P_SAR_ADC_REG0);/*start sample*/
+ count = 0;
+ do {
+ udelay(20);
+ count++;
+ } while ((readl(P_SAR_ADC_REG0) & (0x7<<28))
+ && (count < 100));/*finish sample?*/
+ if (count == 100) {
+ printf("%s : ch7 wait finish sample timeout!\n",__func__);
+ return -1;
+ }
+ value[i] = readl(P_SAR_ADC_FIFO_RD); /*read saradc*/
+ if (((value[i]>>12) & 0x7) == 0x7)
+ value[i] = value[i]&SAMPLE_BIT_MASK;
+ else {
+ printf("%s : not ch7! sample err!\n",__func__);
+ return -1;
+ }
+ }
+ quicksort1(value, NUM);
+ for (i = 0; i < NUM; i++)
+ dbgv("%d ", value[i]);
+ dbgv("\n");
+ for (i = 2; i < NUM-2; i++)
+ value7 += value[i];
+ value7 = value7/(NUM-4);
+ dbgv("the average ch7 adc=%d\n", value7);
+ dbgv("vref_efuse: %d\n",vref_efuse);
+ if ((value7 < (BASE_CH7*94/100)) || (value7 > (BASE_CH7*106/100))) { //1843
+ printf("the average ch7 : %d out of range: %d ~ %d\n",
+ value7, (BASE_CH7*94/100), (BASE_CH7*106/100));
+ printf("replace FT vref...\n");
+ thermal_calibration(4, bak>>1); /*[13:9]*/
+ }
+ /*write back SAR_ADC_REG13[13:8]*/
+ writel(((readl(P_SAR_ADC_REG13))&(~(0x3f<<8)))|
+ ((bak & 0x3f)<<8),
+ P_SAR_ADC_REG13);
+ writel(bak_reg3, P_SAR_ADC_REG3);
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ dbgv("SEC_AO_SEC_SD_CFG12: 0x%x\n",readl(SEC_AO_SEC_SD_CFG12));
+ //run_command("md 0xc1108680 0x10", 0);
+ return 0;
+}
+
+int board_late_init(void){
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ ret = check_vref();
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) {
+ setenv("maxcpus","4");
+ }
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int ddr_size=0;
+ char loc_name[64] = {0};
+ int i;
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+ switch (ddr_size) {
+ case 0x80000000:
+ strcpy(loc_name, "gxl_p212_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "gxl_p212_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "gxl_p212_512m\0");
+ break;
+ default:
+ //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "gxl_p212_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/gxl_p212_v1/lcd.c b/board/amlogic/gxl_p212_v1/lcd.c
new file mode 100755
index 0000000..c738f2f
--- /dev/null
+++ b/board/amlogic/gxl_p212_v1/lcd.c
@@ -0,0 +1,254 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {
+ "lcd_0",LCD_TTL,6,
+ /* basic timing */
+ 1280,720,1650,750,40,220,1,5,20,1,
+ /* clk_attr */
+ 0,0,1,74250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* ttl_attr */
+ 0,1,1,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ 0xff,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+};
+
+//**** Special parameters just for ttl ***//
+static struct ttl_config_s lcd_ttl_config = {
+ .clk_pol = 0,
+ .sync_valid = (1 << 1) | (1 << 0), /* [1]DE, [0]hvsync */
+ .swap_ctrl = (0 << 1) | (0 << 0), /* [1]rb swap, [0]bit swap */
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .ttl_config = &lcd_ttl_config,
+ .lvds_config = &lcd_lvds_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 0,
+ .pinmux_set = {{3, 0x000002a0}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{1, 0xfa030000}, {2, 0xf9fe0409}, {3, 0x00000001}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_D, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinctrl_ver = 0,
+ .pinmux_set = {{2, 0x00000800}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{1, 0x00000400}, {2, 0x00000020}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/gxl_p230_v1/Kconfig b/board/amlogic/gxl_p230_v1/Kconfig
new file mode 100644
index 0000000..b03218c
--- /dev/null
+++ b/board/amlogic/gxl_p230_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxm_q200_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxl_p230_v1"
+
+endif
diff --git a/board/amlogic/gxl_p230_v1/README b/board/amlogic/gxl_p230_v1/README
new file mode 100644
index 0000000..956b1fb
--- /dev/null
+++ b/board/amlogic/gxl_p230_v1/README
@@ -0,0 +1 @@
+p230 config use q200 files.
diff --git a/board/amlogic/gxl_p231_v1/Kconfig b/board/amlogic/gxl_p231_v1/Kconfig
new file mode 100644
index 0000000..5fa57da
--- /dev/null
+++ b/board/amlogic/gxl_p231_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxm_q201_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxl_p231_v1"
+
+endif
diff --git a/board/amlogic/gxl_p231_v1/README b/board/amlogic/gxl_p231_v1/README
new file mode 100644
index 0000000..b8a12ac
--- /dev/null
+++ b/board/amlogic/gxl_p231_v1/README
@@ -0,0 +1 @@
+p231 config use q201 files.
diff --git a/board/amlogic/gxl_p241_v1/Kconfig b/board/amlogic/gxl_p241_v1/Kconfig
new file mode 100644
index 0000000..7d6a814
--- /dev/null
+++ b/board/amlogic/gxl_p241_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxl_p241_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxl_p241_v1"
+
+endif
diff --git a/board/amlogic/gxl_p241_v1/Makefile b/board/amlogic/gxl_p241_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxl_p241_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxl_p241_v1/aml-user-key.sig b/board/amlogic/gxl_p241_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/gxl_p241_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxl_p241_v1/eth_setup.c b/board/amlogic/gxl_p241_v1/eth_setup.c
new file mode 100644
index 0000000..33b5db1
--- /dev/null
+++ b/board/amlogic/gxl_p241_v1/eth_setup.c
@@ -0,0 +1,50 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxl_p241_v1/firmware/board_init.c b/board/amlogic/gxl_p241_v1/firmware/board_init.c
new file mode 100644
index 0000000..22c36d1
--- /dev/null
+++ b/board/amlogic/gxl_p241_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxl_p241_v1/firmware/power.c b/board/amlogic/gxl_p241_v1/firmware/power.c
new file mode 100644
index 0000000..fce6e3c
--- /dev/null
+++ b/board/amlogic/gxl_p241_v1/firmware/power.c
@@ -0,0 +1,185 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5);
+ reg |= (1 << 11); // enable PWM_B
+ P_PIN_MUX_REG2 = reg;
+ break;
+
+ case pwm_d:
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_d);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxl_p241_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxl_p241_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..aa35781
--- /dev/null
+++ b/board/amlogic/gxl_p241_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,171 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+ DVFS(1200000000, 1020+50),
+// DVFS(1512000000, 1110+30),
+};
+
+
+
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_D;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_D = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/gxl_p241_v1/firmware/scp_task/dvfs_board.h b/board/amlogic/gxl_p241_v1/firmware/scp_task/dvfs_board.h
new file mode 100644
index 0000000..ceede58
--- /dev/null
+++ b/board/amlogic/gxl_p241_v1/firmware/scp_task/dvfs_board.h
@@ -0,0 +1,3 @@
+#ifndef __DVFS_BOARD_H__
+extern int pwm_voltage_table[31][2];
+#endif
diff --git a/board/amlogic/gxl_p241_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxl_p241_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100755
index 0000000..b8af1a2
--- /dev/null
+++ b/board/amlogic/gxl_p241_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,289 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "dvfs_board.h"
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB \
+ (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD \
+ (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+#define ON 1
+#define OFF 0
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+static struct pwr_op *g_pwr_op;
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage)
+ break;
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table))
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+
+ switch (id) {
+ case pwm_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+/*GPIOAO_9*/
+static void hdmi_5v_ctrl(unsigned int ctrl)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 9, 0);
+ if (ctrl == ON) {
+ /* VCC5V ON GPIOAO_9 output mode*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 25, 1 << 25);
+ } else {
+ /* VCC5V OFF GPIOAO_9 input mode*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 25, 0);
+ }
+}
+/*GPIODV_25*/
+static void vcck_ctrl(unsigned int ctrl)
+{
+ return; //p241 don't need vcck control
+ if (ctrl == ON) {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 1 << 25);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ } else {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 0);
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+ hdmi_5v_ctrl(OFF);
+ vcck_ctrl(OFF);
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_SLEEP_VOLTAGE);
+ /* reduce power */
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ vcck_ctrl(ON);
+ hdmi_5v_ctrl(ON);
+}
+
+static void power_off_at_24M(void)
+{
+ /* LED GPIODV_24*/
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ if (g_pwr_op->exit_reason != 4) {
+ /* bluetooth wakeup */
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 1 << 24);
+ }
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_2;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_13;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned int ret;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1) {
+ cec_node_init();
+ }
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ ret = remote_detect_key();
+ if (ret == 1)
+ exit_reason = REMOTE_WAKEUP;
+ if (ret == 2)
+ exit_reason = REMOTE_CUS_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<2)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 13))
+ && (readl(PREG_PAD_GPIO4_O) & (0x01 << 12))
+ && !(readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 12)))
+ exit_reason = BT_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+ pwr_op->exit_reason = 0;
+ g_pwr_op = pwr_op;
+}
+
diff --git a/board/amlogic/gxl_p241_v1/firmware/timing.c b/board/amlogic/gxl_p241_v1/firmware/timing.c
new file mode 100644
index 0000000..8646b43
--- /dev/null
+++ b/board/amlogic/gxl_p241_v1/firmware/timing.c
@@ -0,0 +1,717 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 20
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_120OHM 2
+#define LPDDR3_ODT_240OHM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_40OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_0OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+#define CFG_DDR4_DRV_RANK1 DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT_RANK1 DDR4_ODT_48OHM//DDR4_ODT_60OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#define CONFIG_DRAM_VREF_RANK1 750/12// 1+ (50+((50*37)/(37+60/1))) //50// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CONFIG_SOC_VREF (1+ (50+((50*48)/(48+480/(6+1)))))// (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF (1+ (50+((50*34)/(34+60))))// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#else
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#endif
+
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (9),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (9),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = 6,// (6),0
+ .cfg_ddr_wtr = (6+2),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (12),//12-17
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (168),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (39),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = 9,//9,// (4),//rank0 rank1 turn aroud time jiaxing modify should big for 2rank lpddr3
+ .cfg_ddr_cksre = 12,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 12,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (100),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (12),
+ .cfg_ddr_zqcsi = (1000),
+ // .cfg_ddr_rpab = (17),
+ // .cfg_ddr_rppb = (15),
+ // .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ // .cfg_ddr_tdqsckmax = (5),
+ // .cfg_ddr_tckesr = (12),
+ // .cfg_ddr_tdpd = (500),
+ // .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#if (CONFIG_LPDDR_REMAP_SET == LPDDR_DIE_ROW_COL_R14_C9)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#elif (CONFIG_LPDDR_REMAP_SET== LPDDR_DIE_ROW_COL_R13_C10)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#endif /*CONFIG_LPDDR_REMAP_SET*/
+#else
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+#endif /*CONFIG_DDR_TYPE_LPDDR3*/
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b | (1<<22),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+//lpddr3
+ .t_pub_zq0pr = 0x0ca1c, //0x0ca1c, //PUB ZQ0PR //lpddr3
+ .t_pub_zq1pr = 0x1cf3c, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x1cf3c, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+/* 2layer board
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+*/
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+/* 4layer ddr4 */
+ .t_pub_zq0pr = 0x0775d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x6fc5d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x6fc5d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#else // ddr3 and auto
+/* p212 4layer board ddr3 */
+ .t_pub_zq0pr = 0x775d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x6fc5d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x6fc5d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#endif
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+///*lpddr3
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune TAKE CARE LPDDR3 ADD/CMD DELAY
+ .t_pub_aclcdlr = 0,
+ .t_pub_acbdlr3 = 0x2020,//0, //CK0 delay fine tune b-3f //lpddr3 tianhe 2016-10-13
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+//2layer board DDR4
+ .t_pub_acbdlr0 = 0x3f, //0x3f,
+ .t_pub_aclcdlr = 0x28, //0x28,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0x10, //0x10,// 0x10,//0xa, //cs add 22ohm 08 0ohm 0x10
+#else // ddr3 and auto
+//4layer ddr3
+ .t_pub_acbdlr0 = 0,
+ .t_pub_aclcdlr = 0,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0,//0xa, //cs
+#endif
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+
+
+ .t_pub_mr[1] = ( (0|(CFG_DDR4_DRV_RANK1<<1)|((CFG_DDR4_ODT_RANK1)<<8) |
+ (0<<7) |
+ (0 << 3 ))) ,//jiaxing
+ .t_pub_soc_vref_dram_vref_rank1 = ((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF_RANK1))<45)?(0):((((CONFIG_DRAM_VREF_RANK1))<61)?((((((CONFIG_DRAM_VREF_RANK1*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF_RANK1*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF_RANK1*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF_RANK1*1000-60000)/650)))))) ,//jiaxing
+
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ //tianhe lpddr3 20161013
+ .wr_adj_per = {
+ [0] = 90, //aclcdlr
+ [1] = 100,
+ [2] = 120,
+ [3] = 110,
+ [4] = 120,
+ [5] = 105,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 110,
+ [3] = 110,
+ [4] = 110,
+ [5] = 110,},
+#else
+ /* P212 */
+ .wr_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=95,
+ [3]=95,
+ [4]=95,
+ [5]=95,
+ },
+ .rd_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=95,
+ [3]=95,
+ [4]=95,
+ [5]=95,
+ },
+#endif
+ .wr_adj_per_rank1 = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 95,
+ [3] = 95,
+ [4] = 95,
+ [5] = 95,
+ },
+ .rd_adj_per_rank1 = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 95,
+ [3] = 95,
+ [4] = 95,
+ [5] = 95,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+ /* pll ssc setting:
+
+ .ddr_pll_ssc = 0x00120000, ppm1000 center SS, boot log show: Set ddr ssc: ppm1000
+ .ddr_pll_ssc = 0x00124000, ppm1000 up SS, boot log show: Set ddr ssc: ppm1000+
+ .ddr_pll_ssc = 0x00128000, ppm1000 down SS, boot log show: Set ddr ssc: ppm1000-
+
+ .ddr_pll_ssc = 0x00140000, ppm2000 center SS, boot log show: Set ddr ssc: ppm2000
+ .ddr_pll_ssc = 0x00144000, ppm2000 up SS, boot log show: Set ddr ssc: ppm2000+
+ .ddr_pll_ssc = 0x00148000, ppm2000 down SS, boot log show: Set ddr ssc: ppm2000-
+
+ .ddr_pll_ssc = 0x00160000, ppm3000 center SS, boot log show: Set ddr ssc: ppm3000
+ .ddr_pll_ssc = 0x00164000, ppm3000 up SS, boot log show: Set ddr ssc: ppm3000+
+ .ddr_pll_ssc = 0x00168000, ppm3000 down SS, boot log show: Set ddr ssc: ppm3000-
+ */
+ .ddr_pll_ssc = 0x00128000,
+};
diff --git a/board/amlogic/gxl_p241_v1/gxl_p241_v1.c b/board/amlogic/gxl_p241_v1/gxl_p241_v1.c
new file mode 100644
index 0000000..440a5fa
--- /dev/null
+++ b/board/amlogic/gxl_p241_v1/gxl_p241_v1.c
@@ -0,0 +1,548 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+#ifdef DTB_BIND_KERNEL
+#include "storage.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ } else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+ __maybe_unused struct mmc *mmc;
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+#if defined(CONFIG_ENV_IS_NOWHERE) && defined(CONFIG_AML_SD_EMMC)
+ /* try emmc here. */
+ mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ if (!mmc)
+ printf("%s() %d: No MMC found\n", __func__, __LINE__);
+ else if (mmc_init(mmc))
+ printf("%s() %d: MMC init failed\n", __func__, __LINE__);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23);
+ clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23);
+}
+#endif
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24));
+ //set output 1
+ setbits_le32(PREG_PAD_GPIO0_O, (1 << 24));
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) {
+ setenv("maxcpus","4");
+ }
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 7 p241 v1
+ * hwid = 11 p241 v2
+ */
+ unsigned int hwid = 7;
+
+ unsigned int ddr_size=0;
+ char loc_name[64] = {0};
+ int i;
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+ printf("checkhw: hwid = %d\n", hwid);
+
+ switch (hwid) {
+ case 7:
+ printf("checkhw -> 7\n");
+ switch (ddr_size) {
+ case 0x80000000:
+ strcpy(loc_name, "gxl_p241_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "gxl_p241_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "gxl_p241_512m\0");
+ break;
+ default:
+ //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "gxl_p241_unsupport\0");
+ break;
+ }
+ break;
+ case 11:
+ strcpy(loc_name, "gxl_p241_v2-1g\0");
+ break;
+ default:
+ strcpy(loc_name, "gxl_p241_unsupport\0");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/gxl_p271_v1/Kconfig b/board/amlogic/gxl_p271_v1/Kconfig
new file mode 100644
index 0000000..34fd1ba
--- /dev/null
+++ b/board/amlogic/gxl_p271_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxl_p271_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxl_p271_v1"
+
+endif
diff --git a/board/amlogic/gxl_p271_v1/Makefile b/board/amlogic/gxl_p271_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxl_p271_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxl_p271_v1/aml-user-key.sig b/board/amlogic/gxl_p271_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/gxl_p271_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxl_p271_v1/eth_setup.c b/board/amlogic/gxl_p271_v1/eth_setup.c
new file mode 100644
index 0000000..33b5db1
--- /dev/null
+++ b/board/amlogic/gxl_p271_v1/eth_setup.c
@@ -0,0 +1,50 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxl_p271_v1/firmware/board_init.c b/board/amlogic/gxl_p271_v1/firmware/board_init.c
new file mode 100644
index 0000000..22c36d1
--- /dev/null
+++ b/board/amlogic/gxl_p271_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxl_p271_v1/firmware/power.c b/board/amlogic/gxl_p271_v1/firmware/power.c
new file mode 100644
index 0000000..fce6e3c
--- /dev/null
+++ b/board/amlogic/gxl_p271_v1/firmware/power.c
@@ -0,0 +1,185 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5);
+ reg |= (1 << 11); // enable PWM_B
+ P_PIN_MUX_REG2 = reg;
+ break;
+
+ case pwm_d:
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_d);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxl_p271_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxl_p271_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..f15c3e4
--- /dev/null
+++ b/board/amlogic/gxl_p271_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,171 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+ DVFS(1200000000, 1020+50),
+ DVFS(1512000000, 1110+30),
+};
+
+
+
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_D;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_D = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/gxl_p271_v1/firmware/scp_task/dvfs_board.h b/board/amlogic/gxl_p271_v1/firmware/scp_task/dvfs_board.h
new file mode 100644
index 0000000..ceede58
--- /dev/null
+++ b/board/amlogic/gxl_p271_v1/firmware/scp_task/dvfs_board.h
@@ -0,0 +1,3 @@
+#ifndef __DVFS_BOARD_H__
+extern int pwm_voltage_table[31][2];
+#endif
diff --git a/board/amlogic/gxl_p271_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxl_p271_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..373141b
--- /dev/null
+++ b/board/amlogic/gxl_p271_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,286 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "dvfs_board.h"
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB \
+ (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD \
+ (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+#define ON 1
+#define OFF 0
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+static struct pwr_op *g_pwr_op;
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage)
+ break;
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table))
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+
+ switch (id) {
+ case pwm_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+/*GPIOH_3*/
+static void hdmi_5v_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* VCC5V ON GPIOH_3 output mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 0);
+ } else {
+ /* VCC5V OFF GPIOH_3 input mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 1 << 23);
+ }
+}
+/*GPIODV_25*/
+static void vcck_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 1 << 25);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ } else {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 0);
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+ hdmi_5v_ctrl(OFF);
+ vcck_ctrl(OFF);
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_SLEEP_VOLTAGE);
+ /* reduce power */
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ vcck_ctrl(ON);
+ hdmi_5v_ctrl(ON);
+}
+
+static void power_off_at_24M(void)
+{
+ /* LED GPIODV_24*/
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ if (g_pwr_op->exit_reason != 4) {
+ /* bluetooth wakeup */
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 1 << 24);
+ }
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[0]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_2;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count++;
+
+ gpio = &(p->gpio_info[1]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_18;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count++;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned int ret;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1) {
+ cec_node_init();
+ }
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ ret = remote_detect_key();
+ if (ret == 1)
+ exit_reason = REMOTE_WAKEUP;
+ if (ret == 2)
+ exit_reason = REMOTE_CUS_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<2)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 18))
+ && (readl(PREG_PAD_GPIO4_O) & (0x01 << 17))
+ && !(readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 17)))
+ exit_reason = BT_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+ pwr_op->exit_reason = 0;
+ g_pwr_op = pwr_op;
+}
+
diff --git a/board/amlogic/gxl_p271_v1/firmware/timing.c b/board/amlogic/gxl_p271_v1/firmware/timing.c
new file mode 100644
index 0000000..3fd679e
--- /dev/null
+++ b/board/amlogic/gxl_p271_v1/firmware/timing.c
@@ -0,0 +1,693 @@
+
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_120OHM 2
+#define LPDDR3_ODT_240OHM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_40OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_0OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_34OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+//#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+//#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CONFIG_SOC_VREF 1+ (50+((50*48)/(48+480/(6+1)))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF 1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#else
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#endif
+
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (9),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = 9,//12,//(23), //6 7 8 9 10 11 ok ,bit0-3 max is 15 ,why use 15 is bad 2016_11_10 jiaxing ,test should change with ddr frequency ?
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = 6,// (6),0
+ .cfg_ddr_wtr = (6+2),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (12),//12-17
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (168),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (39-2),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = 9,//9,// (4),//rank0 rank1 turn aroud time jiaxing modify should big for 2rank lpddr3
+ .cfg_ddr_cksre = 12,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 12,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (100),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (12),
+ .cfg_ddr_zqcsi = (1000),
+ // .cfg_ddr_rpab = (17),
+ // .cfg_ddr_rppb = (15),
+ // .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ // .cfg_ddr_tdqsckmax = (5),
+ // .cfg_ddr_tckesr = (12),
+ // .cfg_ddr_tdpd = (500),
+ // .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#if (CONFIG_LPDDR_REMAP_SET == LPDDR_DIE_ROW_COL_R14_C9)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#elif (CONFIG_LPDDR_REMAP_SET== LPDDR_DIE_ROW_COL_R13_C10)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#endif /*CONFIG_LPDDR_REMAP_SET*/
+#else
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+#endif /*CONFIG_DDR_TYPE_LPDDR3*/
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+//lpddr3
+ .t_pub_zq0pr = 0x0ca1c, //0x0ca1c, //PUB ZQ0PR //lpddr3
+ .t_pub_zq1pr = 0x1cf3c, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x1cf3c, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+/* 2layer board
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+*/
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+/* 4layer ddr4 */
+ .t_pub_zq0pr = 0x0995d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#else // ddr3 and auto
+/* p212 4layer board ddr3 */
+ .t_pub_zq0pr = 0x5d95d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x5d95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x5d95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#endif
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+///*lpddr3
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune TAKE CARE LPDDR3 ADD/CMD DELAY
+ .t_pub_aclcdlr = 0,
+ .t_pub_acbdlr3 = 0x2020,//0, //CK0 delay fine tune b-3f //lpddr3 tianhe 2016-10-13
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+//2layer board DDR4
+ .t_pub_acbdlr0 = 0, //0x3f,
+ .t_pub_aclcdlr = 0, //0x28,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0, //0x10,// 0x10,//0xa, //cs add 22ohm 08 0ohm 0x10
+#else // ddr3 and auto
+//s905c 2layer ddr3
+ .t_pub_acbdlr0 = 0x3f,
+ .t_pub_aclcdlr = 0,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0x10,//0xa, //cs
+#endif
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ //tianhe lpddr3 20161013
+ .wr_adj_per = {
+ [0] = 90, //aclcdlr
+ [1] = 100,
+ [2] = 120,
+ [3] = 110,
+ [4] = 120,
+ [5] = 105,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 110,
+ [3] = 110,
+ [4] = 110,
+ [5] = 110,},
+#else
+ /* P212 */
+ .wr_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=95,
+ [3]=95,
+ [4]=95,
+ [5]=95,
+ },
+ .rd_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=95,
+ [3]=95,
+ [4]=95,
+ [5]=95,
+ },
+#endif
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+ /* pll ssc setting:
+
+ .ddr_pll_ssc = 0x00120000, ppm1000 center SS, boot log show: Set ddr ssc: ppm1000
+ .ddr_pll_ssc = 0x00124000, ppm1000 up SS, boot log show: Set ddr ssc: ppm1000+
+ .ddr_pll_ssc = 0x00128000, ppm1000 down SS, boot log show: Set ddr ssc: ppm1000-
+
+ .ddr_pll_ssc = 0x00140000, ppm2000 center SS, boot log show: Set ddr ssc: ppm2000
+ .ddr_pll_ssc = 0x00144000, ppm2000 up SS, boot log show: Set ddr ssc: ppm2000+
+ .ddr_pll_ssc = 0x00148000, ppm2000 down SS, boot log show: Set ddr ssc: ppm2000-
+
+ .ddr_pll_ssc = 0x00160000, ppm3000 center SS, boot log show: Set ddr ssc: ppm3000
+ .ddr_pll_ssc = 0x00164000, ppm3000 up SS, boot log show: Set ddr ssc: ppm3000+
+ .ddr_pll_ssc = 0x00168000, ppm3000 down SS, boot log show: Set ddr ssc: ppm3000-
+ */
+ .ddr_pll_ssc = 0x00128000,
+};
diff --git a/board/amlogic/gxl_p271_v1/gxl_p271_v1.c b/board/amlogic/gxl_p271_v1/gxl_p271_v1.c
new file mode 100644
index 0000000..cc3e5bd
--- /dev/null
+++ b/board/amlogic/gxl_p271_v1/gxl_p271_v1.c
@@ -0,0 +1,529 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+#ifdef DTB_BIND_KERNEL
+#include "storage.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ } else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+ __maybe_unused struct mmc *mmc;
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+#if defined(CONFIG_ENV_IS_NOWHERE) && defined(CONFIG_AML_SD_EMMC)
+ /* try emmc here. */
+ mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ if (!mmc)
+ printf("%s() %d: No MMC found\n", __func__, __LINE__);
+ else if (mmc_init(mmc))
+ printf("%s() %d: MMC init failed\n", __func__, __LINE__);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23);
+ clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23);
+}
+#endif
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24));
+ //set output 1
+ setbits_le32(PREG_PAD_GPIO0_O, (1 << 24));
+
+ /*Power on GPIOAO_2 for VCC_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) {
+ setenv("maxcpus","4");
+ }
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int ddr_size=0;
+ char loc_name[64] = {0};
+ int i;
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+ switch (ddr_size) {
+ case 0x80000000:
+ strcpy(loc_name, "gxl_p271_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "gxl_p271_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "gxl_p271_512m\0");
+ break;
+ default:
+ //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "gxl_p271_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/gxl_p271_v1/lcd.c b/board/amlogic/gxl_p271_v1/lcd.c
new file mode 100755
index 0000000..c738f2f
--- /dev/null
+++ b/board/amlogic/gxl_p271_v1/lcd.c
@@ -0,0 +1,254 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {
+ "lcd_0",LCD_TTL,6,
+ /* basic timing */
+ 1280,720,1650,750,40,220,1,5,20,1,
+ /* clk_attr */
+ 0,0,1,74250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* ttl_attr */
+ 0,1,1,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ 0xff,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+};
+
+//**** Special parameters just for ttl ***//
+static struct ttl_config_s lcd_ttl_config = {
+ .clk_pol = 0,
+ .sync_valid = (1 << 1) | (1 << 0), /* [1]DE, [0]hvsync */
+ .swap_ctrl = (0 << 1) | (0 << 0), /* [1]rb swap, [0]bit swap */
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .ttl_config = &lcd_ttl_config,
+ .lvds_config = &lcd_lvds_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 0,
+ .pinmux_set = {{3, 0x000002a0}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{1, 0xfa030000}, {2, 0xf9fe0409}, {3, 0x00000001}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_D, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinctrl_ver = 0,
+ .pinmux_set = {{2, 0x00000800}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{1, 0x00000400}, {2, 0x00000020}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/gxl_p281_v1/Kconfig b/board/amlogic/gxl_p281_v1/Kconfig
new file mode 100644
index 0000000..3e24868
--- /dev/null
+++ b/board/amlogic/gxl_p281_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxl_p281_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxl_p281_v1"
+
+endif
diff --git a/board/amlogic/gxl_p281_v1/Makefile b/board/amlogic/gxl_p281_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxl_p281_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxl_p281_v1/aml-user-key.sig b/board/amlogic/gxl_p281_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/gxl_p281_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxl_p281_v1/eth_setup.c b/board/amlogic/gxl_p281_v1/eth_setup.c
new file mode 100644
index 0000000..33b5db1
--- /dev/null
+++ b/board/amlogic/gxl_p281_v1/eth_setup.c
@@ -0,0 +1,50 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxl_p281_v1/firmware/board_init.c b/board/amlogic/gxl_p281_v1/firmware/board_init.c
new file mode 100644
index 0000000..22c36d1
--- /dev/null
+++ b/board/amlogic/gxl_p281_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxl_p281_v1/firmware/power.c b/board/amlogic/gxl_p281_v1/firmware/power.c
new file mode 100644
index 0000000..fce6e3c
--- /dev/null
+++ b/board/amlogic/gxl_p281_v1/firmware/power.c
@@ -0,0 +1,185 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5);
+ reg |= (1 << 11); // enable PWM_B
+ P_PIN_MUX_REG2 = reg;
+ break;
+
+ case pwm_d:
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_d);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxl_p281_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxl_p281_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..aa35781
--- /dev/null
+++ b/board/amlogic/gxl_p281_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,171 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+ DVFS(1200000000, 1020+50),
+// DVFS(1512000000, 1110+30),
+};
+
+
+
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_D;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_D = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/gxl_p281_v1/firmware/scp_task/dvfs_board.h b/board/amlogic/gxl_p281_v1/firmware/scp_task/dvfs_board.h
new file mode 100644
index 0000000..ceede58
--- /dev/null
+++ b/board/amlogic/gxl_p281_v1/firmware/scp_task/dvfs_board.h
@@ -0,0 +1,3 @@
+#ifndef __DVFS_BOARD_H__
+extern int pwm_voltage_table[31][2];
+#endif
diff --git a/board/amlogic/gxl_p281_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxl_p281_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..5213e19
--- /dev/null
+++ b/board/amlogic/gxl_p281_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,287 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "dvfs_board.h"
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB \
+ (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD \
+ (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+#define ON 1
+#define OFF 0
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+static struct pwr_op *g_pwr_op;
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage)
+ break;
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table))
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+
+ switch (id) {
+ case pwm_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+/*GPIOH_3*/
+static void hdmi_5v_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* VCC5V ON GPIOH_3 output mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 0);
+ } else {
+ /* VCC5V OFF GPIOH_3 input mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 1 << 23);
+ }
+}
+/*GPIODV_25*/
+static void vcck_ctrl(unsigned int ctrl)
+{
+ return; //p281 don't need vcck control
+ if (ctrl == ON) {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 1 << 25);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ } else {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 0);
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+ hdmi_5v_ctrl(OFF);
+ vcck_ctrl(OFF);
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_SLEEP_VOLTAGE);
+ /* reduce power */
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ vcck_ctrl(ON);
+ hdmi_5v_ctrl(ON);
+}
+
+static void power_off_at_24M(void)
+{
+ /* LED GPIODV_24*/
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ if (g_pwr_op->exit_reason != 4) {
+ /* bluetooth wakeup */
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 1 << 24);
+ }
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[0]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_2;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count++;
+
+ gpio = &(p->gpio_info[1]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_18;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count++;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned int ret;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1) {
+ cec_node_init();
+ }
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ ret = remote_detect_key();
+ if (ret == 1)
+ exit_reason = REMOTE_WAKEUP;
+ if (ret == 2)
+ exit_reason = REMOTE_CUS_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<2)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 18))
+ && (readl(PREG_PAD_GPIO4_O) & (0x01 << 17))
+ && !(readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 17)))
+ exit_reason = BT_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+ pwr_op->exit_reason = 0;
+ g_pwr_op = pwr_op;
+}
+
diff --git a/board/amlogic/gxl_p281_v1/firmware/timing.c b/board/amlogic/gxl_p281_v1/firmware/timing.c
new file mode 100644
index 0000000..baafa81
--- /dev/null
+++ b/board/amlogic/gxl_p281_v1/firmware/timing.c
@@ -0,0 +1,694 @@
+
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_120OHM 2
+#define LPDDR3_ODT_240OHM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_40OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_0OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_34OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+//#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+//#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CONFIG_SOC_VREF 1+ (50+((50*48)/(48+480/(6+1)))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF 1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#else
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#endif
+
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (9),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = 9,//12,//(23), //6 7 8 9 10 11 ok ,bit0-3 max is 15 ,why use 15 is bad 2016_11_10 jiaxing ,test should change with ddr frequency ?
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = 6,// (6),0
+ .cfg_ddr_wtr = (6+2),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (12),//12-17
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (168),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (39-2),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = 9,//9,// (4),//rank0 rank1 turn aroud time jiaxing modify should big for 2rank lpddr3
+ .cfg_ddr_cksre = 12,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 12,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (100),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (12),
+ .cfg_ddr_zqcsi = (1000),
+ // .cfg_ddr_rpab = (17),
+ // .cfg_ddr_rppb = (15),
+ // .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ // .cfg_ddr_tdqsckmax = (5),
+ // .cfg_ddr_tckesr = (12),
+ // .cfg_ddr_tdpd = (500),
+ // .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+#if (CONFIG_DDR_REMAP_SET == X4_DDR3)
+ .ddr0_addrmap = {
+ [0]=( 0 | 5 << 5 | 6 << 10 | 7 << 15 | 8 << 20 | 9 << 25 ) ,
+ [1]=( 10| 11<< 5 | 0 << 10 | 14<< 15 | 15<< 20 | 16<< 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21 << 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 29 << 25 ) ,
+ [4]=( 30| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 0 | 5 << 5 | 6 << 10 | 7 << 15 | 8 << 20 | 9 << 25 ) ,
+ [1]=( 10| 11<< 5 | 0 << 10 | 14<< 15 | 15<< 20 | 16<< 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21 << 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 29 << 25 ) ,
+ [4]=( 30| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#elif (CONFIG_DDR_REMAP_SET== LPDDR_DIE_ROW_COL_R13_C10)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#endif /*CONFIG_LPDDR_REMAP_SET*/
+#else
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+#endif /*CONFIG_DDR_TYPE_LPDDR3*/
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = (0x00f05f97 | (1<<19)), //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+//lpddr3
+ .t_pub_zq0pr = 0x0ca1c, //0x0ca1c, //PUB ZQ0PR //lpddr3
+ .t_pub_zq1pr = 0x1cf3c, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x1cf3c, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+/* 2layer board
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+*/
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+/* 4layer ddr4 */
+ .t_pub_zq0pr = 0x0995d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#else // ddr3 and auto
+/* p281 2layer board ddr3 */
+ .t_pub_zq0pr = 0x5d95d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x5d95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x0, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#endif
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+///*lpddr3
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune TAKE CARE LPDDR3 ADD/CMD DELAY
+ .t_pub_aclcdlr = 0,
+ .t_pub_acbdlr3 = 0x2020,//0, //CK0 delay fine tune b-3f //lpddr3 tianhe 2016-10-13
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+//2layer board DDR4
+ .t_pub_acbdlr0 = 0, //0x3f,
+ .t_pub_aclcdlr = 0, //0x28,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0, //0x10,// 0x10,//0xa, //cs add 22ohm 08 0ohm 0x10
+#else // ddr3 and auto
+//4layer ddr3
+ .t_pub_acbdlr0 = 0x18,
+ .t_pub_aclcdlr = 0x20,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0,//0xa, //cs
+#endif
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ //tianhe lpddr3 20161013
+ .wr_adj_per = {
+ [0] = 90, //aclcdlr
+ [1] = 100,
+ [2] = 120,
+ [3] = 110,
+ [4] = 120,
+ [5] = 105,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 110,
+ [3] = 110,
+ [4] = 110,
+ [5] = 110,},
+#else
+ /* P281 */
+ .wr_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=95,
+ [3]=95,
+ [4]=95,
+ [5]=95,
+ },
+ .rd_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=88,
+ [3]=95,
+ [4]=95,
+ [5]=100,
+ },
+#endif
+
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+ /* pll ssc setting:
+
+ .ddr_pll_ssc = 0x00120000, ppm1000 center SS, boot log show: Set ddr ssc: ppm1000
+ .ddr_pll_ssc = 0x00124000, ppm1000 up SS, boot log show: Set ddr ssc: ppm1000+
+ .ddr_pll_ssc = 0x00128000, ppm1000 down SS, boot log show: Set ddr ssc: ppm1000-
+
+ .ddr_pll_ssc = 0x00140000, ppm2000 center SS, boot log show: Set ddr ssc: ppm2000
+ .ddr_pll_ssc = 0x00144000, ppm2000 up SS, boot log show: Set ddr ssc: ppm2000+
+ .ddr_pll_ssc = 0x00148000, ppm2000 down SS, boot log show: Set ddr ssc: ppm2000-
+
+ .ddr_pll_ssc = 0x00160000, ppm3000 center SS, boot log show: Set ddr ssc: ppm3000
+ .ddr_pll_ssc = 0x00164000, ppm3000 up SS, boot log show: Set ddr ssc: ppm3000+
+ .ddr_pll_ssc = 0x00168000, ppm3000 down SS, boot log show: Set ddr ssc: ppm3000-
+ */
+ .ddr_pll_ssc = 0,
+};
diff --git a/board/amlogic/gxl_p281_v1/gxl_p281_v1.c b/board/amlogic/gxl_p281_v1/gxl_p281_v1.c
new file mode 100644
index 0000000..c7293d6
--- /dev/null
+++ b/board/amlogic/gxl_p281_v1/gxl_p281_v1.c
@@ -0,0 +1,524 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+#ifdef DTB_BIND_KERNEL
+#include "storage.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ } else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+ __maybe_unused struct mmc *mmc;
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+#if defined(CONFIG_ENV_IS_NOWHERE) && defined(CONFIG_AML_SD_EMMC)
+ /* try emmc here. */
+ mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ if (!mmc)
+ printf("%s() %d: No MMC found\n", __func__, __LINE__);
+ else if (mmc_init(mmc))
+ printf("%s() %d: MMC init failed\n", __func__, __LINE__);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23);
+ clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23);
+}
+#endif
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 != readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24));
+ //set output 1
+ setbits_le32(PREG_PAD_GPIO0_O, (1 << 24));
+
+ /*Power on GPIOAO_2 for VCC_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) {
+ setenv("maxcpus","4");
+ }
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int ddr_size=0;
+ char loc_name[64] = {0};
+ int i;
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+ switch (ddr_size) {
+
+ case 0x40000000:
+ strcpy(loc_name, "gxl_p281_1g\0");
+ break;
+
+ default:
+ //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "gxl_p281_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/gxl_p400_v1/Kconfig b/board/amlogic/gxl_p400_v1/Kconfig
new file mode 100644
index 0000000..0389ac4
--- /dev/null
+++ b/board/amlogic/gxl_p400_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxl_p400_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxl_p400_v1"
+
+endif
diff --git a/board/amlogic/gxl_p400_v1/Makefile b/board/amlogic/gxl_p400_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxl_p400_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxl_p400_v1/aml-user-key.sig b/board/amlogic/gxl_p400_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/gxl_p400_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxl_p400_v1/eth_setup.c b/board/amlogic/gxl_p400_v1/eth_setup.c
new file mode 100644
index 0000000..33b5db1
--- /dev/null
+++ b/board/amlogic/gxl_p400_v1/eth_setup.c
@@ -0,0 +1,50 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxl_p400_v1/firmware/board_init.c b/board/amlogic/gxl_p400_v1/firmware/board_init.c
new file mode 100644
index 0000000..22c36d1
--- /dev/null
+++ b/board/amlogic/gxl_p400_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxl_p400_v1/firmware/power.c b/board/amlogic/gxl_p400_v1/firmware/power.c
new file mode 100644
index 0000000..0bf4c75
--- /dev/null
+++ b/board/amlogic/gxl_p400_v1/firmware/power.c
@@ -0,0 +1,224 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#define P_PIN_MUX_REG8 (*((volatile unsigned *)(0xda834400 + (0x34 << 2))))
+#define P_PIN_MUX_AO_REG (*((volatile unsigned *)(0xc8100000 + (0x5 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#undef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_PWM_A
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#define P_AO_PWM_PWM_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5);
+ reg |= (1 << 11); // enable PWM_B
+ P_PIN_MUX_REG2 = reg;
+ break;
+
+ case pwm_ao_a:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_AO_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_AO_REG;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 7);
+ P_PIN_MUX_AO_REG = reg;
+
+ reg = P_PIN_MUX_AO_REG;
+ reg |= (1 << 22); // enable PWM_AO_A
+ P_PIN_MUX_AO_REG = reg;
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG8;
+ reg &= ~(1 << 29);
+ P_PIN_MUX_REG8 = reg;
+
+ reg = P_PIN_MUX_REG8;
+ reg |= (1 << 30); // enable PWM_F
+ P_PIN_MUX_REG8 = reg;
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+ case pwm_f:
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ case pwm_ao_a:
+ P_AO_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_ao_a);
+ pwm_init(pwm_f);
+ serial_puts("set vdd cpu_a to ");
+ serial_put_dec(CONFIG_VCCKA_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_a, CONFIG_VCCKA_INIT_VOLTAGE);
+
+ serial_puts("set vdd cpu_b to ");
+ serial_put_dec(CONFIG_VCCKB_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_f, CONFIG_VCCKB_INIT_VOLTAGE);
+
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxl_p400_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxl_p400_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..9e6a648
--- /dev/null
+++ b/board/amlogic/gxl_p400_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,255 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+ DVFS(1200000000, 1020+50),
+ DVFS(1512000000, 1110+30),
+};
+struct scpi_opp_entry vlittle_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+};
+
+
+
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#undef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_PWM_A
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#define P_AO_PWM_PWM_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define P_PIN_MUX_AO_REG (*((volatile unsigned *)(0xc8100000 + (0x5 << 2))))
+#define P_PIN_MUX_REG8 (*((volatile unsigned *)(0xda834400 + (0x34 << 2))))
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_ao_a:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_AO_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_AO_REG;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 7);
+ P_PIN_MUX_AO_REG = reg;
+
+ reg = P_PIN_MUX_AO_REG;
+ reg |= (1 << 22); // enable PWM_AO_A
+ P_PIN_MUX_AO_REG = reg;
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG8;
+ reg &= ~(1 << 29);
+ P_PIN_MUX_REG8 = reg;
+
+ reg = P_PIN_MUX_REG8;
+ reg |= (1 << 30); // enable PWM_F
+ P_PIN_MUX_REG8 = reg;
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+int dvfs_get_voltage(unsigned int domain)
+{
+ int i = 0;
+ unsigned int reg_val = 0x040018;
+
+ if (domain == 0)
+ reg_val = P_AO_PWM_PWM_A;
+
+ if (domain == 1)
+ reg_val = P_PWM_PWM_F;
+
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+ if (!init_flag) {
+ pwm_init(pwm_f);
+ pwm_init(pwm_ao_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage(domain);
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (domain == 0) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (domain == 1) {
+ if (pwm_voltage_table[to][1] >= vlittle_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ if (domain == 0)
+ P_AO_PWM_PWM_A = pwm_voltage_table[to][0];
+ if (domain == 1)
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ if (domain == 0)
+ P_AO_PWM_PWM_A = pwm_voltage_table[cur][0];
+ if (domain == 1)
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ if (domain == 0)
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+ if (domain == 1)
+ cnt = ARRAY_SIZE(vlittle_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ if (domain == 0)
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ if (domain == 1)
+ memcpy(&buf_opp.opp[0], vlittle_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/gxl_p400_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxl_p400_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..3417e6d
--- /dev/null
+++ b/board/amlogic/gxl_p400_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,285 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+
+extern int pwm_voltage_table[31][2];
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+#define P_PWM_PWM_AO_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define ON 1
+#define OFF 0
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_a:
+ uart_puts("set vdd_cpu a to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_AO_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_f:
+ uart_puts("set vdd_cpu a to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+/*GPIOH_3*/
+static void hdmi_5v_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* VCC5V ON GPIOH_3 output mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 0);
+ } else {
+ /* VCC5V OFF GPIOH_3 input mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 1 << 23);
+ }
+}
+/*GPIODV_25*/
+static void vcck_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* vddcpu_a*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 1<<20);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_a, CONFIG_VCCKA_INIT_VOLTAGE);
+
+ /* vddcpu_b*/
+ aml_update_bits(PREG_PAD_GPIO3_EN_N, 1 << 28, 0);
+ aml_update_bits(PREG_PAD_GPIO3_O, 1 << 28, 1<<28);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_f, CONFIG_VCCKB_INIT_VOLTAGE);
+ } else {
+ /* vddcpu_a*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 0);
+
+ /* vddcpu_b*/
+ aml_update_bits(PREG_PAD_GPIO3_EN_N, 1 << 28, 0);
+ aml_update_bits(PREG_PAD_GPIO3_O, 1 << 28, 0);
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+ hdmi_5v_ctrl(OFF);
+ vcck_ctrl(OFF);
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_SLEEP_VOLTAGE); // reduce power
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ vcck_ctrl(ON);
+ hdmi_5v_ctrl(ON);
+}
+
+static void power_off_at_24M(void)
+{
+ /* LED GPIOAO_9*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 9, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 25, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 9, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 25, 1 << 25);
+
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC|ETH_PHY_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_2;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+
+ p->gpio_info_count = ++i;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned int ret;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ ret = remote_detect_key();
+ if (ret == 1)
+ exit_reason = REMOTE_WAKEUP;
+ if (ret == 2)
+ exit_reason = REMOTE_CUS_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<2)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
+
diff --git a/board/amlogic/gxl_p400_v1/firmware/timing.c b/board/amlogic/gxl_p400_v1/firmware/timing.c
new file mode 100644
index 0000000..fbc35f5
--- /dev/null
+++ b/board/amlogic/gxl_p400_v1/firmware/timing.c
@@ -0,0 +1,571 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_40OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_34OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (9),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = 9,//12,//(23), //6 7 8 9 10 11 ok ,bit0-3 max is 15 ,why use 15 is bad 2016_11_10 jiaxing ,test should change with ddr frequency ?
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = 6,// (6),0
+ .cfg_ddr_wtr = (6+2),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (12),//12-17
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (168),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (39-2),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = 9,//9,// (4),//rank0 rank1 turn aroud time jiaxing modify should big for 2rank lpddr3
+ .cfg_ddr_cksre = 12,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 12,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (100),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (12),
+ .cfg_ddr_zqcsi = (1000),
+ // .cfg_ddr_rpab = (17),
+ // .cfg_ddr_rppb = (15),
+ // .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ // .cfg_ddr_tdqsckmax = (5),
+ // .cfg_ddr_tckesr = (12),
+ // .cfg_ddr_tdpd = (500),
+ // .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x5aa59, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x3f94f, //PUB ZQ1PR//0x3f95d, 0x4f95d,
+ .t_pub_zq2pr = 0x3f94f, //PUB ZQ2PR//0x3f95d, 0x4f95d,
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0,
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCKA_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/gxl_p400_v1/gxl_p400_v1.c b/board/amlogic/gxl_p400_v1/gxl_p400_v1.c
new file mode 100644
index 0000000..ed90788
--- /dev/null
+++ b/board/amlogic/gxl_p400_v1/gxl_p400_v1.c
@@ -0,0 +1,517 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+#ifdef CONFIG_INTERNAL_PHY
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+#else
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ //setup ethernet clk need calibrate to configre
+ setbits_le32(P_PERIPHS_PIN_MUX_4, 0xfffc00);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rgmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+ /* hardware reset ethernet phy : gpioz14 connect phyreset pin*/
+ clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 14);
+ clrbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+ udelay(10000);
+ setbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+}
+#endif
+
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+#ifdef CONFIG_INTERNAL_PHY
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+#else
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RGMII);
+#endif
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ } else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 3
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23);
+ clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23);
+}
+#endif
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24));
+ //set output 1
+ setbits_le32(PREG_PAD_GPIO0_O, (1 << 24));
+
+ /*Power on GPIOAO_2 for VCC_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) {
+ setenv("maxcpus","4");
+ }
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXM) {
+ setenv("maxcpus","8");
+ }
+
+ /* load uboot pq value */
+ vpp_pq_load();
+
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
+
diff --git a/board/amlogic/gxl_p401_v1/Kconfig b/board/amlogic/gxl_p401_v1/Kconfig
new file mode 100644
index 0000000..479ca4c
--- /dev/null
+++ b/board/amlogic/gxl_p401_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxl_p401_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxl_p401_v1"
+
+endif
diff --git a/board/amlogic/gxl_p401_v1/Makefile b/board/amlogic/gxl_p401_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxl_p401_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxl_p401_v1/aml-user-key.sig b/board/amlogic/gxl_p401_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/gxl_p401_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxl_p401_v1/eth_setup.c b/board/amlogic/gxl_p401_v1/eth_setup.c
new file mode 100644
index 0000000..33b5db1
--- /dev/null
+++ b/board/amlogic/gxl_p401_v1/eth_setup.c
@@ -0,0 +1,50 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxl_p401_v1/firmware/board_init.c b/board/amlogic/gxl_p401_v1/firmware/board_init.c
new file mode 100644
index 0000000..22c36d1
--- /dev/null
+++ b/board/amlogic/gxl_p401_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxl_p401_v1/firmware/power.c b/board/amlogic/gxl_p401_v1/firmware/power.c
new file mode 100644
index 0000000..0bf4c75
--- /dev/null
+++ b/board/amlogic/gxl_p401_v1/firmware/power.c
@@ -0,0 +1,224 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#define P_PIN_MUX_REG8 (*((volatile unsigned *)(0xda834400 + (0x34 << 2))))
+#define P_PIN_MUX_AO_REG (*((volatile unsigned *)(0xc8100000 + (0x5 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#undef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_PWM_A
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#define P_AO_PWM_PWM_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5);
+ reg |= (1 << 11); // enable PWM_B
+ P_PIN_MUX_REG2 = reg;
+ break;
+
+ case pwm_ao_a:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_AO_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_AO_REG;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 7);
+ P_PIN_MUX_AO_REG = reg;
+
+ reg = P_PIN_MUX_AO_REG;
+ reg |= (1 << 22); // enable PWM_AO_A
+ P_PIN_MUX_AO_REG = reg;
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG8;
+ reg &= ~(1 << 29);
+ P_PIN_MUX_REG8 = reg;
+
+ reg = P_PIN_MUX_REG8;
+ reg |= (1 << 30); // enable PWM_F
+ P_PIN_MUX_REG8 = reg;
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+ case pwm_f:
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ case pwm_ao_a:
+ P_AO_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_ao_a);
+ pwm_init(pwm_f);
+ serial_puts("set vdd cpu_a to ");
+ serial_put_dec(CONFIG_VCCKA_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_a, CONFIG_VCCKA_INIT_VOLTAGE);
+
+ serial_puts("set vdd cpu_b to ");
+ serial_put_dec(CONFIG_VCCKB_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_f, CONFIG_VCCKB_INIT_VOLTAGE);
+
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxl_p401_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxl_p401_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..9e6a648
--- /dev/null
+++ b/board/amlogic/gxl_p401_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,255 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+ DVFS(1200000000, 1020+50),
+ DVFS(1512000000, 1110+30),
+};
+struct scpi_opp_entry vlittle_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+};
+
+
+
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#undef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_PWM_A
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#define P_AO_PWM_PWM_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define P_PIN_MUX_AO_REG (*((volatile unsigned *)(0xc8100000 + (0x5 << 2))))
+#define P_PIN_MUX_REG8 (*((volatile unsigned *)(0xda834400 + (0x34 << 2))))
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_ao_a:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_AO_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_AO_REG;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 7);
+ P_PIN_MUX_AO_REG = reg;
+
+ reg = P_PIN_MUX_AO_REG;
+ reg |= (1 << 22); // enable PWM_AO_A
+ P_PIN_MUX_AO_REG = reg;
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG8;
+ reg &= ~(1 << 29);
+ P_PIN_MUX_REG8 = reg;
+
+ reg = P_PIN_MUX_REG8;
+ reg |= (1 << 30); // enable PWM_F
+ P_PIN_MUX_REG8 = reg;
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+int dvfs_get_voltage(unsigned int domain)
+{
+ int i = 0;
+ unsigned int reg_val = 0x040018;
+
+ if (domain == 0)
+ reg_val = P_AO_PWM_PWM_A;
+
+ if (domain == 1)
+ reg_val = P_PWM_PWM_F;
+
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+ if (!init_flag) {
+ pwm_init(pwm_f);
+ pwm_init(pwm_ao_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage(domain);
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (domain == 0) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (domain == 1) {
+ if (pwm_voltage_table[to][1] >= vlittle_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ if (domain == 0)
+ P_AO_PWM_PWM_A = pwm_voltage_table[to][0];
+ if (domain == 1)
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ if (domain == 0)
+ P_AO_PWM_PWM_A = pwm_voltage_table[cur][0];
+ if (domain == 1)
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ if (domain == 0)
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+ if (domain == 1)
+ cnt = ARRAY_SIZE(vlittle_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ if (domain == 0)
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ if (domain == 1)
+ memcpy(&buf_opp.opp[0], vlittle_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/gxl_p401_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxl_p401_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..3417e6d
--- /dev/null
+++ b/board/amlogic/gxl_p401_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,285 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+
+extern int pwm_voltage_table[31][2];
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+#define P_PWM_PWM_AO_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define ON 1
+#define OFF 0
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_a:
+ uart_puts("set vdd_cpu a to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_AO_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_f:
+ uart_puts("set vdd_cpu a to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+/*GPIOH_3*/
+static void hdmi_5v_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* VCC5V ON GPIOH_3 output mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 0);
+ } else {
+ /* VCC5V OFF GPIOH_3 input mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 1 << 23);
+ }
+}
+/*GPIODV_25*/
+static void vcck_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* vddcpu_a*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 1<<20);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_a, CONFIG_VCCKA_INIT_VOLTAGE);
+
+ /* vddcpu_b*/
+ aml_update_bits(PREG_PAD_GPIO3_EN_N, 1 << 28, 0);
+ aml_update_bits(PREG_PAD_GPIO3_O, 1 << 28, 1<<28);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_f, CONFIG_VCCKB_INIT_VOLTAGE);
+ } else {
+ /* vddcpu_a*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 0);
+
+ /* vddcpu_b*/
+ aml_update_bits(PREG_PAD_GPIO3_EN_N, 1 << 28, 0);
+ aml_update_bits(PREG_PAD_GPIO3_O, 1 << 28, 0);
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+ hdmi_5v_ctrl(OFF);
+ vcck_ctrl(OFF);
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_SLEEP_VOLTAGE); // reduce power
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ vcck_ctrl(ON);
+ hdmi_5v_ctrl(ON);
+}
+
+static void power_off_at_24M(void)
+{
+ /* LED GPIOAO_9*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 9, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 25, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 9, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 25, 1 << 25);
+
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC|ETH_PHY_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_2;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+
+ p->gpio_info_count = ++i;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned int ret;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ ret = remote_detect_key();
+ if (ret == 1)
+ exit_reason = REMOTE_WAKEUP;
+ if (ret == 2)
+ exit_reason = REMOTE_CUS_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<2)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
+
diff --git a/board/amlogic/gxl_p401_v1/firmware/timing.c b/board/amlogic/gxl_p401_v1/firmware/timing.c
new file mode 100644
index 0000000..fbc35f5
--- /dev/null
+++ b/board/amlogic/gxl_p401_v1/firmware/timing.c
@@ -0,0 +1,571 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_40OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_34OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (9),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = 9,//12,//(23), //6 7 8 9 10 11 ok ,bit0-3 max is 15 ,why use 15 is bad 2016_11_10 jiaxing ,test should change with ddr frequency ?
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = 6,// (6),0
+ .cfg_ddr_wtr = (6+2),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (12),//12-17
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (168),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (39-2),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = 9,//9,// (4),//rank0 rank1 turn aroud time jiaxing modify should big for 2rank lpddr3
+ .cfg_ddr_cksre = 12,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 12,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (100),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (12),
+ .cfg_ddr_zqcsi = (1000),
+ // .cfg_ddr_rpab = (17),
+ // .cfg_ddr_rppb = (15),
+ // .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ // .cfg_ddr_tdqsckmax = (5),
+ // .cfg_ddr_tckesr = (12),
+ // .cfg_ddr_tdpd = (500),
+ // .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x5aa59, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x3f94f, //PUB ZQ1PR//0x3f95d, 0x4f95d,
+ .t_pub_zq2pr = 0x3f94f, //PUB ZQ2PR//0x3f95d, 0x4f95d,
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0,
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCKA_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/gxl_p401_v1/gxl_p401_v1.c b/board/amlogic/gxl_p401_v1/gxl_p401_v1.c
new file mode 100644
index 0000000..b018ebd
--- /dev/null
+++ b/board/amlogic/gxl_p401_v1/gxl_p401_v1.c
@@ -0,0 +1,577 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+#ifdef CONFIG_INTERNAL_PHY
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+#else
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ //setup ethernet clk need calibrate to configre
+ setbits_le32(P_PERIPHS_PIN_MUX_4, 0xfffc00);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rgmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+ /* hardware reset ethernet phy : gpioz14 connect phyreset pin*/
+ clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 14);
+ clrbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+ udelay(10000);
+ setbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+}
+#endif
+
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+#ifdef CONFIG_INTERNAL_PHY
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+#else
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RGMII);
+#endif
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ } else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 3
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23);
+ clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23);
+}
+#endif
+
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 220*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 != readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24));
+ //set output 1
+ setbits_le32(PREG_PAD_GPIO0_O, (1 << 24));
+
+ /*Power on GPIOAO_2 for VCC_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) {
+ setenv("maxcpus","4");
+ }
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXM) {
+ setenv("maxcpus","8");
+ }
+
+ /* load uboot pq value */
+ vpp_pq_load();
+
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
+
diff --git a/board/amlogic/gxl_s905x_p0/Kconfig b/board/amlogic/gxl_s905x_p0/Kconfig
new file mode 100644
index 0000000..576e8ab
--- /dev/null
+++ b/board/amlogic/gxl_s905x_p0/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxl_s905x_p0"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxl_s905x_p0"
+
+endif
diff --git a/board/amlogic/gxl_s905x_p0/Makefile b/board/amlogic/gxl_s905x_p0/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxl_s905x_p0/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxl_s905x_p0/aml-user-key.sig b/board/amlogic/gxl_s905x_p0/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/gxl_s905x_p0/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxl_s905x_p0/eth_setup.c b/board/amlogic/gxl_s905x_p0/eth_setup.c
new file mode 100644
index 0000000..33b5db1
--- /dev/null
+++ b/board/amlogic/gxl_s905x_p0/eth_setup.c
@@ -0,0 +1,50 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxl_s905x_p0/firmware/board_init.c b/board/amlogic/gxl_s905x_p0/firmware/board_init.c
new file mode 100644
index 0000000..22c36d1
--- /dev/null
+++ b/board/amlogic/gxl_s905x_p0/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxl_s905x_p0/firmware/power.c b/board/amlogic/gxl_s905x_p0/firmware/power.c
new file mode 100644
index 0000000..fce6e3c
--- /dev/null
+++ b/board/amlogic/gxl_s905x_p0/firmware/power.c
@@ -0,0 +1,185 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5);
+ reg |= (1 << 11); // enable PWM_B
+ P_PIN_MUX_REG2 = reg;
+ break;
+
+ case pwm_d:
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_d);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxl_s905x_p0/firmware/scp_task/dvfs_board.c b/board/amlogic/gxl_s905x_p0/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..f15c3e4
--- /dev/null
+++ b/board/amlogic/gxl_s905x_p0/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,171 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+ DVFS(1200000000, 1020+50),
+ DVFS(1512000000, 1110+30),
+};
+
+
+
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_D;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_D = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/gxl_s905x_p0/firmware/scp_task/dvfs_board.h b/board/amlogic/gxl_s905x_p0/firmware/scp_task/dvfs_board.h
new file mode 100644
index 0000000..ceede58
--- /dev/null
+++ b/board/amlogic/gxl_s905x_p0/firmware/scp_task/dvfs_board.h
@@ -0,0 +1,3 @@
+#ifndef __DVFS_BOARD_H__
+extern int pwm_voltage_table[31][2];
+#endif
diff --git a/board/amlogic/gxl_s905x_p0/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxl_s905x_p0/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..6e75686
--- /dev/null
+++ b/board/amlogic/gxl_s905x_p0/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,287 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "dvfs_board.h"
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB \
+ (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD \
+ (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+#define ON 1
+#define OFF 0
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+static struct pwr_op *g_pwr_op;
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage)
+ break;
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table))
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+
+ switch (id) {
+ case pwm_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+/*GPIOH_3*/
+static void hdmi_5v_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* VCC5V ON GPIOH_3 output mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 0);
+ } else {
+ /* VCC5V OFF GPIOH_3 input mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 1 << 23);
+ }
+}
+/*GPIODV_25*/
+static void vcck_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 1 << 25);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_d, CONFIG_VCCK_INIT_VOLTAGE);
+ } else {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 0);
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+ hdmi_5v_ctrl(OFF);
+ vcck_ctrl(OFF);
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_SLEEP_VOLTAGE);
+ /* reduce power */
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ vcck_ctrl(ON);
+ hdmi_5v_ctrl(ON);
+}
+
+static void power_off_at_24M(void)
+{
+ /* LED GPIODV_24*/
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ if (g_pwr_op->exit_reason != 4) {
+ /* bluetooth wakeup */
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 1 << 24);
+ }
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_2;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_18;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(10, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned int ret;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1) {
+ cec_node_init();
+ }
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ ret = remote_detect_key();
+ if (ret == 1)
+ exit_reason = REMOTE_WAKEUP;
+ if (ret == 2)
+ exit_reason = REMOTE_CUS_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<2)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 18))
+ && (readl(PREG_PAD_GPIO4_O) & (0x01 << 17))
+ && !(readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 17)))
+ exit_reason = BT_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+ pwr_op->exit_reason = 0;
+ g_pwr_op = pwr_op;
+}
+
diff --git a/board/amlogic/gxl_s905x_p0/firmware/timing.c b/board/amlogic/gxl_s905x_p0/firmware/timing.c
new file mode 100644
index 0000000..a2f4892
--- /dev/null
+++ b/board/amlogic/gxl_s905x_p0/firmware/timing.c
@@ -0,0 +1,694 @@
+
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_120OHM 2
+#define LPDDR3_ODT_240OHM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_40OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_0OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_34OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+//#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+//#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CONFIG_SOC_VREF 1+ (50+((50*48)/(48+480/(6+1)))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF 1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#else
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#endif
+
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (9),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = 9,//12,//(23), //6 7 8 9 10 11 ok ,bit0-3 max is 15 ,why use 15 is bad 2016_11_10 jiaxing ,test should change with ddr frequency ?
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = 6,// (6),0
+ .cfg_ddr_wtr = (6+2),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (12),//12-17
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (168),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (39-2),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = 9,//9,// (4),//rank0 rank1 turn aroud time jiaxing modify should big for 2rank lpddr3
+ .cfg_ddr_cksre = 12,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 12,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (100),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (12),
+ .cfg_ddr_zqcsi = (1000),
+ // .cfg_ddr_rpab = (17),
+ // .cfg_ddr_rppb = (15),
+ // .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ // .cfg_ddr_tdqsckmax = (5),
+ // .cfg_ddr_tckesr = (12),
+ // .cfg_ddr_tdpd = (500),
+ // .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#if (CONFIG_LPDDR_REMAP_SET == LPDDR_DIE_ROW_COL_R14_C9)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#elif (CONFIG_LPDDR_REMAP_SET== LPDDR_DIE_ROW_COL_R13_C10)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#endif /*CONFIG_LPDDR_REMAP_SET*/
+#else
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+#endif /*CONFIG_DDR_TYPE_LPDDR3*/
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+//lpddr3
+ .t_pub_zq0pr = 0x0ca1c, //0x0ca1c, //PUB ZQ0PR //lpddr3
+ .t_pub_zq1pr = 0x1cf3c, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x1cf3c, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+/* 2layer board
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+*/
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+/* 4layer ddr4 */
+ .t_pub_zq0pr = 0x0995d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#else // ddr3 and auto
+/* p212 4layer board ddr3 */
+ .t_pub_zq0pr = 0x5d95d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x5d95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x5d95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#endif
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+///*lpddr3
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune TAKE CARE LPDDR3 ADD/CMD DELAY
+ .t_pub_aclcdlr = 0,
+ .t_pub_acbdlr3 = 0x2020,//0, //CK0 delay fine tune b-3f //lpddr3 tianhe 2016-10-13
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+//2layer board DDR4
+ .t_pub_acbdlr0 = 0, //0x3f,
+ .t_pub_aclcdlr = 0, //0x28,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0, //0x10,// 0x10,//0xa, //cs add 22ohm 08 0ohm 0x10
+#else // ddr3 and auto
+//4layer ddr3
+ .t_pub_acbdlr0 = 0,
+ .t_pub_aclcdlr = 0,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0,//0xa, //cs
+#endif
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ //tianhe lpddr3 20161013
+ .wr_adj_per = {
+ [0] = 90, //aclcdlr
+ [1] = 100,
+ [2] = 120,
+ [3] = 110,
+ [4] = 120,
+ [5] = 105,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 110,
+ [3] = 110,
+ [4] = 110,
+ [5] = 110,},
+#else
+ /* P212 */
+ .wr_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=95,
+ [3]=95,
+ [4]=95,
+ [5]=95,
+ },
+ .rd_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=88,
+ [3]=95,
+ [4]=95,
+ [5]=100,
+ },
+#endif
+
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+ /* pll ssc setting:
+
+ .ddr_pll_ssc = 0x00120000, ppm1000 center SS, boot log show: Set ddr ssc: ppm1000
+ .ddr_pll_ssc = 0x00124000, ppm1000 up SS, boot log show: Set ddr ssc: ppm1000+
+ .ddr_pll_ssc = 0x00128000, ppm1000 down SS, boot log show: Set ddr ssc: ppm1000-
+
+ .ddr_pll_ssc = 0x00140000, ppm2000 center SS, boot log show: Set ddr ssc: ppm2000
+ .ddr_pll_ssc = 0x00144000, ppm2000 up SS, boot log show: Set ddr ssc: ppm2000+
+ .ddr_pll_ssc = 0x00148000, ppm2000 down SS, boot log show: Set ddr ssc: ppm2000-
+
+ .ddr_pll_ssc = 0x00160000, ppm3000 center SS, boot log show: Set ddr ssc: ppm3000
+ .ddr_pll_ssc = 0x00164000, ppm3000 up SS, boot log show: Set ddr ssc: ppm3000+
+ .ddr_pll_ssc = 0x00168000, ppm3000 down SS, boot log show: Set ddr ssc: ppm3000-
+ */
+ .ddr_pll_ssc = 0,
+};
diff --git a/board/amlogic/gxl_s905x_p0/gxl_s905x_p0.c b/board/amlogic/gxl_s905x_p0/gxl_s905x_p0.c
new file mode 100644
index 0000000..e46e589
--- /dev/null
+++ b/board/amlogic/gxl_s905x_p0/gxl_s905x_p0.c
@@ -0,0 +1,641 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+#include <asm/arch/mailbox.h>
+#ifdef DTB_BIND_KERNEL
+#include "storage.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ } else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+ __maybe_unused struct mmc *mmc;
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+#if defined(CONFIG_ENV_IS_NOWHERE) && defined(CONFIG_AML_SD_EMMC)
+ /* try emmc here. */
+ mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ if (!mmc)
+ printf("%s() %d: No MMC found\n", __func__, __LINE__);
+ else if (mmc_init(mmc))
+ printf("%s() %d: MMC init failed\n", __func__, __LINE__);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23);
+ clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23);
+}
+#endif
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24));
+ //set output 1
+ setbits_le32(PREG_PAD_GPIO0_O, (1 << 24));
+
+ /*Power on GPIOAO_2 for VCC_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+#define SAMPLE_BIT_MASK 0xfff
+#define NUM 50
+#define BASE_CH7 1843
+#define P_SAR_ADC_REG0 (volatile unsigned int *)0xc1108680
+#define P_SAR_ADC_CHAN_LIST (volatile unsigned int *)0xc1108684
+#define P_SAR_ADC_REG3 (volatile unsigned int *)0xc110868c
+#define P_SAR_ADC_FIFO_RD (volatile unsigned int *)0xc1108698
+#define P_SAR_ADC_DETECT_IDLE_SW (volatile unsigned int *)0xc11086a4
+#define P_SAR_ADC_REG13 (volatile unsigned int *)0xc11086b4
+#if 0
+#define dbgv(fmt, ...) printf(fmt, ##__VA_ARGS__)
+#else
+#define dbgv(fmt, ...)
+#endif
+void quicksort1(unsigned int a[], int numsize)
+{
+ int i = 0, j = numsize-1;
+ int val = a[0];
+ if (numsize > 1) {
+ while (i < j) {
+ for (; j > i; j--)
+ if (a[j] < val) {
+ a[i] = a[j];
+ break;
+ }
+ for (; i < j; i++)
+ if (a[i] > val) {
+ a[j] = a[i];
+ break;
+ }
+ }
+ a[i] = val;
+ quicksort1(a, i);
+ quicksort1(a+i+1, numsize-1-i);
+}
+}
+int check_vref(void)
+{
+ int i,count;
+ unsigned int value[50];
+ unsigned int value7=0;
+ unsigned int bak, bak_reg3;
+ unsigned int vref_efuse = (readl(SEC_AO_SEC_SD_CFG12)>>19)&(0x1f);
+
+ if (!vref_efuse) {
+ dbgv("This chip has no FT vref, no need to check, PASS\n");
+ return 0;
+ }
+ //run_command("md 0xc1108680 0x10", 0);
+ dbgv("SEC_AO_SEC_SD_CFG12: 0x%x\n",readl(SEC_AO_SEC_SD_CFG12));
+ dbgv("vref_efuse: %d\n",vref_efuse);
+
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ bak = (readl(P_SAR_ADC_REG13)>>8)&0x3f; /*back up SAR_ADC_REG13[13:8]*/
+ writel((readl(P_SAR_ADC_REG13)&(~(0x3f<<8)))|(vref_efuse<<9), P_SAR_ADC_REG13);
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ writel(0x00000007, P_SAR_ADC_CHAN_LIST);/*ch7*/
+ //writel(0xc000c|(0x7<<23)|(0x7<<7), P_SAR_ADC_DETECT_IDLE_SW);/*channel 7*/
+ bak_reg3 = readl(P_SAR_ADC_REG3);
+ writel((readl(P_SAR_ADC_REG3)&(~(0x7<<23)))|(0x2<<23), P_SAR_ADC_REG3);/*AVDD18/2*/
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ //run_command("md 0xc1108680 0x10", 0);
+ for (i=0;i<NUM;i++) {
+ writel((readl(P_SAR_ADC_REG0)&(~(1<<0))), P_SAR_ADC_REG0);
+ writel((readl(P_SAR_ADC_REG0)|(1<<0)), P_SAR_ADC_REG0);
+ writel((readl(P_SAR_ADC_REG0)|(1<<2)), P_SAR_ADC_REG0);/*start sample*/
+ count = 0;
+ do {
+ udelay(20);
+ count++;
+ } while ((readl(P_SAR_ADC_REG0) & (0x7<<28))
+ && (count < 100));/*finish sample?*/
+ if (count == 100) {
+ printf("%s : ch7 wait finish sample timeout!\n",__func__);
+ return -1;
+ }
+ value[i] = readl(P_SAR_ADC_FIFO_RD); /*read saradc*/
+ if (((value[i]>>12) & 0x7) == 0x7)
+ value[i] = value[i]&SAMPLE_BIT_MASK;
+ else {
+ printf("%s : not ch7! sample err!\n",__func__);
+ return -1;
+ }
+ }
+ quicksort1(value, NUM);
+ for (i = 0; i < NUM; i++)
+ dbgv("%d ", value[i]);
+ dbgv("\n");
+ for (i = 2; i < NUM-2; i++)
+ value7 += value[i];
+ value7 = value7/(NUM-4);
+ dbgv("the average ch7 adc=%d\n", value7);
+ dbgv("vref_efuse: %d\n",vref_efuse);
+ if ((value7 < (BASE_CH7*94/100)) || (value7 > (BASE_CH7*106/100))) { //1843
+ printf("the average ch7 : %d out of range: %d ~ %d\n",
+ value7, (BASE_CH7*94/100), (BASE_CH7*106/100));
+ printf("replace FT vref...\n");
+ thermal_calibration(4, bak>>1); /*[13:9]*/
+ }
+ /*write back SAR_ADC_REG13[13:8]*/
+ writel(((readl(P_SAR_ADC_REG13))&(~(0x3f<<8)))|
+ ((bak & 0x3f)<<8),
+ P_SAR_ADC_REG13);
+ writel(bak_reg3, P_SAR_ADC_REG3);
+ dbgv("P_SAR_ADC_REG13: 0x%x\n",readl(P_SAR_ADC_REG13));
+ dbgv("SEC_AO_SEC_SD_CFG12: 0x%x\n",readl(SEC_AO_SEC_SD_CFG12));
+ //run_command("md 0xc1108680 0x10", 0);
+ return 0;
+}
+
+int board_late_init(void){
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+#ifndef DTB_BIND_KERNEL
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+#elif defined(CONFIG_DTB_MEM_ADDR)
+ {
+ char cmd[128];
+ int ret;
+ if (!getenv("dtb_mem_addr")) {
+ sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
+ run_command(cmd, 0);
+ }
+ sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
+ ret = run_command(cmd, 0);
+ if (ret) {
+ printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
+ }
+ }
+#endif// #ifndef DTB_BIND_KERNEL
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ ret = check_vref();
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) {
+ setenv("maxcpus","4");
+ }
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int ddr_size=0;
+ char loc_name[64] = {0};
+ int i;
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+ switch (ddr_size) {
+ case 0x80000000:
+ strcpy(loc_name, "gxl_p212_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "gxl_p212_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "gxl_p212_512m\0");
+ break;
+ default:
+ //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "gxl_p212_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/gxl_s905x_p0/lcd.c b/board/amlogic/gxl_s905x_p0/lcd.c
new file mode 100644
index 0000000..24dae0f
--- /dev/null
+++ b/board/amlogic/gxl_s905x_p0/lcd.c
@@ -0,0 +1,236 @@
+/*
+ * AMLOGIC TV LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {
+ "lcd_0",LCD_TTL,6,
+ /* basic timing */
+ 1280,720,1650,750,40,220,1,5,20,1,
+ /* clk_attr */
+ 0,0,1,74250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* ttl_attr */
+ 0,1,1,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ 0xff,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+};
+
+//**** Special parameters just for ttl ***//
+static struct ttl_config_s lcd_ttl_config = {
+ .clk_pol = 0,
+ .sync_valid = (1 << 1) | (1 << 0), /* [1]DE, [0]hvsync */
+ .swap_ctrl = (0 << 1) | (0 << 0), /* [1]rb swap, [0]bit swap */
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .ttl_config = &lcd_ttl_config,
+ .lvds_config = &lcd_lvds_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{3, 0x000002a0}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{1, 0xfa030000}, {2, 0xf9fe0409}, {3, 0x00000001}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+#define LCD_EXTERN_NAME "ext_default"
+#define LCD_EXTERN_CMD_SIZE 9
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_config_s ext_config_dtf = {
+ .lcd_ext_key_valid = 0,
+ .index = LCD_EXTERN_INDEX_INVALID,
+ .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_D, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = LCD_EXTERN_CMD_SIZE,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{2, 0x00000800}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{1, 0x00000400}, {2, 0x00000020}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_config_dtf.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_config_dtf.gpio_name[j], "invalid");
+
+ strcpy(ext_config_dtf.name, LCD_EXTERN_NAME);
+#endif
+}
diff --git a/board/amlogic/gxl_skt_v1/Kconfig b/board/amlogic/gxl_skt_v1/Kconfig
new file mode 100644
index 0000000..15a1d24
--- /dev/null
+++ b/board/amlogic/gxl_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxl_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxl_skt_v1"
+
+endif
diff --git a/board/amlogic/gxl_skt_v1/Makefile b/board/amlogic/gxl_skt_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxl_skt_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxl_skt_v1/aml-user-key-v3.sig b/board/amlogic/gxl_skt_v1/aml-user-key-v3.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/gxl_skt_v1/aml-user-key-v3.sig
Binary files differ
diff --git a/board/amlogic/gxl_skt_v1/aml-user-key.sig b/board/amlogic/gxl_skt_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/gxl_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxl_skt_v1/eth_setup.c b/board/amlogic/gxl_skt_v1/eth_setup.c
new file mode 100644
index 0000000..f7aff48
--- /dev/null
+++ b/board/amlogic/gxl_skt_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/gxb_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxl_skt_v1/firmware/board_init.c b/board/amlogic/gxl_skt_v1/firmware/board_init.c
new file mode 100644
index 0000000..107f13e
--- /dev/null
+++ b/board/amlogic/gxl_skt_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxl_skt_v1/firmware/power.c b/board/amlogic/gxl_skt_v1/firmware/power.c
new file mode 100644
index 0000000..57c08b6
--- /dev/null
+++ b/board/amlogic/gxl_skt_v1/firmware/power.c
@@ -0,0 +1,185 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5);
+ reg |= (1 << 11); // enable PWM_B
+ P_PIN_MUX_REG2 = reg;
+ break;
+
+ case pwm_d:
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 11);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg |= (1 << 12); // enable PWM_D
+ P_PIN_MUX_REG2 = reg;
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_d);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxl_skt_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxl_skt_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..c057658
--- /dev/null
+++ b/board/amlogic/gxl_skt_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,170 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+ DVFS(1200000000, 1020+50),
+};
+
+
+
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5); // clear PWM_VS
+ reg |= (1 << 11); // enable PWM_B
+ P_PIN_MUX_REG2 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_B;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_B = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/gxl_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxl_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..c647add6
--- /dev/null
+++ b/board/amlogic/gxl_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,269 @@
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+
+extern int pwm_voltage_table[31][2];
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+#define ON 1
+#define OFF 0
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+/*GPIOH_3*/
+static void hdmi_5v_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* VCC5V ON GPIOH_3 output mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 0);
+ } else {
+ /* VCC5V OFF GPIOH_3 input mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 1 << 23);
+ }
+}
+/*GPIODV_25*/
+static void vcck_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 1 << 25);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_b, CONFIG_VCCK_INIT_VOLTAGE);
+ } else {
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 25, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 25, 0);
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+ hdmi_5v_ctrl(OFF);
+ vcck_ctrl(OFF);
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_SLEEP_VOLTAGE); // reduce power
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_INIT_VOLTAGE);
+ vcck_ctrl(ON);
+ hdmi_5v_ctrl(ON);
+}
+
+static void power_off_at_24M(void)
+{
+ /* LED GPIODV_24*/
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 0);
+}
+static void power_on_at_24M(void)
+{
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 24, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 24, 1 << 24);
+
+}
+
+static void power_off_at_32k(void)
+{
+}
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ p->gpio_info_count = 0;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[2]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_2;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_18;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<2)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 18)))
+ exit_reason = BT_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/gxl_skt_v1/firmware/timing.c b/board/amlogic/gxl_skt_v1/firmware/timing.c
new file mode 100644
index 0000000..295d172
--- /dev/null
+++ b/board/amlogic/gxl_skt_v1/firmware/timing.c
@@ -0,0 +1,574 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_60OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (9),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = 9,//12,//(23), //6 7 8 9 10 11 ok ,bit0-3 max is 15 ,why use 15 is bad 2016_11_10 jiaxing ,test should change with ddr frequency ?
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = 6,// (6),0
+ .cfg_ddr_wtr = (6+2),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (12),//12-17
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (168),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (39-2),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = 9,//9,// (4),//rank0 rank1 turn aroud time jiaxing modify should big for 2rank lpddr3
+ .cfg_ddr_cksre = 12,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 12,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (100),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (12),
+ .cfg_ddr_zqcsi = (1000),
+ // .cfg_ddr_rpab = (17),
+ // .cfg_ddr_rppb = (15),
+ // .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ // .cfg_ddr_tdqsckmax = (5),
+ // .cfg_ddr_tckesr = (12),
+ // .cfg_ddr_tdpd = (500),
+ // .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x5995d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0x10,
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/gxl_skt_v1/gxl_skt_v1.c b/board/amlogic/gxl_skt_v1/gxl_skt_v1.c
new file mode 100644
index 0000000..6c0aa06
--- /dev/null
+++ b/board/amlogic/gxl_skt_v1/gxl_skt_v1.c
@@ -0,0 +1,576 @@
+
+/*
+ * board/amlogic/gxb_skt_v1/gxb_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/board_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#ifdef CONFIG_AML_SPIFC
+#include <amlogic/spifc.h>
+#endif
+#ifdef CONFIG_AML_SPICC
+#include <amlogic/spicc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+#ifdef CONFIG_PXP_EMULATOR
+ *P_PREG_ETH_REG3 = 0x642000b0;
+#else
+ *P_PREG_ETH_REG3 = 0xe409087f;
+#endif
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 2
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23);
+ clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23);
+}
+#endif
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_11: NOR_D:reg7[13], clr reg7[4] + reg7[15]
+ * BOOT_12: NOR_Q:reg7[12], clr reg7[3]
+ * BOOT_13: NOR_C:reg7[11], clr reg7[2]
+ * BOOT_15: NOR_CS:reg7[10],clr reg7[0] + reg7[28]
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {97/*PIN_BOOT_15*/};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_7);
+ val &= ~((1<<13)|(1<<12)|(1<<11)|(1<<10));
+ if (enable) {
+ val |= (1<<13)|(1<<12)|(1<<11);
+ val &= ~((1<<28)|(1<<15)|(1<<4)|(1<<3)|(1<<2)|(1<<0));
+ }
+ writel(val, P_PERIPHS_PIN_MUX_7);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xc1108c80,
+ .mem_map = 0xcc000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+#ifdef CONFIG_AML_SPICC
+/* generic config in arch gpio/clock.c */
+extern int spicc_clk_enable(bool enable);
+extern int spicc_pinctrl_enable(bool enable);
+
+static const struct spicc_platdata spicc_platdata = {
+ .compatible = "amlogic,meson-txl-spicc",
+ .reg = (void __iomem *)0xc1108d80,
+ .clk_rate = 166666666,
+ .clk_enable = spicc_clk_enable,
+ .pinctrl_enable = spicc_pinctrl_enable,
+ /* case one slave without cs: {"no_cs", 0} */
+ .cs_gpio_names = {"GPIOX_10", 0},
+};
+
+U_BOOT_DEVICE(spicc) = {
+ .name = "spicc",
+ .platdata = &spicc_platdata,
+};
+#endif /* CONFIG_AML_SPICC */
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24));
+ //set output 1
+ setbits_le32(PREG_PAD_GPIO0_O, (1 << 24));
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+#define S805X_SKT_BOARD_ID 1
+#define S905X_SKT_BOARD_ID 12
+int checkhw(char * name)
+{
+ unsigned int board_id=0;
+ char loc_name[64] = {0};
+ board_id = get_board_id();
+ switch (board_id) {
+ case S805X_SKT_BOARD_ID:
+ strcpy(loc_name, "gxl_s805x_skt\0");
+ break;
+ case S905X_SKT_BOARD_ID:
+ strcpy(loc_name, "gxl_s905x_skt\0");
+ break;
+ default:
+ //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "gxl_skt_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/gxm_q200_v1/Kconfig b/board/amlogic/gxm_q200_v1/Kconfig
new file mode 100644
index 0000000..0794d99
--- /dev/null
+++ b/board/amlogic/gxm_q200_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxm_q200_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxm_q200_v1"
+
+endif
diff --git a/board/amlogic/gxm_q200_v1/Makefile b/board/amlogic/gxm_q200_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxm_q200_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxm_q200_v1/aml-user-key.sig b/board/amlogic/gxm_q200_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/gxm_q200_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxm_q200_v1/eth_setup.c b/board/amlogic/gxm_q200_v1/eth_setup.c
new file mode 100644
index 0000000..33b5db1
--- /dev/null
+++ b/board/amlogic/gxm_q200_v1/eth_setup.c
@@ -0,0 +1,50 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxm_q200_v1/firmware/board_init.c b/board/amlogic/gxm_q200_v1/firmware/board_init.c
new file mode 100644
index 0000000..22c36d1
--- /dev/null
+++ b/board/amlogic/gxm_q200_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxm_q200_v1/firmware/power.c b/board/amlogic/gxm_q200_v1/firmware/power.c
new file mode 100644
index 0000000..0bf4c75
--- /dev/null
+++ b/board/amlogic/gxm_q200_v1/firmware/power.c
@@ -0,0 +1,224 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#define P_PIN_MUX_REG8 (*((volatile unsigned *)(0xda834400 + (0x34 << 2))))
+#define P_PIN_MUX_AO_REG (*((volatile unsigned *)(0xc8100000 + (0x5 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#undef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_PWM_A
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#define P_AO_PWM_PWM_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5);
+ reg |= (1 << 11); // enable PWM_B
+ P_PIN_MUX_REG2 = reg;
+ break;
+
+ case pwm_ao_a:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_AO_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_AO_REG;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 7);
+ P_PIN_MUX_AO_REG = reg;
+
+ reg = P_PIN_MUX_AO_REG;
+ reg |= (1 << 22); // enable PWM_AO_A
+ P_PIN_MUX_AO_REG = reg;
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG8;
+ reg &= ~(1 << 29);
+ P_PIN_MUX_REG8 = reg;
+
+ reg = P_PIN_MUX_REG8;
+ reg |= (1 << 30); // enable PWM_F
+ P_PIN_MUX_REG8 = reg;
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+ case pwm_f:
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ case pwm_ao_a:
+ P_AO_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_ao_a);
+ pwm_init(pwm_f);
+ serial_puts("set vdd cpu_a to ");
+ serial_put_dec(CONFIG_VCCKA_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_a, CONFIG_VCCKA_INIT_VOLTAGE);
+
+ serial_puts("set vdd cpu_b to ");
+ serial_put_dec(CONFIG_VCCKB_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_f, CONFIG_VCCKB_INIT_VOLTAGE);
+
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxm_q200_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxm_q200_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..9e6a648
--- /dev/null
+++ b/board/amlogic/gxm_q200_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,255 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+ DVFS(1200000000, 1020+50),
+ DVFS(1512000000, 1110+30),
+};
+struct scpi_opp_entry vlittle_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+};
+
+
+
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#undef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_PWM_A
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#define P_AO_PWM_PWM_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define P_PIN_MUX_AO_REG (*((volatile unsigned *)(0xc8100000 + (0x5 << 2))))
+#define P_PIN_MUX_REG8 (*((volatile unsigned *)(0xda834400 + (0x34 << 2))))
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_ao_a:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_AO_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_AO_REG;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 7);
+ P_PIN_MUX_AO_REG = reg;
+
+ reg = P_PIN_MUX_AO_REG;
+ reg |= (1 << 22); // enable PWM_AO_A
+ P_PIN_MUX_AO_REG = reg;
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG8;
+ reg &= ~(1 << 29);
+ P_PIN_MUX_REG8 = reg;
+
+ reg = P_PIN_MUX_REG8;
+ reg |= (1 << 30); // enable PWM_F
+ P_PIN_MUX_REG8 = reg;
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+int dvfs_get_voltage(unsigned int domain)
+{
+ int i = 0;
+ unsigned int reg_val = 0x040018;
+
+ if (domain == 0)
+ reg_val = P_AO_PWM_PWM_A;
+
+ if (domain == 1)
+ reg_val = P_PWM_PWM_F;
+
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+ if (!init_flag) {
+ pwm_init(pwm_f);
+ pwm_init(pwm_ao_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage(domain);
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (domain == 0) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (domain == 1) {
+ if (pwm_voltage_table[to][1] >= vlittle_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ if (domain == 0)
+ P_AO_PWM_PWM_A = pwm_voltage_table[to][0];
+ if (domain == 1)
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ if (domain == 0)
+ P_AO_PWM_PWM_A = pwm_voltage_table[cur][0];
+ if (domain == 1)
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ if (domain == 0)
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+ if (domain == 1)
+ cnt = ARRAY_SIZE(vlittle_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ if (domain == 0)
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ if (domain == 1)
+ memcpy(&buf_opp.opp[0], vlittle_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/gxm_q200_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxm_q200_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..3417e6d
--- /dev/null
+++ b/board/amlogic/gxm_q200_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,285 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+
+extern int pwm_voltage_table[31][2];
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+#define P_PWM_PWM_AO_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define ON 1
+#define OFF 0
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_a:
+ uart_puts("set vdd_cpu a to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_AO_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_f:
+ uart_puts("set vdd_cpu a to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+/*GPIOH_3*/
+static void hdmi_5v_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* VCC5V ON GPIOH_3 output mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 0);
+ } else {
+ /* VCC5V OFF GPIOH_3 input mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 1 << 23);
+ }
+}
+/*GPIODV_25*/
+static void vcck_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* vddcpu_a*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 1<<20);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_a, CONFIG_VCCKA_INIT_VOLTAGE);
+
+ /* vddcpu_b*/
+ aml_update_bits(PREG_PAD_GPIO3_EN_N, 1 << 28, 0);
+ aml_update_bits(PREG_PAD_GPIO3_O, 1 << 28, 1<<28);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_f, CONFIG_VCCKB_INIT_VOLTAGE);
+ } else {
+ /* vddcpu_a*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 0);
+
+ /* vddcpu_b*/
+ aml_update_bits(PREG_PAD_GPIO3_EN_N, 1 << 28, 0);
+ aml_update_bits(PREG_PAD_GPIO3_O, 1 << 28, 0);
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+ hdmi_5v_ctrl(OFF);
+ vcck_ctrl(OFF);
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_SLEEP_VOLTAGE); // reduce power
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ vcck_ctrl(ON);
+ hdmi_5v_ctrl(ON);
+}
+
+static void power_off_at_24M(void)
+{
+ /* LED GPIOAO_9*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 9, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 25, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 9, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 25, 1 << 25);
+
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC|ETH_PHY_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_2;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+
+ p->gpio_info_count = ++i;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned int ret;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ ret = remote_detect_key();
+ if (ret == 1)
+ exit_reason = REMOTE_WAKEUP;
+ if (ret == 2)
+ exit_reason = REMOTE_CUS_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<2)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
+
diff --git a/board/amlogic/gxm_q200_v1/firmware/timing.c b/board/amlogic/gxm_q200_v1/firmware/timing.c
new file mode 100644
index 0000000..fbc35f5
--- /dev/null
+++ b/board/amlogic/gxm_q200_v1/firmware/timing.c
@@ -0,0 +1,571 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_40OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_34OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (9),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = 9,//12,//(23), //6 7 8 9 10 11 ok ,bit0-3 max is 15 ,why use 15 is bad 2016_11_10 jiaxing ,test should change with ddr frequency ?
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = 6,// (6),0
+ .cfg_ddr_wtr = (6+2),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (12),//12-17
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (168),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (39-2),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = 9,//9,// (4),//rank0 rank1 turn aroud time jiaxing modify should big for 2rank lpddr3
+ .cfg_ddr_cksre = 12,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 12,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (100),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (12),
+ .cfg_ddr_zqcsi = (1000),
+ // .cfg_ddr_rpab = (17),
+ // .cfg_ddr_rppb = (15),
+ // .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ // .cfg_ddr_tdqsckmax = (5),
+ // .cfg_ddr_tckesr = (12),
+ // .cfg_ddr_tdpd = (500),
+ // .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x5aa59, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x3f94f, //PUB ZQ1PR//0x3f95d, 0x4f95d,
+ .t_pub_zq2pr = 0x3f94f, //PUB ZQ2PR//0x3f95d, 0x4f95d,
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0,
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCKA_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/gxm_q200_v1/gxm_q200_v1.c b/board/amlogic/gxm_q200_v1/gxm_q200_v1.c
new file mode 100644
index 0000000..3771ffe
--- /dev/null
+++ b/board/amlogic/gxm_q200_v1/gxm_q200_v1.c
@@ -0,0 +1,523 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+#ifdef CONFIG_INTERNAL_PHY
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+#else
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ //setup ethernet clk need calibrate to configre
+ setbits_le32(P_PERIPHS_PIN_MUX_4, 0xfffc00);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rgmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+ /* hardware reset ethernet phy : gpioz14 connect phyreset pin*/
+ clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 14);
+ clrbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+ udelay(10000);
+ setbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+}
+#endif
+
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+#ifdef CONFIG_INTERNAL_PHY
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+#else
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RGMII);
+#endif
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ } else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 3
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23);
+ clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23);
+}
+#endif
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24));
+ //set output 1
+ setbits_le32(PREG_PAD_GPIO0_O, (1 << 24));
+
+ /*Power on GPIOAO_2 for VCC_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) {
+ setenv("maxcpus","4");
+ setenv("device_product","p230");
+ }
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXM) {
+ setenv("maxcpus","8");
+ setenv("device_product","q200");
+ }
+
+ /* load uboot pq value */
+ vpp_pq_load();
+
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
+
diff --git a/board/amlogic/gxm_q200_v1/lcd.c b/board/amlogic/gxm_q200_v1/lcd.c
new file mode 100644
index 0000000..c738f2f
--- /dev/null
+++ b/board/amlogic/gxm_q200_v1/lcd.c
@@ -0,0 +1,254 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {
+ "lcd_0",LCD_TTL,6,
+ /* basic timing */
+ 1280,720,1650,750,40,220,1,5,20,1,
+ /* clk_attr */
+ 0,0,1,74250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* ttl_attr */
+ 0,1,1,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ 0xff,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+};
+
+//**** Special parameters just for ttl ***//
+static struct ttl_config_s lcd_ttl_config = {
+ .clk_pol = 0,
+ .sync_valid = (1 << 1) | (1 << 0), /* [1]DE, [0]hvsync */
+ .swap_ctrl = (0 << 1) | (0 << 0), /* [1]rb swap, [0]bit swap */
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TABLET,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .ttl_config = &lcd_ttl_config,
+ .lvds_config = &lcd_lvds_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 0,
+ .pinmux_set = {{3, 0x000002a0}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{1, 0xfa030000}, {2, 0xf9fe0409}, {3, 0x00000001}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_D, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinctrl_ver = 0,
+ .pinmux_set = {{2, 0x00000800}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{1, 0x00000400}, {2, 0x00000020}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/gxm_q201_v1/Kconfig b/board/amlogic/gxm_q201_v1/Kconfig
new file mode 100644
index 0000000..da35807
--- /dev/null
+++ b/board/amlogic/gxm_q201_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxm_q201_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxm_q201_v1"
+
+endif
diff --git a/board/amlogic/gxm_q201_v1/Makefile b/board/amlogic/gxm_q201_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxm_q201_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxm_q201_v1/aml-user-key.sig b/board/amlogic/gxm_q201_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/gxm_q201_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxm_q201_v1/eth_setup.c b/board/amlogic/gxm_q201_v1/eth_setup.c
new file mode 100644
index 0000000..33b5db1
--- /dev/null
+++ b/board/amlogic/gxm_q201_v1/eth_setup.c
@@ -0,0 +1,50 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxm_q201_v1/firmware/board_init.c b/board/amlogic/gxm_q201_v1/firmware/board_init.c
new file mode 100644
index 0000000..22c36d1
--- /dev/null
+++ b/board/amlogic/gxm_q201_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxm_q201_v1/firmware/power.c b/board/amlogic/gxm_q201_v1/firmware/power.c
new file mode 100644
index 0000000..0bf4c75
--- /dev/null
+++ b/board/amlogic/gxm_q201_v1/firmware/power.c
@@ -0,0 +1,224 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#define P_PIN_MUX_REG8 (*((volatile unsigned *)(0xda834400 + (0x34 << 2))))
+#define P_PIN_MUX_AO_REG (*((volatile unsigned *)(0xc8100000 + (0x5 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#undef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_PWM_A
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#define P_AO_PWM_PWM_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5);
+ reg |= (1 << 11); // enable PWM_B
+ P_PIN_MUX_REG2 = reg;
+ break;
+
+ case pwm_ao_a:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_AO_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_AO_REG;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 7);
+ P_PIN_MUX_AO_REG = reg;
+
+ reg = P_PIN_MUX_AO_REG;
+ reg |= (1 << 22); // enable PWM_AO_A
+ P_PIN_MUX_AO_REG = reg;
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG8;
+ reg &= ~(1 << 29);
+ P_PIN_MUX_REG8 = reg;
+
+ reg = P_PIN_MUX_REG8;
+ reg |= (1 << 30); // enable PWM_F
+ P_PIN_MUX_REG8 = reg;
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+ case pwm_f:
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ case pwm_ao_a:
+ P_AO_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_ao_a);
+ pwm_init(pwm_f);
+ serial_puts("set vdd cpu_a to ");
+ serial_put_dec(CONFIG_VCCKA_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_a, CONFIG_VCCKA_INIT_VOLTAGE);
+
+ serial_puts("set vdd cpu_b to ");
+ serial_put_dec(CONFIG_VCCKB_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_f, CONFIG_VCCKB_INIT_VOLTAGE);
+
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxm_q201_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxm_q201_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..9e6a648
--- /dev/null
+++ b/board/amlogic/gxm_q201_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,255 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+ DVFS(1200000000, 1020+50),
+ DVFS(1512000000, 1110+30),
+};
+struct scpi_opp_entry vlittle_dvfs_tbl[] = {
+ DVFS( 100000000, 860+50),
+ DVFS( 250000000, 860+50),
+ DVFS( 500000000, 860+50),
+ DVFS( 667000000, 900+50),
+ DVFS(1000000000, 940+50),
+};
+
+
+
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#undef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_PWM_A
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#define P_AO_PWM_PWM_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define P_PIN_MUX_AO_REG (*((volatile unsigned *)(0xc8100000 + (0x5 << 2))))
+#define P_PIN_MUX_REG8 (*((volatile unsigned *)(0xda834400 + (0x34 << 2))))
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_ao_a:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_AO_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_AO_REG;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 7);
+ P_PIN_MUX_AO_REG = reg;
+
+ reg = P_PIN_MUX_AO_REG;
+ reg |= (1 << 22); // enable PWM_AO_A
+ P_PIN_MUX_AO_REG = reg;
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG8;
+ reg &= ~(1 << 29);
+ P_PIN_MUX_REG8 = reg;
+
+ reg = P_PIN_MUX_REG8;
+ reg |= (1 << 30); // enable PWM_F
+ P_PIN_MUX_REG8 = reg;
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+int dvfs_get_voltage(unsigned int domain)
+{
+ int i = 0;
+ unsigned int reg_val = 0x040018;
+
+ if (domain == 0)
+ reg_val = P_AO_PWM_PWM_A;
+
+ if (domain == 1)
+ reg_val = P_PWM_PWM_F;
+
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+ if (!init_flag) {
+ pwm_init(pwm_f);
+ pwm_init(pwm_ao_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage(domain);
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (domain == 0) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (domain == 1) {
+ if (pwm_voltage_table[to][1] >= vlittle_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ if (domain == 0)
+ P_AO_PWM_PWM_A = pwm_voltage_table[to][0];
+ if (domain == 1)
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ if (domain == 0)
+ P_AO_PWM_PWM_A = pwm_voltage_table[cur][0];
+ if (domain == 1)
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ if (domain == 0)
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+ if (domain == 1)
+ cnt = ARRAY_SIZE(vlittle_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ if (domain == 0)
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ if (domain == 1)
+ memcpy(&buf_opp.opp[0], vlittle_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/gxm_q201_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxm_q201_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..abae990
--- /dev/null
+++ b/board/amlogic/gxm_q201_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,304 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+
+extern int pwm_voltage_table[31][2];
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+#define P_PWM_PWM_AO_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define ON 1
+#define OFF 0
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_a:
+ uart_puts("set vdd_cpu a to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_AO_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_f:
+ uart_puts("set vdd_cpu a to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+/*GPIOH_3*/
+static void hdmi_5v_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* VCC5V ON GPIOH_3 output mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 0);
+ } else {
+ /* VCC5V OFF GPIOH_3 input mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 1 << 23);
+ }
+}
+/*GPIODV_25*/
+static void vcck_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* vddcpu_a*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 1<<20);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_a, CONFIG_VCCKA_INIT_VOLTAGE);
+
+ /* vddcpu_b*/
+ aml_update_bits(PREG_PAD_GPIO3_EN_N, 1 << 28, 0);
+ aml_update_bits(PREG_PAD_GPIO3_O, 1 << 28, 1<<28);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_f, CONFIG_VCCKB_INIT_VOLTAGE);
+ } else {
+ /* vddcpu_a*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 0);
+
+ /* vddcpu_b*/
+ aml_update_bits(PREG_PAD_GPIO3_EN_N, 1 << 28, 0);
+ aml_update_bits(PREG_PAD_GPIO3_O, 1 << 28, 0);
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+ hdmi_5v_ctrl(OFF);
+ vcck_ctrl(OFF);
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_SLEEP_VOLTAGE); // reduce power
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ vcck_ctrl(ON);
+ hdmi_5v_ctrl(ON);
+}
+
+static void power_off_at_24M(void)
+{
+ /* LED GPIOAO_9*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 9, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 25, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 9, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 25, 1 << 25);
+
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+ p->gpio_info_count = 0;
+ p->status = RESPONSE_OK;
+ //val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC);
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_2;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+
+ //p->gpio_info_count = 1;
+ p->gpio_info_count = ++i;
+
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOX_18;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned int ret;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ ret = remote_detect_key();
+ if (ret == 1)
+ exit_reason = REMOTE_WAKEUP;
+ if (ret == 2)
+ exit_reason = REMOTE_CUS_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<2)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 18))
+ && (readl(PREG_PAD_GPIO4_O) & (0x01 << 17))
+ && !(readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 17)))
+ exit_reason = BT_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
+
diff --git a/board/amlogic/gxm_q201_v1/firmware/timing.c b/board/amlogic/gxm_q201_v1/firmware/timing.c
new file mode 100644
index 0000000..cba4e9a
--- /dev/null
+++ b/board/amlogic/gxm_q201_v1/firmware/timing.c
@@ -0,0 +1,648 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 20
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#define CFG_DDR4_DRV_RANK1 DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT_RANK1 DDR4_ODT_48OHM//DDR4_ODT_60OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#define CONFIG_SOC_VREF (1+ (50+((50*48)/(48+480/(2+1)))))// (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF (1+ (50+((50*34)/(34+48))))// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+#define CONFIG_DRAM_VREF_RANK1 750/12// 1+ (50+((50*37)/(37+60/1))) //50// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+//#define CONFIG_ZQ_VREF 715/15// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (9),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = 9,//12,//(23), //6 7 8 9 10 11 ok ,bit0-3 max is 15 ,why use 15 is bad 2016_11_10 jiaxing ,test should change with ddr frequency ?
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = 6,// (6),0
+ .cfg_ddr_wtr = (6+2),
+ .cfg_ddr_rp = (17),
+ .cfg_ddr_rcd = (15),
+ .cfg_ddr_ras = (34),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc = (51),
+ .cfg_ddr_mrd = (11),
+ .cfg_ddr_mod = (12),//12-17
+ .cfg_ddr_faw = (40),
+ .cfg_ddr_rfc = (168),
+ .cfg_ddr_wlmrd = (32),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (6),
+ .cfg_ddr_cke = 7,//(6),//need <=7
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (39-2),
+ .cfg_ddr_refi_mddr3 = (0),
+ .cfg_ddr_cl = (12),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (6),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (112),
+ .cfg_ddr_dqs = 9,//9,// (4),//rank0 rank1 turn aroud time jiaxing modify should big for 2rank lpddr3
+ .cfg_ddr_cksre = 12,// (12),//pctl need 2?
+ .cfg_ddr_cksrx = 12,// (12),//pctl need 2?
+ .cfg_ddr_zqcs = (100),
+ .cfg_ddr_zqcl = (288),
+ .cfg_ddr_xpdll = (12),
+ .cfg_ddr_zqcsi = (1000),
+ // .cfg_ddr_rpab = (17),
+ // .cfg_ddr_rppb = (15),
+ // .cfg_ddr_tdqsck = (3),//2500-5500ps if no gate training should (int+1)
+ // .cfg_ddr_tdqsckmax = (5),
+ // .cfg_ddr_tckesr = (12),
+ // .cfg_ddr_tdpd = (500),
+ // .cfg_ddr_taond_aofd = 2,
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#if (CONFIG_LPDDR_REMAP_SET == LPDDR_DIE_ROW_COL_R14_C9)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#elif (CONFIG_LPDDR_REMAP_SET== LPDDR_DIE_ROW_COL_R13_C10)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#endif /*CONFIG_LPDDR_REMAP_SET*/
+#else
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+#endif /*CONFIG_DDR_TYPE_LPDDR3*/
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR zqvref 0x13
+ //.t_pub_zq0pr = 0x5aa59, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ //.t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR//0x3f95d, 0x4f95d,
+ //.t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR//0x3f95d, 0x4f95d,
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ .t_pub_zq0pr = 0x0000bf59, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0002fc5d, //PUB ZQ1PR//0x3f95d, 0x4f95d,
+ .t_pub_zq2pr = 0x0002fc5d, //PUB ZQ2PR//0x3f95d, 0x4f95d,
+ //.t_pub_zq3pr = 0xf5f95d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0x28,
+ .t_pub_aclcdlr = 0x38,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0x18,//0xa, //cs
+ //.t_pub_acbdlr0 = 0x0,
+ //.t_pub_aclcdlr = 0x10,//0x18, ///1t ,if 2t can add some value
+ //.t_pub_acbdlr3 = 0x14,//0xa, //cs
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+
+
+ .t_pub_mr[1] = ( (0|(CFG_DDR4_DRV_RANK1<<1)|((CFG_DDR4_ODT_RANK1)<<8) |
+ (0<<7) |
+ (0 << 3 ))) ,//jiaxing
+ .t_pub_soc_vref_dram_vref_rank1 = ((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF_RANK1))<45)?(0):((((CONFIG_DRAM_VREF_RANK1))<61)?((((((CONFIG_DRAM_VREF_RANK1*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF_RANK1*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF_RANK1*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF_RANK1*1000-60000)/650)))))) ,//jiaxing
+
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 105,
+ [3] = 105,
+ [4] = 105,
+ [5] = 105,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 105,
+ [3] = 95,
+ [4] = 95,
+ [5] = 95,},
+ .wr_adj_per_rank1 = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 90,
+ [3] = 95,
+ [4] = 95,
+ [5] = 95,
+ },
+ .rd_adj_per_rank1 = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 95,
+ [3] = 95,
+ [4] = 95,
+ [5] = 95,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCKA_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/gxm_q201_v1/gxm_q201_v1.c b/board/amlogic/gxm_q201_v1/gxm_q201_v1.c
new file mode 100644
index 0000000..8ef9e36
--- /dev/null
+++ b/board/amlogic/gxm_q201_v1/gxm_q201_v1.c
@@ -0,0 +1,527 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ } else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 3
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23);
+ clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23);
+}
+#endif
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24));
+ //set output 1
+ setbits_le32(PREG_PAD_GPIO0_O, (1 << 24));
+
+ /*Power on GPIOAO_2 for VCC_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) {
+ setenv("maxcpus","4");
+ setenv("device_product","p231");
+ }
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXM) {
+ setenv("maxcpus","8");
+ setenv("device_product","q201");
+ }
+
+ /* load uboot pq value */
+ vpp_pq_load();
+
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int ddr_size=0;
+ char loc_name[64] = {0};
+ int i;
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXM) {
+ switch (ddr_size) {
+ case 0x80000000:
+ strcpy(loc_name, "gxm_q201_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "gxm_q201_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "gxm_q201_512m\0");
+ break;
+ default:
+ //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "gxm_q201_unsupport\0");
+ break;
+ }
+ }
+ else {
+ switch (ddr_size) {
+ case 0x80000000:
+ strcpy(loc_name, "gxl_p231_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "gxl_p231_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "gxl_p231_512m\0");
+ break;
+ default:
+ //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "gxl_p231_unsupport\0");
+ break;
+ }
+ }
+
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/gxm_skt_v1/Kconfig b/board/amlogic/gxm_skt_v1/Kconfig
new file mode 100644
index 0000000..fcace79
--- /dev/null
+++ b/board/amlogic/gxm_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxm_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxl"
+
+config SYS_CONFIG_NAME
+ default "gxm_skt_v1"
+
+endif
diff --git a/board/amlogic/gxm_skt_v1/Makefile b/board/amlogic/gxm_skt_v1/Makefile
new file mode 100644
index 0000000..35a1991
--- /dev/null
+++ b/board/amlogic/gxm_skt_v1/Makefile
@@ -0,0 +1,2 @@
+
+obj-y += $(BOARD).o eth_setup.o
diff --git a/board/amlogic/gxm_skt_v1/aml-user-key.sig b/board/amlogic/gxm_skt_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/gxm_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxm_skt_v1/eth_setup.c b/board/amlogic/gxm_skt_v1/eth_setup.c
new file mode 100644
index 0000000..33b5db1
--- /dev/null
+++ b/board/amlogic/gxm_skt_v1/eth_setup.c
@@ -0,0 +1,50 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxm_skt_v1/firmware/board_init.c b/board/amlogic/gxm_skt_v1/firmware/board_init.c
new file mode 100644
index 0000000..22c36d1
--- /dev/null
+++ b/board/amlogic/gxm_skt_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p201_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxm_skt_v1/firmware/power.c b/board/amlogic/gxm_skt_v1/firmware/power.c
new file mode 100644
index 0000000..16fdea9
--- /dev/null
+++ b/board/amlogic/gxm_skt_v1/firmware/power.c
@@ -0,0 +1,224 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+/* #include <stdio.h> */
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#define P_PIN_MUX_REG8 (*((volatile unsigned *)(0xda834400 + (0x34 << 2))))
+#define P_PIN_MUX_AO_REG (*((volatile unsigned *)(0xc8100000 + (0x5 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#undef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_PWM_A
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#define P_AO_PWM_PWM_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG1;
+ reg &= ~(1 << 10);
+ P_PIN_MUX_REG1 = reg;
+
+ reg = P_PIN_MUX_REG2;
+ reg &= ~(1 << 5);
+ reg |= (1 << 11); /* enable PWM_B */
+ P_PIN_MUX_REG2 = reg;
+ break;
+
+ case pwm_ao_a:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_AO_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_AO_REG;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 7);
+ P_PIN_MUX_AO_REG = reg;
+
+ reg = P_PIN_MUX_AO_REG;
+ reg |= (1 << 22); /* enable PWM_AO_A */
+ P_PIN_MUX_AO_REG = reg;
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG8;
+ reg &= ~(1 << 29);
+ P_PIN_MUX_REG8 = reg;
+
+ reg = P_PIN_MUX_REG8;
+ reg |= (1 << 30); /* enable PWM_F */
+ P_PIN_MUX_REG8 = reg;
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+ case pwm_f:
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ case pwm_ao_a:
+ P_AO_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_ao_a);
+ pwm_init(pwm_f);
+ serial_puts("set vdd cpu_a to ");
+ serial_put_dec(CONFIG_VCCKA_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_a, CONFIG_VCCKA_INIT_VOLTAGE);
+
+ serial_puts("set vdd cpu_b to ");
+ serial_put_dec(CONFIG_VCCKB_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_f, CONFIG_VCCKB_INIT_VOLTAGE);
+
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxm_skt_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxm_skt_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..08195f2
--- /dev/null
+++ b/board/amlogic/gxm_skt_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,258 @@
+
+int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860),
+ DVFS( 250000000, 860),
+ DVFS( 500000000, 860),
+ DVFS( 667000000, 900),
+ DVFS(1000000000, 940),
+ DVFS(1200000000, 1020),
+ DVFS(1416000000, 1110),
+ DVFS(1536000000, 1110),
+ DVFS(1752000000, 1110),
+ DVFS(2016000000, 1110)
+};
+struct scpi_opp_entry vlittle_dvfs_tbl[] = {
+ DVFS( 100000000, 860),
+ DVFS( 250000000, 860),
+ DVFS( 500000000, 860),
+ DVFS( 667000000, 900),
+ DVFS(1000000000, 940),
+};
+
+
+
+#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#undef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_PWM_A
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#define P_AO_PWM_PWM_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define P_PIN_MUX_AO_REG (*((volatile unsigned *)(0xc8100000 + (0x5 << 2))))
+#define P_PIN_MUX_REG8 (*((volatile unsigned *)(0xda834400 + (0x34 << 2))))
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_ao_a:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_AO_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_AO_REG;
+ reg &= ~(1 << 9);
+ reg &= ~(1 << 7);
+ P_PIN_MUX_AO_REG = reg;
+
+ reg = P_PIN_MUX_AO_REG;
+ reg |= (1 << 22); // enable PWM_AO_A
+ P_PIN_MUX_AO_REG = reg;
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG8;
+ reg &= ~(1 << 29);
+ P_PIN_MUX_REG8 = reg;
+
+ reg = P_PIN_MUX_REG8;
+ reg |= (1 << 30); // enable PWM_F
+ P_PIN_MUX_REG8 = reg;
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+int dvfs_get_voltage(unsigned int domain)
+{
+ int i = 0;
+ unsigned int reg_val = 0x040018;
+
+ if (domain == 0)
+ reg_val = P_AO_PWM_PWM_A;
+
+ if (domain == 1)
+ reg_val = P_PWM_PWM_F;
+
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+ if (!init_flag) {
+ pwm_init(pwm_f);
+ pwm_init(pwm_ao_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage(domain);
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (domain == 0) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (domain == 1) {
+ if (pwm_voltage_table[to][1] >= vlittle_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ if (domain == 0)
+ P_AO_PWM_PWM_A = pwm_voltage_table[to][0];
+ if (domain == 1)
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ if (domain == 0)
+ P_AO_PWM_PWM_A = pwm_voltage_table[cur][0];
+ if (domain == 1)
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ if (domain == 0)
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+ if (domain == 1)
+ cnt = ARRAY_SIZE(vlittle_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ if (domain == 0)
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ if (domain == 1)
+ memcpy(&buf_opp.opp[0], vlittle_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/gxm_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxm_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..871c1d1
--- /dev/null
+++ b/board/amlogic/gxm_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,281 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+
+extern int pwm_voltage_table[31][2];
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+#define P_PWM_PWM_AO_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define ON 1
+#define OFF 0
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+};
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_a:
+ uart_puts("set vdd_cpu a to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_AO_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_f:
+ uart_puts("set vdd_cpu a to 0x");
+ uart_put_hex(pwm_voltage_table[to][1], 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+/*GPIOH_3*/
+static void hdmi_5v_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* VCC5V ON GPIOH_3 output mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 0);
+ } else {
+ /* VCC5V OFF GPIOH_3 input mode*/
+ aml_update_bits(PREG_PAD_GPIO1_EN_N, 1 << 23, 1 << 23);
+ }
+}
+/*GPIODV_25*/
+static void vcck_ctrl(unsigned int ctrl)
+{
+ if (ctrl == ON) {
+ /* vddcpu_a*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 1<<20);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_a, CONFIG_VCCKA_INIT_VOLTAGE);
+
+ /* vddcpu_b*/
+ aml_update_bits(PREG_PAD_GPIO3_EN_N, 1 << 28, 0);
+ aml_update_bits(PREG_PAD_GPIO3_O, 1 << 28, 1<<28);
+ /* after power on vcck, should init vcck*/
+ _udelay(5000);
+ pwm_set_voltage(pwm_f, CONFIG_VCCKB_INIT_VOLTAGE);
+ } else {
+ /* vddcpu_a*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 0);
+
+ /* vddcpu_b*/
+ aml_update_bits(PREG_PAD_GPIO3_EN_N, 1 << 28, 0);
+ aml_update_bits(PREG_PAD_GPIO3_O, 1 << 28, 0);
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+ hdmi_5v_ctrl(OFF);
+ vcck_ctrl(OFF);
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_SLEEP_VOLTAGE); // reduce power
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ vcck_ctrl(ON);
+ hdmi_5v_ctrl(ON);
+}
+
+static void power_off_at_24M(void)
+{
+ /* LED GPIOAO_9*/
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 9, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 25, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 9, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 25, 1 << 25);
+
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_2;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+
+ p->gpio_info_count = ++i;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned int ret;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ ret = remote_detect_key();
+ if (ret == 1)
+ exit_reason = REMOTE_WAKEUP;
+ if (ret == 2)
+ exit_reason = REMOTE_CUS_WAKEUP;
+ }
+
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if ((readl(AO_GPIO_I) & (1<<2)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
+
diff --git a/board/amlogic/gxm_skt_v1/firmware/timing.c b/board/amlogic/gxm_skt_v1/firmware/timing.c
new file mode 100644
index 0000000..2477439
--- /dev/null
+++ b/board/amlogic/gxm_skt_v1/firmware/timing.c
@@ -0,0 +1,571 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_60OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_34OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x59959, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0x10,
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=95,
+ [3]=95,
+ [4]=95,
+ [5]=95,
+ },
+ .rd_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=95,
+ [3]=95,
+ [4]=95,
+ [5]=95,
+ },
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCKA_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/gxm_skt_v1/gxm_skt_v1.c b/board/amlogic/gxm_skt_v1/gxm_skt_v1.c
new file mode 100644
index 0000000..9d5f940
--- /dev/null
+++ b/board/amlogic/gxm_skt_v1/gxm_skt_v1.c
@@ -0,0 +1,514 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <amlogic/spifc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ } else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 3
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ clrbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 23);
+ clrbits_le32(P_PREG_PAD_GPIO1_O, 1 << 23);
+}
+#endif
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_11: NOR_D:reg7[13], clr reg7[4] + reg7[15]
+ * BOOT_12: NOR_Q:reg7[12], clr reg7[3]
+ * BOOT_13: NOR_C:reg7[11], clr reg7[2]
+ * BOOT_15: NOR_CS:reg7[10],clr reg7[0] + reg7[28]
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {97/*PIN_BOOT_15*/};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_7);
+ val &= ~((1<<13)|(1<<12)|(1<<11)|(1<<10));
+ if (enable) {
+ val |= (1<<13)|(1<<12)|(1<<11);
+ val &= ~((1<<28)|(1<<15)|(1<<4)|(1<<3)|(1<<2)|(1<<0));
+ }
+ writel(val, P_PERIPHS_PIN_MUX_7);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xc1108c80,
+ .mem_map = 0xcc000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+int board_init(void)
+{
+ //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*for LED*/
+ //clear pinmux
+ clrbits_le32(AO_RTI_PIN_MUX_REG, ((1<<3)|(1<<4)));
+ clrbits_le32(AO_RTI_PIN_MUX_REG2, ((1<<1)|(1<<31)));
+ //set output mode
+ clrbits_le32(PREG_PAD_GPIO0_EN_N, (1 << 24));
+ //set output 1
+ setbits_le32(PREG_PAD_GPIO0_O, (1 << 24));
+
+ /*Power on GPIOAO_2 for VCC_5V*/
+ clrbits_le32(P_AO_GPIO_O_EN_N, ((1<<2)|(1<<18)));
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+
+#ifndef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#endif
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+#ifdef CONFIG_AML_IRDETECT_EARLY
+#ifdef CONFIG_AML_HDMITX20
+static int do_hdmi_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+return 0;
+}
+
+U_BOOT_CMD(hdmi_init, CONFIG_SYS_MAXARGS, 0, do_hdmi_init,
+ "HDMI_INIT sub-system",
+ "hdmit init\n")
+#endif
+#endif
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifndef CONFIG_AML_IRDETECT_EARLY
+ /* after */
+ run_command("cvbs init;hdmitx hpd", 0);
+ run_command("vout output $outputmode", 0);
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) {
+ setenv("maxcpus","4");
+ }
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXM) {
+ setenv("maxcpus","8");
+ }
+
+ /* load uboot pq value */
+ vpp_pq_load();
+
+ return 0;
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
+
diff --git a/board/amlogic/gxtvbb_9023_skt_v1/Kconfig b/board/amlogic/gxtvbb_9023_skt_v1/Kconfig
new file mode 100644
index 0000000..4f8dab9
--- /dev/null
+++ b/board/amlogic/gxtvbb_9023_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GXTV
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxtvbb_9023_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxtvbb"
+
+config SYS_CONFIG_NAME
+ default "gxtvbb_9023_skt_v1"
+
+endif
diff --git a/board/amlogic/gxtvbb_9023_skt_v1/Makefile b/board/amlogic/gxtvbb_9023_skt_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/gxtvbb_9023_skt_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/gxtvbb_9023_skt_v1/aml-user-key.sig b/board/amlogic/gxtvbb_9023_skt_v1/aml-user-key.sig
new file mode 100644
index 0000000..6b51b19
--- /dev/null
+++ b/board/amlogic/gxtvbb_9023_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxtvbb_9023_skt_v1/eth_setup.c b/board/amlogic/gxtvbb_9023_skt_v1/eth_setup.c
new file mode 100644
index 0000000..c5503c3
--- /dev/null
+++ b/board/amlogic/gxtvbb_9023_skt_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxtvbb_9023_skt_v1/firmware/board_init.c b/board/amlogic/gxtvbb_9023_skt_v1/firmware/board_init.c
new file mode 100644
index 0000000..7ad9da6
--- /dev/null
+++ b/board/amlogic/gxtvbb_9023_skt_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxtvbb_9023_skt_v1/firmware/power.c b/board/amlogic/gxtvbb_9023_skt_v1/firmware/power.c
new file mode 100644
index 0000000..b9d7e83
--- /dev/null
+++ b/board/amlogic/gxtvbb_9023_skt_v1/firmware/power.c
@@ -0,0 +1,212 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140},
+};
+
+#define P_PIN_MUX_AO (*((volatile unsigned *)(0xc8100000 + (0x05 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xda834400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#ifdef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_MISC_REG_AB
+#endif
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#ifdef P_AO_PWM_PWM_B
+#undef P_AO_PWM_PWM_B
+#endif
+#define P_AO_PWM_PWM_B (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_A, PWM_AO_B,PWM_F
+ */
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~((1 << 12)|(1<<14)|(1<<22));
+ P_PIN_MUX_REG10 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg |= (1 << 21); // enable PWM_A
+ P_PIN_MUX_REG10 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1)|(1<<0));
+
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_AO_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 21); // enable PWM_AO_B
+ P_PIN_MUX_AO = reg;
+
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1) |(1 << 0));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 22); // enable PWM_f
+ P_PIN_MUX_AO = reg;
+
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+
+ //serial_put_dec( pwm_voltage_table[to][1]);
+ //serial_puts(" mv\n");
+
+ //serial_put_dec( pwm_voltage_table[to][0]);
+ //serial_puts(" mv\n");
+
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ P_AO_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_f:
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxtvbb_9023_skt_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxtvbb_9023_skt_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..35977ff
--- /dev/null
+++ b/board/amlogic/gxtvbb_9023_skt_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,175 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860),
+ DVFS( 250000000, 860),
+ DVFS( 500000000, 860),
+ DVFS( 667000000, 900),
+ DVFS(1000000000, 940),
+ DVFS(1200000000, 980),
+ DVFS(1296000000, 1000),
+ DVFS(1416000000, 1020),
+ DVFS(1536000000, 1050),
+ DVFS(1800000000, 1050),
+};
+
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 22);
+ reg |= (1 << 21); // enable PWM_B
+ P_PIN_MUX_REG3 = reg;
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_B;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_B = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+}
+
diff --git a/board/amlogic/gxtvbb_9023_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxtvbb_9023_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..5be84ab
--- /dev/null
+++ b/board/amlogic/gxtvbb_9023_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,189 @@
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void power_off_at_clk81(void)
+{
+}
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+}
+static void power_on_at_32k(unsigned int suspend_from)
+{
+}
+
+static void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ writel(9, P_ISA_TIMERA);
+}
+static void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+
+static void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ p->gpio_info_count = 0;
+ p->status = RESPONSE_OK;
+ val = (AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC);
+
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+
+ p->sources = val;
+
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ saradc_enable();
+ reset_ao_timera();
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+ wakeup_timer_clear();
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/gxtvbb_9023_skt_v1/firmware/timing.c b/board/amlogic/gxtvbb_9023_skt_v1/firmware/timing.c
new file mode 100644
index 0000000..4385dea
--- /dev/null
+++ b/board/amlogic/gxtvbb_9023_skt_v1/firmware/timing.c
@@ -0,0 +1,388 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 50
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+#define CFG_DDR3_DRV DDR3_DRV_40OHM
+#define CFG_DDR3_ODT DDR3_ODT_120OHM
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_14,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (14),
+ .cfg_ddr_rcd = (14),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (14),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (10),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 0,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+ .ddr_size_detect = CONFIG_DDR_SIZE_AUTO_DETECT,
+ .ddr_drv = CFG_DDR3_DRV,
+ .ddr_odt = CFG_DDR3_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00210000,
+ .t_pub_mr = {0},
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x0380c6a0, //PUB PGCR1
+ //.t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ .t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aafe60, //PUB PGCR3
+ .t_pub_dxccr = 0x00181884, //PUB DXCCR
+ .t_pub_dtcr = 0x43003087, //PUB DTCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+ .t_pub_dcr = 0X8B, //PUB DCR
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ .t_pub_dsgcr = 0x020641f,
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x59, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x19, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x19, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x19, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F21, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = (1<<31)|(0x20<<16)|(0x80<<0)//[B31]hw_exit_idle_en
+ |( 0<<8), //[B10,B9,B8] tfaw_cfg_offset:
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ //.t_pctl0_ppcfg = (0xF0 << 1),
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 1,
+ .t_pctl0_dfitphywrlta = 2,
+ .t_pctl0_dfitrddataen = 3,
+ .t_pctl0_dfitphyrdlat = 16,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype1 = 0x200,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (3 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+ .t_pub_acbdlr0 = 0, //2015.09.21 add for CK0 delay fine tune
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+};
diff --git a/board/amlogic/gxtvbb_9023_skt_v1/gxtvbb_9023_skt_v1.c b/board/amlogic/gxtvbb_9023_skt_v1/gxtvbb_9023_skt_v1.c
new file mode 100644
index 0000000..9f6465e
--- /dev/null
+++ b/board/amlogic/gxtvbb_9023_skt_v1/gxtvbb_9023_skt_v1.c
@@ -0,0 +1,705 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/gxtvbb_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+ #include <asm/arch/io.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <amlogic/spifc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+#ifdef CONFIG_AML_PMU4
+#define AML1220_ADDR 0x35
+#define AML1220_ANALOG_ADDR 0x20
+
+unsigned int pmu4_analog_reg[15] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, /* Reg 0x20 - 0x24 */
+ 0x00, 0x00, 0x00, 0x00, 0x51, /* Reg 0x25 - 0x29 */
+ 0x42, 0x00, 0x42, 0x41, 0x02 /* Reg 0x2a - 0x2e */
+};
+
+#define PMU4_ANALOG_REG_LEN ARRAY_SIZE(pmu4_analog_reg)
+
+int aml_pmu4_read(int add, uint8_t *val)
+{
+ int ret;
+ uint8_t buf[2] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ ,
+ {
+ .addr = AML1220_ADDR,
+ .flags = I2C_M_RD,
+ .len = 1,
+ .buf = val,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ ret = aml_i2c_xfer(msg, 2);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+int aml_pmu4_write(int32_t add, uint8_t val)
+{
+ int ret;
+ uint8_t buf[3] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ buf[2] = val & 0xff;
+ ret = aml_i2c_xfer(msg, 1);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+void pmu4_phy_config(void)
+{
+#if 0
+ int i;
+ uint8_t value;
+ int data;
+ uint8_t data_lo;
+ uint8_t data_hi;
+#endif
+ /* eth ldo */
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+
+ mdelay(10);
+
+ /* pinmux */
+ aml_pmu4_write(0x2c, 0x51);
+ aml_pmu4_write(0x2d, 0x41);
+ aml_pmu4_write(0x20, 0x0);
+ aml_pmu4_write(0x21, 0x3);
+#ifdef EXT_CLK
+ aml_pmu4_write(0x14, 0x01);
+#else
+ aml_pmu4_write(0x14, 0x00);
+#endif
+ aml_pmu4_write(0x15, 0x3f);
+
+ /* pll */
+ aml_pmu4_write(0x78, 0x06);
+ aml_pmu4_write(0x79, 0x05);
+ aml_pmu4_write(0x7a, 0xa1);
+ aml_pmu4_write(0x7b, 0xac);
+ aml_pmu4_write(0x7c, 0x5b);
+ aml_pmu4_write(0x7d, 0xa0);
+ aml_pmu4_write(0x7e, 0x20);
+ aml_pmu4_write(0x7f, 0x49);
+ aml_pmu4_write(0x80, 0xd6);
+ aml_pmu4_write(0x81, 0x0b);
+ aml_pmu4_write(0x82, 0xd1);
+ aml_pmu4_write(0x83, 0x00);
+ aml_pmu4_write(0x84, 0x00);
+ aml_pmu4_write(0x85, 0x00);
+
+ /*cfg4- --- cfg 45 */
+ aml_pmu4_write(0x88, 0x0);
+ aml_pmu4_write(0x89, 0x0);
+ aml_pmu4_write(0x8A, 0x22);
+ aml_pmu4_write(0x8B, 0x01);
+ aml_pmu4_write(0x8C, 0xd0);
+ aml_pmu4_write(0x8D, 0x01);
+ aml_pmu4_write(0x8E, 0x00);
+ aml_pmu4_write(0x93, 0x81);
+
+ /* pmu4 phyid = 20142014 */
+ aml_pmu4_write(0x94, 0x14);
+ aml_pmu4_write(0x95, 0x20);
+
+ aml_pmu4_write(0x96, 0x14);
+ aml_pmu4_write(0x97, 0x20);
+
+ /*phyadd & mode */
+#ifdef EXT_CLK
+ aml_pmu4_write(0x98, 0x73);
+#else
+ aml_pmu4_write(0x98, 0x47);
+#endif
+
+ aml_pmu4_write(0x99, 0x61);
+ aml_pmu4_write(0x9a, 0x07);
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+#if 0
+ value = 0;
+ pr_info("--------> read 0x9c\n");
+ while ((value & 0x01) == 0)
+ aml_pmu4_read(0x9c, &value);
+ pr_info("----2----> read 0x9c over!\n");
+#endif
+ aml_pmu4_write(0x9b, 0x00);
+ aml_pmu4_write(0x9b, 0x80);
+ aml_pmu4_write(0x9b, 0x00);
+#if 0
+ printf("phy init though i2c done\n");
+ for (i = 0; i < 0xb0; i++) {
+ aml_pmu4_read(i, &value);
+ printf(" i2c[%x]=0x%x\n", i, value);
+ }
+ printf("phy reg dump though i2c:\n");
+ for (i = 0; i < 0x20; i++) {
+ aml_pmu4_write(0xa6, i);
+ aml_pmu4_read(0xa7, &data_lo);
+ aml_pmu4_read(0xa8, &data_hi);
+ data = (data_hi << 8) | data_lo;
+ printf(" phy[%x]=0x%x\n", i, data);
+ }
+#endif
+}
+
+static int aml_pmu4_reg_init(unsigned int reg_base, unsigned int *val,
+ unsigned int reg_len)
+{
+ int ret = 0;
+ unsigned int i = 0;
+
+ for (i = 0; i < reg_len; i++) {
+ ret = aml_pmu4_write(reg_base + i, val[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int aml_pmu4_power_init(void)
+{
+ int ret;
+
+ /* pmu4 analog register init */
+ ret = aml_pmu4_reg_init(AML1220_ANALOG_ADDR, &pmu4_analog_reg[0],
+ PMU4_ANALOG_REG_LEN);
+ if (ret < 0)
+ return ret;
+
+ pmu4_phy_config();
+
+ return 0;
+
+}
+
+void setup_pmu4(void)
+{
+ aml_pmu4_power_init();
+}
+#endif
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ //setup ethernet clk need calibrate to configre
+ setbits_le32(P_PERIPHS_PIN_MUX_8, 0x1fffc000);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+#ifndef CONFIG_AML_PMU4
+ /* hardware reset ethernet phy : gpioz14 connect phyreset pin*/
+ clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 14);
+ clrbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+ udelay(100000);
+ setbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+#endif
+}
+
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_AML_PMU4
+ setup_pmu4();
+#endif
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ ret=readl(P_PREG_PAD_GPIO5_I)&(1<<29)?0:1;
+ printf("ret = %d .",ret);
+ if ((readl(P_PERIPHS_PIN_MUX_8)&(3<<9))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I)&(1<<24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 1
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(PERIPHS_PIN_MUX_7, (1<<19)|(1<<20));
+ //enable I2C MASTER AO pins
+ setbits_le32(PERIPHS_PIN_MUX_7,
+ ((MESON_I2C_MASTER_B_GPIOH_3_BIT) | (MESON_I2C_MASTER_B_GPIOH_4_BIT)));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_B,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_b_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOH_4_REG,
+ .scl_bit = MESON_I2C_MASTER_B_GPIOH_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOH_3_REG,
+ .sda_bit = MESON_I2C_MASTER_B_GPIOH_3_BIT,
+ }
+};
+#if 1
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+#include <asm/arch/usb.h>
+#include <asm/arch/gpio.h>
+struct amlogic_usb_config g_usb_config_GXTVBB_skt={
+ CONFIG_GXTVBB_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXTVBB_USB_PHY2_BASE,
+ CONFIG_GXTVBB_USB_PHY3_BASE,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_11: NOR_D:reg5[16], clr none
+ * BOOT_12: NOR_Q:reg5[17], clr none
+ * BOOT_13: NOR_C:reg5[18], clr none
+ * BOOT_18: NOR_CS:reg5[19],clr none
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {71/*BOOT_18*/};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_5);
+ val &= ~((1<<19)|(1<<18)|(1<<17)|(1<<16));
+ if (enable) {
+ val |= (1<<18)|(1<<17)|(1<<16);
+ }
+ writel(val, P_PERIPHS_PIN_MUX_5);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xc1108c80,
+ .mem_map = 0xcc000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+ board_usb_init(&g_usb_config_GXTVBB_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+#ifdef CONFIG_SYS_I2C_AML
+// #ifdef 1
+ board_i2c_init();
+// #endif /*CONFIG_AML_I2C*/
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+ /*add board late init function here*/
+ run_command("setenv fdt_high 0x20000000", 1);
+ run_command("setenv dtb_mem_addr 0x1000000", 1);
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+ vpp_init();
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int boardid = 0;
+ char loc_name[64] = {0};
+ boardid = (readl(AO_SEC_GP_CFG0)>>8)&0xff;
+ printf("%s: boardid = 0x%x\n", __func__,boardid);
+
+ switch (boardid) {
+ case 0:
+ strcpy(loc_name, "gxtvbb_p301_1g\0");
+ break;
+ case 8:
+ strcpy(loc_name, "gxtvbb_p300_2g\0");
+ break;
+ case 12:
+ strcpy(loc_name, "gxtvbb_skt_2g\0");
+ break;
+ default:
+ printf("boardid: 0x%x, multi-dt doesn't support\n", boardid);
+ //strcpy(loc_name, "gxb_p200_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
+
diff --git a/board/amlogic/gxtvbb_9023_skt_v1/lcd.c b/board/amlogic/gxtvbb_9023_skt_v1/lcd.c
new file mode 100755
index 0000000..2990aab
--- /dev/null
+++ b/board/amlogic/gxtvbb_9023_skt_v1/lcd.c
@@ -0,0 +1,320 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOX_3",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,},
+ {LCD_POWER_TYPE_MAX, 0,0,0,},
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,},
+ {LCD_POWER_TYPE_MAX, 0,0,0,},
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOAO_4",
+ "GPIOY_13",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* AOC: public Platform lvds : 1920x1080@60hz 8bit pixel clk@74.25mhz 2prot*/
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{7, 0x00001800}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{7, 0x00000603}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 2,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{10, 0x00800000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{10, 0x0100a000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/gxtvbb_p300_v1/Kconfig b/board/amlogic/gxtvbb_p300_v1/Kconfig
new file mode 100644
index 0000000..fbece76
--- /dev/null
+++ b/board/amlogic/gxtvbb_p300_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GXTV
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxtvbb_p300_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxtvbb"
+
+config SYS_CONFIG_NAME
+ default "gxtvbb_p300_v1"
+
+endif
diff --git a/board/amlogic/gxtvbb_p300_v1/Makefile b/board/amlogic/gxtvbb_p300_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/gxtvbb_p300_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/gxtvbb_p300_v1/aml-user-key.sig b/board/amlogic/gxtvbb_p300_v1/aml-user-key.sig
new file mode 100644
index 0000000..6b51b19
--- /dev/null
+++ b/board/amlogic/gxtvbb_p300_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxtvbb_p300_v1/eth_setup.c b/board/amlogic/gxtvbb_p300_v1/eth_setup.c
new file mode 100644
index 0000000..c5503c3
--- /dev/null
+++ b/board/amlogic/gxtvbb_p300_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxtvbb_p300_v1/firmware/board_init.c b/board/amlogic/gxtvbb_p300_v1/firmware/board_init.c
new file mode 100644
index 0000000..98d49dd
--- /dev/null
+++ b/board/amlogic/gxtvbb_p300_v1/firmware/board_init.c
@@ -0,0 +1,91 @@
+
+/*
+ * board/amlogic/gxtvbb_p300_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+
+#define PNL_AO_GPIO_O_EN_N 0x09
+#define PNL_AO_GPIO_I 0x0a
+
+#define PNL_PREG_PAD_GPIO1_EN_N 0x0f
+#define PNL_PREG_PAD_GPIO1_O 0x10
+#define PNL_PREG_PAD_GPIO1_I 0x11
+
+#define PNL_PREG_PAD_GPIO4_EN_N 0x18
+#define PNL_PREG_PAD_GPIO4_O 0x19
+#define PNL_PREG_PAD_GPIO4_I 0x1a
+
+#define PNL_REG_BASE (0xc8834400L)
+#define PNL_REG(reg) (PNL_REG_BASE + (reg << 2))
+#define PNL_REG_R(_reg) (*(volatile unsigned int *)PNL_REG(_reg))
+#define PNL_REG_W(_reg, _value) *(volatile unsigned int *)PNL_REG(_reg) = (_value);
+void panel_power_init(void)
+{
+ serial_puts("init panel power\n");
+ /* GPIOX_3 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO4_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO4_O) & ~(1 << 3)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO4_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO4_EN_N) & ~(1 << 3)));
+ /* GPIOH_0 */
+/* PNL_REG_W(PNL_PREG_PAD_GPIO1_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_O) & ~(1 << 20)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_EN_N) & ~(1 << 20)));
+*/
+ /* GPIOAO_4 */
+ PNL_REG_W(PNL_AO_GPIO_O_EN_N,
+ (PNL_REG_R(PNL_AO_GPIO_O_EN_N) & ~(1 << 20)));
+ PNL_REG_W(PNL_AO_GPIO_O_EN_N,
+ (PNL_REG_R(PNL_AO_GPIO_O_EN_N) & ~(1 << 4)));
+ /* GPIOY_13 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_O) & ~(1 << 13)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_EN_N) & ~(1 << 13)));
+}
+
+#define SEC_AO_SEC_GP_CFG0 (0xda100000 + (0x90 << 2))
+static int check_is_ddr_inited(void)
+{
+ return ((readl(SEC_AO_SEC_GP_CFG0) >> 16) & 0xffff);
+}
+
+void board_init(void)
+{
+ power_init(0);
+
+ //only run once before ddr inited.
+ if (!check_is_ddr_inited()) {
+ /* dram 1.5V reset */
+ serial_puts("DRAM reset...\n");
+ /* power off ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) & (~((1 << 3) | (1 << 19)))),P_AO_GPIO_O_EN_N);
+ /* need delay */
+ _udelay(200000);
+ /* power on ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) | (1 << 19)),P_AO_GPIO_O_EN_N);
+ _udelay(40000);
+ }
+
+ panel_power_init();
+}
diff --git a/board/amlogic/gxtvbb_p300_v1/firmware/power.c b/board/amlogic/gxtvbb_p300_v1/firmware/power.c
new file mode 100644
index 0000000..7127cf7
--- /dev/null
+++ b/board/amlogic/gxtvbb_p300_v1/firmware/power.c
@@ -0,0 +1,221 @@
+
+/*
+ * board/amlogic/gxtvbb_p300_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140},
+};
+
+#define P_PIN_MUX_AO (*((volatile unsigned *)(0xc8100000 + (0x05 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xda834400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#ifdef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_MISC_REG_AB
+#endif
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#ifdef P_AO_PWM_PWM_B
+#undef P_AO_PWM_PWM_B
+#endif
+#define P_AO_PWM_PWM_B (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_A, PWM_AO_B,PWM_F
+ */
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~((1 << 12)|(1<<14)|(1<<22));
+ P_PIN_MUX_REG10 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg |= (1 << 21); // enable PWM_A
+ P_PIN_MUX_REG10 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1)|(1<<0));
+
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_AO_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 21); // enable PWM_AO_B
+ P_PIN_MUX_AO = reg;
+
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1) |(1 << 0));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 22); // enable PWM_f
+ P_PIN_MUX_AO = reg;
+
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+
+ //serial_put_dec( pwm_voltage_table[to][1]);
+ //serial_puts(" mv\n");
+
+ //serial_put_dec( pwm_voltage_table[to][0]);
+ //serial_puts(" mv\n");
+
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ P_AO_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_f:
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vddee enable AO_8 to low\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~((1 << 8)|(1 << 24));
+ writel(reg, AO_GPIO_O_EN_N);
+ serial_puts("set vddee enable AO_2 to low\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~((1 << 2)|(1 << 18));
+ writel(reg, AO_GPIO_O_EN_N);
+}
diff --git a/board/amlogic/gxtvbb_p300_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxtvbb_p300_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..60292db
--- /dev/null
+++ b/board/amlogic/gxtvbb_p300_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,172 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 1000+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1020+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1536000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1800000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xc8834400 + ( 0x36 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(0x00405000);
+ reg |= (1 << 21); // enable PWM_A
+ P_PIN_MUX_REG10 = reg;
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+}
+
diff --git a/board/amlogic/gxtvbb_p300_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxtvbb_p300_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..c4cc369
--- /dev/null
+++ b/board/amlogic/gxtvbb_p300_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,456 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <config.h>
+#define ON 1
+#define OFF 0
+static unsigned int pwm_voltage_table[][2] = {
+ {0x180004, 900},
+ {0x170005, 910},
+ {0x160006, 920},
+ {0x150007, 930},
+ {0x140008, 940},
+ {0x130009, 950},
+ {0x12000a, 960},
+ {0x11000b, 970},
+ {0x10000c, 980},
+ {0x0f000d, 990},
+ {0x0e000e, 1000},
+ {0x0d000f, 1010},
+ {0x0c0010, 1020},
+ {0x0b0011, 1030},
+ {0x0a0012, 1040},
+ {0x090013, 1050},
+ {0x080014, 1060},
+ {0x070015, 1070},
+ {0x060016, 1080},
+ {0x050017, 1090},
+ {0x040018, 1100},
+ {0x030019, 1110},
+ {0x02001a, 1120},
+ {0x01001b, 1130},
+ {0x00001c, 1140},
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_off_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 5, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 21, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 5, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 21, 1 << 21);
+}
+
+static void power_off_at_clk81(void)
+{
+ power_off_3v3_5v();
+ power_off_usb5v();
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ power_on_usb5v();
+ power_on_3v3_5v();
+ _udelay(10000);
+ _udelay(10000);
+ _udelay(10000);
+ _udelay(10000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+#if 0
+ if (suspend_from == SYS_POWEROFF) {
+ power_switch_to_ee(ON);
+ }
+#endif
+}
+
+static void power_off_at_24M(void)
+{
+}
+
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 3, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 19, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 3, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 19, 1 << 19);
+ _udelay(10000);
+}
+
+static void power_off_ee(void)
+{
+ return;
+ power_switch_to_ee(OFF);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 1 << 24);
+}
+
+static void power_on_ee(void)
+{
+ return;
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 0);
+ _udelay(10000);
+ _udelay(10000);
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_ee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_on_ddr();
+ power_on_ee();
+
+ }
+}
+
+static void wakeup_timer_setup(void)
+{
+ /* 1ms resolution */
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3 << 0) | (0x1 << 12) | (0x1 << 16));
+ writel(value, P_ISA_TIMER_MUX);
+ writel(9, P_ISA_TIMERA);
+}
+
+static void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1 << 12) | (0x1 << 16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+
+static void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ unsigned i = 0;
+
+ p->gpio_info_count = i;
+ p->status = RESPONSE_OK;
+ val = (AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC);
+#ifdef CONFIG_BT_WAKEUP
+ val |= BT_WAKEUP_SRC;
+#endif
+
+#ifdef CONFIG_CEC_WAKEUP
+ val |= CEC_WAKEUP_SRC;
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= WIFI_WAKEUP_SRC;
+#endif
+
+ p->sources = val;
+
+#ifdef CONFIG_BT_WAKEUP
+ {
+ struct wakeup_gpio_info *gpio;
+ /* BT Wakeup: IN: GPIOX[21], OUT: GPIOX[20] */
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP;
+ gpio->gpio_in_idx = GPIOX_21;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = GPIOX_20;
+ gpio->gpio_out_ao = 0;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+ }
+#endif
+
+#ifdef CONFIG_WIFI_WAKEUP
+ if (suspend_from != SYS_POWEROFF) {
+ struct wakeup_gpio_info *gpio;
+ /*WIFI Wakeup: IN: GPIOX[7], OUT: GPIOX[6] */
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = WIFI_WAKEUP;
+ gpio->gpio_in_idx = GPIOX_7;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = GPIOX_6;
+ gpio->gpio_out_ao = 0;
+ gpio->irq = IRQ_GPIO1_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+ }
+#endif
+}
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out * 100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+ uart_puts("enter detect key\n");
+
+ _udelay(10000);
+ /* setup wakeup resources */
+ /*auto suspend: timerA 10ms resolution */
+ if (time_out_ms != 0) {
+ wakeup_timer_setup();
+ if (suspend_from == SYS_POWEROFF) {
+ time_out_ms = time_out * 1000;
+ while (1) {
+ _udelay(1000);
+ time_out_ms--;
+ if (time_out_ms == 0)
+ return AUTO_WAKEUP;
+
+ }
+ }
+ }
+ saradc_enable();
+ reset_ao_timera();
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1; */
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key */
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+#ifdef CONFIG_BT_WAKEUP
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ & (0x01 << 20)) && (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 20)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 21)))
+ exit_reason = BT_WAKEUP;
+ }
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
+ irq[IRQ_GPIO1] = 0xFFFFFFFF;
+ if (suspend_from) {
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ & (0x01 << 6)) && (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 6)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 7)))
+ exit_reason = WIFI_WAKEUP;
+ }
+ }
+#endif
+ if (exit_reason)
+ break;
+ else
+ asm volatile ("wfi");
+ } while (1);
+ wakeup_timer_clear();
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/gxtvbb_p300_v1/firmware/timing.c b/board/amlogic/gxtvbb_p300_v1/firmware/timing.c
new file mode 100644
index 0000000..1ca17a2
--- /dev/null
+++ b/board/amlogic/gxtvbb_p300_v1/firmware/timing.c
@@ -0,0 +1,433 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 50
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+#define CFG_DDR3_DRV DDR3_DRV_40OHM
+#define CFG_DDR3_ODT DDR3_ODT_120OHM
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+ /*
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+*/
+
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 0x10
+#define DDR_RAS_BDL 0
+#define DDR_CAS_BDL 0
+#define DDR_WE_BDL 0
+#define DDR_BA0_BDL 0
+#define DDR_BA1_BDL 0
+#define DDR_BA2_BDL 0
+#define DDR_ACPDD_BDL 0
+#define DDR_CS0_BDL 0
+#define DDR_CS1_BDL 0
+#define DDR_ODT0_BDL 0
+#define DDR_ODT1_BDL 0
+#define DDR_CKE0_BDL 0
+#define DDR_CKE1_BDL 0
+#define DDR_A0_BDL 0
+#define DDR_A1_BDL 0
+#define DDR_A2_BDL 0
+#define DDR_A3_BDL 0
+#define DDR_A4_BDL 0
+#define DDR_A5_BDL 0
+#define DDR_A6_BDL 0
+#define DDR_A7_BDL 0
+#define DDR_A8_BDL 0
+#define DDR_A9_BDL 0
+#define DDR_A10_BDL 0
+#define DDR_A11_BDL 0
+#define DDR_A12_BDL 0
+#define DDR_A13_BDL 0
+#define DDR_A14_BDL 0
+#define DDR_A15_BDL 0
+#endif
+
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_14,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (14),
+ .cfg_ddr_rcd = (14),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (14),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (10),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+ .ddr_size_detect = CONFIG_DDR_SIZE_AUTO_DETECT,
+ .ddr_drv = CFG_DDR3_DRV,
+ .ddr_odt = CFG_DDR3_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00210000,
+ .t_pub_mr = {0},
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x0380c6a0, //PUB PGCR1
+ //.t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ .t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aafe60, //PUB PGCR3
+ .t_pub_dxccr = 0x00181884, //PUB DXCCR
+ .t_pub_dtcr = 0x43003087, //PUB DTCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+ .t_pub_dcr = 0X8B, //PUB DCR
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ .t_pub_dsgcr = 0x020641f,
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x79, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x79, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x79, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x79, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F21, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = (1<<31)|(0x20<<16)|(0x00<<0)//[B31]hw_exit_idle_en
+ |( 0<<8), //[B10,B9,B8] tfaw_cfg_offset:
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ //.t_pctl0_ppcfg = (0xF0 << 1),
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 1,
+ .t_pctl0_dfitphywrlta = 2,
+ .t_pctl0_dfitrddataen = 3,
+ .t_pctl0_dfitphyrdlat = 16,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype1 = 0x200,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (3 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+ .t_pub_acbdlr0 = 0, //0x1F, //2015.09.21 add for CK0 delay fine tune
+
+ /* v2 added */
+ .t_pub_aclcdlr = 0x10,
+ .t_pub_acbdlr3 = 0,
+ .t_pub_acbdlr4 = 0,
+ .t_pub_acbdlr5 = 0,
+
+ .ddr_func = DDR_FUNC,
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+};
diff --git a/board/amlogic/gxtvbb_p300_v1/gxtvbb_p300_v1.c b/board/amlogic/gxtvbb_p300_v1/gxtvbb_p300_v1.c
new file mode 100644
index 0000000..8ddef93
--- /dev/null
+++ b/board/amlogic/gxtvbb_p300_v1/gxtvbb_p300_v1.c
@@ -0,0 +1,717 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/gxtvbb_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+ #include <asm/arch/io.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#ifdef CONFIG_AML_SPICC
+#include <dm.h>
+#include <amlogic/spicc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+#ifdef CONFIG_AML_PMU4
+#define AML1220_ADDR 0x35
+#define AML1220_ANALOG_ADDR 0x20
+
+unsigned int pmu4_analog_reg[15] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, /* Reg 0x20 - 0x24 */
+ 0x00, 0x00, 0x00, 0x00, 0x51, /* Reg 0x25 - 0x29 */
+ 0x42, 0x00, 0x42, 0x41, 0x02 /* Reg 0x2a - 0x2e */
+};
+
+#define PMU4_ANALOG_REG_LEN ARRAY_SIZE(pmu4_analog_reg)
+
+int aml_pmu4_read(int add, uint8_t *val)
+{
+ int ret;
+ uint8_t buf[2] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ ,
+ {
+ .addr = AML1220_ADDR,
+ .flags = I2C_M_RD,
+ .len = 1,
+ .buf = val,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ ret = aml_i2c_xfer(msg, 2);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+int aml_pmu4_write(int32_t add, uint8_t val)
+{
+ int ret;
+ uint8_t buf[3] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ buf[2] = val & 0xff;
+ ret = aml_i2c_xfer(msg, 1);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+void pmu4_phy_config(void)
+{
+#if 0
+ int i;
+ uint8_t value;
+ int data;
+ uint8_t data_lo;
+ uint8_t data_hi;
+#endif
+ /* eth ldo */
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+
+ mdelay(10);
+
+ /* pinmux */
+ aml_pmu4_write(0x2c, 0x51);
+ aml_pmu4_write(0x2d, 0x41);
+ aml_pmu4_write(0x20, 0x0);
+ aml_pmu4_write(0x21, 0x3);
+#ifdef EXT_CLK
+ aml_pmu4_write(0x14, 0x01);
+#else
+ aml_pmu4_write(0x14, 0x00);
+#endif
+ aml_pmu4_write(0x15, 0x3f);
+
+ /* pll */
+ aml_pmu4_write(0x78, 0x00);
+ aml_pmu4_write(0x79, 0x05);
+ aml_pmu4_write(0x7a, 0xa1);
+ aml_pmu4_write(0x7b, 0xac);
+ aml_pmu4_write(0x7c, 0x5b);
+ aml_pmu4_write(0x7d, 0xa0);
+ aml_pmu4_write(0x7e, 0x20);
+ aml_pmu4_write(0x7f, 0x49);
+ aml_pmu4_write(0x80, 0xd6);
+ aml_pmu4_write(0x81, 0x0b);
+ aml_pmu4_write(0x82, 0xd1);
+ aml_pmu4_write(0x83, 0x00);
+ /* 24M to 50M */
+ aml_pmu4_write(0x84, 0x55);
+ aml_pmu4_write(0x85, 0x0d);
+
+ /*cfg4- --- cfg 45 */
+ aml_pmu4_write(0x88, 0x0);
+ aml_pmu4_write(0x89, 0x0);
+ aml_pmu4_write(0x8A, 0x22);
+ aml_pmu4_write(0x8B, 0x01);
+ aml_pmu4_write(0x8C, 0xd0);
+ aml_pmu4_write(0x8D, 0x01);
+ aml_pmu4_write(0x8E, 0x00);
+ aml_pmu4_write(0x93, 0x81);
+
+ /* pmu4 phyid = 20142014 */
+ aml_pmu4_write(0x94, 0x14);
+ aml_pmu4_write(0x95, 0x20);
+
+ aml_pmu4_write(0x96, 0x14);
+ aml_pmu4_write(0x97, 0x20);
+
+ /*phyadd & mode */
+#ifdef EXT_CLK
+ aml_pmu4_write(0x98, 0x73);
+#else
+ aml_pmu4_write(0x98, 0x47);
+#endif
+
+ aml_pmu4_write(0x99, 0x61);
+ aml_pmu4_write(0x9a, 0x07);
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+#if 0
+ value = 0;
+ pr_info("--------> read 0x9c\n");
+ while ((value & 0x01) == 0)
+ aml_pmu4_read(0x9c, &value);
+ pr_info("----2----> read 0x9c over!\n");
+#endif
+ aml_pmu4_write(0x9b, 0x00);
+ aml_pmu4_write(0x9b, 0x80);
+ aml_pmu4_write(0x9b, 0x00);
+#if 0
+ printf("phy init though i2c done\n");
+ for (i = 0; i < 0xb0; i++) {
+ aml_pmu4_read(i, &value);
+ printf(" i2c[%x]=0x%x\n", i, value);
+ }
+ printf("phy reg dump though i2c:\n");
+ for (i = 0; i < 0x20; i++) {
+ aml_pmu4_write(0xa6, i);
+ aml_pmu4_read(0xa7, &data_lo);
+ aml_pmu4_read(0xa8, &data_hi);
+ data = (data_hi << 8) | data_lo;
+ printf(" phy[%x]=0x%x\n", i, data);
+ }
+#endif
+}
+
+static int aml_pmu4_reg_init(unsigned int reg_base, unsigned int *val,
+ unsigned int reg_len)
+{
+ int ret = 0;
+ unsigned int i = 0;
+
+ for (i = 0; i < reg_len; i++) {
+ ret = aml_pmu4_write(reg_base + i, val[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int aml_pmu4_power_init(void)
+{
+ int ret;
+ int i = 0;
+ uint8_t value;
+
+ /* pmu4 analog register init */
+ ret = aml_pmu4_reg_init(AML1220_ANALOG_ADDR, &pmu4_analog_reg[0],
+ PMU4_ANALOG_REG_LEN);
+ if (ret < 0)
+ return ret;
+
+ pmu4_phy_config();
+
+ /* enable input 24M clock */
+ setbits_le32(0xc8100634, 0x93);
+
+ do {
+ aml_pmu4_read(0x9c, &value);
+ mdelay(10);
+ } while (((value & 0x01) == 0) && (i++ < 10));
+ if (!(value&0x01)) {
+ printf("WARING: PMU4 PLL not lock!");
+ }
+
+ return 0;
+
+}
+
+void setup_pmu4(void)
+{
+ aml_pmu4_power_init();
+}
+#endif
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ //setup ethernet clk need calibrate to configre
+ setbits_le32(P_PERIPHS_PIN_MUX_8, 0x1fffc000);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+#ifndef CONFIG_AML_PMU4
+ /* hardware reset ethernet phy : gpioz14 connect phyreset pin*/
+ clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 14);
+ clrbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+ udelay(100000);
+ setbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+#endif
+}
+
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_AML_PMU4
+ setup_pmu4();
+#endif
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ ret=readl(P_PREG_PAD_GPIO5_I)&(1<<29)?0:1;
+ printf("ret = %d .",ret);
+ if ((readl(P_PERIPHS_PIN_MUX_8)&(3<<9))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I)&(1<<24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 1
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(PERIPHS_PIN_MUX_7, (1<<19)|(1<<20));
+ //enable I2C MASTER AO pins
+ setbits_le32(PERIPHS_PIN_MUX_7,
+ ((MESON_I2C_MASTER_B_GPIOH_3_BIT) | (MESON_I2C_MASTER_B_GPIOH_4_BIT)));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_B,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_b_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOH_4_REG,
+ .scl_bit = MESON_I2C_MASTER_B_GPIOH_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOH_3_REG,
+ .sda_bit = MESON_I2C_MASTER_B_GPIOH_3_BIT,
+ }
+};
+#if 1
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+#include <asm/arch/usb.h>
+#include <asm/arch/gpio.h>
+struct amlogic_usb_config g_usb_config_GXTVBB_skt={
+ CONFIG_GXTVBB_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXTVBB_USB_PHY2_BASE,
+ CONFIG_GXTVBB_USB_PHY3_BASE,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+#ifdef CONFIG_AML_SPICC
+/* generic config in arch gpio/clock.c */
+extern int spicc_clk_enable(bool enable);
+extern int spicc_pinctrl_enable(bool enable);
+
+static const struct spicc_platdata spicc_platdata = {
+ .compatible = "amlogic,meson-gx-spicc",
+ .reg = (void __iomem *)0xc1108d80,
+ .clk_rate = 166666666,
+ .clk_enable = spicc_clk_enable,
+ .pinctrl_enable = spicc_pinctrl_enable,
+ /* case one slave without cs: {"no_cs", 0} */
+ .cs_gpio_names = {"GPIOH_9", 0},
+};
+
+U_BOOT_DEVICE(spicc) = {
+ .name = "spicc",
+ .platdata = &spicc_platdata,
+};
+#endif /* CONFIG_AML_SPICC */
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+ board_usb_init(&g_usb_config_GXTVBB_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+#ifdef CONFIG_SYS_I2C_AML
+// #ifdef 1
+ board_i2c_init();
+// #endif /*CONFIG_AML_I2C*/
+#endif
+
+ //temp for p301, usb 5V power
+ //run_command("mw 0xc8100024 BFFF3FDF", 0);
+ run_command("gpio s GPIOAO_5", 0);
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+ vpp_init();
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int boardid = 0;
+ char loc_name[64] = {0};
+ boardid = (readl(AO_SEC_GP_CFG0)>>8)&0xff;
+ printf("%s: boardid = 0x%x\n", __func__,boardid);
+
+ switch (boardid) {
+ case 0:
+ strcpy(loc_name, "gxtvbb_p301_1g\0");
+ break;
+ case 8:
+ strcpy(loc_name, "gxtvbb_p300_2g\0");
+ break;
+ case 12:
+ strcpy(loc_name, "gxtvbb_skt_2g\0");
+ break;
+ default:
+ printf("boardid: 0x%x, multi-dt doesn't support\n", boardid);
+ //strcpy(loc_name, "gxb_p200_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
+
diff --git a/board/amlogic/gxtvbb_p300_v1/lcd.c b/board/amlogic/gxtvbb_p300_v1/lcd.c
new file mode 100755
index 0000000..33d1ae5
--- /dev/null
+++ b/board/amlogic/gxtvbb_p300_v1/lcd.c
@@ -0,0 +1,355 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOX_3",
+ "GPIOX_2",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,50,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_3d_disable[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_CPU, 1,0,10,}, /* 3d_disable */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_3d_disable[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,30,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 1,2,0,}, /* 3d_disable */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOAO_4",
+ "GPIOY_13",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* AOC: public Platform lvds : 1920x1080@60hz 8bit pixel clk@74.25mhz 2prot*/
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_3d_disable, lcd_power_off_step_3d_disable,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{7, 0x00001800}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{7, 0x00000603}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{10, 0x00800000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{10, 0x0100a000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/gxtvbb_p301_v1/Kconfig b/board/amlogic/gxtvbb_p301_v1/Kconfig
new file mode 100644
index 0000000..42dc318
--- /dev/null
+++ b/board/amlogic/gxtvbb_p301_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GXTV
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxtvbb_p301_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxtvbb"
+
+config SYS_CONFIG_NAME
+ default "gxtvbb_p301_v1"
+
+endif
diff --git a/board/amlogic/gxtvbb_p301_v1/Makefile b/board/amlogic/gxtvbb_p301_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/gxtvbb_p301_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/gxtvbb_p301_v1/aml-user-key.sig b/board/amlogic/gxtvbb_p301_v1/aml-user-key.sig
new file mode 100644
index 0000000..6b51b19
--- /dev/null
+++ b/board/amlogic/gxtvbb_p301_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxtvbb_p301_v1/eth_setup.c b/board/amlogic/gxtvbb_p301_v1/eth_setup.c
new file mode 100644
index 0000000..c5503c3
--- /dev/null
+++ b/board/amlogic/gxtvbb_p301_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxtvbb_p301_v1/firmware/board_init.c b/board/amlogic/gxtvbb_p301_v1/firmware/board_init.c
new file mode 100644
index 0000000..07b2e90
--- /dev/null
+++ b/board/amlogic/gxtvbb_p301_v1/firmware/board_init.c
@@ -0,0 +1,95 @@
+
+/*
+ * board/amlogic/gxtvbb_p301_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+
+#define PNL_AO_GPIO_O_EN_N 0x09
+#define PNL_AO_GPIO_I 0x0a
+
+#define PNL_PREG_PAD_GPIO1_EN_N 0x0f
+#define PNL_PREG_PAD_GPIO1_O 0x10
+#define PNL_PREG_PAD_GPIO1_I 0x11
+
+#define PNL_PREG_PAD_GPIO4_EN_N 0x18
+#define PNL_PREG_PAD_GPIO4_O 0x19
+#define PNL_PREG_PAD_GPIO4_I 0x1a
+
+#define PNL_REG_BASE (0xc8834400L)
+#define PNL_REG(reg) (PNL_REG_BASE + (reg << 2))
+#define PNL_REG_R(_reg) (*(volatile unsigned int *)PNL_REG(_reg))
+#define PNL_REG_W(_reg, _value) *(volatile unsigned int *)PNL_REG(_reg) = (_value);
+void panel_power_init(void)
+{
+ serial_puts("init panel power\n");
+ /* GPIOX_3 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO4_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO4_O) & ~(1 << 3)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO4_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO4_EN_N) & ~(1 << 3)));
+ /* GPIOH_0 */
+/* PNL_REG_W(PNL_PREG_PAD_GPIO1_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_O) & ~(1 << 20)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_EN_N) & ~(1 << 20)));
+*/
+ /* GPIOAO_4 */
+ PNL_REG_W(PNL_AO_GPIO_O_EN_N,
+ (PNL_REG_R(PNL_AO_GPIO_O_EN_N) & ~(1 << 20)));
+ PNL_REG_W(PNL_AO_GPIO_O_EN_N,
+ (PNL_REG_R(PNL_AO_GPIO_O_EN_N) & ~(1 << 4)));
+ /* GPIOY_13 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_O) & ~(1 << 13)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_EN_N) & ~(1 << 13)));
+}
+
+#define SEC_AO_SEC_GP_CFG0 (0xda100000 + (0x90 << 2))
+static int check_is_ddr_inited(void)
+{
+ return ((readl(SEC_AO_SEC_GP_CFG0) >> 16) & 0xffff);
+}
+
+void board_init(void)
+{
+ power_init(0);
+
+ //only run once before ddr inited.
+ if (!check_is_ddr_inited()) {
+ /* dram 1.5V reset */
+ serial_puts("DRAM reset...\n");
+ /* power off ddr */
+ //aml_update_bits(P_AO_GPIO_O_EN_N, 1 << 3, 0);
+ //aml_update_bits(P_AO_GPIO_O_EN_N, 1 << 19, 0);
+ writel((readl(P_AO_GPIO_O_EN_N) & (~((1 << 3) | (1 << 19)))),P_AO_GPIO_O_EN_N);
+ /* need delay */
+ _udelay(200000);
+ /* power on ddr */
+ //aml_update_bits(P_AO_GPIO_O_EN_N, 1 << 3, 0);
+ //aml_update_bits(P_AO_GPIO_O_EN_N, 1 << 19, 1 << 19);
+ writel((readl(P_AO_GPIO_O_EN_N) | (1 << 19)),P_AO_GPIO_O_EN_N);
+ _udelay(40000);
+ }
+
+ panel_power_init();
+}
diff --git a/board/amlogic/gxtvbb_p301_v1/firmware/power.c b/board/amlogic/gxtvbb_p301_v1/firmware/power.c
new file mode 100644
index 0000000..33b922d
--- /dev/null
+++ b/board/amlogic/gxtvbb_p301_v1/firmware/power.c
@@ -0,0 +1,221 @@
+
+/*
+ * board/amlogic/gxtvbb_p301_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140},
+};
+
+#define P_PIN_MUX_AO (*((volatile unsigned *)(0xc8100000 + (0x05 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xda834400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#ifdef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_MISC_REG_AB
+#endif
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#ifdef P_AO_PWM_PWM_B
+#undef P_AO_PWM_PWM_B
+#endif
+#define P_AO_PWM_PWM_B (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_A, PWM_AO_B,PWM_F
+ */
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~((1 << 12)|(1<<14)|(1<<22));
+ P_PIN_MUX_REG10 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg |= (1 << 21); // enable PWM_A
+ P_PIN_MUX_REG10 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1)|(1<<0));
+
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_AO_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 21); // enable PWM_AO_B
+ P_PIN_MUX_AO = reg;
+
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1) |(1 << 0));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 22); // enable PWM_f
+ P_PIN_MUX_AO = reg;
+
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+
+ //serial_put_dec( pwm_voltage_table[to][1]);
+ //serial_puts(" mv\n");
+
+ //serial_put_dec( pwm_voltage_table[to][0]);
+ //serial_puts(" mv\n");
+
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ P_AO_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_f:
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vddee enable AO_8 to low\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~((1 << 8)|(1 << 24));
+ writel(reg, AO_GPIO_O_EN_N);
+ serial_puts("set vddee enable AO_2 to low\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~((1 << 2)|(1 << 18));
+ writel(reg, AO_GPIO_O_EN_N);
+}
diff --git a/board/amlogic/gxtvbb_p301_v1/firmware/scp_task/aml_led_pwm.c b/board/amlogic/gxtvbb_p301_v1/firmware/scp_task/aml_led_pwm.c
new file mode 100644
index 0000000..a6fabf4
--- /dev/null
+++ b/board/amlogic/gxtvbb_p301_v1/firmware/scp_task/aml_led_pwm.c
@@ -0,0 +1,181 @@
+#include <amlogic/aml_led.h>
+
+#define LED_DEFAULT_PWM_FREQ 100000
+#define FIN_FREQ (24 * 1000)
+#define DUTY_MAX 1024
+
+static struct aml_led pwm_led;
+static unsigned int ledmode = -1;
+
+static int pwm_calc(int duty, unsigned int pwm_freq, unsigned int *setting)
+{
+ unsigned int div;
+ unsigned int pwm_cnt;
+ unsigned int pwm_lo, pwm_hi;
+
+ if (duty < 0)
+ duty = 0;
+ else if (duty > DUTY_MAX)
+ duty = DUTY_MAX;
+
+ for (div = 0; div < 0x7f; div++) {
+ pwm_cnt = FIN_FREQ * 1000 / (pwm_freq * (div + 1)) - 2;
+ if (pwm_cnt <= 0xffff)
+ break;
+ }
+
+ if (duty == 0) {
+ pwm_hi = 0;
+ pwm_lo = pwm_cnt;
+ }
+ else if (duty == DUTY_MAX) {
+ pwm_hi = pwm_cnt;
+ pwm_lo = 0;
+ }
+ else {
+ pwm_hi = pwm_cnt * duty;
+ pwm_hi /= DUTY_MAX;
+ pwm_lo = pwm_cnt - pwm_hi;
+ }
+
+ setting[0] = div;
+ setting[1] = pwm_lo;
+ setting[2] = pwm_hi;
+ return 0;
+}
+
+/*
+static void pled_gpio_ctrl(int on)
+{
+ unsigned int value;
+
+ value = readl(AO_RTI_PIN_MUX_REG);
+ value &= ~(3<<19);
+ writel(value, AO_RTI_PIN_MUX_REG);
+ value = readl(AO_GPIO_O_EN_N);
+ value &= ~((1<<11)|(1<<27));
+#ifdef CONFIG_LED_PWM_INVERT
+ on = !on;
+#endif
+ value |= (on<<27);
+ //printf("on=%d, value=0x%x\n", on, value);
+ writel(value, AO_GPIO_O_EN_N);
+}
+*/
+
+static void pled_mux_to_pwm(void)
+{
+ unsigned int value;
+ // GPIOAO_11 mux as PWM_AO_A
+ value = readl(AO_RTI_PIN_MUX_REG);
+ value |= (1<<19);
+ value &= ~(1<<20);
+ writel(value, AO_RTI_PIN_MUX_REG);
+}
+
+static void pled_set_brightness(int brightness)
+{
+ unsigned int value;
+ unsigned int setting[3] = {0};
+
+#ifdef CONFIG_LED_PWM_INVERT
+ brightness = DUTY_MAX - brightness;
+#endif
+ pwm_calc(brightness, LED_DEFAULT_PWM_FREQ, &setting[0]);
+
+ value = readl(AO_PWM_MISC_REG_AB);
+ // clk div
+ value &= ~(0x7f<<8);
+ value |= (setting[0]<<8);
+ //clk enable
+ value |= 1<<15;
+ writel(value, AO_PWM_MISC_REG_AB);
+ // duty cycle
+ writel((setting[2] << 16) | setting[1], AO_PWM_PWM_A);
+
+ // enable PWM_AO_A
+ value = readl(AO_PWM_MISC_REG_AB);
+ value |= 0x3;
+ writel(value, AO_PWM_MISC_REG_AB);
+}
+
+static struct coord breath_inflections[]= {
+ {0, 0},
+ {1000, 80},
+ {2000, 256},
+ {2500, 512},
+ {3000, 1024},
+ {3200, 1024},
+ {4200, 512},
+ {5200, 256},
+ {7200, 80},
+ {9200, 0},
+ {9400, 0},
+};
+
+struct aml_led_config pled_config = {
+ .off_brightness = 0,
+ .on_brightness = DUTY_MAX,
+ .flash_off_brightness = 0,
+ .flash_off_time = 350,
+ .flash_on_brightness = DUTY_MAX,
+ .flash_on_time = 400,
+ .breath_inflections = breath_inflections,
+ .breath_inflections_num = 11,
+ .set_brightness = pled_set_brightness,
+};
+
+/*
+ * for suspend
+ */
+void pled_suspend_init(void)
+{
+ if (ledmode == -1)
+ return;
+ pled_mux_to_pwm();
+ aml_led_init(&pwm_led, &pled_config);
+ //if (lwm_get_suspend(ledmode) == SHUTDOWN_MODE)
+ aml_led_event(&pwm_led, LED_EVENT_FLASH, 3);
+ if (lwm_get_standby(ledmode) == LWM_ON)
+ aml_led_event(&pwm_led, LED_EVENT_ON, 0);
+ else if(lwm_get_standby(ledmode) == LWM_FLASH)
+ aml_led_event(&pwm_led, LED_EVENT_FLASH, 0);
+ else if(lwm_get_standby(ledmode) == LWM_BREATH)
+ aml_led_event(&pwm_led, LED_EVENT_BREATH, 0);
+ else
+ aml_led_event(&pwm_led, LED_EVENT_OFF, 0);
+}
+
+void pled_suspend_timer_proc(void)
+{
+ if (ledmode == -1)
+ return;
+ aml_led_timer_proc(&pwm_led);
+}
+
+/*
+ * for scp
+ */
+static void pled_scp_init(int mode)
+{
+ ledmode = mode;
+ pled_mux_to_pwm();
+}
+
+static void pled_scp_timer_proc(int count)
+{
+ int mod = 2;
+
+ if (lwm_get_suspend(ledmode) == RECOVERY_MODE)
+ mod = 3;
+ if (count%mod)
+ pled_set_brightness(pled_config.flash_on_brightness);
+ else
+ pled_set_brightness(pled_config.flash_off_brightness);
+}
+
+struct scp_led pwm_scp_led = {
+ .count = 0,
+ .init = pled_scp_init,
+ .timer_proc = pled_scp_timer_proc,
+};
diff --git a/board/amlogic/gxtvbb_p301_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxtvbb_p301_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..6415a07
--- /dev/null
+++ b/board/amlogic/gxtvbb_p301_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,182 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+#if 0
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#endif
+static int pwm_voltage_table[][2] = {
+ { 0x170005, 910},
+ { 0x130009, 950},
+ { 0x0f000d, 990},
+ { 0x0b0011, 1030},
+ { 0x090013, 1050},
+ { 0x070015, 1070},
+ { 0x040018, 1100},
+};
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 1000+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1020+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1536000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1800000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xc8834400 + ( 0x36 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(0x00405000);
+ reg |= (1 << 21); // enable PWM_A
+ P_PIN_MUX_REG10 = reg;
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+}
+
diff --git a/board/amlogic/gxtvbb_p301_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxtvbb_p301_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..8724a74
--- /dev/null
+++ b/board/amlogic/gxtvbb_p301_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,447 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#ifdef CONFIG_AML_LED
+#include <aml_led.c>
+#include <aml_led_pwm.c>
+#endif
+#include <config.h>
+#define ON 1
+#define OFF 0
+static unsigned int pwm_voltage_table[][2] = {
+ {0x180004, 900},
+ {0x040018, 1100},
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_off_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 5, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 21, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 5, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 21, 1 << 21);
+}
+
+static void power_off_at_clk81(void)
+{
+ power_off_3v3_5v();
+ power_off_usb5v();
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ power_on_usb5v();
+ power_on_3v3_5v();
+ _udelay(10000);
+ _udelay(10000);
+ _udelay(10000);
+ _udelay(10000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+#if 0
+ if (suspend_from == SYS_POWEROFF) {
+ power_switch_to_ee(ON);
+ }
+#endif
+}
+
+static void power_off_at_24M(void)
+{
+}
+
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 3, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 19, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 3, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 19, 1 << 19);
+ _udelay(10000);
+}
+
+static void power_off_ee(void)
+{
+ return;
+ power_switch_to_ee(OFF);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 1 << 24);
+}
+
+static void power_on_ee(void)
+{
+ return;
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 0);
+ _udelay(10000);
+ _udelay(10000);
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_ee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_on_ddr();
+ power_on_ee();
+
+ }
+}
+
+static void wakeup_timer_setup(void)
+{
+ /* 1ms resolution */
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3 << 0) | (0x1 << 12) | (0x1 << 16));
+ writel(value, P_ISA_TIMER_MUX);
+ writel(9, P_ISA_TIMERA);
+}
+
+static void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1 << 12) | (0x1 << 16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+
+static void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ unsigned i = 0;
+
+ p->gpio_info_count = i;
+ p->status = RESPONSE_OK;
+ val = (AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC);
+#ifdef CONFIG_BT_WAKEUP
+ val |= BT_WAKEUP_SRC;
+#endif
+
+#ifdef CONFIG_CEC_WAKEUP
+ val |= CEC_WAKEUP_SRC;
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= WIFI_WAKEUP_SRC;
+#endif
+
+ p->sources = val;
+
+#ifdef CONFIG_BT_WAKEUP
+ {
+ struct wakeup_gpio_info *gpio;
+ /* BT Wakeup: IN: GPIOX[21], OUT: GPIOX[20] */
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP;
+ gpio->gpio_in_idx = GPIOX_21;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = GPIOX_20;
+ gpio->gpio_out_ao = 0;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+ }
+#endif
+
+#ifdef CONFIG_WIFI_WAKEUP
+ if (suspend_from != SYS_POWEROFF) {
+ struct wakeup_gpio_info *gpio;
+ /*WIFI Wakeup: IN: GPIOX[7], OUT: GPIOX[6] */
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = WIFI_WAKEUP;
+ gpio->gpio_in_idx = GPIOX_7;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = GPIOX_6;
+ gpio->gpio_out_ao = 0;
+ gpio->irq = IRQ_GPIO1_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+ }
+#endif
+
+}
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out * 100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+ uart_puts("enter detect key\n");
+
+ _udelay(10000);
+ /* setup wakeup resources */
+ /*auto suspend: timerA 10ms resolution */
+ if (time_out_ms != 0) {
+ wakeup_timer_setup();
+ if (suspend_from == SYS_POWEROFF) {
+ time_out_ms = time_out * 1000;
+ while (1) {
+ _udelay(1000);
+ time_out_ms--;
+ if (time_out_ms == 0)
+ return AUTO_WAKEUP;
+
+ }
+ }
+ }
+ saradc_enable();
+ reset_ao_timera();
+ init_remote();
+#ifdef CONFIG_AML_LED
+ pled_suspend_init();
+#endif
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1; */
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key */
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+#ifdef CONFIG_AML_LED
+ pled_suspend_timer_proc();
+#endif
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+#ifdef CONFIG_BT_WAKEUP
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ & (0x01 << 20)) && (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 20)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 21)))
+ exit_reason = BT_WAKEUP;
+ }
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
+ irq[IRQ_GPIO1] = 0xFFFFFFFF;
+ if (suspend_from) {
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ & (0x01 << 6)) && (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 6)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 7)))
+ exit_reason = WIFI_WAKEUP;
+ }
+ }
+#endif
+ if (exit_reason)
+ break;
+ else
+ asm volatile ("wfi");
+ } while (1);
+ wakeup_timer_clear();
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+#ifdef CONFIG_AML_LED
+ scp_led_register(&pwm_scp_led);
+#endif
+}
diff --git a/board/amlogic/gxtvbb_p301_v1/firmware/timing.c b/board/amlogic/gxtvbb_p301_v1/firmware/timing.c
new file mode 100644
index 0000000..7b0fb1f
--- /dev/null
+++ b/board/amlogic/gxtvbb_p301_v1/firmware/timing.c
@@ -0,0 +1,433 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 50
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+#define CFG_DDR3_DRV DDR3_DRV_40OHM
+#define CFG_DDR3_ODT DDR3_ODT_120OHM
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+ /*
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+*/
+
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 0x10
+#define DDR_RAS_BDL 0
+#define DDR_CAS_BDL 0
+#define DDR_WE_BDL 0
+#define DDR_BA0_BDL 0
+#define DDR_BA1_BDL 0
+#define DDR_BA2_BDL 0
+#define DDR_ACPDD_BDL 0
+#define DDR_CS0_BDL 0
+#define DDR_CS1_BDL 0
+#define DDR_ODT0_BDL 0
+#define DDR_ODT1_BDL 0
+#define DDR_CKE0_BDL 0
+#define DDR_CKE1_BDL 0
+#define DDR_A0_BDL 0
+#define DDR_A1_BDL 0
+#define DDR_A2_BDL 0
+#define DDR_A3_BDL 0
+#define DDR_A4_BDL 0
+#define DDR_A5_BDL 0
+#define DDR_A6_BDL 0
+#define DDR_A7_BDL 0
+#define DDR_A8_BDL 0
+#define DDR_A9_BDL 0
+#define DDR_A10_BDL 0
+#define DDR_A11_BDL 0
+#define DDR_A12_BDL 0
+#define DDR_A13_BDL 0
+#define DDR_A14_BDL 0
+#define DDR_A15_BDL 0
+#endif
+
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_14,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (14),
+ .cfg_ddr_rcd = (14),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (14),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (10),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+ .ddr_size_detect = CONFIG_DDR_SIZE_AUTO_DETECT,
+ .ddr_drv = CFG_DDR3_DRV,
+ .ddr_odt = CFG_DDR3_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00210000,
+ .t_pub_mr = {0},
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x0380c6a0, //PUB PGCR1
+ //.t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ .t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aafe60, //PUB PGCR3
+ .t_pub_dxccr = 0x00181884, //PUB DXCCR
+ .t_pub_dtcr = 0x43003087, //PUB DTCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+ .t_pub_dcr = 0X8B, //PUB DCR
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ .t_pub_dsgcr = 0x020641f,
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x79, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x79, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x79, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x79, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F21, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = (1<<31)|(0x20<<16)|(0x00<<0)//[B31]hw_exit_idle_en
+ |( 0<<8), //[B10,B9,B8] tfaw_cfg_offset:
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ //.t_pctl0_ppcfg = (0xF0 << 1),
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 1,
+ .t_pctl0_dfitphywrlta = 2,
+ .t_pctl0_dfitrddataen = 3,
+ .t_pctl0_dfitphyrdlat = 16,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype1 = 0x200,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (3 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+ .t_pub_acbdlr0 = 0x1F, //2015.09.21 add for CK0 delay fine tune
+
+ /* v2 added */
+ .t_pub_aclcdlr = 0x10,
+ .t_pub_acbdlr3 = 0,
+ .t_pub_acbdlr4 = 0,
+ .t_pub_acbdlr5 = 0,
+
+ .ddr_func = DDR_FUNC,
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+};
diff --git a/board/amlogic/gxtvbb_p301_v1/gxtvbb_p301_v1.c b/board/amlogic/gxtvbb_p301_v1/gxtvbb_p301_v1.c
new file mode 100644
index 0000000..e01fd63
--- /dev/null
+++ b/board/amlogic/gxtvbb_p301_v1/gxtvbb_p301_v1.c
@@ -0,0 +1,939 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/gxtvbb_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+ #include <asm/arch/io.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#ifdef CONFIG_AML_LED
+#include <asm/arch/mailbox.h>
+#include <amlogic/aml_led.h>
+#endif
+#ifdef CONFIG_AML_SPICC
+#include <dm.h>
+#include <amlogic/spicc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+#ifdef CONFIG_AML_PMU4
+#define AML1220_ADDR 0x35
+#define AML1220_ANALOG_ADDR 0x20
+
+unsigned int pmu4_analog_reg[15] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, /* Reg 0x20 - 0x24 */
+ 0x00, 0x00, 0x00, 0x00, 0x51, /* Reg 0x25 - 0x29 */
+ 0x42, 0x00, 0x42, 0x41, 0x02 /* Reg 0x2a - 0x2e */
+};
+
+#define PMU4_ANALOG_REG_LEN ARRAY_SIZE(pmu4_analog_reg)
+
+int aml_pmu4_read(int add, uint8_t *val)
+{
+ int ret;
+ uint8_t buf[2] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ ,
+ {
+ .addr = AML1220_ADDR,
+ .flags = I2C_M_RD,
+ .len = 1,
+ .buf = val,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ ret = aml_i2c_xfer(msg, 2);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+int aml_pmu4_write(int32_t add, uint8_t val)
+{
+ int ret;
+ uint8_t buf[3] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ buf[2] = val & 0xff;
+ ret = aml_i2c_xfer(msg, 1);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+void pmu4_phy_config(void)
+{
+#if 0
+ int i;
+ uint8_t value;
+ int data;
+ uint8_t data_lo;
+ uint8_t data_hi;
+#endif
+ /* eth ldo */
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+
+ mdelay(10);
+
+ /* pinmux */
+ aml_pmu4_write(0x2c, 0x51);
+ aml_pmu4_write(0x2d, 0x41);
+ aml_pmu4_write(0x20, 0x0);
+ aml_pmu4_write(0x21, 0x3);
+#ifdef EXT_CLK
+ aml_pmu4_write(0x14, 0x01);
+#else
+ aml_pmu4_write(0x14, 0x00);
+#endif
+ aml_pmu4_write(0x15, 0x3f);
+
+ /* pll */
+ aml_pmu4_write(0x78, 0x00);
+ aml_pmu4_write(0x79, 0x05);
+ aml_pmu4_write(0x7a, 0xa1);
+ aml_pmu4_write(0x7b, 0xac);
+ aml_pmu4_write(0x7c, 0x5b);
+ aml_pmu4_write(0x7d, 0xa0);
+ aml_pmu4_write(0x7e, 0x20);
+ aml_pmu4_write(0x7f, 0x49);
+ aml_pmu4_write(0x80, 0xd6);
+ aml_pmu4_write(0x81, 0x0b);
+ aml_pmu4_write(0x82, 0xd1);
+ aml_pmu4_write(0x83, 0x00);
+ /* 24M to 50M */
+ aml_pmu4_write(0x84, 0x55);
+ aml_pmu4_write(0x85, 0x0d);
+
+ /*cfg4- --- cfg 45 */
+ aml_pmu4_write(0x88, 0x0);
+ aml_pmu4_write(0x89, 0x0);
+ aml_pmu4_write(0x8A, 0x22);
+ aml_pmu4_write(0x8B, 0x01);
+ aml_pmu4_write(0x8C, 0xd0);
+ aml_pmu4_write(0x8D, 0x01);
+ aml_pmu4_write(0x8E, 0x00);
+ aml_pmu4_write(0x93, 0x81);
+
+ /* pmu4 phyid = 20142014 */
+ aml_pmu4_write(0x94, 0x14);
+ aml_pmu4_write(0x95, 0x20);
+
+ aml_pmu4_write(0x96, 0x14);
+ aml_pmu4_write(0x97, 0x20);
+
+ /*phyadd & mode */
+#ifdef EXT_CLK
+ aml_pmu4_write(0x98, 0x73);
+#else
+ aml_pmu4_write(0x98, 0x47);
+#endif
+
+ aml_pmu4_write(0x99, 0x61);
+ aml_pmu4_write(0x9a, 0x07);
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+#if 0
+ value = 0;
+ pr_info("--------> read 0x9c\n");
+ while ((value & 0x01) == 0)
+ aml_pmu4_read(0x9c, &value);
+ pr_info("----2----> read 0x9c over!\n");
+#endif
+ aml_pmu4_write(0x9b, 0x00);
+ aml_pmu4_write(0x9b, 0x80);
+ aml_pmu4_write(0x9b, 0x00);
+#if 0
+ printf("phy init though i2c done\n");
+ for (i = 0; i < 0xb0; i++) {
+ aml_pmu4_read(i, &value);
+ printf(" i2c[%x]=0x%x\n", i, value);
+ }
+ printf("phy reg dump though i2c:\n");
+ for (i = 0; i < 0x20; i++) {
+ aml_pmu4_write(0xa6, i);
+ aml_pmu4_read(0xa7, &data_lo);
+ aml_pmu4_read(0xa8, &data_hi);
+ data = (data_hi << 8) | data_lo;
+ printf(" phy[%x]=0x%x\n", i, data);
+ }
+#endif
+}
+
+static int aml_pmu4_reg_init(unsigned int reg_base, unsigned int *val,
+ unsigned int reg_len)
+{
+ int ret = 0;
+ unsigned int i = 0;
+
+ for (i = 0; i < reg_len; i++) {
+ ret = aml_pmu4_write(reg_base + i, val[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int aml_pmu4_power_init(void)
+{
+ int ret;
+ int i = 0;
+ uint8_t value;
+
+ /* pmu4 analog register init */
+ ret = aml_pmu4_reg_init(AML1220_ANALOG_ADDR, &pmu4_analog_reg[0],
+ PMU4_ANALOG_REG_LEN);
+ if (ret < 0)
+ return ret;
+
+ pmu4_phy_config();
+
+ /* enable input 24M clock */
+ setbits_le32(0xc8100634, 0x93);
+
+ do {
+ aml_pmu4_read(0x9c, &value);
+ mdelay(10);
+ } while (((value & 0x01) == 0) && (i++ < 10));
+ if(!(value&0x01)) {
+ printf("WARING: PMU4 PLL not lock!");
+ }
+
+ return 0;
+
+}
+
+void setup_pmu4(void)
+{
+ aml_pmu4_power_init();
+}
+#endif
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ //setup ethernet clk need calibrate to configre
+ setbits_le32(P_PERIPHS_PIN_MUX_8, 0x1fffc000);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+#ifndef CONFIG_AML_PMU4
+ /* hardware reset ethernet phy : gpioz14 connect phyreset pin*/
+ clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 14);
+ clrbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+ udelay(100000);
+ setbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+#endif
+}
+
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_AML_PMU4
+ setup_pmu4();
+#endif
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ ret=readl(P_PREG_PAD_GPIO5_I)&(1<<29)?0:1;
+ printf("ret = %d .",ret);
+ if ((readl(P_PERIPHS_PIN_MUX_8)&(3<<9))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I)&(1<<24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 1
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(PERIPHS_PIN_MUX_7, (1<<19)|(1<<20));
+ //enable I2C MASTER AO pins
+ setbits_le32(PERIPHS_PIN_MUX_7,
+ ((MESON_I2C_MASTER_B_GPIOH_3_BIT) | (MESON_I2C_MASTER_B_GPIOH_4_BIT)));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_B,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_b_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOH_4_REG,
+ .scl_bit = MESON_I2C_MASTER_B_GPIOH_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOH_3_REG,
+ .sda_bit = MESON_I2C_MASTER_B_GPIOH_3_BIT,
+ }
+};
+#if 1
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+#include <asm/arch/usb.h>
+#include <asm/arch/gpio.h>
+struct amlogic_usb_config g_usb_config_GXTVBB_skt={
+ CONFIG_GXTVBB_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXTVBB_USB_PHY2_BASE,
+ CONFIG_GXTVBB_USB_PHY3_BASE,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+#ifdef CONFIG_AML_LED
+static enum led_workmode lwm_get_workmode(char *str)
+{
+ if (!str)
+ return LWM_NULL;
+ else if (!strncmp(str, "off", 3))
+ return LWM_OFF;
+ else if (!strncmp(str, "on", 2))
+ return LWM_ON;
+ else if (!strncmp(str, "flash", 5))
+ return LWM_FLASH;
+ else if (!strncmp(str, "breath", 6))
+ return LWM_BREATH;
+ else
+ return LWM_NULL;
+}
+
+/* options example:
+ * ledmode=standby:on,booting:flash,working:breath
+ */
+static unsigned int lwm_parse_workmode(char *options)
+{
+ char *option;
+ enum led_workmode mode;
+ unsigned int ledmode = 0;
+
+ while ((option = strsep(&options, ",")) != NULL) {
+ if (!strncmp(option, "standby:", 8)) {
+ option += 8;
+ mode = lwm_get_workmode(option);
+ lwm_set_standby(ledmode, mode);
+ }
+
+ if (!strncmp(option, "booting:", 8)) {
+ option += 8;
+ mode = lwm_get_workmode(option);
+ lwm_set_booting(ledmode, mode);
+ }
+
+ if (!strncmp(option, "working:", 8)) {
+ option += 8;
+ mode = lwm_get_workmode(option);
+ lwm_set_working(ledmode, mode);
+ }
+ }
+
+ return ledmode;
+}
+
+/*Need add build config here.*/
+static int send_led_timer_data(void)
+{
+ struct led_timer_strc{
+ unsigned int expires;
+ unsigned int expires_count;
+ unsigned int led_mode;
+ } led_val;
+ char *env, env_buf[64];
+
+ env = getenv("jtag");
+ if (strcmp(env, "disable")) {
+ printf("mux to jtag %s, led unavailable\n", env);
+ return -1;
+ }
+ env = getenv("ledmode");
+ if (!env)
+ return -1;
+ strcpy(env_buf, env);
+ env = env_buf;
+ printf("ledmode=%s\n", env);
+ led_val.led_mode = lwm_parse_workmode(env);
+ lwm_set_suspend(led_val.led_mode, SHUTDOWN_MODE);
+ printf("ledmode=0x%x\n", led_val.led_mode);
+ led_val.expires = 350*1000;
+ if (lwm_get_booting(led_val.led_mode) == LWM_ON)
+ led_val.expires_count = 8; //off-on-off-on-off-on-off-on...
+ else
+ led_val.expires_count = 7; //off-on-off-on-off-on-off...
+
+ if (send_usr_data(SCPI_CL_LED_TIMER,(unsigned int *)&led_val,sizeof(led_val))) {
+ printf("send_led_timer_data send error!...\n");
+ return 0;
+ }
+ return 0;
+}
+#endif
+
+/*USE_HDMI_UART_FUNC*/
+#define HDMI_UART_PORT_NUM 3
+
+struct hdmi_uart_date_io {
+ char *power;
+ char *scl;
+ volatile uint32_t * hdmi_sda_reg;
+ unsigned int hdmi_sda_bit;
+ volatile uint32_t * uart_tx_reg;
+ unsigned int uart_tx_bit;
+ volatile uint32_t * hdmi_scl_reg;
+ unsigned int hdmi_scl_bit;
+ volatile uint32_t * uart_rx_reg;
+ unsigned int uart_rx_bit;
+};
+
+struct hdmi_uart_date_io txl_hdmi_uart_date_io[HDMI_UART_PORT_NUM+1]=
+{
+ {"GPIOW_5" ,"GPIOW_7" ,P_PERIPHS_PIN_MUX_5,25,P_PERIPHS_PIN_MUX_5,13,P_PERIPHS_PIN_MUX_5 ,24 ,P_PERIPHS_PIN_MUX_5,12,},
+ {"GPIOW_9", "GPIOW_11",P_PERIPHS_PIN_MUX_5,21,P_PERIPHS_PIN_MUX_5,11,P_PERIPHS_PIN_MUX_5 ,20 ,P_PERIPHS_PIN_MUX_5,10,},
+ {"GPIOW_13","GPIOW_15",P_PERIPHS_PIN_MUX_5,17,P_PERIPHS_PIN_MUX_5,9, P_PERIPHS_PIN_MUX_5 ,16 ,P_PERIPHS_PIN_MUX_5,8,},
+ {NULL, NULL, 0, 0,P_AO_RTI_PIN_MUX_REG,12,0 , 0 ,P_AO_RTI_PIN_MUX_REG,11,},
+};
+
+struct hdmi_uart_date_io gxtvbb_hdmi_uart_date_io[HDMI_UART_PORT_NUM+1]=
+{
+ {"GPIOW_6" ,"GPIOW_5" ,P_PERIPHS_PIN_MUX_6 ,9 ,P_PERIPHS_PIN_MUX_10,1,P_PERIPHS_PIN_MUX_6 ,10 ,P_PERIPHS_PIN_MUX_6,11,},
+ {"GPIOW_10","GPIOW_9" ,P_PERIPHS_PIN_MUX_6 ,14 ,P_PERIPHS_PIN_MUX_10,2,P_PERIPHS_PIN_MUX_6 ,15 ,P_PERIPHS_PIN_MUX_6,16,},
+ {"GPIOW_14","GPIOW_13",P_PERIPHS_PIN_MUX_6 ,19 ,P_PERIPHS_PIN_MUX_10,3,P_PERIPHS_PIN_MUX_6 ,20 ,P_PERIPHS_PIN_MUX_6,21,},
+ {NULL, NULL, 0, 0 ,P_AO_RTI_PIN_MUX_REG,0,0 , 0 ,P_AO_RTI_PIN_MUX_REG,1,},
+};
+
+struct hdmi_uart_det_io {
+ char *power;
+ char *scl;
+ volatile uint32_t * uart_det_power_reg;
+ unsigned int uart_det_power_bit;
+ unsigned int uart_det_power_need_level;
+ volatile uint32_t * uart_det_scl_reg;
+ unsigned int uart_det_scl_bit;
+ unsigned int uart_det_scl_need_level;
+};
+
+struct hdmi_uart_det_io txl_hdmi_uart_det_io[HDMI_UART_PORT_NUM]=
+{
+ {"GPIOW_5" , "GPIOW_7" , P_PREG_PAD_GPIO4_I , 5 , 0, P_PREG_PAD_GPIO4_I ,7 , 1,},
+ {"GPIOW_9", "GPIOW_11", P_PREG_PAD_GPIO4_I , 9 , 0, P_PREG_PAD_GPIO4_I ,11, 1,},
+ {"GPIOW_13", "GPIOW_15" , P_PREG_PAD_GPIO4_I , 13, 0, P_PREG_PAD_GPIO4_I ,15, 1,},
+};
+
+/* in gxtvbb,use hpd port as (txl)scl port */
+struct hdmi_uart_det_io gxtvbb_hdmi_uart_det_io[HDMI_UART_PORT_NUM]=
+{
+ {"GPIOW_6" ,"GPIOW_5" , P_PREG_PAD_GPIO0_I, 6 , 0, P_PREG_PAD_GPIO0_I ,5 , 1,},
+ {"GPIOW_10","GPIOW_9" , P_PREG_PAD_GPIO0_I, 10, 0, P_PREG_PAD_GPIO0_I ,9 , 1,},
+ {"GPIOW_14","GPIOW_13", P_PREG_PAD_GPIO0_I, 14, 0, P_PREG_PAD_GPIO0_I ,13, 1,},
+};
+
+static void init_hdmi_uart_board(void)
+{
+ int i=0;
+ int pwr_value=0,scl_value=0;
+ int flag=0;
+ struct hdmi_uart_date_io *hdmi_uart_date_io;
+ struct hdmi_uart_det_io *hdmi_uart_det_io;
+
+ if (get_cpu_id().family_id <= MESON_CPU_MAJOR_ID_GXTVBB) {
+ hdmi_uart_det_io = gxtvbb_hdmi_uart_det_io;
+ hdmi_uart_date_io = gxtvbb_hdmi_uart_date_io;
+ /*printf("choose gxtvbb board.\n");*/
+ } else {
+ hdmi_uart_det_io = txl_hdmi_uart_det_io;
+ hdmi_uart_date_io = txl_hdmi_uart_date_io;
+ /*printf("choose txl board.\n");*/
+ }
+
+ for (i=0; i<HDMI_UART_PORT_NUM; i++) {
+ pwr_value = readl(hdmi_uart_det_io[i].uart_det_power_reg) >> hdmi_uart_det_io[i].uart_det_power_bit;
+ pwr_value &= 1;
+ scl_value = readl(hdmi_uart_det_io[i].uart_det_scl_reg) >> hdmi_uart_det_io[i].uart_det_scl_bit;
+ scl_value &= 1;
+
+ if ((pwr_value == hdmi_uart_det_io[i].uart_det_power_need_level)
+ && (scl_value == hdmi_uart_det_io[i].uart_det_scl_need_level)) {
+ flag = 1;
+ break;
+ }
+ }
+
+ if (flag == 1) {
+ printf("switch to %d hdmirx_uart port\n",i);
+ /* clean default uart pinmux */
+ writel(readl(hdmi_uart_date_io[3].uart_tx_reg)&~(1 << hdmi_uart_date_io[3].uart_tx_bit),
+ (volatile void *)hdmi_uart_date_io[3].uart_tx_reg);
+ writel(readl(hdmi_uart_date_io[3].uart_rx_reg)&~(1 << hdmi_uart_date_io[3].uart_rx_bit),
+ (volatile void *)hdmi_uart_date_io[3].uart_rx_reg);
+
+ /* set hdmi_uart pinmux */
+ writel(readl(hdmi_uart_date_io[i].hdmi_sda_reg)&~(1 << hdmi_uart_date_io[i].hdmi_sda_bit),
+ (volatile void *)hdmi_uart_date_io[i].hdmi_sda_reg);
+ writel(readl(hdmi_uart_date_io[i].uart_tx_reg)|(1 << hdmi_uart_date_io[i].uart_tx_bit),
+ (volatile void *)hdmi_uart_date_io[i].uart_tx_reg);
+
+ writel(readl(hdmi_uart_date_io[i].hdmi_scl_reg)&~(1 << hdmi_uart_date_io[i].hdmi_scl_bit),
+ (volatile void *)hdmi_uart_date_io[i].hdmi_scl_reg);
+ writel(readl(hdmi_uart_date_io[i].uart_rx_reg)|(1 << hdmi_uart_date_io[i].uart_rx_bit),
+ (volatile void *)hdmi_uart_date_io[i].uart_rx_reg);
+ }
+}
+/*endif*/
+
+#ifdef CONFIG_AML_SPICC
+/* generic config in arch gpio/clock.c */
+extern int spicc_clk_enable(bool enable);
+extern int spicc_pinctrl_enable(bool enable);
+
+static const struct spicc_platdata spicc_platdata = {
+ .compatible = "amlogic,meson-gx-spicc",
+ .reg = (void __iomem *)0xc1108d80,
+ .clk_rate = 166666666,
+ .clk_enable = spicc_clk_enable,
+ .pinctrl_enable = spicc_pinctrl_enable,
+ /* case one slave without cs: {"no_cs", 0} */
+ .cs_gpio_names = {"GPIOH_9", 0},
+};
+
+U_BOOT_DEVICE(spicc) = {
+ .name = "spicc",
+ .platdata = &spicc_platdata,
+};
+#endif /* CONFIG_AML_SPICC */
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG1)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG1))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+ board_usb_init(&g_usb_config_GXTVBB_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+#ifdef CONFIG_SYS_I2C_AML
+// #ifdef 1
+ board_i2c_init();
+// #endif /*CONFIG_AML_I2C*/
+#endif
+
+ //temp for p301, usb 5V power
+ //run_command("mw 0xc8100024 BFFF3FDF", 0);
+ run_command("gpio s GPIOAO_5", 0);
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+ char* env;
+
+ /*USE_HDMI_UART_FUNC*/
+ env = getenv("hdmiuart_mode");
+ /*printf("hdmiuart_mode env:%s\n",env);*/
+ if (env) {
+ if (!strcmp(env,"open")) {
+ printf("CONFIG_HDMI_UART_BOARD\n");
+ init_hdmi_uart_board();
+ }
+ }
+ /*endif*/
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+ vpp_init();
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG1))
+ aml_try_factory_usb_burning(1, gd->bd);
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_LED
+ send_led_timer_data();
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int boardid = 0;
+ char loc_name[64] = {0};
+ boardid = (readl(AO_SEC_GP_CFG0)>>8)&0xff;
+ printf("%s: boardid = 0x%x\n", __func__,boardid);
+
+ switch (boardid) {
+ case 0:
+ strcpy(loc_name, "gxtvbb_p301_1g\0");
+ break;
+ case 8:
+ strcpy(loc_name, "gxtvbb_p300_2g\0");
+ break;
+ case 12:
+ strcpy(loc_name, "gxtvbb_skt_2g\0");
+ break;
+ default:
+ printf("boardid: 0x%x, multi-dt doesn't support\n", boardid);
+ //strcpy(loc_name, "gxb_p200_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
+
diff --git a/board/amlogic/gxtvbb_p301_v1/lcd.c b/board/amlogic/gxtvbb_p301_v1/lcd.c
new file mode 100755
index 0000000..33d1ae5
--- /dev/null
+++ b/board/amlogic/gxtvbb_p301_v1/lcd.c
@@ -0,0 +1,355 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOX_3",
+ "GPIOX_2",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,50,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_3d_disable[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_CPU, 1,0,10,}, /* 3d_disable */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_3d_disable[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,30,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 1,2,0,}, /* 3d_disable */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOAO_4",
+ "GPIOY_13",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* AOC: public Platform lvds : 1920x1080@60hz 8bit pixel clk@74.25mhz 2prot*/
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_3d_disable, lcd_power_off_step_3d_disable,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{7, 0x00001800}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{7, 0x00000603}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{10, 0x00800000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{10, 0x0100a000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/gxtvbb_p310_v1/Kconfig b/board/amlogic/gxtvbb_p310_v1/Kconfig
new file mode 100644
index 0000000..059a949
--- /dev/null
+++ b/board/amlogic/gxtvbb_p310_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GXTV
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxtvbb_p310_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxtvbb"
+
+config SYS_CONFIG_NAME
+ default "gxtvbb_p310_v1"
+
+endif
diff --git a/board/amlogic/gxtvbb_p310_v1/Makefile b/board/amlogic/gxtvbb_p310_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/gxtvbb_p310_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/gxtvbb_p310_v1/aml-user-key.sig b/board/amlogic/gxtvbb_p310_v1/aml-user-key.sig
new file mode 100755
index 0000000..6b51b19
--- /dev/null
+++ b/board/amlogic/gxtvbb_p310_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxtvbb_p310_v1/eth_setup.c b/board/amlogic/gxtvbb_p310_v1/eth_setup.c
new file mode 100644
index 0000000..c5503c3
--- /dev/null
+++ b/board/amlogic/gxtvbb_p310_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxtvbb_p310_v1/firmware/board_init.c b/board/amlogic/gxtvbb_p310_v1/firmware/board_init.c
new file mode 100644
index 0000000..7ad9da6
--- /dev/null
+++ b/board/amlogic/gxtvbb_p310_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxtvbb_p310_v1/firmware/power.c b/board/amlogic/gxtvbb_p310_v1/firmware/power.c
new file mode 100644
index 0000000..7758e4c
--- /dev/null
+++ b/board/amlogic/gxtvbb_p310_v1/firmware/power.c
@@ -0,0 +1,246 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140},
+};
+
+#define P_PIN_MUX_AO (*((volatile unsigned *)(0xc8100000 + (0x05 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xda834400 + (0x36 << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_E (*((volatile unsigned *)(0xc1100000 + (0x21b0 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#define P_AO_OUTPUT_EN (*((volatile unsigned *)(0xc8100000 + (0x09 << 2))))
+
+#ifdef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_MISC_REG_AB
+#endif
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#ifdef P_AO_PWM_PWM_B
+#undef P_AO_PWM_PWM_B
+#endif
+#define P_AO_PWM_PWM_B (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_A, PWM_AO_B,PWM_F
+ */
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~((1 << 12)|(1<<14)|(1<<22));
+ P_PIN_MUX_REG10 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg |= (1 << 21); // enable PWM_A
+ P_PIN_MUX_REG10 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1)|(1<<0));
+
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_AO_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 21); // enable PWM_AO_B
+ P_PIN_MUX_AO = reg;
+ break;
+
+ case pwm_e:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 1) |(1 << 0));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_E = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG7;
+ reg &= ~((1 << 26)| (1 << 18)|(1 << 30));
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG7;
+ reg |= (1 << 29); // enable PWM_E
+ P_PIN_MUX_REG7 = reg;
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1) |(1 << 0));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 22); // enable PWM_f
+ P_PIN_MUX_AO = reg;
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+
+ //serial_put_dec( pwm_voltage_table[to][1]);
+ //serial_puts(" mv\n");
+
+ //serial_put_dec( pwm_voltage_table[to][0]);
+ //serial_puts(" mv\n");
+
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ P_AO_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_e:
+ P_PWM_PWM_E = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_f:
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+static void power_on_3v3_5v(void)
+{
+ unsigned int val = P_AO_OUTPUT_EN;
+ val = val & (~(1 << 2));
+ val = val & (~(1 << 18));
+ P_AO_OUTPUT_EN = val;
+}
+void power_init(int mode)
+{
+
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_e, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_e);
+ pwm_init(pwm_ao_b);
+ power_on_3v3_5v();
+}
diff --git a/board/amlogic/gxtvbb_p310_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxtvbb_p310_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..82b8264
--- /dev/null
+++ b/board/amlogic/gxtvbb_p310_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,175 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 1000+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1020+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1536000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1800000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_E (*((volatile unsigned *)(0xc1100000 + (0x21b0 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 1) |(1 << 0));
+ P_PWM_MISC_REG_EF = reg;
+
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_E = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG7;
+ reg &= ~((1 << 26)| (1 << 18)|(1 << 30));
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG7;
+ reg |= (1 << 29); // enable PWM_E
+ P_PIN_MUX_REG7 = reg;
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_E;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_E = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_E = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+}
+
diff --git a/board/amlogic/gxtvbb_p310_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxtvbb_p310_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..726f5dc
--- /dev/null
+++ b/board/amlogic/gxtvbb_p310_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,306 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+#include <config.h>
+
+static unsigned int pwm_voltage_table[][2] = {
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140},
+};
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ uart_puts("set vddee to 0x");
+ uart_put_hex(voltage, 16);
+ uart_puts("mv\n");
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[to][0];
+ break;
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+
+/*p310:GPIOAO_2: L= POWER on mode, H = standby mode*/
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<18, 1<<18);
+}
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<18, 0);
+}
+
+/*p310 GPIOAO_3 powr on :1, standby :0*/
+static void power_off_vcck(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<3, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<19, 0);
+}
+static void power_on_vcck(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<3, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<19, 1<<19);
+}
+
+
+static void power_off_at_clk81(void)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); // reduce power
+ power_off_3v3_5v();
+ power_off_vcck();
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ power_on_vcck();
+ power_on_3v3_5v();
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+}
+static void power_on_at_32k(unsigned int suspend_from)
+{
+}
+
+static void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ writel(9, P_ISA_TIMERA);
+}
+static void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+
+static void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ p->gpio_info_count = 0;
+ p->status = RESPONSE_OK;
+ val = (AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC);
+
+#ifdef CONFIG_CEC_WAKEUP
+ val |= CEC_WAKEUP_SRC;
+#endif
+
+ p->sources = val;
+
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ saradc_enable();
+ reset_ao_timera();
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/gxtvbb_p310_v1/firmware/timing.c b/board/amlogic/gxtvbb_p310_v1/firmware/timing.c
new file mode 100644
index 0000000..ef65446
--- /dev/null
+++ b/board/amlogic/gxtvbb_p310_v1/firmware/timing.c
@@ -0,0 +1,390 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 50
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+#define CFG_DDR3_DRV DDR3_DRV_40OHM
+#define CFG_DDR3_ODT DDR3_ODT_120OHM
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_14,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (14),
+ .cfg_ddr_rcd = (14),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (14),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (10),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 0,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+ .ddr_size_detect = CONFIG_DDR_SIZE_AUTO_DETECT,
+ .ddr_drv = CFG_DDR3_DRV,
+ .ddr_odt = CFG_DDR3_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00210000,
+ .t_pub_mr = {0},
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x0380c6a0, //PUB PGCR1
+ //.t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ .t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aafe60, //PUB PGCR3
+ .t_pub_dxccr = 0x00181884, //PUB DXCCR
+ .t_pub_dtcr = 0x43003087, //PUB DTCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+ .t_pub_dcr = 0X8B, //PUB DCR
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ .t_pub_dsgcr = 0x020641f,
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x79, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x79, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x79, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x79, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F21, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = (1<<31)|(0x20<<16)|(0x00<<0)//[B31]hw_exit_idle_en
+ |( 0<<8), //[B10,B9,B8] tfaw_cfg_offset:
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ //.t_pctl0_ppcfg = (0xF0 << 1),
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 1,
+ .t_pctl0_dfitphywrlta = 2,
+ .t_pctl0_dfitrddataen = 3,
+ .t_pctl0_dfitphyrdlat = 16,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype1 = 0x200,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (3 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+ .t_pub_acbdlr0 = 0, //2015.09.21 add for CK0 delay fine tune
+
+ .ddr_func = DDR_FUNC,
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+};
diff --git a/board/amlogic/gxtvbb_p310_v1/gxtvbb_p310_v1.c b/board/amlogic/gxtvbb_p310_v1/gxtvbb_p310_v1.c
new file mode 100644
index 0000000..1259471
--- /dev/null
+++ b/board/amlogic/gxtvbb_p310_v1/gxtvbb_p310_v1.c
@@ -0,0 +1,674 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/gxtvbb_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+ #include <asm/arch/io.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+#ifdef CONFIG_AML_PMU4
+#define AML1220_ADDR 0x35
+#define AML1220_ANALOG_ADDR 0x20
+
+unsigned int pmu4_analog_reg[15] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, /* Reg 0x20 - 0x24 */
+ 0x00, 0x00, 0x00, 0x00, 0x51, /* Reg 0x25 - 0x29 */
+ 0x42, 0x00, 0x42, 0x41, 0x02 /* Reg 0x2a - 0x2e */
+};
+
+#define PMU4_ANALOG_REG_LEN ARRAY_SIZE(pmu4_analog_reg)
+
+int aml_pmu4_read(int add, uint8_t *val)
+{
+ int ret;
+ uint8_t buf[2] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ ,
+ {
+ .addr = AML1220_ADDR,
+ .flags = I2C_M_RD,
+ .len = 1,
+ .buf = val,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ ret = aml_i2c_xfer(msg, 2);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+int aml_pmu4_write(int32_t add, uint8_t val)
+{
+ int ret;
+ uint8_t buf[3] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ buf[2] = val & 0xff;
+ ret = aml_i2c_xfer(msg, 1);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+void pmu4_phy_config(void)
+{
+#if 0
+ int i;
+ uint8_t value;
+ int data;
+ uint8_t data_lo;
+ uint8_t data_hi;
+#endif
+ /* eth ldo */
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+
+ mdelay(10);
+
+ /* pinmux */
+ aml_pmu4_write(0x2c, 0x51);
+ aml_pmu4_write(0x2d, 0x41);
+ aml_pmu4_write(0x20, 0x0);
+ aml_pmu4_write(0x21, 0x3);
+#ifdef EXT_CLK
+ aml_pmu4_write(0x14, 0x01);
+#else
+ aml_pmu4_write(0x14, 0x00);
+#endif
+ aml_pmu4_write(0x15, 0x3f);
+
+ /* pll */
+ aml_pmu4_write(0x78, 0x06);
+ aml_pmu4_write(0x79, 0x05);
+ aml_pmu4_write(0x7a, 0xa1);
+ aml_pmu4_write(0x7b, 0xac);
+ aml_pmu4_write(0x7c, 0x5b);
+ aml_pmu4_write(0x7d, 0xa0);
+ aml_pmu4_write(0x7e, 0x20);
+ aml_pmu4_write(0x7f, 0x49);
+ aml_pmu4_write(0x80, 0xd6);
+ aml_pmu4_write(0x81, 0x0b);
+ aml_pmu4_write(0x82, 0xd1);
+ aml_pmu4_write(0x83, 0x00);
+ aml_pmu4_write(0x84, 0x00);
+ aml_pmu4_write(0x85, 0x00);
+
+ /*cfg4- --- cfg 45 */
+ aml_pmu4_write(0x88, 0x0);
+ aml_pmu4_write(0x89, 0x0);
+ aml_pmu4_write(0x8A, 0x22);
+ aml_pmu4_write(0x8B, 0x01);
+ aml_pmu4_write(0x8C, 0xd0);
+ aml_pmu4_write(0x8D, 0x01);
+ aml_pmu4_write(0x8E, 0x00);
+ aml_pmu4_write(0x93, 0x81);
+
+ /* pmu4 phyid = 20142014 */
+ aml_pmu4_write(0x94, 0x14);
+ aml_pmu4_write(0x95, 0x20);
+
+ aml_pmu4_write(0x96, 0x14);
+ aml_pmu4_write(0x97, 0x20);
+
+ /*phyadd & mode */
+#ifdef EXT_CLK
+ aml_pmu4_write(0x98, 0x73);
+#else
+ aml_pmu4_write(0x98, 0x47);
+#endif
+
+ aml_pmu4_write(0x99, 0x61);
+ aml_pmu4_write(0x9a, 0x07);
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+#if 0
+ value = 0;
+ pr_info("--------> read 0x9c\n");
+ while ((value & 0x01) == 0)
+ aml_pmu4_read(0x9c, &value);
+ pr_info("----2----> read 0x9c over!\n");
+#endif
+ aml_pmu4_write(0x9b, 0x00);
+ aml_pmu4_write(0x9b, 0x80);
+ aml_pmu4_write(0x9b, 0x00);
+#if 0
+ printf("phy init though i2c done\n");
+ for (i = 0; i < 0xb0; i++) {
+ aml_pmu4_read(i, &value);
+ printf(" i2c[%x]=0x%x\n", i, value);
+ }
+ printf("phy reg dump though i2c:\n");
+ for (i = 0; i < 0x20; i++) {
+ aml_pmu4_write(0xa6, i);
+ aml_pmu4_read(0xa7, &data_lo);
+ aml_pmu4_read(0xa8, &data_hi);
+ data = (data_hi << 8) | data_lo;
+ printf(" phy[%x]=0x%x\n", i, data);
+ }
+#endif
+}
+
+static int aml_pmu4_reg_init(unsigned int reg_base, unsigned int *val,
+ unsigned int reg_len)
+{
+ int ret = 0;
+ unsigned int i = 0;
+
+ for (i = 0; i < reg_len; i++) {
+ ret = aml_pmu4_write(reg_base + i, val[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int aml_pmu4_power_init(void)
+{
+ int ret;
+
+ /* pmu4 analog register init */
+ ret = aml_pmu4_reg_init(AML1220_ANALOG_ADDR, &pmu4_analog_reg[0],
+ PMU4_ANALOG_REG_LEN);
+ if (ret < 0)
+ return ret;
+
+ pmu4_phy_config();
+
+ return 0;
+
+}
+
+void setup_pmu4(void)
+{
+ aml_pmu4_power_init();
+}
+#endif
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ //setup ethernet clk need calibrate to configre
+ setbits_le32(P_PERIPHS_PIN_MUX_8, 0x1fff8000);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 1;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 1;
+ eth_reg0.b.rgmii_tx_clk_ratio = 4;
+ eth_reg0.b.phy_ref_clk_enable = 1;
+ eth_reg0.b.clk_rmii_i_invert = 0;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rgmii mode
+ setbits_le32(P_PREG_ETH_REG1, 0x20000);// rx delay
+
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+#ifndef CONFIG_AML_PMU4
+ /* hardware reset ethernet phy : gpioz6 connect phyreset pin*/
+ clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 6);
+ clrbits_le32(PREG_PAD_GPIO3_O, 1 << 6);
+ udelay(100000);
+ setbits_le32(PREG_PAD_GPIO3_O, 1 << 6);
+#endif
+}
+
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_AML_PMU4
+ setup_pmu4();
+#endif
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RGMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ ret=readl(P_PREG_PAD_GPIO5_I)&(1<<29)?0:1;
+ printf("ret = %d .",ret);
+ if ((readl(P_PERIPHS_PIN_MUX_8)&(3<<9))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I)&(1<<24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 1
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(PERIPHS_PIN_MUX_7, (1<<19)|(1<<20));
+ //enable I2C MASTER AO pins
+ setbits_le32(PERIPHS_PIN_MUX_7,
+ ((MESON_I2C_MASTER_B_GPIOH_3_BIT) | (MESON_I2C_MASTER_B_GPIOH_4_BIT)));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_B,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_b_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOH_4_REG,
+ .scl_bit = MESON_I2C_MASTER_B_GPIOH_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOH_3_REG,
+ .sda_bit = MESON_I2C_MASTER_B_GPIOH_3_BIT,
+ }
+};
+#if 1
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+#include <asm/arch/usb.h>
+#include <asm/arch/gpio.h>
+struct amlogic_usb_config g_usb_config_GXTVBB_skt={
+ CONFIG_GXTVBB_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXTVBB_USB_PHY2_BASE,
+ CONFIG_GXTVBB_USB_PHY3_BASE,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+ board_usb_init(&g_usb_config_GXTVBB_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+#ifdef CONFIG_SYS_I2C_AML
+// #ifdef 1
+ board_i2c_init();
+// #endif /*CONFIG_AML_I2C*/
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+ run_command("setenv fdt_high 0x20000000", 1);
+ run_command("setenv dtb_mem_addr 0x1000000", 1);
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+ vpp_init();
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int boardid = 0;
+ char loc_name[64] = {0};
+ boardid = (readl(AO_SEC_GP_CFG0)>>8)&0xff;
+ printf("%s: boardid = 0x%x\n", __func__,boardid);
+
+ switch (boardid) {
+ case 0:
+ strcpy(loc_name, "gxtvbb_p301_1g\0");
+ break;
+ case 8:
+ strcpy(loc_name, "gxtvbb_p300_2g\0");
+ break;
+ case 12:
+ strcpy(loc_name, "gxtvbb_skt_2g\0");
+ break;
+ default:
+ printf("boardid: 0x%x, multi-dt doesn't support\n", boardid);
+ //strcpy(loc_name, "gxb_p200_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
+
diff --git a/board/amlogic/gxtvbb_p310_v1/lcd.c b/board/amlogic/gxtvbb_p310_v1/lcd.c
new file mode 100755
index 0000000..d4df429
--- /dev/null
+++ b/board/amlogic/gxtvbb_p310_v1/lcd.c
@@ -0,0 +1,328 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOX_3",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,},
+ {LCD_POWER_TYPE_MAX, 0,0,0,},
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,},
+ {LCD_POWER_TYPE_MAX, 0,0,0,},
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOAO_4",
+ "GPIOY_13",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* AOC: public Platform lvds : 1920x1080@60hz 8bit pixel clk@74.25mhz 2prot*/
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{7, 0x00001800}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{7, 0x00000603}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{10, 0x00800000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{10, 0x0100a000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/gxtvbb_p311_v1/Kconfig b/board/amlogic/gxtvbb_p311_v1/Kconfig
new file mode 100644
index 0000000..75dc788
--- /dev/null
+++ b/board/amlogic/gxtvbb_p311_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GXTV
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxtvbb_p311_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxtvbb"
+
+config SYS_CONFIG_NAME
+ default "gxtvbb_p311_v1"
+
+endif
diff --git a/board/amlogic/gxtvbb_p311_v1/Makefile b/board/amlogic/gxtvbb_p311_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/gxtvbb_p311_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/gxtvbb_p311_v1/aml-user-key.sig b/board/amlogic/gxtvbb_p311_v1/aml-user-key.sig
new file mode 100644
index 0000000..6b51b19
--- /dev/null
+++ b/board/amlogic/gxtvbb_p311_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxtvbb_p311_v1/eth_setup.c b/board/amlogic/gxtvbb_p311_v1/eth_setup.c
new file mode 100644
index 0000000..c5503c3
--- /dev/null
+++ b/board/amlogic/gxtvbb_p311_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxtvbb_p311_v1/firmware/board_init.c b/board/amlogic/gxtvbb_p311_v1/firmware/board_init.c
new file mode 100644
index 0000000..7ad9da6
--- /dev/null
+++ b/board/amlogic/gxtvbb_p311_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxtvbb_p311_v1/firmware/power.c b/board/amlogic/gxtvbb_p311_v1/firmware/power.c
new file mode 100644
index 0000000..1c69e56
--- /dev/null
+++ b/board/amlogic/gxtvbb_p311_v1/firmware/power.c
@@ -0,0 +1,237 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140},
+};
+
+#define P_PIN_MUX_AO (*((volatile unsigned *)(0xc8100000 + (0x05 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xda834400 + (0x36 << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_E (*((volatile unsigned *)(0xc1100000 + (0x21b0 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#ifdef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_MISC_REG_AB
+#endif
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#ifdef P_AO_PWM_PWM_B
+#undef P_AO_PWM_PWM_B
+#endif
+#define P_AO_PWM_PWM_B (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_A, PWM_AO_B,PWM_F
+ */
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~((1 << 12)|(1<<14)|(1<<22));
+ P_PIN_MUX_REG10 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg |= (1 << 21); // enable PWM_A
+ P_PIN_MUX_REG10 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1)|(1<<0));
+
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_AO_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 21); // enable PWM_AO_B
+ P_PIN_MUX_AO = reg;
+ break;
+
+ case pwm_e:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 1) |(1 << 0));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_E = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG7;
+ reg &= ~((1 << 26)| (1 << 18)|(1 << 30));
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG7;
+ reg |= (1 << 29); // enable PWM_E
+ P_PIN_MUX_REG7 = reg;
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1) |(1 << 0));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 22); // enable PWM_f
+ P_PIN_MUX_AO = reg;
+
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+
+ //serial_put_dec( pwm_voltage_table[to][1]);
+ //serial_puts(" mv\n");
+
+ //serial_put_dec( pwm_voltage_table[to][0]);
+ //serial_puts(" mv\n");
+
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ P_AO_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_e:
+ P_PWM_PWM_E = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_f:
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void power_init(int mode)
+{
+
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_e, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_e);
+ pwm_init(pwm_ao_b);
+}
diff --git a/board/amlogic/gxtvbb_p311_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxtvbb_p311_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..164d0d2
--- /dev/null
+++ b/board/amlogic/gxtvbb_p311_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,175 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 860+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 1000+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1020+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1536000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1800000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_E (*((volatile unsigned *)(0xc1100000 + (0x21b0 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 1) |(1 << 0));
+ P_PWM_MISC_REG_EF = reg;
+
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_E = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG7;
+ reg &= ~((1 << 26)| (1 << 18)|(1 << 30));
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG7;
+ reg |= (1 << 29); // enable PWM_E
+ P_PIN_MUX_REG7 = reg;
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_E;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_E = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_E = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+}
+
diff --git a/board/amlogic/gxtvbb_p311_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxtvbb_p311_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..726f5dc
--- /dev/null
+++ b/board/amlogic/gxtvbb_p311_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,306 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+#include <config.h>
+
+static unsigned int pwm_voltage_table[][2] = {
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140},
+};
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ uart_puts("set vddee to 0x");
+ uart_put_hex(voltage, 16);
+ uart_puts("mv\n");
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[to][0];
+ break;
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+
+/*p310:GPIOAO_2: L= POWER on mode, H = standby mode*/
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<18, 1<<18);
+}
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<18, 0);
+}
+
+/*p310 GPIOAO_3 powr on :1, standby :0*/
+static void power_off_vcck(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<3, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<19, 0);
+}
+static void power_on_vcck(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<3, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<19, 1<<19);
+}
+
+
+static void power_off_at_clk81(void)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); // reduce power
+ power_off_3v3_5v();
+ power_off_vcck();
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ power_on_vcck();
+ power_on_3v3_5v();
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+}
+static void power_on_at_32k(unsigned int suspend_from)
+{
+}
+
+static void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ writel(9, P_ISA_TIMERA);
+}
+static void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+
+static void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ p->gpio_info_count = 0;
+ p->status = RESPONSE_OK;
+ val = (AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC);
+
+#ifdef CONFIG_CEC_WAKEUP
+ val |= CEC_WAKEUP_SRC;
+#endif
+
+ p->sources = val;
+
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ saradc_enable();
+ reset_ao_timera();
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ wakeup_timer_clear();
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/gxtvbb_p311_v1/firmware/timing.c b/board/amlogic/gxtvbb_p311_v1/firmware/timing.c
new file mode 100644
index 0000000..ef65446
--- /dev/null
+++ b/board/amlogic/gxtvbb_p311_v1/firmware/timing.c
@@ -0,0 +1,390 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 50
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+#define CFG_DDR3_DRV DDR3_DRV_40OHM
+#define CFG_DDR3_ODT DDR3_ODT_120OHM
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_14,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (14),
+ .cfg_ddr_rcd = (14),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (14),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (10),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 0,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+ .ddr_size_detect = CONFIG_DDR_SIZE_AUTO_DETECT,
+ .ddr_drv = CFG_DDR3_DRV,
+ .ddr_odt = CFG_DDR3_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00210000,
+ .t_pub_mr = {0},
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x0380c6a0, //PUB PGCR1
+ //.t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ .t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aafe60, //PUB PGCR3
+ .t_pub_dxccr = 0x00181884, //PUB DXCCR
+ .t_pub_dtcr = 0x43003087, //PUB DTCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+ .t_pub_dcr = 0X8B, //PUB DCR
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ .t_pub_dsgcr = 0x020641f,
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x79, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x79, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x79, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x79, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F21, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = (1<<31)|(0x20<<16)|(0x00<<0)//[B31]hw_exit_idle_en
+ |( 0<<8), //[B10,B9,B8] tfaw_cfg_offset:
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ //.t_pctl0_ppcfg = (0xF0 << 1),
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 1,
+ .t_pctl0_dfitphywrlta = 2,
+ .t_pctl0_dfitrddataen = 3,
+ .t_pctl0_dfitphyrdlat = 16,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype1 = 0x200,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (3 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+ .t_pub_acbdlr0 = 0, //2015.09.21 add for CK0 delay fine tune
+
+ .ddr_func = DDR_FUNC,
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+};
diff --git a/board/amlogic/gxtvbb_p311_v1/gxtvbb_p311_v1.c b/board/amlogic/gxtvbb_p311_v1/gxtvbb_p311_v1.c
new file mode 100644
index 0000000..21760a3
--- /dev/null
+++ b/board/amlogic/gxtvbb_p311_v1/gxtvbb_p311_v1.c
@@ -0,0 +1,687 @@
+
+/*
+ * board/amlogic/gxtvbb_p311_v1/gxtvbb_p311_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+ #include <asm/arch/io.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+#ifdef CONFIG_AML_PMU4
+#define AML1220_ADDR 0x35
+#define AML1220_ANALOG_ADDR 0x20
+
+unsigned int pmu4_analog_reg[15] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, /* Reg 0x20 - 0x24 */
+ 0x00, 0x00, 0x00, 0x00, 0x51, /* Reg 0x25 - 0x29 */
+ 0x42, 0x00, 0x42, 0x41, 0x02 /* Reg 0x2a - 0x2e */
+};
+
+#define PMU4_ANALOG_REG_LEN ARRAY_SIZE(pmu4_analog_reg)
+
+int aml_pmu4_read(int add, uint8_t *val)
+{
+ int ret;
+ uint8_t buf[2] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ ,
+ {
+ .addr = AML1220_ADDR,
+ .flags = I2C_M_RD,
+ .len = 1,
+ .buf = val,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ ret = aml_i2c_xfer(msg, 2);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+int aml_pmu4_write(int32_t add, uint8_t val)
+{
+ int ret;
+ uint8_t buf[3] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ buf[2] = val & 0xff;
+ ret = aml_i2c_xfer(msg, 1);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+void pmu4_phy_config(void)
+{
+#if 0
+ int i;
+ uint8_t value;
+ int data;
+ uint8_t data_lo;
+ uint8_t data_hi;
+#endif
+ /* eth ldo */
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+
+ mdelay(10);
+
+ /* pinmux */
+ aml_pmu4_write(0x2c, 0x51);
+ aml_pmu4_write(0x2d, 0x41);
+ aml_pmu4_write(0x20, 0x0);
+ aml_pmu4_write(0x21, 0x3);
+#ifdef EXT_CLK
+ aml_pmu4_write(0x14, 0x01);
+#else
+ aml_pmu4_write(0x14, 0x00);
+#endif
+ aml_pmu4_write(0x15, 0x3f);
+
+ /* pll */
+ aml_pmu4_write(0x78, 0x00);
+ aml_pmu4_write(0x79, 0x05);
+ aml_pmu4_write(0x7a, 0xa1);
+ aml_pmu4_write(0x7b, 0xac);
+ aml_pmu4_write(0x7c, 0x5b);
+ aml_pmu4_write(0x7d, 0xa0);
+ aml_pmu4_write(0x7e, 0x20);
+ aml_pmu4_write(0x7f, 0x49);
+ aml_pmu4_write(0x80, 0xd6);
+ aml_pmu4_write(0x81, 0x0b);
+ aml_pmu4_write(0x82, 0xd1);
+ aml_pmu4_write(0x83, 0x00);
+ /* 24M to 50M */
+ aml_pmu4_write(0x84, 0x55);
+ aml_pmu4_write(0x85, 0x0d);
+
+ /*cfg4- --- cfg 45 */
+ aml_pmu4_write(0x88, 0x0);
+ aml_pmu4_write(0x89, 0x0);
+ aml_pmu4_write(0x8A, 0x22);
+ aml_pmu4_write(0x8B, 0x01);
+ aml_pmu4_write(0x8C, 0xd0);
+ aml_pmu4_write(0x8D, 0x01);
+ aml_pmu4_write(0x8E, 0x00);
+ aml_pmu4_write(0x93, 0x81);
+
+ /* pmu4 phyid = 20142014 */
+ aml_pmu4_write(0x94, 0x14);
+ aml_pmu4_write(0x95, 0x20);
+
+ aml_pmu4_write(0x96, 0x14);
+ aml_pmu4_write(0x97, 0x20);
+
+ /*phyadd & mode */
+#ifdef EXT_CLK
+ aml_pmu4_write(0x98, 0x73);
+#else
+ aml_pmu4_write(0x98, 0x47);
+#endif
+
+ aml_pmu4_write(0x99, 0x61);
+ aml_pmu4_write(0x9a, 0x07);
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+#if 0
+ value = 0;
+ pr_info("--------> read 0x9c\n");
+ while ((value & 0x01) == 0)
+ aml_pmu4_read(0x9c, &value);
+ pr_info("----2----> read 0x9c over!\n");
+#endif
+ aml_pmu4_write(0x9b, 0x00);
+ aml_pmu4_write(0x9b, 0x80);
+ aml_pmu4_write(0x9b, 0x00);
+#if 0
+ printf("phy init though i2c done\n");
+ for (i = 0; i < 0xb0; i++) {
+ aml_pmu4_read(i, &value);
+ printf(" i2c[%x]=0x%x\n", i, value);
+ }
+ printf("phy reg dump though i2c:\n");
+ for (i = 0; i < 0x20; i++) {
+ aml_pmu4_write(0xa6, i);
+ aml_pmu4_read(0xa7, &data_lo);
+ aml_pmu4_read(0xa8, &data_hi);
+ data = (data_hi << 8) | data_lo;
+ printf(" phy[%x]=0x%x\n", i, data);
+ }
+#endif
+}
+
+static int aml_pmu4_reg_init(unsigned int reg_base, unsigned int *val,
+ unsigned int reg_len)
+{
+ int ret = 0;
+ unsigned int i = 0;
+
+ for (i = 0; i < reg_len; i++) {
+ ret = aml_pmu4_write(reg_base + i, val[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int aml_pmu4_power_init(void)
+{
+ int ret;
+ int i = 0;
+ uint8_t value;
+
+ /* pmu4 analog register init */
+ ret = aml_pmu4_reg_init(AML1220_ANALOG_ADDR, &pmu4_analog_reg[0],
+ PMU4_ANALOG_REG_LEN);
+ if (ret < 0)
+ return ret;
+
+ pmu4_phy_config();
+
+ /* enable input 24M clock */
+ setbits_le32(0xc8100634, 0x93);
+
+ do {
+ aml_pmu4_read(0x9c, &value);
+ mdelay(10);
+ } while (((value & 0x01) == 0) && (i++ < 10));
+ if (!(value&0x01)) {
+ printf("WARING: PMU4 PLL not lock!");
+ }
+
+ return 0;
+
+}
+
+void setup_pmu4(void)
+{
+ aml_pmu4_power_init();
+}
+#endif
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ //setup ethernet clk need calibrate to configre
+ setbits_le32(P_PERIPHS_PIN_MUX_8, 0x1fff8000);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+#ifndef CONFIG_AML_PMU4
+ /* hardware reset ethernet phy : gpioz6 connect phyreset pin*/
+ clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 6);
+ clrbits_le32(PREG_PAD_GPIO3_O, 1 << 6);
+ udelay(100000);
+ setbits_le32(PREG_PAD_GPIO3_O, 1 << 6);
+#endif
+}
+
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_AML_PMU4
+ setup_pmu4();
+#endif
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ ret=readl(P_PREG_PAD_GPIO5_I)&(1<<29)?0:1;
+ printf("ret = %d .",ret);
+ if ((readl(P_PERIPHS_PIN_MUX_8)&(3<<9))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I)&(1<<24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 1
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(PERIPHS_PIN_MUX_10, (1<<12)|(1<<13)|(1<<21)|(1<<22)|(1<<23)|(1<<24));
+ //enable I2C MASTER AO pins
+ setbits_le32(PERIPHS_PIN_MUX_10,
+ ((MESON_I2C_MASTER_B_GPIOY_12_BIT) | (MESON_I2C_MASTER_B_GPIOY_13_BIT)));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_B,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_b_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOY_13_REG,
+ .scl_bit = MESON_I2C_MASTER_B_GPIOY_13_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOY_12_REG,
+ .sda_bit = MESON_I2C_MASTER_B_GPIOY_12_BIT,
+ }
+};
+#if 1
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+#include <asm/arch/usb.h>
+#include <asm/arch/gpio.h>
+struct amlogic_usb_config g_usb_config_GXTVBB_skt={
+ CONFIG_GXTVBB_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXTVBB_USB_PHY2_BASE,
+ CONFIG_GXTVBB_USB_PHY3_BASE,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+ board_usb_init(&g_usb_config_GXTVBB_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+#ifdef CONFIG_SYS_I2C_AML
+// #ifdef 1
+ board_i2c_init();
+// #endif /*CONFIG_AML_I2C*/
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+
+ /*add board late init function here*/
+ run_command("setenv fdt_high 0x20000000", 1);
+ run_command("setenv dtb_mem_addr 0x1000000", 1);
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+ vpp_init();
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int boardid = 0;
+ char loc_name[64] = {0};
+ boardid = (readl(AO_SEC_GP_CFG0)>>8)&0xff;
+ printf("%s: boardid = 0x%x\n", __func__,boardid);
+
+ switch (boardid) {
+ case 0:
+ strcpy(loc_name, "gxtvbb_p301_1g\0");
+ break;
+ case 8:
+ strcpy(loc_name, "gxtvbb_p300_2g\0");
+ break;
+ case 12:
+ strcpy(loc_name, "gxtvbb_skt_2g\0");
+ break;
+ default:
+ printf("boardid: 0x%x, multi-dt doesn't support\n", boardid);
+ //strcpy(loc_name, "gxb_p200_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
+
diff --git a/board/amlogic/gxtvbb_p311_v1/lcd.c b/board/amlogic/gxtvbb_p311_v1/lcd.c
new file mode 100755
index 0000000..d4df429
--- /dev/null
+++ b/board/amlogic/gxtvbb_p311_v1/lcd.c
@@ -0,0 +1,328 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOX_3",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,},
+ {LCD_POWER_TYPE_MAX, 0,0,0,},
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,},
+ {LCD_POWER_TYPE_MAX, 0,0,0,},
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOAO_4",
+ "GPIOY_13",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* AOC: public Platform lvds : 1920x1080@60hz 8bit pixel clk@74.25mhz 2prot*/
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{7, 0x00001800}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{7, 0x00000603}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{10, 0x00800000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{10, 0x0100a000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/gxtvbb_skt_v1/Kconfig b/board/amlogic/gxtvbb_skt_v1/Kconfig
new file mode 100644
index 0000000..f2b512d
--- /dev/null
+++ b/board/amlogic/gxtvbb_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GXTV
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxtvbb_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxtvbb"
+
+config SYS_CONFIG_NAME
+ default "gxtvbb_skt_v1"
+
+endif
diff --git a/board/amlogic/gxtvbb_skt_v1/Makefile b/board/amlogic/gxtvbb_skt_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/gxtvbb_skt_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/gxtvbb_skt_v1/aml-user-key.sig b/board/amlogic/gxtvbb_skt_v1/aml-user-key.sig
new file mode 100644
index 0000000..6b51b19
--- /dev/null
+++ b/board/amlogic/gxtvbb_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxtvbb_skt_v1/eth_setup.c b/board/amlogic/gxtvbb_skt_v1/eth_setup.c
new file mode 100644
index 0000000..c5503c3
--- /dev/null
+++ b/board/amlogic/gxtvbb_skt_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxtvbb_skt_v1/firmware/board_init.c b/board/amlogic/gxtvbb_skt_v1/firmware/board_init.c
new file mode 100644
index 0000000..7ad9da6
--- /dev/null
+++ b/board/amlogic/gxtvbb_skt_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxtvbb_skt_v1/firmware/power.c b/board/amlogic/gxtvbb_skt_v1/firmware/power.c
new file mode 100644
index 0000000..b9d7e83
--- /dev/null
+++ b/board/amlogic/gxtvbb_skt_v1/firmware/power.c
@@ -0,0 +1,212 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140},
+};
+
+#define P_PIN_MUX_AO (*((volatile unsigned *)(0xc8100000 + (0x05 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xda834400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#ifdef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_MISC_REG_AB
+#endif
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#ifdef P_AO_PWM_PWM_B
+#undef P_AO_PWM_PWM_B
+#endif
+#define P_AO_PWM_PWM_B (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_A, PWM_AO_B,PWM_F
+ */
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~((1 << 12)|(1<<14)|(1<<22));
+ P_PIN_MUX_REG10 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg |= (1 << 21); // enable PWM_A
+ P_PIN_MUX_REG10 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1)|(1<<0));
+
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_AO_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 21); // enable PWM_AO_B
+ P_PIN_MUX_AO = reg;
+
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1) |(1 << 0));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 22); // enable PWM_f
+ P_PIN_MUX_AO = reg;
+
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+
+ //serial_put_dec( pwm_voltage_table[to][1]);
+ //serial_puts(" mv\n");
+
+ //serial_put_dec( pwm_voltage_table[to][0]);
+ //serial_puts(" mv\n");
+
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ P_AO_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_f:
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxtvbb_skt_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxtvbb_skt_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..1c2559e0
--- /dev/null
+++ b/board/amlogic/gxtvbb_skt_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,171 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860),
+ DVFS( 250000000, 860),
+ DVFS( 500000000, 860),
+ DVFS( 667000000, 900),
+ DVFS(1000000000, 940),
+ DVFS(1200000000, 980),
+ DVFS(1296000000, 1000),
+ DVFS(1416000000, 1020),
+ DVFS(1536000000, 1050),
+ DVFS(1800000000, 1050),
+};
+
+
+
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xc8834400 + ( 0x36 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(0x00405000);
+ reg |= (1 << 21); // enable PWM_A
+ P_PIN_MUX_REG10 = reg;
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+}
+
diff --git a/board/amlogic/gxtvbb_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxtvbb_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..6939bb5
--- /dev/null
+++ b/board/amlogic/gxtvbb_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,426 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <config.h>
+
+static unsigned int pwm_voltage_table[][2] = {
+ {0x180004, 900},
+ {0x170005, 910},
+ {0x160006, 920},
+ {0x150007, 930},
+ {0x140008, 940},
+ {0x130009, 950},
+ {0x12000a, 960},
+ {0x11000b, 970},
+ {0x10000c, 980},
+ {0x0f000d, 990},
+ {0x0e000e, 1000},
+ {0x0d000f, 1010},
+ {0x0c0010, 1020},
+ {0x0b0011, 1030},
+ {0x0a0012, 1040},
+ {0x090013, 1050},
+ {0x080014, 1060},
+ {0x070015, 1070},
+ {0x060016, 1080},
+ {0x050017, 1090},
+ {0x040018, 1100},
+ {0x030019, 1110},
+ {0x02001a, 1120},
+ {0x01001b, 1130},
+ {0x00001c, 1140},
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+ return;
+ uart_puts("set vddee to 0x");
+ uart_put_hex(voltage, 16);
+ uart_puts("mv\n");
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[to][0];
+ break;
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_off_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 5, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 21, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 5, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 21, 1 << 21);
+}
+
+static void power_off_at_clk81(void)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); // reduce power
+ power_off_3v3_5v();
+ power_off_usb5v();
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ power_on_usb5v();
+ power_on_3v3_5v();
+ _udelay(6000);
+}
+
+static void power_off_at_24M(void)
+{
+}
+
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 3, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 19, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 3, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 19, 1 << 19);
+}
+
+static void power_off_ee(void)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+ _udelay(100);
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 1 << 24);
+}
+
+static void power_on_ee(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 0);
+ _udelay(10000);
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(500);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_ddr();
+ power_off_ee();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+ if (suspend_from == SYS_POWEROFF) {
+ power_on_ee();
+ power_on_ddr();
+ }
+}
+
+static void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ writel(9, P_ISA_TIMERA);
+}
+static void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+
+static void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ unsigned i = 0;
+
+ p->gpio_info_count = i;
+ p->status = RESPONSE_OK;
+ val = (AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC);
+#ifdef CONFIG_BT_WAKEUP
+ val |= BT_WAKEUP_SRC;
+#endif
+
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= WIFI_WAKEUP_SRC;
+#endif
+
+ p->sources = val;
+
+#ifdef CONFIG_BT_WAKEUP
+ {
+ struct wakeup_gpio_info *gpio;
+ /* BT Wakeup: IN: GPIOX[21], OUT: GPIOX[20] */
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP;
+ gpio->gpio_in_idx = GPIOX_21;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = GPIOX_20;
+ gpio->gpio_out_ao = 0;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+ }
+#endif
+
+#ifdef CONFIG_WIFI_WAKEUP
+ if (suspend_from != SYS_POWEROFF) {
+ struct wakeup_gpio_info *gpio;
+ /*WIFI Wakeup: IN: GPIOX[7], OUT: GPIOX[6] */
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = WIFI_WAKEUP;
+ gpio->gpio_in_idx = GPIOX_7;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = GPIOX_6;
+ gpio->gpio_out_ao = 0;
+ gpio->irq = IRQ_GPIO1_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+ }
+#endif
+
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources */
+ /*auto suspend: timerA 10ms resolution */
+ if (time_out_ms != 0) {
+ wakeup_timer_setup();
+ if (suspend_from == SYS_POWEROFF) {
+ time_out_ms = time_out * 1000;
+ while (1) {
+ _udelay(1000);
+ time_out_ms--;
+ if (time_out_ms == 0)
+ return AUTO_WAKEUP;
+
+ }
+ }
+ }
+ saradc_enable();
+ reset_ao_timera();
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+#ifdef CONFIG_BT_WAKEUP
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ & (0x01 << 20)) && (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 20)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 21)))
+ exit_reason = BT_WAKEUP;
+ }
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
+ irq[IRQ_GPIO1] = 0xFFFFFFFF;
+ if (suspend_from) {
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ & (0x01 << 6)) && (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 6)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 7)))
+ exit_reason = WIFI_WAKEUP;
+ }
+ }
+#endif
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+ wakeup_timer_clear();
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/gxtvbb_skt_v1/firmware/timing.c b/board/amlogic/gxtvbb_skt_v1/firmware/timing.c
new file mode 100644
index 0000000..c6c776e
--- /dev/null
+++ b/board/amlogic/gxtvbb_skt_v1/firmware/timing.c
@@ -0,0 +1,418 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 50
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+#define CFG_DDR3_DRV DDR3_DRV_40OHM
+#define CFG_DDR3_ODT DDR3_ODT_120OHM
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_14,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (14),
+ .cfg_ddr_rcd = (14),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (14),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (10),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 0,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+ .ddr_size_detect = CONFIG_DDR_SIZE_AUTO_DETECT,
+ .ddr_drv = CFG_DDR3_DRV,
+ .ddr_odt = CFG_DDR3_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00210000,
+ .t_pub_mr = {0},
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x0380c6a0, //PUB PGCR1
+ //.t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ .t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aafe60, //PUB PGCR3
+ .t_pub_dxccr = 0x00181884, //PUB DXCCR
+ .t_pub_dtcr = 0x43003087, //PUB DTCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+ .t_pub_dcr = 0X8B, //PUB DCR
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ .t_pub_dsgcr = 0x020641f,
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x59, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x19, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x19, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x19, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F21, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = (1<<31)|(0x20<<16)|(0x80<<0)//[B31]hw_exit_idle_en
+ |( 0<<8), //[B10,B9,B8] tfaw_cfg_offset:
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ //.t_pctl0_ppcfg = (0xF0 << 1),
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 1,
+ .t_pctl0_dfitphywrlta = 2,
+ .t_pctl0_dfitrddataen = 3,
+ .t_pctl0_dfitphyrdlat = 16,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype1 = 0x200,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (3 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+ .t_pub_acbdlr0 = 0, //2015.09.21 add for CK0 delay fine tune
+
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+ .wr_adj_per = { /* dqs tuning demo 2016.01.26 */
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ [6] = 100,
+ [7] = 100,
+ [8] = 100,
+ [9] = 100,
+ [10] = 100,
+ [11] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ [6] = 100,
+ [7] = 100,
+ [8] = 100,
+ [9] = 100,
+ [10] = 100,
+ [11] = 100,
+ },
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+};
diff --git a/board/amlogic/gxtvbb_skt_v1/gxtvbb_skt_v1.c b/board/amlogic/gxtvbb_skt_v1/gxtvbb_skt_v1.c
new file mode 100644
index 0000000..41ecc8b
--- /dev/null
+++ b/board/amlogic/gxtvbb_skt_v1/gxtvbb_skt_v1.c
@@ -0,0 +1,696 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/gxtvbb_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+ #include <asm/arch/io.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <amlogic/spifc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+#ifdef CONFIG_AML_PMU4
+#define AML1220_ADDR 0x35
+#define AML1220_ANALOG_ADDR 0x20
+
+unsigned int pmu4_analog_reg[15] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, /* Reg 0x20 - 0x24 */
+ 0x00, 0x00, 0x00, 0x00, 0x51, /* Reg 0x25 - 0x29 */
+ 0x42, 0x00, 0x42, 0x41, 0x02 /* Reg 0x2a - 0x2e */
+};
+
+#define PMU4_ANALOG_REG_LEN ARRAY_SIZE(pmu4_analog_reg)
+
+int aml_pmu4_read(int add, uint8_t *val)
+{
+ int ret;
+ uint8_t buf[2] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ ,
+ {
+ .addr = AML1220_ADDR,
+ .flags = I2C_M_RD,
+ .len = 1,
+ .buf = val,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ ret = aml_i2c_xfer(msg, 2);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+int aml_pmu4_write(int32_t add, uint8_t val)
+{
+ int ret;
+ uint8_t buf[3] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ buf[2] = val & 0xff;
+ ret = aml_i2c_xfer(msg, 1);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+void pmu4_phy_config(void)
+{
+#if 0
+ int i;
+ uint8_t value;
+ int data;
+ uint8_t data_lo;
+ uint8_t data_hi;
+#endif
+ /* eth ldo */
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+
+ mdelay(10);
+
+ /* pinmux */
+ aml_pmu4_write(0x2c, 0x51);
+ aml_pmu4_write(0x2d, 0x41);
+ aml_pmu4_write(0x20, 0x0);
+ aml_pmu4_write(0x21, 0x3);
+#ifdef EXT_CLK
+ aml_pmu4_write(0x14, 0x01);
+#else
+ aml_pmu4_write(0x14, 0x00);
+#endif
+ aml_pmu4_write(0x15, 0x3f);
+
+ /* pll */
+ aml_pmu4_write(0x78, 0x06);
+ aml_pmu4_write(0x79, 0x05);
+ aml_pmu4_write(0x7a, 0xa1);
+ aml_pmu4_write(0x7b, 0xac);
+ aml_pmu4_write(0x7c, 0x5b);
+ aml_pmu4_write(0x7d, 0xa0);
+ aml_pmu4_write(0x7e, 0x20);
+ aml_pmu4_write(0x7f, 0x49);
+ aml_pmu4_write(0x80, 0xd6);
+ aml_pmu4_write(0x81, 0x0b);
+ aml_pmu4_write(0x82, 0xd1);
+ aml_pmu4_write(0x83, 0x00);
+ aml_pmu4_write(0x84, 0x00);
+ aml_pmu4_write(0x85, 0x00);
+
+ /*cfg4- --- cfg 45 */
+ aml_pmu4_write(0x88, 0x0);
+ aml_pmu4_write(0x89, 0x0);
+ aml_pmu4_write(0x8A, 0x22);
+ aml_pmu4_write(0x8B, 0x01);
+ aml_pmu4_write(0x8C, 0xd0);
+ aml_pmu4_write(0x8D, 0x01);
+ aml_pmu4_write(0x8E, 0x00);
+ aml_pmu4_write(0x93, 0x81);
+
+ /* pmu4 phyid = 20142014 */
+ aml_pmu4_write(0x94, 0x14);
+ aml_pmu4_write(0x95, 0x20);
+
+ aml_pmu4_write(0x96, 0x14);
+ aml_pmu4_write(0x97, 0x20);
+
+ /*phyadd & mode */
+#ifdef EXT_CLK
+ aml_pmu4_write(0x98, 0x73);
+#else
+ aml_pmu4_write(0x98, 0x47);
+#endif
+
+ aml_pmu4_write(0x99, 0x61);
+ aml_pmu4_write(0x9a, 0x07);
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+#if 0
+ value = 0;
+ pr_info("--------> read 0x9c\n");
+ while ((value & 0x01) == 0)
+ aml_pmu4_read(0x9c, &value);
+ pr_info("----2----> read 0x9c over!\n");
+#endif
+ aml_pmu4_write(0x9b, 0x00);
+ aml_pmu4_write(0x9b, 0x80);
+ aml_pmu4_write(0x9b, 0x00);
+#if 0
+ printf("phy init though i2c done\n");
+ for (i = 0; i < 0xb0; i++) {
+ aml_pmu4_read(i, &value);
+ printf(" i2c[%x]=0x%x\n", i, value);
+ }
+ printf("phy reg dump though i2c:\n");
+ for (i = 0; i < 0x20; i++) {
+ aml_pmu4_write(0xa6, i);
+ aml_pmu4_read(0xa7, &data_lo);
+ aml_pmu4_read(0xa8, &data_hi);
+ data = (data_hi << 8) | data_lo;
+ printf(" phy[%x]=0x%x\n", i, data);
+ }
+#endif
+}
+
+static int aml_pmu4_reg_init(unsigned int reg_base, unsigned int *val,
+ unsigned int reg_len)
+{
+ int ret = 0;
+ unsigned int i = 0;
+
+ for (i = 0; i < reg_len; i++) {
+ ret = aml_pmu4_write(reg_base + i, val[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int aml_pmu4_power_init(void)
+{
+ int ret;
+
+ /* pmu4 analog register init */
+ ret = aml_pmu4_reg_init(AML1220_ANALOG_ADDR, &pmu4_analog_reg[0],
+ PMU4_ANALOG_REG_LEN);
+ if (ret < 0)
+ return ret;
+
+ pmu4_phy_config();
+
+ return 0;
+
+}
+
+void setup_pmu4(void)
+{
+ aml_pmu4_power_init();
+}
+#endif
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ //setup ethernet clk need calibrate to configre
+ setbits_le32(P_PERIPHS_PIN_MUX_8, 0x1fffc000);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+#ifndef CONFIG_AML_PMU4
+ /* hardware reset ethernet phy : gpioz14 connect phyreset pin*/
+ clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 14);
+ clrbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+ udelay(100000);
+ setbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+#endif
+}
+
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_AML_PMU4
+ setup_pmu4();
+#endif
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ ret=readl(P_PREG_PAD_GPIO5_I)&(1<<29)?0:1;
+ printf("ret = %d .",ret);
+ if ((readl(P_PERIPHS_PIN_MUX_8)&(3<<9))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I)&(1<<24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 1
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(PERIPHS_PIN_MUX_7, (1<<19)|(1<<20));
+ //enable I2C MASTER AO pins
+ setbits_le32(PERIPHS_PIN_MUX_7,
+ ((MESON_I2C_MASTER_B_GPIOH_3_BIT) | (MESON_I2C_MASTER_B_GPIOH_4_BIT)));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_B,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_b_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOH_4_REG,
+ .scl_bit = MESON_I2C_MASTER_B_GPIOH_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOH_3_REG,
+ .sda_bit = MESON_I2C_MASTER_B_GPIOH_3_BIT,
+ }
+};
+#if 1
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+#include <asm/arch/usb.h>
+#include <asm/arch/gpio.h>
+struct amlogic_usb_config g_usb_config_GXTVBB_skt={
+ CONFIG_GXTVBB_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXTVBB_USB_PHY2_BASE,
+ CONFIG_GXTVBB_USB_PHY3_BASE,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_11: NOR_D:reg5[16], clr none
+ * BOOT_12: NOR_Q:reg5[17], clr none
+ * BOOT_13: NOR_C:reg5[18], clr none
+ * BOOT_18: NOR_CS:reg5[19],clr none
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {71/*BOOT_18*/};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_5);
+ val &= ~((1<<19)|(1<<18)|(1<<17)|(1<<16));
+ if (enable) {
+ val |= (1<<18)|(1<<17)|(1<<16);
+ }
+ writel(val, P_PERIPHS_PIN_MUX_5);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xc1108c80,
+ .mem_map = 0xcc000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+ board_usb_init(&g_usb_config_GXTVBB_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+#ifdef CONFIG_SYS_I2C_AML
+// #ifdef 1
+ board_i2c_init();
+// #endif /*CONFIG_AML_I2C*/
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+ /*add board late init function here*/
+ run_command("setenv fdt_high 0x20000000", 1);
+ run_command("setenv dtb_mem_addr 0x1000000", 1);
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+ vpp_init();
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int boardid = 0;
+ char loc_name[64] = {0};
+ boardid = (readl(AO_SEC_GP_CFG0)>>8)&0xff;
+ printf("%s: boardid = 0x%x\n", __func__,boardid);
+
+ switch (boardid) {
+ case 0:
+ strcpy(loc_name, "gxtvbb_p301_1g\0");
+ break;
+ case 8:
+ strcpy(loc_name, "gxtvbb_p300_2g\0");
+ break;
+ case 12:
+ strcpy(loc_name, "gxtvbb_skt_2g\0");
+ break;
+ default:
+ printf("boardid: 0x%x, multi-dt doesn't support\n", boardid);
+ //strcpy(loc_name, "gxb_p200_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
diff --git a/board/amlogic/gxtvbb_skt_v1/lcd.c b/board/amlogic/gxtvbb_skt_v1/lcd.c
new file mode 100755
index 0000000..0c71183
--- /dev/null
+++ b/board/amlogic/gxtvbb_skt_v1/lcd.c
@@ -0,0 +1,347 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOX_3",
+ "GPIOX_2",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,50,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_3d_disable[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_CPU, 1,0,10,}, /* 3d_disable */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_3d_disable[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,30,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 1,2,0,}, /* 3d_disable */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOAO_4",
+ "GPIOY_13",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* AOC: public Platform lvds : 1920x1080@60hz 8bit pixel clk@74.25mhz 2prot*/
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_3d_disable, lcd_power_off_step_3d_disable,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{7, 0x00001800}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{7, 0x00000603}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 2,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{10, 0x00800000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{10, 0x0100a000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/gxtvbb_t966_skt_v1/Kconfig b/board/amlogic/gxtvbb_t966_skt_v1/Kconfig
new file mode 100644
index 0000000..5877597
--- /dev/null
+++ b/board/amlogic/gxtvbb_t966_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GXTV
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "gxtvbb_t966_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "gxtvbb"
+
+config SYS_CONFIG_NAME
+ default "gxtvbb_t966_skt_v1"
+
+endif
diff --git a/board/amlogic/gxtvbb_t966_skt_v1/Makefile b/board/amlogic/gxtvbb_t966_skt_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/gxtvbb_t966_skt_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/gxtvbb_t966_skt_v1/aml-user-key.sig b/board/amlogic/gxtvbb_t966_skt_v1/aml-user-key.sig
new file mode 100644
index 0000000..6b51b19
--- /dev/null
+++ b/board/amlogic/gxtvbb_t966_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/gxtvbb_t966_skt_v1/eth_setup.c b/board/amlogic/gxtvbb_t966_skt_v1/eth_setup.c
new file mode 100644
index 0000000..c5503c3
--- /dev/null
+++ b/board/amlogic/gxtvbb_t966_skt_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/gxtvbb_t966_skt_v1/firmware/board_init.c b/board/amlogic/gxtvbb_t966_skt_v1/firmware/board_init.c
new file mode 100644
index 0000000..7ad9da6
--- /dev/null
+++ b/board/amlogic/gxtvbb_t966_skt_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/gxtvbb_t966_skt_v1/firmware/power.c b/board/amlogic/gxtvbb_t966_skt_v1/firmware/power.c
new file mode 100644
index 0000000..b9d7e83
--- /dev/null
+++ b/board/amlogic/gxtvbb_t966_skt_v1/firmware/power.c
@@ -0,0 +1,212 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140},
+};
+
+#define P_PIN_MUX_AO (*((volatile unsigned *)(0xc8100000 + (0x05 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xda834400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
+#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
+
+#ifdef P_AO_PWM_MISC_REG_AB
+#undef P_AO_PWM_MISC_REG_AB
+#endif
+#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#ifdef P_AO_PWM_PWM_B
+#undef P_AO_PWM_PWM_B
+#endif
+#define P_AO_PWM_PWM_B (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_A, PWM_AO_B,PWM_F
+ */
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~((1 << 12)|(1<<14)|(1<<22));
+ P_PIN_MUX_REG10 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg |= (1 << 21); // enable PWM_A
+ P_PIN_MUX_REG10 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = P_AO_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1)|(1<<0));
+
+ P_AO_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_AO_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 21); // enable PWM_AO_B
+ P_PIN_MUX_AO = reg;
+
+ break;
+
+ case pwm_f:
+ reg = P_PWM_MISC_REG_EF;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1) |(1 << 0));
+ P_PWM_MISC_REG_EF = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_AO;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_AO = reg;
+
+ reg = P_PIN_MUX_AO;
+ reg |= (1 << 22); // enable PWM_f
+ P_PIN_MUX_AO = reg;
+
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+
+ //serial_put_dec( pwm_voltage_table[to][1]);
+ //serial_puts(" mv\n");
+
+ //serial_put_dec( pwm_voltage_table[to][0]);
+ //serial_puts(" mv\n");
+
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ P_AO_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_f:
+ P_PWM_PWM_F = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+
+ _udelay(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/gxtvbb_t966_skt_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/gxtvbb_t966_skt_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..35977ff
--- /dev/null
+++ b/board/amlogic/gxtvbb_t966_skt_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,175 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860),
+ DVFS( 250000000, 860),
+ DVFS( 500000000, 860),
+ DVFS( 667000000, 900),
+ DVFS(1000000000, 940),
+ DVFS(1200000000, 980),
+ DVFS(1296000000, 1000),
+ DVFS(1416000000, 1020),
+ DVFS(1536000000, 1050),
+ DVFS(1800000000, 1050),
+};
+
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 22);
+ reg |= (1 << 21); // enable PWM_B
+ P_PIN_MUX_REG3 = reg;
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_B;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_B = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+}
+
diff --git a/board/amlogic/gxtvbb_t966_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/gxtvbb_t966_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..fc355ac
--- /dev/null
+++ b/board/amlogic/gxtvbb_t966_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,215 @@
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void power_off_at_clk81(void)
+{
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+}
+static void power_on_at_32k(unsigned int suspend_from)
+{
+}
+
+static void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ writel(9, P_ISA_TIMERA);
+}
+static void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+
+static void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ p->gpio_info_count = 0;
+ p->status = RESPONSE_OK;
+ val = (AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC);
+
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+
+ p->sources = val;
+
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ saradc_enable();
+ reset_ao_timera();
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+ if (suspend_from == SYS_POWEROFF)
+ continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+
+#ifdef CONFIG_BT_WAKEUP
+ if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
+ irq[IRQ_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ & (0x01 << 20)) && (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 20)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 21)))
+ exit_reason = BT_WAKEUP;
+ }
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
+ irq[IRQ_GPIO1] = 0xFFFFFFFF;
+ if (suspend_from) {
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ & (0x01 << 6)) && (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 6)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 7)))
+ exit_reason = WIFI_WAKEUP;
+ }
+ }
+#endif
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+ wakeup_timer_clear();
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/gxtvbb_t966_skt_v1/firmware/timing.c b/board/amlogic/gxtvbb_t966_skt_v1/firmware/timing.c
new file mode 100644
index 0000000..4385dea
--- /dev/null
+++ b/board/amlogic/gxtvbb_t966_skt_v1/firmware/timing.c
@@ -0,0 +1,388 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 50
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+#define CFG_DDR3_DRV DDR3_DRV_40OHM
+#define CFG_DDR3_ODT DDR3_ODT_120OHM
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_14,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (14),
+ .cfg_ddr_rcd = (14),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (14),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (10),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 0,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+ .ddr_size_detect = CONFIG_DDR_SIZE_AUTO_DETECT,
+ .ddr_drv = CFG_DDR3_DRV,
+ .ddr_odt = CFG_DDR3_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00210000,
+ .t_pub_mr = {0},
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x0380c6a0, //PUB PGCR1
+ //.t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ .t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aafe60, //PUB PGCR3
+ .t_pub_dxccr = 0x00181884, //PUB DXCCR
+ .t_pub_dtcr = 0x43003087, //PUB DTCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+ .t_pub_dcr = 0X8B, //PUB DCR
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ .t_pub_dsgcr = 0x020641f,
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x59, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x19, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x19, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x19, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F21, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = (1<<31)|(0x20<<16)|(0x80<<0)//[B31]hw_exit_idle_en
+ |( 0<<8), //[B10,B9,B8] tfaw_cfg_offset:
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ //.t_pctl0_ppcfg = (0xF0 << 1),
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 1,
+ .t_pctl0_dfitphywrlta = 2,
+ .t_pctl0_dfitrddataen = 3,
+ .t_pctl0_dfitphyrdlat = 16,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype1 = 0x200,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (3 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+ .t_pub_acbdlr0 = 0, //2015.09.21 add for CK0 delay fine tune
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+};
diff --git a/board/amlogic/gxtvbb_t966_skt_v1/gxtvbb_t966_skt_v1.c b/board/amlogic/gxtvbb_t966_skt_v1/gxtvbb_t966_skt_v1.c
new file mode 100644
index 0000000..9f6465e
--- /dev/null
+++ b/board/amlogic/gxtvbb_t966_skt_v1/gxtvbb_t966_skt_v1.c
@@ -0,0 +1,705 @@
+
+/*
+ * board/amlogic/gxtvbb_skt_v1/gxtvbb_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+ #include <asm/arch/io.h>
+#endif
+#include <amlogic/canvas.h>
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <amlogic/spifc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+#ifdef CONFIG_AML_PMU4
+#define AML1220_ADDR 0x35
+#define AML1220_ANALOG_ADDR 0x20
+
+unsigned int pmu4_analog_reg[15] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, /* Reg 0x20 - 0x24 */
+ 0x00, 0x00, 0x00, 0x00, 0x51, /* Reg 0x25 - 0x29 */
+ 0x42, 0x00, 0x42, 0x41, 0x02 /* Reg 0x2a - 0x2e */
+};
+
+#define PMU4_ANALOG_REG_LEN ARRAY_SIZE(pmu4_analog_reg)
+
+int aml_pmu4_read(int add, uint8_t *val)
+{
+ int ret;
+ uint8_t buf[2] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ ,
+ {
+ .addr = AML1220_ADDR,
+ .flags = I2C_M_RD,
+ .len = 1,
+ .buf = val,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ ret = aml_i2c_xfer(msg, 2);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+int aml_pmu4_write(int32_t add, uint8_t val)
+{
+ int ret;
+ uint8_t buf[3] = { };
+ struct i2c_msg msg[] = {
+ {
+ .addr = AML1220_ADDR,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ };
+
+ buf[0] = add & 0xff;
+ buf[1] = (add >> 8) & 0x0f;
+ buf[2] = val & 0xff;
+ ret = aml_i2c_xfer(msg, 1);
+ if (ret < 0) {
+ printf("%s: i2c transfer failed, ret:%d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+void pmu4_phy_config(void)
+{
+#if 0
+ int i;
+ uint8_t value;
+ int data;
+ uint8_t data_lo;
+ uint8_t data_hi;
+#endif
+ /* eth ldo */
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+
+ mdelay(10);
+
+ /* pinmux */
+ aml_pmu4_write(0x2c, 0x51);
+ aml_pmu4_write(0x2d, 0x41);
+ aml_pmu4_write(0x20, 0x0);
+ aml_pmu4_write(0x21, 0x3);
+#ifdef EXT_CLK
+ aml_pmu4_write(0x14, 0x01);
+#else
+ aml_pmu4_write(0x14, 0x00);
+#endif
+ aml_pmu4_write(0x15, 0x3f);
+
+ /* pll */
+ aml_pmu4_write(0x78, 0x06);
+ aml_pmu4_write(0x79, 0x05);
+ aml_pmu4_write(0x7a, 0xa1);
+ aml_pmu4_write(0x7b, 0xac);
+ aml_pmu4_write(0x7c, 0x5b);
+ aml_pmu4_write(0x7d, 0xa0);
+ aml_pmu4_write(0x7e, 0x20);
+ aml_pmu4_write(0x7f, 0x49);
+ aml_pmu4_write(0x80, 0xd6);
+ aml_pmu4_write(0x81, 0x0b);
+ aml_pmu4_write(0x82, 0xd1);
+ aml_pmu4_write(0x83, 0x00);
+ aml_pmu4_write(0x84, 0x00);
+ aml_pmu4_write(0x85, 0x00);
+
+ /*cfg4- --- cfg 45 */
+ aml_pmu4_write(0x88, 0x0);
+ aml_pmu4_write(0x89, 0x0);
+ aml_pmu4_write(0x8A, 0x22);
+ aml_pmu4_write(0x8B, 0x01);
+ aml_pmu4_write(0x8C, 0xd0);
+ aml_pmu4_write(0x8D, 0x01);
+ aml_pmu4_write(0x8E, 0x00);
+ aml_pmu4_write(0x93, 0x81);
+
+ /* pmu4 phyid = 20142014 */
+ aml_pmu4_write(0x94, 0x14);
+ aml_pmu4_write(0x95, 0x20);
+
+ aml_pmu4_write(0x96, 0x14);
+ aml_pmu4_write(0x97, 0x20);
+
+ /*phyadd & mode */
+#ifdef EXT_CLK
+ aml_pmu4_write(0x98, 0x73);
+#else
+ aml_pmu4_write(0x98, 0x47);
+#endif
+
+ aml_pmu4_write(0x99, 0x61);
+ aml_pmu4_write(0x9a, 0x07);
+ aml_pmu4_write(0x04, 0x01);
+ aml_pmu4_write(0x05, 0x01);
+#if 0
+ value = 0;
+ pr_info("--------> read 0x9c\n");
+ while ((value & 0x01) == 0)
+ aml_pmu4_read(0x9c, &value);
+ pr_info("----2----> read 0x9c over!\n");
+#endif
+ aml_pmu4_write(0x9b, 0x00);
+ aml_pmu4_write(0x9b, 0x80);
+ aml_pmu4_write(0x9b, 0x00);
+#if 0
+ printf("phy init though i2c done\n");
+ for (i = 0; i < 0xb0; i++) {
+ aml_pmu4_read(i, &value);
+ printf(" i2c[%x]=0x%x\n", i, value);
+ }
+ printf("phy reg dump though i2c:\n");
+ for (i = 0; i < 0x20; i++) {
+ aml_pmu4_write(0xa6, i);
+ aml_pmu4_read(0xa7, &data_lo);
+ aml_pmu4_read(0xa8, &data_hi);
+ data = (data_hi << 8) | data_lo;
+ printf(" phy[%x]=0x%x\n", i, data);
+ }
+#endif
+}
+
+static int aml_pmu4_reg_init(unsigned int reg_base, unsigned int *val,
+ unsigned int reg_len)
+{
+ int ret = 0;
+ unsigned int i = 0;
+
+ for (i = 0; i < reg_len; i++) {
+ ret = aml_pmu4_write(reg_base + i, val[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int aml_pmu4_power_init(void)
+{
+ int ret;
+
+ /* pmu4 analog register init */
+ ret = aml_pmu4_reg_init(AML1220_ANALOG_ADDR, &pmu4_analog_reg[0],
+ PMU4_ANALOG_REG_LEN);
+ if (ret < 0)
+ return ret;
+
+ pmu4_phy_config();
+
+ return 0;
+
+}
+
+void setup_pmu4(void)
+{
+ aml_pmu4_power_init();
+}
+#endif
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ //setup ethernet clk need calibrate to configre
+ setbits_le32(P_PERIPHS_PIN_MUX_8, 0x1fffc000);
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+#ifndef CONFIG_AML_PMU4
+ /* hardware reset ethernet phy : gpioz14 connect phyreset pin*/
+ clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 14);
+ clrbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+ udelay(100000);
+ setbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+#endif
+}
+
+extern int designware_initialize(ulong base_addr, u32 interface);
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_AML_PMU4
+ setup_pmu4();
+#endif
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ ret=readl(P_PREG_PAD_GPIO5_I)&(1<<29)?0:1;
+ printf("ret = %d .",ret);
+ if ((readl(P_PERIPHS_PIN_MUX_8)&(3<<9))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I)&(1<<24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 1
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(PERIPHS_PIN_MUX_7, (1<<19)|(1<<20));
+ //enable I2C MASTER AO pins
+ setbits_le32(PERIPHS_PIN_MUX_7,
+ ((MESON_I2C_MASTER_B_GPIOH_3_BIT) | (MESON_I2C_MASTER_B_GPIOH_4_BIT)));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_B,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_b_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOH_4_REG,
+ .scl_bit = MESON_I2C_MASTER_B_GPIOH_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_B_GPIOH_3_REG,
+ .sda_bit = MESON_I2C_MASTER_B_GPIOH_3_BIT,
+ }
+};
+#if 1
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+#include <asm/arch/usb.h>
+#include <asm/arch/gpio.h>
+struct amlogic_usb_config g_usb_config_GXTVBB_skt={
+ CONFIG_GXTVBB_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXTVBB_USB_PHY2_BASE,
+ CONFIG_GXTVBB_USB_PHY3_BASE,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_11: NOR_D:reg5[16], clr none
+ * BOOT_12: NOR_Q:reg5[17], clr none
+ * BOOT_13: NOR_C:reg5[18], clr none
+ * BOOT_18: NOR_CS:reg5[19],clr none
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {71/*BOOT_18*/};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_5);
+ val &= ~((1<<19)|(1<<18)|(1<<17)|(1<<16));
+ if (enable) {
+ val |= (1<<18)|(1<<17)|(1<<16);
+ }
+ writel(val, P_PERIPHS_PIN_MUX_5);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xc1108c80,
+ .mem_map = 0xcc000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC
+ board_usb_init(&g_usb_config_GXTVBB_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+ canvas_init();
+#ifdef CONFIG_SYS_I2C_AML
+// #ifdef 1
+ board_i2c_init();
+// #endif /*CONFIG_AML_I2C*/
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+ /*add board late init function here*/
+ run_command("setenv fdt_high 0x20000000", 1);
+ run_command("setenv dtb_mem_addr 0x1000000", 1);
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+ vpp_init();
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int boardid = 0;
+ char loc_name[64] = {0};
+ boardid = (readl(AO_SEC_GP_CFG0)>>8)&0xff;
+ printf("%s: boardid = 0x%x\n", __func__,boardid);
+
+ switch (boardid) {
+ case 0:
+ strcpy(loc_name, "gxtvbb_p301_1g\0");
+ break;
+ case 8:
+ strcpy(loc_name, "gxtvbb_p300_2g\0");
+ break;
+ case 12:
+ strcpy(loc_name, "gxtvbb_skt_2g\0");
+ break;
+ default:
+ printf("boardid: 0x%x, multi-dt doesn't support\n", boardid);
+ //strcpy(loc_name, "gxb_p200_unsupport");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "aml_dt",
+ "firstboot",
+
+ NULL//Keep NULL be last to tell END
+};
+
diff --git a/board/amlogic/gxtvbb_t966_skt_v1/lcd.c b/board/amlogic/gxtvbb_t966_skt_v1/lcd.c
new file mode 100755
index 0000000..2990aab
--- /dev/null
+++ b/board/amlogic/gxtvbb_t966_skt_v1/lcd.c
@@ -0,0 +1,320 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOX_3",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,},
+ {LCD_POWER_TYPE_MAX, 0,0,0,},
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,},
+ {LCD_POWER_TYPE_MAX, 0,0,0,},
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOAO_4",
+ "GPIOY_13",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* AOC: public Platform lvds : 1920x1080@60hz 8bit pixel clk@74.25mhz 2prot*/
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{7, 0x00001800}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{7, 0x00000603}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 2,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{10, 0x00800000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{10, 0x0100a000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txhd_r341_v1/Kconfig b/board/amlogic/txhd_r341_v1/Kconfig
new file mode 100644
index 0000000..0c46d34
--- /dev/null
+++ b/board/amlogic/txhd_r341_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_TXHD
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "txhd_r341_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "txhd"
+
+config SYS_CONFIG_NAME
+ default "txhd_r341_v1"
+
+endif
diff --git a/board/amlogic/txhd_r341_v1/Makefile b/board/amlogic/txhd_r341_v1/Makefile
new file mode 100644
index 0000000..963e9c5
--- /dev/null
+++ b/board/amlogic/txhd_r341_v1/Makefile
@@ -0,0 +1,4 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
+obj-y += pwm_table.o
diff --git a/board/amlogic/txhd_r341_v1/aml-user-key.sig b/board/amlogic/txhd_r341_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/txhd_r341_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/txhd_r341_v1/eth_setup.c b/board/amlogic/txhd_r341_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/txhd_r341_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/txhd_r341_v1/firmware/board_init.c b/board/amlogic/txhd_r341_v1/firmware/board_init.c
new file mode 100644
index 0000000..b660c42
--- /dev/null
+++ b/board/amlogic/txhd_r341_v1/firmware/board_init.c
@@ -0,0 +1,30 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+#ifndef CONFIG_PXP_EMULATOR
+ power_init(0);
+#endif
+}
\ No newline at end of file
diff --git a/board/amlogic/txhd_r341_v1/firmware/power.c b/board/amlogic/txhd_r341_v1/firmware/power.c
new file mode 100644
index 0000000..31e9690
--- /dev/null
+++ b/board/amlogic/txhd_r341_v1/firmware/power.c
@@ -0,0 +1,240 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+#include <asm/arch/secure_apb.h>
+
+#define P_EE_TIMER_E (P_ISA_TIMERE)
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_ao_b,
+};
+
+unsigned int _get_time(void)
+{
+ return readl(P_EE_TIMER_E);
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ */
+
+ switch (id) {
+ case pwm_a:
+ reg = readl(P_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ writel(reg, P_PWM_MISC_REG_AB);
+
+ /* set PWM_A pinmux */
+ reg = readl(P_PERIPHS_PIN_MUX_2);
+ reg |= ((1 & 0xf) << 20);
+ writel(reg, P_PERIPHS_PIN_MUX_2);
+ break;
+
+ case pwm_ao_b:
+ reg = readl(P_AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, P_AO_PWM_MISC_REG_AB);
+
+ /* set PWM_AO_B pinmux */
+ reg = readl(P_AO_RTI_PIN_MUX_REG2);;
+ reg |= ((4 & 0xf) << 4);
+ writel(reg, P_AO_RTI_PIN_MUX_REG2);
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+/*
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+*/
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ serial_puts("enter pwm_set_voltage\n");
+ int to;
+
+ switch (id) {
+ case pwm_a:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ writel(pwm_voltage_table[to][0], P_PWM_PWM_A);
+ break;
+
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ writel(pwm_voltage_table_ee[to][0], P_AO_PWM_PWM_B);
+ break;
+
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vddee enable AO 2/10 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~((1 << 2)|(1 << 10));
+ reg |= ((1 << 18)|(1 << 26));
+ writel(reg, AO_GPIO_O_EN_N);
+ serial_puts("set test_n to high\n ");
+ reg = readl(AO_SEC_REG0);
+ reg |= (1 << 0);
+ writel(reg, AO_SEC_REG0);
+ reg = readl(AO_GPIO_O_EN_N);
+ reg |= (1 << 31);
+ writel(reg, AO_GPIO_O_EN_N);
+}
diff --git a/board/amlogic/txhd_r341_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/txhd_r341_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..14d8818
--- /dev/null
+++ b/board/amlogic/txhd_r341_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,192 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+/*
+int pwm_voltage_table[ ][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+*/
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~((1 << 21) | 1 << 12);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(1 << 16);
+ P_PIN_MUX_REG10 = reg;//clear reg10
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/txhd_r341_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/txhd_r341_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..7b67562
--- /dev/null
+++ b/board/amlogic/txhd_r341_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,37 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
diff --git a/board/amlogic/txhd_r341_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/txhd_r341_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..a0af36a
--- /dev/null
+++ b/board/amlogic/txhd_r341_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,379 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "pwm_ctrl.h"
+
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xff807000 + (0x01 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+#define ON 1
+#define OFF 0
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+#if 0
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#endif
+
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ switch (id) {
+ case pwm_a:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table_ee[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_off_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+}
+
+static void power_off_at_clk81(void)
+{
+
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
+ _udelay(10000);
+}
+
+/*timing request:
+ *poweroff vddio3.3v-->delay 20ms-->poweroff vddee
+ */
+static void power_off_vddee(void)
+{
+ unsigned int val;
+
+ /*set test n output low level */
+ _udelay(10000);/*the other 10ms in power_off_at_32k()*/
+ val = readl(AO_GPIO_O_EN_N);
+ val &= ~(0x1 << 31);
+ writel(val, AO_GPIO_O_EN_N);
+
+}
+
+/*timing request:
+ *poweron vddee-->delay 20ms-->poweron vddio3.3v
+ */
+static void power_on_vddee(void)
+{
+ unsigned int val;
+
+ /*set test n output high level */
+ val = readl(AO_GPIO_O_EN_N);
+ val |= 0x1 << 31;
+ writel(val, AO_GPIO_O_EN_N);
+ _udelay(10000);/*the other 10ms in power_on_at_32k()*/
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+ power_off_usb5v();
+ _udelay(5000);
+ power_off_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_vddee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+ if (suspend_from == SYS_POWEROFF)
+ power_on_vddee();
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ _udelay(10000);
+ power_on_3v3_5v();
+ _udelay(10000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ _udelay(10000);
+ _udelay(10000);
+ power_on_usb5v();
+
+ if (suspend_from == SYS_POWEROFF)
+ power_on_ddr();
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ val |= CECB_WAKEUP_SRC;
+#endif
+ p->sources = val;
+ p->gpio_info_count = 0;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ init_remote();
+ saradc_enable();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CECB_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+// if (suspend_from == SYS_POWEROFF)
+// continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/txhd_r341_v1/firmware/timing.c b/board/amlogic/txhd_r341_v1/firmware/timing.c
new file mode 100644
index 0000000..6a7b34b
--- /dev/null
+++ b/board/amlogic/txhd_r341_v1/firmware/timing.c
@@ -0,0 +1,588 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+#define DDR3_WR_ODT_0OHM 0<<3
+#define DDR3_WR_ODT_60OHM 1<<3
+//#define DDR3_WR_ODT_120OHM 1<<4
+
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+//#define CFG_DDR_ODT DDR3_ODT_120OHM //txhd skt board
+#define CFG_DDR_ODT DDR3_ODT_60OHM|DDR3_WR_ODT_60OHM //TXHD R341 REF board
+//#define CFG_DDR_WR_ODT DDR3_ODT_60OHM //TXHD R341 REF board
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0xc00031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0xc00031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+/* txhd skt board
+ .t_pub_acbdlr0 = 0x0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0x20,
+ .t_pub_zq0pr = 0x59959, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f92d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f92d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+*/
+
+//txhd r341 ref board
+ .t_pub_acbdlr0 = 0x18, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0x20,
+ .t_pub_zq0pr = 0x59958, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/txhd_r341_v1/lcd.c b/board/amlogic/txhd_r341_v1/lcd.c
new file mode 100755
index 0000000..1a8e8cf
--- /dev/null
+++ b/board/amlogic/txhd_r341_v1/lcd.c
@@ -0,0 +1,418 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_3",
+ //"GPIOX_2",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,50,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step_gamma_init[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,50,}, /* power on */
+ {LCD_POWER_TYPE_EXTERN,1,0,50,}, /* extern gamma init */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ //"GPIOAO_4",
+ //"GPIOY_13",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* 1920*1080 */
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0xff,1,0,0,0,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* 1366*768 */
+ "lvds_1",LCD_LVDS,8,
+ /* basic timing */
+ 1366,768,1560,806,56,64,0,3,28,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,0,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* 1920*1080 */
+ "mlvds_0",LCD_MLVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* minilvds_attr */
+ 6,0x12304567,0x0,0x110,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0xff,1,0,0,0,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* 1366*768 */
+ "mlvds_1",LCD_MLVDS,8,
+ /* basic timing */
+ 1366,768,1560,806,56,64,0,3,28,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* minilvds_attr */
+ 6,0x45603012,0x0,0xaa0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* 1920*1080 */
+ "mlvds_2",LCD_MLVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* minilvds_attr */
+ 6,0x12304567,0x0,0x110,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_gamma_init, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0xff,1,0,0,0,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_minilvds_pin", //GPIOH_0~15
+ .pinmux_set = {{4, 0x11111111}, {5, 0x00110001}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0xffffffff}, {5, 0x00ff000f}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOZ_1
+ .pinmux_set = {{2, 0x00000040}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x000000f0}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_vs_on_pin", //GPIOZ_1
+ .pinmux_set = {{2, 0x00000030}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x000000f0}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_0_on_pin", //GPIOZ_1
+ .pinmux_set = {{2, 0x00000040}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x000000f0}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_1_on_pin", //GPIOZ_0
+ .pinmux_set = {{2, 0x00000004}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x0000000f}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_0_vs_on_pin", //GPIOZ_1
+ .pinmux_set = {{2, 0x00000030}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x000000f0}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_1_vs_on_pin", //GPIOZ_0
+ .pinmux_set = {{2, 0x00000003}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x0000000f}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct mlvds_config_s lcd_mlvds_config = {
+ .channel_num = 6,
+ .channel_sel0 = 0x45603012,
+ .channel_sel1 = 0x0,
+ .clk_phase = 0x0,
+ .pn_swap = 0, //0=normal, 1=swap
+ .bit_swap = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ // {
+ // .type = LCD_POWER_TYPE_CPU,
+ // .index = 0, /* point to cpu_gpio[] struct */
+ // .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ // .delay = 50, /* unit: ms */
+ // },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ // {
+ // .type = LCD_POWER_TYPE_CPU,
+ // .index = 0, /* point to cpu_gpio[] struct */
+ // .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ // .delay = 100, /* unit: ms */
+ // },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .mlvds_config = &lcd_mlvds_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{4, 0x11111111}, {5, 0x00110001}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0xffffffff}, {5, 0x00ff000f}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 89,
+ 0x00,
+ 0xA2,0xD0,0x80,0x00,0x10,0x10,0x59,0x19,0x4B,0x0B,
+ 0x3A,0x13,0x27,0x2F,0xC2,0xC9,0x29,0xD2,0x7A,0x20,
+ 0xA1,0xC0,0x15,0x01,0x36,0x10,0x10,0xCB,0x0A,0x10,
+ 0x2C,0x1C,0xA0,0xFF,0x00,0x00,0x0B,0x02,0x00,0x00,
+ 0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x10,
+ 0x80,0x00,0x60,0x00,0x00,0x00,0x0D,0x0D,0x20,0x02,
+ 0x00,0x20,0x02,0x00,0x20,0x02,0x00,0x20,0x02,0x00,
+ 0x20,0x02,0x00,0x20,0x02,0x00,0x20,0x02,0x00,0x20,
+ 0x00,0xFF,0x00,0x00,0x0B,0x02,0x00,0x00,
+ 0xff, 0, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 2,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_D, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = 1,
+ .name = "i2c_RT6947",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x33, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_D, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .cmd_size = LCD_EXTERN_CMD_SIZE_DYNAMIC,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{2, 0x00000040}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x000000f0}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txhd_r341_v1/pwm_table.c b/board/amlogic/txhd_r341_v1/pwm_table.c
new file mode 100644
index 0000000..18dc638
--- /dev/null
+++ b/board/amlogic/txhd_r341_v1/pwm_table.c
@@ -0,0 +1,71 @@
+#include <common.h>
+
+const int pwm_cal_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+const int pwm_cal_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
+int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
+
+
diff --git a/board/amlogic/txhd_r341_v1/txhd_r341_v1.c b/board/amlogic/txhd_r341_v1/txhd_r341_v1.c
new file mode 100644
index 0000000..e6197fe
--- /dev/null
+++ b/board/amlogic/txhd_r341_v1/txhd_r341_v1.c
@@ -0,0 +1,445 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/secure_apb.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 22);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 22) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ /*if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }*/
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_pwm_cal_init(0);
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
diff --git a/board/amlogic/txhd_skt_v1/Kconfig b/board/amlogic/txhd_skt_v1/Kconfig
new file mode 100644
index 0000000..f9966cb
--- /dev/null
+++ b/board/amlogic/txhd_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_TXHD
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "txhd_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "txhd"
+
+config SYS_CONFIG_NAME
+ default "txhd_skt_v1"
+
+endif
diff --git a/board/amlogic/txhd_skt_v1/Makefile b/board/amlogic/txhd_skt_v1/Makefile
new file mode 100644
index 0000000..963e9c5
--- /dev/null
+++ b/board/amlogic/txhd_skt_v1/Makefile
@@ -0,0 +1,4 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
+obj-y += pwm_table.o
diff --git a/board/amlogic/txhd_skt_v1/aml-user-key.sig b/board/amlogic/txhd_skt_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/txhd_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/txhd_skt_v1/eth_setup.c b/board/amlogic/txhd_skt_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/txhd_skt_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/txhd_skt_v1/firmware/board_init.c b/board/amlogic/txhd_skt_v1/firmware/board_init.c
new file mode 100644
index 0000000..b660c42
--- /dev/null
+++ b/board/amlogic/txhd_skt_v1/firmware/board_init.c
@@ -0,0 +1,30 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+#ifndef CONFIG_PXP_EMULATOR
+ power_init(0);
+#endif
+}
\ No newline at end of file
diff --git a/board/amlogic/txhd_skt_v1/firmware/power.c b/board/amlogic/txhd_skt_v1/firmware/power.c
new file mode 100644
index 0000000..31e9690
--- /dev/null
+++ b/board/amlogic/txhd_skt_v1/firmware/power.c
@@ -0,0 +1,240 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+#include <asm/arch/secure_apb.h>
+
+#define P_EE_TIMER_E (P_ISA_TIMERE)
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_ao_b,
+};
+
+unsigned int _get_time(void)
+{
+ return readl(P_EE_TIMER_E);
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ */
+
+ switch (id) {
+ case pwm_a:
+ reg = readl(P_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ writel(reg, P_PWM_MISC_REG_AB);
+
+ /* set PWM_A pinmux */
+ reg = readl(P_PERIPHS_PIN_MUX_2);
+ reg |= ((1 & 0xf) << 20);
+ writel(reg, P_PERIPHS_PIN_MUX_2);
+ break;
+
+ case pwm_ao_b:
+ reg = readl(P_AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, P_AO_PWM_MISC_REG_AB);
+
+ /* set PWM_AO_B pinmux */
+ reg = readl(P_AO_RTI_PIN_MUX_REG2);;
+ reg |= ((4 & 0xf) << 4);
+ writel(reg, P_AO_RTI_PIN_MUX_REG2);
+ break;
+
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+/*
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+*/
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ serial_puts("enter pwm_set_voltage\n");
+ int to;
+
+ switch (id) {
+ case pwm_a:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ writel(pwm_voltage_table[to][0], P_PWM_PWM_A);
+ break;
+
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ writel(pwm_voltage_table_ee[to][0], P_AO_PWM_PWM_B);
+ break;
+
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vddee enable AO 2/10 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~((1 << 2)|(1 << 10));
+ reg |= ((1 << 18)|(1 << 26));
+ writel(reg, AO_GPIO_O_EN_N);
+ serial_puts("set test_n to high\n ");
+ reg = readl(AO_SEC_REG0);
+ reg |= (1 << 0);
+ writel(reg, AO_SEC_REG0);
+ reg = readl(AO_GPIO_O_EN_N);
+ reg |= (1 << 31);
+ writel(reg, AO_GPIO_O_EN_N);
+}
diff --git a/board/amlogic/txhd_skt_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/txhd_skt_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..e663d12
--- /dev/null
+++ b/board/amlogic/txhd_skt_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,192 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+/*
+int pwm_voltage_table[ ][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+*/
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 1100+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~((1 << 21) | 1 << 12);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(1 << 16);
+ P_PIN_MUX_REG10 = reg;//clear reg10
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/txhd_skt_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/txhd_skt_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..7b67562
--- /dev/null
+++ b/board/amlogic/txhd_skt_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,37 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
diff --git a/board/amlogic/txhd_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/txhd_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..a647727
--- /dev/null
+++ b/board/amlogic/txhd_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,368 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "pwm_ctrl.h"
+
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xff807000 + (0x01 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+#define ON 1
+#define OFF 0
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+#if 0
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#endif
+
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ switch (id) {
+ case pwm_a:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table_ee[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_off_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+}
+
+static void power_off_at_clk81(void)
+{
+
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
+ _udelay(10000);
+}
+
+/*timing request:
+ *poweroff vddio3.3v-->delay 20ms-->poweroff vddee
+ */
+static void power_off_vddee(void)
+{
+ unsigned int val;
+
+ /*set test n output low level */
+ _udelay(10000);/*the other 10ms in power_off_at_32k()*/
+ val = readl(AO_GPIO_O_EN_N);
+ val &= ~(0x1 << 31);
+ writel(val, AO_GPIO_O_EN_N);
+
+}
+
+/*timing request:
+ *poweron vddee-->delay 20ms-->poweron vddio3.3v
+ */
+static void power_on_vddee(void)
+{
+ unsigned int val;
+
+ /*set test n output high level */
+ val = readl(AO_GPIO_O_EN_N);
+ val |= 0x1 << 31;
+ writel(val, AO_GPIO_O_EN_N);
+ _udelay(10000);/*the other 10ms in power_on_at_32k()*/
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+ power_off_usb5v();
+ _udelay(5000);
+ power_off_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_vddee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+ if (suspend_from == SYS_POWEROFF)
+ power_on_vddee();
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ _udelay(10000);
+ power_on_3v3_5v();
+ _udelay(10000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ _udelay(10000);
+ _udelay(10000);
+ power_on_usb5v();
+
+ if (suspend_from == SYS_POWEROFF)
+ power_on_ddr();
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ val |= CECB_WAKEUP_SRC;
+#endif
+ p->sources = val;
+ p->gpio_info_count = 0;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ init_remote();
+ saradc_enable();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CECB_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+// if (suspend_from == SYS_POWEROFF)
+// continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/txhd_skt_v1/firmware/timing.c b/board/amlogic/txhd_skt_v1/firmware/timing.c
new file mode 100644
index 0000000..7c16251
--- /dev/null
+++ b/board/amlogic/txhd_skt_v1/firmware/timing.c
@@ -0,0 +1,569 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_60OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0xc00031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0xc00031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x59959, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0x10,
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/txhd_skt_v1/lcd.c b/board/amlogic/txhd_skt_v1/lcd.c
new file mode 100755
index 0000000..5e359b7
--- /dev/null
+++ b/board/amlogic/txhd_skt_v1/lcd.c
@@ -0,0 +1,342 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ //"GPIOX_3",
+ //"GPIOX_2",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ //{LCD_POWER_TYPE_CPU, 0,1,50,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ //{LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ //"GPIOAO_4",
+ //"GPIOY_13",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* 1920*1080 */
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0xff,1,0,0,0,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* 1366*768 */
+ "lvds_1",LCD_LVDS,8,
+ /* basic timing */
+ 1366,768,1560,806,56,64,0,3,28,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,0,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* 1920*1080 */
+ "mlvds_0",LCD_MLVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* minilvds_attr */
+ 6,0x12304567,0x0,0x110,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0xff,1,0,0,0,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* 1366*768 */
+ "mlvds_1",LCD_MLVDS,8,
+ /* basic timing */
+ 1366,768,1560,806,56,64,0,3,28,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* minilvds_attr */
+ 6,0x45603012,0x0,0xaa0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_minilvds_pin", //GPIOH_0~15
+ .pinmux_set = {{4, 0x11111111}, {5, 0x11111111}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0xffffffff}, {5, 0xffffffff}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct mlvds_config_s lcd_mlvds_config = {
+ .channel_num = 6,
+ .channel_sel0 = 0x45603012,
+ .channel_sel1 = 0x0,
+ .clk_phase = 0x0,
+ .pn_swap = 0, //0=normal, 1=swap
+ .bit_swap = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ // {
+ // .type = LCD_POWER_TYPE_CPU,
+ // .index = 0, /* point to cpu_gpio[] struct */
+ // .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ // .delay = 50, /* unit: ms */
+ // },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ // {
+ // .type = LCD_POWER_TYPE_CPU,
+ // .index = 0, /* point to cpu_gpio[] struct */
+ // .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ // .delay = 100, /* unit: ms */
+ // },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .mlvds_config = &lcd_mlvds_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{4, 0x11111111}, {5, 0x11111111}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0xffffffff}, {5, 0xffffffff}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = NULL,
+ .pinmux_set = {{2, 0x00000040}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{2, 0x000000f0}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txhd_skt_v1/pwm_table.c b/board/amlogic/txhd_skt_v1/pwm_table.c
new file mode 100644
index 0000000..18dc638
--- /dev/null
+++ b/board/amlogic/txhd_skt_v1/pwm_table.c
@@ -0,0 +1,71 @@
+#include <common.h>
+
+const int pwm_cal_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+const int pwm_cal_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
+int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
+
+
diff --git a/board/amlogic/txhd_skt_v1/txhd_skt_v1.c b/board/amlogic/txhd_skt_v1/txhd_skt_v1.c
new file mode 100644
index 0000000..990ef1f
--- /dev/null
+++ b/board/amlogic/txhd_skt_v1/txhd_skt_v1.c
@@ -0,0 +1,579 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/secure_apb.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm/cpu_id.h>
+#include <linux/mtd/partitions.h>
+#include <linux/sizes.h>
+#include <asm/arch/clock.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/board_id.h>
+#include <dm.h>
+#ifdef CONFIG_AML_SPIFC
+#include <amlogic/spifc.h>
+#endif
+#ifdef CONFIG_AML_SPICC
+#include <amlogic/spicc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 22);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 22) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ /*if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }*/
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_3: NOR_HOLDn:reg0[15:12]=3
+ * BOOT_4: NOR_D:reg0[19:16]=3
+ * BOOT_5: NOR_Q:reg0[23:20]=3
+ * BOOT_6: NOR_C:reg0[27:24]=3
+ * BOOT_9: NOR_WPn:reg1[7:4]=3
+ * BOOT_12: NOR_CS:reg1[19:16]=3
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {50};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_0);
+ val &= ~(0xffff << 12);
+ if (enable)
+ val |= 0x3333 << 12;
+ writel(val, P_PERIPHS_PIN_MUX_0);
+
+ val = readl(P_PERIPHS_PIN_MUX_1);
+ val &= ~((0xf << 4) | (0xf << 16));
+ if (enable)
+ val |= 0x3 << 4; //BOOT_12 work in gpio
+ writel(val, P_PERIPHS_PIN_MUX_1);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xfb000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+#ifdef CONFIG_AML_SPICC
+/* generic config in arch gpio/clock.c */
+extern int spicc_clk_set_rate(int rate);
+extern int spicc_clk_enable(bool enable);
+extern int spicc_pinctrl_enable(bool enable);
+
+static const struct spicc_platdata spicc_platdata = {
+ .compatible = "amlogic,meson-txhd-spicc",
+ .reg = (void __iomem *)0xffd13000,
+ .clk_rate = 666666666,
+ .clk_set_rate = spicc_clk_set_rate,
+ .clk_enable = spicc_clk_enable,
+ .pinctrl_enable = spicc_pinctrl_enable,
+ /* case one slave without cs: {"no_cs", 0} */
+ .cs_gpio_names = {"GPIODV_6", 0},
+};
+
+U_BOOT_DEVICE(spicc) = {
+ .name = "spicc",
+ .platdata = &spicc_platdata,
+};
+#endif /* CONFIG_AML_SPICC */
+
+extern void aml_pwm_cal_init(int mode);
+/*
+ * mtd nand partition table, only care the size!
+ * offset will be calculated by nand driver.
+ */
+#ifdef CONFIG_AML_MTD
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+ /* MUST NOT CHANGE this part unless u know what you are doing!
+ * inherent parition for descrete bootloader to store fip
+ * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+ * name must be same with TPL_PART_NAME
+ */
+ {
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+ },
+#endif
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 15*SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif /* CONFIG_AML_MTD */
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_pwm_cal_init(0);
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
diff --git a/board/amlogic/txl_p320_v1/Kconfig b/board/amlogic/txl_p320_v1/Kconfig
new file mode 100644
index 0000000..4987595
--- /dev/null
+++ b/board/amlogic/txl_p320_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GXTV
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "txl_p320_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "txl"
+
+config SYS_CONFIG_NAME
+ default "txl_p320_v1"
+
+endif
diff --git a/board/amlogic/txl_p320_v1/Makefile b/board/amlogic/txl_p320_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/txl_p320_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/txl_p320_v1/aml-user-key.sig b/board/amlogic/txl_p320_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/txl_p320_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/txl_p320_v1/eth_setup.c b/board/amlogic/txl_p320_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/txl_p320_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/txl_p320_v1/firmware/board_init.c b/board/amlogic/txl_p320_v1/firmware/board_init.c
new file mode 100644
index 0000000..f2d1ecc
--- /dev/null
+++ b/board/amlogic/txl_p320_v1/firmware/board_init.c
@@ -0,0 +1,81 @@
+
+/*
+ * board/amlogic/gxtvbb_p301_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+
+#define PNL_PREG_PAD_GPIO1_EN_N 0x0f
+#define PNL_PREG_PAD_GPIO1_O 0x10
+#define PNL_PREG_PAD_GPIO1_I 0x11
+
+#define PNL_PREG_PAD_GPIO3_EN_N 0x15
+#define PNL_PREG_PAD_GPIO3_O 0x16
+#define PNL_PREG_PAD_GPIO3_I 0x17
+
+#define PNL_REG_BASE (0xc8834400L)
+#define PNL_REG(reg) (PNL_REG_BASE + (reg << 2))
+#define PNL_REG_R(_reg) (*(volatile unsigned int *)PNL_REG(_reg))
+#define PNL_REG_W(_reg, _value) *(volatile unsigned int *)PNL_REG(_reg) = (_value);
+void panel_power_init(void)
+{
+ serial_puts("init panel power\n");
+
+ /* panel: GPIOH_4/5/6/7/8 */ /* remove GPIOH_6 for 2D/3D special case */
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_O) & ~(0x1b << 24)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_EN_N) & ~(0x1b << 24)));
+
+ /* backlight: GPIOZ_2/6/7 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_O) & ~((1 << 2) | (0x3 << 6))));
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_EN_N) & ~((1 << 2) | (0x3 << 6))));
+}
+
+#define SEC_AO_SEC_GP_CFG0 (0xda100000 + (0x90 << 2))
+static int check_is_ddr_inited(void)
+{
+ return ((readl(SEC_AO_SEC_GP_CFG0) >> 16) & 0xffff);
+}
+
+void board_init(void)
+{
+ power_init(0);
+
+ //only run once before ddr inited.
+ if (!check_is_ddr_inited()) {
+ /* dram 1.5V reset */
+ serial_puts("DRAM reset...\n");
+ /* power off ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) & (~((1 << 11) | (1 << 27)))),P_AO_GPIO_O_EN_N);
+ /* need delay, check hw design */
+ _udelay(100000);
+ /* power on ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) | (1 << 27)),P_AO_GPIO_O_EN_N);
+
+ /* dram RC charge time, check hw design */
+ _udelay(10000);
+ }
+
+ panel_power_init();
+}
diff --git a/board/amlogic/txl_p320_v1/firmware/power.c b/board/amlogic/txl_p320_v1/firmware/power.c
new file mode 100644
index 0000000..fe97bf7
--- /dev/null
+++ b/board/amlogic/txl_p320_v1/firmware/power.c
@@ -0,0 +1,182 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/power.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 870},
+ { 0x1b0001, 880},
+ { 0x1a0002, 890},
+ { 0x190003, 900},
+ { 0x180004, 910},
+ { 0x170005, 920},
+ { 0x160006, 930},
+ { 0x150007, 940},
+ { 0x140008, 950},
+ { 0x130009, 960},
+ { 0x12000a, 970},
+ { 0x11000b, 980},
+ { 0x10000c, 990},
+ { 0x0f000d, 1000},
+ { 0x0e000e, 1010},
+ { 0x0d000f, 1020},
+ { 0x0c0010, 1030},
+ { 0x0b0011, 1040},
+ { 0x0a0012, 1050},
+ { 0x090013, 1060},
+ { 0x080014, 1070},
+ { 0x070015, 1080},
+ { 0x060016, 1090},
+ { 0x050017, 1100},
+ { 0x040018, 1110},
+ { 0x030019, 1120},
+ { 0x02001a, 1130},
+ { 0x01001b, 1140},
+ { 0x00001c, 1150}
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_ao_b,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+ int vol;
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26);
+ reg |= (1 << 17);
+ P_PIN_MUX_REG4 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ //vol = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ //writel(vol ,AO_PWM_PWM_B);
+ reg = readl(AO_RTI_PIN_MUX_REG);
+ reg |= (1 << 3);
+ writel(reg, AO_RTI_PIN_MUX_REG);
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vddee enable AO_8 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~(1 << 8);
+ reg |= (1 << 24);
+ writel(reg, AO_GPIO_O_EN_N);
+ serial_puts("set vddee enable AO_2 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~(1 << 2);
+ reg |= (1 << 18);
+ writel(reg, AO_GPIO_O_EN_N);
+}
diff --git a/board/amlogic/txl_p320_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/txl_p320_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..07729c2
--- /dev/null
+++ b/board/amlogic/txl_p320_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,159 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 970+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 1010+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1080+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/txl_p320_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/txl_p320_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..cb148c0
--- /dev/null
+++ b/board/amlogic/txl_p320_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,37 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 870},
+ { 0x1b0001, 880},
+ { 0x1a0002, 890},
+ { 0x190003, 900},
+ { 0x180004, 910},
+ { 0x170005, 920},
+ { 0x160006, 930},
+ { 0x150007, 940},
+ { 0x140008, 950},
+ { 0x130009, 960},
+ { 0x12000a, 970},
+ { 0x11000b, 980},
+ { 0x10000c, 990},
+ { 0x0f000d, 1000},
+ { 0x0e000e, 1010},
+ { 0x0d000f, 1020},
+ { 0x0c0010, 1030},
+ { 0x0b0011, 1040},
+ { 0x0a0012, 1050},
+ { 0x090013, 1060},
+ { 0x080014, 1070},
+ { 0x070015, 1080},
+ { 0x060016, 1090},
+ { 0x050017, 1100},
+ { 0x040018, 1110},
+ { 0x030019, 1120},
+ { 0x02001a, 1130},
+ { 0x01001b, 1140},
+ { 0x00001c, 1150}
+};
diff --git a/board/amlogic/txl_p320_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/txl_p320_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..232c20b
--- /dev/null
+++ b/board/amlogic/txl_p320_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,359 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "pwm_ctrl.h"
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define ON 1
+#define OFF 0
+
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_off_usb5v(void)
+{
+ return;
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ return;
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+}
+
+static void power_off_at_clk81(void)
+{
+
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
+ _udelay(10000);
+}
+static void power_off_ee(void)
+{
+ return;
+ power_switch_to_ee(OFF);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 0);
+}
+
+static void power_on_ee(void)
+{
+ return;
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 1 << 24);
+ _udelay(10000);
+ _udelay(10000);
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+ power_off_usb5v();
+ _udelay(5000);
+ power_off_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_ee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ _udelay(10000);
+ power_on_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ _udelay(10000);
+ _udelay(10000);
+ power_on_usb5v();
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_on_ddr();
+ power_on_ee();
+
+ }
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ //if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+ p->gpio_info_count = 0;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* start timer and enable adc*/
+ reset_ao_timera();
+ saradc_enable();
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ saradc_enable();
+ reset_ao_timera();
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+// if (suspend_from == SYS_POWEROFF)
+// continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ /*uart_puts("timera ...\n");*/
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/txl_p320_v1/firmware/timing.c b/board/amlogic/txl_p320_v1/firmware/timing.c
new file mode 100644
index 0000000..5718d82
--- /dev/null
+++ b/board/amlogic/txl_p320_v1/firmware/timing.c
@@ -0,0 +1,688 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 20
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_120OHM 2
+#define LPDDR3_ODT_240OHM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CONFIG_SOC_VREF (1+ (50+((50*48)/(48+480/(6+1))))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF (1+ (50+((50*37)/(37+48))))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#else
+#define CONFIG_SOC_VREF 51
+#define CONFIG_DRAM_VREF 51
+#endif
+//#define CONFIG_ZQ_VREF 715/15// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (9),
+ .cfg_ddr_refi = (78-2),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = 9,//12,//(23), //6 7 8 9 10 11 ok ,bit0-3 max is 15 ,why use 15 is bad 2016_11_10 jiaxing ,test should change with ddr frequency ?
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#if (CONFIG_LPDDR_REMAP_SET == LPDDR_DIE_ROW_COL_R14_C9)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 0<< 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 |29 << 25 ) ,
+ [4]=( 0| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#elif (CONFIG_LPDDR_REMAP_SET== LPDDR_DIE_ROW_COL_R13_C10)
+ .ddr0_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+ .ddr1_addrmap = {
+ [0]=( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25) ,
+ [1]=( 11| 29 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+ [2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+ [3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
+ [4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+ },
+#endif /*CONFIG_LPDDR_REMAP_SET*/
+#else
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+#endif /*CONFIG_DDR_TYPE_LPDDR3*/
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b | (1<<22),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+//lpddr3
+ .t_pub_zq0pr = 0x0ca1c, //0x0ca1c, //PUB ZQ0PR //lpddr3
+ .t_pub_zq1pr = 0x1cf3c, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x1cf3c, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+/* 2layer board
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+*/
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+/* 4layer ddr4 */
+ .t_pub_zq0pr = 0x09959, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x6f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x6f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#else // ddr3 and auto
+/* p212 4layer board ddr3 */
+ .t_pub_zq0pr = 0x07759, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x6fc5d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x6fc5d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+#endif
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune TAKE CARE LPDDR3 ADD/CMD DELAY
+ .t_pub_aclcdlr = 0,
+ .t_pub_acbdlr3 = 0x2020,//0, //CK0 delay fine tune b-3f //lpddr3 tianhe 2016-10-13
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+//2layer board DDR4
+ .t_pub_acbdlr0 = 0x3f, //0x3f,
+ .t_pub_aclcdlr = 0x50, //0x28,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0x1010, //0x10,// 0x10,//0xa, //cs add 22ohm 08 0ohm 0x10
+#else // ddr3 and auto
+//4layer ddr3
+ .t_pub_acbdlr0 = 0x3f,
+ .t_pub_aclcdlr = 0x50,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0x1010,//0xa, //cs
+#endif
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ //tianhe lpddr3 20161013
+ .wr_adj_per = {
+ [0] = 90, //aclcdlr
+ [1] = 100,
+ [2] = 120,
+ [3] = 110,
+ [4] = 120,
+ [5] = 105,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 110,
+ [3] = 110,
+ [4] = 110,
+ [5] = 110,},
+#else
+ /* P212 */
+ .wr_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=100,
+ [3]=100,
+ [4]=100,
+ [5]=100,
+ },
+ .rd_adj_per = {
+ [0]=100,
+ [1]=100,
+ [2]=95,
+ [3]=95,
+ [4]=95,
+ [5]=95,
+ },
+#endif
+
+ .wr_adj_per_rank1 = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per_rank1 = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 95,
+ [3] = 95,
+ [4] = 95,
+ [5] = 95,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+ .ddr_pll_set = {
+ /* ddr pll ssc config:
+ ppm1000: 0x00120000
+ ppm2000: 0x00140000
+ ppm3000: 0x00160000
+ */
+ [0] = 0x00120000,
+ },
+};
diff --git a/board/amlogic/txl_p320_v1/lcd.c b/board/amlogic/txl_p320_v1/lcd.c
new file mode 100755
index 0000000..9c21e17
--- /dev/null
+++ b/board/amlogic/txl_p320_v1/lcd.c
@@ -0,0 +1,375 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_7",
+ "GPIOZ_3",
+ "GPIOH_4",
+ "GPIOH_5",
+ "GPIOH_6",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,20,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_3d_disable[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_CPU, 4,0,10,}, /* 3d_disable */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_3d_disable[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,20,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 4,2,0,}, /* 3d_disable */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_2",
+ "GPIOZ_6",
+ "GPIOZ_7",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {"lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,30,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {"lvds_1",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,30,0,
+ /* clk_attr */
+ 1,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_3d_disable, lcd_power_off_step_3d_disable,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txl_p320_v1/txl_p320_v1.c b/board/amlogic/txl_p320_v1/txl_p320_v1.c
new file mode 100644
index 0000000..5ceb1f3
--- /dev/null
+++ b/board/amlogic/txl_p320_v1/txl_p320_v1.c
@@ -0,0 +1,532 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm-generic/gpio.h>
+
+#include <asm/arch/mailbox.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/**send_adc_channel_power_key:send adc channel
+ *adc_ch_power_key = 2,0x100;
+ * get env,(2,0x100) 2----------adc channel
+ * 0x100------adc keycode
+ * and keycode to bl301.
+ */
+
+static int send_adc_channel_power_key(void)
+{
+ char *env;
+ unsigned int send_val;
+ unsigned int channel;
+ unsigned int keycode;
+ char *endp;
+ char *s;
+
+ env = getenv("adc_ch_power_key");
+ if (!env) {
+ printf("not set adc env,or try env default -a\n");
+ return -1;
+ }
+ printf("adc env =%s\n", env);
+
+ s = strdup(env);
+ channel = ustrtoul(strsep(&s, ","), &endp, 0);
+ keycode = ustrtoul(strsep(&s, ","), &endp, 0);
+ printf("adc parse channel =%d\n",channel);
+ printf("adc parse keycode = %d\n",keycode);
+
+ send_val = channel << 16 | keycode;
+
+ if (send_usr_data(SCPI_CL_ADC_POWER_KEY, (unsigned int *)&send_val,sizeof(send_val))) {
+ printf("send adc_power_key send error!...\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static int send_ir_power_key(void)
+{
+ char *env;
+ char *endp;
+ unsigned int env_val;
+
+ env = getenv("ir_power_key");
+ if (!env) {
+ printf("not set ir env,or try env default -a\n");
+ return -1;
+ }
+ env_val = ustrtoul(env, &endp, 0);
+ printf("env ir_power_key = %u\n", env_val);
+
+ if (send_usr_data(SCPI_CL_IR_POWER_KEY, (unsigned int *)&env_val,sizeof(env_val))) {
+ printf("send ir_power_key send error!...\n");
+ return -1;
+ }
+ return 0;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret = 0;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ //CLEAR PINMUX
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG,(1<<23)|(1<<5)|(1<<1));//AO_5
+ clrbits_le32(P_PERIPHS_PIN_MUX_2, (1<<13)|(1<<5)|(1<<28));//DV_9
+ //SET GPIOAO_5 OUTPUT 1
+ clrbits_le32(P_AO_GPIO_O_EN_N, 1 << 5);
+ setbits_le32(P_AO_GPIO_O_EN_N, 1 << 21);
+ //SET GPIODV_9 OUTPUT 1
+ clrbits_le32(P_PREG_PAD_GPIO0_EN_N, 1 << 9);
+ setbits_le32(P_PREG_PAD_GPIO0_O, 1 << 9);
+ /* enable 5V for USB, panel, wifi */
+ /* set output mode for GPIOAO_10 */
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<10));
+ /* set output level to high for GPIOAO_10 */
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<26));
+ //run_command("gpio set GPIOAO_4", 0);
+ ret = send_adc_channel_power_key();
+ if (ret != 0) {
+ printf("send adc_power_key failed\n");
+ }
+ ret = send_ir_power_key();
+ if (ret != 0) {
+ printf("send ir_power_key failed\n");
+ }
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
diff --git a/board/amlogic/txl_p321_v1/Kconfig b/board/amlogic/txl_p321_v1/Kconfig
new file mode 100644
index 0000000..b600bec
--- /dev/null
+++ b/board/amlogic/txl_p321_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GXTV
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "txl_p321_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "txl"
+
+config SYS_CONFIG_NAME
+ default "txl_p321_v1"
+
+endif
diff --git a/board/amlogic/txl_p321_v1/Makefile b/board/amlogic/txl_p321_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/txl_p321_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/txl_p321_v1/aml-user-key.sig b/board/amlogic/txl_p321_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/txl_p321_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/txl_p321_v1/eth_setup.c b/board/amlogic/txl_p321_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/txl_p321_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/txl_p321_v1/firmware/board_init.c b/board/amlogic/txl_p321_v1/firmware/board_init.c
new file mode 100644
index 0000000..f2d1ecc
--- /dev/null
+++ b/board/amlogic/txl_p321_v1/firmware/board_init.c
@@ -0,0 +1,81 @@
+
+/*
+ * board/amlogic/gxtvbb_p301_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+
+#define PNL_PREG_PAD_GPIO1_EN_N 0x0f
+#define PNL_PREG_PAD_GPIO1_O 0x10
+#define PNL_PREG_PAD_GPIO1_I 0x11
+
+#define PNL_PREG_PAD_GPIO3_EN_N 0x15
+#define PNL_PREG_PAD_GPIO3_O 0x16
+#define PNL_PREG_PAD_GPIO3_I 0x17
+
+#define PNL_REG_BASE (0xc8834400L)
+#define PNL_REG(reg) (PNL_REG_BASE + (reg << 2))
+#define PNL_REG_R(_reg) (*(volatile unsigned int *)PNL_REG(_reg))
+#define PNL_REG_W(_reg, _value) *(volatile unsigned int *)PNL_REG(_reg) = (_value);
+void panel_power_init(void)
+{
+ serial_puts("init panel power\n");
+
+ /* panel: GPIOH_4/5/6/7/8 */ /* remove GPIOH_6 for 2D/3D special case */
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_O) & ~(0x1b << 24)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_EN_N) & ~(0x1b << 24)));
+
+ /* backlight: GPIOZ_2/6/7 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_O) & ~((1 << 2) | (0x3 << 6))));
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_EN_N) & ~((1 << 2) | (0x3 << 6))));
+}
+
+#define SEC_AO_SEC_GP_CFG0 (0xda100000 + (0x90 << 2))
+static int check_is_ddr_inited(void)
+{
+ return ((readl(SEC_AO_SEC_GP_CFG0) >> 16) & 0xffff);
+}
+
+void board_init(void)
+{
+ power_init(0);
+
+ //only run once before ddr inited.
+ if (!check_is_ddr_inited()) {
+ /* dram 1.5V reset */
+ serial_puts("DRAM reset...\n");
+ /* power off ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) & (~((1 << 11) | (1 << 27)))),P_AO_GPIO_O_EN_N);
+ /* need delay, check hw design */
+ _udelay(100000);
+ /* power on ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) | (1 << 27)),P_AO_GPIO_O_EN_N);
+
+ /* dram RC charge time, check hw design */
+ _udelay(10000);
+ }
+
+ panel_power_init();
+}
diff --git a/board/amlogic/txl_p321_v1/firmware/power.c b/board/amlogic/txl_p321_v1/firmware/power.c
new file mode 100644
index 0000000..fe97bf7
--- /dev/null
+++ b/board/amlogic/txl_p321_v1/firmware/power.c
@@ -0,0 +1,182 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/power.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 870},
+ { 0x1b0001, 880},
+ { 0x1a0002, 890},
+ { 0x190003, 900},
+ { 0x180004, 910},
+ { 0x170005, 920},
+ { 0x160006, 930},
+ { 0x150007, 940},
+ { 0x140008, 950},
+ { 0x130009, 960},
+ { 0x12000a, 970},
+ { 0x11000b, 980},
+ { 0x10000c, 990},
+ { 0x0f000d, 1000},
+ { 0x0e000e, 1010},
+ { 0x0d000f, 1020},
+ { 0x0c0010, 1030},
+ { 0x0b0011, 1040},
+ { 0x0a0012, 1050},
+ { 0x090013, 1060},
+ { 0x080014, 1070},
+ { 0x070015, 1080},
+ { 0x060016, 1090},
+ { 0x050017, 1100},
+ { 0x040018, 1110},
+ { 0x030019, 1120},
+ { 0x02001a, 1130},
+ { 0x01001b, 1140},
+ { 0x00001c, 1150}
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_ao_b,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+ int vol;
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26);
+ reg |= (1 << 17);
+ P_PIN_MUX_REG4 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ //vol = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ //writel(vol ,AO_PWM_PWM_B);
+ reg = readl(AO_RTI_PIN_MUX_REG);
+ reg |= (1 << 3);
+ writel(reg, AO_RTI_PIN_MUX_REG);
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vddee enable AO_8 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~(1 << 8);
+ reg |= (1 << 24);
+ writel(reg, AO_GPIO_O_EN_N);
+ serial_puts("set vddee enable AO_2 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~(1 << 2);
+ reg |= (1 << 18);
+ writel(reg, AO_GPIO_O_EN_N);
+}
diff --git a/board/amlogic/txl_p321_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/txl_p321_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..07729c2
--- /dev/null
+++ b/board/amlogic/txl_p321_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,159 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 970+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 1010+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1080+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/txl_p321_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/txl_p321_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..cb148c0
--- /dev/null
+++ b/board/amlogic/txl_p321_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,37 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 870},
+ { 0x1b0001, 880},
+ { 0x1a0002, 890},
+ { 0x190003, 900},
+ { 0x180004, 910},
+ { 0x170005, 920},
+ { 0x160006, 930},
+ { 0x150007, 940},
+ { 0x140008, 950},
+ { 0x130009, 960},
+ { 0x12000a, 970},
+ { 0x11000b, 980},
+ { 0x10000c, 990},
+ { 0x0f000d, 1000},
+ { 0x0e000e, 1010},
+ { 0x0d000f, 1020},
+ { 0x0c0010, 1030},
+ { 0x0b0011, 1040},
+ { 0x0a0012, 1050},
+ { 0x090013, 1060},
+ { 0x080014, 1070},
+ { 0x070015, 1080},
+ { 0x060016, 1090},
+ { 0x050017, 1100},
+ { 0x040018, 1110},
+ { 0x030019, 1120},
+ { 0x02001a, 1130},
+ { 0x01001b, 1140},
+ { 0x00001c, 1150}
+};
diff --git a/board/amlogic/txl_p321_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/txl_p321_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..b277c22
--- /dev/null
+++ b/board/amlogic/txl_p321_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,428 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "pwm_ctrl.h"
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define ON 1
+#define OFF 0
+
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_off_usb5v(void)
+{
+ unsigned int hwid = 1;
+
+ //CLEAR PINMUX
+ aml_update_bits(AO_RTI_PIN_MUX_REG, (1<<23)|(1<<5)|(1<<1), 0); //AO_5
+ aml_update_bits(PERIPHS_PIN_MUX_2, (1<<13)|(1<<5)|(1<<28), 0); //DV_9
+ //SET GPIOAO_5 OUTPUT 0
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 5, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 21, 0);
+ //SET GPIODV_9 OUTPUT 0
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 9, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 9, 0);
+
+ return ;
+ #if 0
+ //v1
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 0);
+ //v2
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+ #endif
+
+ /* enable 5V for USB, panel, wifi */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+ switch (hwid) {
+ case 1:
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 0);
+ uart_puts("poweroff 5v - hwid 1\n");
+ break;
+ case 2:
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+ uart_puts("poweroff 5v - hwid 2\n");
+ break;
+ default:
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+ uart_puts("poweroff 5v - invalid hwid\n");
+ break;
+ }
+}
+
+static void power_on_usb5v(void)
+{
+ unsigned int hwid = 1;
+
+ //SET GPIOAO_5 OUTPUT 1
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 5, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 21, 1 << 21);
+ //SET GPIODV_9 OUTPUT 1
+ aml_update_bits(PREG_PAD_GPIO0_EN_N, 1 << 9, 0);
+ aml_update_bits(PREG_PAD_GPIO0_O, 1 << 9, 1 << 9);
+
+ return ;
+ #if 0
+ //v1
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 1 << 20);
+ //v2
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+ #endif
+
+ /* enable 5V for USB, panel, wifi */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+ switch (hwid) {
+ case 1:
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 1 << 20);
+ uart_puts("poweron 5v - hwid 1\n");
+ break;
+ case 2:
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+ uart_puts("poweron 5v - hwid 2\n");
+ break;
+ default:
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+ uart_puts("poweron 5v - invalid hwid\n");
+ break;
+ }
+}
+
+static void power_off_at_clk81(void)
+{
+
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
+ _udelay(10000);
+}
+static void power_off_ee(void)
+{
+ return;
+ power_switch_to_ee(OFF);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 0);
+}
+
+static void power_on_ee(void)
+{
+ return;
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 1 << 24);
+ _udelay(10000);
+ _udelay(10000);
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+ power_off_usb5v();
+ _udelay(5000);
+ power_off_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_ee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ _udelay(10000);
+ power_on_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ _udelay(10000);
+ _udelay(10000);
+ power_on_usb5v();
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_on_ddr();
+ power_on_ee();
+
+ }
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ //if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+ p->gpio_info_count = 0;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ saradc_enable();
+ reset_ao_timera();
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+// if (suspend_from == SYS_POWEROFF)
+// continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/txl_p321_v1/firmware/timing.c b/board/amlogic/txl_p321_v1/firmware/timing.c
new file mode 100644
index 0000000..c821248
--- /dev/null
+++ b/board/amlogic/txl_p321_v1/firmware/timing.c
@@ -0,0 +1,587 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 20
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_120OHM 2
+#define LPDDR3_ODT_2400HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_48OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#define CONFIG_SOC_VREF 1+ (50+((50*48)/(48+480/(6+1)))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF 1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+//#define CONFIG_ZQ_VREF 715/15// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b | (1<<22),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR zqvref 0x13
+ //.t_pub_zq0pr = 0x5aa59, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ //.t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR//0x3f95d, 0x4f95d,
+ //.t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR//0x3f95d, 0x4f95d,
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+ //.t_pub_zq3pr = 0xf5f95d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0x3f,
+ .t_pub_aclcdlr = 0x28,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0x10,//0xa, //cs
+ //.t_pub_acbdlr0 = 0x0,
+ //.t_pub_aclcdlr = 0x10,//0x18, ///1t ,if 2t can add some value
+ //.t_pub_acbdlr3 = 0x14,//0xa, //cs
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 95,
+ [3] = 95,
+ [4] = 95,
+ [5] = 95,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 98,
+ [3] = 98,
+ [4] = 98,
+ [5] = 98,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+ .ddr_pll_set = {
+ /* ddr pll ssc config:
+ ppm1000: 0x00120000
+ ppm2000: 0x00140000
+ ppm3000: 0x00160000
+ */
+ [0] = 0x00120000,
+ },
+};
diff --git a/board/amlogic/txl_p321_v1/lcd.c b/board/amlogic/txl_p321_v1/lcd.c
new file mode 100755
index 0000000..9c21e17
--- /dev/null
+++ b/board/amlogic/txl_p321_v1/lcd.c
@@ -0,0 +1,375 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_7",
+ "GPIOZ_3",
+ "GPIOH_4",
+ "GPIOH_5",
+ "GPIOH_6",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,20,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_3d_disable[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_CPU, 4,0,10,}, /* 3d_disable */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_3d_disable[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,20,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 4,2,0,}, /* 3d_disable */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_2",
+ "GPIOZ_6",
+ "GPIOZ_7",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {"lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,30,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {"lvds_1",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,30,0,
+ /* clk_attr */
+ 1,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_3d_disable, lcd_power_off_step_3d_disable,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txl_p321_v1/txl_p321_v1.c b/board/amlogic/txl_p321_v1/txl_p321_v1.c
new file mode 100644
index 0000000..4e29f80
--- /dev/null
+++ b/board/amlogic/txl_p321_v1/txl_p321_v1.c
@@ -0,0 +1,664 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm-generic/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*USE_HDMI_UART_FUNC*/
+#define HDMI_UART_PORT_NUM 3
+
+struct hdmi_uart_date_io {
+ char *power;
+ char *scl;
+ volatile uint32_t * hdmi_sda_reg;
+ unsigned int hdmi_sda_bit;
+ volatile uint32_t * uart_tx_reg;
+ unsigned int uart_tx_bit;
+ volatile uint32_t * hdmi_scl_reg;
+ unsigned int hdmi_scl_bit;
+ volatile uint32_t * uart_rx_reg;
+ unsigned int uart_rx_bit;
+};
+
+struct hdmi_uart_date_io txl_hdmi_uart_date_io[HDMI_UART_PORT_NUM+1]=
+{
+ {"GPIOW_5" ,"GPIOW_7" ,P_PERIPHS_PIN_MUX_5,25,P_PERIPHS_PIN_MUX_5,13,P_PERIPHS_PIN_MUX_5 ,24 ,P_PERIPHS_PIN_MUX_5,12,},
+ {"GPIOW_9", "GPIOW_11",P_PERIPHS_PIN_MUX_5,21,P_PERIPHS_PIN_MUX_5,11,P_PERIPHS_PIN_MUX_5 ,20 ,P_PERIPHS_PIN_MUX_5,10,},
+ {"GPIOW_13","GPIOW_15",P_PERIPHS_PIN_MUX_5,17,P_PERIPHS_PIN_MUX_5,9, P_PERIPHS_PIN_MUX_5 ,16 ,P_PERIPHS_PIN_MUX_5,8,},
+ {NULL, NULL, 0, 0,P_AO_RTI_PIN_MUX_REG,12,0 , 0 ,P_AO_RTI_PIN_MUX_REG,11,},
+};
+
+struct hdmi_uart_date_io gxtvbb_hdmi_uart_date_io[HDMI_UART_PORT_NUM+1]=
+{
+ {"GPIOW_6" ,"GPIOW_5" ,P_PERIPHS_PIN_MUX_6 ,9 ,P_PERIPHS_PIN_MUX_10,1,P_PERIPHS_PIN_MUX_6 ,10 ,P_PERIPHS_PIN_MUX_6,11,},
+ {"GPIOW_10","GPIOW_9" ,P_PERIPHS_PIN_MUX_6 ,14 ,P_PERIPHS_PIN_MUX_10,2,P_PERIPHS_PIN_MUX_6 ,15 ,P_PERIPHS_PIN_MUX_6,16,},
+ {"GPIOW_14","GPIOW_13",P_PERIPHS_PIN_MUX_6 ,19 ,P_PERIPHS_PIN_MUX_10,3,P_PERIPHS_PIN_MUX_6 ,20 ,P_PERIPHS_PIN_MUX_6,21,},
+ {NULL, NULL, 0, 0 ,P_AO_RTI_PIN_MUX_REG,0,0 , 0 ,P_AO_RTI_PIN_MUX_REG,1,},
+};
+
+struct hdmi_uart_det_io {
+ char *power;
+ char *scl;
+ volatile uint32_t * uart_det_power_reg;
+ unsigned int uart_det_power_bit;
+ unsigned int uart_det_power_need_level;
+ volatile uint32_t * uart_det_scl_reg;
+ unsigned int uart_det_scl_bit;
+ unsigned int uart_det_scl_need_level;
+};
+
+struct hdmi_uart_det_io txl_hdmi_uart_det_io[HDMI_UART_PORT_NUM]=
+{
+ {"GPIOW_5" , "GPIOW_7" , P_PREG_PAD_GPIO4_I , 5 , 0, P_PREG_PAD_GPIO4_I ,7 , 1,},
+ {"GPIOW_9", "GPIOW_11", P_PREG_PAD_GPIO4_I , 9 , 0, P_PREG_PAD_GPIO4_I ,11, 1,},
+ {"GPIOW_13", "GPIOW_15" , P_PREG_PAD_GPIO4_I , 13, 0, P_PREG_PAD_GPIO4_I ,15, 1,},
+};
+
+/* in gxtvbb,use hpd port as (txl)scl port */
+struct hdmi_uart_det_io gxtvbb_hdmi_uart_det_io[HDMI_UART_PORT_NUM]=
+{
+ {"GPIOW_6" ,"GPIOW_5" , P_PREG_PAD_GPIO0_I, 6 , 0, P_PREG_PAD_GPIO0_I ,5 , 1,},
+ {"GPIOW_10","GPIOW_9" , P_PREG_PAD_GPIO0_I, 10, 0, P_PREG_PAD_GPIO0_I ,9 , 1,},
+ {"GPIOW_14","GPIOW_13", P_PREG_PAD_GPIO0_I, 14, 0, P_PREG_PAD_GPIO0_I ,13, 1,},
+};
+
+static void init_hdmi_uart_board(void)
+{
+ int i=0;
+ int pwr_value=0,scl_value=0;
+ int flag=0;
+ struct hdmi_uart_date_io *hdmi_uart_date_io;
+ struct hdmi_uart_det_io *hdmi_uart_det_io;
+
+ if (get_cpu_id().family_id <= MESON_CPU_MAJOR_ID_GXTVBB) {
+ hdmi_uart_det_io = gxtvbb_hdmi_uart_det_io;
+ hdmi_uart_date_io = gxtvbb_hdmi_uart_date_io;
+ /*printf("choose gxtvbb board.\n");*/
+ } else {
+ hdmi_uart_det_io = txl_hdmi_uart_det_io;
+ hdmi_uart_date_io = txl_hdmi_uart_date_io;
+ /*printf("choose txl board.\n");*/
+ }
+
+ for (i=0; i<HDMI_UART_PORT_NUM; i++) {
+ pwr_value = readl(hdmi_uart_det_io[i].uart_det_power_reg) >> hdmi_uart_det_io[i].uart_det_power_bit;
+ pwr_value &= 1;
+ scl_value = readl(hdmi_uart_det_io[i].uart_det_scl_reg) >> hdmi_uart_det_io[i].uart_det_scl_bit;
+ scl_value &= 1;
+
+ if ((pwr_value == hdmi_uart_det_io[i].uart_det_power_need_level)
+ && (scl_value == hdmi_uart_det_io[i].uart_det_scl_need_level)) {
+ flag = 1;
+ break;
+ }
+ }
+
+ if (flag == 1) {
+ printf("switch to %d hdmirx_uart port\n",i);
+ /* clean default uart pinmux */
+ writel(readl(hdmi_uart_date_io[3].uart_tx_reg)&~(1 << hdmi_uart_date_io[3].uart_tx_bit),
+ (volatile void *)hdmi_uart_date_io[3].uart_tx_reg);
+ writel(readl(hdmi_uart_date_io[3].uart_rx_reg)&~(1 << hdmi_uart_date_io[3].uart_rx_bit),
+ (volatile void *)hdmi_uart_date_io[3].uart_rx_reg);
+
+ /* set hdmi_uart pinmux */
+ writel(readl(hdmi_uart_date_io[i].hdmi_sda_reg)&~(1 << hdmi_uart_date_io[i].hdmi_sda_bit),
+ (volatile void *)hdmi_uart_date_io[i].hdmi_sda_reg);
+ writel(readl(hdmi_uart_date_io[i].uart_tx_reg)|(1 << hdmi_uart_date_io[i].uart_tx_bit),
+ (volatile void *)hdmi_uart_date_io[i].uart_tx_reg);
+
+ writel(readl(hdmi_uart_date_io[i].hdmi_scl_reg)&~(1 << hdmi_uart_date_io[i].hdmi_scl_bit),
+ (volatile void *)hdmi_uart_date_io[i].hdmi_scl_reg);
+ writel(readl(hdmi_uart_date_io[i].uart_rx_reg)|(1 << hdmi_uart_date_io[i].uart_rx_bit),
+ (volatile void *)hdmi_uart_date_io[i].uart_rx_reg);
+ }
+}
+/*endif*/
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+ char* env;
+ unsigned int hwid = 1;
+
+ /*USE_HDMI_UART_FUNC*/
+ env = getenv("hdmiuart_mode");
+ /*printf("hdmiuart_mode env:%s\n",env);*/
+ if (env) {
+ if (!strcmp(env,"open")) {
+ printf("CONFIG_HDMI_UART_BOARD\n");
+ init_hdmi_uart_board();
+ }
+ }
+ /*endif*/
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ //CLEAR PINMUX
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG,(1<<23)|(1<<5)|(1<<1));//AO_5
+ clrbits_le32(P_PERIPHS_PIN_MUX_2, (1<<13)|(1<<5)|(1<<28));//DV_9
+ //SET GPIOAO_5 OUTPUT 1
+ clrbits_le32(P_AO_GPIO_O_EN_N, 1 << 5);
+ setbits_le32(P_AO_GPIO_O_EN_N, 1 << 21);
+ //SET GPIODV_9 OUTPUT 1
+ clrbits_le32(P_PREG_PAD_GPIO0_EN_N, 1 << 9);
+ setbits_le32(P_PREG_PAD_GPIO0_O, 1 << 9);
+
+ /* enable 5V for USB, panel, wifi */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+ switch (hwid) {
+ case 1:
+ run_command("gpio set GPIOAO_4", 0);
+ break;
+ case 2:
+ /* set output mode for GPIOAO_10 */
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<10));
+ /* set output level to high for GPIOAO_10 */
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<26));
+ break;
+ default:
+ /* set output mode for GPIOAO_10 */
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<10));
+ /* set output level to high for GPIOAO_10 */
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<26));
+ printf("invalid hwid = %d\n", hwid);
+ break;
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 1 p321 v1
+ * hwid = 2 p321 v2
+ */
+ unsigned int ddr_size=0;
+ unsigned int hwid = 1;
+ char loc_name[64] = {0};
+ int i;
+
+ /* read ddr size */
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+
+ switch (hwid) {
+ case 1:
+ strcpy(loc_name, "txl_p321_v1\0");
+ break;
+ case 2:
+ switch (ddr_size) {
+ case 0x80000000:
+ strcpy(loc_name, "txl_p321_v2-2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "txl_p321_v2-1g\0");
+ break;
+ default:
+ strcpy(loc_name, "txl_p321_unsupport");
+ break;
+ }
+ break;
+ default:
+ strcpy(loc_name, "txl_p321_v1");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/txl_p341_v1/Kconfig b/board/amlogic/txl_p341_v1/Kconfig
new file mode 100644
index 0000000..7c93e7b
--- /dev/null
+++ b/board/amlogic/txl_p341_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_TXL
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "txl_p341_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "txl"
+
+config SYS_CONFIG_NAME
+ default "txl_p341_v1"
+
+endif
diff --git a/board/amlogic/txl_p341_v1/Makefile b/board/amlogic/txl_p341_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/txl_p341_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/txl_p341_v1/aml-user-key.sig b/board/amlogic/txl_p341_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/txl_p341_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/txl_p341_v1/eth_setup.c b/board/amlogic/txl_p341_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/txl_p341_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/txl_p341_v1/firmware/board_init.c b/board/amlogic/txl_p341_v1/firmware/board_init.c
new file mode 100644
index 0000000..f2d1ecc
--- /dev/null
+++ b/board/amlogic/txl_p341_v1/firmware/board_init.c
@@ -0,0 +1,81 @@
+
+/*
+ * board/amlogic/gxtvbb_p301_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+
+#define PNL_PREG_PAD_GPIO1_EN_N 0x0f
+#define PNL_PREG_PAD_GPIO1_O 0x10
+#define PNL_PREG_PAD_GPIO1_I 0x11
+
+#define PNL_PREG_PAD_GPIO3_EN_N 0x15
+#define PNL_PREG_PAD_GPIO3_O 0x16
+#define PNL_PREG_PAD_GPIO3_I 0x17
+
+#define PNL_REG_BASE (0xc8834400L)
+#define PNL_REG(reg) (PNL_REG_BASE + (reg << 2))
+#define PNL_REG_R(_reg) (*(volatile unsigned int *)PNL_REG(_reg))
+#define PNL_REG_W(_reg, _value) *(volatile unsigned int *)PNL_REG(_reg) = (_value);
+void panel_power_init(void)
+{
+ serial_puts("init panel power\n");
+
+ /* panel: GPIOH_4/5/6/7/8 */ /* remove GPIOH_6 for 2D/3D special case */
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_O) & ~(0x1b << 24)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_EN_N) & ~(0x1b << 24)));
+
+ /* backlight: GPIOZ_2/6/7 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_O) & ~((1 << 2) | (0x3 << 6))));
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_EN_N) & ~((1 << 2) | (0x3 << 6))));
+}
+
+#define SEC_AO_SEC_GP_CFG0 (0xda100000 + (0x90 << 2))
+static int check_is_ddr_inited(void)
+{
+ return ((readl(SEC_AO_SEC_GP_CFG0) >> 16) & 0xffff);
+}
+
+void board_init(void)
+{
+ power_init(0);
+
+ //only run once before ddr inited.
+ if (!check_is_ddr_inited()) {
+ /* dram 1.5V reset */
+ serial_puts("DRAM reset...\n");
+ /* power off ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) & (~((1 << 11) | (1 << 27)))),P_AO_GPIO_O_EN_N);
+ /* need delay, check hw design */
+ _udelay(100000);
+ /* power on ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) | (1 << 27)),P_AO_GPIO_O_EN_N);
+
+ /* dram RC charge time, check hw design */
+ _udelay(10000);
+ }
+
+ panel_power_init();
+}
diff --git a/board/amlogic/txl_p341_v1/firmware/power.c b/board/amlogic/txl_p341_v1/firmware/power.c
new file mode 100644
index 0000000..de64d0d
--- /dev/null
+++ b/board/amlogic/txl_p341_v1/firmware/power.c
@@ -0,0 +1,184 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/power.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+
+
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_ao_b,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+ int vol;
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26);
+ reg |= (1 << 17);
+ P_PIN_MUX_REG4 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ //vol = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ //writel(vol ,AO_PWM_PWM_B);
+ reg = readl(AO_RTI_PIN_MUX_REG);
+ reg |= (1 << 3);
+ writel(reg, AO_RTI_PIN_MUX_REG);
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vddee enable AO_8 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~(1 << 8);
+ reg |= (1 << 24);
+ writel(reg, AO_GPIO_O_EN_N);
+ serial_puts("set vddee enable AO_2 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~(1 << 2);
+ reg |= (1 << 18);
+ writel(reg, AO_GPIO_O_EN_N);
+}
diff --git a/board/amlogic/txl_p341_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/txl_p341_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..eef06da
--- /dev/null
+++ b/board/amlogic/txl_p341_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,169 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 950+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 950+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 950+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 950+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 950+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 950+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+/*
+ * gpioao_9 pwm_ao_b is used to adjust VDD_EE
+ */
+#define P_PIN_MUX_AO_REG (*((volatile unsigned *)(0xc8100000 + (0x5 << 2))))
+
+#define P_AO_PWM_MISC_REG_AB1 (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+
+void pwm_init(int id)
+{
+//vddee vcck together
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+
+ uart_puts("pwm init in M3\n");
+ reg = P_AO_PWM_MISC_REG_AB1;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_AO_PWM_MISC_REG_AB1 = reg;
+ /*
+ * default set to max voltage
+ */
+
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 14][0];
+ reg = P_PIN_MUX_AO_REG;
+ reg |= (1 << 3);
+ P_PIN_MUX_AO_REG = reg;
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_AO_PWM_PWM_B1;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_ao_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/txl_p341_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/txl_p341_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..7b67562
--- /dev/null
+++ b/board/amlogic/txl_p341_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,37 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
diff --git a/board/amlogic/txl_p341_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/txl_p341_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..54bb46f
--- /dev/null
+++ b/board/amlogic/txl_p341_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,375 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "pwm_ctrl.h"
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define ON 1
+#define OFF 0
+
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_off_usb5v(void)
+{
+ #if 0
+ //v1
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 0);
+ //v2
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+ #endif
+
+ /* enable 5V for USB, panel, wifi */
+
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ //unsigned int hwid = 1;
+ #if 0
+ //v1
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 1 << 20);
+ //v2
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+ #endif
+
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+
+}
+
+static void power_off_at_clk81(void)
+{
+
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
+ _udelay(10000);
+}
+static void power_off_ee(void)
+{
+ return;
+ power_switch_to_ee(OFF);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 0);
+}
+
+static void power_on_ee(void)
+{
+ return;
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 1 << 24);
+ _udelay(10000);
+ _udelay(10000);
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+ power_off_usb5v();
+ _udelay(5000);
+ power_off_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_ee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ _udelay(10000);
+ power_on_3v3_5v();
+ //pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ _udelay(10000);
+ _udelay(10000);
+ power_on_usb5v();
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_on_ddr();
+ power_on_ee();
+
+ }
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ //if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+ p->gpio_info_count = 0;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ saradc_enable();
+ reset_ao_timera();
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+// if (suspend_from == SYS_POWEROFF)
+// continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/txl_p341_v1/firmware/timing.c b/board/amlogic/txl_p341_v1/firmware/timing.c
new file mode 100644
index 0000000..c821248
--- /dev/null
+++ b/board/amlogic/txl_p341_v1/firmware/timing.c
@@ -0,0 +1,587 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 20
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_120OHM 2
+#define LPDDR3_ODT_2400HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_48OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#define CONFIG_SOC_VREF 1+ (50+((50*48)/(48+480/(6+1)))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF 1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+//#define CONFIG_ZQ_VREF 715/15// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b | (1<<22),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR zqvref 0x13
+ //.t_pub_zq0pr = 0x5aa59, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ //.t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR//0x3f95d, 0x4f95d,
+ //.t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR//0x3f95d, 0x4f95d,
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+ //.t_pub_zq3pr = 0xf5f95d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0x3f,
+ .t_pub_aclcdlr = 0x28,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0x10,//0xa, //cs
+ //.t_pub_acbdlr0 = 0x0,
+ //.t_pub_aclcdlr = 0x10,//0x18, ///1t ,if 2t can add some value
+ //.t_pub_acbdlr3 = 0x14,//0xa, //cs
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 95,
+ [3] = 95,
+ [4] = 95,
+ [5] = 95,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 98,
+ [3] = 98,
+ [4] = 98,
+ [5] = 98,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+ .ddr_pll_set = {
+ /* ddr pll ssc config:
+ ppm1000: 0x00120000
+ ppm2000: 0x00140000
+ ppm3000: 0x00160000
+ */
+ [0] = 0x00120000,
+ },
+};
diff --git a/board/amlogic/txl_p341_v1/lcd.c b/board/amlogic/txl_p341_v1/lcd.c
new file mode 100755
index 0000000..9c21e17
--- /dev/null
+++ b/board/amlogic/txl_p341_v1/lcd.c
@@ -0,0 +1,375 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_7",
+ "GPIOZ_3",
+ "GPIOH_4",
+ "GPIOH_5",
+ "GPIOH_6",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,20,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_3d_disable[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_CPU, 4,0,10,}, /* 3d_disable */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_3d_disable[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,20,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 4,2,0,}, /* 3d_disable */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_2",
+ "GPIOZ_6",
+ "GPIOZ_7",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {"lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,30,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {"lvds_1",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,30,0,
+ /* clk_attr */
+ 1,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_3d_disable, lcd_power_off_step_3d_disable,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txl_p341_v1/txl_p341_v1.c b/board/amlogic/txl_p341_v1/txl_p341_v1.c
new file mode 100644
index 0000000..9c4c23e
--- /dev/null
+++ b/board/amlogic/txl_p341_v1/txl_p341_v1.c
@@ -0,0 +1,625 @@
+
+/*
+ * board/amlogic/txl_p341_v1/txl_p341_v1.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm-generic/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*USE_HDMI_UART_FUNC*/
+#define HDMI_UART_PORT_NUM 3
+
+struct hdmi_uart_date_io {
+ char *power;
+ char *scl;
+ volatile uint32_t * hdmi_sda_reg;
+ unsigned int hdmi_sda_bit;
+ volatile uint32_t * uart_tx_reg;
+ unsigned int uart_tx_bit;
+ volatile uint32_t * hdmi_scl_reg;
+ unsigned int hdmi_scl_bit;
+ volatile uint32_t * uart_rx_reg;
+ unsigned int uart_rx_bit;
+};
+
+struct hdmi_uart_date_io txl_hdmi_uart_date_io[HDMI_UART_PORT_NUM+1]=
+{
+ {"GPIOW_5" ,"GPIOW_7" ,P_PERIPHS_PIN_MUX_5,25,P_PERIPHS_PIN_MUX_5,13,P_PERIPHS_PIN_MUX_5 ,24 ,P_PERIPHS_PIN_MUX_5,12,},
+ {"GPIOW_9", "GPIOW_11",P_PERIPHS_PIN_MUX_5,21,P_PERIPHS_PIN_MUX_5,11,P_PERIPHS_PIN_MUX_5 ,20 ,P_PERIPHS_PIN_MUX_5,10,},
+ {"GPIOW_13","GPIOW_15",P_PERIPHS_PIN_MUX_5,17,P_PERIPHS_PIN_MUX_5,9, P_PERIPHS_PIN_MUX_5 ,16 ,P_PERIPHS_PIN_MUX_5,8,},
+ {NULL, NULL, 0, 0,P_AO_RTI_PIN_MUX_REG,12,0 , 0 ,P_AO_RTI_PIN_MUX_REG,11,},
+};
+
+struct hdmi_uart_date_io gxtvbb_hdmi_uart_date_io[HDMI_UART_PORT_NUM+1]=
+{
+ {"GPIOW_6" ,"GPIOW_5" ,P_PERIPHS_PIN_MUX_6 ,9 ,P_PERIPHS_PIN_MUX_10,1,P_PERIPHS_PIN_MUX_6 ,10 ,P_PERIPHS_PIN_MUX_6,11,},
+ {"GPIOW_10","GPIOW_9" ,P_PERIPHS_PIN_MUX_6 ,14 ,P_PERIPHS_PIN_MUX_10,2,P_PERIPHS_PIN_MUX_6 ,15 ,P_PERIPHS_PIN_MUX_6,16,},
+ {"GPIOW_14","GPIOW_13",P_PERIPHS_PIN_MUX_6 ,19 ,P_PERIPHS_PIN_MUX_10,3,P_PERIPHS_PIN_MUX_6 ,20 ,P_PERIPHS_PIN_MUX_6,21,},
+ {NULL, NULL, 0, 0 ,P_AO_RTI_PIN_MUX_REG,0,0 , 0 ,P_AO_RTI_PIN_MUX_REG,1,},
+};
+
+struct hdmi_uart_det_io {
+ char *power;
+ char *scl;
+ volatile uint32_t * uart_det_power_reg;
+ unsigned int uart_det_power_bit;
+ unsigned int uart_det_power_need_level;
+ volatile uint32_t * uart_det_scl_reg;
+ unsigned int uart_det_scl_bit;
+ unsigned int uart_det_scl_need_level;
+};
+
+struct hdmi_uart_det_io txl_hdmi_uart_det_io[HDMI_UART_PORT_NUM]=
+{
+ {"GPIOW_5" , "GPIOW_7" , P_PREG_PAD_GPIO4_I , 5 , 0, P_PREG_PAD_GPIO4_I ,7 , 1,},
+ {"GPIOW_9", "GPIOW_11", P_PREG_PAD_GPIO4_I , 9 , 0, P_PREG_PAD_GPIO4_I ,11, 1,},
+ {"GPIOW_13", "GPIOW_15" , P_PREG_PAD_GPIO4_I , 13, 0, P_PREG_PAD_GPIO4_I ,15, 1,},
+};
+
+/* in gxtvbb,use hpd port as (txl)scl port */
+struct hdmi_uart_det_io gxtvbb_hdmi_uart_det_io[HDMI_UART_PORT_NUM]=
+{
+ {"GPIOW_6" ,"GPIOW_5" , P_PREG_PAD_GPIO0_I, 6 , 0, P_PREG_PAD_GPIO0_I ,5 , 1,},
+ {"GPIOW_10","GPIOW_9" , P_PREG_PAD_GPIO0_I, 10, 0, P_PREG_PAD_GPIO0_I ,9 , 1,},
+ {"GPIOW_14","GPIOW_13", P_PREG_PAD_GPIO0_I, 14, 0, P_PREG_PAD_GPIO0_I ,13, 1,},
+};
+
+static void init_hdmi_uart_board(void)
+{
+ int i=0;
+ int pwr_value=0,scl_value=0;
+ int flag=0;
+ struct hdmi_uart_date_io *hdmi_uart_date_io;
+ struct hdmi_uart_det_io *hdmi_uart_det_io;
+
+ if (get_cpu_id().family_id <= MESON_CPU_MAJOR_ID_GXTVBB) {
+ hdmi_uart_det_io = gxtvbb_hdmi_uart_det_io;
+ hdmi_uart_date_io = gxtvbb_hdmi_uart_date_io;
+ /*printf("choose gxtvbb board.\n");*/
+ } else {
+ hdmi_uart_det_io = txl_hdmi_uart_det_io;
+ hdmi_uart_date_io = txl_hdmi_uart_date_io;
+ /*printf("choose txl board.\n");*/
+ }
+
+ for (i=0; i<HDMI_UART_PORT_NUM; i++) {
+ pwr_value = readl(hdmi_uart_det_io[i].uart_det_power_reg) >> hdmi_uart_det_io[i].uart_det_power_bit;
+ pwr_value &= 1;
+ scl_value = readl(hdmi_uart_det_io[i].uart_det_scl_reg) >> hdmi_uart_det_io[i].uart_det_scl_bit;
+ scl_value &= 1;
+
+ if ((pwr_value == hdmi_uart_det_io[i].uart_det_power_need_level)
+ && (scl_value == hdmi_uart_det_io[i].uart_det_scl_need_level)) {
+ flag = 1;
+ break;
+ }
+ }
+
+ if (flag == 1) {
+ printf("switch to %d hdmirx_uart port\n",i);
+ /* clean default uart pinmux */
+ writel(readl(hdmi_uart_date_io[3].uart_tx_reg)&~(1 << hdmi_uart_date_io[3].uart_tx_bit),
+ (volatile void *)hdmi_uart_date_io[3].uart_tx_reg);
+ writel(readl(hdmi_uart_date_io[3].uart_rx_reg)&~(1 << hdmi_uart_date_io[3].uart_rx_bit),
+ (volatile void *)hdmi_uart_date_io[3].uart_rx_reg);
+
+ /* set hdmi_uart pinmux */
+ writel(readl(hdmi_uart_date_io[i].hdmi_sda_reg)&~(1 << hdmi_uart_date_io[i].hdmi_sda_bit),
+ (volatile void *)hdmi_uart_date_io[i].hdmi_sda_reg);
+ writel(readl(hdmi_uart_date_io[i].uart_tx_reg)|(1 << hdmi_uart_date_io[i].uart_tx_bit),
+ (volatile void *)hdmi_uart_date_io[i].uart_tx_reg);
+
+ writel(readl(hdmi_uart_date_io[i].hdmi_scl_reg)&~(1 << hdmi_uart_date_io[i].hdmi_scl_bit),
+ (volatile void *)hdmi_uart_date_io[i].hdmi_scl_reg);
+ writel(readl(hdmi_uart_date_io[i].uart_rx_reg)|(1 << hdmi_uart_date_io[i].uart_rx_bit),
+ (volatile void *)hdmi_uart_date_io[i].uart_rx_reg);
+ }
+}
+/*endif*/
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+writel(readl(AO_GPIO_O_EN_N) & (~(0x1 << 10)), AO_GPIO_O_EN_N); //set mode: output
+writel(readl(AO_GPIO_O_EN_N) | (0x1 << 26),AO_GPIO_O_EN_N); //output 1
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+ char* env;
+ unsigned int hwid = 1;
+ unsigned int ddr_size=0;
+ int i;
+
+ /*USE_HDMI_UART_FUNC*/
+ env = getenv("hdmiuart_mode");
+ /*printf("hdmiuart_mode env:%s\n",env);*/
+ if (env) {
+ if (!strcmp(env,"open")) {
+ printf("CONFIG_HDMI_UART_BOARD\n");
+ init_hdmi_uart_board();
+ }
+ }
+ /*endif*/
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+ if (ddr_size == 0x20000000) {
+ /* 512M p341 */
+ run_command("setenv display_width 1280; setenv display_height 720;", 0);
+ run_command("setenv fb_addr 0x6000000; setenv fb_width 1280; setenv fb_height 720;", 0);
+ }
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+
+ /* enable 5V for USB, panel, wifi */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+ switch (hwid) {
+ case 1:
+ run_command("gpio set GPIOAO_4", 0);
+ break;
+ case 2:
+ /* set output mode for GPIOAO_10 */
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<10));
+ /* set output level to high for GPIOAO_10 */
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<26));
+ break;
+ default:
+ /* set output mode for GPIOAO_10 */
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<10));
+ /* set output level to high for GPIOAO_10 */
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<26));
+ printf("invalid hwid = %d\n", hwid);
+ break;
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ */
+ unsigned int hwid = 1;
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/txl_p341_v2/Kconfig b/board/amlogic/txl_p341_v2/Kconfig
new file mode 100644
index 0000000..a03c2d6
--- /dev/null
+++ b/board/amlogic/txl_p341_v2/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_TXL
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "txl_p341_v2"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "txl"
+
+config SYS_CONFIG_NAME
+ default "txl_p341_v2"
+
+endif
diff --git a/board/amlogic/txl_p341_v2/Makefile b/board/amlogic/txl_p341_v2/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/txl_p341_v2/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/txl_p341_v2/aml-user-key.sig b/board/amlogic/txl_p341_v2/aml-user-key.sig
new file mode 100755
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/txl_p341_v2/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/txl_p341_v2/eth_setup.c b/board/amlogic/txl_p341_v2/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/txl_p341_v2/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/txl_p341_v2/firmware/board_init.c b/board/amlogic/txl_p341_v2/firmware/board_init.c
new file mode 100644
index 0000000..f2d1ecc
--- /dev/null
+++ b/board/amlogic/txl_p341_v2/firmware/board_init.c
@@ -0,0 +1,81 @@
+
+/*
+ * board/amlogic/gxtvbb_p301_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+
+#define PNL_PREG_PAD_GPIO1_EN_N 0x0f
+#define PNL_PREG_PAD_GPIO1_O 0x10
+#define PNL_PREG_PAD_GPIO1_I 0x11
+
+#define PNL_PREG_PAD_GPIO3_EN_N 0x15
+#define PNL_PREG_PAD_GPIO3_O 0x16
+#define PNL_PREG_PAD_GPIO3_I 0x17
+
+#define PNL_REG_BASE (0xc8834400L)
+#define PNL_REG(reg) (PNL_REG_BASE + (reg << 2))
+#define PNL_REG_R(_reg) (*(volatile unsigned int *)PNL_REG(_reg))
+#define PNL_REG_W(_reg, _value) *(volatile unsigned int *)PNL_REG(_reg) = (_value);
+void panel_power_init(void)
+{
+ serial_puts("init panel power\n");
+
+ /* panel: GPIOH_4/5/6/7/8 */ /* remove GPIOH_6 for 2D/3D special case */
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_O) & ~(0x1b << 24)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_EN_N) & ~(0x1b << 24)));
+
+ /* backlight: GPIOZ_2/6/7 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_O) & ~((1 << 2) | (0x3 << 6))));
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_EN_N) & ~((1 << 2) | (0x3 << 6))));
+}
+
+#define SEC_AO_SEC_GP_CFG0 (0xda100000 + (0x90 << 2))
+static int check_is_ddr_inited(void)
+{
+ return ((readl(SEC_AO_SEC_GP_CFG0) >> 16) & 0xffff);
+}
+
+void board_init(void)
+{
+ power_init(0);
+
+ //only run once before ddr inited.
+ if (!check_is_ddr_inited()) {
+ /* dram 1.5V reset */
+ serial_puts("DRAM reset...\n");
+ /* power off ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) & (~((1 << 11) | (1 << 27)))),P_AO_GPIO_O_EN_N);
+ /* need delay, check hw design */
+ _udelay(100000);
+ /* power on ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) | (1 << 27)),P_AO_GPIO_O_EN_N);
+
+ /* dram RC charge time, check hw design */
+ _udelay(10000);
+ }
+
+ panel_power_init();
+}
diff --git a/board/amlogic/txl_p341_v2/firmware/power.c b/board/amlogic/txl_p341_v2/firmware/power.c
new file mode 100644
index 0000000..395c6e5
--- /dev/null
+++ b/board/amlogic/txl_p341_v2/firmware/power.c
@@ -0,0 +1,182 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/power.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_ao_b,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+ int vol;
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26);
+ reg |= (1 << 17);
+ P_PIN_MUX_REG4 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ //vol = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ //writel(vol ,AO_PWM_PWM_B);
+ reg = readl(AO_RTI_PIN_MUX_REG);
+ reg |= (1 << 3);
+ writel(reg, AO_RTI_PIN_MUX_REG);
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vddee enable AO_8 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~(1 << 8);
+ reg |= (1 << 24);
+ writel(reg, AO_GPIO_O_EN_N);
+ serial_puts("set vddee enable AO_2 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~(1 << 2);
+ reg |= (1 << 18);
+ writel(reg, AO_GPIO_O_EN_N);
+}
diff --git a/board/amlogic/txl_p341_v2/firmware/scp_task/dvfs_board.c b/board/amlogic/txl_p341_v2/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..4f2ea4c
--- /dev/null
+++ b/board/amlogic/txl_p341_v2/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,164 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 970+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 1010+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1080+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+/*
+ * gpioao_9 pwm_ao_b is used to adjust VDD_EE
+ */
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/txl_p341_v2/firmware/scp_task/pwm_ctrl.h b/board/amlogic/txl_p341_v2/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..7b67562
--- /dev/null
+++ b/board/amlogic/txl_p341_v2/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,37 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
diff --git a/board/amlogic/txl_p341_v2/firmware/scp_task/pwr_ctrl.c b/board/amlogic/txl_p341_v2/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..c82a08c
--- /dev/null
+++ b/board/amlogic/txl_p341_v2/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,375 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "pwm_ctrl.h"
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define ON 1
+#define OFF 0
+
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_off_usb5v(void)
+{
+ #if 0
+ //v1
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 0);
+ //v2
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+ #endif
+
+ /* enable 5V for USB, panel, wifi */
+
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ //unsigned int hwid = 1;
+ #if 0
+ //v1
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 1 << 20);
+ //v2
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+ #endif
+
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+
+}
+
+static void power_off_at_clk81(void)
+{
+
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
+ _udelay(10000);
+}
+static void power_off_ee(void)
+{
+ return;
+ power_switch_to_ee(OFF);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 0);
+}
+
+static void power_on_ee(void)
+{
+ return;
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 1 << 24);
+ _udelay(10000);
+ _udelay(10000);
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+ power_off_usb5v();
+ _udelay(5000);
+ power_off_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_ee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ _udelay(10000);
+ power_on_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ _udelay(10000);
+ _udelay(10000);
+ power_on_usb5v();
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_on_ddr();
+ power_on_ee();
+
+ }
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ //if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+ p->gpio_info_count = 0;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ saradc_enable();
+ reset_ao_timera();
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+// if (suspend_from == SYS_POWEROFF)
+// continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/txl_p341_v2/firmware/timing.c b/board/amlogic/txl_p341_v2/firmware/timing.c
new file mode 100644
index 0000000..c821248
--- /dev/null
+++ b/board/amlogic/txl_p341_v2/firmware/timing.c
@@ -0,0 +1,587 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 20
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_120OHM 2
+#define LPDDR3_ODT_2400HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_48OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#define CONFIG_SOC_VREF 1+ (50+((50*48)/(48+480/(6+1)))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF 1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+//#define CONFIG_ZQ_VREF 715/15// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b | (1<<22),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR zqvref 0x13
+ //.t_pub_zq0pr = 0x5aa59, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ //.t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR//0x3f95d, 0x4f95d,
+ //.t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR//0x3f95d, 0x4f95d,
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+ //.t_pub_zq3pr = 0xf5f95d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0x3f,
+ .t_pub_aclcdlr = 0x28,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0x10,//0xa, //cs
+ //.t_pub_acbdlr0 = 0x0,
+ //.t_pub_aclcdlr = 0x10,//0x18, ///1t ,if 2t can add some value
+ //.t_pub_acbdlr3 = 0x14,//0xa, //cs
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 95,
+ [3] = 95,
+ [4] = 95,
+ [5] = 95,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 98,
+ [3] = 98,
+ [4] = 98,
+ [5] = 98,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+ .ddr_pll_set = {
+ /* ddr pll ssc config:
+ ppm1000: 0x00120000
+ ppm2000: 0x00140000
+ ppm3000: 0x00160000
+ */
+ [0] = 0x00120000,
+ },
+};
diff --git a/board/amlogic/txl_p341_v2/lcd.c b/board/amlogic/txl_p341_v2/lcd.c
new file mode 100755
index 0000000..9c21e17
--- /dev/null
+++ b/board/amlogic/txl_p341_v2/lcd.c
@@ -0,0 +1,375 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_7",
+ "GPIOZ_3",
+ "GPIOH_4",
+ "GPIOH_5",
+ "GPIOH_6",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,20,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_3d_disable[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_CPU, 4,0,10,}, /* 3d_disable */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_3d_disable[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,20,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 4,2,0,}, /* 3d_disable */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_2",
+ "GPIOZ_6",
+ "GPIOZ_7",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {"lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,30,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {"lvds_1",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,30,0,
+ /* clk_attr */
+ 1,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_3d_disable, lcd_power_off_step_3d_disable,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txl_p341_v2/txl_p341_v2.c b/board/amlogic/txl_p341_v2/txl_p341_v2.c
new file mode 100644
index 0000000..35c205c
--- /dev/null
+++ b/board/amlogic/txl_p341_v2/txl_p341_v2.c
@@ -0,0 +1,614 @@
+
+/*
+ * board/amlogic/txl_p341_v2/txl_p341_v2.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm-generic/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*USE_HDMI_UART_FUNC*/
+#define HDMI_UART_PORT_NUM 3
+
+struct hdmi_uart_date_io {
+ char *power;
+ char *scl;
+ volatile uint32_t * hdmi_sda_reg;
+ unsigned int hdmi_sda_bit;
+ volatile uint32_t * uart_tx_reg;
+ unsigned int uart_tx_bit;
+ volatile uint32_t * hdmi_scl_reg;
+ unsigned int hdmi_scl_bit;
+ volatile uint32_t * uart_rx_reg;
+ unsigned int uart_rx_bit;
+};
+
+struct hdmi_uart_date_io txl_hdmi_uart_date_io[HDMI_UART_PORT_NUM+1]=
+{
+ {"GPIOW_5" ,"GPIOW_7" ,P_PERIPHS_PIN_MUX_5,25,P_PERIPHS_PIN_MUX_5,13,P_PERIPHS_PIN_MUX_5 ,24 ,P_PERIPHS_PIN_MUX_5,12,},
+ {"GPIOW_9", "GPIOW_11",P_PERIPHS_PIN_MUX_5,21,P_PERIPHS_PIN_MUX_5,11,P_PERIPHS_PIN_MUX_5 ,20 ,P_PERIPHS_PIN_MUX_5,10,},
+ {"GPIOW_13","GPIOW_15",P_PERIPHS_PIN_MUX_5,17,P_PERIPHS_PIN_MUX_5,9, P_PERIPHS_PIN_MUX_5 ,16 ,P_PERIPHS_PIN_MUX_5,8,},
+ {NULL, NULL, 0, 0,P_AO_RTI_PIN_MUX_REG,12,0 , 0 ,P_AO_RTI_PIN_MUX_REG,11,},
+};
+
+struct hdmi_uart_date_io gxtvbb_hdmi_uart_date_io[HDMI_UART_PORT_NUM+1]=
+{
+ {"GPIOW_6" ,"GPIOW_5" ,P_PERIPHS_PIN_MUX_6 ,9 ,P_PERIPHS_PIN_MUX_10,1,P_PERIPHS_PIN_MUX_6 ,10 ,P_PERIPHS_PIN_MUX_6,11,},
+ {"GPIOW_10","GPIOW_9" ,P_PERIPHS_PIN_MUX_6 ,14 ,P_PERIPHS_PIN_MUX_10,2,P_PERIPHS_PIN_MUX_6 ,15 ,P_PERIPHS_PIN_MUX_6,16,},
+ {"GPIOW_14","GPIOW_13",P_PERIPHS_PIN_MUX_6 ,19 ,P_PERIPHS_PIN_MUX_10,3,P_PERIPHS_PIN_MUX_6 ,20 ,P_PERIPHS_PIN_MUX_6,21,},
+ {NULL, NULL, 0, 0 ,P_AO_RTI_PIN_MUX_REG,0,0 , 0 ,P_AO_RTI_PIN_MUX_REG,1,},
+};
+
+struct hdmi_uart_det_io {
+ char *power;
+ char *scl;
+ volatile uint32_t * uart_det_power_reg;
+ unsigned int uart_det_power_bit;
+ unsigned int uart_det_power_need_level;
+ volatile uint32_t * uart_det_scl_reg;
+ unsigned int uart_det_scl_bit;
+ unsigned int uart_det_scl_need_level;
+};
+
+struct hdmi_uart_det_io txl_hdmi_uart_det_io[HDMI_UART_PORT_NUM]=
+{
+ {"GPIOW_5" , "GPIOW_7" , P_PREG_PAD_GPIO4_I , 5 , 0, P_PREG_PAD_GPIO4_I ,7 , 1,},
+ {"GPIOW_9", "GPIOW_11", P_PREG_PAD_GPIO4_I , 9 , 0, P_PREG_PAD_GPIO4_I ,11, 1,},
+ {"GPIOW_13", "GPIOW_15" , P_PREG_PAD_GPIO4_I , 13, 0, P_PREG_PAD_GPIO4_I ,15, 1,},
+};
+
+/* in gxtvbb,use hpd port as (txl)scl port */
+struct hdmi_uart_det_io gxtvbb_hdmi_uart_det_io[HDMI_UART_PORT_NUM]=
+{
+ {"GPIOW_6" ,"GPIOW_5" , P_PREG_PAD_GPIO0_I, 6 , 0, P_PREG_PAD_GPIO0_I ,5 , 1,},
+ {"GPIOW_10","GPIOW_9" , P_PREG_PAD_GPIO0_I, 10, 0, P_PREG_PAD_GPIO0_I ,9 , 1,},
+ {"GPIOW_14","GPIOW_13", P_PREG_PAD_GPIO0_I, 14, 0, P_PREG_PAD_GPIO0_I ,13, 1,},
+};
+
+static void init_hdmi_uart_board(void)
+{
+ int i=0;
+ int pwr_value=0,scl_value=0;
+ int flag=0;
+ struct hdmi_uart_date_io *hdmi_uart_date_io;
+ struct hdmi_uart_det_io *hdmi_uart_det_io;
+
+ if (get_cpu_id().family_id <= MESON_CPU_MAJOR_ID_GXTVBB) {
+ hdmi_uart_det_io = gxtvbb_hdmi_uart_det_io;
+ hdmi_uart_date_io = gxtvbb_hdmi_uart_date_io;
+ /*printf("choose gxtvbb board.\n");*/
+ } else {
+ hdmi_uart_det_io = txl_hdmi_uart_det_io;
+ hdmi_uart_date_io = txl_hdmi_uart_date_io;
+ /*printf("choose txl board.\n");*/
+ }
+
+ for (i=0; i<HDMI_UART_PORT_NUM; i++) {
+ pwr_value = readl(hdmi_uart_det_io[i].uart_det_power_reg) >> hdmi_uart_det_io[i].uart_det_power_bit;
+ pwr_value &= 1;
+ scl_value = readl(hdmi_uart_det_io[i].uart_det_scl_reg) >> hdmi_uart_det_io[i].uart_det_scl_bit;
+ scl_value &= 1;
+
+ if ((pwr_value == hdmi_uart_det_io[i].uart_det_power_need_level)
+ && (scl_value == hdmi_uart_det_io[i].uart_det_scl_need_level)) {
+ flag = 1;
+ break;
+ }
+ }
+
+ if (flag == 1) {
+ printf("switch to %d hdmirx_uart port\n",i);
+ /* clean default uart pinmux */
+ writel(readl(hdmi_uart_date_io[3].uart_tx_reg)&~(1 << hdmi_uart_date_io[3].uart_tx_bit),
+ (volatile void *)hdmi_uart_date_io[3].uart_tx_reg);
+ writel(readl(hdmi_uart_date_io[3].uart_rx_reg)&~(1 << hdmi_uart_date_io[3].uart_rx_bit),
+ (volatile void *)hdmi_uart_date_io[3].uart_rx_reg);
+
+ /* set hdmi_uart pinmux */
+ writel(readl(hdmi_uart_date_io[i].hdmi_sda_reg)&~(1 << hdmi_uart_date_io[i].hdmi_sda_bit),
+ (volatile void *)hdmi_uart_date_io[i].hdmi_sda_reg);
+ writel(readl(hdmi_uart_date_io[i].uart_tx_reg)|(1 << hdmi_uart_date_io[i].uart_tx_bit),
+ (volatile void *)hdmi_uart_date_io[i].uart_tx_reg);
+
+ writel(readl(hdmi_uart_date_io[i].hdmi_scl_reg)&~(1 << hdmi_uart_date_io[i].hdmi_scl_bit),
+ (volatile void *)hdmi_uart_date_io[i].hdmi_scl_reg);
+ writel(readl(hdmi_uart_date_io[i].uart_rx_reg)|(1 << hdmi_uart_date_io[i].uart_rx_bit),
+ (volatile void *)hdmi_uart_date_io[i].uart_rx_reg);
+ }
+}
+/*endif*/
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+writel(readl(AO_GPIO_O_EN_N) & (~(0x1 << 10)), AO_GPIO_O_EN_N); //set mode: output
+writel(readl(AO_GPIO_O_EN_N) | (0x1 << 26),AO_GPIO_O_EN_N); //output 1
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+ char* env;
+ unsigned int hwid = 1;
+
+ /*USE_HDMI_UART_FUNC*/
+ env = getenv("hdmiuart_mode");
+ /*printf("hdmiuart_mode env:%s\n",env);*/
+ if (env) {
+ if (!strcmp(env,"open")) {
+ printf("CONFIG_HDMI_UART_BOARD\n");
+ init_hdmi_uart_board();
+ }
+ }
+ /*endif*/
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+
+ /* enable 5V for USB, panel, wifi */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+ switch (hwid) {
+ case 1:
+ run_command("gpio set GPIOAO_4", 0);
+ break;
+ case 2:
+ /* set output mode for GPIOAO_10 */
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<10));
+ /* set output level to high for GPIOAO_10 */
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<26));
+ break;
+ default:
+ /* set output mode for GPIOAO_10 */
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<10));
+ /* set output level to high for GPIOAO_10 */
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<26));
+ printf("invalid hwid = %d\n", hwid);
+ break;
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ */
+ unsigned int hwid = 1;
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/txl_p346_v1/Kconfig b/board/amlogic/txl_p346_v1/Kconfig
new file mode 100644
index 0000000..4fd501b
--- /dev/null
+++ b/board/amlogic/txl_p346_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_TXL
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "txl_p346_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "txl"
+
+config SYS_CONFIG_NAME
+ default "txl_p346_v1"
+
+endif
diff --git a/board/amlogic/txl_p346_v1/Makefile b/board/amlogic/txl_p346_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/txl_p346_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/txl_p346_v1/aml-user-key.sig b/board/amlogic/txl_p346_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/txl_p346_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/txl_p346_v1/eth_setup.c b/board/amlogic/txl_p346_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/txl_p346_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/txl_p346_v1/firmware/board_init.c b/board/amlogic/txl_p346_v1/firmware/board_init.c
new file mode 100644
index 0000000..14616a7
--- /dev/null
+++ b/board/amlogic/txl_p346_v1/firmware/board_init.c
@@ -0,0 +1,81 @@
+
+/*
+ * board/amlogic/gxtvbb_p301_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+
+#define PNL_PREG_PAD_GPIO1_EN_N 0x0f
+#define PNL_PREG_PAD_GPIO1_O 0x10
+#define PNL_PREG_PAD_GPIO1_I 0x11
+
+#define PNL_PREG_PAD_GPIO3_EN_N 0x15
+#define PNL_PREG_PAD_GPIO3_O 0x16
+#define PNL_PREG_PAD_GPIO3_I 0x17
+
+#define PNL_REG_BASE (0xc8834400L)
+#define PNL_REG(reg) (PNL_REG_BASE + (reg << 2))
+#define PNL_REG_R(_reg) (*(volatile unsigned int *)PNL_REG(_reg))
+#define PNL_REG_W(_reg, _value) *(volatile unsigned int *)PNL_REG(_reg) = (_value);
+void panel_power_init(void)
+{
+ serial_puts("init panel power\n");
+
+ /* panel: GPIOH_4/5/6/7/8 */ /* remove GPIOH_6 for 2D/3D special case */
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_O) & ~(0x1b << 24)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_EN_N) & ~(0x1b << 24)));
+
+ /* backlight: GPIOZ_2/6/7 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_O) & ~((1 << 2) | (0x3 << 6))));
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_EN_N) & ~((1 << 2) | (0x3 << 6))));
+}
+
+#define SEC_AO_SEC_GP_CFG0 (0xda100000 + (0x90 << 2))
+static int check_is_ddr_inited(void)
+{
+ return ((readl(SEC_AO_SEC_GP_CFG0) >> 16) & 0xffff);
+}
+
+void board_init(void)
+{
+ power_init(0);
+
+ //only run once before ddr inited.
+ if (!check_is_ddr_inited()) {
+ /* dram 1.5V reset */
+ serial_puts("DRAM reset...\n");
+ /* power off ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) & (~((1 << 11) | (1 << 27)))),P_AO_GPIO_O_EN_N);
+ /* need delay, check hw design */
+ _udelay(400000);
+ /* power on ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) | (1 << 27)),P_AO_GPIO_O_EN_N);
+
+ /* dram RC charge time, check hw design */
+ _udelay(10000);
+ }
+
+ panel_power_init();
+}
diff --git a/board/amlogic/txl_p346_v1/firmware/power.c b/board/amlogic/txl_p346_v1/firmware/power.c
new file mode 100644
index 0000000..fe97bf7
--- /dev/null
+++ b/board/amlogic/txl_p346_v1/firmware/power.c
@@ -0,0 +1,182 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/power.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 870},
+ { 0x1b0001, 880},
+ { 0x1a0002, 890},
+ { 0x190003, 900},
+ { 0x180004, 910},
+ { 0x170005, 920},
+ { 0x160006, 930},
+ { 0x150007, 940},
+ { 0x140008, 950},
+ { 0x130009, 960},
+ { 0x12000a, 970},
+ { 0x11000b, 980},
+ { 0x10000c, 990},
+ { 0x0f000d, 1000},
+ { 0x0e000e, 1010},
+ { 0x0d000f, 1020},
+ { 0x0c0010, 1030},
+ { 0x0b0011, 1040},
+ { 0x0a0012, 1050},
+ { 0x090013, 1060},
+ { 0x080014, 1070},
+ { 0x070015, 1080},
+ { 0x060016, 1090},
+ { 0x050017, 1100},
+ { 0x040018, 1110},
+ { 0x030019, 1120},
+ { 0x02001a, 1130},
+ { 0x01001b, 1140},
+ { 0x00001c, 1150}
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_ao_b,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+ int vol;
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26);
+ reg |= (1 << 17);
+ P_PIN_MUX_REG4 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ //vol = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ //writel(vol ,AO_PWM_PWM_B);
+ reg = readl(AO_RTI_PIN_MUX_REG);
+ reg |= (1 << 3);
+ writel(reg, AO_RTI_PIN_MUX_REG);
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vddee enable AO_8 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~(1 << 8);
+ reg |= (1 << 24);
+ writel(reg, AO_GPIO_O_EN_N);
+ serial_puts("set vddee enable AO_2 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~(1 << 2);
+ reg |= (1 << 18);
+ writel(reg, AO_GPIO_O_EN_N);
+}
diff --git a/board/amlogic/txl_p346_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/txl_p346_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..4c757b7
--- /dev/null
+++ b/board/amlogic/txl_p346_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,161 @@
+
+/*
+ * board/amlogic/txl_p346_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 970+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 1010+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1080+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+//vddee vcck together
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_REG3 = reg;
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/txl_p346_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/txl_p346_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..cb148c0
--- /dev/null
+++ b/board/amlogic/txl_p346_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,37 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 870},
+ { 0x1b0001, 880},
+ { 0x1a0002, 890},
+ { 0x190003, 900},
+ { 0x180004, 910},
+ { 0x170005, 920},
+ { 0x160006, 930},
+ { 0x150007, 940},
+ { 0x140008, 950},
+ { 0x130009, 960},
+ { 0x12000a, 970},
+ { 0x11000b, 980},
+ { 0x10000c, 990},
+ { 0x0f000d, 1000},
+ { 0x0e000e, 1010},
+ { 0x0d000f, 1020},
+ { 0x0c0010, 1030},
+ { 0x0b0011, 1040},
+ { 0x0a0012, 1050},
+ { 0x090013, 1060},
+ { 0x080014, 1070},
+ { 0x070015, 1080},
+ { 0x060016, 1090},
+ { 0x050017, 1100},
+ { 0x040018, 1110},
+ { 0x030019, 1120},
+ { 0x02001a, 1130},
+ { 0x01001b, 1140},
+ { 0x00001c, 1150}
+};
diff --git a/board/amlogic/txl_p346_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/txl_p346_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..a55c8e6
--- /dev/null
+++ b/board/amlogic/txl_p346_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,353 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "pwm_ctrl.h"
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define ON 1
+#define OFF 0
+
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_off_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+}
+
+static void power_off_at_clk81(void)
+{
+
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
+ _udelay(10000);
+}
+static void power_off_ee(void)
+{
+ return;
+ power_switch_to_ee(OFF);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 0);
+}
+
+static void power_on_ee(void)
+{
+ return;
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 1 << 24);
+ _udelay(10000);
+ _udelay(10000);
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+ power_off_usb5v();
+ _udelay(5000);
+ power_off_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_ee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ _udelay(10000);
+ power_on_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ _udelay(10000);
+ _udelay(10000);
+ power_on_usb5v();
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_on_ddr();
+ power_on_ee();
+
+ }
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+ p->gpio_info_count = 0;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ saradc_enable();
+ reset_ao_timera();
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+// if (suspend_from == SYS_POWEROFF)
+// continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/txl_p346_v1/firmware/timing.c b/board/amlogic/txl_p346_v1/firmware/timing.c
new file mode 100644
index 0000000..c821248
--- /dev/null
+++ b/board/amlogic/txl_p346_v1/firmware/timing.c
@@ -0,0 +1,587 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 20
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_120OHM 2
+#define LPDDR3_ODT_2400HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_48OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#define CONFIG_SOC_VREF 1+ (50+((50*48)/(48+480/(6+1)))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF 1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+//#define CONFIG_ZQ_VREF 715/15// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b | (1<<22),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR zqvref 0x13
+ //.t_pub_zq0pr = 0x5aa59, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ //.t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR//0x3f95d, 0x4f95d,
+ //.t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR//0x3f95d, 0x4f95d,
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+ //.t_pub_zq3pr = 0xf5f95d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0x3f,
+ .t_pub_aclcdlr = 0x28,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0x10,//0xa, //cs
+ //.t_pub_acbdlr0 = 0x0,
+ //.t_pub_aclcdlr = 0x10,//0x18, ///1t ,if 2t can add some value
+ //.t_pub_acbdlr3 = 0x14,//0xa, //cs
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 95,
+ [3] = 95,
+ [4] = 95,
+ [5] = 95,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 98,
+ [3] = 98,
+ [4] = 98,
+ [5] = 98,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+ .ddr_pll_set = {
+ /* ddr pll ssc config:
+ ppm1000: 0x00120000
+ ppm2000: 0x00140000
+ ppm3000: 0x00160000
+ */
+ [0] = 0x00120000,
+ },
+};
diff --git a/board/amlogic/txl_p346_v1/lcd.c b/board/amlogic/txl_p346_v1/lcd.c
new file mode 100755
index 0000000..9c21e17
--- /dev/null
+++ b/board/amlogic/txl_p346_v1/lcd.c
@@ -0,0 +1,375 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_7",
+ "GPIOZ_3",
+ "GPIOH_4",
+ "GPIOH_5",
+ "GPIOH_6",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,20,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_3d_disable[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_CPU, 4,0,10,}, /* 3d_disable */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_3d_disable[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,20,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 4,2,0,}, /* 3d_disable */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_2",
+ "GPIOZ_6",
+ "GPIOZ_7",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {"lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,30,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {"lvds_1",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,30,0,
+ /* clk_attr */
+ 1,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_3d_disable, lcd_power_off_step_3d_disable,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txl_p346_v1/txl_p346_v1.c b/board/amlogic/txl_p346_v1/txl_p346_v1.c
new file mode 100644
index 0000000..34aa775
--- /dev/null
+++ b/board/amlogic/txl_p346_v1/txl_p346_v1.c
@@ -0,0 +1,604 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_p346_v1.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm-generic/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*USE_HDMI_UART_FUNC*/
+#define HDMI_UART_PORT_NUM 3
+
+struct hdmi_uart_date_io {
+ char *power;
+ char *scl;
+ volatile uint32_t * hdmi_sda_reg;
+ unsigned int hdmi_sda_bit;
+ volatile uint32_t * uart_tx_reg;
+ unsigned int uart_tx_bit;
+ volatile uint32_t * hdmi_scl_reg;
+ unsigned int hdmi_scl_bit;
+ volatile uint32_t * uart_rx_reg;
+ unsigned int uart_rx_bit;
+};
+
+struct hdmi_uart_date_io txl_hdmi_uart_date_io[HDMI_UART_PORT_NUM+1]=
+{
+ {"GPIOW_5" ,"GPIOW_7" ,P_PERIPHS_PIN_MUX_5,25,P_PERIPHS_PIN_MUX_5,13,P_PERIPHS_PIN_MUX_5 ,24 ,P_PERIPHS_PIN_MUX_5,12,},
+ {"GPIOW_9", "GPIOW_11",P_PERIPHS_PIN_MUX_5,21,P_PERIPHS_PIN_MUX_5,11,P_PERIPHS_PIN_MUX_5 ,20 ,P_PERIPHS_PIN_MUX_5,10,},
+ {"GPIOW_13","GPIOW_15",P_PERIPHS_PIN_MUX_5,17,P_PERIPHS_PIN_MUX_5,9, P_PERIPHS_PIN_MUX_5 ,16 ,P_PERIPHS_PIN_MUX_5,8,},
+ {NULL, NULL, 0, 0,P_AO_RTI_PIN_MUX_REG,12,0 , 0 ,P_AO_RTI_PIN_MUX_REG,11,},
+};
+
+struct hdmi_uart_date_io gxtvbb_hdmi_uart_date_io[HDMI_UART_PORT_NUM+1]=
+{
+ {"GPIOW_6" ,"GPIOW_5" ,P_PERIPHS_PIN_MUX_6 ,9 ,P_PERIPHS_PIN_MUX_10,1,P_PERIPHS_PIN_MUX_6 ,10 ,P_PERIPHS_PIN_MUX_6,11,},
+ {"GPIOW_10","GPIOW_9" ,P_PERIPHS_PIN_MUX_6 ,14 ,P_PERIPHS_PIN_MUX_10,2,P_PERIPHS_PIN_MUX_6 ,15 ,P_PERIPHS_PIN_MUX_6,16,},
+ {"GPIOW_14","GPIOW_13",P_PERIPHS_PIN_MUX_6 ,19 ,P_PERIPHS_PIN_MUX_10,3,P_PERIPHS_PIN_MUX_6 ,20 ,P_PERIPHS_PIN_MUX_6,21,},
+ {NULL, NULL, 0, 0 ,P_AO_RTI_PIN_MUX_REG,0,0 , 0 ,P_AO_RTI_PIN_MUX_REG,1,},
+};
+
+struct hdmi_uart_det_io {
+ char *power;
+ char *scl;
+ volatile uint32_t * uart_det_power_reg;
+ unsigned int uart_det_power_bit;
+ unsigned int uart_det_power_need_level;
+ volatile uint32_t * uart_det_scl_reg;
+ unsigned int uart_det_scl_bit;
+ unsigned int uart_det_scl_need_level;
+};
+
+struct hdmi_uart_det_io txl_hdmi_uart_det_io[HDMI_UART_PORT_NUM]=
+{
+ {"GPIOW_5" , "GPIOW_7" , P_PREG_PAD_GPIO4_I , 5 , 0, P_PREG_PAD_GPIO4_I ,7 , 1,},
+ {"GPIOW_9", "GPIOW_11", P_PREG_PAD_GPIO4_I , 9 , 0, P_PREG_PAD_GPIO4_I ,11, 1,},
+ {"GPIOW_13", "GPIOW_15" , P_PREG_PAD_GPIO4_I , 13, 0, P_PREG_PAD_GPIO4_I ,15, 1,},
+};
+
+/* in gxtvbb,use hpd port as (txl)scl port */
+struct hdmi_uart_det_io gxtvbb_hdmi_uart_det_io[HDMI_UART_PORT_NUM]=
+{
+ {"GPIOW_6" ,"GPIOW_5" , P_PREG_PAD_GPIO0_I, 6 , 0, P_PREG_PAD_GPIO0_I ,5 , 1,},
+ {"GPIOW_10","GPIOW_9" , P_PREG_PAD_GPIO0_I, 10, 0, P_PREG_PAD_GPIO0_I ,9 , 1,},
+ {"GPIOW_14","GPIOW_13", P_PREG_PAD_GPIO0_I, 14, 0, P_PREG_PAD_GPIO0_I ,13, 1,},
+};
+
+static void init_hdmi_uart_board(void)
+{
+ int i=0;
+ int pwr_value=0,scl_value=0;
+ int flag=0;
+ struct hdmi_uart_date_io *hdmi_uart_date_io;
+ struct hdmi_uart_det_io *hdmi_uart_det_io;
+
+ if (get_cpu_id().family_id <= MESON_CPU_MAJOR_ID_GXTVBB) {
+ hdmi_uart_det_io = gxtvbb_hdmi_uart_det_io;
+ hdmi_uart_date_io = gxtvbb_hdmi_uart_date_io;
+ /*printf("choose gxtvbb board.\n");*/
+ } else {
+ hdmi_uart_det_io = txl_hdmi_uart_det_io;
+ hdmi_uart_date_io = txl_hdmi_uart_date_io;
+ /*printf("choose txl board.\n");*/
+ }
+
+ for (i=0; i<HDMI_UART_PORT_NUM; i++) {
+ pwr_value = readl(hdmi_uart_det_io[i].uart_det_power_reg) >> hdmi_uart_det_io[i].uart_det_power_bit;
+ pwr_value &= 1;
+ scl_value = readl(hdmi_uart_det_io[i].uart_det_scl_reg) >> hdmi_uart_det_io[i].uart_det_scl_bit;
+ scl_value &= 1;
+
+ if ((pwr_value == hdmi_uart_det_io[i].uart_det_power_need_level)
+ && (scl_value == hdmi_uart_det_io[i].uart_det_scl_need_level)) {
+ flag = 1;
+ break;
+ }
+ }
+
+ if (flag == 1) {
+ printf("switch to %d hdmirx_uart port\n",i);
+ /* clean default uart pinmux */
+ writel(readl(hdmi_uart_date_io[3].uart_tx_reg)&~(1 << hdmi_uart_date_io[3].uart_tx_bit),
+ (volatile void *)hdmi_uart_date_io[3].uart_tx_reg);
+ writel(readl(hdmi_uart_date_io[3].uart_rx_reg)&~(1 << hdmi_uart_date_io[3].uart_rx_bit),
+ (volatile void *)hdmi_uart_date_io[3].uart_rx_reg);
+
+ /* set hdmi_uart pinmux */
+ writel(readl(hdmi_uart_date_io[i].hdmi_sda_reg)&~(1 << hdmi_uart_date_io[i].hdmi_sda_bit),
+ (volatile void *)hdmi_uart_date_io[i].hdmi_sda_reg);
+ writel(readl(hdmi_uart_date_io[i].uart_tx_reg)|(1 << hdmi_uart_date_io[i].uart_tx_bit),
+ (volatile void *)hdmi_uart_date_io[i].uart_tx_reg);
+
+ writel(readl(hdmi_uart_date_io[i].hdmi_scl_reg)&~(1 << hdmi_uart_date_io[i].hdmi_scl_bit),
+ (volatile void *)hdmi_uart_date_io[i].hdmi_scl_reg);
+ writel(readl(hdmi_uart_date_io[i].uart_rx_reg)|(1 << hdmi_uart_date_io[i].uart_rx_bit),
+ (volatile void *)hdmi_uart_date_io[i].uart_rx_reg);
+ }
+}
+/*endif*/
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+ char* env;
+
+ /*USE_HDMI_UART_FUNC*/
+ env = getenv("hdmiuart_mode");
+ /*printf("hdmiuart_mode env:%s\n",env);*/
+ if (env) {
+ if (!strcmp(env,"open")) {
+ printf("CONFIG_HDMI_UART_BOARD\n");
+ init_hdmi_uart_board();
+ }
+ }
+ /*endif*/
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ //CLEAR PINMUX
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG,(1<<23)|(1<<5)|(1<<1));//AO_5
+ clrbits_le32(P_PERIPHS_PIN_MUX_2, (1<<13)|(1<<5)|(1<<28));//DV_9
+ //SET GPIOAO_5 OUTPUT 1
+ clrbits_le32(P_AO_GPIO_O_EN_N, 1 << 5);
+ setbits_le32(P_AO_GPIO_O_EN_N, 1 << 21);
+ //SET GPIODV_9 OUTPUT 1
+ clrbits_le32(P_PREG_PAD_GPIO0_EN_N, 1 << 9);
+ setbits_le32(P_PREG_PAD_GPIO0_O, 1 << 9);
+
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<10));
+ /* set output level to high for GPIOAO_10 */
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<26));
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ */
+ unsigned int hwid = 1;
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/txl_skt_v1/Kconfig b/board/amlogic/txl_skt_v1/Kconfig
new file mode 100644
index 0000000..4ed5132
--- /dev/null
+++ b/board/amlogic/txl_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GXTV
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "txl_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "txl"
+
+config SYS_CONFIG_NAME
+ default "txl_skt_v1"
+
+endif
diff --git a/board/amlogic/txl_skt_v1/Makefile b/board/amlogic/txl_skt_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/txl_skt_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/txl_skt_v1/aml-user-key.sig b/board/amlogic/txl_skt_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/txl_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/txl_skt_v1/eth_setup.c b/board/amlogic/txl_skt_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/txl_skt_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/txl_skt_v1/firmware/board_init.c b/board/amlogic/txl_skt_v1/firmware/board_init.c
new file mode 100644
index 0000000..2771433
--- /dev/null
+++ b/board/amlogic/txl_skt_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/txl_skt_v1/firmware/power.c b/board/amlogic/txl_skt_v1/firmware/power.c
new file mode 100644
index 0000000..12843e2
--- /dev/null
+++ b/board/amlogic/txl_skt_v1/firmware/power.c
@@ -0,0 +1,173 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+#define AO_PIN_MUX_REG (*((volatile unsigned *)(0xc8100000 + (0x5 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_ao_b,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ */
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26);
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ writel( pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0],AO_PWM_PWM_B);
+ reg = AO_PIN_MUX_REG;
+ reg |= (1 << 3);
+ AO_PIN_MUX_REG = reg;
+
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ writel(pwm_voltage_table[to][0],AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/txl_skt_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/txl_skt_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..02f277a
--- /dev/null
+++ b/board/amlogic/txl_skt_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,190 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+int pwm_voltage_table[ ][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860),
+ DVFS( 250000000, 860),
+ DVFS( 500000000, 880),
+ DVFS( 667000000, 920),
+ DVFS(1000000000, 960),
+ DVFS(1200000000, 1040),
+ DVFS(1296000000, 1080),
+ DVFS(1416000000, 1110),
+ DVFS(1536000000, 1110),
+ DVFS(1752000000, 1110),
+ DVFS(2016000000, 1110)
+};
+
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..adf2bb2
--- /dev/null
+++ b/board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,324 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define ON 1
+#define OFF 0
+
+static unsigned int pwm_voltage_table[][2] = {
+ {0x190003, 900},
+ {0x0f000d, 1000},
+};
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_off_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+}
+
+static void power_off_at_clk81(void)
+{
+ power_off_3v3_5v();
+ power_off_usb5v();
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ power_on_usb5v();
+ power_on_3v3_5v();
+ _udelay(10000);
+ _udelay(10000);
+ _udelay(10000);
+ _udelay(10000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+#if 0
+ if (suspend_from == SYS_POWEROFF) {
+ power_switch_to_ee(ON);
+ }
+#endif
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
+ _udelay(10000);
+}
+static void power_off_ee(void)
+{
+ return;
+ power_switch_to_ee(OFF);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 0);
+}
+
+static void power_on_ee(void)
+{
+ return;
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 1 << 24);
+ _udelay(10000);
+ _udelay(10000);
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_ee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_on_ddr();
+ power_on_ee();
+
+ }
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+
+ p->status = RESPONSE_OK;
+ val = REMOTE_WAKEUP_SRC | ETH_PHY_WAKEUP_SRC;
+#ifdef CONFIG_CEC_WAKEUP
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+ p->gpio_info_count = 0;
+}
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ saradc_enable();
+ reset_ao_timera();
+ /* setup wakeup resources*/
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+// if (suspend_from == SYS_POWEROFF)
+// continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/txl_skt_v1/firmware/timing.c b/board/amlogic/txl_skt_v1/firmware/timing.c
new file mode 100644
index 0000000..e48bb6a
--- /dev/null
+++ b/board/amlogic/txl_skt_v1/firmware/timing.c
@@ -0,0 +1,569 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_60OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x5995d, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0x10,
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/txl_skt_v1/lcd.c b/board/amlogic/txl_skt_v1/lcd.c
new file mode 100755
index 0000000..1eb6bfa
--- /dev/null
+++ b/board/amlogic/txl_skt_v1/lcd.c
@@ -0,0 +1,355 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ //"GPIOX_3",
+ //"GPIOX_2",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ //{LCD_POWER_TYPE_CPU, 0,1,50,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ //{LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_3d_disable[] = {
+ //{LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ //{LCD_POWER_TYPE_CPU, 1,0,10,}, /* 3d_disable */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_3d_disable[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,30,}, /* signal */
+ //{LCD_POWER_TYPE_CPU, 1,2,0,}, /* 3d_disable */
+ //{LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ //"GPIOAO_4",
+ //"GPIOY_13",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* AOC: public Platform lvds : 1920x1080@60hz 8bit pixel clk@74.25mhz 2prot*/
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0xff,1,0,0,0,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_3d_disable, lcd_power_off_step_3d_disable,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ // {
+ // .type = LCD_POWER_TYPE_CPU,
+ // .index = 0, /* point to cpu_gpio[] struct */
+ // .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ // .delay = 50, /* unit: ms */
+ // },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ // {
+ // .type = LCD_POWER_TYPE_CPU,
+ // .index = 0, /* point to cpu_gpio[] struct */
+ // .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ // .delay = 100, /* unit: ms */
+ // },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txl_skt_v1/txl_skt_v1.c b/board/amlogic/txl_skt_v1/txl_skt_v1.c
new file mode 100644
index 0000000..018a5b6
--- /dev/null
+++ b/board/amlogic/txl_skt_v1/txl_skt_v1.c
@@ -0,0 +1,512 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#ifdef CONFIG_AML_SPIFC
+#include <amlogic/spifc.h>
+#endif
+#ifdef CONFIG_AML_SPICC
+#include <amlogic/spicc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_4: NOR_D:reg7[13], clr reg7[31] reg7[22]
+ * BOOT_5: NOR_Q:reg7[12], clr reg7[31] reg7[21]
+ * BOOT_6: NOR_C:reg7[11], clr reg7[31] reg7[20]
+ * BOOT_11: NOR_CS:reg7[10],clr reg7[28]
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {78/*BOOT_11*/};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_7);
+ val &= ~((1<<13)|(1<<12)|(1<<11)|(1<<10));
+ if (enable) {
+ val |= (1<<13)|(1<<12)|(1<<11);
+ val &= ~((1<<31)|(1<<28)|(1<<22)|(1<<21)|(1<<20));
+ }
+ writel(val, P_PERIPHS_PIN_MUX_7);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xc1108c80,
+ .mem_map = 0xcc000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+#ifdef CONFIG_AML_SPICC
+/* generic config in arch gpio/clock.c */
+extern int spicc_clk_enable(bool enable);
+extern int spicc_pinctrl_enable(bool enable);
+
+static const struct spicc_platdata spicc_platdata = {
+ .compatible = "amlogic,meson-txl-spicc",
+ .reg = (void __iomem *)0xc1108d80,
+ .clk_rate = 166666666,
+ .clk_enable = spicc_clk_enable,
+ .pinctrl_enable = spicc_pinctrl_enable,
+ /* case one slave without cs: {"no_cs", 0} */
+ .cs_gpio_names = {"GPIOZ_3", 0},
+};
+
+U_BOOT_DEVICE(spicc) = {
+ .name = "spicc",
+ .platdata = &spicc_platdata,
+};
+#endif /* CONFIG_AML_SPICC */
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
diff --git a/board/amlogic/txl_t950_skt_v1/Kconfig b/board/amlogic/txl_t950_skt_v1/Kconfig
new file mode 100644
index 0000000..4880d0d
--- /dev/null
+++ b/board/amlogic/txl_t950_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_TXL
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "txl_t950_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "txl"
+
+config SYS_CONFIG_NAME
+ default "txl_t950_skt_v1"
+
+endif
diff --git a/board/amlogic/txl_t950_skt_v1/Makefile b/board/amlogic/txl_t950_skt_v1/Makefile
new file mode 100644
index 0000000..fb7f59a
--- /dev/null
+++ b/board/amlogic/txl_t950_skt_v1/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/txl_t950_skt_v1/aml-user-key.sig b/board/amlogic/txl_t950_skt_v1/aml-user-key.sig
new file mode 100644
index 0000000..b6c5722
--- /dev/null
+++ b/board/amlogic/txl_t950_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/txl_t950_skt_v1/eth_setup.c b/board/amlogic/txl_t950_skt_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/txl_t950_skt_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/txl_t950_skt_v1/firmware/board_init.c b/board/amlogic/txl_t950_skt_v1/firmware/board_init.c
new file mode 100644
index 0000000..f2d1ecc
--- /dev/null
+++ b/board/amlogic/txl_t950_skt_v1/firmware/board_init.c
@@ -0,0 +1,81 @@
+
+/*
+ * board/amlogic/gxtvbb_p301_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+
+#define PNL_PREG_PAD_GPIO1_EN_N 0x0f
+#define PNL_PREG_PAD_GPIO1_O 0x10
+#define PNL_PREG_PAD_GPIO1_I 0x11
+
+#define PNL_PREG_PAD_GPIO3_EN_N 0x15
+#define PNL_PREG_PAD_GPIO3_O 0x16
+#define PNL_PREG_PAD_GPIO3_I 0x17
+
+#define PNL_REG_BASE (0xc8834400L)
+#define PNL_REG(reg) (PNL_REG_BASE + (reg << 2))
+#define PNL_REG_R(_reg) (*(volatile unsigned int *)PNL_REG(_reg))
+#define PNL_REG_W(_reg, _value) *(volatile unsigned int *)PNL_REG(_reg) = (_value);
+void panel_power_init(void)
+{
+ serial_puts("init panel power\n");
+
+ /* panel: GPIOH_4/5/6/7/8 */ /* remove GPIOH_6 for 2D/3D special case */
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_O) & ~(0x1b << 24)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_EN_N) & ~(0x1b << 24)));
+
+ /* backlight: GPIOZ_2/6/7 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_O) & ~((1 << 2) | (0x3 << 6))));
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_EN_N) & ~((1 << 2) | (0x3 << 6))));
+}
+
+#define SEC_AO_SEC_GP_CFG0 (0xda100000 + (0x90 << 2))
+static int check_is_ddr_inited(void)
+{
+ return ((readl(SEC_AO_SEC_GP_CFG0) >> 16) & 0xffff);
+}
+
+void board_init(void)
+{
+ power_init(0);
+
+ //only run once before ddr inited.
+ if (!check_is_ddr_inited()) {
+ /* dram 1.5V reset */
+ serial_puts("DRAM reset...\n");
+ /* power off ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) & (~((1 << 11) | (1 << 27)))),P_AO_GPIO_O_EN_N);
+ /* need delay, check hw design */
+ _udelay(100000);
+ /* power on ddr */
+ writel((readl(P_AO_GPIO_O_EN_N) | (1 << 27)),P_AO_GPIO_O_EN_N);
+
+ /* dram RC charge time, check hw design */
+ _udelay(10000);
+ }
+
+ panel_power_init();
+}
diff --git a/board/amlogic/txl_t950_skt_v1/firmware/power.c b/board/amlogic/txl_t950_skt_v1/firmware/power.c
new file mode 100644
index 0000000..5cd6ab5
--- /dev/null
+++ b/board/amlogic/txl_t950_skt_v1/firmware/power.c
@@ -0,0 +1,173 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/power.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+
+
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_ao_b,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+ int vol;
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26);
+ reg |= (1 << 17);
+ P_PIN_MUX_REG4 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ vol = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ writel(vol ,AO_PWM_PWM_B);
+ reg = readl(AO_RTI_PIN_MUX_REG);
+ reg |= (1 << 3);
+ writel(reg, AO_RTI_PIN_MUX_REG);
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/amlogic/txl_t950_skt_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/txl_t950_skt_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..8fc5dea
--- /dev/null
+++ b/board/amlogic/txl_t950_skt_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,166 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 900 + CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 900 + CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 900 + CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900 + CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910 + CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 940 + CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 980 + CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1050 + CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1488000000, 1070 + CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1536000000, 1080 + CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xda834400 + (0x30 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+
+/*
+ * gpioao_9 pwm_ao_b is used to adjust VDD_EE
+ */
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 21);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/txl_t950_skt_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/txl_t950_skt_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..7b67562
--- /dev/null
+++ b/board/amlogic/txl_t950_skt_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,37 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
diff --git a/board/amlogic/txl_t950_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/txl_t950_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..a2d043b
--- /dev/null
+++ b/board/amlogic/txl_t950_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,373 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "pwm_ctrl.h"
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xc8100400 + (0x55 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+#define ON 1
+#define OFF 0
+
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+static unsigned int ao_timer_ctrl;
+static unsigned int ao_timera;
+
+static void reset_ao_timera(void)
+{
+ unsigned int val;
+ ao_timer_ctrl = readl(AO_TIMER_REG);
+ ao_timera = readl(AO_TIMERA_REG);
+ /* set ao timera work mode and interrrupt time 100us resolution*/
+ val = (1 << 2) | (3 << 0) | (1 << 3);
+ writel(val, AO_TIMER_REG);
+ /* periodic time 10ms */
+ writel(100,AO_TIMERA_REG);
+}
+
+static void restore_ao_timer(void)
+{
+ writel(ao_timer_ctrl,AO_TIMER_REG);
+ writel(ao_timera,AO_TIMERA_REG);
+}
+
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xc1100000 + (0x2154 << 2))))
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_off_usb5v(void)
+{
+ #if 0
+ //v1
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 0);
+ //v2
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+ #endif
+
+ /* enable 5V for USB, panel, wifi */
+
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ //unsigned int hwid = 1;
+ #if 0
+ //v1
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 20, 1 << 20);
+ //v2
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+ #endif
+
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+
+}
+
+static void power_off_at_clk81(void)
+{
+ power_off_3v3_5v();
+ power_off_usb5v();
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ power_on_usb5v();
+ power_on_3v3_5v();
+ _udelay(10000);
+ _udelay(10000);
+ _udelay(10000);
+ _udelay(10000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+#if 0
+ if (suspend_from == SYS_POWEROFF) {
+ power_switch_to_ee(ON);
+ }
+#endif
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
+ _udelay(10000);
+}
+static void power_off_ee(void)
+{
+ return;
+ power_switch_to_ee(OFF);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 0);
+}
+
+static void power_on_ee(void)
+{
+ return;
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 1 << 24);
+ _udelay(10000);
+ _udelay(10000);
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_ee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+
+ if (suspend_from == SYS_POWEROFF) {
+ power_on_ddr();
+ power_on_ee();
+
+ }
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+ p->sources = val;
+ p->gpio_info_count = 0;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ saradc_enable();
+ reset_ao_timera();
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CEC] == IRQ_AO_CEC_NUM) {
+ irq[IRQ_AO_CEC] = 0xFFFFFFFF;
+// if (suspend_from == SYS_POWEROFF)
+// continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+ restore_ao_timer();
+ saradc_disable();
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/txl_t950_skt_v1/firmware/timing.c b/board/amlogic/txl_t950_skt_v1/firmware/timing.c
new file mode 100644
index 0000000..be820d5
--- /dev/null
+++ b/board/amlogic/txl_t950_skt_v1/firmware/timing.c
@@ -0,0 +1,579 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 20
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_120OHM 2
+#define LPDDR3_ODT_2400HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_48OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#define CONFIG_SOC_VREF 1+ (50+((50*48)/(48+480/(6+1)))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF 1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+//#define CONFIG_ZQ_VREF 715/15// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b | (1<<22),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR zqvref 0x13
+ //.t_pub_zq0pr = 0x5aa59, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ //.t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR//0x3f95d, 0x4f95d,
+ //.t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR//0x3f95d, 0x4f95d,
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+ //.t_pub_zq3pr = 0xf5f95d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0x3f,
+ .t_pub_aclcdlr = 0x28,//0x18, ///1t ,if 2t can add some value
+ .t_pub_acbdlr3 = 0x10,//0xa, //cs
+ //.t_pub_acbdlr0 = 0x0,
+ //.t_pub_aclcdlr = 0x10,//0x18, ///1t ,if 2t can add some value
+ //.t_pub_acbdlr3 = 0x14,//0xa, //cs
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 95,
+ [3] = 95,
+ [4] = 95,
+ [5] = 95,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 98,
+ [3] = 98,
+ [4] = 98,
+ [5] = 98,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/txl_t950_skt_v1/lcd.c b/board/amlogic/txl_t950_skt_v1/lcd.c
new file mode 100755
index 0000000..9c21e17
--- /dev/null
+++ b/board/amlogic/txl_t950_skt_v1/lcd.c
@@ -0,0 +1,375 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_7",
+ "GPIOZ_3",
+ "GPIOH_4",
+ "GPIOH_5",
+ "GPIOH_6",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,20,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_3d_disable[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_CPU, 4,0,10,}, /* 3d_disable */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_3d_disable[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,20,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 4,2,0,}, /* 3d_disable */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_2",
+ "GPIOZ_6",
+ "GPIOZ_7",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {"lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,30,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {"lvds_1",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,30,0,
+ /* clk_attr */
+ 1,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*LG: RDL550WY: 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*INL: V580DJ2: 3840x2160@60hz 8lane */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,65,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_3d_disable, lcd_power_off_step_3d_disable,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 20, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txl_t950_skt_v1/txl_t950_skt_v1.c b/board/amlogic/txl_t950_skt_v1/txl_t950_skt_v1.c
new file mode 100644
index 0000000..fb955a5
--- /dev/null
+++ b/board/amlogic/txl_t950_skt_v1/txl_t950_skt_v1.c
@@ -0,0 +1,655 @@
+
+/*
+ * board/amlogic/txl_t950_skt_v1/txl_t950_skt_v1.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <amlogic/spifc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 0;
+ eth_reg0.b.data_endian = 0;
+ eth_reg0.b.desc_endian = 0;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO2_EN_N, 1 << 26);//CARD_6
+ ret = readl(P_PREG_PAD_GPIO2_I) & (1 << 26) ? 0 : 1;
+ printf("%s\n", ret ? "card in" : "card out");
+ if ((readl(P_PERIPHS_PIN_MUX_6) & (3 << 8))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I) & (1 << 24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+/*USE_HDMI_UART_FUNC*/
+#define HDMI_UART_PORT_NUM 3
+
+struct hdmi_uart_date_io {
+ char *power;
+ char *scl;
+ volatile uint32_t * hdmi_sda_reg;
+ unsigned int hdmi_sda_bit;
+ volatile uint32_t * uart_tx_reg;
+ unsigned int uart_tx_bit;
+ volatile uint32_t * hdmi_scl_reg;
+ unsigned int hdmi_scl_bit;
+ volatile uint32_t * uart_rx_reg;
+ unsigned int uart_rx_bit;
+};
+
+struct hdmi_uart_date_io txl_hdmi_uart_date_io[HDMI_UART_PORT_NUM+1]=
+{
+ {"GPIOW_5" ,"GPIOW_7" ,P_PERIPHS_PIN_MUX_5,25,P_PERIPHS_PIN_MUX_5,13,P_PERIPHS_PIN_MUX_5 ,24 ,P_PERIPHS_PIN_MUX_5,12,},
+ {"GPIOW_9", "GPIOW_11",P_PERIPHS_PIN_MUX_5,21,P_PERIPHS_PIN_MUX_5,11,P_PERIPHS_PIN_MUX_5 ,20 ,P_PERIPHS_PIN_MUX_5,10,},
+ {"GPIOW_13","GPIOW_15",P_PERIPHS_PIN_MUX_5,17,P_PERIPHS_PIN_MUX_5,9, P_PERIPHS_PIN_MUX_5 ,16 ,P_PERIPHS_PIN_MUX_5,8,},
+ {NULL, NULL, 0, 0,P_AO_RTI_PIN_MUX_REG,12,0 , 0 ,P_AO_RTI_PIN_MUX_REG,11,},
+};
+
+struct hdmi_uart_date_io gxtvbb_hdmi_uart_date_io[HDMI_UART_PORT_NUM+1]=
+{
+ {"GPIOW_6" ,"GPIOW_5" ,P_PERIPHS_PIN_MUX_6 ,9 ,P_PERIPHS_PIN_MUX_10,1,P_PERIPHS_PIN_MUX_6 ,10 ,P_PERIPHS_PIN_MUX_6,11,},
+ {"GPIOW_10","GPIOW_9" ,P_PERIPHS_PIN_MUX_6 ,14 ,P_PERIPHS_PIN_MUX_10,2,P_PERIPHS_PIN_MUX_6 ,15 ,P_PERIPHS_PIN_MUX_6,16,},
+ {"GPIOW_14","GPIOW_13",P_PERIPHS_PIN_MUX_6 ,19 ,P_PERIPHS_PIN_MUX_10,3,P_PERIPHS_PIN_MUX_6 ,20 ,P_PERIPHS_PIN_MUX_6,21,},
+ {NULL, NULL, 0, 0 ,P_AO_RTI_PIN_MUX_REG,0,0 , 0 ,P_AO_RTI_PIN_MUX_REG,1,},
+};
+
+struct hdmi_uart_det_io {
+ char *power;
+ char *scl;
+ volatile uint32_t * uart_det_power_reg;
+ unsigned int uart_det_power_bit;
+ unsigned int uart_det_power_need_level;
+ volatile uint32_t * uart_det_scl_reg;
+ unsigned int uart_det_scl_bit;
+ unsigned int uart_det_scl_need_level;
+};
+
+struct hdmi_uart_det_io txl_hdmi_uart_det_io[HDMI_UART_PORT_NUM]=
+{
+ {"GPIOW_5" , "GPIOW_7" , P_PREG_PAD_GPIO4_I , 5 , 0, P_PREG_PAD_GPIO4_I ,7 , 1,},
+ {"GPIOW_9", "GPIOW_11", P_PREG_PAD_GPIO4_I , 9 , 0, P_PREG_PAD_GPIO4_I ,11, 1,},
+ {"GPIOW_13", "GPIOW_15" , P_PREG_PAD_GPIO4_I , 13, 0, P_PREG_PAD_GPIO4_I ,15, 1,},
+};
+
+/* in gxtvbb,use hpd port as (txl)scl port */
+struct hdmi_uart_det_io gxtvbb_hdmi_uart_det_io[HDMI_UART_PORT_NUM]=
+{
+ {"GPIOW_6" ,"GPIOW_5" , P_PREG_PAD_GPIO0_I, 6 , 0, P_PREG_PAD_GPIO0_I ,5 , 1,},
+ {"GPIOW_10","GPIOW_9" , P_PREG_PAD_GPIO0_I, 10, 0, P_PREG_PAD_GPIO0_I ,9 , 1,},
+ {"GPIOW_14","GPIOW_13", P_PREG_PAD_GPIO0_I, 14, 0, P_PREG_PAD_GPIO0_I ,13, 1,},
+};
+
+static void init_hdmi_uart_board(void)
+{
+ int i=0;
+ int pwr_value=0,scl_value=0;
+ int flag=0;
+ struct hdmi_uart_date_io *hdmi_uart_date_io;
+ struct hdmi_uart_det_io *hdmi_uart_det_io;
+
+ if (get_cpu_id().family_id <= MESON_CPU_MAJOR_ID_GXTVBB) {
+ hdmi_uart_det_io = gxtvbb_hdmi_uart_det_io;
+ hdmi_uart_date_io = gxtvbb_hdmi_uart_date_io;
+ /*printf("choose gxtvbb board.\n");*/
+ } else {
+ hdmi_uart_det_io = txl_hdmi_uart_det_io;
+ hdmi_uart_date_io = txl_hdmi_uart_date_io;
+ /*printf("choose txl board.\n");*/
+ }
+
+ for (i=0; i<HDMI_UART_PORT_NUM; i++) {
+ pwr_value = readl(hdmi_uart_det_io[i].uart_det_power_reg) >> hdmi_uart_det_io[i].uart_det_power_bit;
+ pwr_value &= 1;
+ scl_value = readl(hdmi_uart_det_io[i].uart_det_scl_reg) >> hdmi_uart_det_io[i].uart_det_scl_bit;
+ scl_value &= 1;
+
+ if ((pwr_value == hdmi_uart_det_io[i].uart_det_power_need_level)
+ && (scl_value == hdmi_uart_det_io[i].uart_det_scl_need_level)) {
+ flag = 1;
+ break;
+ }
+ }
+
+ if (flag == 1) {
+ printf("switch to %d hdmirx_uart port\n",i);
+ /* clean default uart pinmux */
+ writel(readl(hdmi_uart_date_io[3].uart_tx_reg)&~(1 << hdmi_uart_date_io[3].uart_tx_bit),
+ (volatile void *)hdmi_uart_date_io[3].uart_tx_reg);
+ writel(readl(hdmi_uart_date_io[3].uart_rx_reg)&~(1 << hdmi_uart_date_io[3].uart_rx_bit),
+ (volatile void *)hdmi_uart_date_io[3].uart_rx_reg);
+
+ /* set hdmi_uart pinmux */
+ writel(readl(hdmi_uart_date_io[i].hdmi_sda_reg)&~(1 << hdmi_uart_date_io[i].hdmi_sda_bit),
+ (volatile void *)hdmi_uart_date_io[i].hdmi_sda_reg);
+ writel(readl(hdmi_uart_date_io[i].uart_tx_reg)|(1 << hdmi_uart_date_io[i].uart_tx_bit),
+ (volatile void *)hdmi_uart_date_io[i].uart_tx_reg);
+
+ writel(readl(hdmi_uart_date_io[i].hdmi_scl_reg)&~(1 << hdmi_uart_date_io[i].hdmi_scl_bit),
+ (volatile void *)hdmi_uart_date_io[i].hdmi_scl_reg);
+ writel(readl(hdmi_uart_date_io[i].uart_rx_reg)|(1 << hdmi_uart_date_io[i].uart_rx_bit),
+ (volatile void *)hdmi_uart_date_io[i].uart_rx_reg);
+ }
+}
+/*endif*/
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_4: NOR_D:reg7[13], clr reg7[31] reg7[22]
+ * BOOT_5: NOR_Q:reg7[12], clr reg7[31] reg7[21]
+ * BOOT_6: NOR_C:reg7[11], clr reg7[31] reg7[20]
+ * BOOT_11: NOR_CS:reg7[10],clr reg7[28]
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {78/*BOOT_11*/};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_7);
+ val &= ~((1<<13)|(1<<12)|(1<<11)|(1<<10));
+ if (enable) {
+ val |= (1<<13)|(1<<12)|(1<<11);
+ val &= ~((1<<31)|(1<<28)|(1<<22)|(1<<21)|(1<<20));
+ }
+ writel(val, P_PERIPHS_PIN_MUX_7);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xc1108c80,
+ .mem_map = 0xcc000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+writel(readl(AO_GPIO_O_EN_N) & (~(0x1 << 10)), AO_GPIO_O_EN_N); //set mode: output
+writel(readl(AO_GPIO_O_EN_N) | (0x1 << 26),AO_GPIO_O_EN_N); //output 1
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+ char* env;
+ unsigned int hwid = 1;
+
+ /*USE_HDMI_UART_FUNC*/
+ env = getenv("hdmiuart_mode");
+ /*printf("hdmiuart_mode env:%s\n",env);*/
+ if (env) {
+ if (!strcmp(env,"open")) {
+ printf("CONFIG_HDMI_UART_BOARD\n");
+ init_hdmi_uart_board();
+ }
+ }
+ /*endif*/
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+
+ /* enable 5V for USB, panel, wifi */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+ switch (hwid) {
+ case 1:
+ run_command("gpio set GPIOAO_4", 0);
+ break;
+ case 2:
+ /* set output mode for GPIOAO_10 */
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<10));
+ /* set output level to high for GPIOAO_10 */
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<26));
+ break;
+ default:
+ /* set output mode for GPIOAO_10 */
+ clrbits_le32(P_AO_GPIO_O_EN_N, (1<<10));
+ /* set output level to high for GPIOAO_10 */
+ setbits_le32(P_AO_GPIO_O_EN_N, (1<<26));
+ printf("invalid hwid = %d\n", hwid);
+ break;
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ */
+ unsigned int hwid = 1;
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/txlx_t962e_r321_v1/Kconfig b/board/amlogic/txlx_t962e_r321_v1/Kconfig
new file mode 100644
index 0000000..2b7ceb9
--- /dev/null
+++ b/board/amlogic/txlx_t962e_r321_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_TXLX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "txlx_t962e_r321_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "txlx"
+
+config SYS_CONFIG_NAME
+ default "txlx_t962e_r321_v1"
+
+endif
diff --git a/board/amlogic/txlx_t962e_r321_v1/Makefile b/board/amlogic/txlx_t962e_r321_v1/Makefile
new file mode 100644
index 0000000..963e9c5
--- /dev/null
+++ b/board/amlogic/txlx_t962e_r321_v1/Makefile
@@ -0,0 +1,4 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
+obj-y += pwm_table.o
diff --git a/board/amlogic/txlx_t962e_r321_v1/aml-user-key.sig b/board/amlogic/txlx_t962e_r321_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/txlx_t962e_r321_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/txlx_t962e_r321_v1/eth_setup.c b/board/amlogic/txlx_t962e_r321_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/txlx_t962e_r321_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/txlx_t962e_r321_v1/firmware/board_init.c b/board/amlogic/txlx_t962e_r321_v1/firmware/board_init.c
new file mode 100644
index 0000000..f519dda
--- /dev/null
+++ b/board/amlogic/txlx_t962e_r321_v1/firmware/board_init.c
@@ -0,0 +1,65 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+
+#define PNL_PREG_PAD_GPIO1_EN_N 0x0f
+#define PNL_PREG_PAD_GPIO1_O 0x10
+#define PNL_PREG_PAD_GPIO1_I 0x11
+
+#define PNL_PREG_PAD_GPIO3_EN_N 0x15
+#define PNL_PREG_PAD_GPIO3_O 0x16
+#define PNL_PREG_PAD_GPIO3_I 0x17
+
+#define PNL_REG_BASE (0xff634400L)
+#define PNL_REG(reg) (PNL_REG_BASE + (reg << 2))
+#define PNL_REG_R(_reg) (*(volatile unsigned int *)PNL_REG(_reg))
+#define PNL_REG_W(_reg, _value) *(volatile unsigned int *)PNL_REG(_reg) = (_value);
+static void panel_power_init(void)
+{
+ serial_puts("init panel power\n");
+
+ /* panel: GPIOZ_13/8/9 */ /* remove GPIOZ_10 for 2D/3D special case */
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_O) & ~((0x3 << 8) | (1 << 13))));
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_EN_N) & ~((0x3 << 8) | (1 << 13))));
+ /* panel: GPIOH_4/5 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_O) & ~(0x3 << 24)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_EN_N) & ~(0x3 << 24)));
+
+ /* backlight: GPIOZ_4/6/7 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_O) & ~((1 << 4) | (0x3 << 6))));
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_EN_N) & ~((1 << 4) | (0x3 << 6))));
+}
+
+void board_init(void)
+{
+ power_init(0);
+
+ panel_power_init();
+}
\ No newline at end of file
diff --git a/board/amlogic/txlx_t962e_r321_v1/firmware/power.c b/board/amlogic/txlx_t962e_r321_v1/firmware/power.c
new file mode 100644
index 0000000..666f004
--- /dev/null
+++ b/board/amlogic/txlx_t962e_r321_v1/firmware/power.c
@@ -0,0 +1,254 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/power.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+#define AO_PIN_MUX_REG (*((volatile unsigned *)(0xff800000 + (0x05 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_ao_b,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+ int vol;
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~((1 << 21) | 1 << 12);
+ P_PIN_MUX_REG3 = reg;
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(1 << 16);
+ P_PIN_MUX_REG10 = reg;//clear reg10
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26);
+ reg |= (1 << 17);
+ P_PIN_MUX_REG4 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ //writel( pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0],AO_PWM_PWM_B);
+ reg = AO_PIN_MUX_REG;
+ reg |= (1 << 3);
+ AO_PIN_MUX_REG = reg;
+
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+/*
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+*/
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ switch (id) {
+ case pwm_a:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set AO 2/10/11 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~((1 << 2)|(1 << 10)|(1 << 11));
+ reg |= ((1 << 18)|(1 << 26)|(1 << 27));
+ writel(reg, AO_GPIO_O_EN_N);
+ serial_puts("set test_n to high\n ");
+ reg = readl(AO_SEC_REG0);
+ reg |= (1 << 0);
+ writel(reg, AO_SEC_REG0);
+ reg = readl(AO_GPIO_O_EN_N);
+ reg |= (1 << 31);
+ writel(reg, AO_GPIO_O_EN_N);
+}
diff --git a/board/amlogic/txlx_t962e_r321_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/txlx_t962e_r321_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..e9b409b
--- /dev/null
+++ b/board/amlogic/txlx_t962e_r321_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,194 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+/*
+int pwm_voltage_table[ ][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+*/
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~((1 << 21) | 1 << 12);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(1 << 16);
+ P_PIN_MUX_REG10 = reg;//clear reg10
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/txlx_t962e_r321_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/txlx_t962e_r321_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..7b67562
--- /dev/null
+++ b/board/amlogic/txlx_t962e_r321_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,37 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
diff --git a/board/amlogic/txlx_t962e_r321_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/txlx_t962e_r321_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..494a2a9
--- /dev/null
+++ b/board/amlogic/txlx_t962e_r321_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,410 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "pwm_ctrl.h"
+
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xff807000 + (0x01 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+#define ON 1
+#define OFF 0
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+#if 0
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#endif
+
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+ switch (id) {
+ case pwm_a:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table_ee[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_off_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+}
+
+static void power_off_at_clk81(void)
+{
+
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
+ _udelay(10000);
+}
+
+/*timing request:
+ *poweroff vddio3.3v-->delay 20ms-->poweroff vddee
+ */
+static void power_off_vddee(void)
+{
+ unsigned int val;
+
+ /*set test n output low level */
+ _udelay(10000);/*the other 10ms in power_off_at_32k()*/
+ val = readl(AO_GPIO_O_EN_N);
+ val &= ~(0x1 << 31);
+ writel(val, AO_GPIO_O_EN_N);
+
+}
+
+/*timing request:
+ *poweron vddee-->delay 20ms-->poweron vddio3.3v
+ */
+static void power_on_vddee(void)
+{
+ unsigned int val;
+
+ /*set test n output high level */
+ val = readl(AO_GPIO_O_EN_N);
+ val |= 0x1 << 31;
+ writel(val, AO_GPIO_O_EN_N);
+ _udelay(10000);/*the other 10ms in power_on_at_32k()*/
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+ power_off_usb5v();
+ _udelay(5000);
+ power_off_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_vddee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+ if (suspend_from == SYS_POWEROFF)
+ power_on_vddee();
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ _udelay(10000);
+ power_on_3v3_5v();
+ _udelay(10000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ _udelay(10000);
+ _udelay(10000);
+ power_on_usb5v();
+
+ if (suspend_from == SYS_POWEROFF)
+ power_on_ddr();
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ p->gpio_info_count = i;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ val |= CECB_WAKEUP_SRC;
+#endif
+
+#ifdef CONFIG_BT_WAKEUP
+ {
+ struct wakeup_gpio_info *gpio;
+ /* BT Wakeup: IN: GPIOX[21], OUT: GPIOX[20] */
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_12;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+ }
+#endif
+ p->sources = val;
+
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ init_remote();
+ saradc_enable();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CECB_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+// if (suspend_from == SYS_POWEROFF)
+// continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+#ifdef CONFIG_BT_WAKEUP
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(P_AO_GPIO_O_EN_N)
+ & (0x01 << 13)) && (readl(P_AO_GPIO_O_EN_N)
+ & (0x01 << 29)) &&
+ !(readl(P_AO_GPIO_I)
+ & (0x01 << 12))){
+ uart_puts("bt wakeup pin\n");
+ exit_reason = BT_WAKEUP;
+ }
+ }
+#endif
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/txlx_t962e_r321_v1/firmware/timing.c b/board/amlogic/txlx_t962e_r321_v1/firmware/timing.c
new file mode 100644
index 0000000..cf5493e
--- /dev/null
+++ b/board/amlogic/txlx_t962e_r321_v1/firmware/timing.c
@@ -0,0 +1,569 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_60OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x59959, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0x10,
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/txlx_t962e_r321_v1/lcd.c b/board/amlogic/txlx_t962e_r321_v1/lcd.c
new file mode 100755
index 0000000..cf75040
--- /dev/null
+++ b/board/amlogic/txlx_t962e_r321_v1/lcd.c
@@ -0,0 +1,429 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_13", /* PANEL_PWR */
+ "GPIOZ_8", /* SCN_EN */
+ "GPIOZ_9", /* LD_EN2 */
+ "GPIOZ_10", /* 2D_3D */
+ "GPIOH_4", /* LR_IN */
+ "GPIOH_5", /* SEL_LVDS */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,50,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_3d_disable[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_CPU, 3,0,10,}, /* 3d_disable */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_3d_disable[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,30,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 3,2,0,}, /* 3d_disable */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_4", /* BL_EN */
+ "GPIOZ_6", /* BL_PWM */
+ "GPIOZ_7", /* Dimming */
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* for HDMI convert*/
+ "lvds_1",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 1,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* 2-region for HDMI convert */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 1,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_3d_disable, lcd_power_off_step_3d_disable,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOH_0/1
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{0, 0x009c0800}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_vs_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00008000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00010000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_0_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_1_on_pin", //GPIOZ_7
+ .pinmux_set = {{4, 0x00004000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00002000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_0_vs_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00008000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00010000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_1_vs_on_pin", //GPIOZ_7
+ .pinmux_set = {{4, 0x00002000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00004000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{0, 0x009c0800}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txlx_t962e_r321_v1/pwm_table.c b/board/amlogic/txlx_t962e_r321_v1/pwm_table.c
new file mode 100644
index 0000000..18dc638
--- /dev/null
+++ b/board/amlogic/txlx_t962e_r321_v1/pwm_table.c
@@ -0,0 +1,71 @@
+#include <common.h>
+
+const int pwm_cal_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+const int pwm_cal_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
+int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
+
+
diff --git a/board/amlogic/txlx_t962e_r321_v1/txlx_t962e_r321_v1.c b/board/amlogic/txlx_t962e_r321_v1/txlx_t962e_r321_v1.c
new file mode 100644
index 0000000..e96bb68
--- /dev/null
+++ b/board/amlogic/txlx_t962e_r321_v1/txlx_t962e_r321_v1.c
@@ -0,0 +1,488 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm-generic/gpio.h>
+#ifdef CONFIG_AML_SPICC
+#include <dm.h>
+#include <amlogic/spicc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+#ifdef CONFIG_AML_SPICC
+/* generic config in arch gpio/clock.c */
+extern int spicc0_clk_enable(bool enable);
+extern int spicc0_pinctrl_enable(bool enable);
+
+static const struct spicc_platdata spicc0_platdata = {
+ .compatible = "amlogic,meson-txl-spicc",
+ .reg = (void __iomem *)0xffd13000,
+ .clk_rate = 166666666,
+ .clk_enable = spicc0_clk_enable,
+ .pinctrl_enable = spicc0_pinctrl_enable,
+ /* case one slave without cs: {"no_cs", 0} */
+ .cs_gpio_names = {"GPIOZ_3", 0},
+};
+
+U_BOOT_DEVICE(spicc0) = {
+ .name = "spicc",
+ .platdata = &spicc0_platdata,
+};
+#endif /* CONFIG_AML_SPICC */
+
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
+ aml_try_factory_usb_burning(0, gd->bd);
+ }
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_pwm_cal_init(0);
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ run_command("cvbs init", 0);
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
+ aml_try_factory_usb_burning(1, gd->bd);
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ /*
+ * read board hw id
+ * set and select the dts according the board hw id.
+ *
+ * hwid = 1 p321 v1
+ * hwid = 2 p321 v2
+ */
+ unsigned int hwid = 1;
+ char loc_name[64] = {0};
+
+ /* read hwid */
+ hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
+
+ printf("checkhw: hwid = %d\n", hwid);
+
+
+ switch (hwid) {
+ case 1:
+ strcpy(loc_name, "txl_p321_v1\0");
+ break;
+ case 2:
+ strcpy(loc_name, "txl_p321_v2\0");
+ break;
+ default:
+ strcpy(loc_name, "txl_p321_v1");
+ break;
+ }
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/txlx_t962e_skt_v1/Kconfig b/board/amlogic/txlx_t962e_skt_v1/Kconfig
new file mode 100644
index 0000000..9110eb0
--- /dev/null
+++ b/board/amlogic/txlx_t962e_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_TXLX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "txlx_t962e_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "txlx"
+
+config SYS_CONFIG_NAME
+ default "txlx_t962e_skt_v1"
+
+endif
diff --git a/board/amlogic/txlx_t962e_skt_v1/Makefile b/board/amlogic/txlx_t962e_skt_v1/Makefile
new file mode 100644
index 0000000..2f926cc
--- /dev/null
+++ b/board/amlogic/txlx_t962e_skt_v1/Makefile
@@ -0,0 +1,4 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
+obj-y +=pwm_table.o
diff --git a/board/amlogic/txlx_t962e_skt_v1/aml-user-key.sig b/board/amlogic/txlx_t962e_skt_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/txlx_t962e_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/txlx_t962e_skt_v1/eth_setup.c b/board/amlogic/txlx_t962e_skt_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/txlx_t962e_skt_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/txlx_t962e_skt_v1/firmware/board_init.c b/board/amlogic/txlx_t962e_skt_v1/firmware/board_init.c
new file mode 100644
index 0000000..2771433
--- /dev/null
+++ b/board/amlogic/txlx_t962e_skt_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/txlx_t962e_skt_v1/firmware/power.c b/board/amlogic/txlx_t962e_skt_v1/firmware/power.c
new file mode 100644
index 0000000..ba4fc6f
--- /dev/null
+++ b/board/amlogic/txlx_t962e_skt_v1/firmware/power.c
@@ -0,0 +1,256 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+#define AO_PIN_MUX_REG (*((volatile unsigned *)(0xff800000 + (0x05 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_ao_b,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ */
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~((1 << 21) | 1 << 12);
+ P_PIN_MUX_REG3 = reg;
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(1 << 16);
+ P_PIN_MUX_REG10 = reg;//clear reg10
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26);
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ //writel( pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0],AO_PWM_PWM_B);
+ reg = AO_PIN_MUX_REG;
+ reg |= (1 << 3);
+ AO_PIN_MUX_REG = reg;
+
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+/*
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+*/
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ switch (id) {
+ case pwm_a:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vddee enable AO 2/10 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~((1 << 2)|(1 << 10));
+ reg |= ((1 << 18)|(1 << 26));
+ writel(reg, AO_GPIO_O_EN_N);
+ serial_puts("set test_n to high\n ");
+ reg = readl(AO_SEC_REG0);
+ reg |= (1 << 0);
+ writel(reg, AO_SEC_REG0);
+ reg = readl(AO_GPIO_O_EN_N);
+ reg |= (1 << 31);
+ writel(reg, AO_GPIO_O_EN_N);
+}
diff --git a/board/amlogic/txlx_t962e_skt_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/txlx_t962e_skt_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..d7474e8
--- /dev/null
+++ b/board/amlogic/txlx_t962e_skt_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,191 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+/*
+int pwm_voltage_table[ ][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+*/
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~((1 << 21) | 1 << 12);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(1 << 16);
+ P_PIN_MUX_REG10 = reg;//clear reg10
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/txlx_t962e_skt_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/txlx_t962e_skt_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..7b67562
--- /dev/null
+++ b/board/amlogic/txlx_t962e_skt_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,37 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
diff --git a/board/amlogic/txlx_t962e_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/txlx_t962e_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..a647727
--- /dev/null
+++ b/board/amlogic/txlx_t962e_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,368 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "pwm_ctrl.h"
+
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xff807000 + (0x01 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+#define ON 1
+#define OFF 0
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+#if 0
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#endif
+
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ switch (id) {
+ case pwm_a:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table_ee[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_off_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+}
+
+static void power_off_at_clk81(void)
+{
+
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
+ _udelay(10000);
+}
+
+/*timing request:
+ *poweroff vddio3.3v-->delay 20ms-->poweroff vddee
+ */
+static void power_off_vddee(void)
+{
+ unsigned int val;
+
+ /*set test n output low level */
+ _udelay(10000);/*the other 10ms in power_off_at_32k()*/
+ val = readl(AO_GPIO_O_EN_N);
+ val &= ~(0x1 << 31);
+ writel(val, AO_GPIO_O_EN_N);
+
+}
+
+/*timing request:
+ *poweron vddee-->delay 20ms-->poweron vddio3.3v
+ */
+static void power_on_vddee(void)
+{
+ unsigned int val;
+
+ /*set test n output high level */
+ val = readl(AO_GPIO_O_EN_N);
+ val |= 0x1 << 31;
+ writel(val, AO_GPIO_O_EN_N);
+ _udelay(10000);/*the other 10ms in power_on_at_32k()*/
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+ power_off_usb5v();
+ _udelay(5000);
+ power_off_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_vddee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+ if (suspend_from == SYS_POWEROFF)
+ power_on_vddee();
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ _udelay(10000);
+ power_on_3v3_5v();
+ _udelay(10000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ _udelay(10000);
+ _udelay(10000);
+ power_on_usb5v();
+
+ if (suspend_from == SYS_POWEROFF)
+ power_on_ddr();
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ val |= CECB_WAKEUP_SRC;
+#endif
+ p->sources = val;
+ p->gpio_info_count = 0;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ init_remote();
+ saradc_enable();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CECB_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+// if (suspend_from == SYS_POWEROFF)
+// continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/txlx_t962e_skt_v1/firmware/timing.c b/board/amlogic/txlx_t962e_skt_v1/firmware/timing.c
new file mode 100644
index 0000000..cf5493e
--- /dev/null
+++ b/board/amlogic/txlx_t962e_skt_v1/firmware/timing.c
@@ -0,0 +1,569 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_60OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x59959, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0x10,
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/txlx_t962e_skt_v1/lcd.c b/board/amlogic/txlx_t962e_skt_v1/lcd.c
new file mode 100755
index 0000000..e09cba8
--- /dev/null
+++ b/board/amlogic/txlx_t962e_skt_v1/lcd.c
@@ -0,0 +1,358 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ //"GPIOX_3",
+ //"GPIOX_2",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ //{LCD_POWER_TYPE_CPU, 0,1,50,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ //{LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ //"GPIOAO_4",
+ //"GPIOY_13",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0xff,1,0,0,0,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOH_0/1
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{0, 0x009c0800}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_vs_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00008000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00010000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_0_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_1_on_pin", //GPIOZ_7
+ .pinmux_set = {{4, 0x00004000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00002000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_0_vs_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00008000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00010000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_1_vs_on_pin", //GPIOZ_7
+ .pinmux_set = {{4, 0x00002000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00004000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ // {
+ // .type = LCD_POWER_TYPE_CPU,
+ // .index = 0, /* point to cpu_gpio[] struct */
+ // .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ // .delay = 50, /* unit: ms */
+ // },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ // {
+ // .type = LCD_POWER_TYPE_CPU,
+ // .index = 0, /* point to cpu_gpio[] struct */
+ // .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ // .delay = 100, /* unit: ms */
+ // },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{0, 0x009c0800}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txlx_t962e_skt_v1/pwm_table.c b/board/amlogic/txlx_t962e_skt_v1/pwm_table.c
new file mode 100644
index 0000000..18dc638
--- /dev/null
+++ b/board/amlogic/txlx_t962e_skt_v1/pwm_table.c
@@ -0,0 +1,71 @@
+#include <common.h>
+
+const int pwm_cal_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+const int pwm_cal_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
+int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
+
+
diff --git a/board/amlogic/txlx_t962e_skt_v1/txlx_t962e_skt_v1.c b/board/amlogic/txlx_t962e_skt_v1/txlx_t962e_skt_v1.c
new file mode 100644
index 0000000..fe908b3
--- /dev/null
+++ b/board/amlogic/txlx_t962e_skt_v1/txlx_t962e_skt_v1.c
@@ -0,0 +1,456 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txlx_t962e_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/secure_apb.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <amlogic/spifc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_4: NOR_D:reg7[13], clr reg7[31] reg7[22]
+ * BOOT_5: NOR_Q:reg7[12], clr reg7[31] reg7[21]
+ * BOOT_6: NOR_C:reg7[11], clr reg7[31] reg7[20]
+ * BOOT_11: NOR_CS:reg7[10],clr reg7[28]
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {49/*BOOT_11*/};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_7);
+ val &= ~((1<<13)|(1<<12)|(1<<11)|(1<<10));
+ if (enable) {
+ val |= (1<<13)|(1<<12)|(1<<11);
+ val &= ~((1<<31)|(1<<28)|(1<<22)|(1<<21)|(1<<20));
+ }
+ writel(val, P_PERIPHS_PIN_MUX_7);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xfb000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_pwm_cal_init(0);
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
diff --git a/board/amlogic/txlx_t962x_r311_v1/Kconfig b/board/amlogic/txlx_t962x_r311_v1/Kconfig
new file mode 100644
index 0000000..20dd760
--- /dev/null
+++ b/board/amlogic/txlx_t962x_r311_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_TXLX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "txlx_t962x_r311_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "txlx"
+
+config SYS_CONFIG_NAME
+ default "txlx_t962x_r311_v1"
+
+endif
diff --git a/board/amlogic/txlx_t962x_r311_v1/Makefile b/board/amlogic/txlx_t962x_r311_v1/Makefile
new file mode 100644
index 0000000..2f926cc
--- /dev/null
+++ b/board/amlogic/txlx_t962x_r311_v1/Makefile
@@ -0,0 +1,4 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
+obj-y +=pwm_table.o
diff --git a/board/amlogic/txlx_t962x_r311_v1/aml-user-key.sig b/board/amlogic/txlx_t962x_r311_v1/aml-user-key.sig
new file mode 100755
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/txlx_t962x_r311_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/txlx_t962x_r311_v1/eth_setup.c b/board/amlogic/txlx_t962x_r311_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/txlx_t962x_r311_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/txlx_t962x_r311_v1/firmware/board_init.c b/board/amlogic/txlx_t962x_r311_v1/firmware/board_init.c
new file mode 100644
index 0000000..f519dda
--- /dev/null
+++ b/board/amlogic/txlx_t962x_r311_v1/firmware/board_init.c
@@ -0,0 +1,65 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+
+#define PNL_PREG_PAD_GPIO1_EN_N 0x0f
+#define PNL_PREG_PAD_GPIO1_O 0x10
+#define PNL_PREG_PAD_GPIO1_I 0x11
+
+#define PNL_PREG_PAD_GPIO3_EN_N 0x15
+#define PNL_PREG_PAD_GPIO3_O 0x16
+#define PNL_PREG_PAD_GPIO3_I 0x17
+
+#define PNL_REG_BASE (0xff634400L)
+#define PNL_REG(reg) (PNL_REG_BASE + (reg << 2))
+#define PNL_REG_R(_reg) (*(volatile unsigned int *)PNL_REG(_reg))
+#define PNL_REG_W(_reg, _value) *(volatile unsigned int *)PNL_REG(_reg) = (_value);
+static void panel_power_init(void)
+{
+ serial_puts("init panel power\n");
+
+ /* panel: GPIOZ_13/8/9 */ /* remove GPIOZ_10 for 2D/3D special case */
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_O) & ~((0x3 << 8) | (1 << 13))));
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_EN_N) & ~((0x3 << 8) | (1 << 13))));
+ /* panel: GPIOH_4/5 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_O) & ~(0x3 << 24)));
+ PNL_REG_W(PNL_PREG_PAD_GPIO1_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO1_EN_N) & ~(0x3 << 24)));
+
+ /* backlight: GPIOZ_4/6/7 */
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_O,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_O) & ~((1 << 4) | (0x3 << 6))));
+ PNL_REG_W(PNL_PREG_PAD_GPIO3_EN_N,
+ (PNL_REG_R(PNL_PREG_PAD_GPIO3_EN_N) & ~((1 << 4) | (0x3 << 6))));
+}
+
+void board_init(void)
+{
+ power_init(0);
+
+ panel_power_init();
+}
\ No newline at end of file
diff --git a/board/amlogic/txlx_t962x_r311_v1/firmware/power.c b/board/amlogic/txlx_t962x_r311_v1/firmware/power.c
new file mode 100644
index 0000000..666f004
--- /dev/null
+++ b/board/amlogic/txlx_t962x_r311_v1/firmware/power.c
@@ -0,0 +1,254 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/power.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+#define AO_PIN_MUX_REG (*((volatile unsigned *)(0xff800000 + (0x05 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_ao_b,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+ int vol;
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~((1 << 21) | 1 << 12);
+ P_PIN_MUX_REG3 = reg;
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(1 << 16);
+ P_PIN_MUX_REG10 = reg;//clear reg10
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26);
+ reg |= (1 << 17);
+ P_PIN_MUX_REG4 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ //writel( pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0],AO_PWM_PWM_B);
+ reg = AO_PIN_MUX_REG;
+ reg |= (1 << 3);
+ AO_PIN_MUX_REG = reg;
+
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+/*
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+*/
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ switch (id) {
+ case pwm_a:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set AO 2/10/11 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~((1 << 2)|(1 << 10)|(1 << 11));
+ reg |= ((1 << 18)|(1 << 26)|(1 << 27));
+ writel(reg, AO_GPIO_O_EN_N);
+ serial_puts("set test_n to high\n ");
+ reg = readl(AO_SEC_REG0);
+ reg |= (1 << 0);
+ writel(reg, AO_SEC_REG0);
+ reg = readl(AO_GPIO_O_EN_N);
+ reg |= (1 << 31);
+ writel(reg, AO_GPIO_O_EN_N);
+}
diff --git a/board/amlogic/txlx_t962x_r311_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/txlx_t962x_r311_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..e9b409b
--- /dev/null
+++ b/board/amlogic/txlx_t962x_r311_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,194 @@
+
+/*
+ * board/amlogic/txl_p321_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+/*
+int pwm_voltage_table[ ][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+*/
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~((1 << 21) | 1 << 12);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(1 << 16);
+ P_PIN_MUX_REG10 = reg;//clear reg10
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/txlx_t962x_r311_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/txlx_t962x_r311_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..7b67562
--- /dev/null
+++ b/board/amlogic/txlx_t962x_r311_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,37 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
diff --git a/board/amlogic/txlx_t962x_r311_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/txlx_t962x_r311_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..dd4bdfa
--- /dev/null
+++ b/board/amlogic/txlx_t962x_r311_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,410 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "pwm_ctrl.h"
+
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xff807000 + (0x01 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+#define ON 1
+#define OFF 0
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+#if 0
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#endif
+
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+ switch (id) {
+ case pwm_a:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table_ee[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_off_usb5v(void)
+{
+ return;
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ return;
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+}
+
+static void power_off_at_clk81(void)
+{
+
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
+ _udelay(10000);
+}
+
+/*timing request:
+ *poweroff vddio3.3v-->delay 20ms-->poweroff vddee
+ */
+static void power_off_vddee(void)
+{
+ unsigned int val;
+
+ /*set test n output low level */
+ _udelay(10000);/*the other 10ms in power_off_at_32k()*/
+ val = readl(AO_GPIO_O_EN_N);
+ val &= ~(0x1 << 31);
+ writel(val, AO_GPIO_O_EN_N);
+
+}
+
+/*timing request:
+ *poweron vddee-->delay 20ms-->poweron vddio3.3v
+ */
+static void power_on_vddee(void)
+{
+ unsigned int val;
+
+ /*set test n output high level */
+ val = readl(AO_GPIO_O_EN_N);
+ val |= 0x1 << 31;
+ writel(val, AO_GPIO_O_EN_N);
+ _udelay(10000);/*the other 10ms in power_on_at_32k()*/
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+ power_off_usb5v();
+ _udelay(5000);
+ power_off_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_vddee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+ if (suspend_from == SYS_POWEROFF)
+ power_on_vddee();
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ _udelay(10000);
+ power_on_3v3_5v();
+ _udelay(10000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ _udelay(10000);
+ _udelay(10000);
+ power_on_usb5v();
+
+ if (suspend_from == SYS_POWEROFF)
+ power_on_ddr();
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ p->gpio_info_count = i;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ val |= CECB_WAKEUP_SRC;
+#endif
+
+#ifdef CONFIG_BT_WAKEUP
+ {
+ struct wakeup_gpio_info *gpio;
+ /* BT Wakeup: IN: GPIOX[21], OUT: GPIOX[20] */
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_12;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+ }
+#endif
+ p->sources = val;
+
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ init_remote();
+ saradc_enable();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CECB_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+// if (suspend_from == SYS_POWEROFF)
+// continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_TIMERA] == IRQ_TIMERA_NUM) {
+ irq[IRQ_TIMERA] = 0xFFFFFFFF;
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ }
+
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+#ifdef CONFIG_BT_WAKEUP
+ if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
+ irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
+ if (!(readl(P_AO_GPIO_O_EN_N)
+ & (0x01 << 8)) && (readl(P_AO_GPIO_O_EN_N)
+ & (0x01 << 24)) &&
+ !(readl(P_AO_GPIO_I)
+ & (0x01 << 12)))
+ exit_reason = BT_WAKEUP;
+ }
+#endif
+
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/txlx_t962x_r311_v1/firmware/timing.c b/board/amlogic/txlx_t962x_r311_v1/firmware/timing.c
new file mode 100644
index 0000000..c0303df
--- /dev/null
+++ b/board/amlogic/txlx_t962x_r311_v1/firmware/timing.c
@@ -0,0 +1,585 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 20
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_60OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_48OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM//DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_48OHM// DDR4_ODT_80OHM //ddr4 driver use this one
+#define CONFIG_SOC_VREF 1+ (50+((50*48)/(48+480/(6+1)))) // 880/12 //(50+((50*48)/(48+160))) //0//50+50*drv/(drv+odt) (738/12) //0 //0 is auto --70 ---range 44.07---88.04 %
+#define CONFIG_DRAM_VREF 1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0 is auto ---70 --range -- 45---92.50 %
+//#define CONFIG_ZQ_VREF 715/15// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+#define CONFIG_ZQ_VREF 51//60 //700/12// 60//0 //(50) % //tune ddr4 ,ddr3 use 0
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR zqvref 0x13
+ //.t_pub_zq0pr = 0x5aa59, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ //.t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR//0x3f95d, 0x4f95d,
+ //.t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR//0x3f95d, 0x4f95d,
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ .t_pub_zq0pr = 0x00007759, //PUB ZQ0PR, 0x5aa59,0x59959, 0x58859, //99drriver s912 ddr4 maybe 950m is bad
+ .t_pub_zq1pr = 0x0006fc5d, //PUB ZQ1PR//0x8fc5d, 0x4f95d,
+ .t_pub_zq2pr = 0x0006fc5d, //PUB ZQ2PR//0x3fc5d, 0x4f95d,
+ //.t_pub_zq3pr = 0xf5f95d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0x10, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0x10,
+ .t_pub_acbdlr3 = 0x10,//0xa, //cs
+ //.t_pub_acbdlr0 = 0x0,
+ //.t_pub_aclcdlr = 0x10,//0x18, ///1t ,if 2t can add some value
+ //.t_pub_acbdlr3 = 0x14,//0xa, //cs
+ .t_pub_soc_vref_dram_vref =((((CONFIG_SOC_VREF<45)?(0):((((CONFIG_SOC_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_SOC_VREF*1000-44070)/698))))<<8)|(
+ (((CONFIG_DRAM_VREF))<45)?(0):((((CONFIG_DRAM_VREF))<61)?((((((CONFIG_DRAM_VREF*1000-45000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-45000)/650)))|(1<<6))):
+ ((((CONFIG_DRAM_VREF*1000-60000)/650)>0X32)?(0X32):(((CONFIG_DRAM_VREF*1000-60000)/650)))))),
+ .t_pub_mr[7] = ((CONFIG_ZQ_VREF<45)?(0):((((CONFIG_ZQ_VREF*1000-44070)/698)>0X3F)?(0X3F):(((CONFIG_ZQ_VREF*1000-44070)/698)))) ,//jiaxing use for tune zq vref 20160608
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/txlx_t962x_r311_v1/lcd.c b/board/amlogic/txlx_t962x_r311_v1/lcd.c
new file mode 100755
index 0000000..ec14c21
--- /dev/null
+++ b/board/amlogic/txlx_t962x_r311_v1/lcd.c
@@ -0,0 +1,469 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+#include <amlogic/aml_ldim.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_13", /* PANEL_PWR */
+ "GPIOZ_8", /* SCN_EN */
+ "GPIOZ_9", /* LD_EN2 */
+ "GPIOZ_10", /* 2D_3D */
+ "GPIOH_4", /* LR_IN */
+ "GPIOH_5", /* SEL_LVDS */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,50,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_on_step_3d_disable[] = {
+ {LCD_POWER_TYPE_CPU, 0,1,20,}, /* power on */
+ {LCD_POWER_TYPE_CPU, 3,0,10,}, /* 3d_disable */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step_3d_disable[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,30,}, /* signal */
+ {LCD_POWER_TYPE_CPU, 3,2,0,}, /* 3d_disable */
+ {LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOZ_4", /* BL_EN */
+ "GPIOZ_6", /* BL_PWM */
+ "GPIOZ_7", /* Dimming */
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* for HDMI convert*/
+ "lvds_1",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 1,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* 2-region for HDMI convert */
+ "vbyone_2",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 1,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/*BOE: HV550QU2: 3840x2160@60hz 8lane */
+ "vbyone_3",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,1,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step_3d_disable, lcd_power_off_step_3d_disable,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_PWM,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOH_0/1
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{0, 0x009c0800}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_vs_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00008000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00010000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_0_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_1_on_pin", //GPIOZ_7
+ .pinmux_set = {{4, 0x00004000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00002000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_0_vs_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00008000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00010000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_1_vs_on_pin", //GPIOZ_7
+ .pinmux_set = {{4, 0x00002000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00004000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct ldim_pinmux_ctrl_s ldim_pinmux_ctrl[2] = {
+ {
+ .name = "ldim_pwm_vs_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00008000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00010000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_CPU,
+ .index = 0, /* point to cpu_gpio[] struct */
+ .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ .delay = 100, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{0, 0x009c0800}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+};
+
+static unsigned char ldim_ini_data_on[300];
+static unsigned char ldim_ini_data_off[20];
+struct ldim_dev_config_s ldim_config_dft = {
+ .type = LDIM_DEV_TYPE_NORMAL,
+ .cs_hold_delay = 0,
+ .cs_clk_delay = 0,
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+ .lamp_err_gpio = 0xff,
+ .fault_check = 0,
+ .write_check = 0,
+ .dim_min = 0x7f, /* min 3% duty */
+ .dim_max = 0xfff,
+ .cmd_size = 4,
+ .init_on = ldim_ini_data_on,
+ .init_off = ldim_ini_data_off,
+ .pwm_config = {
+ .index = 0,
+ .pwm_method = BL_PWM_POSITIVE,
+ .pwm_port = BL_PWM_MAX,
+ .pwm_duty_max = 100,
+ .pwm_duty_min = 1,
+ },
+ .pinctrl_ver = 1,
+ .ldim_pinmux = ldim_pinmux_ctrl,
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txlx_t962x_r311_v1/pwm_table.c b/board/amlogic/txlx_t962x_r311_v1/pwm_table.c
new file mode 100644
index 0000000..18dc638
--- /dev/null
+++ b/board/amlogic/txlx_t962x_r311_v1/pwm_table.c
@@ -0,0 +1,71 @@
+#include <common.h>
+
+const int pwm_cal_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+const int pwm_cal_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
+int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
+
+
diff --git a/board/amlogic/txlx_t962x_r311_v1/txlx_t962x_r311_v1.c b/board/amlogic/txlx_t962x_r311_v1/txlx_t962x_r311_v1.c
new file mode 100644
index 0000000..31c128a
--- /dev/null
+++ b/board/amlogic/txlx_t962x_r311_v1/txlx_t962x_r311_v1.c
@@ -0,0 +1,486 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/cpu_id.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#include <asm/arch/secure_apb.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm-generic/gpio.h>
+#ifdef CONFIG_AML_SPICC
+#include <dm.h>
+#include <amlogic/spicc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_AML
+
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+#if 0 /* i2c_ao */
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+#endif
+
+ /* i2c_c: GPIOH_2, GPIOH_3 */
+ //disable all other pins which share with I2C_SDA_C & I2C_SCK_C
+ clrbits_le32(P_PERIPHS_PIN_MUX_0, ((1<<22)|(1<<21)|(1<<2)|(1<<1)));
+ //enable I2C MASTER C pins
+ setbits_le32(P_PERIPHS_PIN_MUX_0,
+ (MESON_I2C_MASTER_C_GPIOH_2_BIT |
+ MESON_I2C_MASTER_C_GPIOH_3_BIT));
+
+ udelay(10);
+};
+
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_C,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ },
+ .master_c_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_C_GPIOH_2_REG,
+ .scl_bit = MESON_I2C_MASTER_C_GPIOH_2_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_C_GPIOH_3_REG,
+ .sda_bit = MESON_I2C_MASTER_C_GPIOH_3_BIT,
+ }
+};
+
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+
+#endif
+
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+#ifdef CONFIG_AML_SPICC
+/* generic config in arch gpio/clock.c */
+extern int spicc0_clk_enable(bool enable);
+extern int spicc0_pinctrl_enable(bool enable);
+
+static const struct spicc_platdata spicc0_platdata = {
+ .compatible = "amlogic,meson-txl-spicc",
+ .reg = (void __iomem *)0xffd13000,
+ .clk_rate = 166666666,
+ .clk_enable = spicc0_clk_enable,
+ .pinctrl_enable = spicc0_pinctrl_enable,
+ /* case one slave without cs: {"no_cs", 0} */
+ .cs_gpio_names = {"GPIOZ_3", 0},
+};
+
+U_BOOT_DEVICE(spicc0) = {
+ .name = "spicc",
+ .platdata = &spicc0_platdata,
+};
+#endif /* CONFIG_AML_SPICC */
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_pwm_cal_init(0);
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ writel(readl(P_AO_RTI_PULL_UP_REG)|(1<<12),P_AO_RTI_PULL_UP_REG);
+
+#ifdef CONFIG_SYS_I2C_AML
+ board_i2c_init();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+
+ run_command("ini_model", 0);
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ char loc_name[64] = {0};
+ char *ui_mode = getenv("ui_mode");
+ if (!strcmp(ui_mode, "720p")) {
+ strcpy(loc_name, "txlx_t962x_r311-720p\0");
+ } else {
+ strcpy(loc_name, "txlx_t962x_r311-2g\0");
+ }
+
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+ return 0;
+}
+#endif
+
diff --git a/board/amlogic/txlx_t962x_skt_v1/Kconfig b/board/amlogic/txlx_t962x_skt_v1/Kconfig
new file mode 100644
index 0000000..13697bc
--- /dev/null
+++ b/board/amlogic/txlx_t962x_skt_v1/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_TXLX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "txlx_t962x_skt_v1"
+
+config SYS_VENDOR
+ string
+ default "amlogic"
+
+config SYS_SOC
+ string
+ default "txlx"
+
+config SYS_CONFIG_NAME
+ default "txlx_t962x_skt_v1"
+
+endif
diff --git a/board/amlogic/txlx_t962x_skt_v1/Makefile b/board/amlogic/txlx_t962x_skt_v1/Makefile
new file mode 100644
index 0000000..963e9c5
--- /dev/null
+++ b/board/amlogic/txlx_t962x_skt_v1/Makefile
@@ -0,0 +1,4 @@
+
+obj-y += $(BOARD).o eth_setup.o
+obj-$(CONFIG_AML_LCD) += lcd.o
+obj-y += pwm_table.o
diff --git a/board/amlogic/txlx_t962x_skt_v1/aml-user-key.sig b/board/amlogic/txlx_t962x_skt_v1/aml-user-key.sig
new file mode 100644
index 0000000..2ceabc1
--- /dev/null
+++ b/board/amlogic/txlx_t962x_skt_v1/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/txlx_t962x_skt_v1/eth_setup.c b/board/amlogic/txlx_t962x_skt_v1/eth_setup.c
new file mode 100644
index 0000000..882a37d
--- /dev/null
+++ b/board/amlogic/txlx_t962x_skt_v1/eth_setup.c
@@ -0,0 +1,51 @@
+
+/*
+ * board/amlogic/txl_skt_v1/eth_setup.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/eth_setup.h>
+/*
+ *
+ *setup eth device board socket
+ *
+ */
+struct eth_board_socket* eth_board_setup(char *name){
+ struct eth_board_socket* new_board;
+ new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board) return NULL;
+ if (name != NULL) {
+ new_board->name=(char*)malloc(strlen(name));
+ strncpy(new_board->name,name,strlen(name));
+ }else{
+ new_board->name="gxb";
+ }
+
+ new_board->eth_pinmux_setup=NULL ;
+ new_board->eth_clock_configure=NULL;
+ new_board->eth_hw_reset=NULL;
+ return new_board;
+}
+//pinmux HHI_GCLK_MPEG1[bit 3]
+//
diff --git a/board/amlogic/txlx_t962x_skt_v1/firmware/board_init.c b/board/amlogic/txlx_t962x_skt_v1/firmware/board_init.c
new file mode 100644
index 0000000..2771433
--- /dev/null
+++ b/board/amlogic/txlx_t962x_skt_v1/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/amlogic/txlx_t962x_skt_v1/firmware/power.c b/board/amlogic/txlx_t962x_skt_v1/firmware/power.c
new file mode 100644
index 0000000..ba4fc6f
--- /dev/null
+++ b/board/amlogic/txlx_t962x_skt_v1/firmware/power.c
@@ -0,0 +1,256 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+#define AO_PIN_MUX_REG (*((volatile unsigned *)(0xff800000 + (0x05 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_ao_b,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ */
+
+ switch (id) {
+ case pwm_a:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~((1 << 21) | 1 << 12);
+ P_PIN_MUX_REG3 = reg;
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(1 << 16);
+ P_PIN_MUX_REG10 = reg;//clear reg10
+
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26);
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+ break;
+
+ case pwm_ao_b:
+ reg = readl(AO_PWM_MISC_REG_AB);
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ writel(reg, AO_PWM_MISC_REG_AB);
+ /*
+ * default set to max voltage
+ */
+ //writel( pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0],AO_PWM_PWM_B);
+ reg = AO_PIN_MUX_REG;
+ reg |= (1 << 3);
+ AO_PIN_MUX_REG = reg;
+
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+/*
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_a:
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ writel(pwm_voltage_table[to][0], AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+*/
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ switch (id) {
+ case pwm_a:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ unsigned int reg;
+
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ pwm_init(pwm_a);
+ pwm_init(pwm_ao_b);
+ serial_puts("set vddee enable AO 2/10 to high\n ");
+ reg = readl(AO_GPIO_O_EN_N);
+ reg &= ~((1 << 2)|(1 << 10));
+ reg |= ((1 << 18)|(1 << 26));
+ writel(reg, AO_GPIO_O_EN_N);
+ serial_puts("set test_n to high\n ");
+ reg = readl(AO_SEC_REG0);
+ reg |= (1 << 0);
+ writel(reg, AO_SEC_REG0);
+ reg = readl(AO_GPIO_O_EN_N);
+ reg |= (1 << 31);
+ writel(reg, AO_GPIO_O_EN_N);
+}
diff --git a/board/amlogic/txlx_t962x_skt_v1/firmware/scp_task/dvfs_board.c b/board/amlogic/txlx_t962x_skt_v1/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..ee50598
--- /dev/null
+++ b/board/amlogic/txlx_t962x_skt_v1/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,194 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/dvfs_board.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+/*
+int pwm_voltage_table[ ][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+*/
+#include "pwm_ctrl.h"
+
+#define CHIP_ADJUST 20
+#define RIPPLE_ADJUST 30
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
+ DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
+};
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+
+enum pwm_id {
+ pwm_a = 0,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 8);
+ reg |= ((1 << 15) | (1 << 0));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG3;
+ reg &= ~((1 << 21) | 1 << 12);
+ P_PIN_MUX_REG3 = reg;
+
+ reg = P_PIN_MUX_REG10;
+ reg &= ~(1 << 16);
+ P_PIN_MUX_REG10 = reg;//clear reg10
+ reg = P_PIN_MUX_REG4;
+ reg &= ~(1 << 26); // clear PWM_VS
+ reg |= (1 << 17); // enable PWM_A
+ P_PIN_MUX_REG4 = reg;
+
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_A;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_a);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_A = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+void get_dvfs_info_board(unsigned int domain,
+ unsigned char *info_out, unsigned int *size_out)
+{
+ unsigned int cnt;
+ cnt = ARRAY_SIZE(cpu_dvfs_tbl);
+
+ buf_opp.latency = 200;
+ buf_opp.count = cnt;
+ memset(&buf_opp.opp[0], 0,
+ MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
+
+ memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
+ cnt * sizeof(struct scpi_opp_entry));
+
+ memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
+ *size_out = sizeof(struct scpi_opp);
+ return;
+}
diff --git a/board/amlogic/txlx_t962x_skt_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/txlx_t962x_skt_v1/firmware/scp_task/pwm_ctrl.h
new file mode 100644
index 0000000..7b67562
--- /dev/null
+++ b/board/amlogic/txlx_t962x_skt_v1/firmware/scp_task/pwm_ctrl.h
@@ -0,0 +1,37 @@
+/*
+*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
+*table for Dynamic Voltage/Frequency Scaling
+*/
+
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
diff --git a/board/amlogic/txlx_t962x_skt_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/txlx_t962x_skt_v1/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..a647727
--- /dev/null
+++ b/board/amlogic/txlx_t962x_skt_v1/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,368 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+#include <gpio-gxbb.h>
+#include "pwm_ctrl.h"
+
+#define P_AO_PWM_PWM_B1 (*((volatile unsigned *)(0xff807000 + (0x01 << 2))))
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
+
+#define ON 1
+#define OFF 0
+
+static int pwm_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static void power_on_ddr(void);
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+ pwm_ao_a,
+ pwm_ao_b,
+};
+
+#if 0
+static void power_switch_to_ee(unsigned int pwr_ctrl)
+{
+ if (pwr_ctrl == ON) {
+ writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
+ _udelay(1000);
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ & (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
+ } else {
+ writel(readl(AO_RTI_PWR_CNTL_REG0)
+ | ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
+
+ writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
+ AO_RTI_PWR_CNTL_REG0);
+
+ }
+}
+#endif
+
+static void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ switch (id) {
+ case pwm_a:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ uart_puts("set vcck to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_PWM_PWM_A = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_ao_b:
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ }
+ uart_puts("set vddee to 0x");
+ uart_put_hex(to, 16);
+ uart_puts("mv\n");
+ P_AO_PWM_PWM_B1 = pwm_voltage_table_ee[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 0);
+}
+
+static void power_on_3v3_5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 18, 1 << 18);
+}
+
+static void power_off_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 0);
+}
+
+static void power_on_usb5v(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 10, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 26, 1 << 26);
+}
+
+static void power_off_at_clk81(void)
+{
+
+}
+
+static void power_on_at_clk81(unsigned int suspend_from)
+{
+
+}
+
+static void power_off_at_24M(void)
+{
+}
+static void power_on_at_24M(void)
+{
+}
+
+static void power_off_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 0);
+}
+
+static void power_on_ddr(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
+ _udelay(10000);
+}
+
+/*timing request:
+ *poweroff vddio3.3v-->delay 20ms-->poweroff vddee
+ */
+static void power_off_vddee(void)
+{
+ unsigned int val;
+
+ /*set test n output low level */
+ _udelay(10000);/*the other 10ms in power_off_at_32k()*/
+ val = readl(AO_GPIO_O_EN_N);
+ val &= ~(0x1 << 31);
+ writel(val, AO_GPIO_O_EN_N);
+
+}
+
+/*timing request:
+ *poweron vddee-->delay 20ms-->poweron vddio3.3v
+ */
+static void power_on_vddee(void)
+{
+ unsigned int val;
+
+ /*set test n output high level */
+ val = readl(AO_GPIO_O_EN_N);
+ val |= 0x1 << 31;
+ writel(val, AO_GPIO_O_EN_N);
+ _udelay(10000);/*the other 10ms in power_on_at_32k()*/
+}
+
+static void power_off_at_32k(unsigned int suspend_from)
+{
+ power_off_usb5v();
+ _udelay(5000);
+ power_off_3v3_5v();
+ _udelay(5000);
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
+ if (suspend_from == SYS_POWEROFF) {
+ power_off_vddee();
+ power_off_ddr();
+ }
+}
+
+static void power_on_at_32k(unsigned int suspend_from)
+{
+ if (suspend_from == SYS_POWEROFF)
+ power_on_vddee();
+ pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
+ _udelay(10000);
+ power_on_3v3_5v();
+ _udelay(10000);
+ pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
+ _udelay(10000);
+ _udelay(10000);
+ power_on_usb5v();
+
+ if (suspend_from == SYS_POWEROFF)
+ power_on_ddr();
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
+ ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC);
+#ifdef CONFIG_CEC_WAKEUP
+ val |= CECB_WAKEUP_SRC;
+#endif
+ p->sources = val;
+ p->gpio_info_count = 0;
+}
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ /*10ms generate an interrupt*/
+ writel(9, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned char adc_key_cnt = 0;
+ unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+ init_remote();
+ saradc_enable();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+#ifdef CONFIG_CEC_WAKEUP
+ if (irq[IRQ_AO_CECB] == IRQ_AO_CECB_NUM) {
+ irq[IRQ_AO_CECB] = 0xFFFFFFFF;
+// if (suspend_from == SYS_POWEROFF)
+// continue;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ }
+#endif
+ if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
+ irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
+ if (check_adc_key_resume()) {
+ adc_key_cnt++;
+ /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
+ if (2 == adc_key_cnt)
+ exit_reason = POWER_KEY_WAKEUP;
+ } else {
+ adc_key_cnt = 0;
+ }
+ }
+ if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
+ irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ }
+ if (irq[IRQ_ETH_PHY] == IRQ_ETH_PHY_NUM) {
+ irq[IRQ_ETH_PHY] = 0xFFFFFFFF;
+ exit_reason = ETH_PHY_WAKEUP;
+ }
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ saradc_disable();
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/amlogic/txlx_t962x_skt_v1/firmware/timing.c b/board/amlogic/txlx_t962x_skt_v1/firmware/timing.c
new file mode 100644
index 0000000..cf5493e
--- /dev/null
+++ b/board/amlogic/txlx_t962x_skt_v1/firmware/timing.c
@@ -0,0 +1,569 @@
+
+/*
+ * board/amlogic/txl_skt_v1/firmware/timing.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+/* lpddr2 drv odt */
+#define LPDDR2_DRV_34OHM 1
+#define LPDDR2_DRV_40OHM 2
+#define LPDDR2_DRV_48OHM 3
+#define LPDDR2_DRV_60OHM 4
+#define LPDDR2_DRV_80OHM 6
+#define LPDDR2_DRV_120OHM 7
+#define LPDDR2_ODT_0OHM 0
+
+/* lpddr3 drv odt */
+#define LPDDR3_DRV_34OHM 1
+#define LPDDR3_DRV_40OHM 2
+#define LPDDR3_DRV_48OHM 3
+#define LPDDR3_DRV_60OHM 4
+#define LPDDR3_DRV_80OHM 6
+#define LPDDR3_DRV_34_40OHM 9
+#define LPDDR3_DRV_40_48OHM 10
+#define LPDDR3_DRV_34_48OHM 11
+#define LPDDR3_ODT_0OHM 0
+#define LPDDR3_ODT_60OHM 1
+#define LPDDR3_ODT_12OHM 2
+#define LPDDR3_ODT_240HM 3
+
+#define DDR4_DRV_34OHM 0
+#define DDR4_DRV_48OHM 1
+#define DDR4_ODT_0OHM 0
+#define DDR4_ODT_60OHM 1
+#define DDR4_ODT_120OHM 2
+#define DDR4_ODT_40OHM 3
+#define DDR4_ODT_240OHM 4
+#define DDR4_ODT_48OHM 5
+#define DDR4_ODT_80OHM 6
+#define DDR4_ODT_34OHM 7
+
+#if ((CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) || (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO))
+#define CFG_DDR_DRV DDR3_DRV_34OHM
+#define CFG_DDR_ODT DDR3_ODT_60OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define CFG_DDR_DRV LPDDR2_DRV_48OHM
+#define CFG_DDR_ODT DDR3_ODT_120OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define CFG_DDR_DRV LPDDR3_DRV_48OHM
+#define CFG_DDR_ODT LPDDR3_ODT_12OHM
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+#define CFG_DDR_DRV DDR4_DRV_34OHM //useless, no effect
+#define CFG_DDR_ODT DDR4_ODT_60OHM //useless, no effect
+#endif
+
+#define CFG_DDR4_DRV DDR4_DRV_48OHM //ddr4 driver use this one
+#define CFG_DDR4_ODT DDR4_ODT_60OHM //ddr4 driver use this one
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ /* ddr4 1600 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_1600,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = (28),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (13), //15NS+1CLK
+ .cfg_ddr_cwl = (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (5),
+ },
+ /* ddr4 2400 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR4_2400,
+ .cfg_ddr_rtp = 9,//(4),
+ .cfg_ddr_wtr = 9,//(6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (8),
+ .cfg_ddr_rc =50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ },
+ /* lpddr3 timing */
+ {
+ .identifier = CONFIG_DDR_TIMMING_LPDDR3,
+ .cfg_ddr_rtp = (4),
+ .cfg_ddr_wtr = (6),
+ .cfg_ddr_rp = 15*1.2,//(11),
+ .cfg_ddr_rcd = 15*1.2,//(11),
+ .cfg_ddr_ras = 35*1.2,//(35),
+ .cfg_ddr_rrd = (4),
+ .cfg_ddr_rc = 50*1.2,// (46),//RAS+RP
+ .cfg_ddr_mrd = (8),
+ .cfg_ddr_mod = (24),
+ .cfg_ddr_faw = 35*1.2,//(28),
+ .cfg_ddr_rfc = 350*1.2,//(280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = 9.5*1.2,//(8),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (1024), //597 768 1024
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = 15*1.2,// (11),
+ .cfg_ddr_wr = 15*1.2,// (13), //15NS+1CLK
+ .cfg_ddr_cwl = 12,// (11),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (1024), //597 768 1024
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = 128,
+ .cfg_ddr_zqcl = (256),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ .cfg_ddr_tccdl = (6),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr4_clk = CONFIG_DDR4_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+#if (0 == CONFIG_DDR_SIZE)
+ .ddr_size_detect = 1,
+#else
+ .ddr_size_detect = 0,
+#endif
+ .ddr_drv = CFG_DDR_DRV,
+ .ddr_odt = CFG_DDR_ODT,
+ .ddr4_drv = CFG_DDR4_DRV,
+ .ddr4_odt = CFG_DDR4_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00030000,
+ .t_pub_mr = {
+ (0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
+ (0X6|(1<<6)),
+ 0X20,
+ 0,
+ },
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x02004620, //PUB PGCR1
+ .t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ //.t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aae860, //PUB PGCR3
+ .t_pub_dxccr = 0x20c01ee4, //PUB DXCCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
+ .t_pub_dcr = 0X40C, //PUB DCR
+ .t_pub_dtcr0 = 0x800031c7, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x020641b|(1<<2)|(1<<23),
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+ .t_pub_dcr = 0X89, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237,
+ .t_pub_dsgcr = 0x02064db,
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_AUTO)
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtcr0 = 0x80003187, //PUB DTCR //S905 use 0x800031c7
+ .t_pub_dtcr1 = 0x00010237, //PUB DTCR
+ .t_pub_dsgcr = 0x020641b,
+#endif
+ .t_pub_vtcr1 = 0x0fc00172,
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x59959, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x3f95d, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x3f95d, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x1dd1d, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F01, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = 0, //[B10,B9,B8] tfaw_cfg_offset
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ .t_pctl0_ppcfg = 0,
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 2,
+ .t_pctl0_dfitphywrlta = 7,
+ .t_pctl0_dfitrddataen = 8,
+ .t_pctl0_dfitphyrdlat = 22,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype0 = 16,
+ .t_pctl0_dfitphyupdtype1 = 16,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_dfitctrlupdmax = 64,
+ .t_pctl0_dfiupdcfg = 0x3,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (13 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+ .t_pub_acbdlr0 = 0, //CK0 delay fine tune
+ .t_pub_aclcdlr = 0x10,
+ .ddr_func = DDR_FUNC, /* ddr func demo 2016.01.26 */
+
+ .wr_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,
+ },
+ .rd_adj_per = {
+ [0] = 100,
+ [1] = 100,
+ [2] = 100,
+ [3] = 100,
+ [4] = 100,
+ [5] = 100,},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+#ifdef CONFIG_DEBUG_MODE
+ .debug_mode = CONFIG_DEBUG_MODE,
+ .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
+ .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
+#endif
+};
diff --git a/board/amlogic/txlx_t962x_skt_v1/lcd.c b/board/amlogic/txlx_t962x_skt_v1/lcd.c
new file mode 100755
index 0000000..e09cba8
--- /dev/null
+++ b/board/amlogic/txlx_t962x_skt_v1/lcd.c
@@ -0,0 +1,358 @@
+/*
+ * AMLOGIC LCD panel driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the named License,
+ * or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <amlogic/aml_lcd.h>
+#include <asm/arch/gpio.h>
+
+//Rsv_val = 0xffffffff
+
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ //"GPIOX_3",
+ //"GPIOX_2",
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd_power_on_step[] = {
+ //{LCD_POWER_TYPE_CPU, 0,1,50,}, /* power on */
+ {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+static struct lcd_power_step_s lcd_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
+ //{LCD_POWER_TYPE_CPU, 0,0,100,}, /* power off */
+ {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
+};
+
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ //"GPIOAO_4",
+ //"GPIOY_13",
+ "invalid", /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0",LCD_LVDS,8,
+ /* basic timing */
+ 1920,1080,2200,1125,44,148,0,5,36,0,
+ /* clk_attr */
+ 0,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* lvds_attr */
+ 1,1,0,0,0,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0xff,1,0,0,0,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,2,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {/* public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1",LCD_VBYONE,10,
+ /* basic timing */
+ 3840,2160,4400,2250,33,477,0,6,81,0,
+ /* clk_attr */
+ 2,0,1,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* vbyone_attr */
+ 8,1,4,4,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ /* power step */
+ lcd_power_on_step, lcd_power_off_step,
+ /* backlight */
+ 60,255,10,128,128,
+ BL_CTRL_MAX,0,1,0,200,200,
+ BL_PWM_POSITIVE,BL_PWM_B,180,100,25,1,0,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ Rsv_val,Rsv_val,Rsv_val,Rsv_val,
+ 10,10,Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOH_0/1
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{0, 0x009c0800}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_vs_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00008000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00010000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_0_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_1_on_pin", //GPIOZ_7
+ .pinmux_set = {{4, 0x00004000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00002000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_0_vs_on_pin", //GPIOZ_6
+ .pinmux_set = {{4, 0x00008000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00010000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "bl_pwm_combo_1_vs_on_pin", //GPIOZ_7
+ .pinmux_set = {{4, 0x00002000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00004000}, {3, 0x00200000}, {10, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+//**** Special parameters just for Vbyone ***//
+static struct vbyone_config_s lcd_vbyone_config = {
+ .lane_count = 8,
+ .byte_mode = 4,
+ .region_num = 2,
+ .color_fmt = 4,
+};
+
+//**** Special parameters just for lvds ***//
+static struct lvds_config_s lcd_lvds_config = {
+ .lvds_repack = 1, //0=JEDIA mode, 1=VESA mode
+ .dual_port = 1, //0=single port, 1=double port
+ .pn_swap = 0, //0=normal, 1=swap
+ .port_swap = 0, //0=normal, 1=swap
+ .lane_reverse = 0, //0=normal, 1=swap
+};
+
+static struct lcd_power_ctrl_s lcd_power_ctrl = {
+ .power_on_step = {
+ // {
+ // .type = LCD_POWER_TYPE_CPU,
+ // .index = 0, /* point to cpu_gpio[] struct */
+ // .value = 1, /* 0=output_low, 1=output_high, 2=input */
+ // .delay = 50, /* unit: ms */
+ // },
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 0, /* unit: ms */
+ },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+ .power_off_step = {
+ {
+ .type = LCD_POWER_TYPE_SIGNAL,
+ .delay = 50, /* unit: ms */
+ },
+ // {
+ // .type = LCD_POWER_TYPE_CPU,
+ // .index = 0, /* point to cpu_gpio[] struct */
+ // .value = 0, /* 0=output_low, 1=output_high, 2=input */
+ // .delay = 100, /* unit: ms */
+ // },
+ {
+ .type = LCD_POWER_TYPE_MAX, /* ending flag */
+ },
+ },
+};
+
+struct lcd_config_s lcd_config_dft = {
+ .lcd_mode = LCD_MODE_TV,
+ .lcd_key_valid = 0,
+ .lcd_basic = {
+ .model_name = "default",
+ .lcd_type = LCD_TYPE_MAX, //LCD_TTL /LCD_LVDS/LCD_VBYONE
+ .lcd_bits = 8,
+ .h_active = 1920,
+ .v_active = 1080,
+ .h_period = 2200,
+ .v_period = 1125,
+
+ .screen_width = 16,
+ .screen_height = 9,
+ },
+
+ .lcd_timing = {
+ .clk_auto = 1,
+ .lcd_clk = 60,
+ .ss_level = 0,
+ .fr_adjust_type = 0,
+
+ .hsync_width = 44,
+ .hsync_bp = 148,
+ .hsync_pol = 0,
+ .vsync_width = 5,
+ .vsync_bp = 36,
+ .vsync_pol = 0,
+ },
+
+ .lcd_control = {
+ .lvds_config = &lcd_lvds_config,
+ .vbyone_config = &lcd_vbyone_config,
+ },
+ .lcd_power = &lcd_power_ctrl,
+
+ .pinctrl_ver = 2,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+ .pinmux_set = {{0, 0xc0000000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{0, 0x009c0800}, {LCD_PINMUX_END, 0x0}},
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0x00, 0x20, 0x01, 0x02, 0x00, 0x40, 0xFF, 0x00, 0x00,
+ 0x00, 0x80, 0x02, 0x00, 0x40, 0x62, 0x51, 0x73, 0x00,
+ 0x00, 0x61, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xC1, 0x05, 0x0F, 0x00, 0x08, 0x70, 0x00, 0x00,
+ 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x3D, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0xED, 0x0D, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x23, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, /* delay 10ms */
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
+};
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "ext_default",
+ .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .status = 1, /* 0=disable, 1=enable */
+ .i2c_addr = 0x1c, /* 7bit i2c address */
+ .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for none */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_C, /* LCD_EXTERN_I2C_BUS_AO, LCD_EXTERN_I2C_BUS_A/B/C/D */
+ .spi_gpio_cs = 0,
+ .spi_gpio_clk = 1,
+ .spi_gpio_data = 2,
+ .spi_clk_freq = 0, /* hz */
+ .spi_clk_pol = 0,
+ .cmd_size = 9,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+struct bl_config_s bl_config_dft = {
+ .name = "default",
+ .bl_key_valid = 0,
+
+ .level_default = 100,
+ .level_min = 10,
+ .level_max = 255,
+ .level_mid = 128,
+ .level_mid_mapping = 128,
+ .level = 0,
+
+ .method = BL_CTRL_MAX,
+ .power_on_delay = 200,
+ .power_off_delay = 200,
+
+ .en_gpio = 0xff,
+ .en_gpio_on = 1,
+ .en_gpio_off = 0,
+
+ .bl_pwm = NULL,
+ .bl_pwm_combo0 = NULL,
+ .bl_pwm_combo1 = NULL,
+ .pwm_on_delay = 10,
+ .pwm_off_delay = 10,
+
+ .pinctrl_ver = 2,
+ .bl_pinmux = bl_pinmux_ctrl,
+ .pinmux_set = {{4, 0x00010000}, {LCD_PINMUX_END, 0x0}},
+ .pinmux_clr = {{4, 0x00008000}, {3, 0x00200000}, {LCD_PINMUX_END, 0x0}},
+};
+
+void lcd_config_bsp_init(void)
+{
+ int i, j;
+
+ for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
+ break;
+ strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
+ }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
+ for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bl_config_dft.gpio_name[j], "invalid");
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ for (i = 0; i < LCD_EXTERN_NUM_MAX; i++) {
+ if (ext_config_dtf[i].index == LCD_EXTERN_INDEX_INVALID)
+ break;
+ }
+ ext_common_dft.lcd_ext_num = i;
+
+ for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
+ if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
+ break;
+ strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
+ }
+ for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
+ strcpy(ext_common_dft.gpio_name[j], "invalid");
+
+#endif
+}
diff --git a/board/amlogic/txlx_t962x_skt_v1/pwm_table.c b/board/amlogic/txlx_t962x_skt_v1/pwm_table.c
new file mode 100644
index 0000000..18dc638
--- /dev/null
+++ b/board/amlogic/txlx_t962x_skt_v1/pwm_table.c
@@ -0,0 +1,71 @@
+#include <common.h>
+
+const int pwm_cal_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+const int pwm_cal_voltage_table_ee[][2] = {
+ { 0x1c0000, 810},
+ { 0x1b0001, 820},
+ { 0x1a0002, 830},
+ { 0x190003, 840},
+ { 0x180004, 850},
+ { 0x170005, 860},
+ { 0x160006, 870},
+ { 0x150007, 880},
+ { 0x140008, 890},
+ { 0x130009, 900},
+ { 0x12000a, 910},
+ { 0x11000b, 920},
+ { 0x10000c, 930},
+ { 0x0f000d, 940},
+ { 0x0e000e, 950},
+ { 0x0d000f, 960},
+ { 0x0c0010, 970},
+ { 0x0b0011, 980},
+ { 0x0a0012, 990},
+ { 0x090013, 1000},
+ { 0x080014, 1010},
+ { 0x070015, 1020},
+ { 0x060016, 1030},
+ { 0x050017, 1040},
+ { 0x040018, 1050},
+ { 0x030019, 1060},
+ { 0x02001a, 1070},
+ { 0x01001b, 1080},
+ { 0x00001c, 1090}
+};
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
+int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
+
+
diff --git a/board/amlogic/txlx_t962x_skt_v1/txlx_t962x_skt_v1.c b/board/amlogic/txlx_t962x_skt_v1/txlx_t962x_skt_v1.c
new file mode 100644
index 0000000..456847a
--- /dev/null
+++ b/board/amlogic/txlx_t962x_skt_v1/txlx_t962x_skt_v1.c
@@ -0,0 +1,456 @@
+
+/*
+ * board/amlogic/txl_skt_v1/txl_skt_v1.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/secure_apb.h>
+#ifdef CONFIG_SYS_I2C_AML
+#include <aml_i2c.h>
+#endif
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+#include <vpp.h>
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+#include <amlogic/aml_v2_burning.h>
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/aml_lcd.h>
+#endif
+#include <asm/arch/eth_setup.h>
+#include <phy.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <amlogic/spifc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//new static eth setup
+struct eth_board_socket* eth_board_skt;
+
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+void internalPhyConfig(struct phy_device *phydev)
+{
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ /*Write Analog register 23*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
+ /*Enable fractional PLL*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
+ //Programme fraction FR_PLL_DIV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
+ //## programme fraction FR_PLL_DiV1
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
+}
+
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t eth_reg0;
+
+ eth_reg0.d32 = 0;
+ eth_reg0.b.phy_intf_sel = 4;
+ eth_reg0.b.rx_clk_rmii_invert = 0;
+ eth_reg0.b.rgmii_tx_clk_src = 0;
+ eth_reg0.b.rgmii_tx_clk_phase = 0;
+ eth_reg0.b.rgmii_tx_clk_ratio = 0;
+ eth_reg0.b.phy_ref_clk_enable = 0;
+ eth_reg0.b.clk_rmii_i_invert = 1;
+ eth_reg0.b.clk_en = 1;
+ eth_reg0.b.adj_enable = 0;
+ eth_reg0.b.adj_setup = 0;
+ eth_reg0.b.adj_delay = 0;
+ eth_reg0.b.adj_skew = 0;
+ eth_reg0.b.cali_start = 0;
+ eth_reg0.b.cali_rise = 0;
+ eth_reg0.b.cali_sel = 0;
+ eth_reg0.b.rgmii_rx_reuse = 0;
+ eth_reg0.b.eth_urgent = 0;
+ setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
+ *P_PREG_ETH_REG2 = 0x10110181;
+ *P_PREG_ETH_REG3 = 0xe409087f;
+ setbits_le32(HHI_GCLK_MPEG1,1<<3);
+ /* power on memory */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+}
+
+extern struct eth_board_socket* eth_board_setup(char *name);
+extern int designware_initialize(ulong base_addr, u32 interface);
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+// #define CONFIG_TSD 1
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ board_mmc_register(SDIO_PORT_B);
+ board_mmc_register(SDIO_PORT_C);
+// board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_AML
+#if 0
+static void board_i2c_set_pinmux(void){
+ /*********************************************/
+ /* | I2C_Master_AO |I2C_Slave | */
+ /*********************************************/
+ /* | I2C_SCK | I2C_SCK_SLAVE | */
+ /* GPIOAO_4 | [AO_PIN_MUX: 6] | [AO_PIN_MUX: 2] | */
+ /*********************************************/
+ /* | I2C_SDA | I2C_SDA_SLAVE | */
+ /* GPIOAO_5 | [AO_PIN_MUX: 5] | [AO_PIN_MUX: 1] | */
+ /*********************************************/
+
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG, ((1<<2)|(1<<24)|(1<<1)|(1<<23)));
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+};
+#endif
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+#if 0
+static void board_i2c_init(void)
+{
+ //set I2C pinmux with PCB board layout
+ board_i2c_set_pinmux();
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+#endif
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void){
+ /*add board early init function here*/
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+#include <asm/arch/usb-new.h>
+#include <asm/arch/gpio.h>
+#define CONFIG_GXL_USB_U2_PORT_NUM 4
+#define CONFIG_GXL_USB_U3_PORT_NUM 0
+
+struct amlogic_usb_config g_usb_config_GXL_skt={
+ CONFIG_GXL_XHCI_BASE,
+ USB_ID_MODE_HARDWARE,
+ NULL,//gpio_set_vbus_power, //set_vbus_power
+ CONFIG_GXL_USB_PHY2_BASE,
+ CONFIG_GXL_USB_PHY3_BASE,
+ CONFIG_GXL_USB_U2_PORT_NUM,
+ CONFIG_GXL_USB_U3_PORT_NUM,
+};
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmi_tx_set_hdmi_5v(void)
+{
+}
+#endif
+
+#ifdef CONFIG_AML_SPIFC
+/*
+ * BOOT_4: NOR_D:reg7[13], clr reg7[31] reg7[22]
+ * BOOT_5: NOR_Q:reg7[12], clr reg7[31] reg7[21]
+ * BOOT_6: NOR_C:reg7[11], clr reg7[31] reg7[20]
+ * BOOT_11: NOR_CS:reg7[10],clr reg7[28]
+ */
+#define SPIFC_NUM_CS 1
+static int spifc_cs_gpios[SPIFC_NUM_CS] = {49/*BOOT_11*/};
+
+static int spifc_pinctrl_enable(void *pinctrl, bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_7);
+ val &= ~((1<<13)|(1<<12)|(1<<11)|(1<<10));
+ if (enable) {
+ val |= (1<<13)|(1<<12)|(1<<11);
+ val &= ~((1<<31)|(1<<28)|(1<<22)|(1<<21)|(1<<20));
+ }
+ writel(val, P_PERIPHS_PIN_MUX_7);
+ return 0;
+}
+
+static const struct spifc_platdata spifc_platdata = {
+ .reg = 0xffd14000,
+ .mem_map = 0xfb000000,
+ .pinctrl_enable = spifc_pinctrl_enable,
+ .num_chipselect = SPIFC_NUM_CS,
+ .cs_gpios = spifc_cs_gpios,
+};
+
+U_BOOT_DEVICE(spifc) = {
+ .name = "spifc",
+ .platdata = &spifc_platdata,
+};
+#endif /* CONFIG_AML_SPIFC */
+
+extern void aml_pwm_cal_init(int mode);
+
+int board_init(void)
+{
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_try_factory_usb_burning(0, gd->bd);
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+ aml_pwm_cal_init(0);
+#ifdef CONFIG_USB_XHCI_AMLOGIC_GXL
+ board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
+#endif /*CONFIG_USB_XHCI_AMLOGIC*/
+
+#ifdef CONFIG_AML_NAND
+ extern int amlnf_init(unsigned char flag);
+ amlnf_init(0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void){
+ //update env before anyone using it
+ run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
+ run_command("if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ /*add board late init function here*/
+ int ret;
+ ret = run_command("store dtb read $dtb_mem_addr", 1);
+ if (ret) {
+ printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
+ #ifdef CONFIG_DTB_MEM_ADDR
+ char cmd[64];
+ printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
+ sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
+ ret = run_command(cmd, 1);
+ if (ret) {
+ printf("%s(): %s fail\n", __func__, cmd);
+ }
+ #endif
+ }
+
+ /* load unifykey */
+ run_command("keyunify init 0x1234", 0);
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+ vpp_init();
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_set_hdmi_5v();
+ hdmi_tx_init();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+#ifdef CONFIG_AML_V2_FACTORY_BURN
+ /*aml_try_factory_sdcard_burning(0, gd->bd);*/
+#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AML_TINY_USBTOOL
+int usb_get_update_result(void)
+{
+ unsigned long upgrade_step;
+ upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
+ printf("upgrade_step = %d\n", (int)upgrade_step);
+ if (upgrade_step == 1)
+ {
+ run_command("defenv", 1);
+ run_command("setenv upgrade_step 2", 1);
+ run_command("saveenv", 1);
+ return 0;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
+#endif
+}
diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig
new file mode 100644
index 0000000..b8e380e
--- /dev/null
+++ b/board/aristainetos/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ARISTAINETOS
+
+config SYS_BOARD
+ default "aristainetos"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "aristainetos"
+
+endif
diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS
new file mode 100644
index 0000000..d45d423
--- /dev/null
+++ b/board/aristainetos/MAINTAINERS
@@ -0,0 +1,6 @@
+ARISTAINETOS BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: board/aristainetos/
+F: include/configs/aristainetos.h
+F: configs/aristainetos_defconfig
diff --git a/board/aristainetos/Makefile b/board/aristainetos/Makefile
new file mode 100644
index 0000000..5de48bc
--- /dev/null
+++ b/board/aristainetos/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := aristainetos.o
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
new file mode 100644
index 0000000..67ac260
--- /dev/null
+++ b/board/aristainetos/aristainetos.c
@@ -0,0 +1,525 @@
+/*
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <pwm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define DISP_PAD_CTRL (0x10)
+
+#define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
+
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+struct i2c_pads_info i2c_pad_info3 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+ .gp = IMX_GPIO_NR(3, 17)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart5_pads[] = {
+ MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const gpio_pads[] = {
+ /* LED enable */
+ MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* spi flash WP protect */
+ MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* backlight enable */
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED yellow */
+ MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED red */
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED green */
+ MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED blue */
+ MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* i2c4 scl */
+ MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* i2c4 sda */
+ MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* spi CS 1 */
+ MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const misc_pads[] = {
+ MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG Power enable */
+ MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8),
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* set GPIO_16 as ENET_REF_CLK_OUT */
+ setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+}
+
+iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const ecspi4_pads[] = {
+ MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const display_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
+ MX6_PAD_DI0_PIN4__GPIO4_IO20,
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
+};
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+ MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
+ ? (IMX_GPIO_NR(3, 20)) : -1;
+}
+
+static void setup_spi(void)
+{
+ int i;
+
+ imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
+ for (i = 0; i < 3; i++)
+ enable_spi_clk(true, i);
+
+ /* set cs1 to high */
+ gpio_direction_output(ECSPI4_CS1, 1);
+}
+
+static void setup_iomux_gpio(void)
+{
+ imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+}
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC1_BASE_ADDR},
+ {USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
+ fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+}
+#endif
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct iomuxc *iomuxc_regs =
+ (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ setup_iomux_enet();
+ /* clear gpr1[14], gpr1[18:17] to select anatop clock */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
+
+ ret = enable_fec_anatop_clock(ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ return cpu_eth_init(bis);
+}
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(
+ display_pads,
+ ARRAY_SIZE(display_pads));
+ imx_iomux_v3_setup_multiple_pads(
+ backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+
+ /* enable backlight PWM 3 */
+ if (pwm_init(2, 0, 0))
+ goto error;
+ /* duty cycle 200ns, period: 3000ns */
+ if (pwm_config(2, 200, 3000))
+ goto error;
+ if (pwm_enable(2))
+ goto error;
+ return;
+
+error:
+ puts("error init pwm for backlight\n");
+ return;
+}
+
+struct display_info_t const displays[] = {
+ {
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "lb07wv8",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 33246,
+ .left_margin = 88,
+ .right_margin = 88,
+ .upper_margin = 10,
+ .lower_margin = 10,
+ .hsync_len = 25,
+ .vsync_len = 1,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+ }
+};
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+
+ reg = readl(&mxc_ccm->cs2cdr);
+ /* select pll 5 clock */
+ reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
+ reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+}
+
+/* no console on this board */
+int board_cfb_skip(void)
+{
+ return 1;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_gpio();
+
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
+ return 0;
+}
+
+iomux_v3_cfg_t nfc_pads[] = {
+ MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ imx_iomux_v3_setup_multiple_pads(nfc_pads,
+ ARRAY_SIZE(nfc_pads));
+
+ /* config gpmi and bch clock to 100 MHz */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+
+int board_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ setup_spi();
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+ &i2c_pad_info1);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+ &i2c_pad_info2);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+ &i2c_pad_info3);
+
+ /* i2c4 not used, set it to gpio input */
+ gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
+ gpio_direction_input(IMX_GPIO_NR(1, 7));
+ gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
+ gpio_direction_input(IMX_GPIO_NR(1, 8));
+
+ /* SPI NOR Flash read only */
+ gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
+ gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
+ gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
+
+ /* enable LED */
+ gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
+ gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
+
+ gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
+ gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
+ gpio_request(IMX_GPIO_NR(1, 4), "LED red");
+ gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
+ gpio_request(IMX_GPIO_NR(1, 5), "LED green");
+ gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
+ gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
+ gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
+
+ setup_gpmi_nand();
+
+ /* GPIO_1 for USB_OTG_ID */
+ setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK);
+ imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: aristaitenos\n");
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+ int ret;
+
+ ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
+ if (!ret)
+ gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
+ ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
+ if (!ret)
+ gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ if (port)
+ gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
+ else
+ gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
+ return 0;
+}
+#endif
diff --git a/board/aristainetos/aristainetos.cfg b/board/aristainetos/aristainetos.cfg
new file mode 100644
index 0000000..2290180
--- /dev/null
+++ b/board/aristainetos/aristainetos.cfg
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd
+ */
+BOOT_FROM spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "mt41j128M.cfg"
+#include "clocks.cfg"
diff --git a/board/aristainetos/clocks.cfg b/board/aristainetos/clocks.cfg
new file mode 100644
index 0000000..651449e
--- /dev/null
+++ b/board/aristainetos/clocks.cfg
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00c03f3f
+DATA 4, CCM_CCGR1, 0x0030fcff
+DATA 4, CCM_CCGR2, 0x0fffcfc0
+DATA 4, CCM_CCGR3, 0x3ff0300f
+DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */
+DATA 4, CCM_CCGR5, 0x0f0000c3
+DATA 4, CCM_CCGR6, 0x000003ff
diff --git a/board/aristainetos/ddr-setup.cfg b/board/aristainetos/ddr-setup.cfg
new file mode 100644
index 0000000..c72a3ef
--- /dev/null
+++ b/board/aristainetos/ddr-setup.cfg
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* DDR IO TYPE */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* Clock */
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
+/* Address */
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* Control */
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+/* Data Strobe */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
diff --git a/board/aristainetos/mt41j128M.cfg b/board/aristainetos/mt41j128M.cfg
new file mode 100644
index 0000000..3561655
--- /dev/null
+++ b/board/aristainetos/mt41j128M.cfg
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/* ZQ Calibration */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
+/*
+ * DQS gating, read delay, write delay calibration values
+ * based on calibration compare of 0x00ffff00
+ */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E
+/* read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+/* Complete calibration by forced measurment */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
+/* MR2 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a
+/* MR3 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
+/* MR1 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
+/* MR0 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
+/* final ddr setup */
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
+DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/board/armadeus/apf27/Kconfig b/board/armadeus/apf27/Kconfig
new file mode 100644
index 0000000..65544a8
--- /dev/null
+++ b/board/armadeus/apf27/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_APF27
+
+config SYS_BOARD
+ default "apf27"
+
+config SYS_VENDOR
+ default "armadeus"
+
+config SYS_SOC
+ default "mx27"
+
+config SYS_CONFIG_NAME
+ default "apf27"
+
+endif
diff --git a/board/armadeus/apf27/MAINTAINERS b/board/armadeus/apf27/MAINTAINERS
new file mode 100644
index 0000000..09f0525
--- /dev/null
+++ b/board/armadeus/apf27/MAINTAINERS
@@ -0,0 +1,7 @@
+APF27 BOARD
+M: Philippe Reynes <tremyfr@yahoo.fr>
+M: Eric Jarrige <eric.jarrige@armadeus.org>
+S: Maintained
+F: board/armadeus/apf27/
+F: include/configs/apf27.h
+F: configs/apf27_defconfig
diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
new file mode 100644
index 0000000..5712971
--- /dev/null
+++ b/board/armadeus/apf27/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2012-2013
+# Eric Jarrige <eric.jarrige@armadeus.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := apf27.o
+obj-y += lowlevel_init.o
+obj-$(CONFIG_FPGA) += fpga.o
diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
new file mode 100644
index 0000000..30e720d
--- /dev/null
+++ b/board/armadeus/apf27/apf27.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
+ *
+ * based on the files by
+ * Sascha Hauer, Pengutronix
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <environment.h>
+#include <jffs2/jffs2.h>
+#include <nand.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <asm/errno.h>
+#include "apf27.h"
+#include "crc.h"
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Fuse bank 1 row 8 is "reserved for future use" and therefore available for
+ * customer use. The APF27 board uses this fuse to store the board revision:
+ * 0: initial board revision
+ * 1: first revision - Presence of the second RAM chip on the board is blown in
+ * fuse bank 1 row 9 bit 0 - No hardware change
+ * N: to be defined
+ */
+static u32 get_board_rev(void)
+{
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+
+ return readl(&iim->bank[1].fuse_regs[8]);
+}
+
+/*
+ * Fuse bank 1 row 9 is "reserved for future use" and therefore available for
+ * customer use. The APF27 board revision 1 uses the bit 0 to permanently store
+ * the presence of the second RAM chip
+ * 0: AFP27 with 1 RAM of 64 MiB
+ * 1: AFP27 with 2 RAM chips of 64 MiB each (128MB)
+ */
+static int get_num_ram_bank(void)
+{
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ int nr_dram_banks = 1;
+
+ if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1))
+ nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01;
+ else
+ nr_dram_banks = CONFIG_NR_DRAM_POPULATED;
+
+ return nr_dram_banks;
+}
+
+static void apf27_port_init(int port, u32 gpio_dr, u32 ocr1, u32 ocr2,
+ u32 iconfa1, u32 iconfa2, u32 iconfb1, u32 iconfb2,
+ u32 icr1, u32 icr2, u32 imr, u32 gpio_dir, u32 gpr,
+ u32 puen, u32 gius)
+{
+ struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
+
+ writel(gpio_dr, ®s->port[port].gpio_dr);
+ writel(ocr1, ®s->port[port].ocr1);
+ writel(ocr2, ®s->port[port].ocr2);
+ writel(iconfa1, ®s->port[port].iconfa1);
+ writel(iconfa2, ®s->port[port].iconfa2);
+ writel(iconfb1, ®s->port[port].iconfb1);
+ writel(iconfb2, ®s->port[port].iconfb2);
+ writel(icr1, ®s->port[port].icr1);
+ writel(icr2, ®s->port[port].icr2);
+ writel(imr, ®s->port[port].imr);
+ writel(gpio_dir, ®s->port[port].gpio_dir);
+ writel(gpr, ®s->port[port].gpr);
+ writel(puen, ®s->port[port].puen);
+ writel(gius, ®s->port[port].gius);
+}
+
+#define APF27_PORT_INIT(n) apf27_port_init(PORT##n, ACFG_DR_##n##_VAL, \
+ ACFG_OCR1_##n##_VAL, ACFG_OCR2_##n##_VAL, ACFG_ICFA1_##n##_VAL, \
+ ACFG_ICFA2_##n##_VAL, ACFG_ICFB1_##n##_VAL, ACFG_ICFB2_##n##_VAL, \
+ ACFG_ICR1_##n##_VAL, ACFG_ICR2_##n##_VAL, ACFG_IMR_##n##_VAL, \
+ ACFG_DDIR_##n##_VAL, ACFG_GPR_##n##_VAL, ACFG_PUEN_##n##_VAL, \
+ ACFG_GIUS_##n##_VAL)
+
+static void apf27_iomux_init(void)
+{
+ APF27_PORT_INIT(A);
+ APF27_PORT_INIT(B);
+ APF27_PORT_INIT(C);
+ APF27_PORT_INIT(D);
+ APF27_PORT_INIT(E);
+ APF27_PORT_INIT(F);
+}
+
+static int apf27_devices_init(void)
+{
+ int i;
+ unsigned int mode[] = {
+ PC5_PF_I2C2_DATA,
+ PC6_PF_I2C2_CLK,
+ PD17_PF_I2C_DATA,
+ PD18_PF_I2C_CLK,
+ };
+
+ for (i = 0; i < ARRAY_SIZE(mode); i++)
+ imx_gpio_mode(mode[i]);
+
+#ifdef CONFIG_MXC_UART
+ mx27_uart1_init_pins();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+ mx27_fec_init_pins();
+#endif
+
+#ifdef CONFIG_MXC_MMC
+ mx27_sd2_init_pins();
+ imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16));
+ gpio_request(PC_PWRON, "pc_pwron");
+ gpio_set_value(PC_PWRON, 1);
+#endif
+ return 0;
+}
+
+static void apf27_setup_csx(void)
+{
+ struct weim_regs *weim = (struct weim_regs *)IMX_WEIM_BASE;
+
+ writel(ACFG_CS0U_VAL, &weim->cs0u);
+ writel(ACFG_CS0L_VAL, &weim->cs0l);
+ writel(ACFG_CS0A_VAL, &weim->cs0a);
+
+ writel(ACFG_CS1U_VAL, &weim->cs1u);
+ writel(ACFG_CS1L_VAL, &weim->cs1l);
+ writel(ACFG_CS1A_VAL, &weim->cs1a);
+
+ writel(ACFG_CS2U_VAL, &weim->cs2u);
+ writel(ACFG_CS2L_VAL, &weim->cs2l);
+ writel(ACFG_CS2A_VAL, &weim->cs2a);
+
+ writel(ACFG_CS3U_VAL, &weim->cs3u);
+ writel(ACFG_CS3L_VAL, &weim->cs3l);
+ writel(ACFG_CS3A_VAL, &weim->cs3a);
+
+ writel(ACFG_CS4U_VAL, &weim->cs4u);
+ writel(ACFG_CS4L_VAL, &weim->cs4l);
+ writel(ACFG_CS4A_VAL, &weim->cs4a);
+
+ writel(ACFG_CS5U_VAL, &weim->cs5u);
+ writel(ACFG_CS5L_VAL, &weim->cs5l);
+ writel(ACFG_CS5A_VAL, &weim->cs5a);
+
+ writel(ACFG_EIM_VAL, &weim->eim);
+}
+
+static void apf27_setup_port(void)
+{
+ struct system_control_regs *system =
+ (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+
+ writel(ACFG_FMCR_VAL, &system->fmcr);
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ apf27_setup_csx();
+ apf27_setup_port();
+ apf27_iomux_init();
+ apf27_devices_init();
+#if defined(CONFIG_FPGA)
+ APF27_init_fpga();
+#endif
+
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ if (get_num_ram_bank() > 1)
+ gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ if (get_num_ram_bank() > 1)
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+ else
+ gd->bd->bi_dram[1].size = 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ ulong ramtop;
+
+ if (get_num_ram_bank() > 1)
+ ramtop = PHYS_SDRAM_2 + get_ram_size((void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+ else
+ ramtop = PHYS_SDRAM_1 + get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return ramtop;
+}
+
+int checkboard(void)
+{
+ printf("Board: Armadeus APF27 revision %d\n", get_board_rev());
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+inline void hang(void)
+{
+ for (;;)
+ ;
+}
+
+void board_init_f(ulong bootflag)
+{
+ /*
+ * copy ourselves from where we are running to where we were
+ * linked at. Use ulong pointers as all addresses involved
+ * are 4-byte-aligned.
+ */
+ ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
+ asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
+ asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
+ asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
+ asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
+ for (dst = start_ptr; dst < end_ptr; dst++)
+ *dst = *(dst+(run_ptr-link_ptr));
+
+ /*
+ * branch to nand_boot's link-time address.
+ */
+ asm volatile("ldr pc, =nand_boot");
+}
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/armadeus/apf27/apf27.h b/board/armadeus/apf27/apf27.h
new file mode 100644
index 0000000..64e7e4d
--- /dev/null
+++ b/board/armadeus/apf27/apf27.h
@@ -0,0 +1,489 @@
+/*
+ * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __APF27_H
+#define __APF27_H
+
+/* FPGA program pin configuration */
+#define ACFG_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */
+#define ACFG_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */
+#define ACFG_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */
+#define ACFG_FPGA_RDATA 0xD6000000 /* FPGA data addr */
+#define ACFG_FPGA_WDATA 0xD6000000 /* FPGA data addr */
+#define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */
+#define ACFG_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */
+#define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */
+#define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */
+#define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */
+#define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */
+
+/* MMC pin */
+#define PC_PWRON (GPIO_PORTF | 16)
+
+/*
+ * MPU CLOCK source before PLL
+ * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
+ */
+#define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */
+#define ACFG_MPCTL1_VAL 0
+#define CONFIG_MPLL_FREQ 399
+
+#define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
+
+/* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/
+#define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */
+#define ACFG_SPCTL1_VAL 0
+#define CONFIG_SPLL_FREQ 300 /* MHz */
+
+/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */
+#define CONFIG_ARM_FREQ 399 /* up to 400 MHz */
+
+/* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */
+#define CONFIG_HCLK_FREQ 133 /* (ACFG_CLK_FREQ/2) */
+
+#define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */
+#define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */
+#define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */
+#define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */
+#define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1 */
+#define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2 */
+#define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC */
+#define CONFIG_H264_FREQ 66 /* 66.50 MHz H264 */
+#define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */
+#define CONFIG_CLK0_EN 1 /* CLK0 enabled */
+
+/* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */
+#define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz */
+
+/* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */
+#define CONFIG_USB_FREQ 60 /* 60 MHz */
+
+/*
+ * SDRAM
+ */
+#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
+/* micron 64MB */
+#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11
+ * column address bits
+ */
+#define ACFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13
+ * row address bits
+ */
+#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
+ * 2=4096 3=8192 refresh
+ */
+#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
+ * down delay
+ */
+#define ACFG_SDRAM_W2R_DELAY 1 /* write to read
+ * cycle delay > 0
+ */
+#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
+#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
+ * cycle delay 1..4
+ */
+#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck
+ * SDRAM: 0=1ck 1=2ck
+ */
+#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
+#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
+#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
+#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
+ * refresh to command)
+ */
+#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
+ * estimated fo CL=1
+ * 0=force 3 for lpddr
+ */
+#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
+ * 3=Eighth 4=Sixteenth
+ */
+#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
+ * 2=quater 3=Eighth
+ */
+#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
+#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access
+ * 0 = Burst mode
+ */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 128)
+/* micron 128MB */
+#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11
+ * column address bits
+ */
+#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13
+ * row address bits
+ */
+#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
+ * 2=4096 3=8192 refresh
+ */
+#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
+ * down delay
+ */
+#define ACFG_SDRAM_W2R_DELAY 1 /* write to read
+ * cycle delay > 0
+ */
+#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
+#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
+ * cycle delay 1..4
+ */
+#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck
+ * SDRAM: 0=1ck 1=2ck
+ */
+#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
+#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
+#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
+#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
+ * refresh to command)
+ */
+#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
+ * estimated fo CL=1
+ * 0=force 3 for lpddr
+ */
+#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
+ * 3=Eighth 4=Sixteenth
+ */
+#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
+ * 2=quater 3=Eighth
+ */
+#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
+#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access
+ * 0 = Burst mode
+ */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 256)
+/* micron 256MB */
+#define ACFG_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11
+ * column address bits
+ */
+#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13
+ * row address bits
+ */
+#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
+ * 2=4096 3=8192 refresh
+ */
+#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
+ * down delay
+ */
+#define ACFG_SDRAM_W2R_DELAY 1 /* write to read cycle
+ * delay > 0
+ */
+#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
+#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
+ * cycle delay 1..4
+ */
+#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck
+ * SDRAM: 0=1ck 1=2ck
+ */
+#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
+#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
+#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
+#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
+ * refresh to command)
+ */
+#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
+ * estimated fo CL=1
+ * 0=force 3 for lpddr
+ */
+#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
+ * 3=Eighth 4=Sixteenth
+ */
+#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength
+ * 1=half
+ * 2=quater
+ * 3=Eighth
+ */
+#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
+#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access
+ * 0 = Burst mode
+ */
+#endif
+
+/*
+ * External interface
+ */
+/*
+ * CSCRxU_VAL:
+ * 31| x | x | x x |x x x x| x x | x | x |x x x x|16
+ * |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL |
+ *
+ * 15| x x | x x x x x x | x | x x x x | x x x x |0
+ * | CNC | WSC |EW | WWS | EDC |
+ *
+ * CSCRxL_VAL:
+ * 31| x x x x | x x x x | x x x x | x x x x |16
+ * | OEA | OEN | EBWA | EBWN |
+ * 15|x x x x| x |x x x |x x x x| x | x | x | x | 0
+ * | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN|
+ *
+ * CSCRxA_VAL:
+ * 31| x x x x | x x x x | x x x x | x x x x |16
+ * | EBRA | EBRN | RWA | RWN |
+ * 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0
+ * |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE|
+ */
+
+/* CS0 configuration for 16 bit nor flash */
+#define ACFG_CS0U_VAL 0x0000CC03
+#define ACFG_CS0L_VAL 0xa0330D01
+#define ACFG_CS0A_VAL 0x00220800
+
+#define ACFG_CS1U_VAL 0x00000f00
+#define ACFG_CS1L_VAL 0x00000D01
+#define ACFG_CS1A_VAL 0
+
+#define ACFG_CS2U_VAL 0
+#define ACFG_CS2L_VAL 0
+#define ACFG_CS2A_VAL 0
+
+#define ACFG_CS3U_VAL 0
+#define ACFG_CS3L_VAL 0
+#define ACFG_CS3A_VAL 0
+
+#define ACFG_CS4U_VAL 0
+#define ACFG_CS4L_VAL 0
+#define ACFG_CS4A_VAL 0
+
+/* FPGA 16 bit data bus */
+#define ACFG_CS5U_VAL 0x00000600
+#define ACFG_CS5L_VAL 0x00000D01
+#define ACFG_CS5A_VAL 0
+
+#define ACFG_EIM_VAL 0x00002200
+
+
+/*
+ * FPGA specific settings
+ */
+
+/* CLKO */
+#define ACFG_CCSR_VAL 0x00000305
+/* drive strength CLKO set to 2 */
+#define ACFG_DSCR10_VAL 0x00020000
+/* drive strength A1..A12 set to 2 */
+#define ACFG_DSCR3_VAL 0x02AAAAA8
+/* drive strength ctrl */
+#define ACFG_DSCR7_VAL 0x00020880
+/* drive strength data */
+#define ACFG_DSCR2_VAL 0xAAAAAAAA
+
+
+/*
+ * Default configuration for GPIOs and peripherals
+ */
+#define ACFG_DDIR_A_VAL 0x00000000
+#define ACFG_OCR1_A_VAL 0x00000000
+#define ACFG_OCR2_A_VAL 0x00000000
+#define ACFG_ICFA1_A_VAL 0xFFFFFFFF
+#define ACFG_ICFA2_A_VAL 0xFFFFFFFF
+#define ACFG_ICFB1_A_VAL 0xFFFFFFFF
+#define ACFG_ICFB2_A_VAL 0xFFFFFFFF
+#define ACFG_DR_A_VAL 0x00000000
+#define ACFG_GIUS_A_VAL 0xFFFFFFFF
+#define ACFG_ICR1_A_VAL 0x00000000
+#define ACFG_ICR2_A_VAL 0x00000000
+#define ACFG_IMR_A_VAL 0x00000000
+#define ACFG_GPR_A_VAL 0x00000000
+#define ACFG_PUEN_A_VAL 0xFFFFFFFF
+
+#define ACFG_DDIR_B_VAL 0x00000000
+#define ACFG_OCR1_B_VAL 0x00000000
+#define ACFG_OCR2_B_VAL 0x00000000
+#define ACFG_ICFA1_B_VAL 0xFFFFFFFF
+#define ACFG_ICFA2_B_VAL 0xFFFFFFFF
+#define ACFG_ICFB1_B_VAL 0xFFFFFFFF
+#define ACFG_ICFB2_B_VAL 0xFFFFFFFF
+#define ACFG_DR_B_VAL 0x00000000
+#define ACFG_GIUS_B_VAL 0xFF3FFFF0
+#define ACFG_ICR1_B_VAL 0x00000000
+#define ACFG_ICR2_B_VAL 0x00000000
+#define ACFG_IMR_B_VAL 0x00000000
+#define ACFG_GPR_B_VAL 0x00000000
+#define ACFG_PUEN_B_VAL 0xFFFFFFFF
+
+#define ACFG_DDIR_C_VAL 0x00000000
+#define ACFG_OCR1_C_VAL 0x00000000
+#define ACFG_OCR2_C_VAL 0x00000000
+#define ACFG_ICFA1_C_VAL 0xFFFFFFFF
+#define ACFG_ICFA2_C_VAL 0xFFFFFFFF
+#define ACFG_ICFB1_C_VAL 0xFFFFFFFF
+#define ACFG_ICFB2_C_VAL 0xFFFFFFFF
+#define ACFG_DR_C_VAL 0x00000000
+#define ACFG_GIUS_C_VAL 0xFFFFC07F
+#define ACFG_ICR1_C_VAL 0x00000000
+#define ACFG_ICR2_C_VAL 0x00000000
+#define ACFG_IMR_C_VAL 0x00000000
+#define ACFG_GPR_C_VAL 0x00000000
+#define ACFG_PUEN_C_VAL 0xFFFFFF87
+
+#define ACFG_DDIR_D_VAL 0x00000000
+#define ACFG_OCR1_D_VAL 0x00000000
+#define ACFG_OCR2_D_VAL 0x00000000
+#define ACFG_ICFA1_D_VAL 0xFFFFFFFF
+#define ACFG_ICFA2_D_VAL 0xFFFFFFFF
+#define ACFG_ICFB1_D_VAL 0xFFFFFFFF
+#define ACFG_ICFB2_D_VAL 0xFFFFFFFF
+#define ACFG_DR_D_VAL 0x00000000
+#define ACFG_GIUS_D_VAL 0xFFFFFFFF
+#define ACFG_ICR1_D_VAL 0x00000000
+#define ACFG_ICR2_D_VAL 0x00000000
+#define ACFG_IMR_D_VAL 0x00000000
+#define ACFG_GPR_D_VAL 0x00000000
+#define ACFG_PUEN_D_VAL 0xFFFFFFFF
+
+#define ACFG_DDIR_E_VAL 0x00000000
+#define ACFG_OCR1_E_VAL 0x00000000
+#define ACFG_OCR2_E_VAL 0x00000000
+#define ACFG_ICFA1_E_VAL 0xFFFFFFFF
+#define ACFG_ICFA2_E_VAL 0xFFFFFFFF
+#define ACFG_ICFB1_E_VAL 0xFFFFFFFF
+#define ACFG_ICFB2_E_VAL 0xFFFFFFFF
+#define ACFG_DR_E_VAL 0x00000000
+#define ACFG_GIUS_E_VAL 0xFCFFCCF8
+#define ACFG_ICR1_E_VAL 0x00000000
+#define ACFG_ICR2_E_VAL 0x00000000
+#define ACFG_IMR_E_VAL 0x00000000
+#define ACFG_GPR_E_VAL 0x00000000
+#define ACFG_PUEN_E_VAL 0xFFFFFFFF
+
+#define ACFG_DDIR_F_VAL 0x00000000
+#define ACFG_OCR1_F_VAL 0x00000000
+#define ACFG_OCR2_F_VAL 0x00000000
+#define ACFG_ICFA1_F_VAL 0xFFFFFFFF
+#define ACFG_ICFA2_F_VAL 0xFFFFFFFF
+#define ACFG_ICFB1_F_VAL 0xFFFFFFFF
+#define ACFG_ICFB2_F_VAL 0xFFFFFFFF
+#define ACFG_DR_F_VAL 0x00000000
+#define ACFG_GIUS_F_VAL 0xFF7F8000
+#define ACFG_ICR1_F_VAL 0x00000000
+#define ACFG_ICR2_F_VAL 0x00000000
+#define ACFG_IMR_F_VAL 0x00000000
+#define ACFG_GPR_F_VAL 0x00000000
+#define ACFG_PUEN_F_VAL 0xFFFFFFFF
+
+/* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */
+#define ACFG_GPCR_VAL 0x0003000F
+
+#define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN
+
+/* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */
+#if (CONFIG_NR_DRAM_BANKS == 1)
+#define ACFG_FMCR_VAL 0xFFFFFFF9
+#elif (CONFIG_NR_DRAM_BANKS == 2)
+#define ACFG_FMCR_VAL 0xFFFFFFFB
+#endif
+
+#define ACFG_AIPI1_PSR0_VAL 0x20040304
+#define ACFG_AIPI1_PSR1_VAL 0xDFFBFCFB
+#define ACFG_AIPI2_PSR0_VAL 0x00000000
+#define ACFG_AIPI2_PSR1_VAL 0xFFFFFFFF
+
+/* PCCR enable DMA FEC I2C1 IIM SDHC1 */
+#define ACFG_PCCR0_VAL 0x05070410
+#define ACFG_PCCR1_VAL 0xA14A0608
+
+/*
+ * From here, there should not be any user configuration.
+ * All Equations are automatic
+ */
+
+/* fixme none integer value (7.5ns) => 2*hclock = 15ns */
+#define ACFG_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */
+
+/* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/
+#define CSCR_MASK 0x0300800D
+
+#define ACFG_CSCR_VAL \
+ (CSCR_MASK \
+ |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28) \
+ |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12) \
+ |((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8))
+
+/* SSIx CLKO NFC H264 MSHC */
+#define ACFG_PCDR0_VAL\
+ (((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0) \
+ |((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6) \
+ |(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\
+ |(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\
+ |(((CONFIG_CLK0_DIV)&0x07)<<22)\
+ |(((CONFIG_CLK0_EN)&0x01)<<25)\
+ |(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26))
+
+/* PERCLKx */
+#define ACFG_PCDR1_VAL\
+ (((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0) \
+ |((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8) \
+ |((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16) \
+ |((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24))
+
+/* SDRAM controller programming Values */
+#if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \
+ (ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1))
+#define REG_FIELD_SCL_VAL 3
+#define REG_FIELD_SCLIMX_VAL 0
+#else
+#define REG_FIELD_SCL_VAL\
+ ((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \
+ ACFG_2XHCLK_LGTH)
+#define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL
+#endif
+
+#if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH))
+#define REG_FIELD_SRC_VAL 0
+#else
+#define REG_FIELD_SRC_VAL\
+ ((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \
+ ACFG_2XHCLK_LGTH)
+#endif
+
+/* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/
+#define REG_ESDCTL_BASE_CONFIG (0x80020485\
+ | (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\
+ | (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\
+ | (((ACFG_SDRAM_REFRESH)&0x7)<<13))
+
+#define ACFG_NORMAL_RW_CMD ((0x0<<28)+REG_ESDCTL_BASE_CONFIG)
+#define ACFG_PRECHARGE_CMD ((0x1<<28)+REG_ESDCTL_BASE_CONFIG)
+#define ACFG_AUTOREFRESH_CMD ((0x2<<28)+REG_ESDCTL_BASE_CONFIG)
+#define ACFG_SET_MODE_REG_CMD ((0x3<<28)+REG_ESDCTL_BASE_CONFIG)
+
+/* ESDRAMC Configuration Registers : force CL=3 to lpddr */
+#define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x0\
+ | (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \
+ ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\
+ | (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\
+ | (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \
+ ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \
+ | (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\
+ | (((ACFG_SDRAM_TWR_DELAY)&0x1)<<15)\
+ | (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \
+ ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \
+ | (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
+ ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \
+ | (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\
+ | (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
+ ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \
+ | (((REG_FIELD_SRC_VAL)&0x0F)<<0))
+
+/* Issue Mode register Command to SDRAM */
+#define ACFG_SDRAM_MODE_REGISTER_VAL\
+ ((((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\
+ | (((REG_FIELD_SCL_VAL)&0x7)<<(4))\
+ | ((0)<<(3)) /* sequentiql access */ \
+ /*| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/)
+
+/* Issue Extended Mode register Command to SDRAM */
+#define ACFG_SDRAM_EXT_MODE_REGISTER_VAL\
+ ((ACFG_SDRAM_PARTIAL_ARRAY_SR<<0)\
+ | (ACFG_SDRAM_DRIVE_STRENGH<<(5))\
+ | (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2)))
+
+/* Issue Precharge all Command to SDRAM */
+#define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10)
+
+#endif /* __APF27_H */
diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
new file mode 100644
index 0000000..65a4812
--- /dev/null
+++ b/board/armadeus/apf27/fpga.c
@@ -0,0 +1,225 @@
+/*
+ * (C) Copyright 2002-2013
+ * Eric Jarrige <eric.jarrige@armadeus.org>
+ *
+ * based on the files by
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com
+ * and
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+
+#include <asm/arch/imx-regs.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <command.h>
+#include <config.h>
+#include "fpga.h"
+#include <spartan3.h>
+#include "apf27.h"
+
+/*
+ * Note that these are pointers to code that is in Flash. They will be
+ * relocated at runtime.
+ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
+ * Just take care about the file size
+ */
+xilinx_spartan3_slave_parallel_fns fpga_fns = {
+ fpga_pre_fn,
+ fpga_pgm_fn,
+ fpga_init_fn,
+ NULL,
+ fpga_done_fn,
+ fpga_clk_fn,
+ fpga_cs_fn,
+ fpga_wr_fn,
+ fpga_rdata_fn,
+ fpga_wdata_fn,
+ fpga_busy_fn,
+ fpga_abort_fn,
+ fpga_post_fn,
+};
+
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+ {xilinx_spartan3,
+ slave_parallel,
+ 1196128l/8,
+ (void *)&fpga_fns,
+ 0,
+ &spartan3_op,
+ "3s200aft256"}
+};
+
+/*
+ * Initialize GPIO port B before download
+ */
+int fpga_pre_fn(int cookie)
+{
+ /* Initialize GPIO pins */
+ gpio_set_value(ACFG_FPGA_PWR, 1);
+ imx_gpio_mode(ACFG_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
+ imx_gpio_mode(ACFG_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
+ imx_gpio_mode(ACFG_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+ imx_gpio_mode(ACFG_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+ imx_gpio_mode(ACFG_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+ imx_gpio_mode(ACFG_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+ imx_gpio_mode(ACFG_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO);
+ gpio_set_value(ACFG_FPGA_RESET, 1);
+ imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+ imx_gpio_mode(ACFG_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+ gpio_set_value(ACFG_FPGA_PRG, 1);
+ gpio_set_value(ACFG_FPGA_CLK, 1);
+ gpio_set_value(ACFG_FPGA_RW, 1);
+ gpio_set_value(ACFG_FPGA_CS, 1);
+ gpio_set_value(ACFG_FPGA_SUSPEND, 0);
+ gpio_set_value(ACFG_FPGA_PWR, 0);
+ udelay(30000); /*wait until supply started*/
+
+ return cookie;
+}
+
+/*
+ * Set the FPGA's active-low program line to the specified level
+ */
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+ debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
+ assert ? "high" : "low");
+ gpio_set_value(ACFG_FPGA_PRG, !assert);
+ return assert;
+}
+
+/*
+ * Set the FPGA's active-high clock line to the specified level
+ */
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
+ assert_clk ? "high" : "low");
+ gpio_set_value(ACFG_FPGA_CLK, !assert_clk);
+ return assert_clk;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
+ * asserted (low).
+ */
+int fpga_init_fn(int cookie)
+{
+ int value;
+ debug("%s:%d: INIT check... ", __func__, __LINE__);
+ value = gpio_get_value(ACFG_FPGA_INIT);
+ /* printf("init value read %x",value); */
+#ifdef CONFIG_SYS_FPGA_IS_PROTO
+ return value;
+#else
+ return !value;
+#endif
+}
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int fpga_done_fn(int cookie)
+{
+ debug("%s:%d: DONE check... %s", __func__, __LINE__,
+ gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low");
+ return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL;
+}
+
+/*
+ * Set the FPGA's wr line to the specified level
+ */
+int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+ debug("%s:%d: FPGA RW... %s ", __func__, __LINE__,
+ assert_write ? "high" : "low");
+ gpio_set_value(ACFG_FPGA_RW, !assert_write);
+ return assert_write;
+}
+
+int fpga_cs_fn(int assert_cs, int flush, int cookie)
+{
+ debug("%s:%d: FPGA CS %s ", __func__, __LINE__,
+ assert_cs ? "high" : "low");
+ gpio_set_value(ACFG_FPGA_CS, !assert_cs);
+ return assert_cs;
+}
+
+int fpga_rdata_fn(unsigned char *data, int cookie)
+{
+ debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__,
+ *((char *)ACFG_FPGA_RDATA));
+ *data = (unsigned char)
+ ((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF);
+ return *data;
+}
+
+int fpga_wdata_fn(unsigned char data, int flush, int cookie)
+{
+ debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__,
+ data);
+ *((unsigned short *)ACFG_FPGA_WDATA) = data;
+ return data;
+}
+
+int fpga_abort_fn(int cookie)
+{
+ return fpga_post_fn(cookie);
+}
+
+
+int fpga_busy_fn(int cookie)
+{
+ return 1;
+}
+
+int fpga_post_fn(int cookie)
+{
+ debug("%s:%d: FPGA POST ", __func__, __LINE__);
+
+ imx_gpio_mode(ACFG_FPGA_RW | GPIO_PF | GPIO_PUEN);
+ imx_gpio_mode(ACFG_FPGA_CS | GPIO_PF | GPIO_PUEN);
+ imx_gpio_mode(ACFG_FPGA_CLK | GPIO_PF | GPIO_PUEN);
+ gpio_set_value(ACFG_FPGA_PRG, 1);
+ gpio_set_value(ACFG_FPGA_RESET, 0);
+ imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+ return cookie;
+}
+
+void apf27_fpga_setup(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+ struct system_control_regs *system =
+ (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+
+ /* Configure FPGA CLKO */
+ writel(ACFG_CCSR_VAL, &pll->ccsr);
+
+ /* Configure strentgh for FPGA */
+ writel(ACFG_DSCR10_VAL, &system->dscr10);
+ writel(ACFG_DSCR3_VAL, &system->dscr3);
+ writel(ACFG_DSCR7_VAL, &system->dscr7);
+ writel(ACFG_DSCR2_VAL, &system->dscr2);
+}
+
+/*
+ * Initialize the fpga. Return 1 on success, 0 on failure.
+ */
+void APF27_init_fpga(void)
+{
+ int i;
+
+ apf27_fpga_setup();
+
+ fpga_init();
+
+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+ debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
+ fpga_add(fpga_xilinx, &fpga[i]);
+ }
+
+ return;
+}
diff --git a/board/armadeus/apf27/fpga.h b/board/armadeus/apf27/fpga.h
new file mode 100644
index 0000000..84a5244
--- /dev/null
+++ b/board/armadeus/apf27/fpga.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2002-2013
+ * Eric Jarrige <eric.jarrige@armadeus.org>
+ *
+ * based on the files by
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com
+ * and
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+extern void APF27_init_fpga(void);
+
+extern int fpga_pre_fn(int cookie);
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_rdata_fn(unsigned char *data, int cookie);
+extern int fpga_wdata_fn(unsigned char data, int flush, int cookie);
+extern int fpga_abort_fn(int cookie);
+extern int fpga_post_fn(int cookie);
+extern int fpga_busy_fn(int cookie);
diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S
new file mode 100644
index 0000000..4293cb1
--- /dev/null
+++ b/board/armadeus/apf27/lowlevel_init.S
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <generated/asm-offsets.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <asm/arch/imx-regs.h>
+#include "apf27.h"
+
+ .macro init_aipi
+ /*
+ * setup AIPI1 and AIPI2
+ */
+ write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL
+ write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL
+ write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL
+ write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL
+
+ /* Change SDRAM signal strengh */
+ ldr r0, =GPCR
+ ldr r1, =ACFG_GPCR_VAL
+ ldr r5, [r0]
+ orr r5, r5, r1
+ str r5, [r0]
+
+ .endm /* init_aipi */
+
+ .macro init_clock
+ ldr r0, =CSCR
+ /* disable MPLL/SPLL first */
+ ldr r1, [r0]
+ bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
+ str r1, [r0]
+
+ /*
+ * pll clock initialization predefined in apf27.h
+ */
+ write32 MPCTL0, ACFG_MPCTL0_VAL
+ write32 SPCTL0, ACFG_SPCTL0_VAL
+
+ write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
+
+ /*
+ * add some delay here
+ */
+ mov r1, #0x1000
+ 1: subs r1, r1, #0x1
+ bne 1b
+
+ /* peripheral clock divider */
+ write32 PCDR0, ACFG_PCDR0_VAL
+ write32 PCDR1, ACFG_PCDR1_VAL
+
+ /* Configure PCCR0 and PCCR1 */
+ write32 PCCR0, ACFG_PCCR0_VAL
+ write32 PCCR1, ACFG_PCCR1_VAL
+
+ .endm /* init_clock */
+
+ .macro init_ddr
+ /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
+ ldr r0, =IMX_ESD_BASE
+ ldr r4, =ESDMISC_SDRAM_RDY
+2: ldr r1, [r0, #ESDMISC_ROF]
+ ands r1, r1, r4
+ bpl 2b
+
+ /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
+ ldr r0, =IMX_ESD_BASE
+ ldr r4, =ACFG_ESDMISC_VAL
+ orr r1, r4, #ESDMISC_MDDR_DL_RST
+ str r1, [r0, #ESDMISC_ROF]
+
+ /* Hold for more than 200ns */
+ ldr r1, =0x10000
+1: subs r1, r1, #0x1
+ bne 1b
+
+ str r4, [r0]
+
+ ldr r0, =IMX_ESD_BASE
+ ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
+ str r1, [r0, #ESDCFG0_ROF]
+
+ ldr r0, =IMX_ESD_BASE
+ ldr r1, =ACFG_PRECHARGE_CMD
+ str r1, [r0, #ESDCTL0_ROF]
+
+ /* write8(0xA0001000, any value) */
+ ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
+ strb r2, [r1]
+
+ ldr r1, =ACFG_AUTOREFRESH_CMD
+ str r1, [r0, #ESDCTL0_ROF]
+
+ ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
+
+ ldr r6,=0x7 /* load loop counter */
+1: str r5,[r4] /* run auto-refresh cycle to array 0 */
+ subs r6,r6,#1
+ bne 1b
+
+ ldr r1, =ACFG_SET_MODE_REG_CMD
+ str r1, [r0, #ESDCTL0_ROF]
+
+ /* set standard mode register */
+ ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
+ strb r2, [r4]
+
+ /* set extended mode register */
+ ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
+ strb r5, [r4]
+
+ ldr r1, =ACFG_NORMAL_RW_CMD
+ str r1, [r0, #ESDCTL0_ROF]
+
+ /* 2nd sdram */
+ ldr r0, =IMX_ESD_BASE
+ ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
+ str r1, [r0, #ESDCFG1_ROF]
+
+ ldr r0, =IMX_ESD_BASE
+ ldr r1, =ACFG_PRECHARGE_CMD
+ str r1, [r0, #ESDCTL1_ROF]
+
+ /* write8(0xB0001000, any value) */
+ ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
+ strb r2, [r1]
+
+ ldr r1, =ACFG_AUTOREFRESH_CMD
+ str r1, [r0, #ESDCTL1_ROF]
+
+ ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
+
+ ldr r6,=0x7 /* load loop counter */
+1: str r5,[r4] /* run auto-refresh cycle to array 0 */
+ subs r6,r6,#1
+ bne 1b
+
+ ldr r1, =ACFG_SET_MODE_REG_CMD
+ str r1, [r0, #ESDCTL1_ROF]
+
+ /* set standard mode register */
+ ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
+ strb r2, [r4]
+
+ /* set extended mode register */
+ ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
+ strb r2, [r4]
+
+ ldr r1, =ACFG_NORMAL_RW_CMD
+ str r1, [r0, #ESDCTL1_ROF]
+ .endm /* init_ddr */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ init_aipi
+ init_clock
+#ifdef CONFIG_SPL_BUILD
+ init_ddr
+#endif
+
+ mov pc, lr
diff --git a/board/armltd/integrator/Kconfig b/board/armltd/integrator/Kconfig
new file mode 100644
index 0000000..6153b5d
--- /dev/null
+++ b/board/armltd/integrator/Kconfig
@@ -0,0 +1,103 @@
+if TARGET_INTEGRATORAP_CM720T
+
+config SYS_BOARD
+ default "integrator"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "integratorap"
+
+endif
+
+if TARGET_INTEGRATORAP_CM920T
+
+config SYS_BOARD
+ default "integrator"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "integratorap"
+
+endif
+
+if TARGET_INTEGRATORCP_CM920T
+
+config SYS_BOARD
+ default "integrator"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "integratorcp"
+
+endif
+
+if TARGET_INTEGRATORAP_CM926EJS
+
+config SYS_BOARD
+ default "integrator"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "integratorap"
+
+endif
+
+if TARGET_INTEGRATORCP_CM926EJS
+
+config SYS_BOARD
+ default "integrator"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "integratorcp"
+
+endif
+
+if TARGET_INTEGRATORCP_CM1136
+
+config SYS_BOARD
+ default "integrator"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "integratorcp"
+
+endif
+
+if TARGET_INTEGRATORAP_CM946ES
+
+config SYS_BOARD
+ default "integrator"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "integratorap"
+
+endif
+
+if TARGET_INTEGRATORCP_CM946ES
+
+config SYS_BOARD
+ default "integrator"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "integratorcp"
+
+endif
diff --git a/board/armltd/integrator/MAINTAINERS b/board/armltd/integrator/MAINTAINERS
new file mode 100644
index 0000000..8af765e
--- /dev/null
+++ b/board/armltd/integrator/MAINTAINERS
@@ -0,0 +1,14 @@
+INTEGRATOR BOARD
+M: Linus Walleij <linus.walleij@linaro.org>
+S: Maintained
+F: board/armltd/integrator/
+F: include/configs/integratorcp.h
+F: configs/integratorcp_cm1136_defconfig
+F: include/configs/integratorap.h
+F: configs/integratorap_cm720t_defconfig
+F: configs/integratorap_cm920t_defconfig
+F: configs/integratorcp_cm920t_defconfig
+F: configs/integratorap_cm926ejs_defconfig
+F: configs/integratorcp_cm926ejs_defconfig
+F: configs/integratorap_cm946es_defconfig
+F: configs/integratorcp_cm946es_defconfig
diff --git a/board/armltd/integrator/Makefile b/board/armltd/integrator/Makefile
new file mode 100644
index 0000000..7e5f6b0
--- /dev/null
+++ b/board/armltd/integrator/Makefile
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# ARM Ltd.
+# Philippe Robin, <philippe.robin@arm.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := lowlevel_init.o
+
+obj-y += integrator.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += timer.o
diff --git a/board/armltd/integrator/README b/board/armltd/integrator/README
new file mode 100644
index 0000000..5a0e934
--- /dev/null
+++ b/board/armltd/integrator/README
@@ -0,0 +1,110 @@
+
+ U-Boot for ARM Integrator Development Platforms
+
+ Peter Pearse, ARM Ltd.
+ peter.pearse@arm.com
+ www.arm.com
+
+Manuals available from :-
+http://www.arm.com/products/DevTools/Hardware_Platforms.html
+
+Overview :
+--------
+There are two Integrator variants - Integrator/AP and Integrator/CP.
+Each may be fitted with a variety of core modules (CMs).
+Each CM consists of a ARM processor core and associated hardware e.g
+ FPGA implementing various controllers and/or register
+ SSRAM
+ SDRAM
+ RAM controllers
+ clock generators etc.
+CMs may be fitted with varying amounts of SDRAM using a DIMM socket.
+
+Boot Methods :
+------------
+Integrator platforms can be configured to use U-Boot in at least three ways :-
+a) Run ARM boot monitor, manually run U-Boot image from flash
+b) Run ARM boot monitor, automatically run U-Boot image from flash
+c) Run U-Boot image direct from flash.
+
+In cases a) and b) the ARM boot monitor will have configured the CM and mapped
+writeable memory to 0x00000000 in the Integrator address space.
+U-Boot has to carry out minimal configration before standard code is run.
+
+In case c) it may be necessary for U-Boot to perform CM dependent initialization.
+
+Configuring U-Boot :
+------------------
+ The makefile contains targets for Integrator platforms of both types
+fitted with all current variants of CM. If these targets are to be used with
+boot process c) above then CONFIG_INIT_CRITICAL may need to be defined to ensure
+that the CM is correctly configured.
+
+ There are also targets independent of CM. These may not be suitable for
+boot process c) above. They have been preserved for backward compatibility with
+existing build processes.
+
+Code Hierarchy Applied :
+----------------------
+Code specific to initialization of a particular ARM processor has been placed in
+cpu/arm<>/start.S so that it may be used by other boards.
+
+However, to avoid duplicating code through all processor files, a generic core
+for ARM Integrator CMs has been added
+
+ arch/arm/cpu/arm_intcm
+
+Otherwise. for example, the standard CM reset via the CM control register would
+need placing in each CM processor file......
+
+Code specific to the initialization of the CM, rather than the cpu, and initialization
+of the Integrator board itself, has been placed in
+
+ board/integrator<>/platform.S
+ board/integrator<>/integrator<>.c
+
+Targets
+=======
+The U-Boot make targets map to the available core modules as below.
+
+Integrator/AP is no longer available from ARM.
+Core modules marked ** are also no longer available.
+
+ap720t_config ** CM720T
+ap920t_config ** CM920T
+ap926ejs_config Integrator Core Module for ARM926EJ-STM
+ap946es_config Integrator Core Module for ARM946E-STM
+cp920t_config ** CM920T
+cp926ejs_config Integrator Core Module for ARM926EJ-STM
+cp946es_config Integrator Core Module for ARM946E-STM
+cp1136_config Integrator Core Module ARM1136JF-S TM
+
+The final groups of targets are for core modules where no explicit cpu
+code has yet been added to U-Boot i.e. they all use the same U-Boot binary
+using the generic "arm_intcm" core:
+
+ap966_config Integrator Core Module for ARM966E-S TM
+ap922_config Integrator Core Module for ARM922T TM with ETM
+ap922_XA10_config Integrator Core Module for ARM922T using Altera Excalibur
+ap7_config ** CM7TDMI
+integratorap_config
+ap_config
+
+
+cp966_config Integrator Core Module for ARM966E-S TM
+cp922_config Integrator Core Module for ARM922T TM with ETM
+cp922_XA10_config Integrator Core Module for ARM922T using Altera Excalibur
+cp1026_config Integrator Core Module ARM1026EJ-S TM
+integratorcp_config
+cp_config
+
+The Makefile targets call board/integrator<>/split_by_variant.sh
+to configure various defines in include/configs/integrator<>.h
+to indicate the core module & core configuration and ensure that
+board/integrator<>/u-boot.lds loads the cpu object first in the U-Boot image.
+
+*********************************
+Because of this mechanism
+> make clean
+must be run before each change in configuration
+*********************************
diff --git a/board/armltd/integrator/arm-ebi.h b/board/armltd/integrator/arm-ebi.h
new file mode 100644
index 0000000..6381fcc
--- /dev/null
+++ b/board/armltd/integrator/arm-ebi.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Register definitions for the External Bus Interface (EBI)
+ * found in the ARM Integrator AP and CP reference designs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARM_EBI_H
+#define __ARM_EBI_H
+
+#define EBI_BASE 0x12000000
+
+#define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */
+#define EBI_CSR1_REG 0x04 /* CS1 = Flash */
+#define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */
+#define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */
+/*
+ * The four upper bits are the waitstates for each chip select
+ * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
+ */
+#define EBI_CSR_WAIT_MASK 0xF0
+/* Whether memory is synchronous or asynchronous */
+#define EBI_CSR_SYNC_MASK 0xF7
+#define EBI_CSR_ASYNC 0x00
+#define EBI_CSR_SYNC 0x08
+/* Whether memory is write enabled or not */
+#define EBI_CSR_WREN_MASK 0xFB
+#define EBI_CSR_WREN_DISABLE 0x00
+#define EBI_CSR_WREN_ENABLE 0x04
+/* Memory bit width for each chip select */
+#define EBI_CSR_MEMSIZE_MASK 0xFC
+#define EBI_CSR_MEMSIZE_8BIT 0x00
+#define EBI_CSR_MEMSIZE_16BIT 0x01
+#define EBI_CSR_MEMSIZE_32BIT 0x02
+
+/*
+ * The lock register need to be written with 0xa05f before anything in the
+ * EBI can be changed.
+ */
+#define EBI_LOCK_REG 0x20
+#define EBI_UNLOCK_MAGIC 0xA05F
+
+#endif
diff --git a/board/armltd/integrator/integrator-sc.h b/board/armltd/integrator/integrator-sc.h
new file mode 100644
index 0000000..7a94d67
--- /dev/null
+++ b/board/armltd/integrator/integrator-sc.h
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Register definitions for the System Controller (SC) and
+ * the similar "CP Controller" found in the ARM Integrator/AP and
+ * Integrator/CP reference designs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARM_SC_H
+#define __ARM_SC_H
+
+#define SC_BASE 0x11000000
+
+/*
+ * The system controller registers
+ */
+#define SC_ID_OFFSET 0x00
+#define SC_OSC_OFFSET 0x04
+/* Setting this bit switches to 25 MHz mode, clear means 33 MHz */
+#define SC_OSC_DIVXY (1 << 8)
+#define SC_CTRLS_OFFSET 0x08
+#define SC_CTRLC_OFFSET 0x0C
+/* Set bits by writing CTRLS, clear bits by writing CTRLC */
+#define SC_CTRL_SOFTRESET (1 << 0)
+#define SC_CTRL_FLASHVPP (1 << 1)
+#define SC_CTRL_FLASHWP (1 << 2)
+#define SC_CTRL_UART1DTR (1 << 4)
+#define SC_CTRL_UART1RTS (1 << 5)
+#define SC_CTRL_UART0DTR (1 << 6)
+#define SC_CTRL_UART0RTS (1 << 7)
+#define SC_DEC_OFFSET 0x10
+#define SC_ARB_OFFSET 0x14
+#define SC_PCI_OFFSET 0x18
+#define SC_PCI_PCIEN (1 << 0)
+#define SC_PCI_PCIBINT_CLR (1 << 1)
+#define SC_LOCK_OFFSET 0x1C
+#define SC_LBFADDR_OFFSET 0x20
+#define SC_LBFCODE_OFFSET 0x24
+
+#define SC_ID (SC_BASE + SC_ID_OFFSET)
+#define SC_OSC (SC_BASE + SC_OSC_OFFSET)
+#define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET)
+#define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET)
+#define SC_DEC (SC_BASE + SC_DEC_OFFSET)
+#define SC_ARB (SC_BASE + SC_ARB_OFFSET)
+#define SC_PCI (SC_BASE + SC_PCI_OFFSET)
+#define SC_LOCK (SC_BASE + SC_LOCK_OFFSET)
+#define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET)
+#define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET)
+
+/*
+ * The Integrator/CP as a smaller set of registers, at a different
+ * offset - probably not to disturb old software.
+ */
+
+#define CP_BASE 0xCB000000
+
+#define CP_IDFIELD_OFFSET 0x00
+#define CP_FLASHPROG_OFFSET 0x04
+#define CP_FLASHPROG_FLVPPEN (1 << 0)
+#define CP_FLASHPROG_FLWREN (1 << 1)
+#define CP_FLASHPROG_FLASHSIZE (1 << 2)
+#define CP_FLASHPROG_EXTRABANK (1 << 3)
+#define CP_INTREG_OFFSET 0x08
+#define CP_DECODE_OFFSET 0x0C
+
+#define CP_IDFIELD (CP_BASE + CP_ID_OFFSET)
+#define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET)
+#define CP_INTREG (CP_BASE + CP_INTREG_OFFSET)
+#define CP_DECODE (CP_BASE + CP_DECODE_OFFSET)
+
+#endif
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
new file mode 100644
index 0000000..f0fe0fd
--- /dev/null
+++ b/board/armltd/integrator/integrator.c
@@ -0,0 +1,165 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include "arm-ebi.h"
+#include "integrator-sc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void peripheral_power_enable (void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+ printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ u32 val;
+
+ /* arch number of Integrator Board */
+#ifdef CONFIG_ARCH_CINTEGRATOR
+ gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
+#else
+ gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
+#endif
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x00000100;
+
+ gd->flags = 0;
+
+#ifdef CONFIG_CM_REMAP
+extern void cm_remap(void);
+ cm_remap(); /* remaps writeable memory to 0x00000000 */
+#endif
+
+#ifdef CONFIG_ARCH_CINTEGRATOR
+ /*
+ * Flash protection on the Integrator/CP is in a simple register
+ */
+ val = readl(CP_FLASHPROG);
+ val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
+ writel(val, CP_FLASHPROG);
+#else
+ /*
+ * The Integrator/AP has some special protection mechanisms
+ * for the external memories, first the External Bus Interface (EBI)
+ * then the system controller (SC).
+ *
+ * The system comes up with the flash memory non-writable and
+ * configuration locked. If we want U-Boot to be used for flash
+ * access we cannot have the flash memory locked.
+ */
+ writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
+ val = readl(EBI_BASE + EBI_CSR1_REG);
+ val &= EBI_CSR_WREN_MASK;
+ val |= EBI_CSR_WREN_ENABLE;
+ writel(val, EBI_BASE + EBI_CSR1_REG);
+ writel(0, EBI_BASE + EBI_LOCK_REG);
+
+ /*
+ * Set up the system controller to remove write protection from
+ * the flash memory and enable Vpp
+ */
+ writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
+#endif
+
+ icache_enable ();
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ setenv("verify", "n");
+ return (0);
+}
+
+/*
+ * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
+ * from there, which means we cannot test the RAM underneath the ROM at this
+ * point. It will be unmapped later on, when we are executing from the
+ * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
+ * RAM on higher addresses works fine.
+ */
+#define REMAPPED_FLASH_SZ 0x40000
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+#ifdef CONFIG_CM_SPD_DETECT
+ {
+extern void dram_query(void);
+ u32 cm_reg_sdram;
+ u32 sdram_shift;
+
+ dram_query(); /* Assembler accesses to CM registers */
+ /* Queries the SPD values */
+
+ /* Obtain the SDRAM size from the CM SDRAM register */
+
+ cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
+ /* Register SDRAM size
+ *
+ * 0xXXXXXXbbb000bb 16 MB
+ * 0xXXXXXXbbb001bb 32 MB
+ * 0xXXXXXXbbb010bb 64 MB
+ * 0xXXXXXXbbb011bb 128 MB
+ * 0xXXXXXXbbb100bb 256 MB
+ *
+ */
+ sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
+ gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+ REMAPPED_FLASH_SZ,
+ 0x01000000 << sdram_shift);
+ }
+#else
+ gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
+ REMAPPED_FLASH_SZ,
+ PHYS_SDRAM_1_SIZE);
+#endif /* CM_SPD_DETECT */
+ /* We only have one bank of RAM, set it to whatever was detected */
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ rc += pci_eth_init(bis);
+ return rc;
+}
+#endif
diff --git a/board/armltd/integrator/lowlevel_init.S b/board/armltd/integrator/lowlevel_init.S
new file mode 100644
index 0000000..0fb42ad
--- /dev/null
+++ b/board/armltd/integrator/lowlevel_init.S
@@ -0,0 +1,197 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+ /* Reset using CM control register */
+.global reset_cpu
+reset_cpu:
+ mov r0, #CM_BASE
+ ldr r1,[r0,#OS_CTRL]
+ orr r1,r1,#CMMASK_RESET
+ str r1,[r0,#OS_CTRL]
+
+reset_failed:
+ b reset_failed
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+ /* If U-Boot has been run after the ARM boot monitor
+ * then all the necessary actions have been done
+ * otherwise we are running from user flash mapped to 0x00000000
+ * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
+ * Changes to the (possibly soft) reset defaults of the processor
+ * itself should be performed in cpu/arm<>/start.S
+ * This function affects only the core module or board settings
+ */
+
+#ifdef CONFIG_CM_INIT
+ /* CM has an initialization register
+ * - bits in it are wired into test-chip pins to force
+ * reset defaults
+ * - may need to change its contents for U-Boot
+ */
+
+ /* set the desired CM specific value */
+ mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+ orr r2,r2,#CMMASK_INIT_102
+#else
+
+#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
+ !defined (CONFIG_CM940T)
+
+#ifdef CONFIG_CM_MULTIPLE_SSRAM
+ /* set simple mapping */
+ and r2,r2,#CMMASK_MAP_SIMPLE
+#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
+
+#ifdef CONFIG_CM_TCRAM
+ /* disable TCRAM */
+ and r2,r2,#CMMASK_TCRAM_DISABLE
+#endif /* #ifdef CONFIG_CM_TCRAM */
+
+#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
+ defined (CONFIG_CM1136JF_S)
+
+ and r2,r2,#CMMASK_LE
+
+#endif /* cpu with little endian initialization */
+
+ orr r2,r2,#CMMASK_CMxx6_COMMON
+
+#endif /* CMxx6 code */
+
+#endif /* ARM102xxE value */
+
+ /* read CM_INIT */
+ mov r0, #CM_BASE
+ ldr r1, [r0, #OS_INIT]
+ /* check against desired bit setting */
+ and r3,r1,r2
+ cmp r3,r2
+ beq init_reg_OK
+
+ /* lock for change */
+ mov r3, #CMVAL_LOCK1
+ add r3,r3,#CMVAL_LOCK2
+ str r3, [r0, #OS_LOCK]
+ /* set desired value */
+ orr r1,r1,r2
+ /* write & relock CM_INIT */
+ str r1, [r0, #OS_INIT]
+ mov r1, #CMVAL_UNLOCK
+ str r1, [r0, #OS_LOCK]
+
+ /* soft reset so new values used */
+ b reset_cpu
+
+init_reg_OK:
+
+#endif /* CONFIG_CM_INIT */
+
+ mov pc, lr
+
+#ifdef CONFIG_CM_SPD_DETECT
+ /* Fast memory is available for the DRAM data
+ * - ensure it has been transferred, then summarize the data
+ * into a CM register
+ */
+.globl dram_query
+dram_query:
+ stmfd r13!,{r4-r6,lr}
+ /* set up SDRAM info */
+ /* - based on example code from the CM User Guide */
+ mov r0, #CM_BASE
+
+readspdbit:
+ ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */
+ and r1, r1, #0x20 /* mask SPD bit (5) */
+ cmp r1, #0x20 /* test if set */
+ bne readspdbit
+
+setupsdram:
+ add r0, r0, #OS_SPD /* address the copy of the SDP data */
+ ldrb r1, [r0, #3] /* number of row address lines */
+ ldrb r2, [r0, #4] /* number of column address lines */
+ ldrb r3, [r0, #5] /* number of banks */
+ ldrb r4, [r0, #31] /* module bank density */
+ mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */
+ mov r5, r5, ASL#2 /* size in MB */
+ mov r0, #CM_BASE /* reload for later code */
+ cmp r5, #0x10 /* is it 16MB? */
+ bne not16
+ mov r6, #0x2 /* store size and CAS latency of 2 */
+ b writesize
+
+not16:
+ cmp r5, #0x20 /* is it 32MB? */
+ bne not32
+ mov r6, #0x6
+ b writesize
+
+not32:
+ cmp r5, #0x40 /* is it 64MB? */
+ bne not64
+ mov r6, #0xa
+ b writesize
+
+not64:
+ cmp r5, #0x80 /* is it 128MB? */
+ bne not128
+ mov r6, #0xe
+ b writesize
+
+not128:
+ /* if it is none of these sizes then it is either 256MB, or
+ * there is no SDRAM fitted so default to 256MB
+ */
+ mov r6, #0x12
+
+writesize:
+ mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */
+ orr r2, r1, r2, ASL#12 /* OR in column address lines */
+ orr r3, r2, r3, ASL#16 /* OR in number of banks */
+ orr r6, r6, r3 /* OR in size and CAS latency */
+ str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */
+
+#endif /* #ifdef CONFIG_CM_SPD_DETECT */
+
+ ldmfd r13!,{r4-r6,pc} /* back to caller */
+
+#ifdef CONFIG_CM_REMAP
+ /* CM remap bit is operational
+ * - use it to map writeable memory at 0x00000000, in place of flash
+ */
+.globl cm_remap
+cm_remap:
+ stmfd r13!,{r4-r10,lr}
+
+ mov r0, #CM_BASE
+ ldr r1, [r0, #OS_CTRL]
+ orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
+ str r1, [r0, #OS_CTRL]
+
+ /* Now 0x00000000 is writeable, replace the vectors */
+ ldr r0, =_start /* r0 <- start of vectors */
+ add r2, r0, #64 /* r2 <- past vectors */
+ sub r1,r1,r1 /* destination 0x00000000 */
+
+copy_vec:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ ble copy_vec
+
+ ldmfd r13!,{r4-r10,pc} /* back to caller */
+
+#endif /* #ifdef CONFIG_CM_REMAP */
diff --git a/board/armltd/integrator/pci.c b/board/armltd/integrator/pci.c
new file mode 100644
index 0000000..157138b
--- /dev/null
+++ b/board/armltd/integrator/pci.c
@@ -0,0 +1,459 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * (C) Copyright 2011
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <pci.h>
+#include <asm/io.h>
+#include "integrator-sc.h"
+#include "pci_v3.h"
+
+#define INTEGRATOR_BOOT_ROM_BASE 0x20000000
+#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
+
+/*
+ * These are in the physical addresses on the CPU side, i.e.
+ * where we read and write stuff - you don't want to try to
+ * move these around
+ */
+#define PHYS_PCI_MEM_BASE 0x40000000
+#define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */
+#define PHYS_PCI_CONFIG_BASE 0x61000000
+#define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */
+#define SZ_256M 0x10000000
+
+/*
+ * These are in the PCI BUS address space
+ * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor
+ * we follow the example of the kernel, because that is the address
+ * range that devices actually use - what would they be doing at
+ * 0x40000000?
+ */
+#define PCI_BUS_NONMEM_START 0x00000000
+#define PCI_BUS_NONMEM_SIZE SZ_256M
+
+#define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE)
+#define PCI_BUS_PREMEM_SIZE SZ_256M
+
+#if PCI_BUS_NONMEM_START & 0x000fffff
+#error PCI_BUS_NONMEM_START must be megabyte aligned
+#endif
+#if PCI_BUS_PREMEM_START & 0x000fffff
+#error PCI_BUS_PREMEM_START must be megabyte aligned
+#endif
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+#define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */
+#define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */
+static struct pci_config_table pci_integrator_config_table[] = {
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+ { }
+};
+#endif /* CONFIG_PCI_PNP */
+
+/* V3 access routines */
+#define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
+#define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o)))
+
+#define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
+#define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o)))
+
+#define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o))
+#define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o)))
+
+static unsigned long v3_open_config_window(pci_dev_t bdf, int offset)
+{
+ unsigned int address, mapaddress;
+ unsigned int busnr = PCI_BUS(bdf);
+ unsigned int devfn = PCI_FUNC(bdf);
+
+ /*
+ * Trap out illegal values
+ */
+ if (offset > 255)
+ BUG();
+ if (busnr > 255)
+ BUG();
+ if (devfn > 255)
+ BUG();
+
+ if (busnr == 0) {
+ /*
+ * Linux calls the thing U-Boot calls "DEV" "SLOT"
+ * instead, but it's the same 5 bits
+ */
+ int slot = PCI_DEV(bdf);
+
+ /*
+ * local bus segment so need a type 0 config cycle
+ *
+ * build the PCI configuration "address" with one-hot in
+ * A31-A11
+ *
+ * mapaddress:
+ * 3:1 = config cycle (101)
+ * 0 = PCI A1 & A0 are 0 (0)
+ */
+ address = PCI_FUNC(bdf) << 8;
+ mapaddress = V3_LB_MAP_TYPE_CONFIG;
+
+ if (slot > 12)
+ /*
+ * high order bits are handled by the MAP register
+ */
+ mapaddress |= 1 << (slot - 5);
+ else
+ /*
+ * low order bits handled directly in the address
+ */
+ address |= 1 << (slot + 11);
+ } else {
+ /*
+ * not the local bus segment so need a type 1 config cycle
+ *
+ * address:
+ * 23:16 = bus number
+ * 15:11 = slot number (7:3 of devfn)
+ * 10:8 = func number (2:0 of devfn)
+ *
+ * mapaddress:
+ * 3:1 = config cycle (101)
+ * 0 = PCI A1 & A0 from host bus (1)
+ */
+ mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
+ address = (busnr << 16) | (devfn << 8);
+ }
+
+ /*
+ * Set up base0 to see all 512Mbytes of memory space (not
+ * prefetchable), this frees up base1 for re-use by
+ * configuration memory
+ */
+ v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+ V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
+
+ /*
+ * Set up base1/map1 to point into configuration space.
+ */
+ v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
+ V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
+ v3_writew(V3_LB_MAP1, mapaddress);
+
+ return PHYS_PCI_CONFIG_BASE + address + offset;
+}
+
+static void v3_close_config_window(void)
+{
+ /*
+ * Reassign base1 for use by prefetchable PCI memory
+ */
+ v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
+ V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
+ V3_LB_BASE_ENABLE);
+ v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
+ V3_LB_MAP_TYPE_MEM_MULTIPLE);
+
+ /*
+ * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
+ */
+ v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+ V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
+}
+
+static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf,
+ int offset, unsigned char *val)
+{
+ unsigned long addr;
+
+ addr = v3_open_config_window(bdf, offset);
+ *val = __raw_readb(addr);
+ v3_close_config_window();
+ return 0;
+}
+
+static int pci_integrator_read__word(struct pci_controller *hose,
+ pci_dev_t bdf, int offset,
+ unsigned short *val)
+{
+ unsigned long addr;
+
+ addr = v3_open_config_window(bdf, offset);
+ *val = __raw_readw(addr);
+ v3_close_config_window();
+ return 0;
+}
+
+static int pci_integrator_read_dword(struct pci_controller *hose,
+ pci_dev_t bdf, int offset,
+ unsigned int *val)
+{
+ unsigned long addr;
+
+ addr = v3_open_config_window(bdf, offset);
+ *val = __raw_readl(addr);
+ v3_close_config_window();
+ return 0;
+}
+
+static int pci_integrator_write_byte(struct pci_controller *hose,
+ pci_dev_t bdf, int offset,
+ unsigned char val)
+{
+ unsigned long addr;
+
+ addr = v3_open_config_window(bdf, offset);
+ __raw_writeb((u8)val, addr);
+ __raw_readb(addr);
+ v3_close_config_window();
+ return 0;
+}
+
+static int pci_integrator_write_word(struct pci_controller *hose,
+ pci_dev_t bdf, int offset,
+ unsigned short val)
+{
+ unsigned long addr;
+
+ addr = v3_open_config_window(bdf, offset);
+ __raw_writew((u8)val, addr);
+ __raw_readw(addr);
+ v3_close_config_window();
+ return 0;
+}
+
+static int pci_integrator_write_dword(struct pci_controller *hose,
+ pci_dev_t bdf, int offset,
+ unsigned int val)
+{
+ unsigned long addr;
+
+ addr = v3_open_config_window(bdf, offset);
+ __raw_writel((u8)val, addr);
+ __raw_readl(addr);
+ v3_close_config_window();
+ return 0;
+}
+
+struct pci_controller integrator_hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table: pci_integrator_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+ struct pci_controller *hose = &integrator_hose;
+ u16 val;
+
+ /* setting this register will take the V3 out of reset */
+ __raw_writel(SC_PCI_PCIEN, SC_PCI);
+
+ /* Wait for 230 ms (from spec) before accessing any V3 registers */
+ mdelay(230);
+
+ /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */
+ v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16));
+
+ /* Wait for the mailbox to settle */
+ do {
+ v3_writeb(V3_MAIL_DATA, 0xAA);
+ v3_writeb(V3_MAIL_DATA + 4, 0x55);
+ } while (v3_readb(V3_MAIL_DATA) != 0xAA ||
+ v3_readb(V3_MAIL_DATA + 4) != 0x55);
+
+ /* Make sure that V3 register access is not locked, if it is, unlock it */
+ if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
+ v3_writew(V3_SYSTEM, 0xA05F);
+
+ /*
+ * Ensure that the slave accesses from PCI are disabled while we
+ * setup memory windows
+ */
+ val = v3_readw(V3_PCI_CMD);
+ val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
+ v3_writew(V3_PCI_CMD, val);
+
+ /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
+ val = v3_readw(V3_SYSTEM);
+ val &= ~V3_SYSTEM_M_RST_OUT;
+ v3_writew(V3_SYSTEM, val);
+
+ /* Make all accesses from PCI space retry until we're ready for them */
+ val = v3_readw(V3_PCI_CFG);
+ val |= V3_PCI_CFG_M_RETRY_EN;
+ v3_writew(V3_PCI_CFG, val);
+
+ /*
+ * Set up any V3 PCI Configuration Registers that we absolutely have to.
+ * LB_CFG controls Local Bus protocol.
+ * Enable LocalBus byte strobes for READ accesses too.
+ * set bit 7 BE_IMODE and bit 6 BE_OMODE
+ */
+ val = v3_readw(V3_LB_CFG);
+ val |= 0x0C0;
+ v3_writew(V3_LB_CFG, val);
+
+ /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */
+ val = v3_readw(V3_PCI_CMD);
+ val |= V3_COMMAND_M_MASTER_EN;
+ v3_writew(V3_PCI_CMD, val);
+
+ /*
+ * PCI_MAP0 controls where the PCI to CPU memory window is on
+ * Local Bus
+ */
+ v3_writel(V3_PCI_MAP0,
+ (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB |
+ V3_PCI_MAP_M_REG_EN |
+ V3_PCI_MAP_M_ENABLE));
+
+ /* PCI_BASE0 is the PCI address of the start of the window */
+ v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE);
+
+ /* PCI_MAP1 is LOCAL address of the start of the window */
+ v3_writel(V3_PCI_MAP1,
+ (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB |
+ V3_PCI_MAP_M_REG_EN |
+ V3_PCI_MAP_M_ENABLE));
+
+ /* PCI_BASE1 is the PCI address of the start of the window */
+ v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE);
+
+ /*
+ * Set up memory the windows from local bus memory into PCI
+ * configuration, I/O and Memory regions.
+ * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this.
+ */
+ v3_writew(V3_LB_BASE2,
+ v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE);
+ v3_writew(V3_LB_MAP2, 0);
+
+ /* PCI Configuration, use LB_BASE1/LB_MAP1. */
+
+ /*
+ * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1
+ * Map first 256Mbytes as non-prefetchable via BASE0/MAP0
+ */
+ v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+ V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
+ v3_writew(V3_LB_MAP0,
+ v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM);
+
+ /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
+ v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
+ V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
+ V3_LB_BASE_ENABLE);
+ v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
+ V3_LB_MAP_TYPE_MEM_MULTIPLE);
+
+ /* Dump PCI to local address space mappings */
+ debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0));
+ debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0));
+ debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1));
+ debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1));
+ debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2));
+ debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2));
+ debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE));
+
+ /*
+ * Allow accesses to PCI Configuration space and set up A1, A0 for
+ * type 1 config cycles
+ */
+ val = v3_readw(V3_PCI_CFG);
+ val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1);
+ val |= V3_PCI_CFG_M_AD_LOW0;
+ v3_writew(V3_PCI_CFG, val);
+
+ /* now we can allow incoming PCI MEMORY accesses */
+ val = v3_readw(V3_PCI_CMD);
+ val |= V3_COMMAND_M_MEM_EN;
+ v3_writew(V3_PCI_CMD, val);
+
+ /*
+ * Set RST_OUT to take the PCI bus is out of reset, PCI devices can
+ * now initialise.
+ */
+ val = v3_readw(V3_SYSTEM);
+ val |= V3_SYSTEM_M_RST_OUT;
+ v3_writew(V3_SYSTEM, val);
+
+ /* Lock the V3 system register so that no one else can play with it */
+ val = v3_readw(V3_SYSTEM);
+ val |= V3_SYSTEM_M_LOCK;
+ v3_writew(V3_SYSTEM, val);
+
+ /*
+ * Configure and register the PCI hose
+ */
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ /* System memory space, window 0 256 MB non-prefetchable */
+ pci_set_region(hose->regions + 0,
+ PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE,
+ SZ_256M,
+ PCI_REGION_MEM);
+
+ /* System memory space, window 1 256 MB prefetchable */
+ pci_set_region(hose->regions + 1,
+ PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M,
+ SZ_256M,
+ PCI_REGION_MEM |
+ PCI_REGION_PREFETCH);
+
+ /* PCI I/O space */
+ pci_set_region(hose->regions + 2,
+ 0x00000000, PHYS_PCI_IO_BASE, 0x01000000,
+ PCI_REGION_IO);
+
+ /* PCI Memory - config space */
+ pci_set_region(hose->regions + 3,
+ 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000,
+ PCI_REGION_MEM);
+ /* PCI V3 regs */
+ pci_set_region(hose->regions + 4,
+ 0x00000000, PHYS_PCI_V3_BASE, 0x01000000,
+ PCI_REGION_MEM);
+
+ hose->region_count = 5;
+
+ pci_set_ops(hose,
+ pci_integrator_read_byte,
+ pci_integrator_read__word,
+ pci_integrator_read_dword,
+ pci_integrator_write_byte,
+ pci_integrator_write_word,
+ pci_integrator_write_dword);
+
+ pci_register_hose(hose);
+
+ pciauto_config_init(hose);
+ pciauto_config_device(hose, 0);
+
+ hose->last_busno = pci_hose_scan(hose);
+}
diff --git a/board/armltd/integrator/pci_v3.h b/board/armltd/integrator/pci_v3.h
new file mode 100644
index 0000000..627b49a
--- /dev/null
+++ b/board/armltd/integrator/pci_v3.h
@@ -0,0 +1,188 @@
+/*
+ * arch/arm/include/asm/hardware/pci_v3.h
+ *
+ * Internal header file PCI V3 chip
+ *
+ * Copyright (C) ARM Limited
+ * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef ASM_ARM_HARDWARE_PCI_V3_H
+#define ASM_ARM_HARDWARE_PCI_V3_H
+
+/* -------------------------------------------------------------------------------
+ * V3 Local Bus to PCI Bridge definitions
+ * -------------------------------------------------------------------------------
+ * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
+ * All V3 register names are prefaced by V3_ to avoid clashing with any other
+ * PCI definitions. Their names match the user's manual.
+ *
+ * I'm assuming that I20 is disabled.
+ *
+ */
+#define V3_PCI_VENDOR 0x00000000
+#define V3_PCI_DEVICE 0x00000002
+#define V3_PCI_CMD 0x00000004
+#define V3_PCI_STAT 0x00000006
+#define V3_PCI_CC_REV 0x00000008
+#define V3_PCI_HDR_CFG 0x0000000C
+#define V3_PCI_IO_BASE 0x00000010
+#define V3_PCI_BASE0 0x00000014
+#define V3_PCI_BASE1 0x00000018
+#define V3_PCI_SUB_VENDOR 0x0000002C
+#define V3_PCI_SUB_ID 0x0000002E
+#define V3_PCI_ROM 0x00000030
+#define V3_PCI_BPARAM 0x0000003C
+#define V3_PCI_MAP0 0x00000040
+#define V3_PCI_MAP1 0x00000044
+#define V3_PCI_INT_STAT 0x00000048
+#define V3_PCI_INT_CFG 0x0000004C
+#define V3_LB_BASE0 0x00000054
+#define V3_LB_BASE1 0x00000058
+#define V3_LB_MAP0 0x0000005E
+#define V3_LB_MAP1 0x00000062
+#define V3_LB_BASE2 0x00000064
+#define V3_LB_MAP2 0x00000066
+#define V3_LB_SIZE 0x00000068
+#define V3_LB_IO_BASE 0x0000006E
+#define V3_FIFO_CFG 0x00000070
+#define V3_FIFO_PRIORITY 0x00000072
+#define V3_FIFO_STAT 0x00000074
+#define V3_LB_ISTAT 0x00000076
+#define V3_LB_IMASK 0x00000077
+#define V3_SYSTEM 0x00000078
+#define V3_LB_CFG 0x0000007A
+#define V3_PCI_CFG 0x0000007C
+#define V3_DMA_PCI_ADR0 0x00000080
+#define V3_DMA_PCI_ADR1 0x00000090
+#define V3_DMA_LOCAL_ADR0 0x00000084
+#define V3_DMA_LOCAL_ADR1 0x00000094
+#define V3_DMA_LENGTH0 0x00000088
+#define V3_DMA_LENGTH1 0x00000098
+#define V3_DMA_CSR0 0x0000008B
+#define V3_DMA_CSR1 0x0000009B
+#define V3_DMA_CTLB_ADR0 0x0000008C
+#define V3_DMA_CTLB_ADR1 0x0000009C
+#define V3_DMA_DELAY 0x000000E0
+#define V3_MAIL_DATA 0x000000C0
+#define V3_PCI_MAIL_IEWR 0x000000D0
+#define V3_PCI_MAIL_IERD 0x000000D2
+#define V3_LB_MAIL_IEWR 0x000000D4
+#define V3_LB_MAIL_IERD 0x000000D6
+#define V3_MAIL_WR_STAT 0x000000D8
+#define V3_MAIL_RD_STAT 0x000000DA
+#define V3_QBA_MAP 0x000000DC
+
+/* PCI COMMAND REGISTER bits
+ */
+#define V3_COMMAND_M_FBB_EN (1 << 9)
+#define V3_COMMAND_M_SERR_EN (1 << 8)
+#define V3_COMMAND_M_PAR_EN (1 << 6)
+#define V3_COMMAND_M_MASTER_EN (1 << 2)
+#define V3_COMMAND_M_MEM_EN (1 << 1)
+#define V3_COMMAND_M_IO_EN (1 << 0)
+
+/* SYSTEM REGISTER bits
+ */
+#define V3_SYSTEM_M_RST_OUT (1 << 15)
+#define V3_SYSTEM_M_LOCK (1 << 14)
+
+/* PCI_CFG bits
+ */
+#define V3_PCI_CFG_M_I2O_EN (1 << 15)
+#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
+#define V3_PCI_CFG_M_IO_DIS (1 << 13)
+#define V3_PCI_CFG_M_EN3V (1 << 12)
+#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
+#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
+#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
+
+/* PCI_BASE register bits (PCI -> Local Bus)
+ */
+#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
+#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
+#define V3_PCI_BASE_M_PREFETCH (1 << 3)
+#define V3_PCI_BASE_M_TYPE (3 << 1)
+#define V3_PCI_BASE_M_IO (1 << 0)
+
+/* PCI MAP register bits (PCI -> Local bus)
+ */
+#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
+#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
+#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
+#define V3_PCI_MAP_M_SWAP (3 << 8)
+#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
+#define V3_PCI_MAP_M_REG_EN (1 << 1)
+#define V3_PCI_MAP_M_ENABLE (1 << 0)
+
+#define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_2MB (1 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_4MB (2 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_8MB (3 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_16MB (4 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_32MB (5 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_64MB (6 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_128MB (7 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_256MB (8 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_512MB (9 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_1GB (10 << 4)
+#define V3_PCI_MAP_M_ADR_SIZE_2GB (11 << 4)
+
+/*
+ * LB_BASE0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_BASE_ADR_BASE 0xfff00000
+#define V3_LB_BASE_SWAP (3 << 8)
+#define V3_LB_BASE_ADR_SIZE (15 << 4)
+#define V3_LB_BASE_PREFETCH (1 << 3)
+#define V3_LB_BASE_ENABLE (1 << 0)
+
+#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
+#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
+#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
+#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
+#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
+#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
+#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
+#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
+#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
+#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
+#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
+#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
+
+#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
+
+/*
+ * LB_MAP0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_MAP_MAP_ADR 0xfff0
+#define V3_LB_MAP_TYPE (7 << 1)
+#define V3_LB_MAP_AD_LOW_EN (1 << 0)
+
+#define V3_LB_MAP_TYPE_IACK (0 << 1)
+#define V3_LB_MAP_TYPE_IO (1 << 1)
+#define V3_LB_MAP_TYPE_MEM (3 << 1)
+#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
+#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
+
+/* PCI MAP register bits (PCI -> Local bus) */
+#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
+
+/*
+ * LB_BASE2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_BASE2_ADR_BASE 0xff00
+#define V3_LB_BASE2_SWAP (3 << 6)
+#define V3_LB_BASE2_ENABLE (1 << 0)
+
+#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
+
+/*
+ * LB_MAP2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_MAP2_MAP_ADR 0xff00
+
+#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
+
+#endif
diff --git a/board/armltd/integrator/timer.c b/board/armltd/integrator/timer.c
new file mode 100644
index 0000000..14a52c4
--- /dev/null
+++ b/board/armltd/integrator/timer.c
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+
+#ifdef CONFIG_ARCH_CINTEGRATOR
+#define DIV_CLOCK_INIT 1
+#define TIMER_LOAD_VAL 0xFFFFFFFFL
+#else
+#define DIV_CLOCK_INIT 256
+#define TIMER_LOAD_VAL 0x0000FFFFL
+#endif
+/* The Integrator/CP timer1 is clocked at 1MHz
+ * can be divided by 16 or 256
+ * and can be set up as a 32-bit timer
+ */
+/* U-Boot expects a 32 bit timer, running at CONFIG_SYS_HZ */
+/* Keep total timer count to avoid losing decrements < div_timer */
+static unsigned long long total_count = 0;
+static unsigned long long lastdec; /* Timer reading at last call */
+/* Divisor applied to timer clock */
+static unsigned long long div_clock = DIV_CLOCK_INIT;
+static unsigned long long div_timer = 1; /* Divisor to convert timer reading
+ * change to U-Boot ticks
+ */
+/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
+static ulong timestamp; /* U-Boot ticks since startup */
+
+#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
+
+/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
+ * - unless otherwise stated
+ */
+
+/* starts up a counter
+ * - the Integrator/CP timer can be set up to issue an interrupt */
+int timer_init (void)
+{
+ /* Load timer with initial value */
+ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
+#ifdef CONFIG_ARCH_CINTEGRATOR
+ /* Set timer to be
+ * enabled 1
+ * periodic 1
+ * no interrupts 0
+ * X 0
+ * divider 1 00 == less rounding error
+ * 32 bit 1
+ * wrapping 0
+ */
+ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2;
+#else
+ /* Set timer to be
+ * enabled 1
+ * free-running 0
+ * XX 00
+ * divider 256 10
+ * XX 00
+ */
+ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
+#endif
+
+ /* init the timestamp */
+ total_count = 0ULL;
+ /* capure current decrementer value */
+ lastdec = READ_TIMER;
+ /* start "advancing" time stamp from 0 */
+ timestamp = 0L;
+
+ div_timer = CONFIG_SYS_HZ_CLOCK;
+ do_div(div_timer, CONFIG_SYS_HZ);
+ do_div(div_timer, div_clock);
+
+ return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+ulong get_timer (ulong base_ticks)
+{
+ return get_timer_masked () - base_ticks;
+}
+
+/* delay usec useconds */
+void __udelay (unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ /* Convert to U-Boot ticks */
+ tmo = usec * CONFIG_SYS_HZ;
+ tmo /= (1000000L);
+
+ tmp = get_timer_masked(); /* get current timestamp */
+ tmo += tmp; /* form target timestamp */
+
+ while (get_timer_masked () < tmo) {/* loop till event */
+ /*NOP*/;
+ }
+}
+
+/* converts the timer reading to U-Boot ticks */
+/* the timestamp is the number of ticks since reset */
+ulong get_timer_masked (void)
+{
+ /* get current count */
+ unsigned long long now = READ_TIMER;
+
+ if(now > lastdec) {
+ /* Must have wrapped */
+ total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
+ } else {
+ total_count += lastdec - now;
+ }
+ lastdec = now;
+
+ /* Reuse "now" */
+ now = total_count;
+ do_div(now, div_timer);
+ timestamp = now;
+
+ return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+ udelay(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * Return the timebase clock frequency
+ * i.e. how often the timer decrements
+ */
+ulong get_tbclk (void)
+{
+ unsigned long long tmp = CONFIG_SYS_HZ_CLOCK;
+
+ do_div(tmp, div_clock);
+
+ return tmp;
+}
diff --git a/board/armltd/versatile/MAINTAINERS b/board/armltd/versatile/MAINTAINERS
new file mode 100644
index 0000000..a56dd99
--- /dev/null
+++ b/board/armltd/versatile/MAINTAINERS
@@ -0,0 +1,8 @@
+VERSATILE BOARD
+#M: -
+S: Maintained
+F: board/armltd/versatile/
+F: include/configs/versatile.h
+F: configs/versatileab_defconfig
+F: configs/versatilepb_defconfig
+F: configs/versatileqemu_defconfig
diff --git a/board/armltd/versatile/Makefile b/board/armltd/versatile/Makefile
new file mode 100644
index 0000000..a09a0ae
--- /dev/null
+++ b/board/armltd/versatile/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := versatile.o
+obj-y += lowlevel_init.o
diff --git a/board/armltd/versatile/lowlevel_init.S b/board/armltd/versatile/lowlevel_init.S
new file mode 100644
index 0000000..902d646
--- /dev/null
+++ b/board/armltd/versatile/lowlevel_init.S
@@ -0,0 +1,18 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+ /* All done by Versatile's boot monitor! */
+ mov pc, lr
diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c
new file mode 100644
index 0000000..4e2d342
--- /dev/null
+++ b/board/armltd/versatile/versatile.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+ printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_early_init_f (void)
+{
+ /*
+ * set clock frequency:
+ * VERSATILE_REFCLK is 32KHz
+ * VERSATILE_TIMCLK is 1MHz
+ */
+ *(volatile unsigned int *)(VERSATILE_SCTL_BASE) |=
+ ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
+ (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
+
+ return 0;
+}
+
+int board_init (void)
+{
+ /* arch number of Versatile Board */
+#ifdef CONFIG_ARCH_VERSATILE_AB
+ gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_AB;
+#else
+ gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB;
+#endif
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x00000100;
+
+ gd->flags = 0;
+
+ icache_enable ();
+
+ return 0;
+}
+
+
+int misc_init_r (void)
+{
+ setenv("verify", "n");
+ return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/armltd/vexpress/Kconfig b/board/armltd/vexpress/Kconfig
new file mode 100644
index 0000000..2e15e0d
--- /dev/null
+++ b/board/armltd/vexpress/Kconfig
@@ -0,0 +1,38 @@
+if TARGET_VEXPRESS_CA15_TC2
+
+config SYS_BOARD
+ default "vexpress"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "vexpress_ca15_tc2"
+
+endif
+
+if TARGET_VEXPRESS_CA5X2
+
+config SYS_BOARD
+ default "vexpress"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "vexpress_ca5x2"
+
+endif
+
+if TARGET_VEXPRESS_CA9X4
+
+config SYS_BOARD
+ default "vexpress"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "vexpress_ca9x4"
+
+endif
diff --git a/board/armltd/vexpress/MAINTAINERS b/board/armltd/vexpress/MAINTAINERS
new file mode 100644
index 0000000..a6943d7
--- /dev/null
+++ b/board/armltd/vexpress/MAINTAINERS
@@ -0,0 +1,14 @@
+VEXPRESS BOARD
+#M: -
+S: Maintained
+F: board/armltd/vexpress/
+F: include/configs/vexpress_ca15_tc2.h
+F: configs/vexpress_ca15_tc2_defconfig
+
+VEXPRESS_CA5X2 BOARD
+#M: Matt Waddel <matt.waddel@linaro.org>
+S: Orphan (since 2014-08)
+F: include/configs/vexpress_ca5x2.h
+F: configs/vexpress_ca5x2_defconfig
+F: include/configs/vexpress_ca9x4.h
+F: configs/vexpress_ca9x4_defconfig
diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile
new file mode 100644
index 0000000..1dd6780
--- /dev/null
+++ b/board/armltd/vexpress/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := vexpress_common.o
diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c
new file mode 100644
index 0000000..cb2de2f
--- /dev/null
+++ b/board/armltd/vexpress/vexpress_common.c
@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/systimer.h>
+#include <asm/arch/sysctrl.h>
+#include <asm/arch/wdt.h>
+#include "../drivers/mmc/arm_pl180_mmci.h"
+
+static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
+static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
+
+static void flash__init(void);
+static void vexpress_timer_init(void);
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+ printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+static inline void delay(ulong loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+ gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
+ gd->flags = 0;
+
+ icache_enable();
+ flash__init();
+ vexpress_timer_init();
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+int cpu_mmc_init(bd_t *bis)
+{
+ int rc = 0;
+ (void) bis;
+#ifdef CONFIG_ARM_PL180_MMCI
+ struct pl180_mmc_host *host;
+
+ host = malloc(sizeof(struct pl180_mmc_host));
+ if (!host)
+ return -ENOMEM;
+ memset(host, 0, sizeof(*host));
+
+ strcpy(host->name, "MMC");
+ host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
+ host->pwr_init = INIT_PWR;
+ host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
+ host->voltages = VOLTAGE_WINDOW_MMC;
+ host->caps = 0;
+ host->clock_in = ARM_MCLK;
+ host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
+ host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
+ rc = arm_pl180_mmci_init(host);
+#endif
+ return rc;
+}
+
+static void flash__init(void)
+{
+ /* Setup the sytem control register to allow writing to flash */
+ writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
+ &sysctrl_base->scflashctrl);
+}
+
+int dram_init(void)
+{
+ gd->ram_size =
+ get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size =
+ get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size =
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+}
+
+/*
+ * Start timer:
+ * Setup a 32 bit timer, running at 1KHz
+ * Versatile Express Motherboard provides 1 MHz timer
+ */
+static void vexpress_timer_init(void)
+{
+ /*
+ * Set clock frequency in system controller:
+ * VEXPRESS_REFCLK is 32KHz
+ * VEXPRESS_TIMCLK is 1MHz
+ */
+ writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
+ SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
+ readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
+
+ /*
+ * Set Timer0 to be:
+ * Enabled, free running, no interrupt, 32-bit, wrapping
+ */
+ writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
+ writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
+ writel(SYSTIMER_EN | SYSTIMER_32BIT |
+ readl(&systimer_base->timer0control),
+ &systimer_base->timer0control);
+}
+
+int v2m_cfg_write(u32 devfn, u32 data)
+{
+ /* Configuration interface broken? */
+ u32 val;
+
+ devfn |= SYS_CFG_START | SYS_CFG_WRITE;
+
+ val = readl(V2M_SYS_CFGSTAT);
+ writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
+
+ writel(data, V2M_SYS_CFGDATA);
+ writel(devfn, V2M_SYS_CFGCTRL);
+
+ do {
+ val = readl(V2M_SYS_CFGSTAT);
+ } while (val == 0);
+
+ return !!(val & SYS_CFG_ERR);
+}
+
+/* Use the ARM Watchdog System to cause reset */
+void reset_cpu(ulong addr)
+{
+ if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
+ printf("Unable to reboot\n");
+}
+
+void lowlevel_init(void)
+{
+}
+
+ulong get_board_rev(void){
+ return readl((u32 *)SYS_ID);
+}
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+/* Setting the address at which secondary cores start from.
+ * Versatile Express uses one address for all cores, so ignore corenr
+ */
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ /* The SYSFLAGS register on VExpress needs to be cleared first
+ * by writing to the next address, since any writes to the address
+ * at offset 0 will only be ORed in
+ */
+ writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
+ writel(addr, CONFIG_SYSFLAGS_ADDR);
+}
+#endif
diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
new file mode 100644
index 0000000..7ebea63
--- /dev/null
+++ b/board/armltd/vexpress64/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VEXPRESS_AEMV8A
+
+config SYS_BOARD
+ default "vexpress64"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "vexpress_aemv8a"
+
+endif
diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS
new file mode 100644
index 0000000..66c8dff
--- /dev/null
+++ b/board/armltd/vexpress64/MAINTAINERS
@@ -0,0 +1,11 @@
+VEXPRESS64 BOARD
+M: David Feng <fenghua@phytium.com.cn>
+S: Maintained
+F: board/armltd/vexpress64/
+F: include/configs/vexpress_aemv8a.h
+F: configs/vexpress_aemv8a_defconfig
+
+VEXPRESS_AEMV8A_SEMI BOARD
+M: Linus Walleij <linus.walleij@linaro.org>
+S: Maintained
+F: configs/vexpress_aemv8a_semi_defconfig
diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile
new file mode 100644
index 0000000..e009141
--- /dev/null
+++ b/board/armltd/vexpress64/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := vexpress64.o
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
new file mode 100644
index 0000000..5897318
--- /dev/null
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ * Sharma Bhupesh <bhupesh.sharma@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <asm/semihosting.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ /*
+ * Clear spin table so that secondary processors
+ * observe the correct value after waken up from wfe.
+ */
+ *(unsigned long *)CPU_RELEASE_ADDR = 0;
+
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SEMIHOSTING
+ /*
+ * Please refer to doc/README.semihosting for a more complete
+ * description.
+ *
+ * We require that the board include file defines these env variables:
+ * - kernel_name
+ * - kernel_addr_r
+ * - initrd_name
+ * - initrd_addr_r
+ * - fdt_name
+ * - fdt_addr_r
+ *
+ * For the "fdt chosen" startup macro, this code will then define:
+ * - initrd_end (based on initrd_addr_r plus actual initrd_size)
+ *
+ * We will then load the kernel, initrd, and fdt into the specified
+ * locations in memory in a similar way that the ATF fastmodel code
+ * uses semihosting calls to load other boot stages and u-boot itself.
+ */
+
+ /* Env variable strings */
+ char *kernel_name = getenv("kernel_name");
+ char *kernel_addr_str = getenv("kernel_addr_r");
+ char *initrd_name = getenv("initrd_name");
+ char *initrd_addr_str = getenv("initrd_addr_r");
+ char *fdt_name = getenv("fdt_name");
+ char *fdt_addr_str = getenv("fdt_addr_r");
+ char initrd_end_str[64];
+
+ /* Actual addresses converted from env variables */
+ void *kernel_addr_r;
+ void *initrd_addr_r;
+ void *fdt_addr_r;
+
+ /* Actual initrd base and size */
+ unsigned long initrd_base;
+ unsigned long initrd_size;
+
+ /* Space available */
+ int avail;
+
+ /* Make sure the environment variables needed are set */
+ if (!(kernel_addr_str && initrd_addr_str && fdt_addr_str)) {
+ printf("%s: Define {kernel/initrd/fdt}_addr_r\n", __func__);
+ return -1;
+ }
+ if (!(kernel_name && initrd_name && fdt_name)) {
+ printf("%s: Define {kernel/initrd/fdt}_name\n", __func__);
+ return -1;
+ }
+
+ /* Get exact initrd_size */
+ initrd_size = smh_len(initrd_name);
+ if (initrd_size == -1) {
+ printf("%s: Can't get file size for \'%s\'\n", __func__,
+ initrd_name);
+ return -1;
+ }
+
+ /* Set initrd_end */
+ initrd_base = simple_strtoul(initrd_addr_str, NULL, 16);
+ initrd_addr_r = (void *)initrd_base;
+ sprintf(initrd_end_str, "0x%lx", initrd_base + initrd_size - 1);
+ setenv("initrd_end", initrd_end_str);
+
+ /* Load kernel to memory */
+ fdt_addr_r = (void *)simple_strtoul(fdt_addr_str, NULL, 16);
+ kernel_addr_r = (void *)simple_strtoul(kernel_addr_str, NULL, 16);
+
+ /*
+ * The kernel must be lower in memory than fdt and loading the
+ * kernel must not trample the fdt or vice versa.
+ */
+ avail = fdt_addr_r - kernel_addr_r;
+ if (avail < 0) {
+ printf("%s: fdt must be after kernel\n", __func__);
+ return -1;
+ }
+ smh_load(kernel_name, kernel_addr_r, avail, 1);
+
+ /* Load fdt to memory */
+ smh_load(fdt_name, fdt_addr_r, 0x20000, 1);
+
+ /* Load initrd to memory */
+ smh_load(initrd_name, initrd_addr_r, initrd_size, 1);
+
+#endif /* CONFIG_SEMIHOSTING */
+ return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
+
+/*
+ * Board specific ethernet initialization routine.
+ */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
diff --git a/board/astro/mcf5373l/Kconfig b/board/astro/mcf5373l/Kconfig
new file mode 100644
index 0000000..a7c04ce
--- /dev/null
+++ b/board/astro/mcf5373l/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ASTRO_MCF5373L
+
+config SYS_CPU
+ default "mcf532x"
+
+config SYS_BOARD
+ default "mcf5373l"
+
+config SYS_VENDOR
+ default "astro"
+
+config SYS_CONFIG_NAME
+ default "astro_mcf5373l"
+
+endif
diff --git a/board/astro/mcf5373l/MAINTAINERS b/board/astro/mcf5373l/MAINTAINERS
new file mode 100644
index 0000000..6c23da7
--- /dev/null
+++ b/board/astro/mcf5373l/MAINTAINERS
@@ -0,0 +1,6 @@
+MCF5373L BOARD
+M: Wolfgang Wegner <w.wegner@astro-kom.de>
+S: Maintained
+F: board/astro/mcf5373l/
+F: include/configs/astro_mcf5373l.h
+F: configs/astro_mcf5373l_defconfig
diff --git a/board/astro/mcf5373l/Makefile b/board/astro/mcf5373l/Makefile
new file mode 100644
index 0000000..005d036
--- /dev/null
+++ b/board/astro/mcf5373l/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = mcf5373l.o fpga.o
diff --git a/board/astro/mcf5373l/astro.h b/board/astro/mcf5373l/astro.h
new file mode 100644
index 0000000..b55a6f7
--- /dev/null
+++ b/board/astro/mcf5373l/astro.h
@@ -0,0 +1,44 @@
+#ifndef __ASTRO_H__
+#define __ASTRO_H__
+
+/* in mcf5373l.c */
+int rs_serial_init(int port, int baud);
+void astro_put_char(char ch);
+int astro_is_char(void);
+int astro_get_char(void);
+
+/* in fpga.c */
+int astro5373l_altera_load(void);
+int astro5373l_xilinx_load(void);
+
+/* data structures used for communication (update.c) */
+typedef struct card_id {
+ char card_type;
+ char hardware_version;
+ char software_version;
+ char software_subversion; /* " ","a".."z" */
+ char fpga_version_altera;
+ char fpga_version_xilinx;
+} card_id_t;
+
+typedef struct {
+ unsigned char mode;
+ unsigned char deviation;
+ unsigned short freq;
+} __attribute__ ((packed)) output_params_t;
+
+typedef struct {
+ unsigned short satfreq;
+ unsigned char satdatallg;
+ unsigned short symbolrate;
+ unsigned char viterbirate;
+ unsigned char symbolrate_l;
+ output_params_t output_params;
+ unsigned char reserve;
+ unsigned char card_error;
+ unsigned short dummy_ts_id;
+ unsigned char dummy_pat_ver;
+ unsigned char dummy_sdt_ver;
+} __attribute__ ((packed)) parameters_t;
+
+#endif /* __ASTRO_H__ */
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
new file mode 100644
index 0000000..d1110df
--- /dev/null
+++ b/board/astro/mcf5373l/fpga.c
@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH,
+ * w.wegner@astro-kom.de
+ *
+ * based on the files by
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ * and
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
+
+#include <common.h>
+#include <watchdog.h>
+#include <altera.h>
+#include <ACEX1K.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/immap_5329.h>
+#include <asm/io.h>
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int altera_pre_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+ unsigned char tmp_char;
+ unsigned short tmp_short;
+
+ /* first, set the required pins to GPIO function */
+ /* PAR_T0IN -> GPIO */
+ tmp_char = readb(&gpiop->par_timer);
+ tmp_char &= 0xfc;
+ writeb(tmp_char, &gpiop->par_timer);
+ /* all QSPI pins -> GPIO */
+ writew(0x0000, &gpiop->par_qspi);
+ /* U0RTS, U0CTS -> GPIO */
+ tmp_short = __raw_readw(&gpiop->par_uart);
+ tmp_short &= 0xfff3;
+ __raw_writew(tmp_short, &gpiop->par_uart);
+ /* all PWM pins -> GPIO */
+ writeb(0x00, &gpiop->par_pwm);
+ /* next, set data direction registers */
+ writeb(0x01, &gpiop->pddr_timer);
+ writeb(0x25, &gpiop->pddr_qspi);
+ writeb(0x0c, &gpiop->pddr_uart);
+ writeb(0x04, &gpiop->pddr_pwm);
+
+ /* ensure other SPI peripherals are deselected */
+ writeb(0x08, &gpiop->ppd_uart);
+ writeb(0x38, &gpiop->ppd_qspi);
+
+ /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
+ writeb(0xFB, &gpiop->pclrr_uart);
+ /* enable Altera configuration by clearing QSPI_CS2 and DT0IN */
+ writeb(0xFE, &gpiop->pclrr_timer);
+ writeb(0xDF, &gpiop->pclrr_qspi);
+ return FPGA_SUCCESS;
+}
+
+/* Set the state of CONFIG Pin */
+int altera_config_fn(int assert_config, int flush, int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ if (assert_config)
+ writeb(0x04, &gpiop->ppd_uart);
+ else
+ writeb(0xFB, &gpiop->pclrr_uart);
+ return FPGA_SUCCESS;
+}
+
+/* Returns the state of STATUS Pin */
+int altera_status_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ if (readb(&gpiop->ppd_pwm) & 0x08)
+ return FPGA_FAIL;
+ return FPGA_SUCCESS;
+}
+
+/* Returns the state of CONF_DONE Pin */
+int altera_done_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ if (readb(&gpiop->ppd_pwm) & 0x20)
+ return FPGA_FAIL;
+ return FPGA_SUCCESS;
+}
+
+/*
+ * writes the complete buffer to the FPGA
+ * writing the complete buffer in one function is much faster,
+ * then calling it for every bit
+ */
+int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
+{
+ size_t bytecount = 0;
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+ unsigned char *data = (unsigned char *)buf;
+ unsigned char val = 0;
+ int i;
+ int len_40 = len / 40;
+
+ while (bytecount < len) {
+ val = data[bytecount++];
+ i = 8;
+ do {
+ writeb(0xFB, &gpiop->pclrr_qspi);
+ if (val & 0x01)
+ writeb(0x01, &gpiop->ppd_qspi);
+ else
+ writeb(0xFE, &gpiop->pclrr_qspi);
+ writeb(0x04, &gpiop->ppd_qspi);
+ val >>= 1;
+ i--;
+ } while (i > 0);
+
+ if (bytecount % len_40 == 0) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ WATCHDOG_RESET();
+#endif
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ putc('.'); /* let them know we are alive */
+#endif
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+ if (ctrlc())
+ return FPGA_FAIL;
+#endif
+ }
+ }
+ return FPGA_SUCCESS;
+}
+
+/* called, when programming is aborted */
+int altera_abort_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ writeb(0x20, &gpiop->ppd_qspi);
+ writeb(0x08, &gpiop->ppd_uart);
+ return FPGA_SUCCESS;
+}
+
+/* called, when programming was succesful */
+int altera_post_fn(int cookie)
+{
+ return altera_abort_fn(cookie);
+}
+
+/*
+ * Note that these are pointers to code that is in Flash. They will be
+ * relocated at runtime.
+ * FIXME: relocation not yet working for coldfire, see below!
+ */
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+ altera_pre_fn,
+ altera_config_fn,
+ altera_status_fn,
+ altera_done_fn,
+ altera_write_fn,
+ altera_abort_fn,
+ altera_post_fn
+};
+
+Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = {
+ {Altera_CYC2,
+ passive_serial,
+ 85903,
+ (void *)&altera_fns,
+ NULL,
+ 0}
+};
+
+/* Initialize the fpga. Return 1 on success, 0 on failure. */
+int astro5373l_altera_load(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+ /*
+ * I did not yet manage to get relocation work properly,
+ * so set stuff here instead of static initialisation:
+ */
+ altera_fns.pre = altera_pre_fn;
+ altera_fns.config = altera_config_fn;
+ altera_fns.status = altera_status_fn;
+ altera_fns.done = altera_done_fn;
+ altera_fns.write = altera_write_fn;
+ altera_fns.abort = altera_abort_fn;
+ altera_fns.post = altera_post_fn;
+ altera_fpga[i].iface_fns = (void *)&altera_fns;
+ fpga_add(fpga_altera, &altera_fpga[i]);
+ }
+ return 1;
+}
+
+/* Set the FPGA's PROG_B line to the specified level */
+int xilinx_pgm_config_fn(int assert, int flush, int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ if (assert)
+ writeb(0xFB, &gpiop->pclrr_uart);
+ else
+ writeb(0x04, &gpiop->ppd_uart);
+ return assert;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
+ * asserted (low).
+ */
+int xilinx_init_config_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ return (readb(&gpiop->ppd_pwm) & 0x08) == 0;
+}
+
+/* Test the state of the active-high FPGA DONE pin */
+int xilinx_done_config_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ return (readb(&gpiop->ppd_pwm) & 0x20) >> 5;
+}
+
+/* Abort an FPGA operation */
+int xilinx_abort_config_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+ /* ensure all SPI peripherals and FPGAs are deselected */
+ writeb(0x08, &gpiop->ppd_uart);
+ writeb(0x01, &gpiop->ppd_timer);
+ writeb(0x38, &gpiop->ppd_qspi);
+ return FPGA_FAIL;
+}
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+int xilinx_pre_config_fn(int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+ unsigned char tmp_char;
+ unsigned short tmp_short;
+
+ /* first, set the required pins to GPIO function */
+ /* PAR_T0IN -> GPIO */
+ tmp_char = readb(&gpiop->par_timer);
+ tmp_char &= 0xfc;
+ writeb(tmp_char, &gpiop->par_timer);
+ /* all QSPI pins -> GPIO */
+ writew(0x0000, &gpiop->par_qspi);
+ /* U0RTS, U0CTS -> GPIO */
+ tmp_short = __raw_readw(&gpiop->par_uart);
+ tmp_short &= 0xfff3;
+ __raw_writew(tmp_short, &gpiop->par_uart);
+ /* all PWM pins -> GPIO */
+ writeb(0x00, &gpiop->par_pwm);
+ /* next, set data direction registers */
+ writeb(0x01, &gpiop->pddr_timer);
+ writeb(0x25, &gpiop->pddr_qspi);
+ writeb(0x0c, &gpiop->pddr_uart);
+ writeb(0x04, &gpiop->pddr_pwm);
+
+ /* ensure other SPI peripherals are deselected */
+ writeb(0x08, &gpiop->ppd_uart);
+ writeb(0x38, &gpiop->ppd_qspi);
+ writeb(0x01, &gpiop->ppd_timer);
+
+ /* CONFIG = 0, STATUS = 0 -> FPGA in reset state */
+ writeb(0xFB, &gpiop->pclrr_uart);
+ /* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */
+ writeb(0xF7, &gpiop->pclrr_uart);
+ writeb(0xDF, &gpiop->pclrr_qspi);
+ return 0;
+}
+
+/*
+ * FPGA post configuration function. Should perform a test if FPGA is running.
+ */
+int xilinx_post_config_fn(int cookie)
+{
+ int rc = 0;
+
+ /*
+ * no test yet
+ */
+ return rc;
+}
+
+int xilinx_clk_config_fn(int assert_clk, int flush, int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ if (assert_clk)
+ writeb(0x04, &gpiop->ppd_qspi);
+ else
+ writeb(0xFB, &gpiop->pclrr_qspi);
+ return assert_clk;
+}
+
+int xilinx_wr_config_fn(int assert_write, int flush, int cookie)
+{
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+
+ if (assert_write)
+ writeb(0x01, &gpiop->ppd_qspi);
+ else
+ writeb(0xFE, &gpiop->pclrr_qspi);
+ return assert_write;
+}
+
+int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
+{
+ size_t bytecount = 0;
+ gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
+ unsigned char *data = (unsigned char *)buf;
+ unsigned char val = 0;
+ int i;
+ int len_40 = len / 40;
+
+ for (bytecount = 0; bytecount < len; bytecount++) {
+ val = *(data++);
+ for (i = 8; i > 0; i--) {
+ writeb(0xFB, &gpiop->pclrr_qspi);
+ if (val & 0x80)
+ writeb(0x01, &gpiop->ppd_qspi);
+ else
+ writeb(0xFE, &gpiop->pclrr_qspi);
+ writeb(0x04, &gpiop->ppd_qspi);
+ val <<= 1;
+ }
+ if (bytecount % len_40 == 0) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ WATCHDOG_RESET();
+#endif
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ putc('.'); /* let them know we are alive */
+#endif
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+ if (ctrlc())
+ return FPGA_FAIL;
+#endif
+ }
+ }
+ return FPGA_SUCCESS;
+}
+
+/*
+ * Note that these are pointers to code that is in Flash. They will be
+ * relocated at runtime.
+ * FIXME: relocation not yet working for coldfire, see below!
+ */
+xilinx_spartan3_slave_serial_fns xilinx_fns = {
+ xilinx_pre_config_fn,
+ xilinx_pgm_config_fn,
+ xilinx_clk_config_fn,
+ xilinx_init_config_fn,
+ xilinx_done_config_fn,
+ xilinx_wr_config_fn,
+ 0,
+ xilinx_fastwr_config_fn
+};
+
+xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+ {xilinx_spartan3,
+ slave_serial,
+ XILINX_XC3S4000_SIZE,
+ (void *)&xilinx_fns,
+ 0,
+ &spartan3_op}
+};
+
+/* Initialize the fpga. Return 1 on success, 0 on failure. */
+int astro5373l_xilinx_load(void)
+{
+ int i;
+
+ fpga_init();
+
+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+ /*
+ * I did not yet manage to get relocation work properly,
+ * so set stuff here instead of static initialisation:
+ */
+ xilinx_fns.pre = xilinx_pre_config_fn;
+ xilinx_fns.pgm = xilinx_pgm_config_fn;
+ xilinx_fns.clk = xilinx_clk_config_fn;
+ xilinx_fns.init = xilinx_init_config_fn;
+ xilinx_fns.done = xilinx_done_config_fn;
+ xilinx_fns.wr = xilinx_wr_config_fn;
+ xilinx_fns.bwr = xilinx_fastwr_config_fn;
+ xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
+ fpga_add(fpga_xilinx, &xilinx_fpga[i]);
+ }
+ return 1;
+}
diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c
new file mode 100644
index 0000000..7ec7cb3
--- /dev/null
+++ b/board/astro/mcf5373l/mcf5373l.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/m5329.h>
+#include <asm/immap_5329.h>
+#include <asm/io.h>
+
+/* needed for astro bus: */
+#include <asm/uart.h>
+#include "astro.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+extern void uart_port_conf(void);
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("ASTRO MCF5373L (Urmel) Board\n");
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+ sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
+
+ /*
+ * GPIO configuration for bus should be set correctly from reset,
+ * so we do not care! First, set up address space: at this point,
+ * we should be running from internal SRAM;
+ * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
+ * and do not care where it is
+ */
+ __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
+ &sdp->cs0);
+ __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
+ &sdp->cs1);
+ /*
+ * I am not sure from the data sheet, but it seems burst length
+ * has to be 8 for the 16 bit data bus we use;
+ * so these values are for BL = 8
+ */
+ __raw_writel(0x33211530, &sdp->cfg1);
+ __raw_writel(0x56570000, &sdp->cfg2);
+ /* send PrechargeALL, REF and IREF remain cleared! */
+ __raw_writel(0xE1462C02, &sdp->ctrl);
+ udelay(1);
+ /* refresh SDRAM twice */
+ __raw_writel(0xE1462C04, &sdp->ctrl);
+ udelay(1);
+ __raw_writel(0xE1462C04, &sdp->ctrl);
+ /* init MR */
+ __raw_writel(0x008D0000, &sdp->mode);
+ /* initialize EMR */
+ __raw_writel(0x80010000, &sdp->mode);
+ /* wait until DLL is locked */
+ udelay(1);
+ /*
+ * enable automatic refresh, lock mode register,
+ * clear iref and ipall
+ */
+ __raw_writel(0x71462C00, &sdp->ctrl);
+ /* Dummy write to start SDRAM */
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+#endif
+
+ /*
+ * for get_ram_size() to work, both CS areas have to be
+ * configured, i.e. CS1 has to be explicitely disabled, else
+ * probing for memory will cause the SDRAM bus to hang!
+ * (Do not rely on the SDCS register(s) being set to 0x00000000
+ * during reset as stated in the data sheet.)
+ */
+ return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ 0x80000000 - CONFIG_SYS_SDRAM_BASE);
+}
+
+#define UART_BASE MMAP_UART0
+int rs_serial_init(int port, int baud)
+{
+ uart_t *uart;
+ u32 counter;
+
+ switch (port) {
+ case 0:
+ uart = (uart_t *)(MMAP_UART0);
+ break;
+ case 1:
+ uart = (uart_t *)(MMAP_UART1);
+ break;
+ case 2:
+ uart = (uart_t *)(MMAP_UART2);
+ break;
+ default:
+ uart = (uart_t *)(MMAP_UART0);
+ }
+
+ uart_port_conf();
+
+ /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
+ writeb(UART_UCR_RESET_RX, &uart->ucr);
+ writeb(UART_UCR_RESET_TX, &uart->ucr);
+ writeb(UART_UCR_RESET_ERROR, &uart->ucr);
+ writeb(UART_UCR_RESET_MR, &uart->ucr);
+ __asm__ ("nop");
+
+ writeb(0, &uart->uimr);
+
+ /* write to CSR: RX/TX baud rate from timers */
+ writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
+
+ writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
+ writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
+
+ /* Setting up BaudRate */
+ counter = (u32) (gd->bus_clk / (baud));
+ counter >>= 5;
+
+ /* write to CTUR: divide counter upper byte */
+ writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);
+ /* write to CTLR: divide counter lower byte */
+ writeb((u8) (counter & 0x00ff), &uart->ubg2);
+
+ writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
+
+ return 0;
+}
+
+void astro_put_char(char ch)
+{
+ uart_t *uart;
+ unsigned long timer;
+
+ uart = (uart_t *)(MMAP_UART0);
+ /*
+ * Wait for last character to go. Timeout of 6ms should
+ * be enough for our lowest baud rate of 2400.
+ */
+ timer = get_timer(0);
+ while (get_timer(timer) < 6) {
+ if (readb(&uart->usr) & UART_USR_TXRDY)
+ break;
+ }
+ writeb(ch, &uart->utb);
+
+ return;
+}
+
+int astro_is_char(void)
+{
+ uart_t *uart;
+
+ uart = (uart_t *)(MMAP_UART0);
+ return readb(&uart->usr) & UART_USR_RXRDY;
+}
+
+int astro_get_char(void)
+{
+ uart_t *uart;
+
+ uart = (uart_t *)(MMAP_UART0);
+ while (!(readb(&uart->usr) & UART_USR_RXRDY)) ;
+ return readb(&uart->urb);
+}
+
+int misc_init_r(void)
+{
+ int retval = 0;
+
+ puts("Configure Xilinx FPGA...");
+ retval = astro5373l_xilinx_load();
+ if (!retval) {
+ puts("failed!\n");
+ return retval;
+ }
+ puts("done\n");
+
+ puts("Configure Altera FPGA...");
+ retval = astro5373l_altera_load();
+ if (!retval) {
+ puts("failed!\n");
+ return retval;
+ }
+ puts("done\n");
+
+ return retval;
+}
diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds
new file mode 100644
index 0000000..8ef0620
--- /dev/null
+++ b/board/astro/mcf5373l/u-boot.lds
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf532x/start.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss*)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/atmark-techno/armadillo-800eva/Kconfig b/board/atmark-techno/armadillo-800eva/Kconfig
new file mode 100644
index 0000000..cd37dd4
--- /dev/null
+++ b/board/atmark-techno/armadillo-800eva/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ARMADILLO_800EVA
+
+config SYS_BOARD
+ default "armadillo-800eva"
+
+config SYS_VENDOR
+ default "atmark-techno"
+
+config SYS_CONFIG_NAME
+ default "armadillo-800eva"
+
+endif
diff --git a/board/atmark-techno/armadillo-800eva/MAINTAINERS b/board/atmark-techno/armadillo-800eva/MAINTAINERS
new file mode 100644
index 0000000..6f547d8
--- /dev/null
+++ b/board/atmark-techno/armadillo-800eva/MAINTAINERS
@@ -0,0 +1,6 @@
+ARMADILLO-800EVA BOARD
+M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+S: Maintained
+F: board/atmark-techno/armadillo-800eva/
+F: include/configs/armadillo-800eva.h
+F: configs/armadillo-800eva_defconfig
diff --git a/board/atmark-techno/armadillo-800eva/Makefile b/board/atmark-techno/armadillo-800eva/Makefile
new file mode 100644
index 0000000..2743809
--- /dev/null
+++ b/board/atmark-techno/armadillo-800eva/Makefile
@@ -0,0 +1,20 @@
+#
+# Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+obj-y += armadillo-800eva.o
+
diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
new file mode 100644
index 0000000..0e9c222
--- /dev/null
+++ b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+
+#define s_init_wait(cnt) \
+ ({ \
+ volatile u32 i = 0x10000 * cnt; \
+ while (i > 0) \
+ i--; \
+ })
+
+#define USBCR1 0xE605810A
+
+void s_init(void)
+{
+ struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE;
+ struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE;
+ struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE;
+ struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE;
+ struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE;
+ struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE;
+
+ /* Watchdog init */
+ writew(0xA500, &rwdt0->rwtcsra0);
+ writew(0xA500, &rwdt1->rwtcsra0);
+
+ /* CPG */
+ writel(0xFF800080, &cpg->rmstpcr4);
+ writel(0xFF800080, &cpg->smstpcr4);
+
+ /* USB clock */
+ writel(0x00000080, &cpg->usbckcr);
+ s_init_wait(1);
+
+ /* USBCR1 */
+ writew(0x0710, USBCR1);
+
+ /* FRQCR */
+ writel(0x00000000, &cpg->frqcrb);
+ writel(0x62030533, &cpg->frqcra);
+ writel(0x208A354E, &cpg->frqcrc);
+ writel(0x80331050, &cpg->frqcrb);
+ s_init_wait(1);
+
+ writel(0x00000000, &cpg->frqcrd);
+ s_init_wait(1);
+
+ /* SUBClk */
+ writel(0x0000010B, &cpg->subckcr);
+
+ /* PLL */
+ writel(0x00004004, &cpg->pllc01cr);
+ s_init_wait(1);
+
+ writel(0xa0000000, &cpg->pllc2cr);
+ s_init_wait(2);
+
+ /* BSC */
+ writel(0x0000001B, &bsc->cmncr);
+
+ writel(0x20000000, &dbsc->dbcmd);
+ writel(0x10009C40, &dbsc->dbcmd);
+ s_init_wait(1);
+
+ writel(0x00000007, &dbsc->dbkind);
+ writel(0x0E030A02, &dbsc->dbconf0);
+ writel(0x00000001, &dbsc->dbphytype);
+ writel(0x00000000, &dbsc->dbbl);
+ writel(0x00000006, &dbsc->dbtr0);
+ writel(0x00000005, &dbsc->dbtr1);
+ writel(0x00000000, &dbsc->dbtr2);
+ writel(0x00000006, &dbsc->dbtr3);
+ writel(0x00080006, &dbsc->dbtr4);
+ writel(0x00000015, &dbsc->dbtr5);
+ writel(0x0000000f, &dbsc->dbtr6);
+ writel(0x00000004, &dbsc->dbtr7);
+ writel(0x00000018, &dbsc->dbtr8);
+ writel(0x00000006, &dbsc->dbtr9);
+ writel(0x00000006, &dbsc->dbtr10);
+ writel(0x0000000F, &dbsc->dbtr11);
+ writel(0x0000000D, &dbsc->dbtr12);
+ writel(0x000000A0, &dbsc->dbtr13);
+ writel(0x000A0003, &dbsc->dbtr14);
+ writel(0x00000003, &dbsc->dbtr15);
+ writel(0x40005005, &dbsc->dbtr16);
+ writel(0x0C0C0000, &dbsc->dbtr17);
+ writel(0x00000200, &dbsc->dbtr18);
+ writel(0x00000040, &dbsc->dbtr19);
+ writel(0x00000001, &dbsc->dbrnk0);
+ writel(0x00000110, &dbsc->dbdficnt);
+ writel(0x00000101, &ddrp->funcctrl);
+ writel(0x00000001, &ddrp->dllctrl);
+ writel(0x00000186, &ddrp->zqcalctrl);
+ writel(0xB3440051, &ddrp->zqodtctrl);
+ writel(0x94449443, &ddrp->rdctrl);
+ writel(0x000000C0, &ddrp->rdtmg);
+ writel(0x00000101, &ddrp->fifoinit);
+ writel(0x02060506, &ddrp->outctrl);
+ writel(0x00004646, &ddrp->dqcalofs1);
+ writel(0x00004646, &ddrp->dqcalofs2);
+ writel(0x800000aa, &ddrp->dqcalexp);
+ writel(0x00000000, &ddrp->dllctrl);
+ writel(0x00000000, DDRPNCNT);
+
+ writel(0x0000000C, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00000002, DDRPNCNT);
+
+ writel(0x0000000C, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00000187, &ddrp->zqcalctrl);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00000010, &dbsc->dbdficnt);
+ writel(0x02060507, &ddrp->outctrl);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x21009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x00009C40, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x11000044, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x2A000000, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x2B000000, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+
+ writel(0x29000004, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+
+ writel(0x28001520, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x03000200, &dbsc->dbcmd);
+ readl(&dbsc->dbwait);
+ s_init_wait(1);
+
+ writel(0x000001FF, &dbsc->dbrfcnf0);
+ writel(0x00010C30, &dbsc->dbrfcnf1);
+ writel(0x00000000, &dbsc->dbrfcnf2);
+
+ writel(0x00000001, &dbsc->dbrfen);
+ writel(0x00000001, &dbsc->dbacen);
+
+ /* BSC */
+ writel(0x00410400, &bsc->cs0bcr);
+ writel(0x00410400, &bsc->cs2bcr);
+ writel(0x00410400, &bsc->cs5bbcr);
+ writel(0x02CB0400, &bsc->cs6abcr);
+
+ writel(0x00000440, &bsc->cs0wcr);
+ writel(0x00000440, &bsc->cs2wcr);
+ writel(0x00000240, &bsc->cs5bwcr);
+ writel(0x00000240, &bsc->cs6awcr);
+
+ writel(0x00000005, &bsc->rbwtcnt);
+ writel(0x00000002, &bsc->cs0wcr2);
+ writel(0x00000002, &bsc->cs2wcr2);
+ writel(0x00000002, &bsc->cs4wcr2);
+}
+
+#define GPIO_ICCR (0xE60581A0)
+#define ICCR_15BIT (1 << 15) /* any time 1 */
+#define IIC0_CONTA (1 << 7)
+#define IIC0_CONTB (1 << 6)
+#define IIC1_CONTA (1 << 5)
+#define IIC1_CONTB (1 << 4)
+#define IIC0_PS33E (1 << 1)
+#define IIC1_PS33E (1 << 0)
+#define GPIO_ICCR_DATA \
+ (ICCR_15BIT | \
+ IIC0_CONTA | IIC0_CONTB | IIC1_CONTA | \
+ IIC1_CONTB | IIC0_PS33E | IIC1_PS33E)
+
+#define MSTPCR1 0xE6150134
+#define TMU0_MSTP125 (1 << 25)
+#define I2C0_MSTP116 (1 << 16)
+
+#define MSTPCR3 0xE615013C
+#define I2C1_MSTP323 (1 << 23)
+#define GETHER_MSTP309 (1 << 9)
+
+#define GPIO_SCIFA1_TXD (0xE60520C4)
+#define GPIO_SCIFA1_RXD (0xE60520C3)
+
+int board_early_init_f(void)
+{
+ /* TMU */
+ clrbits_le32(MSTPCR1, TMU0_MSTP125);
+
+ /* GETHER */
+ clrbits_le32(MSTPCR3, GETHER_MSTP309);
+
+ /* I2C 0/1 */
+ clrbits_le32(MSTPCR1, I2C0_MSTP116);
+ clrbits_le32(MSTPCR3, I2C1_MSTP323);
+
+ /* SCIFA1 */
+ writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */
+ writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */
+
+ /* IICCR */
+ writew(GPIO_ICCR_DATA, GPIO_ICCR);
+
+ return 0;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+ /* board id for linux */
+ gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO_800EVA;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
+
+ /* Init PFC controller */
+ r8a7740_pinmux_init();
+
+ /* GETHER Enable */
+ gpio_request(GPIO_FN_ET_CRS, NULL);
+ gpio_request(GPIO_FN_ET_MDC, NULL);
+ gpio_request(GPIO_FN_ET_MDIO, NULL);
+ gpio_request(GPIO_FN_ET_TX_ER, NULL);
+ gpio_request(GPIO_FN_ET_RX_ER, NULL);
+ gpio_request(GPIO_FN_ET_ERXD0, NULL);
+ gpio_request(GPIO_FN_ET_ERXD1, NULL);
+ gpio_request(GPIO_FN_ET_ERXD2, NULL);
+ gpio_request(GPIO_FN_ET_ERXD3, NULL);
+ gpio_request(GPIO_FN_ET_TX_CLK, NULL);
+ gpio_request(GPIO_FN_ET_TX_EN, NULL);
+ gpio_request(GPIO_FN_ET_ETXD0, NULL);
+ gpio_request(GPIO_FN_ET_ETXD1, NULL);
+ gpio_request(GPIO_FN_ET_ETXD2, NULL);
+ gpio_request(GPIO_FN_ET_ETXD3, NULL);
+ gpio_request(GPIO_FN_ET_PHY_INT, NULL);
+ gpio_request(GPIO_FN_ET_COL, NULL);
+ gpio_request(GPIO_FN_ET_RX_DV, NULL);
+ gpio_request(GPIO_FN_ET_RX_CLK, NULL);
+
+ gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
+ gpio_direction_output(GPIO_PORT18, 1);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_RMOBILE_BOARD_STRING
+};
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/atmel/at91rm9200ek/Kconfig b/board/atmel/at91rm9200ek/Kconfig
new file mode 100644
index 0000000..bad4a37
--- /dev/null
+++ b/board/atmel/at91rm9200ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AT91RM9200EK
+
+config SYS_BOARD
+ default "at91rm9200ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "at91rm9200ek"
+
+endif
diff --git a/board/atmel/at91rm9200ek/MAINTAINERS b/board/atmel/at91rm9200ek/MAINTAINERS
new file mode 100644
index 0000000..d2a479b
--- /dev/null
+++ b/board/atmel/at91rm9200ek/MAINTAINERS
@@ -0,0 +1,7 @@
+AT91RM9200EK BOARD
+M: Andreas Bießmann <andreas.devel@gmail.com>
+S: Maintained
+F: board/atmel/at91rm9200ek/
+F: include/configs/at91rm9200ek.h
+F: configs/at91rm9200ek_defconfig
+F: configs/at91rm9200ek_ram_defconfig
diff --git a/board/atmel/at91rm9200ek/Makefile b/board/atmel/at91rm9200ek/Makefile
new file mode 100644
index 0000000..0530830
--- /dev/null
+++ b/board/atmel/at91rm9200ek/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += at91rm9200ek.o
+obj-y += led.o
diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c
new file mode 100644
index 0000000..64ab572
--- /dev/null
+++ b/board/atmel/at91rm9200ek/at91rm9200ek.c
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2010 Andreas Bießmann <andreas.devel@gmail.com>
+ *
+ * derived from previous work
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+int board_init(void)
+{
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+
+ /*
+ * Correct IRDA resistor problem
+ * Set PA23_TXD in Output
+ */
+ writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
+
+ /* arch number of AT91RM9200EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ at91_seriald_hw_init();
+ return 0;
+}
+
+int dram_init (void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+ return at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
+}
+#endif
diff --git a/board/atmel/at91rm9200ek/led.c b/board/atmel/at91rm9200ek/led.c
new file mode 100644
index 0000000..6761b14
--- /dev/null
+++ b/board/atmel/at91rm9200ek/led.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2006
+ * Atmel Nordic AB <www.atmel.com>
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * (C) Copyright 2010
+ * Andreas Bießmann <andreas.devel@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+#include <status_led.h>
+
+/* bit mask in PIO port B */
+#define GREEN_LED (1<<0)
+#define YELLOW_LED (1<<1)
+#define RED_LED (1<<2)
+
+void green_led_on(void)
+{
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+ writel(GREEN_LED, &pio->piob.codr);
+}
+
+void yellow_led_on(void)
+{
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+ writel(YELLOW_LED, &pio->piob.codr);
+}
+
+void red_led_on(void)
+{
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+ writel(RED_LED, &pio->piob.codr);
+}
+
+void green_led_off(void)
+{
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+ writel(GREEN_LED, &pio->piob.sodr);
+}
+
+void yellow_led_off(void)
+{
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+ writel(YELLOW_LED, &pio->piob.sodr);
+}
+
+void red_led_off(void)
+{
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+ writel(RED_LED, &pio->piob.sodr);
+}
+
+void coloured_LED_init (void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+ at91_pio_t *pio = (at91_pio_t *)ATMEL_BASE_PIO;
+
+ /* Enable PIOB clock */
+ writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
+
+ /* Disable peripherals on LEDs */
+ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
+ /* Enable pins as outputs */
+ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
+ /* Turn all LEDs OFF */
+ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
+}
diff --git a/board/atmel/at91sam9260ek/Kconfig b/board/atmel/at91sam9260ek/Kconfig
new file mode 100644
index 0000000..fe00ed5
--- /dev/null
+++ b/board/atmel/at91sam9260ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AT91SAM9260EK
+
+config SYS_BOARD
+ default "at91sam9260ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "at91sam9260ek"
+
+endif
diff --git a/board/atmel/at91sam9260ek/MAINTAINERS b/board/atmel/at91sam9260ek/MAINTAINERS
new file mode 100644
index 0000000..0c7c721
--- /dev/null
+++ b/board/atmel/at91sam9260ek/MAINTAINERS
@@ -0,0 +1,16 @@
+AT91SAM9260EK BOARD
+M: Stelian Pop <stelian@popies.net>
+S: Maintained
+F: board/atmel/at91sam9260ek/
+F: include/configs/at91sam9260ek.h
+F: configs/at91sam9260ek_dataflash_cs0_defconfig
+F: configs/at91sam9260ek_dataflash_cs1_defconfig
+F: configs/at91sam9260ek_nandflash_defconfig
+F: configs/at91sam9g20ek_2mmc_nandflash_defconfig
+F: configs/at91sam9g20ek_dataflash_cs0_defconfig
+F: configs/at91sam9g20ek_dataflash_cs1_defconfig
+F: configs/at91sam9g20ek_mmc_defconfig
+F: configs/at91sam9g20ek_nandflash_defconfig
+F: configs/at91sam9xeek_dataflash_cs0_defconfig
+F: configs/at91sam9xeek_dataflash_cs1_defconfig
+F: configs/at91sam9xeek_nandflash_defconfig
diff --git a/board/atmel/at91sam9260ek/Makefile b/board/atmel/at91sam9260ek/Makefile
new file mode 100644
index 0000000..c6edbee
--- /dev/null
+++ b/board/atmel/at91sam9260ek/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += at91sam9260ek.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
new file mode 100644
index 0000000..7f14af1
--- /dev/null
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <atmel_mci.h>
+
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+# include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9260ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Assign CS3 to NAND/SmartMedia Interface */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9260ek_macb_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+ /* Enable EMAC clock */
+ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA17) => PHY normal mode (not Test mode)
+ * ERX0 (PA14) => PHY ADDR0
+ * ERX1 (PA15) => PHY ADDR1
+ * ERX2 (PA25) => PHY ADDR2
+ * ERX3 (PA26) => PHY ADDR3
+ * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ &pioa->pudr);
+
+ at91_phy_reset();
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ &pioa->puer);
+
+ /* Initialize EMAC=MACB hardware */
+ at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+ at91_mci_hw_init();
+
+ return atmel_mci_init((void *)ATMEL_BASE_MCI);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clocks for all PIOs */
+ writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOC),
+ &pmc->pcer);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ at91_seriald_hw_init();
+#ifdef CONFIG_CMD_NAND
+ at91sam9260ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init((1 << 0) | (1 << 1));
+#endif
+#ifdef CONFIG_MACB
+ at91sam9260ek_macb_hw_init();
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
+#endif
+ return rc;
+}
diff --git a/board/atmel/at91sam9260ek/led.c b/board/atmel/at91sam9260ek/led.c
new file mode 100644
index 0000000..fbe15af
--- /dev/null
+++ b/board/atmel/at91sam9260ek/led.c
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <status_led.h>
+
+void coloured_LED_init(void)
+{
+ /* Clock is enabled in board_early_init_f() */
+ at91_set_gpio_output(CONFIG_RED_LED, 1);
+ at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+ at91_set_gpio_value(CONFIG_RED_LED, 0);
+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}
diff --git a/board/atmel/at91sam9260ek/partition.c b/board/atmel/at91sam9260ek/partition.c
new file mode 100644
index 0000000..e41eefe
--- /dev/null
+++ b/board/atmel/at91sam9260ek/partition.c
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
+};
diff --git a/board/atmel/at91sam9261ek/Kconfig b/board/atmel/at91sam9261ek/Kconfig
new file mode 100644
index 0000000..d839c1a
--- /dev/null
+++ b/board/atmel/at91sam9261ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AT91SAM9261EK
+
+config SYS_BOARD
+ default "at91sam9261ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "at91sam9261ek"
+
+endif
diff --git a/board/atmel/at91sam9261ek/MAINTAINERS b/board/atmel/at91sam9261ek/MAINTAINERS
new file mode 100644
index 0000000..682dfdf
--- /dev/null
+++ b/board/atmel/at91sam9261ek/MAINTAINERS
@@ -0,0 +1,11 @@
+AT91SAM9261EK BOARD
+M: Stelian Pop <stelian@popies.net>
+S: Maintained
+F: board/atmel/at91sam9261ek/
+F: include/configs/at91sam9261ek.h
+F: configs/at91sam9261ek_dataflash_cs0_defconfig
+F: configs/at91sam9261ek_dataflash_cs3_defconfig
+F: configs/at91sam9261ek_nandflash_defconfig
+F: configs/at91sam9g10ek_dataflash_cs0_defconfig
+F: configs/at91sam9g10ek_dataflash_cs3_defconfig
+F: configs/at91sam9g10ek_nandflash_defconfig
diff --git a/board/atmel/at91sam9261ek/Makefile b/board/atmel/at91sam9261ek/Makefile
new file mode 100644
index 0000000..c547fed
--- /dev/null
+++ b/board/atmel/at91sam9261ek/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += at91sam9261ek.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
new file mode 100644
index 0000000..a301d72
--- /dev/null
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -0,0 +1,281 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91sam9261_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
+#include <net.h>
+#include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9261ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+#ifdef CONFIG_AT91SAM9G10EK
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+ &smc->cs[3].cycle);
+#else
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+#endif
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+ writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+ at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
+ at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+static void at91sam9261ek_dm9000_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+ /* Configure SMC CS2 for DM9000 */
+#ifdef CONFIG_AT91SAM9G10EK
+ writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[2].setup);
+ writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
+ AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
+ &smc->cs[2].pulse);
+ writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
+ &smc->cs[2].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+ AT91_SMC_MODE_TDF_CYCLE(1),
+ &smc->cs[2].mode);
+#else
+ writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[2].setup);
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
+ &smc->cs[2].pulse);
+ writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
+ &smc->cs[2].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+ AT91_SMC_MODE_TDF_CYCLE(1),
+ &smc->cs[2].mode);
+#endif
+
+ /* Configure Reset signal as output */
+ at91_set_gpio_output(AT91_PIN_PC10, 0);
+
+ /* Configure Interrupt pin as input, no pull-up */
+ at91_set_gpio_input(AT91_PIN_PC11, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 240,
+ .vl_row = 320,
+ .vl_clk = 4965000,
+ .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = 3,
+ .vl_tft = 1,
+ .vl_hsync_len = 5,
+ .vl_left_margin = 1,
+ .vl_right_margin = 33,
+ .vl_vsync_len = 1,
+ .vl_upper_margin = 1,
+ .vl_lower_margin = 0,
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+ at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
+}
+
+static void at91sam9261ek_lcd_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
+ at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
+ at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
+ at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
+ at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
+ at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
+ at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
+ at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
+ at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
+ at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
+ at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
+ at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
+ at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
+ at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
+ at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
+ at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
+ at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
+ at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
+ at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
+ at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
+ at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
+ at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
+
+ writel(AT91_PMC_HCK1, &pmc->scer);
+
+ /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
+#ifdef CONFIG_AT91SAM9261EK
+ gd->fb_base = ATMEL_BASE_SRAM;
+#endif
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size;
+ int i;
+ char temp[32];
+
+ lcd_printf ("%s\n", U_BOOT_VERSION);
+ lcd_printf ("(C) 2008 ATMEL Corp\n");
+ lcd_printf ("at91support@atmel.com\n");
+ lcd_printf ("%s CPU at %s MHz\n",
+ ATMEL_CPU_NAME,
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+ lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
+ dram_size >> 20,
+ nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_AT91SAM9G10EK
+ /* arch number of AT91SAM9G10EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
+#else
+ /* arch number of AT91SAM9261EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
+#endif
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ at91_seriald_hw_init();
+#ifdef CONFIG_CMD_NAND
+ at91sam9261ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+ at91sam9261ek_dm9000_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ at91sam9261ek_lcd_hw_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_DRIVER_DM9000
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
diff --git a/board/atmel/at91sam9261ek/led.c b/board/atmel/at91sam9261ek/led.c
new file mode 100644
index 0000000..18a68d8
--- /dev/null
+++ b/board/atmel/at91sam9261ek/led.c
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/io.h>
+
+void coloured_LED_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clock */
+ writel(ATMEL_ID_PIOA, &pmc->pcer);
+
+ at91_set_gpio_output(CONFIG_RED_LED, 1);
+ at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+ at91_set_gpio_value(CONFIG_RED_LED, 0);
+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+}
diff --git a/board/atmel/at91sam9261ek/partition.c b/board/atmel/at91sam9261ek/partition.c
new file mode 100644
index 0000000..ed97609
--- /dev/null
+++ b/board/atmel/at91sam9261ek/partition.c
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
+};
diff --git a/board/atmel/at91sam9263ek/Kconfig b/board/atmel/at91sam9263ek/Kconfig
new file mode 100644
index 0000000..311c504
--- /dev/null
+++ b/board/atmel/at91sam9263ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AT91SAM9263EK
+
+config SYS_BOARD
+ default "at91sam9263ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "at91sam9263ek"
+
+endif
diff --git a/board/atmel/at91sam9263ek/MAINTAINERS b/board/atmel/at91sam9263ek/MAINTAINERS
new file mode 100644
index 0000000..3b4b654
--- /dev/null
+++ b/board/atmel/at91sam9263ek/MAINTAINERS
@@ -0,0 +1,10 @@
+AT91SAM9263EK BOARD
+M: Stelian Pop <stelian@popies.net>
+S: Maintained
+F: board/atmel/at91sam9263ek/
+F: include/configs/at91sam9263ek.h
+F: configs/at91sam9263ek_dataflash_defconfig
+F: configs/at91sam9263ek_dataflash_cs0_defconfig
+F: configs/at91sam9263ek_nandflash_defconfig
+F: configs/at91sam9263ek_norflash_defconfig
+F: configs/at91sam9263ek_norflash_boot_defconfig
diff --git a/board/atmel/at91sam9263ek/Makefile b/board/atmel/at91sam9263ek/Makefile
new file mode 100644
index 0000000..7b31f18
--- /dev/null
+++ b/board/atmel/at91sam9263ek/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += at91sam9263ek.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
new file mode 100644
index 0000000..927adb0
--- /dev/null
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -0,0 +1,287 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+#include <atmel_mci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9263ek_nand_hw_init(void)
+{
+ unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
+ at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa[0]);
+
+ /* Enable CS3 */
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+ writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE,
+ &pmc->pcer);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9263ek_macb_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PC25) => PHY normal mode (not Test mode)
+ * ERX0 (PE25) => PHY ADDR0
+ * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(1 << 25, &pio->pioc.pudr);
+ writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
+
+ at91_phy_reset();
+
+ /* Re-enable pull-up */
+ writel(1 << 25, &pio->pioc.puer);
+ writel((1 << 25) | (1 <<26), &pio->pioe.puer);
+
+ at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 240,
+ .vl_row = 320,
+ .vl_clk = 4965000,
+ .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = 3,
+ .vl_tft = 1,
+ .vl_hsync_len = 5,
+ .vl_left_margin = 1,
+ .vl_right_margin = 33,
+ .vl_vsync_len = 1,
+ .vl_upper_margin = 1,
+ .vl_lower_margin = 0,
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+ at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */
+}
+
+static void at91sam9263ek_lcd_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
+ at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
+ at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
+ at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
+ at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
+
+ writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+ gd->fb_base = ATMEL_BASE_SRAM0;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+#ifndef CONFIG_SYS_NO_FLASH
+extern flash_info_t flash_info[];
+#endif
+
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size;
+#ifndef CONFIG_SYS_NO_FLASH
+ ulong flash_size;
+#endif
+ int i;
+ char temp[32];
+
+ lcd_printf ("%s\n", U_BOOT_VERSION);
+ lcd_printf ("(C) 2008 ATMEL Corp\n");
+ lcd_printf ("at91support@atmel.com\n");
+ lcd_printf ("%s CPU at %s MHz\n",
+ ATMEL_CPU_NAME,
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+#ifndef CONFIG_SYS_NO_FLASH
+ flash_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+ flash_size += flash_info[i].size;
+#endif
+ lcd_printf (" %ld MB SDRAM, %ld MB NAND",
+ dram_size >> 20,
+ nand_size >> 20 );
+#ifndef CONFIG_SYS_NO_FLASH
+ lcd_printf (",\n %ld MB NOR",
+ flash_size >> 20);
+#endif
+ lcd_puts ("\n");
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+ at91_mci_hw_init();
+
+ return atmel_mci_init((void *)ATMEL_BASE_MCI1);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clocks for all PIOs */
+ writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOCDE),
+ &pmc->pcer);
+
+ at91_seriald_hw_init();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of AT91SAM9263EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ at91sam9263ek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+ at91sam9263ek_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+ at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ at91sam9263ek_lcd_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
diff --git a/board/atmel/at91sam9263ek/led.c b/board/atmel/at91sam9263ek/led.c
new file mode 100644
index 0000000..e317d99
--- /dev/null
+++ b/board/atmel/at91sam9263ek/led.c
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91sam9263.h>
+
+void coloured_LED_init(void)
+{
+ /* Enable clock */
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ writel(1 << ATMEL_ID_PIOB | 1 << ATMEL_ID_PIOCDE,
+ &pmc->pcer);
+
+ at91_set_gpio_output(CONFIG_RED_LED, 1);
+ at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+ at91_set_gpio_value(CONFIG_RED_LED, 0);
+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+}
diff --git a/board/atmel/at91sam9263ek/partition.c b/board/atmel/at91sam9263ek/partition.c
new file mode 100644
index 0000000..8617f48
--- /dev/null
+++ b/board/atmel/at91sam9263ek/partition.c
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
+};
diff --git a/board/atmel/at91sam9m10g45ek/Kconfig b/board/atmel/at91sam9m10g45ek/Kconfig
new file mode 100644
index 0000000..1bc086a
--- /dev/null
+++ b/board/atmel/at91sam9m10g45ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AT91SAM9M10G45EK
+
+config SYS_BOARD
+ default "at91sam9m10g45ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "at91sam9m10g45ek"
+
+endif
diff --git a/board/atmel/at91sam9m10g45ek/MAINTAINERS b/board/atmel/at91sam9m10g45ek/MAINTAINERS
new file mode 100644
index 0000000..6389e6a
--- /dev/null
+++ b/board/atmel/at91sam9m10g45ek/MAINTAINERS
@@ -0,0 +1,7 @@
+AT91SAM9M10G45EK BOARD
+M: Bo Shen <voice.shen@atmel.com>
+S: Maintained
+F: board/atmel/at91sam9m10g45ek/
+F: include/configs/at91sam9m10g45ek.h
+F: configs/at91sam9m10g45ek_mmc_defconfig
+F: configs/at91sam9m10g45ek_nandflash_defconfig
diff --git a/board/atmel/at91sam9m10g45ek/Makefile b/board/atmel/at91sam9m10g45ek/Makefile
new file mode 100644
index 0000000..e5448ec
--- /dev/null
+++ b/board/atmel/at91sam9m10g45ek/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += at91sam9m10g45ek.o
+obj-y += led.o
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
new file mode 100644
index 0000000..b807ef9
--- /dev/null
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -0,0 +1,325 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#include <atmel_mci.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+void at91sam9m10g45ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+
+ writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void at91sam9m10g45ek_usb_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
+
+ at91_set_gpio_output(AT91_PIN_PD1, 0);
+ at91_set_gpio_output(AT91_PIN_PD3, 0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void at91sam9m10g45ek_macb_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA15) => PHY normal mode (not Test mode)
+ * ERX0 (PA12) => PHY ADDR0
+ * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA12) |
+ pin_to_mask(AT91_PIN_PA13),
+ &pioa->pudr);
+
+ at91_phy_reset();
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA12) |
+ pin_to_mask(AT91_PIN_PA13),
+ &pioa->puer);
+
+ /* And the pins. */
+ at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+
+vidinfo_t panel_info = {
+ .vl_col = 480,
+ .vl_row = 272,
+ .vl_clk = 9000000,
+ .vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
+ ATMEL_LCDC_INVFRAME_NORMAL,
+ .vl_bpix = 3,
+ .vl_tft = 1,
+ .vl_hsync_len = 45,
+ .vl_left_margin = 1,
+ .vl_right_margin = 1,
+ .vl_vsync_len = 1,
+ .vl_upper_margin = 40,
+ .vl_lower_margin = 1,
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+
+void lcd_enable(void)
+{
+ at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
+}
+
+static void at91sam9m10g45ek_lcd_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
+ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
+ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
+ at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
+ at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
+
+ at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
+ at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
+ at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
+ at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
+ at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
+ at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
+ at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
+ at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
+ at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
+ at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
+ at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
+ at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
+ at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
+ at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
+ at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
+ at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
+ at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
+ at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
+ at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
+ at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
+ at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
+ at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
+ at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
+ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
+
+ writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+
+ gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size;
+ int i;
+ char temp[32];
+
+ lcd_printf ("%s\n", U_BOOT_VERSION);
+ lcd_printf ("(C) 2008 ATMEL Corp\n");
+ lcd_printf ("at91support@atmel.com\n");
+ lcd_printf ("%s CPU at %s MHz\n",
+ ATMEL_CPU_NAME,
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+ lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
+ dram_size >> 20,
+ nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+ at91_mci_hw_init();
+
+ return atmel_mci_init((void *)ATMEL_BASE_MCI0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ at91_seriald_hw_init();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of AT91SAM9M10G45EK-Board */
+#ifdef CONFIG_AT91SAM9M10G45EK
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
+#elif defined CONFIG_AT91SAM9G45EKES
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
+#endif
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ at91sam9m10g45ek_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+ at91sam9m10g45ek_usb_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_ATMEL_SPI
+ at91_spi0_hw_init(1 << 4);
+#endif
+#ifdef CONFIG_MACB
+ at91sam9m10g45ek_macb_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ at91sam9m10g45ek_lcd_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch(slave->cs) {
+ case 1:
+ at91_set_gpio_output(AT91_PIN_PB18, 0);
+ break;
+ case 0:
+ default:
+ at91_set_gpio_output(AT91_PIN_PB3, 0);
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch(slave->cs) {
+ case 1:
+ at91_set_gpio_output(AT91_PIN_PB18, 1);
+ break;
+ case 0:
+ default:
+ at91_set_gpio_output(AT91_PIN_PB3, 1);
+ break;
+ }
+}
+#endif /* CONFIG_ATMEL_SPI */
diff --git a/board/atmel/at91sam9m10g45ek/led.c b/board/atmel/at91sam9m10g45ek/led.c
new file mode 100644
index 0000000..fe98723
--- /dev/null
+++ b/board/atmel/at91sam9m10g45ek/led.c
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+
+void coloured_LED_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
+
+ at91_set_gpio_output(CONFIG_RED_LED, 1);
+ at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+ at91_set_gpio_value(CONFIG_RED_LED, 0);
+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}
diff --git a/board/atmel/at91sam9n12ek/Kconfig b/board/atmel/at91sam9n12ek/Kconfig
new file mode 100644
index 0000000..cf1d1a3
--- /dev/null
+++ b/board/atmel/at91sam9n12ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AT91SAM9N12EK
+
+config SYS_BOARD
+ default "at91sam9n12ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "at91sam9n12ek"
+
+endif
diff --git a/board/atmel/at91sam9n12ek/MAINTAINERS b/board/atmel/at91sam9n12ek/MAINTAINERS
new file mode 100644
index 0000000..82a9192
--- /dev/null
+++ b/board/atmel/at91sam9n12ek/MAINTAINERS
@@ -0,0 +1,8 @@
+AT91SAM9N12EK BOARD
+M: Josh Wu <josh.wu@atmel.com>
+S: Maintained
+F: board/atmel/at91sam9n12ek/
+F: include/configs/at91sam9n12ek.h
+F: configs/at91sam9n12ek_mmc_defconfig
+F: configs/at91sam9n12ek_nandflash_defconfig
+F: configs/at91sam9n12ek_spiflash_defconfig
diff --git a/board/atmel/at91sam9n12ek/Makefile b/board/atmel/at91sam9n12ek/Makefile
new file mode 100644
index 0000000..9f069ca
--- /dev/null
+++ b/board/atmel/at91sam9n12ek/Makefile
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2013
+# Josh Wu <josh.wu@atmel.com>
+# Atmel corporation <www.atmel.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += at91sam9n12ek.o
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
new file mode 100644
index 0000000..9adc992
--- /dev/null
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -0,0 +1,259 @@
+/*
+ * (C) Copyright 2013 Atmel Corporation
+ * Josh Wu <josh.wu@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#include <netdev.h>
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+#ifdef CONFIG_NAND_ATMEL
+static void at91sam9n12ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Assign CS3 to NAND/SmartMedia Interface */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+ /* Configure databus */
+ csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
+ /* Configure IO drive */
+ csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(1),
+ &smc->cs[3].mode);
+
+ /* Configure RDY/BSY pin */
+ at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
+
+ /* Configure ENABLE pin for NandFlash */
+ at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
+
+ at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
+ at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
+ at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
+ at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 480,
+ .vl_row = 272,
+ .vl_clk = 9000000,
+ .vl_bpix = LCD_BPP,
+ .vl_sync = 0,
+ .vl_tft = 1,
+ .vl_hsync_len = 5,
+ .vl_left_margin = 8,
+ .vl_right_margin = 43,
+ .vl_vsync_len = 10,
+ .vl_upper_margin = 4,
+ .vl_lower_margin = 12,
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+ at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size;
+ int i;
+ char temp[32];
+
+ lcd_printf("%s\n", U_BOOT_VERSION);
+ lcd_printf("ATMEL Corp\n");
+ lcd_printf("at91@atmel.com\n");
+ lcd_printf("%s CPU at %s MHz\n",
+ ATMEL_CPU_NAME,
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+ lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
+ dram_size >> 20,
+ nand_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 0:
+ at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
+ break;
+ case 1:
+ at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 0:
+ at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
+ break;
+ case 1:
+ at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
+ break;
+ }
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+ at91_mci_hw_init();
+
+ return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
+}
+#endif
+
+#ifdef CONFIG_KS8851_MLL
+void at91sam9n12ek_ks8851_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[2].setup);
+ writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
+ AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
+ &smc->cs[2].pulse);
+ writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
+ &smc->cs[2].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+ AT91_SMC_MODE_TDF_CYCLE(1),
+ &smc->cs[2].mode);
+
+ /* Configure NCS2 PIN */
+ at91_set_b_periph(AT91_PIO_PORTD, 19, 0);
+}
+#endif
+
+#ifdef CONFIG_USB_ATMEL
+void at91sam9n12ek_usb_hw_init(void)
+{
+ at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ /* Enable clocks for all PIOs */
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer);
+
+ at91_seriald_hw_init();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+ at91sam9n12ek_nand_hw_init();
+#endif
+
+#ifdef CONFIG_ATMEL_SPI
+ at91_spi0_hw_init(1 << 0);
+#endif
+
+#ifdef CONFIG_LCD
+ at91_lcd_hw_init();
+#endif
+
+#ifdef CONFIG_KS8851_MLL
+ at91sam9n12ek_ks8851_hw_init();
+#endif
+
+#ifdef CONFIG_USB_ATMEL
+ at91sam9n12ek_usb_hw_init();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_KS8851_MLL
+int board_eth_init(bd_t *bis)
+{
+ return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
diff --git a/board/atmel/at91sam9rlek/Kconfig b/board/atmel/at91sam9rlek/Kconfig
new file mode 100644
index 0000000..438d300
--- /dev/null
+++ b/board/atmel/at91sam9rlek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AT91SAM9RLEK
+
+config SYS_BOARD
+ default "at91sam9rlek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "at91sam9rlek"
+
+endif
diff --git a/board/atmel/at91sam9rlek/MAINTAINERS b/board/atmel/at91sam9rlek/MAINTAINERS
new file mode 100644
index 0000000..7dd8ef7
--- /dev/null
+++ b/board/atmel/at91sam9rlek/MAINTAINERS
@@ -0,0 +1,7 @@
+AT91SAM9RLEK BOARD
+M: Stelian Pop <stelian@popies.net>
+S: Maintained
+F: board/atmel/at91sam9rlek/
+F: include/configs/at91sam9rlek.h
+F: configs/at91sam9rlek_dataflash_defconfig
+F: configs/at91sam9rlek_nandflash_defconfig
diff --git a/board/atmel/at91sam9rlek/Makefile b/board/atmel/at91sam9rlek/Makefile
new file mode 100644
index 0000000..51daf8d
--- /dev/null
+++ b/board/atmel/at91sam9rlek/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += at91sam9rlek.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
new file mode 100644
index 0000000..56ca1d4
--- /dev/null
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9rl.h>
+#include <asm/arch/at91sam9rl_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void at91sam9rlek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+ writel(1 << ATMEL_ID_PIOD, &pmc->pcer);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+ at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
+ at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 240,
+ .vl_row = 320,
+ .vl_clk = 4965000,
+ .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = 3,
+ .vl_tft = 1,
+ .vl_hsync_len = 5,
+ .vl_left_margin = 1,
+ .vl_right_margin = 33,
+ .vl_vsync_len = 1,
+ .vl_upper_margin = 1,
+ .vl_lower_margin = 0,
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+ at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
+}
+static void at91sam9rlek_lcd_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
+ at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
+ at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
+ at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
+ at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
+ at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
+ at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
+ at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
+ at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
+ at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
+ at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
+ at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
+ at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
+ at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
+ at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
+ at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
+ at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
+ at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
+ at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
+ at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
+ at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
+
+ writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size;
+ int i;
+ char temp[32];
+
+ lcd_printf ("%s\n", U_BOOT_VERSION);
+ lcd_printf ("(C) 2008 ATMEL Corp\n");
+ lcd_printf ("at91support@atmel.com\n");
+ lcd_printf ("%s CPU at %s MHz\n",
+ ATMEL_CPU_NAME,
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+ lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
+ dram_size >> 20,
+ nand_size >> 20 );
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+int board_early_init_f(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clocks for all PIOs */
+ writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIOD),
+ &pmc->pcer);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of AT91SAM9RLEK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ at91_seriald_hw_init();
+#ifdef CONFIG_CMD_NAND
+ at91sam9rlek_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_LCD
+ at91sam9rlek_lcd_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
diff --git a/board/atmel/at91sam9rlek/led.c b/board/atmel/at91sam9rlek/led.c
new file mode 100644
index 0000000..fede59c
--- /dev/null
+++ b/board/atmel/at91sam9rlek/led.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9rl.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+void coloured_LED_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clock */
+ writel(ATMEL_ID_PIOD, &pmc->pcer);
+
+ at91_set_gpio_output(CONFIG_RED_LED, 1);
+ at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+ at91_set_gpio_value(CONFIG_RED_LED, 0);
+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+}
diff --git a/board/atmel/at91sam9rlek/partition.c b/board/atmel/at91sam9rlek/partition.c
new file mode 100644
index 0000000..8617f48
--- /dev/null
+++ b/board/atmel/at91sam9rlek/partition.c
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
+};
diff --git a/board/atmel/at91sam9x5ek/Kconfig b/board/atmel/at91sam9x5ek/Kconfig
new file mode 100644
index 0000000..5c5ec61
--- /dev/null
+++ b/board/atmel/at91sam9x5ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AT91SAM9X5EK
+
+config SYS_BOARD
+ default "at91sam9x5ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "at91sam9x5ek"
+
+endif
diff --git a/board/atmel/at91sam9x5ek/MAINTAINERS b/board/atmel/at91sam9x5ek/MAINTAINERS
new file mode 100644
index 0000000..5fea489
--- /dev/null
+++ b/board/atmel/at91sam9x5ek/MAINTAINERS
@@ -0,0 +1,9 @@
+AT91SAM9X5EK BOARD
+M: Bo Shen <voice.shen@atmel.com>
+S: Maintained
+F: board/atmel/at91sam9x5ek/
+F: include/configs/at91sam9x5ek.h
+F: configs/at91sam9x5ek_dataflash_defconfig
+F: configs/at91sam9x5ek_mmc_defconfig
+F: configs/at91sam9x5ek_nandflash_defconfig
+F: configs/at91sam9x5ek_spiflash_defconfig
diff --git a/board/atmel/at91sam9x5ek/Makefile b/board/atmel/at91sam9x5ek/Makefile
new file mode 100644
index 0000000..5c42b6f
--- /dev/null
+++ b/board/atmel/at91sam9x5ek/Makefile
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2012
+# Bo Shen <voice.shen@atmel.com>
+# Atmel corporation <www.atmel.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += at91sam9x5ek.o
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
new file mode 100644
index 0000000..17a2a40
--- /dev/null
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -0,0 +1,295 @@
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#ifdef CONFIG_MACB
+#include <net.h>
+#endif
+#include <netdev.h>
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+#endif
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+#ifdef CONFIG_CMD_NAND
+static void at91sam9x5ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+ /* NAND flash on D16 */
+ csa |= AT91_MATRIX_NFD0_ON_D16;
+
+ /* Configure IO drive */
+ csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(1),
+ &smc->cs[3].mode);
+
+ writel(1 << ATMEL_ID_PIOCD, &pmc->pcer);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+ at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
+ at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
+ at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
+ at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
+ at91_set_a_periph(AT91_PIO_PORTD, 6, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 7, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 9, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 10, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 11, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 12, 1);
+ at91_set_a_periph(AT91_PIO_PORTD, 13, 1);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+#ifdef CONFIG_MACB
+ if (has_emac0())
+ rc = macb_eth_initialize(0,
+ (void *)ATMEL_BASE_EMAC0, 0x00);
+ if (has_emac1())
+ rc = macb_eth_initialize(1,
+ (void *)ATMEL_BASE_EMAC1, 0x00);
+#endif
+ return rc;
+}
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 800,
+ .vl_row = 480,
+ .vl_clk = 24000000,
+ .vl_sync = LCDC_LCDCFG5_HSPOL | LCDC_LCDCFG5_VSPOL,
+ .vl_bpix = LCD_BPP,
+ .vl_tft = 1,
+ .vl_clk_pol = 1,
+ .vl_hsync_len = 128,
+ .vl_left_margin = 64,
+ .vl_right_margin = 64,
+ .vl_vsync_len = 2,
+ .vl_upper_margin = 22,
+ .vl_lower_margin = 21,
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+ if (has_lcdc())
+ at91_set_a_periph(AT91_PIO_PORTC, 29, 1); /* power up */
+}
+
+void lcd_disable(void)
+{
+ if (has_lcdc())
+ at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* power down */
+}
+
+static void at91sam9x5ek_lcd_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ if (has_lcdc()) {
+ at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDPWM */
+ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDISP */
+ at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
+ at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDPCK */
+
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
+ at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
+ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
+ at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
+ at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
+ at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
+ at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
+
+ writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+ }
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size;
+ int i;
+ char temp[32];
+
+ if (has_lcdc()) {
+ lcd_printf("%s\n", U_BOOT_VERSION);
+ lcd_printf("(C) 2012 ATMEL Corp\n");
+ lcd_printf("at91support@atmel.com\n");
+ lcd_printf("%s CPU at %s MHz\n",
+ get_cpu_name(),
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+ lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
+ dram_size >> 20,
+ nand_size >> 20);
+ }
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 1:
+ at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
+ break;
+ case 0:
+ default:
+ at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 1:
+ at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
+ break;
+ case 0:
+ default:
+ at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
+ break;
+ }
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+ at91_mci_hw_init();
+
+ return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ at91_seriald_hw_init();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of AT91SAM9X5EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ at91sam9x5ek_nand_hw_init();
+#endif
+
+#ifdef CONFIG_ATMEL_SPI
+ at91_spi0_hw_init(1 << 4);
+#endif
+
+#ifdef CONFIG_MACB
+ at91_macb_hw_init();
+#endif
+
+#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
+ at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ at91sam9x5ek_lcd_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
diff --git a/board/atmel/atngw100/Kconfig b/board/atmel/atngw100/Kconfig
new file mode 100644
index 0000000..28037b6
--- /dev/null
+++ b/board/atmel/atngw100/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ATNGW100
+
+config SYS_BOARD
+ default "atngw100"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at32ap700x"
+
+config SYS_CONFIG_NAME
+ default "atngw100"
+
+endif
diff --git a/board/atmel/atngw100/MAINTAINERS b/board/atmel/atngw100/MAINTAINERS
new file mode 100644
index 0000000..1c319f6
--- /dev/null
+++ b/board/atmel/atngw100/MAINTAINERS
@@ -0,0 +1,6 @@
+ATNGW100 BOARD
+#M: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+S: Orphan (since 2014-06)
+F: board/atmel/atngw100/
+F: include/configs/atngw100.h
+F: configs/atngw100_defconfig
diff --git a/board/atmel/atngw100/Makefile b/board/atmel/atngw100/Makefile
new file mode 100644
index 0000000..f9b93c9
--- /dev/null
+++ b/board/atmel/atngw100/Makefile
@@ -0,0 +1,6 @@
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := atngw100.o
diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c
new file mode 100644
index 0000000..03d767a
--- /dev/null
+++ b/board/atmel/atngw100/atngw100.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
+static const struct sdram_config sdram_config = {
+ .data_bits = SDRAM_DATA_16BIT,
+ .row_bits = 13,
+ .col_bits = 9,
+ .bank_bits = 2,
+ .cas = 3,
+ .twr = 2,
+ .trc = 7,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 5,
+ .txsr = 5,
+ /* 7.81 us */
+ .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+int board_early_init_f(void)
+{
+ /* Enable SDRAM in the EBI mux */
+ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+ portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+#if defined(CONFIG_MACB)
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+ portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+#if defined(CONFIG_MMC)
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+#if defined(CONFIG_ATMEL_SPI)
+ portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
+#endif
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ unsigned long expected_size;
+ unsigned long actual_size;
+ void *sdram_base;
+
+ sdram_base = uncached(EBI_SDRAM_BASE);
+
+ expected_size = sdram_init(sdram_base, &sdram_config);
+ actual_size = get_ram_size(sdram_base, expected_size);
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return actual_size;
+}
+
+int board_early_init_r(void)
+{
+ gd->bd->bi_phy_id[0] = 0x01;
+ gd->bd->bi_phy_id[1] = 0x03;
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+ macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+ macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
+ return 0;
+}
+#endif
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3)
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
+}
+#endif /* CONFIG_ATMEL_SPI */
diff --git a/board/atmel/atngw100mkii/Kconfig b/board/atmel/atngw100mkii/Kconfig
new file mode 100644
index 0000000..ca04269
--- /dev/null
+++ b/board/atmel/atngw100mkii/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ATNGW100MKII
+
+config SYS_BOARD
+ default "atngw100mkii"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at32ap700x"
+
+config SYS_CONFIG_NAME
+ default "atngw100mkii"
+
+endif
diff --git a/board/atmel/atngw100mkii/MAINTAINERS b/board/atmel/atngw100mkii/MAINTAINERS
new file mode 100644
index 0000000..212363e
--- /dev/null
+++ b/board/atmel/atngw100mkii/MAINTAINERS
@@ -0,0 +1,6 @@
+ATNGW100MKII BOARD
+M: Andreas Bießmann <andreas.devel@googlemail.com>
+S: Maintained
+F: board/atmel/atngw100mkii/
+F: include/configs/atngw100mkii.h
+F: configs/atngw100mkii_defconfig
diff --git a/board/atmel/atngw100mkii/Makefile b/board/atmel/atngw100mkii/Makefile
new file mode 100644
index 0000000..90bf5bc
--- /dev/null
+++ b/board/atmel/atngw100mkii/Makefile
@@ -0,0 +1,6 @@
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := atngw100mkii.o
diff --git a/board/atmel/atngw100mkii/atngw100mkii.c b/board/atmel/atngw100mkii/atngw100mkii.c
new file mode 100644
index 0000000..72d19e4
--- /dev/null
+++ b/board/atmel/atngw100mkii/atngw100mkii.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2010 Atmel Corporation
+ *
+ * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+
+#include <spi.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
+ .virt_pgno = EBI_SRAM_CS3_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT,
+ .phys = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
+static const struct sdram_config sdram_config = {
+ .data_bits = SDRAM_DATA_32BIT,
+ .row_bits = 13,
+ .col_bits = 10,
+ .bank_bits = 2,
+ .cas = 3,
+ .twr = 2,
+ .trc = 7,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 5,
+ .txsr = 6,
+ /* 7.81 us */
+ .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+int board_early_init_f(void)
+{
+ /* Enable SDRAM in the EBI mux */
+ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)
+ | HMATRIX_BIT(EBI_NAND_ENABLE));
+
+ portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND,
+ PORTMUX_DRIVE_HIGH);
+ portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
+ PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
+ | PORTMUX_DRIVE_MIN);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+#if defined(CONFIG_MACB)
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+ portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+#if defined(CONFIG_MMC)
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+#if defined(CONFIG_ATMEL_SPI)
+ portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
+#endif
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ unsigned long expected_size;
+ unsigned long actual_size;
+ void *sdram_base;
+
+ sdram_base = uncached(EBI_SDRAM_BASE);
+
+ expected_size = sdram_init(sdram_base, &sdram_config);
+ actual_size = get_ram_size(sdram_base, expected_size);
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return actual_size;
+}
+
+int board_early_init_r(void)
+{
+ gd->bd->bi_phy_id[0] = 0x01;
+ gd->bd->bi_phy_id[1] = 0x03;
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+ macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+ macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
+ return 0;
+}
+#endif
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3)
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
+}
+#endif /* CONFIG_ATMEL_SPI */
diff --git a/board/atmel/atstk1000/Kconfig b/board/atmel/atstk1000/Kconfig
new file mode 100644
index 0000000..6d41514
--- /dev/null
+++ b/board/atmel/atstk1000/Kconfig
@@ -0,0 +1,63 @@
+if TARGET_ATSTK1002
+
+config SYS_BOARD
+ default "atstk1000"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at32ap700x"
+
+config SYS_CONFIG_NAME
+ default "atstk1002"
+
+endif
+
+if TARGET_ATSTK1003
+
+config SYS_BOARD
+ default "atstk1000"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at32ap700x"
+
+config SYS_CONFIG_NAME
+ default "atstk1003"
+
+endif
+
+if TARGET_ATSTK1004
+
+config SYS_BOARD
+ default "atstk1000"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at32ap700x"
+
+config SYS_CONFIG_NAME
+ default "atstk1004"
+
+endif
+
+if TARGET_ATSTK1006
+
+config SYS_BOARD
+ default "atstk1000"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at32ap700x"
+
+config SYS_CONFIG_NAME
+ default "atstk1006"
+
+endif
diff --git a/board/atmel/atstk1000/MAINTAINERS b/board/atmel/atstk1000/MAINTAINERS
new file mode 100644
index 0000000..378e1b3
--- /dev/null
+++ b/board/atmel/atstk1000/MAINTAINERS
@@ -0,0 +1,12 @@
+ATSTK1000 BOARD
+#M: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+S: Orphan (since 2014-06)
+F: board/atmel/atstk1000/
+F: include/configs/atstk1002.h
+F: configs/atstk1002_defconfig
+F: include/configs/atstk1003.h
+F: configs/atstk1003_defconfig
+F: include/configs/atstk1004.h
+F: configs/atstk1004_defconfig
+F: include/configs/atstk1006.h
+F: configs/atstk1006_defconfig
diff --git a/board/atmel/atstk1000/Makefile b/board/atmel/atstk1000/Makefile
new file mode 100644
index 0000000..ad76631
--- /dev/null
+++ b/board/atmel/atstk1000/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += atstk1000.o
diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c
new file mode 100644
index 0000000..4b6b90f
--- /dev/null
+++ b/board/atmel/atstk1000/atstk1000.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
+static const struct sdram_config sdram_config = {
+#if defined(CONFIG_ATSTK1006)
+ /* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
+ .data_bits = SDRAM_DATA_32BIT,
+ .row_bits = 13,
+ .col_bits = 9,
+ .bank_bits = 2,
+ .cas = 2,
+ .twr = 2,
+ .trc = 7,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 4,
+ .txsr = 7,
+ /* 7.81 us */
+ .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+#else
+ /* MT48LC2M32B2P-5 (8 MB) on motherboard */
+#ifdef CONFIG_ATSTK1004
+ .data_bits = SDRAM_DATA_16BIT,
+#else
+ .data_bits = SDRAM_DATA_32BIT,
+#endif
+#ifdef CONFIG_ATSTK1000_16MB_SDRAM
+ /* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
+ .row_bits = 12,
+#else
+ .row_bits = 11,
+#endif
+ .col_bits = 8,
+ .bank_bits = 2,
+ .cas = 3,
+ .twr = 2,
+ .trc = 7,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 5,
+ .txsr = 5,
+ /* 15.6 us */
+ .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
+#endif
+};
+
+int board_early_init_f(void)
+{
+ /* Enable SDRAM in the EBI mux */
+ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+ portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+#if defined(CONFIG_MACB)
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
+ portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
+#endif
+#if defined(CONFIG_MMC)
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ unsigned long expected_size;
+ unsigned long actual_size;
+ void *sdram_base;
+
+ sdram_base = uncached(EBI_SDRAM_BASE);
+
+ expected_size = sdram_init(sdram_base, &sdram_config);
+ actual_size = get_ram_size(sdram_base, expected_size);
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return actual_size;
+}
+
+int board_early_init_r(void)
+{
+ gd->bd->bi_phy_id[0] = 0x10;
+ gd->bd->bi_phy_id[1] = 0x11;
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+ macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+ macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
+ return 0;
+}
+#endif
diff --git a/board/atmel/sama5d3_xplained/Kconfig b/board/atmel/sama5d3_xplained/Kconfig
new file mode 100644
index 0000000..0ba8a7b
--- /dev/null
+++ b/board/atmel/sama5d3_xplained/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D3_XPLAINED
+
+config SYS_BOARD
+ default "sama5d3_xplained"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama5d3_xplained"
+
+endif
diff --git a/board/atmel/sama5d3_xplained/MAINTAINERS b/board/atmel/sama5d3_xplained/MAINTAINERS
new file mode 100644
index 0000000..8a09c19
--- /dev/null
+++ b/board/atmel/sama5d3_xplained/MAINTAINERS
@@ -0,0 +1,7 @@
+SAMA5D3_XPLAINED BOARD
+M: Bo Shen <voice.shen@atmel.com>
+S: Maintained
+F: board/atmel/sama5d3_xplained/
+F: include/configs/sama5d3_xplained.h
+F: configs/sama5d3_xplained_mmc_defconfig
+F: configs/sama5d3_xplained_nandflash_defconfig
diff --git a/board/atmel/sama5d3_xplained/Makefile b/board/atmel/sama5d3_xplained/Makefile
new file mode 100644
index 0000000..ec82b06
--- /dev/null
+++ b/board/atmel/sama5d3_xplained/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2014
+# Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sama5d3_xplained.o
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
new file mode 100644
index 0000000..92ed4e8
--- /dev/null
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (C) 2014 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <atmel_mci.h>
+#include <net.h>
+#include <netdev.h>
+#include <spl.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/at91_wdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_NAND_ATMEL
+void sama5d3_xplained_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+ at91_periph_clk_enable(ATMEL_ID_SMC);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+ AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
+ AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
+ AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d3_xplained_usb_hw_init(void)
+{
+ at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
+ at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+static void sama5d3_xplained_mci0_hw_init(void)
+{
+ at91_mci_hw_init();
+
+ at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */
+}
+#endif
+
+int board_early_init_f(void)
+{
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+ at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+ at91_seriald_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+ sama5d3_xplained_nand_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+ sama5d3_xplained_usb_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+ sama5d3_xplained_mci0_hw_init();
+#endif
+#ifdef CONFIG_MACB
+ at91_gmac_hw_init();
+ at91_macb_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_MACB
+ macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+ macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+ atmel_mci_init((void *)ATMEL_BASE_MCI0);
+
+ return 0;
+}
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+ sama5d3_xplained_mci0_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+ sama5d3_xplained_nand_hw_init();
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_14 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_ENRDM_ON |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_NDQS_DISABLED |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+ /*
+ * As the DDR2-SDRAm device requires a refresh time is 7.8125us
+ * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
+ */
+ ddr2->rtr = 0x411;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct atmel_mpddr ddr2;
+
+ ddr2_conf(&ddr2);
+
+ /* enable MPDDR clock */
+ at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+ writel(0x4, &pmc->scer);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ u32 tmp;
+
+ tmp = AT91_PMC_PLLAR_29 |
+ AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+ AT91_PMC_PLLXR_MUL(43) |
+ AT91_PMC_PLLXR_DIV(1);
+ at91_plla_init(tmp);
+
+ writel(0x3 << 8, &pmc->pllicpr);
+
+ tmp = AT91_PMC_MCKR_MDIV_4 |
+ AT91_PMC_MCKR_CSS_PLLA;
+ at91_mck_init(tmp);
+}
+#endif
diff --git a/board/atmel/sama5d3xek/Kconfig b/board/atmel/sama5d3xek/Kconfig
new file mode 100644
index 0000000..2a9ed23
--- /dev/null
+++ b/board/atmel/sama5d3xek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D3XEK
+
+config SYS_BOARD
+ default "sama5d3xek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama5d3xek"
+
+endif
diff --git a/board/atmel/sama5d3xek/MAINTAINERS b/board/atmel/sama5d3xek/MAINTAINERS
new file mode 100644
index 0000000..560303c
--- /dev/null
+++ b/board/atmel/sama5d3xek/MAINTAINERS
@@ -0,0 +1,8 @@
+SAMA5D3XEK BOARD
+M: Bo Shen <voice.shen@atmel.com>
+S: Maintained
+F: board/atmel/sama5d3xek/
+F: include/configs/sama5d3xek.h
+F: configs/sama5d3xek_mmc_defconfig
+F: configs/sama5d3xek_nandflash_defconfig
+F: configs/sama5d3xek_spiflash_defconfig
diff --git a/board/atmel/sama5d3xek/Makefile b/board/atmel/sama5d3xek/Makefile
new file mode 100644
index 0000000..7ff7481
--- /dev/null
+++ b/board/atmel/sama5d3xek/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2013
+# Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sama5d3xek.o
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
new file mode 100644
index 0000000..cf6ed8b
--- /dev/null
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -0,0 +1,456 @@
+/*
+ * Copyright (C) 2012 - 2013 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#include <phy.h>
+#include <micrel.h>
+#include <net.h>
+#include <netdev.h>
+#include <spl.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/at91_wdt.h>
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+#include <asm/arch/atmel_usba_udc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_NAND_ATMEL
+void sama5d3xek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+ at91_periph_clk_enable(ATMEL_ID_SMC);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
+ AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
+ AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
+ AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+}
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+static void sama5d3xek_nor_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+ at91_periph_clk_enable(ATMEL_ID_SMC);
+
+ /* Configure SMC CS0 for NOR flash */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[0].setup);
+ writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
+ AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
+ &smc->cs[0].pulse);
+ writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
+ &smc->cs[0].cycle);
+ writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) |
+ AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) |
+ AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)|
+ AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_16 |
+ AT91_SMC_MODE_TDF_CYCLE(1),
+ &smc->cs[0].mode);
+
+ /* Address pin (A1 ~ A23) configuration */
+ at91_set_a_periph(AT91_PIO_PORTE, 1, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 2, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 3, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 4, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 5, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 6, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 7, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 8, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 9, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 10, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 11, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 12, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 13, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 14, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 15, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 16, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 17, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 18, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 19, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 20, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 21, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 22, 0);
+ at91_set_a_periph(AT91_PIO_PORTE, 23, 0);
+ /* CS0 pin configuration */
+ at91_set_a_periph(AT91_PIO_PORTE, 26, 0);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d3xek_usb_hw_init(void)
+{
+ at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
+ at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
+ at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+static void sama5d3xek_mci_hw_init(void)
+{
+ at91_mci_hw_init();
+
+ at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 800,
+ .vl_row = 480,
+ .vl_clk = 24000000,
+ .vl_bpix = LCD_BPP,
+ .vl_tft = 1,
+ .vl_hsync_len = 128,
+ .vl_left_margin = 64,
+ .vl_right_margin = 64,
+ .vl_vsync_len = 2,
+ .vl_upper_margin = 22,
+ .vl_lower_margin = 21,
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+}
+
+void lcd_disable(void)
+{
+}
+
+static void sama5d3xek_lcd_hw_init(void)
+{
+ gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
+
+ /* The higher 8 bit of LCD is board related */
+ at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */
+ at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */
+ at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */
+ at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */
+ at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */
+ at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */
+ at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */
+ at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */
+
+ /* Configure lower 16 bit of LCD and enable clock */
+ at91_lcd_hw_init();
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+ ulong dram_size;
+ uint64_t nand_size;
+ int i;
+ char temp[32];
+
+ lcd_printf("%s\n", U_BOOT_VERSION);
+ lcd_printf("(C) 2013 ATMEL Corp\n");
+ lcd_printf("at91@atmel.com\n");
+ lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+
+ nand_size = 0;
+#ifdef CONFIG_NAND_ATMEL
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+#endif
+ lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
+ dram_size >> 20, nand_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+int board_early_init_f(void)
+{
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+ at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+ at91_seriald_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_NAND_ATMEL
+ sama5d3xek_nand_hw_init();
+#endif
+#ifndef CONFIG_SYS_NO_FLASH
+ sama5d3xek_nor_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+ sama5d3xek_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+ at91_udp_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+ sama5d3xek_mci_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SPI
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+ if (has_emac())
+ at91_macb_hw_init();
+ if (has_gmac())
+ at91_gmac_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ if (has_lcdc())
+ sama5d3xek_lcd_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* board specific timings for GMAC */
+ if (has_gmac()) {
+ /* rx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x2222);
+ /* tx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ 0x2222);
+ /* rx/tx clock delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf2f4);
+ }
+
+ /* always run the PHY's config routine */
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+#ifdef CONFIG_MACB
+ if (has_emac())
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+ if (has_gmac())
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+ usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+ usb_eth_initialize(bis);
+#endif
+#endif
+
+ return rc;
+}
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+ int rc = 0;
+
+ rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
+
+ return rc;
+}
+#endif
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs < 4;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 0:
+ at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
+ case 1:
+ at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
+ case 2:
+ at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
+ case 3:
+ at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
+ default:
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 0:
+ at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
+ case 1:
+ at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
+ case 2:
+ at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
+ case 3:
+ at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
+ default:
+ break;
+ }
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+ sama5d3xek_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+ sama5d3xek_nand_hw_init();
+#elif CONFIG_SYS_USE_SERIALFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_14 |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+ ATMEL_MPDDRC_CR_ENRDM_ON |
+ ATMEL_MPDDRC_CR_NB_8BANKS |
+ ATMEL_MPDDRC_CR_NDQS_DISABLED |
+ ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+ ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+ /*
+ * As the DDR2-SDRAm device requires a refresh time is 7.8125us
+ * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
+ */
+ ddr2->rtr = 0x411;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct atmel_mpddr ddr2;
+
+ ddr2_conf(&ddr2);
+
+ /* enable MPDDR clock */
+ at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+ writel(0x4, &pmc->scer);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ u32 tmp;
+
+ tmp = AT91_PMC_PLLAR_29 |
+ AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+ AT91_PMC_PLLXR_MUL(43) |
+ AT91_PMC_PLLXR_DIV(1);
+ at91_plla_init(tmp);
+
+ writel(0x3 << 8, &pmc->pllicpr);
+
+ tmp = AT91_PMC_MCKR_MDIV_4 |
+ AT91_PMC_MCKR_CSS_PLLA;
+ at91_mck_init(tmp);
+}
+#endif
diff --git a/board/atmel/sama5d4_xplained/Kconfig b/board/atmel/sama5d4_xplained/Kconfig
new file mode 100644
index 0000000..f320a68
--- /dev/null
+++ b/board/atmel/sama5d4_xplained/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D4_XPLAINED
+
+config SYS_BOARD
+ default "sama5d4_xplained"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama5d4_xplained"
+
+endif
diff --git a/board/atmel/sama5d4_xplained/MAINTAINERS b/board/atmel/sama5d4_xplained/MAINTAINERS
new file mode 100644
index 0000000..035f64c
--- /dev/null
+++ b/board/atmel/sama5d4_xplained/MAINTAINERS
@@ -0,0 +1,8 @@
+SAMA5D4 XPLAINED ULTRA BOARD
+M: Bo Shen <voice.shen@atmel.com>
+S: Maintained
+F: board/atmel/sama5d4_xplained/
+F: include/configs/sama5d4_xplained.h
+F: configs/sama5d4_xplained_mmc_defconfig
+F: configs/sama5d4_xplained_nandflash_defconfig
+F: configs/sama5d4_xplained_spiflash_defconfig
diff --git a/board/atmel/sama5d4_xplained/Makefile b/board/atmel/sama5d4_xplained/Makefile
new file mode 100644
index 0000000..c59b12d
--- /dev/null
+++ b/board/atmel/sama5d4_xplained/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2014 Atmel
+# Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sama5d4_xplained.o
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
new file mode 100644
index 0000000..2758c5c
--- /dev/null
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (C) 2014 Atmel
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/sama5d4.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ATMEL_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
+}
+
+static void sama5d4_xplained_spi0_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
+
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_NAND_ATMEL
+static void sama5d4_xplained_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+ at91_periph_clk_enable(ATMEL_ID_SMC);
+
+ /* Configure SMC CS3 for NAND */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+ AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
+ AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
+ AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+
+ at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
+ at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
+ at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
+ at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
+ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
+ at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
+ at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
+ at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
+ at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
+ at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d4_xplained_usb_hw_init(void)
+{
+ at91_set_pio_output(AT91_PIO_PORTE, 11, 1);
+ at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 480,
+ .vl_row = 272,
+ .vl_clk = 9000000,
+ .vl_bpix = LCD_BPP,
+ .vl_tft = 1,
+ .vl_hsync_len = 41,
+ .vl_left_margin = 2,
+ .vl_right_margin = 2,
+ .vl_vsync_len = 11,
+ .vl_upper_margin = 2,
+ .vl_lower_margin = 2,
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+/* No power up/down pin for the LCD pannel */
+void lcd_enable(void) { /* Empty! */ }
+void lcd_disable(void) { /* Empty! */ }
+
+unsigned int has_lcdc(void)
+{
+ return 1;
+}
+
+static void sama5d4_xplained_lcd_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
+ at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
+ at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
+
+ at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
+
+ at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */
+ at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */
+ at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
+ at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
+
+ at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */
+ at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */
+ at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
+ at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size;
+ int i;
+ char temp[32];
+
+ lcd_printf("2014 ATMEL Corp\n");
+ lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+
+ nand_size = 0;
+#ifdef CONFIG_NAND_ATMEL
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+#endif
+ lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
+ dram_size >> 20, nand_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+
+#endif /* CONFIG_LCD */
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void sama5d4_xplained_mci1_hw_init(void)
+{
+ at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
+ at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
+ at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
+ at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
+ at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
+ at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
+
+ /*
+ * As the mci io internal pull down is too strong, so if the io needs
+ * external pull up, the pull up resistor will be very small, if so
+ * the power consumption will increase, so disable the interanl pull
+ * down to save the power.
+ */
+ at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
+ at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
+ at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
+ at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
+ at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
+ at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_MCI1);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ return atmel_mci_init((void *)ATMEL_BASE_MCI1);
+}
+#endif /* CONFIG_GENERIC_ATMEL_MCI */
+
+#ifdef CONFIG_MACB
+void sama5d4_xplained_macb0_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
+ at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
+ at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
+ at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
+ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
+ at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
+ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
+ at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_GMAC0);
+}
+#endif
+
+static void sama5d4_xplained_serial3_hw_init(void)
+{
+ at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
+ at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_USART3);
+}
+
+int board_early_init_f(void)
+{
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+ at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+ sama5d4_xplained_serial3_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+ sama5d4_xplained_spi0_hw_init();
+#endif
+#ifdef CONFIG_NAND_ATMEL
+ sama5d4_xplained_nand_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+ sama5d4_xplained_mci1_hw_init();
+#endif
+#ifdef CONFIG_MACB
+ sama5d4_xplained_macb0_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ sama5d4_xplained_lcd_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+ sama5d4_xplained_usb_hw_init();
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
+#endif
+
+ return rc;
+}
diff --git a/board/atmel/sama5d4ek/Kconfig b/board/atmel/sama5d4ek/Kconfig
new file mode 100644
index 0000000..7dc569c
--- /dev/null
+++ b/board/atmel/sama5d4ek/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D4EK
+
+config SYS_BOARD
+ default "sama5d4ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sama5d4ek"
+
+endif
diff --git a/board/atmel/sama5d4ek/MAINTAINERS b/board/atmel/sama5d4ek/MAINTAINERS
new file mode 100644
index 0000000..afe88dd
--- /dev/null
+++ b/board/atmel/sama5d4ek/MAINTAINERS
@@ -0,0 +1,8 @@
+SAMA5D4EK BOARD
+M: Bo Shen <voice.shen@atmel.com>
+S: Maintained
+F: board/atmel/sama5d4ek/
+F: include/configs/sama5d4ek.h
+F: configs/sama5d4ek_mmc_defconfig
+F: configs/sama5d4ek_nandflash_defconfig
+F: configs/sama5d4ek_spiflash_defconfig
diff --git a/board/atmel/sama5d4ek/Makefile b/board/atmel/sama5d4ek/Makefile
new file mode 100644
index 0000000..55823ba
--- /dev/null
+++ b/board/atmel/sama5d4ek/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2014 Atmel
+# Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sama5d4ek.o
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
new file mode 100644
index 0000000..d3039c0
--- /dev/null
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright (C) 2014 Atmel
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/sama5d4.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <nand.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ATMEL_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
+}
+
+static void sama5d4ek_spi0_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */
+
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_NAND_ATMEL
+static void sama5d4ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+
+ at91_periph_clk_enable(ATMEL_ID_SMC);
+
+ /* Configure SMC CS3 for NAND */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+ AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
+ AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
+ AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+
+ at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
+ at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
+ at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
+ at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
+ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
+ at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
+ at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
+ at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
+ at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
+ at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void sama5d4ek_usb_hw_init(void)
+{
+ at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
+ at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
+ at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 800,
+ .vl_row = 480,
+ .vl_clk = 33260000,
+ .vl_bpix = LCD_BPP,
+ .vl_tft = 1,
+ .vl_hsync_len = 5,
+ .vl_left_margin = 128,
+ .vl_right_margin = 0,
+ .vl_vsync_len = 5,
+ .vl_upper_margin = 23,
+ .vl_lower_margin = 22,
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+/* No power up/down pin for the LCD pannel */
+void lcd_enable(void) { /* Empty! */ }
+void lcd_disable(void) { /* Empty! */ }
+
+unsigned int has_lcdc(void)
+{
+ return 1;
+}
+
+static void sama5d4ek_lcd_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
+ at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
+ at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
+
+ at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
+
+ at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
+ at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
+
+ at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
+ at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size;
+ int i;
+ char temp[32];
+
+ lcd_printf("2014 ATMEL Corp\n");
+ lcd_printf("at91@atmel.com\n");
+ lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+
+ nand_size = 0;
+#ifdef CONFIG_NAND_ATMEL
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+#endif
+ lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
+ dram_size >> 20, nand_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+
+#endif /* CONFIG_LCD */
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void sama5d4ek_mci1_hw_init(void)
+{
+ at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */
+ at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */
+ at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */
+ at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */
+ at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */
+ at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */
+
+ /*
+ * As the mci io internal pull down is too strong, so if the io needs
+ * external pull up, the pull up resistor will be very small, if so
+ * the power consumption will increase, so disable the interanl pull
+ * down to save the power.
+ */
+ at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
+ at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
+ at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
+ at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
+ at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
+ at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_MCI1);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ /* Enable power for MCI1 interface */
+ at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
+
+ return atmel_mci_init((void *)ATMEL_BASE_MCI1);
+}
+#endif /* CONFIG_GENERIC_ATMEL_MCI */
+
+#ifdef CONFIG_MACB
+void sama5d4ek_macb0_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */
+ at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */
+ at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */
+ at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */
+ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */
+ at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */
+ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */
+ at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_GMAC0);
+}
+#endif
+
+static void sama5d4ek_serial3_hw_init(void)
+{
+ at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
+ at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_USART3);
+}
+
+int board_early_init_f(void)
+{
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+ at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+ sama5d4ek_serial3_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+ sama5d4ek_spi0_hw_init();
+#endif
+#ifdef CONFIG_NAND_ATMEL
+ sama5d4ek_nand_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+ sama5d4ek_mci1_hw_init();
+#endif
+#ifdef CONFIG_MACB
+ sama5d4ek_macb0_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ sama5d4ek_lcd_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+ sama5d4ek_usb_hw_init();
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
+#endif
+
+ return rc;
+}
diff --git a/board/avionic-design/common/pinmux-config-tamonten-ng.h b/board/avionic-design/common/pinmux-config-tamonten-ng.h
new file mode 100644
index 0000000..00634f1
--- /dev/null
+++ b/board/avionic-design/common/pinmux-config-tamonten-ng.h
@@ -0,0 +1,385 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_
+#define _PINMUX_CONFIG_TAMONTEN_NG_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static struct pmux_pingrp_config tamonten_ng_pinmux_common[] = {
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS6_N_PI3, RSVD1, UP, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux */
+ LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* I2C1 pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C2 pinmux */
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C3 pinmux */
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C4 pinmux */
+ I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* Power I2C pinmux */
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* UART1 */
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT),
+
+ /* UART2 */
+ DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
+
+ /* UART3 */
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+
+ /* UART4 */
+ DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
+
+ /* DAP */
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+
+ /* I2S1 */
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
+
+ /* SPDIF */
+ DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
+
+ /* I2S2 */
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+
+ /* DAP4 */
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
+
+ /* Tamonten GPIO */
+ DEFAULT_PINMUX(PV2, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI2_CS1_N_PW2, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* LCD */
+ DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
+
+ /* BT656 */
+ LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC_PD7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2_PL0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3_PL1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5_PL3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7_PL5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D11_PT3, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* GPIOs */
+ DEFAULT_PINMUX(PU5, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* LCD BL */
+ DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD10_PH2, RSVD4, NORMAL, NORMAL, OUTPUT),
+
+ /* SPI4 */
+ DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT),
+
+ /* Video input GPIO */
+ DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* Sensor GPIO */
+ DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* JTAG */
+ DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
+
+ /* Power controls */
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* SPI1 */
+ DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
+
+ /* PMU */
+ DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT),
+
+ /* PCI */
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+
+ /* HDMI */
+ DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
+};
+
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+ /* UART1 - NC */
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, INPUT),
+
+ /* UART2 - NC */
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
+
+ /* DAP - NC */
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* DAP4 - NC */
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+
+ /* Tamonten GPIO - NC */
+ DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
+
+ /* BT656 - NC */
+ LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1_PD5, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* GPIO - NC */
+ DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU4, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* Video input - NC */
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB5, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11_PS3, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* KBC keys - NC */
+ DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
+
+ /* PMU - NC */
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* Power rails GPIO - NC */
+ DEFAULT_PINMUX(SPI2_SCK_PX2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB4, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* Others - NC */
+ DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+static struct pmux_drvgrp_config tamonten_ng_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+ DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
+ SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif /* _PINMUX_CONFIG_TAMONTEN_NG_H_ */
diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c
new file mode 100644
index 0000000..86a0844
--- /dev/null
+++ b/board/avionic-design/common/tamonten-ng.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include "pinmux-config-tamonten-ng.h"
+#include <i2c.h>
+
+#define PMU_I2C_ADDRESS 0x2D
+
+#define PMU_REG_LDO5 0x32
+
+#define PMU_REG_LDO_HIGH_POWER 1
+
+/* Voltage selection for the LDOs with 100mV resolution */
+#define PMU_REG_LDO_SEL_100(mV) ((((mV - 1000) / 100) + 2) << 2)
+
+#define PMU_REG_LDO_100(st, mV) (PMU_REG_LDO_##st | PMU_REG_LDO_SEL_100(mV))
+
+#define PMU_LDO5(st, mV) PMU_REG_LDO_100(st, mV)
+
+void pinmux_init(void)
+{
+ pinmux_config_pingrp_table(tamonten_ng_pinmux_common,
+ ARRAY_SIZE(tamonten_ng_pinmux_common));
+ pinmux_config_pingrp_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
+
+ /* Initialize any non-default pad configs (APB_MISC_GP regs) */
+ pinmux_config_drvgrp_table(tamonten_ng_padctrl,
+ ARRAY_SIZE(tamonten_ng_padctrl));
+}
+
+void gpio_early_init(void)
+{
+ /* Turn on the alive signal */
+ gpio_request(GPIO_PV2, "ALIVE");
+ gpio_direction_output(GPIO_PV2, 1);
+
+ /* Remove the reset on the external periph */
+ gpio_request(GPIO_PI4, "nRST_PERIPH");
+ gpio_direction_output(GPIO_PI4, 1);
+}
+
+void pmu_write(uchar reg, uchar data)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(4, PMU_I2C_ADDRESS, &dev);
+ if (ret) {
+ debug("%s: Cannot find PMIC I2C chip\n", __func__);
+ return;
+ }
+ i2c_write(dev, reg, &data, 1);
+}
+
+/*
+ * Do I2C/PMU writes to bring up SD card bus power
+ *
+ */
+void board_sdmmc_voltage_init(void)
+{
+ /* Enable LDO5 with 3.3v for SDMMC3 */
+ pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300));
+
+ /* Switch the power on */
+ gpio_request(GPIO_PJ2, "EN_3V3_EMMC");
+ gpio_direction_output(GPIO_PJ2, 1);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+ /*
+ * NOTE: We don't do mmc-specific pin muxes here.
+ * They were done globally in pinmux_init().
+ */
+
+ /* Bring up the SDIO1 power rail */
+ board_sdmmc_voltage_init();
+}
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
new file mode 100644
index 0000000..9c86779
--- /dev/null
+++ b/board/avionic-design/common/tamonten.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2011-2012
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch-tegra/uart.h>
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+void gpio_early_init(void)
+{
+ gpio_request(GPIO_PI4, NULL);
+ gpio_direction_output(GPIO_PI4, 1);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
+ /* for write-protect GPIO PI6 */
+ pinmux_tristate_disable(PMUX_PINGRP_ATA);
+ /* for CD GPIO PH2 */
+ pinmux_tristate_disable(PMUX_PINGRP_ATD);
+}
+#endif
diff --git a/board/avionic-design/medcom-wide/Kconfig b/board/avionic-design/medcom-wide/Kconfig
new file mode 100644
index 0000000..267647c
--- /dev/null
+++ b/board/avionic-design/medcom-wide/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MEDCOM_WIDE
+
+config SYS_BOARD
+ default "medcom-wide"
+
+config SYS_VENDOR
+ default "avionic-design"
+
+config SYS_CONFIG_NAME
+ default "medcom-wide"
+
+endif
diff --git a/board/avionic-design/medcom-wide/MAINTAINERS b/board/avionic-design/medcom-wide/MAINTAINERS
new file mode 100644
index 0000000..0a00fcf
--- /dev/null
+++ b/board/avionic-design/medcom-wide/MAINTAINERS
@@ -0,0 +1,6 @@
+MEDCOM-WIDE BOARD
+M: Alban Bedel <alban.bedel@avionic-design.de>
+S: Maintained
+F: board/avionic-design/medcom-wide/
+F: include/configs/medcom-wide.h
+F: configs/medcom-wide_defconfig
diff --git a/board/avionic-design/medcom-wide/Makefile b/board/avionic-design/medcom-wide/Makefile
new file mode 100644
index 0000000..bcf7ccf
--- /dev/null
+++ b/board/avionic-design/medcom-wide/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+# (C) Copyright 2011,2012
+# Avionic Design GmbH <www.avionic-design.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ../common/tamonten.o
+
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/avionic-design/plutux/Kconfig b/board/avionic-design/plutux/Kconfig
new file mode 100644
index 0000000..09a3ac9
--- /dev/null
+++ b/board/avionic-design/plutux/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PLUTUX
+
+config SYS_BOARD
+ default "plutux"
+
+config SYS_VENDOR
+ default "avionic-design"
+
+config SYS_CONFIG_NAME
+ default "plutux"
+
+endif
diff --git a/board/avionic-design/plutux/MAINTAINERS b/board/avionic-design/plutux/MAINTAINERS
new file mode 100644
index 0000000..e8ef509
--- /dev/null
+++ b/board/avionic-design/plutux/MAINTAINERS
@@ -0,0 +1,6 @@
+PLUTUX BOARD
+M: Alban Bedel <alban.bedel@avionic-design.de>
+S: Maintained
+F: board/avionic-design/plutux/
+F: include/configs/plutux.h
+F: configs/plutux_defconfig
diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile
new file mode 100644
index 0000000..bcf7ccf
--- /dev/null
+++ b/board/avionic-design/plutux/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+# (C) Copyright 2011,2012
+# Avionic Design GmbH <www.avionic-design.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ../common/tamonten.o
+
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/avionic-design/tec-ng/Kconfig b/board/avionic-design/tec-ng/Kconfig
new file mode 100644
index 0000000..36a0cec
--- /dev/null
+++ b/board/avionic-design/tec-ng/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TEC_NG
+
+config SYS_BOARD
+ default "tec-ng"
+
+config SYS_VENDOR
+ default "avionic-design"
+
+config SYS_CONFIG_NAME
+ default "tec-ng"
+
+endif
diff --git a/board/avionic-design/tec-ng/MAINTAINERS b/board/avionic-design/tec-ng/MAINTAINERS
new file mode 100644
index 0000000..5cbdf8e
--- /dev/null
+++ b/board/avionic-design/tec-ng/MAINTAINERS
@@ -0,0 +1,6 @@
+TEC-NG BOARD
+M: Alban Bedel <alban.bedel@avionic-design.de>
+S: Maintained
+F: board/avionic-design/tec-ng/
+F: include/configs/tec-ng.h
+F: configs/tec-ng_defconfig
diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile
new file mode 100644
index 0000000..a556b92
--- /dev/null
+++ b/board/avionic-design/tec-ng/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013
+# Avionic Design GmbH <www.avionic-design.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ../common/tamonten-ng.o
+
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/avionic-design/tec/Kconfig b/board/avionic-design/tec/Kconfig
new file mode 100644
index 0000000..bc9751b
--- /dev/null
+++ b/board/avionic-design/tec/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TEC
+
+config SYS_BOARD
+ default "tec"
+
+config SYS_VENDOR
+ default "avionic-design"
+
+config SYS_CONFIG_NAME
+ default "tec"
+
+endif
diff --git a/board/avionic-design/tec/MAINTAINERS b/board/avionic-design/tec/MAINTAINERS
new file mode 100644
index 0000000..10f1aac
--- /dev/null
+++ b/board/avionic-design/tec/MAINTAINERS
@@ -0,0 +1,6 @@
+TEC BOARD
+M: Alban Bedel <alban.bedel@avionic-design.de>
+S: Maintained
+F: board/avionic-design/tec/
+F: include/configs/tec.h
+F: configs/tec_defconfig
diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile
new file mode 100644
index 0000000..bcf7ccf
--- /dev/null
+++ b/board/avionic-design/tec/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+# (C) Copyright 2011,2012
+# Avionic Design GmbH <www.avionic-design.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ../common/tamonten.o
+
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/avnet/fx12mm/Kconfig b/board/avnet/fx12mm/Kconfig
new file mode 100644
index 0000000..0b67ebd
--- /dev/null
+++ b/board/avnet/fx12mm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_FX12MM
+
+config SYS_BOARD
+ default "fx12mm"
+
+config SYS_VENDOR
+ default "avnet"
+
+config SYS_CONFIG_NAME
+ default "fx12mm"
+
+endif
diff --git a/board/avnet/fx12mm/MAINTAINERS b/board/avnet/fx12mm/MAINTAINERS
new file mode 100644
index 0000000..c92e258
--- /dev/null
+++ b/board/avnet/fx12mm/MAINTAINERS
@@ -0,0 +1,7 @@
+FX12MM BOARD
+M: Georg Schardt <schardt@team-ctech.de>
+S: Maintained
+F: board/avnet/fx12mm/
+F: include/configs/fx12mm.h
+F: configs/fx12mm_defconfig
+F: configs/fx12mm_flash_defconfig
diff --git a/board/avnet/fx12mm/Makefile b/board/avnet/fx12mm/Makefile
new file mode 100644
index 0000000..618b42f
--- /dev/null
+++ b/board/avnet/fx12mm/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2008
+# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
+# This work has been supported by: Qtechnology http://qtec.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += fx12mm.o
+
+include $(srctree)/board/xilinx/ppc405-generic/Makefile
diff --git a/board/avnet/fx12mm/fx12mm.c b/board/avnet/fx12mm/fx12mm.c
new file mode 100644
index 0000000..92e1cfb
--- /dev/null
+++ b/board/avnet/fx12mm/fx12mm.c
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2008
+ *
+ * Author: Xilinx Inc.
+ *
+ * Modified by:
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+ char buf[64];
+ int i;
+ int l = getenv_f("serial#", buf, sizeof(buf));
+
+ if (l < 0) {
+ printf("Avnet Virtex4 FX12 with no serial #");
+ } else {
+ printf("Avnet Virtex4 FX12 Minimodul # ");
+ for (i = 0; i < l; ++i) {
+ if (buf[i] == ' ')
+ break;
+ putc(buf[i]);
+ }
+ }
+ putc('\n');
+ return 0;
+}
diff --git a/board/avnet/fx12mm/xparameters.h b/board/avnet/fx12mm/xparameters.h
new file mode 100644
index 0000000..94f682f
--- /dev/null
+++ b/board/avnet/fx12mm/xparameters.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2008
+ *
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * CAUTION: This file is based on the xparameters.h automatically
+ * generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5
+ */
+
+#ifndef __XPARAMETER_H__
+#define __XPARAMETER_H__
+
+/* RS232 */
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
+#define XPAR_UARTNS550_0_BASEADDR 0x83E00000
+
+
+/* INT_C */
+#define XPAR_XPS_INTC_0_DEVICE_ID 0
+#define XPAR_XPS_INTC_0_BASEADDR 0x81800000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2
+
+/* CPU core clock */
+#define XPAR_CORE_CLOCK_FREQ_HZ 300000000
+#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
+
+/* RAM */
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
+
+/* FLASH */
+#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000
+
+#endif
diff --git a/board/avnet/v5fx30teval/Kconfig b/board/avnet/v5fx30teval/Kconfig
new file mode 100644
index 0000000..079387b
--- /dev/null
+++ b/board/avnet/v5fx30teval/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_V5FX30TEVAL
+
+config SYS_BOARD
+ default "v5fx30teval"
+
+config SYS_VENDOR
+ default "avnet"
+
+config SYS_CONFIG_NAME
+ default "v5fx30teval"
+
+endif
diff --git a/board/avnet/v5fx30teval/MAINTAINERS b/board/avnet/v5fx30teval/MAINTAINERS
new file mode 100644
index 0000000..91dde7a
--- /dev/null
+++ b/board/avnet/v5fx30teval/MAINTAINERS
@@ -0,0 +1,7 @@
+V5FX30TEVAL BOARD
+M: Ricardo Ribalda <ricardo.ribalda@uam.es>
+S: Maintained
+F: board/avnet/v5fx30teval/
+F: include/configs/v5fx30teval.h
+F: configs/v5fx30teval_defconfig
+F: configs/v5fx30teval_flash_defconfig
diff --git a/board/avnet/v5fx30teval/Makefile b/board/avnet/v5fx30teval/Makefile
new file mode 100644
index 0000000..8c41af0
--- /dev/null
+++ b/board/avnet/v5fx30teval/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2008
+# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
+# This work has been supported by: Qtechnology http://qtec.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += v5fx30teval.o
+
+include $(srctree)/board/xilinx/ppc440-generic/Makefile
diff --git a/board/avnet/v5fx30teval/v5fx30teval.c b/board/avnet/v5fx30teval/v5fx30teval.c
new file mode 100644
index 0000000..68b0eb9
--- /dev/null
+++ b/board/avnet/v5fx30teval/v5fx30teval.c
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+
+int checkboard(void)
+{
+ puts("Avnet Virtex 5 FX30 Evaluation Board\n");
+ return 0;
+}
diff --git a/board/avnet/v5fx30teval/xparameters.h b/board/avnet/v5fx30teval/xparameters.h
new file mode 100644
index 0000000..95b8c28
--- /dev/null
+++ b/board/avnet/v5fx30teval/xparameters.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * based on xparameters.h by Xilinx
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
+#define XPAR_INTC_0_BASEADDR 0x81800000
+#define XPAR_UARTLITE_0_BASEADDR 0x84000000
+#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000
+#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
+#define XPAR_UARTLITE_0_BAUDRATE 9600
+
+#endif
diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig
new file mode 100644
index 0000000..7f8a6a1
--- /dev/null
+++ b/board/bachmann/ot1200/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_OT1200
+
+config SYS_BOARD
+ default "ot1200"
+
+config SYS_VENDOR
+ default "bachmann"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "ot1200"
+
+endif
diff --git a/board/bachmann/ot1200/MAINTAINERS b/board/bachmann/ot1200/MAINTAINERS
new file mode 100644
index 0000000..ad75c24
--- /dev/null
+++ b/board/bachmann/ot1200/MAINTAINERS
@@ -0,0 +1,6 @@
+BACHMANN ELECTRONIC OT1200 BOARD
+M: Christian Gmeiner <christian.gmeiner@gmail.com>
+S: Maintained
+F: board/bachmann/ot1200
+F: include/configs/ot1200.h
+F: configs/ot1200*_defconfig
diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile
new file mode 100644
index 0000000..1bd42e8
--- /dev/null
+++ b/board/bachmann/ot1200/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
+# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ot1200.o
diff --git a/board/bachmann/ot1200/README b/board/bachmann/ot1200/README
new file mode 100644
index 0000000..c03d44e
--- /dev/null
+++ b/board/bachmann/ot1200/README
@@ -0,0 +1,20 @@
+U-Boot for the Bachmann electronic GmbH OT1200 devices
+
+There are two different versions of the base board, which differ
+in the way ethernet is done. The variant detection is done during
+runtime based on the address of the found phy.
+
+- "mr" variant
+FEC is connected directly to an ethernet switch (KSZ8895). The ethernet
+port is always up and auto-negotiation is not possible.
+
+- normal variant
+FEC is connected to a normal phy and auto-negotiation is possible.
+
+
+The variant name is part of the dtb file name loaded by u-boot. This
+make is possible to boot the linux kernel and make use variant specific
+devicetree (fixed-phy link).
+
+In order to support different display resoltuions/sizes the OT1200 devices
+are making use of EDID data stored in an i2c EEPROM.
diff --git a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
new file mode 100644
index 0000000..bb6c60b
--- /dev/null
+++ b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+
+DATA 4 0x020e05ac 0x00020030
+DATA 4 0x020e05b4 0x00020030
+DATA 4 0x020e0528 0x00020030
+DATA 4 0x020e0520 0x00020030
+
+DATA 4 0x020e0514 0x00020030
+DATA 4 0x020e0510 0x00020030
+DATA 4 0x020e05bc 0x00020030
+DATA 4 0x020e05c4 0x00020030
+
+DATA 4 0x020e056c 0x00020030
+DATA 4 0x020e0578 0x00020030
+DATA 4 0x020e0588 0x00020030
+DATA 4 0x020e0594 0x00020030
+
+DATA 4 0x020e057c 0x00020030
+DATA 4 0x020e0590 0x00003000
+DATA 4 0x020e0598 0x00003000
+DATA 4 0x020e058c 0x00000000
+
+DATA 4 0x020e059c 0x00003030
+DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0750 0x00020000
+
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0798 0x000C0000
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b0018 0x00081740
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b000c 0x555A7974
+DATA 4 0x021b0010 0xDB538F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b002c 0x000026D2
+
+DATA 4 0x021b0030 0x005A1023
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0x831A0000
+
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x0408803A
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x0000803B
+DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x00428039
+DATA 4 0x021b001c 0x19308030
+DATA 4 0x021b001c 0x19308038
+
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b001c 0x04008048
+DATA 4 0x021b0800 0xA1380003
+DATA 4 0x021b4800 0xA1380003
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b4818 0x00022227
+
+DATA 4 0x021b083c 0x434B0350
+DATA 4 0x021b0840 0x034C0359
+DATA 4 0x021b483c 0x434B0350
+DATA 4 0x021b4840 0x03650348
+DATA 4 0x021b0848 0x4436383B
+DATA 4 0x021b4848 0x39393341
+DATA 4 0x021b0850 0x35373933
+DATA 4 0x021b4850 0x48254A36
+
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+
+DATA 4 0x021b480c 0x00440044
+DATA 4 0x021b4810 0x00440044
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b001c 0x00000000
+DATA 4 0x021b0404 0x00011006
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4 0x020c4060 0x000000fb
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
new file mode 100644
index 0000000..93f3d65
--- /dev/null
+++ b/board/bachmann/ot1200/ot1200.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014, Bachmann electronic GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sata.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/arch/crm_regs.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <pca953x.h>
+#include <asm/gpio.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
+ PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \
+ PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
+ PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+ MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+static void setup_iomux_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
+}
+
+static iomux_v3_cfg_t const feature_pads[] = {
+ /* SD card detect */
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
+
+ /* eMMC soldered? */
+ MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
+};
+
+static void setup_iomux_features(void)
+{
+ imx_iomux_v3_setup_multiple_pads(feature_pads,
+ ARRAY_SIZE(feature_pads));
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_spi();
+ setup_iomux_features();
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret;
+
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
+ gpio_direction_input(IMX_GPIO_NR(4, 5));
+ ret = gpio_get_value(IMX_GPIO_NR(4, 5));
+ } else {
+ gpio_direction_input(IMX_GPIO_NR(1, 5));
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
+ }
+
+ return ret;
+}
+
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ u32 index = 0;
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+ usdhc_cfg[0].max_bus_width = 8;
+ usdhc_cfg[1].max_bus_width = 4;
+
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C3 - IO expander */
+static struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+ .gp = IMX_GPIO_NR(3, 17)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+static iomux_v3_cfg_t const pwm_pad[] = {
+ MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM),
+};
+
+static void leds_on(void)
+{
+ /* turn on all possible leds connected via GPIO expander */
+ i2c_set_bus_num(2);
+ pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
+ pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
+}
+
+static void backlight_lcd_off(void)
+{
+ unsigned gpio = IMX_GPIO_NR(2, 0);
+ gpio_direction_output(gpio, 0);
+
+ gpio = IMX_GPIO_NR(2, 3);
+ gpio_direction_output(gpio, 0);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ uint32_t base = IMX_FEC_BASE;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret;
+
+ setup_iomux_enet();
+
+ bus = fec_get_miibus(base, -1);
+ if (!bus)
+ return 0;
+
+ /* scan phy 0 and 5 */
+ phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
+ if (!phydev) {
+ free(bus);
+ return 0;
+ }
+
+ /* depending on the phy address we can detect our board version */
+ if (phydev->addr == 0)
+ setenv("boardver", "");
+ else
+ setenv("boardver", "mr");
+
+ printf("using phy at %d\n", phydev->addr);
+ ret = fec_probe(bis, -1, base, bus, phydev);
+ if (ret) {
+ printf("FEC MXC: %s:failed\n", __func__);
+ free(phydev);
+ free(bus);
+ }
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ backlight_lcd_off();
+
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+ leds_on();
+
+ /* enable ecspi3 clocks */
+ enable_cspi_clock(1, 2);
+
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: "CONFIG_SYS_BOARD"\n");
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ return 0;
+}
diff --git a/board/balloon3/Kconfig b/board/balloon3/Kconfig
new file mode 100644
index 0000000..53b7a9a
--- /dev/null
+++ b/board/balloon3/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BALLOON3
+
+config SYS_BOARD
+ default "balloon3"
+
+config SYS_CONFIG_NAME
+ default "balloon3"
+
+endif
diff --git a/board/balloon3/MAINTAINERS b/board/balloon3/MAINTAINERS
new file mode 100644
index 0000000..df9a5bb
--- /dev/null
+++ b/board/balloon3/MAINTAINERS
@@ -0,0 +1,6 @@
+BALLOON3 BOARD
+M: Marek Vasut <marek.vasut@gmail.com>
+S: Maintained
+F: board/balloon3/
+F: include/configs/balloon3.h
+F: configs/balloon3_defconfig
diff --git a/board/balloon3/Makefile b/board/balloon3/Makefile
new file mode 100644
index 0000000..d7fb5e0
--- /dev/null
+++ b/board/balloon3/Makefile
@@ -0,0 +1,9 @@
+#
+# Balloon3 Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := balloon3.o
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
new file mode 100644
index 0000000..aa108ca
--- /dev/null
+++ b/board/balloon3/balloon3.c
@@ -0,0 +1,221 @@
+/*
+ * Balloon3 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pxa.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <spartan3.h>
+#include <command.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void balloon3_init_fpga(void);
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* arch number of vpac270 */
+ gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Init the FPGA */
+ balloon3_init_fpga();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ pxa2xx_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+}
+
+#ifdef CONFIG_CMD_USB
+int board_usb_init(int index, enum usb_init_type init)
+{
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
+
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
+
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+ /* Clear any OTG Pin Hold */
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+ /* Set port power control mask bits, only 3 ports. */
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+ /* enable port 2 */
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+void usb_board_stop(void)
+{
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+ udelay(11);
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
+ udelay(10);
+
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+ return;
+}
+#endif
+
+#if defined(CONFIG_FPGA)
+/* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
+int fpga_pgm_fn(int nassert, int nflush, int cookie)
+{
+ if (nassert)
+ writel(0x80, GPCR3);
+ else
+ writel(0x80, GPSR3);
+ if (nflush)
+ writel(0x100, GPCR3);
+ else
+ writel(0x100, GPSR3);
+ return nassert;
+}
+
+/* Check GPIO83 -- INITB */
+int fpga_init_fn(int cookie)
+{
+ return !(readl(GPLR2) & 0x80000);
+}
+
+/* Check GPIO84 -- BUSY */
+int fpga_busy_fn(int cookie)
+{
+ return !(readl(GPLR2) & 0x100000);
+}
+
+/* Check GPIO111 -- DONE */
+int fpga_done_fn(int cookie)
+{
+ return readl(GPLR3) & 0x8000;
+}
+
+/* Configure GPIO104 as GPIO and deassert it */
+int fpga_pre_config_fn(int cookie)
+{
+ writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
+ writel(0x100, GPCR3);
+ return 0;
+}
+
+/* Configure GPIO104 as nSKTSEL */
+int fpga_post_config_fn(int cookie)
+{
+ writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
+ return 0;
+}
+
+/* Toggle RDnWR */
+int fpga_wr_fn(int nassert_write, int flush, int cookie)
+{
+ udelay(1000);
+
+ if (nassert_write)
+ writel(0x100, GPCR3);
+ else
+ writel(0x100, GPSR3);
+
+ return nassert_write;
+}
+
+/* Write program to the FPGA */
+int fpga_wdata_fn(uchar data, int flush, int cookie)
+{
+ writeb(data, 0x10f00000);
+ return 0;
+}
+
+/* Toggle Clock pin -- NO-OP */
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ return assert_clk;
+}
+
+/* Toggle ChipSelect pin -- NO-OP */
+int fpga_cs_fn(int assert_clk, int flush, int cookie)
+{
+ return assert_clk;
+}
+
+xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = {
+ fpga_pre_config_fn,
+ fpga_pgm_fn,
+ fpga_init_fn,
+ NULL, /* err */
+ fpga_done_fn,
+ fpga_clk_fn,
+ fpga_cs_fn,
+ fpga_wr_fn,
+ NULL, /* rdata */
+ fpga_wdata_fn,
+ fpga_busy_fn,
+ NULL, /* abort */
+ fpga_post_config_fn,
+};
+
+xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
+ (void *)&balloon3_fpga_fns, 0);
+
+/* Initialize the FPGA */
+void balloon3_init_fpga(void)
+{
+ fpga_init();
+ fpga_add(fpga_xilinx, &fpga);
+}
+#else
+void balloon3_init_fpga(void) {}
+#endif /* CONFIG_FPGA */
diff --git a/board/barco/titanium/Kconfig b/board/barco/titanium/Kconfig
new file mode 100644
index 0000000..b6f7c85
--- /dev/null
+++ b/board/barco/titanium/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TITANIUM
+
+config SYS_BOARD
+ default "titanium"
+
+config SYS_VENDOR
+ default "barco"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "titanium"
+
+endif
diff --git a/board/barco/titanium/MAINTAINERS b/board/barco/titanium/MAINTAINERS
new file mode 100644
index 0000000..7e9913f
--- /dev/null
+++ b/board/barco/titanium/MAINTAINERS
@@ -0,0 +1,6 @@
+TITANIUM BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/barco/titanium/
+F: include/configs/titanium.h
+F: configs/titanium_defconfig
diff --git a/board/barco/titanium/Makefile b/board/barco/titanium/Makefile
new file mode 100644
index 0000000..0ad4cb9
--- /dev/null
+++ b/board/barco/titanium/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := titanium.o
diff --git a/board/barco/titanium/imximage.cfg b/board/barco/titanium/imximage.cfg
new file mode 100644
index 0000000..7219256
--- /dev/null
+++ b/board/barco/titanium/imximage.cfg
@@ -0,0 +1,167 @@
+/*
+ * Projectiondesign AS
+ * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * sd, nand
+ */
+BOOT_FROM nand
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/*
+ * MDMISC mirroring interleaved (row/bank/col)
+ */
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
+
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c
new file mode 100644
index 0000000..84a7b84
--- /dev/null
+++ b/board/barco/titanium/titanium.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart4_pads[] = {
+ MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+struct i2c_pads_info i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
+ .gp = IMX_GPIO_NR(7, 11)
+ }
+};
+
+iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const enet_pads1[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* pin 35 - 1 (PHY_AD2) on reset */
+ MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 32 - 1 - (MODE0) all */
+ MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 31 - 1 - (MODE1) all */
+ MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 28 - 1 - (MODE2) all */
+ MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 27 - 1 - (MODE3) all */
+ MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+ MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 42 PHY nRST */
+ MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads2[] = {
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+iomux_v3_cfg_t nfc_pads[] = {
+ MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ imx_iomux_v3_setup_multiple_pads(nfc_pads,
+ ARRAY_SIZE(nfc_pads));
+
+ /* config gpmi and bch clock to 100 MHz */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+
+static void setup_iomux_enet(void)
+{
+ gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+ gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+ imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+ gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+
+ /* Need delay 10ms according to KSZ9021 spec */
+ udelay(1000 * 10);
+ gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+
+ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+}
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+ return 0;
+}
+
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ { USDHC3_BASE_ADDR },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
+ gpio_direction_input(IMX_GPIO_NR(7, 0));
+ return !gpio_get_value(IMX_GPIO_NR(7, 0));
+ }
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ /*
+ * Only one USDHC controller on titianium
+ */
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* min rx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
+ /* min tx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
+ /* max rx/tx clock delay, min rx/tx control */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+
+ return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+ setup_gpmi_nand();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Titanium\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* NAND */
+ { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
+ /* 4 bit bus width */
+ { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
+ { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
+ { NULL, 0 },
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
diff --git a/board/bc3450/Kconfig b/board/bc3450/Kconfig
new file mode 100644
index 0000000..a0fc19f
--- /dev/null
+++ b/board/bc3450/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BC3450
+
+config SYS_BOARD
+ default "bc3450"
+
+config SYS_CONFIG_NAME
+ default "BC3450"
+
+endif
diff --git a/board/bc3450/MAINTAINERS b/board/bc3450/MAINTAINERS
new file mode 100644
index 0000000..81a7076
--- /dev/null
+++ b/board/bc3450/MAINTAINERS
@@ -0,0 +1,6 @@
+BC3450 BOARD
+#M: -
+S: Maintained
+F: board/bc3450/
+F: include/configs/BC3450.h
+F: configs/BC3450_defconfig
diff --git a/board/bc3450/Makefile b/board/bc3450/Makefile
new file mode 100644
index 0000000..b8d22ba
--- /dev/null
+++ b/board/bc3450/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bc3450.o cmd_bc3450.o
diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c
new file mode 100644
index 0000000..a5c6d75
--- /dev/null
+++ b/board/bc3450/bc3450.c
@@ -0,0 +1,586 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * (C) Copyright 2006
+ * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <netdev.h>
+
+#ifdef CONFIG_VIDEO_SM501
+#include <sm501.h>
+#endif
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+#ifdef CONFIG_RTC_MPC5200
+#include <rtc.h>
+#endif
+
+#ifdef CONFIG_PS2MULT
+void ps2mult_early_init(void);
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
+ hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+ hi_addr_bit;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+#endif
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+ hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+ hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set tap delay */
+ *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+ __builtin_ffs(dramsize >> 20) - 1;
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ }
+
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
+
+ /* find RAM size using SDRAM CS1 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize2 = test1;
+ } else {
+ dramsize2 = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20)) {
+ dramsize2 = 0;
+ }
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+ | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13) {
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ } else {
+ dramsize = 0;
+ }
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ if (dramsize2 >= 0x13) {
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ } else {
+ dramsize2 = 0;
+ }
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ return dramsize;
+}
+
+int checkboard (void)
+{
+#if defined (CONFIG_TQM5200)
+ puts ("Board: TQM5200 (TQ-Components GmbH)\n");
+#endif
+
+#if defined (CONFIG_BC3450)
+ puts ("Dev: GERSYS BC3450\n");
+#endif
+
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+ debug ("init_ide_reset\n");
+
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+ debug ("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+ } else {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+ }
+}
+#endif
+
+#ifdef CONFIG_POST
+/*
+ * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
+ * is left open, no keypress is detected.
+ */
+int post_hotkeys_pressed(void)
+{
+ struct mpc5xxx_gpio *gpio;
+
+ gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
+
+ /*
+ * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
+ * CODEC or UART mode. Consumer IrDA should still be possible.
+ */
+ gpio->port_config &= ~(0x07000000);
+ gpio->port_config |= 0x03000000;
+
+ /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
+ gpio->simple_gpioe |= 0x20000000;
+
+ /* Configure GPIO_IRDA_1 as input */
+ gpio->simple_ddr &= ~(0x20000000);
+
+ return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+#ifdef CONFIG_RTC_MPC5200
+ struct rtc_time t;
+
+ /* set to Wed Dec 31 19:00:00 1969 */
+ t.tm_sec = t.tm_min = 0;
+ t.tm_hour = 19;
+ t.tm_mday = 31;
+ t.tm_mon = 12;
+ t.tm_year = 1969;
+ t.tm_wday = 3;
+
+ rtc_set(&t);
+#endif /* CONFIG_RTC_MPC5200 */
+
+#ifdef CONFIG_PS2MULT
+ ps2mult_early_init();
+#endif /* CONFIG_PS2MULT */
+ return (0);
+}
+#endif /* CONFIG_BOARD_EARLY_INIT_R */
+
+
+int last_stage_init (void)
+{
+ /*
+ * auto scan for really existing devices and re-set chip select
+ * configuration.
+ */
+ u16 save, tmp;
+ int restore;
+
+ /*
+ * Check for SRAM and SRAM size
+ */
+
+ /* save original SRAM content */
+ save = *(volatile u16 *)CONFIG_SYS_CS2_START;
+ restore = 1;
+
+ /* write test pattern to SRAM */
+ *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
+ __asm__ volatile ("sync");
+ /*
+ * Put a different pattern on the data lines: otherwise they may float
+ * long enough to read back what we wrote.
+ */
+ tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
+ if (tmp == 0xA5A5)
+ puts ("!! possible error in SRAM detection\n");
+
+ if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
+ /* no SRAM at all, disable cs */
+ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
+ *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
+ *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
+ restore = 0;
+ __asm__ volatile ("sync");
+ } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
+ /* make sure that we access a mirrored address */
+ *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
+ __asm__ volatile ("sync");
+ if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
+ /* SRAM size = 512 kByte */
+ *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
+ 0x80000);
+ __asm__ volatile ("sync");
+ puts ("SRAM: 512 kB\n");
+ }
+ else
+ puts ("!! possible error in SRAM detection\n");
+ } else {
+ puts ("SRAM: 1 MB\n");
+ }
+ /* restore origianl SRAM content */
+ if (restore) {
+ *(volatile u16 *)CONFIG_SYS_CS2_START = save;
+ __asm__ volatile ("sync");
+ }
+
+ /*
+ * Check for Grafic Controller
+ */
+
+ /* save origianl FB content */
+ save = *(volatile u16 *)CONFIG_SYS_CS1_START;
+ restore = 1;
+
+ /* write test pattern to FB memory */
+ *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
+ __asm__ volatile ("sync");
+ /*
+ * Put a different pattern on the data lines: otherwise they may float
+ * long enough to read back what we wrote.
+ */
+ tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
+ if (tmp == 0xA5A5)
+ puts ("!! possible error in grafic controller detection\n");
+
+ if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
+ /* no grafic controller at all, disable cs */
+ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
+ *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
+ *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
+ restore = 0;
+ __asm__ volatile ("sync");
+ } else {
+ puts ("VGA: SMI501 (Voyager) with 8 MB\n");
+ }
+ /* restore origianl FB content */
+ if (restore) {
+ *(volatile u16 *)CONFIG_SYS_CS1_START = save;
+ __asm__ volatile ("sync");
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_VIDEO_SM501
+
+#define DISPLAY_WIDTH 640
+#define DISPLAY_HEIGHT 480
+
+#ifdef CONFIG_VIDEO_SM501_8BPP
+#error CONFIG_VIDEO_SM501_8BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_8BPP */
+
+#ifdef CONFIG_VIDEO_SM501_16BPP
+#error CONFIG_VIDEO_SM501_16BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_16BPP */
+
+#ifdef CONFIG_VIDEO_SM501_32BPP
+static const SMI_REGS init_regs [] =
+{
+#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
+ /* FP only */
+ {0x00004, 0x0},
+ {0x00048, 0x00021807},
+ {0x0004C, 0x091a0a01},
+ {0x00054, 0x1},
+ {0x00040, 0x00021807},
+ {0x00044, 0x091a0a01},
+ {0x00054, 0x0},
+ {0x80000, 0x01013106},
+ {0x80004, 0xc428bb17},
+ {0x80000, 0x03013106},
+ {0x8000C, 0x00000000},
+ {0x80010, 0x0a000a00},
+ {0x80014, 0x02800000},
+ {0x80018, 0x01e00000},
+ {0x8001C, 0x00000000},
+ {0x80020, 0x01e00280},
+ {0x80024, 0x02fa027f},
+ {0x80028, 0x004a028b},
+ {0x8002C, 0x020c01df},
+ {0x80030, 0x000201e9},
+ {0x80200, 0x00010200},
+ {0x80000, 0x0f013106},
+#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
+ /* CRT only */
+ {0x00004, 0x0},
+ {0x00048, 0x00021807},
+ {0x0004C, 0x10090a01},
+ {0x00054, 0x1},
+ {0x00040, 0x00021807},
+ {0x00044, 0x10090a01},
+ {0x00054, 0x0},
+ {0x80200, 0x00010000},
+ {0x80204, 0x0},
+ {0x80208, 0x0A000A00},
+ {0x8020C, 0x02fa027f},
+ {0x80210, 0x004a028b},
+ {0x80214, 0x020c01df},
+ {0x80218, 0x000201e9},
+ {0x80200, 0x00013306},
+#else /* panel + CRT */
+ {0x00004, 0x0},
+ {0x00048, 0x00021807},
+ {0x0004C, 0x091a0a01},
+ {0x00054, 0x1},
+ {0x00040, 0x00021807},
+ {0x00044, 0x091a0a01},
+ {0x00054, 0x0},
+ {0x80000, 0x0f013106},
+ {0x80004, 0xc428bb17},
+ {0x8000C, 0x00000000},
+ {0x80010, 0x0a000a00},
+ {0x80014, 0x02800000},
+ {0x80018, 0x01e00000},
+ {0x8001C, 0x00000000},
+ {0x80020, 0x01e00280},
+ {0x80024, 0x02fa027f},
+ {0x80028, 0x004a028b},
+ {0x8002C, 0x020c01df},
+ {0x80030, 0x000201e9},
+ {0x80200, 0x00010000},
+#endif
+ {0, 0}
+};
+#endif /* CONFIG_VIDEO_SM501_32BPP */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+ if (line_number == 1) {
+#if defined (CONFIG_TQM5200)
+ strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
+#else
+#error No supported board selected
+#endif /* CONFIG_TQM5200 */
+
+#if defined (CONFIG_BC3450)
+ } else if (line_number == 2) {
+ strcpy (info, " Dev: GERSYS BC3450");
+#endif /* CONFIG_BC3450 */
+ }
+ else {
+ info [0] = '\0';
+ }
+}
+#endif
+
+/*
+ * Returns SM501 register base address. First thing called in the
+ * driver. Checks if SM501 is physically present.
+ */
+unsigned int board_video_init (void)
+{
+ u16 save, tmp;
+ int restore, ret;
+
+ /*
+ * Check for Grafic Controller
+ */
+
+ /* save origianl FB content */
+ save = *(volatile u16 *)CONFIG_SYS_CS1_START;
+ restore = 1;
+
+ /* write test pattern to FB memory */
+ *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
+ __asm__ volatile ("sync");
+ /*
+ * Put a different pattern on the data lines: otherwise they may float
+ * long enough to read back what we wrote.
+ */
+ tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
+ if (tmp == 0xA5A5)
+ puts ("!! possible error in grafic controller detection\n");
+
+ if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
+ /* no grafic controller found */
+ restore = 0;
+ ret = 0;
+ } else {
+ ret = SM501_MMIO_BASE;
+ }
+
+ if (restore) {
+ *(volatile u16 *)CONFIG_SYS_CS1_START = save;
+ __asm__ volatile ("sync");
+ }
+ return ret;
+}
+
+/*
+ * Returns SM501 framebuffer address
+ */
+unsigned int board_video_get_fb (void)
+{
+ return SM501_FB_BASE;
+}
+
+/*
+ * Called after initializing the SM501 and before clearing the screen.
+ */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/*
+ * Return a pointer to the initialization sequence.
+ */
+const SMI_REGS *board_get_regs (void)
+{
+ return init_regs;
+}
+
+int board_get_width (void)
+{
+ return DISPLAY_WIDTH;
+}
+
+int board_get_height (void)
+{
+ return DISPLAY_HEIGHT;
+}
+
+#endif /* CONFIG_VIDEO_SM501 */
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c
new file mode 100644
index 0000000..3c6e798
--- /dev/null
+++ b/board/bc3450/cmd_bc3450.c
@@ -0,0 +1,805 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
+ *
+ * (C) Copyright 2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+
+/*
+ * BC3450 specific commands
+ */
+#if defined(CONFIG_CMD_BSP)
+
+/*
+ * Definitions for DS1620 chip
+ */
+#define THERM_START_CONVERT 0xee
+#define THERM_RESET 0xaf
+#define THERM_READ_CONFIG 0xac
+#define THERM_READ_TEMP 0xaa
+#define THERM_READ_TL 0xa2
+#define THERM_READ_TH 0xa1
+#define THERM_WRITE_CONFIG 0x0c
+#define THERM_WRITE_TL 0x02
+#define THERM_WRITE_TH 0x01
+
+#define CONFIG_SYS_1SHOT 1
+#define CONFIG_SYS_STANDALONE 0
+
+struct therm {
+ int hi;
+ int lo;
+};
+
+/*
+ * SM501 Register
+ */
+#define SM501_GPIO_CTRL_LOW 0x00000008UL /* gpio pins 0..31 */
+#define SM501_GPIO_CTRL_HIGH 0x0000000CUL /* gpio pins 32..63 */
+#define SM501_POWER_MODE0_GATE 0x00000040UL
+#define SM501_POWER_MODE1_GATE 0x00000048UL
+#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
+#define SM501_GPIO_DATA_LOW 0x00010000UL
+#define SM501_GPIO_DATA_HIGH 0x00010004UL
+#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL
+#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
+#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL
+#define SM501_CRT_DISPLAY_CONTROL 0x00080200UL
+
+/* SM501 CRT Display Control Bits */
+#define SM501_CDC_SEL (1 << 9)
+#define SM501_CDC_TE (1 << 8)
+#define SM501_CDC_E (1 << 2)
+
+/* SM501 Panel Display Control Bits */
+#define SM501_PDC_FPEN (1 << 27)
+#define SM501_PDC_BIAS (1 << 26)
+#define SM501_PDC_DATA (1 << 25)
+#define SM501_PDC_VDDEN (1 << 24)
+
+/* SM501 GPIO Data LOW Bits */
+#define SM501_GPIO24 0x01000000
+#define SM501_GPIO25 0x02000000
+#define SM501_GPIO26 0x04000000
+#define SM501_GPIO27 0x08000000
+#define SM501_GPIO28 0x10000000
+#define SM501_GPIO29 0x20000000
+#define SM501_GPIO30 0x40000000
+#define SM501_GPIO31 0x80000000
+
+/* SM501 GPIO Data HIGH Bits */
+#define SM501_GPIO46 0x00004000
+#define SM501_GPIO47 0x00008000
+#define SM501_GPIO48 0x00010000
+#define SM501_GPIO49 0x00020000
+#define SM501_GPIO50 0x00040000
+#define SM501_GPIO51 0x00080000
+
+/* BC3450 GPIOs @ SM501 Data LOW */
+#define DIP (SM501_GPIO24 | SM501_GPIO25 | SM501_GPIO26 | SM501_GPIO27)
+#define DS1620_DQ SM501_GPIO29 /* I/O */
+#define DS1620_CLK SM501_GPIO30 /* High active O/P */
+#define DS1620_RES SM501_GPIO31 /* Low active O/P */
+/* BC3450 GPIOs @ SM501 Data HIGH */
+#define BUZZER SM501_GPIO47 /* Low active O/P */
+#define DS1620_TLOW SM501_GPIO48 /* High active I/P */
+#define PWR_OFF SM501_GPIO49 /* Low active O/P */
+#define FP_DATA_TRI SM501_GPIO50 /* High active O/P */
+
+
+/*
+ * Initialise GPIO on SM501
+ *
+ * This function may be called from several other functions.
+ * Yet, the initialisation sequence is executed only the first
+ * time the function is called.
+ */
+int sm501_gpio_init (void)
+{
+ static int init_done = 0;
+
+ if (init_done) {
+ debug("sm501_gpio_init: nothing to be done.\n");
+ return 1;
+ }
+
+ /* enable SM501 GPIO control (in both power modes) */
+ *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE0_GATE) |=
+ POWER_MODE_GATE_GPIO_PWM_I2C;
+ *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE1_GATE) |=
+ POWER_MODE_GATE_GPIO_PWM_I2C;
+
+ /* set up default O/Ps */
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
+ ~(DS1620_RES | DS1620_CLK);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ;
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
+ ~(FP_DATA_TRI);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |=
+ (BUZZER | PWR_OFF);
+
+ /* configure directions for SM501 GPIO pins */
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_LOW) &= ~(0xFF << 24);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_HIGH) &=
+ ~(0x3F << 14);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &=
+ ~(DIP | DS1620_DQ);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |=
+ (DS1620_RES | DS1620_CLK);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) &=
+ ~DS1620_TLOW;
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) |=
+ (PWR_OFF | BUZZER | FP_DATA_TRI);
+
+ init_done = 1;
+ debug("sm501_gpio_init: done.\n");
+
+ return 0;
+}
+
+
+/*
+ * dip - read Config Inputs
+ *
+ * read and prints the dip switch
+ * and/or external config inputs (4bits) 0...0x0F
+ */
+int cmd_dip (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ vu_long rc = 0;
+
+ sm501_gpio_init ();
+
+ /* read dip switch */
+ rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
+ rc = ~rc;
+ rc &= DIP;
+ rc = (int) (rc >> 24);
+
+ /* plausibility check */
+ if (rc > 0x0F)
+ return -1;
+
+ printf ("0x%lx\n", rc);
+ return 0;
+}
+
+U_BOOT_CMD (dip, 1, 1, cmd_dip,
+ "read dip switch and config inputs",
+ "\n"
+ " - prints the state of the dip switch and/or\n"
+ " external configuration inputs as hex value.\n"
+ " - \"Config 1\" is the LSB");
+
+
+/*
+ * buz - turns Buzzer on/off
+ */
+#ifdef CONFIG_BC3450_BUZZER
+static int cmd_buz (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc != 2) {
+ printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
+ return 1;
+ }
+
+ sm501_gpio_init ();
+
+ if (strncmp (argv[1], "on", 2) == 0) {
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
+ ~(BUZZER);
+ return 0;
+ } else if (strncmp (argv[1], "off", 3) == 0) {
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |=
+ BUZZER;
+ return 0;
+ }
+ printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
+ return 1;
+}
+
+U_BOOT_CMD (buz, 2, 1, cmd_buz,
+ "turns buzzer on/off",
+ "\n" "buz <on/off>\n" " - turns the buzzer on or off");
+#endif /* CONFIG_BC3450_BUZZER */
+
+
+/*
+ * fp - front panel commands
+ */
+static int cmd_fp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ sm501_gpio_init ();
+
+ if (strncmp (argv[1], "on", 2) == 0) {
+ /* turn on VDD first */
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_VDDEN;
+ udelay (1000);
+ /* then put data on */
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_DATA;
+ /* wait some time and enable backlight */
+ udelay (1000);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS;
+ udelay (1000);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN;
+ return 0;
+ } else if (strncmp (argv[1], "off", 3) == 0) {
+ /* turn off the backlight first */
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN;
+ udelay (1000);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS;
+ udelay (200000);
+ /* wait some time, then remove data */
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_DATA;
+ udelay (1000);
+ /* and remove VDD last */
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) &=
+ ~SM501_PDC_VDDEN;
+ return 0;
+ } else if (strncmp (argv[1], "bl", 2) == 0) {
+ /* turn on/off backlight only */
+ if (strncmp (argv[2], "on", 2) == 0) {
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) |=
+ SM501_PDC_BIAS;
+ udelay (1000);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) |=
+ SM501_PDC_FPEN;
+ return 0;
+ } else if (strncmp (argv[2], "off", 3) == 0) {
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) &=
+ ~SM501_PDC_FPEN;
+ udelay (1000);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) &=
+ ~SM501_PDC_BIAS;
+ return 0;
+ }
+ }
+#ifdef CONFIG_BC3450_CRT
+ else if (strncmp (argv[1], "crt", 3) == 0) {
+ /* enables/disables the crt output (debug only) */
+ if (strncmp (argv[2], "on", 2) == 0) {
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_CRT_DISPLAY_CONTROL) |=
+ (SM501_CDC_TE | SM501_CDC_E);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_CRT_DISPLAY_CONTROL) &=
+ ~SM501_CDC_SEL;
+ return 0;
+ } else if (strncmp (argv[2], "off", 3) == 0) {
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_CRT_DISPLAY_CONTROL) &=
+ ~(SM501_CDC_TE | SM501_CDC_E);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_CRT_DISPLAY_CONTROL) |=
+ SM501_CDC_SEL;
+ return 0;
+ }
+ }
+#endif /* CONFIG_BC3450_CRT */
+ printf ("Usage:%s\n", cmdtp->help);
+ return 1;
+}
+
+U_BOOT_CMD (fp, 3, 1, cmd_fp,
+ "front panes access functions",
+ "\n"
+ "fp bl <on/off>\n"
+ " - turns the CCFL backlight of the display on/off\n"
+ "fp <on/off>\n" " - turns the whole display on/off"
+#ifdef CONFIG_BC3450_CRT
+ "\n"
+ "fp crt <on/off>\n"
+ " - enables/disables the crt output (debug only)"
+#endif /* CONFIG_BC3450_CRT */
+ );
+
+/*
+ * temp - DS1620 thermometer
+ */
+/* GERSYS BC3450 specific functions */
+static inline void bc_ds1620_set_clk (int clk)
+{
+ if (clk)
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |=
+ DS1620_CLK;
+ else
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
+ ~DS1620_CLK;
+}
+
+static inline void bc_ds1620_set_data (int dat)
+{
+ if (dat)
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |=
+ DS1620_DQ;
+ else
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
+ ~DS1620_DQ;
+}
+
+static inline int bc_ds1620_get_data (void)
+{
+ vu_long rc;
+
+ rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
+ rc &= DS1620_DQ;
+ if (rc != 0)
+ rc = 1;
+ return (int) rc;
+}
+
+static inline void bc_ds1620_set_data_dir (int dir)
+{
+ if (dir) /* in */
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~DS1620_DQ;
+ else /* out */
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= DS1620_DQ;
+}
+
+static inline void bc_ds1620_set_reset (int res)
+{
+ if (res)
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_RES;
+ else
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_RES;
+}
+
+/* hardware independent functions */
+static void ds1620_send_bits (int nr, int value)
+{
+ int i;
+
+ for (i = 0; i < nr; i++) {
+ bc_ds1620_set_data (value & 1);
+ bc_ds1620_set_clk (0);
+ udelay (1);
+ bc_ds1620_set_clk (1);
+ udelay (1);
+
+ value >>= 1;
+ }
+}
+
+static unsigned int ds1620_recv_bits (int nr)
+{
+ unsigned int value = 0, mask = 1;
+ int i;
+
+ bc_ds1620_set_data (0);
+
+ for (i = 0; i < nr; i++) {
+ bc_ds1620_set_clk (0);
+ udelay (1);
+
+ if (bc_ds1620_get_data ())
+ value |= mask;
+
+ mask <<= 1;
+
+ bc_ds1620_set_clk (1);
+ udelay (1);
+ }
+
+ return value;
+}
+
+static void ds1620_out (int cmd, int bits, int value)
+{
+ bc_ds1620_set_clk (1);
+ bc_ds1620_set_data_dir (0);
+
+ bc_ds1620_set_reset (0);
+ udelay (1);
+ bc_ds1620_set_reset (1);
+
+ udelay (1);
+
+ ds1620_send_bits (8, cmd);
+ if (bits)
+ ds1620_send_bits (bits, value);
+
+ udelay (1);
+
+ /* go stand alone */
+ bc_ds1620_set_data_dir (1);
+ bc_ds1620_set_reset (0);
+ bc_ds1620_set_clk (0);
+
+ udelay (10000);
+}
+
+static unsigned int ds1620_in (int cmd, int bits)
+{
+ unsigned int value;
+
+ bc_ds1620_set_clk (1);
+ bc_ds1620_set_data_dir (0);
+
+ bc_ds1620_set_reset (0);
+ udelay (1);
+ bc_ds1620_set_reset (1);
+
+ udelay (1);
+
+ ds1620_send_bits (8, cmd);
+
+ bc_ds1620_set_data_dir (1);
+ value = ds1620_recv_bits (bits);
+
+ /* go stand alone */
+ bc_ds1620_set_data_dir (1);
+ bc_ds1620_set_reset (0);
+ bc_ds1620_set_clk (0);
+
+ return value;
+}
+
+static int cvt_9_to_int (unsigned int val)
+{
+ if (val & 0x100)
+ val |= 0xfffffe00;
+
+ return val;
+}
+
+/* set thermostate thresholds */
+static void ds1620_write_state (struct therm *therm)
+{
+ ds1620_out (THERM_WRITE_TL, 9, therm->lo);
+ ds1620_out (THERM_WRITE_TH, 9, therm->hi);
+ ds1620_out (THERM_START_CONVERT, 0, 0);
+}
+
+static int cmd_temp (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ int i;
+ struct therm therm;
+
+ sm501_gpio_init ();
+
+ /* print temperature */
+ if (argc == 1) {
+ i = cvt_9_to_int (ds1620_in (THERM_READ_TEMP, 9));
+ printf ("%d.%d C\n", i >> 1, i & 1 ? 5 : 0);
+ return 0;
+ }
+
+ /* set to default operation */
+ if (strncmp (argv[1], "set", 3) == 0) {
+ if (strncmp (argv[2], "default", 3) == 0) {
+ therm.hi = +88;
+ therm.lo = -20;
+ therm.hi <<= 1;
+ therm.lo <<= 1;
+ ds1620_write_state (&therm);
+ ds1620_out (THERM_WRITE_CONFIG, 8, CONFIG_SYS_STANDALONE);
+ return 0;
+ }
+ }
+
+ printf ("Usage:%s\n", cmdtp->help);
+ return 1;
+}
+
+U_BOOT_CMD (temp, 3, 1, cmd_temp,
+ "print current temperature",
+ "\n" "temp\n" " - print current temperature");
+
+#ifdef CONFIG_BC3450_CAN
+/*
+ * Initialise CAN interface
+ *
+ * return 1 on CAN initialization failure
+ * return 0 if no failure
+ */
+int can_init (void)
+{
+ static int init_done = 0;
+ int i;
+ struct mpc5xxx_mscan *can1 =
+ (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
+ struct mpc5xxx_mscan *can2 =
+ (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
+
+ /* GPIO configuration of the CAN pins is done in BC3450.h */
+
+ if (!init_done) {
+ /* init CAN 1 */
+ can1->canctl1 |= 0x80; /* CAN enable */
+ udelay (100);
+
+ i = 0;
+ can1->canctl0 |= 0x02; /* sleep mode */
+ /* wait until sleep mode reached */
+ while (!(can1->canctl1 & 0x02)) {
+ udelay (10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 initialize error, "
+ "can not enter sleep mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ i = 0;
+ can1->canctl0 = 0x01; /* enter init mode */
+ /* wait until init mode reached */
+ while (!(can1->canctl1 & 0x01)) {
+ udelay (10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 initialize error, "
+ "can not enter init mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ can1->canctl1 = 0x80;
+ can1->canctl1 |= 0x40;
+ can1->canbtr0 = 0x0F;
+ can1->canbtr1 = 0x7F;
+ can1->canidac &= ~(0x30);
+ can1->canidar1 = 0x00;
+ can1->canidar3 = 0x00;
+ can1->canidar5 = 0x00;
+ can1->canidar7 = 0x00;
+ can1->canidmr0 = 0xFF;
+ can1->canidmr1 = 0xFF;
+ can1->canidmr2 = 0xFF;
+ can1->canidmr3 = 0xFF;
+ can1->canidmr4 = 0xFF;
+ can1->canidmr5 = 0xFF;
+ can1->canidmr6 = 0xFF;
+ can1->canidmr7 = 0xFF;
+
+ i = 0;
+ can1->canctl0 &= ~(0x01); /* leave init mode */
+ can1->canctl0 &= ~(0x02);
+ /* wait until init and sleep mode left */
+ while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
+ udelay (10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 initialize error, "
+ "can not leave init/sleep mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+
+ /* init CAN 2 */
+ can2->canctl1 |= 0x80; /* CAN enable */
+ udelay (100);
+
+ i = 0;
+ can2->canctl0 |= 0x02; /* sleep mode */
+ /* wait until sleep mode reached */
+ while (!(can2->canctl1 & 0x02)) {
+ udelay (10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 initialize error, "
+ "can not enter sleep mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ i = 0;
+ can2->canctl0 = 0x01; /* enter init mode */
+ /* wait until init mode reached */
+ while (!(can2->canctl1 & 0x01)) {
+ udelay (10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 initialize error, "
+ "can not enter init mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ can2->canctl1 = 0x80;
+ can2->canctl1 |= 0x40;
+ can2->canbtr0 = 0x0F;
+ can2->canbtr1 = 0x7F;
+ can2->canidac &= ~(0x30);
+ can2->canidar1 = 0x00;
+ can2->canidar3 = 0x00;
+ can2->canidar5 = 0x00;
+ can2->canidar7 = 0x00;
+ can2->canidmr0 = 0xFF;
+ can2->canidmr1 = 0xFF;
+ can2->canidmr2 = 0xFF;
+ can2->canidmr3 = 0xFF;
+ can2->canidmr4 = 0xFF;
+ can2->canidmr5 = 0xFF;
+ can2->canidmr6 = 0xFF;
+ can2->canidmr7 = 0xFF;
+ can2->canctl0 &= ~(0x01); /* leave init mode */
+ can2->canctl0 &= ~(0x02);
+
+ i = 0;
+ /* wait until init mode left */
+ while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
+ udelay (10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 initialize error, "
+ "can not leave init/sleep mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ init_done = 1;
+ }
+ return 0;
+}
+
+/*
+ * Do CAN test
+ * by sending message between CAN1 and CAN2
+ *
+ * return 1 on CAN failure
+ * return 0 if no failure
+ */
+int do_can (char * const argv[])
+{
+ int i;
+ struct mpc5xxx_mscan *can1 =
+ (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
+ struct mpc5xxx_mscan *can2 =
+ (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
+
+ /* send a message on CAN1 */
+ can1->cantbsel = 0x01;
+ can1->cantxfg.idr[0] = 0x55;
+ can1->cantxfg.idr[1] = 0x00;
+ can1->cantxfg.idr[1] &= ~0x8;
+ can1->cantxfg.idr[1] &= ~0x10;
+ can1->cantxfg.dsr[0] = 0xCC;
+ can1->cantxfg.dlr = 1;
+ can1->cantxfg.tbpr = 0;
+ can1->cantflg = 0x01;
+
+ i = 0;
+ while ((can1->cantflg & 0x01) == 0) {
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 send timeout, "
+ "can not send message!\n", __FUNCTION__);
+ return 1;
+ }
+ udelay (1000);
+ }
+ udelay (1000);
+
+ i = 0;
+ while (!(can2->canrflg & 0x01)) {
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 receive timeout, "
+ "no message received!\n", __FUNCTION__);
+ return 1;
+ }
+ udelay (1000);
+ }
+
+ if (can2->canrxfg.dsr[0] != 0xCC) {
+ printf ("%s: CAN2 receive error, "
+ "data mismatch!\n", __FUNCTION__);
+ return 1;
+ }
+
+ /* send a message on CAN2 */
+ can2->cantbsel = 0x01;
+ can2->cantxfg.idr[0] = 0x55;
+ can2->cantxfg.idr[1] = 0x00;
+ can2->cantxfg.idr[1] &= ~0x8;
+ can2->cantxfg.idr[1] &= ~0x10;
+ can2->cantxfg.dsr[0] = 0xCC;
+ can2->cantxfg.dlr = 1;
+ can2->cantxfg.tbpr = 0;
+ can2->cantflg = 0x01;
+
+ i = 0;
+ while ((can2->cantflg & 0x01) == 0) {
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 send error, "
+ "can not send message!\n", __FUNCTION__);
+ return 1;
+ }
+ udelay (1000);
+ }
+ udelay (1000);
+
+ i = 0;
+ while (!(can1->canrflg & 0x01)) {
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 receive timeout, "
+ "no message received!\n", __FUNCTION__);
+ return 1;
+ }
+ udelay (1000);
+ }
+
+ if (can1->canrxfg.dsr[0] != 0xCC) {
+ printf ("%s: CAN1 receive error 0x%02x\n",
+ __FUNCTION__, (can1->canrxfg.dsr[0]));
+ return 1;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_BC3450_CAN */
+
+/*
+ * test - BC3450 HW test routines
+ */
+int cmd_test (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_BC3450_CAN
+ int rcode;
+
+ can_init ();
+#endif /* CONFIG_BC3450_CAN */
+
+ sm501_gpio_init ();
+
+ if (argc != 2) {
+ printf ("Usage:%s\n", cmdtp->help);
+ return 1;
+ }
+
+ if (strncmp (argv[1], "unit-off", 8) == 0) {
+ printf ("waiting 2 seconds...\n");
+ udelay (2000000);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
+ ~PWR_OFF;
+ return 0;
+ }
+#ifdef CONFIG_BC3450_CAN
+ else if (strncmp (argv[1], "can", 2) == 0) {
+ rcode = do_can (argv);
+ if (simple_strtoul (argv[2], NULL, 10) == 2) {
+ if (rcode == 0)
+ printf ("OK\n");
+ else
+ printf ("Error\n");
+ }
+ return rcode;
+ }
+#endif /* CONFIG_BC3450_CAN */
+
+ printf ("Usage:%s\n", cmdtp->help);
+ return 1;
+}
+
+U_BOOT_CMD (test, 2, 1, cmd_test, "unit test routines", "\n"
+#ifdef CONFIG_BC3450_CAN
+ "test can\n"
+ " - connect CAN1 (X8) with CAN2 (X9) for this test\n"
+#endif /* CONFIG_BC3450_CAN */
+ "test unit-off\n"
+ " - turns off the BC3450 unit\n"
+ " WARNING: Unsaved environment variables will be lost!"
+);
+#endif
diff --git a/board/bc3450/mt48lc16m16a2-75.h b/board/bc3450/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..3d99796
--- /dev/null
+++ b/board/bc3450/mt48lc16m16a2-75.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 0 /* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x00CD0000
+/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */
+/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
+#define SDRAM_CONFIG2 0x8AD70000
+/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */
diff --git a/board/bct-brettl2/Kconfig b/board/bct-brettl2/Kconfig
new file mode 100644
index 0000000..9c5407e
--- /dev/null
+++ b/board/bct-brettl2/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BCT_BRETTL2
+
+config SYS_BOARD
+ default "bct-brettl2"
+
+config SYS_CONFIG_NAME
+ default "bct-brettl2"
+
+endif
diff --git a/board/bct-brettl2/MAINTAINERS b/board/bct-brettl2/MAINTAINERS
new file mode 100644
index 0000000..32245d4
--- /dev/null
+++ b/board/bct-brettl2/MAINTAINERS
@@ -0,0 +1,6 @@
+BCT-BRETTL2 BOARD
+M: Peter Meerwald <devel@bct-electronic.com>
+S: Maintained
+F: board/bct-brettl2/
+F: include/configs/bct-brettl2.h
+F: configs/bct-brettl2_defconfig
diff --git a/board/bct-brettl2/Makefile b/board/bct-brettl2/Makefile
new file mode 100644
index 0000000..12154b6
--- /dev/null
+++ b/board/bct-brettl2/Makefile
@@ -0,0 +1,13 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bct-brettl2.o gpio_cfi_flash.o cled.o
+obj-$(CONFIG_BFIN_MAC) += smsc9303.o
diff --git a/board/bct-brettl2/bct-brettl2.c b/board/bct-brettl2/bct-brettl2.c
new file mode 100644
index 0000000..6be9b18
--- /dev/null
+++ b/board/bct-brettl2/bct-brettl2.c
@@ -0,0 +1,122 @@
+/*
+ * U-boot - main board file for BCT brettl2
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/portmux.h>
+#include <asm/gpio.h>
+#include <net.h>
+#include <netdev.h>
+#include <miiphy.h>
+
+#include "../cm-bf537e/gpio_cfi_flash.h"
+#include "smsc9303.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: bct-brettl2 board\n");
+ printf(" Support: http://www.bct-electronic.com/\n");
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+ puts("Warning: Generating 'random' MAC address\n");
+ eth_random_addr(mac_addr);
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int retry = 3;
+ int ret;
+
+ ret = bfin_EMAC_initialize(bis);
+
+ uchar enetaddr[6];
+ if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ printf("setting MAC %pM\n", enetaddr);
+ }
+ puts(" ");
+
+ puts("initialize SMSC LAN9303i ethernet switch\n");
+
+ while (retry-- > 0) {
+ if (init_smsc9303i_mii())
+ return ret;
+ }
+
+ return ret;
+}
+#endif
+
+static void init_tlv320aic31(void)
+{
+ puts("Audio: setup TIMER0 to enable 16.384 MHz clock for tlv320aic31\n");
+ peripheral_request(P_TMR0, "tlv320aic31 clock");
+ bfin_write_TIMER0_CONFIG(0x020d);
+ bfin_write_TIMER0_PERIOD(0x0008);
+ bfin_write_TIMER0_WIDTH(0x0008/2);
+ bfin_write_TIMER_ENABLE(bfin_read_TIMER_ENABLE() | 1);
+ SSYNC();
+ udelay(10000);
+
+ puts(" resetting tlv320aic31\n");
+
+ gpio_request(GPIO_PF2, "tlv320aic31");
+ gpio_direction_output(GPIO_PF2, 0);
+ udelay(10000);
+ gpio_direction_output(GPIO_PF2, 1);
+ udelay(10000);
+ gpio_free(GPIO_PF2);
+}
+
+static void init_mute_pin(void)
+{
+ printf(" unmute class D amplifier\n");
+
+ gpio_request(GPIO_PF5, "mute");
+ gpio_direction_output(GPIO_PF5, 1);
+ gpio_free(GPIO_PF5);
+}
+
+/* sometimes LEDs (speech, status) are still on after reboot, turn 'em off */
+static void turn_leds_off(void)
+{
+ printf(" turn LEDs off\n");
+
+ gpio_request(GPIO_PF6, "led");
+ gpio_direction_output(GPIO_PF6, 0);
+ gpio_free(GPIO_PF6);
+
+ gpio_request(GPIO_PF15, "led");
+ gpio_direction_output(GPIO_PF15, 0);
+ gpio_free(GPIO_PF15);
+}
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+ gpio_cfi_flash_init();
+ init_tlv320aic31();
+ init_mute_pin();
+ turn_leds_off();
+
+ return 0;
+}
diff --git a/board/bct-brettl2/cled.c b/board/bct-brettl2/cled.c
new file mode 100644
index 0000000..dcb91bd
--- /dev/null
+++ b/board/bct-brettl2/cled.c
@@ -0,0 +1,32 @@
+/*
+ * cled.c - control color led
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+
+int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong addr = 0x20000000 + 0x200000; /* AMS2 */
+ uchar data;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ data = simple_strtoul(argv[1], NULL, 10);
+ outb(data, addr);
+
+ printf("cled, write %02x\n", data);
+
+ return 0;
+}
+
+U_BOOT_CMD(cled, 2, 0, do_cled,
+ "set/clear color LED",
+ "");
diff --git a/board/bct-brettl2/gpio_cfi_flash.c b/board/bct-brettl2/gpio_cfi_flash.c
new file mode 100644
index 0000000..b385c7f
--- /dev/null
+++ b/board/bct-brettl2/gpio_cfi_flash.c
@@ -0,0 +1,4 @@
+#define GPIO_PIN_1 GPIO_PG5
+#define GPIO_PIN_2 GPIO_PG6
+#define GPIO_PIN_3 GPIO_PG7
+#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/bct-brettl2/smsc9303.c b/board/bct-brettl2/smsc9303.c
new file mode 100644
index 0000000..15eea7a
--- /dev/null
+++ b/board/bct-brettl2/smsc9303.c
@@ -0,0 +1,176 @@
+/*
+ * smsc9303.c - routines to initialize SMSC 9303 switch
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <miiphy.h>
+
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+
+static int smc9303i_write_mii(unsigned char addr, unsigned char reg, unsigned short data)
+{
+ const char *devname = miiphy_get_current_dev();
+
+ if (!devname)
+ return 0;
+
+ if (miiphy_write(devname, addr, reg, data) != 0)
+ return 0;
+
+ return 1;
+}
+
+static int smc9303i_write_reg(unsigned short reg, unsigned int data)
+{
+ const char *devname = miiphy_get_current_dev();
+ unsigned char mii_addr = 0x10 | (reg >> 6);
+ unsigned char mii_reg = (reg & 0x3c) >> 1;
+
+ if (!devname)
+ return 0;
+
+ if (miiphy_write(devname, mii_addr, mii_reg|0, data & 0xffff) != 0)
+ return 0;
+
+ if (miiphy_write(devname, mii_addr, mii_reg|1, data >> 16) != 0)
+ return 0;
+
+ return 1;
+}
+
+static int smc9303i_read_reg(unsigned short reg, unsigned int *data)
+{
+ const char *devname = miiphy_get_current_dev();
+ unsigned char mii_addr = 0x10 | (reg >> 6);
+ unsigned char mii_reg = (reg & 0x3c) >> 1;
+ unsigned short tmp1, tmp2;
+
+ if (!devname)
+ return 0;
+
+ if (miiphy_read(devname, mii_addr, mii_reg|0, &tmp1) != 0)
+ return 0;
+
+ if (miiphy_read(devname, mii_addr, mii_reg|1, &tmp2) != 0)
+ return 0;
+
+ *data = (tmp2 << 16) | tmp1;
+
+ return 1;
+}
+
+#if 0
+static int smc9303i_read_mii(unsigned char addr, unsigned char reg, unsigned short *data)
+{
+ const char *devname = miiphy_get_current_dev();
+
+ if (!devname)
+ return 0;
+
+ if (miiphy_read(devname, addr, reg, data) != 0)
+ return 0;
+
+ return 1;
+}
+#endif
+
+typedef struct {
+ unsigned short reg;
+ unsigned int value;
+} smsc9303i_config_entry1_t;
+
+static const smsc9303i_config_entry1_t smsc9303i_config_table1[] =
+{
+ {0x1a0, 0x00000006}, /* Port 1 Manual Flow Control Register */
+ {0x1a4, 0x00000006}, /* Port 2 Manual Flow Control Register */
+ {0x1a8, 0x00000006}, /* Port 0 Manual Flow Control Register */
+};
+
+typedef struct
+{
+ unsigned char addr;
+ unsigned char reg;
+ unsigned short value;
+} smsc9303i_config_entry2_t;
+
+static const smsc9303i_config_entry2_t smsc9303i_config_table2[] =
+{
+ {0x01, 0x00, 0x0100}, /* Port0 PHY Basic Control Register */
+ {0x02, 0x00, 0x1100}, /* Port1 PHY Basic Control Register */
+ {0x03, 0x00, 0x1100}, /* Port2 PHY Basic Control Register */
+
+ {0x01, 0x04, 0x0001}, /* Port0 PHY Auto-Negotiation Advertisement Register */
+ {0x02, 0x04, 0x2de1}, /* Port1 PHY Auto-Negotiation Advertisement Register */
+ {0x03, 0x04, 0x2de1}, /* Port2 PHY Auto-Negotiation Advertisement Register */
+
+ {0x01, 0x11, 0x0000}, /* Port0 PHY Mode Control/Status Register */
+ {0x02, 0x11, 0x0000}, /* Port1 PHY Mode Control/Status Register */
+ {0x03, 0x11, 0x0000}, /* Port2 PHY Mode Control/Status Register */
+
+ {0x01, 0x12, 0x0021}, /* Port0 PHY Special Modes Register */
+ {0x02, 0x12, 0x00e2}, /* Port1 PHY Special Modes Register */
+ {0x03, 0x12, 0x00e3}, /* Port2 PHY Special Modes Register */
+ {0x01, 0x1b, 0x0000}, /* Port0 PHY Special Control/Status Indication Register */
+ {0x02, 0x1b, 0x0000}, /* Port1 PHY Special Control/Status Indication Register */
+ {0x03, 0x1b, 0x0000}, /* Port2 PHY Special Control/Status Indication Register */
+ {0x01, 0x1e, 0x0000}, /* Port0 PHY Interrupt Source Flags Register */
+ {0x02, 0x1e, 0x0000}, /* Port1 PHY Interrupt Source Flags Register */
+ {0x03, 0x1e, 0x0000}, /* Port2 PHY Interrupt Source Flags Register */
+};
+
+int init_smsc9303i_mii(void)
+{
+ unsigned int data;
+ unsigned int i;
+
+ printf(" reset SMSC LAN9303i\n");
+
+ gpio_request(GPIO_PG10, "smsc9303");
+ gpio_direction_output(GPIO_PG10, 0);
+ udelay(10000);
+ gpio_direction_output(GPIO_PG10, 1);
+ udelay(10000);
+
+ gpio_free(GPIO_PG10);
+
+#if defined(CONFIG_MII_INIT)
+ mii_init();
+#endif
+
+ printf(" write SMSC LAN9303i configuration\n");
+
+ if (!smc9303i_read_reg(0x50, &data))
+ return 0;
+
+ if ((data >> 16) != 0x9303) {
+ /* chip id not found */
+ printf(" error identifying SMSC LAN9303i\n");
+ return 0;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table1); i++) {
+ const smsc9303i_config_entry1_t *entry = &smsc9303i_config_table1[i];
+
+ if (!smc9303i_write_reg(entry->reg, entry->value)) {
+ printf(" error writing SMSC LAN9303i configuration\n");
+ return 0;
+ }
+ }
+
+ for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table2); i++) {
+ const smsc9303i_config_entry2_t *entry = &smsc9303i_config_table2[i];
+
+ if (!smc9303i_write_mii(entry->addr, entry->reg, entry->value)) {
+ printf(" error writing SMSC LAN9303i configuration\n");
+ return 0;
+ }
+ }
+
+ return 1;
+}
diff --git a/board/bct-brettl2/smsc9303.h b/board/bct-brettl2/smsc9303.h
new file mode 100644
index 0000000..a4ba40e
--- /dev/null
+++ b/board/bct-brettl2/smsc9303.h
@@ -0,0 +1,9 @@
+/*
+ * smsc9303.h - routines to initialize SMSC 9303 switch
+ *
+ * Copyright (c) 2010 BCT Electronic GmbH
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+int init_smsc9303i_mii(void);
diff --git a/board/bf506f-ezkit/Kconfig b/board/bf506f-ezkit/Kconfig
new file mode 100644
index 0000000..e6fc12c
--- /dev/null
+++ b/board/bf506f-ezkit/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF506F_EZKIT
+
+config SYS_BOARD
+ default "bf506f-ezkit"
+
+config SYS_CONFIG_NAME
+ default "bf506f-ezkit"
+
+endif
diff --git a/board/bf506f-ezkit/MAINTAINERS b/board/bf506f-ezkit/MAINTAINERS
new file mode 100644
index 0000000..aaf1b7e
--- /dev/null
+++ b/board/bf506f-ezkit/MAINTAINERS
@@ -0,0 +1,6 @@
+BF506F-EZKIT BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf506f-ezkit/
+F: include/configs/bf506f-ezkit.h
+F: configs/bf506f-ezkit_defconfig
diff --git a/board/bf506f-ezkit/Makefile b/board/bf506f-ezkit/Makefile
new file mode 100644
index 0000000..0f134f9
--- /dev/null
+++ b/board/bf506f-ezkit/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf506f-ezkit.o
diff --git a/board/bf506f-ezkit/bf506f-ezkit.c b/board/bf506f-ezkit/bf506f-ezkit.c
new file mode 100644
index 0000000..638500d
--- /dev/null
+++ b/board/bf506f-ezkit/bf506f-ezkit.c
@@ -0,0 +1,27 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+
+int checkboard(void)
+{
+ printf("Board: ADI BF506F EZ-Kit board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ bfin_write_EBIU_MODE(1);
+ SSYNC();
+ bfin_write_FLASH_CONTROL_CLEAR(1);
+ udelay(1);
+ bfin_write_FLASH_CONTROL_SET(1);
+ return 0;
+}
diff --git a/board/bf518f-ezbrd/Kconfig b/board/bf518f-ezbrd/Kconfig
new file mode 100644
index 0000000..a0e80a8
--- /dev/null
+++ b/board/bf518f-ezbrd/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF518F_EZBRD
+
+config SYS_BOARD
+ default "bf518f-ezbrd"
+
+config SYS_CONFIG_NAME
+ default "bf518f-ezbrd"
+
+endif
diff --git a/board/bf518f-ezbrd/MAINTAINERS b/board/bf518f-ezbrd/MAINTAINERS
new file mode 100644
index 0000000..6727ae4
--- /dev/null
+++ b/board/bf518f-ezbrd/MAINTAINERS
@@ -0,0 +1,6 @@
+BF518F-EZBRD BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf518f-ezbrd/
+F: include/configs/bf518f-ezbrd.h
+F: configs/bf518f-ezbrd_defconfig
diff --git a/board/bf518f-ezbrd/Makefile b/board/bf518f-ezbrd/Makefile
new file mode 100644
index 0000000..3a6abaa
--- /dev/null
+++ b/board/bf518f-ezbrd/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf518f-ezbrd.o
diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c
new file mode 100644
index 0000000..3a94a57
--- /dev/null
+++ b/board/bf518f-ezbrd/bf518f-ezbrd.c
@@ -0,0 +1,176 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <asm/blackfin.h>
+#include <asm/portmux.h>
+#include <asm/mach-common/bits/otp.h>
+#include <asm/sdh.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF518F EZ-Board board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+static void board_init_enetaddr(uchar *mac_addr)
+{
+#ifdef CONFIG_SYS_NO_FLASH
+# define USE_MAC_IN_FLASH 0
+#else
+# define USE_MAC_IN_FLASH 1
+#endif
+ bool valid_mac = false;
+
+ if (USE_MAC_IN_FLASH) {
+ /* we cram the MAC in the last flash sector */
+ uchar *board_mac_addr = (uchar *)0x203F0096;
+ if (is_valid_ether_addr(board_mac_addr)) {
+ memcpy(mac_addr, board_mac_addr, 6);
+ valid_mac = true;
+ }
+ }
+
+ if (!valid_mac) {
+ puts("Warning: Generating 'random' MAC address\n");
+ eth_random_addr(mac_addr);
+ }
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+/* Only the first run of boards had a KSZ switch */
+#if defined(CONFIG_BFIN_SPI) && __SILICON_REVISION__ == 0
+# define KSZ_POSSIBLE 1
+#else
+# define KSZ_POSSIBLE 0
+#endif
+
+#define KSZ_MAX_HZ 5000000
+
+#define KSZ_WRITE 0x02
+#define KSZ_READ 0x03
+
+#define KSZ_REG_CHID 0x00 /* Register 0: Chip ID0 */
+#define KSZ_REG_STPID 0x01 /* Register 1: Chip ID1 / Start Switch */
+#define KSZ_REG_GC9 0x0b /* Register 11: Global Control 9 */
+#define KSZ_REG_P3C0 0x30 /* Register 48: Port 3 Control 0 */
+
+static int ksz8893m_transfer(struct spi_slave *slave, uchar dir, uchar reg,
+ uchar data, uchar result[3])
+{
+ unsigned char dout[3] = { dir, reg, data, };
+ return spi_xfer(slave, sizeof(dout) * 8, dout, result, SPI_XFER_BEGIN | SPI_XFER_END);
+}
+
+static int ksz8893m_reg_set(struct spi_slave *slave, uchar reg, uchar data)
+{
+ unsigned char din[3];
+ return ksz8893m_transfer(slave, KSZ_WRITE, reg, data, din);
+}
+
+static int ksz8893m_reg_read(struct spi_slave *slave, uchar reg)
+{
+ int ret;
+ unsigned char din[3];
+ ret = ksz8893m_transfer(slave, KSZ_READ, reg, 0, din);
+ return ret ? ret : din[2];
+}
+
+static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask)
+{
+ return ksz8893m_reg_set(slave, reg, ksz8893m_reg_read(slave, reg) & mask);
+}
+
+static int ksz8893m_reset(struct spi_slave *slave)
+{
+ int ret = 0;
+
+ /* Disable STPID mode */
+ ret |= ksz8893m_reg_clear(slave, KSZ_REG_GC9, 0x01);
+
+ /* Disable VLAN tag insert on Port3 */
+ ret |= ksz8893m_reg_clear(slave, KSZ_REG_P3C0, 0x04);
+
+ /* Start switch */
+ ret |= ksz8893m_reg_set(slave, KSZ_REG_STPID, 0x01);
+
+ return ret;
+}
+
+static bool board_ksz_init(void)
+{
+ static bool switch_is_alive = false;
+
+ if (!switch_is_alive) {
+ struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3);
+ if (slave) {
+ if (!spi_claim_bus(slave)) {
+ bool phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88);
+ int ret = phy_is_ksz ? ksz8893m_reset(slave) : 0;
+ switch_is_alive = (ret == 0);
+ spi_release_bus(slave);
+ }
+ spi_free_slave(slave);
+ }
+ }
+
+ return switch_is_alive;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ if (KSZ_POSSIBLE) {
+ if (!board_ksz_init())
+ return 0;
+ }
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+ /* we use the last sector for the MAC address / POST LDR */
+ extern flash_info_t flash_info[];
+ flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
+#endif
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /* connect async banks by default */
+ const unsigned short pins[] = {
+ P_AMS2, P_AMS3, 0,
+ };
+ return peripheral_request_list(pins, "async");
+}
+
+#ifdef CONFIG_BFIN_SDH
+int board_mmc_init(bd_t *bis)
+{
+ return bfin_mmc_init(bis);
+}
+#endif
diff --git a/board/bf525-ucr2/Kconfig b/board/bf525-ucr2/Kconfig
new file mode 100644
index 0000000..cd52daa
--- /dev/null
+++ b/board/bf525-ucr2/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF525_UCR2
+
+config SYS_BOARD
+ default "bf525-ucr2"
+
+config SYS_CONFIG_NAME
+ default "bf525-ucr2"
+
+endif
diff --git a/board/bf525-ucr2/MAINTAINERS b/board/bf525-ucr2/MAINTAINERS
new file mode 100644
index 0000000..f2e9575
--- /dev/null
+++ b/board/bf525-ucr2/MAINTAINERS
@@ -0,0 +1,7 @@
+BF525-UCR2 BOARD
+M: Haitao Zhang <hzhang@ucrobotics.com>
+M: Chong Huang <chuang@ucrobotics.com>
+S: Maintained
+F: board/bf525-ucr2/
+F: include/configs/bf525-ucr2.h
+F: configs/bf525-ucr2_defconfig
diff --git a/board/bf525-ucr2/Makefile b/board/bf525-ucr2/Makefile
new file mode 100644
index 0000000..8de71a1
--- /dev/null
+++ b/board/bf525-ucr2/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf525-ucr2.o
diff --git a/board/bf525-ucr2/bf525-ucr2.c b/board/bf525-ucr2/bf525-ucr2.c
new file mode 100644
index 0000000..3e6df1f
--- /dev/null
+++ b/board/bf525-ucr2/bf525-ucr2.c
@@ -0,0 +1,16 @@
+/* U-boot - bf525-ucr2.c board specific routines
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+
+int checkboard(void)
+{
+ printf("Board: bf525-ucr2\n");
+ printf("Support: http://www.ucrobotics.com/\n");
+ return 0;
+}
diff --git a/board/bf526-ezbrd/Kconfig b/board/bf526-ezbrd/Kconfig
new file mode 100644
index 0000000..e138ea5
--- /dev/null
+++ b/board/bf526-ezbrd/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF526_EZBRD
+
+config SYS_BOARD
+ default "bf526-ezbrd"
+
+config SYS_CONFIG_NAME
+ default "bf526-ezbrd"
+
+endif
diff --git a/board/bf526-ezbrd/MAINTAINERS b/board/bf526-ezbrd/MAINTAINERS
new file mode 100644
index 0000000..f7c2d18
--- /dev/null
+++ b/board/bf526-ezbrd/MAINTAINERS
@@ -0,0 +1,6 @@
+BF526-EZBRD BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf526-ezbrd/
+F: include/configs/bf526-ezbrd.h
+F: configs/bf526-ezbrd_defconfig
diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile
new file mode 100644
index 0000000..34ac563
--- /dev/null
+++ b/board/bf526-ezbrd/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf526-ezbrd.o
diff --git a/board/bf526-ezbrd/bf526-ezbrd.c b/board/bf526-ezbrd/bf526-ezbrd.c
new file mode 100644
index 0000000..368d6be
--- /dev/null
+++ b/board/bf526-ezbrd/bf526-ezbrd.c
@@ -0,0 +1,74 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/otp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF526 EZ-Board board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+#ifdef CONFIG_SYS_NO_FLASH
+# define USE_MAC_IN_FLASH 0
+#else
+# define USE_MAC_IN_FLASH 1
+#endif
+ bool valid_mac = false;
+
+ if (USE_MAC_IN_FLASH) {
+ /* we cram the MAC in the last flash sector */
+ uchar *board_mac_addr = (uchar *)0x203F0096;
+ if (is_valid_ether_addr(board_mac_addr)) {
+ memcpy(mac_addr, board_mac_addr, 6);
+ valid_mac = true;
+ }
+ }
+
+ if (!valid_mac) {
+ puts("Warning: Generating 'random' MAC address\n");
+ eth_random_addr(mac_addr);
+ }
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+ /* we use the last sector for the MAC address / POST LDR */
+ extern flash_info_t flash_info[];
+ flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
+#endif
+
+ return 0;
+}
diff --git a/board/bf527-ad7160-eval/Kconfig b/board/bf527-ad7160-eval/Kconfig
new file mode 100644
index 0000000..fe56241
--- /dev/null
+++ b/board/bf527-ad7160-eval/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF527_AD7160_EVAL
+
+config SYS_BOARD
+ default "bf527-ad7160-eval"
+
+config SYS_CONFIG_NAME
+ default "bf527-ad7160-eval"
+
+endif
diff --git a/board/bf527-ad7160-eval/MAINTAINERS b/board/bf527-ad7160-eval/MAINTAINERS
new file mode 100644
index 0000000..e93de1a
--- /dev/null
+++ b/board/bf527-ad7160-eval/MAINTAINERS
@@ -0,0 +1,6 @@
+BF527-AD7160-EVAL BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf527-ad7160-eval/
+F: include/configs/bf527-ad7160-eval.h
+F: configs/bf527-ad7160-eval_defconfig
diff --git a/board/bf527-ad7160-eval/Makefile b/board/bf527-ad7160-eval/Makefile
new file mode 100644
index 0000000..9d8ecf1
--- /dev/null
+++ b/board/bf527-ad7160-eval/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf527-ad7160-eval.o
diff --git a/board/bf527-ad7160-eval/bf527-ad7160-eval.c b/board/bf527-ad7160-eval/bf527-ad7160-eval.c
new file mode 100644
index 0000000..ea405b6
--- /dev/null
+++ b/board/bf527-ad7160-eval/bf527-ad7160-eval.c
@@ -0,0 +1,25 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/pll.h>
+
+int checkboard(void)
+{
+ printf("Board: ADI BF527 AD7160-EVAL board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ /* CLKIN Buffer Output Enable */
+ bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
+ return 0;
+}
diff --git a/board/bf527-ezkit/Kconfig b/board/bf527-ezkit/Kconfig
new file mode 100644
index 0000000..df49d7a
--- /dev/null
+++ b/board/bf527-ezkit/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF527_EZKIT
+
+config SYS_BOARD
+ default "bf527-ezkit"
+
+config SYS_CONFIG_NAME
+ default "bf527-ezkit"
+
+endif
diff --git a/board/bf527-ezkit/MAINTAINERS b/board/bf527-ezkit/MAINTAINERS
new file mode 100644
index 0000000..7a95396
--- /dev/null
+++ b/board/bf527-ezkit/MAINTAINERS
@@ -0,0 +1,7 @@
+BF527-EZKIT BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf527-ezkit/
+F: include/configs/bf527-ezkit.h
+F: configs/bf527-ezkit_defconfig
+F: configs/bf527-ezkit-v2_defconfig
diff --git a/board/bf527-ezkit/Makefile b/board/bf527-ezkit/Makefile
new file mode 100644
index 0000000..cedd821
--- /dev/null
+++ b/board/bf527-ezkit/Makefile
@@ -0,0 +1,13 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf527-ezkit.o
+obj-$(CONFIG_VIDEO) += video.o
diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c
new file mode 100644
index 0000000..88e1869
--- /dev/null
+++ b/board/bf527-ezkit/bf527-ezkit.c
@@ -0,0 +1,81 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/mach-common/bits/otp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF527 EZ-Kit board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+ bool valid_mac = false;
+
+ /* the MAC is stored in OTP memory page 0xDF */
+ uint32_t ret;
+ uint64_t otp_mac;
+
+ ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
+ if (!(ret & OTP_MASTER_ERROR)) {
+ uchar *otp_mac_p = (uchar *)&otp_mac;
+
+ for (ret = 0; ret < 6; ++ret)
+ mac_addr[ret] = otp_mac_p[5 - ret];
+
+ if (is_valid_ether_addr(mac_addr))
+ valid_mac = true;
+ }
+
+ if (!valid_mac) {
+ puts("Warning: Generating 'random' MAC address\n");
+ eth_random_addr(mac_addr);
+ }
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_BLACKFIN
+void board_musb_init(void)
+{
+ /*
+ * BF527 EZ-KITs require PG13 to be high for HOST mode
+ */
+ gpio_request(GPIO_PG13, "musb-vbus");
+ gpio_direction_output(GPIO_PG13, 1);
+}
+#endif
diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c
new file mode 100644
index 0000000..c2bf145
--- /dev/null
+++ b/board/bf527-ezkit/video.c
@@ -0,0 +1,447 @@
+/*
+ * video.c - run splash screen on lcd
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/blackfin.h>
+#include <asm/portmux.h>
+#include <asm/mach-common/bits/dma.h>
+#include <spi.h>
+#include <linux/types.h>
+#include <stdio_dev.h>
+
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
+
+#include <asm/mach-common/bits/ppi.h>
+#include <asm/mach-common/bits/timer.h>
+
+#define LCD_X_RES 320 /* Horizontal Resolution */
+#define LCD_Y_RES 240 /* Vertical Resolution */
+#define DMA_BUS_SIZE 16
+
+#include EASYLOGO_HEADER
+
+#ifdef CONFIG_BF527_EZKIT_REV_2_1 /* lq035q1 */
+
+/* Interface 16/18-bit TFT over an 8-bit wide PPI using a
+ * small Programmable Logic Device (CPLD)
+ * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
+ */
+
+#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
+#define LCD_BPP 16 /* Bit Per Pixel */
+#define CLOCKS_PPIX 2 /* Clocks per pixel */
+#define CPLD_DELAY 3 /* RGB565 pipeline delay */
+#endif
+
+#ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
+#define LCD_BPP 24 /* Bit Per Pixel */
+#define CLOCKS_PPIX 3 /* Clocks per pixel */
+#define CPLD_DELAY 5 /* RGB888 pipeline delay */
+#endif
+
+/*
+ * HS and VS timing parameters (all in number of PPI clk ticks)
+ */
+
+#define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
+#define H_PERIOD (336 * CLOCKS_PPIX) /* HS period */
+#define H_PULSE (2 * CLOCKS_PPIX) /* HS pulse width */
+#define H_START (7 * CLOCKS_PPIX + CPLD_DELAY) /* first valid pixel */
+
+#define U_LINE 4 /* Blanking Lines */
+
+#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
+#define V_PULSE (2 * CLOCKS_PPIX) /* VS pulse width (1-5 H_PERIODs) */
+#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
+
+#define ACTIVE_VIDEO_MEM_OFFSET ((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8))
+
+/*
+ * LCD Modes
+ */
+#define LQ035_RL (0 << 8) /* Right -> Left Scan */
+#define LQ035_LR (1 << 8) /* Left -> Right Scan */
+#define LQ035_TB (1 << 9) /* Top -> Botton Scan */
+#define LQ035_BT (0 << 9) /* Botton -> Top Scan */
+#define LQ035_BGR (1 << 11) /* Use BGR format */
+#define LQ035_RGB (0 << 11) /* Use RGB format */
+#define LQ035_NORM (1 << 13) /* Reversal */
+#define LQ035_REV (0 << 13) /* Reversal */
+
+#define LQ035_INDEX 0x74
+#define LQ035_DATA 0x76
+
+#define LQ035_DRIVER_OUTPUT_CTL 0x1
+#define LQ035_SHUT_CTL 0x11
+
+#define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
+#define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
+
+#define LQ035_SHUT (1 << 0) /* Shutdown */
+#define LQ035_ON (0 << 0) /* Shutdown */
+
+#ifndef CONFIG_LQ035Q1_LCD_MODE
+#define CONFIG_LQ035Q1_LCD_MODE (LQ035_NORM | LQ035_RL | LQ035_TB | LQ035_BGR)
+#endif
+
+#else /* t350mcqb */
+
+#define LCD_BPP 24 /* Bit Per Pixel */
+#define CLOCKS_PPIX 3 /* Clocks per pixel */
+
+/* HS and VS timing parameters (all in number of PPI clk ticks) */
+#define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
+#define H_PERIOD (408 * CLOCKS_PPIX) /* HS period */
+#define H_PULSE 90 /* HS pulse width */
+#define H_START 204 /* first valid pixel */
+
+#define U_LINE 1 /* Blanking Lines */
+
+#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
+#define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
+#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
+
+#define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
+#endif
+
+#define LCD_PIXEL_SIZE (LCD_BPP / 8)
+#define DMA_SIZE16 2
+
+#define PPI_TX_MODE 0x2
+#define PPI_XFER_TYPE_11 0xC
+#define PPI_PORT_CFG_01 0x10
+#define PPI_PACK_EN 0x80
+#define PPI_POLS_1 0x8000
+
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
+static struct spi_slave *slave;
+static int lq035q1_control(unsigned char reg, unsigned short value)
+{
+ int ret;
+ u8 regs[3] = {LQ035_INDEX, 0, 0};
+ u8 data[3] = {LQ035_DATA, 0, 0};
+ u8 dummy[3];
+
+ regs[2] = reg;
+ data[1] = value >> 8;
+ data[2] = value & 0xFF;
+
+ if (!slave) {
+ /* FIXME: Verify the max SCK rate */
+ slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS,
+ CONFIG_LQ035Q1_SPI_CS, 20000000,
+ SPI_MODE_3);
+ if (!slave)
+ return -1;
+ }
+
+ if (spi_claim_bus(slave))
+ return -1;
+
+ ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+ ret |= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+
+ spi_release_bus(slave);
+
+ return ret;
+}
+#endif
+
+/* enable and disable PPI functions */
+void EnablePPI(void)
+{
+ bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
+}
+
+void DisablePPI(void)
+{
+ bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
+}
+
+void Init_Ports(void)
+{
+ const unsigned short pins[] = {
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
+ P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0,
+ };
+ peripheral_request_list(pins, "lcd");
+}
+
+void Init_PPI(void)
+{
+
+ bfin_write_PPI_DELAY(H_START);
+ bfin_write_PPI_COUNT(H_ACTPIX - 1);
+ bfin_write_PPI_FRAME(V_LINES);
+
+ /* PPI control, to be replaced with definitions */
+ bfin_write_PPI_CONTROL(
+ PPI_TX_MODE | /* output mode , PORT_DIR */
+ PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
+ PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
+ PPI_PACK_EN | /* packing enabled PACK_EN */
+ PPI_POLS_1 /* faling edge syncs POLS */
+ );
+}
+
+void Init_DMA(void *dst)
+{
+ bfin_write_DMA0_START_ADDR(dst);
+
+ /* X count */
+ bfin_write_DMA0_X_COUNT(H_ACTPIX / 2);
+ bfin_write_DMA0_X_MODIFY(DMA_BUS_SIZE / 8);
+
+ /* Y count */
+ bfin_write_DMA0_Y_COUNT(V_LINES);
+ bfin_write_DMA0_Y_MODIFY(DMA_BUS_SIZE / 8);
+
+ /* DMA Config */
+ bfin_write_DMA0_CONFIG(
+ WDSIZE_16 | /* 16 bit DMA */
+ DMA2D | /* 2D DMA */
+ FLOW_AUTO /* autobuffer mode */
+ );
+}
+
+void EnableDMA(void)
+{
+ bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() | DMAEN);
+}
+
+void DisableDMA(void)
+{
+ bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN);
+}
+
+/* Init TIMER0 as Frame Sync 1 generator */
+void InitTIMER0(void)
+{
+ bfin_write_TIMER_DISABLE(TIMDIS0); /* disable Timer */
+ SSYNC();
+ bfin_write_TIMER_STATUS(TIMIL0 | TOVF_ERR0 | TRUN0); /* clear status */
+ SSYNC();
+
+ bfin_write_TIMER0_PERIOD(H_PERIOD);
+ SSYNC();
+ bfin_write_TIMER0_WIDTH(H_PULSE);
+ SSYNC();
+
+ bfin_write_TIMER0_CONFIG(
+ PWM_OUT |
+ PERIOD_CNT |
+ TIN_SEL |
+ CLK_SEL |
+ EMU_RUN
+ );
+ SSYNC();
+}
+
+void EnableTIMER0(void)
+{
+ bfin_write_TIMER_ENABLE(TIMEN0);
+ SSYNC();
+}
+
+void DisableTIMER0(void)
+{
+ bfin_write_TIMER_DISABLE(TIMDIS0);
+ SSYNC();
+}
+
+
+void InitTIMER1(void)
+{
+ bfin_write_TIMER_DISABLE(TIMDIS1); /* disable Timer */
+ SSYNC();
+ bfin_write_TIMER_STATUS(TIMIL1 | TOVF_ERR1 | TRUN1); /* clear status */
+ SSYNC();
+
+ bfin_write_TIMER1_PERIOD(V_PERIOD);
+ SSYNC();
+ bfin_write_TIMER1_WIDTH(V_PULSE);
+ SSYNC();
+
+ bfin_write_TIMER1_CONFIG(
+ PWM_OUT |
+ PERIOD_CNT |
+ TIN_SEL |
+ CLK_SEL |
+ EMU_RUN
+ );
+ SSYNC();
+}
+
+void EnableTIMER1(void)
+{
+ bfin_write_TIMER_ENABLE(TIMEN1);
+ SSYNC();
+}
+
+void DisableTIMER1(void)
+{
+ bfin_write_TIMER_DISABLE(TIMDIS1);
+ SSYNC();
+}
+
+void EnableTIMER12(void)
+{
+ bfin_write_TIMER_ENABLE(TIMEN1 | TIMEN0);
+ SSYNC();
+}
+
+int video_init(void *dst)
+{
+
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
+ lq035q1_control(LQ035_SHUT_CTL, LQ035_ON);
+ lq035q1_control(LQ035_DRIVER_OUTPUT_CTL, (CONFIG_LQ035Q1_LCD_MODE &
+ LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT);
+#endif
+ Init_Ports();
+ Init_DMA(dst);
+ EnableDMA();
+ InitTIMER0();
+ InitTIMER1();
+ Init_PPI();
+ EnablePPI();
+
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
+ EnableTIMER12();
+#else
+ /* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
+ EnableTIMER1();
+ /* Add Some Delay ... */
+ SSYNC();
+ SSYNC();
+ SSYNC();
+ SSYNC();
+
+ /* now start frame sync 1 */
+ EnableTIMER0();
+#endif
+
+ return 0;
+}
+
+static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
+{
+ if (dcache_status())
+ blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
+
+ bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+
+ /* Setup destination start address */
+ bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
+ + (y * LCD_X_RES * LCD_PIXEL_SIZE));
+ /* Setup destination xcount */
+ bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+ /* Setup destination xmodify */
+ bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
+
+ /* Setup destination ycount */
+ bfin_write_MDMA_D0_Y_COUNT(logo->height);
+ /* Setup destination ymodify */
+ bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
+
+
+ /* Setup Source start address */
+ bfin_write_MDMA_S0_START_ADDR(logo->data);
+ /* Setup Source xcount */
+ bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+ /* Setup Source xmodify */
+ bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
+
+ /* Setup Source ycount */
+ bfin_write_MDMA_S0_Y_COUNT(logo->height);
+ /* Setup Source ymodify */
+ bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
+
+
+ /* Enable source DMA */
+ bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
+ SSYNC();
+ bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
+
+ while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
+
+ bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+ bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+
+}
+
+void video_stop(void)
+{
+ DisablePPI();
+ DisableDMA();
+ DisableTIMER0();
+ DisableTIMER1();
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
+ lq035q1_control(LQ035_SHUT_CTL, LQ035_SHUT);
+#endif
+}
+
+int drv_video_init(void)
+{
+ int error, devices = 1;
+ struct stdio_dev videodev;
+
+ u8 *dst;
+ u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
+
+ dst = malloc(fbmem_size);
+
+ if (dst == NULL) {
+ printf("Failed to alloc FB memory\n");
+ return -1;
+ }
+
+#ifdef EASYLOGO_ENABLE_GZIP
+ unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+ unsigned long src_len = EASYLOGO_ENABLE_GZIP;
+ error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
+ bfin_logo.data = data;
+#elif defined(EASYLOGO_ENABLE_LZMA)
+ unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+ SizeT lzma_len = bfin_logo.size;
+ error = lzmaBuffToBuffDecompress(data, &lzma_len,
+ bfin_logo.data, EASYLOGO_ENABLE_LZMA);
+ bfin_logo.data = data;
+#else
+ error = 0;
+#endif
+
+ if (error) {
+ puts("Failed to decompress logo\n");
+ free(dst);
+ return -1;
+ }
+
+ memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
+
+ dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
+ (LCD_X_RES - bfin_logo.width) / 2,
+ (LCD_Y_RES - bfin_logo.height) / 2);
+
+ video_init(dst); /* Video initialization */
+
+ memset(&videodev, 0, sizeof(videodev));
+
+ strcpy(videodev.name, "video");
+ videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
+ videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
+
+ error = stdio_register(&videodev);
+
+ return (error == 0) ? devices : error;
+}
diff --git a/board/bf527-sdp/Kconfig b/board/bf527-sdp/Kconfig
new file mode 100644
index 0000000..928bd77
--- /dev/null
+++ b/board/bf527-sdp/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF527_SDP
+
+config SYS_BOARD
+ default "bf527-sdp"
+
+config SYS_CONFIG_NAME
+ default "bf527-sdp"
+
+endif
diff --git a/board/bf527-sdp/MAINTAINERS b/board/bf527-sdp/MAINTAINERS
new file mode 100644
index 0000000..32ccfc5
--- /dev/null
+++ b/board/bf527-sdp/MAINTAINERS
@@ -0,0 +1,6 @@
+BF527-SDP BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf527-sdp/
+F: include/configs/bf527-sdp.h
+F: configs/bf527-sdp_defconfig
diff --git a/board/bf527-sdp/Makefile b/board/bf527-sdp/Makefile
new file mode 100644
index 0000000..1ddb026
--- /dev/null
+++ b/board/bf527-sdp/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf527-sdp.o
diff --git a/board/bf527-sdp/bf527-sdp.c b/board/bf527-sdp/bf527-sdp.c
new file mode 100644
index 0000000..504869d
--- /dev/null
+++ b/board/bf527-sdp/bf527-sdp.c
@@ -0,0 +1,32 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/mach-common/bits/pll.h>
+
+int checkboard(void)
+{
+ printf("Board: ADI BF527 SDP board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+
+ /* Enable access to parallel flash */
+ gpio_request(GPIO_PG0, "parallel-flash");
+ gpio_direction_output(GPIO_PG0, 0);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ /* CLKIN Buffer Output Enable */
+ bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
+
+ return 0;
+}
diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk
new file mode 100644
index 0000000..1d46cfc
--- /dev/null
+++ b/board/bf527-sdp/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6
diff --git a/board/bf533-ezkit/Kconfig b/board/bf533-ezkit/Kconfig
new file mode 100644
index 0000000..555ab29
--- /dev/null
+++ b/board/bf533-ezkit/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF533_EZKIT
+
+config SYS_BOARD
+ default "bf533-ezkit"
+
+config SYS_CONFIG_NAME
+ default "bf533-ezkit"
+
+endif
diff --git a/board/bf533-ezkit/MAINTAINERS b/board/bf533-ezkit/MAINTAINERS
new file mode 100644
index 0000000..bfa7c3c
--- /dev/null
+++ b/board/bf533-ezkit/MAINTAINERS
@@ -0,0 +1,6 @@
+BF533-EZKIT BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf533-ezkit/
+F: include/configs/bf533-ezkit.h
+F: configs/bf533-ezkit_defconfig
diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile
new file mode 100644
index 0000000..6838cf0
--- /dev/null
+++ b/board/bf533-ezkit/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf533-ezkit.o flash.o
diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c
new file mode 100644
index 0000000..81e390c
--- /dev/null
+++ b/board/bf533-ezkit/bf533-ezkit.c
@@ -0,0 +1,44 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include "psd4256.h"
+#include "flash-defines.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF533 EZ-Kit Lite board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+ /* Set direction bits for Video en/decoder reset as output */
+ *(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DIR) =
+ PSDA_VDEC_RST | PSDA_VENC_RST;
+ /* Deactivate Video en/decoder reset lines */
+ *(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DOUT) =
+ PSDA_VDEC_RST | PSDA_VENC_RST;
+
+ return 0;
+}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk
new file mode 100644
index 0000000..7f9138b
--- /dev/null
+++ b/board/bf533-ezkit/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h
new file mode 100644
index 0000000..fa32203
--- /dev/null
+++ b/board/bf533-ezkit/flash-defines.h
@@ -0,0 +1,106 @@
+/*
+ * U-boot - flash-defines.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FLASHDEFINES_H__
+#define __FLASHDEFINES_H__
+
+#include <common.h>
+
+#define V_ULONG(a) (*(volatile unsigned long *)( a ))
+#define V_BYTE(a) (*(volatile unsigned char *)( a ))
+#define BUFFER_SIZE 0x80000
+#define NO_COMMAND 0
+#define GET_CODES 1
+#define RESET 2
+#define WRITE 3
+#define FILL 4
+#define ERASE_ALL 5
+#define ERASE_SECT 6
+#define READ 7
+#define GET_SECTNUM 8
+#define FLASH_START_L 0x0000
+#define FLASH_START_H 0x2000
+#define FLASH_TOT_SECT 40
+#define FLASH_SIZE 0x220000
+#define FLASH_MAN_ST 2
+#define CONFIG_SYS_FLASH0_BASE 0x20000000
+#define CONFIG_SYS_FLASH1_BASE 0x20200000
+#define RESET_VAL 0xF0
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+int get_codes(void);
+int poll_toggle_bit(long lOffset);
+void reset_flash(void);
+int erase_flash(void);
+int erase_block_flash(int, unsigned long);
+void unlock_flash(long lOffset);
+int write_data(long lStart, long lCount, uchar *pnData);
+int FillData(long lStart, long lCount, long lStride, int *pnData);
+int read_data(long lStart, long lCount, long lStride, int *pnData);
+int read_flash(long nOffset, int *pnValue);
+int write_flash(long nOffset, int nValue);
+void get_sector_number(long lOffset, int *pnSector);
+int GetSectorProtectionStatus(flash_info_t * info, int nSector);
+int GetOffset(int nBlock);
+
+#define WRITESEQ1 0x0AAA
+#define WRITESEQ2 0x0554
+#define WRITESEQ3 0x0AAA
+#define WRITESEQ4 0x0AAA
+#define WRITESEQ5 0x0554
+#define WRITESEQ6 0x0AAA
+#define WRITEDATA1 0xaa
+#define WRITEDATA2 0x55
+#define WRITEDATA3 0x80
+#define WRITEDATA4 0xaa
+#define WRITEDATA5 0x55
+#define WRITEDATA6 0x10
+#define PriFlashABegin 0
+#define SecFlashABegin 32
+#define SecFlashBBegin 36
+#define PriFlashAOff 0x0
+#define PriFlashBOff 0x100000
+#define SecFlashAOff 0x200000
+#define SecFlashBOff 0x280000
+#define INVALIDLOCNSTART 0x20270000
+#define INVALIDLOCNEND 0x20280000
+#define BlockEraseVal 0x30
+#define UNLOCKDATA1 0xaa
+#define UNLOCKDATA2 0x55
+#define UNLOCKDATA3 0xa0
+#define GETCODEDATA1 0xaa
+#define GETCODEDATA2 0x55
+#define GETCODEDATA3 0x90
+#define SecFlashASec1Off 0x200000
+#define SecFlashASec2Off 0x204000
+#define SecFlashASec3Off 0x206000
+#define SecFlashASec4Off 0x208000
+#define SecFlashAEndOff 0x210000
+#define SecFlashBSec1Off 0x280000
+#define SecFlashBSec2Off 0x284000
+#define SecFlashBSec3Off 0x286000
+#define SecFlashBSec4Off 0x288000
+#define SecFlashBEndOff 0x290000
+
+#define SECT32 32
+#define SECT33 33
+#define SECT34 34
+#define SECT35 35
+#define SECT36 36
+#define SECT37 37
+#define SECT38 38
+#define SECT39 39
+
+#define FLASH_SUCCESS 0
+#define FLASH_FAIL -1
+
+#endif
diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c
new file mode 100644
index 0000000..fd06b31
--- /dev/null
+++ b/board/bf533-ezkit/flash.c
@@ -0,0 +1,473 @@
+/*
+ * U-boot - flash.c Flash driver for PSD4256GV
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include "flash-defines.h"
+
+int AFP_NumSectors = 40;
+long AFP_SectorSize1 = 0x10000;
+int AFP_SectorSize2 = 0x4000;
+
+void flash_reset(void)
+{
+ reset_flash();
+}
+
+unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
+{
+ int id = 0, i = 0;
+ static int FlagDev = 1;
+
+ id = get_codes();
+ if (FlagDev) {
+#ifdef DEBUG
+ printf("Device ID of the Flash is %x\n", id);
+#endif
+ FlagDev = 0;
+ }
+ info->flash_id = id;
+
+ switch (bank_flag) {
+ case 0:
+ for (i = PriFlashABegin; i < SecFlashABegin; i++)
+ info->start[i] = (baseaddr + (i * AFP_SectorSize1));
+ info->size = 0x200000;
+ info->sector_count = 32;
+ break;
+ case 1:
+ info->start[0] = baseaddr + SecFlashASec1Off;
+ info->start[1] = baseaddr + SecFlashASec2Off;
+ info->start[2] = baseaddr + SecFlashASec3Off;
+ info->start[3] = baseaddr + SecFlashASec4Off;
+ info->size = 0x10000;
+ info->sector_count = 4;
+ break;
+ case 2:
+ info->start[0] = baseaddr + SecFlashBSec1Off;
+ info->start[1] = baseaddr + SecFlashBSec2Off;
+ info->start[2] = baseaddr + SecFlashBSec3Off;
+ info->start[3] = baseaddr + SecFlashBSec4Off;
+ info->size = 0x10000;
+ info->sector_count = 4;
+ break;
+ }
+ return (info->size);
+}
+
+unsigned long flash_init(void)
+{
+ unsigned long size_b0, size_b1, size_b2;
+ int i;
+
+ size_b0 = size_b1 = size_b2 = 0;
+#ifdef DEBUG
+ printf("Flash Memory Start 0x%x\n", CONFIG_SYS_FLASH_BASE);
+ printf("Memory Map for the Flash\n");
+ printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n");
+ printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n");
+ printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n");
+ printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n");
+ printf("Please type command flinfo for information on Sectors \n");
+#endif
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0], 0);
+ size_b1 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[1], 1);
+ size_b2 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[2], 2);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 >> 20);
+ }
+
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH0_BASE,
+ (flash_info[0].start[2] - 1), &flash_info[0]);
+
+ return (size_b0 + size_b1 + size_b2);
+}
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id) {
+ case FLASH_PSD4256GV:
+ printf("ST Microelectronics ");
+ break;
+ default:
+ printf("Unknown Vendor: (0x%08lX) ", info->flash_id);
+ break;
+ }
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf("\n");
+ return;
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ int cnt = 0, i;
+ int prot, sect;
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ else
+ printf("\n");
+
+ cnt = s_last - s_first + 1;
+
+ if (cnt == FLASH_TOT_SECT) {
+ printf("Erasing flash, Please Wait \n");
+ if (erase_flash() < 0) {
+ printf("Erasing flash failed \n");
+ return FLASH_FAIL;
+ }
+ } else {
+ printf("Erasing Flash locations, Please Wait\n");
+ for (i = s_first; i <= s_last; i++) {
+ if (info->protect[i] == 0) { /* not protected */
+ if (erase_block_flash(i, info->start[i]) < 0) {
+ printf("Error Sector erasing \n");
+ return FLASH_FAIL;
+ }
+ }
+ }
+ }
+ return FLASH_SUCCESS;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ int ret;
+ int d;
+ if (addr % 2) {
+ read_flash(addr - 1 - CONFIG_SYS_FLASH_BASE, &d);
+ d = (int)((d & 0x00FF) | (*src++ << 8));
+ ret = write_data(addr - 1, 2, (uchar *) & d);
+ if (ret == FLASH_FAIL)
+ return ERR_NOT_ERASED;
+ ret = write_data(addr + 1, cnt - 1, src);
+ } else
+ ret = write_data(addr, cnt, src);
+ if (ret == FLASH_FAIL)
+ return ERR_NOT_ERASED;
+ return FLASH_SUCCESS;
+}
+
+int write_data(long lStart, long lCount, uchar * pnData)
+{
+ long i = 0;
+ unsigned long ulOffset = lStart - CONFIG_SYS_FLASH_BASE;
+ int d;
+ int nSector = 0;
+ int flag = 0;
+
+ if (lCount % 2) {
+ flag = 1;
+ lCount = lCount - 1;
+ }
+
+ for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
+ get_sector_number(ulOffset, &nSector);
+ read_flash(ulOffset, &d);
+ if (d != 0xffff) {
+ printf
+ ("Flash not erased at offset 0x%lx Please erase to reprogram\n",
+ ulOffset);
+ return FLASH_FAIL;
+ }
+ unlock_flash(ulOffset);
+ d = (int)(pnData[i] | pnData[i + 1] << 8);
+ write_flash(ulOffset, d);
+ if (poll_toggle_bit(ulOffset) < 0) {
+ printf("Error programming the flash \n");
+ return FLASH_FAIL;
+ }
+ if ((i > 0) && (!(i % AFP_SectorSize2)))
+ printf(".");
+ }
+ if (flag) {
+ get_sector_number(ulOffset, &nSector);
+ read_flash(ulOffset, &d);
+ if (d != 0xffff) {
+ printf
+ ("Flash not erased at offset 0x%lx Please erase to reprogram\n",
+ ulOffset);
+ return FLASH_FAIL;
+ }
+ unlock_flash(ulOffset);
+ d = (int)(pnData[i] | (d & 0xFF00));
+ write_flash(ulOffset, d);
+ if (poll_toggle_bit(ulOffset) < 0) {
+ printf("Error programming the flash \n");
+ return FLASH_FAIL;
+ }
+ }
+ return FLASH_SUCCESS;
+}
+
+int read_data(long ulStart, long lCount, long lStride, int *pnData)
+{
+ long i = 0;
+ int j = 0;
+ long ulOffset = ulStart;
+ int iShift = 0;
+ int iNumWords = 2;
+ int nLeftover = lCount % 4;
+ int nHi, nLow;
+ int nSector = 0;
+
+ for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
+ for (iShift = 0, j = 0; j < iNumWords; j += 2) {
+ if ((ulOffset >= INVALIDLOCNSTART)
+ && (ulOffset < INVALIDLOCNEND))
+ return FLASH_FAIL;
+
+ get_sector_number(ulOffset, &nSector);
+ read_flash(ulOffset, &nLow);
+ ulOffset += (lStride * 2);
+ read_flash(ulOffset, &nHi);
+ ulOffset += (lStride * 2);
+ pnData[i] = (nHi << 16) | nLow;
+ }
+ }
+ if (nLeftover > 0) {
+ if ((ulOffset >= INVALIDLOCNSTART)
+ && (ulOffset < INVALIDLOCNEND))
+ return FLASH_FAIL;
+
+ get_sector_number(ulOffset, &nSector);
+ read_flash(ulOffset, &pnData[i]);
+ }
+ return FLASH_SUCCESS;
+}
+
+int write_flash(long nOffset, int nValue)
+{
+ long addr;
+
+ addr = (CONFIG_SYS_FLASH_BASE + nOffset);
+ SSYNC();
+ *(unsigned volatile short *)addr = nValue;
+ SSYNC();
+ if (poll_toggle_bit(nOffset) < 0)
+ return FLASH_FAIL;
+ return FLASH_SUCCESS;
+}
+
+int read_flash(long nOffset, int *pnValue)
+{
+ int nValue = 0x0;
+ long addr = (CONFIG_SYS_FLASH_BASE + nOffset);
+
+ if (nOffset != 0x2)
+ reset_flash();
+ SSYNC();
+ nValue = *(volatile unsigned short *)addr;
+ SSYNC();
+ *pnValue = nValue;
+ return true;
+}
+
+int poll_toggle_bit(long lOffset)
+{
+ unsigned int u1, u2;
+ unsigned long timeout = 0xFFFFFFFF;
+ volatile unsigned long *FB =
+ (volatile unsigned long *)(0x20000000 + lOffset);
+ while (1) {
+ if (timeout < 0)
+ break;
+ u1 = *(volatile unsigned short *)FB;
+ u2 = *(volatile unsigned short *)FB;
+ if ((u1 & 0x0040) == (u2 & 0x0040))
+ return FLASH_SUCCESS;
+ if ((u2 & 0x0020) == 0x0000)
+ continue;
+ u1 = *(volatile unsigned short *)FB;
+ if ((u2 & 0x0040) == (u1 & 0x0040))
+ return FLASH_SUCCESS;
+ else {
+ reset_flash();
+ return FLASH_FAIL;
+ }
+ timeout--;
+ }
+ printf("Time out occured \n");
+ if (timeout < 0)
+ return FLASH_FAIL;
+}
+
+void reset_flash(void)
+{
+ write_flash(WRITESEQ1, RESET_VAL);
+ /* Wait for 10 micro seconds */
+ udelay(10);
+}
+
+int erase_flash(void)
+{
+ write_flash(WRITESEQ1, WRITEDATA1);
+ write_flash(WRITESEQ2, WRITEDATA2);
+ write_flash(WRITESEQ3, WRITEDATA3);
+ write_flash(WRITESEQ4, WRITEDATA4);
+ write_flash(WRITESEQ5, WRITEDATA5);
+ write_flash(WRITESEQ6, WRITEDATA6);
+
+ if (poll_toggle_bit(0x0000) < 0)
+ return FLASH_FAIL;
+
+ write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1);
+ write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2);
+ write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3);
+ write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4);
+ write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5);
+ write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6);
+
+ if (poll_toggle_bit(SecFlashASec1Off) < 0)
+ return FLASH_FAIL;
+
+ write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1);
+ write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2);
+ write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3);
+ write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4);
+ write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5);
+ write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6);
+
+ if (poll_toggle_bit(PriFlashBOff) < 0)
+ return FLASH_FAIL;
+
+ write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1);
+ write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2);
+ write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3);
+ write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4);
+ write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5);
+ write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6);
+
+ if (poll_toggle_bit(SecFlashBOff) < 0)
+ return FLASH_FAIL;
+
+ return FLASH_SUCCESS;
+}
+
+int erase_block_flash(int nBlock, unsigned long address)
+{
+ long ulSectorOff = 0x0;
+
+ if ((nBlock < 0) || (nBlock > AFP_NumSectors))
+ return false;
+
+ ulSectorOff = (address - CONFIG_SYS_FLASH_BASE);
+
+ write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
+ write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
+ write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
+ write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
+ write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
+
+ write_flash(ulSectorOff, BlockEraseVal);
+
+ if (poll_toggle_bit(ulSectorOff) < 0)
+ return FLASH_FAIL;
+
+ return FLASH_SUCCESS;
+}
+
+void unlock_flash(long ulOffset)
+{
+ unsigned long ulOffsetAddr = ulOffset;
+ ulOffsetAddr &= 0xFFFF0000;
+
+ write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
+ write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
+ write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
+}
+
+int get_codes()
+{
+ int dev_id = 0;
+
+ write_flash(WRITESEQ1, GETCODEDATA1);
+ write_flash(WRITESEQ2, GETCODEDATA2);
+ write_flash(WRITESEQ3, GETCODEDATA3);
+
+ read_flash(0x0002, &dev_id);
+ dev_id &= 0x00FF;
+
+ reset_flash();
+
+ return dev_id;
+}
+
+void get_sector_number(long ulOffset, int *pnSector)
+{
+ int nSector = 0;
+
+ if (ulOffset >= SecFlashAOff) {
+ if ((ulOffset < SecFlashASec1Off)
+ && (ulOffset < SecFlashASec2Off)) {
+ nSector = SECT32;
+ } else if ((ulOffset >= SecFlashASec2Off)
+ && (ulOffset < SecFlashASec3Off)) {
+ nSector = SECT33;
+ } else if ((ulOffset >= SecFlashASec3Off)
+ && (ulOffset < SecFlashASec4Off)) {
+ nSector = SECT34;
+ } else if ((ulOffset >= SecFlashASec4Off)
+ && (ulOffset < SecFlashAEndOff)) {
+ nSector = SECT35;
+ }
+ } else if (ulOffset >= SecFlashBOff) {
+ if ((ulOffset < SecFlashBSec1Off)
+ && (ulOffset < SecFlashBSec2Off)) {
+ nSector = SECT36;
+ }
+ if ((ulOffset < SecFlashBSec2Off)
+ && (ulOffset < SecFlashBSec3Off)) {
+ nSector = SECT37;
+ }
+ if ((ulOffset < SecFlashBSec3Off)
+ && (ulOffset < SecFlashBSec4Off)) {
+ nSector = SECT38;
+ }
+ if ((ulOffset < SecFlashBSec4Off)
+ && (ulOffset < SecFlashBEndOff)) {
+ nSector = SECT39;
+ }
+ } else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) {
+ nSector = ulOffset & 0xffff0000;
+ nSector = ulOffset >> 16;
+ nSector = nSector & 0x000ff;
+ }
+
+ if ((nSector >= 0) && (nSector < AFP_NumSectors)) {
+ *pnSector = nSector;
+ }
+}
diff --git a/board/bf533-ezkit/psd4256.h b/board/bf533-ezkit/psd4256.h
new file mode 100644
index 0000000..56c6442
--- /dev/null
+++ b/board/bf533-ezkit/psd4256.h
@@ -0,0 +1,51 @@
+/*
+ * U-boot - psd4256.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Flash A/B Port A configuration registers.
+ * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
+ * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
+ */
+
+#define PSD_PORTA_DIN 0x070000
+#define PSD_PORTA_DOUT 0x070004
+#define PSD_PORTA_DIR 0x070006
+
+/*
+ * Flash A/B Port B configuration registers
+ * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
+ * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
+ */
+
+#define PSD_PORTB_DIN 0x070001
+#define PSD_PORTB_DOUT 0x070005
+#define PSD_PORTB_DIR 0x070007
+
+/*
+ * Flash A Port A Bit definitions
+ */
+
+#define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */
+#define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */
+#define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */
+#define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */
+#define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */
+
+/*
+ * Flash A Port B Bit definitions
+ */
+
+#define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */
+#define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */
+#define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */
+#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */
+#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */
+#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */
diff --git a/board/bf533-stamp/Kconfig b/board/bf533-stamp/Kconfig
new file mode 100644
index 0000000..0cffde3
--- /dev/null
+++ b/board/bf533-stamp/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF533_STAMP
+
+config SYS_BOARD
+ default "bf533-stamp"
+
+config SYS_CONFIG_NAME
+ default "bf533-stamp"
+
+endif
diff --git a/board/bf533-stamp/MAINTAINERS b/board/bf533-stamp/MAINTAINERS
new file mode 100644
index 0000000..c7aeefa
--- /dev/null
+++ b/board/bf533-stamp/MAINTAINERS
@@ -0,0 +1,6 @@
+BF533-STAMP BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf533-stamp/
+F: include/configs/bf533-stamp.h
+F: configs/bf533-stamp_defconfig
diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile
new file mode 100644
index 0000000..244f9e0
--- /dev/null
+++ b/board/bf533-stamp/Makefile
@@ -0,0 +1,14 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf533-stamp.o
+obj-$(CONFIG_STAMP_CF) += ide-cf.o
+obj-$(CONFIG_VIDEO) += video.o
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
new file mode 100644
index 0000000..585f5f1
--- /dev/null
+++ b/board/bf533-stamp/bf533-stamp.c
@@ -0,0 +1,119 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF533 Stamp board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+/* PF0 and PF1 are used to switch between the ethernet and flash:
+ * PF0 PF1
+ * flash: 0 0
+ * ether: 1 0
+ */
+void swap_to(int device_id)
+{
+ gpio_request(GPIO_PF0, "eth_flash_swap");
+ gpio_request(GPIO_PF1, "eth_flash_swap");
+ gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
+ gpio_direction_output(GPIO_PF1, 0);
+ SSYNC();
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+#ifdef CONFIG_STAMP_CF
+ cf_ide_init();
+#endif
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+
+#define STATUS_LED_OFF 0
+#define STATUS_LED_ON 1
+
+static int gpio_setup;
+
+static void stamp_led_set(int LED1, int LED2, int LED3)
+{
+ if (!gpio_setup) {
+ gpio_request(GPIO_PF2, "boot_progress");
+ gpio_request(GPIO_PF3, "boot_progress");
+ gpio_request(GPIO_PF4, "boot_progress");
+ gpio_direction_output(GPIO_PF2, LED1);
+ gpio_direction_output(GPIO_PF3, LED2);
+ gpio_direction_output(GPIO_PF4, LED3);
+ gpio_setup = 1;
+ } else {
+ gpio_set_value(GPIO_PF2, LED1);
+ gpio_set_value(GPIO_PF3, LED2);
+ gpio_set_value(GPIO_PF4, LED3);
+ }
+}
+
+void show_boot_progress(int status)
+{
+ switch (status) {
+ case BOOTSTAGE_ID_CHECK_MAGIC:
+ stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
+ break;
+ case BOOTSTAGE_ID_CHECK_HEADER:
+ stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
+ break;
+ case BOOTSTAGE_ID_CHECK_CHECKSUM:
+ stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
+ break;
+ case BOOTSTAGE_ID_CHECK_ARCH:
+ stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
+ break;
+ case BOOTSTAGE_ID_CHECK_IMAGETYPE:
+ case BOOTSTAGE_ID_DECOMP_IMAGE:
+ stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
+ break;
+ case BOOTSTAGE_ID_KERNEL_LOADED:
+ case BOOTSTAGE_ID_CHECK_BOOT_OS:
+ stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
+ break;
+ case BOOTSTAGE_ID_BOOT_OS_RETURNED:
+ case BOOTSTAGE_ID_RD_MAGIC:
+ case BOOTSTAGE_ID_RD_HDR_CHECKSUM:
+ case BOOTSTAGE_ID_RD_CHECKSUM:
+ case BOOTSTAGE_ID_RAMDISK:
+ case BOOTSTAGE_ID_NO_RAMDISK:
+ case BOOTSTAGE_ID_RUN_OS:
+ stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_OFF);
+ break;
+ default:
+ stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
+ break;
+ }
+}
+#endif
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk
new file mode 100644
index 0000000..7f9138b
--- /dev/null
+++ b/board/bf533-stamp/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf533-stamp/ide-cf.c b/board/bf533-stamp/ide-cf.c
new file mode 100644
index 0000000..3e4080e
--- /dev/null
+++ b/board/bf533-stamp/ide-cf.c
@@ -0,0 +1,98 @@
+/*
+ * CF IDE addon card code
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+void cf_outb(unsigned char val, volatile unsigned char *addr)
+{
+ /* "ETHERNET" means the expansion memory banks */
+ swap_to(ETHERNET);
+
+ *addr = val;
+ SSYNC();
+
+ swap_to(FLASH);
+}
+
+unsigned char cf_inb(volatile unsigned char *addr)
+{
+ unsigned char c;
+
+ swap_to(ETHERNET);
+
+ c = *addr;
+ SSYNC();
+
+ swap_to(FLASH);
+
+ return c;
+}
+
+void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
+{
+ int i;
+
+ swap_to(ETHERNET);
+
+ for (i = 0; i < words; i++) {
+ *(sect_buf + i) = *addr;
+ SSYNC();
+ }
+
+ swap_to(FLASH);
+}
+
+void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
+{
+ int i;
+
+ swap_to(ETHERNET);
+
+ for (i = 0; i < words; i++) {
+ *addr = *(sect_buf + i);
+ SSYNC();
+ }
+
+ swap_to(FLASH);
+}
+
+/* Definitions used in Compact Flash Boot support */
+#define FIO_EDGE_CF_BITS 0x0000
+#define FIO_POLAR_CF_BITS 0x0000
+#define FIO_EDGE_BITS 0x1E0
+#define FIO_POLAR_BITS 0x160
+
+/* Compact flash status bits in status register */
+#define CF_STAT_BITS 0x00000060
+
+void cf_ide_init(void)
+{
+ int i, cf_stat;
+
+ /* Check whether CF card is inserted */
+ bfin_write_FIO_EDGE(FIO_EDGE_CF_BITS);
+ bfin_write_FIO_POLAR(FIO_POLAR_CF_BITS);
+ for (i = 0; i < 0x300; i++)
+ asm volatile("nop;");
+
+ cf_stat = bfin_read_FIO_FLAG_S() & CF_STAT_BITS;
+
+ bfin_write_FIO_EDGE(FIO_EDGE_BITS);
+ bfin_write_FIO_POLAR(FIO_POLAR_BITS);
+
+ if (!cf_stat) {
+ for (i = 0; i < 0x3000; i++)
+ asm volatile("nop;");
+
+ ide_init();
+ }
+}
diff --git a/board/bf533-stamp/video.c b/board/bf533-stamp/video.c
new file mode 100644
index 0000000..75b8adc
--- /dev/null
+++ b/board/bf533-stamp/video.c
@@ -0,0 +1,171 @@
+/*
+ * BF533-STAMP splash driver
+ *
+ * Copyright (c) 2006-2008 Analog Devices Inc.
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ * (C) Copyright 2002
+ * Wolfgang Denk, wd@denx.de
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/dma.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <stdio_dev.h>
+
+#define DMA_SIZE16 2
+
+#include <asm/mach-common/bits/ppi.h>
+
+#define NTSC_FRAME_ADDR 0x06000000
+#include "video.h"
+
+/* NTSC OUTPUT SIZE 720 * 240 */
+#define VERTICAL 2
+#define HORIZONTAL 4
+
+int is_vblank_line(const int line)
+{
+ /*
+ * This array contains a single bit for each line in
+ * an NTSC frame.
+ */
+ if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
+ return true;
+
+ return false;
+}
+
+int NTSC_framebuffer_init(char *base_address)
+{
+ const int NTSC_frames = 1;
+ const int NTSC_lines = 525;
+ char *dest = base_address;
+ int frame_num, line_num;
+
+ for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
+ for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
+ unsigned int code;
+ int offset = 0;
+ int i;
+
+ if (is_vblank_line(line_num))
+ offset++;
+
+ if (line_num > 266 || line_num < 3)
+ offset += 2;
+
+ /* Output EAV code */
+ code = system_code_map[offset].eav;
+ write_dest_byte((char)(code >> 24) & 0xff);
+ write_dest_byte((char)(code >> 16) & 0xff);
+ write_dest_byte((char)(code >> 8) & 0xff);
+ write_dest_byte((char)(code) & 0xff);
+
+ /* Output horizontal blanking */
+ for (i = 0; i < 67 * 2; ++i) {
+ write_dest_byte(0x80);
+ write_dest_byte(0x10);
+ }
+
+ /* Output SAV */
+ code = system_code_map[offset].sav;
+ write_dest_byte((char)(code >> 24) & 0xff);
+ write_dest_byte((char)(code >> 16) & 0xff);
+ write_dest_byte((char)(code >> 8) & 0xff);
+ write_dest_byte((char)(code) & 0xff);
+
+ /* Output empty horizontal data */
+ for (i = 0; i < 360 * 2; ++i) {
+ write_dest_byte(0x80);
+ write_dest_byte(0x10);
+ }
+ }
+ }
+
+ return dest - base_address;
+}
+
+void fill_frame(char *Frame, int Value)
+{
+ int *OddPtr32;
+ int OddLine;
+ int *EvenPtr32;
+ int EvenLine;
+ int i;
+ int *data;
+ int m, n;
+
+ /* fill odd and even frames */
+ for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
+ OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
+ EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
+ for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
+ *OddPtr32 = Value;
+ *EvenPtr32 = Value;
+ }
+ }
+
+ for (m = 0; m < VERTICAL; m++) {
+ data = (int *)u_boot_logo.data;
+ for (OddLine = (22 + m), EvenLine = (285 + m);
+ OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
+ OddLine += VERTICAL, EvenLine += VERTICAL) {
+ OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
+ EvenPtr32 =
+ (int *)((Frame + ((EvenLine) * 1716)) + 276);
+ for (i = 0; i < u_boot_logo.width / 2; i++) {
+ /* enlarge one pixel to m x n */
+ for (n = 0; n < HORIZONTAL; n++) {
+ *OddPtr32++ = *data;
+ *EvenPtr32++ = *data;
+ }
+ data++;
+ }
+ }
+ }
+}
+
+static void video_init(char *NTSCFrame)
+{
+ NTSC_framebuffer_init(NTSCFrame);
+ fill_frame(NTSCFrame, BLUE);
+
+ bfin_write_PPI_CONTROL(0x0082);
+ bfin_write_PPI_FRAME(0x020D);
+
+ bfin_write_DMA0_START_ADDR(NTSCFrame);
+ bfin_write_DMA0_X_COUNT(0x035A);
+ bfin_write_DMA0_X_MODIFY(0x0002);
+ bfin_write_DMA0_Y_COUNT(0x020D);
+ bfin_write_DMA0_Y_MODIFY(0x0002);
+ bfin_write_DMA0_CONFIG(0x1015);
+ bfin_write_PPI_CONTROL(0x0083);
+}
+
+void video_stop(void)
+{
+ bfin_write_PPI_CONTROL(0);
+ bfin_write_DMA0_CONFIG(0);
+}
+
+int drv_video_init(void)
+{
+ struct stdio_dev videodev;
+
+ video_init((void *)NTSC_FRAME_ADDR);
+
+ memset(&videodev, 0, sizeof(videodev));
+ strcpy(videodev.name, "video");
+ videodev.ext = DEV_EXT_VIDEO;
+ videodev.flags = DEV_FLAGS_SYSTEM;
+
+ return stdio_register(&videodev);
+}
diff --git a/board/bf533-stamp/video.h b/board/bf533-stamp/video.h
new file mode 100644
index 0000000..949c3d8
--- /dev/null
+++ b/board/bf533-stamp/video.h
@@ -0,0 +1,22 @@
+#include <video_logo.h>
+#define write_dest_byte(val) {*dest++=val;}
+#define BLACK (0x01800180) /* black pixel pattern */
+#define BLUE (0x296E29F0) /* blue pixel pattern */
+#define RED (0x51F0515A) /* red pixel pattern */
+#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */
+#define GREEN (0x91229136) /* green pixel pattern */
+#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
+#define YELLOW (0xD292D210) /* yellow pixel pattern */
+#define WHITE (0xFE80FE80) /* white pixel pattern */
+
+typedef struct {
+ unsigned int sav;
+ unsigned int eav;
+} system_code_type;
+
+const system_code_type system_code_map[] = {
+ { 0xFF000080, 0xFF00009D },
+ { 0xFF0000AB, 0xFF0000B6 },
+ { 0xFF0000C7, 0xFF0000DA },
+ { 0xFF0000EC, 0xFF0000F1 },
+};
diff --git a/board/bf537-minotaur/Kconfig b/board/bf537-minotaur/Kconfig
new file mode 100644
index 0000000..204f609
--- /dev/null
+++ b/board/bf537-minotaur/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF537_MINOTAUR
+
+config SYS_BOARD
+ default "bf537-minotaur"
+
+config SYS_CONFIG_NAME
+ default "bf537-minotaur"
+
+endif
diff --git a/board/bf537-minotaur/MAINTAINERS b/board/bf537-minotaur/MAINTAINERS
new file mode 100644
index 0000000..04643b1
--- /dev/null
+++ b/board/bf537-minotaur/MAINTAINERS
@@ -0,0 +1,6 @@
+BF537-MINOTAUR BOARD
+M: Martin Strubel <strubel@section5.ch>
+S: Maintained
+F: board/bf537-minotaur/
+F: include/configs/bf537-minotaur.h
+F: configs/bf537-minotaur_defconfig
diff --git a/board/bf537-minotaur/Makefile b/board/bf537-minotaur/Makefile
new file mode 100644
index 0000000..66d2f05
--- /dev/null
+++ b/board/bf537-minotaur/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf537-minotaur.o
diff --git a/board/bf537-minotaur/bf537-minotaur.c b/board/bf537-minotaur/bf537-minotaur.c
new file mode 100644
index 0000000..ca61ef9
--- /dev/null
+++ b/board/bf537-minotaur/bf537-minotaur.c
@@ -0,0 +1,48 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <net.h>
+#include <asm/blackfin.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: CSP BF537 Minotaur board\n");
+ printf(" Support: http://www.camsig.co.uk/\n");
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+ puts("Warning: Generating 'random' MAC address\n");
+ eth_random_addr(mac_addr);
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+ return 0;
+}
diff --git a/board/bf537-minotaur/config.mk b/board/bf537-minotaur/config.mk
new file mode 100644
index 0000000..7402f44
--- /dev/null
+++ b/board/bf537-minotaur/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/bf537-pnav/Kconfig b/board/bf537-pnav/Kconfig
new file mode 100644
index 0000000..acb1f89
--- /dev/null
+++ b/board/bf537-pnav/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF537_PNAV
+
+config SYS_BOARD
+ default "bf537-pnav"
+
+config SYS_CONFIG_NAME
+ default "bf537-pnav"
+
+endif
diff --git a/board/bf537-pnav/MAINTAINERS b/board/bf537-pnav/MAINTAINERS
new file mode 100644
index 0000000..b8b22a3
--- /dev/null
+++ b/board/bf537-pnav/MAINTAINERS
@@ -0,0 +1,6 @@
+BF537-PNAV BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf537-pnav/
+F: include/configs/bf537-pnav.h
+F: configs/bf537-pnav_defconfig
diff --git a/board/bf537-pnav/Makefile b/board/bf537-pnav/Makefile
new file mode 100644
index 0000000..ffcdf1f
--- /dev/null
+++ b/board/bf537-pnav/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf537-pnav.o
diff --git a/board/bf537-pnav/bf537-pnav.c b/board/bf537-pnav/bf537-pnav.c
new file mode 100644
index 0000000..df00110
--- /dev/null
+++ b/board/bf537-pnav/bf537-pnav.c
@@ -0,0 +1,48 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <net.h>
+#include <asm/blackfin.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF537 PNAV board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+ puts("Warning: Generating 'random' MAC address\n");
+ eth_random_addr(mac_addr);
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+ return 0;
+}
diff --git a/board/bf537-srv1/Kconfig b/board/bf537-srv1/Kconfig
new file mode 100644
index 0000000..2ddcd69
--- /dev/null
+++ b/board/bf537-srv1/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF537_SRV1
+
+config SYS_BOARD
+ default "bf537-srv1"
+
+config SYS_CONFIG_NAME
+ default "bf537-srv1"
+
+endif
diff --git a/board/bf537-srv1/MAINTAINERS b/board/bf537-srv1/MAINTAINERS
new file mode 100644
index 0000000..c8f1458
--- /dev/null
+++ b/board/bf537-srv1/MAINTAINERS
@@ -0,0 +1,6 @@
+BF537-SRV1 BOARD
+M: Martin Strubel <strubel@section5.ch>
+S: Maintained
+F: board/bf537-srv1/
+F: include/configs/bf537-srv1.h
+F: configs/bf537-srv1_defconfig
diff --git a/board/bf537-srv1/Makefile b/board/bf537-srv1/Makefile
new file mode 100644
index 0000000..cd0da27
--- /dev/null
+++ b/board/bf537-srv1/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf537-srv1.o
diff --git a/board/bf537-srv1/bf537-srv1.c b/board/bf537-srv1/bf537-srv1.c
new file mode 100644
index 0000000..725296a
--- /dev/null
+++ b/board/bf537-srv1/bf537-srv1.c
@@ -0,0 +1,48 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <net.h>
+#include <asm/blackfin.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Surveyor SRV1 board\n");
+ printf(" Support: http://www.surveyor.com/\n");
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+ puts("Warning: Generating 'random' MAC address\n");
+ eth_random_addr(mac_addr);
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+ return 0;
+}
diff --git a/board/bf537-srv1/config.mk b/board/bf537-srv1/config.mk
new file mode 100644
index 0000000..7402f44
--- /dev/null
+++ b/board/bf537-srv1/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/bf537-stamp/Kconfig b/board/bf537-stamp/Kconfig
new file mode 100644
index 0000000..4f86128
--- /dev/null
+++ b/board/bf537-stamp/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF537_STAMP
+
+config SYS_BOARD
+ default "bf537-stamp"
+
+config SYS_CONFIG_NAME
+ default "bf537-stamp"
+
+endif
diff --git a/board/bf537-stamp/MAINTAINERS b/board/bf537-stamp/MAINTAINERS
new file mode 100644
index 0000000..7d9c133
--- /dev/null
+++ b/board/bf537-stamp/MAINTAINERS
@@ -0,0 +1,6 @@
+BF537-STAMP BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf537-stamp/
+F: include/configs/bf537-stamp.h
+F: configs/bf537-stamp_defconfig
diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile
new file mode 100644
index 0000000..234119a
--- /dev/null
+++ b/board/bf537-stamp/Makefile
@@ -0,0 +1,14 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf537-stamp.o
+obj-$(CONFIG_BFIN_IDE) += ide-cf.o
+obj-$(CONFIG_HAS_POST) += post-memory.o
diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c
new file mode 100644
index 0000000..32045a9
--- /dev/null
+++ b/board/bf537-stamp/bf537-stamp.c
@@ -0,0 +1,82 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <net.h>
+#include <asm/mach-common/bits/bootrom.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF537 stamp board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+#ifdef CONFIG_SYS_NO_FLASH
+# define USE_MAC_IN_FLASH 0
+#else
+# define USE_MAC_IN_FLASH 1
+#endif
+ bool valid_mac = false;
+
+ if (USE_MAC_IN_FLASH) {
+ /* we cram the MAC in the last flash sector */
+ uchar *board_mac_addr = (uchar *)0x203F0000;
+ if (is_valid_ether_addr(board_mac_addr)) {
+ memcpy(mac_addr, board_mac_addr, 6);
+ valid_mac = true;
+ }
+ }
+
+ if (!valid_mac) {
+ puts("Warning: Generating 'random' MAC address\n");
+ eth_random_addr(mac_addr);
+ }
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+ /* we use the last sector for the MAC address / POST LDR */
+ extern flash_info_t flash_info[];
+ flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
+#endif
+
+#ifdef CONFIG_BFIN_IDE
+ cf_ide_init();
+#endif
+
+ return 0;
+}
diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk
new file mode 100644
index 0000000..ab0fbec
--- /dev/null
+++ b/board/bf537-stamp/config.mk
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/bf537-stamp/ide-cf.c b/board/bf537-stamp/ide-cf.c
new file mode 100644
index 0000000..5a3720d
--- /dev/null
+++ b/board/bf537-stamp/ide-cf.c
@@ -0,0 +1,66 @@
+/*
+ * CF IDE addon card code
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/blackfin.h>
+
+void cf_outb(unsigned char val, volatile unsigned char *addr)
+{
+ *(addr) = val;
+ SSYNC();
+}
+
+unsigned char cf_inb(volatile unsigned char *addr)
+{
+ volatile unsigned char c;
+
+ c = *(addr);
+ SSYNC();
+
+ return c;
+}
+
+void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
+{
+ int i;
+
+ for (i = 0; i < words; i++)
+ *(sect_buf + i) = *(addr);
+ SSYNC();
+}
+
+void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
+{
+ int i;
+
+ for (i = 0; i < words; i++)
+ *(addr) = *(sect_buf + i);
+ SSYNC();
+}
+
+void cf_ide_init(void)
+{
+#if defined(CONFIG_BFIN_TRUE_IDE)
+ /* Enable ATASEL when in True IDE mode */
+ printf("Using CF True IDE Mode\n");
+ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
+ udelay(1000);
+#elif defined(CONFIG_BFIN_CF_IDE)
+ /* Disable ATASEL when we're in Common Memory Mode */
+ printf("Using CF Common Memory Mode\n");
+ cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
+ udelay(1000);
+#elif defined(CONFIG_BFIN_HDD_IDE)
+ printf("Using HDD IDE Mode\n");
+#endif
+ ide_init();
+}
diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c
new file mode 100644
index 0000000..2dea92f
--- /dev/null
+++ b/board/bf537-stamp/post-memory.c
@@ -0,0 +1,257 @@
+#include <common.h>
+#include <asm/io.h>
+
+#include <post.h>
+#include <watchdog.h>
+
+#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+#define CLKIN 25000000
+#define PATTERN1 0x5A5A5A5A
+#define PATTERN2 0xAAAAAAAA
+
+#define CCLK_NUM 4
+#define SCLK_NUM 3
+
+void post_out_buff(char *buff);
+void post_init_pll(int mult, int div);
+int post_init_sdram(int sclk);
+void post_init_uart(int sclk);
+
+const int pll[CCLK_NUM][SCLK_NUM][2] = {
+ { {20, 4}, {20, 5}, {20, 10} }, /* CCLK = 500M */
+ { {16, 4}, {16, 5}, {16, 8} }, /* CCLK = 400M */
+ { {8, 2}, {8, 4}, {8, 5} }, /* CCLK = 200M */
+ { {4, 1}, {4, 2}, {4, 4} } /* CCLK = 100M */
+};
+const char *const log[CCLK_NUM][SCLK_NUM] = {
+ {"CCLK-500MHz SCLK-125MHz: Writing...\0",
+ "CCLK-500MHz SCLK-100MHz: Writing...\0",
+ "CCLK-500MHz SCLK- 50MHz: Writing...\0",},
+ {"CCLK-400MHz SCLK-100MHz: Writing...\0",
+ "CCLK-400MHz SCLK- 80MHz: Writing...\0",
+ "CCLK-400MHz SCLK- 50MHz: Writing...\0",},
+ {"CCLK-200MHz SCLK-100MHz: Writing...\0",
+ "CCLK-200MHz SCLK- 50MHz: Writing...\0",
+ "CCLK-200MHz SCLK- 40MHz: Writing...\0",},
+ {"CCLK-100MHz SCLK-100MHz: Writing...\0",
+ "CCLK-100MHz SCLK- 50MHz: Writing...\0",
+ "CCLK-100MHz SCLK- 25MHz: Writing...\0",},
+};
+
+int memory_post_test(int flags)
+{
+ int addr;
+ int m, n;
+ int sclk, sclk_temp;
+ int ret = 1;
+
+ sclk_temp = CLKIN / 1000000;
+ sclk_temp = sclk_temp * CONFIG_VCO_MULT;
+ for (sclk = 0; sclk_temp > 0; sclk++)
+ sclk_temp -= CONFIG_SCLK_DIV;
+ sclk = sclk * 1000000;
+ post_init_uart(sclk);
+ if (post_hotkeys_pressed() == 0)
+ return 0;
+
+ for (m = 0; m < CCLK_NUM; m++) {
+ for (n = 0; n < SCLK_NUM; n++) {
+ /* Calculate the sclk */
+ sclk_temp = CLKIN / 1000000;
+ sclk_temp = sclk_temp * pll[m][n][0];
+ for (sclk = 0; sclk_temp > 0; sclk++)
+ sclk_temp -= pll[m][n][1];
+ sclk = sclk * 1000000;
+
+ post_init_pll(pll[m][n][0], pll[m][n][1]);
+ post_init_sdram(sclk);
+ post_init_uart(sclk);
+ post_out_buff("\n\r\0");
+ post_out_buff(log[m][n]);
+ for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4)
+ *(unsigned long *)addr = PATTERN1;
+ post_out_buff("Reading...\0");
+ for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4) {
+ if ((*(unsigned long *)addr) != PATTERN1) {
+ post_out_buff("Error\n\r\0");
+ ret = 0;
+ }
+ }
+ post_out_buff("OK\n\r\0");
+ }
+ }
+ if (ret)
+ post_out_buff("memory POST passed\n\r\0");
+ else
+ post_out_buff("memory POST failed\n\r\0");
+
+ post_out_buff("\n\r\n\r\0");
+ return 1;
+}
+
+void post_init_uart(int sclk)
+{
+ int divisor;
+
+ for (divisor = 0; sclk > 0; divisor++)
+ sclk -= 57600 * 16;
+
+ bfin_write_PORTF_FER(0x000F);
+ bfin_write_PORTH_FER(0xFFFF);
+
+ bfin_write_UART_GCTL(0x00);
+ bfin_write_UART_LCR(0x83);
+ SSYNC();
+ bfin_write_UART_DLL(divisor & 0xFF);
+ SSYNC();
+ bfin_write_UART_DLH((divisor >> 8) & 0xFF);
+ SSYNC();
+ bfin_write_UART_LCR(0x03);
+ SSYNC();
+ bfin_write_UART_GCTL(0x01);
+ SSYNC();
+}
+
+void post_out_buff(char *buff)
+{
+
+ int i = 0;
+ for (i = 0; i < 0x80000; i++)
+ ;
+ i = 0;
+ while ((buff[i] != '\0') && (i != 100)) {
+ while (!(bfin_read_pUART_LSR() & 0x20)) ;
+ bfin_write_UART_THR(buff[i]);
+ SSYNC();
+ i++;
+ }
+ for (i = 0; i < 0x80000; i++)
+ ;
+}
+
+void post_init_pll(int mult, int div)
+{
+
+ bfin_write_SIC_IWR(0x01);
+ bfin_write_PLL_CTL((mult << 9));
+ bfin_write_PLL_DIV(div);
+ asm("CLI R2;");
+ asm("IDLE;");
+ asm("STI R2;");
+ while (!(bfin_read_PLL_STAT() & 0x20)) ;
+}
+
+int post_init_sdram(int sclk)
+{
+ int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num, SDRAM_tRCD,
+ SDRAM_tWR;
+ int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE, SDRAM_WIDTH,
+ mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
+
+ if ((sclk > 119402985)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_7;
+ SDRAM_tRAS_num = 7;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 104477612) && (sclk <= 119402985)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_6;
+ SDRAM_tRAS_num = 6;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 89552239) && (sclk <= 104477612)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_5;
+ SDRAM_tRAS_num = 5;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 74626866) && (sclk <= 89552239)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_4;
+ SDRAM_tRAS_num = 4;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 66666667) && (sclk <= 74626866)) {
+ SDRAM_tRP = TRP_2;
+ SDRAM_tRP_num = 2;
+ SDRAM_tRAS = TRAS_3;
+ SDRAM_tRAS_num = 3;
+ SDRAM_tRCD = TRCD_2;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 59701493) && (sclk <= 66666667)) {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_4;
+ SDRAM_tRAS_num = 4;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 44776119) && (sclk <= 59701493)) {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_3;
+ SDRAM_tRAS_num = 3;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ } else if ((sclk > 29850746) && (sclk <= 44776119)) {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_2;
+ SDRAM_tRAS_num = 2;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ } else if (sclk <= 29850746) {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_1;
+ SDRAM_tRAS_num = 1;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ } else {
+ SDRAM_tRP = TRP_1;
+ SDRAM_tRP_num = 1;
+ SDRAM_tRAS = TRAS_1;
+ SDRAM_tRAS_num = 1;
+ SDRAM_tRCD = TRCD_1;
+ SDRAM_tWR = TWR_2;
+ }
+ /*SDRAM INFORMATION: */
+ SDRAM_Tref = 64; /* Refresh period in milliseconds */
+ SDRAM_NRA = 4096; /* Number of row addresses in SDRAM */
+ SDRAM_CL = CL_3; /* 2 */
+
+ SDRAM_SIZE = EBSZ_64;
+ SDRAM_WIDTH = EBCAW_10;
+
+ mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
+
+ /* Equation from section 17 (p17-46) of BF533 HRM */
+ mem_SDRRC =
+ (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) -
+ (SDRAM_tRAS_num + SDRAM_tRP_num);
+
+ /* Enable SCLK Out */
+ mem_SDGCTL =
+ (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
+ | PSS);
+
+ SSYNC();
+
+ bfin_write_EBIU_SDGCTL(bfin_write_EBIU_SDGCTL() | 0x1000000);
+ /* Set the SDRAM Refresh Rate control register based on SSCLK value */
+ bfin_write_EBIU_SDRRC(mem_SDRRC);
+
+ /* SDRAM Memory Bank Control Register */
+ bfin_write_EBIU_SDBCTL(mem_SDBCTL);
+
+ /* SDRAM Memory Global Control Register */
+ bfin_write_EBIU_SDGCTL(mem_SDGCTL);
+ SSYNC();
+ return mem_SDRRC;
+}
+
+#endif /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
diff --git a/board/bf538f-ezkit/Kconfig b/board/bf538f-ezkit/Kconfig
new file mode 100644
index 0000000..e40fcdb
--- /dev/null
+++ b/board/bf538f-ezkit/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF538F_EZKIT
+
+config SYS_BOARD
+ default "bf538f-ezkit"
+
+config SYS_CONFIG_NAME
+ default "bf538f-ezkit"
+
+endif
diff --git a/board/bf538f-ezkit/MAINTAINERS b/board/bf538f-ezkit/MAINTAINERS
new file mode 100644
index 0000000..7964735
--- /dev/null
+++ b/board/bf538f-ezkit/MAINTAINERS
@@ -0,0 +1,6 @@
+BF538F-EZKIT BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf538f-ezkit/
+F: include/configs/bf538f-ezkit.h
+F: configs/bf538f-ezkit_defconfig
diff --git a/board/bf538f-ezkit/Makefile b/board/bf538f-ezkit/Makefile
new file mode 100644
index 0000000..7c8cda0
--- /dev/null
+++ b/board/bf538f-ezkit/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf538f-ezkit.o
diff --git a/board/bf538f-ezkit/bf538f-ezkit.c b/board/bf538f-ezkit/bf538f-ezkit.c
new file mode 100644
index 0000000..49d30e7
--- /dev/null
+++ b/board/bf538f-ezkit/bf538f-ezkit.c
@@ -0,0 +1,28 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF538F EZ-Kit Lite board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk
new file mode 100644
index 0000000..7f9138b
--- /dev/null
+++ b/board/bf538f-ezkit/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf548-ezkit/Kconfig b/board/bf548-ezkit/Kconfig
new file mode 100644
index 0000000..550227f
--- /dev/null
+++ b/board/bf548-ezkit/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF548_EZKIT
+
+config SYS_BOARD
+ default "bf548-ezkit"
+
+config SYS_CONFIG_NAME
+ default "bf548-ezkit"
+
+endif
diff --git a/board/bf548-ezkit/MAINTAINERS b/board/bf548-ezkit/MAINTAINERS
new file mode 100644
index 0000000..e2683bb
--- /dev/null
+++ b/board/bf548-ezkit/MAINTAINERS
@@ -0,0 +1,6 @@
+BF548-EZKIT BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf548-ezkit/
+F: include/configs/bf548-ezkit.h
+F: configs/bf548-ezkit_defconfig
diff --git a/board/bf548-ezkit/Makefile b/board/bf548-ezkit/Makefile
new file mode 100644
index 0000000..6f4200b
--- /dev/null
+++ b/board/bf548-ezkit/Makefile
@@ -0,0 +1,13 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf548-ezkit.o
+obj-$(CONFIG_VIDEO) += video.o
diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c
new file mode 100644
index 0000000..cb9ee86
--- /dev/null
+++ b/board/bf548-ezkit/bf548-ezkit.c
@@ -0,0 +1,64 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
+#include <asm/sdh.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF548 EZ-Kit board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /* Set async addr lines as peripheral */
+ const unsigned short pins[] = {
+ P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+ P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
+ P_A21, P_A22, P_A23, P_A24, 0
+ };
+ return peripheral_request_list(pins, "async");
+}
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
+
+#ifdef CONFIG_BFIN_SDH
+int board_mmc_init(bd_t *bis)
+{
+ return bfin_mmc_init(bis);
+}
+#endif
+
+#ifdef CONFIG_USB_BLACKFIN
+void board_musb_init(void)
+{
+ /*
+ * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both device
+ * and OTG host modes, while rev 1.1 and greater require PE7 to
+ * be low for device mode and high for host mode. We set it high
+ * here because we are in host mode.
+ */
+ gpio_request(GPIO_PE7, "musb-vbus");
+ gpio_direction_output(GPIO_PE7, 1);
+}
+#endif
diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk
new file mode 100644
index 0000000..7bb8e9c
--- /dev/null
+++ b/board/bf548-ezkit/config.mk
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
+LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1
+LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
+LDR_FLAGS-BFIN_BOOT_UART := --dma 1
+LDR_FLAGS-BFIN_BOOT_NAND := --dma 6
diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c
new file mode 100644
index 0000000..47e68c6
--- /dev/null
+++ b/board/bf548-ezkit/video.c
@@ -0,0 +1,337 @@
+/*
+ * video.c - run splash screen on lcd
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
+#include <asm/mach-common/bits/dma.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <stdio_dev.h>
+
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
+
+#define DMA_SIZE16 2
+
+#include <asm/mach-common/bits/eppi.h>
+
+#include EASYLOGO_HEADER
+
+#define LCD_X_RES 480 /*Horizontal Resolution */
+#define LCD_Y_RES 272 /* Vertical Resolution */
+
+#define LCD_BPP 24 /* Bit Per Pixel */
+#define LCD_PIXEL_SIZE (LCD_BPP / 8)
+#define DMA_BUS_SIZE 32
+#define ACTIVE_VIDEO_MEM_OFFSET 0
+
+/* -- Horizontal synchronizing --
+ *
+ * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
+ * (LCY-W-06602A Page 9 of 22)
+ *
+ * Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
+ *
+ * Period TH - 525 - Clock
+ * Pulse width THp - 41 - Clock
+ * Horizontal period THd - 480 - Clock
+ * Back porch THb - 2 - Clock
+ * Front porch THf - 2 - Clock
+ *
+ * -- Vertical synchronizing --
+ * Period TV - 286 - Line
+ * Pulse width TVp - 10 - Line
+ * Vertical period TVd - 272 - Line
+ * Back porch TVb - 2 - Line
+ * Front porch TVf - 2 - Line
+ */
+
+#define LCD_CLK (8*1000*1000) /* 8MHz */
+
+/* # active data to transfer after Horizontal Delay clock */
+#define EPPI_HCOUNT LCD_X_RES
+
+/* # active lines to transfer after Vertical Delay clock */
+#define EPPI_VCOUNT LCD_Y_RES
+
+/* Samples per Line = 480 (active data) + 45 (padding) */
+#define EPPI_LINE 525
+
+/* Lines per Frame = 272 (active data) + 14 (padding) */
+#define EPPI_FRAME 286
+
+/* FS1 (Hsync) Width (Typical)*/
+#define EPPI_FS1W_HBL 41
+
+/* FS1 (Hsync) Period (Typical) */
+#define EPPI_FS1P_AVPL EPPI_LINE
+
+/* Horizontal Delay clock after assertion of Hsync (Typical) */
+#define EPPI_HDELAY 43
+
+/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */
+#define EPPI_FS2W_LVB (EPPI_LINE * 10)
+
+ /* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */
+#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME)
+
+/* Vertical Delay after assertion of Vsync (2 Lines) */
+#define EPPI_VDELAY 12
+
+#define EPPI_CLIP 0xFF00FF00
+
+/* EPPI Control register configuration value for RGB out
+ * - EPPI as Output
+ * GP 2 frame sync mode,
+ * Internal Clock generation disabled, Internal FS generation enabled,
+ * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
+ * FS1 & FS2 are active high,
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
+ * Swapping Enabled,
+ * One (DMA) Channel Mode,
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ * Regular watermark - when FIFO is 100% full,
+ * Urgent watermark - when FIFO is 75% full
+ */
+
+#define EPPI_CONTROL (0x20136E2E)
+
+static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
+{
+ u32 sclk = get_sclk();
+
+ /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
+
+ return (((sclk / target_ppi_clk) / 2) - 1);
+}
+
+void Init_PPI(void)
+{
+ u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
+
+ bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
+ bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
+ bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
+ bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
+ bfin_write_EPPI0_CLIP(EPPI_CLIP);
+
+ bfin_write_EPPI0_FRAME(EPPI_FRAME);
+ bfin_write_EPPI0_LINE(EPPI_LINE);
+
+ bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
+ bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
+ bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
+ bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
+
+ bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
+
+/*
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ */
+#if defined(CONFIG_VIDEO_RGB666)
+ bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
+ RGB_FMT_EN);
+#else
+ bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
+ ~RGB_FMT_EN);
+#endif
+
+}
+
+#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
+
+void Init_DMA(void *dst)
+{
+
+#if defined(CONFIG_DEB_DMA_URGENT)
+ bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
+#endif
+
+ bfin_write_DMA12_START_ADDR(dst);
+
+ /* X count */
+ bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
+ bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
+
+ /* Y count */
+ bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
+ bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
+
+ /* DMA Config */
+ bfin_write_DMA12_CONFIG(
+ WDSIZE_32 | /* 32 bit DMA */
+ DMA2D | /* 2D DMA */
+ FLOW_AUTO /* autobuffer mode */
+ );
+}
+
+void Init_Ports(void)
+{
+ const unsigned short pins[] = {
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
+ P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
+ P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
+ P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
+#if !defined(CONFIG_VIDEO_RGB666)
+ P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
+ P_PPI0_D23,
+#endif
+ P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
+ };
+ peripheral_request_list(pins, "lcd");
+
+ gpio_request(GPIO_PE3, "lcd-disp");
+ gpio_direction_output(GPIO_PE3, 1);
+}
+
+void EnableDMA(void)
+{
+ bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
+}
+
+void DisableDMA(void)
+{
+ bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
+}
+
+/* enable and disable PPI functions */
+void EnablePPI(void)
+{
+ bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
+}
+
+void DisablePPI(void)
+{
+ bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
+}
+
+int video_init(void *dst)
+{
+ Init_Ports();
+ Init_DMA(dst);
+ EnableDMA();
+ Init_PPI();
+ EnablePPI();
+
+ return 0;
+}
+
+void video_stop(void)
+{
+ DisablePPI();
+ DisableDMA();
+}
+
+static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
+{
+ if (dcache_status())
+ blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
+
+ bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+
+ /* Setup destination start address */
+ bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
+ + (y * LCD_X_RES * LCD_PIXEL_SIZE));
+ /* Setup destination xcount */
+ bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+ /* Setup destination xmodify */
+ bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
+
+ /* Setup destination ycount */
+ bfin_write_MDMA_D0_Y_COUNT(logo->height);
+ /* Setup destination ymodify */
+ bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
+
+
+ /* Setup Source start address */
+ bfin_write_MDMA_S0_START_ADDR(logo->data);
+ /* Setup Source xcount */
+ bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+ /* Setup Source xmodify */
+ bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
+
+ /* Setup Source ycount */
+ bfin_write_MDMA_S0_Y_COUNT(logo->height);
+ /* Setup Source ymodify */
+ bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
+
+
+ /* Enable source DMA */
+ bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
+ SSYNC();
+ bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
+
+ while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
+
+ bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+ bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
+
+}
+
+int drv_video_init(void)
+{
+ int error, devices = 1;
+ struct stdio_dev videodev;
+
+ u8 *dst;
+ u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
+
+ dst = malloc(fbmem_size);
+
+ if (dst == NULL) {
+ printf("Failed to alloc FB memory\n");
+ return -1;
+ }
+
+#ifdef EASYLOGO_ENABLE_GZIP
+ unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+ unsigned long src_len = EASYLOGO_ENABLE_GZIP;
+ error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
+ bfin_logo.data = data;
+#elif defined(EASYLOGO_ENABLE_LZMA)
+ unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+ SizeT lzma_len = bfin_logo.size;
+ error = lzmaBuffToBuffDecompress(data, &lzma_len,
+ bfin_logo.data, EASYLOGO_ENABLE_LZMA);
+ bfin_logo.data = data;
+#else
+ error = 0;
+#endif
+
+ if (error) {
+ puts("Failed to decompress logo\n");
+ free(dst);
+ return -1;
+ }
+
+ memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
+
+ dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
+ (LCD_X_RES - bfin_logo.width) / 2,
+ (LCD_Y_RES - bfin_logo.height) / 2);
+
+ video_init(dst); /* Video initialization */
+
+ memset(&videodev, 0, sizeof(videodev));
+
+ strcpy(videodev.name, "video");
+ videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
+ videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
+
+ error = stdio_register(&videodev);
+
+ return (error == 0) ? devices : error;
+}
diff --git a/board/bf561-acvilon/Kconfig b/board/bf561-acvilon/Kconfig
new file mode 100644
index 0000000..ba1580d
--- /dev/null
+++ b/board/bf561-acvilon/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF561_ACVILON
+
+config SYS_BOARD
+ default "bf561-acvilon"
+
+config SYS_CONFIG_NAME
+ default "bf561-acvilon"
+
+endif
diff --git a/board/bf561-acvilon/MAINTAINERS b/board/bf561-acvilon/MAINTAINERS
new file mode 100644
index 0000000..056ee0b
--- /dev/null
+++ b/board/bf561-acvilon/MAINTAINERS
@@ -0,0 +1,6 @@
+BF561-ACVILON BOARD
+M: Valentin Yakovenkov <yakovenkov@niistt.ru>
+S: Maintained
+F: board/bf561-acvilon/
+F: include/configs/bf561-acvilon.h
+F: configs/bf561-acvilon_defconfig
diff --git a/board/bf561-acvilon/Makefile b/board/bf561-acvilon/Makefile
new file mode 100644
index 0000000..48bec28
--- /dev/null
+++ b/board/bf561-acvilon/Makefile
@@ -0,0 +1,14 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2009 CJSC "NII STT", Russia, Smolensk
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf561-acvilon.o
diff --git a/board/bf561-acvilon/bf561-acvilon.c b/board/bf561-acvilon/bf561-acvilon.c
new file mode 100644
index 0000000..da4c844
--- /dev/null
+++ b/board/bf561-acvilon/bf561-acvilon.c
@@ -0,0 +1,38 @@
+/*
+ * File: board/bf561-acvilon/bf561-acvilon.c
+ * Based on: board/bf561-ezkit/bf561-ezkit.c
+ * Author:
+ *
+ * Created: 2009-06-23
+ * Description: Acvilon System On Module board file
+ *
+ * Modified:
+ * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Bugs:
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: CJSC \"NII STT\"-=Acvilon Platform=- [U-Boot]\n");
+ printf(" Support: http://www.niistt.ru/\n");
+ return 0;
+}
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk
new file mode 100644
index 0000000..854d7db
--- /dev/null
+++ b/board/bf561-acvilon/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/bf561-ezkit/Kconfig b/board/bf561-ezkit/Kconfig
new file mode 100644
index 0000000..495a5c5
--- /dev/null
+++ b/board/bf561-ezkit/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF561_EZKIT
+
+config SYS_BOARD
+ default "bf561-ezkit"
+
+config SYS_CONFIG_NAME
+ default "bf561-ezkit"
+
+endif
diff --git a/board/bf561-ezkit/MAINTAINERS b/board/bf561-ezkit/MAINTAINERS
new file mode 100644
index 0000000..5ced3bb
--- /dev/null
+++ b/board/bf561-ezkit/MAINTAINERS
@@ -0,0 +1,6 @@
+BF561-EZKIT BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf561-ezkit/
+F: include/configs/bf561-ezkit.h
+F: configs/bf561-ezkit_defconfig
diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile
new file mode 100644
index 0000000..23c7101
--- /dev/null
+++ b/board/bf561-ezkit/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf561-ezkit.o
diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c
new file mode 100644
index 0000000..8441838
--- /dev/null
+++ b/board/bf561-ezkit/bf561-ezkit.c
@@ -0,0 +1,30 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: ADI BF561 EZ-Kit Lite board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk
new file mode 100644
index 0000000..854d7db
--- /dev/null
+++ b/board/bf561-ezkit/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/bf609-ezkit/Kconfig b/board/bf609-ezkit/Kconfig
new file mode 100644
index 0000000..7992e1e
--- /dev/null
+++ b/board/bf609-ezkit/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BF609_EZKIT
+
+config SYS_BOARD
+ default "bf609-ezkit"
+
+config SYS_CONFIG_NAME
+ default "bf609-ezkit"
+
+endif
diff --git a/board/bf609-ezkit/MAINTAINERS b/board/bf609-ezkit/MAINTAINERS
new file mode 100644
index 0000000..acfc6c7
--- /dev/null
+++ b/board/bf609-ezkit/MAINTAINERS
@@ -0,0 +1,6 @@
+BF609-EZKIT BOARD
+M: Sonic Zhang <sonic.adi@gmail.com>
+S: Maintained
+F: board/bf609-ezkit/
+F: include/configs/bf609-ezkit.h
+F: configs/bf609-ezkit_defconfig
diff --git a/board/bf609-ezkit/Makefile b/board/bf609-ezkit/Makefile
new file mode 100644
index 0000000..3bfd088
--- /dev/null
+++ b/board/bf609-ezkit/Makefile
@@ -0,0 +1,13 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := bf609-ezkit.o
+obj-$(CONFIG_BFIN_SOFT_SWITCH) += soft_switch.o
diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c
new file mode 100644
index 0000000..43a4330
--- /dev/null
+++ b/board/bf609-ezkit/bf609-ezkit.c
@@ -0,0 +1,68 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+#include <asm/sdh.h>
+#include <asm/portmux.h>
+#include "soft_switch.h"
+
+int checkboard(void)
+{
+ printf("Board: ADI BF609 EZ-Kit board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ static const unsigned short pins[] = {
+ P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+ P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
+ P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
+ };
+ peripheral_request_list(pins, "smc0");
+
+ return 0;
+}
+
+#ifdef CONFIG_DESIGNWARE_ETH
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+ if (CONFIG_DW_PORTS & 1) {
+ static const unsigned short pins[] = P_RMII0;
+ if (!peripheral_request_list(pins, "emac0"))
+ ret += designware_initialize(EMAC0_MACCFG, 0);
+ }
+ if (CONFIG_DW_PORTS & 2) {
+ static const unsigned short pins[] = P_RMII1;
+ if (!peripheral_request_list(pins, "emac1"))
+ ret += designware_initialize(EMAC1_MACCFG, 0);
+ }
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_BFIN_SDH
+int board_mmc_init(bd_t *bis)
+{
+ return bfin_mmc_init(bis);
+}
+#endif
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+ printf("other init\n");
+ return setup_board_switches();
+}
diff --git a/board/bf609-ezkit/soft_switch.c b/board/bf609-ezkit/soft_switch.c
new file mode 100644
index 0000000..e0c8d93
--- /dev/null
+++ b/board/bf609-ezkit/soft_switch.c
@@ -0,0 +1,171 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "soft_switch.h"
+
+struct switch_config {
+ uchar dir0; /* IODIRA */
+ uchar dir1; /* IODIRB */
+ uchar value0; /* OLATA */
+ uchar value1; /* OLATB */
+};
+
+static struct switch_config switch_config_array[NUM_SWITCH] = {
+ {
+/*
+ U45 Port A U45 Port B
+
+ 7--------------- RMII_CLK_EN | 7--------------- ~TEMP_THERM_EN
+ | 6------------- ~CNT0ZM_EN | | 6------------- ~TEMP_IRQ_EN
+ | | 5----------- ~CNT0DG_EN | | | 5----------- ~UART0CTS_146_EN
+ | | | 4--------- ~CNT0UD_EN | | | | 4--------- ~UART0CTS_RST_EN
+ | | | | 3------- ~CAN0RX_EN | | | | | 3------- ~UART0CTS_RTS_LPBK
+ | | | | | 2----- ~CAN0_ERR_EN | | | | | | 2----- ~UART0CTS_EN
+ | | | | | | 1--- ~CAN_STB | | | | | | | 1--- ~UART0RX_EN
+ | | | | | | | 0- CAN_EN | | | | | | | | 0- ~UART0RTS_EN
+ | | | | | | | | | | | | | | | | |
+ O O O O O O O O | O O O O O O O O (I/O direction)
+ 1 0 0 0 0 0 1 1 | 1 1 1 1 1 0 0 0 (value being set)
+*/
+ .dir0 = 0x0, /* all output */
+ .dir1 = 0x0, /* all output */
+ .value0 = RMII_CLK_EN | CAN_STB | CAN_EN,
+ .value1 = TEMP_THERM_EN | TEMP_IRQ_EN | UART0CTS_146_EN
+ | UART0CTS_RST_EN | UART0CTS_RTS_LPBK,
+ },
+ {
+/*
+ U46 Port A U46 Port B
+
+ 7--------------- ~LED4_GPIO_EN | 7--------------- EMPTY
+ | 6------------- ~LED3_GPIO_EN | | 6------------- ~SPI0D3_EN
+ | | 5----------- ~LED2_GPIO_EN | | | 5----------- ~SPI0D2_EN
+ | | | 4--------- ~LED1_GPIO_EN | | | | 4--------- ~SPIFLASH_CS_EN
+ | | | | 3------- SMC0_LP0_EN | | | | | 3------- ~SD_WP_EN
+ | | | | | 2----- EMPTY | | | | | | 2----- ~SD_CD_EN
+ | | | | | | 1--- SMC0_EPPI2 | | | | | | | 1--- ~PUSHBUTTON2_EN
+ _LP1_SWITCH
+ | | | | | | | 0- OVERRIDE_SMC0 | | | | | | | | 0- ~PUSHBUTTON1_EN
+ _LP0_BOOT
+ | | | | | | | | | | | | | | | | |
+ O O O O O O O O | O O O O O O O O (I/O direction)
+ 0 0 0 0 0 X 0 1 | X 0 0 0 0 0 0 0 (value being set)
+*/
+ .dir0 = 0x0, /* all output */
+ .dir1 = 0x0, /* all output */
+#ifdef CONFIG_BFIN_LINKPORT
+ .value0 = OVERRIDE_SMC0_LP0_BOOT,
+#else
+ .value0 = SMC0_EPPI2_LP1_SWITCH,
+#endif
+ .value1 = 0x0,
+ },
+ {
+/*
+ U47 Port A U47 Port B
+
+ 7--------------- ~PD2_SPI0MISO | 7--------------- EMPTY
+ _EI3_EN
+ | 6------------- ~PD1_SPI0D3 | | 6------------- EMPTY
+ _EPPI1D17
+ _SPI0SEL2
+ _EI3_EN
+ | | 5----------- ~PD0_SPI0D2 | | | 5----------- EMPTY
+ _EPPI1D16
+ _SPI0SEL3
+ _EI3_EN
+ | | | 4--------- ~WAKE_PUSH | | | | 4--------- EMPTY
+ BUTTON_EN
+ | | | | 3------- ~ETHERNET_EN | | | | | 3------- EMPTY
+ | | | | | 2----- PHYAD0 | | | | | | 2----- EMPTY
+ | | | | | | 1--- PHY_PWR | | | | | | | 1--- ~PD4_SPI0CK_EI3_EN
+ _DWN_INT
+ | | | | | | | 0- ~PHYINT_EN | | | | | | | | 0- ~PD3_SPI0MOSI_EI3_EN
+ | | | | | | | | | | | | | | | | |
+ O O O O O I I O | O O O O O O O O (I/O direction)
+ 1 1 1 0 0 0 0 0 | X X X X X X 1 1 (value being set)
+*/
+ .dir0 = 0x6, /* bits 1 and 2 input, all others output */
+ .dir1 = 0x0, /* all output */
+ .value0 = PD1_SPI0D3_EN | PD0_SPI0D2_EN,
+ .value1 = 0,
+ },
+};
+
+static int setup_soft_switch(int addr, struct switch_config *config)
+{
+ int ret = 0;
+
+ ret = i2c_write(addr, OLATA, 1, &config->value0, 1);
+ if (ret)
+ return ret;
+ ret = i2c_write(addr, OLATB, 1, &config->value1, 1);
+ if (ret)
+ return ret;
+
+ ret = i2c_write(addr, IODIRA, 1, &config->dir0, 1);
+ if (ret)
+ return ret;
+ return i2c_write(addr, IODIRB, 1, &config->dir1, 1);
+}
+
+int config_switch_bit(int addr, int port, int bit, int dir, uchar value)
+{
+ int ret, data_reg, dir_reg;
+ uchar tmp;
+
+ if (port == IO_PORT_A) {
+ data_reg = OLATA;
+ dir_reg = IODIRA;
+ } else {
+ data_reg = OLATB;
+ dir_reg = IODIRB;
+ }
+
+ if (dir == IO_PORT_INPUT) {
+ ret = i2c_read(addr, dir_reg, 1, &tmp, 1);
+ if (ret)
+ return ret;
+ tmp |= bit;
+ return i2c_write(addr, dir_reg, 1, &tmp, 1);
+ } else {
+ ret = i2c_read(addr, data_reg, 1, &tmp, 1);
+ if (ret)
+ return ret;
+ if (value)
+ tmp |= bit;
+ else
+ tmp &= ~bit;
+ ret = i2c_write(addr, data_reg, 1, &tmp, 1);
+ if (ret)
+ return ret;
+ ret = i2c_read(addr, dir_reg, 1, &tmp, 1);
+ if (ret)
+ return ret;
+ tmp &= ~bit;
+ return i2c_write(addr, dir_reg, 1, &tmp, 1);
+ }
+}
+
+int setup_board_switches(void)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < NUM_SWITCH; i++) {
+ ret = setup_soft_switch(SWITCH_ADDR + i,
+ &switch_config_array[i]);
+ if (ret)
+ return ret;
+ }
+ return 0;
+}
diff --git a/board/bf609-ezkit/soft_switch.h b/board/bf609-ezkit/soft_switch.h
new file mode 100644
index 0000000..d147fe1
--- /dev/null
+++ b/board/bf609-ezkit/soft_switch.h
@@ -0,0 +1,80 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BOARD_SOFT_SWITCH_H__
+#define __BOARD_SOFT_SWITCH_H__
+
+#include <asm/soft_switch.h>
+
+/* switch 0 port A */
+#define CAN_EN 0x1
+#define CAN_STB 0x2
+#define CAN0_ERR_EN 0x4
+#define CAN0RX_EN 0x8
+#define CNT0UD_EN 0x10
+#define CNT0DG_EN 0x20
+#define CNT0ZM_EN 0x40
+#define RMII_CLK_EN 0x80
+
+/* switch 0 port B */
+#define UART0RTS_EN 0x1
+#define UART0RX_EN 0x2
+#define UART0CTS_EN 0x4
+#define UART0CTS_RTS_LPBK 0x8
+#define UART0CTS_RST_EN 0x10
+#define UART0CTS_146_EN 0x20
+#define TEMP_IRQ_EN 0x40
+#define TEMP_THERM_EN 0x80
+
+/* switch 1 port A */
+#define OVERRIDE_SMC0_LP0_BOOT 0x1
+#define SMC0_EPPI2_LP1_SWITCH 0x2
+#define SMC0_LP0_EN 0x8
+#define LED1_GPIO_EN 0x10
+#define LED2_GPIO_EN 0x20
+#define LED3_GPIO_EN 0x40
+#define LED4_GPIO_EN 0x80
+
+/* switch 1 port B */
+#define PUSHBUTTON1_EN 0x1
+#define PUSHBUTTON2_EN 0x2
+#define SD_CD_EN 0x4
+#define SD_WP_EN 0x8
+#define SPIFLASH_CS_EN 0x10
+#define SPI0D2_EN 0x20
+#define SPI0D3_EN 0x40
+
+/* switch 2 port A */
+#define PHYINT_EN 0x1
+#define PHY_PWR_DWN_INT 0x2
+#define PHYAD0 0x4
+#define ETHERNET_EN 0x8
+#define WAKE_PUSHBUTTON_EN 0x10
+#define PD0_SPI0D2_EN 0x20
+#define PD1_SPI0D3_EN 0x40
+#define PD2_SPI0MISO_EN 0x80
+
+/* switch 2 port B */
+#define PD3_SPI0MOSI_EN 0x1
+#define PD4_SPI0CK_EN 0x2
+
+#ifdef CONFIG_BFIN_BOARD_VERSION_1_0
+#define SWITCH_ADDR 0x21
+#else
+#define SWITCH_ADDR 0x20
+#endif
+
+#define NUM_SWITCH 3
+#define IODIRA 0x0
+#define IODIRB 0x1
+#define OLATA 0x14
+#define OLATB 0x15
+
+int setup_board_switches(void);
+
+#endif /* __BOARD_SOFT_SWITCH_H__ */
diff --git a/board/blackstamp/Kconfig b/board/blackstamp/Kconfig
new file mode 100644
index 0000000..7ce086a
--- /dev/null
+++ b/board/blackstamp/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BLACKSTAMP
+
+config SYS_BOARD
+ default "blackstamp"
+
+config SYS_CONFIG_NAME
+ default "blackstamp"
+
+endif
diff --git a/board/blackstamp/MAINTAINERS b/board/blackstamp/MAINTAINERS
new file mode 100644
index 0000000..a0d72c6
--- /dev/null
+++ b/board/blackstamp/MAINTAINERS
@@ -0,0 +1,8 @@
+BLACKSTAMP BOARD
+M: Wojtek Skulski <skulski@pas.rochester.edu>
+M: Wojtek Skulski <info@skutek.com>
+M: Benjamin Matthews <mben12@gmail.com>
+S: Maintained
+F: board/blackstamp/
+F: include/configs/blackstamp.h
+F: configs/blackstamp_defconfig
diff --git a/board/blackstamp/Makefile b/board/blackstamp/Makefile
new file mode 100644
index 0000000..38e5da7
--- /dev/null
+++ b/board/blackstamp/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := blackstamp.o
diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c
new file mode 100644
index 0000000..06d004a
--- /dev/null
+++ b/board/blackstamp/blackstamp.c
@@ -0,0 +1,41 @@
+/*
+ * U-boot - blackstamp.c BlackStamp board specific routines
+ * Most code stolen from boards/bf533-stamp/bf533-stamp.c
+ * Edited to the BlackStamp by Ben Matthews for UR LLE
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: BlackStamp\n");
+ printf("Support: http://blackfin.uclinux.org/gf/project/blackstamp/\n");
+ return 0;
+}
+
+#ifdef SHARED_RESOURCES
+void swap_to(int device_id)
+{
+ gpio_request(GPIO_PF0, "eth_flash_swap");
+ gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
+ SSYNC();
+}
+#endif
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/board/blackvme/Kconfig b/board/blackvme/Kconfig
new file mode 100644
index 0000000..5e73f84
--- /dev/null
+++ b/board/blackvme/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BLACKVME
+
+config SYS_BOARD
+ default "blackvme"
+
+config SYS_CONFIG_NAME
+ default "blackvme"
+
+endif
diff --git a/board/blackvme/MAINTAINERS b/board/blackvme/MAINTAINERS
new file mode 100644
index 0000000..3f8b32c
--- /dev/null
+++ b/board/blackvme/MAINTAINERS
@@ -0,0 +1,8 @@
+BLACKVME BOARD
+M: Wojtek Skulski <skulski@pas.rochester.edu>
+M: Wojtek Skulski <info@skutek.com>
+M: Benjamin Matthews <mben12@gmail.com>
+S: Maintained
+F: board/blackvme/
+F: include/configs/blackvme.h
+F: configs/blackvme_defconfig
diff --git a/board/blackvme/Makefile b/board/blackvme/Makefile
new file mode 100644
index 0000000..4ff989a
--- /dev/null
+++ b/board/blackvme/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := blackvme.o
diff --git a/board/blackvme/blackvme.c b/board/blackvme/blackvme.c
new file mode 100644
index 0000000..eccdaf3
--- /dev/null
+++ b/board/blackvme/blackvme.c
@@ -0,0 +1,31 @@
+/* U-boot - blackvme.c board specific routines
+ * (c) Wojtek Skulski 2010 info@skutek.com
+ * Board info: http://www.skutek.com
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+int checkboard(void)
+{
+ printf("Board: BlackVME\n");
+ printf("Support: http://www.skutek.com/\n");
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_AX88180
+/*
+ * The ax88180 driver had to be patched to work around a bug
+ * in Marvell 88E1111 B2 silicon. E-mail me for explanations.
+ */
+int board_eth_init(bd_t *bis)
+{
+ return ax88180_initialize(bis);
+}
+#endif /* CONFIG_DRIVER_AX88180 */
diff --git a/board/bluegiga/apx4devkit/Kconfig b/board/bluegiga/apx4devkit/Kconfig
new file mode 100644
index 0000000..f327fa1
--- /dev/null
+++ b/board/bluegiga/apx4devkit/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_APX4DEVKIT
+
+config SYS_BOARD
+ default "apx4devkit"
+
+config SYS_VENDOR
+ default "bluegiga"
+
+config SYS_SOC
+ default "mxs"
+
+config SYS_CONFIG_NAME
+ default "apx4devkit"
+
+endif
diff --git a/board/bluegiga/apx4devkit/MAINTAINERS b/board/bluegiga/apx4devkit/MAINTAINERS
new file mode 100644
index 0000000..286e9e9
--- /dev/null
+++ b/board/bluegiga/apx4devkit/MAINTAINERS
@@ -0,0 +1,6 @@
+APX4DEVKIT BOARD
+M: Lauri Hintsala <lauri.hintsala@bluegiga.com>
+S: Maintained
+F: board/bluegiga/apx4devkit/
+F: include/configs/apx4devkit.h
+F: configs/apx4devkit_defconfig
diff --git a/board/bluegiga/apx4devkit/Makefile b/board/bluegiga/apx4devkit/Makefile
new file mode 100644
index 0000000..a7fcb63
--- /dev/null
+++ b/board/bluegiga/apx4devkit/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := apx4devkit.o
+else
+obj-y := spl_boot.o
+endif
diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c
new file mode 100644
index 0000000..08e79bd
--- /dev/null
+++ b/board/bluegiga/apx4devkit/apx4devkit.c
@@ -0,0 +1,139 @@
+/*
+ * Bluegiga APX4 Development Kit
+ *
+ * Copyright (C) 2012 Bluegiga Technologies Oy
+ *
+ * Authors:
+ * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
+ * Lauri Hintsala <lauri.hintsala@bluegiga.com>
+ *
+ * Based on m28evk.c:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Functions */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ return mxsmmc_initialize(bis, 0, NULL, NULL);
+}
+#endif
+
+
+#ifdef CONFIG_CMD_NET
+
+#define MII_PHY_CTRL2 0x1f
+int fecmxc_mii_postcall(int phy)
+{
+ /* change PHY RMII clock to 50MHz */
+ miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+ struct eth_device *dev;
+
+ ret = cpu_eth_init(bis);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC clocks\n");
+ return ret;
+ }
+
+ ret = fecmxc_initialize(bis);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC\n");
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC");
+ if (!dev) {
+ printf("FEC MXS: Unable to get FEC device entry\n");
+ return -EINVAL;
+ }
+
+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+ if (ret) {
+ printf("FEC MXS: Unable to register FEC MII postcall\n");
+ return ret;
+ }
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+#define MXS_OCOTP_MAX_TIMEOUT 1000000
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ struct mxs_ocotp_regs *ocotp_regs =
+ (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
+
+ serialnr->high = 0;
+ serialnr->low = 0;
+
+ writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
+
+ if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+ MXS_OCOTP_MAX_TIMEOUT)) {
+ printf("MXS: Can't get serial number from OCOTP\n");
+ return;
+ }
+
+ serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3);
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+ if (getenv("revision#") != NULL)
+ return simple_strtoul(getenv("revision#"), NULL, 10);
+ return 0;
+}
+#endif
diff --git a/board/bluegiga/apx4devkit/spl_boot.c b/board/bluegiga/apx4devkit/spl_boot.c
new file mode 100644
index 0000000..81419f9
--- /dev/null
+++ b/board/bluegiga/apx4devkit/spl_boot.c
@@ -0,0 +1,153 @@
+/*
+ * Bluegiga APX4 Development Kit
+ *
+ * Copyright (C) 2012 Bluegiga Technologies Oy
+ *
+ * Authors:
+ * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
+ * Lauri Hintsala <lauri.hintsala@bluegiga.com>
+ *
+ * Based on spl_boot.c:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* DUART */
+ MX28_PAD_PWM0__DUART_RX,
+ MX28_PAD_PWM1__DUART_TX,
+
+ /* LED */
+ MX28_PAD_PWM3__GPIO_3_28,
+
+ /* MMC0 */
+ MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL),
+ MX28_PAD_SSP0_SCK__SSP0_SCK |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
+ /* GPMI NAND */
+ MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+ MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+
+ /* FEC0 */
+ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+ /* EMI */
+ MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+};
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+
+ /* switch LED on */
+ gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+}
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ /*
+ * All address lines are routed from CPU to memory chip.
+ * ADDR_PINS field is set to zero.
+ */
+ dram_vals[0x74 >> 2] = 0x0f02000a;
+
+ /* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */
+ dram_vals[0x7c >> 2] = 0x00000101;
+}
diff --git a/board/bluewater/snapper9260/Kconfig b/board/bluewater/snapper9260/Kconfig
new file mode 100644
index 0000000..c896c46
--- /dev/null
+++ b/board/bluewater/snapper9260/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SNAPPER9260
+
+config SYS_BOARD
+ default "snapper9260"
+
+config SYS_VENDOR
+ default "bluewater"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "snapper9260"
+
+endif
diff --git a/board/bluewater/snapper9260/MAINTAINERS b/board/bluewater/snapper9260/MAINTAINERS
new file mode 100644
index 0000000..1f8f4d6
--- /dev/null
+++ b/board/bluewater/snapper9260/MAINTAINERS
@@ -0,0 +1,7 @@
+SNAPPER9260 BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/bluewater/snapper9260/
+F: include/configs/snapper9260.h
+F: configs/snapper9260_defconfig
+F: configs/snapper9g20_defconfig
diff --git a/board/bluewater/snapper9260/Makefile b/board/bluewater/snapper9260/Makefile
new file mode 100644
index 0000000..af7f0da
--- /dev/null
+++ b/board/bluewater/snapper9260/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2011 Bluewater Systems
+# Ryan Mallon <ryan@bluewatersys.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += snapper9260.o
diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c
new file mode 100644
index 0000000..95633b0
--- /dev/null
+++ b/board/bluewater/snapper9260/snapper9260.c
@@ -0,0 +1,156 @@
+/*
+ * Bluewater Systems Snapper 9260/9G20 modules
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ * Author: Andre Renaud <andre@bluewatersys.com>
+ * Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/atmel_serial.h>
+#include <net.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO Expander pins */
+#define IO_EXP_ETH_RESET (0 << 1)
+#define IO_EXP_ETH_POWER (1 << 1)
+
+static void macb_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+
+ /* Disable pull-ups to prevent PHY going into test mode */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA18),
+ &pioa->pudr);
+
+ /* Power down ethernet */
+ pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
+ pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
+
+ /* Hold ethernet in reset */
+ pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
+ pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
+
+ /* Enable ethernet power */
+ pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
+
+ at91_phy_reset();
+
+ /* Bring the ethernet out of reset */
+ pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
+
+ /* The phy internal reset take 21ms */
+ udelay(21 * 1000);
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA18),
+ &pioa->puer);
+
+ at91_macb_hw_init();
+}
+
+static void nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Enable CS3 as NAND/SmartMedia */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+
+ /* Configure RDY/BSY */
+ gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
+ gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+ /* Enable NandFlash */
+ gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
+ gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+int board_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable PIO clocks */
+ writel((1 << ATMEL_ID_PIOA) |
+ (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOC), &pmc->pcer);
+
+ /* The mach-type is the same for both Snapper 9260 and 9G20 */
+ gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ /* Initialise peripherals */
+ at91_seriald_hw_init();
+ i2c_set_bus_num(0);
+ nand_hw_init();
+ macb_hw_init();
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+void reset_phy(void)
+{
+}
+
+static struct atmel_serial_platdata at91sam9260_serial_plat = {
+ .base_addr = ATMEL_BASE_DBGU,
+};
+
+U_BOOT_DEVICE(at91sam9260_serial) = {
+ .name = "serial_atmel",
+ .platdata = &at91sam9260_serial_plat,
+};
diff --git a/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
new file mode 100644
index 0000000..6c68146
--- /dev/null
+++ b/board/boundary/nitrogen6x/1066mhz_4x128mx16.cfg
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7974
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42720306
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026F0266
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4273030A
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02740240
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45393B3E
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x403A3747
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40434541
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x473E4A3B
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0011000E
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x000E001B
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00190015
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00070018
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
new file mode 100644
index 0000000..1096f77
--- /dev/null
+++ b/board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42740304
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026e0265
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x02750306
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02720244
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x463d4041
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c47
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x37414441
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4633473b
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0025001f
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00290027
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f002b
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000f0029
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/boundary/nitrogen6x/6x_bootscript.txt b/board/boundary/nitrogen6x/6x_bootscript.txt
new file mode 100644
index 0000000..061b3a4
--- /dev/null
+++ b/board/boundary/nitrogen6x/6x_bootscript.txt
@@ -0,0 +1,63 @@
+setenv bootargs enable_wait_mode=off
+setenv nextcon 0;
+
+if hdmidet ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
+ setenv fbmem "fbmem=28M";
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no HDMI monitor";
+fi
+
+i2c dev 2
+if i2c probe 0x04 ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
+ if test "0" -eq $nextcon; then
+ setenv fbmem "fbmem=10M";
+ else
+ setenv fbmem ${fbmem},10M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no Freescale display";
+fi
+
+if i2c probe 0x38 ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
+ if test "0" -eq $nextcon; then
+ setenv fbmem "fbmem=10M";
+ else
+ setenv fbmem ${fbmem},10M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no 1024x600 display";
+fi
+
+if i2c probe 0x48 ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666
+ if test "0" -eq $nextcon; then
+ setenv fbmem "fbmem=10M";
+ else
+ setenv fbmem ${fbmem},10M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no 800x480 display";
+fi
+
+while test "3" -ne $nextcon ; do
+ setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
+ setexpr nextcon $nextcon + 1 ;
+done
+
+setenv bootargs $bootargs $fbmem
+setenv bootargs "$bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 rootwait"
+
+if test "sata" = "${dtype}" ; then
+ setenv bootargs "$bootargs root=/dev/sda1" ;
+else
+ setenv "bootargs $bootargs root=/dev/mmcblk0p1" ;
+fi
+${fs}load ${dtype} ${disk}:1 10800000 /boot/uImage && bootm 10800000 ;
+echo "Error loading kernel image"
diff --git a/board/boundary/nitrogen6x/6x_bootscript_android.txt b/board/boundary/nitrogen6x/6x_bootscript_android.txt
new file mode 100644
index 0000000..0982cf8
--- /dev/null
+++ b/board/boundary/nitrogen6x/6x_bootscript_android.txt
@@ -0,0 +1,64 @@
+${dtype} dev ${disk}
+
+setenv bootargs enable_wait_mode=off
+setenv nextcon 0;
+setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ;
+
+i2c dev 2
+
+if i2c probe 0x04 ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
+ if test "0" -eq $nextcon; then
+ setenv fbcon "fbcon=10M";
+ else
+ setenv fbcon ${fbcon},10M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no Freescale display";
+fi
+
+if i2c probe 0x38 ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
+ if test "0" -eq $nextcon; then
+ setenv fbcon "fbcon=10M";
+ else
+ setenv fbcon ${fbcon},10M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no 1024x600 display";
+fi
+
+if i2c probe 0x48 ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration
+ if test "0" -eq $nextcon; then
+ setenv fbcon "fbcon=10M";
+ else
+ setenv fbcon ${fbcon},10M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no 800x480 display";
+fi
+
+if hdmidet ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
+ if test "0" -eq $nextcon; then
+ setenv fbcon "fbcon=28M";
+ else
+ setenv fbcon ${fbcon},28M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no HDMI monitor";
+fi
+
+while test "3" -ne $nextcon ; do
+ setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
+ setexpr nextcon $nextcon + 1 ;
+done
+
+setenv bootargs $bootargs fbcon=$fbcon
+${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000
+echo "Error loading kernel image"
diff --git a/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt
new file mode 100644
index 0000000..0982cf8
--- /dev/null
+++ b/board/boundary/nitrogen6x/6x_bootscript_android_recovery.txt
@@ -0,0 +1,64 @@
+${dtype} dev ${disk}
+
+setenv bootargs enable_wait_mode=off
+setenv nextcon 0;
+setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ;
+
+i2c dev 2
+
+if i2c probe 0x04 ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
+ if test "0" -eq $nextcon; then
+ setenv fbcon "fbcon=10M";
+ else
+ setenv fbcon ${fbcon},10M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no Freescale display";
+fi
+
+if i2c probe 0x38 ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
+ if test "0" -eq $nextcon; then
+ setenv fbcon "fbcon=10M";
+ else
+ setenv fbcon ${fbcon},10M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no 1024x600 display";
+fi
+
+if i2c probe 0x48 ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration
+ if test "0" -eq $nextcon; then
+ setenv fbcon "fbcon=10M";
+ else
+ setenv fbcon ${fbcon},10M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no 800x480 display";
+fi
+
+if hdmidet ; then
+ setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
+ if test "0" -eq $nextcon; then
+ setenv fbcon "fbcon=28M";
+ else
+ setenv fbcon ${fbcon},28M
+ fi
+ setexpr nextcon $nextcon + 1
+else
+ echo "------ no HDMI monitor";
+fi
+
+while test "3" -ne $nextcon ; do
+ setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
+ setexpr nextcon $nextcon + 1 ;
+done
+
+setenv bootargs $bootargs fbcon=$fbcon
+${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000
+echo "Error loading kernel image"
diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt
new file mode 100644
index 0000000..1a62bbf
--- /dev/null
+++ b/board/boundary/nitrogen6x/6x_upgrade.txt
@@ -0,0 +1,45 @@
+setenv stdout serial,vga
+echo "check U-Boot" ;
+setenv offset 0x400
+if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then
+ echo "read $filesize bytes from SD card" ;
+ if sf probe || sf probe || \
+ sf probe 1 27000000 || sf probe 1 27000000 ; then
+ echo "probed SPI ROM" ;
+ if sf read 0x12400000 $offset $filesize ; then
+ if cmp.b 0x12000000 0x12400000 $filesize ; then
+ echo "------- U-Boot versions match" ;
+ else
+ echo "Need U-Boot upgrade" ;
+ echo "Program in 5 seconds" ;
+ for n in 5 4 3 2 1 ; do
+ echo $n ;
+ sleep 1 ;
+ done
+ echo "erasing" ;
+ sf erase 0 0xC0000 ;
+ # two steps to prevent bricking
+ echo "programming" ;
+ sf write 0x12000000 $offset $filesize ;
+ echo "verifying" ;
+ if sf read 0x12400000 $offset $filesize ; then
+ if cmp.b 0x12000000 0x12400000 $filesize ; then
+ while echo "---- U-Boot upgraded. reset" ; do
+ sleep 120
+ done
+ else
+ echo "Read verification error" ;
+ fi
+ else
+ echo "Error re-reading EEPROM" ;
+ fi
+ fi
+ else
+ echo "Error reading boot loader from EEPROM" ;
+ fi
+ else
+ echo "Error initializing EEPROM" ;
+ fi ;
+else
+ echo "No U-Boot image found on SD card" ;
+fi
diff --git a/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg
new file mode 100644
index 0000000..e005a64
--- /dev/null
+++ b/board/boundary/nitrogen6x/800mhz_2x128mx16.cfg
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg
new file mode 100644
index 0000000..581d44c
--- /dev/null
+++ b/board/boundary/nitrogen6x/800mhz_2x256mx16.cfg
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg
new file mode 100644
index 0000000..1069342
--- /dev/null
+++ b/board/boundary/nitrogen6x/800mhz_4x128mx16.cfg
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420F020F
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01760175
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x41640171
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015E0160
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45464B4A
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x49484A46
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40402E32
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3A3A3231
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x003A003A
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0030002F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x002F0038
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00270039
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg
new file mode 100644
index 0000000..7c7a3d1
--- /dev/null
+++ b/board/boundary/nitrogen6x/800mhz_4x256mx16.cfg
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/boundary/nitrogen6x/Kconfig b/board/boundary/nitrogen6x/Kconfig
new file mode 100644
index 0000000..03b0f6f
--- /dev/null
+++ b/board/boundary/nitrogen6x/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_NITROGEN6X
+
+config SYS_BOARD
+ default "nitrogen6x"
+
+config SYS_VENDOR
+ default "boundary"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "nitrogen6x"
+
+endif
diff --git a/board/boundary/nitrogen6x/MAINTAINERS b/board/boundary/nitrogen6x/MAINTAINERS
new file mode 100644
index 0000000..cb06c03
--- /dev/null
+++ b/board/boundary/nitrogen6x/MAINTAINERS
@@ -0,0 +1,12 @@
+NITROGEN6X BOARD
+M: Eric Nelson <eric.nelson@boundarydevices.com>
+S: Maintained
+F: board/boundary/nitrogen6x/
+F: include/configs/nitrogen6x.h
+F: configs/mx6qsabrelite_defconfig
+F: configs/nitrogen6dl_defconfig
+F: configs/nitrogen6dl2g_defconfig
+F: configs/nitrogen6q_defconfig
+F: configs/nitrogen6q2g_defconfig
+F: configs/nitrogen6s_defconfig
+F: configs/nitrogen6s1g_defconfig
diff --git a/board/boundary/nitrogen6x/Makefile b/board/boundary/nitrogen6x/Makefile
new file mode 100644
index 0000000..f875d68
--- /dev/null
+++ b/board/boundary/nitrogen6x/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
+# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nitrogen6x.o
diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README
new file mode 100644
index 0000000..9d84265
--- /dev/null
+++ b/board/boundary/nitrogen6x/README
@@ -0,0 +1,92 @@
+U-Boot for the Boundary Devices Nitrogen6X and
+Freescale i.MX6Q SabreLite boards
+
+This file contains information for the port of
+U-Boot to the Boundary Devices Nitrogen6X and
+Freescale i.MX6Q SabreLite boards.
+
+1. Boot source, boot from SPI NOR
+---------------------------------
+The configuration in this directory supports both the
+Nitrogen6X and Freescale SabreLite board, but in a
+different fashion from Freescale's implementation in
+board/freescale/mx6qsabrelite.
+
+In particular, this image supports booting from SPI NOR
+and saving the environment to SPI NOR.
+
+It does not support 'boot from SD' at offset 0x400
+except through the 'bmode' command.
+ http://lists.denx.de/pipermail/u-boot/2012-August/131151.html
+
+2. Boots using 6x_bootscript on SATA or SD card
+-----------------------------------------------
+The default bootcmd for these boards is configured
+to look for and source a boot script named '6x_bootscript'
+in the root of the first partition of the following
+devices:
+
+ sata 0
+ mmc 0
+ mmc 1
+
+They're searched in the order listed above, trying both the
+ext2 and fat filesystems.
+
+2. Maintaining the SPI NOR
+--------------------------
+A couple of convenience commands
+
+ clearenv - clear environment to factory default
+ upgradeu - look and source a boot script named
+ '6x_upgrade' to upgrade the U-Boot version
+ in SPI NOR. The search is the same as for
+ 6x_bootscript described above.
+
+3. Display support
+------------------
+U-Boot support for the following displays is configured by
+default:
+
+ HDMI - 1024 x 768 for maximum compatibility
+ Hannstar-XGA - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1)
+ wsvga-lvds - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600)
+ wvga-rgb - 800 x 480 RGB (Boundary p/n Nit6X_800x480)
+
+Since the ipuv3_fb display driver currently supports only a single display,
+this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect
+or the I2C touch controller of the LVDS and RGB displays in the priority
+listed above.
+
+Setting 'panel' environment variable to one of the names above will
+override auto-detection and force activation of the specified panel.
+
+4. Building
+------------
+
+To build U-Boot for one of the Nitrogen6x or SabreLite board:
+
+ make nitrogen6x_config
+ make
+
+Note that 'nitrogen6x' is a placeholder. The complete list of supported
+board configurations is shown in the boards.cfg file:
+ nitrogen6q i.MX6Q/6D 1GB
+ nitrogen6dl i.MX6DL 1GB
+ nitrogen6s i.MX6S 512MB
+ nitrogen6q2g i.MX6Q/6D 2GB
+ nitrogen6dl2g i.MX6DL 2GB
+ nitrogen6s1g i.MX6S 1GB
+
+The -6q variants support either the i.MX6Quad or i.MX6Dual processors
+and are configured for a 64-bit memory bus at 1066 MHz.
+
+The -6dl variants also use a 64-bit memory bus, operated at 800MHz.
+
+The -6s variants use a 32-bit memory bus at 800MHz.
+
+If you place the u-boot.imx into a single-partition SD card
+along with a binary version of the boot script 6x_upgrade.txt,
+you can program it using 'upgradeu':
+
+ U-Boot> run upgradeu
diff --git a/board/boundary/nitrogen6x/README.mx6qsabrelite b/board/boundary/nitrogen6x/README.mx6qsabrelite
new file mode 100644
index 0000000..12a9c85
--- /dev/null
+++ b/board/boundary/nitrogen6x/README.mx6qsabrelite
@@ -0,0 +1,72 @@
+U-Boot for the Freescale i.MX6q SabreLite board
+
+This file contains information for the port of U-Boot to the Freescale
+i.MX6q SabreLite board.
+
+1. Boot source, boot from SD card
+---------------------------------
+
+The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports
+boot from SD card only. However, by default, the SabreLite
+boards boot from the SPI NOR flash. These boards need to be reflashed with
+a small SD card loader to support boot from SD card. This small SD card loader
+will be flashed into the SPI NOR. The board will still boot from SPI NOR, but
+the loader will in turn request the BootROM to load the U-Boot from SD card.
+
+The SD card loader is available from
+
+https://wiki.linaro.org/Boards/MX6QSabreLite
+
+under a open-source 3-clause BSD license.
+
+To update the SPI-NOR on the SabreLite board without the Freescale
+manufacturing tool use the following procedure:
+
+1. Write this SD card loader onto a large SD card using:
+
+ sudo dd if=iMX6DQ_SPI_to_uSDHC3.bin of=/dev/sXx
+
+Note: Replace sXx with the device representing the SD card in your system.
+
+Note: This writes SD card loader at address 0
+
+2. Put this SD card into the slot for the large SD card (SD3 on the bottom of
+the board). Make sure SW1 switch is at position "00", so that it can boot
+from the fuses.
+
+3. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot
+(the default one the board is shipped with, starting from the SPI NOR) and
+enter the following commands:
+
+ MX6Q SABRELITE U-Boot > mmc dev 0
+ MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200
+ MX6Q SABRELITE U-Boot > sf probe
+ MX6Q SABRELITE U-Boot > sf erase 0 0x40000
+ MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000
+
+4. done.
+
+In case you somehow do not succeed with this procedure you will have to use
+the Freescale manufacturing tool in order to reflash the SPI-NOR.
+
+Note: The board now boots from full size SD3 on the bottom of the board. NOT
+ the micro SD4/BOOT slot on the top of the board. I.e. you have to use
+ full size SD cards.
+
+This information is taken from
+
+https://wiki.linaro.org/Boards/MX6QSabreLite
+
+2. Build
+--------
+
+To build U-Boot for the SabreLite board:
+
+ make mx6qsabrelite_config
+ make
+
+To copy the resulting u-boot.imx to the SD card:
+
+ sudo dd if=u-boot.imx of=/dev/sXx bs=512 seek=2&&sudo sync
+
+Note: Replace sXx with the device representing the SD card in your system.
diff --git a/board/boundary/nitrogen6x/clocks.cfg b/board/boundary/nitrogen6x/clocks.cfg
new file mode 100644
index 0000000..8bddb91
--- /dev/null
+++ b/board/boundary/nitrogen6x/clocks.cfg
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/boundary/nitrogen6x/ddr-setup.cfg b/board/boundary/nitrogen6x/ddr-setup.cfg
new file mode 100644
index 0000000..2748d40
--- /dev/null
+++ b/board/boundary/nitrogen6x/ddr-setup.cfg
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6DL ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 32 bits x16/x32
+ */
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/*
+ * MDMISC mirroring interleaved (row/bank/col)
+ */
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
+
+/*
+ * MDSCR con_req
+ */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg
new file mode 100644
index 0000000..1cdccad
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "800mhz_4x128mx16.cfg"
+#include "clocks.cfg"
diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
new file mode 100644
index 0000000..516d67e
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "800mhz_4x256mx16.cfg"
+#include "clocks.cfg"
diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg
new file mode 100644
index 0000000..b6642e6
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6q.cfg
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "1066mhz_4x128mx16.cfg"
+#include "clocks.cfg"
diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
new file mode 100644
index 0000000..fe6dfc1
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "1066mhz_4x256mx16.cfg"
+#include "clocks.cfg"
diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg
new file mode 100644
index 0000000..ca30cd6
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6s.cfg
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "800mhz_2x128mx16.cfg"
+#include "clocks.cfg"
diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
new file mode 100644
index 0000000..b1489fb
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "800mhz_2x256mx16.cfg"
+#include "clocks.cfg"
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
new file mode 100644
index 0000000..e8ea256
--- /dev/null
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -0,0 +1,1022 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/sata.h>
+#include <asm/imx-common/spi.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <i2c.h>
+#include <input.h>
+#include <netdev.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_SRE_SLOW)
+
+#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+
+#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
+
+int dram_init(void)
+{
+ gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C1, SGTL5000 */
+static struct i2c_pads_info i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+
+/* I2C2 Camera, MIPI */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+/* I2C3, J15 - RGB connector */
+static struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
+ .gp = IMX_GPIO_NR(1, 5)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
+ .gp = IMX_GPIO_NR(7, 11)
+ }
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t const enet_pads1[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* pin 35 - 1 (PHY_AD2) on reset */
+ MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 32 - 1 - (MODE0) all */
+ MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 31 - 1 - (MODE1) all */
+ MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 28 - 1 - (MODE2) all */
+ MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 27 - 1 - (MODE3) all */
+ MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+ MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 42 PHY nRST */
+ MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads2[] = {
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const misc_pads[] = {
+ MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
+ MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* OTG Power enable */
+ MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
+};
+
+/* wl1271 pads on nitrogen6x */
+static iomux_v3_cfg_t const wl12xx_pads[] = {
+ (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
+ | MUX_PAD_CTRL(WEAK_PULLDOWN),
+ (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
+ | MUX_PAD_CTRL(OUTPUT_40OHM),
+ (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
+ | MUX_PAD_CTRL(OUTPUT_40OHM),
+};
+#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
+#define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
+#define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
+
+/* Button assignments for J14 */
+static iomux_v3_cfg_t const button_pads[] = {
+ /* Menu */
+ MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Back */
+ MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Labelled Search (mapped to Power under Android) */
+ MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Home */
+ MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Volume Down */
+ MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+ /* Volume Up */
+ MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
+ gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
+ gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+ imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+ gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+
+ /* Need delay 10ms according to KSZ9021 spec */
+ udelay(1000 * 10);
+ gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
+ gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
+
+ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+ udelay(100); /* Wait 100 us before using mii interface */
+}
+
+static iomux_v3_cfg_t const usb_pads[] = {
+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+
+ /* Reset USB hub */
+ gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
+ mdelay(2);
+ gpio_set_value(IMX_GPIO_NR(7, 12), 1);
+
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ if (port)
+ return 0;
+ gpio_set_value(GP_USB_OTG_PWR, on);
+ return 0;
+}
+
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
+ IMX_GPIO_NR(2, 6);
+
+ gpio_direction_input(gp_cd);
+ return !gpio_get_value(gp_cd);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ u32 index = 0;
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+ usdhc_cfg[0].max_bus_width = 4;
+ usdhc_cfg[1].max_bus_width = 4;
+
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
+}
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+ /* SS1 */
+ MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+ ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* min rx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
+ /* min tx data delay */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
+ /* max rx/tx clock delay, min rx/tx control */
+ ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ uint32_t base = IMX_FEC_BASE;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret;
+
+ setup_iomux_enet();
+
+#ifdef CONFIG_FEC_MXC
+ bus = fec_get_miibus(base, -1);
+ if (!bus)
+ return 0;
+ /* scan phy 4,5,6,7 */
+ phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
+ if (!phydev) {
+ free(bus);
+ return 0;
+ }
+ printf("using phy at %d\n", phydev->addr);
+ ret = fec_probe(bis, -1, base, bus, phydev);
+ if (ret) {
+ printf("FEC MXC: %s:failed\n", __func__);
+ free(phydev);
+ free(bus);
+ }
+#endif
+
+#ifdef CONFIG_CI_UDC
+ /* For otg ethernet*/
+ usb_eth_initialize(bis);
+#endif
+ return 0;
+}
+
+static void setup_buttons(void)
+{
+ imx_iomux_v3_setup_multiple_pads(button_pads,
+ ARRAY_SIZE(button_pads));
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+ /* Backlight on RGB connector: J15 */
+ MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
+
+ /* Backlight on LVDS connector: J6 */
+ MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
+};
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
+ MX6_PAD_DI0_PIN4__GPIO4_IO20,
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+ return ((0 == i2c_set_bus_num(dev->bus))
+ &&
+ (0 == i2c_probe(dev->addr)));
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)
+ IOMUXC_BASE_ADDR;
+ u32 reg = readl(&iomux->gpr[2]);
+ reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+ writel(reg, &iomux->gpr[2]);
+ gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+}
+
+static void enable_lvds_jeida(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)
+ IOMUXC_BASE_ADDR;
+ u32 reg = readl(&iomux->gpr[2]);
+ reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+ |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
+ writel(reg, &iomux->gpr[2]);
+ gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+}
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(
+ rgb_pads,
+ ARRAY_SIZE(rgb_pads));
+ gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+}
+
+struct display_info_t const displays[] = {{
+ .bus = 1,
+ .addr = 0x50,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_i2c,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 0,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_lvds_jeida,
+ .mode = {
+ .name = "LDB-WXGA",
+ .refresh = 60,
+ .xres = 1280,
+ .yres = 800,
+ .pixclock = 14065,
+ .left_margin = 40,
+ .right_margin = 40,
+ .upper_margin = 3,
+ .lower_margin = 80,
+ .hsync_len = 10,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 0,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "LDB-WXGA-S",
+ .refresh = 60,
+ .xres = 1280,
+ .yres = 800,
+ .pixclock = 14065,
+ .left_margin = 40,
+ .right_margin = 40,
+ .upper_margin = 3,
+ .lower_margin = 80,
+ .hsync_len = 10,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 2,
+ .addr = 0x4,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .detect = detect_i2c,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "Hannstar-XGA",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 0,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .detect = NULL,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "LG-9.7",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385, /* ~65MHz */
+ .left_margin = 480,
+ .right_margin = 260,
+ .upper_margin = 16,
+ .lower_margin = 6,
+ .hsync_len = 250,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 2,
+ .addr = 0x38,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .detect = detect_i2c,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "wsvga-lvds",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 600,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 2,
+ .addr = 0x10,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = detect_i2c,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "fusion7",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 33898,
+ .left_margin = 96,
+ .right_margin = 24,
+ .upper_margin = 3,
+ .lower_margin = 10,
+ .hsync_len = 72,
+ .vsync_len = 7,
+ .sync = 0x40000002,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 0,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = NULL,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "svga",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 600,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 2,
+ .addr = 0x41,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .detect = detect_i2c,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "amp1024x600",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 600,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 0,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .detect = 0,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "wvga-lvds",
+ .refresh = 57,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 2,
+ .addr = 0x48,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = detect_i2c,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "wvga-rgb",
+ .refresh = 57,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 37037,
+ .left_margin = 40,
+ .right_margin = 60,
+ .upper_margin = 10,
+ .lower_margin = 10,
+ .hsync_len = 20,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 0,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "qvga",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = 37037,
+ .left_margin = 38,
+ .right_margin = 37,
+ .upper_margin = 16,
+ .lower_margin = 15,
+ .hsync_len = 30,
+ .vsync_len = 3,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+int board_cfb_skip(void)
+{
+ return NULL != getenv("novideo");
+}
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+ /* Turn on LDB0,IPU,IPU DI0 clocks */
+ reg = __raw_readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+ |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+ |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+ |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+ |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+ |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+ |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+ |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+ |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+ |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+
+ /* backlights off until needed */
+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+ gpio_direction_input(LVDS_BACKLIGHT_GP);
+ gpio_direction_input(RGB_BACKLIGHT_GP);
+}
+#endif
+
+static iomux_v3_cfg_t const init_pads[] = {
+ /* SGTL5000 sys_mclk */
+ NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
+
+ /* J5 - Camera MCLK */
+ NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
+
+ /* wl1271 pads on nitrogen6x */
+ /* WL12XX_WL_IRQ_GP */
+ NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
+ /* WL12XX_WL_ENABLE_GP */
+ NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
+ /* WL12XX_BT_ENABLE_GP */
+ NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
+ /* USB otg power */
+ NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
+ NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
+ NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
+ NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
+ NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
+};
+
+#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
+
+static unsigned gpios_out_low[] = {
+ /* Disable wl1271 */
+ IMX_GPIO_NR(6, 15), /* disable wireless */
+ IMX_GPIO_NR(6, 16), /* disable bluetooth */
+ IMX_GPIO_NR(3, 22), /* disable USB otg power */
+ IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */
+ IMX_GPIO_NR(1, 8), /* ov5642 reset */
+};
+
+static unsigned gpios_out_high[] = {
+ IMX_GPIO_NR(1, 6), /* ov5642 powerdown */
+ IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */
+};
+
+static void set_gpios(unsigned *p, int cnt, int val)
+{
+ int i;
+
+ for (i = 0; i < cnt; i++)
+ gpio_direction_output(*p++, val);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
+ set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
+ gpio_direction_input(WL12XX_WL_IRQ_GP);
+
+ imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
+ imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
+ setup_buttons();
+
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
+ return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_init(void)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ clrsetbits_le32(&iomuxc_regs->gpr[1],
+ IOMUXC_GPR1_OTG_ID_MASK,
+ IOMUXC_GPR1_OTG_ID_GPIO1);
+
+ imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_MXC_SPI
+ setup_spi();
+#endif
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ if (gpio_get_value(WL12XX_WL_IRQ_GP))
+ puts("Board: Nitrogen6X\n");
+ else
+ puts("Board: SABRE Lite\n");
+
+ return 0;
+}
+
+struct button_key {
+ char const *name;
+ unsigned gpnum;
+ char ident;
+};
+
+static struct button_key const buttons[] = {
+ {"back", IMX_GPIO_NR(2, 2), 'B'},
+ {"home", IMX_GPIO_NR(2, 4), 'H'},
+ {"menu", IMX_GPIO_NR(2, 1), 'M'},
+ {"search", IMX_GPIO_NR(2, 3), 'S'},
+ {"volup", IMX_GPIO_NR(7, 13), 'V'},
+ {"voldown", IMX_GPIO_NR(4, 5), 'v'},
+};
+
+/*
+ * generate a null-terminated string containing the buttons pressed
+ * returns number of keys pressed
+ */
+static int read_keys(char *buf)
+{
+ int i, numpressed = 0;
+ for (i = 0; i < ARRAY_SIZE(buttons); i++) {
+ if (!gpio_get_value(buttons[i].gpnum))
+ buf[numpressed++] = buttons[i].ident;
+ }
+ buf[numpressed] = '\0';
+ return numpressed;
+}
+
+static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char envvalue[ARRAY_SIZE(buttons)+1];
+ int numpressed = read_keys(envvalue);
+ setenv("keybd", envvalue);
+ return numpressed == 0;
+}
+
+U_BOOT_CMD(
+ kbd, 1, 1, do_kbd,
+ "Tests for keypresses, sets 'keybd' environment variable",
+ "Returns 0 (true) to shell if key is pressed."
+);
+
+#ifdef CONFIG_PREBOOT
+static char const kbd_magic_prefix[] = "key_magic";
+static char const kbd_command_prefix[] = "key_cmd";
+
+static void preboot_keys(void)
+{
+ int numpressed;
+ char keypress[ARRAY_SIZE(buttons)+1];
+ numpressed = read_keys(keypress);
+ if (numpressed) {
+ char *kbd_magic_keys = getenv("magic_keys");
+ char *suffix;
+ /*
+ * loop over all magic keys
+ */
+ for (suffix = kbd_magic_keys; *suffix; ++suffix) {
+ char *keys;
+ char magic[sizeof(kbd_magic_prefix) + 1];
+ sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
+ keys = getenv(magic);
+ if (keys) {
+ if (!strcmp(keys, keypress))
+ break;
+ }
+ }
+ if (*suffix) {
+ char cmd_name[sizeof(kbd_command_prefix) + 1];
+ char *cmd;
+ sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
+ cmd = getenv(cmd_name);
+ if (cmd) {
+ setenv("preboot", cmd);
+ return;
+ }
+ }
+ }
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_PREBOOT
+ preboot_keys();
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ return 0;
+}
diff --git a/board/br4/Kconfig b/board/br4/Kconfig
new file mode 100644
index 0000000..a10a060
--- /dev/null
+++ b/board/br4/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_BR4
+
+config SYS_BOARD
+ default "br4"
+
+config SYS_CONFIG_NAME
+ default "br4"
+
+endif
diff --git a/board/br4/MAINTAINERS b/board/br4/MAINTAINERS
new file mode 100644
index 0000000..4085da5
--- /dev/null
+++ b/board/br4/MAINTAINERS
@@ -0,0 +1,6 @@
+BR4 BOARD
+M: Dimitar Penev <dpn@switchfin.org>
+S: Maintained
+F: board/br4/
+F: include/configs/br4.h
+F: configs/br4_defconfig
diff --git a/board/br4/Makefile b/board/br4/Makefile
new file mode 100644
index 0000000..68e24ab
--- /dev/null
+++ b/board/br4/Makefile
@@ -0,0 +1,14 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) Switchfin Org. <dpn@switchfin.org>
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := br4.o
diff --git a/board/br4/br4.c b/board/br4/br4.c
new file mode 100644
index 0000000..bc034e3
--- /dev/null
+++ b/board/br4/br4.c
@@ -0,0 +1,30 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) Switchfin Org. <dpn@switchfin.org>
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+
+int checkboard(void)
+{
+ printf("Board: Switchvoice BR4 Appliance\n");
+ printf(" Support: http://www.switchvoice.com/\n");
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
diff --git a/board/broadcom/bcm11130/MAINTAINERS b/board/broadcom/bcm11130/MAINTAINERS
new file mode 100644
index 0000000..b22e86f
--- /dev/null
+++ b/board/broadcom/bcm11130/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM11130 BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcm28155_ap/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm11130_defconfig
diff --git a/board/broadcom/bcm11130_nand/MAINTAINERS b/board/broadcom/bcm11130_nand/MAINTAINERS
new file mode 100644
index 0000000..881db5b
--- /dev/null
+++ b/board/broadcom/bcm11130_nand/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM11130_NAND BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcm28155_ap/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm11130_nand_defconfig
diff --git a/board/broadcom/bcm28155_ap/Kconfig b/board/broadcom/bcm28155_ap/Kconfig
new file mode 100644
index 0000000..f1b4e08
--- /dev/null
+++ b/board/broadcom/bcm28155_ap/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BCM28155_AP
+
+config SYS_BOARD
+ default "bcm28155_ap"
+
+config SYS_VENDOR
+ default "broadcom"
+
+config SYS_SOC
+ default "bcm281xx"
+
+config SYS_CONFIG_NAME
+ default "bcm28155_ap"
+
+endif
diff --git a/board/broadcom/bcm28155_ap/MAINTAINERS b/board/broadcom/bcm28155_ap/MAINTAINERS
new file mode 100644
index 0000000..a74c394
--- /dev/null
+++ b/board/broadcom/bcm28155_ap/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM28155_AP BOARD
+M: Tim Kryger <tim.kryger@linaro.org>
+S: Maintained
+F: board/broadcom/bcm28155_ap/
+F: include/configs/bcm28155_ap.h
+F: configs/bcm28155_ap_defconfig
diff --git a/board/broadcom/bcm28155_ap/Makefile b/board/broadcom/bcm28155_ap/Makefile
new file mode 100644
index 0000000..4bb9e70
--- /dev/null
+++ b/board/broadcom/bcm28155_ap/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += bcm28155_ap.o
diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c
new file mode 100644
index 0000000..940a1c2
--- /dev/null
+++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <mmc.h>
+#include <asm/kona-common/kona_sdhci.h>
+#include <asm/kona-common/clk.h>
+#include <asm/arch/sysmap.h>
+
+#define SECWATCHDOG_SDOGCR_OFFSET 0x00000000
+#define SECWATCHDOG_SDOGCR_EN_SHIFT 27
+#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26
+#define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20
+#define SECWATCHDOG_SDOGCR_LD_SHIFT 0
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * board_init - early hardware init
+ */
+int board_init(void)
+{
+ printf("Relocation Offset is: %08lx\n", gd->reloc_off);
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ clk_init();
+
+ return 0;
+}
+
+/*
+ * misc_init_r - miscellaneous platform dependent initializations
+ */
+int misc_init_r(void)
+{
+ /* Disable watchdog reset - watchdog unused */
+ writel((0 << SECWATCHDOG_SDOGCR_EN_SHIFT) |
+ (0 << SECWATCHDOG_SDOGCR_SRSTEN_SHIFT) |
+ (4 << SECWATCHDOG_SDOGCR_CLKS_SHIFT) |
+ (0x5a0 << SECWATCHDOG_SDOGCR_LD_SHIFT),
+ (SECWD_BASE_ADDR + SECWATCHDOG_SDOGCR_OFFSET));
+
+ return 0;
+}
+
+/*
+ * dram_init - sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+/* This is called after dram_init() so use get_ram_size result */
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+#ifdef CONFIG_KONA_SDHCI
+/*
+ * mmc_init - Initializes mmc
+ */
+int board_mmc_init(bd_t *bis)
+{
+ int ret = 0;
+
+ /* Register eMMC - SDIO2 */
+ ret = kona_sdhci_init(1, 400000, 0);
+ if (ret)
+ return ret;
+
+ /* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */
+ ret = kona_sdhci_init(3, 400000, 0);
+ return ret;
+}
+#endif
diff --git a/board/broadcom/bcm28155_w1d/MAINTAINERS b/board/broadcom/bcm28155_w1d/MAINTAINERS
new file mode 100644
index 0000000..a436490
--- /dev/null
+++ b/board/broadcom/bcm28155_w1d/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM28155_W1D BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcm28155_ap/
+F: include/configs/bcm28155_ap.h
+F: configs/bcm28155_w1d_defconfig
diff --git a/board/broadcom/bcm911360_entphn-ns/MAINTAINERS b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS
new file mode 100644
index 0000000..b5f0207
--- /dev/null
+++ b/board/broadcom/bcm911360_entphn-ns/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM911360_ENTPHN-NS BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm911360_entphn-ns_defconfig
diff --git a/board/broadcom/bcm911360_entphn/MAINTAINERS b/board/broadcom/bcm911360_entphn/MAINTAINERS
new file mode 100644
index 0000000..fb7ee2b
--- /dev/null
+++ b/board/broadcom/bcm911360_entphn/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM911360_ENTPHN BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm911360_entphn_defconfig
diff --git a/board/broadcom/bcm911360k/MAINTAINERS b/board/broadcom/bcm911360k/MAINTAINERS
new file mode 100644
index 0000000..754a15f
--- /dev/null
+++ b/board/broadcom/bcm911360k/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM911360K BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm911360k_defconfig
diff --git a/board/broadcom/bcm958300k-ns/MAINTAINERS b/board/broadcom/bcm958300k-ns/MAINTAINERS
new file mode 100644
index 0000000..763401a
--- /dev/null
+++ b/board/broadcom/bcm958300k-ns/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM958300K-NS BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm958300k-ns_defconfig
diff --git a/board/broadcom/bcm958300k/MAINTAINERS b/board/broadcom/bcm958300k/MAINTAINERS
new file mode 100644
index 0000000..8afc728
--- /dev/null
+++ b/board/broadcom/bcm958300k/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM958300K BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm958300k_defconfig
diff --git a/board/broadcom/bcm958305k/MAINTAINERS b/board/broadcom/bcm958305k/MAINTAINERS
new file mode 100644
index 0000000..179fd4e
--- /dev/null
+++ b/board/broadcom/bcm958305k/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM958305K BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmcygnus/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm958305k_defconfig
diff --git a/board/broadcom/bcm958622hr/MAINTAINERS b/board/broadcom/bcm958622hr/MAINTAINERS
new file mode 100644
index 0000000..d08aded
--- /dev/null
+++ b/board/broadcom/bcm958622hr/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM958622HR BOARD
+M: Steve Rae <srae@broadcom.com>
+S: Maintained
+F: board/broadcom/bcmnsp/
+F: include/configs/bcm_ep_board.h
+F: configs/bcm958622hr_defconfig
diff --git a/board/broadcom/bcm_ep/Makefile b/board/broadcom/bcm_ep/Makefile
new file mode 100644
index 0000000..8914e54
--- /dev/null
+++ b/board/broadcom/bcm_ep/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2014 Broadcom Corporation.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o
diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c
new file mode 100644
index 0000000..6a70a2e
--- /dev/null
+++ b/board/broadcom/bcm_ep/board.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <config.h>
+#include <asm/system.h>
+#include <asm/iproc-common/armpll.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * board_init - early hardware init
+ */
+int board_init(void)
+{
+ /*
+ * Address of boot parameters passed to kernel
+ * Use default offset 0x100
+ */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+/*
+ * dram_init - sets u-boot's idea of sdram size
+ */
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+int board_early_init_f(void)
+{
+ uint32_t status = 0;
+
+ /* Setup PLL if required */
+#if defined(CONFIG_ARMCLK)
+ armpll_config(CONFIG_ARMCLK);
+#endif
+
+ return status;
+}
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+}
+
+void smp_kick_all_cpus(void)
+{
+}
+
+void smp_waitloop(unsigned previous_address)
+{
+}
+#endif
diff --git a/board/broadcom/bcmcygnus/Kconfig b/board/broadcom/bcmcygnus/Kconfig
new file mode 100644
index 0000000..faba4cf
--- /dev/null
+++ b/board/broadcom/bcmcygnus/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BCMCYGNUS
+
+config SYS_BOARD
+ default "bcm_ep"
+
+config SYS_VENDOR
+ default "broadcom"
+
+config SYS_SOC
+ default "bcmcygnus"
+
+config SYS_CONFIG_NAME
+ default "bcm_ep_board"
+
+endif
diff --git a/board/broadcom/bcmnsp/Kconfig b/board/broadcom/bcmnsp/Kconfig
new file mode 100644
index 0000000..a975082
--- /dev/null
+++ b/board/broadcom/bcmnsp/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BCMNSP
+
+config SYS_BOARD
+ default "bcm_ep"
+
+config SYS_VENDOR
+ default "broadcom"
+
+config SYS_SOC
+ default "bcmnsp"
+
+config SYS_CONFIG_NAME
+ default "bcm_ep_board"
+
+endif
diff --git a/board/buffalo/lsxl/Kconfig b/board/buffalo/lsxl/Kconfig
new file mode 100644
index 0000000..ef78896
--- /dev/null
+++ b/board/buffalo/lsxl/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_LSXL
+
+config SYS_BOARD
+ default "lsxl"
+
+config SYS_VENDOR
+ default "buffalo"
+
+config SYS_CONFIG_NAME
+ default "lsxl"
+
+endif
diff --git a/board/buffalo/lsxl/MAINTAINERS b/board/buffalo/lsxl/MAINTAINERS
new file mode 100644
index 0000000..facc2dd
--- /dev/null
+++ b/board/buffalo/lsxl/MAINTAINERS
@@ -0,0 +1,7 @@
+LSXL BOARD
+M: Michael Walle <michael@walle.cc>
+S: Maintained
+F: board/buffalo/lsxl/
+F: include/configs/lsxl.h
+F: configs/lschlv2_defconfig
+F: configs/lsxhl_defconfig
diff --git a/board/buffalo/lsxl/Makefile b/board/buffalo/lsxl/Makefile
new file mode 100644
index 0000000..1b01b40
--- /dev/null
+++ b/board/buffalo/lsxl/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2012 Michael Walle
+# Michael Walle <michael@walle.cc>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := lsxl.o
diff --git a/board/buffalo/lsxl/kwbimage-lschl.cfg b/board/buffalo/lsxl/kwbimage-lschl.cfg
new file mode 100644
index 0000000..5fc122f
--- /dev/null
+++ b/board/buffalo/lsxl/kwbimage-lschl.cfg
@@ -0,0 +1,213 @@
+#
+# Copyright (c) 2012 Michael Walle
+# Michael Walle <michael@walle.cc>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100E0 0x1B1B1B9B
+
+# L2 RAM Timing 0
+DATA 0xFFD20134 0xBBBBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# L2 RAM Timing 1
+DATA 0xFFD20138 0x00BBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# DDR Configuration register
+DATA 0xFFD01400 0x43000618
+# bit13-0: 0x618, 1560 DDR2 clks refresh rate
+# bit23-14: 0 required
+# bit24: 1, enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: 0 required
+# bit31-30: 0b01 required
+
+# DDR Controller Control Low
+DATA 0xFFD01404 0x39543000
+# bit3-0: 0 required
+# bit4: 0, addr/cmd in same cycle
+# bit5: 0, clk is driven during self refresh, we don't care for APX
+# bit6: 0, use recommended falling edge of clk for addr/cmd
+# bit11-7: 0 required
+# bit12: 1 required
+# bit13: 1 required
+# bit14: 0, input buffer always powered up
+# bit17-15: 0 required
+# bit18: 1, cpu lock transaction enabled
+# bit19: 0 required
+# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0, no additional STARTBURST delay
+
+# DDR Timing (Low)
+DATA 0xFFD01408 0x3302444F
+# bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0])
+# bit7-4: 4, 5 cycle tRCD
+# bit11-8: 4, 5 cyle tRP
+# bit15-12: 4, 5 cyle tWR
+# bit19-16: 2, 3 cyle tWTR
+# bit20: 0, 16 cycle tRAS (tRAS[4])
+# bit23-21: 0 required
+# bit27-24: 3, 4 cycle tRRD
+# bit31-28: 3, 4 cyle tRTP
+
+# DDR Timing (High)
+DATA 0xFFD0140C 0x00000823
+# bit6-0: 0x23, 35 cycle tRFC
+# bit8-7: 0, 1 cycle tR2R
+# bit10-9: 0, 1 cyle tR2W
+# bit12-11: 1, 2 cylce tW2W
+# bit31-13: 0 required
+
+# DDR Address Control
+DATA 0xFFD01410 0x00000009
+# bit1-0: 1, Cs0width=x16
+# bit3-2: 2, Cs0size=512Mbit
+# bit5-4: 0, Cs1width=nonexistent
+# bit7-6: 0, Cs1size=nonexistent
+# bit9-8: 0, Cs2width=nonexistent
+# bit11-10: 0, Cs2size=nonexistent
+# bit13-12: 0, Cs3width=nonexistent
+# bit15-14: 0, Cs3size=nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+# DDR Open Pages Control
+DATA 0xFFD01414 0x00000000
+# bit0: 0, OPEn=OpenPage enabled
+# bit31-1: 0 required
+
+# DDR Operation
+DATA 0xFFD01418 0x00000000
+# bit3-0: 0, Cmd=Normal SDRAM Mode
+# bit31-4: 0 required
+
+# DDR Mode
+DATA 0xFFD0141C 0x00000652
+# bit2-0: 2, Burst Length (2 required)
+# bit3: 0, Burst Type (0 required)
+# bit6-4: 5, CAS Latency (CL) 5
+# bit7: 0, (Test Mode) Normal operation
+# bit8: 0, (Reset DLL) Normal operation
+# bit11-9: 3, Write recovery for auto-precharge (3 required)
+# bit12: 0, Fast Active power down exit time (0 required)
+# bit31-13: 0 required
+
+# DDR Extended Mode
+DATA 0xFFD01420 0x00000042
+# bit0: 0, DRAM DLL enabled
+# bit1: 1, DRAM drive strength reduced
+# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
+# bit5-3: 0 required
+# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
+# bit9-7: 0 required
+# bit10: 0, differential DQS enabled
+# bit11: 0 required
+# bit12: 0, DRAM output buffer enabled
+# bit31-13: 0 required
+
+# DDR Controller Control High
+DATA 0xFFD01424 0x0000F17F
+# bit2-0: 0x7 required
+# bit3: 1, MBUS Burst Chop disabled
+# bit6-4: 0x7 required
+# bit7: 0 required (???)
+# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9: 0, no half clock cycle addition to dataout
+# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11: 0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf required
+# bit31-16: 0 required
+
+# DDR2 ODT Read Timing (default values)
+DATA 0xFFD01428 0x00085520
+# bit3-0: 0 required
+# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
+# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
+# bit31-20: 0 required
+
+# DDR2 ODT Write Timing (default values)
+DATA 0xFFD0147C 0x00008552
+# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
+# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
+# bit31-16: 0 required
+
+# CS[0]n Base address
+DATA 0xFFD01500 0x00000000
+# at 0x0
+
+# CS[0]n Size
+DATA 0xFFD01504 0x03FFFFF1
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 0x0, CS0 hit selected
+# bit23-4: 0xfffff required
+# bit31-24: 0x03, Size (i.e. 64MB)
+
+# CS[1]n Size
+DATA 0xFFD0150C 0x00000000
+# window disabled
+
+# CS[2]n Size
+DATA 0xFFD01514 0x00000000
+# window disabled
+
+# CS[3]n Size
+DATA 0xFFD0151C 0x00000000
+# window disabled
+
+# DDR ODT Control (Low)
+DATA 0xFFD01494 0x003C0000
+# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
+# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
+# bit15-8: 0 required
+# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
+# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
+# bit31-24: 0 required
+
+# DDR ODT Control (High)
+DATA 0xFFD01498 0x00000000
+# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
+# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
+# bit31-4 0 required
+
+# CPU ODT Control
+DATA 0xFFD0149C 0x0000E80F
+# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
+# bit9-8: 0, Internal ODT assertion is controlled by fiels
+# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
+# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
+# bit14: 1, M_STARTBURST_IN ODT enabled
+# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
+# bit20-16: 0, Pad N channel driving strength for ODT
+# bit25-21: 0, Pad P channel driving strength for ODT
+# bit31-26: 0 required
+
+# DDR Initialization Control
+DATA 0xFFD01480 0x00000001
+# bit0: 1, enable DDR init upon this register write
+# bit31-1: 0, required
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/buffalo/lsxl/kwbimage-lsxhl.cfg b/board/buffalo/lsxl/kwbimage-lsxhl.cfg
new file mode 100644
index 0000000..80e2c02
--- /dev/null
+++ b/board/buffalo/lsxl/kwbimage-lsxhl.cfg
@@ -0,0 +1,213 @@
+#
+# Copyright (c) 2012 Michael Walle
+# Michael Walle <michael@walle.cc>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100E0 0x1B1B9B9B
+
+# L2 RAM Timing 0
+DATA 0xFFD20134 0xBBBBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# L2 RAM Timing 1
+DATA 0xFFD20138 0x00BBBBBB
+# not further specified in HW manual, timing taken from original vendor port
+
+# DDR Configuration register
+DATA 0xFFD01400 0x43000618
+# bit13-0: 0x618, 1560 DDR2 clks refresh rate
+# bit23-14: 0 required
+# bit24: 1, enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: 0 required
+# bit31-30: 0b01 required
+
+# DDR Controller Control Low
+DATA 0xFFD01404 0x39543010
+# bit3-0: 0 required
+# bit4: 1, T2 mode, addr/cmd are driven for two cycles
+# bit5: 0, clk is driven during self refresh, we don't care for APX
+# bit6: 0, use recommended falling edge of clk for addr/cmd
+# bit11-7: 0 required
+# bit12: 1 required
+# bit13: 1 required
+# bit14: 0, input buffer always powered up
+# bit17-15: 0 required
+# bit18: 1, cpu lock transaction enabled
+# bit19: 0 required
+# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0, no additional STARTBURST delay
+
+# DDR Timing (Low)
+DATA 0xFFD01408 0x22125441
+# bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0])
+# bit7-4: 4, 5 cycle tRCD
+# bit11-8: 4, 5 cyle tRP
+# bit15-12: 5, 6 cyle tWR
+# bit19-16: 2, 3 cyle tWTR
+# bit20: 1, 18 cycle tRAS (tRAS[4])
+# bit23-21: 0 required
+# bit27-24: 2, 3 cycle tRRD
+# bit31-28: 2, 3 cyle tRTP
+
+# DDR Timing (High)
+DATA 0xFFD0140C 0x00000832
+# bit6-0: 0x32, 50 cycle tRFC
+# bit8-7: 0, 1 cycle tR2R
+# bit10-9: 0, 1 cyle tR2W
+# bit12-11: 1, 2 cylce tW2W
+# bit31-13: 0 required
+
+# DDR Address Control
+DATA 0xFFD01410 0x0000000C
+# bit1-0: 0, Cs0width=x8
+# bit3-2: 3, Cs0size=1Gbit
+# bit5-4: 0, Cs1width=nonexistent
+# bit7-6: 0, Cs1size=nonexistent
+# bit9-8: 0, Cs2width=nonexistent
+# bit11-10: 0, Cs2size=nonexistent
+# bit13-12: 0, Cs3width=nonexistent
+# bit15-14: 0, Cs3size=nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+# DDR Open Pages Control
+DATA 0xFFD01414 0x00000000
+# bit0: 0, OPEn=OpenPage enabled
+# bit31-1: 0 required
+
+# DDR Operation
+DATA 0xFFD01418 0x00000000
+# bit3-0: 0, Cmd=Normal SDRAM Mode
+# bit31-4: 0 required
+
+# DDR Mode
+DATA 0xFFD0141C 0x00000652
+# bit2-0: 2, Burst Length (2 required)
+# bit3: 0, Burst Type (0 required)
+# bit6-4: 5, CAS Latency (CL) 5
+# bit7: 0, (Test Mode) Normal operation
+# bit8: 0, (Reset DLL) Normal operation
+# bit11-9: 3, Write recovery for auto-precharge (3 required)
+# bit12: 0, Fast Active power down exit time (0 required)
+# bit31-13: 0 required
+
+# DDR Extended Mode
+DATA 0xFFD01420 0x00000006
+# bit0: 0, DRAM DLL enabled
+# bit1: 1, DRAM drive strength reduced
+# bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination)
+# bit5-3: 0 required
+# bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination)
+# bit9-7: 0 required
+# bit10: 0, differential DQS enabled
+# bit11: 0 required
+# bit12: 0, DRAM output buffer enabled
+# bit31-13: 0 required
+
+# DDR Controller Control High
+DATA 0xFFD01424 0x0000F17F
+# bit2-0: 0x7 required
+# bit3: 1, MBUS Burst Chop disabled
+# bit6-4: 0x7 required
+# bit7: 0 required (???)
+# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9: 0, no half clock cycle addition to dataout
+# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11: 0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf required
+# bit31-16: 0 required
+
+# DDR2 ODT Read Timing (default values)
+DATA 0xFFD01428 0x00085520
+# bit3-0: 0 required
+# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
+# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
+# bit31-20: 0 required
+
+# DDR2 ODT Write Timing (default values)
+DATA 0xFFD0147C 0x00008552
+# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
+# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
+# bit31-16: 0 required
+
+# CS[0]n Base address
+DATA 0xFFD01500 0x00000000
+# at 0x0
+
+# CS[0]n Size
+DATA 0xFFD01504 0x0FFFFFF1
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 0x0, CS0 hit selected
+# bit23-4: 0xfffff required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+# CS[1]n Size
+DATA 0xFFD0150C 0x00000000
+# window disabled
+
+# CS[2]n Size
+DATA 0xFFD01514 0x00000000
+# window disabled
+
+# CS[3]n Size
+DATA 0xFFD0151C 0x00000000
+# window disabled
+
+# DDR ODT Control (Low)
+DATA 0xFFD01494 0x00010000
+# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
+# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
+# bit15-8: 0 required
+# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
+# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
+# bit31-24: 0 required
+
+# DDR ODT Control (High)
+DATA 0xFFD01498 0x00000000
+# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
+# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
+# bit31-4 0 required
+
+# CPU ODT Control
+DATA 0xFFD0149C 0x0000E80F
+# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
+# bit9-8: 0, Internal ODT assertion is controlled by fiels
+# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
+# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
+# bit14: 1, M_STARTBURST_IN ODT enabled
+# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
+# bit20-16: 0, Pad N channel driving strength for ODT
+# bit25-21: 0, Pad P channel driving strength for ODT
+# bit31-26: 0 required
+
+# DDR Initialization Control
+DATA 0xFFD01480 0x00000001
+# bit0: 1, enable DDR init upon this register write
+# bit31-1: 0, required
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
new file mode 100644
index 0000000..b0d49c4
--- /dev/null
+++ b/board/buffalo/lsxl/lsxl.c
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * Based on sheevaplug/sheevaplug.c by
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#include "lsxl.h"
+
+/*
+ * Rescue mode
+ *
+ * Selected by holding the push button for 3 seconds, while powering on
+ * the device.
+ *
+ * These linkstations don't have a (populated) serial port. There is no
+ * way to access an (unmodified) board other than using the netconsole. If
+ * you want to recover from a bad environment setting or an empty environment,
+ * you can do this only with a working network connection. Therefore, a random
+ * ethernet address is generated if none is set and a DHCP request is sent.
+ * After a successful DHCP response is received, the network settings are
+ * configured and the ncip is unset. Therefore, all netconsole packets are
+ * broadcasted.
+ * Additionally, the bootsource is set to 'rescue'.
+ */
+
+#ifndef CONFIG_ENV_OVERWRITE
+# error "You need to set CONFIG_ENV_OVERWRITE"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(LSXL_OE_VAL_LOW,
+ LSXL_OE_VAL_HIGH,
+ LSXL_OE_LOW, LSXL_OE_HIGH);
+
+ /*
+ * Multi-Purpose Pins Functionality configuration
+ * These strappings are taken from the original vendor uboot port.
+ */
+ static const u32 kwmpp_config[] = {
+ MPP0_SPI_SCn,
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_UART0_RXD,
+ MPP5_UART0_TXD,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_GPIO,
+ MPP9_GPIO,
+ MPP10_GPO, /* HDD power */
+ MPP11_GPIO, /* USB Vbus enable */
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_GPO, /* fan speed high */
+ MPP19_GPO, /* fan speed low */
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO, /* function LED */
+ MPP37_GPIO, /* alarm LED */
+ MPP38_GPIO, /* info LED */
+ MPP39_GPIO, /* power LED */
+ MPP40_GPIO, /* fan alarm */
+ MPP41_GPIO, /* funtion button */
+ MPP42_GPIO, /* power switch */
+ MPP43_GPIO, /* power auto switch */
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO, /* function red LED */
+ MPP49_GPIO,
+ 0
+ };
+
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+
+ return 0;
+}
+
+#define LED_OFF 0
+#define LED_ALARM_ON 1
+#define LED_ALARM_BLINKING 2
+#define LED_POWER_ON 3
+#define LED_POWER_BLINKING 4
+#define LED_INFO_ON 5
+#define LED_INFO_BLINKING 6
+
+static void __set_led(int blink_alarm, int blink_info, int blink_power,
+ int value_alarm, int value_info, int value_power)
+{
+ kw_gpio_set_blink(GPIO_ALARM_LED, blink_alarm);
+ kw_gpio_set_blink(GPIO_INFO_LED, blink_info);
+ kw_gpio_set_blink(GPIO_POWER_LED, blink_power);
+ kw_gpio_set_value(GPIO_ALARM_LED, value_alarm);
+ kw_gpio_set_value(GPIO_INFO_LED, value_info);
+ kw_gpio_set_value(GPIO_POWER_LED, value_power);
+}
+
+static void set_led(int state)
+{
+ switch (state) {
+ case LED_OFF:
+ __set_led(0, 0, 0, 1, 1, 1);
+ break;
+ case LED_ALARM_ON:
+ __set_led(0, 0, 0, 0, 1, 1);
+ break;
+ case LED_ALARM_BLINKING:
+ __set_led(1, 0, 0, 1, 1, 1);
+ break;
+ case LED_INFO_ON:
+ __set_led(0, 0, 0, 1, 0, 1);
+ break;
+ case LED_INFO_BLINKING:
+ __set_led(0, 1, 0, 1, 1, 1);
+ break;
+ case LED_POWER_ON:
+ __set_led(0, 0, 0, 1, 1, 0);
+ break;
+ case LED_POWER_BLINKING:
+ __set_led(0, 0, 1, 1, 1, 1);
+ break;
+ }
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ set_led(LED_POWER_BLINKING);
+
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+static void check_power_switch(void)
+{
+ if (kw_gpio_get_value(GPIO_POWER_SWITCH)) {
+ /* turn off fan, HDD and USB power */
+ kw_gpio_set_value(GPIO_HDD_POWER, 0);
+ kw_gpio_set_value(GPIO_USB_VBUS, 0);
+ kw_gpio_set_value(GPIO_FAN_HIGH, 1);
+ kw_gpio_set_value(GPIO_FAN_LOW, 1);
+ set_led(LED_OFF);
+
+ /* loop until released */
+ while (kw_gpio_get_value(GPIO_POWER_SWITCH))
+ ;
+
+ /* turn power on again */
+ kw_gpio_set_value(GPIO_HDD_POWER, 1);
+ kw_gpio_set_value(GPIO_USB_VBUS, 1);
+ kw_gpio_set_value(GPIO_FAN_HIGH, 0);
+ kw_gpio_set_value(GPIO_FAN_LOW, 0);
+ set_led(LED_POWER_BLINKING);
+ }
+}
+
+void check_enetaddr(void)
+{
+ uchar enetaddr[6];
+
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ /* signal unset/invalid ethaddr to user */
+ set_led(LED_INFO_BLINKING);
+ }
+}
+
+static void erase_environment(void)
+{
+ struct spi_flash *flash;
+
+ printf("Erasing environment..\n");
+ flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!flash) {
+ printf("Erasing flash failed\n");
+ return;
+ }
+
+ spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE);
+ spi_flash_free(flash);
+ do_reset(NULL, 0, 0, NULL);
+}
+
+static void rescue_mode(void)
+{
+ uchar enetaddr[6];
+
+ printf("Entering rescue mode..\n");
+#ifdef CONFIG_RANDOM_MACADDR
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ eth_random_addr(enetaddr);
+ if (eth_setenv_enetaddr("ethaddr", enetaddr)) {
+ printf("Failed to set ethernet address\n");
+ set_led(LED_ALARM_BLINKING);
+ return;
+ }
+ }
+#endif
+ setenv("bootsource", "rescue");
+}
+
+static void check_push_button(void)
+{
+ int i = 0;
+
+ while (!kw_gpio_get_value(GPIO_FUNC_BUTTON)) {
+ udelay(100000);
+ i++;
+
+ if (i == 10)
+ set_led(LED_INFO_ON);
+
+ if (i >= 100) {
+ set_led(LED_INFO_BLINKING);
+ break;
+ }
+ }
+
+ if (i >= 100)
+ erase_environment();
+ else if (i >= 10)
+ rescue_mode();
+}
+
+int misc_init_r(void)
+{
+ check_power_switch();
+ check_enetaddr();
+ check_push_button();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int progress)
+{
+ if (progress > 0)
+ return;
+
+ /* this is not an error, eg. bootp with autoload=no will trigger this */
+ if (progress == -BOOTSTAGE_ID_NET_LOADED)
+ return;
+
+ set_led(LED_ALARM_BLINKING);
+}
+#endif
diff --git a/board/buffalo/lsxl/lsxl.h b/board/buffalo/lsxl/lsxl.h
new file mode 100644
index 0000000..d5e79ac
--- /dev/null
+++ b/board/buffalo/lsxl/lsxl.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LSXL_H
+#define __LSXL_H
+
+#define GPIO_HDD_POWER 10
+#define GPIO_USB_VBUS 11
+#define GPIO_FAN_HIGH 18
+#define GPIO_FAN_LOW 19
+#define GPIO_FUNC_LED 36
+#define GPIO_ALARM_LED 37
+#define GPIO_INFO_LED 38
+#define GPIO_POWER_LED 39
+#define GPIO_FAN_LOCK 40
+#define GPIO_FUNC_BUTTON 41
+#define GPIO_POWER_SWITCH 42
+#define GPIO_POWER_AUTO_SWITCH 43
+#define GPIO_FUNC_RED_LED 48
+
+#define _BIT(x) (1<<(x))
+
+#define LSXL_OE_LOW (~(_BIT(GPIO_HDD_POWER) \
+ | _BIT(GPIO_USB_VBUS) \
+ | _BIT(GPIO_FAN_HIGH) \
+ | _BIT(GPIO_FAN_LOW)))
+
+#define LSXL_OE_HIGH (~(_BIT(GPIO_FUNC_LED - 32) \
+ | _BIT(GPIO_ALARM_LED - 32) \
+ | _BIT(GPIO_INFO_LED - 32) \
+ | _BIT(GPIO_POWER_LED - 32) \
+ | _BIT(GPIO_FUNC_RED_LED - 32)))
+
+#define LSXL_OE_VAL_LOW (_BIT(GPIO_HDD_POWER) \
+ | _BIT(GPIO_USB_VBUS))
+
+#define LSXL_OE_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \
+ | _BIT(GPIO_ALARM_LED - 32) \
+ | _BIT(GPIO_INFO_LED - 32) \
+ | _BIT(GPIO_POWER_LED - 32) \
+ | _BIT(GPIO_FUNC_RED_LED - 32))
+
+#define LSXL_POL_VAL_LOW (_BIT(GPIO_FAN_HIGH) \
+ | _BIT(GPIO_FAN_LOW))
+
+#define LSXL_POL_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \
+ | _BIT(GPIO_ALARM_LED - 32) \
+ | _BIT(GPIO_INFO_LED - 32) \
+ | _BIT(GPIO_POWER_LED - 32) \
+ | _BIT(GPIO_FUNC_BUTTON - 32) \
+ | _BIT(GPIO_POWER_SWITCH - 32) \
+ | _BIT(GPIO_POWER_AUTO_SWITCH - 32) \
+ | _BIT(GPIO_FUNC_RED_LED - 32))
+
+#endif /* __LSXL_H */
diff --git a/board/calao/sbc35_a9g20/Kconfig b/board/calao/sbc35_a9g20/Kconfig
new file mode 100644
index 0000000..fb5a1a3
--- /dev/null
+++ b/board/calao/sbc35_a9g20/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SBC35_A9G20
+
+config SYS_BOARD
+ default "sbc35_a9g20"
+
+config SYS_VENDOR
+ default "calao"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "sbc35_a9g20"
+
+endif
diff --git a/board/calao/sbc35_a9g20/MAINTAINERS b/board/calao/sbc35_a9g20/MAINTAINERS
new file mode 100644
index 0000000..0ac8225
--- /dev/null
+++ b/board/calao/sbc35_a9g20/MAINTAINERS
@@ -0,0 +1,7 @@
+SBC35_A9G20 BOARD
+#M: Albin Tonnerre <albin.tonnerre@free-electrons.com>
+S: Orphan (since 2014-06)
+F: board/calao/sbc35_a9g20/
+F: include/configs/sbc35_a9g20.h
+F: configs/sbc35_a9g20_eeprom_defconfig
+F: configs/sbc35_a9g20_nandflash_defconfig
diff --git a/board/calao/sbc35_a9g20/Makefile b/board/calao/sbc35_a9g20/Makefile
new file mode 100644
index 0000000..9ae2d24
--- /dev/null
+++ b/board/calao/sbc35_a9g20/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sbc35_a9g20.o
+obj-$(CONFIG_ATMEL_SPI) += spi.o
diff --git a/board/calao/sbc35_a9g20/config.mk b/board/calao/sbc35_a9g20/config.mk
new file mode 100644
index 0000000..e554a45
--- /dev/null
+++ b/board/calao/sbc35_a9g20/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c
new file mode 100644
index 0000000..2074a93
--- /dev/null
+++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free-Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void sbc35_a9g20_nand_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+ writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void sbc35_a9g20_macb_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+ /* Enable EMAC clock */
+ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA17) => PHY normal mode (not Test mode)
+ * ERX0 (PA14) => PHY ADDR0
+ * ERX1 (PA15) => PHY ADDR1
+ * ERX2 (PA25) => PHY ADDR2
+ * ERX3 (PA26) => PHY ADDR3
+ * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ &pioa->pudr);
+
+ at91_phy_reset();
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA25) |
+ pin_to_mask(AT91_PIN_PA26) |
+ pin_to_mask(AT91_PIN_PA28),
+ &pioa->puer);
+
+ at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ at91_seriald_hw_init();
+ sbc35_a9g20_nand_hw_init();
+#ifdef CONFIG_ATMEL_SPI
+ at91_spi0_hw_init(1 << 4 | 1 << 5);
+#endif
+#ifdef CONFIG_MACB
+ sbc35_a9g20_macb_hw_init();
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
+#endif
+ return rc;
+}
diff --git a/board/calao/sbc35_a9g20/spi.c b/board/calao/sbc35_a9g20/spi.c
new file mode 100644
index 0000000..254c7a3
--- /dev/null
+++ b/board/calao/sbc35_a9g20/spi.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_spi.h>
+#include <asm/arch/gpio.h>
+#include <spi.h>
+
+#define SBC_A9260_CS0_PIN AT91_PIN_PA3
+#define SBC_A9260_CS1_PIN AT91_PIN_PC11
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && (cs == 1 || cs == 0);
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ if(slave->cs == 0)
+ at91_set_gpio_value(SBC_A9260_CS0_PIN, 0);
+ else if(slave->cs == 1)
+ at91_set_gpio_value(SBC_A9260_CS1_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ if(slave->cs == 0)
+ at91_set_gpio_value(SBC_A9260_CS0_PIN, 1);
+ else if(slave->cs == 1)
+ at91_set_gpio_value(SBC_A9260_CS1_PIN, 1);
+}
+
+void spi_init_f(void)
+{
+ /* everything done in board_init */
+}
diff --git a/board/calao/tny_a9260/Kconfig b/board/calao/tny_a9260/Kconfig
new file mode 100644
index 0000000..b1de8f8
--- /dev/null
+++ b/board/calao/tny_a9260/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TNY_A9260
+
+config SYS_BOARD
+ default "tny_a9260"
+
+config SYS_VENDOR
+ default "calao"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "tny_a9260"
+
+endif
diff --git a/board/calao/tny_a9260/MAINTAINERS b/board/calao/tny_a9260/MAINTAINERS
new file mode 100644
index 0000000..1f24e39
--- /dev/null
+++ b/board/calao/tny_a9260/MAINTAINERS
@@ -0,0 +1,9 @@
+TNY_A9260 BOARD
+#M: Albin Tonnerre <albin.tonnerre@free-electrons.com>
+S: Orphan (since 2014-06)
+F: board/calao/tny_a9260/
+F: include/configs/tny_a9260.h
+F: configs/tny_a9260_eeprom_defconfig
+F: configs/tny_a9260_nandflash_defconfig
+F: configs/tny_a9g20_eeprom_defconfig
+F: configs/tny_a9g20_nandflash_defconfig
diff --git a/board/calao/tny_a9260/Makefile b/board/calao/tny_a9260/Makefile
new file mode 100644
index 0000000..55a6157
--- /dev/null
+++ b/board/calao/tny_a9260/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += tny_a9260.o
+obj-$(CONFIG_ATMEL_SPI) += spi.o
diff --git a/board/calao/tny_a9260/config.mk b/board/calao/tny_a9260/config.mk
new file mode 100644
index 0000000..e554a45
--- /dev/null
+++ b/board/calao/tny_a9260/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/board/calao/tny_a9260/spi.c b/board/calao/tny_a9260/spi.c
new file mode 100644
index 0000000..26ba5f5
--- /dev/null
+++ b/board/calao/tny_a9260/spi.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_spi.h>
+#include <asm/arch/gpio.h>
+#include <spi.h>
+
+#define TNY_A9260_CS_PIN AT91_PIN_PC11
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ at91_set_gpio_value(TNY_A9260_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ at91_set_gpio_value(TNY_A9260_CS_PIN, 1);
+}
+
+void spi_init_f(void)
+{
+ /* everything done in board_init */
+}
diff --git a/board/calao/tny_a9260/tny_a9260.c b/board/calao/tny_a9260/tny_a9260.c
new file mode 100644
index 0000000..337be43
--- /dev/null
+++ b/board/calao/tny_a9260/tny_a9260.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void tny_a9260_nand_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Assign CS3 to NAND/SmartMedia Interface */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+ writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ at91_seriald_hw_init();
+ tny_a9260_nand_hw_init();
+ at91_spi0_hw_init(1 << 5);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
diff --git a/board/calao/usb_a9263/Kconfig b/board/calao/usb_a9263/Kconfig
new file mode 100644
index 0000000..7a159dc
--- /dev/null
+++ b/board/calao/usb_a9263/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_USB_A9263
+
+config SYS_BOARD
+ default "usb_a9263"
+
+config SYS_VENDOR
+ default "calao"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "usb_a9263"
+
+endif
diff --git a/board/calao/usb_a9263/MAINTAINERS b/board/calao/usb_a9263/MAINTAINERS
new file mode 100644
index 0000000..2f39cd3
--- /dev/null
+++ b/board/calao/usb_a9263/MAINTAINERS
@@ -0,0 +1,6 @@
+USB_A9263 BOARD
+M: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+S: Maintained
+F: board/calao/usb_a9263/
+F: include/configs/usb_a9263.h
+F: configs/usb_a9263_dataflash_defconfig
diff --git a/board/calao/usb_a9263/Makefile b/board/calao/usb_a9263/Makefile
new file mode 100644
index 0000000..8a22b3e
--- /dev/null
+++ b/board/calao/usb_a9263/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2013
+# Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += usb_a9263.o
diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c
new file mode 100644
index 0000000..266e950
--- /dev/null
+++ b/board/calao/usb_a9263/usb_a9263.c
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2007-2013
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
+ * Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm-generic/gpio.h>
+#include <asm/io.h>
+#include <net.h>
+#include <netdev.h>
+#include <dataflash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_HAS_DATAFLASH
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x00001FFF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+ {0x00002000, 0x00003FFF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00004000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
+};
+#endif
+
+#ifdef CONFIG_CMD_NAND
+static void usb_a9263_nand_hw_init(void)
+{
+ unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0;
+ at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX;
+ at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa[0]);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode);
+
+ writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, &pmc->pcer);
+
+ /* Configure RDY/BSY */
+ gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
+ gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+ /* Enable NandFlash */
+ gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
+ gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void usb_a9263_macb_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PC25) => PHY normal mode (not Test mode)
+ * ERX0 (PE25) => PHY ADDR0
+ * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
+ *
+ * PHY has internal weak pull-up/pull-down
+ */
+ gpio_request(GPIO_PIN_PC(25), "PHY mode");
+ gpio_direction_input(GPIO_PIN_PC(25));
+
+ gpio_request(GPIO_PIN_PE(25), "PHY ADDR0");
+ gpio_direction_input(GPIO_PIN_PE(25));
+
+ gpio_request(GPIO_PIN_PE(26), "PHY ADDR1");
+ gpio_direction_input(GPIO_PIN_PE(26));
+
+ at91_phy_reset();
+
+ /* It will set proper pinmux for ports PC25, PE25-26 */
+ at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ usb_a9263_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+ usb_a9263_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+ at91_uhp_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x0001);
+#endif
+ return rc;
+}
diff --git a/board/canmb/Kconfig b/board/canmb/Kconfig
new file mode 100644
index 0000000..b5cf205
--- /dev/null
+++ b/board/canmb/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_CANMB
+
+config SYS_BOARD
+ default "canmb"
+
+config SYS_CONFIG_NAME
+ default "canmb"
+
+endif
diff --git a/board/canmb/MAINTAINERS b/board/canmb/MAINTAINERS
new file mode 100644
index 0000000..71750ea
--- /dev/null
+++ b/board/canmb/MAINTAINERS
@@ -0,0 +1,6 @@
+CANMB BOARD
+#M: -
+S: Maintained
+F: board/canmb/
+F: include/configs/canmb.h
+F: configs/canmb_defconfig
diff --git a/board/canmb/Makefile b/board/canmb/Makefile
new file mode 100644
index 0000000..4286a91
--- /dev/null
+++ b/board/canmb/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2005-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := canmb.o
+
diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c
new file mode 100644
index 0000000..15c934d
--- /dev/null
+++ b/board/canmb/canmb.c
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m32s2-75.h"
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+#endif
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set tap delay */
+ *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ }
+
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+ /* find RAM size using SDRAM CS1 only */
+ if (!dramsize)
+ sdram_start(0);
+ test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ if (!dramsize) {
+ sdram_start(1);
+ test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ }
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize2 = test1;
+ } else {
+ dramsize2 = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20)) {
+ dramsize2 = 0;
+ }
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+ | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13) {
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ } else {
+ dramsize = 0;
+ }
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ if (dramsize2 >= 0x13) {
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ } else {
+ dramsize2 = 0;
+ }
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+ puts ("Board: CANMB\n");
+ return 0;
+}
+
+int board_early_init_r (void)
+{
+ *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+ *(vu_long *)MPC5XXX_BOOTCS_START =
+ *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
+ *(vu_long *)MPC5XXX_BOOTCS_STOP =
+ *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
+ return 0;
+}
diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h
new file mode 100644
index 0000000..0133eaa
--- /dev/null
+++ b/board/canmb/mt48lc16m32s2-75.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 0 /* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/cirrus/edb93xx/Kconfig b/board/cirrus/edb93xx/Kconfig
new file mode 100644
index 0000000..c5f4897
--- /dev/null
+++ b/board/cirrus/edb93xx/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EDB93XX
+
+config SYS_BOARD
+ default "edb93xx"
+
+config SYS_VENDOR
+ default "cirrus"
+
+config SYS_SOC
+ default "ep93xx"
+
+config SYS_CONFIG_NAME
+ default "edb93xx"
+
+endif
diff --git a/board/cirrus/edb93xx/MAINTAINERS b/board/cirrus/edb93xx/MAINTAINERS
new file mode 100644
index 0000000..3bb2843
--- /dev/null
+++ b/board/cirrus/edb93xx/MAINTAINERS
@@ -0,0 +1,6 @@
+EDB93XX BOARD
+M: Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
+S: Maintained
+F: board/cirrus/edb93xx/
+F: include/configs/edb93xx.h
+F: configs/edb9315a_defconfig
diff --git a/board/cirrus/edb93xx/Makefile b/board/cirrus/edb93xx/Makefile
new file mode 100644
index 0000000..d03c498
--- /dev/null
+++ b/board/cirrus/edb93xx/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2013
+# Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd <at> denx.de.
+#
+# * SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := edb93xx.o
diff --git a/board/cirrus/edb93xx/edb93xx.c b/board/cirrus/edb93xx/edb93xx.c
new file mode 100644
index 0000000..8963d3a
--- /dev/null
+++ b/board/cirrus/edb93xx/edb93xx.c
@@ -0,0 +1,382 @@
+/*
+ * Board initialization for EP93xx
+ *
+ * Copyright (C) 2013
+ * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
+ *
+ * Copyright (C) 2009
+ * Matthias Kaehlcke <matthias <at> kaehlcke.net>
+ *
+ * (C) Copyright 2002 2003
+ * Network Audio Technologies, Inc. <www.netaudiotech.com>
+ * Adam Bezanson <bezanson <at> netaudiotech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/ep93xx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * usb_div: 4, nbyp2: 1, pll2_en: 1
+ * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
+ * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
+ */
+#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+ 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+ 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
+ SYSCON_CLKSET2_PLL2_EN | \
+ SYSCON_CLKSET2_NBYP2 | \
+ 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
+
+#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
+ SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
+ 1 << SMC_BCR_MW_SHIFT)
+
+/* delay execution before timers are initialized */
+static inline void early_udelay(uint32_t usecs)
+{
+ /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
+ register uint32_t loops = (usecs * 1000) / 20;
+
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+#ifndef CONFIG_EP93XX_NO_FLASH_CFG
+static void flash_cfg(void)
+{
+ struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
+
+ writel(SMC_BCR6_VALUE, &smc->bcr6);
+}
+#else
+#define flash_cfg()
+#endif
+
+int board_init(void)
+{
+ /*
+ * Setup PLL2, PPL1 has been set during lowlevel init
+ */
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+ writel(CLKSET2_VAL, &syscon->clkset2);
+
+ /*
+ * the user's guide recommends to wait at least 1 ms for PLL2 to
+ * stabilize
+ */
+ early_udelay(1000);
+
+ /* Go to Async mode */
+ __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
+ __asm__ volatile ("orr r0, r0, #0xc0000000");
+ __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
+
+ icache_enable();
+
+#ifdef USE_920T_MMU
+ dcache_enable();
+#endif
+
+ /* Machine number, as defined in linux/arch/arm/tools/mach-types */
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* We have a console */
+ gd->have_console = 1;
+
+ enable_interrupts();
+
+ flash_cfg();
+
+ green_led_on();
+ red_led_off();
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
+ * 14.7456/2 MHz
+ */
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+ writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ep93xx_eth_initialize(0, MAC_BASE);
+}
+
+static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
+ unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
+{
+ if (dram_bank_cnt == 1) {
+ dram_bank_base[0] = PHYS_SDRAM_1;
+ } else {
+ /* Table lookup for holes in address space. Maximum memory
+ * for the single SDCS may be up to 256Mb. We start scanning
+ * banks from 1Mb, so it could be up to 128 banks theoretically.
+ * We need at maximum 7 bits for the loockup, 8 slots is
+ * enough for the worst case.
+ */
+ unsigned tbl[8];
+ unsigned i = dram_bank_cnt / 2;
+ unsigned j = 0x00100000; /* 1 Mb */
+ unsigned *ptbl = tbl;
+ do {
+ while (!(dram_addr_mask & j)) {
+ j <<= 1;
+ }
+ *ptbl++ = j;
+ j <<= 1;
+ i >>= 1;
+ } while (i != 0);
+
+ for (i = dram_bank_cnt, j = 0;
+ (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
+ unsigned addr = PHYS_SDRAM_1;
+ unsigned k;
+ unsigned bit;
+
+ for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
+ if (bit & j)
+ addr |= tbl[k];
+ }
+
+ dram_bank_base[j] = addr;
+ }
+ }
+}
+
+/* called in board_init_f (before relocation) */
+static unsigned dram_init_banksize_int(int print)
+{
+ /*
+ * Collect information of banks that has been filled during lowlevel
+ * initialization
+ */
+ unsigned i;
+ unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
+ unsigned dram_total = 0;
+ unsigned dram_bank_size = *(unsigned *)
+ (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
+ unsigned dram_addr_mask = *(unsigned *)
+ (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
+ unsigned dram_bank_cnt = *(unsigned *)
+ (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
+
+ dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
+
+ for (i = 0; i < dram_bank_cnt; i++) {
+ gd->bd->bi_dram[i].start = dram_bank_base[i];
+ gd->bd->bi_dram[i].size = dram_bank_size;
+ dram_total += dram_bank_size;
+ }
+ for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = 0;
+ gd->bd->bi_dram[i].size = 0;
+ }
+
+ if (print) {
+ printf("DRAM mask: %08x\n", dram_addr_mask);
+ printf("DRAM total %u banks:\n", dram_bank_cnt);
+ printf("bank base-address size\n");
+
+ if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
+ printf("WARNING! UBoot was configured for %u banks,\n"
+ "but %u has been found. "
+ "Supressing extra memory banks\n",
+ CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
+ dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
+ }
+
+ for (i = 0; i < dram_bank_cnt; i++) {
+ printf(" %u %08x %08x\n",
+ i, dram_bank_base[i], dram_bank_size);
+ }
+ printf(" ------------------------------------------\n"
+ "Total %9d\n\n",
+ dram_total);
+ }
+
+ return dram_total;
+}
+
+void dram_init_banksize(void)
+{
+ dram_init_banksize_int(0);
+}
+
+/* called in board_init_f (before relocation) */
+int dram_init(void)
+{
+ struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+ unsigned sec_id = readl(SECURITY_EXTENSIONID);
+ unsigned chip_id = readl(&syscon->chipid);
+
+ printf("CPU: Cirrus Logic ");
+ switch (sec_id & 0x000001FE) {
+ case 0x00000008:
+ printf("EP9301");
+ break;
+ case 0x00000004:
+ printf("EP9307");
+ break;
+ case 0x00000002:
+ printf("EP931x");
+ break;
+ case 0x00000000:
+ printf("EP9315");
+ break;
+ default:
+ printf("<unknown>");
+ break;
+ }
+
+ printf(" - Rev. ");
+ switch (chip_id & 0xF0000000) {
+ case 0x00000000:
+ printf("A");
+ break;
+ case 0x10000000:
+ printf("B");
+ break;
+ case 0x20000000:
+ printf("C");
+ break;
+ case 0x30000000:
+ printf("D0");
+ break;
+ case 0x40000000:
+ printf("D1");
+ break;
+ case 0x50000000:
+ printf("E0");
+ break;
+ case 0x60000000:
+ printf("E1");
+ break;
+ case 0x70000000:
+ printf("E2");
+ break;
+ default:
+ printf("?");
+ break;
+ }
+ printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
+
+ gd->ram_size = dram_init_banksize_int(1);
+ return 0;
+}
+
+
+#ifdef CONFIG_EP93XX_SPI
+#include <spi.h>
+
+/*
+ * EGIO0-EGIPO7 -> port A
+ * EGIO8-EGIP15 -> port B
+ */
+
+static void ep93xx_set_epgio(unsigned num)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
+ if (num < 8)
+ writel(readl(®s->padr) | (1<<num), ®s->padr);
+ else
+ writel(readl(®s->pbdr) | (1<<(num-8)), ®s->pbdr);
+}
+
+static void ep93xx_clear_epgio(unsigned num)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
+ if (num < 8)
+ writel(readl(®s->padr) & (~(1<<num)), ®s->padr);
+ else
+ writel(readl(®s->pbdr) & (~(1<<(num-8))), ®s->pbdr);
+}
+
+static void ep93xx_dir_epgio_out(unsigned num)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
+ if (num < 8)
+ writel(readl(®s->paddr) | (1<<num), ®s->paddr);
+ else
+ writel(readl(®s->pbddr) | (1<<(num-8)), ®s->pbddr);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (bus == 0 && cs < 16)
+ return 1;
+
+ return 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ ep93xx_clear_epgio(slave->cs);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ ep93xx_set_epgio(slave->cs);
+}
+
+#ifdef CONFIG_MMC_SPI
+#include <mmc.h>
+
+#ifndef CONFIG_MMC_SPI_CS_EPGIO
+# define CONFIG_MMC_SPI_CS_EPGIO 4
+#endif
+
+#ifndef CONFIG_MMC_SPI_SPEED
+# define CONFIG_MMC_SPI_SPEED 25000000
+#endif
+
+#ifndef CONFIG_MMC_SPI_MODE
+# define CONFIG_MMC_SPI_MODE SPI_MODE_0
+#endif
+
+int board_mmc_init(bd_t *bis)
+{
+ struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
+
+ ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO);
+ ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO);
+
+#ifdef CONFIG_MMC_SPI_POWER_EGPIO
+ ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO);
+ ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO);
+#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO)
+ ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO);
+ ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO);
+#endif
+ struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO,
+ CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE);
+
+ if (!mmc) {
+ printf("Failed to create MMC Device\n");
+ return 1;
+ }
+ mmc_init(mmc);
+ return 0;
+}
+
+
+#endif /* CONFIG_MMC_SPI */
+#endif /* CONFIG_EP93XX_SPI */
diff --git a/board/cirrus/edb93xx/u-boot.lds b/board/cirrus/edb93xx/u-boot.lds
new file mode 100644
index 0000000..4aa7891
--- /dev/null
+++ b/board/cirrus/edb93xx/u-boot.lds
@@ -0,0 +1,116 @@
+/*
+ *
+ * Copyright (C) 2013
+ * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
+ *
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text : {
+ *(.__image_copy_start)
+ *(.vectors)
+ arch/arm/cpu/arm920t/start.o (.text*)
+ . = 0x1000;
+
+ LONG(0x53555243)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ .dynsym _image_binary_end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu.hash : { *(.gnu.hash) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
+ .gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
+}
diff --git a/board/cloudengines/pogo_e02/Kconfig b/board/cloudengines/pogo_e02/Kconfig
new file mode 100644
index 0000000..eaa68d9
--- /dev/null
+++ b/board/cloudengines/pogo_e02/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_POGO_E02
+
+config SYS_BOARD
+ default "pogo_e02"
+
+config SYS_VENDOR
+ default "cloudengines"
+
+config SYS_CONFIG_NAME
+ default "pogo_e02"
+
+endif
diff --git a/board/cloudengines/pogo_e02/MAINTAINERS b/board/cloudengines/pogo_e02/MAINTAINERS
new file mode 100644
index 0000000..42c5dda
--- /dev/null
+++ b/board/cloudengines/pogo_e02/MAINTAINERS
@@ -0,0 +1,6 @@
+POGO_E02 BOARD
+M: Dave Purdy <david.c.purdy@gmail.com>
+S: Maintained
+F: board/cloudengines/pogo_e02/
+F: include/configs/pogo_e02.h
+F: configs/pogo_e02_defconfig
diff --git a/board/cloudengines/pogo_e02/Makefile b/board/cloudengines/pogo_e02/Makefile
new file mode 100644
index 0000000..8ff0f45
--- /dev/null
+++ b/board/cloudengines/pogo_e02/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := pogo_e02.o
diff --git a/board/cloudengines/pogo_e02/kwbimage.cfg b/board/cloudengines/pogo_e02/kwbimage.cfg
new file mode 100644
index 0000000..b80e647
--- /dev/null
+++ b/board/cloudengines/pogo_e02/kwbimage.cfg
@@ -0,0 +1,155 @@
+#
+# Copyright (C) 2012
+# David Purdy <david.c.purdy@gmail.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xffd100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xffd01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xffd01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xffd01410 0x000000cc # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=x8
+# bit7-6: 11, Cs1size=1Gb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xffd01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xffd01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xffd0141c 0x00000c52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xffd01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xffd01424 0x0000f17f # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xffd0150c 0x00000000 # CS[2]n Size, window disabled
+
+DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
+# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xffd0149c 0x0000e803 # CPU ODT Control
+DATA 0xffd01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c
new file mode 100644
index 0000000..8309d06
--- /dev/null
+++ b/board/cloudengines/pogo_e02/pogo_e02.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2012
+ * David Purdy <david.c.purdy@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "pogo_e02.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
+ POGO_E02_OE_VAL_HIGH,
+ POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_UART0_RTS,
+ MPP9_UART0_CTS,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP29_TSMP9, /* USB Power Enable */
+ MPP48_GPIO, /* LED green */
+ MPP49_GPIO, /* LED orange */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Boot parameters address */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..(%s) could not read PHY dev address\n", __func__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ debug("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/cloudengines/pogo_e02/pogo_e02.h b/board/cloudengines/pogo_e02/pogo_e02.h
new file mode 100644
index 0000000..108d343
--- /dev/null
+++ b/board/cloudengines/pogo_e02/pogo_e02.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2012
+ * David Purdy <david.c.purdy@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __POGO_E02_H
+#define __POGO_E02_H
+
+/* GPIO configuration */
+#define POGO_E02_OE_LOW (~(0))
+#define POGO_E02_OE_HIGH (~(0))
+#define POGO_E02_OE_VAL_LOW (1 << 29)
+#define POGO_E02_OE_VAL_HIGH 0
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __POGO_E02_H */
diff --git a/board/cm-bf527/Kconfig b/board/cm-bf527/Kconfig
new file mode 100644
index 0000000..8d14179
--- /dev/null
+++ b/board/cm-bf527/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_CM_BF527
+
+config SYS_BOARD
+ default "cm-bf527"
+
+config SYS_CONFIG_NAME
+ default "cm-bf527"
+
+endif
diff --git a/board/cm-bf527/MAINTAINERS b/board/cm-bf527/MAINTAINERS
new file mode 100644
index 0000000..fefcfcf
--- /dev/null
+++ b/board/cm-bf527/MAINTAINERS
@@ -0,0 +1,6 @@
+CM-BF527 BOARD
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+S: Orphan (since 2014-03)
+F: board/cm-bf527/
+F: include/configs/cm-bf527.h
+F: configs/cm-bf527_defconfig
diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile
new file mode 100644
index 0000000..ff8ad43
--- /dev/null
+++ b/board/cm-bf527/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cm-bf527.o gpio_cfi_flash.o
diff --git a/board/cm-bf527/cm-bf527.c b/board/cm-bf527/cm-bf527.c
new file mode 100644
index 0000000..1533eb9
--- /dev/null
+++ b/board/cm-bf527/cm-bf527.c
@@ -0,0 +1,71 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/otp.h>
+#include "../cm-bf537e/gpio_cfi_flash.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix CM-BF527 board\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+ bool valid_mac = false;
+
+ /* the MAC is stored in OTP memory page 0xDF */
+ uint32_t ret;
+ uint64_t otp_mac;
+
+ ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
+ if (!(ret & OTP_MASTER_ERROR)) {
+ uchar *otp_mac_p = (uchar *)&otp_mac;
+
+ for (ret = 0; ret < 6; ++ret)
+ mac_addr[ret] = otp_mac_p[5 - ret];
+
+ if (is_valid_ether_addr(mac_addr))
+ valid_mac = true;
+ }
+
+ if (!valid_mac) {
+ puts("Warning: Generating 'random' MAC address\n");
+ eth_random_addr(mac_addr);
+ }
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+ gpio_cfi_flash_init();
+
+ return 0;
+}
diff --git a/board/cm-bf527/gpio_cfi_flash.c b/board/cm-bf527/gpio_cfi_flash.c
new file mode 100644
index 0000000..6e62fff
--- /dev/null
+++ b/board/cm-bf527/gpio_cfi_flash.c
@@ -0,0 +1,3 @@
+#define GPIO_PIN_1 GPIO_PH9
+#define GPIO_PIN_2 GPIO_PG11
+#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/cm-bf533/Kconfig b/board/cm-bf533/Kconfig
new file mode 100644
index 0000000..cedd752
--- /dev/null
+++ b/board/cm-bf533/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_CM_BF533
+
+config SYS_BOARD
+ default "cm-bf533"
+
+config SYS_CONFIG_NAME
+ default "cm-bf533"
+
+endif
diff --git a/board/cm-bf533/MAINTAINERS b/board/cm-bf533/MAINTAINERS
new file mode 100644
index 0000000..0bf51fb
--- /dev/null
+++ b/board/cm-bf533/MAINTAINERS
@@ -0,0 +1,6 @@
+CM-BF533 BOARD
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+S: Orphan (since 2014-03)
+F: board/cm-bf533/
+F: include/configs/cm-bf533.h
+F: configs/cm-bf533_defconfig
diff --git a/board/cm-bf533/Makefile b/board/cm-bf533/Makefile
new file mode 100644
index 0000000..ec99638
--- /dev/null
+++ b/board/cm-bf533/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cm-bf533.o
diff --git a/board/cm-bf533/cm-bf533.c b/board/cm-bf533/cm-bf533.c
new file mode 100644
index 0000000..a863195
--- /dev/null
+++ b/board/cm-bf533/cm-bf533.c
@@ -0,0 +1,26 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix CM-BF533 board\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk
new file mode 100644
index 0000000..7f9138b
--- /dev/null
+++ b/board/cm-bf533/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537e/Kconfig b/board/cm-bf537e/Kconfig
new file mode 100644
index 0000000..af2e548
--- /dev/null
+++ b/board/cm-bf537e/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_CM_BF537E
+
+config SYS_BOARD
+ default "cm-bf537e"
+
+config SYS_CONFIG_NAME
+ default "cm-bf537e"
+
+endif
diff --git a/board/cm-bf537e/MAINTAINERS b/board/cm-bf537e/MAINTAINERS
new file mode 100644
index 0000000..63d2428
--- /dev/null
+++ b/board/cm-bf537e/MAINTAINERS
@@ -0,0 +1,6 @@
+CM-BF537E BOARD
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+S: Orphan (since 2014-03)
+F: board/cm-bf537e/
+F: include/configs/cm-bf537e.h
+F: configs/cm-bf537e_defconfig
diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile
new file mode 100644
index 0000000..be8056f
--- /dev/null
+++ b/board/cm-bf537e/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cm-bf537e.o gpio_cfi_flash.o
diff --git a/board/cm-bf537e/cm-bf537e.c b/board/cm-bf537e/cm-bf537e.c
new file mode 100644
index 0000000..e79f90f
--- /dev/null
+++ b/board/cm-bf537e/cm-bf537e.c
@@ -0,0 +1,59 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include "gpio_cfi_flash.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix CM-BF537E board\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+static void board_init_enetaddr(char *var)
+{
+ uchar enetaddr[6];
+
+ if (eth_getenv_enetaddr(var, enetaddr))
+ return;
+
+ printf("Warning: %s: generating 'random' MAC address\n", var);
+ eth_random_addr(enetaddr);
+ eth_setenv_enetaddr(var, enetaddr);
+}
+
+#ifndef CONFIG_BFIN_MAC
+# define bfin_EMAC_initialize(x) 1
+#endif
+#ifndef CONFIG_SMC911X
+# define smc911x_initialize(n, x) 1
+#endif
+int board_eth_init(bd_t *bis)
+{
+ /* return ok if at least 1 eth device works */
+ return bfin_EMAC_initialize(bis) &
+ smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+
+int misc_init_r(void)
+{
+ board_init_enetaddr("ethaddr");
+ board_init_enetaddr("eth1addr");
+
+ gpio_cfi_flash_init();
+
+ return 0;
+}
diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk
new file mode 100644
index 0000000..7f9138b
--- /dev/null
+++ b/board/cm-bf537e/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537e/gpio_cfi_flash.c b/board/cm-bf537e/gpio_cfi_flash.c
new file mode 100644
index 0000000..1075cc4
--- /dev/null
+++ b/board/cm-bf537e/gpio_cfi_flash.c
@@ -0,0 +1,81 @@
+/*
+ * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
+ *
+ * Copyright (c) 2009-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include "gpio_cfi_flash.h"
+
+/* Allow this driver to be shared among boards */
+#ifndef GPIO_PIN_1
+#define GPIO_PIN_1 GPIO_PF4
+#endif
+#define GPIO_MASK_1 (1 << 21)
+#ifndef GPIO_PIN_2
+#define GPIO_MASK_2 (0)
+#else
+#define GPIO_MASK_2 (1 << 22)
+#endif
+#ifndef GPIO_PIN_3
+#define GPIO_MASK_3 (0)
+#else
+#define GPIO_MASK_3 (1 << 23)
+#endif
+#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2 | GPIO_MASK_3)
+
+void *gpio_cfi_flash_swizzle(void *vaddr)
+{
+ unsigned long addr = (unsigned long)vaddr;
+
+ gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
+
+#ifdef GPIO_PIN_2
+ gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
+#endif
+
+#ifdef GPIO_PIN_3
+ gpio_set_value(GPIO_PIN_3, addr & GPIO_MASK_3);
+#endif
+
+ SSYNC();
+ udelay(1);
+
+ return (void *)(addr & ~GPIO_MASK);
+}
+
+#define __raw_writeq(value, addr) *(volatile u64 *)addr = value
+#define __raw_readq(addr) *(volatile u64 *)addr
+
+#define MAKE_FLASH(size, sfx) \
+void flash_write##size(u##size value, void *addr) \
+{ \
+ __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \
+} \
+u##size flash_read##size(void *addr) \
+{ \
+ return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \
+}
+MAKE_FLASH(8, b) /* flash_write8() flash_read8() */
+MAKE_FLASH(16, w) /* flash_write16() flash_read16() */
+MAKE_FLASH(32, l) /* flash_write32() flash_read32() */
+MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
+
+void gpio_cfi_flash_init(void)
+{
+ gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
+ gpio_direction_output(GPIO_PIN_1, 0);
+#ifdef GPIO_PIN_2
+ gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
+ gpio_direction_output(GPIO_PIN_2, 0);
+#endif
+#ifdef GPIO_PIN_3
+ gpio_request(GPIO_PIN_3, "gpio_cfi_flash");
+ gpio_direction_output(GPIO_PIN_3, 0);
+#endif
+}
diff --git a/board/cm-bf537e/gpio_cfi_flash.h b/board/cm-bf537e/gpio_cfi_flash.h
new file mode 100644
index 0000000..5211e97
--- /dev/null
+++ b/board/cm-bf537e/gpio_cfi_flash.h
@@ -0,0 +1,10 @@
+/*
+ * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+void *gpio_cfi_flash_swizzle(void *vaddr);
+void gpio_cfi_flash_init(void);
diff --git a/board/cm-bf537u/Kconfig b/board/cm-bf537u/Kconfig
new file mode 100644
index 0000000..baf9e8c
--- /dev/null
+++ b/board/cm-bf537u/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_CM_BF537U
+
+config SYS_BOARD
+ default "cm-bf537u"
+
+config SYS_CONFIG_NAME
+ default "cm-bf537u"
+
+endif
diff --git a/board/cm-bf537u/MAINTAINERS b/board/cm-bf537u/MAINTAINERS
new file mode 100644
index 0000000..a89cfca
--- /dev/null
+++ b/board/cm-bf537u/MAINTAINERS
@@ -0,0 +1,6 @@
+CM-BF537U BOARD
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+S: Orphan (since 2014-03)
+F: board/cm-bf537u/
+F: include/configs/cm-bf537u.h
+F: configs/cm-bf537u_defconfig
diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile
new file mode 100644
index 0000000..38dd3fb
--- /dev/null
+++ b/board/cm-bf537u/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cm-bf537u.o gpio_cfi_flash.o
diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c
new file mode 100644
index 0000000..632cbda
--- /dev/null
+++ b/board/cm-bf537u/cm-bf537u.c
@@ -0,0 +1,59 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include "../cm-bf537e/gpio_cfi_flash.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix CM-BF537U board\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+static void board_init_enetaddr(char *var)
+{
+ uchar enetaddr[6];
+
+ if (eth_getenv_enetaddr(var, enetaddr))
+ return;
+
+ printf("Warning: %s: generating 'random' MAC address\n", var);
+ eth_random_addr(enetaddr);
+ eth_setenv_enetaddr(var, enetaddr);
+}
+
+#ifndef CONFIG_BFIN_MAC
+# define bfin_EMAC_initialize(x) 1
+#endif
+#ifndef CONFIG_SMC911X
+# define smc911x_initialize(n, x) 1
+#endif
+int board_eth_init(bd_t *bis)
+{
+ /* return ok if at least 1 eth device works */
+ return bfin_EMAC_initialize(bis) &
+ smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+
+int misc_init_r(void)
+{
+ board_init_enetaddr("ethaddr");
+ board_init_enetaddr("eth1addr");
+
+ gpio_cfi_flash_init();
+
+ return 0;
+}
diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk
new file mode 100644
index 0000000..7f9138b
--- /dev/null
+++ b/board/cm-bf537u/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537u/gpio_cfi_flash.c b/board/cm-bf537u/gpio_cfi_flash.c
new file mode 100644
index 0000000..ef5ea8b
--- /dev/null
+++ b/board/cm-bf537u/gpio_cfi_flash.c
@@ -0,0 +1,2 @@
+#define GPIO_PIN_1 GPIO_PH0
+#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/cm-bf548/Kconfig b/board/cm-bf548/Kconfig
new file mode 100644
index 0000000..b96cb5f
--- /dev/null
+++ b/board/cm-bf548/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_CM_BF548
+
+config SYS_BOARD
+ default "cm-bf548"
+
+config SYS_CONFIG_NAME
+ default "cm-bf548"
+
+endif
diff --git a/board/cm-bf548/MAINTAINERS b/board/cm-bf548/MAINTAINERS
new file mode 100644
index 0000000..b7f5779
--- /dev/null
+++ b/board/cm-bf548/MAINTAINERS
@@ -0,0 +1,6 @@
+CM-BF548 BOARD
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+S: Orphan (since 2014-03)
+F: board/cm-bf548/
+F: include/configs/cm-bf548.h
+F: configs/cm-bf548_defconfig
diff --git a/board/cm-bf548/Makefile b/board/cm-bf548/Makefile
new file mode 100644
index 0000000..98aca32
--- /dev/null
+++ b/board/cm-bf548/Makefile
@@ -0,0 +1,13 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cm-bf548.o
+obj-$(CONFIG_VIDEO) += video.o
diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c
new file mode 100644
index 0000000..90ce4c3
--- /dev/null
+++ b/board/cm-bf548/cm-bf548.c
@@ -0,0 +1,43 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/portmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix CM-BF548 board\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /* Set async addr lines as peripheral */
+ const unsigned short pins[] = {
+ P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+ P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
+ P_A21, P_A22, P_A23, P_A24, 0
+ };
+ return peripheral_request_list(pins, "async");
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk
new file mode 100644
index 0000000..beb9834
--- /dev/null
+++ b/board/cm-bf548/config.mk
@@ -0,0 +1,14 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --dma 6
+LDR_FLAGS-BFIN_BOOT_FIFO := --dma 1
+LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
+LDR_FLAGS-BFIN_BOOT_UART := --dma 1
diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c
new file mode 100644
index 0000000..b098615
--- /dev/null
+++ b/board/cm-bf548/video.c
@@ -0,0 +1,341 @@
+/*
+ * video.c - run splash screen on lcd
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <stdarg.h>
+#include <common.h>
+#include <config.h>
+#include <malloc.h>
+#include <asm/blackfin.h>
+#include <asm/clock.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
+#include <asm/mach-common/bits/dma.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <stdio_dev.h>
+
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
+
+#define DMA_SIZE16 2
+
+#include <asm/mach-common/bits/eppi.h>
+
+#include EASYLOGO_HEADER
+
+#define LCD_X_RES 480 /*Horizontal Resolution */
+#define LCD_Y_RES 272 /* Vertical Resolution */
+
+#define LCD_BPP 24 /* Bit Per Pixel */
+#define LCD_PIXEL_SIZE (LCD_BPP / 8)
+#define DMA_BUS_SIZE 32
+#define ACTIVE_VIDEO_MEM_OFFSET 0
+
+/* -- Horizontal synchronizing --
+ *
+ * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
+ * (LCY-W-06602A Page 9 of 22)
+ *
+ * Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
+ *
+ * Period TH - 525 - Clock
+ * Pulse width THp - 41 - Clock
+ * Horizontal period THd - 480 - Clock
+ * Back porch THb - 2 - Clock
+ * Front porch THf - 2 - Clock
+ *
+ * -- Vertical synchronizing --
+ * Period TV - 286 - Line
+ * Pulse width TVp - 10 - Line
+ * Vertical period TVd - 272 - Line
+ * Back porch TVb - 2 - Line
+ * Front porch TVf - 2 - Line
+ */
+
+#define LCD_CLK (8*1000*1000) /* 8MHz */
+
+/* # active data to transfer after Horizontal Delay clock */
+#define EPPI_HCOUNT LCD_X_RES
+
+/* # active lines to transfer after Vertical Delay clock */
+#define EPPI_VCOUNT LCD_Y_RES
+
+/* Samples per Line = 480 (active data) + 45 (padding) */
+#define EPPI_LINE 525
+
+/* Lines per Frame = 272 (active data) + 14 (padding) */
+#define EPPI_FRAME 286
+
+/* FS1 (Hsync) Width (Typical)*/
+#define EPPI_FS1W_HBL 41
+
+/* FS1 (Hsync) Period (Typical) */
+#define EPPI_FS1P_AVPL EPPI_LINE
+
+/* Horizontal Delay clock after assertion of Hsync (Typical) */
+#define EPPI_HDELAY 43
+
+/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */
+#define EPPI_FS2W_LVB (EPPI_LINE * 10)
+
+ /* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */
+#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME)
+
+/* Vertical Delay after assertion of Vsync (2 Lines) */
+#define EPPI_VDELAY 12
+
+#define EPPI_CLIP 0xFF00FF00
+
+/* EPPI Control register configuration value for RGB out
+ * - EPPI as Output
+ * GP 2 frame sync mode,
+ * Internal Clock generation disabled, Internal FS generation enabled,
+ * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
+ * FS1 & FS2 are active high,
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
+ * Swapping Enabled,
+ * One (DMA) Channel Mode,
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ * Regular watermark - when FIFO is 100% full,
+ * Urgent watermark - when FIFO is 75% full
+ */
+
+#define EPPI_CONTROL (0x20136E2E)
+
+static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
+{
+ u32 sclk = get_sclk();
+
+ /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
+
+ return (((sclk / target_ppi_clk) / 2) - 1);
+}
+
+void Init_PPI(void)
+{
+ u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
+
+ bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
+ bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
+ bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
+ bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
+ bfin_write_EPPI0_CLIP(EPPI_CLIP);
+
+ bfin_write_EPPI0_FRAME(EPPI_FRAME);
+ bfin_write_EPPI0_LINE(EPPI_LINE);
+
+ bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
+ bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
+ bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
+ bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
+
+ bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
+
+/*
+ * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
+ * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
+ */
+#if defined(CONFIG_VIDEO_RGB666)
+ bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
+ RGB_FMT_EN);
+#else
+ bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
+ ~RGB_FMT_EN);
+#endif
+
+}
+
+#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
+
+void Init_DMA(void *dst)
+{
+#if defined(CONFIG_DEB_DMA_URGENT)
+ bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
+#endif
+
+ bfin_write_DMA12_START_ADDR(dst);
+
+ /* X count */
+ bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
+ bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
+
+ /* Y count */
+ bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
+ bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
+
+ /* DMA Config */
+ bfin_write_DMA12_CONFIG(
+ WDSIZE_32 | /* 32 bit DMA */
+ DMA2D | /* 2D DMA */
+ FLOW_AUTO /* autobuffer mode */
+ );
+}
+
+void Init_Ports(void)
+{
+ const unsigned short pins[] = {
+ P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
+ P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
+ P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
+ P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
+#if !defined(CONFIG_VIDEO_RGB666)
+ P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
+ P_PPI0_D23,
+#endif
+ P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
+ };
+ peripheral_request_list(pins, "lcd");
+
+ gpio_request(GPIO_PE3, "lcd-disp");
+ gpio_direction_output(GPIO_PE3, 1);
+}
+
+void EnableDMA(void)
+{
+ bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
+}
+
+void DisableDMA(void)
+{
+ bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
+}
+
+/* enable and disable PPI functions */
+void EnablePPI(void)
+{
+ bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
+}
+
+void DisablePPI(void)
+{
+ bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
+}
+
+int video_init(void *dst)
+{
+ Init_Ports();
+ Init_DMA(dst);
+ EnableDMA();
+ Init_PPI();
+ EnablePPI();
+
+ return 0;
+}
+
+void video_stop(void)
+{
+ DisablePPI();
+ DisableDMA();
+}
+
+static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
+{
+ if (dcache_status())
+ blackfin_dcache_flush_range(logo->data,
+ logo->data + logo->size);
+
+ bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+
+ /* Setup destination start address */
+ bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
+ + (y * LCD_X_RES * LCD_PIXEL_SIZE));
+ /* Setup destination xcount */
+ bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+ /* Setup destination xmodify */
+ bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
+
+ /* Setup destination ycount */
+ bfin_write_MDMA_D0_Y_COUNT(logo->height);
+ /* Setup destination ymodify */
+ bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE +
+ DMA_SIZE16);
+
+ /* Setup Source start address */
+ bfin_write_MDMA_S0_START_ADDR(logo->data);
+ /* Setup Source xcount */
+ bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
+ /* Setup Source xmodify */
+ bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
+
+ /* Setup Source ycount */
+ bfin_write_MDMA_S0_Y_COUNT(logo->height);
+ /* Setup Source ymodify */
+ bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
+
+ /* Enable source DMA */
+ bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
+ SSYNC();
+ bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
+
+ while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) ;
+
+ bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE
+ | DMA_ERR);
+ bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE
+ | DMA_ERR);
+
+}
+
+int drv_video_init(void)
+{
+ int error, devices = 1;
+ struct stdio_dev videodev;
+
+ u8 *dst;
+ u32 fbmem_size =
+ LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
+
+ dst = malloc(fbmem_size);
+
+ if (dst == NULL) {
+ printf("Failed to alloc FB memory\n");
+ return -1;
+ }
+
+#ifdef EASYLOGO_ENABLE_GZIP
+ unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+ unsigned long src_len = EASYLOGO_ENABLE_GZIP;
+ error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
+ bfin_logo.data = data;
+#elif defined(EASYLOGO_ENABLE_LZMA)
+ unsigned char *data = EASYLOGO_DECOMP_BUFFER;
+ SizeT lzma_len = bfin_logo.size;
+ error = lzmaBuffToBuffDecompress(data, &lzma_len,
+ bfin_logo.data, EASYLOGO_ENABLE_LZMA);
+ bfin_logo.data = data;
+#else
+ error = 0;
+#endif
+
+ if (error) {
+ puts("Failed to decompress logo\n");
+ free(dst);
+ return -1;
+ }
+
+ memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0],
+ fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
+
+ dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
+ (LCD_X_RES - bfin_logo.width) / 2,
+ (LCD_Y_RES - bfin_logo.height) / 2);
+
+ video_init(dst); /* Video initialization */
+
+ memset(&videodev, 0, sizeof(videodev));
+
+ strcpy(videodev.name, "video");
+ videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
+ videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
+
+ error = stdio_register(&videodev);
+
+ return (error == 0) ? devices : error;
+}
diff --git a/board/cm-bf561/Kconfig b/board/cm-bf561/Kconfig
new file mode 100644
index 0000000..8b302a5
--- /dev/null
+++ b/board/cm-bf561/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_CM_BF561
+
+config SYS_BOARD
+ default "cm-bf561"
+
+config SYS_CONFIG_NAME
+ default "cm-bf561"
+
+endif
diff --git a/board/cm-bf561/MAINTAINERS b/board/cm-bf561/MAINTAINERS
new file mode 100644
index 0000000..9c86c8d
--- /dev/null
+++ b/board/cm-bf561/MAINTAINERS
@@ -0,0 +1,6 @@
+CM-BF561 BOARD
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+S: Orphan (since 2014-03)
+F: board/cm-bf561/
+F: include/configs/cm-bf561.h
+F: configs/cm-bf561_defconfig
diff --git a/board/cm-bf561/Makefile b/board/cm-bf561/Makefile
new file mode 100644
index 0000000..c8764fb
--- /dev/null
+++ b/board/cm-bf561/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cm-bf561.o
diff --git a/board/cm-bf561/cm-bf561.c b/board/cm-bf561/cm-bf561.c
new file mode 100644
index 0000000..5741f64
--- /dev/null
+++ b/board/cm-bf561/cm-bf561.c
@@ -0,0 +1,26 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix CM-BF561 core module\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk
new file mode 100644
index 0000000..854d7db
--- /dev/null
+++ b/board/cm-bf561/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/cm4008/Kconfig b/board/cm4008/Kconfig
new file mode 100644
index 0000000..de87d5b
--- /dev/null
+++ b/board/cm4008/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CM4008
+
+config SYS_BOARD
+ default "cm4008"
+
+config SYS_SOC
+ default "ks8695"
+
+config SYS_CONFIG_NAME
+ default "cm4008"
+
+endif
diff --git a/board/cm4008/MAINTAINERS b/board/cm4008/MAINTAINERS
new file mode 100644
index 0000000..5f08bc3
--- /dev/null
+++ b/board/cm4008/MAINTAINERS
@@ -0,0 +1,6 @@
+CM4008 BOARD
+M: Greg Ungerer <greg.ungerer@opengear.com>
+S: Maintained
+F: board/cm4008/
+F: include/configs/cm4008.h
+F: configs/cm4008_defconfig
diff --git a/board/cm4008/Makefile b/board/cm4008/Makefile
new file mode 100644
index 0000000..04b1529
--- /dev/null
+++ b/board/cm4008/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cm4008.o flash.o
diff --git a/board/cm4008/cm4008.c b/board/cm4008/cm4008.c
new file mode 100644
index 0000000..740e164
--- /dev/null
+++ b/board/cm4008/cm4008.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
+#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int env_flash_cmdline (void)
+{
+ char *sp = (char *) 0x0201c020;
+ char *ep;
+ int len;
+
+ /* Check if "erase" push button is depressed */
+ if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
+ printf("### Entering network recovery mode...\n");
+ setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0");
+ setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
+ setenv("bootdelay", "2");
+ return 0;
+ }
+
+ /* Check for flash based kernel boot args to use as default */
+ for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
+ ;
+
+ if ((len > 0) && (len <1024))
+ setenv("bootargs", sp);
+
+ return 0;
+}
+
+int board_late_init (void)
+{
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return ks8695_eth_initialize();
+}
+
+int board_init (void)
+{
+ /* arch number of CM4008 */
+ gd->bd->bi_arch_number = 624;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x00000100;
+
+ /* power down all but port 0 on the switch */
+ ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
+ ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return (0);
+}
diff --git a/board/cm4008/config.mk b/board/cm4008/config.mk
new file mode 100644
index 0000000..0d5923b
--- /dev/null
+++ b/board/cm4008/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x00f00000
diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c
new file mode 100644
index 0000000..8315a57
--- /dev/null
+++ b/board/cm4008/flash.c
@@ -0,0 +1,395 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+#include <asm/sections.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, unsigned char data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ int i;
+ ulong size = 0;
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+ switch (i) {
+ case 0:
+ flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
+ flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+ break;
+ case 1:
+ /* ignore for now */
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ break;
+ default:
+ panic ("configured too many flash banks!\n");
+ break;
+ }
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors
+ */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
+ &flash_info[0]);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return;
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+ info->protect[i] = 0;
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ printf ("INTEL ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F128J3A:
+ printf ("28F128J3A\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+ return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
+{
+ volatile unsigned char value;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x5555] = 0xAA;
+ addr[0x2AAA] = 0x55;
+ addr[0x5555] = 0x90;
+
+ mb ();
+ value = addr[0];
+
+ switch (value) {
+
+ case (unsigned char)INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ addr[0] = 0xFF; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ mb ();
+ value = addr[2]; /* device ID */
+
+ switch (value) {
+
+ case (unsigned char)INTEL_ID_28F640J3A:
+ info->flash_id += FLASH_28F640J3A;
+ info->sector_count = 64;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+
+ case (unsigned char)INTEL_ID_28F128J3A:
+ info->flash_id += FLASH_28F128J3A;
+ info->sector_count = 128;
+ info->size = 0x01000000;
+ break; /* => 16 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ break;
+ }
+
+ if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ }
+
+ addr[0] = 0xFF; /* restore read mode */
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ int prot, sect;
+ ulong type;
+ int rcode = 0;
+ ulong start;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ type = (info->flash_id & FLASH_VENDMASK);
+ if ((type != FLASH_MAN_INTEL)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot)
+ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+ else
+ printf ("\n");
+
+ /* Disable interrupts which might cause a timeout here */
+ disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ volatile unsigned char *addr;
+ unsigned char status;
+
+ printf ("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ addr = (volatile unsigned char *) (info->start[sect]);
+ *addr = 0x50; /* clear status register */
+ *addr = 0x20; /* erase setup */
+ *addr = 0xD0; /* erase confirm */
+
+ while (((status = *addr) & 0x80) != 0x80) {
+ if (get_timer(start) >
+ CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = 0xB0; /* suspend erase */
+ *addr = 0xFF; /* reset to read mode */
+ rcode = 1;
+ break;
+ }
+ }
+
+ *addr = 0x50; /* clear status register cmd */
+ *addr = 0xFF; /* resest to read mode */
+
+ printf (" done\n");
+ }
+ }
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ unsigned char data;
+ int count, i, l, rc, port_width;
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return 4;
+
+ wp = addr;
+ port_width = 1;
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < port_width && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_data (info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ count = 0;
+ while (cnt >= port_width) {
+ data = 0;
+ for (i = 0; i < port_width; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_data (info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ cnt -= port_width;
+ if (count++ > 0x800) {
+ spin_wheel ();
+ count = 0;
+ }
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, unsigned char data)
+{
+ volatile unsigned char *addr = (volatile unsigned char *) dest;
+ ulong status;
+ ulong start;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+ (ulong) * addr);
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ disable_interrupts();
+
+ *addr = 0x40; /* write setup */
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ /* wait while polling the status register */
+ while (((status = *addr) & 0x80) != 0x80) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ *addr = 0xFF; /* restore read mode */
+ return (1);
+ }
+ }
+
+ *addr = 0xFF; /* restore read mode */
+
+ return (0);
+}
+
+void inline spin_wheel (void)
+{
+ static int p = 0;
+ static char w[] = "\\/-";
+
+ printf ("\010%c", w[p]);
+ (++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/cm41xx/Kconfig b/board/cm41xx/Kconfig
new file mode 100644
index 0000000..99e675b
--- /dev/null
+++ b/board/cm41xx/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CM41XX
+
+config SYS_BOARD
+ default "cm41xx"
+
+config SYS_SOC
+ default "ks8695"
+
+config SYS_CONFIG_NAME
+ default "cm41xx"
+
+endif
diff --git a/board/cm41xx/MAINTAINERS b/board/cm41xx/MAINTAINERS
new file mode 100644
index 0000000..f10eeb5
--- /dev/null
+++ b/board/cm41xx/MAINTAINERS
@@ -0,0 +1,6 @@
+CM41XX BOARD
+#M: -
+S: Maintained
+F: board/cm41xx/
+F: include/configs/cm41xx.h
+F: configs/cm41xx_defconfig
diff --git a/board/cm41xx/Makefile b/board/cm41xx/Makefile
new file mode 100644
index 0000000..b71ea05
--- /dev/null
+++ b/board/cm41xx/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cm41xx.o flash.o
diff --git a/board/cm41xx/cm41xx.c b/board/cm41xx/cm41xx.c
new file mode 100644
index 0000000..eabad48
--- /dev/null
+++ b/board/cm41xx/cm41xx.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
+#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int env_flash_cmdline (void)
+{
+ char *sp = (char *) 0x0201c020;
+ char *ep;
+ int len;
+
+ /* Check if "erase" push button is depressed */
+ if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
+ printf("### Entering network recovery mode...\n");
+ setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0");
+ setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
+ setenv("bootdelay", "2");
+ return 0;
+ }
+
+ /* Check for flash based kernel boot args to use as default */
+ for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
+ ;
+
+ if ((len > 0) && (len <1024))
+ setenv("bootargs", sp);
+
+ return 0;
+}
+
+int board_late_init (void)
+{
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return ks8695_eth_initialize();
+}
+
+int board_init (void)
+{
+ /* arch number of CM41xx */
+ gd->bd->bi_arch_number = 672;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x00000100;
+
+ /* power down all but port 0 on the switch */
+ ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
+ ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return (0);
+}
diff --git a/board/cm41xx/config.mk b/board/cm41xx/config.mk
new file mode 100644
index 0000000..0d5923b
--- /dev/null
+++ b/board/cm41xx/config.mk
@@ -0,0 +1 @@
+CONFIG_SYS_TEXT_BASE = 0x00f00000
diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c
new file mode 100644
index 0000000..8315a57
--- /dev/null
+++ b/board/cm41xx/flash.c
@@ -0,0 +1,395 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+#include <asm/sections.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, unsigned char data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ int i;
+ ulong size = 0;
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+ switch (i) {
+ case 0:
+ flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
+ flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+ break;
+ case 1:
+ /* ignore for now */
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ break;
+ default:
+ panic ("configured too many flash banks!\n");
+ break;
+ }
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors
+ */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start),
+ &flash_info[0]);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return;
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+ info->protect[i] = 0;
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ printf ("INTEL ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F128J3A:
+ printf ("28F128J3A\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+ return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
+{
+ volatile unsigned char value;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x5555] = 0xAA;
+ addr[0x2AAA] = 0x55;
+ addr[0x5555] = 0x90;
+
+ mb ();
+ value = addr[0];
+
+ switch (value) {
+
+ case (unsigned char)INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ addr[0] = 0xFF; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ mb ();
+ value = addr[2]; /* device ID */
+
+ switch (value) {
+
+ case (unsigned char)INTEL_ID_28F640J3A:
+ info->flash_id += FLASH_28F640J3A;
+ info->sector_count = 64;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+
+ case (unsigned char)INTEL_ID_28F128J3A:
+ info->flash_id += FLASH_28F128J3A;
+ info->sector_count = 128;
+ info->size = 0x01000000;
+ break; /* => 16 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ break;
+ }
+
+ if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ }
+
+ addr[0] = 0xFF; /* restore read mode */
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ int prot, sect;
+ ulong type;
+ int rcode = 0;
+ ulong start;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ type = (info->flash_id & FLASH_VENDMASK);
+ if ((type != FLASH_MAN_INTEL)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot)
+ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+ else
+ printf ("\n");
+
+ /* Disable interrupts which might cause a timeout here */
+ disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ volatile unsigned char *addr;
+ unsigned char status;
+
+ printf ("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ addr = (volatile unsigned char *) (info->start[sect]);
+ *addr = 0x50; /* clear status register */
+ *addr = 0x20; /* erase setup */
+ *addr = 0xD0; /* erase confirm */
+
+ while (((status = *addr) & 0x80) != 0x80) {
+ if (get_timer(start) >
+ CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = 0xB0; /* suspend erase */
+ *addr = 0xFF; /* reset to read mode */
+ rcode = 1;
+ break;
+ }
+ }
+
+ *addr = 0x50; /* clear status register cmd */
+ *addr = 0xFF; /* resest to read mode */
+
+ printf (" done\n");
+ }
+ }
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ unsigned char data;
+ int count, i, l, rc, port_width;
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return 4;
+
+ wp = addr;
+ port_width = 1;
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < port_width && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_data (info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ count = 0;
+ while (cnt >= port_width) {
+ data = 0;
+ for (i = 0; i < port_width; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_data (info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ cnt -= port_width;
+ if (count++ > 0x800) {
+ spin_wheel ();
+ count = 0;
+ }
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, unsigned char data)
+{
+ volatile unsigned char *addr = (volatile unsigned char *) dest;
+ ulong status;
+ ulong start;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+ (ulong) * addr);
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ disable_interrupts();
+
+ *addr = 0x40; /* write setup */
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ /* wait while polling the status register */
+ while (((status = *addr) & 0x80) != 0x80) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ *addr = 0xFF; /* restore read mode */
+ return (1);
+ }
+ }
+
+ *addr = 0xFF; /* restore read mode */
+
+ return (0);
+}
+
+void inline spin_wheel (void)
+{
+ static int p = 0;
+ static char w[] = "\\/-";
+
+ printf ("\010%c", w[p]);
+ (++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/cm5200/Kconfig b/board/cm5200/Kconfig
new file mode 100644
index 0000000..ccea5c9
--- /dev/null
+++ b/board/cm5200/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_CM5200
+
+config SYS_BOARD
+ default "cm5200"
+
+config SYS_CONFIG_NAME
+ default "cm5200"
+
+endif
diff --git a/board/cm5200/MAINTAINERS b/board/cm5200/MAINTAINERS
new file mode 100644
index 0000000..1e1df3f
--- /dev/null
+++ b/board/cm5200/MAINTAINERS
@@ -0,0 +1,6 @@
+CM5200 BOARD
+#M: -
+S: Maintained
+F: board/cm5200/
+F: include/configs/cm5200.h
+F: configs/cm5200_defconfig
diff --git a/board/cm5200/Makefile b/board/cm5200/Makefile
new file mode 100644
index 0000000..76f8b9f
--- /dev/null
+++ b/board/cm5200/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cm5200.o cmd_cm5200.o fwupdate.o
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
new file mode 100644
index 0000000..5276907
--- /dev/null
+++ b/board/cm5200/cm5200.c
@@ -0,0 +1,369 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * Adapted to U-Boot 1.2 by:
+ * Bartlomiej Sieka <tur@semihalf.com>:
+ * - HW ID readout from EEPROM
+ * - module detection
+ * Grzegorz Bernacki <gjb@semihalf.com>:
+ * - run-time SDRAM controller configuration
+ * - LIBFDT support
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#ifdef CONFIG_OF_LIBFDT
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
+
+#include "cm5200.h"
+#include "fwupdate.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static hw_id_t hw_id;
+
+
+#ifndef CONFIG_SYS_RAMBOOT
+/*
+ * Helper function to initialize SDRAM controller.
+ */
+static void sdram_start(int hi_addr, mem_conf_t *mem_conf)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000000 |
+ hi_addr_bit;
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000002 |
+ hi_addr_bit;
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
+ hi_addr_bit;
+
+ /* auto refresh, second time */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
+ hi_addr_bit;
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = mem_conf->mode;
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit;
+}
+#endif /* CONFIG_SYS_RAMBOOT */
+
+
+/*
+ * Retrieve memory configuration for a given module. board_type is the index
+ * in hw_id_list[] corresponding to the module we are executing on; we return
+ * SDRAM controller settings approprate for this module.
+ */
+static mem_conf_t* get_mem_config(int board_type)
+{
+ switch(board_type){
+ case CM1_QA:
+ return memory_config[0];
+ case CM11_QA:
+ case CMU1_QA:
+ return memory_config[1];
+ default:
+ printf("ERROR: Unknown module, using a default SDRAM "
+ "configuration - things may not work!!!.\n");
+ return memory_config[0];
+ }
+}
+
+
+/*
+ * Initalize SDRAM - configure SDRAM controller, detect memory size.
+ */
+phys_size_t initdram(int board_type)
+{
+ ulong dramsize = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+ mem_conf_t *mem_conf;
+
+ mem_conf = get_mem_config(board_type);
+
+ /* configure SDRAM start/end for detection */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = mem_conf->config1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2;
+
+ sdram_start(0, mem_conf);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1, mem_conf);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0, mem_conf);
+ dramsize = test1;
+ } else
+ dramsize = test2;
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+ __builtin_ffs(dramsize >> 20) - 1;
+ } else
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+#else /* CONFIG_SYS_RAMBOOT */
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13)
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ else
+ dramsize = 0;
+#endif /* !CONFIG_SYS_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of
+ * the MPC5200B User's Manual.
+ */
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+
+ return dramsize;
+}
+
+
+/*
+ * Read module hardware identification data from the I2C EEPROM.
+ */
+static void read_hw_id(hw_id_t hw_id)
+{
+ int i;
+ for (i = 0; i < HW_ID_ELEM_COUNT; ++i)
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM,
+ hw_id_format[i].offset,
+ 2,
+ (uchar *)&hw_id[i][0],
+ hw_id_format[i].length) != 0)
+ printf("ERROR: can't read HW ID from EEPROM\n");
+}
+
+
+/*
+ * Identify module we are running on, set gd->board_type to the index in
+ * hw_id_list[] corresponding to the module identifed, or to
+ * CM5200_UNKNOWN_MODULE if we can't identify the module.
+ */
+static void identify_module(hw_id_t hw_id)
+{
+ int i, j, element;
+ char match;
+ gd->board_type = CM5200_UNKNOWN_MODULE;
+ for (i = 0; i < sizeof (hw_id_list) / sizeof (char **); ++i) {
+ match = 1;
+ for (j = 0; j < sizeof (hw_id_identify) / sizeof (int); ++j) {
+ element = hw_id_identify[j];
+ if (strncmp(hw_id_list[i][element],
+ &hw_id[element][0],
+ hw_id_format[element].length) != 0) {
+ match = 0;
+ break;
+ }
+ }
+ if (match) {
+ gd->board_type = i;
+ break;
+ }
+ }
+}
+
+
+/*
+ * Compose string with module name.
+ * buf is assumed to have enough space, and be null-terminated.
+ */
+static void compose_module_name(hw_id_t hw_id, char *buf)
+{
+ char tmp[MODULE_NAME_MAXLEN];
+ strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
+ strncat(buf, ".", 1);
+ strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
+ strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
+ strncat(buf, " (", 2);
+ strncat(buf, &hw_id[IDENTIFICATION_NUMBER][0],
+ hw_id_format[IDENTIFICATION_NUMBER].length);
+ sprintf(tmp, " / %u.%u)",
+ hw_id[MAJOR_SW_VERSION][0],
+ hw_id[MINOR_SW_VERSION][0]);
+ strcat(buf, tmp);
+}
+
+
+/*
+ * Compose string with hostname.
+ * buf is assumed to have enough space, and be null-terminated.
+ */
+static void compose_hostname(hw_id_t hw_id, char *buf)
+{
+ char *p;
+ strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
+ strncat(buf, "_", 1);
+ strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
+ strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
+ for (p = buf; *p; ++p)
+ *p = tolower(*p);
+
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+/*
+ * Update 'model' and 'memory' properties in the blob according to the module
+ * that we are running on.
+ */
+static void ft_blob_update(void *blob, bd_t *bd)
+{
+ int len, ret, nodeoffset = 0;
+ char module_name[MODULE_NAME_MAXLEN] = {0};
+
+ compose_module_name(hw_id, module_name);
+ len = strlen(module_name) + 1;
+
+ ret = fdt_setprop(blob, nodeoffset, "model", module_name, len);
+ if (ret < 0)
+ printf("ft_blob_update(): cannot set /model property err:%s\n",
+ fdt_strerror(ret));
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+
+
+/*
+ * Read HW ID from I2C EEPROM and detect the modue we are running on. Note
+ * that we need to use local variable for readout, because global data is not
+ * writable yet (and we'll have to redo the readout later on).
+ */
+int checkboard(void)
+{
+ hw_id_t hw_id_tmp;
+ char module_name_tmp[MODULE_NAME_MAXLEN] = "";
+
+ /*
+ * We need I2C to access HW ID data from EEPROM, so we call i2c_init()
+ * here despite the fact that it will be called again later on. We
+ * also use a little trick to silence I2C-related output.
+ */
+ gd->flags |= GD_FLG_SILENT;
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ gd->flags &= ~GD_FLG_SILENT;
+
+ read_hw_id(hw_id_tmp);
+ identify_module(hw_id_tmp); /* this sets gd->board_type */
+ compose_module_name(hw_id_tmp, module_name_tmp);
+
+ if (gd->board_type != CM5200_UNKNOWN_MODULE)
+ printf("Board: %s\n", module_name_tmp);
+ else
+ printf("Board: unrecognized cm5200 module (%s)\n",
+ module_name_tmp);
+
+ return 0;
+}
+
+
+int board_early_init_r(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write access for detection
+ * process. Note that CS_BOOT cannot be cleared when executing in
+ * flash.
+ */
+ *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+
+ /* Now that we can write to global data, read HW ID again. */
+ read_hw_id(hw_id);
+ return 0;
+}
+
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+ uchar buf[6];
+ char str[18];
+ char hostname[MODULE_NAME_MAXLEN];
+
+ /* Read ethaddr from EEPROM */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) {
+ sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X",
+ buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ /* Check if MAC addr is owned by Schindler */
+ if (strstr(str, "00:06:C3") != str)
+ printf(LOG_PREFIX "Warning - Illegal MAC address (%s)"
+ " in EEPROM.\n", str);
+ else {
+ printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n",
+ str);
+ setenv("ethaddr", str);
+ }
+ } else {
+ printf(LOG_PREFIX "Warning - Unable to read MAC from I2C"
+ " device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM,
+ CONFIG_MAC_OFFSET);
+ }
+#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) */
+ if (!getenv("ethaddr"))
+ printf(LOG_PREFIX "MAC address not set, networking is not "
+ "operational\n");
+
+ /* set the hostname appropriate to the module we're running on */
+ hostname[0] = 0x00;
+ compose_hostname(hw_id, hostname);
+ setenv("hostname", hostname);
+
+ return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+
+#ifdef CONFIG_LAST_STAGE_INIT
+int last_stage_init(void)
+{
+#ifdef CONFIG_USB_STORAGE
+ cm5200_fwupdate();
+#endif /* CONFIG_USB_STORAGE */
+ return 0;
+}
+#endif /* CONFIG_LAST_STAGE_INIT */
+
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ ft_blob_update(blob, bd);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/cm5200/cm5200.h b/board/cm5200/cm5200.h
new file mode 100644
index 0000000..c2573f3
--- /dev/null
+++ b/board/cm5200/cm5200.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * Author: Bartlomiej Sieka <tur@semihalf.com>
+ * Author: Grzegorz Bernacki <gjb@semihalf.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CM5200_H
+#define _CM5200_H
+
+
+/*
+ * Definitions and declarations for the modules of the cm5200 platform. Mostly
+ * related to reading the hardware identification data (HW ID) from the I2C
+ * EEPROM, detection of the particular module we are executing on, and
+ * appropriate SDRAM controller initialization.
+ */
+
+
+#define CM5200_UNKNOWN_MODULE 0xffffffff
+
+enum {
+ DEVICE_NAME, /* 0 */
+ GENERATION, /* 1 */
+ PCB_NAME, /* 2 */
+ FORM, /* 3 */
+ VERSION, /* 4 */
+ IDENTIFICATION_NUMBER, /* 5 */
+ MAJOR_SW_VERSION, /* 6 */
+ MINOR_SW_VERSION, /* 7 */
+ /* add new alements above this line */
+ HW_ID_ELEM_COUNT /* count */
+};
+
+/*
+ * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition"
+ */
+
+#define DEVICE_NAME_OFFSET 0x02
+#define GENERATION_OFFSET 0x0b
+#define PCB_NAME_OFFSET 0x0c
+#define FORM_OFFSET 0x15
+#define VERSION_OFFSET 0x16
+#define IDENTIFICATION_NUMBER_OFFSET 0x19
+#define MAJOR_SW_VERSION_OFFSET 0x0480
+#define MINOR_SW_VERSION_OFFSET 0x0481
+
+
+#define DEVICE_NAME_LEN 0x09
+#define GENERATION_LEN 0x01
+#define PCB_NAME_LEN 0x09
+#define FORM_LEN 0x01
+#define VERSION_LEN 0x03
+#define IDENTIFICATION_NUMBER_LEN 0x09
+#define MAJOR_SW_VERSION_LEN 0x01
+#define MINOR_SW_VERSION_LEN 0x01
+
+#define HW_ID_ELEM_MAXLEN 0x09 /* MAX(XXX_LEN) */
+
+/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */
+#define MODULE_NAME_MAXLEN 64
+
+
+/* storage for HW ID read from EEPROM */
+typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN];
+
+
+/* HW ID layout in EEPROM */
+static struct {
+ unsigned int offset;
+ unsigned int length;
+} hw_id_format[HW_ID_ELEM_COUNT] = {
+ {DEVICE_NAME_OFFSET, DEVICE_NAME_LEN},
+ {GENERATION_OFFSET, GENERATION_LEN},
+ {PCB_NAME_OFFSET, PCB_NAME_LEN},
+ {FORM_OFFSET, FORM_LEN},
+ {VERSION_OFFSET, VERSION_LEN},
+ {IDENTIFICATION_NUMBER_OFFSET, IDENTIFICATION_NUMBER_LEN},
+ {MAJOR_SW_VERSION_OFFSET, MAJOR_SW_VERSION_LEN},
+ {MINOR_SW_VERSION_OFFSET, MINOR_SW_VERSION_LEN},
+};
+
+
+/* HW ID data found in EEPROM on supported modules */
+static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = {
+ "CM", /* DEVICE_NAME */
+ "1", /* GENERATION */
+ "CM1", /* PCB_NAME */
+ "Q", /* FORM */
+ "A", /* VERSION */
+ "591881", /* IDENTIFICATION_NUMBER */
+ "", /* MAJOR_SW_VERSION */
+ "", /* MINOR_SW_VERSION */
+};
+
+static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = {
+ "CM", /* DEVICE_NAME */
+ "1", /* GENERATION */
+ "CM11", /* PCB_NAME */
+ "Q", /* FORM */
+ "A", /* VERSION */
+ "594200", /* IDENTIFICATION_NUMBER */
+ "", /* MAJOR_SW_VERSION */
+ "", /* MINOR_SW_VERSION */
+};
+
+static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = {
+ "CMU", /* DEVICE_NAME */
+ "1", /* GENERATION */
+ "CMU1", /* PCB_NAME */
+ "Q", /* FORM */
+ "A", /* VERSION */
+ "594128", /* IDENTIFICATION_NUMBER */
+ "", /* MAJOR_SW_VERSION */
+ "", /* MINOR_SW_VERSION */
+};
+
+
+/* list of known modules */
+static char **hw_id_list[] = {
+ cm1_qa_hw_id,
+ cm11_qa_hw_id,
+ cmu1_qa_hw_id,
+};
+
+/* indices to the above list - keep in sync */
+enum {
+ CM1_QA,
+ CM11_QA,
+ CMU1_QA,
+};
+
+
+/* identify modules based on these hw id elements */
+static int hw_id_identify[] = {
+ PCB_NAME,
+ FORM,
+ VERSION,
+};
+
+
+/* Registers' settings for SDRAM controller intialization */
+typedef struct {
+ ulong mode;
+ ulong control;
+ ulong config1;
+ ulong config2;
+} mem_conf_t;
+
+static mem_conf_t k4s561632E = {
+ 0x00CD0000, /* CASL 3, burst length 8 */
+ 0x514F0000,
+ 0xE2333900,
+ 0x8EE70000
+};
+
+static mem_conf_t mt48lc32m16a2 = {
+ 0x00CD0000, /* CASL 3, burst length 8 */
+ 0x514F0000,
+ 0xD2322800,
+ 0x8AD70000
+};
+
+static mem_conf_t* memory_config[] = {
+ &k4s561632E,
+ &mt48lc32m16a2
+};
+
+#endif /* _CM5200_H */
diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c
new file mode 100644
index 0000000..9c40ad7
--- /dev/null
+++ b/board/cm5200/cmd_cm5200.c
@@ -0,0 +1,432 @@
+/*
+ * (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com>
+ *
+ * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <usb.h>
+
+#ifdef CONFIG_CMD_BSP
+
+static int do_i2c_test(char * const argv[])
+{
+ unsigned char temp, temp1;
+
+ printf("Starting I2C Test\n"
+ "Please set Jumper:\nI2C SDA 2-3\nI2C SCL 2-3\n\n"
+ "Please press any key to start\n\n");
+ getc();
+
+ temp = 0xf0; /* set io 0-4 as output */
+ i2c_write(CONFIG_SYS_I2C_IO, 3, 1, (uchar *)&temp, 1);
+
+ printf("Press I2C4-7. LED I2C0-3 should have the same state\n\n"
+ "Press any key to stop\n\n");
+
+ while (!tstc()) {
+ i2c_read(CONFIG_SYS_I2C_IO, 0, 1, (uchar *)&temp, 1);
+ temp1 = (temp >> 4) & 0x03;
+ temp1 |= (temp >> 3) & 0x08; /* S302 -> LED303 */
+ temp1 |= (temp >> 5) & 0x04; /* S303 -> LED302 */
+ temp = temp1;
+ i2c_write(CONFIG_SYS_I2C_IO, 1, 1, (uchar *)&temp, 1);
+ }
+ getc();
+
+ return 0;
+}
+
+static int do_usb_test(char * const argv[])
+{
+ int i;
+ static int usb_stor_curr_dev = -1; /* current device */
+
+ printf("Starting USB Test\n"
+ "Please insert USB Memmory Stick\n\n"
+ "Please press any key to start\n\n");
+ getc();
+
+ usb_stop();
+ printf("(Re)start USB...\n");
+ i = usb_init();
+#ifdef CONFIG_USB_STORAGE
+ /* try to recognize storage devices immediately */
+ if (i >= 0)
+ usb_stor_curr_dev = usb_stor_scan(1);
+#endif /* CONFIG_USB_STORAGE */
+ if (usb_stor_curr_dev >= 0)
+ printf("Found USB Storage Dev continue with Test...\n");
+ else {
+ printf("No USB Storage Device detected.. Stop Test\n");
+ return 1;
+ }
+
+ usb_stor_info();
+
+ printf("stopping USB..\n");
+ usb_stop();
+
+ return 0;
+}
+
+static int do_led_test(char * const argv[])
+{
+ int i = 0;
+ struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+ printf("Starting LED Test\n"
+ "Please set Switch S500 all off\n\n"
+ "Please press any key to start\n\n");
+ getc();
+
+ /* configure timer 2-3 for simple GPIO output High */
+ gpt->gpt2.emsr |= 0x00000034;
+ gpt->gpt3.emsr |= 0x00000034;
+
+ (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000;
+ (*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000;
+ printf("Please press any key to stop\n\n");
+ while (!tstc()) {
+ if (i == 1) {
+ (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
+ gpt->gpt2.emsr &= ~0x00000010;
+ gpt->gpt3.emsr &= ~0x00000010;
+ } else if (i == 2) {
+ (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
+ gpt->gpt2.emsr &= ~0x00000010;
+ gpt->gpt3.emsr |= 0x00000010;
+ } else if (i >= 3) {
+ (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
+ gpt->gpt3.emsr &= ~0x00000010;
+ gpt->gpt2.emsr |= 0x00000010;
+ i = 0;
+ }
+ i++;
+ udelay(200000);
+ }
+ getc();
+
+ (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
+ gpt->gpt2.emsr |= 0x00000010;
+ gpt->gpt3.emsr |= 0x00000010;
+
+ return 0;
+}
+
+static int do_rs232_test(char * const argv[])
+{
+ int error_status = 0;
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+ /* Configure PSC 2-3-6 as GPIO */
+ gpio->port_config &= 0xFF0FF80F;
+
+ switch (simple_strtoul(argv[2], NULL, 10)) {
+ case 1:
+ /* check RTS <-> CTS loop */
+ /* set rts to 0 */
+ printf("Uart 1 test: RX TX tested by using U-Boot\n"
+ "Please connect RTS with CTS on Uart1 plug\n\n"
+ "Press any key to start\n\n");
+ getc();
+
+ psc1->op1 |= 0x01;
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ /* check status at cts */
+ if ((psc1->ip & 0x01) != 0) {
+ error_status = 3;
+ printf("%s: failure at rs232_1, cts status is %d "
+ "(should be 0)\n",
+ __FUNCTION__, (psc1->ip & 0x01));
+ }
+
+ /* set rts to 1 */
+ psc1->op0 |= 0x01;
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ /* check status at cts */
+ if ((psc1->ip & 0x01) != 1) {
+ error_status = 3;
+ printf("%s: failure at rs232_1, cts status is %d "
+ "(should be 1)\n",
+ __FUNCTION__, (psc1->ip & 0x01));
+ }
+ break;
+ case 2:
+ /* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */
+ printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n"
+ "\nPress any key to start\n\n");
+ getc();
+
+ gpio->simple_gpioe &= ~(0x000000F0);
+ gpio->simple_gpioe |= 0x000000F0;
+ gpio->simple_ddr &= ~(0x000000F0);
+ gpio->simple_ddr |= 0x00000050;
+
+ /* check TXD <-> RXD loop */
+ /* set TXD to 1 */
+ gpio->simple_dvo |= (1 << 4);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000020) != 0x00000020) {
+ error_status = 2;
+ printf("%s: failure at rs232_2, rxd status is %d "
+ "(should be 1)\n", __FUNCTION__,
+ (gpio->simple_ival & 0x00000020) >> 5);
+ }
+
+ /* set TXD to 0 */
+ gpio->simple_dvo &= ~(1 << 4);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000020) != 0x00000000) {
+ error_status = 2;
+ printf("%s: failure at rs232_2, rxd status is %d "
+ "(should be 0)\n", __FUNCTION__,
+ (gpio->simple_ival & 0x00000020) >> 5);
+ }
+
+ /* check RTS <-> CTS loop */
+ /* set RTS to 1 */
+ gpio->simple_dvo |= (1 << 6);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000080) != 0x00000080) {
+ error_status = 3;
+ printf("%s: failure at rs232_2, cts status is %d "
+ "(should be 1)\n", __FUNCTION__,
+ (gpio->simple_ival & 0x00000080) >> 7);
+ }
+
+ /* set RTS to 0 */
+ gpio->simple_dvo &= ~(1 << 6);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000080) != 0x00000000) {
+ error_status = 3;
+ printf("%s: failure at rs232_2, cts status is %d "
+ "(should be 0)\n", __FUNCTION__,
+ (gpio->simple_ival & 0x00000080) >> 7);
+ }
+ break;
+ case 3:
+ /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
+ printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n"
+ "\nPress any key to start\n\n");
+ getc();
+
+ gpio->simple_gpioe &= ~(0x00000F00);
+ gpio->simple_gpioe |= 0x00000F00;
+
+ gpio->simple_ddr &= ~(0x00000F00);
+ gpio->simple_ddr |= 0x00000500;
+
+ /* check TXD <-> RXD loop */
+ /* set TXD to 1 */
+ gpio->simple_dvo |= (1 << 8);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
+ error_status = 2;
+ printf("%s: failure at rs232_3, rxd status is %d "
+ "(should be 1)\n", __FUNCTION__,
+ (gpio->simple_ival & 0x00000200) >> 9);
+ }
+
+ /* set TXD to 0 */
+ gpio->simple_dvo &= ~(1 << 8);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
+ error_status = 2;
+ printf("%s: failure at rs232_3, rxd status is %d "
+ "(should be 0)\n", __FUNCTION__,
+ (gpio->simple_ival & 0x00000200) >> 9);
+ }
+
+ /* check RTS <-> CTS loop */
+ /* set RTS to 1 */
+ gpio->simple_dvo |= (1 << 10);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
+ error_status = 3;
+ printf("%s: failure at rs232_3, cts status is %d "
+ "(should be 1)\n", __FUNCTION__,
+ (gpio->simple_ival & 0x00000800) >> 11);
+ }
+
+ /* set RTS to 0 */
+ gpio->simple_dvo &= ~(1 << 10);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
+ error_status = 3;
+ printf("%s: failure at rs232_3, cts status is %d "
+ "(should be 0)\n", __FUNCTION__,
+ (gpio->simple_ival & 0x00000800) >> 11);
+ }
+ break;
+ case 4:
+ /* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */
+ printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n"
+ "\nPress any key to start\n\n");
+ getc();
+
+ gpio->simple_gpioe &= ~(0xF0000000);
+ gpio->simple_gpioe |= 0x30000000;
+
+ gpio->simple_ddr &= ~(0xf0000000);
+ gpio->simple_ddr |= 0x30000000;
+
+ (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000;
+ (*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000);
+
+ /* check TXD <-> RXD loop */
+ /* set TXD to 1 */
+ gpio->simple_dvo |= (1 << 28);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
+ 0x10000000) {
+ error_status = 2;
+ printf("%s: failure at rs232_4, rxd status is %lu "
+ "(should be 1)\n", __FUNCTION__,
+ ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
+ 0x10000000) >> 28);
+ }
+
+ /* set TXD to 0 */
+ gpio->simple_dvo &= ~(1 << 28);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
+ 0x00000000) {
+ error_status = 2;
+ printf("%s: failure at rs232_4, rxd status is %lu "
+ "(should be 0)\n", __FUNCTION__,
+ ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
+ 0x10000000) >> 28);
+ }
+
+ /* check RTS <-> CTS loop */
+ /* set RTS to 1 */
+ gpio->simple_dvo |= (1 << 29);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
+ 0x20000000) {
+ error_status = 3;
+ printf("%s: failure at rs232_4, cts status is %lu "
+ "(should be 1)\n", __FUNCTION__,
+ ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
+ 0x20000000) >> 29);
+ }
+
+ /* set RTS to 0 */
+ gpio->simple_dvo &= ~(1 << 29);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
+ 0x00000000) {
+ error_status = 3;
+ printf("%s: failure at rs232_4, cts status is %lu "
+ "(should be 0)\n", __FUNCTION__,
+ ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
+ 0x20000000) >> 29);
+ }
+ break;
+ default:
+ printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
+ error_status = 1;
+ break;
+ }
+ gpio->port_config |= (CONFIG_SYS_GPS_PORT_CONFIG & 0xFF0FF80F);
+
+ return error_status;
+}
+
+static int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rcode = -1;
+
+ switch (argc) {
+ case 2:
+ if (strncmp(argv[1], "i2c", 3) == 0)
+ rcode = do_i2c_test(argv);
+ else if (strncmp(argv[1], "led", 3) == 0)
+ rcode = do_led_test(argv);
+ else if (strncmp(argv[1], "usb", 3) == 0)
+ rcode = do_usb_test(argv);
+ break;
+ case 3:
+ if (strncmp(argv[1], "rs232", 3) == 0)
+ rcode = do_rs232_test(argv);
+ break;
+ }
+
+ switch (rcode) {
+ case -1:
+ printf("Usage:\n"
+ "fkt { i2c | led | usb }\n"
+ "fkt rs232 number\n");
+ rcode = 1;
+ break;
+ case 0:
+ printf("Test passed\n");
+ break;
+ default:
+ printf("Test failed with code: %d\n", rcode);
+ }
+
+ return rcode;
+}
+
+U_BOOT_CMD(
+ fkt, 4, 1, cmd_fkt,
+ "Function test routines",
+ "i2c\n"
+ " - Test I2C communication\n"
+ "fkt led\n"
+ " - Test LEDs\n"
+ "fkt rs232 number\n"
+ " - Test RS232 (loopback plug(s) for RS232 required)\n"
+ "fkt usb\n"
+ " - Test USB communication"
+);
+#endif /* CONFIG_CMD_BSP */
diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c
new file mode 100644
index 0000000..06d5023
--- /dev/null
+++ b/board/cm5200/fwupdate.c
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2007 Schindler Lift Inc.
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * Author: Michel Marti <mma@objectxp.com>
+ * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>:
+ * - code clean-up
+ * - bugfix for overwriting bootargs by user
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <image.h>
+#include <usb.h>
+#include <fat.h>
+
+#include "fwupdate.h"
+
+extern long do_fat_read(const char *, void *, unsigned long, int);
+extern int do_fat_fsload(cmd_tbl_t *, int, int, char * const []);
+
+static int load_rescue_image(ulong);
+
+void cm5200_fwupdate(void)
+{
+ cmd_tbl_t *bcmd;
+ char *rsargs;
+ char *tmp = NULL;
+ char ka[16];
+ char * const argv[3] = { "bootm", ka, NULL };
+
+ /* Check if rescue system is disabled... */
+ if (getenv("norescue")) {
+ printf(LOG_PREFIX "Rescue System disabled.\n");
+ return;
+ }
+
+ /* Check if we have a USB storage device and load image */
+ if (load_rescue_image(LOAD_ADDR))
+ return;
+
+ bcmd = find_cmd("bootm");
+ if (!bcmd)
+ return;
+
+ sprintf(ka, "%lx", (ulong)LOAD_ADDR);
+
+ /* prepare our bootargs */
+ rsargs = getenv("rs-args");
+ if (!rsargs)
+ rsargs = RS_BOOTARGS;
+ else {
+ tmp = malloc(strlen(rsargs+1));
+ if (!tmp) {
+ printf(LOG_PREFIX "Memory allocation failed\n");
+ return;
+ }
+ strcpy(tmp, rsargs);
+ rsargs = tmp;
+ }
+
+ setenv("bootargs", rsargs);
+
+ if (rsargs == tmp)
+ free(rsargs);
+
+ printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs);
+ do_bootm(bcmd, 0, 2, argv);
+}
+
+static int load_rescue_image(ulong addr)
+{
+ disk_partition_t info;
+ int devno;
+ int partno;
+ int i;
+ char fwdir[64];
+ char nxri[128];
+ char *tmp;
+ char dev[7];
+ char addr_str[16];
+ char * const argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL };
+ block_dev_desc_t *stor_dev = NULL;
+ cmd_tbl_t *bcmd;
+
+ /* Get name of firmware directory */
+ tmp = getenv("fw-dir");
+
+ /* Copy it into fwdir */
+ strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir));
+ fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */
+
+ printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB"
+ " storage...\n", fwdir);
+ usb_stop();
+ if (usb_init() != 0)
+ return 1;
+
+ /* Check for storage device */
+ if (usb_stor_scan(1) != 0) {
+ usb_stop();
+ return 1;
+ }
+
+ /* Detect storage device */
+ for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) {
+ stor_dev = usb_stor_get_dev(devno);
+ if (stor_dev->type != DEV_TYPE_UNKNOWN)
+ break;
+ }
+ if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) {
+ printf(LOG_PREFIX "No valid storage device found...\n");
+ usb_stop();
+ return 1;
+ }
+
+ /* Detect partition */
+ for (partno = -1, i = 0; i < 6; i++) {
+ if (get_partition_info(stor_dev, i, &info) == 0) {
+ if (fat_register_device(stor_dev, i) == 0) {
+ /* Check if rescue image is present */
+ FW_DEBUG("Looking for firmware directory '%s'"
+ " on partition %d\n", fwdir, i);
+ if (do_fat_read(fwdir, NULL, 0, LS_NO) == -1) {
+ FW_DEBUG("No NX rescue image on "
+ "partition %d.\n", i);
+ partno = -2;
+ } else {
+ partno = i;
+ FW_DEBUG("Partition %d contains "
+ "firmware directory\n", partno);
+ break;
+ }
+ }
+ }
+ }
+
+ if (partno < 0) {
+ switch (partno) {
+ case -1:
+ printf(LOG_PREFIX "Error: No valid (FAT) partition "
+ "detected\n");
+ break;
+ case -2:
+ printf(LOG_PREFIX "Error: No NX rescue image on FAT "
+ "partition\n");
+ break;
+ default:
+ printf(LOG_PREFIX "Error: Failed with code %d\n",
+ partno);
+ }
+ usb_stop();
+ return 1;
+ }
+
+ /* Load the rescue image */
+ bcmd = find_cmd("fatload");
+ if (!bcmd) {
+ printf(LOG_PREFIX "Error - 'fatload' command not present.\n");
+ usb_stop();
+ return 1;
+ }
+
+ tmp = getenv("nx-rescue-image");
+ sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE);
+ sprintf(dev, "%d:%d", devno, partno);
+ sprintf(addr_str, "%lx", addr);
+
+ FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n",
+ dev, addr_str, nxri);
+
+ if (do_fat_fsload(bcmd, 0, 5, argv) != 0) {
+ usb_stop();
+ return 1;
+ }
+
+ /* Stop USB */
+ usb_stop();
+ return 0;
+}
diff --git a/board/cm5200/fwupdate.h b/board/cm5200/fwupdate.h
new file mode 100644
index 0000000..6ddf0ba
--- /dev/null
+++ b/board/cm5200/fwupdate.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007 Schindler Lift Inc.
+ *
+ * Author: Michel Marti <mma@objectxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FW_UPDATE_H
+#define __FW_UPDATE_H
+
+/* Default prefix for output messages */
+#define LOG_PREFIX "CM5200:"
+
+/* Extra debug macro */
+#ifdef CONFIG_FWUPDATE_DEBUG
+#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt)
+#else
+#define FW_DEBUG(fmt...)
+#endif
+
+/* Name of the directory holding firmware images */
+#define FW_DIR "nx-fw"
+#define RESCUE_IMAGE "nxrs.img"
+#define LOAD_ADDR 0x400000
+#define RS_BOOTARGS "ramdisk_size=8192K"
+
+/* Main function for fwupdate */
+void cm5200_fwupdate(void);
+
+#endif /* __FW_UPDATE_H */
diff --git a/board/cmi/Kconfig b/board/cmi/Kconfig
new file mode 100644
index 0000000..6efe6b1
--- /dev/null
+++ b/board/cmi/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_CMI_MPC5XX
+
+config SYS_BOARD
+ default "cmi"
+
+config SYS_CONFIG_NAME
+ default "cmi_mpc5xx"
+
+endif
diff --git a/board/cmi/MAINTAINERS b/board/cmi/MAINTAINERS
new file mode 100644
index 0000000..60701bf
--- /dev/null
+++ b/board/cmi/MAINTAINERS
@@ -0,0 +1,6 @@
+CMI BOARD
+#M: -
+S: Maintained
+F: board/cmi/
+F: include/configs/cmi_mpc5xx.h
+F: configs/cmi_mpc5xx_defconfig
diff --git a/board/cmi/Makefile b/board/cmi/Makefile
new file mode 100644
index 0000000..cd3bb0d
--- /dev/null
+++ b/board/cmi/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := flash.o cmi.o
diff --git a/board/cmi/README b/board/cmi/README
new file mode 100644
index 0000000..0edd50a
--- /dev/null
+++ b/board/cmi/README
@@ -0,0 +1,84 @@
+
+Summary:
+========
+
+This file contains information about the cmi board configuration.
+Please see cmi_mpc5xx_config for further details. The cmi board is
+a customer specific board but should work with small modifications
+on every board which has a MPC5xx and either a 28F128J3A,
+28F320J3A or 28F640J3A Intel flash mounted.
+
+Board Discription:
+==================
+
+* Motorola MPC555
+* RS232 connection
+* Intel flash 28F640J3A
+* Micron SRAM 1M
+* Altera PLD
+
+Bootstrap:
+==========
+
+In contrast to the usual boot sequence used in U-Boot, on the
+cmi board we don't boot from the external flash directly.
+Because of we use a 16-bit flash and don't sample a RCW
+from the data bus to set the startup buswidth to 16-bit.
+Unfortunatly the default width, sampled from the default RCW
+is 32-bit. For this reason we burn the proper RCW into the
+internal flash shadow location and boot after power-on or
+reset from the internal flash and then branch to 0x02000100
+where the U-Boot reset vector handler is located.
+
+Memory Map:
+===========
+
+Memory Map after relocation:
+
+ 0x0000 0000 CONFIG_SYS_SDRAM_BASE
+ :
+ 0x000F 9FFF
+ :
+ :
+ 0x0100 0000 CONFIG_SYS_IMMR (Internal memory map base adress)
+ :
+ 0x0130 7FFF
+ :
+ :
+ 0x0200 0000 CONFIG_SYS_FLASH_BASE
+ :
+ 0x027C FFFF
+ :
+ :
+ 0x0300 0000 PLD_BASE
+
+Flash Partition:
+
+ 0x0200 0000 Block 0 and 1 contain U-Boot except
+ : environment
+ :
+ 0x0201 FFFF
+ 0x0202 0000 Block 2 contains environment (.ppcenv)
+ :
+ 0x0202 FFFF
+
+See README file for futher information about U-Boot relocation
+and partitioning.
+
+Tested Features:
+================
+
+* U-Boot commands: go, loads, loadb, all memory features, printenv,
+ setenv, saveenv, protect, erase, fli, bdi, mtest, reset, version,
+ coninfo, help (see configuration file for available commands)
+
+* Blinking led to indicate boot process
+
+Added or Changed Files:
+=======================
+
+u-boot-0.2.0/board/cmi/*
+u-boot-0.2.0/include/configs/cmi_mpc5xx.h
+
+Regards,
+Martin
diff --git a/board/cmi/cmi.c b/board/cmi/cmi.c
new file mode 100644
index 0000000..37028c3
--- /dev/null
+++ b/board/cmi/cmi.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * File: cmi.c
+ *
+ * Discription: For generic board specific functions
+ *
+ */
+
+
+#include <common.h>
+#include <mpc5xx.h>
+
+#define SRAM_SIZE 1024000L /* 1M RAM available*/
+
+#if defined(__APPLE__)
+/* Leading underscore on symbols */
+# define SYM_CHAR "_"
+#else /* No leading character on symbols */
+# define SYM_CHAR
+#endif
+
+/*
+ * Macros to generate global absolutes.
+ */
+#define GEN_SYMNAME(str) SYM_CHAR #str
+#define GEN_VALUE(str) #str
+#define GEN_ABS(name, value) \
+ asm (".globl " GEN_SYMNAME(name)); \
+ asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
+
+/*
+ * Check the board
+ */
+int checkboard(void)
+{
+ puts ("Board: ### No HW ID - assuming CMI board\n");
+ return (0);
+}
+
+/*
+ * Get RAM size.
+ */
+phys_size_t initdram(int board_type)
+{
+ return (SRAM_SIZE); /* We currently have a static size adapted for cmi board. */
+}
+
+/*
+ * Absolute environment address for linker file.
+ */
+GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE);
diff --git a/board/cmi/flash.c b/board/cmi/flash.c
new file mode 100644
index 0000000..d9986f9
--- /dev/null
+++ b/board/cmi/flash.c
@@ -0,0 +1,501 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * File: flash.c
+ *
+ * Discription: This Driver is for 28F320J3A, 28F640J3A and
+ * 28F128J3A Intel flashs working in 16 Bit mode.
+ * They are single bank flashs.
+ *
+ * Most of this code is taken from existing u-boot
+ * source code.
+ */
+
+
+#include <common.h>
+#include <mpc5xx.h>
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef CONFIG_ENV_ADDR
+# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef CONFIG_ENV_SIZE
+# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef CONFIG_ENV_SECT_SIZE
+# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+# endif
+#endif
+
+#define FLASH_ID_MASK 0xFFFF
+#define FLASH_BLOCK_SIZE 0x00010000
+#define FLASH_CMD_READ_ID 0x0090
+#define FLASH_CMD_RESET 0x00ff
+#define FLASH_CMD_BLOCK_ERASE 0x0020
+#define FLASH_CMD_ERASE_CONFIRM 0x00D0
+#define FLASH_CMD_CLEAR_STATUS 0x0050
+#define FLASH_CMD_SUSPEND_ERASE 0x00B0
+#define FLASH_CMD_WRITE 0x0040
+#define FLASH_CMD_PROTECT 0x0060
+#define FLASH_CMD_PROTECT_SET 0x0001
+#define FLASH_CMD_PROTECT_CLEAR 0x00D0
+#define FLASH_STATUS_DONE 0x0080
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*
+ * Local function prototypes
+ */
+static ulong flash_get_size (vu_short *addr, flash_info_t *info);
+static int write_short (flash_info_t *info, ulong dest, ushort data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*
+ * Initialize flash
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+#if 1
+ debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
+#endif
+ size_b0 = flash_get_size((vu_short *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0: "
+ "ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+ flash_info[0].flash_id,
+ size_b0, size_b0<<20);
+ }
+
+ flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+ &flash_info[0]);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+ &flash_info[0]);
+#endif
+
+ return size_b0;
+}
+
+/*
+ * Compute start adress of each sector (block)
+ */
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + i * FLASH_BLOCK_SIZE;
+ }
+ return;
+
+ default:
+ printf ("Don't know sector offsets for flash type 0x%lx\n",
+ info->flash_id);
+ return;
+ }
+}
+
+/*
+ * Print flash information
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("Fujitsu "); break;
+ case FLASH_MAN_SST: printf ("SST "); break;
+ case FLASH_MAN_STM: printf ("STM "); break;
+ case FLASH_MAN_INTEL: printf ("Intel "); break;
+ case FLASH_MAN_MT: printf ("MT "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F320J3A: printf ("28F320J3A (32Mbit) 16-Bit\n");
+ break;
+ case FLASH_28F640J3A: printf ("28F640J3A (64Mbit) 16-Bit\n");
+ break;
+ case FLASH_28F128J3A: printf ("28F128J3A (128Mbit) 16-Bit\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ if (info->size >= (1 << 20)) {
+ i = 20;
+ } else {
+ i = 10;
+ }
+ printf (" Size: %ld %cB in %d Sectors\n",
+ info->size >> i,
+ (i == 20) ? 'M' : 'k',
+ info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*
+ * Get size of flash in bytes.
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_short *addr, flash_info_t *info)
+{
+ vu_short value;
+
+ /* Read Manufacturer ID */
+ addr[0] = FLASH_CMD_READ_ID;
+ value = addr[0];
+
+ switch (value) {
+ case (AMD_MANUFACT & FLASH_ID_MASK):
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (FUJ_MANUFACT & FLASH_ID_MASK):
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (SST_MANUFACT & FLASH_ID_MASK):
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (STM_MANUFACT & FLASH_ID_MASK):
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ case (INTEL_MANUFACT & FLASH_ID_MASK):
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ addr[0] = FLASH_CMD_RESET; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr[1]; /* device ID */
+
+ switch (value) {
+ case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
+ info->flash_id += FLASH_28F320J3A;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ break; /* => 32 MBit */
+
+ case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+ info->flash_id += FLASH_28F640J3A;
+ info->sector_count = 64;
+ info->size = 0x00800000;
+ break; /* => 64 MBit */
+
+ case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+ info->flash_id += FLASH_28F128J3A;
+ info->sector_count = 128;
+ info->size = 0x01000000;
+ break; /* => 128 MBit */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ addr[0] = FLASH_CMD_RESET; /* restore read mode */
+ return (0); /* => no or unknown flash */
+
+ }
+
+ if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ }
+
+ addr[0] = FLASH_CMD_RESET; /* restore read mode */
+
+ return (info->size);
+}
+
+
+/*
+ * Erase unprotected sectors
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+ printf ("Can erase only Intel flash types - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ start = get_timer (0);
+ last = start;
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_short *addr = (vu_short *)(info->start[sect]);
+ unsigned long status;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+#ifdef DEBUG
+ printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]);
+#endif
+
+ *addr = FLASH_CMD_CLEAR_STATUS;
+ *addr = FLASH_CMD_BLOCK_ERASE;
+ *addr = FLASH_CMD_ERASE_CONFIRM;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) {
+ if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Flash erase timeout at address %lx\n", info->start[sect]);
+ *addr = FLASH_CMD_SUSPEND_ERASE;
+ *addr = FLASH_CMD_RESET;
+ return 1;
+ }
+
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+ *addr = FLASH_CMD_RESET;
+ }
+ }
+ printf (" done\n");
+ return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ ushort data;
+ int i, rc;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return 4;
+ }
+
+ wp = (addr & ~1); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start byte
+ */
+
+ if (addr - wp) {
+ data = 0;
+ data = (data << 8) | *src++;
+ --cnt;
+ if ((rc = write_short(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 2;
+ }
+
+ /*
+ * handle word aligned part
+ */
+
+ while (cnt >= 2) {
+ data = 0;
+ for (i=0; i<2; ++i) {
+ data = (data << 8) | *src++;
+ }
+
+ if ((rc = write_short(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 2;
+ cnt -= 2;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+
+ data = 0;
+ for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<2; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_short(info, wp, data));
+
+}
+
+/*
+ * Write 16 bit (short) to flash
+ */
+
+static int write_short (flash_info_t *info, ulong dest, ushort data)
+{
+ vu_short *addr = (vu_short*)(info->start[0]);
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_short *)dest) & data) != data) {
+ return (2);
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ if (!(info->flash_id & FLASH_VENDMASK)) {
+ return 4;
+ }
+ *addr = FLASH_CMD_ERASE_CONFIRM;
+ *addr = FLASH_CMD_WRITE;
+
+ *((vu_short *)dest) = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag) {
+ enable_interrupts();
+ }
+
+ /* data polling for D7 */
+ start = get_timer (0);
+
+ /* wait for error or finish */
+ while(!(addr[0] & FLASH_STATUS_DONE)){
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ addr[0] = FLASH_CMD_RESET;
+ return (1);
+ }
+ }
+
+ *addr = FLASH_CMD_RESET;
+ return (0);
+}
+
+/*
+ * Protects a flash sector
+ */
+
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+ vu_short *addr = (vu_short*)(info->start[sector]);
+ ulong start;
+
+ *addr = FLASH_CMD_CLEAR_STATUS;
+ *addr = FLASH_CMD_PROTECT;
+
+ if(prot) {
+ *addr = FLASH_CMD_PROTECT_SET;
+ } else {
+ *addr = FLASH_CMD_PROTECT_CLEAR;
+ }
+
+ /* wait for error or finish */
+ start = get_timer (0);
+ while(!(addr[0] & FLASH_STATUS_DONE)){
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Flash protect timeout at address %lx\n", info->start[sector]);
+ addr[0] = FLASH_CMD_RESET;
+ return (1);
+ }
+ }
+ /* Set software protect flag */
+ info->protect[sector] = prot;
+ *addr = FLASH_CMD_RESET;
+ return (0);
+}
diff --git a/board/cobra5272/Kconfig b/board/cobra5272/Kconfig
new file mode 100644
index 0000000..ba04622
--- /dev/null
+++ b/board/cobra5272/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_COBRA5272
+
+config SYS_CPU
+ default "mcf52x2"
+
+config SYS_BOARD
+ default "cobra5272"
+
+config SYS_CONFIG_NAME
+ default "cobra5272"
+
+endif
diff --git a/board/cobra5272/MAINTAINERS b/board/cobra5272/MAINTAINERS
new file mode 100644
index 0000000..a064da2
--- /dev/null
+++ b/board/cobra5272/MAINTAINERS
@@ -0,0 +1,6 @@
+COBRA5272 BOARD
+#M: -
+S: Maintained
+F: board/cobra5272/
+F: include/configs/cobra5272.h
+F: configs/cobra5272_defconfig
diff --git a/board/cobra5272/Makefile b/board/cobra5272/Makefile
new file mode 100644
index 0000000..fbbbb87
--- /dev/null
+++ b/board/cobra5272/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cobra5272.o flash.o
diff --git a/board/cobra5272/README b/board/cobra5272/README
new file mode 100644
index 0000000..ae0f148
--- /dev/null
+++ b/board/cobra5272/README
@@ -0,0 +1,156 @@
+File: README.COBRA5272
+Author: Florian Schlote for Sentec elektronik (linux@sentec-elektronik.de)
+Contents: This is the README of u-boot (Universal bootloader) for our
+ COBRA5272 board.
+Version: v01.00
+Date: Tue Mar 30 00:28:33 CEST 2004
+License: This document is published under the GNU GPL
+______________________________________________________________________
+
+CHANGES
+040330 v01.00 Creation
+
+______________________________________________________________________
+
+
+CONFIGURING
+-----------
+
+1. Modify include/configs/cobra5272.h acc. to your prefs
+
+2. If necessary, modify board/cobra5272/config.mk (see below)
+
+3.
+
+> make cobra5272_config
+
+> make
+
+
+Please refer to u-boot README (general info, u-boot-x-x-x/README),
+to u-boot-x-x-x/doc/README.COBRA5272 and
+to the comments in u-boot-x-x-x/include/configs/cobra5272.h
+
+Configuring u-boot is done by commenting/uncommenting preprocessor defines.
+
+Default configuration is
+
+ FLASH version (for further info see subsection below)
+ link address 0xffe00000
+
+ 16 MB RAM
+
+ network enabled
+ no default IP address for target, host set, no MACaddress set
+
+ bootdelay for autoboot 5 sec.
+ autoboot disabled
+
+
+#-----------------------------------
+# u-boot FLASH version & RAM version
+#-----------------------------------
+
+The u-boot bootloader for Coldfire processors can be configured
+
+ 1. as a standalone bootloader residing in flash & relocating itself to RAM on
+ startup automatically => "FLASH version"
+
+ 2. as a RAM version which will not load from flash automatically as it needs a
+ prestage bootloader ("chainloading") & is running only from the RAM address it
+ is linked to => "RAM version"
+
+ This version may be very helpful when installing u-boot for the first time
+ since it can be used to make available s. th. like a "bootstrap
+ mechanism".
+
+
+How to build the different images:
+
+------------------------------
+Flash version
+------------------------------
+
+Compile u-boot
+
+in dir ./u-boot-x-x-x/
+
+please first check:
+
+ in ./include/configs/cobra5272.h
+
+ CONFIG_MONITOR_IS_IN_RAM has to be undefined, e. g. as follows:
+
+ #if 0
+ #define CONFIG_MONITOR_IS_IN_RAM
+ /* define if monitor is started from a pre-loader */
+ #endif
+
+ => u-boot as single bootloader starting from flash
+
+
+ in board/cobra5272/config.mk CONFIG_SYS_TEXT_BASE should be
+
+ CONFIG_SYS_TEXT_BASE = 0xffe00000
+
+ => linking address for u-boot as single bootloader stored in flash
+
+then:
+
+ host> make cobra5272_config
+ rm -f include/config.h include/config.mk
+ Configuring for cobra5272 board...
+ host> make
+ [...]
+
+ host> cp u-boot.bin /tftpboot/u-boot_flash.bin
+
+
+------------------------------
+RAM version
+------------------------------
+
+in dir ./u-boot-x-x-x/
+
+ host> make distclean
+
+please modify the settings:
+
+ in ./include/configs/cobra5272.h
+
+ CONFIG_MONITOR_IS_IN_RAM now has to be defined, e. g. as follows:
+
+ #if 1
+ #define CONFIG_MONITOR_IS_IN_RAM
+ /*define if monitor is started from a pre-loader */
+ #endif
+
+ => u-boot as RAM version, chainloaded by another bootloader or using bdm cable
+
+
+ in board/cobra5272/config.mk CONFIG_SYS_TEXT_BASE should be
+
+ CONFIG_SYS_TEXT_BASE = 0x00020000
+
+ => target linking address for RAM
+
+
+then:
+
+ host> make cobra5272_config
+ rm -f include/config.h include/config.mk
+ Configuring for cobra5272 board...
+ host> make
+ [...]
+
+ host> cp u-boot.bin /tftpboot/u-boot_ram.bin
+
+
+----
+HINT
+----
+
+If the m68k-elf-toolchain & the m68k-bdm-gdb is installed you can run the RAM
+version by typing (in dir ./u-boot-x-x-x/)
+"board/cobra5272/bdm/load-cobra_uboot" ,
+in ./u-boot-x-x-x/ the RAM version u-boot (elf format) has to be available.
diff --git a/board/cobra5272/bdm/cobra5272_uboot.gdb b/board/cobra5272/bdm/cobra5272_uboot.gdb
new file mode 100644
index 0000000..61e778e
--- /dev/null
+++ b/board/cobra5272/bdm/cobra5272_uboot.gdb
@@ -0,0 +1,169 @@
+#
+# GDB Init script for the Coldfire 5272 processor.
+#
+# The main purpose of this script is to configure the
+# DRAM controller so code can be loaded.
+#
+# This file was changed to suite the senTec COBRA5272 board.
+#
+
+define addresses
+
+set $mbar = 0x10000001
+set $scr = $mbar - 1 + 0x004
+set $spr = $mbar - 1 + 0x006
+set $pmr = $mbar - 1 + 0x008
+set $apmr = $mbar - 1 + 0x00e
+set $dir = $mbar - 1 + 0x010
+set $icr1 = $mbar - 1 + 0x020
+set $icr2 = $mbar - 1 + 0x024
+set $icr3 = $mbar - 1 + 0x028
+set $icr4 = $mbar - 1 + 0x02c
+set $isr = $mbar - 1 + 0x030
+set $pitr = $mbar - 1 + 0x034
+set $piwr = $mbar - 1 + 0x038
+set $pivr = $mbar - 1 + 0x03f
+set $csbr0 = $mbar - 1 + 0x040
+set $csor0 = $mbar - 1 + 0x044
+set $csbr1 = $mbar - 1 + 0x048
+set $csor1 = $mbar - 1 + 0x04c
+set $csbr2 = $mbar - 1 + 0x050
+set $csor2 = $mbar - 1 + 0x054
+set $csbr3 = $mbar - 1 + 0x058
+set $csor3 = $mbar - 1 + 0x05c
+set $csbr4 = $mbar - 1 + 0x060
+set $csor4 = $mbar - 1 + 0x064
+set $csbr5 = $mbar - 1 + 0x068
+set $csor5 = $mbar - 1 + 0x06c
+set $csbr6 = $mbar - 1 + 0x070
+set $csor6 = $mbar - 1 + 0x074
+set $csbr7 = $mbar - 1 + 0x078
+set $csor7 = $mbar - 1 + 0x07c
+set $pacnt = $mbar - 1 + 0x080
+set $paddr = $mbar - 1 + 0x084
+set $padat = $mbar - 1 + 0x086
+set $pbcnt = $mbar - 1 + 0x088
+set $pbddr = $mbar - 1 + 0x08c
+set $pbdat = $mbar - 1 + 0x08e
+set $pcddr = $mbar - 1 + 0x094
+set $pcdat = $mbar - 1 + 0x096
+set $pdcnt = $mbar - 1 + 0x098
+set $sdcr = $mbar - 1 + 0x180
+set $sdtr = $mbar - 1 + 0x184
+set $wrrr = $mbar - 1 + 0x280
+set $wirr = $mbar - 1 + 0x283
+set $wcr = $mbar - 1 + 0x288
+set $wer = $mbar - 1 + 0x28c
+
+end
+
+
+#
+# Setup system configuration
+#
+define setup-sys
+set *((unsigned short *) $scr) = 0x0003
+set *((unsigned short *) $spr) = 0xffff
+set *((unsigned char *) $pivr) = 0x4f
+end
+
+
+#
+# Setup Chip Selects (as per Motorola M5272C3 board)
+#
+define setup-cs
+
+# CS0 -- FLASH
+set *((unsigned long *) $csbr0) = 0xffe00201
+set *((unsigned long *) $csor0) = 0xffe00014
+
+# CS1 -- external bus test
+set *((unsigned long *) $csbr1) = 0x0
+set *((unsigned long *) $csor1) = 0x0
+
+# CS2 -- Optional FSRAM
+set *((unsigned long *) $csbr2) = 0x30000001
+set *((unsigned long *) $csor2) = 0xfff80000
+
+# CS3 -- not used
+set *((unsigned long *) $csbr3) = 0x0
+set *((unsigned long *) $csor3) = 0x0
+
+# CS4 -- not used
+set *((unsigned long *) $csbr4) = 0x0
+set *((unsigned long *) $csor4) = 0x0
+
+# CS5 -- PLI socket0
+set *((unsigned long *) $csbr5) = 0x0
+set *((unsigned long *) $csor5) = 0x0
+
+# CS6 -- PLI socket1
+set *((unsigned long *) $csbr6) = 0x0
+set *((unsigned long *) $csor6) = 0x0
+
+# CS7 -- SDRAM
+set *((unsigned long *) $csbr7) = 0x00000701
+set *((unsigned long *) $csor7) = 0xff00007c
+
+end
+
+
+#
+# Setup the DRAM controller.
+#
+
+define setup-dram
+set *((unsigned long *) $sdtr) = 0x0000f539
+set *((unsigned long *) $sdcr) = 0x00004211
+
+# Dummy write to start SDRAM
+set *((unsigned long *) 0) = 0
+end
+
+
+#
+# Setup for GPIO pins
+#
+define setup-ppio
+
+# PORT A -- the LED's
+set *((unsigned long *) $pacnt) = 0x00000000
+# lower 8 bits for output:
+set *((unsigned short *) $paddr) = 0xff
+# LED's off:
+set *((unsigned short *) $padat) = 0xff
+
+# PORT B
+set *((unsigned long *) $pbcnt) = 0x55554155
+set *((unsigned short *) $pbddr) = 0x0000
+set *((unsigned short *) $pbdat) = 0x17ea
+
+# PORT C
+#set *((unsigned short *) $pcddr) = 0x0000
+#set *((unsigned short *) $pcdat) = 0x1898
+
+# PORT D
+set *((unsigned long *) $pdcnt) = 0x00000000
+
+end
+
+
+#
+# Added for uClinux-coldfire target...
+#
+target bdm /dev/bdm
+
+addresses
+setup-sys
+setup-cs
+setup-dram
+setup-ppio
+set print pretty
+set print asm-demangle
+display/i $pc
+
+
+#
+load u-boot
+set $pc=0x20000
+c
diff --git a/board/cobra5272/bdm/gdbinit.reset b/board/cobra5272/bdm/gdbinit.reset
new file mode 100644
index 0000000..5f1e482
--- /dev/null
+++ b/board/cobra5272/bdm/gdbinit.reset
@@ -0,0 +1,2 @@
+target bdm /dev/bdmcf0
+q
diff --git a/board/cobra5272/bdm/load-cobra_uboot b/board/cobra5272/bdm/load-cobra_uboot
new file mode 100644
index 0000000..933c7e7
--- /dev/null
+++ b/board/cobra5272/bdm/load-cobra_uboot
@@ -0,0 +1,2 @@
+m68k-bdm-elf-gdb -n -x board/cobra5272/bdm/cobra5272_uboot.gdb u-boot
+
diff --git a/board/cobra5272/bdm/reset b/board/cobra5272/bdm/reset
new file mode 100644
index 0000000..8bef00b
--- /dev/null
+++ b/board/cobra5272/bdm/reset
@@ -0,0 +1,2 @@
+m68k-bdm-elf-gdb -n -x bdm/gdbinit.reset
+
diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c
new file mode 100644
index 0000000..0f3bcc5
--- /dev/null
+++ b/board/cobra5272/cobra5272.c
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+
+int checkboard (void)
+{
+ puts ("Board: ");
+ puts ("senTec COBRA5272 Board\n");
+ return 0;
+};
+
+phys_size_t initdram (int board_type)
+{
+ volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
+
+ sdp->sdram_sdtr = 0xf539;
+ sdp->sdram_sdcr = 0x4211;
+
+ /* Dummy write to start SDRAM */
+ *((volatile unsigned long *) 0) = 0;
+
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram (void)
+{
+ /* TODO: XXX XXX XXX */
+ printf ("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/cobra5272/config.mk b/board/cobra5272/config.mk
new file mode 100644
index 0000000..1af25e1
--- /dev/null
+++ b/board/cobra5272/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffe00000
diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c
new file mode 100644
index 0000000..c0b8337
--- /dev/null
+++ b/board/cobra5272/flash.c
@@ -0,0 +1,364 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
+#define FLASH_BANK_SIZE 0x200000
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case (AMD_MANUFACT & FLASH_VENDMASK):
+ printf ("AMD: ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case (AMD_ID_PL160CB & FLASH_TYPEMASK):
+ printf ("AM29PL160CB (16Mbit)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ goto Done;
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+ if ((i % 5) == 0) {
+ printf ("\n ");
+ }
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+
+Done:
+ return;
+}
+
+
+unsigned long flash_init (void)
+{
+ int i, j;
+ ulong size = 0;
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+ ulong flashbase = 0;
+
+ flash_info[i].flash_id =
+ (AMD_MANUFACT & FLASH_VENDMASK) |
+ (AMD_ID_PL160CB & FLASH_TYPEMASK);
+ flash_info[i].size = FLASH_BANK_SIZE;
+ flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+ if (i == 0)
+ flashbase = PHYS_FLASH_1;
+ else
+ panic ("configured to many flash banks!\n");
+
+ for (j = 0; j < flash_info[i].sector_count; j++) {
+ if (j == 0) {
+ /* 1st is 16 KiB */
+ flash_info[i].start[j] = flashbase;
+ }
+ if ((j >= 1) && (j <= 2)) {
+ /* 2nd and 3rd are 8 KiB */
+ flash_info[i].start[j] =
+ flashbase + 0x4000 + 0x2000 * (j - 1);
+ }
+ if (j == 3) {
+ /* 4th is 224 KiB */
+ flash_info[i].start[j] = flashbase + 0x8000;
+ }
+ if ((j >= 4) && (j <= 10)) {
+ /* rest is 256 KiB */
+ flash_info[i].start[j] =
+ flashbase + 0x40000 + 0x40000 * (j -
+ 4);
+ }
+ }
+ size += flash_info[i].size;
+ }
+
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
+
+ return size;
+}
+
+
+#define CMD_READ_ARRAY 0x00F0
+#define CMD_UNLOCK1 0x00AA
+#define CMD_UNLOCK2 0x0055
+#define CMD_ERASE_SETUP 0x0080
+#define CMD_ERASE_CONFIRM 0x0030
+#define CMD_PROGRAM 0x00A0
+#define CMD_UNLOCK_BYPASS 0x0020
+
+#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
+
+#define BIT_ERASE_DONE 0x0080
+#define BIT_RDY_MASK 0x0080
+#define BIT_PROGRAM_ERROR 0x0020
+#define BIT_TIMEOUT 0x80000000 /* our flag */
+
+#define READY 1
+#define ERR 2
+#define TMO 4
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ ulong result;
+ int iflag, cflag, prot, sect;
+ int rc = ERR_OK;
+ int chip1;
+ ulong start;
+
+ /* first look for protection bits */
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return ERR_UNKNOWN_FLASH_TYPE;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ return ERR_INVAL;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) !=
+ (AMD_MANUFACT & FLASH_VENDMASK)) {
+ return ERR_UNKNOWN_FLASH_VENDOR;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot)
+ return ERR_PROTECTED;
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+
+ cflag = icache_status ();
+ icache_disable ();
+ iflag = disable_interrupts ();
+
+ printf ("\n");
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+ printf ("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ if (info->protect[sect] == 0) { /* not protected */
+ volatile u16 *addr =
+ (volatile u16 *) (info->start[sect]);
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ *addr = CMD_ERASE_CONFIRM;
+
+ /* wait until flash is ready */
+ chip1 = 0;
+
+ do {
+ result = *addr;
+
+ /* check timeout */
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+ chip1 = TMO;
+ break;
+ }
+
+ if (!chip1
+ && (result & 0xFFFF) & BIT_ERASE_DONE)
+ chip1 = READY;
+
+ } while (!chip1);
+
+ MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+ if (chip1 == ERR) {
+ rc = ERR_PROG_ERROR;
+ goto outahere;
+ }
+ if (chip1 == TMO) {
+ rc = ERR_TIMOUT;
+ goto outahere;
+ }
+
+ printf ("ok.\n");
+ } else { /* it was protected */
+
+ printf ("protected!\n");
+ }
+ }
+
+ if (ctrlc ())
+ printf ("User Interrupt!\n");
+
+ outahere:
+ /* allow flash to settle - wait 10 ms */
+ udelay (10000);
+
+ if (iflag)
+ enable_interrupts ();
+
+ if (cflag)
+ icache_enable ();
+
+ return rc;
+}
+
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+ volatile u16 *addr = (volatile u16 *) dest;
+ ulong result;
+ int rc = ERR_OK;
+ int cflag, iflag;
+ int chip1;
+ ulong start;
+
+ /*
+ * Check if Flash is (sufficiently) erased
+ */
+ result = *addr;
+ if ((result & data) != data)
+ return ERR_NOT_ERASED;
+
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+
+ cflag = icache_status ();
+ icache_disable ();
+ iflag = disable_interrupts ();
+
+ MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+ MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+ MEM_FLASH_ADDR1 = CMD_PROGRAM;
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ /* wait until flash is ready */
+ chip1 = 0;
+ do {
+ result = *addr;
+
+ /* check timeout */
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ chip1 = ERR | TMO;
+ break;
+ }
+ if (!chip1 && ((result & 0x80) == (data & 0x80)))
+ chip1 = READY;
+
+ } while (!chip1);
+
+ *addr = CMD_READ_ARRAY;
+
+ if (chip1 == ERR || *addr != data)
+ rc = ERR_PROG_ERROR;
+
+ if (iflag)
+ enable_interrupts ();
+
+ if (cflag)
+ icache_enable ();
+
+ return rc;
+}
+
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong wp, data;
+ int rc;
+
+ if (addr & 1) {
+ printf ("unaligned destination not supported\n");
+ return ERR_ALIGN;
+ }
+
+#if 0
+ if (cnt & 1) {
+ printf ("odd transfer sizes not supported\n");
+ return ERR_ALIGN;
+ }
+#endif
+
+ wp = addr;
+
+ if (addr & 1) {
+ data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
+ src);
+ if ((rc = write_word (info, wp - 1, data)) != 0) {
+ return (rc);
+ }
+ src += 1;
+ wp += 1;
+ cnt -= 1;
+ }
+
+ while (cnt >= 2) {
+ data = *((volatile u16 *) src);
+ if ((rc = write_word (info, wp, data)) != 0) {
+ return (rc);
+ }
+ src += 2;
+ wp += 2;
+ cnt -= 2;
+ }
+
+ if (cnt == 1) {
+ data = (*((volatile u8 *) src) << 8) |
+ *((volatile u8 *) (wp + 1));
+ if ((rc = write_word (info, wp, data)) != 0) {
+ return (rc);
+ }
+ src += 1;
+ wp += 1;
+ cnt -= 1;
+ }
+
+ return ERR_OK;
+}
diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds
new file mode 100644
index 0000000..e91b7e1
--- /dev/null
+++ b/board/cobra5272/u-boot.lds
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ .text :
+ {
+ arch/m68k/cpu/mcf52x2/start.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/comelit/dig297/Kconfig b/board/comelit/dig297/Kconfig
new file mode 100644
index 0000000..6dccaff
--- /dev/null
+++ b/board/comelit/dig297/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DIG297
+
+config SYS_BOARD
+ default "dig297"
+
+config SYS_VENDOR
+ default "comelit"
+
+config SYS_CONFIG_NAME
+ default "dig297"
+
+endif
diff --git a/board/comelit/dig297/MAINTAINERS b/board/comelit/dig297/MAINTAINERS
new file mode 100644
index 0000000..318374e
--- /dev/null
+++ b/board/comelit/dig297/MAINTAINERS
@@ -0,0 +1,6 @@
+DIG297 BOARD
+M: Luca Ceresoli <luca.ceresoli@comelit.it>
+S: Maintained
+F: board/comelit/dig297/
+F: include/configs/dig297.h
+F: configs/dig297_defconfig
diff --git a/board/comelit/dig297/Makefile b/board/comelit/dig297/Makefile
new file mode 100644
index 0000000..1c85b63
--- /dev/null
+++ b/board/comelit/dig297/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dig297.o
diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c
new file mode 100644
index 0000000..9d4c41b
--- /dev/null
+++ b/board/comelit/dig297/dig297.c
@@ -0,0 +1,182 @@
+/*
+ * (C) Copyright 2011 Comelit Group SpA
+ * Luca Ceresoli <luca.ceresoli@comelit.it>
+ *
+ * Based on board/ti/beagle/beagle.c:
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/omap3-regs.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include "dig297.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NET
+static void setup_net_chip(void);
+
+#define NET_LAN9221_RESET_GPIO 12
+
+/* GPMC CS 5 connected to an SMSC LAN9220 ethernet controller */
+#define NET_LAN9220_GPMC_CONFIG1 (DEVICESIZE_16BIT)
+#define NET_LAN9220_GPMC_CONFIG2 (CSWROFFTIME(8) | \
+ CSRDOFFTIME(7) | \
+ ADVONTIME(1))
+#define NET_LAN9220_GPMC_CONFIG3 (ADVWROFFTIME(2) | \
+ ADVRDOFFTIME(2) | \
+ ADVONTIME(1))
+#define NET_LAN9220_GPMC_CONFIG4 (WEOFFTIME(8) | \
+ WEONTIME(1) | \
+ OEOFFTIME(7)| \
+ OEONTIME(1))
+#define NET_LAN9220_GPMC_CONFIG5 (PAGEBURSTACCESSTIME(0) | \
+ RDACCESSTIME(6) | \
+ WRCYCLETIME(0x1D) | \
+ RDCYCLETIME(0x1D))
+#define NET_LAN9220_GPMC_CONFIG6 ((1 << 31) | \
+ WRACCESSTIME(0x1D) | \
+ WRDATAONADMUXBUS(3))
+
+static const u32 gpmc_lan_config[] = {
+ NET_LAN9220_GPMC_CONFIG1,
+ NET_LAN9220_GPMC_CONFIG2,
+ NET_LAN9220_GPMC_CONFIG3,
+ NET_LAN9220_GPMC_CONFIG4,
+ NET_LAN9220_GPMC_CONFIG5,
+ NET_LAN9220_GPMC_CONFIG6,
+ /* CONFIG7: computed by enable_gpmc_cs_config() */
+};
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE;
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+
+ twl4030_power_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+
+ /*
+ * GPIO list
+ * - 159 OUT (GPIO5+31): reset for remote camera interface connector.
+ * - 19 OUT (GPIO1+19): integrated speaker amplifier (1=on, 0=shdn).
+ * - 20 OUT (GPIO1+20): handset amplifier (1=on, 0=shdn).
+ */
+
+ /* Configure GPIOs to output */
+ writel(~(GPIO19 | GPIO20), &gpio1_base->oe);
+ writel(~(GPIO31), &gpio5_base->oe);
+
+ /* Set GPIO values */
+ writel((GPIO19 | GPIO20), &gpio1_base->setdataout);
+ writel(0, &gpio5_base->setdataout);
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_DIG297();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Configure GPMC registers */
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
+ CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 12 as output pin and send a magic pulse through it */
+ if (!gpio_request(NET_LAN9221_RESET_GPIO, "")) {
+ gpio_direction_output(NET_LAN9221_RESET_GPIO, 0);
+ gpio_set_value(NET_LAN9221_RESET_GPIO, 1);
+ udelay(1);
+ gpio_set_value(NET_LAN9221_RESET_GPIO, 0);
+ udelay(31000); /* Should be >= 30ms according to datasheet */
+ gpio_set_value(NET_LAN9221_RESET_GPIO, 1);
+ }
+}
+#endif /* CONFIG_CMD_NET */
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ return rc;
+}
diff --git a/board/comelit/dig297/dig297.h b/board/comelit/dig297/dig297.h
new file mode 100644
index 0000000..8edfc09
--- /dev/null
+++ b/board/comelit/dig297/dig297.h
@@ -0,0 +1,367 @@
+/*
+ * (C) Copyright 2011 Comelit Group SpA
+ * Luca Ceresoli <luca.ceresoli@comelit.it>
+ *
+ * Based on board/ti/beagle/beagle.h:
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _DIG297_H_
+#define _DIG297_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "OMAP3 DIG297 board",
+ "NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DIG297() \
+/*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)) /*sdrc_cke1: NC*/\
+/*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*NAND*/\
+ /* GPMC_nCS1/2: not available on CUS package*/\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M0)) /*GPMC_nBE1: NC*/\
+ /* GPMC_WAIT2: not available on CUS package*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | DIS | M0)) /*GPMC_WAIT3: NC*/\
+ /* GPMC_CLK: NC (only asyncronous peripherals are connected) */\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ /* GPMC_WAIT1: not available on CUS package*/\
+/*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ /* DSS_ACBIAS: AC BIAS: connected to TFT, not to be driven */\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTU | EN | M7))\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+/*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+/*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+/*Expansion card */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
+/*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+/*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
+/*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
+ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+/*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+/* USB EHCI (port 2) */\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
+/* MCSPI1: to TOUCH controller TSC2046 (ADS7846 compatible).*/\
+ /*
+ * McSPI1_CLK.
+ * IEN needed fot the McSPI to "receive" the clock and be able to
+ * sample SOMI. See http://e2e.ti.com/support/arm174_microprocessors/
+ * omap_applications_processors/f/42/p/29444/102394.aspx#102394
+ */\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTD | EN | M0)) /*McSPI1_SIMO*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) /*McSPI1_SOMI*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTU | EN | M0)) /*McSPI1_CS0*/\
+/* MCSPI2: to HIMAX TFT controller.*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IDIS | PTD | EN | M0)) /*MCSPI2_CLK*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IDIS | PTD | EN | M0)) /*MCSPI3_SIMO*/\
+ /* MCSPI3_SOMI: NC because HIMAX in monodirectional (no SOMI line) */\
+ MUX_VAL(CP(MCSPI2_SOMI), (IDIS | PTU | DIS | M7))\
+ MUX_VAL(CP(MCSPI2_CS0), (IDIS | PTU | EN | M0)) /*MCSPI3_CS0*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTU | DIS | M7)) /*Safe mode: NC*/\
+/* GPIO */\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M4)) /*GPIO_12*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) /*GPIO_13*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M4)) /*GPIO_14*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | EN | M4)) /*GPIO_15*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | EN | M4)) /*GPIO_16*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M4)) /*GPIO_17*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTD | EN | M4)) /*GPIO_18*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTD | EN | M4)) /*GPIO_19*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTD | EN | M4)) /*GPIO_20*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTD | EN | M4)) /*GPIO_21*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M4)) /*GPIO_23*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | EN | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | EN | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | EN | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | EN | M4)) /*GPIO_164*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | DIS | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) /*GPIO_177*/\
+/*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */
+
+#endif
diff --git a/board/compal/paz00/Kconfig b/board/compal/paz00/Kconfig
new file mode 100644
index 0000000..30ba11d
--- /dev/null
+++ b/board/compal/paz00/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PAZ00
+
+config SYS_BOARD
+ default "paz00"
+
+config SYS_VENDOR
+ default "compal"
+
+config SYS_CONFIG_NAME
+ default "paz00"
+
+endif
diff --git a/board/compal/paz00/MAINTAINERS b/board/compal/paz00/MAINTAINERS
new file mode 100644
index 0000000..ee2b2e9
--- /dev/null
+++ b/board/compal/paz00/MAINTAINERS
@@ -0,0 +1,7 @@
+PAZ00 BOARD
+M: Tom Warren <twarren@nvidia.com>
+M: Stephen Warren <swarren@nvidia.com>
+S: Maintained
+F: board/compal/paz00/
+F: include/configs/paz00.h
+F: configs/paz00_defconfig
diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile
new file mode 100644
index 0000000..e6a0b29
--- /dev/null
+++ b/board/compal/paz00/Makefile
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+
+obj-y := paz00.o
+
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
new file mode 100644
index 0000000..462ab05
--- /dev/null
+++ b/board/compal/paz00/paz00.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/pinmux.h>
+#include <asm/gpio.h>
+
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+ /* SDMMC4: config 3, x8 on 2nd set of pins */
+ pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
+ pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
+
+ pinmux_tristate_disable(PMUX_PINGRP_ATB);
+ pinmux_tristate_disable(PMUX_PINGRP_GMA);
+ pinmux_tristate_disable(PMUX_PINGRP_GME);
+
+ /* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
+ pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
+
+ pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
+
+ /* For power GPIO PV1 */
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
+ /* For CD GPIO PV5 */
+ pinmux_tristate_disable(PMUX_PINGRP_GPV);
+}
+#endif
+
+#ifdef CONFIG_LCD
+/* this is a weak define that we are overriding */
+void pin_mux_display(void)
+{
+ debug("init display pinmux\n");
+
+ /* EN_VDD_PANEL GPIO A4 */
+ pinmux_tristate_disable(PMUX_PINGRP_DAP2);
+}
+#endif
diff --git a/board/compulab/cm_fx6/Kconfig b/board/compulab/cm_fx6/Kconfig
new file mode 100644
index 0000000..508c21f
--- /dev/null
+++ b/board/compulab/cm_fx6/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CM_FX6
+
+config SYS_BOARD
+ default "cm_fx6"
+
+config SYS_VENDOR
+ default "compulab"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "cm_fx6"
+
+endif
diff --git a/board/compulab/cm_fx6/MAINTAINERS b/board/compulab/cm_fx6/MAINTAINERS
new file mode 100644
index 0000000..5b2623a
--- /dev/null
+++ b/board/compulab/cm_fx6/MAINTAINERS
@@ -0,0 +1,6 @@
+CM_FX6 BOARD
+M: Nikita Kiryanov <nikita@compulab.co.il>
+S: Maintained
+F: board/compulab/cm_fx6/
+F: include/configs/cm_fx6.h
+F: configs/cm_fx6_defconfig
diff --git a/board/compulab/cm_fx6/Makefile b/board/compulab/cm_fx6/Makefile
new file mode 100644
index 0000000..3e5c903
--- /dev/null
+++ b/board/compulab/cm_fx6/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Nikita Kiryanov <nikita@compulab.co.il>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+obj-y = common.o spl.o
+else
+obj-y = common.o cm_fx6.o
+endif
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
new file mode 100644
index 0000000..84e3643
--- /dev/null
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -0,0 +1,584 @@
+/*
+ * Board functions for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <fdt_support.h>
+#include <sata.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/iomux.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/sata.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <dm/platform_data/serial_mxc.h>
+#include "common.h"
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DWC_AHSATA
+static int cm_fx6_issd_gpios[] = {
+ /* The order of the GPIOs in the array is important! */
+ CM_FX6_SATA_LDO_EN,
+ CM_FX6_SATA_PHY_SLP,
+ CM_FX6_SATA_NRSTDLY,
+ CM_FX6_SATA_PWREN,
+ CM_FX6_SATA_NSTANDBY1,
+ CM_FX6_SATA_NSTANDBY2,
+};
+
+static void cm_fx6_sata_power(int on)
+{
+ int i;
+
+ if (!on) { /* tell the iSSD that the power will be removed */
+ gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
+ mdelay(10);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
+ gpio_direction_output(cm_fx6_issd_gpios[i], on);
+ udelay(100);
+ }
+
+ if (!on) /* for compatibility lower the power loss interrupt */
+ gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
+}
+
+static iomux_v3_cfg_t const sata_pads[] = {
+ /* SATA PWR */
+ IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ /* SATA CTRL */
+ IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static int cm_fx6_setup_issd(void)
+{
+ int ret, i;
+
+ SETUP_IOMUX_PADS(sata_pads);
+
+ for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
+ ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
+ if (ret)
+ return ret;
+ }
+
+ ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+#define CM_FX6_SATA_INIT_RETRIES 10
+int sata_initialize(void)
+{
+ int err, i;
+
+ /* Make sure this gpio has logical 0 value */
+ gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
+ udelay(100);
+ cm_fx6_sata_power(1);
+
+ for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
+ err = setup_sata();
+ if (err) {
+ printf("SATA setup failed: %d\n", err);
+ return err;
+ }
+
+ udelay(100);
+
+ err = __sata_initialize();
+ if (!err)
+ break;
+
+ /* There is no device on the SATA port */
+ if (sata_port_status(0, 0) == 0)
+ break;
+
+ /* There's a device, but link not established. Retry */
+ }
+
+ return err;
+}
+
+int sata_stop(void)
+{
+ __sata_stop();
+ cm_fx6_sata_power(0);
+ mdelay(250);
+
+ return 0;
+}
+#else
+static int cm_fx6_setup_issd(void) { return 0; }
+#endif
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+I2C_PADS(i2c0_pads,
+ PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ IMX_GPIO_NR(3, 21),
+ PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ IMX_GPIO_NR(3, 28));
+
+I2C_PADS(i2c1_pads,
+ PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ IMX_GPIO_NR(4, 12),
+ PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ IMX_GPIO_NR(4, 13));
+
+I2C_PADS(i2c2_pads,
+ PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ IMX_GPIO_NR(1, 3),
+ PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ IMX_GPIO_NR(1, 6));
+
+
+static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
+{
+ int ret;
+
+ ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
+ if (ret)
+ printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
+
+ return ret;
+}
+
+static int cm_fx6_setup_i2c(void)
+{
+ int ret = 0, err;
+
+ /* i2c<x>_pads are wierd macro variables; we can't use an array */
+ err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
+ if (err)
+ ret = err;
+ err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
+ if (err)
+ ret = err;
+ err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
+ if (err)
+ ret = err;
+
+ return ret;
+}
+#else
+static int cm_fx6_setup_i2c(void) { return 0; }
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+#define MX6_USBNC_BASEADDR 0x2184800
+#define USBNC_USB_H1_PWR_POL (1 << 9)
+
+static int cm_fx6_setup_usb_host(void)
+{
+ int err;
+
+ err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
+ if (err)
+ return err;
+
+ SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
+
+ return 0;
+}
+
+static int cm_fx6_setup_usb_otg(void)
+{
+ int err;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
+ if (err) {
+ printf("USB OTG pwr gpio request failed: %d\n", err);
+ return err;
+ }
+
+ SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
+ MUX_PAD_CTRL(WEAK_PULLDOWN));
+ clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
+ /* disable ext. charger detect, or it'll affect signal quality at dp. */
+ return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ int ret;
+ u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
+
+ /* Only 1 host controller in use. port 0 is OTG & needs no attention */
+ if (port != 1)
+ return 0;
+
+ /* Set PWR polarity to match power switch's enable polarity */
+ setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
+ ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
+ if (ret)
+ return ret;
+
+ udelay(10);
+ ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
+ if (ret)
+ return ret;
+
+ mdelay(1);
+
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ if (port == 0)
+ return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
+
+ return 0;
+}
+#else
+static int cm_fx6_setup_usb_otg(void) { return 0; }
+static int cm_fx6_setup_usb_host(void) { return 0; }
+#endif
+
+#ifdef CONFIG_FEC_MXC
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* Ar8031 phy SmartEEE feature cause link status generates glitch,
+ * which cause ethernet link down/up issue, so disable SmartEEE
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= ~(0x1 << 8);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+};
+
+static int handle_mac_address(void)
+{
+ unsigned char enetaddr[6];
+ int rc;
+
+ rc = eth_getenv_enetaddr("ethaddr", enetaddr);
+ if (rc)
+ return 0;
+
+ rc = cl_eeprom_read_mac_addr(enetaddr);
+ if (rc)
+ return rc;
+
+ if (!is_valid_ether_addr(enetaddr))
+ return -1;
+
+ return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int err;
+
+ err = handle_mac_address();
+ if (err)
+ puts("No MAC address found\n");
+
+ SETUP_IOMUX_PADS(enet_pads);
+ /* phy reset */
+ err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
+ if (err)
+ printf("Etnernet NRST gpio request failed: %d\n", err);
+ gpio_direction_output(CM_FX6_ENET_NRST, 0);
+ udelay(500);
+ gpio_set_value(CM_FX6_ENET_NRST, 1);
+ enable_enet_clk(1);
+ return cpu_eth_init(bis);
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const nand_pads[] = {
+ IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void cm_fx6_setup_gpmi_nand(void)
+{
+ SETUP_IOMUX_PADS(nand_pads);
+ /* Enable clock roots */
+ enable_usdhc_clk(1, 3);
+ enable_usdhc_clk(1, 4);
+
+ setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
+}
+#else
+static void cm_fx6_setup_gpmi_nand(void) {}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC1_BASE_ADDR},
+ {USDHC2_BASE_ADDR},
+ {USDHC3_BASE_ADDR},
+};
+
+static enum mxc_clock usdhc_clk[3] = {
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int i;
+
+ cm_fx6_set_usdhc_iomux();
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
+ usdhc_cfg[i].max_bus_width = 4;
+ fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ enable_usdhc_clk(1, i);
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+int cm_fx6_setup_ecspi(void)
+{
+ cm_fx6_set_ecspi_iomux();
+ return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
+}
+#else
+int cm_fx6_setup_ecspi(void) { return 0; }
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ uint8_t enetaddr[6];
+
+ /* MAC addr */
+ if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ fdt_find_and_setprop(blob, "/fec", "local-mac-address",
+ enetaddr, 6, 1);
+ }
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ int ret;
+
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+ cm_fx6_setup_gpmi_nand();
+
+ ret = cm_fx6_setup_ecspi();
+ if (ret)
+ printf("Warning: ECSPI setup failed: %d\n", ret);
+
+ ret = cm_fx6_setup_usb_otg();
+ if (ret)
+ printf("Warning: USB OTG setup failed: %d\n", ret);
+
+ ret = cm_fx6_setup_usb_host();
+ if (ret)
+ printf("Warning: USB host setup failed: %d\n", ret);
+
+ /*
+ * cm-fx6 may have iSSD not assembled and in this case it has
+ * bypasses for a (m)SATA socket on the baseboard. The socketed
+ * device is not controlled by those GPIOs. So just print a warning
+ * if the setup fails.
+ */
+ ret = cm_fx6_setup_issd();
+ if (ret)
+ printf("Warning: iSSD setup failed: %d\n", ret);
+
+ /* Warn on failure but do not abort boot */
+ ret = cm_fx6_setup_i2c();
+ if (ret)
+ printf("Warning: I2C setup failed: %d\n", ret);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: CM-FX6\n");
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+
+ switch (gd->ram_size) {
+ case 0x10000000: /* DDR_16BIT_256MB */
+ gd->bd->bi_dram[0].size = 0x10000000;
+ gd->bd->bi_dram[1].size = 0;
+ break;
+ case 0x20000000: /* DDR_32BIT_512MB */
+ gd->bd->bi_dram[0].size = 0x20000000;
+ gd->bd->bi_dram[1].size = 0;
+ break;
+ case 0x40000000:
+ if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
+ gd->bd->bi_dram[0].size = 0x20000000;
+ gd->bd->bi_dram[1].size = 0x20000000;
+ } else { /* DDR_64BIT_1GB */
+ gd->bd->bi_dram[0].size = 0x40000000;
+ gd->bd->bi_dram[1].size = 0;
+ }
+ break;
+ case 0x80000000: /* DDR_64BIT_2GB */
+ gd->bd->bi_dram[0].size = 0x40000000;
+ gd->bd->bi_dram[1].size = 0x40000000;
+ break;
+ case 0xEFF00000: /* DDR_64BIT_4GB */
+ gd->bd->bi_dram[0].size = 0x70000000;
+ gd->bd->bi_dram[1].size = 0x7FF00000;
+ break;
+ }
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ switch (gd->ram_size) {
+ case 0x10000000:
+ case 0x20000000:
+ case 0x40000000:
+ case 0x80000000:
+ break;
+ case 0xF0000000:
+ gd->ram_size -= 0x100000;
+ break;
+ default:
+ printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
+ return -1;
+ }
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return cl_eeprom_get_board_rev();
+}
+
+static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
+ .reg = (struct mxc_uart *)UART4_BASE,
+};
+
+U_BOOT_DEVICE(cm_fx6_serial) = {
+ .name = "serial_mxc",
+ .platdata = &cm_fx6_mxc_serial_plat,
+};
diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c
new file mode 100644
index 0000000..59c9d1a
--- /dev/null
+++ b/board/compulab/cm_fx6/common.c
@@ -0,0 +1,85 @@
+/*
+ * Code used by both U-Boot and SPL for Compulab CM-FX6
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/spi.h>
+#include <fsl_esdhc.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc_pads[] = {
+ IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+void cm_fx6_set_usdhc_iomux(void)
+{
+ SETUP_IOMUX_PADS(usdhc_pads);
+}
+
+/* CINS bit doesn't work, so always try to access the MMC card */
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#define ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const ecspi_pads[] = {
+ IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
+};
+
+void cm_fx6_set_ecspi_iomux(void)
+{
+ SETUP_IOMUX_PADS(ecspi_pads);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (CM_FX6_ECSPI_BUS0_CS0) : -1;
+}
+#endif
diff --git a/board/compulab/cm_fx6/common.h b/board/compulab/cm_fx6/common.h
new file mode 100644
index 0000000..76097f8
--- /dev/null
+++ b/board/compulab/cm_fx6/common.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/clock.h>
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define CM_FX6_ECSPI_BUS0_CS0 IMX_GPIO_NR(2, 30)
+#define CM_FX6_GREEN_LED IMX_GPIO_NR(2, 31)
+#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8)
+#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8)
+#define CM_FX6_USB_HUB_RST IMX_GPIO_NR(7, 8)
+#define SB_FX6_USB_OTG_PWR IMX_GPIO_NR(3, 22)
+#define CM_FX6_ENET_NRST IMX_GPIO_NR(2, 8)
+#define CM_FX6_USB_HUB_RST IMX_GPIO_NR(7, 8)
+#define SB_FX6_USB_OTG_PWR IMX_GPIO_NR(3, 22)
+#define CM_FX6_SATA_PWREN IMX_GPIO_NR(1, 28)
+#define CM_FX6_SATA_VDDC_CTRL IMX_GPIO_NR(1, 30)
+#define CM_FX6_SATA_LDO_EN IMX_GPIO_NR(2, 16)
+#define CM_FX6_SATA_NSTANDBY1 IMX_GPIO_NR(3, 20)
+#define CM_FX6_SATA_PHY_SLP IMX_GPIO_NR(3, 23)
+#define CM_FX6_SATA_STBY_REQ IMX_GPIO_NR(3, 29)
+#define CM_FX6_SATA_NSTANDBY2 IMX_GPIO_NR(5, 2)
+#define CM_FX6_SATA_NRSTDLY IMX_GPIO_NR(6, 6)
+#define CM_FX6_SATA_PWLOSS_INT IMX_GPIO_NR(6, 31)
+
+
+void cm_fx6_set_usdhc_iomux(void);
+void cm_fx6_set_ecspi_iomux(void);
diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c
new file mode 100644
index 0000000..6fe937b
--- /dev/null
+++ b/board/compulab/cm_fx6/spl.c
@@ -0,0 +1,367 @@
+/*
+ * SPL specific code for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <fsl_esdhc.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ddr_config {
+ DDR_16BIT_256MB,
+ DDR_32BIT_512MB,
+ DDR_32BIT_1GB,
+ DDR_64BIT_1GB,
+ DDR_64BIT_2GB,
+ DDR_64BIT_4GB,
+ DDR_UNKNOWN,
+};
+
+/*
+ * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to
+ * Freescale QRM, but this is exactly the value used by the automatic
+ * calibration script and it works also in all our tests, so we leave
+ * it as is at this point.
+ */
+#define CM_FX6_DDR_IOMUX_CFG \
+ .dram_sdqs0 = 0x00000038, \
+ .dram_sdqs1 = 0x00000038, \
+ .dram_sdqs2 = 0x00000038, \
+ .dram_sdqs3 = 0x00000038, \
+ .dram_sdqs4 = 0x00000038, \
+ .dram_sdqs5 = 0x00000038, \
+ .dram_sdqs6 = 0x00000038, \
+ .dram_sdqs7 = 0x00000038, \
+ .dram_dqm0 = 0x00000038, \
+ .dram_dqm1 = 0x00000038, \
+ .dram_dqm2 = 0x00000038, \
+ .dram_dqm3 = 0x00000038, \
+ .dram_dqm4 = 0x00000038, \
+ .dram_dqm5 = 0x00000038, \
+ .dram_dqm6 = 0x00000038, \
+ .dram_dqm7 = 0x00000038, \
+ .dram_cas = 0x00000038, \
+ .dram_ras = 0x00000038, \
+ .dram_sdclk_0 = 0x00000038, \
+ .dram_sdclk_1 = 0x00000038, \
+ .dram_sdcke0 = 0x00003000, \
+ .dram_sdcke1 = 0x00003000, \
+ .dram_reset = 0x00000038, \
+ .dram_sdba2 = 0x00000000, \
+ .dram_sdodt0 = 0x00000038, \
+ .dram_sdodt1 = 0x00000038,
+
+#define CM_FX6_GPR_IOMUX_CFG \
+ .grp_b0ds = 0x00000038, \
+ .grp_b1ds = 0x00000038, \
+ .grp_b2ds = 0x00000038, \
+ .grp_b3ds = 0x00000038, \
+ .grp_b4ds = 0x00000038, \
+ .grp_b5ds = 0x00000038, \
+ .grp_b6ds = 0x00000038, \
+ .grp_b7ds = 0x00000038, \
+ .grp_addds = 0x00000038, \
+ .grp_ddrmode_ctl = 0x00020000, \
+ .grp_ddrpke = 0x00000000, \
+ .grp_ddrmode = 0x00020000, \
+ .grp_ctlds = 0x00000038, \
+ .grp_ddr_type = 0x000C0000,
+
+static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG };
+static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG };
+static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG };
+static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG };
+
+static struct mx6_mmdc_calibration cm_fx6_calib_s = {
+ .p0_mpwldectrl0 = 0x005B0061,
+ .p0_mpwldectrl1 = 0x004F0055,
+ .p0_mpdgctrl0 = 0x0314030C,
+ .p0_mpdgctrl1 = 0x025C0268,
+ .p0_mprddlctl = 0x42464646,
+ .p0_mpwrdlctl = 0x36322C34,
+};
+
+static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
+ .cs1_mirror = 1,
+ .cs_density = 16,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 0,
+ .ralat = 5,
+ .walat = 1,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
+ .mem_speed = 800,
+ .density = 4,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1800,
+ .trcmin = 5200,
+ .trasmin = 3600,
+ .SRT = 0,
+};
+
+static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset)
+{
+ if (reset)
+ ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
+
+ switch (dram_config) {
+ case DDR_16BIT_256MB:
+ cm_fx6_sysinfo_s.dsize = 0;
+ cm_fx6_sysinfo_s.ncs = 1;
+ break;
+ case DDR_32BIT_512MB:
+ cm_fx6_sysinfo_s.dsize = 1;
+ cm_fx6_sysinfo_s.ncs = 1;
+ break;
+ case DDR_32BIT_1GB:
+ cm_fx6_sysinfo_s.dsize = 1;
+ cm_fx6_sysinfo_s.ncs = 2;
+ break;
+ default:
+ puts("Tried to setup invalid DDR configuration\n");
+ hang();
+ }
+
+ mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s);
+ udelay(100);
+}
+
+static struct mx6_mmdc_calibration cm_fx6_calib_q = {
+ .p0_mpwldectrl0 = 0x00630068,
+ .p0_mpwldectrl1 = 0x0068005D,
+ .p0_mpdgctrl0 = 0x04140428,
+ .p0_mpdgctrl1 = 0x037C037C,
+ .p0_mprddlctl = 0x3C30303A,
+ .p0_mpwrdlctl = 0x3A344038,
+ .p1_mpwldectrl0 = 0x0035004C,
+ .p1_mpwldectrl1 = 0x00170026,
+ .p1_mpdgctrl0 = 0x0374037C,
+ .p1_mpdgctrl1 = 0x0350032C,
+ .p1_mprddlctl = 0x30322A3C,
+ .p1_mpwrdlctl = 0x48304A3E,
+};
+
+static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
+ .cs_density = 16,
+ .cs1_mirror = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 0,
+ .ralat = 5,
+ .walat = 1,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
+ .mem_speed = 1066,
+ .density = 4,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1324,
+ .trcmin = 59500,
+ .trasmin = 9750,
+ .SRT = 0,
+};
+
+static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset)
+{
+ if (reset)
+ ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
+
+ cm_fx6_ddr3_cfg_q.rowaddr = 14;
+ switch (dram_config) {
+ case DDR_16BIT_256MB:
+ cm_fx6_sysinfo_q.dsize = 0;
+ cm_fx6_sysinfo_q.ncs = 1;
+ break;
+ case DDR_32BIT_512MB:
+ cm_fx6_sysinfo_q.dsize = 1;
+ cm_fx6_sysinfo_q.ncs = 1;
+ break;
+ case DDR_64BIT_1GB:
+ cm_fx6_sysinfo_q.dsize = 2;
+ cm_fx6_sysinfo_q.ncs = 1;
+ break;
+ case DDR_64BIT_2GB:
+ cm_fx6_sysinfo_q.dsize = 2;
+ cm_fx6_sysinfo_q.ncs = 2;
+ break;
+ case DDR_64BIT_4GB:
+ cm_fx6_sysinfo_q.dsize = 2;
+ cm_fx6_sysinfo_q.ncs = 2;
+ cm_fx6_ddr3_cfg_q.rowaddr = 15;
+ break;
+ default:
+ puts("Tried to setup invalid DDR configuration\n");
+ hang();
+ }
+
+ mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q);
+ udelay(100);
+}
+
+static int cm_fx6_spl_dram_init(void)
+{
+ unsigned long bank1_size, bank2_size;
+
+ switch (get_cpu_type()) {
+ case MXC_CPU_MX6SOLO:
+ mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s);
+
+ spl_mx6s_dram_init(DDR_32BIT_1GB, false);
+ bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+ bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000);
+ if (bank1_size == 0x20000000) {
+ if (bank2_size == 0x20000000)
+ return 0;
+
+ spl_mx6s_dram_init(DDR_32BIT_512MB, true);
+ return 0;
+ }
+
+ spl_mx6s_dram_init(DDR_16BIT_256MB, true);
+ bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+ if (bank1_size == 0x10000000)
+ return 0;
+
+ break;
+ case MXC_CPU_MX6D:
+ case MXC_CPU_MX6Q:
+ mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q);
+
+ spl_mx6q_dram_init(DDR_64BIT_4GB, false);
+ bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+ if (bank1_size == 0x80000000)
+ return 0;
+
+ if (bank1_size == 0x40000000) {
+ bank2_size = get_ram_size((long int *)PHYS_SDRAM_2,
+ 0x80000000);
+ if (bank2_size == 0x40000000) {
+ /* Don't do a full reset here */
+ spl_mx6q_dram_init(DDR_64BIT_2GB, false);
+ } else {
+ spl_mx6q_dram_init(DDR_64BIT_1GB, true);
+ }
+
+ return 0;
+ }
+
+ spl_mx6q_dram_init(DDR_32BIT_512MB, true);
+ bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+ if (bank1_size == 0x20000000)
+ return 0;
+
+ spl_mx6q_dram_init(DDR_16BIT_256MB, true);
+ bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
+ if (bank1_size == 0x10000000)
+ return 0;
+
+ break;
+ }
+
+ return -1;
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void cm_fx6_setup_uart(void)
+{
+ SETUP_IOMUX_PADS(uart4_pads);
+ enable_uart_clk(1);
+}
+
+#ifdef CONFIG_SPL_SPI_SUPPORT
+static void cm_fx6_setup_ecspi(void)
+{
+ cm_fx6_set_ecspi_iomux();
+ enable_cspi_clock(1, 0);
+}
+#else
+static void cm_fx6_setup_ecspi(void) { }
+#endif
+
+void board_init_f(ulong dummy)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ gd = &gdata;
+ /*
+ * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
+ * initializes DMA very early (before all board code), so the only
+ * opportunity we have to initialize APBHDMA clocks is in SPL.
+ */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+ enable_usdhc_clk(1, 2);
+
+ arch_cpu_init();
+ timer_init();
+ cm_fx6_setup_ecspi();
+ cm_fx6_setup_uart();
+ get_clocks();
+ preloader_console_init();
+ gpio_direction_output(CM_FX6_GREEN_LED, 1);
+ if (cm_fx6_spl_dram_init()) {
+ puts("!!!ERROR!!! DRAM detection failed!!!\n");
+ hang();
+ }
+
+ memset(__bss_start, 0, __bss_end - __bss_start);
+ board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+ u32 boot_device = spl_boot_device();
+
+ if (boot_device == BOOT_DEVICE_SPI)
+ puts("Booting from SPI flash\n");
+ else if (boot_device == BOOT_DEVICE_MMC1)
+ puts("Booting from MMC\n");
+ else
+ puts("Unknown boot device\n");
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+static struct fsl_esdhc_cfg usdhc_cfg = {
+ .esdhc_base = USDHC3_BASE_ADDR,
+ .max_bus_width = 4,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ cm_fx6_set_usdhc_iomux();
+
+ usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif
diff --git a/board/compulab/cm_t335/Kconfig b/board/compulab/cm_t335/Kconfig
new file mode 100644
index 0000000..683efde
--- /dev/null
+++ b/board/compulab/cm_t335/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CM_T335
+
+config SYS_BOARD
+ default "cm_t335"
+
+config SYS_VENDOR
+ default "compulab"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "cm_t335"
+
+endif
diff --git a/board/compulab/cm_t335/MAINTAINERS b/board/compulab/cm_t335/MAINTAINERS
new file mode 100644
index 0000000..5fb922c
--- /dev/null
+++ b/board/compulab/cm_t335/MAINTAINERS
@@ -0,0 +1,6 @@
+CM_T335 BOARD
+M: Igor Grinberg <grinberg@compulab.co.il>
+S: Maintained
+F: board/compulab/cm_t335/
+F: include/configs/cm_t335.h
+F: configs/cm_t335_defconfig
diff --git a/board/compulab/cm_t335/Makefile b/board/compulab/cm_t335/Makefile
new file mode 100644
index 0000000..b405caa
--- /dev/null
+++ b/board/compulab/cm_t335/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/
+#
+# Author: Ilya Ledvich <ilya@compulab.co.il>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cm_t335.o
+obj-$(CONFIG_SPL_BUILD) += mux.o spl.o
diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c
new file mode 100644
index 0000000..9583149
--- /dev/null
+++ b/board/compulab/cm_t335/cm_t335.c
@@ -0,0 +1,162 @@
+/*
+ * Board functions for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <cpsw.h>
+
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware_am33xx.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ gpmc_init();
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+#endif
+ return 0;
+}
+
+#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slave = {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ .phy_if = PHY_INTERFACE_MODE_RGMII,
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = &cpsw_slave,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+/* PHY reset GPIO */
+#define GPIO_PHY_RST GPIO_PIN(3, 7)
+
+static void board_phy_init(void)
+{
+ gpio_request(GPIO_PHY_RST, "phy_rst");
+ gpio_direction_output(GPIO_PHY_RST, 0);
+ mdelay(2);
+ gpio_set_value(GPIO_PHY_RST, 1);
+ mdelay(2);
+}
+
+static void get_efuse_mac_addr(uchar *enetaddr)
+{
+ uint32_t mac_hi, mac_lo;
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ enetaddr[0] = mac_hi & 0xFF;
+ enetaddr[1] = (mac_hi & 0xFF00) >> 8;
+ enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
+ enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
+ enetaddr[4] = mac_lo & 0xFF;
+ enetaddr[5] = (mac_lo & 0xFF00) >> 8;
+}
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int handle_mac_address(void)
+{
+ uchar enetaddr[6];
+ int rv;
+
+ rv = eth_getenv_enetaddr("ethaddr", enetaddr);
+ if (rv)
+ return 0;
+
+ rv = cl_eeprom_read_mac_addr(enetaddr);
+ if (rv)
+ get_efuse_mac_addr(enetaddr);
+
+ if (!is_valid_ether_addr(enetaddr))
+ return -1;
+
+ return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
+#define AR8051_PHY_DEBUG_DATA_REG 0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
+#define AR8051_RGMII_TX_CLK_DLY 0x100
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+ const char *devname;
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+ rv = handle_mac_address();
+ if (rv)
+ printf("No MAC address found!\n");
+
+ writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
+
+ board_phy_init();
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+
+ /*
+ * CPSW RGMII Internal Delay Mode is not supported in all PVT
+ * operating points. So we must set the TX clock delay feature
+ * in the AR8051 PHY. Since we only support a single ethernet
+ * device, we only do this for the first instance.
+ */
+ devname = miiphy_get_current_dev();
+
+ miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
+ AR8051_DEBUG_RGMII_CLK_DLY_REG);
+ miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
+ AR8051_RGMII_TX_CLK_DLY);
+ return n;
+}
+#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */
diff --git a/board/compulab/cm_t335/mux.c b/board/compulab/cm_t335/mux.c
new file mode 100644
index 0000000..7d2beb0
--- /dev/null
+++ b/board/compulab/cm_t335/mux.c
@@ -0,0 +1,117 @@
+/*
+ * Pinmux configuration for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+ {-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
+ {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
+ {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+ /* I2C_DATA */
+ {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+ /* I2C_SCLK */
+ {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
+static struct module_pin_mux eth_phy_rst_pin_mux[] = {
+ {OFFSET(emu0), (MODE(7) | PULLUDDIS)}, /* GPIO3_7 */
+ {-1},
+};
+
+static struct module_pin_mux status_led_pin_mux[] = {
+ {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)}, /* GPIO2_0 */
+ {-1},
+};
+
+void set_uart_mux_conf(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+ configure_module_pin_mux(uart1_pin_mux);
+}
+
+void set_mux_conf_regs(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(i2c1_pin_mux);
+ configure_module_pin_mux(rgmii1_pin_mux);
+ configure_module_pin_mux(eth_phy_rst_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(nand_pin_mux);
+ configure_module_pin_mux(status_led_pin_mux);
+}
diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c
new file mode 100644
index 0000000..d574364
--- /dev/null
+++ b/board/compulab/cm_t335/spl.c
@@ -0,0 +1,114 @@
+/*
+ * SPL specific code for Compulab CM-T335 board
+ *
+ * Board functions for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clocks_am33xx.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware_am33xx.h>
+#include <linux/sizes.h>
+
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
+};
+
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41J128MJT125_RD_DQS,
+ .datawdsratio0 = MT41J128MJT125_WR_DQS,
+ .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
+ .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41J128MJT125_RATIO,
+ .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41J128MJT125_RATIO,
+ .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41J128MJT125_RATIO,
+ .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41J128MJT125_EMIF_SDCFG,
+ .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
+ .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
+ .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
+ .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
+ .zq_config = MT41J128MJT125_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
+};
+
+const struct dpll_params dpll_ddr = {
+/* M N M2 M3 M4 M5 M6 */
+ 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+ /* Get the frequency */
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr;
+}
+
+static void probe_sdram_size(long size)
+{
+ switch (size) {
+ case SZ_512M:
+ ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
+ break;
+ case SZ_256M:
+ ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
+ break;
+ case SZ_128M:
+ ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
+ break;
+ default:
+ puts("Failed configuring DRAM, resetting...\n\n");
+ reset_cpu(0);
+ }
+ debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
+ config_ddr(303, &ioregs, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+
+void sdram_init(void)
+{
+ long size = SZ_1G;
+
+ do {
+ size = size / 2;
+ probe_sdram_size(size);
+ } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size);
+
+ return;
+}
diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds
new file mode 100644
index 0000000..6275836
--- /dev/null
+++ b/board/compulab/cm_t335/u-boot.lds
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.__image_copy_start)
+ *(.vectors)
+ CPUDIR/start.o (.text*)
+ board/compulab/cm_t335/built-in.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ .hash : { *(.hash*) }
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ .dynsym _image_binary_end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
+}
diff --git a/board/compulab/cm_t35/Kconfig b/board/compulab/cm_t35/Kconfig
new file mode 100644
index 0000000..d87741f
--- /dev/null
+++ b/board/compulab/cm_t35/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CM_T35
+
+config SYS_BOARD
+ default "cm_t35"
+
+config SYS_VENDOR
+ default "compulab"
+
+config SYS_CONFIG_NAME
+ default "cm_t35"
+
+endif
diff --git a/board/compulab/cm_t35/MAINTAINERS b/board/compulab/cm_t35/MAINTAINERS
new file mode 100644
index 0000000..fc5d73f
--- /dev/null
+++ b/board/compulab/cm_t35/MAINTAINERS
@@ -0,0 +1,6 @@
+CM_T35 BOARD
+M: Igor Grinberg <grinberg@compulab.co.il>
+S: Maintained
+F: board/compulab/cm_t35/
+F: include/configs/cm_t35.h
+F: configs/cm_t35_defconfig
diff --git a/board/compulab/cm_t35/Makefile b/board/compulab/cm_t35/Makefile
new file mode 100644
index 0000000..ede250b
--- /dev/null
+++ b/board/compulab/cm_t35/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Nikita Kiryanov <nikita@compulab.co.il>
+# Igor Grinberg <grinberg@compulab.co.il>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cm_t35.o
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
new file mode 100644
index 0000000..43463d5
--- /dev/null
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -0,0 +1,501 @@
+/*
+ * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Mike Rapoport <mike@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * Derived from omap3evm and Beagle Board by
+ * Manikandan Pillai <mani.pillai@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <netdev.h>
+#include <net.h>
+#include <i2c.h>
+#include <usb.h>
+#include <mmc.h>
+#include <twl4030.h>
+#include <linux/compiler.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include <asm/ehci-omap.h>
+#include <asm/gpio.h>
+
+#include "../common/common.h"
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "CM-T3x board",
+ "NAND",
+};
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings->mr = MICRON_V_MR_165;
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+}
+#endif
+
+#define CM_T35_SPLASH_NAND_OFFSET 0x100000
+
+int splash_screen_prepare(void)
+{
+ return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET);
+}
+
+/*
+ * Routine: board_init
+ * Description: hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ /* board id for Linux */
+ if (get_cpu_family() == CPU_OMAP34XX)
+ gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
+ else
+ gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+
+ return 0;
+}
+
+/*
+ * Routine: get_board_rev
+ * Description: read system revision
+ */
+u32 get_board_rev(void)
+{
+ return cl_eeprom_get_board_rev();
+};
+
+int misc_init_r(void)
+{
+ cl_print_pcb_info();
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+static void cm_t3x_set_common_muxconf(void)
+{
+ /* SDRC */
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
+
+ /* GPMC */
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
+
+ /* SB-T35 Ethernet */
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
+
+ /* DVI enable */
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/
+
+ /* DataImage backlight */
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
+
+ /* CM-T3x Ethernet */
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
+ MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/
+
+ /* DSS */
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
+
+ /* serial interface */
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/
+
+ /* mUSB */
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
+
+ /* USB EHCI */
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
+
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
+
+ /* SB_T35_USB_HUB_RESET_GPIO */
+ MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/
+
+ /* I2C1 */
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
+ /* I2C2 */
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
+ /* I2C3 */
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
+
+ /* control and debug */
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
+
+ /* MMC1 */
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
+
+ /* SPI */
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
+
+ /* display controls */
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
+}
+
+static void cm_t35_set_muxconf(void)
+{
+ /* DSS */
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
+
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
+
+ /* MMC1 */
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
+}
+
+static void cm_t3730_set_muxconf(void)
+{
+ /* DSS */
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/
+
+ MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/
+ MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/
+ MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/
+ MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/
+ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/
+}
+
+void set_muxconf_regs(void)
+{
+ cm_t3x_set_common_muxconf();
+
+ if (get_cpu_family() == CPU_OMAP34XX)
+ cm_t35_set_muxconf();
+ else
+ cm_t3730_set_muxconf();
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#define SB_T35_WP_GPIO 59
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ u8 val;
+
+ if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val))
+ return -1;
+
+ return !(val & 1);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO);
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+/*
+ * Routine: reset_net_chip
+ * Description: reset the Ethernet controller via TPS65930 GPIO
+ */
+static int cm_t3x_reset_net_chip(int gpio)
+{
+ /* Set GPIO1 of TPS65930 as output */
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
+ 0x02);
+ /* Send a pulse on the GPIO pin */
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
+ 0x02);
+ udelay(1);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09,
+ 0x02);
+ mdelay(40);
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
+ 0x02);
+ mdelay(1);
+ return 0;
+}
+#else
+static inline int cm_t3x_reset_net_chip(int gpio) { return 0; }
+#endif
+
+#ifdef CONFIG_SMC911X
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int handle_mac_address(void)
+{
+ unsigned char enetaddr[6];
+ int rc;
+
+ rc = eth_getenv_enetaddr("ethaddr", enetaddr);
+ if (rc)
+ return 0;
+
+ rc = cl_eeprom_read_mac_addr(enetaddr);
+ if (rc)
+ return rc;
+
+ if (!is_valid_ether_addr(enetaddr))
+ return -1;
+
+ return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+/*
+ * Routine: board_eth_init
+ * Description: initialize module and base-board Ethernet chips
+ */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0, rc1 = 0;
+
+ rc1 = handle_mac_address();
+ if (rc1)
+ printf("No MAC address found! ");
+
+ rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE,
+ cm_t3x_reset_net_chip, -EINVAL);
+ if (rc1 > 0)
+ rc++;
+
+ rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL);
+ if (rc1 > 0)
+ rc++;
+
+ return rc;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_OMAP
+struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+#define SB_T35_USB_HUB_RESET_GPIO 167
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ u8 val;
+ int offset;
+
+ cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
+
+ offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
+ twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
+ /* Set GPIO6 and GPIO7 of TPS65930 as output */
+ val |= 0xC0;
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val);
+ offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1;
+ /* Take both PHYs out of reset */
+ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0);
+ udelay(1);
+
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(void)
+{
+ cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
+ return omap_ehci_hcd_stop();
+}
+#endif /* CONFIG_USB_EHCI_OMAP */
diff --git a/board/compulab/cm_t3517/Kconfig b/board/compulab/cm_t3517/Kconfig
new file mode 100644
index 0000000..2f5473d
--- /dev/null
+++ b/board/compulab/cm_t3517/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CM_T3517
+
+config SYS_BOARD
+ default "cm_t3517"
+
+config SYS_VENDOR
+ default "compulab"
+
+config SYS_CONFIG_NAME
+ default "cm_t3517"
+
+endif
diff --git a/board/compulab/cm_t3517/MAINTAINERS b/board/compulab/cm_t3517/MAINTAINERS
new file mode 100644
index 0000000..fbb6882
--- /dev/null
+++ b/board/compulab/cm_t3517/MAINTAINERS
@@ -0,0 +1,6 @@
+CM_T3517 BOARD
+M: Igor Grinberg <grinberg@compulab.co.il>
+S: Maintained
+F: board/compulab/cm_t3517/
+F: include/configs/cm_t3517.h
+F: configs/cm_t3517_defconfig
diff --git a/board/compulab/cm_t3517/Makefile b/board/compulab/cm_t3517/Makefile
new file mode 100644
index 0000000..4f0db01
--- /dev/null
+++ b/board/compulab/cm_t3517/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Igor Grinberg <grinberg@compulab.co.il>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cm_t3517.o mux.o
diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c
new file mode 100644
index 0000000..cac1ad9
--- /dev/null
+++ b/board/compulab/cm_t3517/cm_t3517.c
@@ -0,0 +1,231 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <net.h>
+#include <netdev.h>
+#include <usb.h>
+#include <mmc.h>
+#include <linux/compiler.h>
+#include <linux/usb/musb.h>
+
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/am35x_def.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/ehci-omap.h>
+
+#include "../common/common.h"
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "CM-T3517 board",
+ "NAND 128/512M",
+};
+
+#ifdef CONFIG_USB_MUSB_AM35X
+static struct musb_hdrc_config cm_t3517_musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12,
+};
+
+static struct omap_musb_board_data cm_t3517_musb_board_data = {
+ .set_phy_power = am35x_musb_phy_power,
+ .clear_irq = am35x_musb_clear_irq,
+ .reset = am35x_musb_reset,
+};
+
+static struct musb_hdrc_platform_data cm_t3517_musb_pdata = {
+#if defined(CONFIG_MUSB_HOST)
+ .mode = MUSB_HOST,
+#elif defined(CONFIG_MUSB_GADGET)
+ .mode = MUSB_PERIPHERAL,
+#else
+#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET"
+#endif
+ .config = &cm_t3517_musb_config,
+ .power = 250,
+ .platform_ops = &am35x_ops,
+ .board_data = &cm_t3517_musb_board_data,
+};
+
+static void cm_t3517_musb_init(void)
+{
+ /*
+ * Set up USB clock/mode in the DEVCONF2 register.
+ * USB2.0 PHY reference clock is 13 MHz
+ */
+ clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+ CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
+ CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
+ CONF2_VBDTCTEN | CONF2_DATPOL);
+
+ if (musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data,
+ (void *)AM35XX_IPSS_USBOTGSS_BASE))
+ printf("Failed initializing AM35x MUSB!\n");
+}
+#else
+static inline void am3517_evm_musb_init(void) {}
+#endif
+
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+
+ cm_t3517_musb_init();
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ cl_print_pcb_info();
+ dieid_num_r();
+
+ return 0;
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#define SB_T35_CD_GPIO 144
+#define SB_T35_WP_GPIO 59
+
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO);
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONTROL_EFUSE_EMAC_LSB 0x48002380
+#define CONTROL_EFUSE_EMAC_MSB 0x48002384
+
+static int am3517_get_efuse_enetaddr(u8 *enetaddr)
+{
+ u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB);
+ u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB);
+
+ enetaddr[0] = (u8)((msb >> 16) & 0xff);
+ enetaddr[1] = (u8)((msb >> 8) & 0xff);
+ enetaddr[2] = (u8)(msb & 0xff);
+ enetaddr[3] = (u8)((lsb >> 16) & 0xff);
+ enetaddr[4] = (u8)((lsb >> 8) & 0xff);
+ enetaddr[5] = (u8)(lsb & 0xff);
+
+ return is_valid_ether_addr(enetaddr);
+}
+
+static inline int cm_t3517_init_emac(bd_t *bis)
+{
+ int ret = cpu_eth_init(bis);
+
+ if (ret > 0)
+ return ret;
+
+ printf("Failed initializing EMAC! ");
+ return 0;
+}
+#else /* !CONFIG_DRIVER_TI_EMAC */
+static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; }
+static inline int cm_t3517_init_emac(bd_t *bis) { return 0; }
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int cm_t3517_handle_mac_address(void)
+{
+ unsigned char enetaddr[6];
+ int ret;
+
+ ret = eth_getenv_enetaddr("ethaddr", enetaddr);
+ if (ret)
+ return 0;
+
+ ret = cl_eeprom_read_mac_addr(enetaddr);
+ if (ret) {
+ ret = am3517_get_efuse_enetaddr(enetaddr);
+ if (ret)
+ return ret;
+ }
+
+ if (!is_valid_ether_addr(enetaddr))
+ return -1;
+
+ return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+#define SB_T35_ETH_RST_GPIO 164
+
+/*
+ * Routine: board_eth_init
+ * Description: initialize module and base-board Ethernet chips
+ */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0, rc1 = 0;
+
+ rc1 = cm_t3517_handle_mac_address();
+ if (rc1)
+ printf("No MAC address found! ");
+
+ rc1 = cm_t3517_init_emac(bis);
+ if (rc1 > 0)
+ rc++;
+
+ rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE,
+ NULL, SB_T35_ETH_RST_GPIO);
+ if (rc1 > 0)
+ rc++;
+
+ return rc;
+}
+
+#ifdef CONFIG_USB_EHCI_OMAP
+static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+#define CM_T3517_USB_HUB_RESET_GPIO 152
+#define SB_T35_USB_HUB_RESET_GPIO 98
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst");
+ cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
+
+ return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(void)
+{
+ cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO);
+ cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
+
+ return omap_ehci_hcd_stop();
+}
+#endif /* CONFIG_USB_EHCI_OMAP */
diff --git a/board/compulab/cm_t3517/mux.c b/board/compulab/cm_t3517/mux.c
new file mode 100644
index 0000000..88ce2cc
--- /dev/null
+++ b/board/compulab/cm_t3517/mux.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+
+void set_muxconf_regs(void)
+{
+ /* SDRC */
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
+
+ /* GPMC */
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
+
+ /* SB-T35 Ethernet */
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0));
+ /* DVI enable */
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/
+ /* DataImage backlight */
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
+
+ /* SB-T35 SD/MMC WP GPIO59 */
+ MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
+ /* SB-T35 Audio Enable GPIO61 */
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
+ /* SB-T35 Ethernet IRQ GPIO65 */
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/
+
+ /* UART3 Console */
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
+ /* RTC V3020 nCS GPIO163 */
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/
+ /* SB-T35 Ethernet nRESET GPIO164 */
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/
+
+ /* SB-T35 SD/MMC CD GPIO144 */
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/
+ /* WIFI nRESET GPIO145 */
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/
+ /* USB1 PHY Reset GPIO 146 */
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/
+ /* USB2 PHY Reset GPIO 147 */
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/
+
+ /* MMC1 */
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
+
+ /* DSS */
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0));
+
+ /* I2C */
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
+
+ /* SB-T35 USB HUB Reset GPIO98 */
+ MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/
+ /* CM-T3517 USB HUB Reset GPIO152 */
+ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/
+
+ /* RMII */
+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(RMII_MDIO_CLK), (M0));
+ MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_TXD0), (IDIS | M0));
+ MUX_VAL(CP(RMII_TXD1), (IDIS | M0));
+ MUX_VAL(CP(RMII_TXEN), (IDIS | M0));
+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0));
+
+ /* Green LED GPIO186 */
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/
+
+ /* SPI */
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
+ /* LCD reset GPIO157 */
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
+
+ /* RTC V3020 CS Enable GPIO160 */
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/
+ /* SB-T35 LVDS Transmitter SHDN GPIO162 */
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/
+
+ /* USB0 - mUSB */
+ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0));
+ /* USB1 EHCI */
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
+ /* USB2 EHCI */
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
+
+ /* SYS_BOOT */
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/
+}
diff --git a/board/compulab/cm_t54/Kconfig b/board/compulab/cm_t54/Kconfig
new file mode 100644
index 0000000..52d3880
--- /dev/null
+++ b/board/compulab/cm_t54/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CM_T54
+
+config SYS_BOARD
+ default "cm_t54"
+
+config SYS_VENDOR
+ default "compulab"
+
+config SYS_CONFIG_NAME
+ default "cm_t54"
+
+endif
diff --git a/board/compulab/cm_t54/MAINTAINERS b/board/compulab/cm_t54/MAINTAINERS
new file mode 100644
index 0000000..461fe09
--- /dev/null
+++ b/board/compulab/cm_t54/MAINTAINERS
@@ -0,0 +1,6 @@
+CM_T54 BOARD
+M: Dmitry Lifshitz <lifshitz@compulab.co.il>
+S: Maintained
+F: board/compulab/cm_t54/
+F: include/configs/cm_t54.h
+F: configs/cm_t54_defconfig
diff --git a/board/compulab/cm_t54/Makefile b/board/compulab/cm_t54/Makefile
new file mode 100644
index 0000000..298ddd2
--- /dev/null
+++ b/board/compulab/cm_t54/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2014 Compulab Ltd - http://compulab.co.il/
+#
+# Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cm_t54.o
+obj-$(CONFIG_SPL_BUILD) += mux.o spl.o
diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c
new file mode 100644
index 0000000..2c2530a
--- /dev/null
+++ b/board/compulab/cm_t54/cm_t54.c
@@ -0,0 +1,259 @@
+/*
+ * Board functions for Compulab CM-T54 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <usb.h>
+#include <mmc.h>
+#include <palmas.h>
+#include <spl.h>
+
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ehci.h>
+#include <asm/ehci-omap.h>
+
+#include "../common/eeprom.h"
+
+#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
+#define DIE_ID_REG_OFFSET 0x200
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_SPL_BUILD)
+inline void set_muxconf_regs_essential(void){};
+#endif
+
+const struct omap_sysinfo sysinfo = {
+ "Board: CM-T54\n"
+};
+
+/*
+ * Routine: board_init
+ * Description: hardware init.
+ */
+int board_init(void)
+{
+ gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: cm_t54_palmas_regulator_set
+ * Description: select voltage and turn on/off Palmas PMIC regulator.
+ */
+static int cm_t54_palmas_regulator_set(u8 vreg, u8 vval, u8 creg, u8 cval)
+{
+ int err;
+
+ /* Setup voltage */
+ err = palmas_i2c_write_u8(TWL603X_CHIP_P1, vreg, vval);
+ if (err) {
+ printf("cm_t54: could not set regulator 0x%02x voltage : %d\n",
+ vreg, err);
+ return err;
+ }
+
+ /* Turn on/off regulator */
+ err = palmas_i2c_write_u8(TWL603X_CHIP_P1, creg, cval);
+ if (err) {
+ printf("cm_t54: could not turn on/off regulator 0x%02x : %d\n",
+ creg, err);
+ return err;
+ }
+
+ return 0;
+}
+
+/*
+ * Routine: mmc_get_env_part
+ * Description: setup environment storage device partition.
+ */
+#ifdef CONFIG_SYS_MMC_ENV_PART
+uint mmc_get_env_part(struct mmc *mmc)
+{
+ u32 bootmode = gd->arch.omap_boot_params.omap_bootmode;
+ uint bootpart = CONFIG_SYS_MMC_ENV_PART;
+
+ /*
+ * If booted from eMMC boot partition then force eMMC
+ * FIRST boot partition to be env storage
+ */
+ if (bootmode == BOOT_DEVICE_MMC2)
+ bootpart = 1;
+
+ return bootpart;
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#define SB_T54_CD_GPIO 228
+#define SB_T54_WP_GPIO 229
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret0, ret1;
+
+ ret0 = omap_mmc_init(0, 0, 0, SB_T54_CD_GPIO, SB_T54_WP_GPIO);
+ if (ret0)
+ printf("cm_t54: failed to initialize mmc0\n");
+
+ ret1 = omap_mmc_init(1, 0, 0, -1, -1);
+ if (ret1)
+ printf("cm_t54: failed to initialize mmc1\n");
+
+ if (ret0 && ret1)
+ return -1;
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_HOST_ETHER
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ uint8_t enetaddr[6];
+
+ /* MAC addr */
+ if (eth_getenv_enetaddr("usbethaddr", enetaddr)) {
+ fdt_find_and_setprop(blob, "/smsc95xx@0", "mac-address",
+ enetaddr, 6, 1);
+ }
+
+ return 0;
+}
+
+static void generate_mac_addr(uint8_t *enetaddr)
+{
+ int reg;
+
+ reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
+
+ /*
+ * create a fake MAC address from the processor ID code.
+ * first byte is 0x02 to signify locally administered.
+ */
+ enetaddr[0] = 0x02;
+ enetaddr[1] = readl(reg + 0x10) & 0xff;
+ enetaddr[2] = readl(reg + 0xC) & 0xff;
+ enetaddr[3] = readl(reg + 0x8) & 0xff;
+ enetaddr[4] = readl(reg) & 0xff;
+ enetaddr[5] = (readl(reg) >> 8) & 0xff;
+}
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int handle_mac_address(void)
+{
+ uint8_t enetaddr[6];
+ int ret;
+
+ ret = eth_getenv_enetaddr("usbethaddr", enetaddr);
+ if (ret)
+ return 0;
+
+ ret = cl_eeprom_read_mac_addr(enetaddr);
+ if (ret || !is_valid_ether_addr(enetaddr))
+ generate_mac_addr(enetaddr);
+
+ if (!is_valid_ether_addr(enetaddr))
+ return -1;
+
+ return eth_setenv_enetaddr("usbethaddr", enetaddr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return handle_mac_address();
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
+ .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
+};
+
+static void setup_host_clocks(bool enable)
+{
+ int usbhost_clk = OPTFCLKEN_HSIC60M_P3_CLK |
+ OPTFCLKEN_HSIC480M_P3_CLK |
+ OPTFCLKEN_HSIC60M_P2_CLK |
+ OPTFCLKEN_HSIC480M_P2_CLK |
+ OPTFCLKEN_UTMI_P3_CLK |
+ OPTFCLKEN_UTMI_P2_CLK;
+
+ int usbtll_clk = OPTFCLKEN_USB_CH1_CLK_ENABLE |
+ OPTFCLKEN_USB_CH2_CLK_ENABLE;
+
+ int usbhub_clk = CKOBUFFER_CLK_ENABLE_MASK;
+
+ if (enable) {
+ /* Enable port 2 and 3 clocks*/
+ setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk);
+ /* Enable port 2 and 3 usb host ports tll clocks*/
+ setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk);
+ /* Request FREF_XTAL_CLK clock for HSIC USB Hub */
+ setbits_le32((*ctrl)->control_ckobuffer, usbhub_clk);
+ } else {
+ clrbits_le32((*ctrl)->control_ckobuffer, usbhub_clk);
+ clrbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk);
+ clrbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk);
+ }
+}
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ int ret;
+
+ /* VCC_3V3_ETH */
+ cm_t54_palmas_regulator_set(SMPS9_VOLTAGE, SMPS_VOLT_3V3, SMPS9_CTRL,
+ SMPS_MODE_SLP_AUTO | SMPS_MODE_ACT_AUTO);
+
+ setup_host_clocks(true);
+
+ ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+ if (ret < 0)
+ printf("cm_t54: Failed to initialize ehci : %d\n", ret);
+
+ return ret;
+}
+
+int ehci_hcd_stop(void)
+{
+ int ret = omap_ehci_hcd_stop();
+
+ setup_host_clocks(false);
+
+ cm_t54_palmas_regulator_set(SMPS9_VOLTAGE, SMPS_VOLT_OFF,
+ SMPS9_CTRL, SMPS_MODE_SLP_AUTO);
+
+ return ret;
+}
+
+void usb_hub_reset_devices(int port)
+{
+ /* The LAN9730 needs to be reset after the port power has been set. */
+ if (port == 3) {
+ gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
+ udelay(10);
+ gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
+ }
+}
+#endif
+
diff --git a/board/compulab/cm_t54/mux.c b/board/compulab/cm_t54/mux.c
new file mode 100644
index 0000000..da35383
--- /dev/null
+++ b/board/compulab/cm_t54/mux.c
@@ -0,0 +1,94 @@
+/*
+ * Pinmux configuration for Compulab CM-T54 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CM_T54_MUX_DATA_H
+#define _CM_T54_MUX_DATA_H
+
+#include <asm/arch/mux_omap5.h>
+#include <asm/arch/sys_proto.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+ /* MMC1 - SD CARD */
+ {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */
+ {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */
+ {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0 */
+ {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1 */
+ {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2 */
+ {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3 */
+
+ /* SD CARD CD and WP GPIOs*/
+ {TIMER5_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_228 */
+ {TIMER6_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_229 */
+
+ /* MMC2 - eMMC */
+ {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
+ {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
+ {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */
+ {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */
+ {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */
+ {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */
+ {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */
+ {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */
+ {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */
+ {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */
+
+ /* UART4 */
+ {I2C5_SCL, (PTU | IEN | M2)}, /* UART4_RX */
+ {I2C5_SDA, (M2)}, /* UART4_TX */
+
+ /* Led */
+ {HSI2_CAFLAG, (PTU | M6)}, /* GPIO3_80 */
+
+ /* I2C1 */
+ {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */
+ {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */
+
+ /* USBB2, USBB3 */
+ {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */
+ {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */
+ {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE */
+ {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */
+
+ /* USB Hub and USB Eth reset GPIOs */
+ {HSI2_CAREADY, (PTD | M6)}, /* GPIO3_76 */
+ {HSI2_ACDATA, (PTD | M6)}, /* GPIO3_83 */
+
+ /* I2C4 */
+ {I2C4_SCL, (PTU | IEN | M0)}, /* I2C4_SCL */
+ {I2C4_SDA, (PTU | IEN | M0)}, /* I2C4_SDA */
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+ {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
+ {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
+ {SYS_32K, (IEN | M0)}, /* SYS_32K */
+
+ /* USB Hub clock */
+ {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */
+};
+
+/*
+ * Routine: set_muxconf_regs_essential
+ * Description: setup board pinmux configuration.
+ */
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_essential,
+ sizeof(wkup_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+#endif /* _CM_T54_MUX_DATA_H */
diff --git a/board/compulab/cm_t54/spl.c b/board/compulab/cm_t54/spl.c
new file mode 100644
index 0000000..5c7b2c8
--- /dev/null
+++ b/board/compulab/cm_t54/spl.c
@@ -0,0 +1,66 @@
+/*
+ * SPL specific code for Compulab CM-T54 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/emif.h>
+
+const struct emif_regs emif_regs_ddr3_532_mhz_cm_t54 = {
+#if defined(CONFIG_DRAM_1G) || defined(CONFIG_DRAM_512M)
+ .sdram_config_init = 0x618522B2,
+ .sdram_config = 0x618522B2,
+#elif defined(CONFIG_DRAM_2G)
+ .sdram_config_init = 0x618522BA,
+ .sdram_config = 0x618522BA,
+#endif
+ .sdram_config2 = 0x0,
+ .ref_ctrl = 0x00001040,
+ .sdram_tim1 = 0xEEEF36F3,
+ .sdram_tim2 = 0x348F7FDA,
+ .sdram_tim3 = 0x027F88A8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x1007190B,
+ .temp_alert_config = 0x00000000,
+
+ .emif_ddr_phy_ctlr_1_init = 0x0030400B,
+ .emif_ddr_phy_ctlr_1 = 0x0034400B,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x40000305,
+};
+
+const struct dmm_lisa_map_regs lisa_map_cm_t54 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x0,
+
+#ifdef CONFIG_DRAM_2G
+ .dmm_lisa_map_2 = 0x80740300,
+#elif defined(CONFIG_DRAM_1G)
+ .dmm_lisa_map_2 = 0x80640300,
+#elif defined(CONFIG_DRAM_512M)
+ .dmm_lisa_map_2 = 0x80500100,
+#endif
+ .dmm_lisa_map_3 = 0x00000000,
+ .is_ma_present = 0x1,
+};
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+ *regs = &emif_regs_ddr3_532_mhz_cm_t54;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+{
+ *dmm_lisa_regs = &lisa_map_cm_t54;
+}
diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile
new file mode 100644
index 0000000..dbf0009
--- /dev/null
+++ b/board/compulab/common/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Author: Igor Grinberg <grinberg@compulab.co.il>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += common.o
+obj-$(CONFIG_SYS_I2C) += eeprom.o
+obj-$(CONFIG_LCD) += omap3_display.o
+obj-$(CONFIG_SPLASH_SCREEN) += splash.o
+obj-$(CONFIG_SMC911X) += omap3_smc911x.o
diff --git a/board/compulab/common/common.c b/board/compulab/common/common.c
new file mode 100644
index 0000000..b25d9a2
--- /dev/null
+++ b/board/compulab/common/common.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bootm.h>
+#include <asm/gpio.h>
+
+#include "common.h"
+#include "eeprom.h"
+
+void cl_print_pcb_info(void)
+{
+ u32 board_rev = get_board_rev();
+ u32 rev_major = board_rev / 100;
+ u32 rev_minor = board_rev - (rev_major * 100);
+
+ if ((rev_minor / 10) * 10 == rev_minor)
+ rev_minor = rev_minor / 10;
+
+ printf("PCB: %u.%u\n", rev_major, rev_minor);
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void __weak get_board_serial(struct tag_serialnr *serialnr)
+{
+ /*
+ * This corresponds to what happens when we can communicate with the
+ * eeprom but don't get a valid board serial value.
+ */
+ serialnr->low = 0;
+ serialnr->high = 0;
+};
+#endif
+
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label)
+{
+ if (gpio_request(gpio, label)) {
+ printf("Error: can't obtain GPIO%d for %s", gpio, label);
+ return -1;
+ }
+
+ gpio_direction_output(gpio, 0);
+ udelay(10);
+ gpio_set_value(gpio, 1);
+ udelay(1000);
+ return 0;
+}
+
+void cl_usb_hub_deinit(int gpio)
+{
+ gpio_free(gpio);
+}
+#endif
diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h
new file mode 100644
index 0000000..68ffb11
--- /dev/null
+++ b/board/compulab/common/common.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CL_COMMON_
+#define _CL_COMMON_
+
+#include <asm/errno.h>
+
+void cl_print_pcb_info(void);
+
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label);
+void cl_usb_hub_deinit(int gpio);
+#else /* !CONFIG_CMD_USB */
+static inline int cl_usb_hub_init(int gpio, const char *label)
+{
+ return -ENOSYS;
+}
+static inline void cl_usb_hub_deinit(int gpio) {}
+#endif /* CONFIG_CMD_USB */
+
+#ifdef CONFIG_SPLASH_SCREEN
+int cl_splash_screen_prepare(int nand_offset);
+#else /* !CONFIG_SPLASH_SCREEN */
+static inline int cl_splash_screen_prepare(int nand_offset)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_SPLASH_SCREEN */
+
+#ifdef CONFIG_SMC911X
+int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+ int (*reset)(int), int rst_gpio);
+#else /* !CONFIG_SMC911X */
+static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+ int (*reset)(int), int rst_gpio)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_SMC911X */
+
+#endif /* _CL_COMMON_ */
diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c
new file mode 100644
index 0000000..a45e7be
--- /dev/null
+++ b/board/compulab/common/eeprom.c
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
+# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#endif
+
+#ifndef CONFIG_SYS_I2C_EEPROM_BUS
+#define CONFIG_SYS_I2C_EEPROM_BUS 0
+#endif
+
+#define EEPROM_LAYOUT_VER_OFFSET 44
+#define BOARD_SERIAL_OFFSET 20
+#define BOARD_SERIAL_OFFSET_LEGACY 8
+#define BOARD_REV_OFFSET 0
+#define BOARD_REV_OFFSET_LEGACY 6
+#define BOARD_REV_SIZE 2
+#define MAC_ADDR_OFFSET 4
+#define MAC_ADDR_OFFSET_LEGACY 0
+
+#define LAYOUT_INVALID 0
+#define LAYOUT_LEGACY 0xff
+
+static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */
+
+static int cl_eeprom_read(uint offset, uchar *buf, int len)
+{
+ int res;
+ unsigned int current_i2c_bus = i2c_get_bus_num();
+
+ res = i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
+ if (res < 0)
+ return res;
+
+ res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len);
+
+ i2c_set_bus_num(current_i2c_bus);
+
+ return res;
+}
+
+static int cl_eeprom_setup_layout(void)
+{
+ int res;
+
+ if (cl_eeprom_layout != LAYOUT_INVALID)
+ return 0;
+
+ res = cl_eeprom_read(EEPROM_LAYOUT_VER_OFFSET,
+ (uchar *)&cl_eeprom_layout, 1);
+ if (res) {
+ cl_eeprom_layout = LAYOUT_INVALID;
+ return res;
+ }
+
+ if (cl_eeprom_layout == 0 || cl_eeprom_layout >= 0x20)
+ cl_eeprom_layout = LAYOUT_LEGACY;
+
+ return 0;
+}
+
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ u32 serial[2];
+ uint offset;
+
+ memset(serialnr, 0, sizeof(*serialnr));
+
+ if (cl_eeprom_setup_layout())
+ return;
+
+ offset = (cl_eeprom_layout != LAYOUT_LEGACY) ?
+ BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY;
+
+ if (cl_eeprom_read(offset, (uchar *)serial, 8))
+ return;
+
+ if (serial[0] != 0xffffffff && serial[1] != 0xffffffff) {
+ serialnr->low = serial[0];
+ serialnr->high = serial[1];
+ }
+}
+
+/*
+ * Routine: cl_eeprom_read_mac_addr
+ * Description: read mac address and store it in buf.
+ */
+int cl_eeprom_read_mac_addr(uchar *buf)
+{
+ uint offset;
+
+ if (cl_eeprom_setup_layout())
+ return 0;
+
+ offset = (cl_eeprom_layout != LAYOUT_LEGACY) ?
+ MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY;
+
+ return cl_eeprom_read(offset, buf, 6);
+}
+
+static u32 board_rev;
+
+/*
+ * Routine: cl_eeprom_get_board_rev
+ * Description: read system revision from eeprom
+ */
+u32 cl_eeprom_get_board_rev(void)
+{
+ char str[5]; /* Legacy representation can contain at most 4 digits */
+ uint offset = BOARD_REV_OFFSET_LEGACY;
+
+ if (board_rev)
+ return board_rev;
+
+ if (cl_eeprom_setup_layout())
+ return 0;
+
+ if (cl_eeprom_layout != LAYOUT_LEGACY)
+ offset = BOARD_REV_OFFSET;
+
+ if (cl_eeprom_read(offset, (uchar *)&board_rev, BOARD_REV_SIZE))
+ return 0;
+
+ /*
+ * Convert legacy syntactic representation to semantic
+ * representation. i.e. for rev 1.00: 0x100 --> 0x64
+ */
+ if (cl_eeprom_layout == LAYOUT_LEGACY) {
+ sprintf(str, "%x", board_rev);
+ board_rev = simple_strtoul(str, NULL, 10);
+ }
+
+ return board_rev;
+};
diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h
new file mode 100644
index 0000000..85d5bf0
--- /dev/null
+++ b/board/compulab/common/eeprom.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EEPROM_
+#define _EEPROM_
+
+#ifdef CONFIG_SYS_I2C
+int cl_eeprom_read_mac_addr(uchar *buf);
+u32 cl_eeprom_get_board_rev(void);
+#else
+static inline int cl_eeprom_read_mac_addr(uchar *buf)
+{
+ return 1;
+}
+static inline u32 cl_eeprom_get_board_rev(void)
+{
+ return 0;
+}
+#endif
+
+#endif
diff --git a/board/compulab/common/omap3_display.c b/board/compulab/common/omap3_display.c
new file mode 100644
index 0000000..61707f5
--- /dev/null
+++ b/board/compulab/common/omap3_display.c
@@ -0,0 +1,454 @@
+/*
+ * (C) Copyright 2012 - 2013 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * Parsing code based on linux/drivers/video/pxafb.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <asm/arch/dss.h>
+#include <lcd.h>
+#include <scf0403_lcd.h>
+#include <asm/arch-omap3/dss.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum display_type {
+ NONE,
+ DVI,
+ DVI_CUSTOM,
+ DATA_IMAGE, /* #define CONFIG_SCF0403_LCD to use */
+};
+
+#define CMAP_ADDR 0x80100000
+
+/*
+ * The frame buffer is allocated before we have the chance to parse user input.
+ * To make sure enough memory is allocated for all resolutions, we define
+ * vl_{col | row} to the maximal resolution supported by OMAP3.
+ */
+vidinfo_t panel_info = {
+ .vl_col = 1400,
+ .vl_row = 1050,
+ .vl_bpix = LCD_BPP,
+ .cmap = (ushort *)CMAP_ADDR,
+};
+
+static struct panel_config panel_cfg;
+static enum display_type lcd_def;
+
+/*
+ * A note on DVI presets;
+ * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can
+ * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to
+ * support two BMP types with one setting.
+ */
+static const struct panel_config preset_dvi_640X480 = {
+ .lcd_size = PANEL_LCD_SIZE(640, 480),
+ .timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96),
+ .timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2),
+ .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
+ .divisor = 12 | (1 << 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_800X600 = {
+ .lcd_size = PANEL_LCD_SIZE(800, 600),
+ .timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128),
+ .timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4),
+ .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
+ .divisor = 8 | (1 << 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1024X768 = {
+ .lcd_size = PANEL_LCD_SIZE(1024, 768),
+ .timing_h = DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136),
+ .timing_v = DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6),
+ .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
+ .divisor = 5 | (1 << 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1152X864 = {
+ .lcd_size = PANEL_LCD_SIZE(1152, 864),
+ .timing_h = DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128),
+ .timing_v = DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3),
+ .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
+ .divisor = 4 | (1 << 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1280X960 = {
+ .lcd_size = PANEL_LCD_SIZE(1280, 960),
+ .timing_h = DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112),
+ .timing_v = DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3),
+ .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
+ .divisor = 3 | (1 << 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1280X1024 = {
+ .lcd_size = PANEL_LCD_SIZE(1280, 1024),
+ .timing_h = DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112),
+ .timing_v = DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3),
+ .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC,
+ .divisor = 3 | (1 << 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dataimage_480X800 = {
+ .lcd_size = PANEL_LCD_SIZE(480, 800),
+ .timing_h = DSS_HBP(2) | DSS_HFP(2) | DSS_HSW(2),
+ .timing_v = DSS_VBP(17) | DSS_VFP(20) | DSS_VSW(3),
+ .pol_freq = DSS_IVS | DSS_IHS | DSS_IPC | DSS_ONOFF,
+ .divisor = 10 | (1 << 10),
+ .data_lines = LCD_INTERFACE_18_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+/*
+ * set_resolution_params()
+ *
+ * Due to usage of multiple display related APIs resolution data is located in
+ * more than one place. This function updates them all.
+ */
+static void set_resolution_params(int x, int y)
+{
+ panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y);
+ panel_info.vl_col = x;
+ panel_info.vl_row = y;
+ lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+}
+
+static void set_preset(const struct panel_config preset, int x_res, int y_res)
+{
+ panel_cfg = preset;
+ set_resolution_params(x_res, y_res);
+}
+
+static enum display_type set_dvi_preset(const struct panel_config preset,
+ int x_res, int y_res)
+{
+ set_preset(preset, x_res, y_res);
+ return DVI;
+}
+
+static enum display_type set_dataimage_preset(const struct panel_config preset,
+ int x_res, int y_res)
+{
+ set_preset(preset, x_res, y_res);
+ return DATA_IMAGE;
+}
+
+/*
+ * parse_mode() - parse the mode parameter of custom lcd settings
+ *
+ * @mode: <res_x>x<res_y>
+ *
+ * Returns -1 on error, 0 on success.
+ */
+static int parse_mode(const char *mode)
+{
+ unsigned int modelen = strlen(mode);
+ int res_specified = 0;
+ unsigned int xres = 0, yres = 0;
+ int yres_specified = 0;
+ int i;
+
+ for (i = modelen - 1; i >= 0; i--) {
+ switch (mode[i]) {
+ case 'x':
+ if (!yres_specified) {
+ yres = simple_strtoul(&mode[i + 1], NULL, 0);
+ yres_specified = 1;
+ } else {
+ goto done_parsing;
+ }
+
+ break;
+ case '0' ... '9':
+ break;
+ default:
+ goto done_parsing;
+ }
+ }
+
+ if (i < 0 && yres_specified) {
+ xres = simple_strtoul(mode, NULL, 0);
+ res_specified = 1;
+ }
+
+done_parsing:
+ if (res_specified) {
+ set_resolution_params(xres, yres);
+ } else {
+ printf("LCD: invalid mode: %s\n", mode);
+ return -1;
+ }
+
+ return 0;
+}
+
+#define PIXEL_CLK_NUMERATOR (26 * 432 / 39)
+/*
+ * parse_pixclock() - Parse the pixclock parameter of custom lcd settings
+ *
+ * @pixclock: the desired pixel clock
+ *
+ * Returns -1 on error, 0 on success.
+ *
+ * Handling the pixel_clock:
+ *
+ * Pixel clock is defined in the OMAP35x TRM as follows:
+ * pixel_clock =
+ * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) /
+ * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] *
+ * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1))
+ *
+ * In practice, this means that in order to set the
+ * divisor for the desired pixel clock one needs to
+ * solve the following equation:
+ *
+ * 26 * 432 / (39 * <pixel_clock>) = DSS.DISPC_DIVISOR[6:0]
+ *
+ * NOTE: the explicit equation above is reduced. Do not
+ * try to infer anything from these numbers.
+ */
+static int parse_pixclock(char *pixclock)
+{
+ int divisor, pixclock_val;
+ char *pixclk_start = pixclock;
+
+ pixclock_val = simple_strtoul(pixclock, &pixclock, 10);
+ divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val);
+ /* 0 and 1 are illegal values for PCD */
+ if (divisor <= 1)
+ divisor = 2;
+
+ panel_cfg.divisor = divisor | (1 << 16);
+ if (pixclock[0] != '\0') {
+ printf("LCD: invalid value for pixclock:%s\n", pixclk_start);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * parse_setting() - parse a single setting of custom lcd parameters
+ *
+ * @setting: The custom lcd setting <name>:<value>
+ *
+ * Returns -1 on failure, 0 on success.
+ */
+static int parse_setting(char *setting)
+{
+ int num_val;
+ char *setting_start = setting;
+
+ if (!strncmp(setting, "mode:", 5)) {
+ return parse_mode(setting + 5);
+ } else if (!strncmp(setting, "pixclock:", 9)) {
+ return parse_pixclock(setting + 9);
+ } else if (!strncmp(setting, "left:", 5)) {
+ num_val = simple_strtoul(setting + 5, &setting, 0);
+ panel_cfg.timing_h |= DSS_HBP(num_val);
+ } else if (!strncmp(setting, "right:", 6)) {
+ num_val = simple_strtoul(setting + 6, &setting, 0);
+ panel_cfg.timing_h |= DSS_HFP(num_val);
+ } else if (!strncmp(setting, "upper:", 6)) {
+ num_val = simple_strtoul(setting + 6, &setting, 0);
+ panel_cfg.timing_v |= DSS_VBP(num_val);
+ } else if (!strncmp(setting, "lower:", 6)) {
+ num_val = simple_strtoul(setting + 6, &setting, 0);
+ panel_cfg.timing_v |= DSS_VFP(num_val);
+ } else if (!strncmp(setting, "hsynclen:", 9)) {
+ num_val = simple_strtoul(setting + 9, &setting, 0);
+ panel_cfg.timing_h |= DSS_HSW(num_val);
+ } else if (!strncmp(setting, "vsynclen:", 9)) {
+ num_val = simple_strtoul(setting + 9, &setting, 0);
+ panel_cfg.timing_v |= DSS_VSW(num_val);
+ } else if (!strncmp(setting, "hsync:", 6)) {
+ if (simple_strtoul(setting + 6, &setting, 0) == 0)
+ panel_cfg.pol_freq |= DSS_IHS;
+ else
+ panel_cfg.pol_freq &= ~DSS_IHS;
+ } else if (!strncmp(setting, "vsync:", 6)) {
+ if (simple_strtoul(setting + 6, &setting, 0) == 0)
+ panel_cfg.pol_freq |= DSS_IVS;
+ else
+ panel_cfg.pol_freq &= ~DSS_IVS;
+ } else if (!strncmp(setting, "outputen:", 9)) {
+ if (simple_strtoul(setting + 9, &setting, 0) == 0)
+ panel_cfg.pol_freq |= DSS_IEO;
+ else
+ panel_cfg.pol_freq &= ~DSS_IEO;
+ } else if (!strncmp(setting, "pixclockpol:", 12)) {
+ if (simple_strtoul(setting + 12, &setting, 0) == 0)
+ panel_cfg.pol_freq |= DSS_IPC;
+ else
+ panel_cfg.pol_freq &= ~DSS_IPC;
+ } else if (!strncmp(setting, "active", 6)) {
+ panel_cfg.panel_type = ACTIVE_DISPLAY;
+ return 0; /* Avoid sanity check below */
+ } else if (!strncmp(setting, "passive", 7)) {
+ panel_cfg.panel_type = PASSIVE_DISPLAY;
+ return 0; /* Avoid sanity check below */
+ } else if (!strncmp(setting, "display:", 8)) {
+ if (!strncmp(setting + 8, "dvi", 3)) {
+ lcd_def = DVI_CUSTOM;
+ return 0; /* Avoid sanity check below */
+ }
+ } else {
+ printf("LCD: unknown option %s\n", setting_start);
+ return -1;
+ }
+
+ if (setting[0] != '\0') {
+ printf("LCD: invalid value for %s\n", setting_start);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * env_parse_customlcd() - parse custom lcd params from an environment variable.
+ *
+ * @custom_lcd_params: The environment variable containing the lcd params.
+ *
+ * Returns -1 on failure, 0 on success.
+ */
+static int parse_customlcd(char *custom_lcd_params)
+{
+ char params_cpy[160];
+ char *setting;
+
+ strncpy(params_cpy, custom_lcd_params, 160);
+ setting = strtok(params_cpy, ",");
+ while (setting) {
+ if (parse_setting(setting) < 0)
+ return -1;
+
+ setting = strtok(NULL, ",");
+ }
+
+ /* Currently we don't support changing this via custom lcd params */
+ panel_cfg.data_lines = LCD_INTERFACE_24_BIT;
+ panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */
+
+ return 0;
+}
+
+/*
+ * env_parse_displaytype() - parse display type.
+ *
+ * Parses the environment variable "displaytype", which contains the
+ * name of the display type or preset, in which case it applies its
+ * configurations.
+ *
+ * Returns the type of display that was specified.
+ */
+static enum display_type env_parse_displaytype(char *displaytype)
+{
+ if (!strncmp(displaytype, "dvi640x480", 10))
+ return set_dvi_preset(preset_dvi_640X480, 640, 480);
+ else if (!strncmp(displaytype, "dvi800x600", 10))
+ return set_dvi_preset(preset_dvi_800X600, 800, 600);
+ else if (!strncmp(displaytype, "dvi1024x768", 11))
+ return set_dvi_preset(preset_dvi_1024X768, 1024, 768);
+ else if (!strncmp(displaytype, "dvi1152x864", 11))
+ return set_dvi_preset(preset_dvi_1152X864, 1152, 864);
+ else if (!strncmp(displaytype, "dvi1280x960", 11))
+ return set_dvi_preset(preset_dvi_1280X960, 1280, 960);
+ else if (!strncmp(displaytype, "dvi1280x1024", 12))
+ return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024);
+ else if (!strncmp(displaytype, "dataimage480x800", 16))
+ return set_dataimage_preset(preset_dataimage_480X800, 480, 800);
+
+ return NONE;
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ struct prcm *prcm = (struct prcm *)PRCM_BASE;
+ char *custom_lcd;
+ char *displaytype = getenv("displaytype");
+
+ if (displaytype == NULL)
+ return;
+
+ lcd_def = env_parse_displaytype(displaytype);
+ /* If we did not recognize the preset, check if it's an env variable */
+ if (lcd_def == NONE) {
+ custom_lcd = getenv(displaytype);
+ if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0)
+ return;
+ }
+
+ panel_cfg.frame_buffer = lcdbase;
+ omap3_dss_panel_config(&panel_cfg);
+ /*
+ * Pixel clock is defined with many divisions and only few
+ * multiplications of the system clock. Since DSS FCLK divisor is set
+ * to 16 by default, we need to set it to a smaller value, like 3
+ * (chosen via trial and error).
+ */
+ clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
+}
+
+#ifdef CONFIG_SCF0403_LCD
+static void scf0403_enable(void)
+{
+ gpio_direction_output(58, 1);
+ scf0403_init(157);
+}
+#else
+static inline void scf0403_enable(void) {}
+#endif
+
+void lcd_enable(void)
+{
+ switch (lcd_def) {
+ case NONE:
+ return;
+ case DVI:
+ case DVI_CUSTOM:
+ gpio_direction_output(54, 0); /* Turn on DVI */
+ break;
+ case DATA_IMAGE:
+ scf0403_enable();
+ break;
+ }
+
+ omap3_dss_enable();
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {}
diff --git a/board/compulab/common/omap3_smc911x.c b/board/compulab/common/omap3_smc911x.c
new file mode 100644
index 0000000..4561661
--- /dev/null
+++ b/board/compulab/common/omap3_smc911x.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+
+#include "common.h"
+
+static u32 cl_omap3_smc911x_gpmc_net_config[GPMC_MAX_REG] = {
+ NET_GPMC_CONFIG1,
+ NET_GPMC_CONFIG2,
+ NET_GPMC_CONFIG3,
+ NET_GPMC_CONFIG4,
+ NET_GPMC_CONFIG5,
+ NET_GPMC_CONFIG6,
+ 0
+};
+
+static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ enable_gpmc_cs_config(cl_omap3_smc911x_gpmc_net_config,
+ &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+}
+
+#ifdef CONFIG_OMAP_GPIO
+static int cl_omap3_smc911x_reset_net_chip(int gpio)
+{
+ int err;
+
+ if (!gpio_is_valid(gpio))
+ return -EINVAL;
+
+ err = gpio_request(gpio, "eth rst");
+ if (err)
+ return err;
+
+ /* Set gpio as output and send a pulse */
+ gpio_direction_output(gpio, 1);
+ udelay(1);
+ gpio_set_value(gpio, 0);
+ mdelay(40);
+ gpio_set_value(gpio, 1);
+ mdelay(1);
+
+ return 0;
+}
+#else /* !CONFIG_OMAP_GPIO */
+static inline int cl_omap3_smc911x_reset_net_chip(int gpio) { return 0; }
+#endif /* CONFIG_OMAP_GPIO */
+
+int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+ int (*reset)(int), int rst_gpio)
+{
+ int ret;
+
+ cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr);
+
+ if (reset)
+ reset(rst_gpio);
+ else
+ cl_omap3_smc911x_reset_net_chip(rst_gpio);
+
+ ret = smc911x_initialize(id, base_addr);
+ if (ret > 0)
+ return ret;
+
+ printf("Failed initializing SMC911x! ");
+ return 0;
+}
diff --git a/board/compulab/common/splash.c b/board/compulab/common/splash.c
new file mode 100644
index 0000000..49ed49b
--- /dev/null
+++ b/board/compulab/common/splash.c
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <bmp_layout.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
+{
+ struct bmp_header *bmp_hdr;
+ int res;
+ size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
+
+ if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
+ goto splash_address_too_high;
+
+ res = nand_read_skip_bad(&nand_info[nand_curr_device],
+ nand_offset, &bmp_header_size,
+ NULL, nand_info[nand_curr_device].size,
+ (u_char *)bmp_load_addr);
+ if (res < 0)
+ return res;
+
+ bmp_hdr = (struct bmp_header *)bmp_load_addr;
+ bmp_size = le32_to_cpu(bmp_hdr->file_size);
+
+ if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
+ goto splash_address_too_high;
+
+ return nand_read_skip_bad(&nand_info[nand_curr_device],
+ nand_offset, &bmp_size,
+ NULL, nand_info[nand_curr_device].size,
+ (u_char *)bmp_load_addr);
+
+splash_address_too_high:
+ printf("Error: splashimage address too high. Data overwrites U-Boot "
+ "and/or placed beyond DRAM boundaries.\n");
+
+ return -1;
+}
+#else
+static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
+{
+ return -1;
+}
+#endif /* CONFIG_CMD_NAND */
+
+int cl_splash_screen_prepare(int nand_offset)
+{
+ char *env_splashimage_value;
+ u32 bmp_load_addr;
+
+ env_splashimage_value = getenv("splashimage");
+ if (env_splashimage_value == NULL)
+ return -1;
+
+ bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
+ if (bmp_load_addr == 0) {
+ printf("Error: bad splashimage address specified\n");
+ return -1;
+ }
+
+ return splash_load_from_nand(bmp_load_addr, nand_offset);
+}
diff --git a/board/compulab/trimslice/Kconfig b/board/compulab/trimslice/Kconfig
new file mode 100644
index 0000000..3576914
--- /dev/null
+++ b/board/compulab/trimslice/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TRIMSLICE
+
+config SYS_BOARD
+ default "trimslice"
+
+config SYS_VENDOR
+ default "compulab"
+
+config SYS_CONFIG_NAME
+ default "trimslice"
+
+endif
diff --git a/board/compulab/trimslice/MAINTAINERS b/board/compulab/trimslice/MAINTAINERS
new file mode 100644
index 0000000..85b1200
--- /dev/null
+++ b/board/compulab/trimslice/MAINTAINERS
@@ -0,0 +1,7 @@
+TRIMSLICE BOARD
+M: Tom Warren <twarren@nvidia.com>
+M: Stephen Warren <swarren@nvidia.com>
+S: Maintained
+F: board/compulab/trimslice/
+F: include/configs/trimslice.h
+F: configs/trimslice_defconfig
diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile
new file mode 100644
index 0000000..311eb92
--- /dev/null
+++ b/board/compulab/trimslice/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := trimslice.o
+
+include $(srctree)/board/nvidia/common/common.mk
diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c
new file mode 100644
index 0000000..c9da80d
--- /dev/null
+++ b/board/compulab/trimslice/trimslice.c
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <netdev.h>
+
+void pin_mux_usb(void)
+{
+ /*
+ * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
+ * in the current device tree.
+ */
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
+}
+
+void pin_mux_spi(void)
+{
+ funcmux_select(PERIPH_ID_SPI1, FUNCMUX_SPI1_GMC_GMD);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+ funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT);
+ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+
+ /* For CD GPIO PP1 */
+ pinmux_tristate_disable(PMUX_PINGRP_DAP3);
+}
+
+#ifdef CONFIG_PCI
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+#endif
diff --git a/board/congatec/cgtqmx6eval/Kconfig b/board/congatec/cgtqmx6eval/Kconfig
new file mode 100644
index 0000000..0a837bd
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CGTQMX6EVAL
+
+config SYS_BOARD
+ default "cgtqmx6eval"
+
+config SYS_VENDOR
+ default "congatec"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "cgtqmx6eval"
+
+endif
diff --git a/board/congatec/cgtqmx6eval/MAINTAINERS b/board/congatec/cgtqmx6eval/MAINTAINERS
new file mode 100644
index 0000000..35f4a2a
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/MAINTAINERS
@@ -0,0 +1,6 @@
+CGTQMX6EVAL BOARD
+#M: Leo Sartre <lsartre@adeneo-embedded.com>
+S: Orphan (since 2014-06)
+F: board/congatec/cgtqmx6eval/
+F: include/configs/cgtqmx6eval.h
+F: configs/cgtqmx6qeval_defconfig
diff --git a/board/congatec/cgtqmx6eval/Makefile b/board/congatec/cgtqmx6eval/Makefile
new file mode 100644
index 0000000..1bce473
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+# (C) Copyright 2013 Adeneo Embedded <www.adeneo-embedded.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cgtqmx6eval.o
diff --git a/board/congatec/cgtqmx6eval/README b/board/congatec/cgtqmx6eval/README
new file mode 100644
index 0000000..5e76d2a
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/README
@@ -0,0 +1,28 @@
+U-Boot for the Congatec Conga-QEVAl Evaluation Carrier board with
+qmx6 quad module.
+
+This file contains information for the port of U-Boot to the Congatec
+Conga-QEVAl Evaluation Carrier board with qmx6 quad module.
+
+1. Boot source, boot from SD card
+---------------------------------
+
+By default, the Congatec board can boot only from the SPI-NOR.
+But, with the u-boot version provided with the board you can write boot
+registers to force the board to reboot and boot from the SD slot. If
+"bmode" command is not available from your pre-installed u-boot, these
+instruction will produce the same effect:
+
+conga-QMX6 U-Boot > mw.l 0x20d8040 0x3850
+conga-QMX6 U-Boot > mw.l 0x020d8044 0x10000000
+conga-QMX6 U-Boot > reset
+resetting ...
+
+The the board will reboot and, if you have written your SD correctly
+the board will use u-boot that live into the SD
+
+To copy the resulting u-boot.imx to the SD card:
+
+ dd if=u-boot.imx of=/dev/xxx bs=512 seek=2
+
+Note: Replace xxx with the device representing the SD card in your system.
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
new file mode 100644
index 0000000..7492534
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Based on mx6qsabrelite.c file
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Leo Sartre, <lsartre@adeneo-embedded.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[] = {
+ {USDHC2_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ gpio_direction_input(IMX_GPIO_NR(1, 4));
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
+ break;
+ case USDHC4_BASE_ADDR:
+ gpio_direction_input(IMX_GPIO_NR(2, 6));
+ ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
+ break;
+ default:
+ printf("Bad USDHC interface\n");
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ s32 status = 0;
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+
+ status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
+ fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+
+ return status;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Conga-QEVAL QMX6 Quad\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
+ {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ return 0;
+}
diff --git a/board/congatec/cgtqmx6eval/imximage.cfg b/board/congatec/cgtqmx6eval/imximage.cfg
new file mode 100644
index 0000000..bb6c60b
--- /dev/null
+++ b/board/congatec/cgtqmx6eval/imximage.cfg
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+
+DATA 4 0x020e05ac 0x00020030
+DATA 4 0x020e05b4 0x00020030
+DATA 4 0x020e0528 0x00020030
+DATA 4 0x020e0520 0x00020030
+
+DATA 4 0x020e0514 0x00020030
+DATA 4 0x020e0510 0x00020030
+DATA 4 0x020e05bc 0x00020030
+DATA 4 0x020e05c4 0x00020030
+
+DATA 4 0x020e056c 0x00020030
+DATA 4 0x020e0578 0x00020030
+DATA 4 0x020e0588 0x00020030
+DATA 4 0x020e0594 0x00020030
+
+DATA 4 0x020e057c 0x00020030
+DATA 4 0x020e0590 0x00003000
+DATA 4 0x020e0598 0x00003000
+DATA 4 0x020e058c 0x00000000
+
+DATA 4 0x020e059c 0x00003030
+DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0750 0x00020000
+
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0798 0x000C0000
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b0018 0x00081740
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b000c 0x555A7974
+DATA 4 0x021b0010 0xDB538F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b002c 0x000026D2
+
+DATA 4 0x021b0030 0x005A1023
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0x831A0000
+
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x0408803A
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x0000803B
+DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x00428039
+DATA 4 0x021b001c 0x19308030
+DATA 4 0x021b001c 0x19308038
+
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b001c 0x04008048
+DATA 4 0x021b0800 0xA1380003
+DATA 4 0x021b4800 0xA1380003
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b4818 0x00022227
+
+DATA 4 0x021b083c 0x434B0350
+DATA 4 0x021b0840 0x034C0359
+DATA 4 0x021b483c 0x434B0350
+DATA 4 0x021b4840 0x03650348
+DATA 4 0x021b0848 0x4436383B
+DATA 4 0x021b4848 0x39393341
+DATA 4 0x021b0850 0x35373933
+DATA 4 0x021b4850 0x48254A36
+
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+
+DATA 4 0x021b480c 0x00440044
+DATA 4 0x021b4810 0x00440044
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b001c 0x00000000
+DATA 4 0x021b0404 0x00011006
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4 0x020c4060 0x000000fb
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
new file mode 100644
index 0000000..6ca6ced
--- /dev/null
+++ b/board/coreboot/coreboot/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_COREBOOT
+
+config SYS_BOARD
+ default "coreboot"
+
+config SYS_VENDOR
+ default "coreboot"
+
+config SYS_SOC
+ default "coreboot"
+
+config SYS_CONFIG_NAME
+ default "coreboot"
+
+endif
diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
new file mode 100644
index 0000000..6ce66f5
--- /dev/null
+++ b/board/coreboot/coreboot/MAINTAINERS
@@ -0,0 +1,6 @@
+COREBOOT BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/coreboot/coreboot/
+F: include/configs/coreboot.h
+F: configs/coreboot-x86_defconfig
diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile
new file mode 100644
index 0000000..27ebe78
--- /dev/null
+++ b/board/coreboot/coreboot/Makefile
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ@gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += coreboot_start.o coreboot.o
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
new file mode 100644
index 0000000..154faf6
--- /dev/null
+++ b/board/coreboot/coreboot/coreboot.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+#include <asm/gpio.h>
+
+int arch_early_init_r(void)
+{
+ if (cros_ec_board_init())
+ return -1;
+
+ return 0;
+}
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+ return;
+}
diff --git a/board/coreboot/coreboot/coreboot_start.S b/board/coreboot/coreboot/coreboot_start.S
new file mode 100644
index 0000000..932fe6c
--- /dev/null
+++ b/board/coreboot/coreboot/coreboot_start.S
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+ /* No 32-bit board specific initialisation */
+ jmp early_board_init_ret
diff --git a/board/corscience/tricorder/Kconfig b/board/corscience/tricorder/Kconfig
new file mode 100644
index 0000000..345ac83
--- /dev/null
+++ b/board/corscience/tricorder/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TRICORDER
+
+config SYS_BOARD
+ default "tricorder"
+
+config SYS_VENDOR
+ default "corscience"
+
+config SYS_CONFIG_NAME
+ default "tricorder"
+
+endif
diff --git a/board/corscience/tricorder/MAINTAINERS b/board/corscience/tricorder/MAINTAINERS
new file mode 100644
index 0000000..8a8171b
--- /dev/null
+++ b/board/corscience/tricorder/MAINTAINERS
@@ -0,0 +1,7 @@
+TRICORDER BOARD
+M: Thomas Weber <weber@corscience.de>
+S: Maintained
+F: board/corscience/tricorder/
+F: include/configs/tricorder.h
+F: configs/tricorder_defconfig
+F: configs/tricorder_flash_defconfig
diff --git a/board/corscience/tricorder/Makefile b/board/corscience/tricorder/Makefile
new file mode 100644
index 0000000..266432d
--- /dev/null
+++ b/board/corscience/tricorder/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2012
+# Thomas Weber <weber@corscience.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := tricorder.o tricorder-eeprom.o led.o
diff --git a/board/corscience/tricorder/led.c b/board/corscience/tricorder/led.c
new file mode 100644
index 0000000..30f2f50
--- /dev/null
+++ b/board/corscience/tricorder/led.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2013 Corscience GmbH & Co.KG
+ * Andreas Bießmann <andreas.biessmann@corscience.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <status_led.h>
+#include <twl4030.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+
+#define TRICORDER_STATUS_LED_YELLOW 42
+#define TRICORDER_STATUS_LED_GREEN 43
+
+void __led_init(led_id_t mask, int state)
+{
+ __led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+ int toggle_gpio = 0;
+#ifdef STATUS_LED_BIT
+ if (!toggle_gpio && STATUS_LED_BIT & mask)
+ toggle_gpio = TRICORDER_STATUS_LED_GREEN;
+#endif
+#ifdef STATUS_LED_BIT1
+ if (!toggle_gpio && STATUS_LED_BIT1 & mask)
+ toggle_gpio = TRICORDER_STATUS_LED_YELLOW;
+#endif
+#ifdef STATUS_LED_BIT2
+ if (!toggle_gpio && STATUS_LED_BIT2 & mask) {
+ uint8_t val;
+ twl4030_i2c_read_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN,
+ &val);
+ val ^= (TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDAPWM);
+ twl4030_i2c_write_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN,
+ val);
+ }
+#endif
+ if (toggle_gpio) {
+ int state;
+ gpio_request(toggle_gpio, "");
+ state = gpio_get_value(toggle_gpio);
+ gpio_set_value(toggle_gpio, !state);
+ }
+}
+
+void __led_set(led_id_t mask, int state)
+{
+#ifdef STATUS_LED_BIT
+ if (STATUS_LED_BIT & mask) {
+ gpio_request(TRICORDER_STATUS_LED_GREEN, "");
+ gpio_direction_output(TRICORDER_STATUS_LED_GREEN, 0);
+ gpio_set_value(TRICORDER_STATUS_LED_GREEN, state);
+ }
+#endif
+#ifdef STATUS_LED_BIT1
+ if (STATUS_LED_BIT1 & mask) {
+ gpio_request(TRICORDER_STATUS_LED_YELLOW, "");
+ gpio_direction_output(TRICORDER_STATUS_LED_YELLOW, 0);
+ gpio_set_value(TRICORDER_STATUS_LED_YELLOW, state);
+ }
+#endif
+#ifdef STATUS_LED_BIT2
+ if (STATUS_LED_BIT2 & mask) {
+ if (STATUS_LED_OFF == state)
+ twl4030_i2c_write_u8(TWL4030_CHIP_LED,
+ TWL4030_LED_LEDEN, 0);
+ else
+ twl4030_i2c_write_u8(TWL4030_CHIP_LED,
+ TWL4030_LED_LEDEN,
+ (TWL4030_LED_LEDEN_LEDAON |
+ TWL4030_LED_LEDEN_LEDAPWM));
+ }
+#endif
+}
diff --git a/board/corscience/tricorder/tricorder-eeprom.c b/board/corscience/tricorder/tricorder-eeprom.c
new file mode 100644
index 0000000..1c74a0f
--- /dev/null
+++ b/board/corscience/tricorder/tricorder-eeprom.c
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2013
+ * Corscience GmbH & Co. KG, <www.corscience.de>
+ * Andreas Bießmann <andreas.biessmann@corscience.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <i2c.h>
+
+#include "tricorder-eeprom.h"
+
+static inline void warn_wrong_value(const char *msg, unsigned int a,
+ unsigned int b)
+{
+ printf("Expected EEPROM %s %08x, got %08x\n", msg, a, b);
+}
+
+static int handle_eeprom_v0(struct tricorder_eeprom *eeprom)
+{
+ struct tricorder_eeprom_v0 {
+ uint32_t magic;
+ uint16_t length;
+ uint16_t version;
+ char board_name[TRICORDER_BOARD_NAME_LENGTH];
+ char board_version[TRICORDER_BOARD_VERSION_LENGTH];
+ char board_serial[TRICORDER_BOARD_SERIAL_LENGTH];
+ uint32_t crc32;
+ } __packed eepromv0;
+ uint32_t crc;
+
+ printf("Old EEPROM (v0), consider rewrite!\n");
+
+ if (be16_to_cpu(eeprom->length) != sizeof(eepromv0)) {
+ warn_wrong_value("length", sizeof(eepromv0),
+ be16_to_cpu(eeprom->length));
+ return 1;
+ }
+
+ memcpy(&eepromv0, eeprom, sizeof(eepromv0));
+
+ crc = crc32(0L, (unsigned char *)&eepromv0,
+ sizeof(eepromv0) - sizeof(eepromv0.crc32));
+ if (be32_to_cpu(eepromv0.crc32) != crc) {
+ warn_wrong_value("CRC", be32_to_cpu(eepromv0.crc32),
+ crc);
+ return 1;
+ }
+
+ /* Ok the content is correct, do the conversion */
+ memset(eeprom->interface_version, 0x0,
+ TRICORDER_INTERFACE_VERSION_LENGTH);
+ crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE);
+ eeprom->crc32 = cpu_to_be32(crc);
+
+ return 0;
+}
+
+static int handle_eeprom_v1(struct tricorder_eeprom *eeprom)
+{
+ uint32_t crc;
+
+ if (be16_to_cpu(eeprom->length) != TRICORDER_EEPROM_SIZE) {
+ warn_wrong_value("length", TRICORDER_EEPROM_SIZE,
+ be16_to_cpu(eeprom->length));
+ return 1;
+ }
+
+ crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE);
+ if (be32_to_cpu(eeprom->crc32) != crc) {
+ warn_wrong_value("CRC", be32_to_cpu(eeprom->crc32), crc);
+ return 1;
+ }
+
+ return 0;
+}
+
+int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom)
+{
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
+
+ i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE);
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+ if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) {
+ warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC,
+ be32_to_cpu(eeprom->magic));
+ return 1;
+ }
+
+ switch (be16_to_cpu(eeprom->version)) {
+ case 0:
+ return handle_eeprom_v0(eeprom);
+ case 1:
+ return handle_eeprom_v1(eeprom);
+ default:
+ warn_wrong_value("version", TRICORDER_EEPROM_VERSION,
+ be16_to_cpu(eeprom->version));
+ return 1;
+ }
+}
+
+#if !defined(CONFIG_SPL)
+int tricorder_eeprom_read(unsigned devaddr)
+{
+ struct tricorder_eeprom eeprom;
+ int ret = tricorder_get_eeprom(devaddr, &eeprom);
+
+ if (ret)
+ return ret;
+
+ printf("Board type: %.*s\n",
+ sizeof(eeprom.board_name), eeprom.board_name);
+ printf("Board version: %.*s\n",
+ sizeof(eeprom.board_version), eeprom.board_version);
+ printf("Board serial: %.*s\n",
+ sizeof(eeprom.board_serial), eeprom.board_serial);
+ printf("Board interface version: %.*s\n",
+ sizeof(eeprom.interface_version),
+ eeprom.interface_version);
+
+ return ret;
+}
+
+int tricorder_eeprom_write(unsigned devaddr, const char *name,
+ const char *version, const char *serial, const char *interface)
+{
+ struct tricorder_eeprom eeprom, eeprom_verify;
+ size_t length;
+ uint32_t crc;
+ int ret;
+ unsigned char *p;
+ int i;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
+ memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE);
+
+ eeprom.magic = cpu_to_be32(TRICORDER_EEPROM_MAGIC);
+ eeprom.length = cpu_to_be16(TRICORDER_EEPROM_SIZE);
+ eeprom.version = cpu_to_be16(TRICORDER_EEPROM_VERSION);
+
+ length = min(sizeof(eeprom.board_name), strlen(name));
+ strncpy(eeprom.board_name, name, length);
+
+ length = min(sizeof(eeprom.board_version), strlen(version));
+ strncpy(eeprom.board_version, version, length);
+
+ length = min(sizeof(eeprom.board_serial), strlen(serial));
+ strncpy(eeprom.board_serial, serial, length);
+
+ if (interface) {
+ length = min(sizeof(eeprom.interface_version),
+ strlen(interface));
+ strncpy(eeprom.interface_version, interface, length);
+ }
+
+ crc = crc32(0L, (unsigned char *)&eeprom, TRICORDER_EEPROM_CRC_SIZE);
+ eeprom.crc32 = cpu_to_be32(crc);
+
+#if defined(DEBUG)
+ puts("Tricorder EEPROM content:\n");
+ print_buffer(0, &eeprom, 1, sizeof(eeprom), 16);
+#endif
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ /* do page write to the eeprom */
+ for (i = 0, p = (unsigned char *)&eeprom;
+ i < sizeof(eeprom);
+ i += 32, p += 32) {
+ ret = i2c_write(devaddr, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ p, min(sizeof(eeprom) - i, 32));
+ if (ret)
+ break;
+ udelay(5000); /* 5ms write cycle timing */
+ }
+
+ ret = i2c_read(devaddr, 0, 2, (unsigned char *)&eeprom_verify,
+ TRICORDER_EEPROM_SIZE);
+
+ if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) {
+ printf("Tricorder: Could not verify EEPROM content!\n");
+ ret = 1;
+ }
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+ return ret;
+}
+
+int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ if (argc == 3) {
+ ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
+ eeprom_init();
+ if (strcmp(argv[1], "read") == 0) {
+ int rcode;
+
+ rcode = tricorder_eeprom_read(dev_addr);
+
+ return rcode;
+ }
+ } else if (argc == 6 || argc == 7) {
+ ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
+ char *name = argv[3];
+ char *version = argv[4];
+ char *serial = argv[5];
+ char *interface = NULL;
+ eeprom_init();
+
+ if (argc == 7)
+ interface = argv[6];
+
+ if (strcmp(argv[1], "write") == 0) {
+ int rcode;
+
+ rcode = tricorder_eeprom_write(dev_addr, name, version,
+ serial, interface);
+
+ return rcode;
+ }
+ }
+
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ tricordereeprom, 7, 1, do_tricorder_eeprom,
+ "Tricorder EEPROM",
+ "read devaddr\n"
+ " - read Tricorder EEPROM at devaddr and print content\n"
+ "tricordereeprom write devaddr name version serial [interface]\n"
+ " - write Tricorder EEPROM at devaddr with 'name', 'version'"
+ "and 'serial'\n"
+ " optional add an HW interface parameter"
+);
+#endif /* CONFIG_SPL */
diff --git a/board/corscience/tricorder/tricorder-eeprom.h b/board/corscience/tricorder/tricorder-eeprom.h
new file mode 100644
index 0000000..06ed9a5
--- /dev/null
+++ b/board/corscience/tricorder/tricorder-eeprom.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2013
+ * Corscience GmbH & Co. KG, <www.corscience.de>
+ * Andreas Bießmann <andreas.biessmann@corscience.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef TRICORDER_EEPROM_H_
+#define TRICORDER_EEPROM_H_
+
+#include <linux/compiler.h>
+
+#define TRICORDER_EEPROM_MAGIC 0xc2a94f52
+#define TRICORDER_EEPROM_VERSION 1
+
+#define TRICORDER_BOARD_NAME_LENGTH 12
+#define TRICORDER_BOARD_VERSION_LENGTH 4
+#define TRICORDER_BOARD_SERIAL_LENGTH 12
+#define TRICORDER_INTERFACE_VERSION_LENGTH 4
+
+struct tricorder_eeprom {
+ uint32_t magic;
+ uint16_t length;
+ uint16_t version;
+ char board_name[TRICORDER_BOARD_NAME_LENGTH];
+ char board_version[TRICORDER_BOARD_VERSION_LENGTH];
+ char board_serial[TRICORDER_BOARD_SERIAL_LENGTH];
+ char interface_version[TRICORDER_INTERFACE_VERSION_LENGTH];
+ uint32_t crc32;
+} __packed;
+
+#define TRICORDER_EEPROM_SIZE sizeof(struct tricorder_eeprom)
+#define TRICORDER_EEPROM_CRC_SIZE (TRICORDER_EEPROM_SIZE - \
+ sizeof(uint32_t))
+
+/**
+ * @brief read eeprom information from a specific eeprom address
+ */
+int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom);
+
+#endif /* TRICORDER_EEPROM_H_ */
diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c
new file mode 100644
index 0000000..0fddf45
--- /dev/null
+++ b/board/corscience/tricorder/tricorder.c
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2012
+ * Corscience GmbH & Co. KG, <www.corscience.de>
+ * Thomas Weber <weber@corscience.de>
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Devkit8000 code by
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include "tricorder.h"
+#include "tricorder-eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/**
+ * get_eeprom - read the eeprom
+ *
+ * @eeprom - pointer to a eeprom struct to fill
+ *
+ * This function will panic() on wrong EEPROM content
+ */
+static void get_eeprom(struct tricorder_eeprom *eeprom)
+{
+ int ret;
+
+ if (!eeprom)
+ panic("No eeprom given!\n");
+
+ ret = gpio_request(7, "BMS");
+ if (ret)
+ panic("gpio: requesting BMS pin failed\n");
+
+ ret = gpio_direction_input(7);
+ if (ret)
+ panic("gpio: set BMS as input failed\n");
+
+ ret = gpio_get_value(7);
+ if (ret < 0)
+ panic("gpio: get BMS pin state failed\n");
+
+ gpio_free(7);
+
+ if (ret == 0) {
+ /* BMS is _not_ set, do the EEPROM check */
+ ret = tricorder_get_eeprom(0x51, eeprom);
+ if (!ret) {
+ if (strncmp(eeprom->board_name, "CS10411", 7) != 0)
+ panic("Wrong board name '%.*s'\n",
+ sizeof(eeprom->board_name),
+ eeprom->board_name);
+ if (eeprom->board_version[0] < 'D')
+ panic("Wrong board version '%.*s'\n",
+ sizeof(eeprom->board_version),
+ eeprom->board_version);
+ } else {
+ panic("Could not get board revision\n");
+ }
+ } else {
+ memset(eeprom, 0, TRICORDER_EEPROM_SIZE);
+ }
+}
+
+/**
+ * print_hwversion - print out a HW version string
+ *
+ * @eeprom - pointer to the eeprom
+ */
+static void print_hwversion(struct tricorder_eeprom *eeprom)
+{
+ size_t len;
+ if (!eeprom)
+ panic("No eeprom given!");
+
+ printf("Board %.*s:%.*s serial %.*s",
+ sizeof(eeprom->board_name), eeprom->board_name,
+ sizeof(eeprom->board_version), eeprom->board_version,
+ sizeof(eeprom->board_serial), eeprom->board_serial);
+
+ len = strnlen(eeprom->interface_version,
+ sizeof(eeprom->interface_version));
+ if (len > 0)
+ printf(" HW interface version %.*s",
+ sizeof(eeprom->interface_version),
+ eeprom->interface_version);
+ puts("\n");
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ struct tricorder_eeprom eeprom;
+ get_eeprom(&eeprom);
+ print_hwversion(&eeprom);
+
+ twl4030_power_init();
+ status_led_set(0, STATUS_LED_ON);
+ status_led_set(1, STATUS_LED_ON);
+ status_led_set(2, STATUS_LED_ON);
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_TRICORDER();
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !(defined(CONFIG_SPL_BUILD))
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank. This
+ * provides the timing values back to the function that configures
+ * the memory. We have either one or two banks of 128MB DDR.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ struct tricorder_eeprom eeprom;
+ get_eeprom(&eeprom);
+
+ /* General SDRC config */
+ if (eeprom.board_version[0] > 'D') {
+ /* use optimized timings for our SDRAM device */
+ timings->mcfg = MCFG((256 << 20), 14);
+#define MT46H64M32_TDAL 6 /* Twr/Tck + Trp/tck */
+ /* 15/6 + 18/6 = 5.5 -> 6 */
+#define MT46H64M32_TDPL 3 /* 15/6 = 2.5 -> 3 (Twr) */
+#define MT46H64M32_TRRD 2 /* 12/6 = 2 */
+#define MT46H64M32_TRCD 3 /* 18/6 = 3 */
+#define MT46H64M32_TRP 3 /* 18/6 = 3 */
+#define MT46H64M32_TRAS 7 /* 42/6 = 7 */
+#define MT46H64M32_TRC 10 /* 60/6 = 10 */
+#define MT46H64M32_TRFC 12 /* 72/6 = 12 */
+ timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC,
+ MT46H64M32_TRAS, MT46H64M32_TRP,
+ MT46H64M32_TRCD, MT46H64M32_TRRD,
+ MT46H64M32_TDPL,
+ MT46H64M32_TDAL);
+
+#define MT46H64M32_TWTR 1
+#define MT46H64M32_TCKE 1
+#define MT46H64M32_XSR 19 /* 112.5/6 = 18.75 => ~19 */
+#define MT46H64M32_TXP 1
+ timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE,
+ MT46H64M32_TXP, MT46H64M32_XSR);
+
+ timings->mr = MICRON_V_MR_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ } else {
+ /* use conservative beagleboard timings as default */
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->mr = MICRON_V_MR_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ }
+}
diff --git a/board/corscience/tricorder/tricorder.h b/board/corscience/tricorder/tricorder.h
new file mode 100644
index 0000000..67c35c5
--- /dev/null
+++ b/board/corscience/tricorder/tricorder.h
@@ -0,0 +1,359 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Corscience GmbH & Co. KG, <www.corscience.de>
+ * Thomas Weber <weber@corscience.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _TRICORDER_H_
+#define _TRICORDER_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "OMAP3 Tricorder",
+ "NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_TRICORDER() \
+ /* SDRC */\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /* GPMC */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO 42*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO 43*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0 NAND*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ /* DSS */\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /* CAMERA */\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /* Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /* MMC Slot */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
+ /* Expansion Header */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\
+ MUX_VAL(CP(UART2_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_144*/\
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*GPIO_148*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*GPIO_151*/\
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*GPIO_152*/\
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*GPIO_153*/\
+ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*GPIO_154*/\
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*GPIO_155*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*GPIO_160*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /* Serial Interface */\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | EN | M4)) /*GPIO_163 - LED2*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)) /*GPIO_164 - LED3*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ /* Host USB0 */\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*MCSPI1_SOMI*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | DIS | M0)) /*MCSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | DIS | M0)) /*MCSPI1_CS1*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+ /* USB EHCI (port 2) */\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*HSUSB2_DATA2*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA7*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA4*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA5*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*HSUSB2_DATA6*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*HSUSB2_DATA3*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 - BOOTMODE*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | EN | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | EN | M4)) /*GPIO_186 - LED1*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_12*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | EN | M4)) /*GPIO_13*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTU | EN | M1)) /*SPI3_SIMO*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTU | EN | M1)) /*SPI3_SOMI*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTU | EN | M1)) /*SPI3_CS0*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IDIS | PTU | EN | M1)) /*SPI3_CLK*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTU | EN | M4)) /*GPIO_18*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTU | EN | M4)) /*GPIO_19*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTU | EN | M4)) /*GPIO_20*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTU | EN | M1)) /*SPI3_CS1*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M4)) /*MSECURE*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\
+ /*HSUSB2 */\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTU | EN | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | EN | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | EN | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /*GPIO_29*/\
+ /* */\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*D2D_MCAD1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*D2D_MCAD2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*D2D_MCAD3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*D2D_MCAD4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*D2D_MCAD5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*D2D_MCAD6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*D2D_MCAD7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*D2D_MCAD8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*D2D_MCAD9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*D2D_MCAD10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*D2D_MCAD11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*D2D_MCAD12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*D2D_MCAD13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*D2D_MCAD14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*D2D_MCAD15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*D2D_MCAD16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*D2D_MCAD17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*D2D_MCAD18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*D2D_MCAD19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*D2D_MCAD20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*D2D_MCAD21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*D2D_MCAD22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*D2D_MCAD23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*D2D_MCAD24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*D2D_MCAD25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*D2D_MCAD26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*D2D_MCAD27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*D2D_MCAD28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*D2D_MCAD29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*D2D_MCAD30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*D2D_MCAD31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*D2D_MCAD32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*D2D_MCAD33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*D2D_MCAD34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*D2D_MCAD35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*D2D_MCAD36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*D2D_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*D2D_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*D2D_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*D2D_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*D2D_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*D2D_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*D2D_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*D2D_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*D2D_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*D2D_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*D2D_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*D2D_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*D2D_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*D2D_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*D2D_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*D2D_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*D2D_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*D2D_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*D2D_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*D2D_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*D2D_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*D2D_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*D2D_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*D2D_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*D2D_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+
+#endif
diff --git a/board/creative/xfi3/Kconfig b/board/creative/xfi3/Kconfig
new file mode 100644
index 0000000..7b681cd
--- /dev/null
+++ b/board/creative/xfi3/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_XFI3
+
+config SYS_BOARD
+ default "xfi3"
+
+config SYS_VENDOR
+ default "creative"
+
+config SYS_SOC
+ default "mxs"
+
+config SYS_CONFIG_NAME
+ default "xfi3"
+
+endif
diff --git a/board/creative/xfi3/MAINTAINERS b/board/creative/xfi3/MAINTAINERS
new file mode 100644
index 0000000..fb8235a
--- /dev/null
+++ b/board/creative/xfi3/MAINTAINERS
@@ -0,0 +1,6 @@
+XFI3 BOARD
+M: Marek Vasut <marek.vasut@gmail.com>
+S: Maintained
+F: board/creative/xfi3/
+F: include/configs/xfi3.h
+F: configs/xfi3_defconfig
diff --git a/board/creative/xfi3/Makefile b/board/creative/xfi3/Makefile
new file mode 100644
index 0000000..e8eb9ab
--- /dev/null
+++ b/board/creative/xfi3/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := xfi3.o
+else
+obj-y := spl_boot.o
+endif
diff --git a/board/creative/xfi3/spl_boot.c b/board/creative/xfi3/spl_boot.c
new file mode 100644
index 0000000..af7aa0e
--- /dev/null
+++ b/board/creative/xfi3/spl_boot.c
@@ -0,0 +1,134 @@
+/*
+ * Creative ZEN X-Fi3 setup
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* EMI */
+ MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
+
+ MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+
+ MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+
+ MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+
+ MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D07__GPIO_0_7 | MUX_CONFIG_SSP,
+
+ MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_WRN__SSP2_SCK | MUX_CONFIG_SSP,
+
+ /* PWM -- FIXME */
+ MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP,
+};
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ /* mDDR configuration values */
+ const uint32_t regs[] = {
+ 0x01010001, 0x00010000, 0x01000000, 0x00000001,
+ 0x00010101, 0x00000001, 0x00010000, 0x01000001,
+ 0x01010000, 0x00000001, 0x07000200, 0x04070203,
+ 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d,
+ 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313,
+ 0x03061323, 0x0000000a, 0x00080008, 0x00200020,
+ 0x00200020, 0x00200020, 0x000003f7, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000020, 0x00000000,
+ 0x001023cd, 0x20410010, 0x00006665, 0x00000000,
+ 0x00000101, 0x00000001, 0x00000000, 0x00000000,
+ };
+ memcpy(dram_vals, regs, sizeof(regs));
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/creative/xfi3/xfi3.c b/board/creative/xfi3/xfi3.c
new file mode 100644
index 0000000..1d83ea8
--- /dev/null
+++ b/board/creative/xfi3/xfi3.c
@@ -0,0 +1,224 @@
+/*
+ * Creative ZEN X-Fi3 board
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * Hardware investigation done by:
+ *
+ * Amaury Pouly <amaury.pouly@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+#ifdef CONFIG_CMD_MMC
+static int xfi3_mmc_cd(int id)
+{
+ switch (id) {
+ case 0:
+ /* The SSP_DETECT is inverted on this board. */
+ return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
+ case 1:
+ /* Phison bridge always present */
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /* MicroSD slot */
+ gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
+ gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0);
+ ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
+ if (ret)
+ return ret;
+
+ /* Phison SD-NAND bridge */
+ ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
+{
+ struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+ const unsigned int timeout = 0x10000;
+
+ if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
+ timeout))
+ return -ETIMEDOUT;
+
+ writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
+ (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
+ ®s->hw_lcdif_transfer_count);
+
+ writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
+ ®s->hw_lcdif_ctrl_clr);
+
+ if (data)
+ writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set);
+
+ writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
+
+ if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29,
+ timeout))
+ return -ETIMEDOUT;
+
+ writel(payload, ®s->hw_lcdif_data);
+ return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
+ timeout);
+}
+
+static void mxsfb_write_register(uint32_t reg, uint32_t data)
+{
+ mxsfb_write_byte(reg, 0);
+ mxsfb_write_byte(data, 1);
+}
+
+static const struct {
+ uint8_t reg;
+ uint8_t delay;
+ uint16_t val;
+} lcd_regs[] = {
+ { 0x01, 0, 0x001c },
+ { 0x02, 0, 0x0100 },
+ /* Writing 0x30 to reg. 0x03 flips the LCD */
+ { 0x03, 0, 0x1038 },
+ { 0x08, 0, 0x0808 },
+ /* This can contain 0x111 to rotate the LCD. */
+ { 0x0c, 0, 0x0000 },
+ { 0x0f, 0, 0x0c01 },
+ { 0x20, 0, 0x0000 },
+ { 0x21, 30, 0x0000 },
+ /* Wait 30 mS here */
+ { 0x10, 0, 0x0a00 },
+ { 0x11, 30, 0x1038 },
+ /* Wait 30 mS here */
+ { 0x12, 0, 0x1010 },
+ { 0x13, 0, 0x0050 },
+ { 0x14, 0, 0x4f58 },
+ { 0x30, 0, 0x0000 },
+ { 0x31, 0, 0x00db },
+ { 0x32, 0, 0x0000 },
+ { 0x33, 0, 0x0000 },
+ { 0x34, 0, 0x00db },
+ { 0x35, 0, 0x0000 },
+ { 0x36, 0, 0x00af },
+ { 0x37, 0, 0x0000 },
+ { 0x38, 0, 0x00db },
+ { 0x39, 0, 0x0000 },
+ { 0x50, 0, 0x0000 },
+ { 0x51, 0, 0x0705 },
+ { 0x52, 0, 0x0e0a },
+ { 0x53, 0, 0x0300 },
+ { 0x54, 0, 0x0a0e },
+ { 0x55, 0, 0x0507 },
+ { 0x56, 0, 0x0000 },
+ { 0x57, 0, 0x0003 },
+ { 0x58, 0, 0x090a },
+ { 0x59, 30, 0x0a09 },
+ /* Wait 30 mS here */
+ { 0x07, 30, 0x1017 },
+ /* Wait 40 mS here */
+ { 0x36, 0, 0x00af },
+ { 0x37, 0, 0x0000 },
+ { 0x38, 0, 0x00db },
+ { 0x39, 0, 0x0000 },
+ { 0x20, 0, 0x0000 },
+ { 0x21, 0, 0x0000 },
+};
+
+void board_mxsfb_system_setup(void)
+{
+ struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+ int i;
+
+ /* Switch the LCDIF into System-Mode */
+ writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
+ LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr);
+
+ /* Restart the SmartLCD controller */
+ mdelay(50);
+ writel(1, ®s->hw_lcdif_ctrl1_set);
+ mdelay(50);
+ writel(1, ®s->hw_lcdif_ctrl1_clr);
+ mdelay(50);
+ writel(1, ®s->hw_lcdif_ctrl1_set);
+ mdelay(50);
+
+ /* Program the SmartLCD controller */
+ writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set);
+
+ writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
+ (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
+ (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
+ (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET),
+ ®s->hw_lcdif_timing);
+
+ /*
+ * OTM2201A init and configuration sequence.
+ */
+ for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
+ mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
+ if (lcd_regs[i].delay)
+ mdelay(lcd_regs[i].delay);
+ }
+ /* Turn on Framebuffer Upload Mode */
+ mxsfb_write_byte(0x22, 0);
+
+ writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
+ ®s->hw_lcdif_ctrl_set);
+}
+#endif
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ /* Turn on PWM backlight */
+ gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ usb_eth_initialize(bis);
+ return 0;
+}
diff --git a/board/csb272/Kconfig b/board/csb272/Kconfig
new file mode 100644
index 0000000..eed04f0
--- /dev/null
+++ b/board/csb272/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_CSB272
+
+config SYS_BOARD
+ default "csb272"
+
+config SYS_CONFIG_NAME
+ default "csb272"
+
+endif
diff --git a/board/csb272/MAINTAINERS b/board/csb272/MAINTAINERS
new file mode 100644
index 0000000..4bc95ea
--- /dev/null
+++ b/board/csb272/MAINTAINERS
@@ -0,0 +1,6 @@
+CSB272 BOARD
+M: Tolunay Orkun <torkun@nextio.com>
+S: Maintained
+F: board/csb272/
+F: include/configs/csb272.h
+F: configs/csb272_defconfig
diff --git a/board/csb272/Makefile b/board/csb272/Makefile
new file mode 100644
index 0000000..36ec9b6
--- /dev/null
+++ b/board/csb272/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = csb272.o
+obj-y += init.o
diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
new file mode 100644
index 0000000..dc2c950
--- /dev/null
+++ b/board/csb272/csb272.c
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/ppc4xx-emac.h>
+
+void sdram_init(void);
+
+/*
+ * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
+ *
+ * CLKA output => Epson LCD Controller
+ * CLKB output => Not Connected
+ * CLKC output => Ethernet
+ * CLKD output => UART external clock
+ *
+ * Note: these values are obtained from device after init by micromonitor
+*/
+uchar pll_fs6377_regs[16] = {
+ 0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
+ 0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
+
+/*
+ * pll_init: Initialize AMIS IC FS6377-01 PLL
+ *
+ * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
+ *
+ */
+int pll_init(void)
+{
+ i2c_set_bus_num(0);
+
+ return i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1,
+ (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
+}
+
+/*
+ * board_early_init_f: do early board initialization
+ *
+ */
+int board_early_init_f(void)
+{
+ /* initialize PLL so UART, LCD, Ethernet clocked at correctly */
+ (void) get_clocks();
+ pll_init();
+
+ /*-------------------------------------------------------------------------+
+ | Interrupt controller setup for the Walnut board.
+ | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
+ | IRQ 16 405GP internally generated; active low; level sensitive
+ | IRQ 17-24 RESERVED
+ | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+ | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+ | IRQ 27 (EXT IRQ 2) Not Used
+ | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+ | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+ | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+ | Note for Walnut board:
+ | An interrupt taken for the FPGA (IRQ 25) indicates that either
+ | the Mouse, Keyboard, IRDA, or External Expansion caused the
+ | interrupt. The FPGA must be read to determine which device
+ | caused the interrupt. The default setting of the FPGA clears
+ |
+ +-------------------------------------------------------------------------*/
+
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */
+
+ return 0; /* success */
+}
+
+/*
+ * checkboard: identify/verify the board we are running
+ *
+ * Remark: we just assume it is correct board here!
+ *
+ */
+int checkboard(void)
+{
+ printf("BOARD: Cogent CSB272\n");
+
+ return 0; /* success */
+}
+
+/*
+ * initram: Determine the size of mounted DRAM
+ *
+ * Size is determined by reading SDRAM configuration registers as
+ * configured by initialization code
+ *
+ */
+phys_size_t initdram (int board_type)
+{
+ ulong tot_size;
+ ulong bank_size;
+ ulong tmp;
+
+ /*
+ * ToDo: Move the asm init routine sdram_init() to this C file,
+ * or even better use some common ppc4xx code available
+ * in arch/powerpc/cpu/ppc4xx
+ */
+ sdram_init();
+
+ tot_size = 0;
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ tmp = mfdcr (SDRAM0_CFGDATA);
+ if (tmp & 0x00000001) {
+ bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+ tot_size += bank_size;
+ }
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+ tmp = mfdcr (SDRAM0_CFGDATA);
+ if (tmp & 0x00000001) {
+ bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+ tot_size += bank_size;
+ }
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+ tmp = mfdcr (SDRAM0_CFGDATA);
+ if (tmp & 0x00000001) {
+ bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+ tot_size += bank_size;
+ }
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+ tmp = mfdcr (SDRAM0_CFGDATA);
+ if (tmp & 0x00000001) {
+ bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+ tot_size += bank_size;
+ }
+
+ return tot_size;
+}
+
+/*
+ * last_stage_init: final configurations (such as PHY etc)
+ *
+ */
+int last_stage_init(void)
+{
+ /* initialize the PHY */
+ miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
+
+ /* AUTO neg */
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
+ BMCR_ANENABLE | BMCR_ANRESTART);
+
+ /* LEDs */
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
+
+
+ return 0; /* success */
+}
diff --git a/board/csb272/init.S b/board/csb272/init.S
new file mode 100644
index 0000000..bf1d986
--- /dev/null
+++ b/board/csb272/init.S
@@ -0,0 +1,196 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0 IBM-pibs
+ */
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define LI32(reg,val) \
+ addis reg,0,val@h;\
+ ori reg,reg,val@l
+
+#define WDCR_EBC(reg,val) \
+ addi r4,0,reg;\
+ mtdcr EBC0_CFGADDR,r4;\
+ addis r4,0,val@h;\
+ ori r4,r4,val@l;\
+ mtdcr EBC0_CFGDATA,r4
+
+#define WDCR_SDRAM(reg,val) \
+ addi r4,0,reg;\
+ mtdcr SDRAM0_CFGADDR,r4;\
+ addis r4,0,val@h;\
+ ori r4,r4,val@l;\
+ mtdcr SDRAM0_CFGDATA,r4
+
+/******************************************************************************
+ * Function: ext_bus_cntlr_init
+ *
+ * Description: Configures EBC Controller and a few basic chip selects.
+ *
+ * CS0 is setup to get the Boot Flash out of the addresss range
+ * so that we may setup a stack. CS7 is setup so that we can
+ * access and reset the hardware watchdog.
+ *
+ * IMPORTANT: For pass1 this code must run from
+ * cache since you can not reliably change a peripheral banks
+ * timing register (pbxap) while running code from that bank.
+ * For ex., since we are running from ROM on bank 0, we can NOT
+ * execute the code that modifies bank 0 timings from ROM, so
+ * we run it from cache.
+ *
+ * Notes: Does NOT use the stack.
+ *****************************************************************************/
+ .section ".text"
+ .align 2
+ .globl ext_bus_cntlr_init
+ .type ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+ mflr r0
+ /********************************************************************
+ * Prefetch entire ext_bus_cntrl_init function into the icache.
+ * This is necessary because we are going to change the same CS we
+ * are executing from. Otherwise a CPU lockup may occur.
+ *******************************************************************/
+ bl ..getAddr
+..getAddr:
+ mflr r3 /* get address of ..getAddr */
+
+ /* Calculate number of cache lines for this function */
+ addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
+ mtctr r4
+..ebcloop:
+ icbt r0, r3 /* prefetch cache line for addr in r3*/
+ addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
+ bdnz ..ebcloop /* continue for $CTR cache lines */
+
+ /********************************************************************
+ * Delay to ensure all accesses to ROM are complete before changing
+ * bank 0 timings. 200usec should be enough.
+ * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+ *******************************************************************/
+ addis r3, 0, 0x0
+ ori r3, r3, 0xA000 /* wait 200us from reset */
+ mtctr r3
+..spinlp:
+ bdnz ..spinlp /* spin loop */
+
+ /********************************************************************
+ * SETUP CPC0_CR0
+ *******************************************************************/
+ LI32(r4, 0x007000c0)
+ mtdcr CPC0_CR0, r4
+
+ /********************************************************************
+ * Setup CPC0_CR1: Change PCIINT signal to PerWE
+ *******************************************************************/
+ mfdcr r4, CPC0_CR1
+ ori r4, r4, 0x4000
+ mtdcr CPC0_CR1, r4
+
+ /********************************************************************
+ * Setup External Bus Controller (EBC).
+ *******************************************************************/
+ WDCR_EBC(EBC0_CFG, 0xd84c0000)
+ /********************************************************************
+ * Memory Bank 0 (Intel 28F128J3 Flash) initialization
+ *******************************************************************/
+ /*WDCR_EBC(PB1AP, 0x02869200)*/
+ WDCR_EBC(PB1AP, 0x07869200)
+ WDCR_EBC(PB0CR, 0xfe0bc000)
+ /********************************************************************
+ * Memory Bank 1 (Holtek HT6542B PS/2) initialization
+ *******************************************************************/
+ WDCR_EBC(PB1AP, 0x1f869200)
+ WDCR_EBC(PB1CR, 0xf0818000)
+ /********************************************************************
+ * Memory Bank 2 (Epson S1D13506) initialization
+ *******************************************************************/
+ WDCR_EBC(PB2AP, 0x05860300)
+ WDCR_EBC(PB2CR, 0xf045a000)
+ /********************************************************************
+ * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
+ *******************************************************************/
+ WDCR_EBC(PB3AP, 0x0387d200)
+ WDCR_EBC(PB3CR, 0xf021c000)
+ /********************************************************************
+ * Memory Bank 4-7 (Unused) initialization
+ *******************************************************************/
+ WDCR_EBC(PB4AP, 0)
+ WDCR_EBC(PB4CR, 0)
+ WDCR_EBC(PB5AP, 0)
+ WDCR_EBC(PB5CR, 0)
+ WDCR_EBC(PB6AP, 0)
+ WDCR_EBC(PB6CR, 0)
+ WDCR_EBC(PB7AP, 0)
+ WDCR_EBC(PB7CR, 0)
+
+ /* We are all done */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function: sdram_init
+ *
+ * Description: Configures SDRAM memory banks.
+ *
+ * Notes: Does NOT use the stack.
+ *****************************************************************************/
+ .section ".text"
+ .align 2
+ .globl sdram_init
+ .type sdram_init, @function
+sdram_init:
+
+ /*
+ * Disable memory controller to allow
+ * values to be changed.
+ */
+ WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
+
+ /*
+ * Configure Memory Banks
+ */
+ WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
+ WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
+ WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
+ WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
+
+ /*
+ * Set up SDTR1 (SDRAM Timing Register)
+ */
+ WDCR_SDRAM(SDRAM0_TR, 0x00854009)
+
+ /*
+ * Set RTR (Refresh Timing Register)
+ */
+ WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
+ /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
+
+ /********************************************************************
+ * Delay to ensure 200usec have elapsed since reset. Assume worst
+ * case that the core is running 200Mhz:
+ * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+ *******************************************************************/
+ addis r3, 0, 0x0000
+ ori r3, r3, 0xA000 /* Wait >200us from reset */
+ mtctr r3
+..spinlp2:
+ bdnz ..spinlp2 /* spin loop */
+
+ /********************************************************************
+ * Set memory controller options reg, MCOPT1.
+ *******************************************************************/
+ WDCR_SDRAM(SDRAM0_CFG,0x80800000)
+
+..sdri_done:
+ blr /* Return to calling function */
+.Lfe1: .size sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */
diff --git a/board/csb472/Kconfig b/board/csb472/Kconfig
new file mode 100644
index 0000000..53b1e7a
--- /dev/null
+++ b/board/csb472/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_CSB472
+
+config SYS_BOARD
+ default "csb472"
+
+config SYS_CONFIG_NAME
+ default "csb472"
+
+endif
diff --git a/board/csb472/MAINTAINERS b/board/csb472/MAINTAINERS
new file mode 100644
index 0000000..25041ed
--- /dev/null
+++ b/board/csb472/MAINTAINERS
@@ -0,0 +1,6 @@
+CSB472 BOARD
+M: Tolunay Orkun <torkun@nextio.com>
+S: Maintained
+F: board/csb472/
+F: include/configs/csb472.h
+F: configs/csb472_defconfig
diff --git a/board/csb472/Makefile b/board/csb472/Makefile
new file mode 100644
index 0000000..5f7e8b5
--- /dev/null
+++ b/board/csb472/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = csb472.o
+obj-y += init.o
diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c
new file mode 100644
index 0000000..b1de18c
--- /dev/null
+++ b/board/csb472/csb472.c
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/ppc4xx-emac.h>
+
+void sdram_init(void);
+
+/*
+ * board_early_init_f: do early board initialization
+ *
+ */
+int board_early_init_f(void)
+{
+ /*-------------------------------------------------------------------------+
+ | Interrupt controller setup for the Walnut board.
+ | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
+ | IRQ 16 405GP internally generated; active low; level sensitive
+ | IRQ 17-24 RESERVED
+ | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+ | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+ | IRQ 27 (EXT IRQ 2) Not Used
+ | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+ | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+ | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+ | Note for Walnut board:
+ | An interrupt taken for the FPGA (IRQ 25) indicates that either
+ | the Mouse, Keyboard, IRDA, or External Expansion caused the
+ | interrupt. The FPGA must be read to determine which device
+ | caused the interrupt. The default setting of the FPGA clears
+ |
+ +-------------------------------------------------------------------------*/
+
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr (UIC0PR, 0xFFFFFF83); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */
+
+ return 0; /* success */
+}
+
+/*
+ * checkboard: identify/verify the board we are running
+ *
+ * Remark: we just assume it is correct board here!
+ *
+ */
+int checkboard(void)
+{
+ printf("BOARD: Cogent CSB472\n");
+
+ return 0; /* success */
+}
+
+/*
+ * initram: Determine the size of mounted DRAM
+ *
+ * Size is determined by reading SDRAM configuration registers as
+ * configured by initialization code
+ *
+ */
+phys_size_t initdram (int board_type)
+{
+ ulong tot_size;
+ ulong bank_size;
+ ulong tmp;
+
+ /*
+ * ToDo: Move the asm init routine sdram_init() to this C file,
+ * or even better use some common ppc4xx code available
+ * in arch/powerpc/cpu/ppc4xx
+ */
+ sdram_init();
+
+ tot_size = 0;
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ tmp = mfdcr (SDRAM0_CFGDATA);
+ if (tmp & 0x00000001) {
+ bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+ tot_size += bank_size;
+ }
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+ tmp = mfdcr (SDRAM0_CFGDATA);
+ if (tmp & 0x00000001) {
+ bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+ tot_size += bank_size;
+ }
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+ tmp = mfdcr (SDRAM0_CFGDATA);
+ if (tmp & 0x00000001) {
+ bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+ tot_size += bank_size;
+ }
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+ tmp = mfdcr (SDRAM0_CFGDATA);
+ if (tmp & 0x00000001) {
+ bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+ tot_size += bank_size;
+ }
+
+ return tot_size;
+}
+
+/*
+ * last_stage_init: final configurations (such as PHY etc)
+ *
+ */
+int last_stage_init(void)
+{
+ /* initialize the PHY */
+ miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
+
+ /* AUTO neg */
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
+ BMCR_ANENABLE | BMCR_ANRESTART);
+
+ /* LEDs */
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
+
+ return 0; /* success */
+}
diff --git a/board/csb472/init.S b/board/csb472/init.S
new file mode 100644
index 0000000..7383a70
--- /dev/null
+++ b/board/csb472/init.S
@@ -0,0 +1,192 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0 IBM-pibs
+ */
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define LI32(reg,val) \
+ addis reg,0,val@h;\
+ ori reg,reg,val@l
+
+#define WDCR_EBC(reg,val) \
+ addi r4,0,reg;\
+ mtdcr EBC0_CFGADDR,r4;\
+ addis r4,0,val@h;\
+ ori r4,r4,val@l;\
+ mtdcr EBC0_CFGDATA,r4
+
+#define WDCR_SDRAM(reg,val) \
+ addi r4,0,reg;\
+ mtdcr SDRAM0_CFGADDR,r4;\
+ addis r4,0,val@h;\
+ ori r4,r4,val@l;\
+ mtdcr SDRAM0_CFGDATA,r4
+
+/******************************************************************************
+ * Function: ext_bus_cntlr_init
+ *
+ * Description: Configures EBC Controller and a few basic chip selects.
+ *
+ * CS0 is setup to get the Boot Flash out of the addresss range
+ * so that we may setup a stack. CS7 is setup so that we can
+ * access and reset the hardware watchdog.
+ *
+ * IMPORTANT: For pass1 this code must run from
+ * cache since you can not reliably change a peripheral banks
+ * timing register (pbxap) while running code from that bank.
+ * For ex., since we are running from ROM on bank 0, we can NOT
+ * execute the code that modifies bank 0 timings from ROM, so
+ * we run it from cache.
+ *
+ * Notes: Does NOT use the stack.
+ *****************************************************************************/
+ .section ".text"
+ .align 2
+ .globl ext_bus_cntlr_init
+ .type ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+ mflr r0
+ /********************************************************************
+ * Prefetch entire ext_bus_cntrl_init function into the icache.
+ * This is necessary because we are going to change the same CS we
+ * are executing from. Otherwise a CPU lockup may occur.
+ *******************************************************************/
+ bl ..getAddr
+..getAddr:
+ mflr r3 /* get address of ..getAddr */
+
+ /* Calculate number of cache lines for this function */
+ addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
+ mtctr r4
+..ebcloop:
+ icbt r0, r3 /* prefetch cache line for addr in r3*/
+ addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
+ bdnz ..ebcloop /* continue for $CTR cache lines */
+
+ /********************************************************************
+ * Delay to ensure all accesses to ROM are complete before changing
+ * bank 0 timings. 200usec should be enough.
+ * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+ *******************************************************************/
+ addis r3, 0, 0x0
+ ori r3, r3, 0xA000 /* wait 200us from reset */
+ mtctr r3
+..spinlp:
+ bdnz ..spinlp /* spin loop */
+
+ /********************************************************************
+ * SETUP CPC0_CR0
+ *******************************************************************/
+ LI32(r4, 0x00c01030)
+ mtdcr CPC0_CR0, r4
+
+ /********************************************************************
+ * Setup CPC0_CR1: Change PCIINT signal to PerWE
+ *******************************************************************/
+ mfdcr r4, CPC0_CR1
+ ori r4, r4, 0x4000
+ mtdcr CPC0_CR1, r4
+
+ /********************************************************************
+ * Setup External Bus Controller (EBC).
+ *******************************************************************/
+ WDCR_EBC(EBC0_CFG, 0xd84c0000)
+ /********************************************************************
+ * Memory Bank 0 (Intel 28F640J3 Flash) initialization
+ *******************************************************************/
+ /*WDCR_EBC(PB1AP, 0x03055200)*/
+ /*WDCR_EBC(PB1AP, 0x04055200)*/
+ WDCR_EBC(PB1AP, 0x08055200)
+ WDCR_EBC(PB0CR, 0xff87a000)
+ /********************************************************************
+ * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
+ *******************************************************************/
+ /*WDCR_EBC(PB3AP, 0x07869200)*/
+ WDCR_EBC(PB3AP, 0x04055200)
+ WDCR_EBC(PB3CR, 0xf081c000)
+ /********************************************************************
+ * Memory Bank 1,2,4-7 (Unused) initialization
+ *******************************************************************/
+ WDCR_EBC(PB1AP, 0)
+ WDCR_EBC(PB1CR, 0)
+ WDCR_EBC(PB2AP, 0)
+ WDCR_EBC(PB2CR, 0)
+ WDCR_EBC(PB4AP, 0)
+ WDCR_EBC(PB4CR, 0)
+ WDCR_EBC(PB5AP, 0)
+ WDCR_EBC(PB5CR, 0)
+ WDCR_EBC(PB6AP, 0)
+ WDCR_EBC(PB6CR, 0)
+ WDCR_EBC(PB7AP, 0)
+ WDCR_EBC(PB7CR, 0)
+
+ /* We are all done */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function: sdram_init
+ *
+ * Description: Configures SDRAM memory banks.
+ *
+ * Notes: Does NOT use the stack.
+ *****************************************************************************/
+ .section ".text"
+ .align 2
+ .globl sdram_init
+ .type sdram_init, @function
+sdram_init:
+
+ /*
+ * Disable memory controller to allow
+ * values to be changed.
+ */
+ WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
+
+ /*
+ * Configure Memory Banks
+ */
+ WDCR_SDRAM(SDRAM0_B0CR, 0x00062001)
+ WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
+ WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
+ WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
+
+ /*
+ * Set up SDTR1 (SDRAM Timing Register)
+ */
+ WDCR_SDRAM(SDRAM0_TR, 0x00854009)
+
+ /*
+ * Set RTR (Refresh Timing Register)
+ */
+ WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
+ /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
+
+ /********************************************************************
+ * Delay to ensure 200usec have elapsed since reset. Assume worst
+ * case that the core is running 200Mhz:
+ * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+ *******************************************************************/
+ addis r3, 0, 0x0000
+ ori r3, r3, 0xA000 /* Wait >200us from reset */
+ mtctr r3
+..spinlp2:
+ bdnz ..spinlp2 /* spin loop */
+
+ /********************************************************************
+ * Set memory controller options reg, MCOPT1.
+ *******************************************************************/
+ WDCR_SDRAM(SDRAM0_CFG,0x80800000)
+
+..sdri_done:
+ blr /* Return to calling function */
+.Lfe1: .size sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */
diff --git a/board/d-link/dns325/Kconfig b/board/d-link/dns325/Kconfig
new file mode 100644
index 0000000..f6341ad
--- /dev/null
+++ b/board/d-link/dns325/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DNS325
+
+config SYS_BOARD
+ default "dns325"
+
+config SYS_VENDOR
+ default "d-link"
+
+config SYS_CONFIG_NAME
+ default "dns325"
+
+endif
diff --git a/board/d-link/dns325/MAINTAINERS b/board/d-link/dns325/MAINTAINERS
new file mode 100644
index 0000000..a37b799
--- /dev/null
+++ b/board/d-link/dns325/MAINTAINERS
@@ -0,0 +1,6 @@
+DNS325 BOARD
+M: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
+S: Maintained
+F: board/d-link/dns325/
+F: include/configs/dns325.h
+F: configs/dns325_defconfig
diff --git a/board/d-link/dns325/Makefile b/board/d-link/dns325/Makefile
new file mode 100644
index 0000000..c39afca
--- /dev/null
+++ b/board/d-link/dns325/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2011
+# Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dns325.o
diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c
new file mode 100644
index 0000000..75dd775
--- /dev/null
+++ b/board/d-link/dns325/dns325.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2011
+ * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+#include "dns325.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /* Gpio configuration */
+ mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
+ DNS325_OE_LOW, DNS325_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_SATA1_ACTn, /* sata1(left) status led */
+ MPP21_SATA0_ACTn, /* sata0(right) status led */
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO, /* power off out */
+ MPP25_GPIO,
+ MPP26_GPIO, /* power led */
+ MPP27_GPIO, /* sata0(right) error led */
+ MPP28_GPIO, /* sata1(left) error led */
+ MPP29_GPIO, /* usb error led */
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO, /* power key */
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO, /* enable sata 0 */
+ MPP40_GPIO, /* enable sata 1 */
+ MPP41_GPIO, /* hdd0 present */
+ MPP42_GPIO, /* hdd1 present */
+ MPP43_GPIO, /* usb status led */
+ MPP44_GPIO, /* fan status */
+ MPP45_GPIO, /* fan high speed */
+ MPP46_GPIO, /* fan low speed */
+ MPP47_GPIO, /* usb umount */
+ MPP48_GPIO, /* factory reset */
+ MPP49_GPIO, /* thermal sensor */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+
+ kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
+
+ kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Boot parameters address */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..(%s) could not read PHY dev address\n", __func__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ debug("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/d-link/dns325/dns325.h b/board/d-link/dns325/dns325.h
new file mode 100644
index 0000000..0167111
--- /dev/null
+++ b/board/d-link/dns325/dns325.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2011
+ * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DNS325_H
+#define __DNS325_H
+
+/* GPIO configuration */
+#define DNS325_OE_LOW 0x00000000
+#define DNS325_OE_HIGH 0x00039604
+#define DNS325_OE_VAL_LOW 0x38000000 /* disable leds */
+#define DNS325_OE_VAL_HIGH 0x00000800 /* disable leds */
+
+#define DNS325_GPIO_LED_POWER 26
+#define DNS325_GPIO_SATA0_EN 39
+#define DNS325_GPIO_SATA1_EN 40
+
+/* PHY related */
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __DNS325_H */
diff --git a/board/d-link/dns325/kwbimage.cfg b/board/d-link/dns325/kwbimage.cfg
new file mode 100644
index 0000000..dbd31a1
--- /dev/null
+++ b/board/d-link/dns325/kwbimage.cfg
@@ -0,0 +1,192 @@
+#
+# Copyright (C) 2011
+# Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30, 3120 DDR2 clks refresh rate
+# bit23-14: 0 required
+# bit24: 1, enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: 0 required
+# bit31-30: 0b01 required
+
+DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
+# bit3-0: 0 required
+# bit4: 0, addr/cmd in smame cycle
+# bit5: 0, clk is driven during self refresh, we don't care for APX
+# bit6: 0, use recommended falling edge of clk for addr/cmd
+# bit11-7: 0 required
+# bit12: 1 required
+# bit13: 1 required
+# bit14: 0, input buffer always powered up
+# bit17-15: 0 required
+# bit18: 1, cpu lock transaction enabled
+# bit19: 0 required
+# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0, no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low)
+# bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
+# bit7-4: 5, 6 cycle tRCD
+# bit11-8: 4, 5 cyle tRP
+# bit15-12: 5, 6 cyle tWR
+# bit19-16: 2, 3 cyle tWTR
+# bit20: 1, 18 cycle tRAS (tRAS[4])
+# bit23-21: 0 required
+# bit27-24: 2, 3 cycle tRRD
+# bit31-28: 2, 3 cyle tRTP
+
+DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
+# bit6-0: 0x33, 33 cycle tRFC
+# bit8-7: 0, 1 cycle tR2R
+# bit10-9: 0, 1 cyle tR2W
+# bit12-11: 1, 2 cylce tW2W
+# bit31-13: 0 required
+
+DATA 0xFFD01410 0x0000000c # DDR Address Control
+# bit1-0: 0, Cs0width=x8
+# bit3-2: 3, Cs0size=1Gb
+# bit5-4: 0, Cs1width=nonexistent
+# bit7-6: 0, Cs1size=nonexistent
+# bit9-8: 0, Cs2width=nonexistent
+# bit11-10: 0, Cs2size=nonexistent
+# bit13-12: 0, Cs3width=nonexistent
+# bit15-14: 0, Cs3size=nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OPEn=OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0, Cmd=Normal SDRAM Mode
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, Burst Length (2 required)
+# bit3: 0, Burst Type (0 required)
+# bit6-4: 5, CAS Latency (CL) 5
+# bit7: 0, (Test Mode) Normal operation
+# bit8: 0, (Reset DLL) Normal operation
+# bit11-9: 0, Write recovery for auto-precharge (3 required ??)
+# bit12: 0, Fast Active power down exit time (0 required)
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DRAM DLL enabled
+# bit1: 0, DRAM drive strength normal
+# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
+# bit5-3: 0 required
+# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
+# bit9-7: 0 required
+# bit10: 0, differential DQS enabled
+# bit11: 0 required
+# bit12: 0, DRAM output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 0x7 required
+# bit3: 1, MBUS Burst Chop disabled
+# bit6-4: 0x7 required
+# bit7: 0 required
+# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9: 0, no half clock cycle addition to dataout
+# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11: 0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing
+# bit3-0: 0 required
+# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
+# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
+# bit31-20: 0 required
+
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing
+# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
+# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
+# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
+# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
+# bit31-16: 0 required
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 0x0, CS0 hit selected
+# bit23-4: 0xfffff required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 1, CS1 hit selected
+# bit23-4: 0xfffff required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
+# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
+# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
+# bit15-8: 0 required
+# bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
+# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
+# bit31-24: 0 required
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
+# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
+# bit31-4 0 required
+
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+# bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
+# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
+# bit9-8: 0, Internal ODT assertion is controlled by fiels
+# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
+# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
+# bit14: 1, M_STARTBURST_IN ODT enabled
+# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
+# bit20-16: 0, Pad N channel driving strength for ODT
+# bit25-21: 0, Pad P channel driving strength for ODT
+# bit31-26: 0 required
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+# bit0: 1, enable DDR init upon this register write
+# bit31-1: 0, required
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/dave/PPChameleonEVB/Kconfig b/board/dave/PPChameleonEVB/Kconfig
new file mode 100644
index 0000000..bfe0011
--- /dev/null
+++ b/board/dave/PPChameleonEVB/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_CATCENTER
+
+config SYS_BOARD
+ default "PPChameleonEVB"
+
+config SYS_VENDOR
+ default "dave"
+
+config SYS_CONFIG_NAME
+ default "CATcenter"
+
+endif
+
+if TARGET_PPCHAMELEONEVB
+
+config SYS_BOARD
+ default "PPChameleonEVB"
+
+config SYS_VENDOR
+ default "dave"
+
+config SYS_CONFIG_NAME
+ default "PPChameleonEVB"
+
+endif
diff --git a/board/dave/PPChameleonEVB/MAINTAINERS b/board/dave/PPChameleonEVB/MAINTAINERS
new file mode 100644
index 0000000..d43c6d0
--- /dev/null
+++ b/board/dave/PPChameleonEVB/MAINTAINERS
@@ -0,0 +1,20 @@
+PPCHAMELEONEVB BOARD
+#M: -
+S: Maintained
+F: board/dave/PPChameleonEVB/
+F: include/configs/CATcenter.h
+F: configs/CATcenter_defconfig
+F: configs/CATcenter_25_defconfig
+F: configs/CATcenter_33_defconfig
+
+PPCHAMELEONEVB BOARD
+M: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+S: Maintained
+F: include/configs/PPChameleonEVB.h
+F: configs/PPChameleonEVB_defconfig
+F: configs/PPChameleonEVB_BA_25_defconfig
+F: configs/PPChameleonEVB_BA_33_defconfig
+F: configs/PPChameleonEVB_HI_25_defconfig
+F: configs/PPChameleonEVB_HI_33_defconfig
+F: configs/PPChameleonEVB_ME_25_defconfig
+F: configs/PPChameleonEVB_ME_33_defconfig
diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile
new file mode 100644
index 0000000..31edc4a
--- /dev/null
+++ b/board/dave/PPChameleonEVB/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = PPChameleonEVB.o flash.o nand.o
diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c
new file mode 100644
index 0000000..c9ab50e
--- /dev/null
+++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c
@@ -0,0 +1,231 @@
+/*
+ * (C) Copyright 2003
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+int board_early_init_f (void)
+{
+ out32(GPIO0_OR, CONFIG_SYS_NAND0_CE); /* set initial outputs */
+ out32(GPIO0_OR, CONFIG_SYS_NAND1_CE); /* set initial outputs */
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0)
+ * IRQ 26 (EXT IRQ 1)
+ * IRQ 27 (EXT IRQ 2)
+ * IRQ 28 (EXT IRQ 3)
+ * IRQ 29 (EXT IRQ 4)
+ * IRQ 30 (EXT IRQ 5)
+ * IRQ 31 (EXT IRQ 6)
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ */
+#if 1 /* test-only */
+ mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+#else
+ mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */
+#endif
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+ return 0; /* dummy implementation */
+}
+
+extern flash_info_t flash_info[]; /* info for FLASH chips */
+
+int misc_init_r (void)
+{
+ /* adjust flash start and size as well as the offset */
+ gd->bd->bi_flashstart = 0 - flash_info[0].size;
+ gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN;
+#if 0
+ volatile unsigned short *fpga_mode =
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
+ volatile unsigned char *duart0_mcr =
+ (unsigned char *)((ulong)DUART0_BA + 4);
+ volatile unsigned char *duart1_mcr =
+ (unsigned char *)((ulong)DUART1_BA + 4);
+
+ bd_t *bd = gd->bd;
+ char * tmp; /* Temporary char pointer */
+ unsigned char *dst;
+ ulong len = sizeof(fpgadata);
+ int status;
+ int index;
+ int i;
+ unsigned long CPC0_CR0Reg;
+
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ printf ("GUNZIP ERROR - must RESET board to recover\n");
+ do_reset (NULL, 0, 0, NULL);
+ }
+
+ status = fpga_boot(dst, len);
+ if (status != 0) {
+ printf("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf("(Timeout: DONE not high after programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("FPGA: %s\n", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+ /* delayed reboot */
+ for (i=20; i>0; i--) {
+ printf("Rebooting in %2d seconds \r",i);
+ for (index=0;index<1000;index++)
+ udelay(1000);
+ }
+ putc ('\n');
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ puts("FPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("%s ", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+
+ free(dst);
+
+ /*
+ * Reset FPGA via FPGA_DATA pin
+ */
+ SET_FPGA(FPGA_PRG | FPGA_CLK);
+ udelay(1000); /* wait 1ms */
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+ udelay(1000); /* wait 1ms */
+#endif
+
+#if 0
+ /*
+ * Enable power on PS/2 interface
+ */
+ *fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET;
+
+ /*
+ * Enable interrupts in exar duart mcr[3]
+ */
+ *duart0_mcr = 0x08;
+ *duart1_mcr = 0x08;
+#endif
+ return (0);
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming PPChameleonEVB");
+ } else {
+ puts(str);
+ }
+
+ putc ('\n');
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+ /* TODO: XXX XXX XXX */
+ printf ("test: 16 MB - ok\n");
+
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_CFB_CONSOLE
+# ifdef CONFIG_CONSOLE_EXTRA_INFO
+# include <video_fb.h>
+extern GraphicDevice smi;
+
+void video_get_info_str (int line_number, char *info)
+{
+ uint pvr = get_pvr ();
+
+ /* init video info strings for graphic console */
+ switch (line_number) {
+ case 1:
+ switch (pvr) {
+ case PVR_405EP_RB:
+ sprintf (info, " AMCC PowerPC 405EP Rev. B");
+ break;
+ default:
+ sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
+ break;
+ }
+ return;
+ case 2:
+ sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
+ return;
+ case 3:
+ sprintf (info, " %s", smi.modeIdent);
+ return;
+ }
+
+ /* no more info lines */
+ *info = 0;
+ return;
+}
+# endif /* CONFIG_CONSOLE_EXTRA_INFO */
+#endif /* CONFIG_CFB_CONSOLE */
diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c
new file mode 100644
index 0000000..771151b
--- /dev/null
+++ b/board/dave/PPChameleonEVB/flash.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#ifdef __DEBUG_START_FROM_SRAM__
+ return CONFIG_SYS_DUMMY_FLASH_SIZE;
+#else
+ unsigned long size;
+ int i;
+ uint pbcr;
+ unsigned long base;
+ int size_val = 0;
+
+ debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
+ debug("[%s, %d] flash_info = 0x%p ...\n", __func__, __LINE__,
+ flash_info);
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ debug("[%s, %d] Calling flash_get_size ...\n", __FUNCTION__, __LINE__);
+ size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size, size<<20);
+ }
+
+ debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+
+ /* Setup offsets */
+ flash_get_offsets (-size, &flash_info[0]);
+ debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base = -size;
+ switch (size) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+ debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+ flash_info[0].size = size;
+
+ return (size);
+#endif
+}
diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c
new file mode 100644
index 0000000..a191a0c
--- /dev/null
+++ b/board/dave/PPChameleonEVB/nand.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
+ */
+static void ppchameleonevb_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+ ulong base = (ulong) this->IO_ADDR_W;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if ( ctrl & NAND_CLE )
+ MACRO_NAND_CTL_SETCLE((unsigned long)base);
+ else
+ MACRO_NAND_CTL_CLRCLE((unsigned long)base);
+ if ( ctrl & NAND_ALE )
+ MACRO_NAND_CTL_CLRCLE((unsigned long)base);
+ else
+ MACRO_NAND_CTL_CLRALE((unsigned long)base);
+ if ( ctrl & NAND_NCE )
+ MACRO_NAND_ENABLE_CE((unsigned long)base);
+ else
+ MACRO_NAND_DISABLE_CE((unsigned long)base);
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+
+/*
+ * read device ready pin
+ * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
+ */
+static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ ulong rb_gpio_pin;
+
+ /* use the base addr to find out which chip are we dealing with */
+ switch((ulong) this->IO_ADDR_W) {
+ case CONFIG_SYS_NAND0_BASE:
+ rb_gpio_pin = CONFIG_SYS_NAND0_RDY;
+ break;
+ case CONFIG_SYS_NAND1_BASE:
+ rb_gpio_pin = CONFIG_SYS_NAND1_RDY;
+ break;
+ default: /* this should never happen */
+ return 0;
+ break;
+ }
+
+ if (in32(GPIO0_IR) & rb_gpio_pin)
+ return 1;
+ return 0;
+}
+
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - cmd_ctrl: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
+ * only be provided if a hardware ECC is available
+ * - ecc.mode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ * read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ * nand_scan about special functionality. See the defines for further
+ * explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+
+ nand->cmd_ctrl = ppchameleonevb_hwcontrol;
+ nand->dev_ready = ppchameleonevb_device_ready;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->chip_delay = NAND_BIG_DELAY_US;
+ nand->options = NAND_SAMSUNG_LP_OPTIONS;
+ return 0;
+}
+#endif
diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds
new file mode 100644
index 0000000..94b7076
--- /dev/null
+++ b/board/dave/PPChameleonEVB/u-boot.lds
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "config.h"
+
+#ifndef RESET_VECTOR_ADDRESS
+#define RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+OUTPUT_ARCH(powerpc)
+
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .text :
+ {
+ *(.text*)
+ } :text
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } :text
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
+ . = 0xFFFF8000;
+ .ppcenv :
+ {
+ common/env_embedded.o(.ppcenv);
+ }
+
+ .resetvec RESET_VECTOR_ADDRESS :
+ {
+ KEEP(*(.resetvec))
+ } :text = 0xffff
+
+ . = RESET_VECTOR_ADDRESS + 0x4;
+
+ /*
+ * Make sure that the bss segment isn't linked at 0x0, otherwise its
+ * address won't be updated during relocation fixups. Note that
+ * this is a temporary fix. Code to dynamically the fixup the bss
+ * location will be added in the future. When the bss relocation
+ * fixup code is present this workaround should be removed.
+ */
+#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
+ . |= 0x10;
+#endif
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ } :bss
+
+ . = ALIGN(4);
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/dave/common/flash.c b/board/dave/common/flash.c
new file mode 100644
index 0000000..f05adf9
--- /dev/null
+++ b/board/dave/common/flash.c
@@ -0,0 +1,691 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+ short n;
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+ /* set sector offsets for bottom boot block type */
+ for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
+ info->start[i] = base;
+ base += 8 << 10;
+ }
+ while (i < info->sector_count) { /* 64k regular sectors */
+ info->start[i] = base;
+ base += 64 << 10;
+ ++i;
+ }
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ case FLASH_MAN_SST: printf ("SST "); break;
+ case FLASH_MAN_STM: printf ("ST "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n");
+ break;
+ case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n");
+ break;
+ case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n");
+ break;
+ case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AM640U: printf ("AM29LV640D (64 M, uniform sector)\n");
+ break;
+ case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_STMW320DT: printf ("M29W320DT (32 M, top sector)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count-1))
+ size = info->start[i+1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k=0; k<size; k++)
+ {
+ if (*flash++ != 0xffffffff)
+ {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf ("\n ");
+ /* print empty and read-only info */
+ printf (" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " ");
+#else
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+#endif
+
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ short n;
+ CONFIG_SYS_FLASH_WORD_SIZE value;
+ ulong base = (ulong)addr;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
+
+ debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
+
+ value = addr2[CONFIG_SYS_FLASH_READ0];
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
+ info->flash_id += FLASH_STMW320DT;
+ info->sector_count = 67;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
+ info->flash_id += FLASH_AMDL322T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
+ info->flash_id += FLASH_AMDL322B;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
+ info->flash_id += FLASH_AMDL323T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
+ info->flash_id += FLASH_AMDL323B;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
+ info->flash_id += FLASH_AM640U;
+ info->sector_count = 128;
+ info->size = 0x00800000; break; /* => 8 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
+ info->flash_id += FLASH_SST800A;
+ info->sector_count = 16;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
+ info->flash_id += FLASH_SST160A;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+ /* set sector offsets for bottom boot block type */
+ for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
+ info->start[i] = base;
+ base += 8 << 10;
+ }
+ while (i < info->sector_count) { /* 64k regular sectors */
+ info->start[i] = base;
+ base += 64 << 10;
+ ++i;
+ }
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ /* 1 x 16k boot sector */
+ base -= 16 << 10;
+ --i;
+ info->start[i] = base;
+ /* 2 x 8k boot sectors */
+ for (n=0; n<2; ++n) {
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ /* 1 x 32k boot sector */
+ base -= 32 << 10;
+ --i;
+ info->start[i] = base;
+
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+ *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050; /* block erase */
+ for (i=0; i<50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ if (sect == s_first) {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ }
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+ while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+DONE:
+ /* reset to read mode */
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+ addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+#ifdef CONFIG_B2
+ data = data | ((*(uchar *)cp)<<(8*i));
+#else
+ data = (data << 8) | (*(uchar *)cp);
+#endif
+ }
+ for (; i<4 && cnt>0; ++i) {
+#ifdef CONFIG_B2
+ data = data | ((*src++)<<(8*i));
+#else
+ data = (data << 8) | *src++;
+#endif
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+#ifdef CONFIG_B2
+ data = data | ((*(uchar *)cp)<<(8*i));
+#else
+ data = (data << 8) | (*(uchar *)cp);
+#endif
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+#ifdef CONFIG_B2
+ data = (*(ulong*)src);
+ src += 4;
+#else
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+#endif
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+#ifdef CONFIG_B2
+ data = data | ((*src++)<<(8*i));
+#else
+ data = (data << 8) | *src++;
+#endif
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+#ifdef CONFIG_B2
+ data = data | ((*(uchar *)cp)<<(8*i));
+#else
+ data = (data << 8) | (*(uchar *)cp);
+#endif
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ ulong *data_ptr = &data;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
+ ulong start;
+ int flag;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((volatile ulong *)dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
+ {
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+ (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/davedenx/aria/Kconfig b/board/davedenx/aria/Kconfig
new file mode 100644
index 0000000..54a86b9
--- /dev/null
+++ b/board/davedenx/aria/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ARIA
+
+config SYS_BOARD
+ default "aria"
+
+config SYS_VENDOR
+ default "davedenx"
+
+config SYS_CONFIG_NAME
+ default "aria"
+
+endif
diff --git a/board/davedenx/aria/MAINTAINERS b/board/davedenx/aria/MAINTAINERS
new file mode 100644
index 0000000..a6152c9
--- /dev/null
+++ b/board/davedenx/aria/MAINTAINERS
@@ -0,0 +1,6 @@
+ARIA BOARD
+M: Wolfgang Denk <wd@denx.de>
+S: Maintained
+F: board/davedenx/aria/
+F: include/configs/aria.h
+F: configs/aria_defconfig
diff --git a/board/davedenx/aria/Makefile b/board/davedenx/aria/Makefile
new file mode 100644
index 0000000..dd38b7f
--- /dev/null
+++ b/board/davedenx/aria/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := aria.o
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
new file mode 100644
index 0000000..a15a9ed
--- /dev/null
+++ b/board/davedenx/aria/aria.c
@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t initdram (int board_type)
+{
+ return fixed_sdram(NULL, NULL, 0);
+}
+
+int misc_init_r(void)
+{
+ u32 tmp;
+
+ /* we use I2C-2 for on-board eeprom */
+ i2c_set_bus_num(2);
+
+ tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
+ printf("FPGA: %u-%u.%u.%u\n",
+ (tmp & 0xFF000000) >> 24,
+ (tmp & 0x00FF0000) >> 16,
+ (tmp & 0x0000FF00) >> 8,
+ tmp & 0x000000FF
+ );
+
+ return 0;
+}
+
+static iopin_t ioregs_init[] = {
+ /*
+ * FEC
+ */
+
+ /* FEC on PSCx_x*/
+ {
+ offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ {
+ offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ {
+ offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+
+ /*
+ * DIU
+ */
+ /* FUNC2=DIU CLK */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIU_HSYNC */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /*
+ * On board SRAM
+ */
+ /* FUNC2=/LPC CS6 */
+ {
+ offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+};
+
+int checkboard (void)
+{
+ puts("Board: ARIA\n");
+
+ /* initialize function mux & slew rate IO inter alia on IO Pins */
+
+ iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/davedenx/qong/Kconfig b/board/davedenx/qong/Kconfig
new file mode 100644
index 0000000..76cf343
--- /dev/null
+++ b/board/davedenx/qong/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_QONG
+
+config SYS_BOARD
+ default "qong"
+
+config SYS_VENDOR
+ default "davedenx"
+
+config SYS_SOC
+ default "mx31"
+
+config SYS_CONFIG_NAME
+ default "qong"
+
+endif
diff --git a/board/davedenx/qong/MAINTAINERS b/board/davedenx/qong/MAINTAINERS
new file mode 100644
index 0000000..a275b5b
--- /dev/null
+++ b/board/davedenx/qong/MAINTAINERS
@@ -0,0 +1,6 @@
+QONG BOARD
+M: Wolfgang Denk <wd@denx.de>
+S: Maintained
+F: board/davedenx/qong/
+F: include/configs/qong.h
+F: configs/qong_defconfig
diff --git a/board/davedenx/qong/Makefile b/board/davedenx/qong/Makefile
new file mode 100644
index 0000000..48c443d
--- /dev/null
+++ b/board/davedenx/qong/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2009
+# Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := qong.o fpga.o
+obj-y += lowlevel_init.o
diff --git a/board/davedenx/qong/fpga.c b/board/davedenx/qong/fpga.c
new file mode 100644
index 0000000..2eaad1e
--- /dev/null
+++ b/board/davedenx/qong/fpga.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/gpio.h>
+#include <fpga.h>
+#include <lattice.h>
+#include "qong_fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+static void qong_jtag_init(void)
+{
+ return;
+}
+
+static void qong_fpga_jtag_set_tdi(int value)
+{
+ gpio_set_value(QONG_FPGA_TDI_PIN, value);
+}
+
+static void qong_fpga_jtag_set_tms(int value)
+{
+ gpio_set_value(QONG_FPGA_TMS_PIN, value);
+}
+
+static void qong_fpga_jtag_set_tck(int value)
+{
+ gpio_set_value(QONG_FPGA_TCK_PIN, value);
+}
+
+static int qong_fpga_jtag_get_tdo(void)
+{
+ return gpio_get_value(QONG_FPGA_TDO_PIN);
+}
+
+lattice_board_specific_func qong_fpga_fns = {
+ qong_jtag_init,
+ qong_fpga_jtag_set_tdi,
+ qong_fpga_jtag_set_tms,
+ qong_fpga_jtag_set_tck,
+ qong_fpga_jtag_get_tdo
+};
+
+Lattice_desc qong_fpga[CONFIG_FPGA_COUNT] = {
+ {
+ Lattice_XP2,
+ lattice_jtag_mode,
+ 356519,
+ (void *) &qong_fpga_fns,
+ NULL,
+ 0,
+ "lfxp2_5e_ftbga256"
+ },
+};
+
+int qong_fpga_init(void)
+{
+ int i;
+
+ fpga_init();
+
+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+ fpga_add(fpga_lattice, &qong_fpga[i]);
+ }
+ return 0;
+}
+
+#endif
diff --git a/board/davedenx/qong/lowlevel_init.S b/board/davedenx/qong/lowlevel_init.S
new file mode 100644
index 0000000..8887023
--- /dev/null
+++ b/board/davedenx/qong/lowlevel_init.S
@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * Based on board/freescale/mx31ads/lowlevel_init.S
+ * by Guennadi Liakhovetski.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/imx-regs.h>
+
+.macro REG reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ strb r3, [r2]
+.endm
+
+.macro DELAY loops
+ ldr r2, =\loops
+1:
+ subs r2, r2, #1
+ nop
+ bcs 1b
+.endm
+
+.macro SETUP_RAM cfg, ctl
+ /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
+ REG 0xB8001010, 0x00000004
+ ldr r3, =\cfg
+ ldr r2, =WEIM_ESDCFG0
+ str r3, [r2]
+ REG 0xB8001000, 0x92100000
+ REG 0x80000f00, 0x12344321
+ REG 0xB8001000, 0xa2100000
+ REG 0x80000000, 0x12344321
+ REG 0x80000000, 0x12344321
+ REG 0xB8001000, 0xb2100000
+ REG8 0x80000033, 0xda
+ REG8 0x81000000, 0xff
+ ldr r3, =\ctl
+ ldr r2, =WEIM_ESDCTL0
+ str r3, [r2]
+ REG 0x80000000, 0xDEADBEEF
+ REG 0xB8001010, 0x0000000c
+
+.endm
+/* RedBoot: To support 133MHz DDR */
+.macro init_drive_strength
+ /*
+ * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+ * in SW_PAD_CTL registers
+ */
+
+ /* SDCLK */
+ ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
+ ldr r0, [r1, #0x6C]
+ bic r0, r0, #(1 << 12)
+ str r0, [r1, #0x6C]
+
+ /* CAS */
+ ldr r0, [r1, #0x70]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x70]
+
+ /* RAS */
+ ldr r0, [r1, #0x74]
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x74]
+
+ /* CS2 (CSD0) */
+ ldr r0, [r1, #0x7C]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x7C]
+
+ /* DQM3 */
+ ldr r0, [r1, #0x84]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x84]
+
+ /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+ ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+ ldr r0, [r1, #0x88]
+ bic r0, r0, #(1 << 22)
+ bic r0, r0, #(1 << 12)
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x88]
+ add r1, r1, #4
+ subs r2, r2, #0x1
+ bne pad_loop
+.endm /* init_drive_strength */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ init_drive_strength
+
+ /* Image Processing Unit: */
+ /* Too early to switch display on? */
+ /* Switch on Display Interface */
+ REG IPU_CONF, IPU_CONF_DI_EN
+ /* Clock Control Module: */
+ REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
+
+ DELAY 0x40000
+
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
+ /* Switch to MCU PLL */
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+ /* 399-133-66.5 */
+ ldr r0, =CCM_BASE
+ ldr r1, =0xFF871650
+ /* PDR0 */
+ str r1, [r0, #0x4]
+ ldr r1, MPCTL_PARAM_399
+ /* MPCTL */
+ str r1, [r0, #0x10]
+
+ /* Set UPLL=240MHz, USB=60MHz */
+ ldr r1, =0x49FCFE7F
+ /* PDR1 */
+ str r1, [r0, #0x8]
+ ldr r1, UPCTL_PARAM_240
+ /* UPCTL */
+ str r1, [r0, #0x14]
+ /* default CLKO to 1/8 of the ARM core */
+ mov r1, #0x00000208
+ /* COSR */
+ str r1, [r0, #0x1c]
+
+ /* Default: 1, 4, 12, 1 */
+ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+check_ddr_module:
+/* Set stackpointer in internal RAM to call get_ram_size */
+ ldr sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16)
+ stmfd sp!, {r0-r11, ip, lr}
+ mov ip, lr /* save link reg across call */
+
+ ldr r0,=0x08000000
+ SETUP_RAM ESDCFG0_256MB, ESDCTL0_256MB
+ ldr r0,=0x80000000
+ ldr r1,=0x10000000
+ bl get_ram_size
+ ldr r1,=0x10000000
+ cmp r0,r1
+ beq restore_regs
+ SETUP_RAM ESDCFG0_128MB, ESDCTL0_128MB
+ ldr r0,=0x80000000
+ ldr r1,=0x08000000
+ bl get_ram_size
+ ldr r1,=0x08000000
+ cmp r0,r1
+ beq restore_regs
+
+restore_regs:
+ ldmfd sp!, {r0-r11, ip, lr}
+ mov lr, ip /* restore link reg */
+
+ mov pc, lr
+
+
+MPCTL_PARAM_399:
+ .word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
+UPCTL_PARAM_240:
+ .word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0))
+
+ .equ ESDCFG0_128MB, \
+ (0 << 21) + /* tXP */ \
+ (1 << 20) + /* tWTR */ \
+ (2 << 18) + /* tRP */ \
+ (1 << 16) + /* tMRD */ \
+ (0 << 15) + /* tWR */ \
+ (5 << 12) + /* tRAS */ \
+ (1 << 10) + /* tRRD */ \
+ (3 << 8) + /* tCAS */ \
+ (2 << 4) + /* tRCD */ \
+ (0x0F << 0) /* tRC */
+
+ .equ ESDCTL0_128MB, \
+ (1 << 31) + /* enable */ \
+ (0 << 28) + /* mode */ \
+ (0 << 27) + /* supervisor protect */ \
+ (2 << 24) + /* 13 rows */ \
+ (2 << 20) + /* 10 cols */ \
+ (2 << 16) + /* 32 bit */ \
+ (3 << 13) + /* 7.81us (64ms/8192) */ \
+ (0 << 10) + /* power down timer */ \
+ (0 << 8) + /* full page */ \
+ (1 << 7) + /* burst length */ \
+ (0 << 0) /* precharge timer */
+
+ .equ ESDCFG0_256MB, \
+ (3 << 21) + /* tXP */ \
+ (0 << 20) + /* tWTR */ \
+ (2 << 18) + /* tRP */ \
+ (1 << 16) + /* tMRD */ \
+ (0 << 15) + /* tWR */ \
+ (5 << 12) + /* tRAS */ \
+ (1 << 10) + /* tRRD */ \
+ (3 << 8) + /* tCAS */ \
+ (2 << 4) + /* tRCD */ \
+ (7 << 0) /* tRC */
+
+ .equ ESDCTL0_256MB, \
+ (1 << 31) + \
+ (0 << 28) + \
+ (0 << 27) + \
+ (3 << 24) + /* 14 rows */ \
+ (2 << 20) + /* 10 cols */ \
+ (2 << 16) + \
+ (4 << 13) + /* 3.91us (64ms/16384) */ \
+ (0 << 10) + \
+ (0 << 8) + \
+ (1 << 7) + \
+ (0 << 0)
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
new file mode 100644
index 0000000..ad1694b
--- /dev/null
+++ b/board/davedenx/qong/qong.c
@@ -0,0 +1,259 @@
+/*
+ *
+ * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <asm/gpio.h>
+#include "qong_fpga.h"
+#include <watchdog.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+static void qong_fpga_reset(void)
+{
+ gpio_set_value(QONG_FPGA_RST_PIN, 0);
+ udelay(30);
+ gpio_set_value(QONG_FPGA_RST_PIN, 1);
+
+ udelay(300);
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_QONG_FPGA
+ /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
+ static const struct mxc_weimcs cs1 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(1, &cs1);
+
+ /* setup pins for FPGA */
+ mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
+
+ /* FPGA reset Pin */
+ /* rstn = 0 */
+ gpio_direction_output(QONG_FPGA_RST_PIN, 0);
+
+ /* set interrupt pin as input */
+ gpio_direction_input(QONG_FPGA_IRQ_PIN);
+
+ /* FPGA JTAG Interface */
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
+ gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
+ gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
+ gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
+ gpio_direction_input(QONG_FPGA_TDO_PIN);
+#endif
+
+ /* setup pins for UART1 */
+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+ mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+ /* setup pins for SPI (pmic) */
+ mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+ mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+ mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+ mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+ mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+
+ /* Setup pins for USB2 Host */
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
+
+#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+ mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
+ mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
+ mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
+ mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
+ mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
+ mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
+ mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
+ mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
+ mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
+ mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
+ mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
+ mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
+
+ mx31_set_gpr(MUX_PGP_UH2, 1);
+
+ return 0;
+
+}
+
+int board_init(void)
+{
+ /* Chip selects */
+ /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
+ /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
+ static const struct mxc_weimcs cs0 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(0, &cs0);
+
+ /* board id for linux */
+ gd->bd->bi_arch_number = MACH_TYPE_QONG;
+ gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
+
+ qong_fpga_init();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ u32 val;
+ struct pmic *p;
+ int ret;
+
+ ret = pmic_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return -ENODEV;
+ /* Enable RTC battery */
+ pmic_reg_read(p, REG_POWER_CTL0, &val);
+ pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
+ pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
+
+#ifdef CONFIG_HW_WATCHDOG
+ hw_watchdog_init();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: DAVE/DENX Qong\n");
+ return 0;
+}
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_QONG_FPGA
+ u32 tmp;
+
+ tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
+ printf("FPGA: ");
+ printf("version register = %u.%u.%u\n",
+ (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
+#endif
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
+ return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
+#else
+ return 0;
+#endif
+}
+
+#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
+static void board_nand_setup(void)
+{
+ /* CS3: NAND 8-bit */
+ static const struct mxc_weimcs cs3 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(3, &cs3);
+
+ mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
+
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
+
+ /* Make sure to reset the fpga else you cannot access NAND */
+ qong_fpga_reset();
+
+ /* Enable NAND flash */
+ gpio_set_value(15, 1);
+ gpio_set_value(14, 1);
+ gpio_direction_output(15, 0);
+ gpio_direction_input(16);
+ gpio_direction_input(14);
+
+}
+
+int qong_nand_rdy(void *chip)
+{
+ udelay(1);
+ return gpio_get_value(16);
+}
+
+void qong_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ if (chip >= 0)
+ gpio_set_value(15, 0);
+ else
+ gpio_set_value(15, 1);
+
+}
+
+void qong_nand_plat_init(void *chip)
+{
+ struct nand_chip *nand = (struct nand_chip *)chip;
+ nand->chip_delay = 20;
+ nand->select_chip = qong_nand_select_chip;
+ nand->options &= ~NAND_BUSWIDTH_16;
+ board_nand_setup();
+}
+
+#endif
diff --git a/board/davedenx/qong/qong_fpga.h b/board/davedenx/qong/qong_fpga.h
new file mode 100644
index 0000000..2a619f7
--- /dev/null
+++ b/board/davedenx/qong/qong_fpga.h
@@ -0,0 +1,23 @@
+/*
+ *
+ * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef QONG_FPGA_H
+#define QONG_FPGA_H
+
+#define QONG_FPGA_CTRL_BASE CONFIG_FPGA_BASE
+#define QONG_FPGA_CTRL_VERSION (QONG_FPGA_CTRL_BASE + 0x00000000)
+#define QONG_FPGA_PERIPH_SIZE (1 << 24)
+
+#define QONG_FPGA_TCK_PIN 26
+#define QONG_FPGA_TMS_PIN 25
+#define QONG_FPGA_TDI_PIN 8
+#define QONG_FPGA_TDO_PIN 7
+#define QONG_FPGA_RST_PIN 48
+#define QONG_FPGA_IRQ_PIN 40
+
+int qong_fpga_init(void);
+#endif /* QONG_FPGA_H */
diff --git a/board/davinci/da8xxevm/Kconfig b/board/davinci/da8xxevm/Kconfig
new file mode 100644
index 0000000..1a841ce
--- /dev/null
+++ b/board/davinci/da8xxevm/Kconfig
@@ -0,0 +1,38 @@
+if TARGET_DA830EVM
+
+config SYS_BOARD
+ default "da8xxevm"
+
+config SYS_VENDOR
+ default "davinci"
+
+config SYS_CONFIG_NAME
+ default "da830evm"
+
+endif
+
+if TARGET_DA850EVM
+
+config SYS_BOARD
+ default "da8xxevm"
+
+config SYS_VENDOR
+ default "davinci"
+
+config SYS_CONFIG_NAME
+ default "da850evm"
+
+endif
+
+if TARGET_HAWKBOARD
+
+config SYS_BOARD
+ default "da8xxevm"
+
+config SYS_VENDOR
+ default "davinci"
+
+config SYS_CONFIG_NAME
+ default "hawkboard"
+
+endif
diff --git a/board/davinci/da8xxevm/MAINTAINERS b/board/davinci/da8xxevm/MAINTAINERS
new file mode 100644
index 0000000..dd66f07
--- /dev/null
+++ b/board/davinci/da8xxevm/MAINTAINERS
@@ -0,0 +1,22 @@
+DA8XXEVM BOARD
+M: Nick Thompson <nick.thompson@gefanuc.com>
+S: Maintained
+F: board/davinci/da8xxevm/
+F: include/configs/da830evm.h
+F: configs/da830evm_defconfig
+
+DA850_AM18XXEVM BOARD
+M: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+S: Maintained
+F: include/configs/da850evm.h
+F: configs/da850_am18xxevm_defconfig
+F: configs/da850evm_defconfig
+F: configs/da850evm_direct_nor_defconfig
+
+HAWKBOARD BOARD
+M: Syed Mohammed Khasim <sm.khasim@gmail.com>
+M: Sughosh Ganu <urwithsughosh@gmail.com>
+S: Maintained
+F: include/configs/hawkboard.h
+F: configs/hawkboard_defconfig
+F: configs/hawkboard_uart_defconfig
diff --git a/board/davinci/da8xxevm/Makefile b/board/davinci/da8xxevm/Makefile
new file mode 100644
index 0000000..d3acacc
--- /dev/null
+++ b/board/davinci/da8xxevm/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o
+obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o
+obj-$(CONFIG_MACH_DAVINCI_HAWK) += hawkboard.o
diff --git a/board/davinci/da8xxevm/README.da850 b/board/davinci/da8xxevm/README.da850
new file mode 100644
index 0000000..313a1ef
--- /dev/null
+++ b/board/davinci/da8xxevm/README.da850
@@ -0,0 +1,68 @@
+Summary
+=======
+The README is for the boot procedure used for various DA850 (or compatible
+parts such as the AM1808) based boards.
+
+In the context of U-Boot, the board is booted in three stages. The initial
+bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits
+in the internal ROM. The RBL initializes the internal memory and then
+depending on the exact board and pin configurations will initialize another
+controller (such as SPI or NAND) to continue the boot process by loading
+the secondary program loader (SPL). The SPL will initialize the system
+further (some clocks, SDRAM) and then load the full u-boot from a
+predefined location in persistent storage to DDR and jumps to the u-boot
+entry point.
+
+AIS is an image format defined by TI for the images that are to be loaded
+to memory by the RBL. The image is divided into a series of sections and
+the image's entry point is specified. Each section comes with meta data
+like the target address the section is to be copied to and the size of the
+section, which is used by the RBL to load the image. At the end of the
+image the RBL jumps to the image entry point. The AIS format allows for
+other things such as programming the clocks and SDRAM if the header is
+programmed for it. We do not take advantage of this and instead use SPL as
+it allows for additional flexibility (run-time detect of board revision,
+loading the next image from a different media, etc).
+
+
+Compilation
+===========
+The exact build target you need will depend on the board you have. For
+Logic PD boards, or other boards which store the ethernet MAC address at
+the end of SPI flash, run 'make da850evm'. For boards which store the
+ethernet MAC address in the i2c EEPROM located at 0x50, run
+'make da850_am18xxevm'. Once this build completes you will have a
+u-boot.ais file that needs to be written to the correct persistent
+storage.
+
+
+Flashing the images to SPI
+==========================
+The AIS image can be written to SPI flash using the following commands.
+Assuming that the network is configured and enabled and the u-boot.ais file
+is tftp'able.
+
+U-Boot > sf probe 0
+U-Boot > sf erase 0 +320000
+U-Boot > tftp u-boot.ais
+U-Boot > sf write c0700000 0 $filesize
+
+
+Recovery
+========
+
+In the case of a "bricked" board, you need to use the TI tools found
+here[1] to write the u-boot.ais file. An example of recovering to the SPI
+flash of an AM1808 would be:
+
+$ mono sfh_OMAP-L138.exe -targetType AM1808 -p /dev/ttyUSB0 \
+ -flash_noubl /path/to/u-boot.ais
+
+For other target types and flash locations:
+
+$ mono sfh_OMAP-L138.exe -h
+
+Links
+=====
+[1]
+ http://processors.wiki.ti.com/index.php/Serial_Boot_and_Flash_Loading_Utility_for_OMAP-L138
diff --git a/board/davinci/da8xxevm/README.hawkboard b/board/davinci/da8xxevm/README.hawkboard
new file mode 100644
index 0000000..d6ae02e
--- /dev/null
+++ b/board/davinci/da8xxevm/README.hawkboard
@@ -0,0 +1,92 @@
+Summary
+=======
+The README is for the boot procedure used for TI's OMAP-L138 based
+hawkboard. The hawkboard comes with a 128MiB Nand flash and a 128MiB
+DDR SDRAM along with a host of other controllers.
+
+The hawkboard is booted in three stages. The initial bootloader which
+executes upon reset is the Rom Boot Loader(RBL) which sits in the
+internal ROM of the omap. The RBL initialises the memory and the nand
+controller, and copies the image stored at a predefined location(block
+1) of the nand flash. The image loaded by the RBL to the memory is the
+AIS signed spl image. This, in turns copies the u-boot binary from the
+nand flash to the memory and jumps to the u-boot entry point.
+
+AIS is an image format defined by TI for the images that are to be
+loaded to memory by the RBL. The image is divided into a series of
+sections and the image's entry point is specified. Each section comes
+with meta data like the target address the section is to be copied to
+and the size of the section, which is used by the RBL to load the
+image. At the end of the image the RBL jumps to the image entry
+point.
+
+The secondary stage bootloader(spl) which is loaded by the RBL then
+loads the u-boot from a predefined location in the nand to the memory
+and jumps to the u-boot entry point.
+
+The reason a secondary stage bootloader is used is because the ECC
+layout expected by the RBL is not the same as that used by
+u-boot/linux. This also implies that for flashing the spl image,we
+need to use the u-boot which uses the ECC layout expected by the
+RBL[1]. Booting u-boot over UART(UART boot) is explained here[2].
+
+
+Compilation
+===========
+Three images might be needed
+
+* spl - This is the secondary bootloader which boots the u-boot
+ binary.
+
+* u-boot binary - This is the image flashed to the nand and copied to
+ the memory by the spl.
+
+ Both the images get compiled with hawkboard_config, with the TOPDIR
+ containing the u-boot images, and the spl image under the spl
+ directory.
+
+ The spl image needs to be processed with the AISGen tool for
+ generating the AIS signed image to be flashed. Steps for generating
+ the AIS image are explained here[3].
+
+* u-boot for uart boot - This is same as the u-boot binary generated
+ above, with the sole difference of the CONFIG_SYS_TEXT_BASE being
+ 0xc1080000, as expected by the RBL.
+
+ hawkboard_uart_config
+
+
+Flashing the images to Nand
+===========================
+The spl AIS image needs to be flashed to the block 1 of the Nand
+flash, as that is the location the RBL expects the image[4]. For
+flashing the spl, boot over the u-boot specified in [1], and flash the
+image
+
+=> tftpboot 0xc0700000 <nand_spl_ais.bin>
+=> nand erase 0x20000 0x20000
+=> nand write.e 0xc0700000 0x20000 <nand_spl_size>
+
+The u-boot binary is flashed at location 0xe0000(block 6) of the nand
+flash. The spl loader expects the u-boot at this location. For
+flashing the u-boot binary
+
+=> tftpboot 0xc0700000 u-boot.bin
+=> nand erase 0xe0000 0x40000
+=> nand write.e 0xc0700000 0xe0000 <u-boot-size>
+
+
+Links
+=====
+
+[1]
+ http://code.google.com/p/hawkboard/downloads/detail?name=u-boot_uart_ais_v1.bin
+
+[2]
+ http://elinux.org/Hawkboard#Booting_u-boot_over_UART
+
+[3]
+ http://elinux.org/Hawkboard#Signing_u-boot_for_UART_boot
+
+[4]
+ http://processors.wiki.ti.com/index.php/RBL_UBL_and_host_program#RBL_booting_from_NAND_and_ECC.2FBad_blocks
diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c
new file mode 100644
index 0000000..c40587f
--- /dev/null
+++ b/board/davinci/da8xxevm/da830evm.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ *
+ * Base on code from TI. Original Notices follow:
+ *
+ * (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
+ *
+ * Modified for DA8xx EVM.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * SPDX-License-Identifier: GPL-2.0+
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/arch/pinmux_defs.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/davinci_misc.h>
+
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pinmux_resource pinmuxes[] = {
+#ifdef CONFIG_SPI_FLASH
+ PINMUX_ITEM(spi0_pins_base),
+ PINMUX_ITEM(spi0_pins_scs0),
+ PINMUX_ITEM(spi0_pins_ena),
+#endif
+ PINMUX_ITEM(uart2_pins_txrx),
+ PINMUX_ITEM(i2c0_pins),
+#ifdef CONFIG_USB_DA8XX
+ PINMUX_ITEM(usb_pins),
+#endif
+#ifdef CONFIG_USE_NAND
+ PINMUX_ITEM(emifa_pins),
+ PINMUX_ITEM(emifa_pins_cs0),
+ PINMUX_ITEM(emifa_pins_cs2),
+ PINMUX_ITEM(emifa_pins_cs3),
+#endif
+#if defined(CONFIG_DRIVER_TI_EMAC)
+ PINMUX_ITEM(emac_pins_rmii),
+ PINMUX_ITEM(emac_pins_mdio),
+ PINMUX_ITEM(emac_pins_rmii_clk_source),
+#endif
+#ifdef CONFIG_DAVINCI_MMC
+ PINMUX_ITEM(mmc0_pins_8bit)
+#endif
+};
+
+static const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
+ { DAVINCI_LPSC_SPI0 }, /* Serial Flash */
+ { DAVINCI_LPSC_EMAC }, /* image download */
+ { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_GPIO },
+#ifdef CONFIG_DAVINCI_MMC
+ { DAVINCI_LPSC_MMC_SD },
+#endif
+
+};
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .host_caps = MMC_MODE_8BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
+
+ printf("%x\n", mmc_sd0.input_clk);
+
+ /* Add slot-0 to mmc subsystem */
+ return davinci_mmc_init(bis, &mmc_sd0);
+}
+#endif
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+ irq_init();
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+ /* EMIFA 100MHz clock select */
+ writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2,
+ &davinci_syscfg_regs->cfgchip3);
+ /* NAND CS setup */
+ writel((DAVINCI_ABCR_WSETUP(0) |
+ DAVINCI_ABCR_WSTROBE(2) |
+ DAVINCI_ABCR_WHOLD(0) |
+ DAVINCI_ABCR_RSETUP(0) |
+ DAVINCI_ABCR_RSTROBE(2) |
+ DAVINCI_ABCR_RHOLD(0) |
+ DAVINCI_ABCR_TA(2) |
+ DAVINCI_ABCR_ASIZE_8BIT),
+ &davinci_emif_regs->ab2cr);
+#endif
+
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /*
+ * Power on required peripherals
+ * ARM does not have access by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+ return 1;
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ writel(readl(&davinci_syscfg_regs->suspsrc) &
+ ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART2),
+ &davinci_syscfg_regs->suspsrc);
+
+ /* configure pinmux settings */
+ if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
+ return 1;
+
+ /* enable the console UART */
+ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+ DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+ return(0);
+}
+
+
+#ifdef CONFIG_NAND_DAVINCI
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_DRIVER_TI_EMAC)
+
+#define PHY_SW_I2C_ADDR 0x5f /* Address of PHY on i2c bus */
+
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+ u_int8_t mac_addr[6];
+ u_int8_t switch_start_cmd[2] = { 0x01, 0x23 };
+ struct eth_device *dev;
+
+ /* Read Ethernet MAC address from EEPROM */
+ if (dvevm_read_mac_address(mac_addr))
+ /* set address env if not already set */
+ davinci_sync_env_enetaddr(mac_addr);
+
+ /* read the address back from env */
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr))
+ return -1;
+
+ /* enable the Ethernet switch in the 3 port PHY */
+ if (i2c_write(PHY_SW_I2C_ADDR, 0, 0,
+ switch_start_cmd, sizeof(switch_start_cmd))) {
+ printf("Ethernet switch start failed!\n");
+ return -1;
+ }
+
+ /* finally, initialise the driver */
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ dev = eth_get_dev();
+
+ /* provide the resulting addr to the driver */
+ memcpy(dev->enetaddr, mac_addr, 6);
+ dev->write_hwaddr(dev);
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
new file mode 100644
index 0000000..b9ca38e
--- /dev/null
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -0,0 +1,494 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/arch/pinmux_defs.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/errno.h>
+#include <hwconfig.h>
+
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define HAS_RMII 1
+#else
+#define HAS_RMII 0
+#endif
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+#define CFG_MAC_ADDR_SPI_BUS 0
+#define CFG_MAC_ADDR_SPI_CS 0
+#define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
+
+#define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
+
+#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
+static int get_mac_addr(u8 *addr)
+{
+ struct spi_flash *flash;
+ int ret;
+
+ flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS,
+ CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE);
+ if (!flash) {
+ printf("Error - unable to probe SPI flash.\n");
+ return -1;
+ }
+
+ ret = spi_flash_read(flash, CFG_MAC_ADDR_OFFSET, 6, addr);
+ if (ret) {
+ printf("Error - unable to read MAC address from SPI flash.\n");
+ return -1;
+ }
+
+ return ret;
+}
+#endif
+
+void dsp_lpsc_on(unsigned domain, unsigned int id)
+{
+ dv_reg_p mdstat, mdctl, ptstat, ptcmd;
+ struct davinci_psc_regs *psc_regs;
+
+ psc_regs = davinci_psc0_regs;
+ mdstat = &psc_regs->psc0.mdstat[id];
+ mdctl = &psc_regs->psc0.mdctl[id];
+ ptstat = &psc_regs->ptstat;
+ ptcmd = &psc_regs->ptcmd;
+
+ while (*ptstat & (0x1 << domain))
+ ;
+
+ if ((*mdstat & 0x1f) == 0x03)
+ return; /* Already on and enabled */
+
+ *mdctl |= 0x03;
+
+ *ptcmd = 0x1 << domain;
+
+ while (*ptstat & (0x1 << domain))
+ ;
+ while ((*mdstat & 0x1f) != 0x03)
+ ; /* Probably an overkill... */
+}
+
+static void dspwake(void)
+{
+ unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
+ u32 val;
+
+ /* if the device is ARM only, return */
+ if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
+ return;
+
+ if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
+ return;
+
+ *resetvect++ = 0x1E000; /* DSP Idle */
+ /* clear out the next 10 words as NOP */
+ memset(resetvect, 0, sizeof(unsigned) *10);
+
+ /* setup the DSP reset vector */
+ writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
+
+ dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
+ val = readl(PSC0_MDCTL + (15 * 4));
+ val |= 0x100;
+ writel(val, (PSC0_MDCTL + (15 * 4)));
+}
+
+int misc_init_r(void)
+{
+ dspwake();
+
+#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM)
+
+ uchar env_enetaddr[6];
+ int enetaddr_found;
+
+ enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr);
+
+#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
+ int spi_mac_read;
+ uchar buff[6];
+
+ spi_mac_read = get_mac_addr(buff);
+
+ /*
+ * MAC address not present in the environment
+ * try and read the MAC address from SPI flash
+ * and set it.
+ */
+ if (!enetaddr_found) {
+ if (!spi_mac_read) {
+ if (is_valid_ether_addr(buff)) {
+ if (eth_setenv_enetaddr("ethaddr", buff)) {
+ printf("Warning: Failed to "
+ "set MAC address from SPI flash\n");
+ }
+ } else {
+ printf("Warning: Invalid "
+ "MAC address read from SPI flash\n");
+ }
+ }
+ } else {
+ /*
+ * MAC address present in environment compare it with
+ * the MAC address in SPI flash and warn on mismatch
+ */
+ if (!spi_mac_read && is_valid_ether_addr(buff) &&
+ memcmp(env_enetaddr, buff, 6))
+ printf("Warning: MAC address in SPI flash don't match "
+ "with the MAC address in the environment\n");
+ printf("Default using MAC address from environment\n");
+ }
+#endif
+ uint8_t enetaddr[8];
+ int eeprom_mac_read;
+
+ /* Read Ethernet MAC address from EEPROM */
+ eeprom_mac_read = dvevm_read_mac_address(enetaddr);
+
+ /*
+ * MAC address not present in the environment
+ * try and read the MAC address from EEPROM flash
+ * and set it.
+ */
+ if (!enetaddr_found) {
+ if (eeprom_mac_read)
+ /* Set Ethernet MAC address from EEPROM */
+ davinci_sync_env_enetaddr(enetaddr);
+ } else {
+ /*
+ * MAC address present in environment compare it with
+ * the MAC address in EEPROM and warn on mismatch
+ */
+ if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
+ printf("Warning: MAC address in EEPROM don't match "
+ "with the MAC address in the environment\n");
+ printf("Default using MAC address from environment\n");
+ }
+
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
+
+ /* Add slot-0 to mmc subsystem */
+ return davinci_mmc_init(bis, &mmc_sd0);
+}
+#endif
+
+static const struct pinmux_config gpio_pins[] = {
+#ifdef CONFIG_USE_NOR
+ /* GP0[11] is required for NOR to work on Rev 3 EVMs */
+ { pinmux(0), 8, 4 }, /* GP0[11] */
+#endif
+#ifdef CONFIG_DAVINCI_MMC
+ /* GP0[11] is required for SD to work on Rev 3 EVMs */
+ { pinmux(0), 8, 4 }, /* GP0[11] */
+#endif
+};
+
+const struct pinmux_resource pinmuxes[] = {
+#ifdef CONFIG_DRIVER_TI_EMAC
+ PINMUX_ITEM(emac_pins_mdio),
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+ PINMUX_ITEM(emac_pins_rmii),
+#else
+ PINMUX_ITEM(emac_pins_mii),
+#endif
+#endif
+#ifdef CONFIG_SPI_FLASH
+ PINMUX_ITEM(spi1_pins_base),
+ PINMUX_ITEM(spi1_pins_scs0),
+#endif
+ PINMUX_ITEM(uart2_pins_txrx),
+ PINMUX_ITEM(uart2_pins_rtscts),
+ PINMUX_ITEM(i2c0_pins),
+#ifdef CONFIG_NAND_DAVINCI
+ PINMUX_ITEM(emifa_pins_cs3),
+ PINMUX_ITEM(emifa_pins_cs4),
+ PINMUX_ITEM(emifa_pins_nand),
+#elif defined(CONFIG_USE_NOR)
+ PINMUX_ITEM(emifa_pins_cs2),
+ PINMUX_ITEM(emifa_pins_nor),
+#endif
+ PINMUX_ITEM(gpio_pins),
+#ifdef CONFIG_DAVINCI_MMC
+ PINMUX_ITEM(mmc0_pins),
+#endif
+};
+
+const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
+
+const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
+ { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
+ { DAVINCI_LPSC_EMAC }, /* image download */
+ { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_GPIO },
+#ifdef CONFIG_DAVINCI_MMC
+ { DAVINCI_LPSC_MMC_SD },
+#endif
+};
+
+const int lpsc_size = ARRAY_SIZE(lpsc);
+
+#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
+#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
+#endif
+
+#define REV_AM18X_EVM 0x100
+
+/*
+ * get_board_rev() - setup to pass kernel board revision information
+ * Returns:
+ * bit[0-3] Maximum cpu clock rate supported by onboard SoC
+ * 0000b - 300 MHz
+ * 0001b - 372 MHz
+ * 0010b - 408 MHz
+ * 0011b - 456 MHz
+ */
+u32 get_board_rev(void)
+{
+ char *s;
+ u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
+ u32 rev = 0;
+
+ s = getenv("maxcpuclk");
+ if (s)
+ maxcpuclk = simple_strtoul(s, NULL, 10);
+
+ if (maxcpuclk >= 456000000)
+ rev = 3;
+ else if (maxcpuclk >= 408000000)
+ rev = 2;
+ else if (maxcpuclk >= 372000000)
+ rev = 1;
+#ifdef CONFIG_DA850_AM18X_EVM
+ rev |= REV_AM18X_EVM;
+#endif
+ return rev;
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * Power on required peripherals
+ * ARM does not have access by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+ return 1;
+
+ return 0;
+}
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+ irq_init();
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+ /*
+ * NAND CS setup - cycle counts based on da850evm NAND timings in the
+ * Linux kernel @ 25MHz EMIFA
+ */
+ writel((DAVINCI_ABCR_WSETUP(2) |
+ DAVINCI_ABCR_WSTROBE(2) |
+ DAVINCI_ABCR_WHOLD(1) |
+ DAVINCI_ABCR_RSETUP(1) |
+ DAVINCI_ABCR_RSTROBE(4) |
+ DAVINCI_ABCR_RHOLD(0) |
+ DAVINCI_ABCR_TA(1) |
+ DAVINCI_ABCR_ASIZE_8BIT),
+ &davinci_emif_regs->ab2cr); /* CS3 */
+#endif
+
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ writel(readl(&davinci_syscfg_regs->suspsrc) &
+ ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART2),
+ &davinci_syscfg_regs->suspsrc);
+
+ /* configure pinmux settings */
+ if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
+ return 1;
+
+#ifdef CONFIG_USE_NOR
+ /* Set the GPIO direction as output */
+ clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
+
+ /* Set the output as low */
+ writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
+#endif
+
+#ifdef CONFIG_DAVINCI_MMC
+ /* Set the GPIO direction as output */
+ clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
+
+ /* Set the output as high */
+ writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+ davinci_emac_mii_mode_sel(HAS_RMII);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+ /* enable the console UART */
+ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+ DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+/**
+ * rmii_hw_init
+ *
+ * DA850/OMAP-L138 EVM can interface to a daughter card for
+ * additional features. This card has an I2C GPIO Expander TCA6416
+ * to select the required functions like camera, RMII Ethernet,
+ * character LCD, video.
+ *
+ * Initialization of the expander involves configuring the
+ * polarity and direction of the ports. P07-P05 are used here.
+ * These ports are connected to a Mux chip which enables only one
+ * functionality at a time.
+ *
+ * For RMII phy to respond, the MII MDIO clock has to be disabled
+ * since both the PHY devices have address as zero. The MII MDIO
+ * clock is controlled via GPIO2[6].
+ *
+ * This code is valid for Beta version of the hardware
+ */
+int rmii_hw_init(void)
+{
+ const struct pinmux_config gpio_pins[] = {
+ { pinmux(6), 8, 1 }
+ };
+ u_int8_t buf[2];
+ unsigned int temp;
+ int ret;
+
+ /* PinMux for GPIO */
+ if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
+ return 1;
+
+ /* I2C Exapnder configuration */
+ /* Set polarity to non-inverted */
+ buf[0] = 0x0;
+ buf[1] = 0x0;
+ ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
+ if (ret) {
+ printf("\nExpander @ 0x%02x write FAILED!!!\n",
+ CONFIG_SYS_I2C_EXPANDER_ADDR);
+ return ret;
+ }
+
+ /* Configure P07-P05 as outputs */
+ buf[0] = 0x1f;
+ buf[1] = 0xff;
+ ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
+ if (ret) {
+ printf("\nExpander @ 0x%02x write FAILED!!!\n",
+ CONFIG_SYS_I2C_EXPANDER_ADDR);
+ }
+
+ /* For Ethernet RMII selection
+ * P07(SelA)=0
+ * P06(SelB)=1
+ * P05(SelC)=1
+ */
+ if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+ printf("\nExpander @ 0x%02x read FAILED!!!\n",
+ CONFIG_SYS_I2C_EXPANDER_ADDR);
+ }
+
+ buf[0] &= 0x1f;
+ buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
+ if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
+ printf("\nExpander @ 0x%02x write FAILED!!!\n",
+ CONFIG_SYS_I2C_EXPANDER_ADDR);
+ }
+
+ /* Set the output as high */
+ temp = REG(GPIO_BANK2_REG_SET_ADDR);
+ temp |= (0x01 << 6);
+ REG(GPIO_BANK2_REG_SET_ADDR) = temp;
+
+ /* Set the GPIO direction as output */
+ temp = REG(GPIO_BANK2_REG_DIR_ADDR);
+ temp &= ~(0x01 << 6);
+ REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
+
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
+ /* Select RMII fucntion through the expander */
+ if (rmii_hw_init())
+ printf("RMII hardware init failed!!!\n");
+#endif
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
diff --git a/board/davinci/da8xxevm/hawkboard-ais-nand.cfg b/board/davinci/da8xxevm/hawkboard-ais-nand.cfg
new file mode 100644
index 0000000..2b12b6c
--- /dev/null
+++ b/board/davinci/da8xxevm/hawkboard-ais-nand.cfg
@@ -0,0 +1,4 @@
+# PLL0CFG0 PLL0CFG1
+PLL0 0x00180001 0x00000205
+# PLL1CFG0 PLL1CFG1 DRPYC1R SDCR SDTIMR1 SDTIMR2 SDRCR CLK2XSRC
+DDR2 0x15010001 0x00000002 0x00000043 0x00134632 0x26492a09 0x7d13c722 0x00000249 0x00000000
diff --git a/board/davinci/da8xxevm/hawkboard.c b/board/davinci/da8xxevm/hawkboard.c
new file mode 100644
index 0000000..d5992a5
--- /dev/null
+++ b/board/davinci/da8xxevm/hawkboard.c
@@ -0,0 +1,120 @@
+/*
+ * Modified for Hawkboard - Syed Mohammed Khasim <khasim@beagleboard.org>
+ *
+ * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2004 Texas Instruments.
+ * Copyright (C) 2012 Sughosh Ganu <urwithsughosh@gmail.com>.
+ *
+ * ----------------------------------------------------------------------------
+ * SPDX-License-Identifier: GPL-2.0+
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/pinmux_defs.h>
+#include <asm/arch/da8xx-usb.h>
+#include <ns16550.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct pinmux_resource pinmuxes[] = {
+ PINMUX_ITEM(emac_pins_mii),
+ PINMUX_ITEM(emac_pins_mdio),
+ PINMUX_ITEM(emifa_pins_cs3),
+ PINMUX_ITEM(emifa_pins_cs4),
+ PINMUX_ITEM(emifa_pins_nand),
+ PINMUX_ITEM(uart2_pins_txrx),
+ PINMUX_ITEM(uart2_pins_rtscts),
+};
+
+const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
+
+const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
+ { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
+ { DAVINCI_LPSC_EMAC }, /* image download */
+ { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_GPIO },
+};
+
+const int lpsc_size = ARRAY_SIZE(lpsc);
+
+int board_init(void)
+{
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_HAWKBOARD;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * Kick Registers need to be set to allow access to Pin Mux registers
+ */
+ writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
+ writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
+
+ /* set cfgchip3 to select mii */
+ writel(readl(&davinci_syscfg_regs->cfgchip3) &
+ ~(1 << 8), &davinci_syscfg_regs->cfgchip3);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ char buf[32];
+
+ printf("ARM Clock : %s MHz\n",
+ strmhz(buf, clk_get(DAVINCI_ARM_CLKID)));
+
+ return 0;
+}
+
+int usb_phy_on(void)
+{
+ u32 timeout;
+ u32 cfgchip2;
+
+ cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
+
+ cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN |
+ CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ |
+ CFGCHIP2_USB1PHYCLKMUX);
+ cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON |
+ CFGCHIP2_REFFREQ_24MHZ | CFGCHIP2_USB2PHYCLKMUX |
+ CFGCHIP2_USB1SUSPENDM;
+
+ writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
+
+ /* wait until the usb phy pll locks */
+ timeout = DA8XX_USB_OTG_TIMEOUT;
+ while (timeout--)
+ if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD)
+ return 1;
+
+ /* USB phy was not turned on */
+ return 0;
+}
+
+void usb_phy_off(void)
+{
+ u32 cfgchip2;
+
+ /*
+ * Power down the on-chip PHY.
+ */
+ cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2);
+ cfgchip2 &= ~(CFGCHIP2_PHY_PLLON | CFGCHIP2_USB1SUSPENDM);
+ cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | CFGCHIP2_RESET;
+ writel(cfgchip2, &davinci_syscfg_regs->cfgchip2);
+}
diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
new file mode 100644
index 0000000..ab4f50c
--- /dev/null
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ __start = .;
+ *(.vectors)
+ arch/arm/cpu/arm926ejs/start.o (.text*)
+ *(.text*)
+ } >.sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ . = ALIGN(4);
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ } >.sram
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } >.sram
+
+ __image_copy_end = .;
+
+ .end :
+ {
+ *(.__end)
+ }
+}
diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
new file mode 100644
index 0000000..5c629db
--- /dev/null
+++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0xc1080000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.vectors)
+ arch/arm/cpu/arm926ejs/start.o (.text*)
+ arch/arm/cpu/arm926ejs/built-in.o (.text*)
+ drivers/mtd/nand/built-in.o (.text*)
+
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata*) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data)
+ __datarel_start = .;
+ *(.data.rel)
+ __datarelrolocal_start = .;
+ *(.data.rel.ro.local)
+ __datarellocal_start = .;
+ *(.data.rel.local)
+ __datarelro_start = .;
+ *(.data.rel.ro)
+ }
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+ __rel_dyn_start = .;
+ __rel_dyn_end = .;
+
+ __got_start = .;
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __got_end = .;
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ }
+
+ .end :
+ {
+ *(.__end)
+ }
+}
diff --git a/board/davinci/dm355evm/Kconfig b/board/davinci/dm355evm/Kconfig
new file mode 100644
index 0000000..ec2c276
--- /dev/null
+++ b/board/davinci/dm355evm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DAVINCI_DM355EVM
+
+config SYS_BOARD
+ default "dm355evm"
+
+config SYS_VENDOR
+ default "davinci"
+
+config SYS_CONFIG_NAME
+ default "davinci_dm355evm"
+
+endif
diff --git a/board/davinci/dm355evm/MAINTAINERS b/board/davinci/dm355evm/MAINTAINERS
new file mode 100644
index 0000000..c017e09
--- /dev/null
+++ b/board/davinci/dm355evm/MAINTAINERS
@@ -0,0 +1,6 @@
+DM355EVM BOARD
+#M: Sandeep Paulraj <s-paulraj@ti.com>
+S: Orphan (since 2014-08)
+F: board/davinci/dm355evm/
+F: include/configs/davinci_dm355evm.h
+F: configs/davinci_dm355evm_defconfig
diff --git a/board/davinci/dm355evm/Makefile b/board/davinci/dm355evm/Makefile
new file mode 100644
index 0000000..bcb7e6f
--- /dev/null
+++ b/board/davinci/dm355evm/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dm355evm.o
diff --git a/board/davinci/dm355evm/config.mk b/board/davinci/dm355evm/config.mk
new file mode 100644
index 0000000..9a06300
--- /dev/null
+++ b/board/davinci/dm355evm/config.mk
@@ -0,0 +1,11 @@
+#
+# Spectrum Digital DM355 EVM board
+# dm355evm board has 1 bank of 128 MB DDR RAM
+# Physical Address: 8000'0000 to 8800'0000
+#
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c
new file mode 100644
index 0000000..e5a958f
--- /dev/null
+++ b/board/davinci/dm355evm/dm355evm.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2009 David Brownell
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/davinci_misc.h>
+#include <net.h>
+#include <netdev.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * With the DM355 EVM, u-boot is *always* a third stage loader,
+ * unless a JTAG debugger handles the first two stages:
+ *
+ * - 1st stage is ROM Boot Loader (RBL), which searches for a
+ * second stage loader in one of three places based on SW7:
+ * NAND (with MMC/SD fallback), MMC/SD, or UART.
+ *
+ * - 2nd stage is User Boot Loader (UBL), using at most 30KB
+ * of on-chip SRAM, responsible for lowlevel init, and for
+ * loading the third stage loader into DRAM.
+ *
+ * - 3rd stage, that's us!
+ */
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ /* We expect the UBL to have handled "lowlevel init", which
+ * involves setting up at least:
+ * - clocks
+ * + PLL1 (for ARM and peripherals) and PLL2 (for DDR)
+ * + clock divisors for those PLLs
+ * + LPSC_DDR module enabled
+ * + LPSC_TIMER0 module (still) enabled
+ * - EMIF
+ * + DDR init and timings
+ * + AEMIF timings (for NAND and DM9000)
+ * - pinmux
+ *
+ * Some of that is repeated here, mostly as a precaution.
+ */
+
+ /* AEMIF: Some "address" lines are available as GPIOs. A3..A13
+ * could be too if we used A12 as a GPIO during NAND chipselect
+ * (and Linux did too), letting us control the LED on A7/GPIO61.
+ */
+ REG(PINMUX2) = 0x0c08;
+
+ /* UART0 may still be in SyncReset if we didn't boot from UART */
+ davinci_enable_uart0();
+
+ /* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */
+ lpsc_on(DAVINCI_LPSC_TPCC);
+ lpsc_on(DAVINCI_LPSC_TPTC0);
+ lpsc_on(DAVINCI_LPSC_TPTC1);
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+
+static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *this = mtd->priv;
+ unsigned long wbase = (unsigned long) this->IO_ADDR_W;
+ unsigned long rbase = (unsigned long) this->IO_ADDR_R;
+
+ if (chip == 1) {
+ __set_bit(14, &wbase);
+ __set_bit(14, &rbase);
+ } else {
+ __clear_bit(14, &wbase);
+ __clear_bit(14, &rbase);
+ }
+ this->IO_ADDR_W = (void *)wbase;
+ this->IO_ADDR_R = (void *)rbase;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+ nand->select_chip = nand_dm355evm_select_chip;
+ return 0;
+}
+
+#endif
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .input_clk = 108000000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_1,
+};
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+static struct davinci_mmc mmc_sd1 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
+ .input_clk = 108000000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_1,
+};
+#endif
+
+int board_mmc_init(bd_t *bis)
+{
+ int err;
+
+ /* Add slot-0 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd0);
+ if (err)
+ return err;
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+ /* Add slot-1 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd1);
+#endif
+
+ return err;
+}
+#endif
diff --git a/board/davinci/dm355leopard/Kconfig b/board/davinci/dm355leopard/Kconfig
new file mode 100644
index 0000000..ab4230a
--- /dev/null
+++ b/board/davinci/dm355leopard/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DAVINCI_DM355LEOPARD
+
+config SYS_BOARD
+ default "dm355leopard"
+
+config SYS_VENDOR
+ default "davinci"
+
+config SYS_CONFIG_NAME
+ default "davinci_dm355leopard"
+
+endif
diff --git a/board/davinci/dm355leopard/MAINTAINERS b/board/davinci/dm355leopard/MAINTAINERS
new file mode 100644
index 0000000..ed04d43
--- /dev/null
+++ b/board/davinci/dm355leopard/MAINTAINERS
@@ -0,0 +1,6 @@
+DM355LEOPARD BOARD
+#M: Sandeep Paulraj <s-paulraj@ti.com>
+S: Orphan (since 2014-08)
+F: board/davinci/dm355leopard/
+F: include/configs/davinci_dm355leopard.h
+F: configs/davinci_dm355leopard_defconfig
diff --git a/board/davinci/dm355leopard/Makefile b/board/davinci/dm355leopard/Makefile
new file mode 100644
index 0000000..7035429
--- /dev/null
+++ b/board/davinci/dm355leopard/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dm355leopard.o
diff --git a/board/davinci/dm355leopard/config.mk b/board/davinci/dm355leopard/config.mk
new file mode 100644
index 0000000..28ff3f3
--- /dev/null
+++ b/board/davinci/dm355leopard/config.mk
@@ -0,0 +1,6 @@
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c
new file mode 100644
index 0000000..53902f9
--- /dev/null
+++ b/board/davinci/dm355leopard/dm355leopard.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/davinci_misc.h>
+#include <net.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ struct davinci_gpio *gpio01_base =
+ (struct davinci_gpio *)DAVINCI_GPIO_BANK01;
+ struct davinci_gpio *gpio23_base =
+ (struct davinci_gpio *)DAVINCI_GPIO_BANK23;
+ struct davinci_gpio *gpio67_base =
+ (struct davinci_gpio *)DAVINCI_GPIO_BANK67;
+
+ gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ /* GIO 9 & 10 are used for IO */
+ writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3);
+
+ /* Interrupt set GIO 9 */
+ writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN);
+
+ /* set GIO 9 input */
+ writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir);
+
+ /* Both edge trigger GIO 9 */
+ writel((readl(&gpio01_base->set_rising) | (1 << 9)),
+ &gpio01_base->set_rising);
+ writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir);
+
+ /* output low */
+ writel((readl(&gpio01_base->set_data) & ~(1 << 5)),
+ &gpio01_base->set_data);
+
+ /* set GIO 10 output */
+ writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir);
+
+ /* output high */
+ writel((readl(&gpio01_base->set_data) | (1 << 10)),
+ &gpio01_base->set_data);
+
+ /* set GIO 32 output */
+ writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir);
+
+ /* output High */
+ writel((readl(&gpio23_base->set_data) | (1 << 0)),
+ &gpio23_base->set_data);
+
+ /* Enable UART1 MUX Lines */
+ writel((readl(PINMUX0) & ~3), PINMUX0);
+ writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir);
+ writel((readl(&gpio67_base->set_data) | (1 << 6)),
+ &gpio67_base->set_data);
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+
+ return 0;
+}
+#endif
diff --git a/board/davinci/dm365evm/Kconfig b/board/davinci/dm365evm/Kconfig
new file mode 100644
index 0000000..724c7b6
--- /dev/null
+++ b/board/davinci/dm365evm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DAVINCI_DM365EVM
+
+config SYS_BOARD
+ default "dm365evm"
+
+config SYS_VENDOR
+ default "davinci"
+
+config SYS_CONFIG_NAME
+ default "davinci_dm365evm"
+
+endif
diff --git a/board/davinci/dm365evm/MAINTAINERS b/board/davinci/dm365evm/MAINTAINERS
new file mode 100644
index 0000000..97c3ed3
--- /dev/null
+++ b/board/davinci/dm365evm/MAINTAINERS
@@ -0,0 +1,6 @@
+DM365EVM BOARD
+#M: Sandeep Paulraj <s-paulraj@ti.com>
+S: Orphan (since 2014-08)
+F: board/davinci/dm365evm/
+F: include/configs/davinci_dm365evm.h
+F: configs/davinci_dm365evm_defconfig
diff --git a/board/davinci/dm365evm/Makefile b/board/davinci/dm365evm/Makefile
new file mode 100644
index 0000000..d35d81c
--- /dev/null
+++ b/board/davinci/dm365evm/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dm365evm.o
diff --git a/board/davinci/dm365evm/config.mk b/board/davinci/dm365evm/config.mk
new file mode 100644
index 0000000..7b1e900
--- /dev/null
+++ b/board/davinci/dm365evm/config.mk
@@ -0,0 +1,11 @@
+#
+# Spectrum Digital DM365 EVM board
+# DM365 EVM board has 1 bank of 128 MB DDR RAM
+# Physical Address: 8000'0000 to 8800'0000
+#
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c
new file mode 100644
index 0000000..24bec56
--- /dev/null
+++ b/board/davinci/dm365evm/dm365evm.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/gpio.h>
+#include <netdev.h>
+#include <asm/arch/davinci_misc.h>
+#ifdef CONFIG_DAVINCI_MMC
+#include <mmc.h>
+#include <asm/arch/sdmmc_defs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM365_EVM;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+int board_eth_init(bd_t *bis)
+{
+ uint8_t eeprom_enetaddr[6];
+ int i;
+ struct davinci_gpio *gpio1_base =
+ (struct davinci_gpio *)DAVINCI_GPIO_BANK01;
+
+ /* Configure PINMUX 3 to enable EMAC pins */
+ writel((readl(PINMUX3) | 0x1affff), PINMUX3);
+
+ /* Configure GPIO20 as output */
+ writel((readl(&gpio1_base->dir) & ~(1 << 20)), &gpio1_base->dir);
+
+ /* Toggle GPIO 20 */
+ for (i = 0; i < 20; i++) {
+ /* GPIO 20 low */
+ writel((readl(&gpio1_base->out_data) & ~(1 << 20)),
+ &gpio1_base->out_data);
+
+ udelay(1000);
+
+ /* GPIO 20 high */
+ writel((readl(&gpio1_base->out_data) | (1 << 20)),
+ &gpio1_base->out_data);
+ }
+
+ /* Configure I2C pins so that EEPROM can be read */
+ writel((readl(PINMUX3) | 0x01400000), PINMUX3);
+
+ /* Read Ethernet MAC address from EEPROM */
+ if (dvevm_read_mac_address(eeprom_enetaddr))
+ davinci_sync_env_enetaddr(eeprom_enetaddr);
+
+ davinci_emac_initialize();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *this = mtd->priv;
+ unsigned long wbase = (unsigned long) this->IO_ADDR_W;
+ unsigned long rbase = (unsigned long) this->IO_ADDR_R;
+
+ if (chip == 1) {
+ __set_bit(14, &wbase);
+ __set_bit(14, &rbase);
+ } else {
+ __clear_bit(14, &wbase);
+ __clear_bit(14, &rbase);
+ }
+ this->IO_ADDR_W = (void *)wbase;
+ this->IO_ADDR_R = (void *)rbase;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+ nand->select_chip = nand_dm365evm_select_chip;
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd0 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
+ .input_clk = 121500000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+static struct davinci_mmc mmc_sd1 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
+ .input_clk = 121500000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+#endif
+
+int board_mmc_init(bd_t *bis)
+{
+ int err;
+
+ /* Add slot-0 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd0);
+ if (err)
+ return err;
+
+#ifdef CONFIG_DAVINCI_MMC_SD1
+#define PUPDCTL1 0x01c4007c
+ /* PINMUX(4)-DAT0-3/CMD; PINMUX(0)-CLK */
+ writel((readl(PINMUX4) | 0x55400000), PINMUX4);
+ writel((readl(PINMUX0) | 0x00010000), PINMUX0);
+
+ /* Configure MMC/SD pins as pullup */
+ writel((readl(PUPDCTL1) & ~0x07c0), PUPDCTL1);
+
+ /* Add slot-1 to mmc subsystem */
+ err = davinci_mmc_init(bis, &mmc_sd1);
+#endif
+
+ return err;
+}
+#endif
diff --git a/board/davinci/dm6467evm/Kconfig b/board/davinci/dm6467evm/Kconfig
new file mode 100644
index 0000000..56d2ab4
--- /dev/null
+++ b/board/davinci/dm6467evm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DAVINCI_DM6467EVM
+
+config SYS_BOARD
+ default "dm6467evm"
+
+config SYS_VENDOR
+ default "davinci"
+
+config SYS_CONFIG_NAME
+ default "davinci_dm6467evm"
+
+endif
diff --git a/board/davinci/dm6467evm/MAINTAINERS b/board/davinci/dm6467evm/MAINTAINERS
new file mode 100644
index 0000000..8ca53c4
--- /dev/null
+++ b/board/davinci/dm6467evm/MAINTAINERS
@@ -0,0 +1,7 @@
+DM6467EVM BOARD
+#M: Sandeep Paulraj <s-paulraj@ti.com>
+S: Orphan (since 2014-08)
+F: board/davinci/dm6467evm/
+F: include/configs/davinci_dm6467evm.h
+F: configs/davinci_dm6467evm_defconfig
+F: configs/davinci_dm6467Tevm_defconfig
diff --git a/board/davinci/dm6467evm/Makefile b/board/davinci/dm6467evm/Makefile
new file mode 100644
index 0000000..acbbdd5
--- /dev/null
+++ b/board/davinci/dm6467evm/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dm6467evm.o
diff --git a/board/davinci/dm6467evm/config.mk b/board/davinci/dm6467evm/config.mk
new file mode 100644
index 0000000..3751043
--- /dev/null
+++ b/board/davinci/dm6467evm/config.mk
@@ -0,0 +1,2 @@
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c
new file mode 100644
index 0000000..e51cc9e
--- /dev/null
+++ b/board/davinci/dm6467evm/dm6467evm.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/davinci_nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define REV_DM6467EVM 0
+#define REV_DM6467TEVM 1
+/*
+ * get_board_rev() - setup to pass kernel board revision information
+ * Returns:
+ * bit[0-3] System clock frequency
+ * 0000b - 27 MHz
+ * 0001b - 33 MHz
+ */
+u32 get_board_rev(void)
+{
+
+#ifdef CONFIG_DAVINCI_DM6467TEVM
+ return REV_DM6467TEVM;
+#else
+ return REV_DM6467EVM;
+#endif
+
+}
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ lpsc_on(DAVINCI_DM646X_LPSC_TIMER0);
+ lpsc_on(DAVINCI_DM646X_LPSC_UART0);
+ lpsc_on(DAVINCI_DM646X_LPSC_I2C);
+ lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
+
+ /* Enable GIO3.3V cells used for EMAC */
+ REG(VDD3P3V_PWDN) = 0x80000c0;
+
+ /* Select UART function on UART0 */
+ REG(PINMUX0) &= ~(0x0000003f << 18);
+ REG(PINMUX1) &= ~(0x00000003);
+
+ return 0;
+}
+
+#if defined(CONFIG_DRIVER_TI_EMAC)
+
+int board_eth_init(bd_t *bis)
+{
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+#ifdef CONFIG_NAND_DAVINCI
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+
+ return 0;
+}
+#endif
diff --git a/board/davinci/dvevm/Kconfig b/board/davinci/dvevm/Kconfig
new file mode 100644
index 0000000..3f0ef82
--- /dev/null
+++ b/board/davinci/dvevm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DAVINCI_DVEVM
+
+config SYS_BOARD
+ default "dvevm"
+
+config SYS_VENDOR
+ default "davinci"
+
+config SYS_CONFIG_NAME
+ default "davinci_dvevm"
+
+endif
diff --git a/board/davinci/dvevm/MAINTAINERS b/board/davinci/dvevm/MAINTAINERS
new file mode 100644
index 0000000..a718b90
--- /dev/null
+++ b/board/davinci/dvevm/MAINTAINERS
@@ -0,0 +1,6 @@
+DVEVM BOARD
+#M: -
+S: Maintained
+F: board/davinci/dvevm/
+F: include/configs/davinci_dvevm.h
+F: configs/davinci_dvevm_defconfig
diff --git a/board/davinci/dvevm/Makefile b/board/davinci/dvevm/Makefile
new file mode 100644
index 0000000..7ade325
--- /dev/null
+++ b/board/davinci/dvevm/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dvevm.o
+obj-y += board_init.o
diff --git a/board/davinci/dvevm/board_init.S b/board/davinci/dvevm/board_init.S
new file mode 100644
index 0000000..ded0590
--- /dev/null
+++ b/board/davinci/dvevm/board_init.S
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Board-specific low level initialization code. Called at the very end
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * initialization required.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+.globl dv_board_init
+dv_board_init:
+
+ mov pc, lr
diff --git a/board/davinci/dvevm/config.mk b/board/davinci/dvevm/config.mk
new file mode 100644
index 0000000..ed80707
--- /dev/null
+++ b/board/davinci/dvevm/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Swaminathan <swami.iyer@ti.com>
+#
+# Davinci EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Davinci EVM has 1 bank of 256 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 9000'0000
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# Visioneering Corp. Sonata board (ARM926EJS) cpu
+#
+# Sonata board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
+#
+# Schmoogie board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# we load ourself to 8108 '0000
+#
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c
new file mode 100644
index 0000000..c34bde4
--- /dev/null
+++ b/board/davinci/dvevm/dvevm.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * SPDX-License-Identifier: GPL-2.0+
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* Configure AEMIF pins (although this should be configured at boot time
+ * with pull-up/pull-down resistors) */
+ REG(PINMUX0) = 0x00000c1f;
+
+ davinci_errata_workarounds();
+
+ /* Power on required peripherals */
+ lpsc_on(DAVINCI_LPSC_GPIO);
+ lpsc_on(DAVINCI_LPSC_USB);
+
+#if !defined(CONFIG_SYS_USE_DSPLINK)
+ /* Powerup the DSP */
+ dsp_on();
+#endif /* CONFIG_SYS_USE_DSPLINK */
+
+ davinci_enable_uart0();
+ davinci_enable_emac();
+ davinci_enable_i2c();
+
+ lpsc_on(DAVINCI_LPSC_TIMER1);
+ timer_init();
+
+ return(0);
+}
+
+int misc_init_r(void)
+{
+ uint8_t video_mode;
+ uint8_t eeprom_enetaddr[6];
+
+ /* Read Ethernet MAC address from EEPROM if available. */
+ if (dvevm_read_mac_address(eeprom_enetaddr))
+ davinci_sync_env_enetaddr(eeprom_enetaddr);
+
+ i2c_read(0x39, 0x00, 1, &video_mode, 1);
+
+ setenv("videostd", ((video_mode & 0x80) ? "pal" : "ntsc"));
+
+ return(0);
+}
+
+#ifdef CONFIG_USB_DAVINCI
+
+/* IO Expander I2C address and USB VBUS enable mask */
+#define IOEXP_I2C_ADDR 0x3A
+#define IOEXP_VBUSEN_MASK 1
+
+/*
+ * This function enables USB VBUS by writting to IO expander using I2C.
+ * Note that the I2C is already initialized at this stage. This
+ * function is used by davinci specific USB wrapper code.
+ */
+void enable_vbus(void)
+{
+ uchar data; /* IO Expander data to enable VBUS */
+
+ /* Write to IO expander to enable VBUS */
+ i2c_read(IOEXP_I2C_ADDR, 0, 0, &data, 1);
+ data &= ~IOEXP_VBUSEN_MASK;
+ i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1);
+}
+#endif
diff --git a/board/davinci/ea20/Kconfig b/board/davinci/ea20/Kconfig
new file mode 100644
index 0000000..ae5b16e
--- /dev/null
+++ b/board/davinci/ea20/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_EA20
+
+config SYS_BOARD
+ default "ea20"
+
+config SYS_VENDOR
+ default "davinci"
+
+config SYS_CONFIG_NAME
+ default "ea20"
+
+endif
diff --git a/board/davinci/ea20/MAINTAINERS b/board/davinci/ea20/MAINTAINERS
new file mode 100644
index 0000000..5c300a3
--- /dev/null
+++ b/board/davinci/ea20/MAINTAINERS
@@ -0,0 +1,6 @@
+EA20 BOARD
+M: Stefano Babic <sbabic@denx.de>
+S: Maintained
+F: board/davinci/ea20/
+F: include/configs/ea20.h
+F: configs/ea20_defconfig
diff --git a/board/davinci/ea20/Makefile b/board/davinci/ea20/Makefile
new file mode 100644
index 0000000..a5311c4
--- /dev/null
+++ b/board/davinci/ea20/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ea20.o
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
new file mode 100644
index 0000000..66804d7
--- /dev/null
+++ b/board/davinci/ea20/ea20.c
@@ -0,0 +1,339 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Based on da850evm.c, original Copyrights follow:
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/io.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/gpio.h>
+#include "../../../drivers/video/da8xx-fb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct da8xx_panel lcd_panel = {
+ /* Casio COM57H531x */
+ .name = "Casio_COM57H531x",
+ .width = 640,
+ .height = 480,
+ .hfp = 12,
+ .hbp = 144,
+ .hsw = 30,
+ .vfp = 10,
+ .vbp = 35,
+ .vsw = 3,
+ .pxl_clk = 25000000,
+ .invert_pxl_clk = 0,
+};
+
+static const struct display_panel disp_panel = {
+ QVGA,
+ 16,
+ 16,
+ COLOR_ACTIVE,
+};
+
+static const struct lcd_ctrl_config lcd_cfg = {
+ &disp_panel,
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 16,
+ .fdd = 255,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+};
+
+/* SPI0 pin muxer settings */
+static const struct pinmux_config spi1_pins[] = {
+ { pinmux(5), 1, 1 },
+ { pinmux(5), 1, 2 },
+ { pinmux(5), 1, 4 },
+ { pinmux(5), 1, 5 }
+};
+
+/* I2C pin muxer settings */
+static const struct pinmux_config i2c_pins[] = {
+ { pinmux(4), 2, 2 },
+ { pinmux(4), 2, 3 }
+};
+
+/* UART0 pin muxer settings */
+static const struct pinmux_config uart_pins[] = {
+ { pinmux(3), 2, 7 },
+ { pinmux(3), 2, 6 },
+ { pinmux(3), 2, 4 },
+ { pinmux(3), 2, 5 }
+};
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define HAS_RMII 1
+static const struct pinmux_config emac_pins[] = {
+ { pinmux(14), 8, 2 },
+ { pinmux(14), 8, 3 },
+ { pinmux(14), 8, 4 },
+ { pinmux(14), 8, 5 },
+ { pinmux(14), 8, 6 },
+ { pinmux(14), 8, 7 },
+ { pinmux(15), 8, 1 },
+ { pinmux(4), 8, 0 },
+ { pinmux(4), 8, 1 }
+};
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+const struct pinmux_config nand_pins[] = {
+ { pinmux(7), 1, 0}, /* CS2 */
+ { pinmux(7), 0, 1}, /* CS3 in three state*/
+ { pinmux(7), 1, 4 }, /* EMA_WE */
+ { pinmux(7), 1, 5 }, /* EMA_OE */
+ { pinmux(9), 1, 0 }, /* EMA_D[7] */
+ { pinmux(9), 1, 1 }, /* EMA_D[6] */
+ { pinmux(9), 1, 2 }, /* EMA_D[5] */
+ { pinmux(9), 1, 3 }, /* EMA_D[4] */
+ { pinmux(9), 1, 4 }, /* EMA_D[3] */
+ { pinmux(9), 1, 5 }, /* EMA_D[2] */
+ { pinmux(9), 1, 6 }, /* EMA_D[1] */
+ { pinmux(9), 1, 7 }, /* EMA_D[0] */
+ { pinmux(12), 1, 5 }, /* EMA_A[2] */
+ { pinmux(12), 1, 6 }, /* EMA_A[1] */
+ { pinmux(6), 1, 0 } /* EMA_CLK */
+};
+#endif
+
+const struct pinmux_config gpio_pins[] = {
+ { pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/
+ { pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/
+ { pinmux(13), 8, 3 }, /* GPIO6[12] U0_SW1 on EA20-00101_2*/
+ { pinmux(19), 8, 5 }, /* GPIO6[1] DISP_ON */
+ { pinmux(14), 8, 1 } /* GPIO6[6] LCD_B_PWR*/
+};
+
+const struct pinmux_config lcd_pins[] = {
+ { pinmux(17), 2, 1 }, /* LCD_D_0 */
+ { pinmux(17), 2, 0 }, /* LCD_D_1 */
+ { pinmux(16), 2, 7 }, /* LCD_D_2 */
+ { pinmux(16), 2, 6 }, /* LCD_D_3 */
+ { pinmux(16), 2, 5 }, /* LCD_D_4 */
+ { pinmux(16), 2, 4 }, /* LCD_D_5 */
+ { pinmux(16), 2, 3 }, /* LCD_D_6 */
+ { pinmux(16), 2, 2 }, /* LCD_D_7 */
+ { pinmux(18), 2, 1 }, /* LCD_D_8 */
+ { pinmux(18), 2, 0 }, /* LCD_D_9 */
+ { pinmux(17), 2, 7 }, /* LCD_D_10 */
+ { pinmux(17), 2, 6 }, /* LCD_D_11 */
+ { pinmux(17), 2, 5 }, /* LCD_D_12 */
+ { pinmux(17), 2, 4 }, /* LCD_D_13 */
+ { pinmux(17), 2, 3 }, /* LCD_D_14 */
+ { pinmux(17), 2, 2 }, /* LCD_D_15 */
+ { pinmux(18), 2, 6 }, /* LCD_PCLK */
+ { pinmux(19), 2, 0 }, /* LCD_HSYNC */
+ { pinmux(19), 2, 1 }, /* LCD_VSYNC */
+ { pinmux(19), 2, 6 }, /* DA850_NLCD_AC_ENB_CS */
+};
+
+const struct pinmux_config halten_pin[] = {
+ { pinmux(3), 4, 2 } /* GPIO8[6] HALTEN */
+};
+
+static const struct pinmux_resource pinmuxes[] = {
+#ifdef CONFIG_SPI_FLASH
+ PINMUX_ITEM(spi1_pins),
+#endif
+ PINMUX_ITEM(uart_pins),
+ PINMUX_ITEM(i2c_pins),
+#ifdef CONFIG_NAND_DAVINCI
+ PINMUX_ITEM(nand_pins),
+#endif
+#ifdef CONFIG_VIDEO
+ PINMUX_ITEM(lcd_pins),
+#endif
+};
+
+static const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
+ { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
+ { DAVINCI_LPSC_EMAC }, /* image download */
+ { DAVINCI_LPSC_UART0 }, /* console */
+ { DAVINCI_LPSC_GPIO },
+ { DAVINCI_LPSC_LCDC }, /* LCD */
+};
+
+int board_early_init_f(void)
+{
+ /* PinMux for GPIO */
+ if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
+ return 1;
+
+ /* Set DISP_ON high to enable LCD output*/
+ gpio_direction_output(97, 1);
+
+ /* Set the RESETOUTn low */
+ gpio_direction_output(111, 0);
+
+ /* Set U0_SW0 low for UART0 as console*/
+ gpio_direction_output(106, 0);
+
+ /* Set U0_SW1 low for UART0 as console*/
+ gpio_direction_output(108, 0);
+
+ /* Set LCD_B_PWR low to power down LCD Backlight*/
+ gpio_direction_output(102, 0);
+
+#ifndef CONFIG_USE_IRQ
+ irq_init();
+#endif
+
+ /*
+ * NAND CS setup - cycle counts based on da850evm NAND timings in the
+ * Linux kernel @ 25MHz EMIFA
+ */
+#ifdef CONFIG_NAND_DAVINCI
+ writel((DAVINCI_ABCR_WSETUP(0) |
+ DAVINCI_ABCR_WSTROBE(1) |
+ DAVINCI_ABCR_WHOLD(0) |
+ DAVINCI_ABCR_RSETUP(0) |
+ DAVINCI_ABCR_RSTROBE(1) |
+ DAVINCI_ABCR_RHOLD(0) |
+ DAVINCI_ABCR_TA(0) |
+ DAVINCI_ABCR_ASIZE_8BIT),
+ &davinci_emif_regs->ab1cr); /* CS2 */
+#endif
+
+ /*
+ * Power on required peripherals
+ * ARM does not have access by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+ return 1;
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ writel(readl(&davinci_syscfg_regs->suspsrc) &
+ ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART0),
+ &davinci_syscfg_regs->suspsrc);
+
+ /* configure pinmux settings */
+ if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
+ return 1;
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+ if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
+ return 1;
+
+ davinci_emac_mii_mode_sel(HAS_RMII);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+ /* enable the console UART */
+ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+ DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart0_ctrl_regs->pwremu_mgmt);
+
+ /*
+ * Reconfigure the LCDC priority to the highest to ensure that
+ * the throughput/latency requirements for the LCDC are met.
+ */
+ writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff,
+ &davinci_syscfg_regs->mstpri[2]);
+
+
+ return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_init(void)
+{
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_EA20;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ da8xx_video_init(&lcd_panel, &lcd_cfg, 16);
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+
+int board_late_init(void)
+{
+ unsigned char buf[2];
+ int ret;
+
+ /* PinMux for HALTEN */
+ if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
+ return 1;
+
+ /* Set HALTEN to high */
+ gpio_direction_output(134, 1);
+
+ /* Set fixed contrast settings for LCD via I2C potentiometer */
+ buf[0] = 0x00;
+ buf[1] = 0xd7;
+ ret = i2c_write(0x2e, 6, 1, buf, 2);
+ if (ret)
+ puts("\nContrast Settings FAILED\n");
+
+ /* Set LCD_B_PWR high to power up LCD Backlight*/
+ gpio_set_value(102, 1);
+ return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ /*
+ * This board has a RMII PHY. However, the MDC line on the SOM
+ * must not be disabled (there is no MII PHY on the
+ * baseboard) via the GPIO2[6], because this pin
+ * disables at the same time the SPI flash.
+ */
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
diff --git a/board/davinci/schmoogie/Kconfig b/board/davinci/schmoogie/Kconfig
new file mode 100644
index 0000000..3581075
--- /dev/null
+++ b/board/davinci/schmoogie/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DAVINCI_SCHMOOGIE
+
+config SYS_BOARD
+ default "schmoogie"
+
+config SYS_VENDOR
+ default "davinci"
+
+config SYS_CONFIG_NAME
+ default "davinci_schmoogie"
+
+endif
diff --git a/board/davinci/schmoogie/MAINTAINERS b/board/davinci/schmoogie/MAINTAINERS
new file mode 100644
index 0000000..808e7fc
--- /dev/null
+++ b/board/davinci/schmoogie/MAINTAINERS
@@ -0,0 +1,6 @@
+SCHMOOGIE BOARD
+#M: -
+S: Maintained
+F: board/davinci/schmoogie/
+F: include/configs/davinci_schmoogie.h
+F: configs/davinci_schmoogie_defconfig
diff --git a/board/davinci/schmoogie/Makefile b/board/davinci/schmoogie/Makefile
new file mode 100644
index 0000000..e170d55
--- /dev/null
+++ b/board/davinci/schmoogie/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := schmoogie.o
+obj-y += board_init.o
diff --git a/board/davinci/schmoogie/board_init.S b/board/davinci/schmoogie/board_init.S
new file mode 100644
index 0000000..ded0590
--- /dev/null
+++ b/board/davinci/schmoogie/board_init.S
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Board-specific low level initialization code. Called at the very end
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * initialization required.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+.globl dv_board_init
+dv_board_init:
+
+ mov pc, lr
diff --git a/board/davinci/schmoogie/config.mk b/board/davinci/schmoogie/config.mk
new file mode 100644
index 0000000..ed80707
--- /dev/null
+++ b/board/davinci/schmoogie/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Swaminathan <swami.iyer@ti.com>
+#
+# Davinci EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Davinci EVM has 1 bank of 256 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 9000'0000
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# Visioneering Corp. Sonata board (ARM926EJS) cpu
+#
+# Sonata board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
+#
+# Schmoogie board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# we load ourself to 8108 '0000
+#
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c
new file mode 100644
index 0000000..741afc4
--- /dev/null
+++ b/board/davinci/schmoogie/schmoogie.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * SPDX-License-Identifier: GPL-2.0+
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* Configure AEMIF pins (although this should be configured at boot time
+ * with pull-up/pull-down resistors) */
+ REG(PINMUX0) = 0x00000c1f;
+
+ davinci_errata_workarounds();
+
+ /* Power on required peripherals */
+ lpsc_on(DAVINCI_LPSC_GPIO);
+
+#if !defined(CONFIG_SYS_USE_DSPLINK)
+ /* Powerup the DSP */
+ dsp_on();
+#endif /* CONFIG_SYS_USE_DSPLINK */
+
+ davinci_enable_uart0();
+ davinci_enable_emac();
+ davinci_enable_i2c();
+
+ lpsc_on(DAVINCI_LPSC_TIMER1);
+ timer_init();
+
+ return(0);
+}
+
+int misc_init_r(void)
+{
+ u_int8_t tmp[20], buf[10];
+ int i = 0;
+
+ /* Set serial number from UID chip */
+ const u_int8_t crc_tbl[256] = {
+ 0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83,
+ 0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41,
+ 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e,
+ 0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc,
+ 0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0,
+ 0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62,
+ 0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d,
+ 0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff,
+ 0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5,
+ 0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07,
+ 0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58,
+ 0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a,
+ 0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6,
+ 0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24,
+ 0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b,
+ 0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9,
+ 0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f,
+ 0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd,
+ 0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92,
+ 0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50,
+ 0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c,
+ 0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee,
+ 0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1,
+ 0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73,
+ 0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49,
+ 0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b,
+ 0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4,
+ 0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16,
+ 0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a,
+ 0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8,
+ 0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7,
+ 0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
+ };
+
+ /* Set serial number from UID chip */
+ if (i2c_read(CONFIG_SYS_UID_ADDR, 0, 1, buf, 8)) {
+ printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
+ setenv("serial#", "FAILED");
+ } else {
+ if (buf[0] != 0x70) {
+ /* Device Family Code */
+ printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
+ setenv("serial#", "FAILED");
+ }
+ }
+ /* Now check CRC */
+ tmp[0] = 0;
+ for (i = 0; i < 8; i++)
+ tmp[0] = crc_tbl[tmp[0] ^ buf[i]];
+
+ if (tmp[0] != 0) {
+ printf("\nUID @ 0x%02x - BAD CRC!!!\n", CONFIG_SYS_UID_ADDR);
+ setenv("serial#", "FAILED");
+ } else {
+ /* CRC OK, set "serial" env variable */
+ sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x",
+ buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]);
+ setenv("serial#", (char *)&tmp[0]);
+ }
+
+ return(0);
+}
diff --git a/board/davinci/sffsdr/Kconfig b/board/davinci/sffsdr/Kconfig
new file mode 100644
index 0000000..dc48f31
--- /dev/null
+++ b/board/davinci/sffsdr/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DAVINCI_SFFSDR
+
+config SYS_BOARD
+ default "sffsdr"
+
+config SYS_VENDOR
+ default "davinci"
+
+config SYS_CONFIG_NAME
+ default "davinci_sffsdr"
+
+endif
diff --git a/board/davinci/sffsdr/MAINTAINERS b/board/davinci/sffsdr/MAINTAINERS
new file mode 100644
index 0000000..5c7e132
--- /dev/null
+++ b/board/davinci/sffsdr/MAINTAINERS
@@ -0,0 +1,6 @@
+SFFSDR BOARD
+#M: -
+S: Maintained
+F: board/davinci/sffsdr/
+F: include/configs/davinci_sffsdr.h
+F: configs/davinci_sffsdr_defconfig
diff --git a/board/davinci/sffsdr/Makefile b/board/davinci/sffsdr/Makefile
new file mode 100644
index 0000000..4ab30a4
--- /dev/null
+++ b/board/davinci/sffsdr/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := sffsdr.o
+obj-y += board_init.o
diff --git a/board/davinci/sffsdr/board_init.S b/board/davinci/sffsdr/board_init.S
new file mode 100644
index 0000000..ded0590
--- /dev/null
+++ b/board/davinci/sffsdr/board_init.S
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Board-specific low level initialization code. Called at the very end
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * initialization required.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+.globl dv_board_init
+dv_board_init:
+
+ mov pc, lr
diff --git a/board/davinci/sffsdr/config.mk b/board/davinci/sffsdr/config.mk
new file mode 100644
index 0000000..4fe9007
--- /dev/null
+++ b/board/davinci/sffsdr/config.mk
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+# Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
+#
+# Lyrtech SFF SDR board (ARM926EJS) cpu
+#
+# SFF SDR board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 87FF'FFFF
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# Integrity kernel is expected to be at 8000'0000, entry 8000'00D0,
+# up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc).
+#
+# we load ourself to 8400'0000 to provide at least 32MB spacing
+# between us and the Integrity kernel image
+CONFIG_SYS_TEXT_BASE = 0x84000000
diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c
new file mode 100644
index 0000000..f6ab91e
--- /dev/null
+++ b/board/davinci/sffsdr/sffsdr.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/davinci_misc.h>
+
+#define DAVINCI_A3CR (0x01E00014) /* EMIF-A CS3 config register. */
+#define DAVINCI_A3CR_VAL (0x3FFFFFFD) /* EMIF-A CS3 value for FPGA. */
+
+#define INTEGRITY_SYSCFG_OFFSET 0x7E8
+#define INTEGRITY_CHECKWORD_OFFSET 0x7F8
+#define INTEGRITY_CHECKWORD_VALUE 0x10ADBEEF
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /* arch number of the board */
+ gd->bd->bi_arch_number = MACH_TYPE_SFFSDR;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ davinci_errata_workarounds();
+
+ /* Power on required peripherals */
+ lpsc_on(DAVINCI_LPSC_GPIO);
+
+#if !defined(CONFIG_SYS_USE_DSPLINK)
+ /* Powerup the DSP */
+ dsp_on();
+#endif /* CONFIG_SYS_USE_DSPLINK */
+
+ davinci_enable_uart0();
+ davinci_enable_emac();
+ davinci_enable_i2c();
+
+ lpsc_on(DAVINCI_LPSC_TIMER1);
+ timer_init();
+
+ return(0);
+}
+
+/* Read ethernet MAC address from Integrity data structure inside EEPROM.
+ * Returns 1 if found, 0 otherwise.
+ */
+static int sffsdr_read_mac_address(uint8_t *buf)
+{
+ u_int32_t value, mac[2], address;
+
+ /* Read Integrity data structure checkword. */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
+ goto err;
+ if (value != INTEGRITY_CHECKWORD_VALUE)
+ return 0;
+
+ /* Read SYSCFG structure offset. */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
+ goto err;
+ address = 0x800 + (int) value; /* Address of SYSCFG structure. */
+
+ /* Read NET CONFIG structure offset. */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
+ goto err;
+ address = 0x800 + (int) value; /* Address of NET CONFIG structure. */
+ address += 12; /* Address of NET INTERFACE CONFIG structure. */
+
+ /* Read NET INTERFACE CONFIG 2 structure offset. */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
+ goto err;
+ address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE
+ * CONFIG 2 structure. */
+
+ /* Read MAC address. */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8))
+ goto err;
+
+ buf[0] = mac[0] >> 24;
+ buf[1] = mac[0] >> 16;
+ buf[2] = mac[0] >> 8;
+ buf[3] = mac[0];
+ buf[4] = mac[1] >> 24;
+ buf[5] = mac[1] >> 16;
+
+ return 1; /* Found */
+
+err:
+ printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
+ return 0;
+}
+
+/* Platform dependent initialisation. */
+int misc_init_r(void)
+{
+ uint8_t i2cbuf;
+ uint8_t eeprom_enetaddr[6];
+
+ /* EMIF-A CS3 configuration for FPGA. */
+ REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
+
+ /* Configure I2C switch (PCA9543) to enable channel 0. */
+ i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0;
+ if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0,
+ CONFIG_SYS_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) {
+ printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9543_ADDR);
+ return 1;
+ }
+
+ /* Read Ethernet MAC address from EEPROM if available. */
+ if (sffsdr_read_mac_address(eeprom_enetaddr))
+ davinci_sync_env_enetaddr(eeprom_enetaddr);
+
+ return(0);
+}
diff --git a/board/davinci/sonata/Kconfig b/board/davinci/sonata/Kconfig
new file mode 100644
index 0000000..4440d95
--- /dev/null
+++ b/board/davinci/sonata/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DAVINCI_SONATA
+
+config SYS_BOARD
+ default "sonata"
+
+config SYS_VENDOR
+ default "davinci"
+
+config SYS_CONFIG_NAME
+ default "davinci_sonata"
+
+endif
diff --git a/board/davinci/sonata/MAINTAINERS b/board/davinci/sonata/MAINTAINERS
new file mode 100644
index 0000000..40659e5
--- /dev/null
+++ b/board/davinci/sonata/MAINTAINERS
@@ -0,0 +1,6 @@
+SONATA BOARD
+#M: -
+S: Maintained
+F: board/davinci/sonata/
+F: include/configs/davinci_sonata.h
+F: configs/davinci_sonata_defconfig
diff --git a/board/davinci/sonata/Makefile b/board/davinci/sonata/Makefile
new file mode 100644
index 0000000..92e1a18
--- /dev/null
+++ b/board/davinci/sonata/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := sonata.o
+obj-y += board_init.o
diff --git a/board/davinci/sonata/board_init.S b/board/davinci/sonata/board_init.S
new file mode 100644
index 0000000..0a47ad5
--- /dev/null
+++ b/board/davinci/sonata/board_init.S
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Board-specific low level initialization code. Called at the very end
+ * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
+ * initialization required.
+ *
+ * For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer
+ * Sonata boards, AFAIK, don't use this so it's just return by default. Ask
+ * Visioneering if they reinvented the wheel once again to make sure :)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+.globl dv_board_init
+dv_board_init:
+#ifdef SONATA_BOARD_GPIOWP
+ /* Set PINMUX0 to enable GPIO4 */
+ ldr r0, _PINMUX0
+ ldr r1, GPIO4_EN_MASK
+ ldr r2, [r0]
+ and r2, r2, r1
+ str r2, [r0]
+
+ /* Enable GPIO LPSC module */
+ ldr r0, PTSTAT
+
+gpio_ptstat_loop1:
+ ldr r2, [r0]
+ tst r2, $0x00000001
+ bne gpio_ptstat_loop1
+
+ ldr r1, MDCTL_GPIO
+ ldr r2, [r1]
+ and r2, r2, $0xfffffff8
+ orr r2, r2, $0x00000003
+ str r2, [r1]
+
+ orr r2, r2, $0x00000200
+ str r2, [r1]
+
+ ldr r1, PTCMD
+ mov r2, $0x00000001
+ str r2, [r1]
+
+gpio_ptstat_loop2:
+ ldr r2, [r0]
+ tst r2, $0x00000001
+ bne gpio_ptstat_loop2
+
+ ldr r0, MDSTAT_GPIO
+gpio_mdstat_loop:
+ ldr r2, [r0]
+ and r2, r2, $0x0000001f
+ teq r2, $0x00000003
+ bne gpio_mdstat_loop
+
+ /* GPIO4 -> output */
+ ldr r0, GPIO_DIR01
+ mov r1, $0x10
+ ldr r2, [r0]
+ bic r2, r2, r0
+ str r2, [r0]
+
+ /* Set it to 0 (Write Protect) */
+ ldr r0, GPIO_CLR_DATA01
+ str r1, [r0]
+#endif
+
+ mov pc, lr
+
+#ifdef SONATA_BOARD_GPIOWP
+.ltorg
+
+GPIO4_EN_MASK:
+ .word 0xf77fffff
+MDCTL_GPIO:
+ .word 0x01c41a68
+MDSTAT_GPIO:
+ .word 0x01c41868
+GPIO_DIR01:
+ .word 0x01c67010
+GPIO_CLR_DATA01:
+ .word 0x01c6701c
+#endif
diff --git a/board/davinci/sonata/config.mk b/board/davinci/sonata/config.mk
new file mode 100644
index 0000000..ed80707
--- /dev/null
+++ b/board/davinci/sonata/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Swaminathan <swami.iyer@ti.com>
+#
+# Davinci EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Davinci EVM has 1 bank of 256 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 9000'0000
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# Visioneering Corp. Sonata board (ARM926EJS) cpu
+#
+# Sonata board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
+#
+# Schmoogie board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# we load ourself to 8108 '0000
+#
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+CONFIG_SYS_TEXT_BASE = 0x81080000
diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c
new file mode 100644
index 0000000..f5c3258
--- /dev/null
+++ b/board/davinci/sonata/sonata.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * SPDX-License-Identifier: GPL-2.0+
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/davinci_misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ /* Configure AEMIF pins (although this should be configured at boot time
+ * with pull-up/pull-down resistors) */
+ REG(PINMUX0) = 0x00000c1f;
+
+ davinci_errata_workarounds();
+
+ /* Power on required peripherals */
+ lpsc_on(DAVINCI_LPSC_GPIO);
+
+#if !defined(CONFIG_SYS_USE_DSPLINK)
+ /* Powerup the DSP */
+ dsp_on();
+#endif /* CONFIG_SYS_USE_DSPLINK */
+
+ davinci_enable_uart0();
+ davinci_enable_emac();
+ davinci_enable_i2c();
+
+ lpsc_on(DAVINCI_LPSC_TIMER1);
+ timer_init();
+
+ return(0);
+}
+
+int misc_init_r(void)
+{
+ uint8_t eeprom_enetaddr[6];
+
+ /* Read Ethernet MAC address from EEPROM if available. */
+ if (dvevm_read_mac_address(eeprom_enetaddr))
+ davinci_sync_env_enetaddr(eeprom_enetaddr);
+
+ return(0);
+}
+
+#ifdef CONFIG_NAND_DAVINCI
+
+/* Set WP on deselect, write enable on select */
+static void nand_sonata_select_chip(struct mtd_info *mtd, int chip)
+{
+#define GPIO_SET_DATA01 0x01c67018
+#define GPIO_CLR_DATA01 0x01c6701c
+#define GPIO_NAND_WP (1 << 4)
+#ifdef SONATA_BOARD_GPIOWP
+ if (chip < 0) {
+ REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
+ } else {
+ REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
+ }
+#endif
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+ nand->select_chip = nand_sonata_select_chip;
+ return 0;
+}
+
+#endif /* CONFIG_NAND_DAVINCI */
diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
new file mode 100644
index 0000000..1286e45
--- /dev/null
+++ b/board/dbau1x00/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_DBAU1X00
+
+config SYS_BOARD
+ default "dbau1x00"
+
+config SYS_SOC
+ default "au1x00"
+
+config SYS_CONFIG_NAME
+ default "dbau1x00"
+
+menu "dbau1x00 board options"
+
+choice
+ prompt "Select au1x00 SoC type"
+
+config DBAU1100
+ bool "Select AU1100"
+
+config DBAU1500
+ bool "Select AU1500"
+
+config DBAU1550
+ bool "Select AU1550"
+
+endchoice
+
+endmenu
+
+endif
diff --git a/board/dbau1x00/MAINTAINERS b/board/dbau1x00/MAINTAINERS
new file mode 100644
index 0000000..b94ed81
--- /dev/null
+++ b/board/dbau1x00/MAINTAINERS
@@ -0,0 +1,10 @@
+DBAU1X00 BOARD
+M: Thomas Lange <thomas@corelatus.se>
+S: Maintained
+F: board/dbau1x00/
+F: include/configs/dbau1x00.h
+F: configs/dbau1000_defconfig
+F: configs/dbau1100_defconfig
+F: configs/dbau1500_defconfig
+F: configs/dbau1550_defconfig
+F: configs/dbau1550_el_defconfig
diff --git a/board/dbau1x00/Makefile b/board/dbau1x00/Makefile
new file mode 100644
index 0000000..2f14402
--- /dev/null
+++ b/board/dbau1x00/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = dbau1x00.o
+obj-y += lowlevel_init.o
diff --git a/board/dbau1x00/README b/board/dbau1x00/README
new file mode 100644
index 0000000..b1e9494
--- /dev/null
+++ b/board/dbau1x00/README
@@ -0,0 +1,63 @@
+By Thomas.Lange@corelatus.se 2004-Oct-05
+----------------------------------------
+DbAu1xx0 are development boards from AMD containing
+an Alchemy AU1xx0 series cpu with mips32 core.
+Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
+
+Limitations & comments
+----------------------
+Support was originally big endian only.
+I have not tested, but several u-boot users report working
+configurations in little endian mode.
+
+I named the board dbau1x00, to allow
+support for all three development boards
+( dbau1000, dbau1100 and dbau1500 ).
+Now there is a new board called dbau1550 also, which
+should be supported RSN.
+
+I only have a dbau1000, so my testing is limited
+to this board.
+
+The board has two different flash banks, that can
+be selected via dip switch. This makes it possible
+to test new bootloaders without thrashing the YAMON
+boot loader delivered with board.
+
+NOTE! When you switch between the two boot flashes, the
+base addresses will be swapped.
+Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has
+to match the address where u-boot is located when you
+actually launch.
+
+Ethernet only supported for mac0.
+
+PCMCIA only supported for slot 0, only 3.3V.
+
+PCMCIA IDE tested with Sandisk Compact Flash and
+IBM microdrive.
+
+###################################
+######## NOTE!!!!!! #########
+###################################
+If you partition a disk on another system (e.g. laptop),
+all bytes will be swapped on 16bit level when using
+PCMCIA and running cpu in big endian mode!!!!
+
+This is probably due to an error in Au1000 chip.
+
+Solution:
+
+a) Boot via network and partition disk directly from
+dbau1x00. The endian will then be correct.
+
+b) Partition disk on "laptop" and fill it with all files
+you need. Then write a simple program that endian swaps
+whole disk,
+
+Example:
+Original "laptop" byte order:
+B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
+
+Dbau1000 byte order will then be:
+B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
diff --git a/board/dbau1x00/config.mk b/board/dbau1x00/config.mk
new file mode 100644
index 0000000..b378ac8
--- /dev/null
+++ b/board/dbau1x00/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#
+# AMD development board AMD Alchemy DbAu1x00, MIPS32 core
+#
+
+# ROM version
+CONFIG_SYS_TEXT_BASE = 0xbfc00000
+
+# RAM version
+#CONFIG_SYS_TEXT_BASE = 0x80100000
diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c
new file mode 100644
index 0000000..bd20f6e
--- /dev/null
+++ b/board/dbau1x00/dbau1x00.c
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+#include <asm/io.h>
+
+phys_size_t initdram(int board_type)
+{
+ /* Sdram is setup by assembler code */
+ /* If memory could be changed, we should return the true value here */
+ return MEM_SIZE*1024*1024;
+}
+
+#define BCSR_PCMCIA_PC0DRVEN 0x0010
+#define BCSR_PCMCIA_PC0RST 0x0080
+
+/* In arch/mips/cpu/cpu.c */
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
+
+int checkboard (void)
+{
+#ifdef CONFIG_IDE_PCMCIA
+ u16 status;
+ volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
+#endif /* CONFIG_IDE_PCMCIA */
+ volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
+ volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
+ u32 proc_id;
+
+ *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
+
+ proc_id = read_c0_prid();
+
+ switch (proc_id >> 24) {
+ case 0:
+ puts ("Board: Merlot (DbAu1000)\n");
+ printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
+ (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+ break;
+ case 1:
+ puts ("Board: DbAu1500\n");
+ printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
+ (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+ break;
+ case 2:
+ puts ("Board: DbAu1100\n");
+ printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
+ (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+ break;
+ case 3:
+ puts ("Board: DbAu1550\n");
+ printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
+ (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+ break;
+ default:
+ printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
+ }
+
+ set_io_port_base(0);
+
+#ifdef CONFIG_IDE_PCMCIA
+ /* Enable 3.3 V on slot 0 ( VCC )
+ No 5V */
+ status = 4;
+ *pcmcia_bcsr = status;
+
+ status |= BCSR_PCMCIA_PC0DRVEN;
+ *pcmcia_bcsr = status;
+ au_sync();
+
+ udelay(300*1000);
+
+ status |= BCSR_PCMCIA_PC0RST;
+ *pcmcia_bcsr = status;
+ au_sync();
+
+ udelay(100*1000);
+
+ /* PCMCIA is on a 36 bit physical address.
+ We need to map it into a 32 bit addresses */
+
+#if 0
+ /* We dont need theese unless we run whole pcmcia package */
+ write_one_tlb(20, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
+ 0x3C000017, /* Lo0 */
+ 0x3C200017); /* Lo1 */
+
+ write_one_tlb(21, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
+ 0x3D000017, /* Lo0 */
+ 0x3D200017); /* Lo1 */
+#endif /* 0 */
+ write_one_tlb(22, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
+ 0x3E000017, /* Lo0 */
+ 0x3E200017); /* Lo1 */
+#endif /* CONFIG_IDE_PCMCIA */
+
+ /* Release reset of ethernet PHY chips */
+ /* Always do this, because linux does not know about it */
+ *phy = 3;
+
+ return 0;
+}
diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S
new file mode 100644
index 0000000..842fb76
--- /dev/null
+++ b/board/dbau1x00/lowlevel_init.S
@@ -0,0 +1,589 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#define AU1500_SYS_ADDR 0xB1900000
+#define sys_endian 0x0038
+#define CP0_Config0 $16
+#define CPU_SCALE ((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
+#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000)
+
+ .text
+ .set noreorder
+ .set mips32
+
+ .globl lowlevel_init
+lowlevel_init:
+ /*
+ * Step 1) Establish CPU endian mode.
+ * Db1500-specific:
+ * Switch S1.1 Off(bit7 reads 1) is Little Endian
+ * Switch S1.1 On (bit7 reads 0) is Big Endian
+ */
+#ifdef CONFIG_DBAU1550
+ li t0, MEM_STCFG2
+ li t1, 0x00000040
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME2
+ li t1, 0x22080a20
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR2
+ li t1, 0x10c03f00
+ sw t1, 0(t0)
+#else
+ li t0, MEM_STCFG1
+ li t1, 0x00000080
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME1
+ li t1, 0x22080a20
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR1
+ li t1, 0x10c03f00
+ sw t1, 0(t0)
+#endif
+
+ li t0, DB1XX0_BCSR_ADDR
+ lw t1,8(t0)
+ andi t1,t1,0x80
+ beq zero,t1,big_endian
+ nop
+little_endian:
+
+ /* Change Au1 core to little endian */
+ li t0, AU1500_SYS_ADDR
+ li t1, 1
+ sw t1, sys_endian(t0)
+ mfc0 t2, CP0_CONFIG
+ mtc0 t2, CP0_CONFIG
+ nop
+ nop
+
+ /* Big Endian is default so nothing to do but fall through */
+
+big_endian:
+
+ /*
+ * Step 2) Establish Status Register
+ * (set BEV, clear ERL, clear EXL, clear IE)
+ */
+ li t1, 0x00400000
+ mtc0 t1, CP0_STATUS
+
+ /*
+ * Step 3) Establish CP0 Config0
+ * (set OD, set K0=3)
+ */
+ li t1, 0x00080003
+ mtc0 t1, CP0_CONFIG
+
+ /*
+ * Step 4) Disable Watchpoint facilities
+ */
+ li t1, 0x00000000
+ mtc0 t1, CP0_WATCHLO
+ mtc0 t1, CP0_IWATCHLO
+ /*
+ * Step 5) Disable the performance counters
+ */
+ mtc0 zero, CP0_PERFORMANCE
+ nop
+
+ /*
+ * Step 6) Establish EJTAG Debug register
+ */
+ mtc0 zero, CP0_DEBUG
+ nop
+
+ /*
+ * Step 7) Establish Cause
+ * (set IV bit)
+ */
+ li t1, 0x00800000
+ mtc0 t1, CP0_CAUSE
+
+ /* Establish Wired (and Random) */
+ mtc0 zero, CP0_WIRED
+ nop
+
+#ifdef CONFIG_DBAU1550
+ /* No workaround if running from ram */
+ lui t0, 0xffc0
+ lui t3, 0xbfc0
+ and t1, ra, t0
+ bne t1, t3, noCacheJump
+ nop
+
+ /*** From AMD YAMON ***/
+ /*
+ * Step 8) Initialize the caches
+ */
+ li t0, (16*1024)
+ li t1, 32
+ li t2, 0x80000000
+ addu t3, t0, t2
+cacheloop:
+ cache 0, 0(t2)
+ cache 1, 0(t2)
+ addu t2, t1
+ bne t2, t3, cacheloop
+ nop
+
+ /* Save return address */
+ move t3, ra
+
+ /* Run from cacheable space now */
+ bal cachehere
+ nop
+cachehere:
+ li t1, ~0x20000000 /* convert to KSEG0 */
+ and t0, ra, t1
+ addi t0, 5*4 /* 5 insns beyond cachehere */
+ jr t0
+ nop
+
+ /* Restore return address */
+ move ra, t3
+
+ /*
+ * Step 9) Initialize the TLB
+ */
+ li t0, 0 # index value
+ li t1, 0x00000000 # entryhi value
+ li t2, 32 # 32 entries
+
+tlbloop:
+ /* Probe TLB for matching EntryHi */
+ mtc0 t1, CP0_ENTRYHI
+ tlbp
+ nop
+
+ /* Examine Index[P], 1=no matching entry */
+ mfc0 t3, CP0_INDEX
+ li t4, 0x80000000
+ and t3, t4, t3
+ addiu t1, t1, 1 # increment t1 (asid)
+ beq zero, t3, tlbloop
+ nop
+
+ /* Initialize the TLB entry */
+ mtc0 t0, CP0_INDEX
+ mtc0 zero, CP0_ENTRYLO0
+ mtc0 zero, CP0_ENTRYLO1
+ mtc0 zero, CP0_PAGEMASK
+ tlbwi
+
+ /* Do it again */
+ addiu t0, t0, 1
+ bne t0, t2, tlbloop
+ nop
+
+#endif /* CONFIG_DBAU1550 */
+
+ /* First setup pll:s to make serial work ok */
+ /* We have a 12 MHz crystal */
+ li t0, SYS_CPUPLL
+ li t1, CPU_SCALE /* CPU clock */
+ sw t1, 0(t0)
+ sync
+ nop
+ nop
+
+ /* wait 1mS for clocks to settle */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+ /* Setup AUX PLL */
+ li t0, SYS_AUXPLL
+ li t1, 0x20 /* 96 MHz */
+ sw t1, 0(t0) /* aux pll */
+ sync
+
+#ifdef CONFIG_DBAU1550
+ /* Static memory controller */
+ /* RCE0 - can not change while fetching, do so from icache */
+ move t2, ra /* Store return address */
+ bal getAddr
+ nop
+
+getAddr:
+ move t1, ra
+ move ra, t2 /* Move return addess back */
+
+ cache 0x14,0(t1)
+ cache 0x14,32(t1)
+ /*** /From YAMON ***/
+
+noCacheJump:
+#endif /* CONFIG_DBAU1550 */
+
+#ifdef CONFIG_DBAU1550
+ li t0, MEM_STTIME0
+ li t1, 0x040181D7
+ sw t1, 0(t0)
+
+ /* RCE0 AMD MirrorBit Flash (?) */
+ li t0, MEM_STCFG0
+ li t1, 0x00000003
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR0
+ li t1, 0x11803E00
+ sw t1, 0(t0)
+#else /* CONFIG_DBAU1550 */
+ li t0, MEM_STTIME0
+ li t1, 0x040181D7
+ sw t1, 0(t0)
+
+ /* RCE0 AMD 29LV640M MirrorBit Flash */
+ li t0, MEM_STCFG0
+ li t1, 0x00000013
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR0
+ li t1, 0x11E03F80
+ sw t1, 0(t0)
+#endif /* CONFIG_DBAU1550 */
+
+ /* RCE1 CPLD Board Logic */
+ li t0, MEM_STCFG1
+ li t1, 0x00000080
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME1
+ li t1, 0x22080a20
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR1
+ li t1, 0x10c03f00
+ sw t1, 0(t0)
+
+#ifdef CONFIG_DBAU1550
+ /* RCE2 CPLD Board Logic */
+ li t0, MEM_STCFG2
+ li t1, 0x00000040
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME2
+ li t1, 0x22080a20
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR2
+ li t1, 0x10c03f00
+ sw t1, 0(t0)
+#else
+ li t0, MEM_STCFG2
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME2
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR2
+ li t1, 0x00000000
+ sw t1, 0(t0)
+#endif
+
+ /* RCE3 PCMCIA 250ns */
+ li t0, MEM_STCFG3
+ li t1, 0x00000002
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME3
+ li t1, 0x280E3E07
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR3
+ li t1, 0x10000000
+ sw t1, 0(t0)
+
+ sync
+
+ /* Set peripherals to a known state */
+ li t0, IC0_CFG0CLR
+ li t1, 0xFFFFFFFF
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG0CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG1CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG2CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_SRCSET
+ sw t1, 0(t0)
+
+ li t0, IC0_ASSIGNSET
+ sw t1, 0(t0)
+
+ li t0, IC0_WAKECLR
+ sw t1, 0(t0)
+
+ li t0, IC0_RISINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC0_FALLINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC0_TESTBIT
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, IC1_CFG0CLR
+ li t1, 0xFFFFFFFF
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG0CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG1CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG2CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_SRCSET
+ sw t1, 0(t0)
+
+ li t0, IC1_ASSIGNSET
+ sw t1, 0(t0)
+
+ li t0, IC1_WAKECLR
+ sw t1, 0(t0)
+
+ li t0, IC1_RISINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC1_FALLINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC1_TESTBIT
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, SYS_FREQCTRL0
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_FREQCTRL1
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_CLKSRC
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_PININPUTEN
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, 0xB1100100
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, 0xB1400100
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+
+ li t0, SYS_WAKEMSK
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_WAKESRC
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ /* wait 1mS before setup */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+
+#ifdef CONFIG_DBAU1550
+/* SDCS 0,1,2 DDR SDRAM */
+ li t0, MEM_SDMODE0
+ li t1, 0x04276221
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE1
+ li t1, 0x04276221
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE2
+ li t1, 0x04276221
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR0
+ li t1, 0xe21003f0
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR1
+ li t1, 0xe21043f0
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR2
+ li t1, 0xe21083f0
+ sw t1, 0(t0)
+
+ sync
+
+ li t0, MEM_SDCONFIGA
+ li t1, 0x9030060a /* Program refresh - disabled */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDCONFIGB
+ li t1, 0x00028000
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDPRECMD /* Precharge all */
+ li t1, 0
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD0
+ li t1, 0x40000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD1
+ li t1, 0x40000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD2
+ li t1, 0x40000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD0
+ li t1, 0x00000063
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD1
+ li t1, 0x00000063
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD2
+ li t1, 0x00000063
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDPRECMD /* Precharge all */
+ sw zero, 0(t0)
+ sync
+
+ /* Issue 2 autoref */
+ li t0, MEM_SDAUTOREF
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDAUTOREF
+ sw zero, 0(t0)
+ sync
+
+ /* Enable refresh */
+ li t0, MEM_SDCONFIGA
+ li t1, 0x9830060a /* Program refresh - enabled */
+ sw t1, 0(t0)
+ sync
+
+#else /* CONFIG_DBAU1550 */
+/* SDCS 0,1 SDRAM */
+ li t0, MEM_SDMODE0
+ li t1, 0x005522AA
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE1
+ li t1, 0x005522AA
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE2
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR0
+ li t1, 0x001003F8
+ sw t1, 0(t0)
+
+
+ li t0, MEM_SDADDR1
+ li t1, 0x001023F8
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR2
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x64000C24 /* Disable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDPRECMD
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDAUTOREF
+ sw zero, 0(t0)
+ sync
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x66000C24 /* Enable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD0
+ li t1, 0x00000033
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD1
+ li t1, 0x00000033
+ sw t1, 0(t0)
+ sync
+
+#endif /* CONFIG_DBAU1550 */
+ /* wait 1mS after setup */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+
+ li t0, SYS_PINFUNC
+ li t1, 0x00008080
+ sw t1, 0(t0)
+
+ li t0, SYS_TRIOUTCLR
+ li t1, 0x00001FFF
+ sw t1, 0(t0)
+
+ li t0, SYS_OUTPUTCLR
+ li t1, 0x00008000
+ sw t1, 0(t0)
+ sync
+
+ jr ra
+ nop
diff --git a/board/denx/m28evk/Kconfig b/board/denx/m28evk/Kconfig
new file mode 100644
index 0000000..dd4dc4d
--- /dev/null
+++ b/board/denx/m28evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M28EVK
+
+config SYS_BOARD
+ default "m28evk"
+
+config SYS_VENDOR
+ default "denx"
+
+config SYS_SOC
+ default "mxs"
+
+config SYS_CONFIG_NAME
+ default "m28evk"
+
+endif
diff --git a/board/denx/m28evk/MAINTAINERS b/board/denx/m28evk/MAINTAINERS
new file mode 100644
index 0000000..b0535a9
--- /dev/null
+++ b/board/denx/m28evk/MAINTAINERS
@@ -0,0 +1,6 @@
+M28EVK BOARD
+M: Marek Vasut <marek.vasut@gmail.com>
+S: Maintained
+F: board/denx/m28evk/
+F: include/configs/m28evk.h
+F: configs/m28evk_defconfig
diff --git a/board/denx/m28evk/Makefile b/board/denx/m28evk/Makefile
new file mode 100644
index 0000000..5e890b1
--- /dev/null
+++ b/board/denx/m28evk/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := m28evk.o
+else
+obj-y := spl_boot.o
+endif
diff --git a/board/denx/m28evk/README b/board/denx/m28evk/README
new file mode 100644
index 0000000..cb3ae20
--- /dev/null
+++ b/board/denx/m28evk/README
@@ -0,0 +1,13 @@
+DENX M28EVK
+===========
+
+Files of the M28/M28EVK port
+----------------------------
+
+arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28
+arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28
+board/denx/m28evk/ - M28EVK board specific files
+include/configs/m28evk.h - M28EVK configuration file
+
+Follow the instructions from doc/README.mxs to generate a bootable SD card or to
+boot from NAND flash.
diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c
new file mode 100644
index 0000000..33d38cf
--- /dev/null
+++ b/board/denx/m28evk/m28evk.c
@@ -0,0 +1,173 @@
+/*
+ * DENX M28 module
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+ /* SSP2 clock at 160MHz */
+ mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
+
+#ifdef CONFIG_CMD_USB
+ mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
+ mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
+ MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
+ gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
+
+ mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 |
+ MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
+ gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0);
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+#ifdef CONFIG_CMD_MMC
+static int m28_mmc_wp(int id)
+{
+ if (id != 0) {
+ printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
+ return 1;
+ }
+
+ return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ /* Configure WP as input. */
+ gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
+ /* Turn on the power to the card. */
+ gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+
+ return mxsmmc_initialize(bis, 0, m28_mmc_wp, NULL);
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+
+#define MII_OPMODE_STRAP_OVERRIDE 0x16
+#define MII_PHY_CTRL1 0x1e
+#define MII_PHY_CTRL2 0x1f
+
+int fecmxc_mii_postcall(int phy)
+{
+#if defined(CONFIG_DENX_M28_V11) || defined(CONFIG_DENX_M28_V10)
+ /* KZ8031 PHY on old boards. */
+ const uint32_t freq = 0x0080;
+#else
+ /* KZ8021 PHY on new boards. */
+ const uint32_t freq = 0x0000;
+#endif
+
+ miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
+ miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
+ if (phy == 3)
+ miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct eth_device *dev;
+ int ret;
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+ CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
+ CLKCTRL_ENET_TIME_SEL_RMII_CLK);
+
+#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
+ /* Reset the new PHY */
+ gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
+ udelay(10000);
+ gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1);
+ udelay(10000);
+#endif
+
+ ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC0\n");
+ return ret;
+ }
+
+ ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC1\n");
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC0");
+ if (!dev) {
+ printf("FEC MXS: Unable to get FEC0 device entry\n");
+ return -EINVAL;
+ }
+
+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+ if (ret) {
+ printf("FEC MXS: Unable to register FEC0 mii postcall\n");
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC1");
+ if (!dev) {
+ printf("FEC MXS: Unable to get FEC1 device entry\n");
+ return -EINVAL;
+ }
+
+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+ if (ret) {
+ printf("FEC MXS: Unable to register FEC1 mii postcall\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+#endif
diff --git a/board/denx/m28evk/spl_boot.c b/board/denx/m28evk/spl_boot.c
new file mode 100644
index 0000000..5a1010e
--- /dev/null
+++ b/board/denx/m28evk/spl_boot.c
@@ -0,0 +1,206 @@
+/*
+ * DENX M28 Boot setup
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_GPMI (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* LED */
+ MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
+
+ /* framebuffer */
+ MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+
+ /* UART1 */
+#ifdef CONFIG_DENX_M28_V10
+ MX28_PAD_AUART0_CTS__DUART_RX,
+ MX28_PAD_AUART0_RTS__DUART_TX,
+#else
+ MX28_PAD_PWM0__DUART_RX,
+ MX28_PAD_PWM1__DUART_TX,
+#endif
+ MX28_PAD_AUART0_TX__DUART_RTS,
+ MX28_PAD_AUART0_RX__DUART_CTS,
+
+ /* UART2 */
+ MX28_PAD_AUART1_RX__AUART1_RX,
+ MX28_PAD_AUART1_TX__AUART1_TX,
+ MX28_PAD_AUART1_RTS__AUART1_RTS,
+ MX28_PAD_AUART1_CTS__AUART1_CTS,
+
+ /* CAN */
+ MX28_PAD_GPMI_RDY2__CAN0_TX,
+ MX28_PAD_GPMI_RDY3__CAN0_RX,
+
+ /* TSC2007 */
+ MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC,
+
+ /* MMC0 */
+ MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+ MX28_PAD_SSP0_SCK__SSP0_SCK |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+ MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), /* Power */
+ MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP */
+
+ /* GPMI NAND */
+ MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+ MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+
+ /* FEC Ethernet */
+ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+ MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
+ MX28_PAD_AUART2_RTS__GPIO_3_11, /* PHY reset */
+#endif
+
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+ /* EMI */
+ MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+ /* SPI2 (for flash) */
+ MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_SS0__SSP2_D3 |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+};
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/denx/m53evk/Kconfig b/board/denx/m53evk/Kconfig
new file mode 100644
index 0000000..0696ad7
--- /dev/null
+++ b/board/denx/m53evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M53EVK
+
+config SYS_BOARD
+ default "m53evk"
+
+config SYS_VENDOR
+ default "denx"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "m53evk"
+
+endif
diff --git a/board/denx/m53evk/MAINTAINERS b/board/denx/m53evk/MAINTAINERS
new file mode 100644
index 0000000..5d8c764
--- /dev/null
+++ b/board/denx/m53evk/MAINTAINERS
@@ -0,0 +1,6 @@
+M53EVK BOARD
+M: Marek Vasut <marek.vasut@gmail.com>
+S: Maintained
+F: board/denx/m53evk/
+F: include/configs/m53evk.h
+F: configs/m53evk_defconfig
diff --git a/board/denx/m53evk/Makefile b/board/denx/m53evk/Makefile
new file mode 100644
index 0000000..19b8977
--- /dev/null
+++ b/board/denx/m53evk/Makefile
@@ -0,0 +1,8 @@
+#
+# DENX M53EVK
+# Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := m53evk.o
diff --git a/board/denx/m53evk/imximage.cfg b/board/denx/m53evk/imximage.cfg
new file mode 100644
index 0000000..4cd002c
--- /dev/null
+++ b/board/denx/m53evk/imximage.cfg
@@ -0,0 +1,92 @@
+/*
+ * DENX M53 DRAM init values
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION 2
+
+
+/* Boot Offset 0x400, valid for both SD and NAND boot. */
+BOOT_OFFSET FLASH_OFFSET_STANDARD
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */
+DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */
+DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */
+DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */
+
+DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */
+DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */
+DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */
+
+DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */
+DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */
+DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */
+
+DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */
+DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */
+DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */
+
+DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */
+DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */
+DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */
+
+DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */
+DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */
+
+DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */
+DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */
+DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */
+DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */
+
+DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */
+DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */
+
+/* ESDCTL */
+DATA 4 0x63fd9088 0x32383535
+DATA 4 0x63fd9090 0x40383538
+DATA 4 0x63fd907c 0x0136014d
+DATA 4 0x63fd9080 0x01510141
+
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd900c 0x555952e3
+DATA 4 0x63fd9010 0xb68e8b63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x092080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x09208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00001800
+DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000
diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c
new file mode 100644
index 0000000..5dd6cdd
--- /dev/null
+++ b/board/denx/m53evk/m53evk.c
@@ -0,0 +1,402 @@
+/*
+ * DENX M53 module
+ *
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/imx-common/mx5_video.h>
+#include <asm/spl.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <spl.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+#include <usb/ehci-fsl.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+/* Special MXCFB sync flags are here. */
+#include "../drivers/video/mxcfb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uint32_t mx53_dram_size[2];
+
+phys_size_t get_effective_memsize(void)
+{
+ /*
+ * WARNING: We must override get_effective_memsize() function here
+ * to report only the size of the first DRAM bank. This is to make
+ * U-Boot relocator place U-Boot into valid memory, that is, at the
+ * end of the first DRAM bank. If we did not override this function
+ * like so, U-Boot would be placed at the address of the first DRAM
+ * bank + total DRAM size - sizeof(uboot), which in the setup where
+ * each DRAM bank contains 512MiB of DRAM would result in placing
+ * U-Boot into invalid memory area close to the end of the first
+ * DRAM bank.
+ */
+ return mx53_dram_size[0];
+}
+
+int dram_init(void)
+{
+ mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+ mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+
+ gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = mx53_dram_size[0];
+
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = mx53_dram_size[1];
+}
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart_pads[] = {
+ MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+ MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+ if (port == 0) {
+ /* USB OTG PWRON */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
+ gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
+
+ /* USB OTG Over Current */
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
+ } else if (port == 1) {
+ /* USB Host PWRON */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
+ gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
+
+ /* USB Host Over Current */
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
+ }
+
+ return 0;
+}
+#endif
+
+static void setup_iomux_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ /* MDIO pads */
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+
+ /* FEC 0 pads */
+ NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+
+ /* FEC 1 pads */
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg = {
+ MMC_SDHC1_BASE_ADDR,
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+ gpio_direction_input(IMX_GPIO_NR(1, 1));
+
+ return !gpio_get_value(IMX_GPIO_NR(1, 1));
+}
+
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA13__GPIO3_13,
+
+ MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
+ };
+
+ esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+
+ /* GPIO 2_31 is SD power */
+ gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+#endif
+
+#ifdef CONFIG_VIDEO
+static struct fb_videomode const ampire_wvga = {
+ .name = "Ampire",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 29851, /* picosecond (33.5 MHz) */
+ .left_margin = 89,
+ .right_margin = 164,
+ .upper_margin = 23,
+ .lower_margin = 10,
+ .hsync_len = 10,
+ .vsync_len = 10,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+};
+
+int board_video_skip(void)
+{
+ int ret;
+ ret = ipuv3_fb_init(&ire_wvga, 1, IPU_PIX_FMT_RGB666);
+ if (ret)
+ printf("Ampire LCD cannot be configured: %d\n", ret);
+ return ret;
+}
+#endif
+
+#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+ static const iomux_v3_cfg_t i2c_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
+}
+
+static void setup_iomux_video(void)
+{
+ static const iomux_v3_cfg_t lcd_pads[] = {
+ MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
+ MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
+ MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
+ MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
+ MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
+ MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
+ MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
+ MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
+ MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
+ MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
+ MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
+ MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
+ MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
+ MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
+ MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
+ MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
+ MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
+ MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
+ MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
+ MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
+ MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
+ MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
+ MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
+ MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
+ MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
+ MX53_PAD_EIM_DA13__IPU_DI1_D0_CS,
+ MX53_PAD_EIM_DA14__IPU_DI1_D1_CS,
+ MX53_PAD_EIM_DA15__IPU_DI1_PIN1,
+ MX53_PAD_EIM_DA11__IPU_DI1_PIN2,
+ MX53_PAD_EIM_DA12__IPU_DI1_PIN3,
+ MX53_PAD_EIM_A25__IPU_DI1_PIN12,
+ MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+}
+
+static void setup_iomux_nand(void)
+{
+ static const iomux_v3_cfg_t nand_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
+ PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
+ PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+}
+
+static void m53_set_clock(void)
+{
+ int ret;
+ const uint32_t ref_clk = MXC_HCLK;
+ const uint32_t dramclk = 400;
+ uint32_t cpuclk;
+
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
+ PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
+ gpio_direction_input(IMX_GPIO_NR(4, 0));
+
+ /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
+ cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
+
+ ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
+ if (ret)
+ printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
+
+ ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
+ if (ret) {
+ printf("CPU: Switch peripheral clock to %dMHz failed\n",
+ dramclk);
+ }
+
+ ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
+ if (ret)
+ printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
+}
+
+static void m53_set_nand(void)
+{
+ u32 i;
+
+ /* NAND flash is muxed on ATA pins */
+ setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
+
+ /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
+ for (i = 0x4; i < 0x94; i += 0x18) {
+ clrbits_le32(WEIM_BASE_ADDR + i,
+ WEIM_GCR2_MUX16_BYP_GRANT_MASK);
+ }
+
+ mxc_set_clock(0, 33, MXC_NFC_CLK);
+ enable_nfc_clk(1);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+ setup_iomux_i2c();
+ setup_iomux_nand();
+ setup_iomux_video();
+
+ m53_set_clock();
+
+ mxc_set_sata_internal_clock();
+
+ /* NAND clock @ 33MHz */
+ m53_set_nand();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: DENX M53EVK\n");
+
+ return 0;
+}
+
+/*
+ * NAND SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+ setup_iomux_nand();
+ m53_set_clock();
+ m53_set_nand();
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_NAND;
+}
+#endif
diff --git a/board/dnp5370/Kconfig b/board/dnp5370/Kconfig
new file mode 100644
index 0000000..797081d
--- /dev/null
+++ b/board/dnp5370/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_DNP5370
+
+config SYS_BOARD
+ default "dnp5370"
+
+config SYS_CONFIG_NAME
+ default "dnp5370"
+
+endif
diff --git a/board/dnp5370/MAINTAINERS b/board/dnp5370/MAINTAINERS
new file mode 100644
index 0000000..8333891
--- /dev/null
+++ b/board/dnp5370/MAINTAINERS
@@ -0,0 +1,6 @@
+DNP5370 BOARD
+M: M.Hasewinkel (MHA) <info@ssv-embedded.de>
+S: Maintained
+F: board/dnp5370/
+F: include/configs/dnp5370.h
+F: configs/dnp5370_defconfig
diff --git a/board/dnp5370/Makefile b/board/dnp5370/Makefile
new file mode 100644
index 0000000..865522f
--- /dev/null
+++ b/board/dnp5370/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := dnp5370.o
diff --git a/board/dnp5370/README b/board/dnp5370/README
new file mode 100644
index 0000000..0172698
--- /dev/null
+++ b/board/dnp5370/README
@@ -0,0 +1,67 @@
+This document describes the board support for
+Dil/NetPC DNP/5370 (http://www.dilnetpc.com/dnp0086.htm) module.
+The distributor is SSV (http://www.ssv-embedded.de),
+
+The module used to develop the support files contains:
+
+* Processor: Blackfin BF537 Rev 0.3 (600 MHz core / 120MHz RAM)
+
+* RAM: 32 MB SDRAM
+ Hynix HY57V561620FTP-H 810EA
+ Connected to Blackfin via "Expansion Bus"
+ Address range 0x0000.0000 - 0x1fff.ffff
+
+* NOR flash: 32 MBit (4 MByte)
+ Exel Semiconductor ES29LVS320EB
+ Connected to Blackfin via "Expansion Bus",
+ Chip Selects 0, 1 and 2, each is connected
+ to a 1 MB memory bank at Blackfin, therefore
+ only 3 MB accessible.
+ Address range 0x2000.0000 - 0x202f.ffff
+ CFI compatible
+
+ Exel Semiconductor was bought by Rohm Semiconductor (www.rohm.com).
+
+* NAND flash: 64 MBit (8 MByte)
+ Atmel 45DB642D-CNU
+ Connected to Blackfin via SPI
+ CFI compatible
+
+* Davicom DM9161EP Ethernet PHY
+
+* A SD card reader, connected via SPI
+
+* Hardware watchdog MAX823 or TPS3823
+
+(other devices not listed here)
+
+To run it, the module must be inserted in a 64 pin DIL socket
+on another board, e.g. DNP/EVA13 (together: SSV SK28).
+
+The Blackfin is booted from NOR flash. The NOR flash data begins
+with the U-Boot code and is then followed by the Linux code.
+Finally, the MAC is stored in the last sector.
+You may need to adjust these settings to your needs.
+The memory map used to develop the board support is:
+
+Memory map:
+0x00000000 .. 0x01ffffff SDRAM
+0x20000000 .. 0x202fffff NOR flash
+
+RAM use:
+0x01f9bffc .. 0x01fbbffb U-Boot stack
+0x01f9c000 .. 0x01f9ffff U-Boot global data
+0x01fa0000 .. 0x01fbffff U-Boot malloc() RAM
+0x01fc0000 .. 0x01ffffff U-Boot execution RAM
+
+NOR flash use:
+0x20000000 .. 0x0002ffff U-Boot
+0x20004000 .. 0x20005fff U-Boot environment
+0x20030000 .. 0x202effff Linux kernel image
+0x202f0000 .. 0x202fffff MAC address sector
+
+NOR flash is 0x00300000 (3145728) bytes large (3 MB).
+Max space for compressed kernel in flash is 0x002c0000 (2883584) bytes (2.75 MB)
+Max space for u-boot in flash is 0x00030000 (196608) bytes (192 KB)
+
+The module is hardwired to BYPASS boot mode.
diff --git a/board/dnp5370/dnp5370.c b/board/dnp5370/dnp5370.c
new file mode 100644
index 0000000..df721c9
--- /dev/null
+++ b/board/dnp5370/dnp5370.c
@@ -0,0 +1,87 @@
+/*
+ * U-boot - main board file
+ *
+ * (C) Copyright 2010 3ality Digital Systems
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/gpio.h>
+
+static void disable_external_watchdog(void)
+{
+#ifdef CONFIG_DNP5370_EXT_WD_DISABLE
+ /* disable external HW watchdog with PH13 = WD1 = 1 */
+ gpio_request(GPIO_PH13, "ext_wd");
+ gpio_direction_output(GPIO_PH13, 1);
+#endif
+}
+
+int checkboard(void)
+{
+ printf("Board: SSV DilNet DNP5370\n");
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+#ifdef CONFIG_SYS_NO_FLASH
+# define USE_MAC_IN_FLASH 0
+#else
+# define USE_MAC_IN_FLASH 1
+#endif
+ bool valid_mac = false;
+
+ if (USE_MAC_IN_FLASH) {
+ /* we cram the MAC in the last flash sector */
+ uchar *board_mac_addr = (uchar *)0x202F0000;
+ if (is_valid_ether_addr(board_mac_addr)) {
+ memcpy(mac_addr, board_mac_addr, 6);
+ valid_mac = true;
+ }
+ }
+
+ if (!valid_mac) {
+ puts("Warning: Generating 'random' MAC address\n");
+ eth_random_addr(mac_addr);
+ }
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+ disable_external_watchdog();
+
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+ /* we use the last sector for the MAC address / POST LDR */
+ extern flash_info_t flash_info[];
+ flash_protect(FLAG_PROTECT_SET, 0x202F0000, 0x202FFFFF, &flash_info[0]);
+#endif
+
+ return 0;
+}
diff --git a/board/earthlcd/favr-32-ezkit/Kconfig b/board/earthlcd/favr-32-ezkit/Kconfig
new file mode 100644
index 0000000..50e29ec
--- /dev/null
+++ b/board/earthlcd/favr-32-ezkit/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_FAVR_32_EZKIT
+
+config SYS_BOARD
+ default "favr-32-ezkit"
+
+config SYS_VENDOR
+ default "earthlcd"
+
+config SYS_SOC
+ default "at32ap700x"
+
+config SYS_CONFIG_NAME
+ default "favr-32-ezkit"
+
+endif
diff --git a/board/earthlcd/favr-32-ezkit/MAINTAINERS b/board/earthlcd/favr-32-ezkit/MAINTAINERS
new file mode 100644
index 0000000..89ba862
--- /dev/null
+++ b/board/earthlcd/favr-32-ezkit/MAINTAINERS
@@ -0,0 +1,6 @@
+FAVR-32-EZKIT BOARD
+#M: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
+S: Orphan (since 2014-06)
+F: board/earthlcd/favr-32-ezkit/
+F: include/configs/favr-32-ezkit.h
+F: configs/favr-32-ezkit_defconfig
diff --git a/board/earthlcd/favr-32-ezkit/Makefile b/board/earthlcd/favr-32-ezkit/Makefile
new file mode 100644
index 0000000..f712ab9
--- /dev/null
+++ b/board/earthlcd/favr-32-ezkit/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2008 Atmel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := favr-32-ezkit.o flash.o
diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
new file mode 100644
index 0000000..a74547b
--- /dev/null
+++ b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
+static const struct sdram_config sdram_config = {
+ /* MT48LC4M32B2P-6 (16 MB) */
+ .data_bits = SDRAM_DATA_32BIT,
+ .row_bits = 12,
+ .col_bits = 8,
+ .bank_bits = 2,
+ .cas = 3,
+ .twr = 2,
+ .trc = 7,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 5,
+ .txsr = 5,
+ /* 15.6 us */
+ .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
+};
+
+int board_early_init_f(void)
+{
+ /* Enable SDRAM in the EBI mux */
+ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+ portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
+ portmux_enable_usart3(PORTMUX_DRIVE_MIN);
+#if defined(CONFIG_MACB)
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+#if defined(CONFIG_MMC)
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ unsigned long expected_size;
+ unsigned long actual_size;
+ void *sdram_base;
+
+ sdram_base = uncached(EBI_SDRAM_BASE);
+
+ expected_size = sdram_init(sdram_base, &sdram_config);
+ actual_size = get_ram_size(sdram_base, expected_size);
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return actual_size;
+}
+
+int board_early_init_r(void)
+{
+ gd->bd->bi_phy_id[0] = 0x01;
+ return 0;
+}
+
+#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
+int board_eth_init(bd_t *bi)
+{
+ return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
+ bi->bi_phy_id[0]);
+}
+#endif
diff --git a/board/earthlcd/favr-32-ezkit/flash.c b/board/earthlcd/favr-32-ezkit/flash.c
new file mode 100644
index 0000000..e45c6f4
--- /dev/null
+++ b/board/earthlcd/favr-32-ezkit/flash.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+
+#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH
+#include <asm/arch/cacheflush.h>
+#include <asm/io.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+flash_info_t flash_info[1];
+
+static void flash_identify(uint16_t *flash, flash_info_t *info)
+{
+ unsigned long flags;
+
+ flags = disable_interrupts();
+
+ dcache_flush_unlocked();
+
+ writew(0xaa, flash + 0x555);
+ writew(0x55, flash + 0xaaa);
+ writew(0x90, flash + 0x555);
+ info->flash_id = readl(flash);
+ writew(0xff, flash);
+
+ readw(flash);
+
+ if (flags)
+ enable_interrupts();
+}
+
+unsigned long flash_init(void)
+{
+ unsigned long addr;
+ unsigned int i;
+
+ flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
+ flash_info[0].sector_count = 135;
+
+ flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]);
+
+ for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
+ flash_info[0].start[i] = addr;
+ for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
+ flash_info[0].start[i] = addr;
+
+ return CONFIG_SYS_FLASH_SIZE;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+ printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n",
+ info->flash_id >> 16, info->flash_id & 0xffff);
+ printf("Size: %ld MB in %d sectors\n",
+ info->size >> 10, info->sector_count);
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+ unsigned long flags;
+ unsigned long start_time;
+ uint16_t *fb, *sb;
+ unsigned int i;
+ int ret;
+ uint16_t status;
+
+ if ((s_first < 0) || (s_first > s_last)
+ || (s_last >= info->sector_count)) {
+ puts("Error: first and/or last sector out of range\n");
+ return ERR_INVAL;
+ }
+
+ for (i = s_first; i < s_last; i++)
+ if (info->protect[i]) {
+ printf("Error: sector %d is protected\n", i);
+ return ERR_PROTECTED;
+ }
+
+ fb = (uint16_t *)uncached(info->start[0]);
+
+ dcache_flush_unlocked();
+
+ for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
+ printf("Erasing sector %3d...", i);
+
+ sb = (uint16_t *)uncached(info->start[i]);
+
+ flags = disable_interrupts();
+
+ start_time = get_timer(0);
+
+ /* Unlock sector */
+ writew(0xaa, fb + 0x555);
+ writew(0x70, sb);
+
+ /* Erase sector */
+ writew(0xaa, fb + 0x555);
+ writew(0x55, fb + 0xaaa);
+ writew(0x80, fb + 0x555);
+ writew(0xaa, fb + 0x555);
+ writew(0x55, fb + 0xaaa);
+ writew(0x30, sb);
+
+ /* Wait for completion */
+ ret = ERR_OK;
+ do {
+ /* TODO: Timeout */
+ status = readw(sb);
+ } while ((status != 0xffff) && !(status & 0x28));
+
+ writew(0xf0, fb);
+
+ /*
+ * Make sure the command actually makes it to the bus
+ * before we re-enable interrupts.
+ */
+ readw(fb);
+
+ if (flags)
+ enable_interrupts();
+
+ if (status != 0xffff) {
+ printf("Flash erase error at address 0x%p: 0x%02x\n",
+ sb, status);
+ ret = ERR_PROG_ERROR;
+ break;
+ }
+ }
+
+ if (ctrlc())
+ printf("User interrupt!\n");
+
+ return ERR_OK;
+}
+
+int write_buff(flash_info_t *info, uchar *src,
+ ulong addr, ulong count)
+{
+ unsigned long flags;
+ uint16_t *base, *p, *s, *end;
+ uint16_t word, status, status1;
+ int ret = ERR_OK;
+
+ if (addr < info->start[0]
+ || (addr + count) > (info->start[0] + info->size)
+ || (addr + count) < addr) {
+ puts("Error: invalid address range\n");
+ return ERR_INVAL;
+ }
+
+ if (addr & 1 || count & 1 || (unsigned int)src & 1) {
+ puts("Error: misaligned source, destination or count\n");
+ return ERR_ALIGN;
+ }
+
+ base = (uint16_t *)uncached(info->start[0]);
+ end = (uint16_t *)uncached(addr + count);
+
+ flags = disable_interrupts();
+
+ dcache_flush_unlocked();
+ sync_write_buffer();
+
+ for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
+ p < end && !ctrlc(); p++, s++) {
+ word = *s;
+
+ writew(0xaa, base + 0x555);
+ writew(0x55, base + 0xaaa);
+ writew(0xa0, base + 0x555);
+ writew(word, p);
+
+ sync_write_buffer();
+
+ /* Wait for completion */
+ status1 = readw(p);
+ do {
+ /* TODO: Timeout */
+ status = status1;
+ status1 = readw(p);
+ } while (((status ^ status1) & 0x40) /* toggled */
+ && !(status1 & 0x28)); /* error bits */
+
+ /*
+ * We'll need to check once again for toggle bit
+ * because the toggle bit may stop toggling as I/O5
+ * changes to "1" (ref at49bv642.pdf p9)
+ */
+ status1 = readw(p);
+ status = readw(p);
+ if ((status ^ status1) & 0x40) {
+ printf("Flash write error at address 0x%p: "
+ "0x%02x != 0x%02x\n",
+ p, status,word);
+ ret = ERR_PROG_ERROR;
+ writew(0xf0, base);
+ readw(base);
+ break;
+ }
+
+ writew(0xf0, base);
+ readw(base);
+ }
+
+ if (flags)
+ enable_interrupts();
+
+ return ret;
+}
+
+#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */
diff --git a/board/egnite/ethernut5/Kconfig b/board/egnite/ethernut5/Kconfig
new file mode 100644
index 0000000..c42c734
--- /dev/null
+++ b/board/egnite/ethernut5/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ETHERNUT5
+
+config SYS_BOARD
+ default "ethernut5"
+
+config SYS_VENDOR
+ default "egnite"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "ethernut5"
+
+endif
diff --git a/board/egnite/ethernut5/MAINTAINERS b/board/egnite/ethernut5/MAINTAINERS
new file mode 100644
index 0000000..a4ad913
--- /dev/null
+++ b/board/egnite/ethernut5/MAINTAINERS
@@ -0,0 +1,6 @@
+ETHERNUT5 BOARD
+M: egnite GmbH <info@egnite.de>
+S: Maintained
+F: board/egnite/ethernut5/
+F: include/configs/ethernut5.h
+F: configs/ethernut5_defconfig
diff --git a/board/egnite/ethernut5/Makefile b/board/egnite/ethernut5/Makefile
new file mode 100644
index 0000000..2513873
--- /dev/null
+++ b/board/egnite/ethernut5/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2010
+# egnite GmbH
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ethernut5.o
+obj-y += ethernut5_pwrman.o
diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c
new file mode 100644
index 0000000..b45213c
--- /dev/null
+++ b/board/egnite/ethernut5/ethernut5.c
@@ -0,0 +1,255 @@
+/*
+ * (C) Copyright 2011
+ * egnite GmbH <info@egnite.de>
+ *
+ * (C) Copyright 2010
+ * Ole Reinhardt <ole.reinhardt@thermotemp.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Ethernut 5 general board support
+ *
+ * Ethernut is an open source hardware and software project for
+ * embedded Ethernet devices. Hardware layouts and CAD files are
+ * freely available under BSD-like license.
+ *
+ * Ethernut 5 is the first member of the Ethernut board family
+ * with U-Boot and Linux support. This implementation is based
+ * on the original work done by Ole Reinhardt, but heavily modified
+ * to support additional features and the latest board revision 5.0F.
+ *
+ * Main board components are by default:
+ *
+ * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash
+ * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM
+ * 512 MBytes Micron MT29F4G08ABADA NAND Flash
+ * 4 MBytes Atmel AT45DB321D DataFlash
+ * SMSC LAN8710 Ethernet PHY
+ * Atmel ATmega168 MCU used for power management
+ * Linear Technology LTC4411 PoE controller
+ *
+ * U-Boot relevant board interfaces are:
+ *
+ * 100 Mbit Ethernet with IEEE 802.3af PoE
+ * RS-232 serial port
+ * USB host and device
+ * MMC/SD-Card slot
+ * Expansion port with I2C, SPI and more...
+ *
+ * Typically the U-Boot image is loaded from serial DataFlash into
+ * SDRAM by the samboot boot loader, which is located in internal
+ * NOR Flash and provides all essential initializations like CPU
+ * and peripheral clocks and, of course, the SDRAM configuration.
+ *
+ * For testing purposes it is also possibly to directly transfer
+ * the image into SDRAM via JTAG. A tested configuration exists
+ * for the Turtelizer 2 hardware dongle and the OpenOCD software.
+ * In this case the latter will do the basic hardware configuration
+ * via its reset-init script.
+ *
+ * For additional information visit the project home page at
+ * http://www.ethernut.de/
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <spi.h>
+#include <dataflash.h>
+#include <mmc.h>
+#include <atmel_mci.h>
+
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_spi.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include "ethernut5_pwrman.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}
+};
+
+/*
+ * In fact we have 7 partitions, but u-boot supports 5 only. This is
+ * no big deal, because the first partition is reserved for applications
+ * and the last one is used by Nut/OS. Both need not to be visible here.
+ */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ { 0x00021000, 0x00041FFF, FLAG_PROTECT_SET, 0, "setup" },
+ { 0x00042000, 0x000C5FFF, FLAG_PROTECT_SET, 0, "uboot" },
+ { 0x000C6000, 0x00359FFF, FLAG_PROTECT_SET, 0, "kernel" },
+ { 0x0035A000, 0x003DDFFF, FLAG_PROTECT_SET, 0, "nutos" },
+ { 0x003DE000, 0x003FEFFF, FLAG_PROTECT_CLEAR, 0, "env" }
+};
+
+/*
+ * This is called last during early initialization. Most of the basic
+ * hardware interfaces are up and running.
+ *
+ * The SDRAM hardware has been configured by the first stage boot loader.
+ * We only need to announce its size, using u-boot's memory check.
+ */
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void ethernut5_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Assign CS3 to NAND/SmartMedia Interface */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+#ifdef CONFIG_SYS_NAND_READY_PIN
+ /* Ready pin is optional. */
+ at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+#endif
+ gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+/*
+ * This is called first during late initialization.
+ */
+int board_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clocks for all PIOs */
+ writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOC),
+ &pmc->pcer);
+ /* Set adress of boot parameters. */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ /* Initialize UARTs and power management. */
+ at91_seriald_hw_init();
+ ethernut5_power_init();
+#ifdef CONFIG_CMD_NAND
+ ethernut5_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_MACB
+/*
+ * This is optionally called last during late initialization.
+ */
+int board_eth_init(bd_t *bis)
+{
+ const char *devname;
+ unsigned short mode;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable on-chip EMAC clock. */
+ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+ /* Need to reset PHY via power management. */
+ ethernut5_phy_reset();
+ /* Set peripheral pins. */
+ at91_macb_hw_init();
+ /* Basic EMAC initialization. */
+ if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
+ return -1;
+ /*
+ * Early board revisions have a pull-down at the PHY's MODE0
+ * strap pin, which forces the PHY into power down. Here we
+ * switch to all-capable mode.
+ */
+ devname = miiphy_get_current_dev();
+ if (miiphy_read(devname, 0, 18, &mode) == 0) {
+ /* Set mode[2:0] to 0b111. */
+ mode |= 0x00E0;
+ miiphy_write(devname, 0, 18, mode);
+ /* Soft reset overrides strap pins. */
+ miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
+ }
+ /* Sync environment with network devices, needed for nfsroot. */
+ return eth_init(gd->bd);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable MCI clock. */
+ writel(1 << ATMEL_ID_MCI, &pmc->pcer);
+ /* Initialize MCI hardware. */
+ at91_mci_hw_init();
+ /* Register the device. */
+ return atmel_mci_init((void *)ATMEL_BASE_MCI);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
+}
+#endif
+
+#ifdef CONFIG_ATMEL_SPI
+/*
+ * Note, that u-boot uses different code for SPI bus access. While
+ * memory routines use automatic chip select control, the serial
+ * flash support requires 'manual' GPIO control. Thus, we switch
+ * modes.
+ */
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* Enable NPCS0 in GPIO mode. This disables peripheral control. */
+ at91_set_pio_output(AT91_PIO_PORTA, 3, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* Disable NPCS0 in GPIO mode. */
+ at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
+ /* Switch back to peripheral chip select control. */
+ at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+#endif
diff --git a/board/egnite/ethernut5/ethernut5_pwrman.c b/board/egnite/ethernut5/ethernut5_pwrman.c
new file mode 100644
index 0000000..f17317e
--- /dev/null
+++ b/board/egnite/ethernut5/ethernut5_pwrman.c
@@ -0,0 +1,322 @@
+/*
+ * (C) Copyright 2011
+ * egnite GmbH <info@egnite.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Ethernut 5 power management support
+ *
+ * This board may be supplied via USB, IEEE 802.3af PoE or an
+ * auxiliary DC input. An on-board ATmega168 microcontroller,
+ * the so called power management controller or PMC, is used
+ * to select the supply source and to switch on and off certain
+ * energy consuming board components. This allows to reduce the
+ * total stand-by consumption to less than 70mW.
+ *
+ * The main CPU communicates with the PMC via I2C. When
+ * CONFIG_CMD_BSP is defined in the board configuration file,
+ * then the board specific command 'pwrman' becomes available,
+ * which allows to manually deal with the PMC.
+ *
+ * Two distinct registers are provided by the PMC for enabling
+ * and disabling specific features. This avoids the often seen
+ * read-modify-write cycle or shadow register requirement.
+ * Additional registers are available to query the board
+ * status and temperature, the auxiliary voltage and to control
+ * the green user LED that is integrated in the reset switch.
+ *
+ * Note, that the AVR firmware of the PMC is released under BSDL.
+ *
+ * For additional information visit the project home page at
+ * http://www.ethernut.de/
+ */
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+#include "ethernut5_pwrman.h"
+
+/* PMC firmware version */
+static int pwrman_major;
+static int pwrman_minor;
+
+/*
+ * Enable Ethernut 5 power management.
+ *
+ * This function must be called during board initialization.
+ * While we are using u-boot's I2C subsystem, it may be required
+ * to enable the serial port before calling this function,
+ * in particular when debugging is enabled.
+ *
+ * If board specific commands are not available, we will activate
+ * all board components.
+ */
+void ethernut5_power_init(void)
+{
+ pwrman_minor = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VERS);
+ pwrman_major = pwrman_minor >> 4;
+ pwrman_minor &= 15;
+
+#ifndef CONFIG_CMD_BSP
+ /* Do not modify anything, if we do not have a known version. */
+ if (pwrman_major == 2) {
+ /* Without board specific commands we enable all features. */
+ i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, ~PWRMAN_ETHRST);
+ i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
+ }
+#endif
+}
+
+/*
+ * Reset Ethernet PHY.
+ *
+ * This function allows the re-configure the PHY after
+ * changing its strap pins.
+ */
+void ethernut5_phy_reset(void)
+{
+ /* Do not modify anything, if we do not have a known version. */
+ if (pwrman_major != 2)
+ return;
+
+ /*
+ * Make sure that the Ethernet clock is enabled and the PHY reset
+ * is disabled for at least 100 us.
+ */
+ i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHCLK);
+ i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
+ udelay(100);
+
+ /*
+ * LAN8710 strap pins are
+ * PA14 => PHY MODE0
+ * PA15 => PHY MODE1
+ * PA17 => PHY MODE2 => 111b all capable
+ * PA18 => PHY ADDR0 => 0b
+ */
+ at91_set_pio_input(AT91_PIO_PORTA, 14, 1);
+ at91_set_pio_input(AT91_PIO_PORTA, 15, 1);
+ at91_set_pio_input(AT91_PIO_PORTA, 17, 1);
+ at91_set_pio_input(AT91_PIO_PORTA, 18, 0);
+
+ /* Activate PHY reset for 100 us. */
+ i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHRST);
+ udelay(100);
+ i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST);
+
+ at91_set_pio_input(AT91_PIO_PORTA, 14, 1);
+}
+
+/*
+ * Output the firmware version we got during initialization.
+ */
+void ethernut5_print_version(void)
+{
+ printf("%u.%u\n", pwrman_major, pwrman_minor);
+}
+
+/*
+ * All code below this point is optional and implements
+ * the 'pwrman' command.
+ */
+#ifdef CONFIG_CMD_BSP
+
+/* Human readable names of PMC features */
+char *pwrman_feat[8] = {
+ "board", "vbin", "vbout", "mmc",
+ "rs232", "ethclk", "ethrst", "wakeup"
+};
+
+/*
+ * Print all feature names, that have its related flags enabled.
+ */
+static void print_flagged_features(u8 flags)
+{
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ if (flags & (1 << i))
+ printf("%s ", pwrman_feat[i]);
+ }
+}
+
+/*
+ * Return flags of a given list of feature names.
+ *
+ * The function stops at the first unknown list entry and
+ * returns the number of detected names as a function result.
+ */
+static int feature_flags(char * const names[], int num, u8 *flags)
+{
+ int i, j;
+
+ *flags = 0;
+ for (i = 0; i < num; i++) {
+ for (j = 0; j < 8; j++) {
+ if (strcmp(pwrman_feat[j], names[i]) == 0) {
+ *flags |= 1 << j;
+ break;
+ }
+ }
+ if (j > 7)
+ break;
+ }
+ return i;
+}
+
+void ethernut5_print_power(void)
+{
+ u8 flags;
+ int i;
+
+ flags = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA);
+ for (i = 0; i < 2; i++) {
+ if (flags) {
+ print_flagged_features(flags);
+ printf("%s\n", i ? "off" : "on");
+ }
+ flags = ~flags;
+ }
+}
+
+void ethernut5_print_celsius(void)
+{
+ int val;
+
+ /* Read ADC value from LM50 and return Celsius degrees. */
+ val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_TEMP);
+ val *= 5000; /* 100mV/degree with 5V reference */
+ val += 128; /* 8 bit resolution */
+ val /= 256;
+ val -= 450; /* Celsius offset, still x10 */
+ /* Output full degrees. */
+ printf("%d\n", (val + 5) / 10);
+}
+
+void ethernut5_print_voltage(void)
+{
+ int val;
+
+ /* Read ADC value from divider and return voltage. */
+ val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VAUX);
+ /* Resistors are 100k and 12.1k */
+ val += 5;
+ val *= 180948;
+ val /= 100000;
+ val++;
+ /* Calculation was done in 0.1V units. */
+ printf("%d\n", (val + 5) / 10);
+}
+
+/*
+ * Process the board specific 'pwrman' command.
+ */
+int do_pwrman(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u8 val;
+ int i;
+
+ if (argc == 1) {
+ ethernut5_print_power();
+ } else if (argc == 2 && strcmp(argv[1], "reset") == 0) {
+ at91_set_pio_output(AT91_PIO_PORTB, 8, 1);
+ udelay(100);
+ at91_set_pio_output(AT91_PIO_PORTB, 8, 0);
+ udelay(100000);
+ } else if (argc == 2 && strcmp(argv[1], "temp") == 0) {
+ ethernut5_print_celsius();
+ } else if (argc == 2 && strcmp(argv[1], "vaux") == 0) {
+ ethernut5_print_voltage();
+ } else if (argc == 2 && strcmp(argv[1], "version") == 0) {
+ ethernut5_print_version();
+ } else if (strcmp(argv[1], "led") == 0) {
+ /* Control the green status LED. Blink frequency unit
+ ** is 0.1s, very roughly. */
+ if (argc == 2) {
+ /* No more arguments, output current settings. */
+ val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL);
+ printf("led %u %u\n", val >> 4, val & 15);
+ } else {
+ /* First argument specifies the on-time. */
+ val = (u8) simple_strtoul(argv[2], NULL, 0);
+ val <<= 4;
+ if (argc > 3) {
+ /* Second argument specifies the off-time. */
+ val |= (u8) (simple_strtoul(argv[3], NULL, 0)
+ & 15);
+ }
+ /* Update the LED control register. */
+ i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL, val);
+ }
+ } else {
+ /* We expect a list of features followed an optional status. */
+ argc--;
+ i = feature_flags(&argv[1], argc, &val);
+ if (argc == i) {
+ /* We got a list only, print status. */
+ val &= i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_STA);
+ if (val) {
+ if (i > 1)
+ print_flagged_features(val);
+ printf("active\n");
+ } else {
+ printf("inactive\n");
+ }
+ } else {
+ /* More arguments. */
+ if (i == 0) {
+ /* No given feature, use despensibles. */
+ val = PWRMAN_DISPENSIBLE;
+ }
+ if (strcmp(argv[i + 1], "on") == 0) {
+ /* Enable features. */
+ i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA,
+ val);
+ } else if (strcmp(argv[i + 1], "off") == 0) {
+ /* Disable features. */
+ i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS,
+ val);
+ } else {
+ printf("Bad parameter %s\n", argv[i + 1]);
+ return 1;
+ }
+ }
+ }
+ return 0;
+}
+
+U_BOOT_CMD(
+ pwrman, CONFIG_SYS_MAXARGS, 1, do_pwrman,
+ "power management",
+ "- print settings\n"
+ "pwrman feature ...\n"
+ " - print status\n"
+ "pwrman [feature ...] on|off\n"
+ " - enable/disable specified or all dispensible features\n"
+ "pwrman led [on-time [off-time]]\n"
+ " - print or set led blink timer\n"
+ "pwrman temp\n"
+ " - print board temperature (Celsius)\n"
+ "pwrman vaux\n"
+ " - print auxiliary input voltage\n"
+ "pwrman reset\n"
+ " - reset power management controller\n"
+ "pwrman version\n"
+ " - print firmware version\n"
+ "\n"
+ " features, (*)=dispensible:\n"
+ " board - 1.8V and 3.3V supply\n"
+ " vbin - supply via USB device connector\n"
+ " vbout - USB host connector supply(*)\n"
+ " mmc - MMC slot supply(*)\n"
+ " rs232 - RS232 driver\n"
+ " ethclk - Ethernet PHY clock(*)\n"
+ " ethrst - Ethernet PHY reset\n"
+ " wakeup - RTC alarm"
+);
+#endif /* CONFIG_CMD_BSP */
diff --git a/board/egnite/ethernut5/ethernut5_pwrman.h b/board/egnite/ethernut5/ethernut5_pwrman.h
new file mode 100644
index 0000000..22c9daa
--- /dev/null
+++ b/board/egnite/ethernut5/ethernut5_pwrman.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2011
+ * egnite GmbH <info@egnite.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Ethernut 5 power management support
+ *
+ * For additional information visit the project home page at
+ * http://www.ethernut.de/
+ */
+
+/* I2C address of the PMC */
+#define PWRMAN_I2C_ADDR 0x22
+
+/* PMC registers */
+#define PWRMAN_REG_VERS 0 /* Version register */
+#define PWRMAN_REG_STA 1 /* Feature status register */
+#define PWRMAN_REG_ENA 2 /* Feature enable register */
+#define PWRMAN_REG_DIS 3 /* Feature disable register */
+#define PWRMAN_REG_TEMP 4 /* Board temperature */
+#define PWRMAN_REG_VAUX 6 /* Auxiliary input voltage */
+#define PWRMAN_REG_LEDCTL 8 /* LED blinking timer. */
+
+/* Feature flags used in status, enable and disable registers */
+#define PWRMAN_BOARD 0x01 /* 1.8V and 3.3V supply */
+#define PWRMAN_VBIN 0x02 /* VBUS input at device connector */
+#define PWRMAN_VBOUT 0x04 /* VBUS output at host connector */
+#define PWRMAN_MMC 0x08 /* Memory card supply */
+#define PWRMAN_RS232 0x10 /* RS-232 driver shutdown */
+#define PWRMAN_ETHCLK 0x20 /* Ethernet clock enable */
+#define PWRMAN_ETHRST 0x40 /* Ethernet PHY reset */
+#define PWRMAN_WAKEUP 0x80 /* RTC wake-up */
+
+/* Features, which are not essential to keep u-boot alive */
+#define PWRMAN_DISPENSIBLE (PWRMAN_VBOUT | PWRMAN_MMC | PWRMAN_ETHCLK)
+
+/* Enable Ethernut 5 power management. */
+extern void ethernut5_power_init(void);
+
+/* Reset Ethernet PHY. */
+extern void ethernut5_phy_reset(void);
+
+extern void ethernut5_print_version(void);
+
+#ifdef CONFIG_CMD_BSP
+extern void ethernut5_print_power(void);
+extern void ethernut5_print_celsius(void);
+extern void ethernut5_print_voltage(void);
+#endif
diff --git a/board/eltec/elppc/Kconfig b/board/eltec/elppc/Kconfig
new file mode 100644
index 0000000..d4003e5
--- /dev/null
+++ b/board/eltec/elppc/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ELPPC
+
+config SYS_BOARD
+ default "elppc"
+
+config SYS_VENDOR
+ default "eltec"
+
+config SYS_CONFIG_NAME
+ default "ELPPC"
+
+endif
diff --git a/board/eltec/elppc/MAINTAINERS b/board/eltec/elppc/MAINTAINERS
new file mode 100644
index 0000000..e3b35f1
--- /dev/null
+++ b/board/eltec/elppc/MAINTAINERS
@@ -0,0 +1,6 @@
+ELPPC BOARD
+#M: -
+S: Maintained
+F: board/eltec/elppc/
+F: include/configs/ELPPC.h
+F: configs/ELPPC_defconfig
diff --git a/board/eltec/elppc/Makefile b/board/eltec/elppc/Makefile
new file mode 100644
index 0000000..791f2fb
--- /dev/null
+++ b/board/eltec/elppc/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = elppc.o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o
+obj-y += asm_init.o
diff --git a/board/eltec/elppc/asm_init.S b/board/eltec/elppc/asm_init.S
new file mode 100644
index 0000000..10fdfa2
--- /dev/null
+++ b/board/eltec/elppc/asm_init.S
@@ -0,0 +1,862 @@
+/*
+ * (C) Copyright 2001 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * ELTEC ELPPC RAM initialization
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/processor.h>
+#include <version.h>
+#include <mpc106.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+.globl board_asm_init
+board_asm_init:
+
+/*
+ * setup pointer to message block
+ */
+ mflr r13 /* save away link register */
+ bl get_lnk_reg /* r3=addr of next instruction */
+ subi r4, r3, 8 /* r4=board_asm_init addr */
+ addi r29, r4, (MessageBlock-board_asm_init)
+
+/*
+ * dcache_disable
+ */
+ mfspr r3, HID0
+ li r4, HID0_DCE
+ andc r3, r3, r4
+ mr r2, r3
+ ori r3, r3, HID0_DCI
+ sync
+ mtspr HID0, r3
+ mtspr HID0, r2
+ isync
+ sync
+/*
+ * icache_disable
+ */
+ mfspr r3, HID0
+ li r4, 0
+ ori r4, r4, HID0_ICE
+ andc r3, r3, r4
+ sync
+ mtspr HID0, r3
+/*
+ * invalidate caches
+ */
+ ori r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE)
+ or r4, r4, r3
+ isync
+ mtspr HID0, r4
+ andc r4, r4, r3
+ isync
+ mtspr HID0, r4
+ isync
+/*
+ * icache_enable
+ */
+ mfspr r3, HID0
+ ori r3, r3, (HID0_ICE | HID0_ICFI)
+ sync
+ mtspr HID0, r3
+
+
+/*
+ * setup memory controller
+ */
+ lis r1, MPC106_REG_ADDR@h
+ ori r1, r1, MPC106_REG_ADDR@l
+ lis r2, MPC106_REG_DATA@h
+ ori r2, r2, MPC106_REG_DATA@l
+
+ /* Configure PICR1 */
+ lis r3, MPC106_REG@h
+ ori r3, r3, PCI_PICR1
+ stwbrx r3, 0, r1
+ addis r3, r0, 0xFF14
+ ori r3, r3, 0x1CC8
+ eieio
+ stwbrx r3, 0, r2
+
+ /* Configure PICR2 */
+ lis r3, MPC106_REG@h
+ ori r3, r3, PCI_PICR2
+ stwbrx r3, 0, r1
+ addis r3, r0, 0x0000
+ ori r3, r3, 0x0000
+ eieio
+ stwbrx r3, 0, r2
+
+ /* Configure EUMBAR */
+ lis r3, MPC106_REG@h
+ ori r3, r3, 0x0078 /* offest of EUMBAR in PCI config space */
+ stwbrx r3, 0, r1
+ lis r3, MPC107_EUMB_ADDR@h
+ eieio
+ stwbrx r3, 0, r2
+
+ /* Configure Address Map B Option Reg */
+ lis r3, MPC106_REG@h
+ ori r3, r3, 0x00e0 /* offest of AMBOR in PCI config space */
+ stwbrx r3, 0, r1
+ lis r3, 0
+ eieio
+ stwbrx r3, 0, r2
+
+ /* Configure I2C Controller */
+ lis r14, MPC107_I2C_ADDR@h /* base of I2C controller */
+ ori r14, r14, MPC107_I2C_ADDR@l
+ lis r3, 0x2b10 /* I2C clock = 100MHz/1024 */
+ stw r3, 4(r14)
+ li r3, 0 /* clear arbitration */
+ eieio
+ stw r3, 12(r14)
+
+ /* Configure MCCR1 */
+ lis r3, MPC106_REG@h
+ ori r3, r3, MPC106_MCCR1
+ stwbrx r3, 0, r1
+ addis r3, r0, 0x0660 /* don't set MEMGO now ! */
+ ori r3, r3, 0x0000
+ eieio
+ stwbrx r3, 0, r2
+
+ /* Configure MCCR2 */
+ lis r3, MPC106_REG@h
+ ori r3, r3, MPC106_MCCR2
+ stwbrx r3, 0, r1
+ addis r3, r0, 0x0400
+ ori r3, r3, 0x1800
+ eieio
+ stwbrx r3, 0, r2
+
+
+ /* Configure MCCR3 */
+ lis r3, MPC106_REG@h
+ ori r3, r3, MPC106_MCCR3
+ stwbrx r3, 0, r1
+ addis r3, r0, 0x0230
+ ori r3, r3, 0x0000
+ eieio
+ stwbrx r3, 0, r2
+
+ /* Configure MCCR4 */
+ lis r3, MPC106_REG@h
+ ori r3, r3, MPC106_MCCR4
+ stwbrx r3, 0, r1
+ addis r3, r0, 0x2532
+ ori r3, r3, 0x2220
+ eieio
+ stwbrx r3, 0, r2
+
+/*
+ * configure memory interface (MICRs)
+ */
+ addis r3, r0, 0x8000 /* ADDR_80 */
+ ori r3, r3, 0x0080 /* SMEMADD1 */
+ stwbrx r3, 0, r1
+ addis r3, r0, 0xFFFF
+ ori r3, r3, 0x4000
+ eieio
+ stwbrx r3, 0, r2
+
+ addis r3, r0, 0x8000 /* ADDR_84 */
+ ori r3, r3, 0x0084 /* SMEMADD2 */
+ stwbrx r3, 0, r1
+ addis r3, r0, 0xFFFF
+ ori r3, r3, 0xFFFF
+ eieio
+ stwbrx r3, 0, r2
+
+ addis r3, r0, 0x8000 /* ADDR_88 */
+ ori r3, r3, 0x0088 /* EXTSMEM1 */
+ stwbrx r3, 0, r1
+ addis r3, r0, 0x0303
+ ori r3, r3, 0x0000
+ eieio
+ stwbrx r3, 0, r2
+
+ addis r3, r0, 0x8000 /* ADDR_8C */
+ ori r3, r3, 0x008c /* EXTSMEM2 */
+ stwbrx r3, 0, r1
+ addis r3, r0, 0x0303
+ ori r3, r3, 0x0303
+ eieio
+ stwbrx r3, 0, r2
+
+ addis r3, r0, 0x8000 /* ADDR_90 */
+ ori r3, r3, 0x0090 /* EMEMADD1 */
+ stwbrx r3, 0, r1
+ addis r3, r0, 0xFFFF
+ ori r3, r3, 0x7F3F
+ eieio
+ stwbrx r3, 0, r2
+
+ addis r3, r0, 0x8000 /* ADDR_94 */
+ ori r3, r3, 0x0094 /* EMEMADD2 */
+ stwbrx r3, 0, r1
+ addis r3, r0, 0xFFFF
+ ori r3, r3, 0xFFFF
+ eieio
+ stwbrx r3, 0, r2
+
+ addis r3, r0, 0x8000 /* ADDR_98 */
+ ori r3, r3, 0x0098 /* EXTEMEM1 */
+ stwbrx r3, 0, r1
+ addis r3, r0, 0x0303
+ ori r3, r3, 0x0000
+ eieio
+ stwbrx r3, 0, r2
+
+ addis r3, r0, 0x8000 /* ADDR_9C */
+ ori r3, r3, 0x009c /* EXTEMEM2 */
+ stwbrx r3, 0, r1
+ addis r3, r0, 0x0303
+ ori r3, r3, 0x0303
+ eieio
+ stwbrx r3, 0, r2
+
+ addis r3, r0, 0x8000 /* ADDR_A0 */
+ ori r3, r3, 0x00a0 /* MEMBNKEN */
+ stwbrx r3, 0, r1
+ addis r3, r0, 0x0000
+ ori r3, r3, 0x0003
+ eieio
+ stwbrx r3, 0, r2
+
+/*
+ * must wait at least 100us after HRESET to issue a MEMGO
+ */
+ lis r0, 1
+ mtctr r0
+memStartWait:
+ bdnz memStartWait
+
+/*
+ * enable RAM Operations through MCCR1 (MEMGO)
+ */
+ lis r3, 0x8000
+ ori r3, r3, 0x00f0
+ stwbrx r3, r0, r1
+ sync
+ lwbrx r3, 0, r2
+ lis r0, 0x0008
+ or r3, r0, r3
+ stwbrx r3, 0, r2
+ sync
+
+/*
+ * set LEDs first time
+ */
+ li r3, 0x1
+ lis r30, CONFIG_SYS_USR_LED_BASE@h
+ stb r3, 2(r30)
+ sync
+
+/*
+ * init COM1 for polled output
+ */
+ lis r8, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+ ori r8, r8, CONFIG_SYS_NS16550_COM1@l
+ li r9, 0x00
+ stb r9, 1(r8) /* int disabled */
+ eieio
+ li r9, 0x00
+ stb r9, 4(r8) /* modem ctrl */
+ eieio
+ li r9, 0x80
+ stb r9, 3(r8) /* link ctrl */
+ eieio
+ li r9, (CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE)
+ stb r9, 0(r8) /* baud rate (LSB)*/
+ eieio
+ li r9, ((CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8)
+ stb r9, 1(r8) /* baud rate (MSB) */
+ eieio
+ li r9, 0x07
+ stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */
+ eieio
+ li r9, 0x0b
+ stb r9, 4(r8) /* enable the receiver and transmitter (modem ctrl) */
+ eieio
+waitEmpty:
+ lbz r9, 5(r8) /* transmit empty */
+ andi. r9, r9, 0x40
+ beq waitEmpty
+ li r9, 0x47
+ stb r9, 3(r8) /* send break, 8 data bits, 2 stop bit, no parity */
+ eieio
+
+ lis r0, 0x0001
+ mtctr r0
+waitCOM1:
+ lwz r0, 5(r8) /* load from port for delay */
+ bdnz waitCOM1
+
+waitEmpty1:
+ lbz r9, 5(r8) /* transmit empty */
+ andi. r9, r9, 0x40
+ beq waitEmpty1
+ li r9, 0x07
+ stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */
+ eieio
+
+/*
+ * intro message from message block
+ */
+ addi r3, r29, (MnewLine-MessageBlock)
+ bl Printf
+ addi r3, r29, (MinitLogo-MessageBlock)
+ bl Printf
+
+/*
+ * memory cofiguration using SPD information stored on the SODIMMs
+ */
+ addi r3, r29, (Mspd01-MessageBlock)
+ bl Printf
+
+ li r17, 0
+
+ li r3, 0x0002 /* get RAM type from spd for bank0/1 */
+ bl spdRead
+
+ cmpi 0, 0, r3, -1 /* error ? */
+ bne noSpdError
+
+ addi r3, r29, (Mfail-MessageBlock)
+ bl Printf
+
+ li r6, 0xe /* error codes in r6 and r7 */
+ li r7, 0x0
+ b toggleError /* fail - loop forever */
+
+noSpdError:
+ mr r15, r3 /* save r3 */
+
+ addi r3, r29, (Mok-MessageBlock)
+ bl Printf
+
+ cmpli 0, 0, r15, 0x0004 /* SDRAM ? */
+ beq isSDRAM
+
+ addi r3, r29, (MramTyp-MessageBlock)
+ bl Printf
+
+ li r6, 0xd /* error codes in r6 and r7 */
+ li r7, 0x0
+ b toggleError /* fail - loop forever */
+
+isSDRAM:
+ li r3, 0x0012 /* get supported CAS latencies from byte 18 */
+ bl spdRead
+ mr r15, r3
+ li r3, 0x09
+ andi. r0, r15, 0x04
+ bne maxCLis3
+ li r3, 0x17
+maxCLis3:
+ andi. r0, r15, 0x02
+ bne CL2
+
+ addi r3, r29, (MramTyp-MessageBlock)
+ bl Printf
+
+ li r6, 0xc /* error codes in r6 and r7 */
+ li r7, 0x0
+ b toggleError /* fail - loop forever */
+CL2:
+ bl spdRead
+ cmpli 0, 0, r3, 0xa1 /* cycle time must be 10ns max. */
+ blt speedOk
+
+ addi r3, r29, (MramTyp-MessageBlock)
+ bl Printf
+
+ li r6, 0xb /* error codes in r6 and r7 */
+ li r7, 0x0
+ b toggleError /* fail - loop forever */
+speedOk:
+ lis r20, 0x06e8 /* preset MCR1 value */
+
+ li r3, 0x0011 /* get number of internal banks from spd for bank0/1 */
+ bl spdRead
+
+ cmpli 0, 0, r3, 0x02
+ beq SD_2B
+ cmpli 0, 0, r3, 0x04
+ beq SD_4B
+memConfErr:
+ addi r3, r29, (MramConfErr-MessageBlock)
+ bl Printf
+
+ li r6, 0xa /* error codes in r6 and r7 */
+ li r7, 0x0
+ b toggleError /* fail - loop forever */
+
+SD_2B:
+ li r3, 0x0003 /* get number of row bits from spd for bank0/1 */
+ bl spdRead
+ cmpli 0, 0, r3, 0x0b
+ beq row11x2
+ cmpli 0, 0, r3, 0x0c
+ beq row12x2or13x2
+ cmpli 0, 0, r3, 0x0d
+ beq row12x2or13x2
+ b memConfErr
+SD_4B:
+ li r3, 0x0003 /* get number of row bits from spd for bank0/1 */
+ bl spdRead
+ cmpli 0, 0, r3, 0x0b
+ beq row11x4or12x4
+ cmpli 0, 0, r3, 0x0c
+ beq row11x4or12x4
+ cmpli 0, 0, r3, 0x0d
+ beq row13x4
+ b memConfErr
+row12x2or13x2:
+ ori r20, r20, 0x05
+ b row11x4or12x4
+row13x4:
+ ori r20, r20, 0x0a
+ b row11x4or12x4
+row11x2:
+ ori r20, r20, 0x0f
+row11x4or12x4:
+ /* get the size of bank 0-1 */
+
+ li r3, 0x001f /* get bank size from spd for bank0/1 */
+ bl spdRead
+
+ rlwinm r16, r3, 2, 24, 29 /* calculate size in MByte (128 MB max.) */
+
+ li r3, 0x0005 /* get number of banks from spd for bank0/1 */
+ bl spdRead
+
+ cmpi 0, 0, r3, 2 /* 2 banks ? */
+ bne SDRAMnobank1
+
+ mr r17, r16
+
+SDRAMnobank1:
+ li r3, 0x000c /* get refresh from spd for bank0/1 */
+ bl spdRead
+ andi. r3, r3, 0x007f /* mask selfrefresh bit */
+ li r4, 0x1800 /* refesh cycle 1536 clocks left shifted 2 */
+ cmpli 0, 0, r3, 0x0000 /* 15.6 us ? */
+ beq writeRefresh
+
+ li r4, 0x0c00 /* refesh cycle 768 clocks left shifted 2 */
+ cmpli 0, 0, r3, 0x0002 /* 7.8 us ? */
+ beq writeRefresh
+
+ li r4, 0x3000 /* refesh cycle 3072 clocks left shifted 2 */
+ cmpli 0, 0, r3, 0x0003 /* 31.3 us ? */
+ beq writeRefresh
+
+ li r4, 0x6000 /* refesh cycle 6144 clocks left shifted 2 */
+ cmpli 0, 0, r3, 0x0004 /* 62.5 us ? */
+ beq writeRefresh
+
+ li r4, 0
+ ori r4, r4, 0xc000 /* refesh cycle 8224 clocks left shifted 2 */
+ cmpli 0, 0, r3, 0x0005 /* 125 us ? */
+ beq writeRefresh
+
+ b memConfErr
+
+writeRefresh:
+ lis r21, 0x0400 /* preset MCCR2 value */
+ or r21, r21, r4
+
+ /* Overwrite MCCR1 */
+ lis r3, MPC106_REG@h
+ ori r3, r3, MPC106_MCCR1
+ stwbrx r3, 0, r1
+ eieio
+ stwbrx r20, 0, r2
+
+ /* Overwrite MCCR2 */
+ lis r3, MPC106_REG@h
+ ori r3, r3, MPC106_MCCR2
+ stwbrx r3, 0, r1
+ eieio
+ stwbrx r21, 0, r2
+
+ /* set the memory boundary registers for bank 0-3 */
+ li r20, 0
+ lis r23, 0x0303
+ lis r24, 0x0303
+ subi r21, r16, 1 /* calculate end address bank0 */
+ li r22, 1
+
+ cmpi 0, 0, r17, 0 /* bank1 present ? */
+ beq nobank1
+
+ andi. r3, r16, 0x00ff /* calculate start address of bank1 */
+ andi. r4, r16, 0x0300
+ rlwinm r3, r3, 8, 16, 23
+ or r20, r20, r3
+ or r23, r23, r4
+
+ add r16, r16, r17 /* add to total memory size */
+
+ subi r3, r16, 1 /* calculate end address of bank1 */
+ andi. r4, r3, 0x0300
+ andi. r3, r3, 0x00ff
+ rlwinm r3, r3, 8, 16, 23
+ or r21, r21, r3
+ or r24, r24, r4
+
+ ori r22, r22, 2 /* enable bank1 */
+ b bankOk
+nobank1:
+ ori r23, r23, 0x0300 /* set bank1 start to unused area */
+ ori r24, r24, 0x0300 /* set bank1 end to unused area */
+bankOk:
+ addi r3, r29, (Mactivate-MessageBlock)
+ bl Printf
+ mr r3, r16
+ bl OutDec
+ addi r3, r29, (Mact0123e-MessageBlock)
+ bl Printf
+
+/*
+ * overwrite MSAR1, MEAR1, EMSAR1, and EMEAR1
+ */
+ addis r3, r0, 0x8000 /* ADDR_80 */
+ ori r3, r3, 0x0080 /* MSAR1 */
+ stwbrx r3, 0, r1
+ eieio
+ stwbrx r20, 0, r2
+
+ addis r3, r0, 0x8000 /* ADDR_88 */
+ ori r3, r3, 0x0088 /* EMSAR1 */
+ stwbrx r3, 0, r1
+ eieio
+ stwbrx r23, 0, r2
+
+ addis r3, r0, 0x8000 /* ADDR_90 */
+ ori r3, r3, 0x0090 /* MEAR1 */
+ stwbrx r3, 0, r1
+ eieio
+ stwbrx r21, 0, r2
+
+ addis r3, r0, 0x8000 /* ADDR_98 */
+ ori r3, r3, 0x0098 /* EMEAR1 */
+ stwbrx r3, 0, r1
+ eieio
+ stwbrx r24, 0, r2
+
+ addis r3, r0, 0x8000 /* ADDR_A0 */
+ ori r3, r3, 0x00a0 /* MBER */
+ stwbrx r3, 0, r1
+ eieio
+ stwbrx r22, 0, r2
+
+/*
+ * delay to let SDRAM go through several initialization/refresh cycles
+ */
+ lis r3, 3
+ mtctr r3
+memStartWait_1:
+ bdnz memStartWait_1
+ eieio
+
+/*
+ * set LEDs end
+ */
+ li r3, 0xf
+ lis r30, CONFIG_SYS_USR_LED_BASE@h
+ stb r3, 2(r30)
+ sync
+
+ mtlr r13
+ blr /* EXIT board_asm_init ... */
+
+/*----------------------------------------------------------------------------*/
+/*
+ * print a message to COM1 in polling mode (r10=COM1 port, r3=(char*)string)
+ */
+
+Printf:
+ lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+ ori r10, r10, CONFIG_SYS_NS16550_COM1@l
+WaitChr:
+ lbz r0, 5(r10) /* read link status */
+ eieio
+ andi. r0, r0, 0x40 /* mask transmitter empty bit */
+ beq cr0, WaitChr /* wait till empty */
+ lbzx r0, r0, r3 /* get char */
+ stb r0, 0(r10) /* write to transmit reg */
+ eieio
+ addi r3, r3, 1 /* next char */
+ lbzx r0, r0, r3 /* get char */
+ cmpwi cr1, r0, 0 /* end of string ? */
+ bne cr1, WaitChr
+ blr
+
+/*
+ * print a char to COM1 in polling mode (r10=COM1 port, r3=char)
+ */
+OutChr:
+ lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+ ori r10, r10, CONFIG_SYS_NS16550_COM1@l
+OutChr1:
+ lbz r0, 5(r10) /* read link status */
+ eieio
+ andi. r0, r0, 0x40 /* mask transmitter empty bit */
+ beq cr0, OutChr1 /* wait till empty */
+ stb r3, 0(r10) /* write to transmit reg */
+ eieio
+ blr
+
+/*
+ * print 8/4/2 digits hex value to COM1 in polling mode (r10=COM1 port, r3=val)
+ */
+OutHex2:
+ li r9, 4 /* shift reg for 2 digits */
+ b OHstart
+OutHex4:
+ li r9, 12 /* shift reg for 4 digits */
+ b OHstart
+OutHex:
+ li r9, 28 /* shift reg for 8 digits */
+OHstart:
+ lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+ ori r10, r10, CONFIG_SYS_NS16550_COM1@l
+OutDig:
+ lbz r0, 0(r29) /* slow down dummy read */
+ lbz r0, 5(r10) /* read link status */
+ eieio
+ andi. r0, r0, 0x40 /* mask transmitter empty bit */
+ beq cr0, OutDig
+ sraw r0, r3, r9
+ clrlwi r0, r0, 28
+ cmpwi cr1, r0, 9
+ ble cr1, digIsNum
+ addic r0, r0, 55
+ b nextDig
+digIsNum:
+ addic r0, r0, 48
+nextDig:
+ stb r0, 0(r10) /* write to transmit reg */
+ eieio
+ addic. r9, r9, -4
+ bge OutDig
+ blr
+
+/*
+ * print 3 digits hdec value to COM1 in polling mode
+ * (r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch)
+ */
+OutDec:
+ li r6, 10
+ divwu r0, r3, r6 /* r0 = r3 / 10, r9 = r3 mod 10 */
+ mullw r10, r0, r6
+ subf r9, r10, r3
+ mr r3, r0
+ divwu r0, r3, r6 /* r0 = r3 / 10, r8 = r3 mod 10 */
+ mullw r10, r0, r6
+ subf r8, r10, r3
+ mr r3, r0
+ divwu r0, r3, r6 /* r0 = r3 / 10, r7 = r3 mod 10 */
+ mullw r10, r0, r6
+ subf r7, r10, r3
+ lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+ ori r10, r10, CONFIG_SYS_NS16550_COM1@l
+ or. r7, r7, r7
+ bne noblank1
+ li r3, 0x20
+ b OutDec4
+noblank1:
+ addi r3, r7, 48 /* convert to ASCII */
+OutDec4:
+ lbz r0, 0(r29) /* slow down dummy read */
+ lbz r0, 5(r10) /* read link status */
+ eieio
+ andi. r0, r0, 0x40 /* mask transmitter empty bit */
+ beq cr0, OutDec4
+ stb r3, 0(r10) /* x00 to transmit */
+ eieio
+ or. r7, r7, r8
+ beq OutDec5
+ addi r3, r8, 48 /* convert to ASCII */
+OutDec5:
+ lbz r0, 0(r29) /* slow down dummy read */
+ lbz r0, 5(r10) /* read link status */
+ eieio
+ andi. r0, r0, 0x40 /* mask transmitter empty bit */
+ beq cr0, OutDec5
+ stb r3, 0(r10) /* x0 to transmit */
+ eieio
+ addi r3, r9, 48 /* convert to ASCII */
+OutDec6:
+ lbz r0, 0(r29) /* slow down dummy read */
+ lbz r0, 5(r10) /* read link status */
+ eieio
+ andi. r0, r0, 0x40 /* mask transmitter empty bit */
+ beq cr0, OutDec6
+ stb r3, 0(r10) /* x to transmit */
+ eieio
+ blr
+
+/*
+ * hang endless loop
+ */
+toggleError: /* fail type in r6, r7=0xff, toggle LEDs */
+ stb r7, 2(r30) /* r7 to LED */
+ li r0, 0
+ lis r9, 127
+ ori r9, r9, 65535
+toggleError1:
+ addic r0, r0, 1
+ cmpw cr1, r0, r9
+ ble cr1, toggleError1
+ stb r6, 2(r30) /* r6 to LED */
+ li r0, 0
+ lis r9, 127
+ ori r9, r9, 65535
+toggleError2:
+ addic r0, r0, 1
+ cmpw cr1, r0, r9
+ ble cr1, toggleError2
+ b toggleError
+
+/*
+ * routines to read from ram spd
+ */
+spdWaitIdle:
+ lis r0, 0x1 /* timeout for about 100us */
+ mtctr r0
+iSpd:
+ lbz r10, 12(r14)
+ andi. r10, r10, 0x20 /* mask and test MBB */
+ beq idle
+ bdnz iSpd
+ orc. r10, r0, r0 /* return -1 to caller */
+idle:
+ bclr 20, 0 /* return to caller */
+
+waitSpd:
+ lis r0, 0x10 /* timeout for about 1.5ms */
+ mtctr r0
+wSpd:
+ lbz r10, 12(r14)
+ andi. r10, r10, 0x82
+ cmpli 0, 0, r10, 0x82 /* test MCF and MIF set */
+ beq wend
+ bdnz wSpd
+ orc. r10, r0, r0 /* return -1 to caller */
+ bclr 20, 0 /* return to caller */
+
+wend:
+ li r10, 0
+ stb r10, 12(r14) /* clear status */
+ bclr 20, 0 /* return to caller */
+
+/*
+ * spdread
+ * in: r3 adr to read
+ * out: r3 val or -1 for error
+ * uses r10, assumes that r14 points to I2C controller
+ */
+spdRead:
+ mfspr r25, 8 /* save link register */
+
+ bl spdWaitIdle
+ bne spdErr
+
+ li r10, 0x80 /* start with MEN */
+ stb r10, 8(r14)
+ eieio
+
+ li r10, 0xb0 /* start as master */
+ stb r10, 8(r14)
+ eieio
+
+ li r10, 0xa0 /* write device 0xA0 */
+ stb r10, 16(r14)
+ eieio
+ bl waitSpd
+ bne spdErr
+
+ lbz r10, 12(r14) /* test ACK */
+ andi. r10, r10, 0x01
+ bne gotNoAck
+
+ stb r3, 16(r14) /* data address */
+ eieio
+ bl waitSpd
+ bne spdErr
+
+
+ li r10, 0xb4 /* switch to read - restart */
+ stb r10, 8(r14)
+ eieio
+
+ li r10, 0xa1 /* read device 0xA0 */
+ stb r10, 16(r14)
+ eieio
+ bl waitSpd
+ bne spdErr
+
+ li r10, 0xa8 /* no ACK */
+ stb r10, 8(r14)
+ eieio
+
+ lbz r10, 16(r14) /* trigger read next byte */
+ eieio
+ bl waitSpd
+ bne spdErr
+
+ li r10, 0x88 /* generate STOP condition */
+ stb r10, 8(r14)
+ eieio
+
+ lbz r3, 16(r14) /* return read byte */
+
+ mtspr 8, r25 /* restore link register */
+ blr
+
+gotNoAck:
+ li r10, 0x80 /* generate STOP condition */
+ stb r10, 8(r14)
+ eieio
+spdErr:
+ orc r3, r0, r0 /* return -1 */
+ mtspr 8, r25 /* restore link register */
+ blr
+
+get_lnk_reg:
+ mflr r3 /* return link reg */
+ blr
+
+MessageBlock:
+
+MinitLogo:
+ .ascii "\015\012*** ELTEC Elektronik, Mainz ***\015\012"
+ .ascii "\015\012Initialising RAM\015\012\000"
+Mspd01:
+ .ascii " Reading SPD of SODIMM ...... \000"
+MramTyp:
+ .ascii "\015\012\SDRAM with CL=2 at 100 MHz required!\015\012\000"
+MramConfErr:
+ .ascii "\015\012\Unsupported SODIMM Configuration!\015\012\000"
+Mactivate:
+ .ascii " Activating \000"
+Mact0123e:
+ .ascii " MByte.\015\012\000"
+Mok:
+ .ascii "OK \015\012\000"
+Mfail:
+ .ascii "FAILED \015\012\000"
+MnewLine:
+ .ascii "\015\012\000"
+ .align 4
diff --git a/board/eltec/elppc/eepro100_srom.c b/board/eltec/elppc/eepro100_srom.c
new file mode 100644
index 0000000..05ba9c4
--- /dev/null
+++ b/board/eltec/elppc/eepro100_srom.c
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Local network srom writing for first time run
+ */
+
+/* includes */
+#include <common.h>
+#include <pci.h>
+#include <net.h>
+#include "srom.h"
+
+extern int eepro100_write_eeprom (struct eth_device *dev,
+ int location, int addr_len,
+ unsigned short data);
+
+/*----------------------------------------------------------------------------*/
+
+unsigned short eepro100_srom_checksum (unsigned short *sromdata)
+{
+ unsigned short sum = 0;
+ unsigned int i;
+
+ for (i = 0; i < (EE_SIZE - 1); i++) {
+ sum += sromdata[i];
+ }
+ return (EE_CHECKSUM - sum);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int eepro100_srom_store (unsigned short *source)
+{
+ int count;
+ struct eth_device onboard_dev;
+
+ /* get onboard network iobase */
+ pci_read_config_dword (PCI_BDF (0, 0x10, 0), PCI_BASE_ADDRESS_0,
+ (unsigned int *) &onboard_dev.iobase);
+ onboard_dev.iobase &= ~0xf;
+
+ source[63] = eepro100_srom_checksum (source);
+
+ for (count = 0; count < EE_SIZE; count++) {
+ if (eepro100_write_eeprom ((struct eth_device *) &onboard_dev,
+ count, EE_ADDR_BITS,
+ SROM_SHORT (source)) == -1) {
+ return -1;
+ }
+ source++;
+ }
+ return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+
+#ifdef EEPRO100_SROM_CHECK
+
+extern int read_eeprom (struct eth_device *dev, int location, int addr_len);
+
+void eepro100_srom_load (unsigned short *destination)
+{
+ int count;
+ struct eth_device onboard_dev;
+
+#ifdef DEBUG
+ int lr = 0;
+
+ printf ("eepro100_srom_download:\n");
+#endif
+
+ /* get onboard network iobase */
+ pci_read_config_dword (PCI_BDF (0, 0x10, 0), PCI_BASE_ADDRESS_0,
+ &onboard_dev.iobase);
+ onboard_dev.iobase &= ~0xf;
+
+ memset (destination, 0x65, 128);
+
+ for (count = 0; count < 0x40; count++) {
+ *destination++ = read_eeprom ((struct eth_device *) &onboard_dev,
+ count, EE_ADDR_BITS);
+#ifdef DEBUG
+ printf ("%04x ", *(destination - 1));
+ if (lr++ == 7) {
+ printf ("\n");
+ lr = 0;
+ }
+#endif
+ }
+}
+#endif /* EEPRO100_SROM_CHECK */
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c
new file mode 100644
index 0000000..ac814b8
--- /dev/null
+++ b/board/eltec/elppc/elppc.c
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc106.h>
+#include <video_fb.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+int checkboard (void)
+{
+ puts ("Board: ELTEC PowerPC\n");
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int checkflash (void)
+{
+ /* TODO */
+ printf ("Test not implemented !\n");
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static unsigned int mpc106_read_cfg_dword (unsigned int reg)
+{
+ unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
+
+ out32r (MPC106_REG_ADDR, reg_addr);
+
+ return (in32r (MPC106_REG_DATA | (reg & 0x3)));
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int dram_size (int board_type)
+{
+ /*
+ * No actual initialisation to do - done when setting up
+ * PICRs MCCRs ME/SARs etc in asm_init.S.
+ */
+
+ register unsigned long i, msar1, mear1, memSize;
+
+#if defined(CONFIG_SYS_MEMTEST)
+ register unsigned long reg;
+
+ printf ("Testing DRAM\n");
+
+ /* write each mem addr with it's address */
+ for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4)
+ *reg = reg;
+
+ for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) {
+ if (*reg != reg)
+ return -1;
+ }
+#endif
+
+ /*
+ * Since MPC107 memory controller chip has already been set to
+ * control all memory, just read and interpret its memory boundery register.
+ */
+ memSize = 0;
+ msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
+ mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
+ i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
+
+ do {
+ if (i & 0x01) /* is bank enabled ? */
+ memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
+ msar1 >>= 8;
+ mear1 >>= 8;
+ i >>= 1;
+ } while (i);
+
+ return (memSize * 0x100000);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+ return dram_size (board_type);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * The BAB 911 can be reset by writing bit 0 of the Processor Initialization
+ * Register PI in the MPC 107 (at offset 0x41090 of the Embedded Utilities
+ * Memory Block).
+ */
+int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ out8 (MPC107_EUMB_PI, 1);
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_WATCHDOG)
+
+/*
+ * Since the 7xx CPUs don't have an internal watchdog, this function is
+ * board specific.
+ */
+void watchdog_reset (void)
+{
+}
+#endif /* CONFIG_WATCHDOG */
+
+/* ------------------------------------------------------------------------- */
+
+void after_reloc (ulong dest_addr)
+{
+ /*
+ * Jump to the main U-Boot board init code
+ */
+ board_init_r ((gd_t *)gd, dest_addr);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+extern GraphicDevice smi;
+
+void video_get_info_str (int line_number, char *info)
+{
+ /* init video info strings for graphic console */
+ switch (line_number) {
+ case 1:
+ sprintf (info, " MPC7xx V%d.%d at %d / %d MHz",
+ (get_pvr () >> 8) & 0xFF, get_pvr () & 0xFF, 400, 100);
+ return;
+ case 2:
+ sprintf (info, " ELTEC ELPPC with %ld MB DRAM and %ld MB FLASH",
+ dram_size (0) / 0x100000, flash_init () / 0x100000);
+ return;
+ case 3:
+ sprintf (info, " %s", smi.modeIdent);
+ return;
+ }
+
+ /* no more info lines */
+ *info = 0;
+ return;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
diff --git a/board/eltec/elppc/flash.c b/board/eltec/elppc/flash.c
new file mode 100644
index 0000000..2b41685
--- /dev/null
+++ b/board/eltec/elppc/flash.c
@@ -0,0 +1,496 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC).
+ * fixed monitor protection part
+ *
+ * 09-18-2001 Andreas Heppel: Reduced the code in here to the usage
+ * of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use
+ * any other.
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*flash command address offsets*/
+
+#define ADDR0 (0x555)
+#define ADDR1 (0x2AA)
+#define ADDR3 (0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*----------------------------------------------------------------------------*/
+
+unsigned long flash_init (void)
+{
+ unsigned long size1, size2;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+ {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* initialise 1st flash */
+ size1 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN)
+ {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size1, size1<<20);
+ }
+
+ /* initialise 2nd flash */
+ size2 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+ if (flash_info[1].flash_id == FLASH_UNKNOWN)
+ {
+ printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+ size2, size2<<20);
+ }
+
+ /* monitor protection ON by default */
+ if (size1 == 512*1024)
+ {
+ (void)flash_protect(FLAG_PROTECT_SET,
+ FLASH_BASE0_PRELIM,
+ FLASH_BASE0_PRELIM+monitor_flash_len-1,
+ &flash_info[0]);
+ }
+ if (size2 == 512*1024)
+ {
+ (void)flash_protect(FLAG_PROTECT_SET,
+ FLASH_BASE1_PRELIM,
+ FLASH_BASE1_PRELIM+monitor_flash_len-1,
+ &flash_info[1]);
+ }
+ if (size2 == 4*1024*1024)
+ {
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
+ &flash_info[1]);
+ }
+
+ return (size1 + size2);
+}
+
+/*----------------------------------------------------------------------------*/
+
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ flash_init();
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf ("AMD ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case AMD_ID_F040B:
+ printf ("AM29F040B (4 Mbit)\n");
+ break;
+ case AMD_ID_F016D:
+ printf ("AM29F016D (16 Mbit)\n");
+ break;
+ case AMD_ID_F032B:
+ printf ("AM29F032B (32 Mbit)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ if (info->size >= (1 << 20)) {
+ printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+ } else {
+ printf (" Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count);
+ }
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count-1))
+ size = info->start[i+1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k=0; k<size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf ("\n ");
+
+ printf (" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " ");
+ }
+ printf ("\n");
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ ulong vendor, devid;
+ ulong base = (ulong)addr;
+ volatile unsigned char *caddr = (unsigned char *)addr;
+
+#ifdef DEBUG
+ printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr);
+#endif
+
+ /* Write auto select command: read Manufacturer ID */
+ caddr[0] = 0xF0; /* reset bank */
+ udelay(10);
+
+ eieio();
+ caddr[0x555] = 0xAA;
+ udelay(10);
+ caddr[0x2AA] = 0x55;
+ udelay(10);
+ caddr[0x555] = 0x90;
+
+ udelay(10);
+
+ vendor = caddr[0];
+ devid = caddr[1];
+
+#ifdef DEBUG
+ printf("Manufacturer: 0x%lx\n", vendor);
+#endif
+
+ vendor &= 0xff;
+ devid &= 0xff;
+
+ /* We accept only two AMD types */
+ switch (vendor) {
+ case (FLASH_WORD_SIZE)AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ switch (devid) {
+ case (FLASH_WORD_SIZE)AMD_ID_F040B:
+ info->flash_id |= AMD_ID_F040B;
+ info->sector_count = 8;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (FLASH_WORD_SIZE)AMD_ID_F016D:
+ info->flash_id |= AMD_ID_F016D;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (FLASH_WORD_SIZE)AMD_ID_F032B:
+ info->flash_id |= AMD_ID_F032B;
+ info->sector_count = 64;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+#ifdef DEBUG
+ printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size);
+#endif
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* sector base address */
+ info->start[i] = base + i * (info->size / info->sector_count);
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ caddr = (volatile unsigned char *)(info->start[i]);
+ info->protect[i] = caddr[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ caddr = (volatile unsigned char *)info->start[0];
+ caddr[0] = 0xF0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+ int rc = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ((info->flash_id == FLASH_UNKNOWN) ||
+ (info->flash_id > FLASH_AMD_COMP)) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+ if (info->flash_id & FLASH_MAN_SST) {
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
+ udelay(30000); /* wait 30 ms */
+ }
+ else
+ addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (FLASH_WORD_SIZE *)(info->start[l_sect]);
+ while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ serial_putc ('.');
+ last = now;
+ }
+ }
+
+DONE:
+ /* reset to read mode */
+ addr = (FLASH_WORD_SIZE *)info->start[0];
+ addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return rc;
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*----------------------------------------------------------------------------*/
+/* Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+ volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+ volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+ ulong start;
+ int flag;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((volatile FLASH_WORD_SIZE *)dest) &
+ (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+ {
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
+ (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c
new file mode 100644
index 0000000..2acf800
--- /dev/null
+++ b/board/eltec/elppc/misc.c
@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* includes */
+#include <common.h>
+#include <cli.h>
+#include <linux/ctype.h>
+#include <pci.h>
+#include <net.h>
+#include "srom.h"
+
+/* imports */
+extern int l2_cache_enable (int l2control);
+extern int eepro100_write_eeprom (struct eth_device *dev, int location,
+ int addr_len, unsigned short data);
+extern int read_eeprom (struct eth_device *dev, int location, int addr_len);
+
+/*----------------------------------------------------------------------------*/
+/*
+ * read/write to nvram is only byte access
+ */
+void *nvram_read (void *dest, const long src, size_t count)
+{
+ uchar *d = (uchar *) dest;
+ uchar *s = (uchar *) (CONFIG_ENV_MAP_ADRS + src);
+
+ while (count--)
+ *d++ = *s++;
+
+ return dest;
+}
+
+void nvram_write (long dest, const void *src, size_t count)
+{
+ uchar *d = (uchar *) (CONFIG_ENV_MAP_ADRS + dest);
+ uchar *s = (uchar *) src;
+
+ while (count--)
+ *d++ = *s++;
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * handle sroms on ELPPC
+ * fix ether address
+ * set serial console as default
+ */
+int misc_init_r (void)
+{
+ revinfo eerev;
+ u_char *ptr;
+ u_int i, l, initSrom, copyNv;
+ char buf[256];
+ char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+ 0, 0, 0, 0, 10, 11, 12, 13, 14, 15
+ };
+
+ /* Clock setting for MPC107 i2c */
+ mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b);
+
+ /* Reset the EPIC */
+ out32r (MPC107_EUMB_GCR, 0xa0000000);
+ while (in32r (MPC107_EUMB_GCR) & 0x80000000); /* Wait for reset to complete */
+ out32r (MPC107_EUMB_GCR, 0x20000000); /* Put into into mixed mode */
+ while (in32r (MPC107_EUMB_IACKR) != 0xff); /* Clear all pending interrupts */
+
+ /*
+ * Check/Remake revision info
+ */
+ initSrom = 0;
+ copyNv = 0;
+
+ /* read out current revision srom contens */
+ mpc107_srom_load (0x0000, (u_char *) & eerev, sizeof (revinfo),
+ SECOND_DEVICE, FIRST_BLOCK);
+
+ /* read out current nvram shadow image */
+ nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE);
+
+ if (strcmp (eerev.magic, "ELTEC") != 0) {
+ /* srom is not initialized -> create a default revision info */
+ for (i = 0, ptr = (u_char *) & eerev; i < sizeof (revinfo);
+ i++)
+ *ptr++ = 0x00;
+ strcpy (eerev.magic, "ELTEC");
+ eerev.revrev[0] = 1;
+ eerev.revrev[1] = 0;
+ eerev.size = 0x00E0;
+ eerev.category[0] = 0x01;
+
+ /* node id from dead e128 as default */
+ eerev.etheraddr[0] = 0x00;
+ eerev.etheraddr[1] = 0x00;
+ eerev.etheraddr[2] = 0x5B;
+ eerev.etheraddr[3] = 0x00;
+ eerev.etheraddr[4] = 0x2E;
+ eerev.etheraddr[5] = 0x4D;
+
+ /* cache config word for ELPPC */
+ memset(&eerev.res[0], 0, 4);
+
+ initSrom = 1; /* force dialog */
+ copyNv = 1; /* copy to nvram */
+ }
+
+ if ((copyNv == 0)
+ && (el_srom_checksum ((u_char *) & eerev, CONFIG_SYS_SROM_SIZE) !=
+ el_srom_checksum ((u_char *) buf, CONFIG_SYS_SROM_SIZE))) {
+ printf ("Invalid revision info copy in nvram !\n");
+ printf ("Press key:\n <c> to copy current revision info to nvram.\n");
+ printf (" <r> to reenter revision info.\n");
+ printf ("=> ");
+ if (0 != cli_readline(NULL)) {
+ switch ((char) toupper (console_buffer[0])) {
+ case 'C':
+ copyNv = 1;
+ break;
+ case 'R':
+ copyNv = 1;
+ initSrom = 1;
+ break;
+ }
+ }
+ }
+
+ if (initSrom) {
+ memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */
+ printf ("Enter revision number (0-9): %c ",
+ eerev.revision[0][0]);
+ if (0 != cli_readline(NULL)) {
+ eerev.revision[0][0] =
+ (char) toupper (console_buffer[0]);
+ memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
+ }
+
+ printf ("Enter revision character (A-Z): %c ",
+ eerev.revision[0][1]);
+ if (1 == cli_readline(NULL)) {
+ eerev.revision[0][1] =
+ (char) toupper (console_buffer[0]);
+ }
+
+ printf ("Enter board name (V-XXXX-XXXX): %s ",
+ (char *) &eerev.board);
+ if (11 == cli_readline(NULL)) {
+ for (i = 0; i < 11; i++)
+ eerev.board[i] =
+ (char) toupper (console_buffer[i]);
+ eerev.board[11] = '\0';
+ }
+
+ printf ("Enter serial number: %s ", (char *) &eerev.serial);
+ if (6 == cli_readline(NULL)) {
+ for (i = 0; i < 6; i++)
+ eerev.serial[i] = console_buffer[i];
+ eerev.serial[6] = '\0';
+ }
+
+ printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]);
+ if (12 == cli_readline(NULL)) {
+ for (i = 0; i < 12; i += 2)
+ eerev.etheraddr[i >> 1] =
+ (char) (16 *
+ hex[toupper
+ (console_buffer[i]) -
+ '0'] +
+ hex[toupper
+ (console_buffer[i + 1]) -
+ '0']);
+ }
+
+ l = strlen ((char *) &eerev.text);
+ printf ("Add to text section (max 64 chr): %s ",
+ (char *) &eerev.text);
+ if (0 != cli_readline(NULL)) {
+ for (i = l; i < 63; i++)
+ eerev.text[i] = console_buffer[i - l];
+ eerev.text[63] = '\0';
+ }
+
+ /* prepare network eeprom */
+ memset (buf, 0, 128);
+
+ buf[0] = eerev.etheraddr[1];
+ buf[1] = eerev.etheraddr[0];
+ buf[2] = eerev.etheraddr[3];
+ buf[3] = eerev.etheraddr[2];
+ buf[4] = eerev.etheraddr[5];
+ buf[5] = eerev.etheraddr[4];
+
+ buf[20] = 0x48;
+ buf[21] = 0xB2;
+
+ buf[22] = 0x00;
+ buf[23] = 0x04;
+
+ buf[24] = 0x14;
+ buf[25] = 0x33;
+
+ printf ("\nSRom: Writing i82559 info ........ ");
+ if (eepro100_srom_store ((unsigned short *) buf) == -1)
+ printf ("FAILED\n");
+ else
+ printf ("OK\n");
+
+ /* update CRC */
+ eerev.crc =
+ el_srom_checksum ((u_char *) eerev.board, eerev.size);
+
+ /* write new values */
+ printf ("\nSRom: Writing revision info ...... ");
+ if (mpc107_srom_store
+ ((BLOCK_SIZE - sizeof (revinfo)), (u_char *) & eerev,
+ sizeof (revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
+ printf ("FAILED\n\n");
+ else
+ printf ("OK\n\n");
+
+ /* write new values as shadow image to nvram */
+ nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev,
+ CONFIG_SYS_SROM_SIZE);
+
+ }
+
+ /*if (initSrom) */
+ /* copy current values as shadow image to nvram */
+ if (initSrom == 0 && copyNv == 1)
+ nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev,
+ CONFIG_SYS_SROM_SIZE);
+
+ /* update environment */
+ sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+ eerev.etheraddr[0], eerev.etheraddr[1],
+ eerev.etheraddr[2], eerev.etheraddr[3],
+ eerev.etheraddr[4], eerev.etheraddr[5]);
+ setenv ("ethaddr", buf);
+
+ /* print actual board identification */
+ printf ("Ident: %s Ser %s Rev %c%c\n",
+ eerev.board, (char *) &eerev.serial,
+ eerev.revision[0][0], eerev.revision[0][1]);
+
+ return (0);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/elppc/mpc107_i2c.c b/board/eltec/elppc/mpc107_i2c.c
new file mode 100644
index 0000000..4f95703
--- /dev/null
+++ b/board/eltec/elppc/mpc107_i2c.c
@@ -0,0 +1,304 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* includes */
+#include <common.h>
+#include "srom.h"
+
+/* locals */
+static unsigned long mpc107_eumb_addr = 0;
+
+/*----------------------------------------------------------------------------*/
+
+/*
+ * calculate checksum for ELTEC revision srom
+ */
+unsigned long el_srom_checksum (ptr, size)
+register unsigned char *ptr;
+unsigned long size;
+{
+ u_long f, accu = 0;
+ u_int i;
+ u_char byte;
+
+ for (; size; size--)
+ {
+ byte = *ptr++;
+ for (i = 8; i; i--)
+ {
+ f = ((byte & 1) ^ (accu & 1)) ? 0x84083001 : 0;
+ accu >>= 1; accu ^= f;
+ byte >>= 1;
+ }
+ }
+ return(accu);
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int mpc107_i2c_wait ( unsigned long timeout )
+{
+ unsigned long x;
+
+ while (((x = in32r(MPC107_I2CSR)) & 0x82) != 0x82)
+ {
+ if (!timeout--)
+ return -1;
+ }
+
+ if (x & 0x10)
+ {
+ return -1;
+ }
+ out32r(MPC107_I2CSR, 0);
+
+ return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int mpc107_i2c_wait_idle ( unsigned long timeout )
+{
+ while (in32r(MPC107_I2CSR) & 0x20)
+ {
+ if (!timeout--)
+ return -1;
+ }
+ return 0;
+}
+
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_i2c_read_byte (
+ unsigned char device,
+ unsigned char block,
+ unsigned char offset )
+{
+ unsigned long timeout = MPC107_I2C_TIMEOUT;
+ int data;
+
+ if (!mpc107_eumb_addr)
+ return -6;
+
+ mpc107_i2c_wait_idle (timeout);
+
+ /* Start with MEN */
+ out32r(MPC107_I2CCR, 0x80);
+
+ /* Start as master */
+ out32r(MPC107_I2CCR, 0xB0);
+ out32r(MPC107_I2CDR, (0xA0 | device | block));
+
+ if (mpc107_i2c_wait(timeout) < 0)
+ {
+ printf("mpc107_i2c_read Error 1\n");
+ return -2;
+ }
+
+ if (in32r(MPC107_I2CSR)&0x1)
+ {
+ /* Generate STOP condition; device busy or not existing */
+ out32r(MPC107_I2CCR, 0x80);
+ return -1;
+ }
+
+ /* Data address */
+ out32r(MPC107_I2CDR, offset);
+
+ if (mpc107_i2c_wait(timeout) < 0)
+ {
+ printf("mpc107_i2c_read Error 2\n");
+ return -3;
+ }
+
+ /* Switch to read - restart */
+ out32r(MPC107_I2CCR, 0xB4);
+ out32r(MPC107_I2CDR, (0xA1 | device | block));
+
+ if (mpc107_i2c_wait(timeout) < 0)
+ {
+ printf("mpc107_i2c_read Error 3\n");
+ return -4;
+ }
+
+ out32r(MPC107_I2CCR, 0xA8); /* no ACK */
+ in32r(MPC107_I2CDR);
+
+ if (mpc107_i2c_wait(timeout) < 0)
+ {
+ printf("mpc107_i2c_read Error 4\n");
+ return -5;
+ }
+ /* Generate STOP condition */
+ out32r(MPC107_I2CCR, 0x88);
+
+ /* read */
+ data = in32r(MPC107_I2CDR);
+
+ return (data);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_i2c_write_byte (
+ unsigned char device,
+ unsigned char block,
+ unsigned char offset,
+ unsigned char val )
+{
+
+ unsigned long timeout = MPC107_I2C_TIMEOUT;
+
+ if (!mpc107_eumb_addr)
+ return -6;
+
+ mpc107_i2c_wait_idle(timeout);
+
+ /* Start with MEN */
+ out32r(MPC107_I2CCR, 0x80);
+
+ /* Start as master */
+ out32r(MPC107_I2CCR, 0xB0);
+ out32r(MPC107_I2CDR, (0xA0 | device | block));
+
+ if (mpc107_i2c_wait(timeout) < 0)
+ {
+ printf("mpc107_i2c_write Error 1\n");
+ return -1;
+ }
+
+ /* Data address */
+ out32r(MPC107_I2CDR, offset);
+
+ if (mpc107_i2c_wait(timeout) < 0)
+ {
+ printf("mpc107_i2c_write Error 2\n");
+ return -1;
+ }
+
+ /* Write */
+ out32r(MPC107_I2CDR, val);
+ if (mpc107_i2c_wait(timeout) < 0)
+ {
+ printf("mpc107_i2c_write Error 3\n");
+ return -1;
+ }
+
+ /* Generate Stop Condition */
+ out32r(MPC107_I2CCR, 0x80);
+
+ /* Return ACK or no ACK */
+ return (in32r(MPC107_I2CSR) & 0x01);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_srom_load (
+ unsigned char addr,
+ unsigned char *pBuf,
+ int cnt,
+ unsigned char device,
+ unsigned char block )
+{
+ register int i;
+ int val;
+ int timeout;
+
+ for (i = 0; i < cnt; i++)
+ {
+ timeout=100;
+ do
+ {
+ val = mpc107_i2c_read_byte (device, block, addr);
+ if (val < -1)
+ {
+ printf("i2c_read_error %d at dev %x block %x addr %x\n",
+ val, device, block, addr);
+ return -1;
+ }
+ else if (timeout==0)
+ {
+ printf ("i2c_read_error: timeout at dev %x block %x addr %x\n",
+ device, block, addr);
+ return -1;
+ }
+ timeout--;
+ } while (val == -1); /* if no ack: try again! */
+
+ *pBuf++ = (unsigned char)val;
+ addr++;
+
+ if ((addr == 0) && (i != cnt-1)) /* is it the same block ? */
+ {
+ if (block == FIRST_BLOCK)
+ block = SECOND_BLOCK;
+ else
+ {
+ printf ("ic2_read_error: read beyond 2. block !\n");
+ return -1;
+ }
+ }
+ }
+ udelay(100000);
+ return (cnt);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_srom_store (
+ unsigned char addr,
+ unsigned char *pBuf,
+ int cnt,
+ unsigned char device,
+ unsigned char block )
+{
+ register int i;
+
+ for (i = 0; i < cnt; i++)
+ {
+ while (mpc107_i2c_write_byte (device,block,addr,*pBuf) == 1);
+ addr++;
+ pBuf++;
+
+ if ((addr == 0) && (i != cnt-1)) /* is it the same block ? */
+ {
+ if (block == FIRST_BLOCK)
+ block = SECOND_BLOCK;
+ else
+ {
+ printf ("ic2_write_error: write beyond 2. block !\n");
+ return -1;
+ }
+ }
+ }
+ udelay(100000);
+ return(cnt);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_i2c_init ( unsigned long eumb_addr, unsigned long divider )
+{
+ unsigned long x;
+
+ if (eumb_addr)
+ mpc107_eumb_addr = eumb_addr;
+ else
+ return -1;
+
+ /* Set I2C clock */
+ x = in32r(MPC107_I2CFDR) & 0xffffff00;
+ out32r(MPC107_I2CFDR, (x | divider));
+
+ /* Clear arbitration */
+ out32r(MPC107_I2CSR, 0);
+
+ return mpc107_eumb_addr;
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/elppc/pci.c b/board/eltec/elppc/pci.c
new file mode 100644
index 0000000..d81a41a
--- /dev/null
+++ b/board/eltec/elppc/pci.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * PCI initialisation for the MPC10x.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <mpc106.h>
+
+#ifdef CONFIG_PCI
+
+struct pci_controller local_hose;
+
+void pci_init_board(void)
+{
+ struct pci_controller* hose = (struct pci_controller *)&local_hose;
+ u16 reg16;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ pci_set_region(hose->regions + 0,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_SYS_PCI_MEM_BUS,
+ CONFIG_SYS_PCI_MEM_PHYS,
+ CONFIG_SYS_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* ISA/PCI memory space */
+ pci_set_region(hose->regions + 2,
+ CONFIG_SYS_ISA_MEM_BUS,
+ CONFIG_SYS_ISA_MEM_PHYS,
+ CONFIG_SYS_ISA_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI I/O space */
+ pci_set_region(hose->regions + 3,
+ CONFIG_SYS_PCI_IO_BUS,
+ CONFIG_SYS_PCI_IO_PHYS,
+ CONFIG_SYS_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ /* ISA/PCI I/O space */
+ pci_set_region(hose->regions + 4,
+ CONFIG_SYS_ISA_IO_BUS,
+ CONFIG_SYS_ISA_IO_PHYS,
+ CONFIG_SYS_ISA_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 5;
+
+ pci_setup_indirect(hose,
+ MPC106_REG_ADDR,
+ MPC106_REG_DATA);
+
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+
+ /* Initialises the MPC10x PCI Configuration regs. */
+ pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+ /* Clear non-reserved bits in status register */
+ pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+}
+
+#endif /* CONFIG_PCI */
diff --git a/board/eltec/elppc/srom.h b/board/eltec/elppc/srom.h
new file mode 100644
index 0000000..662daf8
--- /dev/null
+++ b/board/eltec/elppc/srom.h
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* common srom defs */
+#define FIRST_DEVICE 0x00
+#define SECOND_DEVICE 0x04
+#define FIRST_BLOCK 0x00
+#define SECOND_BLOCK 0x02
+#define BLOCK_SIZE 0x100
+#define ERROR (-1)
+
+#define CLK2P0TO1_1MB_PB_0P5DH 0x79000100
+#define CLK2P5TO1_1MB_PB_0P5DH 0x7B000100
+
+#define CPU_TYPE_740 0x08
+#define CPU_TYPE_750 0x08
+#define CPU_TYPE ((get_pvr()>>16)&0xffff)
+
+#define ABS(x) ((x<0)?-x:x)
+#define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8)
+
+/* bab7xx ELTEC srom */
+#define I2C_BUS_DAT (CONFIG_SYS_ISA_IO + 0x220)
+#define I2C_BUS_DIR (CONFIG_SYS_ISA_IO + 0x221)
+
+/* srom at mpc107 */
+#define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */
+#define MPC107_I2CFDR (mpc107_eumb_addr + 0x3004) /* freq divider */
+#define MPC107_I2CCR (mpc107_eumb_addr + 0x3008) /* control */
+#define MPC107_I2CSR (mpc107_eumb_addr + 0x300c) /* status */
+#define MPC107_I2CDR (mpc107_eumb_addr + 0x3010) /* data */
+#define MPC107_I2C_TIMEOUT 10000000
+
+/* i82559 */
+#define EE_ADDR_BITS 6
+#define EE_SIZE 0x40 /* 0x40 words */
+#define EE_CHECKSUM 0xBABA
+
+/* dc21143 */
+#define DEC_SROM_SIZE 128
+
+
+/*
+ * structure of revision srom
+ */
+typedef struct {
+ char magic[8]; /* 000 - Magic number */
+ char revrev[2]; /* 008 - Revision of structure */
+ unsigned short size; /* 00A - Size of CRC area */
+ unsigned long crc; /* 00C - CRC */
+ char board[16]; /* 010 - Board Revision information */
+ char option[4][16]; /* 020 - Option Revision information */
+ char serial[8]; /* 060 - Board serial number */
+ char etheraddr[6]; /* 068 - Ethernet node addresse */
+ char reserved[2]; /* 06E - Reserved */
+ char revision[7][2]; /* 070 - Revision codes */
+ char category[2]; /* 07E - Category codes */
+ char text[64]; /* 080 - Text field */
+ char res[64]; /* 0C0 - Reserved */
+} revinfo;
+
+unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size);
+int el_srom_load (unsigned char addr, unsigned char *buf, int cnt,
+ unsigned char device, unsigned char block);
+int el_srom_store (unsigned char addr, unsigned char *buf, int cnt,
+ unsigned char device, unsigned char block);
+
+int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider);
+int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset);
+int mpc107_i2c_write_byte (unsigned char device, unsigned char block,
+ unsigned char offset, unsigned char val);
+int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt,
+ unsigned char device, unsigned char block);
+int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt,
+ unsigned char device, unsigned char block);
+
+int dc_srom_load (unsigned short *dest);
+int dc_srom_store (unsigned short *src);
+
+unsigned short eepro100_srom_checksum (unsigned short *sromdata);
+void eepro100_srom_load (unsigned short *destination);
+int eepro100_srom_store (unsigned short *source);
diff --git a/board/embest/mx6boards/Kconfig b/board/embest/mx6boards/Kconfig
new file mode 100644
index 0000000..53a39d3
--- /dev/null
+++ b/board/embest/mx6boards/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EMBESTMX6BOARDS
+
+config SYS_BOARD
+ default "mx6boards"
+
+config SYS_VENDOR
+ default "embest"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "embestmx6boards"
+
+endif
diff --git a/board/embest/mx6boards/MAINTAINERS b/board/embest/mx6boards/MAINTAINERS
new file mode 100644
index 0000000..0ffd466
--- /dev/null
+++ b/board/embest/mx6boards/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6BOARDS BOARD
+M: Eric Bénard <eric@eukrea.com>
+S: Maintained
+F: board/embest/mx6boards/
+F: include/configs/embestmx6boards.h
+F: configs/marsboard_defconfig
+F: configs/riotboard_defconfig
diff --git a/board/embest/mx6boards/Makefile b/board/embest/mx6boards/Makefile
new file mode 100644
index 0000000..467fb50
--- /dev/null
+++ b/board/embest/mx6boards/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6boards.o
diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c
new file mode 100644
index 0000000..f8c7468
--- /dev/null
+++ b/board/embest/mx6boards/mx6boards.c
@@ -0,0 +1,610 @@
+/*
+ * Copyright (C) 2014 Eukréa Electromatique
+ * Author: Eric Bénard <eric@eukrea.com>
+ * Fabio Estevam <fabio.estevam@freescale.com>
+ * Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * based on sabresd.c which is :
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * and on hummingboard.c which is :
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/spi.h>
+#include <asm/imx-common/video.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
+ PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+static int board_type = -1;
+#define BOARD_IS_MARSBOARD 0
+#define BOARD_IS_RIOTBOARD 1
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* GPIO16 -> AR8035 25MHz */
+ MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ /* AR8035 PHY Reset */
+ MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ /* AR8035 PHY Interrupt */
+ MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* Reset AR8035 PHY */
+ gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
+ mdelay(2);
+ gpio_set_value(IMX_GPIO_NR(3, 31), 1);
+}
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ /* from linux/arch/arm/mach-imx/mach-imx6q.c :
+ * Ar803x phy SmartEEE feature cause link status generates glitch,
+ * which cause ethernet link down/up issue, so disable SmartEEE
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
+ MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
+ MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* eMMC RST */
+ MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC2_BASE_ADDR},
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ if (board_type == BOARD_IS_RIOTBOARD)
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ else if (board_type == BOARD_IS_MARSBOARD)
+ ret = 1; /* eMMC/uSDHC3 is always present */
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = 1; /* eMMC/uSDHC4 is always present */
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ int i;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * ** RiOTboard :
+ * mmc0 SDCard slot (bottom)
+ * mmc1 uSDCard slot (top)
+ * mmc2 eMMC
+ * ** MarSBoard :
+ * mmc0 uSDCard slot (bottom)
+ * mmc1 eMMC
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ if (board_type == BOARD_IS_RIOTBOARD) {
+ imx_iomux_v3_setup_multiple_pads(
+ riotboard_usdhc3_pads,
+ ARRAY_SIZE(riotboard_usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ } else {
+ gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
+ udelay(250);
+ gpio_set_value(IMX_GPIO_NR(7, 8), 1);
+ }
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ usdhc_cfg[2].max_bus_width = 4;
+ gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
+ udelay(250);
+ gpio_set_value(IMX_GPIO_NR(6, 8), 1);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+ MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
+}
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+struct i2c_pads_info i2c_pad_info3 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(1, 5)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+
+iomux_v3_cfg_t const tft_pads_riot[] = {
+ /* LCD_PWR_EN */
+ MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* TOUCH_INT */
+ MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED_PWR_EN */
+ MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* BL LEVEL */
+ MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const tft_pads_mars[] = {
+ /* LCD_PWR_EN */
+ MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* TOUCH_INT */
+ MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED_PWR_EN */
+ MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* BL LEVEL (PWM4) */
+ MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)
+ IOMUXC_BASE_ADDR;
+ setbits_le32(&iomux->gpr[2],
+ IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
+ /* set backlight level to ON */
+ if (board_type == BOARD_IS_RIOTBOARD)
+ gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
+ else if (board_type == BOARD_IS_MARSBOARD)
+ gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
+}
+
+static void disable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* set backlight level to OFF */
+ if (board_type == BOARD_IS_RIOTBOARD)
+ gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
+ else if (board_type == BOARD_IS_MARSBOARD)
+ gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
+
+ clrbits_le32(&iomux->gpr[2],
+ IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ disable_lvds(dev);
+ imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+ return (0 == i2c_set_bus_num(dev->bus)) &&
+ (0 == i2c_probe(dev->addr));
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 2,
+ .addr = 0x1,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .detect = detect_i2c,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "LCD8000-97C",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 100,
+ .right_margin = 200,
+ .upper_margin = 10,
+ .lower_margin = 20,
+ .hsync_len = 20,
+ .vsync_len = 8,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ /* Turn on LDB0, IPU,IPU DI0 clocks */
+ setbits_le32(&mxc_ccm->CCGR3,
+ MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+ /* set LDB0 clk select to 011/011 */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
+ (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+
+ setbits_le32(&mxc_ccm->cscmr2,
+ MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+ setbits_le32(&mxc_ccm->chsccdr,
+ (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+ | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+ | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+ | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+ | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ clrsetbits_le32(&iomux->gpr[3],
+ IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+ IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
+ IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+
+ return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ u32 cputype = cpu_type(get_cpu_rev());
+
+ switch (cputype) {
+ case MXC_CPU_MX6SOLO:
+ board_type = BOARD_IS_RIOTBOARD;
+ break;
+ case MXC_CPU_MX6D:
+ board_type = BOARD_IS_MARSBOARD;
+ break;
+ }
+
+ setup_iomux_uart();
+
+ if (board_type == BOARD_IS_RIOTBOARD)
+ imx_iomux_v3_setup_multiple_pads(
+ tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
+ else if (board_type == BOARD_IS_MARSBOARD)
+ imx_iomux_v3_setup_multiple_pads(
+ tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
+#if defined(CONFIG_VIDEO_IPUV3)
+ /* power ON LCD */
+ gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
+ /* touch interrupt is an input */
+ gpio_direction_input(IMX_GPIO_NR(6, 14));
+ /* power ON backlight */
+ gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
+ /* set backlight level to off */
+ if (board_type == BOARD_IS_RIOTBOARD)
+ gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
+ else if (board_type == BOARD_IS_MARSBOARD)
+ gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
+ setup_display();
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ /* i2c2 : HDMI EDID */
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ /* i2c3 : LVDS, Expansion connector */
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+#ifdef CONFIG_MXC_SPI
+ setup_spi();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode riotboard_boot_modes[] = {
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+static const struct boot_mode marsboard_boot_modes[] = {
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ if (board_type == BOARD_IS_RIOTBOARD)
+ add_board_boot_modes(riotboard_boot_modes);
+ else if (board_type == BOARD_IS_RIOTBOARD)
+ add_board_boot_modes(marsboard_boot_modes);
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: ");
+ if (board_type == BOARD_IS_MARSBOARD)
+ puts("MarSBoard\n");
+ else if (board_type == BOARD_IS_RIOTBOARD)
+ puts("RIoTboard\n");
+ else
+ printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
+
+ return 0;
+}
diff --git a/board/enbw/enbw_cmc/Kconfig b/board/enbw/enbw_cmc/Kconfig
new file mode 100644
index 0000000..796736d
--- /dev/null
+++ b/board/enbw/enbw_cmc/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ENBW_CMC
+
+config SYS_BOARD
+ default "enbw_cmc"
+
+config SYS_VENDOR
+ default "enbw"
+
+config SYS_CONFIG_NAME
+ default "enbw_cmc"
+
+endif
diff --git a/board/enbw/enbw_cmc/MAINTAINERS b/board/enbw/enbw_cmc/MAINTAINERS
new file mode 100644
index 0000000..f7c9920
--- /dev/null
+++ b/board/enbw/enbw_cmc/MAINTAINERS
@@ -0,0 +1,6 @@
+ENBW_CMC BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: board/enbw/enbw_cmc/
+F: include/configs/enbw_cmc.h
+F: configs/enbw_cmc_defconfig
diff --git a/board/enbw/enbw_cmc/Makefile b/board/enbw/enbw_cmc/Makefile
new file mode 100644
index 0000000..054d6e7
--- /dev/null
+++ b/board/enbw/enbw_cmc/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := enbw_cmc.o
diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c
new file mode 100644
index 0000000..53b8362
--- /dev/null
+++ b/board/enbw/enbw_cmc/enbw_cmc.c
@@ -0,0 +1,893 @@
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <linux/ctype.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/da850_lowlevel.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sdmmc_defs.h>
+#include <asm/arch/timer_defs.h>
+#include <asm/davinci_rtc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF },
+ { DAVINCI_LPSC_SPI1 },
+ { DAVINCI_LPSC_ARM_RAM_ROM },
+ { DAVINCI_LPSC_UART0 },
+ { DAVINCI_LPSC_EMAC },
+ { DAVINCI_LPSC_UART0 },
+ { DAVINCI_LPSC_GPIO },
+ { DAVINCI_LPSC_DDR_EMIF },
+ { DAVINCI_LPSC_UART1 },
+ { DAVINCI_LPSC_UART2 },
+ { DAVINCI_LPSC_MMC_SD1 },
+ { DAVINCI_LPSC_USB20 },
+ { DAVINCI_LPSC_USB11 },
+};
+
+const int lpsc_size = ARRAY_SIZE(lpsc);
+
+static const struct pinmux_config enbw_pins[] = {
+ { pinmux(0), 8, 0 },
+ { pinmux(0), 8, 1 },
+ { pinmux(0), 8, 2 },
+ { pinmux(0), 8, 3 },
+ { pinmux(0), 8, 4 },
+ { pinmux(0), 8, 5 },
+ { pinmux(1), 4, 0 },
+ { pinmux(1), 8, 1 },
+ { pinmux(1), 8, 2 },
+ { pinmux(1), 8, 3 },
+ { pinmux(1), 8, 4 },
+ { pinmux(1), 8, 5 },
+ { pinmux(1), 8, 6 },
+ { pinmux(1), 4, 7 },
+ { pinmux(2), 8, 0 },
+ { pinmux(5), 1, 0 },
+ { pinmux(5), 1, 3 },
+ { pinmux(5), 1, 7 },
+ { pinmux(5), 1, 5 },
+ { pinmux(5), 1, 4 },
+ { pinmux(5), 1, 3 },
+ { pinmux(5), 1, 2 },
+ { pinmux(5), 1, 1 },
+ { pinmux(5), 1, 0 },
+ { pinmux(6), 8, 0 },
+ { pinmux(6), 8, 1 },
+ { pinmux(6), 8, 2 },
+ { pinmux(6), 8, 3 },
+ { pinmux(6), 8, 4 },
+ { pinmux(6), 8, 5 },
+ { pinmux(6), 1, 7 },
+ { pinmux(7), 8, 2 },
+ { pinmux(7), 1, 3 },
+ { pinmux(7), 8, 6 },
+ { pinmux(7), 1, 7 },
+ { pinmux(13), 8, 2 },
+ { pinmux(13), 8, 3 },
+ { pinmux(13), 8, 4 },
+ { pinmux(13), 8, 5 },
+ { pinmux(13), 8, 6 },
+ { pinmux(13), 8, 7 },
+ { pinmux(14), 8, 0 },
+ { pinmux(14), 8, 1 },
+ { pinmux(16), 8, 1 },
+ { pinmux(16), 8, 2 },
+ { pinmux(16), 8, 3 },
+ { pinmux(16), 8, 4 },
+ { pinmux(16), 8, 5 },
+ { pinmux(16), 8, 6 },
+ { pinmux(16), 8, 7 },
+ { pinmux(17), 1, 0 },
+ { pinmux(17), 1, 1 },
+ { pinmux(17), 1, 2 },
+ { pinmux(17), 8, 3 },
+ { pinmux(17), 8, 4 },
+ { pinmux(17), 8, 5 },
+ { pinmux(17), 8, 6 },
+ { pinmux(17), 8, 7 },
+ { pinmux(18), 8, 0 },
+ { pinmux(18), 8, 1 },
+ { pinmux(18), 2, 2 },
+ { pinmux(18), 2, 3 },
+ { pinmux(18), 2, 4 },
+ { pinmux(18), 8, 6 },
+ { pinmux(18), 8, 7 },
+ { pinmux(19), 8, 0 },
+ { pinmux(19), 2, 1 },
+ { pinmux(19), 2, 2 },
+ { pinmux(19), 2, 3 },
+ { pinmux(19), 2, 4 },
+ { pinmux(19), 8, 5 },
+ { pinmux(19), 8, 6 },
+};
+
+const struct pinmux_resource pinmuxes[] = {
+ PINMUX_ITEM(emac_pins_mii),
+ PINMUX_ITEM(emac_pins_mdio),
+ PINMUX_ITEM(i2c0_pins),
+ PINMUX_ITEM(emifa_pins_cs2),
+ PINMUX_ITEM(emifa_pins_cs3),
+ PINMUX_ITEM(emifa_pins_cs4),
+ PINMUX_ITEM(emifa_pins_nand),
+ PINMUX_ITEM(emifa_pins_nor),
+ PINMUX_ITEM(spi1_pins_base),
+ PINMUX_ITEM(spi1_pins_scs0),
+ PINMUX_ITEM(uart1_pins_txrx),
+ PINMUX_ITEM(uart2_pins_txrx),
+ PINMUX_ITEM(uart2_pins_rtscts),
+ PINMUX_ITEM(enbw_pins),
+};
+
+const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
+
+struct gpio_config {
+ char name[GPIO_NAME_SIZE];
+ unsigned char bank;
+ unsigned char gpio;
+ unsigned char out;
+ unsigned char value;
+};
+
+static const struct gpio_config enbw_gpio_config_hut[] = {
+ { "RS485 enable", 8, 11, 1, 0 },
+ { "RS485 iso", 8, 10, 1, 1 },
+ { "W2HUT RS485 Rx ena", 8, 9, 1, 0 },
+ { "W2HUT RS485 iso", 8, 8, 1, 1 },
+};
+
+static const struct gpio_config enbw_gpio_config_w[] = {
+ { "RS485 enable", 8, 11, 1, 0 },
+ { "RS485 iso", 8, 10, 1, 0 },
+ { "W2HUT RS485 Rx ena", 8, 9, 1, 0 },
+ { "W2HUT RS485 iso", 8, 8, 1, 0 },
+};
+
+static const struct gpio_config enbw_gpio_config[] = {
+ { "LAN reset", 7, 15, 1, 1 },
+ { "ena 11V PLC", 7, 14, 1, 0 },
+ { "ena 1.5V PLC", 7, 13, 1, 0 },
+ { "disable VBUS", 7, 12, 1, 1 },
+ { "PLC reset", 6, 13, 1, 0 },
+ { "LCM RS", 6, 12, 1, 0 },
+ { "LCM R/W", 6, 11, 1, 0 },
+ { "PLC pairing", 6, 10, 1, 1 },
+ { "PLC MDIO CLK", 6, 9, 1, 0 },
+ { "HK218", 6, 8, 1, 0 },
+ { "HK218 Rx", 6, 1, 1, 1 },
+ { "TPM reset", 6, 0, 1, 0 },
+ { "Board-Type", 3, 9, 0, 0 },
+ { "HW-ID0", 2, 7, 0, 0 },
+ { "HW-ID1", 2, 6, 0, 0 },
+ { "HW-ID2", 2, 3, 0, 0 },
+ { "PV-IF RxD ena", 0, 15, 1, 1 },
+ { "LED1", 1, 15, 1, 1 },
+ { "LED2", 0, 1, 1, 1 },
+ { "LED3", 0, 2, 1, 1 },
+ { "LED4", 0, 3, 1, 1 },
+ { "LED5", 0, 4, 1, 1 },
+ { "LED6", 0, 5, 1, 0 },
+ { "LED7", 0, 6, 1, 0 },
+ { "LED8", 0, 14, 1, 0 },
+ { "USER1", 0, 12, 0, 0 },
+ { "USER2", 0, 13, 0, 0 },
+};
+
+#define PHY_POWER 0x0800
+
+static void enbw_cmc_switch(int port, int on)
+{
+ const char *devname;
+ unsigned char phyaddr = 3;
+ unsigned char reg = 0;
+ unsigned short data;
+
+ if (port == 1)
+ phyaddr = 2;
+
+ devname = miiphy_get_current_dev();
+ if (!devname) {
+ printf("Error: no mii device\n");
+ return;
+ }
+ if (miiphy_read(devname, phyaddr, reg, &data) != 0) {
+ printf("Error reading from the PHY addr=%02x reg=%02x\n",
+ phyaddr, reg);
+ return;
+ }
+
+ if (on)
+ data &= ~PHY_POWER;
+ else
+ data |= PHY_POWER;
+
+ if (miiphy_write(devname, phyaddr, reg, data) != 0) {
+ printf("Error writing to the PHY addr=%02x reg=%02x\n",
+ phyaddr, reg);
+ return;
+ }
+}
+
+static int enbw_cmc_init_gpio(const struct gpio_config *conf, int sz)
+{
+ int i, ret;
+
+ for (i = 0; i < sz; i++) {
+ int gpio = conf[i].bank * 16 +
+ conf[i].gpio;
+
+ ret = gpio_request(gpio, conf[i].name);
+ if (ret) {
+ printf("%s: Could not get %s gpio\n", __func__,
+ conf[i].name);
+ return ret;
+ }
+
+ if (conf[i].out)
+ gpio_direction_output(gpio,
+ conf[i].value);
+ else
+ gpio_direction_input(gpio);
+ }
+
+ return 0;
+}
+
+int board_init(void)
+{
+ int board_type, hw_id;
+
+#ifndef CONFIG_USE_IRQ
+ irq_init();
+#endif
+ /* address of boot parameters, not used as booting with DTT */
+ gd->bd->bi_boot_params = 0;
+
+ enbw_cmc_init_gpio(enbw_gpio_config, ARRAY_SIZE(enbw_gpio_config));
+
+ /* detect HW version */
+ board_type = gpio_get_value(CONFIG_ENBW_CMC_BOARD_TYPE);
+ hw_id = gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT0) +
+ (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT1) << 1) +
+ (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT2) << 2);
+ printf("BOARD: CMC-%s hw id: %d\n", (board_type ? "w2" : "hut"),
+ hw_id);
+ if (board_type)
+ enbw_cmc_init_gpio(enbw_gpio_config_w,
+ ARRAY_SIZE(enbw_gpio_config_w));
+ else
+ enbw_cmc_init_gpio(enbw_gpio_config_hut,
+ ARRAY_SIZE(enbw_gpio_config_hut));
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ clrbits_le32(&davinci_syscfg_regs->suspsrc,
+ (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART2));
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+#define KSZ_CMD_READ 0x03
+#define KSZ_CMD_WRITE 0x02
+#define KSZ_ID 0x95
+
+static int enbw_cmc_switch_read(struct spi_slave *spi, u8 reg, u8 *val)
+{
+ unsigned long flags = SPI_XFER_BEGIN;
+ int ret;
+ int cmd_len;
+ u8 cmd[2];
+
+ cmd[0] = KSZ_CMD_READ;
+ cmd[1] = reg;
+ cmd_len = 2;
+
+ ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
+ if (ret) {
+ debug("Failed to send command (%zu bytes): %d\n",
+ cmd_len, ret);
+ return -EINVAL;
+ }
+ flags |= SPI_XFER_END;
+ *val = 0;
+ cmd_len = 1;
+ ret = spi_xfer(spi, cmd_len * 8, NULL, val, flags);
+ if (ret) {
+ debug("Failed to read (%zu bytes): %d\n",
+ cmd_len, ret);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int enbw_cmc_switch_read_ident(struct spi_slave *spi)
+{
+ int ret;
+ u8 val;
+
+ ret = enbw_cmc_switch_read(spi, 0, &val);
+ if (ret) {
+ debug("Failed to read\n");
+ return -EINVAL;
+ }
+
+ if (val != KSZ_ID)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int enbw_cmc_switch_write(struct spi_slave *spi, unsigned long reg,
+ unsigned long val)
+{
+ unsigned long flags = SPI_XFER_BEGIN;
+ int ret;
+ int cmd_len;
+ u8 cmd[3];
+
+ cmd[0] = KSZ_CMD_WRITE;
+ cmd[1] = reg;
+ cmd[2] = val;
+ cmd_len = 3;
+ flags |= SPI_XFER_END;
+
+ ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
+ if (ret) {
+ debug("Failed to send command (%zu bytes): %d\n",
+ cmd_len, ret);
+ return -EINVAL;
+ }
+
+ udelay(1000);
+ ret = enbw_cmc_switch_read(spi, reg, &cmd[0]);
+ if (ret) {
+ debug("Failed to read\n");
+ return -EINVAL;
+ }
+ if (val != cmd[0])
+ debug("warning: reg: %lx va: %x soll: %lx\n",
+ reg, cmd[0], val);
+
+ return 0;
+}
+
+static int enbw_cmc_eof(unsigned char *ptr)
+{
+ if (*ptr == 0xff)
+ return 1;
+
+ return 0;
+}
+
+static char *enbw_cmc_getnewline(char *ptr)
+{
+ while (*ptr != 0x0a) {
+ ptr++;
+ if (enbw_cmc_eof((unsigned char *)ptr))
+ return NULL;
+ }
+
+ ptr++;
+ return ptr;
+}
+
+static char *enbw_cmc_getvalue(char *ptr, int *value)
+{
+ int end = 0;
+
+ *value = -EINVAL;
+
+ if (!isxdigit(*ptr))
+ end = 1;
+
+ while (end) {
+ if ((*ptr == '#') || (*ptr == ';')) {
+ ptr = enbw_cmc_getnewline(ptr);
+ return ptr;
+ }
+ if (ptr != NULL) {
+ if (isxdigit(*ptr)) {
+ end = 0;
+ } else if (*ptr == 0x0a) {
+ ptr++;
+ return ptr;
+ } else {
+ ptr++;
+ if (enbw_cmc_eof((unsigned char *)ptr))
+ return NULL;
+ }
+ } else {
+ return NULL;
+ }
+ }
+ *value = (int)simple_strtoul((const char *)ptr, &ptr, 16);
+ ptr++;
+ return ptr;
+}
+
+static struct spi_slave *enbw_cmc_init_spi(void)
+{
+ struct spi_slave *spi;
+ int ret;
+
+ spi = spi_setup_slave(0, 0, 1000000, 0);
+ if (!spi) {
+ printf("Failed to set up slave\n");
+ return NULL;
+ }
+
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ debug("Failed to claim SPI bus: %d\n", ret);
+ goto err_claim_bus;
+ }
+
+ ret = enbw_cmc_switch_read_ident(spi);
+ if (ret)
+ goto err_read;
+
+ return spi;
+err_read:
+ spi_release_bus(spi);
+err_claim_bus:
+ spi_free_slave(spi);
+ return NULL;
+}
+
+static int enbw_cmc_config_switch(unsigned long addr)
+{
+ struct spi_slave *spi;
+ char *ptr = (char *)addr;
+ int value, reg;
+ int ret = 0;
+
+ debug("configure switch with file on addr: 0x%lx\n", addr);
+
+ spi = enbw_cmc_init_spi();
+ if (!spi)
+ return -EINVAL;
+
+ while (ptr != NULL) {
+ ptr = enbw_cmc_getvalue(ptr, ®);
+ if (ptr != NULL) {
+ ptr = enbw_cmc_getvalue(ptr, &value);
+ if ((ptr != NULL) && (value >= 0))
+ if (enbw_cmc_switch_write(spi, reg, value)) {
+ /* error writing to switch */
+ ptr = NULL;
+ ret = -EINVAL;
+ }
+ }
+ }
+
+ spi_release_bus(spi);
+ spi_free_slave(spi);
+ return ret;
+}
+
+static int do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ unsigned long addr;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+ enbw_cmc_config_switch(addr);
+
+ return 0;
+}
+
+U_BOOT_CMD(switch, 3, 1, do_switch,
+ "switch addr",
+ "[addr]"
+);
+
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+ struct spi_slave *spi;
+ const char *s;
+ size_t len = 0;
+ int config = 1;
+
+ davinci_emac_mii_mode_sel(0);
+
+ /* send a config file to the switch */
+ s = hwconfig_subarg("switch", "config", &len);
+ if (len) {
+ unsigned long addr = simple_strtoul(s, NULL, 16);
+
+ config = enbw_cmc_config_switch(addr);
+ }
+
+ if (config) {
+ /*
+ * no valid config file -> do we have some args in
+ * hwconfig ?
+ */
+ if ((hwconfig_subarg("switch", "lan", &len)) ||
+ (hwconfig_subarg("switch", "lmn", &len))) {
+ /* If so start switch */
+ spi = enbw_cmc_init_spi();
+ if (spi) {
+ if (enbw_cmc_switch_write(spi, 1, 0))
+ config = 0;
+ udelay(10000);
+ if (enbw_cmc_switch_write(spi, 1, 1))
+ config = 0;
+ spi_release_bus(spi);
+ spi_free_slave(spi);
+ }
+ } else {
+ config = 0;
+ }
+ }
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ if (config) {
+ if (hwconfig_subarg_cmp("switch", "lan", "on"))
+ /* Switch port lan on */
+ enbw_cmc_switch(1, 1);
+ else
+ enbw_cmc_switch(1, 0);
+
+ if (hwconfig_subarg_cmp("switch", "lmn", "on"))
+ /* Switch port pwl on */
+ enbw_cmc_switch(2, 1);
+ else
+ enbw_cmc_switch(2, 0);
+ }
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+#ifdef CONFIG_PREBOOT
+static uchar kbd_magic_prefix[] = "key_magic_";
+static uchar kbd_command_prefix[] = "key_cmd_";
+
+struct kbd_data_t {
+ char s1;
+};
+
+struct kbd_data_t *get_keys(struct kbd_data_t *kbd_data)
+{
+ /* read SW1 + SW2 */
+ kbd_data->s1 = gpio_get_value(12) +
+ (gpio_get_value(13) << 1);
+ return kbd_data;
+}
+
+static int compare_magic(const struct kbd_data_t *kbd_data, char *str)
+{
+ char s1 = str[0];
+
+ if (s1 >= '0' && s1 <= '9')
+ s1 -= '0';
+ else if (s1 >= 'a' && s1 <= 'f')
+ s1 = s1 - 'a' + 10;
+ else if (s1 >= 'A' && s1 <= 'F')
+ s1 = s1 - 'A' + 10;
+ else
+ return -1;
+
+ if (s1 != kbd_data->s1)
+ return -1;
+
+ return 0;
+}
+
+static char *key_match(const struct kbd_data_t *kbd_data)
+{
+ char magic[sizeof(kbd_magic_prefix) + 1];
+ char *suffix;
+ char *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can be appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ kbd_magic_keys = getenv("magic_keys");
+ if (kbd_magic_keys == NULL)
+ kbd_magic_keys = "";
+
+ /*
+ * loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix = kbd_magic_keys; *suffix ||
+ suffix == kbd_magic_keys; ++suffix) {
+ sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
+
+ if (compare_magic(kbd_data, getenv(magic)) == 0) {
+ char cmd_name[sizeof(kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
+ cmd = getenv(cmd_name);
+
+ return cmd;
+ }
+ }
+
+ return NULL;
+}
+#endif /* CONFIG_PREBOOT */
+
+int misc_init_r(void)
+{
+ char *s, buf[32];
+#ifdef CONFIG_PREBOOT
+ struct kbd_data_t kbd_data;
+ /* Decode keys */
+ char *str = strdup(key_match(get_keys(&kbd_data)));
+ /* Set or delete definition */
+ setenv("preboot", str);
+ free(str);
+#endif /* CONFIG_PREBOOT */
+
+ /* count all restarts, and save this in an environment var */
+ s = getenv("restartcount");
+
+ if (s)
+ sprintf(buf, "%ld", simple_strtoul(s, NULL, 10) + 1);
+ else
+ strcpy(buf, "1");
+
+ setenv("restartcount", buf);
+ saveenv();
+
+#ifdef CONFIG_HW_WATCHDOG
+ davinci_hw_watchdog_enable();
+#endif
+
+ return 0;
+}
+
+struct cmc_led {
+ char name[20];
+ unsigned char bank;
+ unsigned char gpio;
+};
+
+struct cmc_led led_table[] = {
+ {"led1", 1, 15},
+ {"led2", 0, 1},
+ {"led3", 0, 2},
+ {"led4", 0, 3},
+ {"led5", 0, 4},
+ {"led6", 0, 5},
+ {"led7", 0, 6},
+ {"led8", 0, 14},
+};
+
+static int cmc_get_led_state(struct cmc_led *led)
+{
+ int value;
+ int gpio = led->bank * 16 + led->gpio;
+
+ value = gpio_get_value(gpio);
+
+ return value;
+}
+
+static int cmc_set_led_state(struct cmc_led *led, int state)
+{
+ int gpio = led->bank * 16 + led->gpio;
+
+ gpio_set_value(gpio, state);
+ return 0;
+}
+
+static int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct cmc_led *led;
+ int found = 0;
+ int i = 0;
+ int only_print = 0;
+ int len = ARRAY_SIZE(led_table);
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ if (argc < 3)
+ only_print = 1;
+
+ led = led_table;
+ while ((!found) && (i < len)) {
+ if (strcmp(argv[1], led->name) == 0) {
+ found = 1;
+ } else {
+ led++;
+ i++;
+ }
+ }
+ if (!found)
+ return cmd_usage(cmdtp);
+
+ if (only_print) {
+ if (cmc_get_led_state(led))
+ printf("on\n");
+ else
+ printf("off\n");
+
+ return 0;
+ }
+ if (strcmp(argv[2], "on") == 0)
+ cmc_set_led_state(led, 1);
+ else
+ cmc_set_led_state(led, 0);
+
+ return 0;
+}
+
+U_BOOT_CMD(led, 3, 1, do_led,
+ "switch on/off board led",
+ "[name] [on/off]"
+);
+
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ davinci_hw_watchdog_reset();
+}
+#endif
+
+#if defined(CONFIG_POST)
+void arch_memory_failure_handle(void)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank01;
+ int state = 1;
+
+ /*
+ * if memor< failure blink with the LED 1,2 and 3
+ * as we running from flash, we cannot use the gpio
+ * api here, so access the gpio pin direct through
+ * the gpio register.
+ */
+ while (1) {
+ if (state) {
+ clrbits_le32(&gpio->out_data, 0x80000006);
+ state = 0;
+ } else {
+ setbits_le32(&gpio->out_data, 0x80000006);
+ state = 1;
+ }
+ udelay(500);
+ }
+}
+#endif
+
+ulong post_word_load(void)
+{
+ struct davinci_rtc *reg =
+ (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR;
+
+ return in_be32(®->scratch2);
+}
+
+void post_word_store(ulong value)
+{
+ struct davinci_rtc *reg =
+ (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR;
+
+ /*
+ * write RTC kick register to enable write
+ * for RTC Scratch registers. Cratch0 and 1 are
+ * used for bootcount values.
+ */
+ writel(RTC_KICK0R_WE, ®->kick0r);
+ writel(RTC_KICK1R_WE, ®->kick1r);
+ out_be32(®->scratch2, value);
+}
+
+void board_gpio_init(void)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank01;
+
+ /*
+ * set LED (gpio Interface not usable here)
+ * set LED pins to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x8000407e);
+ clrbits_le32(&gpio->out_data, 0x8000407e);
+ /* set LED 1 - 5 to state on */
+ setbits_le32(&gpio->out_data, 0x8000001e);
+
+ /*
+ * set some gpio pins to low, this is needed early,
+ * so we have no gpio Interface here
+ * gpios:
+ * 8[8] Mode PV select low
+ * 8[9] Debug Rx Enable low
+ * 8[10] Mode Select PV low
+ * 8[11] Counter Interface RS485 Rx-Enable low
+ */
+ gpio = davinci_gpio_bank8;
+ clrbits_le32(&gpio->dir, 0x00000f00);
+ clrbits_le32(&gpio->out_data, 0x0f00);
+}
+
+int board_late_init(void)
+{
+ cmc_set_led_state(&led_table[4], 0);
+
+ return 0;
+}
+
+void show_boot_progress(int val)
+{
+ switch (val) {
+ case 1:
+ cmc_set_led_state(&led_table[4], 1);
+ break;
+ case 4:
+ cmc_set_led_state(&led_table[4], 0);
+ break;
+ case 15:
+ cmc_set_led_state(&led_table[4], 1);
+ break;
+ }
+}
+
+#ifdef CONFIG_DAVINCI_MMC
+static struct davinci_mmc mmc_sd1 = {
+ .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE,
+ .input_clk = 228000000,
+ .host_caps = MMC_MODE_4BIT,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .version = MMC_CTLR_VERSION_2,
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ mmc_sd1.input_clk = clk_get(DAVINCI_MMC_CLKID);
+ /* Add slot-0 to mmc subsystem */
+ return davinci_mmc_init(bis, &mmc_sd1);
+}
+#endif
diff --git a/board/esd/apc405/Kconfig b/board/esd/apc405/Kconfig
new file mode 100644
index 0000000..6b03460
--- /dev/null
+++ b/board/esd/apc405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_APC405
+
+config SYS_BOARD
+ default "apc405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "APC405"
+
+endif
diff --git a/board/esd/apc405/MAINTAINERS b/board/esd/apc405/MAINTAINERS
new file mode 100644
index 0000000..7f2a33f
--- /dev/null
+++ b/board/esd/apc405/MAINTAINERS
@@ -0,0 +1,6 @@
+APC405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/apc405/
+F: include/configs/APC405.h
+F: configs/APC405_defconfig
diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile
new file mode 100644
index 0000000..ada8bfd
--- /dev/null
+++ b/board/esd/apc405/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = apc405.o \
+ ../common/misc.o \
+ ../common/auto_update.o
diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
new file mode 100644
index 0000000..5cc1d0d
--- /dev/null
+++ b/board/esd/apc405/apc405.c
@@ -0,0 +1,461 @@
+/*
+ * (C) Copyright 2005-2008
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <flash.h>
+#include <mtd/cfi_flash.h>
+#include <asm/4xx_pci.h>
+#include <pci.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef FPGA_DEBUG
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+#ifdef CONFIG_LCD_USED
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp[] =
+{
+#include "logo_640_480_24bpp.c"
+};
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+#include "../common/s1d13505_640_480_16bpp.h"
+#include "../common/s1d13806_640_480_16bpp.h"
+#endif /* CONFIG_LCD_USED */
+
+/*
+ * include common auto-update code (for esd boards)
+ */
+#include "../common/auto_update.h"
+
+au_image_t au_image[] = {
+ {"preinst.img", 0, -1, AU_SCRIPT},
+ {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
+ {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
+ {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
+ {"work.img", 0xfe500000, 0x01400000, AU_NOR},
+ {"data.img", 0xff900000, 0x00580000, AU_NOR},
+ {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
+ {"postinst.img", 0, 0, AU_SCRIPT},
+};
+
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+
+int board_revision(void)
+{
+ unsigned long CPC0_CR0Reg;
+ unsigned long value;
+
+ /*
+ * Get version of APC405 board from GPIO's
+ */
+
+ /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
+ out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
+
+ /* wait some time before reading input */
+ udelay(1000);
+
+ /* get config bits */
+ value = in_be32((void*)GPIO0_IR) & 0x001c0000;
+ /*
+ * Restore GPIO settings
+ */
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+ switch (value) {
+ case 0x001c0000:
+ /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
+ return 2;
+ case 0x000c0000:
+ /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
+ return 3;
+ case 0x00180000:
+ /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
+ return 6;
+ case 0x00140000:
+ /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
+ return 8;
+ default:
+ /* should not be reached! */
+ return 0;
+ }
+}
+
+int board_early_init_f (void)
+{
+ /*
+ * First pull fpga-prg pin low, to disable fpga logic
+ */
+ out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
+ out_be32((void*)GPIO0_OR, 0); /* pull prg low */
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks
+ */
+ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ /*
+ * New boards have a single 32MB flash connected to CS0
+ * instead of two 16MB flashes on CS0+1.
+ */
+ if (board_revision() >= 8) {
+ /* disable CS1 */
+ mtebc(PB1AP, 0);
+ mtebc(PB1CR, 0);
+
+ /* resize CS0 to 32MB */
+ mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
+ mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
+ }
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ if (gd->board_type >= 8)
+ cfi_flash_num_flash_banks = 1;
+
+ return 0;
+}
+
+#define FUJI_BASE 0xf0100200
+#define LCDBL_PWM 0xa0
+#define LCDBL_PWMMIN 0xa4
+#define LCDBL_PWMMAX 0xa8
+
+int misc_init_r(void)
+{
+ u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
+ u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
+ u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
+ u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
+ unsigned char *dst;
+ ulong len = sizeof(fpgadata);
+ int status;
+ int index;
+ int i;
+ unsigned long CPC0_CR0Reg;
+ char *str;
+ uchar *logo_addr;
+ ulong logo_size;
+ ushort minb, maxb;
+ int result;
+
+ /*
+ * Setup GPIO pins (CS6+CS7 as GPIO)
+ */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
+
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ printf("GUNZIP ERROR - must RESET board to recover\n");
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ status = fpga_boot(dst, len);
+ if (status != 0) {
+ printf("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf("(Timeout: "
+ "INIT not low after asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf("(Timeout: "
+ "INIT not high after deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf("(Timeout: "
+ "DONE not high after programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = dst[index];
+ printf("FPGA: %s\n", &(dst[index+1]));
+ index += len + 3;
+ }
+ putc('\n');
+ /* delayed reboot */
+ for (i = 20; i > 0; i--) {
+ printf("Rebooting in %2d seconds \r",i);
+ for (index = 0; index < 1000; index++)
+ udelay(1000);
+ }
+ putc('\n');
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ /* restore gpio/cs settings */
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+ puts("FPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = dst[index];
+ printf("%s ", &(dst[index + 1]));
+ index += len + 3;
+ }
+ putc('\n');
+
+ free(dst);
+
+ /*
+ * Reset FPGA via FPGA_DATA pin
+ */
+ SET_FPGA(FPGA_PRG | FPGA_CLK);
+ udelay(1000); /* wait 1ms */
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+ udelay(1000); /* wait 1ms */
+
+ /*
+ * Write board revision in FPGA
+ */
+ out_be16(fpga_ctrl2,
+ (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
+
+ /*
+ * Enable power on PS/2 interface (with reset)
+ */
+ out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
+ for (i=0;i<100;i++)
+ udelay(1000);
+ udelay(1000);
+ out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
+
+ /*
+ * Enable interrupts in exar duart mcr[3]
+ */
+ out_8(duart0_mcr, 0x08);
+ out_8(duart1_mcr, 0x08);
+
+ /*
+ * Init lcd interface and display logo
+ */
+ str = getenv("splashimage");
+ if (str) {
+ logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
+ logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
+ } else {
+ logo_addr = logo_bmp;
+ logo_size = sizeof(logo_bmp);
+ }
+
+ if (gd->board_type >= 6) {
+ result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+ (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+ regs_13505_640_480_16bpp,
+ sizeof(regs_13505_640_480_16bpp) /
+ sizeof(regs_13505_640_480_16bpp[0]),
+ logo_addr, logo_size);
+ if (result && str) {
+ /* retry with internal image */
+ logo_addr = logo_bmp;
+ logo_size = sizeof(logo_bmp);
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+ (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+ regs_13505_640_480_16bpp,
+ sizeof(regs_13505_640_480_16bpp) /
+ sizeof(regs_13505_640_480_16bpp[0]),
+ logo_addr, logo_size);
+ }
+ } else {
+ result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+ (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+ regs_13806_640_480_16bpp,
+ sizeof(regs_13806_640_480_16bpp) /
+ sizeof(regs_13806_640_480_16bpp[0]),
+ logo_addr, logo_size);
+ if (result && str) {
+ /* retry with internal image */
+ logo_addr = logo_bmp;
+ logo_size = sizeof(logo_bmp);
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+ (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+ regs_13806_640_480_16bpp,
+ sizeof(regs_13806_640_480_16bpp) /
+ sizeof(regs_13806_640_480_16bpp[0]),
+ logo_addr, logo_size);
+ }
+ }
+
+ /*
+ * Reset microcontroller and setup backlight PWM controller
+ */
+ out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
+ for (i=0;i<10;i++)
+ udelay(1000);
+ out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
+
+ minb = 0;
+ maxb = 0xff;
+ str = getenv("lcdbl");
+ if (str) {
+ minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
+ if (str && (*str=',')) {
+ str++;
+ maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
+ } else
+ minb = 0;
+
+ out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
+ out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
+
+ printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
+ }
+ out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
+
+ /*
+ * fix environment for field updated units
+ */
+ if (getenv("altbootcmd") == NULL) {
+ setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
+ setenv("usbargs", CONFIG_SYS_USB_ARGS);
+ setenv("bootcmd", CONFIG_BOOTCOMMAND);
+ setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
+ setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
+ setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
+ saveenv();
+ }
+
+ return (0);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming APC405");
+ } else {
+ puts(str);
+ }
+
+ gd->board_type = board_revision();
+ printf(", Rev. 1.%ld\n", gd->board_type);
+
+ return 0;
+}
+
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+ u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
+
+ /*
+ * Assert or deassert CompactFlash Reset Pin
+ */
+ if (on) {
+ out_be16(fpga_mode,
+ in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
+ } else {
+ out_be16(fpga_mode,
+ in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
+ }
+}
+#endif /* CONFIG_IDE_RESET */
+
+void reset_phy(void)
+{
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+}
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+int usb_board_stop(void)
+{
+ unsigned short tmp;
+ int i;
+
+ /*
+ * reset PCI bus
+ * This is required to make some very old Linux OHCI driver
+ * work after U-Boot has used the OHCI controller.
+ */
+ pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
+ pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
+
+ for (i = 0; i < 100; i++)
+ udelay(1000);
+
+ pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return usb_board_stop();
+}
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
diff --git a/board/esd/apc405/fpgadata.c b/board/esd/apc405/fpgadata.c
new file mode 100644
index 0000000..b68668c
--- /dev/null
+++ b/board/esd/apc405/fpgadata.c
@@ -0,0 +1,4008 @@
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diff --git a/board/esd/apc405/logo_640_480_24bpp.c b/board/esd/apc405/logo_640_480_24bpp.c
new file mode 100644
index 0000000..a218032
--- /dev/null
+++ b/board/esd/apc405/logo_640_480_24bpp.c
@@ -0,0 +1,1129 @@
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diff --git a/board/esd/ar405/Kconfig b/board/esd/ar405/Kconfig
new file mode 100644
index 0000000..4ad9d51
--- /dev/null
+++ b/board/esd/ar405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AR405
+
+config SYS_BOARD
+ default "ar405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "AR405"
+
+endif
diff --git a/board/esd/ar405/MAINTAINERS b/board/esd/ar405/MAINTAINERS
new file mode 100644
index 0000000..be74ff7
--- /dev/null
+++ b/board/esd/ar405/MAINTAINERS
@@ -0,0 +1,6 @@
+AR405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/ar405/
+F: include/configs/AR405.h
+F: configs/AR405_defconfig
diff --git a/board/esd/ar405/Makefile b/board/esd/ar405/Makefile
new file mode 100644
index 0000000..dd54f54
--- /dev/null
+++ b/board/esd/ar405/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ar405.o flash.o ../common/misc.o
diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c
new file mode 100644
index 0000000..d33aba4
--- /dev/null
+++ b/board/esd/ar405/ar405.c
@@ -0,0 +1,394 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "ar405.h"
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+const unsigned char fpgadata_xl30[] = {
+#include "fpgadata_xl30.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+ int index, len, i;
+ int status;
+
+#ifdef FPGA_DEBUG
+ /* set up serial port with default baudrate */
+ (void) get_clocks ();
+ gd->baudrate = CONFIG_BAUDRATE;
+ serial_init ();
+ console_init_f ();
+#endif
+
+ /*
+ * Boot onboard FPGA
+ */
+ /* first try 40er image */
+ gd->board_type = 40;
+ status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+ if (status != 0) {
+ /* try xl30er image */
+ gd->board_type = 30;
+ status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
+ if (status != 0) {
+ /* booting FPGA failed */
+#ifndef FPGA_DEBUG
+ /* set up serial port with default baudrate */
+ (void) get_clocks ();
+ gd->baudrate = CONFIG_BAUDRATE;
+ serial_init ();
+ console_init_f ();
+#endif
+ printf ("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf ("(Timeout: DONE not high after programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = fpgadata[index];
+ printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+ index += len + 3;
+ }
+ putc ('\n');
+ /* delayed reboot */
+ for (i = 20; i > 0; i--) {
+ printf ("Rebooting in %2d seconds \r", i);
+ for (index = 0; index < 1000; index++)
+ udelay (1000);
+ }
+ putc ('\n');
+ do_reset (NULL, 0, 0, NULL);
+ }
+ }
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ int index;
+ int len;
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof (str));
+ const unsigned char *fpga;
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming AR405");
+ } else {
+ puts(str);
+ }
+
+ puts ("\nFPGA: ");
+
+ /* display infos on fpgaimage */
+ if (gd->board_type == 30) {
+ fpga = fpgadata_xl30;
+ } else {
+ fpga = fpgadata;
+ }
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = fpga[index];
+ printf ("%s ", &(fpga[index + 1]));
+ index += len + 3;
+ }
+
+ putc ('\n');
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+
+ return 0;
+}
+
+
+#if 1 /* test-only: some internal test routines... */
+#define DIGEN ((void *)0xf03000b4) /* u8 */
+#define DIGOUT ((void *)0xf03000b0) /* u16 */
+#define DIGIN ((void *)0xf03000a0) /* u16 */
+
+/*
+ * Some test routines
+ */
+int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i;
+ int k;
+ int start;
+ int end;
+
+ if (argc != 3) {
+ puts("Usage: digtest n_start n_end (digtest 0 7)\n");
+ return 0;
+ }
+
+ start = simple_strtol (argv[1], NULL, 10);
+ end = simple_strtol (argv[2], NULL, 10);
+
+ /*
+ * Enable digital outputs
+ */
+ out_8(DIGEN, 0x08);
+
+ printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n",
+ start, end);
+
+ /*
+ * Set outputs one by one
+ */
+ for (;;) {
+ for (i=start; i<=end; i++) {
+ out_be16(DIGOUT, 0x0001 << i);
+ for (k=0; k<200; k++)
+ udelay(1000);
+
+ if (in_be16(DIGIN) != (0x0001 << i)) {
+ printf("ERROR: OUT=0x%04X, IN=0x%04X\n",
+ 0x0001 << i, in_be16(DIGIN));
+ return 0;
+ }
+
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return 0;
+ }
+ }
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ digtest, 3, 1, do_digtest,
+ "Test digital in-/output",
+ ""
+);
+
+#define ERROR_DELTA 256
+
+struct io {
+ short val;
+ short dummy;
+};
+
+int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ short val;
+ int i;
+ int volt;
+ struct io *out;
+ struct io *in;
+
+ out = (struct io *)0xf0300090;
+ in = (struct io *)0xf0300000;
+
+ i = simple_strtol (argv[1], NULL, 10);
+
+ volt = 0;
+ printf("Setting Channel %d to %dV...\n", i, volt);
+ out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
+ udelay(10000);
+ val = in_be16((void *)&(in[i*2].val));
+ printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+ if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+ (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+ printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+ ((volt * 0x7fff) / 40) + ERROR_DELTA);
+ return -1;
+ }
+ val = in_be16((void *)&(in[i*2+1].val));
+ printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+ if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+ (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+ printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+ ((volt * 0x7fff) / 40) + ERROR_DELTA);
+ return -1;
+ }
+
+ volt = 5;
+ printf("Setting Channel %d to %dV...\n", i, volt);
+ out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
+ udelay(10000);
+ val = in_be16((void *)&(in[i*2].val));
+ printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+ if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+ (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+ printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+ ((volt * 0x7fff) / 40) + ERROR_DELTA);
+ return -1;
+ }
+ val = in_be16((void *)&(in[i*2+1].val));
+ printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+ if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+ (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+ printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+ ((volt * 0x7fff) / 40) + ERROR_DELTA);
+ return -1;
+ }
+
+ volt = 10;
+ printf("Setting Channel %d to %dV...\n", i, volt);
+ out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
+ udelay(10000);
+ val = in_be16((void *)&(in[i*2].val));
+ printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+ if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+ (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+ printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+ ((volt * 0x7fff) / 40) + ERROR_DELTA);
+ return -1;
+ }
+ val = in_be16((void *)&(in[i*2+1].val));
+ printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+ if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+ (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+ printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+ ((volt * 0x7fff) / 40) + ERROR_DELTA);
+ return -1;
+ }
+
+ printf("Channel %d OK!\n", i);
+
+ return 0;
+}
+U_BOOT_CMD(
+ anatest, 2, 1, do_anatest,
+ "Test analog in-/output",
+ ""
+);
+
+
+int counter = 0;
+
+void cyclicInt(void *ptr)
+{
+ out_be16((void *)0xf03000e8, 0x0800); /* ack int */
+ counter++;
+}
+
+
+int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong *incin;
+ int i;
+
+ incin = (ulong *)0xf0300040;
+
+ /*
+ * Clear inc counter
+ */
+ out_be32((void *)&incin[0], 0);
+ out_be32((void *)&incin[1], 0);
+ out_be32((void *)&incin[2], 0);
+ out_be32((void *)&incin[3], 0);
+
+ incin = (ulong *)0xf0300050;
+
+ /*
+ * Inc a little
+ */
+ for (i=0; i<10000; i++) {
+ switch (i & 0x03) {
+ case 0:
+ out_8(DIGEN, 0x02);
+ break;
+ case 1:
+ out_8(DIGEN, 0x03);
+ break;
+ case 2:
+ out_8(DIGEN, 0x01);
+ break;
+ case 3:
+ out_8(DIGEN, 0x00);
+ break;
+ }
+ udelay(10);
+ }
+
+ printf("Inc 0 = %d\n", in_be32((void *)&incin[0]));
+ printf("Inc 1 = %d\n", in_be32((void *)&incin[1]));
+ printf("Inc 2 = %d\n", in_be32((void *)&incin[2]));
+ printf("Inc 3 = %d\n", in_be32((void *)&incin[3]));
+
+ out_be16((void *)0xf03000e0, 0x0c80-1); /* set counter */
+ out_be16((void *)0xf03000ec,
+ in_be16((void *)0xf03000ec) | 0x0800); /* enable int */
+ irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL);
+ printf("counter=%d\n", counter);
+
+ return 0;
+}
+U_BOOT_CMD(
+ inctest, 3, 1, do_inctest,
+ "Test incremental encoder inputs",
+ ""
+);
+#endif
diff --git a/board/esd/ar405/ar405.h b/board/esd/ar405/ar405.h
new file mode 100644
index 0000000..75e7950
--- /dev/null
+++ b/board/esd/ar405/ar405.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ * Start Address Length
+ * +-----------------------+ 0x4000_0000 Start of Flash -----------------
+ * | MON8xx code | 0x4000_0100 Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused) |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses | 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) | 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address | 0x04
+ * +-----------------------+ 0x4001_FFC0 ^
+ * | Hardware Information | 0x40 | MON8xx
+ * +=======================+ 0x4002_0000 (sector border) -----------------
+ * | Autostart Header | | Applications
+ * | ... | v
+ *
+ *****************************************************************************/
diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c
new file mode 100644
index 0000000..23e8164
--- /dev/null
+++ b/board/esd/ar405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b0 = -size_b0;
+ switch (size_b0) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/ar405/fpgadata.c b/board/esd/ar405/fpgadata.c
new file mode 100644
index 0000000..055ab6b
--- /dev/null
+++ b/board/esd/ar405/fpgadata.c
@@ -0,0 +1,5500 @@
+0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
+0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0d,
+0x70, 0x70, 0x63, 0x5f, 0x61, 0x72, 0x30, 0x31,
+0x2e, 0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b,
+0x73, 0x34, 0x30, 0x78, 0x6c, 0x70, 0x71, 0x32,
+0x34, 0x30, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30,
+0x30, 0x31, 0x2f, 0x30, 0x32, 0x2f, 0x31, 0x34,
+0x00, 0x64, 0x00, 0x09, 0x31, 0x35, 0x3a, 0x34,
+0x30, 0x3a, 0x30, 0x34, 0x00, 0x65, 0xe2, 0x01,
+0x00, 0x00, 0xab, 0x8e, 0xff, 0x30, 0xe5, 0xe5,
+0xe8, 0xe5, 0x03, 0xe8, 0x04, 0x01, 0x02, 0x11,
+0x09, 0x09, 0x01, 0x07, 0x02, 0x04, 0x04, 0x06,
+0x09, 0x07, 0x04, 0x04, 0x04, 0x04, 0x03, 0x07,
+0x02, 0x04, 0x09, 0x04, 0x04, 0x0b, 0x09, 0x09,
+0x03, 0x07, 0x02, 0x09, 0x04, 0x04, 0x04, 0x04,
+0x0e, 0x04, 0x04, 0x09, 0x03, 0x07, 0x02, 0x04,
+0x03, 0x03, 0x03, 0x07, 0xe5, 0x01, 0x0d, 0x02,
+0x02, 0x03, 0x02, 0x02, 0x03, 0x02, 0x02, 0x03,
+0x19, 0x03, 0x02, 0x02, 0x03, 0x02, 0x08, 0x09,
+0x07, 0x13, 0x03, 0x11, 0x02, 0x06, 0x03, 0x05,
+0x03, 0x05, 0x11, 0x1d, 0x1f, 0x13, 0x10, 0x01,
+0x01, 0xe3, 0x4c, 0xe5, 0x01, 0x0a, 0x04, 0x01,
+0xe5, 0x05, 0x01, 0xe5, 0x05, 0x01, 0xe5, 0x05,
+0x09, 0x04, 0x04, 0x02, 0x06, 0x01, 0xe5, 0x05,
+0x01, 0x02, 0x04, 0x04, 0x04, 0x09, 0x09, 0x09,
+0x09, 0x04, 0x06, 0x01, 0x07, 0x09, 0x04, 0x04,
+0x09, 0x06, 0x02, 0x09, 0x09, 0x04, 0x01, 0xe7,
+0x03, 0x04, 0x07, 0xe6, 0x08, 0x09, 0x09, 0x0e,
+0x01, 0xe6, 0x13, 0x09, 0x09, 0x09, 0x03, 0x05,
+0x03, 0x05, 0x09, 0x09, 0x09, 0x09, 0xe5, 0x07,
+0x03, 0x05, 0xe5, 0x07, 0xe5, 0x01, 0x05, 0x0b,
+0xe5, 0x07, 0xe5, 0x07, 0x09, 0x03, 0x05, 0xe6,
+0xe5, 0x04, 0xe5, 0x01, 0x05, 0xe5, 0x01, 0x05,
+0xe5, 0xe6, 0x04, 0x03, 0x05, 0xe5, 0xe6, 0x04,
+0xe5, 0x07, 0x03, 0x05, 0xe5, 0x07, 0x0b, 0x01,
+0x0e, 0x05, 0x03, 0x05, 0x03, 0x05, 0x1d, 0x03,
+0x05, 0x03, 0x44, 0xe5, 0xe5, 0x2e, 0x1c, 0x01,
+0x13, 0x32, 0x01, 0xe3, 0x4d, 0xe5, 0x0f, 0x09,
+0x09, 0x27, 0x09, 0x42, 0x04, 0x4a, 0x44, 0x01,
+0x01, 0x01, 0x12, 0x09, 0x09, 0x01, 0x06, 0x01,
+0x12, 0x09, 0x0a, 0x09, 0x11, 0x21, 0x13, 0x11,
+0x15, 0x1d, 0x1b, 0x0c, 0x0d, 0x03, 0x03, 0x01,
+0x31, 0x31, 0x47, 0x81, 0xe5, 0xe5, 0xe5, 0x77,
+0x3e, 0xe5, 0x19, 0xe5, 0x1b, 0x3b, 0xe5, 0xe5,
+0x5a, 0x3d, 0x1f, 0x74, 0xe6, 0xe5, 0x28, 0x5b,
+0x09, 0xe5, 0x0a, 0x08, 0xe5, 0x08, 0x1d, 0x11,
+0xe6, 0x37, 0x12, 0x01, 0x01, 0x09, 0x06, 0x09,
+0x09, 0x09, 0xe5, 0x07, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x01, 0x03, 0x03, 0x03, 0x05,
+0x05, 0x05, 0x09, 0x09, 0x09, 0x09, 0x09, 0xe5,
+0x07, 0x09, 0x09, 0x09, 0x05, 0x03, 0x09, 0x09,
+0x09, 0x10, 0xe5, 0x0f, 0x09, 0x09, 0x04, 0x04,
+0x09, 0x09, 0x05, 0x03, 0x05, 0x03, 0x01, 0x07,
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diff --git a/board/esd/ar405/fpgadata_xl30.c b/board/esd/ar405/fpgadata_xl30.c
new file mode 100644
index 0000000..42a9206
--- /dev/null
+++ b/board/esd/ar405/fpgadata_xl30.c
@@ -0,0 +1,4872 @@
+0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
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+0x04, 0x04, 0x05, 0x05, 0x02, 0x13, 0x0a, 0x03,
+0x18, 0x09, 0x0b, 0xe5, 0x04, 0x02, 0x09, 0x01,
+0x07, 0x07, 0x01, 0x07, 0x08, 0xe5, 0xe5, 0x02,
+0x01, 0x01, 0x01, 0x04, 0x0e, 0x09, 0x09, 0x0f,
+0x01, 0xe5, 0x0b, 0xe6, 0x07, 0xe5, 0x05, 0x01,
+0xe5, 0x02, 0x04, 0xe5, 0x07, 0xe5, 0x04, 0x02,
+0xe5, 0x04, 0x02, 0xe5, 0x04, 0x02, 0xe5, 0x07,
+0xe6, 0x06, 0xe6, 0x06, 0xe5, 0x07, 0xe5, 0x08,
+0xe6, 0x07, 0xe5, 0x07, 0xe5, 0x06, 0xe6, 0x07,
+0x13, 0x03, 0x03, 0x0b, 0xe5, 0x01, 0x05, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x0e, 0x01, 0xe6, 0x02,
+0x09, 0x01, 0x07, 0x05, 0x03, 0x01, 0x07, 0x07,
+0x01, 0x01, 0x07, 0x08, 0xe5, 0xe5, 0x06, 0x09,
+0x04, 0x04, 0x09, 0x09, 0x0a, 0xe5, 0x02, 0x05,
+0x09, 0x05, 0x03, 0x12, 0x0c, 0x04, 0x05, 0x06,
+0x08, 0xe5, 0x08, 0x09, 0x0b, 0x06, 0x01, 0x0e,
+0xe5, 0x07, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
+0x07, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5,
+0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05,
+0x09, 0x09, 0x09, 0xe5, 0x07, 0x02, 0x06, 0xe5,
+0xe5, 0x05, 0xe5, 0xe5, 0x0b, 0x02, 0xe5, 0x0d,
+0x02, 0x06, 0x01, 0x07, 0x09, 0x01, 0x02, 0x04,
+0x09, 0x01, 0x07, 0x09, 0x01, 0x07, 0x03, 0x05,
+0x05, 0x03, 0x02, 0x06, 0x0b, 0x04, 0x04, 0x09,
+0x1f, 0x07, 0x13, 0x09, 0x09, 0x09, 0x02, 0x10,
+0x12, 0x44, 0x02, 0x04, 0xe5, 0x04, 0x02, 0xe5,
+0x18, 0x25, 0x01, 0x01, 0x21, 0x2f, 0x05, 0x01,
+0x01, 0x0e, 0x09, 0x02, 0x06, 0x02, 0x06, 0x09,
+0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0x04, 0x09,
+0x09, 0x09, 0x01, 0xe5, 0x05, 0x05, 0x03, 0x02,
+0x05, 0x02, 0x09, 0x02, 0xe5, 0x04, 0x04, 0x03,
+0xe5, 0x07, 0x03, 0x05, 0xe5, 0x08, 0x05, 0x02,
+0xe5, 0x02, 0x03, 0x01, 0x04, 0x04, 0x09, 0x09,
+0x09, 0x06, 0xe5, 0xe5, 0x06, 0x18, 0x09, 0x09,
+0x1d, 0x0f, 0x13, 0x03, 0x0a, 0x0a, 0x04, 0x10,
+0x09, 0x06, 0xe5, 0xe5, 0x4a, 0xe5, 0x01, 0x07,
+0x08, 0xe5, 0x07, 0x09, 0x09, 0x03, 0x05, 0x09,
+0x09, 0xe5, 0x07, 0x09, 0x09, 0x09, 0x05, 0x03,
+0x06, 0xe5, 0x02, 0x09, 0x09, 0x09, 0xe5, 0x07,
+0x07, 0x01, 0x01, 0x07, 0x01, 0x07, 0x05, 0x03,
+0x01, 0x07, 0x09, 0x09, 0x0e, 0x01, 0xe5, 0x03,
+0x61, 0x11, 0x01, 0x07, 0x0b, 0x09, 0x09, 0x03,
+0x05, 0x02, 0xe5, 0x05, 0x15, 0x3b, 0xe5, 0x14,
+0x13, 0x13, 0x09, 0x14, 0x09, 0x0d, 0x09, 0x06,
+0x04, 0x09, 0x04, 0xe5, 0x02, 0x04, 0x04, 0x18,
+0x13, 0x09, 0x27, 0xe5, 0xe5, 0x09, 0x17, 0x06,
+0x02, 0x4f, 0x4f, 0x09, 0x2b, 0x05, 0xe6, 0x0a,
+0x3b, 0x27, 0x5b, 0x3c, 0xe6, 0x3c, 0x5b, 0x1e,
+0x26, 0x27, 0xe5, 0xe5, 0x03, 0x10, 0x31, 0x2a,
+0x05, 0x03, 0x05, 0x02, 0x02, 0x05, 0x03, 0x05,
+0x03, 0x05, 0xe5, 0x01, 0x05, 0x14, 0x13, 0x29,
+0x06, 0xe5, 0xe6, 0x46, 0x27, 0x15, 0x46, 0x33,
+0x05, 0xe5, 0x01, 0x04, 0x57, 0xa9, 0x03, 0x14,
+0x09, 0x09, 0x09, 0x09, 0x09, 0xe6, 0x06, 0x09,
+0xe6, 0x06, 0x09, 0xe6, 0x06, 0x09, 0x0b, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0xe6, 0x06, 0x09,
+0x09, 0x09, 0x09, 0x0a, 0x02, 0x05, 0x09, 0x08,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x05, 0x01, 0xe5, 0x07, 0xe5, 0x05, 0x01,
+0xe5, 0x07, 0xe5, 0x05, 0x02, 0x09, 0x07, 0x03,
+0x09, 0x09, 0x09, 0x09, 0x04, 0x03, 0xe5, 0x07,
+0xe5, 0x05, 0x01, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x08, 0x09, 0x10, 0xe6, 0x15, 0x05, 0x03, 0x05,
+0x03, 0x05, 0x03, 0x05, 0x03, 0x05, 0x03, 0x05,
+0x03, 0x05, 0x03, 0x09, 0x05, 0x03, 0x04, 0x09,
+0x05, 0x05, 0x09, 0x09, 0x09, 0x14, 0x03, 0x09,
+0x05, 0x03, 0x09, 0x27, 0x01, 0x0d, 0x03, 0x03,
+0x05, 0x03, 0x05, 0x03, 0x05, 0x03, 0x05, 0x03,
+0x09, 0x05, 0x03, 0x09, 0x05, 0x03, 0x09, 0x01,
+0x04, 0x04, 0x04, 0x06, 0x04, 0x04, 0x04, 0x04,
+0x04, 0x04, 0x04, 0x06, 0x0b, 0x03, 0x09, 0x09,
+0x09, 0x09, 0x03, 0x05, 0x03, 0x0d, 0x02, 0x01,
+0x0b, 0x06, 0x01, 0x02, 0x01, 0x04, 0x02, 0x01,
+0x04, 0x02, 0x01, 0x04, 0x02, 0x01, 0x04, 0x02,
+0x01, 0x01, 0x05, 0x01, 0x04, 0x02, 0x01, 0x01,
+0x05, 0x01, 0x02, 0x01, 0x02, 0x01, 0x01, 0xe5,
+0x06, 0x02, 0x02, 0x03, 0x02, 0x02, 0x05, 0x02,
+0x02, 0x03, 0x02, 0x02, 0x03, 0x02, 0x02, 0x03,
+0x02, 0x02, 0x02, 0x04, 0x02, 0x01, 0x04, 0x02,
+0x01, 0x01, 0xe5, 0x03, 0x01, 0x01, 0x02, 0x04,
+0x02, 0x01, 0x02, 0x01, 0x01, 0x02, 0x04, 0x04,
+0x04, 0x06, 0x02, 0x02, 0xe6, 0xe5, 0xe5, 0xff,
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
diff --git a/board/esd/ash405/Kconfig b/board/esd/ash405/Kconfig
new file mode 100644
index 0000000..02c7c14
--- /dev/null
+++ b/board/esd/ash405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ASH405
+
+config SYS_BOARD
+ default "ash405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "ASH405"
+
+endif
diff --git a/board/esd/ash405/MAINTAINERS b/board/esd/ash405/MAINTAINERS
new file mode 100644
index 0000000..a9dae90
--- /dev/null
+++ b/board/esd/ash405/MAINTAINERS
@@ -0,0 +1,6 @@
+ASH405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/ash405/
+F: include/configs/ASH405.h
+F: configs/ASH405_defconfig
diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile
new file mode 100644
index 0000000..aab8de4
--- /dev/null
+++ b/board/esd/ash405/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ash405.o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c
new file mode 100644
index 0000000..4460a19
--- /dev/null
+++ b/board/esd/ash405/ash405.c
@@ -0,0 +1,182 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ */
+ mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ unsigned char *dst;
+ ulong len = sizeof(fpgadata);
+ int status;
+ int index;
+ int i;
+
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ printf ("GUNZIP ERROR - must RESET board to recover\n");
+ do_reset (NULL, 0, 0, NULL);
+ }
+
+ status = fpga_boot(dst, len);
+ if (status != 0) {
+ printf("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf("(Timeout: DONE not high after programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("FPGA: %s\n", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+ /* delayed reboot */
+ for (i=20; i>0; i--) {
+ printf("Rebooting in %2d seconds \r",i);
+ for (index=0;index<1000;index++)
+ udelay(1000);
+ }
+ putc ('\n');
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ puts("FPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("%s ", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+
+ free(dst);
+
+ /*
+ * Reset FPGA via FPGA_DATA pin
+ */
+ SET_FPGA(FPGA_PRG | FPGA_CLK);
+ udelay(1000); /* wait 1ms */
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+ udelay(1000); /* wait 1ms */
+
+ /*
+ * Reset external DUARTs
+ */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
+ udelay(10); /* wait 10us */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
+ udelay(1000); /* wait 1ms */
+
+ /*
+ * Enable interrupts in exar duart mcr[3]
+ */
+ out_8((void *)(DUART0_BA + 4), 0x08);
+ out_8((void *)(DUART1_BA + 4), 0x08);
+ out_8((void *)(DUART2_BA + 4), 0x08);
+ out_8((void *)(DUART3_BA + 4), 0x08);
+
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming ASH405");
+ } else {
+ puts(str);
+ }
+
+ putc ('\n');
+
+ return 0;
+}
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c
new file mode 100644
index 0000000..23e8164
--- /dev/null
+++ b/board/esd/ash405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b0 = -size_b0;
+ switch (size_b0) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/ash405/fpgadata.c b/board/esd/ash405/fpgadata.c
new file mode 100644
index 0000000..6e29053
--- /dev/null
+++ b/board/esd/ash405/fpgadata.c
@@ -0,0 +1,4983 @@
+0x1f, 0x8b, 0x08, 0x08, 0x5c, 0xa1, 0x5d, 0x3f,
+0x00, 0x03, 0x61, 0x73, 0x68, 0x34, 0x30, 0x35,
+0x5f, 0x31, 0x5f, 0x30, 0x32, 0x2e, 0x62, 0x69,
+0x74, 0x00, 0xec, 0xfd, 0x0f, 0x78, 0x1c, 0xe5,
+0x91, 0x2f, 0x0a, 0x57, 0xbf, 0xdd, 0x92, 0x5f,
+0x4d, 0x8f, 0x34, 0xad, 0x91, 0x4c, 0x14, 0x30,
+0xa6, 0x35, 0x92, 0xcd, 0x58, 0x19, 0xc9, 0xe3,
+0x91, 0x90, 0x85, 0x10, 0xa3, 0xb6, 0x24, 0x58,
+0x45, 0x36, 0x58, 0x71, 0xd8, 0x2c, 0x67, 0x97,
+0x93, 0x1d, 0x88, 0x93, 0xe3, 0xdd, 0x75, 0x72,
+0x1c, 0x36, 0x37, 0xc7, 0x21, 0x6c, 0xf2, 0x6a,
+0x24, 0xe3, 0xb1, 0x65, 0xe3, 0xc1, 0x38, 0xc1,
+0x04, 0x92, 0x3b, 0xfe, 0x43, 0x10, 0xe0, 0x24,
+0x63, 0xd9, 0x60, 0x19, 0x1b, 0x68, 0x09, 0x41,
+0xc6, 0xb6, 0xb0, 0x15, 0xc7, 0x9b, 0x35, 0xc4,
+0x0b, 0x63, 0x50, 0x88, 0x30, 0x82, 0xc8, 0xe0,
+0x24, 0xb2, 0x2d, 0xec, 0x5b, 0xd5, 0x23, 0xcd,
+0xf4, 0x38, 0x7b, 0xf6, 0xec, 0xde, 0xf3, 0xdc,
+0xef, 0xdb, 0xef, 0xbb, 0xab, 0x73, 0x9e, 0x67,
+0x2b, 0xdd, 0xed, 0xa6, 0xfb, 0x9d, 0xb7, 0xab,
+0x7e, 0x55, 0xf5, 0xab, 0x2a, 0xc8, 0x73, 0x8d,
+0xa7, 0xfe, 0x1f, 0x80, 0x74, 0x37, 0x68, 0x77,
+0xff, 0xfd, 0x8a, 0x1a, 0xff, 0x0d, 0x7f, 0xbd,
+0xe0, 0xaf, 0xfd, 0x81, 0xaa, 0xaf, 0x7d, 0x69,
+0x39, 0xdc, 0x03, 0x6a, 0xe0, 0xef, 0x6f, 0xf0,
+0x7f, 0xf9, 0x1b, 0x5f, 0x5f, 0x50, 0x53, 0x03,
+0x5f, 0xc2, 0xff, 0xe5, 0xf7, 0x57, 0xcf, 0xf7,
+0xdf, 0x88, 0xff, 0x1f, 0x96, 0x43, 0xde, 0x82,
+0x05, 0xf5, 0x35, 0xb5, 0xf5, 0xfe, 0x1a, 0xf8,
+0x32, 0x48, 0xd5, 0x3b, 0x2f, 0xe3, 0xdf, 0xd3,
+0x8f, 0xfe, 0xf9, 0x57, 0xfc, 0x20, 0x24, 0x00,
+0x98, 0xe1, 0x97, 0x42, 0xf4, 0x7f, 0x55, 0xbf,
+0xa4, 0x4b, 0x20, 0x1a, 0x2b, 0xfd, 0x60, 0xd2,
+0xff, 0x86, 0xa9, 0xf3, 0x79, 0x7e, 0xd0, 0xed,
+0xff, 0x5b, 0xf2, 0x83, 0x01, 0xed, 0x60, 0x6c,
+0x00, 0xb7, 0x1f, 0xfe, 0xd7, 0x7f, 0x86, 0x22,
+0xa6, 0xc5, 0x7f, 0xe7, 0xf5, 0x97, 0x0f, 0x8b,
+0xff, 0xe9, 0x55, 0x99, 0xbf, 0xc6, 0x8f, 0x62,
+0xd3, 0x22, 0xfb, 0x37, 0xdc, 0x5f, 0x32, 0x20,
+0x7d, 0xff, 0x37, 0xfe, 0x4d, 0xf7, 0xff, 0xc3,
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+0x24, 0xd3, 0x98, 0x32, 0x20, 0xd2, 0xf7, 0x49,
+0xf1, 0x7c, 0x04, 0xfd, 0x82, 0x01, 0xdd, 0xc8,
+0x55, 0x31, 0x1f, 0x6a, 0x2c, 0x24, 0x50, 0x4c,
+0x4c, 0x36, 0xdd, 0x94, 0xff, 0x36, 0xd2, 0x60,
+0x3f, 0xac, 0xe1, 0x95, 0x1a, 0x41, 0xf1, 0xad,
+0x09, 0x1f, 0x8e, 0x4f, 0x19, 0x95, 0x5d, 0xdf,
+0x45, 0x4b, 0xee, 0xf6, 0x16, 0xc3, 0xb6, 0xed,
+0xdc, 0xd2, 0xc6, 0x75, 0x6e, 0x15, 0x3e, 0x12,
+0x68, 0x02, 0x67, 0x2c, 0x77, 0xc5, 0xa2, 0x6a,
+0x5f, 0xae, 0x8c, 0xb2, 0xf5, 0x8b, 0x16, 0x10,
+0x1f, 0x9e, 0x41, 0x1a, 0xcc, 0x91, 0x79, 0xc1,
+0x2d, 0x66, 0x26, 0xbf, 0x1d, 0x1b, 0x23, 0x4f,
+0x02, 0x5f, 0xf3, 0xe7, 0xd3, 0xae, 0xc8, 0xf8,
+0x13, 0x56, 0x63, 0x62, 0x3c, 0x77, 0x17, 0xf9,
+0x90, 0x8c, 0x73, 0x9c, 0x1d, 0x2f, 0xc4, 0xe0,
+0x38, 0x7f, 0x3a, 0xf2, 0x00, 0xcd, 0x2b, 0x3a,
+0x7f, 0x3e, 0xcc, 0x5a, 0x62, 0x63, 0x8c, 0x07,
+0x27, 0xf0, 0x76, 0xe4, 0x86, 0x85, 0x43, 0xf8,
+0x16, 0xcd, 0x33, 0x61, 0xc1, 0x15, 0x9f, 0xc9,
+0xb8, 0x05, 0x8d, 0x5e, 0xe4, 0x9a, 0xf9, 0xe3,
+0x87, 0x73, 0x17, 0x6a, 0x0b, 0x58, 0xa1, 0xc1,
+0xb0, 0xbf, 0x26, 0x96, 0xd0, 0x38, 0x27, 0x78,
+0x06, 0x2e, 0x41, 0x1b, 0x4d, 0x3f, 0x31, 0x23,
+0x63, 0xfe, 0xbc, 0x81, 0x34, 0x18, 0xff, 0xba,
+0xd8, 0x01, 0x96, 0x7a, 0x15, 0x2f, 0x87, 0x58,
+0x18, 0xed, 0x10, 0x16, 0x76, 0xc4, 0x81, 0x06,
+0xc5, 0x8e, 0x91, 0x3f, 0x38, 0xdf, 0x90, 0x06,
+0x63, 0x3e, 0xfc, 0xa2, 0x8f, 0x34, 0x38, 0x6c,
+0x9d, 0xe2, 0xc3, 0xc4, 0x18, 0xfd, 0xf1, 0xfc,
+0x52, 0x8d, 0xf2, 0x59, 0x1f, 0x06, 0x38, 0x7f,
+0x7a, 0x76, 0xd5, 0xb7, 0x1c, 0x3c, 0xd5, 0xe3,
+0xdf, 0xd1, 0xc1, 0x68, 0xd0, 0x46, 0x80, 0xb1,
+0x7f, 0xb0, 0xa4, 0x1c, 0x95, 0xbd, 0x39, 0x0b,
+0x2e, 0xd1, 0xaf, 0x97, 0x0f, 0x45, 0x49, 0x34,
+0x21, 0xa0, 0x16, 0xc3, 0xa8, 0x6c, 0x7e, 0x62,
+0x1e, 0x7a, 0xc8, 0x87, 0x1b, 0x34, 0x55, 0xf0,
+0x4f, 0x41, 0xd0, 0xb7, 0xe0, 0x34, 0x16, 0x36,
+0x26, 0xc6, 0xc8, 0x37, 0x1c, 0x4f, 0xf5, 0x2c,
+0xf2, 0x61, 0x88, 0xf1, 0x70, 0x1e, 0x69, 0x10,
+0x4b, 0x6c, 0xc2, 0xc2, 0x7d, 0xc2, 0xc2, 0xfd,
+0xdc, 0x10, 0x5b, 0x96, 0xd1, 0x18, 0xe3, 0x11,
+0x49, 0xfe, 0xe4, 0xb1, 0x2a, 0xc1, 0xfc, 0xb1,
+0xf4, 0x69, 0x58, 0xa7, 0xd8, 0xb9, 0x1e, 0x7d,
+0x15, 0x56, 0xc8, 0x54, 0xcc, 0xfd, 0xa3, 0x30,
+0x6d, 0x2a, 0xb0, 0xd2, 0xec, 0x0d, 0xf6, 0x42,
+0x71, 0x64, 0x61, 0xfe, 0x0c, 0x44, 0x77, 0x0d,
+0xf3, 0x27, 0x57, 0xc4, 0x16, 0x1b, 0x0d, 0x18,
+0xd7, 0x2f, 0xe5, 0x87, 0xd1, 0x1a, 0xd0, 0xf1,
+0x1a, 0xd1, 0xf1, 0xfa, 0x52, 0x62, 0x69, 0x7d,
+0x22, 0x2f, 0x58, 0xd8, 0xb2, 0x37, 0x38, 0xd9,
+0x59, 0x2b, 0x2e, 0xe4, 0x9a, 0x3d, 0xe3, 0x7c,
+0x0f, 0x40, 0xc8, 0x97, 0xc2, 0x85, 0xcb, 0xf9,
+0xaf, 0xe1, 0x3b, 0xfa, 0x16, 0x98, 0x9d, 0x97,
+0xf0, 0xd3, 0x43, 0xc6, 0x18, 0x0f, 0xf2, 0xe4,
+0xaa, 0x9a, 0xef, 0xe6, 0x83, 0xc1, 0x18, 0xea,
+0x6a, 0x5e, 0xe5, 0xcb, 0xf0, 0x8b, 0xac, 0x77,
+0x4a, 0x01, 0x19, 0x6c, 0x21, 0x63, 0x1f, 0x1b,
+0xe3, 0x69, 0xca, 0xed, 0x9b, 0x6e, 0x17, 0xf3,
+0x01, 0x63, 0x67, 0xe4, 0x7a, 0xad, 0x92, 0xf3,
+0x8d, 0x0c, 0x6f, 0x9e, 0x36, 0x66, 0xfe, 0x28,
+0xcd, 0x87, 0x65, 0xe4, 0xd5, 0x19, 0xf7, 0x11,
+0xb3, 0xfd, 0xd3, 0xd9, 0x48, 0xf8, 0x30, 0xda,
+0x79, 0xd7, 0x46, 0x53, 0x73, 0x0e, 0x65, 0x82,
+0x85, 0xa9, 0x89, 0xcc, 0xfc, 0xf1, 0xe5, 0xeb,
+0xe7, 0xa4, 0x8f, 0xb8, 0xbc, 0x11, 0xd8, 0x65,
+0xe9, 0x0b, 0x47, 0x29, 0x8c, 0x1d, 0xa9, 0xf3,
+0xc7, 0x21, 0x23, 0x94, 0x31, 0x7f, 0x68, 0x02,
+0xa6, 0xc9, 0x67, 0x63, 0xc9, 0x45, 0x53, 0x12,
+0xec, 0x3d, 0xa3, 0x70, 0xe8, 0x65, 0xf9, 0x03,
+0x44, 0x83, 0x3d, 0xba, 0x0d, 0x6c, 0x3f, 0xe5,
+0x10, 0x16, 0xc2, 0xa3, 0x40, 0xd1, 0x9c, 0x3f,
+0x9b, 0x62, 0xab, 0xd1, 0xbf, 0x53, 0x7b, 0xd1,
+0xdd, 0xcc, 0x6d, 0xa9, 0x31, 0x9a, 0xf9, 0xcd,
+0xfc, 0x96, 0x7a, 0xf3, 0xce, 0xaa, 0x36, 0x63,
+0x32, 0xc6, 0x78, 0x84, 0xb5, 0xfc, 0x41, 0x63,
+0x71, 0xd0, 0xae, 0x39, 0xb7, 0x3f, 0xed, 0xea,
+0xab, 0xff, 0xcf, 0x85, 0x18, 0x03, 0x20, 0x01,
+0x83, 0x76, 0xd5, 0xc8, 0x1f, 0xbc, 0x5e, 0x5f,
+0x6d, 0xdd, 0xbd, 0xfe, 0xc3, 0x8d, 0xf7, 0x8f,
+0x9e, 0xbd, 0x7a, 0x89, 0xf8, 0xf0, 0xfb, 0xf7,
+0x34, 0x1f, 0xde, 0xc8, 0xf8, 0xb0, 0x68, 0x74,
+0x87, 0x8b, 0x19, 0x1f, 0xbe, 0x46, 0x7c, 0xf8,
+0xe0, 0xbe, 0xe6, 0xc3, 0x3f, 0x32, 0x3e, 0x3c,
+0xc5, 0x63, 0x8f, 0xab, 0xe7, 0x09, 0x0b, 0x7f,
+0x1f, 0x3c, 0xb8, 0x7f, 0xf1, 0xaf, 0x04, 0x14,
+0x91, 0x18, 0x67, 0xf0, 0x61, 0xfc, 0xdf, 0xff,
+0xfc, 0x0d, 0xfb, 0xff, 0x3d, 0x01, 0xc5, 0x8f,
+0x67, 0xf1, 0xe1, 0xcb, 0x13, 0x3e, 0x7c, 0x6e,
+0xe9, 0xd5, 0x5f, 0x0f, 0xea, 0xd4, 0xff, 0xda,
+0x54, 0xff, 0x7b, 0x4f, 0x3e, 0x7a, 0x0f, 0xa1,
+0x81, 0xbe, 0xd8, 0xe8, 0x41, 0xb3, 0xf4, 0xe4,
+0x6b, 0x61, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5,
+0x62, 0xb1, 0x58, 0xff, 0x77, 0xc5, 0xb5, 0x83,
+0xe4, 0xda, 0x81, 0xc5, 0x62, 0xb1, 0x58, 0x2c,
+0x16, 0x8b, 0xc5, 0x62, 0xcd, 0x56, 0x5c, 0x3b,
+0x14, 0xb8, 0x76, 0x60, 0xb1, 0x58, 0x2c, 0x16,
+0x8b, 0xc5, 0x62, 0xb1, 0x58, 0xb3, 0x15, 0xd7,
+0x0e, 0x56, 0x5c, 0x3b, 0xfc, 0xd7, 0x43, 0x61,
+0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1,
+0x58, 0xff, 0xa2, 0x3c, 0x7a, 0x81, 0x1c, 0x0a,
+0xb7, 0x3d, 0x88, 0xdf, 0x89, 0xc9, 0x7b, 0xa0,
+0x1e, 0xfb, 0x79, 0x42, 0xf2, 0xb7, 0x73, 0x1e,
+0x0c, 0x45, 0xb6, 0xce, 0x7b, 0xef, 0x4c, 0xf7,
+0xfb, 0x07, 0x18, 0x78, 0xae, 0x50, 0xf1, 0x33,
+0x01, 0x00,
diff --git a/board/esd/cms700/Kconfig b/board/esd/cms700/Kconfig
new file mode 100644
index 0000000..da11bc0
--- /dev/null
+++ b/board/esd/cms700/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CMS700
+
+config SYS_BOARD
+ default "cms700"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "CMS700"
+
+endif
diff --git a/board/esd/cms700/MAINTAINERS b/board/esd/cms700/MAINTAINERS
new file mode 100644
index 0000000..0191c8b
--- /dev/null
+++ b/board/esd/cms700/MAINTAINERS
@@ -0,0 +1,6 @@
+CMS700 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/cms700/
+F: include/configs/CMS700.h
+F: configs/CMS700_defconfig
diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile
new file mode 100644
index 0000000..2bf5006
--- /dev/null
+++ b/board/esd/cms700/Makefile
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD = ../common/xilinx_jtag/lenval.o \
+ ../common/xilinx_jtag/micro.o \
+ ../common/xilinx_jtag/ports.o
+
+obj-y = cms700.o flash.o \
+ ../common/misc.o \
+ $(CPLD) \
+ ../common/esd405ep_nand.o \
diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
new file mode 100644
index 0000000..40d7621
--- /dev/null
+++ b/board/esd/cms700/cms700.c
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2005-2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+int board_early_init_f (void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ */
+ mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ /*
+ * Reset CPLD via GPIO12 (CS3) pin
+ */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET);
+ udelay(1000); /* wait 1ms */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET);
+ udelay(1000); /* wait 1ms */
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /*
+ * Setup and enable EEPROM write protection
+ */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+#define LED_REG (CONFIG_SYS_PLD_BASE + 0x1000)
+int checkboard (void)
+{
+ char str[64];
+ int flashcnt;
+ int delay;
+
+ puts ("Board: ");
+
+ if (getenv_f("serial#", str, sizeof(str)) == -1) {
+ puts ("### No HW ID - assuming CMS700");
+ } else {
+ puts(str);
+ }
+
+ printf(" (PLD-Version=%02d)\n",
+ in_8((void *)(CONFIG_SYS_PLD_BASE + 0x1001)));
+
+ /*
+ * Flash LEDs
+ */
+ for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+ out_8((void *)LED_REG, 0x00); /* LEDs off */
+ for (delay = 0; delay < 100; delay++)
+ udelay(1000);
+ out_8((void *)LED_REG, 0x0f); /* LEDs on */
+ for (delay = 0; delay < 50; delay++)
+ udelay(1000);
+ }
+ out_8((void *)LED_REG, 0x70);
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO_SINT2. */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO_SINT2. */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts ("Query of write access state failed.\n");
+ } else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0) {
+ puts ("Setup of write access state failed.\n");
+ }
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "Enable / disable / query EEPROM write access",
+ ""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c
new file mode 100644
index 0000000..23e8164
--- /dev/null
+++ b/board/esd/cms700/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b0 = -size_b0;
+ switch (size_b0) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
new file mode 100644
index 0000000..f3f70ff
--- /dev/null
+++ b/board/esd/common/auto_update.c
@@ -0,0 +1,478 @@
+/*
+ * (C) Copyright 2003-2004
+ * Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <command.h>
+#include <image.h>
+#include <asm/byteorder.h>
+#include <fat.h>
+#include <flash.h>
+#include <part.h>
+
+#include "auto_update.h"
+
+#ifdef CONFIG_AUTO_UPDATE
+
+#if !defined(CONFIG_CMD_FAT)
+#error "must define CONFIG_CMD_FAT"
+#endif
+
+extern au_image_t au_image[];
+extern int N_AU_IMAGES;
+
+/* where to load files into memory */
+#define LOAD_ADDR ((unsigned char *)0x100000)
+#define MAX_LOADSZ 0x1c00000
+
+/* externals */
+long do_fat_read (const char *filename, void *buffer,
+ unsigned long maxsize, int dols);
+
+extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
+
+int au_check_cksum_valid(int i, long nbytes)
+{
+ image_header_t *hdr;
+
+ hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+ if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+ puts ("Non legacy image format not supported\n");
+ return -1;
+ }
+#endif
+
+ if ((au_image[i].type == AU_FIRMWARE) &&
+ (au_image[i].size != image_get_data_size (hdr))) {
+ printf ("Image %s has wrong size\n", au_image[i].name);
+ return -1;
+ }
+
+ if (nbytes != (image_get_image_size (hdr))) {
+ printf ("Image %s bad total SIZE\n", au_image[i].name);
+ return -1;
+ }
+
+ /* check the data CRC */
+ if (!image_check_dcrc (hdr)) {
+ printf ("Image %s bad data checksum\n", au_image[i].name);
+ return -1;
+ }
+ return 0;
+}
+
+int au_check_header_valid(int i, long nbytes)
+{
+ image_header_t *hdr;
+
+ hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+ if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+ puts ("Non legacy image format not supported\n");
+ return -1;
+ }
+#endif
+
+ /* check the easy ones first */
+ if (nbytes < image_get_header_size ()) {
+ printf ("Image %s bad header SIZE\n", au_image[i].name);
+ return -1;
+ }
+ if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) {
+ printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name);
+ return -1;
+ }
+ if (!image_check_hcrc (hdr)) {
+ printf ("Image %s bad header checksum\n", au_image[i].name);
+ return -1;
+ }
+
+ /* check the type - could do this all in one gigantic if() */
+ if (((au_image[i].type & AU_TYPEMASK) == AU_FIRMWARE) &&
+ !image_check_type (hdr, IH_TYPE_FIRMWARE)) {
+ printf ("Image %s wrong type\n", au_image[i].name);
+ return -1;
+ }
+ if (((au_image[i].type & AU_TYPEMASK) == AU_SCRIPT) &&
+ !image_check_type (hdr, IH_TYPE_SCRIPT)) {
+ printf ("Image %s wrong type\n", au_image[i].name);
+ return -1;
+ }
+
+ return 0;
+}
+
+int au_do_update(int i, long sz)
+{
+ image_header_t *hdr;
+ char *addr;
+ long start, end;
+ int off, rc;
+ uint nbytes;
+ int k;
+
+ hdr = (image_header_t *)LOAD_ADDR;
+#if defined(CONFIG_FIT)
+ if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+ puts ("Non legacy image format not supported\n");
+ return -1;
+ }
+#endif
+
+ switch (au_image[i].type & AU_TYPEMASK) {
+ case AU_SCRIPT:
+ printf("Executing script %s\n", au_image[i].name);
+
+ /* execute a script */
+ if (image_check_type (hdr, IH_TYPE_SCRIPT)) {
+ addr = (char *)((char *)hdr + image_get_header_size ());
+ /* stick a NULL at the end of the script, otherwise */
+ /* parse_string_outer() runs off the end. */
+ addr[image_get_data_size (hdr)] = 0;
+ addr += 8;
+
+ /*
+ * Replace cr/lf with ;
+ */
+ k = 0;
+ while (addr[k] != 0) {
+ if ((addr[k] == 10) || (addr[k] == 13)) {
+ addr[k] = ';';
+ }
+ k++;
+ }
+
+ run_command(addr, 0);
+ return 0;
+ }
+
+ break;
+
+ case AU_FIRMWARE:
+ case AU_NOR:
+ case AU_NAND:
+ start = au_image[i].start;
+ end = au_image[i].start + au_image[i].size - 1;
+
+ /*
+ * do not update firmware when image is already in flash.
+ */
+ if (au_image[i].type == AU_FIRMWARE) {
+ char *orig = (char*)start;
+ char *new = (char *)((char *)hdr +
+ image_get_header_size ());
+ nbytes = image_get_data_size (hdr);
+
+ while (--nbytes) {
+ if (*orig++ != *new++) {
+ break;
+ }
+ }
+ if (!nbytes) {
+ printf ("Skipping firmware update - "
+ "images are identical\n");
+ break;
+ }
+ }
+
+ /* unprotect the address range */
+ if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) ||
+ (au_image[i].type == AU_FIRMWARE)) {
+ flash_sect_protect (0, start, end);
+ }
+
+ /*
+ * erase the address range.
+ */
+ if (au_image[i].type != AU_NAND) {
+ printf ("Updating NOR FLASH with image %s\n",
+ au_image[i].name);
+ debug ("flash_sect_erase(%lx, %lx);\n", start, end);
+ flash_sect_erase (start, end);
+ }
+
+ udelay(10000);
+
+ /* strip the header - except for the kernel and ramdisk */
+ if (au_image[i].type != AU_FIRMWARE) {
+ addr = (char *)hdr;
+ off = image_get_header_size ();
+ nbytes = image_get_image_size (hdr);
+ } else {
+ addr = (char *)((char *)hdr + image_get_header_size ());
+ off = 0;
+ nbytes = image_get_data_size (hdr);
+ }
+
+ /*
+ * copy the data from RAM to FLASH
+ */
+ if (au_image[i].type != AU_NAND) {
+ debug ("flash_write(%p, %lx, %x)\n",
+ addr, start, nbytes);
+ rc = flash_write ((char *)addr, start,
+ (nbytes + 1) & ~1);
+ } else {
+ rc = -1;
+ }
+ if (rc != 0) {
+ printf ("Flashing failed due to error %d\n", rc);
+ return -1;
+ }
+
+ /*
+ * check the dcrc of the copy
+ */
+ if (au_image[i].type != AU_NAND) {
+ rc = crc32 (0, (uchar *)(start + off),
+ image_get_data_size (hdr));
+ }
+ if (rc != image_get_dcrc (hdr)) {
+ printf ("Image %s Bad Data Checksum After COPY\n",
+ au_image[i].name);
+ return -1;
+ }
+
+ /* protect the address range */
+ /* this assumes that ONLY the firmware is protected! */
+ if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) ||
+ (au_image[i].type == AU_FIRMWARE)) {
+ flash_sect_protect (1, start, end);
+ }
+
+ break;
+
+ default:
+ printf("Wrong image type selected!\n");
+ }
+
+ return 0;
+}
+
+static void process_macros (const char *input, char *output)
+{
+ char c, prev;
+ const char *varname_start = NULL;
+ int inputcnt = strlen (input);
+ int outputcnt = CONFIG_SYS_CBSIZE;
+ int state = 0; /* 0 = waiting for '$' */
+ /* 1 = waiting for '(' or '{' */
+ /* 2 = waiting for ')' or '}' */
+ /* 3 = waiting for ''' */
+#ifdef DEBUG_PARSER
+ char *output_start = output;
+
+ printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n",
+ strlen(input), input);
+#endif
+
+ prev = '\0'; /* previous character */
+
+ while (inputcnt && outputcnt) {
+ c = *input++;
+ inputcnt--;
+
+ if (state != 3) {
+ /* remove one level of escape characters */
+ if ((c == '\\') && (prev != '\\')) {
+ if (inputcnt-- == 0)
+ break;
+ prev = c;
+ c = *input++;
+ }
+ }
+
+ switch (state) {
+ case 0: /* Waiting for (unescaped) $ */
+ if ((c == '\'') && (prev != '\\')) {
+ state = 3;
+ break;
+ }
+ if ((c == '$') && (prev != '\\')) {
+ state++;
+ } else {
+ *(output++) = c;
+ outputcnt--;
+ }
+ break;
+ case 1: /* Waiting for ( */
+ if (c == '(' || c == '{') {
+ state++;
+ varname_start = input;
+ } else {
+ state = 0;
+ *(output++) = '$';
+ outputcnt--;
+
+ if (outputcnt) {
+ *(output++) = c;
+ outputcnt--;
+ }
+ }
+ break;
+ case 2: /* Waiting for ) */
+ if (c == ')' || c == '}') {
+ int i;
+ char envname[CONFIG_SYS_CBSIZE], *envval;
+ /* Varname # of chars */
+ int envcnt = input - varname_start - 1;
+
+ /* Get the varname */
+ for (i = 0; i < envcnt; i++) {
+ envname[i] = varname_start[i];
+ }
+ envname[i] = 0;
+
+ /* Get its value */
+ envval = getenv (envname);
+
+ /* Copy into the line if it exists */
+ if (envval != NULL)
+ while ((*envval) && outputcnt) {
+ *(output++) = *(envval++);
+ outputcnt--;
+ }
+ /* Look for another '$' */
+ state = 0;
+ }
+ break;
+ case 3: /* Waiting for ' */
+ if ((c == '\'') && (prev != '\\')) {
+ state = 0;
+ } else {
+ *(output++) = c;
+ outputcnt--;
+ }
+ break;
+ }
+ prev = c;
+ }
+
+ if (outputcnt)
+ *output = 0;
+
+#ifdef DEBUG_PARSER
+ printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n",
+ strlen (output_start), output_start);
+#endif
+}
+
+/*
+ * this is called from board_init() after the hardware has been set up
+ * and is usable. That seems like a good time to do this.
+ * Right now the return value is ignored.
+ */
+int do_auto_update(void)
+{
+ block_dev_desc_t *stor_dev = NULL;
+ long sz;
+ int i, res, old_ctrlc;
+ char buffer[32];
+ char str[80];
+ int n;
+
+ if (ide_dev_desc[0].type != DEV_TYPE_UNKNOWN) {
+ stor_dev = get_dev ("ide", 0);
+ if (stor_dev == NULL) {
+ debug ("ide: unknown device\n");
+ return -1;
+ }
+ }
+
+ if (fat_register_device (stor_dev, 1) != 0) {
+ debug ("Unable to register ide disk 0:1\n");
+ return -1;
+ }
+
+ /*
+ * Check if magic file is present
+ */
+ if ((n = do_fat_read (AU_MAGIC_FILE, buffer,
+ sizeof(buffer), LS_NO)) <= 0) {
+ debug ("No auto_update magic file (n=%d)\n", n);
+ return -1;
+ }
+
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+ board_auto_update_show (1);
+#endif
+ puts("\nAutoUpdate Disk detected! Trying to update system...\n");
+
+ /* make sure that we see CTRL-C and save the old state */
+ old_ctrlc = disable_ctrlc (0);
+
+ /* just loop thru all the possible files */
+ for (i = 0; i < N_AU_IMAGES; i++) {
+ /*
+ * Try to expand the environment var in the fname
+ */
+ process_macros (au_image[i].name, str);
+ strcpy (au_image[i].name, str);
+
+ printf("Reading %s ...", au_image[i].name);
+ /* just read the header */
+ sz = do_fat_read (au_image[i].name, LOAD_ADDR,
+ image_get_header_size (), LS_NO);
+ debug ("read %s sz %ld hdr %d\n",
+ au_image[i].name, sz, image_get_header_size ());
+ if (sz <= 0 || sz < image_get_header_size ()) {
+ puts(" not found\n");
+ continue;
+ }
+ if (au_check_header_valid (i, sz) < 0) {
+ puts(" header not valid\n");
+ continue;
+ }
+ sz = do_fat_read (au_image[i].name, LOAD_ADDR,
+ MAX_LOADSZ, LS_NO);
+ debug ("read %s sz %ld hdr %d\n",
+ au_image[i].name, sz, image_get_header_size ());
+ if (sz <= 0 || sz <= image_get_header_size ()) {
+ puts(" not found\n");
+ continue;
+ }
+ if (au_check_cksum_valid (i, sz) < 0) {
+ puts(" checksum not valid\n");
+ continue;
+ }
+ puts(" done\n");
+
+ do {
+ res = au_do_update (i, sz);
+ /* let the user break out of the loop */
+ if (ctrlc() || had_ctrlc ()) {
+ clear_ctrlc ();
+ break;
+ }
+ } while (res < 0);
+ }
+
+ /* restore the old state */
+ disable_ctrlc (old_ctrlc);
+
+ puts("AutoUpdate finished\n\n");
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+ board_auto_update_show (0);
+#endif
+
+ return 0;
+}
+
+int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ do_auto_update();
+
+ return 0;
+}
+U_BOOT_CMD(
+ autoupd, 1, 1, auto_update,
+ "Automatically update images",
+ ""
+);
+#endif /* CONFIG_AUTO_UPDATE */
diff --git a/board/esd/common/auto_update.h b/board/esd/common/auto_update.h
new file mode 100644
index 0000000..be8f439
--- /dev/null
+++ b/board/esd/common/auto_update.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _AUTO_UPDATE_H_
+#define _AUTO_UPDATE_H_
+
+#define MBR_MAGIC 0x07081967
+#define MBR_MAGIC_ADDR 0x100 /* offset 0x100 should be free space */
+
+#define AU_MAGIC_FILE "__auto_update"
+
+#define AU_TYPEMASK 0x000000ff
+#define AU_FLAGMASK 0xffff0000
+
+#define AU_PROTECT 0x80000000
+
+#define AU_SCRIPT 0x01
+#define AU_FIRMWARE (0x02 | AU_PROTECT)
+#define AU_NOR 0x03
+#define AU_NAND 0x04
+
+struct au_image_s {
+ char name[80];
+ ulong start;
+ ulong size;
+ ulong type;
+};
+
+typedef struct au_image_s au_image_t;
+
+int do_auto_update(void);
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+void board_auto_update_show(int au_active);
+#endif
+
+#endif /* #ifndef _AUTO_UPDATE_H_ */
diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c
new file mode 100644
index 0000000..95d1891
--- /dev/null
+++ b/board/esd/common/cmd_loadpci.c
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2005-2008
+ * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#if !defined(CONFIG_440)
+#include <asm/4xx_pci.h>
+#endif
+
+#if defined(CONFIG_CMD_BSP)
+#define ADDRMASK 0xfffff000
+
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 *ptr = 0;
+ int count = 0;
+ int count2 = 0;
+ char addr[16];
+ char str[] = "\\|/-";
+ u32 la, ptm1la;
+
+#if defined(CONFIG_440)
+ ptm1la = in32r(PCIL0_PTM1LA);
+#else
+ ptm1la = in32r(PTM1LA);
+#endif
+ while(1) {
+ /*
+ * Mark sync address
+ */
+ ptr = (u32 *)ptm1la;
+ memset(ptr, 0, 0x20);
+
+ *ptr = 0xffffffff;
+ puts("\nWaiting for action from pci host -");
+
+ /*
+ * Wait for host to write the start address
+ */
+ while (*ptr == 0xffffffff) {
+ count++;
+ if (!(count % 100)) {
+ count2++;
+ putc(0x08); /* backspace */
+ putc(str[count2 % 4]);
+ }
+
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return 0;
+ }
+
+ udelay(1000);
+ }
+
+ printf("\nGot bootcode %08x: ", *ptr);
+ la = ptm1la + (*ptr & ADDRMASK);
+ sprintf(addr, "%08x", la);
+
+ switch (*ptr & ~ADDRMASK) {
+ case 0:
+ /*
+ * Boot image via bootm
+ */
+ printf("booting image at addr 0x%s ...\n", addr);
+ setenv("loadaddr", addr);
+ do_bootm(cmdtp, 0, 0, NULL);
+ break;
+
+ case 1:
+ /*
+ * Boot image via "source" command
+ */
+ printf("executing script at addr 0x%s ...\n", addr);
+ source(la, NULL);
+ break;
+
+ case 2:
+ /*
+ * Call run_cmd
+ */
+ printf("running command at addr 0x%s ...\n", addr);
+ run_command((char *)la, 0);
+ break;
+
+ default:
+ printf("unhandled boot method\n");
+ break;
+ }
+ }
+}
+
+U_BOOT_CMD(
+ loadpci, 1, 1, do_loadpci,
+ "Wait for pci bootcmd and boot it",
+ ""
+);
+
+#endif
diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c
new file mode 100644
index 0000000..f46936c
--- /dev/null
+++ b/board/esd/common/esd405ep_nand.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+#include <asm/io.h>
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ */
+static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if ( ctrl & NAND_CLE )
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE);
+ else
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);
+ if ( ctrl & NAND_ALE )
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE);
+ else
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);
+ if ( ctrl & NAND_NCE )
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE);
+ else
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+
+/*
+ * read device ready pin
+ */
+static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
+{
+ if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY)
+ return 1;
+ return 0;
+}
+
+
+int board_nand_init(struct nand_chip *nand)
+{
+ /*
+ * Set NAND-FLASH GPIO signals to defaults
+ */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+
+ /*
+ * Initialize nand_chip structure
+ */
+ nand->cmd_ctrl = esd405ep_nand_hwcontrol;
+ nand->dev_ready = esd405ep_nand_device_ready;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->chip_delay = NAND_BIG_DELAY_US;
+ nand->options = NAND_SAMSUNG_LP_OPTIONS;
+ return 0;
+}
+#endif
diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c
new file mode 100644
index 0000000..e3512c7
--- /dev/null
+++ b/board/esd/common/flash.c
@@ -0,0 +1,659 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#ifdef __PPC__
+#include <asm/ppc4xx.h>
+#endif
+#include <asm/processor.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+ short n;
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+ /* set sector offsets for bottom boot block type */
+ for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
+ info->start[i] = base;
+ base += 8 << 10;
+ }
+ while (i < info->sector_count) { /* 64k regular sectors */
+ info->start[i] = base;
+ base += 64 << 10;
+ ++i;
+ }
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ case FLASH_MAN_SST: printf ("SST "); break;
+ case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n");
+ break;
+ case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n");
+ break;
+ case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n");
+ break;
+ case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AM640U: printf ("AM29LV640D (64 M, uniform sector)\n");
+ break;
+ case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST320: printf ("SST39LF/VF320 (32 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST640: printf ("SST39LF/VF640 (64 Mbit, uniform sector size)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count-1))
+ size = info->start[i+1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k=0; k<size; k++)
+ {
+ if (*flash++ != 0xffffffff)
+ {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf ("\n ");
+ /* print empty and read-only info */
+ printf (" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " ");
+#else
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+#endif
+
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ short n;
+ CONFIG_SYS_FLASH_WORD_SIZE value;
+ ulong base = (ulong)addr;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
+
+ value = addr2[CONFIG_SYS_FLASH_READ0];
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+ info->flash_id = FLASH_MAN_EXCEL;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
+ info->flash_id += FLASH_AMDL322T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
+ info->flash_id += FLASH_AMDL322B;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
+ info->flash_id += FLASH_AMDL323T;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
+ info->flash_id += FLASH_AMDL323B;
+ info->sector_count = 71;
+ info->size = 0x00400000; break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
+ info->flash_id += FLASH_AM640U;
+ info->sector_count = 128;
+ info->size = 0x00800000; break; /* => 8 MB */
+
+#if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM))
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
+ info->flash_id += FLASH_SST800A;
+ info->sector_count = 16;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1601:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1602:
+ info->flash_id += FLASH_SST160A;
+ info->sector_count = 32;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3201:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3202:
+ info->flash_id += FLASH_SST320;
+ info->sector_count = 64;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6401:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6402:
+ info->flash_id += FLASH_SST640;
+ info->sector_count = 128;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+#endif
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+ /* set sector offsets for bottom boot block type */
+ for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
+ info->start[i] = base;
+ base += 8 << 10;
+ }
+ while (i < info->sector_count) { /* 64k regular sectors */
+ info->start[i] = base;
+ base += 64 << 10;
+ ++i;
+ }
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+ if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+ *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050; /* block erase */
+ for (i=0; i<50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ if (sect == s_first) {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ }
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+ while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+DONE:
+ /* reset to read mode */
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+ addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ ulong *data_ptr = &data;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
+ ulong start;
+ int flag;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
+ {
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+ (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c
new file mode 100644
index 0000000..5c70b47
--- /dev/null
+++ b/board/esd/common/fpga.c
@@ -0,0 +1,261 @@
+/*
+ * (C) Copyright 2001-2004
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef FPGA_DEBUG
+#define DBG(x...) printf(x)
+#else
+#define DBG(x...)
+#endif /* DEBUG */
+
+#define MAX_ONES 226
+
+#ifdef CONFIG_SYS_FPGA_PRG
+# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output) */
+# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */
+# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */
+# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */
+# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */
+#else
+# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
+# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
+# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
+# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
+# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
+#endif
+
+#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
+#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
+#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
+
+#ifndef SET_FPGA
+# define SET_FPGA(data) out_be32((void *)GPIO0_OR, data)
+#endif
+
+#ifdef FPGA_PROG_ACTIVE_HIGH
+# define FPGA_PRG_LOW FPGA_PRG
+# define FPGA_PRG_HIGH 0
+#else
+# define FPGA_PRG_LOW 0
+# define FPGA_PRG_HIGH FPGA_PRG
+#endif
+
+#define FPGA_CLK_LOW 0
+#define FPGA_CLK_HIGH FPGA_CLK
+
+#define FPGA_DATA_LOW 0
+#define FPGA_DATA_HIGH FPGA_DATA
+
+#define FPGA_WRITE_1 { \
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set data to 1 */ \
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set clock to 1 */ \
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
+
+#define FPGA_WRITE_0 { \
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_LOW); /* set data to 0 */ \
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW); /* set clock to 1 */ \
+ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */
+
+#ifndef FPGA_DONE_STATE
+# define FPGA_DONE_STATE (in_be32((void *)GPIO0_IR) & FPGA_DONE)
+#endif
+#ifndef FPGA_INIT_STATE
+# define FPGA_INIT_STATE (in_be32((void *)GPIO0_IR) & FPGA_INIT)
+#endif
+
+
+static int fpga_boot (const unsigned char *fpgadata, int size)
+{
+ int i, index, len;
+ int count;
+ unsigned char b;
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+ int j;
+#else
+ int bit;
+#endif
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = fpgadata[index];
+ DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
+ index += len + 3;
+ }
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+ /* search for preamble 0xFFFFFFFF */
+ while (1) {
+ if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
+ && (fpgadata[index + 2] == 0xff)
+ && (fpgadata[index + 3] == 0xff))
+ break; /* preamble found */
+ else
+ index++;
+ }
+#else
+ /* search for preamble 0xFF2X */
+ for (index = 0; index < size - 1; index++) {
+ if ((fpgadata[index] == 0xff)
+ && ((fpgadata[index + 1] & 0xf0) == 0x30))
+ break;
+ }
+ index += 2;
+#endif
+
+ DBG ("FPGA: configdata starts at position 0x%x\n", index);
+ DBG ("FPGA: length of fpga-data %d\n", size - index);
+
+ /*
+ * Setup port pins for fpga programming
+ */
+#ifndef CONFIG_M5249
+ out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
+ /* setup for output */
+ out_be32 ((void *)GPIO0_TCR,
+ in_be32 ((void *)GPIO0_TCR) |
+ FPGA_PRG | FPGA_CLK | FPGA_DATA);
+#endif
+ SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */
+
+ DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+ DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+ /*
+ * Init fpga by asserting and deasserting PROGRAM*
+ */
+ SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */
+
+ /* Wait for FPGA init line low */
+ count = 0;
+ while (FPGA_INIT_STATE) {
+ udelay (1000); /* wait 1ms */
+ /* Check for timeout - 100us max, so use 3ms */
+ if (count++ > 3) {
+ DBG ("FPGA: Booting failed!\n");
+ return ERROR_FPGA_PRG_INIT_LOW;
+ }
+ }
+
+ DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+ DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+ /* deassert PROGRAM* */
+ SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */
+
+ /* Wait for FPGA end of init period . */
+ count = 0;
+ while (!(FPGA_INIT_STATE)) {
+ udelay (1000); /* wait 1ms */
+ /* Check for timeout */
+ if (count++ > 3) {
+ DBG ("FPGA: Booting failed!\n");
+ return ERROR_FPGA_PRG_INIT_HIGH;
+ }
+ }
+
+ DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+ DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+ DBG ("write configuration data into fpga\n");
+ /* write configuration-data into fpga... */
+
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
+ /*
+ * Load uncompressed image into fpga
+ */
+ for (i = index; i < size; i++) {
+ b = fpgadata[i];
+ for (j = 0; j < 8; j++) {
+ if ((b & 0x80) == 0x80) {
+ FPGA_WRITE_1;
+ } else {
+ FPGA_WRITE_0;
+ }
+ b <<= 1;
+ }
+ }
+#else
+ /* send 0xff 0x20 */
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_1;
+ FPGA_WRITE_0;
+ FPGA_WRITE_0;
+ FPGA_WRITE_1;
+ FPGA_WRITE_0;
+ FPGA_WRITE_0;
+ FPGA_WRITE_0;
+ FPGA_WRITE_0;
+ FPGA_WRITE_0;
+
+ /*
+ ** Bit_DeCompression
+ ** Code 1 .. maxOnes : n '1's followed by '0'
+ ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
+ ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
+ ** 255 : '1'
+ */
+
+ for (i = index; i < size; i++) {
+ b = fpgadata[i];
+ if ((b >= 1) && (b <= MAX_ONES)) {
+ for (bit = 0; bit < b; bit++) {
+ FPGA_WRITE_1;
+ }
+ FPGA_WRITE_0;
+ } else if (b == (MAX_ONES + 1)) {
+ for (bit = 1; bit < b; bit++) {
+ FPGA_WRITE_1;
+ }
+ } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
+ for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
+ FPGA_WRITE_0;
+ }
+ FPGA_WRITE_1;
+ } else if (b == 255) {
+ FPGA_WRITE_1;
+ }
+ }
+#endif
+
+ DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
+ DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
+
+ /*
+ * Check if fpga's DONE signal - correctly booted ?
+ */
+
+ /* Wait for FPGA end of programming period . */
+ count = 0;
+ while (!(FPGA_DONE_STATE)) {
+ udelay (1000); /* wait 1ms */
+ /* Check for timeout */
+ if (count++ > 3) {
+ DBG ("FPGA: Booting failed!\n");
+ return ERROR_FPGA_PRG_DONE;
+ }
+ }
+
+ DBG ("FPGA: Booting successful!\n");
+ return 0;
+}
diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c
new file mode 100644
index 0000000..22a59e4
--- /dev/null
+++ b/board/esd/common/lcd.c
@@ -0,0 +1,359 @@
+/*
+ * (C) Copyright 2003-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "asm/io.h"
+#include "lcd.h"
+
+
+extern int video_display_bitmap (ulong, int, int);
+
+
+int palette_index;
+int palette_value;
+int lcd_depth;
+unsigned char *glob_lcd_reg;
+unsigned char *glob_lcd_mem;
+
+#if defined(CONFIG_SYS_LCD_ENDIAN)
+void lcd_setup(int lcd, int config)
+{
+ if (lcd == 0) {
+ /*
+ * Set endianess and reset lcd controller 0 (small)
+ */
+
+ /* set reset to low */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD0_RST);
+ udelay(10); /* wait 10us */
+ if (config == 1) {
+ /* big-endian */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
+ } else {
+ /* little-endian */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
+ }
+ udelay(10); /* wait 10us */
+ /* set reset to high */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD0_RST);
+ } else {
+ /*
+ * Set endianess and reset lcd controller 1 (big)
+ */
+
+ /* set reset to low */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD1_RST);
+ udelay(10); /* wait 10us */
+ if (config == 1) {
+ /* big-endian */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
+ } else {
+ /* little-endian */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
+ }
+ udelay(10); /* wait 10us */
+ /* set reset to high */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD1_RST);
+ }
+
+ /*
+ * CONFIG_SYS_LCD_ENDIAN may also be FPGA_RESET, so set inactive
+ */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
+}
+#endif /* CONFIG_SYS_LCD_ENDIAN */
+
+
+int lcd_bmp(uchar *logo_bmp)
+{
+ int i;
+ uchar *ptr;
+ ushort *ptr2;
+ ushort val;
+ unsigned char *dst = NULL;
+ int x, y;
+ int width, height, bpp, colors, line_size;
+ int header_size;
+ unsigned char *bmp;
+ unsigned char r, g, b;
+ BITMAPINFOHEADER *bm_info;
+ ulong len;
+
+ /*
+ * Check for bmp mark 'BM'
+ */
+ if (*(ushort *)logo_bmp != 0x424d) {
+ /*
+ * Decompress bmp image
+ */
+ len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
+ dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
+ if (dst == NULL) {
+ printf("Error: malloc for gunzip failed!\n");
+ return 1;
+ }
+ if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE,
+ (uchar *)logo_bmp, &len) != 0) {
+ free(dst);
+ return 1;
+ }
+ if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) {
+ printf("Image could be truncated"
+ " (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n");
+ }
+
+ /*
+ * Check for bmp mark 'BM'
+ */
+ if (*(ushort *)dst != 0x424d) {
+ printf("LCD: Unknown image format!\n");
+ free(dst);
+ return 1;
+ }
+ } else {
+ /*
+ * Uncompressed BMP image, just use this pointer
+ */
+ dst = (uchar *)logo_bmp;
+ }
+
+ /*
+ * Get image info from bmp-header
+ */
+ bm_info = (BITMAPINFOHEADER *)(dst + 14);
+ bpp = LOAD_SHORT(bm_info->biBitCount);
+ width = LOAD_LONG(bm_info->biWidth);
+ height = LOAD_LONG(bm_info->biHeight);
+ switch (bpp) {
+ case 1:
+ colors = 1;
+ line_size = width >> 3;
+ break;
+ case 4:
+ colors = 16;
+ line_size = width >> 1;
+ break;
+ case 8:
+ colors = 256;
+ line_size = width;
+ break;
+ case 24:
+ colors = 0;
+ line_size = width * 3;
+ break;
+ default:
+ printf("LCD: Unknown bpp (%d) im image!\n", bpp);
+ if ((dst != NULL) && (dst != (uchar *)logo_bmp))
+ free(dst);
+ return 1;
+ }
+ printf(" (%d*%d, %dbpp)\n", width, height, bpp);
+
+ /*
+ * Write color palette
+ */
+ if ((colors <= 256) && (lcd_depth <= 8)) {
+ ptr = (unsigned char *)(dst + 14 + 40);
+ for (i = 0; i < colors; i++) {
+ b = *ptr++;
+ g = *ptr++;
+ r = *ptr++;
+ ptr++;
+ S1D_WRITE_PALETTE(glob_lcd_reg, i, r, g, b);
+ }
+ }
+
+ /*
+ * Write bitmap data into framebuffer
+ */
+ ptr = glob_lcd_mem;
+ ptr2 = (ushort *)glob_lcd_mem;
+ header_size = 14 + 40 + 4*colors; /* skip bmp header */
+ for (y = 0; y < height; y++) {
+ bmp = &dst[(height-1-y)*line_size + header_size];
+ if (lcd_depth == 16) {
+ if (bpp == 24) {
+ for (x = 0; x < width; x++) {
+ /*
+ * Generate epson 16bpp fb-format
+ * from 24bpp image
+ */
+ b = *bmp++ >> 3;
+ g = *bmp++ >> 2;
+ r = *bmp++ >> 3;
+ val = ((r & 0x1f) << 11) |
+ ((g & 0x3f) << 5) |
+ (b & 0x1f);
+ *ptr2++ = val;
+ }
+ } else if (bpp == 8) {
+ for (x = 0; x < line_size; x++) {
+ /* query rgb value from palette */
+ ptr = (unsigned char *)(dst + 14 + 40);
+ ptr += (*bmp++) << 2;
+ b = *ptr++ >> 3;
+ g = *ptr++ >> 2;
+ r = *ptr++ >> 3;
+ val = ((r & 0x1f) << 11) |
+ ((g & 0x3f) << 5) |
+ (b & 0x1f);
+ *ptr2++ = val;
+ }
+ }
+ } else {
+ for (x = 0; x < line_size; x++)
+ *ptr++ = *bmp++;
+ }
+ }
+
+ if ((dst != NULL) && (dst != (uchar *)logo_bmp))
+ free(dst);
+ return 0;
+}
+
+
+int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
+ uchar *logo_bmp, ulong len)
+{
+ int i;
+ ushort s1dReg;
+ uchar s1dValue;
+ int reg_byte_swap;
+
+ /*
+ * Detect epson
+ */
+ out_8(&lcd_reg[0], 0x00);
+ out_8(&lcd_reg[1], 0x00);
+
+ if (in_8(&lcd_reg[0]) == 0x1c) {
+ /*
+ * Big epson detected
+ */
+ reg_byte_swap = false;
+ palette_index = 0x1e2;
+ palette_value = 0x1e4;
+ lcd_depth = 16;
+ puts("LCD: S1D13806");
+ } else if (in_8(&lcd_reg[1]) == 0x1c) {
+ /*
+ * Big epson detected (with register swap bug)
+ */
+ reg_byte_swap = true;
+ palette_index = 0x1e3;
+ palette_value = 0x1e5;
+ lcd_depth = 16;
+ puts("LCD: S1D13806S");
+ } else if (in_8(&lcd_reg[0]) == 0x18) {
+ /*
+ * Small epson detected (704)
+ */
+ reg_byte_swap = false;
+ palette_index = 0x15;
+ palette_value = 0x17;
+ lcd_depth = 8;
+ puts("LCD: S1D13704");
+ } else if (in_8(&lcd_reg[0x10000]) == 0x24) {
+ /*
+ * Small epson detected (705)
+ */
+ reg_byte_swap = false;
+ palette_index = 0x15;
+ palette_value = 0x17;
+ lcd_depth = 8;
+ lcd_reg += 0x10000; /* add offset for 705 regs */
+ puts("LCD: S1D13705");
+ } else {
+ out_8(&lcd_reg[0x1a], 0x00);
+ udelay(1000);
+ if (in_8(&lcd_reg[1]) == 0x0c) {
+ /*
+ * S1D13505 detected
+ */
+ reg_byte_swap = true;
+ palette_index = 0x25;
+ palette_value = 0x27;
+ lcd_depth = 16;
+
+ puts("LCD: S1D13505");
+ } else {
+ puts("LCD: No controller detected!\n");
+ return 1;
+ }
+ }
+
+ /*
+ * Setup lcd controller regs
+ */
+ for (i = 0; i < reg_count; i++) {
+ s1dReg = regs[i].Index;
+ if (reg_byte_swap) {
+ if ((s1dReg & 0x0001) == 0)
+ s1dReg |= 0x0001;
+ else
+ s1dReg &= ~0x0001;
+ }
+ s1dValue = regs[i].Value;
+ out_8(&lcd_reg[s1dReg], s1dValue);
+ }
+
+ /*
+ * Save reg & mem pointer for later usage (e.g. bmp command)
+ */
+ glob_lcd_reg = lcd_reg;
+ glob_lcd_mem = lcd_mem;
+
+ /*
+ * Display bmp image
+ */
+ return lcd_bmp(logo_bmp);
+}
+
+int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong addr;
+#ifdef CONFIG_VIDEO_SM501
+ char *str;
+#endif
+ if (argc != 2)
+ return cmd_usage(cmdtp);
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+#ifdef CONFIG_VIDEO_SM501
+ str = getenv("bd_type");
+ if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) {
+ /*
+ * SM501 available, use standard bmp command
+ */
+ return video_display_bitmap(addr, 0, 0);
+ } else {
+ /*
+ * No SM501 available, use esd epson bmp command
+ */
+ return lcd_bmp((uchar *)addr);
+ }
+#else
+ return lcd_bmp((uchar *)addr);
+#endif
+}
+
+U_BOOT_CMD(
+ esdbmp, 2, 1, do_esdbmp,
+ "display BMP image",
+ "<imageAddr> - display image"
+);
diff --git a/board/esd/common/lcd.h b/board/esd/common/lcd.h
new file mode 100644
index 0000000..5b14bf9
--- /dev/null
+++ b/board/esd/common/lcd.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2003-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Neutralize little endians.
+ */
+#define SWAP_LONG(data) ((unsigned long) \
+ (((unsigned long)(data) >> 24) | \
+ ((unsigned long)(data) << 24) | \
+ (((unsigned long)(data) >> 8) & 0x0000ff00 ) | \
+ (((unsigned long)(data) << 8) & 0x00ff0000 )))
+#define SWAP_SHORT(data) ((unsigned short) \
+ (((unsigned short)(data) >> 8 ) | \
+ ((unsigned short)(data) << 8 )))
+#define LOAD_LONG(data) SWAP_LONG(data)
+#define LOAD_SHORT(data) SWAP_SHORT(data)
+
+#define S1D_WRITE_PALETTE(p,i,r,g,b) \
+ { \
+ out_8(&((uchar*)(p))[palette_index], (uchar)(i)); \
+ out_8(&((uchar*)(p))[palette_index], (uchar)(r)); \
+ out_8(&((uchar*)(p))[palette_index], (uchar)(g)); \
+ out_8(&((uchar*)(p))[palette_index], (uchar)(b)); \
+ }
+
+typedef struct
+{
+ ushort Index;
+ uchar Value;
+} S1D_REGS;
+
+typedef struct /**** BMP file info structure ****/
+{
+ unsigned int biSize; /* Size of info header */
+ int biWidth; /* Width of image */
+ int biHeight; /* Height of image */
+ unsigned short biPlanes; /* Number of color planes */
+ unsigned short biBitCount; /* Number of bits per pixel */
+ unsigned int biCompression; /* Type of compression to use */
+ unsigned int biSizeImage; /* Size of image data */
+ int biXPelsPerMeter; /* X pixels per meter */
+ int biYPelsPerMeter; /* Y pixels per meter */
+ unsigned int biClrUsed; /* Number of colors used */
+ unsigned int biClrImportant; /* Number of important colors */
+} BITMAPINFOHEADER;
diff --git a/board/esd/common/misc.c b/board/esd/common/misc.c
new file mode 100644
index 0000000..79cd612
--- /dev/null
+++ b/board/esd/common/misc.c
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_LXT971_NO_SLEEP
+#include <miiphy.h>
+#endif
+
+
+#ifdef CONFIG_LXT971_NO_SLEEP
+void lxt971_no_sleep(void)
+{
+ unsigned short reg;
+
+ miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, ®);
+ reg &= ~0x0040; /* disable sleep mode */
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg);
+}
+#endif /* CONFIG_LXT971_NO_SLEEP */
diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c
new file mode 100644
index 0000000..faebdb1
--- /dev/null
+++ b/board/esd/common/pci.c
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+
+u_long pci9054_iobase;
+
+
+#define PCI_PRIMARY_CAR (0x500000dc) /* PCI config address reg */
+#define PCI_PRIMARY_CDR (0x80000000) /* PCI config data reg */
+
+
+/*-----------------------------------------------------------------------------+
+| Subroutine: pci9054_read_config_dword
+| Description: Read a PCI configuration register
+| Inputs:
+| hose PCI Controller
+| dev PCI Bus+Device+Function number
+| offset Configuration register number
+| value Address of the configuration register value
+| Return value:
+| 0 Successful
++-----------------------------------------------------------------------------*/
+int pci9054_read_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32* value)
+{
+ unsigned long conAdrVal;
+ unsigned long val;
+
+ /* generate coded value for CON_ADR register */
+ conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+ /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
+ *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+ /* Note: *pResult comes back as -1 if machine check happened */
+ val = in32r(PCI_PRIMARY_CDR);
+
+ *value = (unsigned long) val;
+
+ out32r(PCI_PRIMARY_CAR, 0);
+
+ if ((*(unsigned long *)0x50000304) & 0x60000000)
+ {
+ /* clear pci master/target abort bits */
+ *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+ }
+
+ return 0;
+}
+
+/*-----------------------------------------------------------------------------+
+| Subroutine: pci9054_write_config_dword
+| Description: Write a PCI configuration register.
+| Inputs:
+| hose PCI Controller
+| dev PCI Bus+Device+Function number
+| offset Configuration register number
+| Value Configuration register value
+| Return value:
+| 0 Successful
+| Updated for pass2 errata #6. Need to disable interrupts and clear the
+| PCICFGADR reg after writing the PCICFGDATA reg.
++-----------------------------------------------------------------------------*/
+int pci9054_write_config_dword(struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 value)
+{
+ unsigned long conAdrVal;
+
+ conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+ *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+ out32r(PCI_PRIMARY_CDR, value);
+
+ out32r(PCI_PRIMARY_CAR, 0);
+
+ /* clear pci master/target abort bits */
+ *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+#ifdef CONFIG_DASA_SIM
+static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
+ struct pci_config_table *_)
+{
+ unsigned int iobase;
+ unsigned short status = 0;
+ unsigned char timer;
+
+ /*
+ * Configure PLX PCI9054
+ */
+ pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status);
+ status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+ pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status);
+
+ /* Check the latency timer for values >= 0x60.
+ */
+ pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
+ if (timer < 0x60)
+ {
+ pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
+ }
+
+ /* Set I/O base register.
+ */
+ pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE);
+ pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
+
+ pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
+
+ if (pci9054_iobase == 0xffffffff)
+ {
+ printf("Error: Can not set I/O base register.\n");
+ return;
+ }
+}
+#endif
+
+static struct pci_config_table pci9054_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN),
+ pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE,
+ CONFIG_SYS_ETH_IOBASE,
+ PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
+#ifdef CONFIG_DASA_SIM
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN),
+ pci_dasa_sim_config_pci9054 },
+#endif
+#endif
+ { }
+};
+
+static struct pci_controller pci9054_hose = {
+ config_table: pci9054_config_table,
+};
+
+void pci_init_board(void)
+{
+ struct pci_controller *hose = &pci9054_hose;
+
+ /*
+ * Register the hose
+ */
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ /* System memory space */
+ pci_set_region(hose->regions + 0,
+ 0x00000000, 0x00000000, 0x01000000,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+ /* PCI Memory space */
+ pci_set_region(hose->regions + 1,
+ 0x00000000, 0xc0000000, 0x10000000,
+ PCI_REGION_MEM);
+
+ pci_set_ops(hose,
+ pci_hose_read_config_byte_via_dword,
+ pci_hose_read_config_word_via_dword,
+ pci9054_read_config_dword,
+ pci_hose_write_config_byte_via_dword,
+ pci_hose_write_config_word_via_dword,
+ pci9054_write_config_dword);
+
+ hose->region_count = 2;
+
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+}
diff --git a/board/esd/common/s1d13505_640_480_16bpp.h b/board/esd/common/s1d13505_640_480_16bpp.h
new file mode 100644
index 0000000..ca11683
--- /dev/null
+++ b/board/esd/common/s1d13505_640_480_16bpp.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Panel: 640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz)
+ * Memory: DRAM (MCLK=40.000 MHz)
+ */
+static S1D_REGS regs_13505_640_480_16bpp[] =
+{
+ {0x1B,0x00}, /* Miscellaneous Register */
+ {0x23,0x20}, /* Performance Enhancement Register 1 */
+ {0x01,0x30}, /* Memory Configuration Register */
+ {0x22,0x24}, /* Performance Enhancement Register 0 */
+ {0x02,0x25}, /* Panel Type Register */
+ {0x03,0x00}, /* MOD Rate Register */
+ {0x04,0x4F}, /* Horizontal Display Width Register */
+ {0x05,0x0c}, /* Horizontal Non-Display Period Register */
+ {0x06,0x00}, /* HRTC/FPLINE Start Position Register */
+ {0x07,0x01}, /* HRTC/FPLINE Pulse Width Register */
+ {0x08,0xDF}, /* Vertical Display Height Register 0 */
+ {0x09,0x01}, /* Vertical Display Height Register 1 */
+ {0x0A,0x3E}, /* Vertical Non-Display Period Register */
+ {0x0B,0x00}, /* VRTC/FPFRAME Start Position Register */
+ {0x0C,0x01}, /* VRTC/FPFRAME Pulse Width Register */
+ {0x0E,0xFF}, /* Screen 1 Line Compare Register 0 */
+ {0x0F,0x03}, /* Screen 1 Line Compare Register 1 */
+ {0x10,0x00}, /* Screen 1 Display Start Address Register 0 */
+ {0x11,0x00}, /* Screen 1 Display Start Address Register 1 */
+ {0x12,0x00}, /* Screen 1 Display Start Address Register 2 */
+ {0x13,0x00}, /* Screen 2 Display Start Address Register 0 */
+ {0x14,0x00}, /* Screen 2 Display Start Address Register 1 */
+ {0x15,0x00}, /* Screen 2 Display Start Address Register 2 */
+ {0x16,0x80}, /* Memory Address Offset Register 0 */
+ {0x17,0x02}, /* Memory Address Offset Register 1 */
+ {0x18,0x00}, /* Pixel Panning Register */
+ {0x19,0x01}, /* Clock Configuration Register */
+ {0x1A,0x00}, /* Power Save Configuration Register */
+ {0x1C,0x00}, /* MD Configuration Readback Register 0 */
+ {0x1E,0x06}, /* General IO Pins Configuration Register 0 */
+ {0x1F,0x00}, /* General IO Pins Configuration Register 1 */
+ {0x20,0x00}, /* General IO Pins Control Register 0 */
+ {0x21,0x00}, /* General IO Pins Control Register 1 */
+ {0x23,0x20}, /* Performance Enhancement Register 1 */
+ {0x0D,0x15}, /* Display Mode Register */
+};
diff --git a/board/esd/common/s1d13704_320_240_4bpp.h b/board/esd/common/s1d13704_320_240_4bpp.h
new file mode 100644
index 0000000..bd910e8
--- /dev/null
+++ b/board/esd/common/s1d13704_320_240_4bpp.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generic Header information generated by 13704CFG.EXE (Build 10)
+ * Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz)
+ */
+
+static S1D_REGS regs_13704_320_240_4bpp[] =
+{
+ { 0x00, 0x00 }, /* Revision Code Register */
+ { 0x01, 0x04 }, /*00*/ /* Mode Register 0 Register */
+ { 0x02, 0xA4 }, /*a0*/ /* Mode Register 1 Register */
+ { 0x03, 0x83 }, /*03*/ /* Mode Register 2 Register - bit7 is LUT bypass */
+ { 0x04, 0x27 }, /* Horizontal Panel Size Register */
+ { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */
+ { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */
+ { 0x07, 0x00 }, /* FPLINE Start Position Register */
+ { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */
+ { 0x09, 0x00 }, /* FPFRAME Start Position Register */
+ { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */
+ { 0x0B, 0x00 }, /* MOD Rate Register */
+ { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */
+ { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */
+ { 0x0E, 0x00 }, /* Not Used */
+ { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */
+ { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */
+ { 0x11, 0x00 }, /* Not Used */
+ { 0x12, 0x00 }, /* Memory Address Offset Register */
+ { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */
+ { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */
+ { 0x15, 0x00 }, /* Look-Up Table Address Register */
+ { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */
+ { 0x17, 0x00 }, /* Look-Up Table Data Register */
+ { 0x18, 0x01 }, /* GPIO Configuration Control Register */
+ { 0x19, 0x01 }, /* GPIO Status/Control Register */
+ { 0x1A, 0x00 }, /* Scratch Pad Register */
+ { 0x1B, 0x00 }, /* SwivelView Mode Register */
+ { 0x1C, 0xA0 }, /* Line Byte Count Register */
+ { 0x1D, 0x00 }, /* Not Used */
+ { 0x1E, 0x00 }, /* Not Used */
+ { 0x1F, 0x00 }, /* Not Used */
+};
diff --git a/board/esd/common/s1d13705_320_240_8bpp.h b/board/esd/common/s1d13705_320_240_8bpp.h
new file mode 100644
index 0000000..041b4a9
--- /dev/null
+++ b/board/esd/common/s1d13705_320_240_8bpp.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generic Header information generated by 13704CFG.EXE (Build 10)
+ * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
+ */
+
+static S1D_REGS regs_13705_320_240_8bpp[] =
+{
+ { 0x00, 0x00 }, /* Revision Code Register */
+ { 0x01, 0x23 }, /* Mode Register 0 Register */
+ { 0x02, 0xE0 }, /* Mode Register 1 Register */
+ { 0x03, 0x03 }, /* Mode Register 2 Register - bit7 is LUT bypass */
+ { 0x04, 0x27 }, /* Horizontal Panel Size Register */
+ { 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */
+ { 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */
+ { 0x07, 0x00 }, /* FPLINE Start Position Register */
+ { 0x08, 0x00 }, /* Horizontal Non-Display Period Register */
+ { 0x09, 0x01 }, /* FPFRAME Start Position Register */
+ { 0x0A, 0x02 }, /* Vertical Non-Display Period Register */
+ { 0x0B, 0x00 }, /* MOD Rate Register */
+ { 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */
+ { 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */
+ { 0x0E, 0x00 }, /* Not Used */
+ { 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */
+ { 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */
+ { 0x11, 0x00 }, /* Not Used */
+ { 0x12, 0x00 }, /* Memory Address Offset Register */
+ { 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */
+ { 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */
+ { 0x15, 0x00 }, /* Look-Up Table Address Register */
+ { 0x16, 0x00 }, /* Look-Up Table Bank Select Register */
+ { 0x17, 0x00 }, /* Look-Up Table Data Register */
+ { 0x18, 0x01 }, /* GPIO Configuration Control Register */
+ { 0x19, 0x01 }, /* GPIO Status/Control Register */
+ { 0x1A, 0x00 }, /* Scratch Pad Register */
+ { 0x1B, 0x00 }, /* SwivelView Mode Register */
+ { 0x1C, 0xFF }, /* Line Byte Count Register */
+ { 0x1D, 0x00 }, /* Not Used */
+ { 0x1E, 0x00 }, /* Not Used */
+ { 0x1F, 0x00 }, /* Not Used */
+};
diff --git a/board/esd/common/s1d13806_1024_768_8bpp.h b/board/esd/common/s1d13806_1024_768_8bpp.h
new file mode 100644
index 0000000..615fa33
--- /dev/null
+++ b/board/esd/common/s1d13806_1024_768_8bpp.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * File generated by S1D13806CFG.EXE
+ * Panel: (active) 1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz)
+ */
+
+static S1D_REGS regs_13806_1024_768_8bpp[] =
+{
+ {0x0001,0x00}, /* Miscellaneous Register */
+ {0x01FC,0x00}, /* Display Mode Register */
+ {0x0004,0x00}, /* General IO Pins Configuration Register 0 */
+ {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
+ {0x0008,0x00}, /* General IO Pins Control Register 0 */
+ {0x0009,0x00}, /* General IO Pins Control Register 1 */
+ {0x0010,0x00}, /* Memory Clock Configuration Register */
+ {0x0014,0x01}, /* LCD Pixel Clock Configuration Register */
+ {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */
+ {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
+ {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
+ {0x0021,0x03}, /* DRAM Refresh Rate Register */
+ {0x002A,0x00}, /* DRAM Timings Control Register 0 */
+ {0x002B,0x01}, /* DRAM Timings Control Register 1 */
+ {0x0020,0x80}, /* Memory Configuration Register */
+ {0x0030,0x55}, /* Panel Type Register */
+ {0x0031,0x00}, /* MOD Rate Register */
+ {0x0032,0x7F}, /* LCD Horizontal Display Width Register */
+ {0x0034,0x12}, /* LCD Horizontal Non-Display Period Register */
+ {0x0035,0x01}, /* TFT FPLINE Start Position Register */
+ {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
+ {0x0038,0xFF}, /* LCD Vertical Display Height Register 0 */
+ {0x0039,0x02}, /* LCD Vertical Display Height Register 1 */
+ {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
+ {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */
+ {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
+ {0x0040,0x03}, /* LCD Display Mode Register */
+ {0x0041,0x00}, /* LCD Miscellaneous Register */
+ {0x0042,0x00}, /* LCD Display Start Address Register 0 */
+ {0x0043,0x00}, /* LCD Display Start Address Register 1 */
+ {0x0044,0x00}, /* LCD Display Start Address Register 2 */
+ {0x0046,0x00}, /* LCD Memory Address Offset Register 0 */
+ {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
+ {0x0048,0x00}, /* LCD Pixel Panning Register */
+ {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
+ {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
+ {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
+ {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
+ {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
+ {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
+ {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
+ {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
+ {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
+ {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
+ {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
+ {0x005B,0x10}, /* TV Output Control Register */
+ {0x0060,0x03}, /* CRT/TV Display Mode Register */
+ {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
+ {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
+ {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
+ {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */
+ {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */
+ {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
+ {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
+ {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
+ {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
+ {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
+ {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
+ {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
+ {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
+ {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
+ {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
+ {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
+ {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
+ {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
+ {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
+ {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
+ {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
+ {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
+ {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
+ {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
+ {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
+ {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
+ {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
+ {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
+ {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
+ {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
+ {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
+ {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
+ {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
+ {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
+ {0x0100,0x00}, /* BitBlt Control Register 0 */
+ {0x0101,0x00}, /* BitBlt Control Register 1 */
+ {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
+ {0x0103,0x00}, /* BitBlt Operation Register */
+ {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
+ {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
+ {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
+ {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
+ {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
+ {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
+ {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
+ {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
+ {0x0110,0x00}, /* BitBlt Width Register 0 */
+ {0x0111,0x00}, /* BitBlt Width Register 1 */
+ {0x0112,0x00}, /* BitBlt Height Register 0 */
+ {0x0113,0x00}, /* BitBlt Height Register 1 */
+ {0x0114,0x00}, /* BitBlt Background Color Register 0 */
+ {0x0115,0x00}, /* BitBlt Background Color Register 1 */
+ {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
+ {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
+ {0x01E0,0x00}, /* Look-Up Table Mode Register */
+ {0x01E2,0x00}, /* Look-Up Table Address Register */
+ {0x01F0,0x10}, /* Power Save Configuration Register */
+ {0x01F1,0x00}, /* Power Save Status Register */
+ {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
+ {0x01FC,0x01}, /* Display Mode Register */
+};
diff --git a/board/esd/common/s1d13806_320_240_4bpp.h b/board/esd/common/s1d13806_320_240_4bpp.h
new file mode 100644
index 0000000..2531f47
--- /dev/null
+++ b/board/esd/common/s1d13806_320_240_4bpp.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * File generated by S1D13806CFG.EXE
+ * Panel: (active) 320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz)
+ */
+
+static S1D_REGS regs_13806_320_240_4bpp[] =
+{
+ {0x0001,0x00}, /* Miscellaneous Register */
+ {0x01FC,0x00}, /* Display Mode Register */
+ {0x0004,0x08}, /* General IO Pins Configuration Register 0 */
+ {0x0005,0x08}, /* General IO Pins Configuration Register 1 */
+ {0x0008,0x08}, /* General IO Pins Control Register 0 */
+ {0x0009,0x00}, /* General IO Pins Control Register 1 */
+ {0x0010,0x00}, /* Memory Clock Configuration Register */
+ {0x0014,0x32}, /* LCD Pixel Clock Configuration Register */
+ {0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */
+ {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
+ {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
+ {0x0021,0x03}, /* DRAM Refresh Rate Register */
+ {0x002A,0x00}, /* DRAM Timings Control Register 0 */
+ {0x002B,0x01}, /* DRAM Timings Control Register 1 */
+ {0x0020,0x80}, /* Memory Configuration Register */
+ {0x0030,0x00}, /* Panel Type Register */
+ {0x0031,0x00}, /* MOD Rate Register */
+ {0x0032,0x27}, /* LCD Horizontal Display Width Register */
+ {0x0034,0x03}, /* LCD Horizontal Non-Display Period Register */
+ {0x0035,0x01}, /* TFT FPLINE Start Position Register */
+ {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
+ {0x0038,0xEF}, /* LCD Vertical Display Height Register 0 */
+ {0x0039,0x00}, /* LCD Vertical Display Height Register 1 */
+ {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
+ {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */
+ {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
+ {0x0040,0x02}, /* LCD Display Mode Register */
+ {0x0041,0x00}, /* LCD Miscellaneous Register */
+ {0x0042,0x00}, /* LCD Display Start Address Register 0 */
+ {0x0043,0x00}, /* LCD Display Start Address Register 1 */
+ {0x0044,0x00}, /* LCD Display Start Address Register 2 */
+ {0x0046,0x50}, /* LCD Memory Address Offset Register 0 */
+ {0x0047,0x00}, /* LCD Memory Address Offset Register 1 */
+ {0x0048,0x00}, /* LCD Pixel Panning Register */
+ {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
+ {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
+ {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
+ {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
+ {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
+ {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
+ {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
+ {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
+ {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
+ {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
+ {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
+ {0x005B,0x10}, /* TV Output Control Register */
+ {0x0060,0x03}, /* CRT/TV Display Mode Register */
+ {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
+ {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
+ {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
+ {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */
+ {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */
+ {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
+ {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
+ {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
+ {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
+ {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
+ {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
+ {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
+ {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
+ {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
+ {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
+ {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
+ {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
+ {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
+ {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
+ {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
+ {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
+ {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
+ {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
+ {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
+ {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
+ {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
+ {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
+ {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
+ {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
+ {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
+ {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
+ {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
+ {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
+ {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
+ {0x0100,0x00}, /* BitBlt Control Register 0 */
+ {0x0101,0x00}, /* BitBlt Control Register 1 */
+ {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
+ {0x0103,0x00}, /* BitBlt Operation Register */
+ {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
+ {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
+ {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
+ {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
+ {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
+ {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
+ {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
+ {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
+ {0x0110,0x00}, /* BitBlt Width Register 0 */
+ {0x0111,0x00}, /* BitBlt Width Register 1 */
+ {0x0112,0x00}, /* BitBlt Height Register 0 */
+ {0x0113,0x00}, /* BitBlt Height Register 1 */
+ {0x0114,0x00}, /* BitBlt Background Color Register 0 */
+ {0x0115,0x00}, /* BitBlt Background Color Register 1 */
+ {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
+ {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
+ {0x01E0,0x00}, /* Look-Up Table Mode Register */
+ {0x01E2,0x00}, /* Look-Up Table Address Register */
+ {0x01F0,0x10}, /* Power Save Configuration Register */
+ {0x01F1,0x00}, /* Power Save Status Register */
+ {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
+ {0x01FC,0x01}, /* Display Mode Register */
+};
diff --git a/board/esd/common/s1d13806_640_480_16bpp.h b/board/esd/common/s1d13806_640_480_16bpp.h
new file mode 100644
index 0000000..38fc1a7
--- /dev/null
+++ b/board/esd/common/s1d13806_640_480_16bpp.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * File generated by S1D13806CFG.EXE
+ * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
+ */
+
+static S1D_REGS regs_13806_640_480_16bpp[] =
+{
+ {0x0001,0x00}, /* Miscellaneous Register */
+ {0x01FC,0x00}, /* Display Mode Register */
+ {0x0004,0x18}, /* General IO Pins Configuration Register 0 */
+ {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
+ {0x0008,0x18}, /* General IO Pins Control Register 0 */
+ {0x0009,0x00}, /* General IO Pins Control Register 1 */
+ {0x0010,0x00}, /* Memory Clock Configuration Register */
+ {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */
+ {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
+ {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
+ {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
+ {0x0021,0x03}, /* DRAM Refresh Rate Register */
+ {0x002A,0x00}, /* DRAM Timings Control Register 0 */
+ {0x002B,0x01}, /* DRAM Timings Control Register 1 */
+ {0x0020,0x80}, /* Memory Configuration Register */
+ {0x0030,0x25}, /* Panel Type Register */
+ {0x0031,0x00}, /* MOD Rate Register */
+ {0x0032,0x4F}, /* LCD Horizontal Display Width Register */
+ {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
+ {0x0035,0x00}, /* TFT FPLINE Start Position Register */
+ {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
+ {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
+ {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
+ {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */
+ {0x003B,0x00}, /* TFT FPFRAME Start Position Register */
+ {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
+ {0x0040,0x05}, /* LCD Display Mode Register */
+ {0x0041,0x00}, /* LCD Miscellaneous Register */
+ {0x0042,0x00}, /* LCD Display Start Address Register 0 */
+ {0x0043,0x00}, /* LCD Display Start Address Register 1 */
+ {0x0044,0x00}, /* LCD Display Start Address Register 2 */
+ {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
+ {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
+ {0x0048,0x00}, /* LCD Pixel Panning Register */
+ {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
+ {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
+ {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
+ {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
+ {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
+ {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
+ {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
+ {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
+ {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
+ {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
+ {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
+ {0x005B,0x10}, /* TV Output Control Register */
+ {0x0060,0x05}, /* CRT/TV Display Mode Register */
+ {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
+ {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
+ {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
+ {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
+ {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
+ {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
+ {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
+ {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
+ {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
+ {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
+ {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
+ {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
+ {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
+ {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
+ {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
+ {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
+ {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
+ {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
+ {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
+ {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
+ {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
+ {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
+ {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
+ {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
+ {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
+ {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
+ {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
+ {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
+ {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
+ {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
+ {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
+ {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
+ {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
+ {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
+ {0x0100,0x00}, /* BitBlt Control Register 0 */
+ {0x0101,0x00}, /* BitBlt Control Register 1 */
+ {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
+ {0x0103,0x00}, /* BitBlt Operation Register */
+ {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
+ {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
+ {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
+ {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
+ {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
+ {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
+ {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
+ {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
+ {0x0110,0x00}, /* BitBlt Width Register 0 */
+ {0x0111,0x00}, /* BitBlt Width Register 1 */
+ {0x0112,0x00}, /* BitBlt Height Register 0 */
+ {0x0113,0x00}, /* BitBlt Height Register 1 */
+ {0x0114,0x00}, /* BitBlt Background Color Register 0 */
+ {0x0115,0x00}, /* BitBlt Background Color Register 1 */
+ {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
+ {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
+ {0x01E0,0x00}, /* Look-Up Table Mode Register */
+ {0x01E2,0x00}, /* Look-Up Table Address Register */
+ {0x01F0,0x10}, /* Power Save Configuration Register */
+ {0x01F1,0x00}, /* Power Save Status Register */
+ {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
+ {0x01FC,0x01}, /* Display Mode Register */
+};
diff --git a/board/esd/common/xilinx_jtag/lenval.c b/board/esd/common/xilinx_jtag/lenval.c
new file mode 100644
index 0000000..5405efb
--- /dev/null
+++ b/board/esd/common/xilinx_jtag/lenval.c
@@ -0,0 +1,201 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*******************************************************/
+/* file: lenval.c */
+/* abstract: This file contains routines for using */
+/* the lenVal data structure. */
+/*******************************************************/
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include "lenval.h"
+#include "ports.h"
+
+
+/*****************************************************************************
+ * Function: value
+ * Description: Extract the long value from the lenval array.
+ * Parameters: plvValue - ptr to lenval.
+ * Returns: long - the extracted value.
+ *****************************************************************************/
+long value( lenVal* plvValue )
+{
+ long lValue; /* result to hold the accumulated result */
+ short sIndex;
+
+ lValue = 0;
+ for ( sIndex = 0; sIndex < plvValue->len ; ++sIndex )
+ {
+ lValue <<= 8; /* shift the accumulated result */
+ lValue |= plvValue->val[ sIndex]; /* get the last byte first */
+ }
+
+ return( lValue );
+}
+
+/*****************************************************************************
+ * Function: initLenVal
+ * Description: Initialize the lenval array with the given value.
+ * Assumes lValue is less than 256.
+ * Parameters: plv - ptr to lenval.
+ * lValue - the value to set.
+ * Returns: void.
+ *****************************************************************************/
+void initLenVal( lenVal* plv,
+ long lValue )
+{
+ plv->len = 1;
+ plv->val[0] = (unsigned char)lValue;
+}
+
+/*****************************************************************************
+ * Function: EqualLenVal
+ * Description: Compare two lenval arrays with an optional mask.
+ * Parameters: plvTdoExpected - ptr to lenval #1.
+ * plvTdoCaptured - ptr to lenval #2.
+ * plvTdoMask - optional ptr to mask (=0 if no mask).
+ * Returns: short - 0 = mismatch; 1 = equal.
+ *****************************************************************************/
+short EqualLenVal( lenVal* plvTdoExpected,
+ lenVal* plvTdoCaptured,
+ lenVal* plvTdoMask )
+{
+ short sEqual;
+ short sIndex;
+ unsigned char ucByteVal1;
+ unsigned char ucByteVal2;
+ unsigned char ucByteMask;
+
+ sEqual = 1;
+ sIndex = plvTdoExpected->len;
+
+ while ( sEqual && sIndex-- )
+ {
+ ucByteVal1 = plvTdoExpected->val[ sIndex ];
+ ucByteVal2 = plvTdoCaptured->val[ sIndex ];
+ if ( plvTdoMask )
+ {
+ ucByteMask = plvTdoMask->val[ sIndex ];
+ ucByteVal1 &= ucByteMask;
+ ucByteVal2 &= ucByteMask;
+ }
+ if ( ucByteVal1 != ucByteVal2 )
+ {
+ sEqual = 0;
+ }
+ }
+
+ return( sEqual );
+}
+
+
+/*****************************************************************************
+ * Function: RetBit
+ * Description: return the (byte, bit) of lv (reading from left to right).
+ * Parameters: plv - ptr to lenval.
+ * iByte - the byte to get the bit from.
+ * iBit - the bit number (0=msb)
+ * Returns: short - the bit value.
+ *****************************************************************************/
+short RetBit( lenVal* plv,
+ int iByte,
+ int iBit )
+{
+ /* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */
+ /* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */
+ return( (short)( ( plv->val[ iByte ] >> ( 7 - iBit ) ) & 0x1 ) );
+}
+
+/*****************************************************************************
+ * Function: SetBit
+ * Description: set the (byte, bit) of lv equal to val
+ * Example: SetBit("00000000",byte, 1) equals "01000000".
+ * Parameters: plv - ptr to lenval.
+ * iByte - the byte to get the bit from.
+ * iBit - the bit number (0=msb).
+ * sVal - the bit value to set.
+ * Returns: void.
+ *****************************************************************************/
+void SetBit( lenVal* plv,
+ int iByte,
+ int iBit,
+ short sVal )
+{
+ unsigned char ucByteVal;
+ unsigned char ucBitMask;
+
+ ucBitMask = (unsigned char)(1 << ( 7 - iBit ));
+ ucByteVal = (unsigned char)(plv->val[ iByte ] & (~ucBitMask));
+
+ if ( sVal )
+ {
+ ucByteVal |= ucBitMask;
+ }
+ plv->val[ iByte ] = ucByteVal;
+}
+
+/*****************************************************************************
+ * Function: AddVal
+ * Description: add val1 to val2 and store in resVal;
+ * assumes val1 and val2 are of equal length.
+ * Parameters: plvResVal - ptr to result.
+ * plvVal1 - ptr of addendum.
+ * plvVal2 - ptr of addendum.
+ * Returns: void.
+ *****************************************************************************/
+void addVal( lenVal* plvResVal,
+ lenVal* plvVal1,
+ lenVal* plvVal2 )
+{
+ unsigned char ucCarry;
+ unsigned short usSum;
+ unsigned short usVal1;
+ unsigned short usVal2;
+ short sIndex;
+
+ plvResVal->len = plvVal1->len; /* set up length of result */
+
+ /* start at least significant bit and add bytes */
+ ucCarry = 0;
+ sIndex = plvVal1->len;
+ while ( sIndex-- )
+ {
+ usVal1 = plvVal1->val[ sIndex ]; /* i'th byte of val1 */
+ usVal2 = plvVal2->val[ sIndex ]; /* i'th byte of val2 */
+
+ /* add the two bytes plus carry from previous addition */
+ usSum = (unsigned short)( usVal1 + usVal2 + ucCarry );
+
+ /* set up carry for next byte */
+ ucCarry = (unsigned char)( ( usSum > 255 ) ? 1 : 0 );
+
+ /* set the i'th byte of the result */
+ plvResVal->val[ sIndex ] = (unsigned char)usSum;
+ }
+}
+
+/*****************************************************************************
+ * Function: readVal
+ * Description: read from XSVF numBytes bytes of data into x.
+ * Parameters: plv - ptr to lenval in which to put the bytes read.
+ * sNumBytes - the number of bytes to read.
+ * Returns: void.
+ *****************************************************************************/
+void readVal( lenVal* plv,
+ short sNumBytes )
+{
+ unsigned char* pucVal;
+
+ plv->len = sNumBytes; /* set the length of the lenVal */
+ for ( pucVal = plv->val; sNumBytes; --sNumBytes, ++pucVal )
+ {
+ /* read a byte of data into the lenVal */
+ readByte( pucVal );
+ }
+}
diff --git a/board/esd/common/xilinx_jtag/lenval.h b/board/esd/common/xilinx_jtag/lenval.h
new file mode 100644
index 0000000..3273eec
--- /dev/null
+++ b/board/esd/common/xilinx_jtag/lenval.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*******************************************************/
+/* file: lenval.h */
+/* abstract: This file contains a description of the */
+/* data structure "lenval". */
+/*******************************************************/
+
+#ifndef lenval_dot_h
+#define lenval_dot_h
+
+/* the lenVal structure is a byte oriented type used to store an */
+/* arbitrary length binary value. As an example, the hex value */
+/* 0x0e3d is represented as a lenVal with len=2 (since 2 bytes */
+/* and val[0]=0e and val[1]=3d. val[2-MAX_LEN] are undefined */
+
+/* maximum length (in bytes) of value to read in */
+/* this needs to be at least 4, and longer than the */
+/* length of the longest SDR instruction. If there is, */
+/* only 1 device in the chain, MAX_LEN must be at least */
+/* ceil(27/8) == 4. For 6 devices in a chain, MAX_LEN */
+/* must be 5, for 14 devices MAX_LEN must be 6, for 20 */
+/* devices MAX_LEN must be 7, etc.. */
+/* You can safely set MAX_LEN to a smaller number if you*/
+/* know how many devices will be in your chain. */
+#define MAX_LEN 7000
+
+
+typedef struct var_len_byte
+{
+ short len; /* number of chars in this value */
+ unsigned char val[MAX_LEN+1]; /* bytes of data */
+} lenVal;
+
+
+/* return the long representation of a lenVal */
+extern long value(lenVal *x);
+
+/* set lenVal equal to value */
+extern void initLenVal(lenVal *x, long value);
+
+/* check if expected equals actual (taking the mask into account) */
+extern short EqualLenVal(lenVal *expected, lenVal *actual, lenVal *mask);
+
+/* add val1+val2 and put the result in resVal */
+extern void addVal(lenVal *resVal, lenVal *val1, lenVal *val2);
+
+/* return the (byte, bit) of lv (reading from left to right) */
+extern short RetBit(lenVal *lv, int byte, int bit);
+
+/* set the (byte, bit) of lv equal to val (e.g. SetBit("00000000",byte, 1)
+ equals "01000000" */
+extern void SetBit(lenVal *lv, int byte, int bit, short val);
+
+/* read from XSVF numBytes bytes of data into x */
+extern void readVal(lenVal *x, short numBytes);
+
+#endif
diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c
new file mode 100644
index 0000000..556636c
--- /dev/null
+++ b/board/esd/common/xilinx_jtag/micro.c
@@ -0,0 +1,1854 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*****************************************************************************
+ * file: micro.c
+ * abstract: This file contains the function, xsvfExecute(),
+ * call for interpreting the XSVF commands.
+ * Usage: Call xsvfExecute() to process XSVF data.
+ * The XSVF data is retrieved by readByte() in ports.c
+ * Remove the main function if you already have one.
+ * Options: XSVF_SUPPORT_COMPRESSION
+ * This define supports the XC9500/XL compression scheme.
+ * This define adds support for XSDRINC and XSETSDRMASKS.
+ * XSVF_SUPPORT_ERRORCODES
+ * This define causes the xsvfExecute function to return
+ * an error code for specific errors. See error codes below.
+ * If this is not defined, the return value defaults to the
+ * legacy values for backward compatibility:
+ * 1 = success; 0 = failure.
+ * Debugging: DEBUG_MODE (Legacy name)
+ * Define DEBUG_MODE to compile with debugging features.
+ * Both micro.c and ports.c must be compiled with the DEBUG_MODE
+ * defined to enable the standalone main implementation in
+ * micro.c that reads XSVF from a file.
+ * History: v2.00 - Original XSVF implementation.
+ * v4.04 - Added delay at end of XSIR for XC18v00 support.
+ * Added new commands for CoolRunner support:
+ * XSTATE, XENDIR, XENDDR
+ * v4.05 - Cleanup micro.c but leave ports.c intact.
+ * v4.06 - Fix xsvfGotoTapState for retry transition.
+ * v4.07 - Update example waitTime implementations for
+ * compatibility with Virtex-II.
+ * v4.10 - Add new XSIR2 command that supports a 2-byte
+ * IR-length parameter for IR shifts > 255 bits.
+ * v4.11 - No change. Update version to match SVF2XSVF xlator.
+ * v4.14 - Added XCOMMENT.
+ * v5.00 - Improve XSTATE support.
+ * Added XWAIT.
+ *****************************************************************************/
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+#include "micro.h"
+#include "lenval.h"
+#include "ports.h"
+
+const unsigned char *xsvfdata;
+
+/*============================================================================
+ * XSVF #define
+ ============================================================================*/
+
+#define XSVF_VERSION "5.00"
+
+/*****************************************************************************
+ * Define: XSVF_SUPPORT_COMPRESSION
+ * Description: Define this to support the XC9500/XL XSVF data compression
+ * scheme.
+ * Code size can be reduced by NOT supporting this feature.
+ * However, you must use the -nc (no compress) option when
+ * translating SVF to XSVF using the SVF2XSVF translator.
+ * Corresponding, uncompressed XSVF may be larger.
+ *****************************************************************************/
+#ifndef XSVF_SUPPORT_COMPRESSION
+#define XSVF_SUPPORT_COMPRESSION 1
+#endif
+
+/*****************************************************************************
+ * Define: XSVF_SUPPORT_ERRORCODES
+ * Description: Define this to support the new XSVF error codes.
+ * (The original XSVF player just returned 1 for success and
+ * 0 for an unspecified failure.)
+ *****************************************************************************/
+#ifndef XSVF_SUPPORT_ERRORCODES
+#define XSVF_SUPPORT_ERRORCODES 1
+#endif
+
+#ifdef XSVF_SUPPORT_ERRORCODES
+#define XSVF_ERRORCODE(errorCode) errorCode
+#else /* Use legacy error code */
+#define XSVF_ERRORCODE(errorCode) ((errorCode==XSVF_ERROR_NONE)?1:0)
+#endif /* XSVF_SUPPORT_ERRORCODES */
+
+
+/*============================================================================
+ * DEBUG_MODE #define
+ ============================================================================*/
+#define DEBUG_MODE
+
+#ifdef DEBUG_MODE
+#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ printf( pzFormat ); }
+#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ printf( pzFormat, arg1 ); }
+#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ printf( pzFormat, arg1, arg2 ); }
+#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ printf( pzFormat, arg1, arg2, arg3 ); }
+#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ xsvfPrintLenVal(plenVal); }
+#else /* !DEBUG_MODE */
+#define XSVFDBG_PRINTF(iDebugLevel,pzFormat)
+#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1)
+#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2)
+#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3)
+#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal)
+#endif /* DEBUG_MODE */
+
+
+/*============================================================================
+ * XSVF Type Declarations
+ ============================================================================*/
+
+/*****************************************************************************
+ * Struct: SXsvfInfo
+ * Description: This structure contains all of the data used during the
+ * execution of the XSVF. Some data is persistent, predefined
+ * information (e.g. lRunTestTime). The bulk of this struct's
+ * size is due to the lenVal structs (defined in lenval.h)
+ * which contain buffers for the active shift data. The MAX_LEN
+ * #define in lenval.h defines the size of these buffers.
+ * These buffers must be large enough to store the longest
+ * shift data in your XSVF file. For example:
+ * MAX_LEN >= ( longest_shift_data_in_bits / 8 )
+ * Because the lenVal struct dominates the space usage of this
+ * struct, the rough size of this struct is:
+ * sizeof( SXsvfInfo ) ~= MAX_LEN * 7 (number of lenVals)
+ * xsvfInitialize() contains initialization code for the data
+ * in this struct.
+ * xsvfCleanup() contains cleanup code for the data in this
+ * struct.
+ *****************************************************************************/
+typedef struct tagSXsvfInfo
+{
+ /* XSVF status information */
+ unsigned char ucComplete; /* 0 = running; 1 = complete */
+ unsigned char ucCommand; /* Current XSVF command byte */
+ long lCommandCount; /* Number of commands processed */
+ int iErrorCode; /* An error code. 0 = no error. */
+
+ /* TAP state/sequencing information */
+ unsigned char ucTapState; /* Current TAP state */
+ unsigned char ucEndIR; /* ENDIR TAP state (See SVF) */
+ unsigned char ucEndDR; /* ENDDR TAP state (See SVF) */
+
+ /* RUNTEST information */
+ unsigned char ucMaxRepeat; /* Max repeat loops (for xc9500/xl) */
+ long lRunTestTime; /* Pre-specified RUNTEST time (usec) */
+
+ /* Shift Data Info and Buffers */
+ long lShiftLengthBits; /* Len. current shift data in bits */
+ short sShiftLengthBytes; /* Len. current shift data in bytes */
+
+ lenVal lvTdi; /* Current TDI shift data */
+ lenVal lvTdoExpected; /* Expected TDO shift data */
+ lenVal lvTdoCaptured; /* Captured TDO shift data */
+ lenVal lvTdoMask; /* TDO mask: 0=dontcare; 1=compare */
+
+#ifdef XSVF_SUPPORT_COMPRESSION
+ /* XSDRINC Data Buffers */
+ lenVal lvAddressMask; /* Address mask for XSDRINC */
+ lenVal lvDataMask; /* Data mask for XSDRINC */
+ lenVal lvNextData; /* Next data for XSDRINC */
+#endif /* XSVF_SUPPORT_COMPRESSION */
+} SXsvfInfo;
+
+/* Declare pointer to functions that perform XSVF commands */
+typedef int (*TXsvfDoCmdFuncPtr)( SXsvfInfo* );
+
+/*============================================================================
+ * XSVF Command Bytes
+ ============================================================================*/
+
+/* encodings of xsvf instructions */
+#define XCOMPLETE 0
+#define XTDOMASK 1
+#define XSIR 2
+#define XSDR 3
+#define XRUNTEST 4
+/* Reserved 5 */
+/* Reserved 6 */
+#define XREPEAT 7
+#define XSDRSIZE 8
+#define XSDRTDO 9
+#define XSETSDRMASKS 10
+#define XSDRINC 11
+#define XSDRB 12
+#define XSDRC 13
+#define XSDRE 14
+#define XSDRTDOB 15
+#define XSDRTDOC 16
+#define XSDRTDOE 17
+#define XSTATE 18 /* 4.00 */
+#define XENDIR 19 /* 4.04 */
+#define XENDDR 20 /* 4.04 */
+#define XSIR2 21 /* 4.10 */
+#define XCOMMENT 22 /* 4.14 */
+#define XWAIT 23 /* 5.00 */
+/* Insert new commands here */
+/* and add corresponding xsvfDoCmd function to xsvf_pfDoCmd below. */
+#define XLASTCMD 24 /* Last command marker */
+
+
+/*============================================================================
+ * XSVF Command Parameter Values
+ ============================================================================*/
+
+#define XSTATE_RESET 0 /* 4.00 parameter for XSTATE */
+#define XSTATE_RUNTEST 1 /* 4.00 parameter for XSTATE */
+
+#define XENDXR_RUNTEST 0 /* 4.04 parameter for XENDIR/DR */
+#define XENDXR_PAUSE 1 /* 4.04 parameter for XENDIR/DR */
+
+/* TAP states */
+#define XTAPSTATE_RESET 0x00
+#define XTAPSTATE_RUNTEST 0x01 /* a.k.a. IDLE */
+#define XTAPSTATE_SELECTDR 0x02
+#define XTAPSTATE_CAPTUREDR 0x03
+#define XTAPSTATE_SHIFTDR 0x04
+#define XTAPSTATE_EXIT1DR 0x05
+#define XTAPSTATE_PAUSEDR 0x06
+#define XTAPSTATE_EXIT2DR 0x07
+#define XTAPSTATE_UPDATEDR 0x08
+#define XTAPSTATE_IRSTATES 0x09 /* All IR states begin here */
+#define XTAPSTATE_SELECTIR 0x09
+#define XTAPSTATE_CAPTUREIR 0x0A
+#define XTAPSTATE_SHIFTIR 0x0B
+#define XTAPSTATE_EXIT1IR 0x0C
+#define XTAPSTATE_PAUSEIR 0x0D
+#define XTAPSTATE_EXIT2IR 0x0E
+#define XTAPSTATE_UPDATEIR 0x0F
+
+/*============================================================================
+ * XSVF Function Prototypes
+ ============================================================================*/
+
+int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo ); /* Illegal command function */
+int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSIR( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDR( SXsvfInfo* pXsvfInfo );
+int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo );
+int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo );
+int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo );
+int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo );
+/* Insert new command functions here */
+
+/*============================================================================
+ * XSVF Global Variables
+ ============================================================================*/
+
+/* Array of XSVF command functions. Must follow command byte value order! */
+/* If your compiler cannot take this form, then convert to a switch statement*/
+TXsvfDoCmdFuncPtr xsvf_pfDoCmd[] =
+{
+ xsvfDoXCOMPLETE, /* 0 */
+ xsvfDoXTDOMASK, /* 1 */
+ xsvfDoXSIR, /* 2 */
+ xsvfDoXSDR, /* 3 */
+ xsvfDoXRUNTEST, /* 4 */
+ xsvfDoIllegalCmd, /* 5 */
+ xsvfDoIllegalCmd, /* 6 */
+ xsvfDoXREPEAT, /* 7 */
+ xsvfDoXSDRSIZE, /* 8 */
+ xsvfDoXSDRTDO, /* 9 */
+#ifdef XSVF_SUPPORT_COMPRESSION
+ xsvfDoXSETSDRMASKS, /* 10 */
+ xsvfDoXSDRINC, /* 11 */
+#else
+ xsvfDoIllegalCmd, /* 10 */
+ xsvfDoIllegalCmd, /* 11 */
+#endif /* XSVF_SUPPORT_COMPRESSION */
+ xsvfDoXSDRBCE, /* 12 */
+ xsvfDoXSDRBCE, /* 13 */
+ xsvfDoXSDRBCE, /* 14 */
+ xsvfDoXSDRTDOBCE, /* 15 */
+ xsvfDoXSDRTDOBCE, /* 16 */
+ xsvfDoXSDRTDOBCE, /* 17 */
+ xsvfDoXSTATE, /* 18 */
+ xsvfDoXENDXR, /* 19 */
+ xsvfDoXENDXR, /* 20 */
+ xsvfDoXSIR2, /* 21 */
+ xsvfDoXCOMMENT, /* 22 */
+ xsvfDoXWAIT /* 23 */
+/* Insert new command functions here */
+};
+
+#ifdef DEBUG_MODE
+char* xsvf_pzCommandName[] =
+{
+ "XCOMPLETE",
+ "XTDOMASK",
+ "XSIR",
+ "XSDR",
+ "XRUNTEST",
+ "Reserved5",
+ "Reserved6",
+ "XREPEAT",
+ "XSDRSIZE",
+ "XSDRTDO",
+ "XSETSDRMASKS",
+ "XSDRINC",
+ "XSDRB",
+ "XSDRC",
+ "XSDRE",
+ "XSDRTDOB",
+ "XSDRTDOC",
+ "XSDRTDOE",
+ "XSTATE",
+ "XENDIR",
+ "XENDDR",
+ "XSIR2",
+ "XCOMMENT",
+ "XWAIT"
+};
+
+char* xsvf_pzErrorName[] =
+{
+ "No error",
+ "ERROR: Unknown",
+ "ERROR: TDO mismatch",
+ "ERROR: TDO mismatch and exceeded max retries",
+ "ERROR: Unsupported XSVF command",
+ "ERROR: Illegal state specification",
+ "ERROR: Data overflows allocated MAX_LEN buffer size"
+};
+
+char* xsvf_pzTapState[] =
+{
+ "RESET", /* 0x00 */
+ "RUNTEST/IDLE", /* 0x01 */
+ "DRSELECT", /* 0x02 */
+ "DRCAPTURE", /* 0x03 */
+ "DRSHIFT", /* 0x04 */
+ "DREXIT1", /* 0x05 */
+ "DRPAUSE", /* 0x06 */
+ "DREXIT2", /* 0x07 */
+ "DRUPDATE", /* 0x08 */
+ "IRSELECT", /* 0x09 */
+ "IRCAPTURE", /* 0x0A */
+ "IRSHIFT", /* 0x0B */
+ "IREXIT1", /* 0x0C */
+ "IRPAUSE", /* 0x0D */
+ "IREXIT2", /* 0x0E */
+ "IRUPDATE" /* 0x0F */
+};
+#endif /* DEBUG_MODE */
+
+/*#ifdef DEBUG_MODE */
+/* FILE* in; /XXX* Legacy DEBUG_MODE file pointer */
+int xsvf_iDebugLevel;
+/*#endif /XXX* DEBUG_MODE */
+
+/*============================================================================
+ * Utility Functions
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function: xsvfPrintLenVal
+ * Description: Print the lenval value in hex.
+ * Parameters: plv - ptr to lenval.
+ * Returns: void.
+ *****************************************************************************/
+#ifdef DEBUG_MODE
+void xsvfPrintLenVal( lenVal *plv )
+{
+ int i;
+
+ if ( plv )
+ {
+ printf( "0x" );
+ for ( i = 0; i < plv->len; ++i )
+ {
+ printf( "%02x", ((unsigned int)(plv->val[ i ])) );
+ }
+ }
+}
+#endif /* DEBUG_MODE */
+
+
+/*****************************************************************************
+ * Function: xsvfInfoInit
+ * Description: Initialize the xsvfInfo data.
+ * Parameters: pXsvfInfo - ptr to the XSVF info structure.
+ * Returns: int - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfInfoInit( SXsvfInfo* pXsvfInfo )
+{
+ XSVFDBG_PRINTF1( 4, " sizeof( SXsvfInfo ) = %d bytes\n",
+ sizeof( SXsvfInfo ) );
+
+ pXsvfInfo->ucComplete = 0;
+ pXsvfInfo->ucCommand = XCOMPLETE;
+ pXsvfInfo->lCommandCount = 0;
+ pXsvfInfo->iErrorCode = XSVF_ERROR_NONE;
+ pXsvfInfo->ucMaxRepeat = 0;
+ pXsvfInfo->ucTapState = XTAPSTATE_RESET;
+ pXsvfInfo->ucEndIR = XTAPSTATE_RUNTEST;
+ pXsvfInfo->ucEndDR = XTAPSTATE_RUNTEST;
+ pXsvfInfo->lShiftLengthBits = 0L;
+ pXsvfInfo->sShiftLengthBytes= 0;
+ pXsvfInfo->lRunTestTime = 0L;
+
+ return( 0 );
+}
+
+/*****************************************************************************
+ * Function: xsvfInfoCleanup
+ * Description: Cleanup the xsvfInfo data.
+ * Parameters: pXsvfInfo - ptr to the XSVF info structure.
+ * Returns: void.
+ *****************************************************************************/
+void xsvfInfoCleanup( SXsvfInfo* pXsvfInfo )
+{
+}
+
+/*****************************************************************************
+ * Function: xsvfGetAsNumBytes
+ * Description: Calculate the number of bytes the given number of bits
+ * consumes.
+ * Parameters: lNumBits - the number of bits.
+ * Returns: short - the number of bytes to store the number of bits.
+ *****************************************************************************/
+short xsvfGetAsNumBytes( long lNumBits )
+{
+ return( (short)( ( lNumBits + 7L ) / 8L ) );
+}
+
+/*****************************************************************************
+ * Function: xsvfTmsTransition
+ * Description: Apply TMS and transition TAP controller by applying one TCK
+ * cycle.
+ * Parameters: sTms - new TMS value.
+ * Returns: void.
+ *****************************************************************************/
+void xsvfTmsTransition( short sTms )
+{
+ setPort( TMS, sTms );
+ setPort( TCK, 0 );
+ setPort( TCK, 1 );
+}
+
+/*****************************************************************************
+ * Function: xsvfGotoTapState
+ * Description: From the current TAP state, go to the named TAP state.
+ * A target state of RESET ALWAYS causes TMS reset sequence.
+ * All SVF standard stable state paths are supported.
+ * All state transitions are supported except for the following
+ * which cause an XSVF_ERROR_ILLEGALSTATE:
+ * - Target==DREXIT2; Start!=DRPAUSE
+ * - Target==IREXIT2; Start!=IRPAUSE
+ * Parameters: pucTapState - Current TAP state; returns final TAP state.
+ * ucTargetState - New target TAP state.
+ * Returns: int - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfGotoTapState( unsigned char* pucTapState,
+ unsigned char ucTargetState )
+{
+ int i;
+ int iErrorCode;
+
+ iErrorCode = XSVF_ERROR_NONE;
+ if ( ucTargetState == XTAPSTATE_RESET )
+ {
+ /* If RESET, always perform TMS reset sequence to reset/sync TAPs */
+ xsvfTmsTransition( 1 );
+ for ( i = 0; i < 5; ++i )
+ {
+ setPort( TCK, 0 );
+ setPort( TCK, 1 );
+ }
+ *pucTapState = XTAPSTATE_RESET;
+ XSVFDBG_PRINTF( 3, " TMS Reset Sequence -> Test-Logic-Reset\n" );
+ XSVFDBG_PRINTF1( 3, " TAP State = %s\n",
+ xsvf_pzTapState[ *pucTapState ] );
+ } else if ( ( ucTargetState != *pucTapState ) &&
+ ( ( ( ucTargetState == XTAPSTATE_EXIT2DR ) && ( *pucTapState != XTAPSTATE_PAUSEDR ) ) ||
+ ( ( ucTargetState == XTAPSTATE_EXIT2IR ) && ( *pucTapState != XTAPSTATE_PAUSEIR ) ) ) )
+ {
+ /* Trap illegal TAP state path specification */
+ iErrorCode = XSVF_ERROR_ILLEGALSTATE;
+ } else {
+ if ( ucTargetState == *pucTapState )
+ {
+ /* Already in target state. Do nothing except when in DRPAUSE
+ or in IRPAUSE to comply with SVF standard */
+ if ( ucTargetState == XTAPSTATE_PAUSEDR )
+ {
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_EXIT2DR;
+ XSVFDBG_PRINTF1( 3, " TAP State = %s\n",
+ xsvf_pzTapState[ *pucTapState ] );
+ }
+ else if ( ucTargetState == XTAPSTATE_PAUSEIR )
+ {
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_EXIT2IR;
+ XSVFDBG_PRINTF1( 3, " TAP State = %s\n",
+ xsvf_pzTapState[ *pucTapState ] );
+ }
+ }
+
+ /* Perform TAP state transitions to get to the target state */
+ while ( ucTargetState != *pucTapState )
+ {
+ switch ( *pucTapState )
+ {
+ case XTAPSTATE_RESET:
+ xsvfTmsTransition( 0 );
+ *pucTapState = XTAPSTATE_RUNTEST;
+ break;
+ case XTAPSTATE_RUNTEST:
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_SELECTDR;
+ break;
+ case XTAPSTATE_SELECTDR:
+ if ( ucTargetState >= XTAPSTATE_IRSTATES )
+ {
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_SELECTIR;
+ }
+ else
+ {
+ xsvfTmsTransition( 0 );
+ *pucTapState = XTAPSTATE_CAPTUREDR;
+ }
+ break;
+ case XTAPSTATE_CAPTUREDR:
+ if ( ucTargetState == XTAPSTATE_SHIFTDR )
+ {
+ xsvfTmsTransition( 0 );
+ *pucTapState = XTAPSTATE_SHIFTDR;
+ }
+ else
+ {
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_EXIT1DR;
+ }
+ break;
+ case XTAPSTATE_SHIFTDR:
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_EXIT1DR;
+ break;
+ case XTAPSTATE_EXIT1DR:
+ if ( ucTargetState == XTAPSTATE_PAUSEDR )
+ {
+ xsvfTmsTransition( 0 );
+ *pucTapState = XTAPSTATE_PAUSEDR;
+ }
+ else
+ {
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_UPDATEDR;
+ }
+ break;
+ case XTAPSTATE_PAUSEDR:
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_EXIT2DR;
+ break;
+ case XTAPSTATE_EXIT2DR:
+ if ( ucTargetState == XTAPSTATE_SHIFTDR )
+ {
+ xsvfTmsTransition( 0 );
+ *pucTapState = XTAPSTATE_SHIFTDR;
+ }
+ else
+ {
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_UPDATEDR;
+ }
+ break;
+ case XTAPSTATE_UPDATEDR:
+ if ( ucTargetState == XTAPSTATE_RUNTEST )
+ {
+ xsvfTmsTransition( 0 );
+ *pucTapState = XTAPSTATE_RUNTEST;
+ }
+ else
+ {
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_SELECTDR;
+ }
+ break;
+ case XTAPSTATE_SELECTIR:
+ xsvfTmsTransition( 0 );
+ *pucTapState = XTAPSTATE_CAPTUREIR;
+ break;
+ case XTAPSTATE_CAPTUREIR:
+ if ( ucTargetState == XTAPSTATE_SHIFTIR )
+ {
+ xsvfTmsTransition( 0 );
+ *pucTapState = XTAPSTATE_SHIFTIR;
+ }
+ else
+ {
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_EXIT1IR;
+ }
+ break;
+ case XTAPSTATE_SHIFTIR:
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_EXIT1IR;
+ break;
+ case XTAPSTATE_EXIT1IR:
+ if ( ucTargetState == XTAPSTATE_PAUSEIR )
+ {
+ xsvfTmsTransition( 0 );
+ *pucTapState = XTAPSTATE_PAUSEIR;
+ }
+ else
+ {
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_UPDATEIR;
+ }
+ break;
+ case XTAPSTATE_PAUSEIR:
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_EXIT2IR;
+ break;
+ case XTAPSTATE_EXIT2IR:
+ if ( ucTargetState == XTAPSTATE_SHIFTIR )
+ {
+ xsvfTmsTransition( 0 );
+ *pucTapState = XTAPSTATE_SHIFTIR;
+ }
+ else
+ {
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_UPDATEIR;
+ }
+ break;
+ case XTAPSTATE_UPDATEIR:
+ if ( ucTargetState == XTAPSTATE_RUNTEST )
+ {
+ xsvfTmsTransition( 0 );
+ *pucTapState = XTAPSTATE_RUNTEST;
+ }
+ else
+ {
+ xsvfTmsTransition( 1 );
+ *pucTapState = XTAPSTATE_SELECTDR;
+ }
+ break;
+ default:
+ iErrorCode = XSVF_ERROR_ILLEGALSTATE;
+ *pucTapState = ucTargetState; /* Exit while loop */
+ break;
+ }
+ XSVFDBG_PRINTF1( 3, " TAP State = %s\n",
+ xsvf_pzTapState[ *pucTapState ] );
+ }
+ }
+
+ return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfShiftOnly
+ * Description: Assumes that starting TAP state is SHIFT-DR or SHIFT-IR.
+ * Shift the given TDI data into the JTAG scan chain.
+ * Optionally, save the TDO data shifted out of the scan chain.
+ * Last shift cycle is special: capture last TDO, set last TDI,
+ * but does not pulse TCK. Caller must pulse TCK and optionally
+ * set TMS=1 to exit shift state.
+ * Parameters: lNumBits - number of bits to shift.
+ * plvTdi - ptr to lenval for TDI data.
+ * plvTdoCaptured - ptr to lenval for storing captured TDO data.
+ * iExitShift - 1=exit at end of shift; 0=stay in Shift-DR.
+ * Returns: void.
+ *****************************************************************************/
+void xsvfShiftOnly( long lNumBits,
+ lenVal* plvTdi,
+ lenVal* plvTdoCaptured,
+ int iExitShift )
+{
+ unsigned char* pucTdi;
+ unsigned char* pucTdo;
+ unsigned char ucTdiByte;
+ unsigned char ucTdoByte;
+ unsigned char ucTdoBit;
+ int i;
+
+ /* assert( ( ( lNumBits + 7 ) / 8 ) == plvTdi->len ); */
+
+ /* Initialize TDO storage len == TDI len */
+ pucTdo = 0;
+ if ( plvTdoCaptured )
+ {
+ plvTdoCaptured->len = plvTdi->len;
+ pucTdo = plvTdoCaptured->val + plvTdi->len;
+ }
+
+ /* Shift LSB first. val[N-1] == LSB. val[0] == MSB. */
+ pucTdi = plvTdi->val + plvTdi->len;
+ while ( lNumBits )
+ {
+ /* Process on a byte-basis */
+ ucTdiByte = (*(--pucTdi));
+ ucTdoByte = 0;
+ for ( i = 0; ( lNumBits && ( i < 8 ) ); ++i )
+ {
+ --lNumBits;
+ if ( iExitShift && !lNumBits )
+ {
+ /* Exit Shift-DR state */
+ setPort( TMS, 1 );
+ }
+
+ /* Set the new TDI value */
+ setPort( TDI, (short)(ucTdiByte & 1) );
+ ucTdiByte >>= 1;
+
+ /* Set TCK low */
+ setPort( TCK, 0 );
+
+ if ( pucTdo )
+ {
+ /* Save the TDO value */
+ ucTdoBit = readTDOBit();
+ ucTdoByte |= ( ucTdoBit << i );
+ }
+
+ /* Set TCK high */
+ setPort( TCK, 1 );
+ }
+
+ /* Save the TDO byte value */
+ if ( pucTdo )
+ {
+ (*(--pucTdo)) = ucTdoByte;
+ }
+ }
+}
+
+/*****************************************************************************
+ * Function: xsvfShift
+ * Description: Goes to the given starting TAP state.
+ * Calls xsvfShiftOnly to shift in the given TDI data and
+ * optionally capture the TDO data.
+ * Compares the TDO captured data against the TDO expected
+ * data.
+ * If a data mismatch occurs, then executes the exception
+ * handling loop upto ucMaxRepeat times.
+ * Parameters: pucTapState - Ptr to current TAP state.
+ * ucStartState - Starting shift state: Shift-DR or Shift-IR.
+ * lNumBits - number of bits to shift.
+ * plvTdi - ptr to lenval for TDI data.
+ * plvTdoCaptured - ptr to lenval for storing TDO data.
+ * plvTdoExpected - ptr to expected TDO data.
+ * plvTdoMask - ptr to TDO mask.
+ * ucEndState - state in which to end the shift.
+ * lRunTestTime - amount of time to wait after the shift.
+ * ucMaxRepeat - Maximum number of retries on TDO mismatch.
+ * Returns: int - 0 = success; otherwise TDO mismatch.
+ * Notes: XC9500XL-only Optimization:
+ * Skip the waitTime() if plvTdoMask->val[0:plvTdoMask->len-1]
+ * is NOT all zeros and sMatch==1.
+ *****************************************************************************/
+int xsvfShift( unsigned char* pucTapState,
+ unsigned char ucStartState,
+ long lNumBits,
+ lenVal* plvTdi,
+ lenVal* plvTdoCaptured,
+ lenVal* plvTdoExpected,
+ lenVal* plvTdoMask,
+ unsigned char ucEndState,
+ long lRunTestTime,
+ unsigned char ucMaxRepeat )
+{
+ int iErrorCode;
+ int iMismatch;
+ unsigned char ucRepeat;
+ int iExitShift;
+
+ iErrorCode = XSVF_ERROR_NONE;
+ iMismatch = 0;
+ ucRepeat = 0;
+ iExitShift = ( ucStartState != ucEndState );
+
+ XSVFDBG_PRINTF1( 3, " Shift Length = %ld\n", lNumBits );
+ XSVFDBG_PRINTF( 4, " TDI = ");
+ XSVFDBG_PRINTLENVAL( 4, plvTdi );
+ XSVFDBG_PRINTF( 4, "\n");
+ XSVFDBG_PRINTF( 4, " TDO Expected = ");
+ XSVFDBG_PRINTLENVAL( 4, plvTdoExpected );
+ XSVFDBG_PRINTF( 4, "\n");
+
+ if ( !lNumBits )
+ {
+ /* Compatibility with XSVF2.00: XSDR 0 = no shift, but wait in RTI */
+ if ( lRunTestTime )
+ {
+ /* Wait for prespecified XRUNTEST time */
+ xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST );
+ XSVFDBG_PRINTF1( 3, " Wait = %ld usec\n", lRunTestTime );
+ waitTime( lRunTestTime );
+ }
+ }
+ else
+ {
+ do
+ {
+ /* Goto Shift-DR or Shift-IR */
+ xsvfGotoTapState( pucTapState, ucStartState );
+
+ /* Shift TDI and capture TDO */
+ xsvfShiftOnly( lNumBits, plvTdi, plvTdoCaptured, iExitShift );
+
+ if ( plvTdoExpected )
+ {
+ /* Compare TDO data to expected TDO data */
+ iMismatch = !EqualLenVal( plvTdoExpected,
+ plvTdoCaptured,
+ plvTdoMask );
+ }
+
+ if ( iExitShift )
+ {
+ /* Update TAP state: Shift->Exit */
+ ++(*pucTapState);
+ XSVFDBG_PRINTF1( 3, " TAP State = %s\n",
+ xsvf_pzTapState[ *pucTapState ] );
+
+ if ( iMismatch && lRunTestTime && ( ucRepeat < ucMaxRepeat ) )
+ {
+ XSVFDBG_PRINTF( 4, " TDO Expected = ");
+ XSVFDBG_PRINTLENVAL( 4, plvTdoExpected );
+ XSVFDBG_PRINTF( 4, "\n");
+ XSVFDBG_PRINTF( 4, " TDO Captured = ");
+ XSVFDBG_PRINTLENVAL( 4, plvTdoCaptured );
+ XSVFDBG_PRINTF( 4, "\n");
+ XSVFDBG_PRINTF( 4, " TDO Mask = ");
+ XSVFDBG_PRINTLENVAL( 4, plvTdoMask );
+ XSVFDBG_PRINTF( 4, "\n");
+ XSVFDBG_PRINTF1( 3, " Retry #%d\n", ( ucRepeat + 1 ) );
+ /* Do exception handling retry - ShiftDR only */
+ xsvfGotoTapState( pucTapState, XTAPSTATE_PAUSEDR );
+ /* Shift 1 extra bit */
+ xsvfGotoTapState( pucTapState, XTAPSTATE_SHIFTDR );
+ /* Increment RUNTEST time by an additional 25% */
+ lRunTestTime += ( lRunTestTime >> 2 );
+ }
+ else
+ {
+ /* Do normal exit from Shift-XR */
+ xsvfGotoTapState( pucTapState, ucEndState );
+ }
+
+ if ( lRunTestTime )
+ {
+ /* Wait for prespecified XRUNTEST time */
+ xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST );
+ XSVFDBG_PRINTF1( 3, " Wait = %ld usec\n", lRunTestTime );
+ waitTime( lRunTestTime );
+ }
+ }
+ } while ( iMismatch && ( ucRepeat++ < ucMaxRepeat ) );
+ }
+
+ if ( iMismatch )
+ {
+ XSVFDBG_PRINTF( 1, " TDO Expected = ");
+ XSVFDBG_PRINTLENVAL( 1, plvTdoExpected );
+ XSVFDBG_PRINTF( 1, "\n");
+ XSVFDBG_PRINTF( 1, " TDO Captured = ");
+ XSVFDBG_PRINTLENVAL( 1, plvTdoCaptured );
+ XSVFDBG_PRINTF( 1, "\n");
+ XSVFDBG_PRINTF( 1, " TDO Mask = ");
+ XSVFDBG_PRINTLENVAL( 1, plvTdoMask );
+ XSVFDBG_PRINTF( 1, "\n");
+ if ( ucMaxRepeat && ( ucRepeat > ucMaxRepeat ) )
+ {
+ iErrorCode = XSVF_ERROR_MAXRETRIES;
+ }
+ else
+ {
+ iErrorCode = XSVF_ERROR_TDOMISMATCH;
+ }
+ }
+
+ return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfBasicXSDRTDO
+ * Description: Get the XSDRTDO parameters and execute the XSDRTDO command.
+ * This is the common function for all XSDRTDO commands.
+ * Parameters: pucTapState - Current TAP state.
+ * lShiftLengthBits - number of bits to shift.
+ * sShiftLengthBytes - number of bytes to read.
+ * plvTdi - ptr to lenval for TDI data.
+ * lvTdoCaptured - ptr to lenval for storing TDO data.
+ * iEndState - state in which to end the shift.
+ * lRunTestTime - amount of time to wait after the shift.
+ * ucMaxRepeat - maximum xc9500/xl retries.
+ * Returns: int - 0 = success; otherwise TDO mismatch.
+ *****************************************************************************/
+int xsvfBasicXSDRTDO( unsigned char* pucTapState,
+ long lShiftLengthBits,
+ short sShiftLengthBytes,
+ lenVal* plvTdi,
+ lenVal* plvTdoCaptured,
+ lenVal* plvTdoExpected,
+ lenVal* plvTdoMask,
+ unsigned char ucEndState,
+ long lRunTestTime,
+ unsigned char ucMaxRepeat )
+{
+ readVal( plvTdi, sShiftLengthBytes );
+ if ( plvTdoExpected )
+ {
+ readVal( plvTdoExpected, sShiftLengthBytes );
+ }
+ return( xsvfShift( pucTapState, XTAPSTATE_SHIFTDR, lShiftLengthBits,
+ plvTdi, plvTdoCaptured, plvTdoExpected, plvTdoMask,
+ ucEndState, lRunTestTime, ucMaxRepeat ) );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoSDRMasking
+ * Description: Update the data value with the next XSDRINC data and address.
+ * Example: dataVal=0x01ff, nextData=0xab, addressMask=0x0100,
+ * dataMask=0x00ff, should set dataVal to 0x02ab
+ * Parameters: plvTdi - The current TDI value.
+ * plvNextData - the next data value.
+ * plvAddressMask - the address mask.
+ * plvDataMask - the data mask.
+ * Returns: void.
+ *****************************************************************************/
+#ifdef XSVF_SUPPORT_COMPRESSION
+void xsvfDoSDRMasking( lenVal* plvTdi,
+ lenVal* plvNextData,
+ lenVal* plvAddressMask,
+ lenVal* plvDataMask )
+{
+ int i;
+ unsigned char ucTdi;
+ unsigned char ucTdiMask;
+ unsigned char ucDataMask;
+ unsigned char ucNextData;
+ unsigned char ucNextMask;
+ short sNextData;
+
+ /* add the address Mask to dataVal and return as a new dataVal */
+ addVal( plvTdi, plvTdi, plvAddressMask );
+
+ ucNextData = 0;
+ ucNextMask = 0;
+ sNextData = plvNextData->len;
+ for ( i = plvDataMask->len - 1; i >= 0; --i )
+ {
+ /* Go through data mask in reverse order looking for mask (1) bits */
+ ucDataMask = plvDataMask->val[ i ];
+ if ( ucDataMask )
+ {
+ /* Retrieve the corresponding TDI byte value */
+ ucTdi = plvTdi->val[ i ];
+
+ /* For each bit in the data mask byte, look for 1's */
+ ucTdiMask = 1;
+ while ( ucDataMask )
+ {
+ if ( ucDataMask & 1 )
+ {
+ if ( !ucNextMask )
+ {
+ /* Get the next data byte */
+ ucNextData = plvNextData->val[ --sNextData ];
+ ucNextMask = 1;
+ }
+
+ /* Set or clear the data bit according to the next data */
+ if ( ucNextData & ucNextMask )
+ {
+ ucTdi |= ucTdiMask; /* Set bit */
+ }
+ else
+ {
+ ucTdi &= ( ~ucTdiMask ); /* Clear bit */
+ }
+
+ /* Update the next data */
+ ucNextMask <<= 1;
+ }
+ ucTdiMask <<= 1;
+ ucDataMask >>= 1;
+ }
+
+ /* Update the TDI value */
+ plvTdi->val[ i ] = ucTdi;
+ }
+ }
+}
+#endif /* XSVF_SUPPORT_COMPRESSION */
+
+/*============================================================================
+ * XSVF Command Functions (type = TXsvfDoCmdFuncPtr)
+ * These functions update pXsvfInfo->iErrorCode only on an error.
+ * Otherwise, the error code is left alone.
+ * The function returns the error code from the function.
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function: xsvfDoIllegalCmd
+ * Description: Function place holder for illegal/unsupported commands.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo )
+{
+ XSVFDBG_PRINTF2( 0, "ERROR: Encountered unsupported command #%d (%s)\n",
+ ((unsigned int)(pXsvfInfo->ucCommand)),
+ ((pXsvfInfo->ucCommand < XLASTCMD)
+ ? (xsvf_pzCommandName[pXsvfInfo->ucCommand])
+ : "Unknown") );
+ pXsvfInfo->iErrorCode = XSVF_ERROR_ILLEGALCMD;
+ return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXCOMPLETE
+ * Description: XCOMPLETE (no parameters)
+ * Update complete status for XSVF player.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo )
+{
+ pXsvfInfo->ucComplete = 1;
+ return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXTDOMASK
+ * Description: XTDOMASK <lenVal.TdoMask[XSDRSIZE]>
+ * Prespecify the TDO compare mask.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo )
+{
+ readVal( &(pXsvfInfo->lvTdoMask), pXsvfInfo->sShiftLengthBytes );
+ XSVFDBG_PRINTF( 4, " TDO Mask = ");
+ XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvTdoMask) );
+ XSVFDBG_PRINTF( 4, "\n");
+ return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXSIR
+ * Description: XSIR <(byte)shiftlen> <lenVal.TDI[shiftlen]>
+ * Get the instruction and shift the instruction into the TAP.
+ * If prespecified XRUNTEST!=0, goto RUNTEST and wait after
+ * the shift for XRUNTEST usec.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSIR( SXsvfInfo* pXsvfInfo )
+{
+ unsigned char ucShiftIrBits;
+ short sShiftIrBytes;
+ int iErrorCode;
+
+ /* Get the shift length and store */
+ readByte( &ucShiftIrBits );
+ sShiftIrBytes = xsvfGetAsNumBytes( ucShiftIrBits );
+ XSVFDBG_PRINTF1( 3, " XSIR length = %d\n",
+ ((unsigned int)ucShiftIrBits) );
+
+ if ( sShiftIrBytes > MAX_LEN )
+ {
+ iErrorCode = XSVF_ERROR_DATAOVERFLOW;
+ }
+ else
+ {
+ /* Get and store instruction to shift in */
+ readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( ucShiftIrBits ) );
+
+ /* Shift the data */
+ iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR,
+ ucShiftIrBits, &(pXsvfInfo->lvTdi),
+ /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
+ /*plvTdoMask*/0, pXsvfInfo->ucEndIR,
+ pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 );
+ }
+
+ if ( iErrorCode != XSVF_ERROR_NONE )
+ {
+ pXsvfInfo->iErrorCode = iErrorCode;
+ }
+ return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXSIR2
+ * Description: XSIR <(2-byte)shiftlen> <lenVal.TDI[shiftlen]>
+ * Get the instruction and shift the instruction into the TAP.
+ * If prespecified XRUNTEST!=0, goto RUNTEST and wait after
+ * the shift for XRUNTEST usec.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo )
+{
+ long lShiftIrBits;
+ short sShiftIrBytes;
+ int iErrorCode;
+
+ /* Get the shift length and store */
+ readVal( &(pXsvfInfo->lvTdi), 2 );
+ lShiftIrBits = value( &(pXsvfInfo->lvTdi) );
+ sShiftIrBytes = xsvfGetAsNumBytes( lShiftIrBits );
+ XSVFDBG_PRINTF1( 3, " XSIR2 length = %d\n", (int)lShiftIrBits);
+
+ if ( sShiftIrBytes > MAX_LEN )
+ {
+ iErrorCode = XSVF_ERROR_DATAOVERFLOW;
+ }
+ else
+ {
+ /* Get and store instruction to shift in */
+ readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( lShiftIrBits ) );
+
+ /* Shift the data */
+ iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR,
+ lShiftIrBits, &(pXsvfInfo->lvTdi),
+ /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
+ /*plvTdoMask*/0, pXsvfInfo->ucEndIR,
+ pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 );
+ }
+
+ if ( iErrorCode != XSVF_ERROR_NONE )
+ {
+ pXsvfInfo->iErrorCode = iErrorCode;
+ }
+ return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXSDR
+ * Description: XSDR <lenVal.TDI[XSDRSIZE]>
+ * Shift the given TDI data into the JTAG scan chain.
+ * Compare the captured TDO with the expected TDO from the
+ * previous XSDRTDO command using the previously specified
+ * XTDOMASK.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDR( SXsvfInfo* pXsvfInfo )
+{
+ int iErrorCode;
+ readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes );
+ /* use TDOExpected from last XSDRTDO instruction */
+ iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR,
+ pXsvfInfo->lShiftLengthBits, &(pXsvfInfo->lvTdi),
+ &(pXsvfInfo->lvTdoCaptured),
+ &(pXsvfInfo->lvTdoExpected),
+ &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR,
+ pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat );
+ if ( iErrorCode != XSVF_ERROR_NONE )
+ {
+ pXsvfInfo->iErrorCode = iErrorCode;
+ }
+ return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXRUNTEST
+ * Description: XRUNTEST <uint32>
+ * Prespecify the XRUNTEST wait time for shift operations.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo )
+{
+ readVal( &(pXsvfInfo->lvTdi), 4 );
+ pXsvfInfo->lRunTestTime = value( &(pXsvfInfo->lvTdi) );
+ XSVFDBG_PRINTF1( 3, " XRUNTEST = %ld\n", pXsvfInfo->lRunTestTime );
+ return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXREPEAT
+ * Description: XREPEAT <byte>
+ * Prespecify the maximum number of XC9500/XL retries.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo )
+{
+ readByte( &(pXsvfInfo->ucMaxRepeat) );
+ XSVFDBG_PRINTF1( 3, " XREPEAT = %d\n",
+ ((unsigned int)(pXsvfInfo->ucMaxRepeat)) );
+ return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXSDRSIZE
+ * Description: XSDRSIZE <uint32>
+ * Prespecify the XRUNTEST wait time for shift operations.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo )
+{
+ int iErrorCode;
+ iErrorCode = XSVF_ERROR_NONE;
+ readVal( &(pXsvfInfo->lvTdi), 4 );
+ pXsvfInfo->lShiftLengthBits = value( &(pXsvfInfo->lvTdi) );
+ pXsvfInfo->sShiftLengthBytes= xsvfGetAsNumBytes( pXsvfInfo->lShiftLengthBits );
+ XSVFDBG_PRINTF1( 3, " XSDRSIZE = %ld\n", pXsvfInfo->lShiftLengthBits );
+ if ( pXsvfInfo->sShiftLengthBytes > MAX_LEN )
+ {
+ iErrorCode = XSVF_ERROR_DATAOVERFLOW;
+ pXsvfInfo->iErrorCode = iErrorCode;
+ }
+ return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXSDRTDO
+ * Description: XSDRTDO <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]>
+ * Get the TDI and expected TDO values. Then, shift.
+ * Compare the expected TDO with the captured TDO using the
+ * prespecified XTDOMASK.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo )
+{
+ int iErrorCode;
+ iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
+ pXsvfInfo->lShiftLengthBits,
+ pXsvfInfo->sShiftLengthBytes,
+ &(pXsvfInfo->lvTdi),
+ &(pXsvfInfo->lvTdoCaptured),
+ &(pXsvfInfo->lvTdoExpected),
+ &(pXsvfInfo->lvTdoMask),
+ pXsvfInfo->ucEndDR,
+ pXsvfInfo->lRunTestTime,
+ pXsvfInfo->ucMaxRepeat );
+ if ( iErrorCode != XSVF_ERROR_NONE )
+ {
+ pXsvfInfo->iErrorCode = iErrorCode;
+ }
+ return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXSETSDRMASKS
+ * Description: XSETSDRMASKS <lenVal.AddressMask[XSDRSIZE]>
+ * <lenVal.DataMask[XSDRSIZE]>
+ * Get the prespecified address and data mask for the XSDRINC
+ * command.
+ * Used for xc9500/xl compressed XSVF data.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+#ifdef XSVF_SUPPORT_COMPRESSION
+int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo )
+{
+ /* read the addressMask */
+ readVal( &(pXsvfInfo->lvAddressMask), pXsvfInfo->sShiftLengthBytes );
+ /* read the dataMask */
+ readVal( &(pXsvfInfo->lvDataMask), pXsvfInfo->sShiftLengthBytes );
+
+ XSVFDBG_PRINTF( 4, " Address Mask = " );
+ XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvAddressMask) );
+ XSVFDBG_PRINTF( 4, "\n" );
+ XSVFDBG_PRINTF( 4, " Data Mask = " );
+ XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvDataMask) );
+ XSVFDBG_PRINTF( 4, "\n" );
+
+ return( XSVF_ERROR_NONE );
+}
+#endif /* XSVF_SUPPORT_COMPRESSION */
+
+/*****************************************************************************
+ * Function: xsvfDoXSDRINC
+ * Description: XSDRINC <lenVal.firstTDI[XSDRSIZE]> <byte(numTimes)>
+ * <lenVal.data[XSETSDRMASKS.dataMask.len]> ...
+ * Get the XSDRINC parameters and execute the XSDRINC command.
+ * XSDRINC starts by loading the first TDI shift value.
+ * Then, for numTimes, XSDRINC gets the next piece of data,
+ * replaces the bits from the starting TDI as defined by the
+ * XSETSDRMASKS.dataMask, adds the address mask from
+ * XSETSDRMASKS.addressMask, shifts the new TDI value,
+ * and compares the TDO to the expected TDO from the previous
+ * XSDRTDO command using the XTDOMASK.
+ * Used for xc9500/xl compressed XSVF data.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+#ifdef XSVF_SUPPORT_COMPRESSION
+int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo )
+{
+ int iErrorCode;
+ int iDataMaskLen;
+ unsigned char ucDataMask;
+ unsigned char ucNumTimes;
+ unsigned char i;
+
+ readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes );
+ iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR,
+ pXsvfInfo->lShiftLengthBits,
+ &(pXsvfInfo->lvTdi), &(pXsvfInfo->lvTdoCaptured),
+ &(pXsvfInfo->lvTdoExpected),
+ &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR,
+ pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat );
+ if ( !iErrorCode )
+ {
+ /* Calculate number of data mask bits */
+ iDataMaskLen = 0;
+ for ( i = 0; i < pXsvfInfo->lvDataMask.len; ++i )
+ {
+ ucDataMask = pXsvfInfo->lvDataMask.val[ i ];
+ while ( ucDataMask )
+ {
+ iDataMaskLen += ( ucDataMask & 1 );
+ ucDataMask >>= 1;
+ }
+ }
+
+ /* Get the number of data pieces, i.e. number of times to shift */
+ readByte( &ucNumTimes );
+
+ /* For numTimes, get data, fix TDI, and shift */
+ for ( i = 0; !iErrorCode && ( i < ucNumTimes ); ++i )
+ {
+ readVal( &(pXsvfInfo->lvNextData),
+ xsvfGetAsNumBytes( iDataMaskLen ) );
+ xsvfDoSDRMasking( &(pXsvfInfo->lvTdi),
+ &(pXsvfInfo->lvNextData),
+ &(pXsvfInfo->lvAddressMask),
+ &(pXsvfInfo->lvDataMask) );
+ iErrorCode = xsvfShift( &(pXsvfInfo->ucTapState),
+ XTAPSTATE_SHIFTDR,
+ pXsvfInfo->lShiftLengthBits,
+ &(pXsvfInfo->lvTdi),
+ &(pXsvfInfo->lvTdoCaptured),
+ &(pXsvfInfo->lvTdoExpected),
+ &(pXsvfInfo->lvTdoMask),
+ pXsvfInfo->ucEndDR,
+ pXsvfInfo->lRunTestTime,
+ pXsvfInfo->ucMaxRepeat );
+ }
+ }
+ if ( iErrorCode != XSVF_ERROR_NONE )
+ {
+ pXsvfInfo->iErrorCode = iErrorCode;
+ }
+ return( iErrorCode );
+}
+#endif /* XSVF_SUPPORT_COMPRESSION */
+
+/*****************************************************************************
+ * Function: xsvfDoXSDRBCE
+ * Description: XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]>
+ * If not already in SHIFTDR, goto SHIFTDR.
+ * Shift the given TDI data into the JTAG scan chain.
+ * Ignore TDO.
+ * If cmd==XSDRE, then goto ENDDR. Otherwise, stay in ShiftDR.
+ * XSDRB, XSDRC, and XSDRE are the same implementation.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo )
+{
+ unsigned char ucEndDR;
+ int iErrorCode;
+ ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRE ) ?
+ pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR);
+ iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
+ pXsvfInfo->lShiftLengthBits,
+ pXsvfInfo->sShiftLengthBytes,
+ &(pXsvfInfo->lvTdi),
+ /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
+ /*plvTdoMask*/0, ucEndDR,
+ /*lRunTestTime*/0, /*ucMaxRepeat*/0 );
+ if ( iErrorCode != XSVF_ERROR_NONE )
+ {
+ pXsvfInfo->iErrorCode = iErrorCode;
+ }
+ return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXSDRTDOBCE
+ * Description: XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]>
+ * If not already in SHIFTDR, goto SHIFTDR.
+ * Shift the given TDI data into the JTAG scan chain.
+ * Compare TDO, but do NOT use XTDOMASK.
+ * If cmd==XSDRTDOE, then goto ENDDR. Otherwise, stay in ShiftDR.
+ * XSDRTDOB, XSDRTDOC, and XSDRTDOE are the same implementation.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo )
+{
+ unsigned char ucEndDR;
+ int iErrorCode;
+ ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRTDOE ) ?
+ pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR);
+ iErrorCode = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
+ pXsvfInfo->lShiftLengthBits,
+ pXsvfInfo->sShiftLengthBytes,
+ &(pXsvfInfo->lvTdi),
+ &(pXsvfInfo->lvTdoCaptured),
+ &(pXsvfInfo->lvTdoExpected),
+ /*plvTdoMask*/0, ucEndDR,
+ /*lRunTestTime*/0, /*ucMaxRepeat*/0 );
+ if ( iErrorCode != XSVF_ERROR_NONE )
+ {
+ pXsvfInfo->iErrorCode = iErrorCode;
+ }
+ return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXSTATE
+ * Description: XSTATE <byte>
+ * <byte> == XTAPSTATE;
+ * Get the state parameter and transition the TAP to that state.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo )
+{
+ unsigned char ucNextState;
+ int iErrorCode;
+ readByte( &ucNextState );
+ iErrorCode = xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucNextState );
+ if ( iErrorCode != XSVF_ERROR_NONE )
+ {
+ pXsvfInfo->iErrorCode = iErrorCode;
+ }
+ return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXENDXR
+ * Description: XENDIR/XENDDR <byte>
+ * <byte>: 0 = RUNTEST; 1 = PAUSE.
+ * Get the prespecified XENDIR or XENDDR.
+ * Both XENDIR and XENDDR use the same implementation.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo )
+{
+ int iErrorCode;
+ unsigned char ucEndState;
+
+ iErrorCode = XSVF_ERROR_NONE;
+ readByte( &ucEndState );
+ if ( ( ucEndState != XENDXR_RUNTEST ) && ( ucEndState != XENDXR_PAUSE ) )
+ {
+ iErrorCode = XSVF_ERROR_ILLEGALSTATE;
+ }
+ else
+ {
+
+ if ( pXsvfInfo->ucCommand == XENDIR )
+ {
+ if ( ucEndState == XENDXR_RUNTEST )
+ {
+ pXsvfInfo->ucEndIR = XTAPSTATE_RUNTEST;
+ }
+ else
+ {
+ pXsvfInfo->ucEndIR = XTAPSTATE_PAUSEIR;
+ }
+ XSVFDBG_PRINTF1( 3, " ENDIR State = %s\n",
+ xsvf_pzTapState[ pXsvfInfo->ucEndIR ] );
+ }
+ else /* XENDDR */
+ {
+ if ( ucEndState == XENDXR_RUNTEST )
+ {
+ pXsvfInfo->ucEndDR = XTAPSTATE_RUNTEST;
+ }
+ else
+ {
+ pXsvfInfo->ucEndDR = XTAPSTATE_PAUSEDR;
+ }
+ XSVFDBG_PRINTF1( 3, " ENDDR State = %s\n",
+ xsvf_pzTapState[ pXsvfInfo->ucEndDR ] );
+ }
+ }
+
+ if ( iErrorCode != XSVF_ERROR_NONE )
+ {
+ pXsvfInfo->iErrorCode = iErrorCode;
+ }
+ return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXCOMMENT
+ * Description: XCOMMENT <text string ending in \0>
+ * <text string ending in \0> == text comment;
+ * Arbitrary comment embedded in the XSVF.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo )
+{
+ /* Use the comment for debugging */
+ /* Otherwise, read through the comment to the end '\0' and ignore */
+ unsigned char ucText;
+
+ if ( xsvf_iDebugLevel > 0 )
+ {
+ putc( ' ' );
+ }
+
+ do
+ {
+ readByte( &ucText );
+ if ( xsvf_iDebugLevel > 0 )
+ {
+ putc( ucText ? ucText : '\n' );
+ }
+ } while ( ucText );
+
+ pXsvfInfo->iErrorCode = XSVF_ERROR_NONE;
+
+ return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfDoXWAIT
+ * Description: XWAIT <wait_state> <end_state> <wait_time>
+ * If not already in <wait_state>, then go to <wait_state>.
+ * Wait in <wait_state> for <wait_time> microseconds.
+ * Finally, if not already in <end_state>, then goto <end_state>.
+ * Parameters: pXsvfInfo - XSVF information pointer.
+ * Returns: int - 0 = success; non-zero = error.
+ *****************************************************************************/
+int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo )
+{
+ unsigned char ucWaitState;
+ unsigned char ucEndState;
+ long lWaitTime;
+
+ /* Get Parameters */
+ /* <wait_state> */
+ readVal( &(pXsvfInfo->lvTdi), 1 );
+ ucWaitState = pXsvfInfo->lvTdi.val[0];
+
+ /* <end_state> */
+ readVal( &(pXsvfInfo->lvTdi), 1 );
+ ucEndState = pXsvfInfo->lvTdi.val[0];
+
+ /* <wait_time> */
+ readVal( &(pXsvfInfo->lvTdi), 4 );
+ lWaitTime = value( &(pXsvfInfo->lvTdi) );
+ XSVFDBG_PRINTF2( 3, " XWAIT: state = %s; time = %ld\n",
+ xsvf_pzTapState[ ucWaitState ], lWaitTime );
+
+ /* If not already in <wait_state>, go to <wait_state> */
+ if ( pXsvfInfo->ucTapState != ucWaitState )
+ {
+ xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucWaitState );
+ }
+
+ /* Wait for <wait_time> microseconds */
+ waitTime( lWaitTime );
+
+ /* If not already in <end_state>, go to <end_state> */
+ if ( pXsvfInfo->ucTapState != ucEndState )
+ {
+ xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucEndState );
+ }
+
+ return( XSVF_ERROR_NONE );
+}
+
+
+/*============================================================================
+ * Execution Control Functions
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function: xsvfInitialize
+ * Description: Initialize the xsvf player.
+ * Call this before running the player to initialize the data
+ * in the SXsvfInfo struct.
+ * xsvfCleanup is called to clean up the data in SXsvfInfo
+ * after the XSVF is played.
+ * Parameters: pXsvfInfo - ptr to the XSVF information.
+ * Returns: int - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfInitialize( SXsvfInfo* pXsvfInfo )
+{
+ /* Initialize values */
+ pXsvfInfo->iErrorCode = xsvfInfoInit( pXsvfInfo );
+
+ if ( !pXsvfInfo->iErrorCode )
+ {
+ /* Initialize the TAPs */
+ pXsvfInfo->iErrorCode = xsvfGotoTapState( &(pXsvfInfo->ucTapState),
+ XTAPSTATE_RESET );
+ }
+
+ return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfRun
+ * Description: Run the xsvf player for a single command and return.
+ * First, call xsvfInitialize.
+ * Then, repeatedly call this function until an error is detected
+ * or until the pXsvfInfo->ucComplete variable is non-zero.
+ * Finally, call xsvfCleanup to cleanup any remnants.
+ * Parameters: pXsvfInfo - ptr to the XSVF information.
+ * Returns: int - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfRun( SXsvfInfo* pXsvfInfo )
+{
+ /* Process the XSVF commands */
+ if ( (!pXsvfInfo->iErrorCode) && (!pXsvfInfo->ucComplete) )
+ {
+ /* read 1 byte for the instruction */
+ readByte( &(pXsvfInfo->ucCommand) );
+ ++(pXsvfInfo->lCommandCount);
+
+ if ( pXsvfInfo->ucCommand < XLASTCMD )
+ {
+ /* Execute the command. Func sets error code. */
+ XSVFDBG_PRINTF1( 2, " %s\n",
+ xsvf_pzCommandName[pXsvfInfo->ucCommand] );
+ /* If your compiler cannot take this form,
+ then convert to a switch statement */
+#if 0 /* test-only */
+ xsvf_pfDoCmd[ pXsvfInfo->ucCommand ]( pXsvfInfo );
+#else
+ switch (pXsvfInfo->ucCommand) {
+ case 0:
+ xsvfDoXCOMPLETE(pXsvfInfo); /* 0 */
+ break;
+ case 1:
+ xsvfDoXTDOMASK(pXsvfInfo); /* 1 */
+ break;
+ case 2:
+ xsvfDoXSIR(pXsvfInfo); /* 2 */
+ break;
+ case 3:
+ xsvfDoXSDR(pXsvfInfo); /* 3 */
+ break;
+ case 4:
+ xsvfDoXRUNTEST(pXsvfInfo); /* 4 */
+ break;
+ case 5:
+ xsvfDoIllegalCmd(pXsvfInfo); /* 5 */
+ break;
+ case 6:
+ xsvfDoIllegalCmd(pXsvfInfo); /* 6 */
+ break;
+ case 7:
+ xsvfDoXREPEAT(pXsvfInfo); /* 7 */
+ break;
+ case 8:
+ xsvfDoXSDRSIZE(pXsvfInfo); /* 8 */
+ break;
+ case 9:
+ xsvfDoXSDRTDO(pXsvfInfo); /* 9 */
+ break;
+#ifdef XSVF_SUPPORT_COMPRESSION
+ case 10:
+ xsvfDoXSETSDRMASKS(pXsvfInfo); /* 10 */
+ break;
+ case 11:
+ xsvfDoXSDRINC(pXsvfInfo); /* 11 */
+ break;
+#else
+ case 10:
+ xsvfDoIllegalCmd(pXsvfInfo); /* 10 */
+ break;
+ case 11:
+ xsvfDoIllegalCmd(pXsvfInfo); /* 11 */
+ break;
+#endif /* XSVF_SUPPORT_COMPRESSION */
+ case 12:
+ xsvfDoXSDRBCE(pXsvfInfo); /* 12 */
+ break;
+ case 13:
+ xsvfDoXSDRBCE(pXsvfInfo); /* 13 */
+ break;
+ case 14:
+ xsvfDoXSDRBCE(pXsvfInfo); /* 14 */
+ break;
+ case 15:
+ xsvfDoXSDRTDOBCE(pXsvfInfo); /* 15 */
+ break;
+ case 16:
+ xsvfDoXSDRTDOBCE(pXsvfInfo); /* 16 */
+ break;
+ case 17:
+ xsvfDoXSDRTDOBCE(pXsvfInfo); /* 17 */
+ break;
+ case 18:
+ xsvfDoXSTATE(pXsvfInfo); /* 18 */
+ break;
+ case 19:
+ xsvfDoXENDXR(pXsvfInfo); /* 19 */
+ break;
+ case 20:
+ xsvfDoXENDXR(pXsvfInfo); /* 20 */
+ break;
+ case 21:
+ xsvfDoXSIR2(pXsvfInfo); /* 21 */
+ break;
+ case 22:
+ xsvfDoXCOMMENT(pXsvfInfo); /* 22 */
+ break;
+ case 23:
+ xsvfDoXWAIT(pXsvfInfo); /* 23 */
+ break;
+ }
+#endif
+ }
+ else
+ {
+ /* Illegal command value. Func sets error code. */
+ xsvfDoIllegalCmd( pXsvfInfo );
+ }
+ }
+
+ return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function: xsvfCleanup
+ * Description: cleanup remnants of the xsvf player.
+ * Parameters: pXsvfInfo - ptr to the XSVF information.
+ * Returns: void.
+ *****************************************************************************/
+void xsvfCleanup( SXsvfInfo* pXsvfInfo )
+{
+ xsvfInfoCleanup( pXsvfInfo );
+}
+
+
+/*============================================================================
+ * xsvfExecute() - The primary entry point to the XSVF player
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function: xsvfExecute
+ * Description: Process, interpret, and apply the XSVF commands.
+ * See port.c:readByte for source of XSVF data.
+ * Parameters: none.
+ * Returns: int - Legacy result values: 1 == success; 0 == failed.
+ *****************************************************************************/
+int xsvfExecute(void)
+{
+ SXsvfInfo xsvfInfo;
+
+ xsvfInitialize( &xsvfInfo );
+
+ while ( !xsvfInfo.iErrorCode && (!xsvfInfo.ucComplete) )
+ {
+ xsvfRun( &xsvfInfo );
+ }
+
+ if ( xsvfInfo.iErrorCode )
+ {
+ XSVFDBG_PRINTF1( 0, "%s\n", xsvf_pzErrorName[
+ ( xsvfInfo.iErrorCode < XSVF_ERROR_LAST )
+ ? xsvfInfo.iErrorCode : XSVF_ERROR_UNKNOWN ] );
+ XSVFDBG_PRINTF2( 0, "ERROR at or near XSVF command #%ld. See line #%ld in the XSVF ASCII file.\n",
+ xsvfInfo.lCommandCount, xsvfInfo.lCommandCount );
+ }
+ else
+ {
+ XSVFDBG_PRINTF( 0, "SUCCESS - Completed XSVF execution.\n" );
+ }
+
+ xsvfCleanup( &xsvfInfo );
+
+ return( XSVF_ERRORCODE(xsvfInfo.iErrorCode) );
+}
+
+
+/*****************************************************************************
+ * Function: do_cpld
+ * Description: main function.
+ * Specified here for creating stand-alone debug executable.
+ * Embedded users should call xsvfExecute() directly.
+ * Parameters: iArgc - number of command-line arguments.
+ * ppzArgv - array of ptrs to strings (command-line arguments).
+ * Returns: int - Legacy return value: 1 = success; 0 = error.
+ *****************************************************************************/
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int iErrorCode;
+ unsigned long duration;
+ unsigned long long startClock, endClock;
+
+ if (argc == 2)
+ xsvfdata = (unsigned char *)simple_strtoul(argv[1], NULL, 16);
+ else {
+#ifdef CONFIG_SYS_XSVF_DEFAULT_ADDR
+ xsvfdata = (unsigned char *)CONFIG_SYS_XSVF_DEFAULT_ADDR;
+#else
+ printf("Usage:\ncpld %s\n", cmdtp->help);
+ return -1;
+#endif
+ }
+
+ iErrorCode = XSVF_ERRORCODE( XSVF_ERROR_NONE );
+ xsvf_iDebugLevel = 0;
+
+ printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION);
+ printf("Reading XSVF data @ %p\n", xsvfdata);
+
+ /* Initialize the I/O. SetPort initializes I/O on first call */
+ setPort( TMS, 1 );
+
+ /* Execute the XSVF in the file */
+ startClock = get_ticks();
+ iErrorCode = xsvfExecute();
+ endClock = get_ticks();
+ duration = (unsigned long)(endClock - startClock);
+ printf("\nExecution Time = %d seconds\n", (int)(duration/get_tbclk()));
+
+ return( iErrorCode );
+}
+U_BOOT_CMD(
+ cpld, 2, 1, do_cpld,
+ "program onboard CPLD",
+ "<xsvf-addr>"
+);
diff --git a/board/esd/common/xilinx_jtag/micro.h b/board/esd/common/xilinx_jtag/micro.h
new file mode 100644
index 0000000..e9a7612
--- /dev/null
+++ b/board/esd/common/xilinx_jtag/micro.h
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*****************************************************************************
+ * File: micro.h
+ * Description: This header file contains the function prototype to the
+ * primary interface function for the XSVF player.
+ * Usage: FIRST - PORTS.C
+ * Customize the ports.c function implementations to establish
+ * the correct protocol for communicating with your JTAG ports
+ * (setPort() and readTDOBit()) and tune the waitTime() delay
+ * function. Also, establish access to the XSVF data source
+ * in the readByte() function.
+ * FINALLY - Call xsvfExecute().
+ *****************************************************************************/
+#ifndef XSVF_MICRO_H
+#define XSVF_MICRO_H
+
+/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
+#define XSVF_LEGACY_SUCCESS 1
+#define XSVF_LEGACY_ERROR 0
+
+/* 4.04 [NEW] Error codes for xsvfExecute. */
+/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
+#define XSVF_ERROR_NONE 0
+#define XSVF_ERROR_UNKNOWN 1
+#define XSVF_ERROR_TDOMISMATCH 2
+#define XSVF_ERROR_MAXRETRIES 3 /* TDO mismatch after max retries */
+#define XSVF_ERROR_ILLEGALCMD 4
+#define XSVF_ERROR_ILLEGALSTATE 5
+#define XSVF_ERROR_DATAOVERFLOW 6 /* Data > lenVal MAX_LEN buffer size*/
+/* Insert new errors here */
+#define XSVF_ERROR_LAST 7
+
+/*****************************************************************************
+ * Function: xsvfExecute
+ * Description: Process, interpret, and apply the XSVF commands.
+ * See port.c:readByte for source of XSVF data.
+ * Parameters: none.
+ * Returns: int - For error codes see above.
+ *****************************************************************************/
+int xsvfExecute(void);
+
+#endif /* XSVF_MICRO_H */
diff --git a/board/esd/common/xilinx_jtag/ports.c b/board/esd/common/xilinx_jtag/ports.c
new file mode 100644
index 0000000..d79dbd1
--- /dev/null
+++ b/board/esd/common/xilinx_jtag/ports.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*******************************************************/
+/* file: ports.c */
+/* abstract: This file contains the routines to */
+/* output values on the JTAG ports, to read */
+/* the TDO bit, and to read a byte of data */
+/* from the prom */
+/* */
+/*******************************************************/
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#include "ports.h"
+
+static unsigned long output = 0;
+static int filepos = 0;
+static int oldstate = 0;
+static int newstate = 0;
+static int readptr = 0;
+
+extern const unsigned char *xsvfdata;
+
+/* if in debugging mode, then just set the variables */
+void setPort(short p,short val)
+{
+ if (p==TMS) {
+ if (val) {
+ output |= JTAG_TMS;
+ } else {
+ output &= ~JTAG_TMS;
+ }
+ }
+ if (p==TDI) {
+ if (val) {
+ output |= JTAG_TDI;
+ } else {
+ output &= ~JTAG_TDI;
+ }
+ }
+ if (p==TCK) {
+ if (val) {
+ output |= JTAG_TCK;
+ } else {
+ output &= ~JTAG_TCK;
+ }
+ out_be32((void *)GPIO0_OR, output);
+ }
+}
+
+
+/* toggle tck LH */
+void pulseClock(void)
+{
+ setPort(TCK,0); /* set the TCK port to low */
+ setPort(TCK,1); /* set the TCK port to high */
+}
+
+
+/* read in a byte of data from the prom */
+void readByte(unsigned char *data)
+{
+ /* pretend reading using a file */
+ *data = xsvfdata[readptr++];
+ newstate = filepos++ >> 10;
+ if (newstate != oldstate) {
+ printf("%4d kB\r\r\r\r", newstate);
+ oldstate = newstate;
+ }
+}
+
+/* read the TDO bit from port */
+unsigned char readTDOBit(void)
+{
+ unsigned long inputs;
+
+ inputs = in_be32((void *)GPIO0_IR);
+ if (inputs & JTAG_TDO)
+ return 1;
+ else
+ return 0;
+}
+
+
+/* Wait at least the specified number of microsec. */
+/* Use a timer if possible; otherwise estimate the number of instructions */
+/* necessary to be run based on the microcontroller speed. For this example */
+/* we pulse the TCK port a number of times based on the processor speed. */
+void waitTime(long microsec)
+{
+ udelay(microsec); /* esd */
+}
diff --git a/board/esd/common/xilinx_jtag/ports.h b/board/esd/common/xilinx_jtag/ports.h
new file mode 100644
index 0000000..8ee7de9
--- /dev/null
+++ b/board/esd/common/xilinx_jtag/ports.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*******************************************************/
+/* file: ports.h */
+/* abstract: This file contains extern declarations */
+/* for providing stimulus to the JTAG ports.*/
+/*******************************************************/
+
+#ifndef ports_dot_h
+#define ports_dot_h
+
+/* these constants are used to send the appropriate ports to setPort */
+/* they should be enumerated types, but some of the microcontroller */
+/* compilers don't like enumerated types */
+#define TCK (short) 0
+#define TMS (short) 1
+#define TDI (short) 2
+
+/*
+ * Use CONFIG_SYS_FPGA_xxx defines from board include file.
+ */
+#define JTAG_TMS CONFIG_SYS_FPGA_PRG /* output */
+#define JTAG_TCK CONFIG_SYS_FPGA_CLK /* output */
+#define JTAG_TDI CONFIG_SYS_FPGA_DATA /* output */
+#define JTAG_TDO CONFIG_SYS_FPGA_DONE /* input */
+
+/* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */
+void setPort(short p, short val);
+
+/* read the TDO bit and store it in val */
+unsigned char readTDOBit(void);
+
+/* make clock go down->up->down*/
+void pulseClock(void);
+
+/* read the next byte of data from the xsvf file */
+void readByte(unsigned char *data);
+
+void waitTime(long microsec);
+
+#endif
diff --git a/board/esd/cpci2dp/Kconfig b/board/esd/cpci2dp/Kconfig
new file mode 100644
index 0000000..646e8ff
--- /dev/null
+++ b/board/esd/cpci2dp/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CPCI2DP
+
+config SYS_BOARD
+ default "cpci2dp"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "CPCI2DP"
+
+endif
diff --git a/board/esd/cpci2dp/MAINTAINERS b/board/esd/cpci2dp/MAINTAINERS
new file mode 100644
index 0000000..660e185
--- /dev/null
+++ b/board/esd/cpci2dp/MAINTAINERS
@@ -0,0 +1,6 @@
+CPCI2DP BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/cpci2dp/
+F: include/configs/CPCI2DP.h
+F: configs/CPCI2DP_defconfig
diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile
new file mode 100644
index 0000000..ce2c6dd
--- /dev/null
+++ b/board/esd/cpci2dp/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cpci2dp.o flash.o ../common/misc.o ../common/cmd_loadpci.o
diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
new file mode 100644
index 0000000..336c551
--- /dev/null
+++ b/board/esd/cpci2dp/cpci2dp.c
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f (void)
+{
+ unsigned long CPC0_CR0Reg;
+
+ /*
+ * Setup GPIO pins
+ */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg |
+ ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED |
+ CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
+
+ /* set output pins to high */
+ out_be32((void *)GPIO0_OR, CONFIG_SYS_EEPROM_WP);
+ /* setup for output (LED=off) */
+ out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) unused
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
+
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ unsigned long CPC0_CR0Reg;
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /*
+ * Select cts (and not dsr) on uart1
+ */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
+
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming CPCI2DP");
+ } else {
+ puts(str);
+ }
+
+ printf(" (Ver 1.0)");
+
+ putc ('\n');
+
+ return 0;
+}
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state) {
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO_SINT2. */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO_SINT2. */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void *)GPIO0_OR) &
+ CONFIG_SYS_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts ("Query of write access state failed.\n");
+ } else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0) {
+ puts ("Setup of write access state failed.\n");
+ }
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(
+ eepwren, 2, 0, do_eep_wren,
+ "Enable / disable / query EEPROM write access",
+ ""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c
new file mode 100644
index 0000000..34bdc05
--- /dev/null
+++ b/board/esd/cpci2dp/flash.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b0 = -size_b0;
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+ /* printf("PB1CR = %x\n", pbcr); */
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -monitor_flash_len,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/cpci405/Kconfig b/board/esd/cpci405/Kconfig
new file mode 100644
index 0000000..bc56907
--- /dev/null
+++ b/board/esd/cpci405/Kconfig
@@ -0,0 +1,51 @@
+if TARGET_CPCI405
+
+config SYS_BOARD
+ default "cpci405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "CPCI405"
+
+endif
+
+if TARGET_CPCI4052
+
+config SYS_BOARD
+ default "cpci405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "CPCI4052"
+
+endif
+
+if TARGET_CPCI405AB
+
+config SYS_BOARD
+ default "cpci405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "CPCI405AB"
+
+endif
+
+if TARGET_CPCI405DT
+
+config SYS_BOARD
+ default "cpci405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "CPCI405DT"
+
+endif
diff --git a/board/esd/cpci405/MAINTAINERS b/board/esd/cpci405/MAINTAINERS
new file mode 100644
index 0000000..1da58dc
--- /dev/null
+++ b/board/esd/cpci405/MAINTAINERS
@@ -0,0 +1,12 @@
+CPCI405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/cpci405/
+F: include/configs/CPCI405.h
+F: configs/CPCI405_defconfig
+F: include/configs/CPCI4052.h
+F: configs/CPCI4052_defconfig
+F: include/configs/CPCI405AB.h
+F: configs/CPCI405AB_defconfig
+F: include/configs/CPCI405DT.h
+F: configs/CPCI405DT_defconfig
diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile
new file mode 100644
index 0000000..b140571
--- /dev/null
+++ b/board/esd/cpci405/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cpci405.o flash.o ../common/misc.o ../common/auto_update.o
+obj-y += ../common/cmd_loadpci.o
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
new file mode 100644
index 0000000..e23ec55
--- /dev/null
+++ b/board/esd/cpci405/cpci405.c
@@ -0,0 +1,769 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <net.h>
+#include <pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+#undef FPGA_DEBUG
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] =
+{
+#if defined(CONFIG_CPCI405_VER2)
+# if defined(CONFIG_CPCI405AB)
+# include "fpgadata_cpci405ab.c"
+# else
+# include "fpgadata_cpci4052.c"
+# endif
+#else
+# include "fpgadata_cpci405.c"
+#endif
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+#include "../common/auto_update.h"
+
+#if defined(CONFIG_CPCI405AB)
+au_image_t au_image[] = {
+ {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
+ {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+ {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
+ {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
+ {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
+};
+#else
+#if defined(CONFIG_CPCI405_VER2)
+au_image_t au_image[] = {
+ {"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
+ {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+ {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
+ {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
+ {"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
+};
+#else
+au_image_t au_image[] = {
+ {"cpci405/preinst.img", 0, -1, AU_SCRIPT},
+ {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+ {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
+ {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
+ {"cpci405/postinst.img", 0, 0, AU_SCRIPT},
+};
+#endif
+#endif
+
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+
+/* Prototypes */
+int cpci405_version(void);
+void lxt971_no_sleep(void);
+
+int board_early_init_f(void)
+{
+#ifndef CONFIG_CPCI405_VER2
+ int index, len, i;
+ int status;
+#endif
+
+#ifdef FPGA_DEBUG
+ /* set up serial port with default baudrate */
+ (void)get_clocks();
+ gd->baudrate = CONFIG_BAUDRATE;
+ serial_init();
+ console_init_f();
+#endif
+
+ /*
+ * First pull fpga-prg pin low,
+ * to disable fpga logic (on version 2 board)
+ */
+ out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
+ out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
+ out_be32((void *)GPIO0_OR, 0); /* pull prg low */
+
+ /*
+ * Boot onboard FPGA
+ */
+#ifndef CONFIG_CPCI405_VER2
+ if (cpci405_version() == 1) {
+ status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
+ if (status != 0) {
+ /* booting FPGA failed */
+#ifndef FPGA_DEBUG
+ /* set up serial port with default baudrate */
+ (void)get_clocks();
+ gd->baudrate = CONFIG_BAUDRATE;
+ serial_init();
+ console_init_f();
+#endif
+ printf("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf("(Timeout: INIT not low after "
+ "asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf("(Timeout: INIT not high after "
+ "deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf("(Timeout: DONE not high after "
+ "programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = fpgadata[index];
+ printf("FPGA: %s\n", &(fpgadata[index + 1]));
+ index += len + 3;
+ }
+ putc('\n');
+ /* delayed reboot */
+ for (i = 20; i > 0; i--) {
+ printf("Rebooting in %2d seconds \r",i);
+ for (index = 0; index < 1000; index++)
+ udelay(1000);
+ }
+ putc('\n');
+ do_reset(NULL, 0, 0, NULL);
+ }
+ }
+#endif /* !CONFIG_CPCI405_VER2 */
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
+ * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+#if defined(CONFIG_CPCI405_6U)
+ if (cpci405_version() == 3) {
+ mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
+ } else {
+ mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
+ }
+#else
+ mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
+#endif
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,
+ * INT0 highest priority */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ return 0;
+}
+
+int ctermm2(void)
+{
+#if defined(CONFIG_CPCI405_VER2)
+ return 0; /* no, board is cpci405 */
+#else
+ if ((in_8((void*)0xf0000400) == 0x00) &&
+ (in_8((void*)0xf0000401) == 0x01))
+ return 0; /* no, board is cpci405 */
+ else
+ return -1; /* yes, board is cterm-m2 */
+#endif
+}
+
+int cpci405_host(void)
+{
+ if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
+ return -1; /* yes, board is cpci405 host */
+ else
+ return 0; /* no, board is cpci405 adapter */
+}
+
+int cpci405_version(void)
+{
+ unsigned long CPC0_CR0Reg;
+ unsigned long value;
+
+ /*
+ * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+ */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
+ out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
+ udelay(1000); /* wait some time before reading input */
+ value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
+
+ /*
+ * Restore GPIO settings
+ */
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+ switch (value) {
+ case 0x00180000:
+ /* CS2==1 && CS3==1 -> version 1 */
+ return 1;
+ case 0x00080000:
+ /* CS2==0 && CS3==1 -> version 2 */
+ return 2;
+ case 0x00100000:
+ /* CS2==1 && CS3==0 -> version 3 or 6U board */
+ return 3;
+ case 0x00000000:
+ /* CS2==0 && CS3==0 -> version 4 */
+ return 4;
+ default:
+ /* should not be reached! */
+ return 2;
+ }
+}
+
+int misc_init_r (void)
+{
+ unsigned long CPC0_CR0Reg;
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+#if defined(CONFIG_CPCI405_VER2)
+ {
+ unsigned char *dst;
+ ulong len = sizeof(fpgadata);
+ int status;
+ int index;
+ int i;
+
+ /*
+ * On CPCI-405 version 2 the environment is saved in eeprom!
+ * FPGA can be gzip compressed (malloc) and booted this late.
+ */
+ if (cpci405_version() >= 2) {
+ /*
+ * Setup GPIO pins (CS6+CS7 as GPIO)
+ */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
+
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
+ (uchar *)fpgadata, &len) != 0) {
+ printf("GUNZIP ERROR - must RESET board to recover\n");
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ status = fpga_boot(dst, len);
+ if (status != 0) {
+ printf("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf("(Timeout: INIT not low after "
+ "asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf("(Timeout: INIT not high after "
+ "deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf("(Timeout: DONE not high after "
+ "programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = dst[index];
+ printf("FPGA: %s\n", &(dst[index + 1]));
+ index += len + 3;
+ }
+ putc('\n');
+ /* delayed reboot */
+ for (i = 20; i > 0; i--) {
+ printf("Rebooting in %2d seconds \r", i);
+ for (index = 0; index < 1000; index++)
+ udelay(1000);
+ }
+ putc('\n');
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ /* restore gpio/cs settings */
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+ puts("FPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = dst[index];
+ printf("%s ", &(dst[index + 1]));
+ index += len + 3;
+ }
+ putc('\n');
+
+ free(dst);
+
+ /*
+ * Reset FPGA via FPGA_DATA pin
+ */
+ SET_FPGA(FPGA_PRG | FPGA_CLK);
+ udelay(1000); /* wait 1ms */
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+ udelay(1000); /* wait 1ms */
+
+#if defined(CONFIG_CPCI405_6U)
+#error HIER GETH ES WEITER MIT IO ACCESSORS
+ if (cpci405_version() == 3) {
+ /*
+ * Enable outputs in fpga on version 3 board
+ */
+ out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+ in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+ CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
+
+ /*
+ * Set outputs to 0
+ */
+ out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
+
+ /*
+ * Reset external DUART
+ */
+ out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+ in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+ CONFIG_SYS_FPGA_MODE_DUART_RESET);
+ udelay(100);
+ out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+ in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
+ ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
+ }
+#endif
+ }
+ else {
+ puts("\n*** U-Boot Version does not match Board Version!\n");
+ puts("*** CPCI-405 Version 1.x detected!\n");
+ puts("*** Please use correct U-Boot version "
+ "(CPCI405 instead of CPCI4052)!\n\n");
+ }
+ }
+#else /* CONFIG_CPCI405_VER2 */
+ if (cpci405_version() >= 2) {
+ puts("\n*** U-Boot Version does not match Board Version!\n");
+ puts("*** CPCI-405 Board Version 2.x detected!\n");
+ puts("*** Please use correct U-Boot version "
+ "(CPCI4052 instead of CPCI405)!\n\n");
+ }
+#endif /* CONFIG_CPCI405_VER2 */
+
+ /*
+ * Select cts (and not dsr) on uart1
+ */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+#ifndef CONFIG_CPCI405_VER2
+ int index;
+ int len;
+#endif
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+ unsigned short ver;
+
+ puts("Board: ");
+
+ if (i == -1)
+ puts("### No HW ID - assuming CPCI405");
+ else
+ puts(str);
+
+ ver = cpci405_version();
+ printf(" (Ver %d.x, ", ver);
+
+ if (ctermm2()) {
+ char str[4];
+
+ /*
+ * Read board-id and save in env-variable
+ */
+ sprintf(str, "%d", *(unsigned char *)0xf0000400);
+ setenv("boardid", str);
+ printf("CTERM-M2 - Id=%s)", str);
+ } else {
+ if (cpci405_host())
+ puts("PCI Host Version)");
+ else
+ puts("PCI Adapter Version)");
+ }
+
+#ifndef CONFIG_CPCI405_VER2
+ puts("\nFPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = fpgadata[index];
+ printf("%s ", &(fpgadata[index + 1]));
+ index += len + 3;
+ }
+#endif
+
+ putc('\n');
+ return 0;
+}
+
+void reset_phy(void)
+{
+#if defined(CONFIG_LXT971_NO_SLEEP)
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
+
+#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
+void ide_set_reset(int on)
+{
+ /*
+ * Assert or deassert CompactFlash Reset Pin
+ */
+ if (on) { /* assert RESET */
+ out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+ in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
+ ~CONFIG_SYS_FPGA_MODE_CF_RESET);
+ } else { /* release RESET */
+ out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+ in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+ CONFIG_SYS_FPGA_MODE_CF_RESET);
+ }
+}
+
+#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
+
+#if defined(CONFIG_PCI)
+void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char int_line = 0xff;
+
+ /*
+ * Write pci interrupt line register (cpci405 specific)
+ */
+ switch (PCI_DEV(dev) & 0x03) {
+ case 0:
+ int_line = 27 + 2;
+ break;
+ case 1:
+ int_line = 27 + 3;
+ break;
+ case 2:
+ int_line = 27 + 0;
+ break;
+ case 3:
+ int_line = 27 + 1;
+ break;
+ }
+
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+int pci_pre_init(struct pci_controller *hose)
+{
+ hose->fixup_irq = cpci405_pci_fixup_irq;
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int rc;
+
+ __ft_board_setup(blob, bd);
+
+ /*
+ * Disable PCI in adapter mode.
+ */
+ if (!cpci405_host()) {
+ rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
+ "disabled", sizeof("disabled"), 1);
+ if (rc) {
+ printf("Unable to update property status in PCI node, "
+ "err=%s\n",
+ fdt_strerror(rc));
+ }
+ }
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CPCI405AB)
+#define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+ CONFIG_SYS_FPGA_MODE), \
+ in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+ CONFIG_SYS_FPGA_MODE)) | \
+ CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+
+#define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+ CONFIG_SYS_FPGA_MODE), \
+ in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+ CONFIG_SYS_FPGA_MODE)) & \
+ ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+
+#define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+ CONFIG_SYS_FPGA_STATUS)) & \
+ CONFIG_SYS_FPGA_MODE_1WIRE)
+
+/*
+ * Generate a 1-wire reset, return 1 if no presence detect was found,
+ * return 0 otherwise.
+ * (NOTE: Does not handle alarm presence from DS2404/DS1994)
+ */
+int OWTouchReset(void)
+{
+ int result;
+
+ ONE_WIRE_CLEAR;
+ udelay(480);
+ ONE_WIRE_SET;
+ udelay(70);
+
+ result = ONE_WIRE_GET;
+
+ udelay(410);
+ return result;
+}
+
+/*
+ * Send 1 a 1-wire write bit.
+ * Provide 10us recovery time.
+ */
+void OWWriteBit(int bit)
+{
+ if (bit) {
+ /*
+ * write '1' bit
+ */
+ ONE_WIRE_CLEAR;
+ udelay(6);
+ ONE_WIRE_SET;
+ udelay(64);
+ } else {
+ /*
+ * write '0' bit
+ */
+ ONE_WIRE_CLEAR;
+ udelay(60);
+ ONE_WIRE_SET;
+ udelay(10);
+ }
+}
+
+/*
+ * Read a bit from the 1-wire bus and return it.
+ * Provide 10us recovery time.
+ */
+int OWReadBit(void)
+{
+ int result;
+
+ ONE_WIRE_CLEAR;
+ udelay(6);
+ ONE_WIRE_SET;
+ udelay(9);
+
+ result = ONE_WIRE_GET;
+
+ udelay(55);
+ return result;
+}
+
+void OWWriteByte(int data)
+{
+ int loop;
+
+ for (loop = 0; loop < 8; loop++) {
+ OWWriteBit(data & 0x01);
+ data >>= 1;
+ }
+}
+
+int OWReadByte(void)
+{
+ int loop, result = 0;
+
+ for (loop = 0; loop < 8; loop++) {
+ result >>= 1;
+ if (OWReadBit())
+ result |= 0x80;
+ }
+
+ return result;
+}
+
+int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned short val;
+ int result;
+ int i;
+ unsigned char ow_id[6];
+ char str[32];
+
+ /*
+ * Clear 1-wire bit (open drain with pull-up)
+ */
+ val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
+ CONFIG_SYS_FPGA_MODE));
+ val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
+ out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
+ CONFIG_SYS_FPGA_MODE), val);
+
+ result = OWTouchReset();
+ if (result != 0)
+ puts("No 1-wire device detected!\n");
+
+ OWWriteByte(0x33); /* send read rom command */
+ OWReadByte(); /* skip family code ( == 0x01) */
+ for (i = 0; i < 6; i++)
+ ow_id[i] = OWReadByte();
+ OWReadByte(); /* read crc */
+
+ sprintf(str, "%02X%02X%02X%02X%02X%02X",
+ ow_id[0], ow_id[1], ow_id[2], ow_id[3], ow_id[4], ow_id[5]);
+ printf("Setting environment variable 'ow_id' to %s\n", str);
+ setenv("ow_id", str);
+
+ return 0;
+}
+U_BOOT_CMD(
+ onewire, 1, 1, do_onewire,
+ "Read 1-write ID",
+ ""
+);
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
+#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
+
+/*
+ * Write backplane ip-address...
+ */
+int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *buf;
+ ulong crc;
+ char str[32];
+ char *ptr;
+ IPaddr_t ipaddr;
+
+ buf = malloc(CONFIG_ENV_SIZE_2);
+ if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
+ (uchar *)buf, CONFIG_ENV_SIZE_2))
+ puts("\nError reading backplane EEPROM!\n");
+ else {
+ crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
+ if (crc != *(ulong *)buf) {
+ printf("ERROR: crc mismatch %08lx %08lx\n",
+ crc, *(ulong *)buf);
+ return -1;
+ }
+
+ /*
+ * Find bp_ip
+ */
+ ptr = strstr(buf+4, "bp_ip=");
+ if (ptr == NULL) {
+ printf("ERROR: bp_ip not found!\n");
+ return -1;
+ }
+ ptr += 6;
+ ipaddr = string_to_ip(ptr);
+
+ /*
+ * Update whole ip-addr
+ */
+ sprintf(str, "%pI4", &ipaddr);
+ setenv("ipaddr", str);
+ printf("Updated ip_addr from bp_eeprom to %s!\n", str);
+ }
+
+ free(buf);
+
+ return 0;
+}
+U_BOOT_CMD(
+ getbpip, 1, 1, do_get_bpip,
+ "Update IP-Address with Backplane IP-Address",
+ ""
+);
+
+/*
+ * Set and print backplane ip...
+ */
+int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *buf;
+ char str[32];
+ ulong crc;
+
+ if (argc < 2) {
+ puts("ERROR!\n");
+ return -1;
+ }
+
+ printf("Setting bp_ip to %s\n", argv[1]);
+ buf = malloc(CONFIG_ENV_SIZE_2);
+ memset(buf, 0, CONFIG_ENV_SIZE_2);
+ sprintf(str, "bp_ip=%s", argv[1]);
+ strcpy(buf+4, str);
+ crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
+ *(ulong *)buf = crc;
+
+ if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
+ 0, (uchar *)buf, CONFIG_ENV_SIZE_2))
+ puts("\nError writing backplane EEPROM!\n");
+
+ free(buf);
+
+ return 0;
+}
+U_BOOT_CMD(
+ setbpip, 2, 1, do_set_bpip,
+ "Write Backplane IP-Address",
+ ""
+);
+
+#endif /* CONFIG_CPCI405AB */
diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c
new file mode 100644
index 0000000..091652b
--- /dev/null
+++ b/board/esd/cpci405/flash.c
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long calc_size(unsigned long size)
+{
+ switch (size) {
+ case 1 << 20:
+ return 0;
+ case 2 << 20:
+ return 1;
+ case 4 << 20:
+ return 2;
+ case 8 << 20:
+ return 3;
+ case 16 << 20:
+ return 4;
+ default:
+ return 0;
+ }
+}
+
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+ uint pbcr;
+ unsigned long base_b0, base_b1;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ base_b0 = FLASH_BASE0_PRELIM;
+ size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ base_b1 = FLASH_BASE1_PRELIM;
+ size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+ /* Re-do sizing to get full correct info */
+
+ if (size_b1) {
+ if (size_b1 < (1 << 20)) {
+ /* minimum CS size on PPC405GP is 1MB !!! */
+ size_b1 = 1 << 20;
+ }
+ base_b1 = -size_b1;
+ mtdcr (EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr (EBC0_CFGDATA);
+ mtdcr (EBC0_CFGADDR, PB0CR);
+ pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17);
+ mtdcr (EBC0_CFGDATA, pbcr);
+#if 0 /* test-only */
+ printf("size_b1=%x base_b1=%x PB1CR = %x\n",
+ size_b1, base_b1, pbcr); /* test-only */
+#endif
+ }
+
+ if (size_b0) {
+ if (size_b0 < (1 << 20)) {
+ /* minimum CS size on PPC405GP is 1MB !!! */
+ size_b0 = 1 << 20;
+ }
+ base_b0 = base_b1 - size_b0;
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ pbcr = mfdcr (EBC0_CFGDATA);
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17);
+ mtdcr (EBC0_CFGDATA, pbcr);
+#if 0 /* test-only */
+ printf("size_b0=%x base_b0=%x PB0CR = %x\n",
+ size_b0, base_b0, pbcr); /* test-only */
+#endif
+ }
+
+ size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+ flash_get_offsets (base_b0, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ base_b0 + size_b0 - monitor_flash_len,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+
+ if (size_b1) {
+ /* Re-do sizing to get full correct info */
+ size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+ flash_get_offsets (base_b1, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ base_b1 + size_b1 - monitor_flash_len,
+ base_b1 + size_b1 - 1, &flash_info[1]);
+ /* monitor protection OFF by default (one is enough) */
+ flash_protect (FLAG_PROTECT_CLEAR,
+ base_b0 + size_b0 - monitor_flash_len,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+ } else {
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+
+ return (size_b0 + size_b1);
+}
diff --git a/board/esd/cpci405/fpgadata_cpci405.c b/board/esd/cpci405/fpgadata_cpci405.c
new file mode 100644
index 0000000..46c2fed
--- /dev/null
+++ b/board/esd/cpci405/fpgadata_cpci405.c
@@ -0,0 +1,683 @@
+0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
+0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0d,
+0x63, 0x70, 0x63, 0x69, 0x34, 0x30, 0x35, 0x32,
+0x2e, 0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b,
+0x73, 0x30, 0x35, 0x78, 0x6c, 0x76, 0x71, 0x31,
+0x30, 0x30, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30,
+0x30, 0x31, 0x2f, 0x30, 0x35, 0x2f, 0x31, 0x30,
+0x00, 0x64, 0x00, 0x09, 0x31, 0x35, 0x3a, 0x31,
+0x35, 0x3a, 0x32, 0x33, 0x00, 0x65, 0xe2, 0x01,
+0x00, 0x00, 0x15, 0x08, 0xff, 0x30, 0xe8, 0x01,
+0x01, 0x01, 0x01, 0xe7, 0xe6, 0x04, 0x01, 0x02,
+0x11, 0x05, 0x03, 0x05, 0x03, 0x05, 0x03, 0x05,
+0x03, 0x04, 0x04, 0x0b, 0x02, 0x02, 0x01, 0x04,
+0x02, 0x01, 0x0b, 0x07, 0x01, 0x01, 0x0d, 0x03,
+0x05, 0x09, 0x03, 0x05, 0x03, 0x05, 0x03, 0x0b,
+0x13, 0x01, 0x06, 0xe5, 0xe5, 0x02, 0x03, 0x0c,
+0x01, 0xe6, 0x11, 0x08, 0x13, 0x16, 0x08, 0x1e,
+0x0b, 0xe5, 0xe6, 0x0e, 0x09, 0x09, 0x09, 0x09,
+0x0b, 0x07, 0xe6, 0x08, 0x02, 0xe5, 0x04, 0x01,
+0xe6, 0x04, 0x0e, 0x01, 0x01, 0x14, 0x09, 0x09,
+0x09, 0x09, 0x05, 0x05, 0xe5, 0xe6, 0x04, 0x03,
+0x05, 0xe5, 0x01, 0x05, 0xe5, 0x07, 0x0c, 0xe5,
+0x5b, 0x01, 0x01, 0x05, 0x01, 0x11, 0x02, 0xe5,
+0xe5, 0x48, 0x13, 0x1a, 0x01, 0xe6, 0x3e, 0x0b,
+0x10, 0x03, 0x05, 0x13, 0x03, 0x01, 0x28, 0x14,
+0x11, 0x24, 0x03, 0xe5, 0xe6, 0xe5, 0x5d, 0x01,
+0x17, 0xe5, 0x01, 0x01, 0x0b, 0xe5, 0x12, 0x09,
+0x49, 0x03, 0x01, 0x01, 0x0d, 0x31, 0x0a, 0x2f,
+0x01, 0xe6, 0x28, 0x15, 0x1e, 0x1b, 0xe5, 0x01,
+0x10, 0x09, 0x09, 0x09, 0x09, 0x0b, 0x09, 0x09,
+0x09, 0x09, 0x05, 0x02, 0x04, 0x03, 0x10, 0x09,
+0x09, 0x04, 0x04, 0x09, 0x01, 0x05, 0x03, 0x09,
+0x13, 0x05, 0x03, 0x0e, 0x01, 0xe5, 0x0c, 0xe5,
+0x07, 0xe5, 0x04, 0x02, 0xe5, 0x04, 0x02, 0xe5,
+0x04, 0x02, 0xe5, 0x04, 0x03, 0xe6, 0x07, 0xe5,
+0x04, 0x02, 0xe5, 0x05, 0x01, 0xe5, 0xe5, 0x05,
+0xe5, 0x0e, 0x03, 0x10, 0x09, 0x09, 0x09, 0x09,
+0x06, 0x0d, 0x0a, 0xe5, 0x06, 0x0a, 0x0e, 0x01,
+0xe5, 0x05, 0x06, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x01, 0x05, 0xe5, 0x07, 0xe5, 0x09, 0xe5, 0x07,
+0xe5, 0x02, 0x04, 0xe5, 0xe5, 0x01, 0x03, 0xe5,
+0x07, 0xe5, 0x07, 0x02, 0x05, 0xe6, 0x0e, 0x09,
+0x09, 0x09, 0x09, 0x0d, 0x13, 0x03, 0x05, 0x02,
+0xe5, 0x02, 0x08, 0x05, 0xe8, 0x0c, 0x07, 0x01,
+0x09, 0x09, 0x06, 0x02, 0x05, 0x03, 0x01, 0x02,
+0x02, 0x01, 0x01, 0x06, 0x02, 0x02, 0x06, 0x02,
+0x06, 0x0a, 0x06, 0xe5, 0xe5, 0x0c, 0x02, 0x06,
+0x02, 0x06, 0x02, 0x04, 0x01, 0x02, 0x06, 0x02,
+0x06, 0x01, 0x02, 0x06, 0x02, 0x06, 0x01, 0xe6,
+0x02, 0xe6, 0xe6, 0x05, 0x02, 0x0d, 0x02, 0xe5,
+0x02, 0x2b, 0x01, 0x06, 0x0b, 0x0c, 0x06, 0x01,
+0x01, 0xe5, 0x14, 0x02, 0x03, 0xe5, 0xe6, 0x13,
+0x23, 0x0a, 0x14, 0x04, 0x1c, 0xe5, 0xe6, 0x27,
+0x01, 0x0e, 0x0a, 0x03, 0x13, 0x1d, 0x02, 0xe5,
+0x0d, 0x04, 0xe7, 0x14, 0x0e, 0x05, 0xe5, 0x05,
+0x0c, 0x03, 0x0a, 0x01, 0x09, 0x0a, 0x01, 0x10,
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diff --git a/board/esd/cpci405/fpgadata_cpci4052.c b/board/esd/cpci405/fpgadata_cpci4052.c
new file mode 100644
index 0000000..bedbb1f
--- /dev/null
+++ b/board/esd/cpci405/fpgadata_cpci4052.c
@@ -0,0 +1,1529 @@
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diff --git a/board/esd/cpci405/fpgadata_cpci405ab.c b/board/esd/cpci405/fpgadata_cpci405ab.c
new file mode 100644
index 0000000..acbc696
--- /dev/null
+++ b/board/esd/cpci405/fpgadata_cpci405ab.c
@@ -0,0 +1,2569 @@
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+0x9c, 0x70, 0x79, 0x59, 0x40, 0x6c, 0x16, 0x87,
+0x5c, 0x95, 0x52, 0x03, 0xbb, 0xa2, 0xe3, 0x15,
+0xc3, 0xba, 0x0f, 0x62, 0x4a, 0x04, 0xe7, 0x59,
+0x91, 0x18, 0x2e, 0x5b, 0x00, 0x0d, 0x11, 0x09,
+0x01, 0x1a, 0x67, 0xcb, 0x9e, 0xaf, 0x08, 0x81,
+0x2c, 0x5c, 0x4e, 0xe8, 0xaa, 0xda, 0x8a, 0x57,
+0x3a, 0xd8, 0x15, 0xb0, 0xc7, 0x65, 0x28, 0x76,
+0x40, 0xc7, 0x8d, 0xbf, 0xca, 0xac, 0xaf, 0x42,
+0x6a, 0xcf, 0x17, 0x2b, 0x0a, 0x3c, 0x0c, 0x33,
+0x8d, 0x3c, 0x8a, 0x78, 0x3a, 0x0d, 0x72, 0xd1,
+0x50, 0x7e, 0x80, 0xab, 0x65, 0xa6, 0x71, 0xbd,
+0x33, 0xae, 0x58, 0x4e, 0xa5, 0x54, 0xc0, 0x1f,
+0x5d, 0x4e, 0xa5, 0xeb, 0x32, 0x58, 0x8c, 0x46,
+0xf1, 0x0a, 0x69, 0xbd, 0xd6, 0xe0, 0x3c, 0xc3,
+0x26, 0x8c, 0x1d, 0x74, 0xc3, 0xdb, 0x24, 0x6f,
+0x81, 0x1e, 0x28, 0x6b, 0x42, 0x00, 0x2b, 0x61,
+0x86, 0xa1, 0x6a, 0x72, 0x09, 0x98, 0xf6, 0xb8,
+0x14, 0x28, 0x83, 0xfc, 0x45, 0xf2, 0x6d, 0xd0,
+0x07, 0x33, 0x16, 0xe5, 0x37, 0x35, 0x34, 0xc1,
+0x2b, 0x70, 0x25, 0xa8, 0x4d, 0x78, 0xa5, 0xd7,
+0x5e, 0xcb, 0x0d, 0x0a, 0xae, 0xa6, 0xe6, 0xc5,
+0x5e, 0x5c, 0x5f, 0xdc, 0x98, 0x2a, 0xd6, 0x57,
+0x08, 0x0d, 0xea, 0x8c, 0x0b, 0xb8, 0x5f, 0x09,
+0xe1, 0xec, 0x94, 0x1b, 0x2a, 0xfb, 0x79, 0x21,
+0xca, 0xe4, 0x68, 0x40, 0x2a, 0x90, 0x50, 0x5a,
+0xf3, 0x15, 0x6d, 0xe4, 0xb8, 0xac, 0x09, 0x5c,
+0x56, 0x18, 0x2e, 0x1b, 0x77, 0x49, 0x08, 0xd0,
+0x52, 0xa1, 0xdd, 0xe6, 0x3a, 0xc3, 0x68, 0x2a,
+0x2c, 0x5e, 0x7c, 0xdd, 0xa2, 0x4d, 0x86, 0xd9,
+0xa4, 0x15, 0x17, 0xbb, 0xa4, 0x42, 0xe3, 0x3a,
+0x68, 0x2a, 0x56, 0xd8, 0x8a, 0x73, 0xfc, 0x46,
+0x22, 0x82, 0x5e, 0xc4, 0xc5, 0x03, 0xed, 0xd2,
+0xe2, 0xb5, 0x2e, 0x1d, 0x5f, 0xb4, 0x48, 0xa9,
+0x86, 0x93, 0x8f, 0xfe, 0x50, 0xcc, 0x98, 0xe1,
+0xee, 0x41, 0x5c, 0x4e, 0x08, 0x5c, 0x6e, 0x81,
+0x84, 0x81, 0x86, 0x44, 0x5a, 0x8c, 0x04, 0xc7,
+0x65, 0xf1, 0x9c, 0xaf, 0xbb, 0xe9, 0xe5, 0x5b,
+0x63, 0x6f, 0xf6, 0x97, 0xcd, 0x57, 0xf3, 0x8b,
+0x6e, 0x35, 0xda, 0xd1, 0xc8, 0xbb, 0x49, 0xbe,
+0xd5, 0x78, 0xb3, 0xff, 0xca, 0xf9, 0xaa, 0xe1,
+0x8c, 0x6b, 0x6d, 0xf3, 0x8c, 0xa9, 0xad, 0xb9,
+0x4a, 0xa1, 0x59, 0x81, 0x58, 0x00, 0xdf, 0x28,
+0x2b, 0x49, 0x91, 0x55, 0x85, 0x53, 0xdb, 0x11,
+0x14, 0x4c, 0x7b, 0x35, 0x97, 0x0b, 0x5c, 0x5e,
+0xb2, 0xac, 0xbc, 0x34, 0xba, 0xdf, 0x3f, 0xb7,
+0x7d, 0x03, 0x1a, 0x06, 0x37, 0xfe, 0xfb, 0x71,
+0xb9, 0x6a, 0xec, 0xc6, 0x9f, 0xbc, 0x3c, 0x76,
+0xe6, 0xdc, 0xca, 0xaa, 0xb1, 0xa5, 0xfb, 0xde,
+0xf8, 0xe4, 0x4c, 0x06, 0x97, 0x33, 0xf7, 0x99,
+0x37, 0xb6, 0x64, 0xac, 0x68, 0xec, 0xcc, 0xe8,
+0xc9, 0x79, 0x63, 0x4b, 0x8f, 0xbe, 0x71, 0xfa,
+0x4c, 0x06, 0x97, 0x33, 0x6d, 0xae, 0xe1, 0xb8,
+0x3c, 0x20, 0x70, 0xd9, 0x7f, 0x15, 0xc7, 0xe5,
+0x9b, 0x19, 0x2e, 0x3f, 0x70, 0xd6, 0x69, 0x43,
+0xda, 0x61, 0x1b, 0x54, 0x1a, 0xee, 0xa9, 0xbd,
+0x96, 0xa1, 0xb1, 0x2b, 0x87, 0x99, 0xe1, 0xb4,
+0x41, 0xbf, 0xe5, 0x38, 0xb0, 0x09, 0x46, 0xa6,
+0xd3, 0xed, 0xec, 0x55, 0xe0, 0xe8, 0x33, 0xc9,
+0x70, 0x3e, 0xdc, 0xed, 0x19, 0x30, 0xd5, 0xb4,
+0x0c, 0xbe, 0xc6, 0x0e, 0x73, 0xc3, 0xf9, 0x50,
+0xf1, 0x92, 0x4d, 0x36, 0xbc, 0xa6, 0xd3, 0xe7,
+0x2f, 0x6f, 0x65, 0xf7, 0x98, 0x31, 0x78, 0xfe,
+0xeb, 0xc3, 0x20, 0x8e, 0xa1, 0xc8, 0x6e, 0x4a,
+0xec, 0x36, 0x17, 0xfd, 0x1a, 0x6e, 0x78, 0x7b,
+0xed, 0x36, 0xee, 0x76, 0xb2, 0x0d, 0x76, 0x19,
+0xb3, 0x35, 0xf7, 0xba, 0x30, 0x37, 0xa6, 0x1e,
+0xb4, 0xaf, 0x90, 0x3f, 0xfd, 0xf9, 0xa8, 0x93,
+0x9f, 0x4f, 0xe6, 0x8a, 0xdd, 0x1f, 0x0d, 0x72,
+0x43, 0xf8, 0x34, 0xbe, 0x8f, 0xcf, 0x87, 0x1b,
+0xce, 0xf3, 0xf9, 0x3e, 0x30, 0x99, 0x85, 0x75,
+0x9f, 0x75, 0xa1, 0x2f, 0x7b, 0xce, 0x4e, 0x7f,
+0xb0, 0xf1, 0x7f, 0xf2, 0x7c, 0xf8, 0x7c, 0x7d,
+0xc9, 0x73, 0x76, 0x5a, 0x68, 0xac, 0x46, 0xf7,
+0x65, 0x1f, 0x91, 0xd3, 0xfb, 0x53, 0x3e, 0xb5,
+0xb5, 0x7f, 0xe4, 0x8f, 0x3e, 0xdf, 0x9f, 0x7a,
+0x9b, 0xff, 0xc6, 0x4f, 0xfd, 0xd8, 0xd8, 0x98,
+0x79, 0x71, 0xe3, 0xff, 0xd3, 0x6d, 0x48, 0xf6,
+0x12, 0x1e, 0x6f, 0x64, 0x1a, 0x89, 0xa5, 0x37,
+0xf1, 0x5d, 0x1d, 0xbf, 0x06, 0xff, 0x0b, 0x6b,
+0x59, 0xbb, 0x88, 0xe1, 0x7c, 0xbe, 0x74, 0x2d,
+0xdb, 0x0d, 0xbe, 0x7c, 0x05, 0x66, 0x5a, 0xa9,
+0x99, 0x25, 0xac, 0x4e, 0x58, 0xd4, 0x81, 0x3f,
+0x65, 0x2d, 0x67, 0xda, 0x88, 0xb5, 0xfc, 0x7d,
+0x5c, 0xcb, 0xd6, 0x12, 0x9e, 0xb4, 0x96, 0xd5,
+0x3f, 0xb6, 0x96, 0x9d, 0x36, 0x7f, 0xe4, 0xf9,
+0x8c, 0x5b, 0xcb, 0xc0, 0xd7, 0xb2, 0xb5, 0x84,
+0xad, 0x45, 0x8d, 0x46, 0xaf, 0xf2, 0x27, 0xdf,
+0xe7, 0x4f, 0xf1, 0x75, 0x7f, 0xca, 0x73, 0x86,
+0x0c, 0x71, 0xbe, 0xc8, 0xe7, 0xab, 0xb5, 0xfc,
+0xff, 0xbe, 0x36, 0xff, 0xf9, 0x27, 0x04, 0xba,
+0x44, 0xf8, 0xff, 0x46, 0xae, 0xff, 0x2f, 0xfe,
+0xd3, 0xaf, 0x3e, 0x5f, 0x7d, 0xbe, 0xfa, 0x7c,
+0xf5, 0xf9, 0xea, 0xf3, 0xd5, 0xe7, 0xab, 0xcf,
+0x57, 0x9f, 0xff, 0x5f, 0x7c, 0x78, 0xbc, 0x44,
+0x78, 0xbc, 0x64, 0xfc, 0x3f, 0xdd, 0x97, 0xaf,
+0x3e, 0x5f, 0x7d, 0xbe, 0xfa, 0x7c, 0xf5, 0xf9,
+0xea, 0xf3, 0xd5, 0xe7, 0xab, 0xcf, 0x57, 0x9f,
+0xff, 0xbb, 0x3f, 0x21, 0x2e, 0x0c, 0x7b, 0xa3,
+0x36, 0x04, 0xbc, 0xa8, 0x2b, 0x87, 0xc0, 0xc8,
+0xfb, 0xd3, 0xfe, 0x1d, 0x6f, 0xef, 0x0a, 0x41,
+0x42, 0xca, 0xdc, 0xa7, 0xe7, 0x1f, 0x27, 0xf6,
+0xf5, 0xff, 0x02, 0xd6, 0x2c, 0x67, 0x26, 0xbd,
+0xa4, 0x00, 0x00,
diff --git a/board/esd/cpci5200/Kconfig b/board/esd/cpci5200/Kconfig
new file mode 100644
index 0000000..ddd9418
--- /dev/null
+++ b/board/esd/cpci5200/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CPCI5200
+
+config SYS_BOARD
+ default "cpci5200"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "cpci5200"
+
+endif
diff --git a/board/esd/cpci5200/MAINTAINERS b/board/esd/cpci5200/MAINTAINERS
new file mode 100644
index 0000000..184d3cc
--- /dev/null
+++ b/board/esd/cpci5200/MAINTAINERS
@@ -0,0 +1,6 @@
+CPCI5200 BOARD
+M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+S: Maintained
+F: board/esd/cpci5200/
+F: include/configs/cpci5200.h
+F: configs/cpci5200_defconfig
diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile
new file mode 100644
index 0000000..8421f54
--- /dev/null
+++ b/board/esd/cpci5200/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Objects for Xilinx JTAG programming (CPLD)
+# CPLD = ../common/xilinx_jtag/lenval.o \
+# ../common/xilinx_jtag/micro.o \
+# ../common/xilinx_jtag/ports.o
+
+# obj-y = cpci5200.o flash.o $(CPLD)
+obj-y = cpci5200.o strataflash.o
diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c
new file mode 100644
index 0000000..8bded0b
--- /dev/null
+++ b/board/esd/cpci5200/cpci5200.c
@@ -0,0 +1,284 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * cpci5200.c - main board support/init for the esd cpci5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+#include <netdev.h>
+
+#include "mt46v16m16-75.h"
+
+void init_ata_reset(void);
+
+static void sdram_start(int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register: extended mode */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+ /* set tap delay */
+ *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
+
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+ 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
+ } else {
+#if 0
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
+#else
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+ 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
+#endif
+ }
+
+#if 0
+ /* find RAM size using SDRAM CS1 only */
+ sdram_start(0);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ sdram_start(1);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ sdram_start(0);
+#endif
+ /* set SDRAM CS1 size according to the amount of RAM found */
+
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+
+ init_ata_reset();
+ return (dramsize);
+}
+
+int checkboard(void)
+{
+ puts("Board: esd CPCI5200 (cpci5200)\n");
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+ if (size == 0x02000000) {
+ /* adjust mapping */
+ *(vu_long *) MPC5XXX_BOOTCS_START =
+ *(vu_long *) MPC5XXX_CS0_START =
+ START_REG(CONFIG_SYS_BOOTCS_START | size);
+ *(vu_long *) MPC5XXX_BOOTCS_STOP =
+ *(vu_long *) MPC5XXX_CS0_STOP =
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+ }
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void) {
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+void init_ide_reset(void)
+{
+ debug("init_ide_reset\n");
+
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+ debug("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+ } else {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+ }
+}
+#endif
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6 0x40000000UL
+#define GPIO_USB0 0x00010000UL
+#define GPIO_USB9 0x08000000UL
+#define GPIO_USB9S 0x00080000UL
+
+void init_ata_reset(void)
+{
+ debug("init_ata_reset\n");
+
+ /* Configure GPIO_WU6 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+ __asm__ volatile ("sync");
+
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+ __asm__ volatile ("sync");
+
+ *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+ *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+ __asm__ volatile ("sync");
+
+ if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+ __asm__ volatile ("sync");
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int addr;
+ unsigned int size;
+ int i;
+ volatile unsigned long *ptr;
+
+ addr = simple_strtol(argv[1], NULL, 16);
+ size = simple_strtol(argv[2], NULL, 16);
+
+ printf("\nWriting at addr %08x, size %08x.\n", addr, size);
+
+ while (1) {
+ ptr = (volatile unsigned long *)addr;
+ for (i = 0; i < (size >> 2); i++) {
+ *ptr++ = i;
+ }
+
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return 0;
+ }
+ putc('.');
+ }
+ return 0;
+}
+
+U_BOOT_CMD(writepci, 3, 1, do_writepci,
+ "Write some data to pcibus",
+ "<addr> <size>\n"
+ ""
+);
diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h
new file mode 100644
index 0000000..63a4032
--- /dev/null
+++ b/board/esd/cpci5200/mt46v16m16-75.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x705f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c
new file mode 100644
index 0000000..7dc2e58
--- /dev/null
+++ b/board/esd/cpci5200/strataflash.c
@@ -0,0 +1,786 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+
+#undef DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI 0x98
+#define FLASH_CMD_READ_ID 0x90
+#define FLASH_CMD_RESET 0xff
+#define FLASH_CMD_BLOCK_ERASE 0x20
+#define FLASH_CMD_ERASE_CONFIRM 0xD0
+#define FLASH_CMD_WRITE 0x40
+#define FLASH_CMD_PROTECT 0x60
+#define FLASH_CMD_PROTECT_SET 0x01
+#define FLASH_CMD_PROTECT_CLEAR 0xD0
+#define FLASH_CMD_CLEAR_STATUS 0x50
+#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
+
+#define FLASH_STATUS_DONE 0x80
+#define FLASH_STATUS_ESS 0x40
+#define FLASH_STATUS_ECLBS 0x20
+#define FLASH_STATUS_PSLBS 0x10
+#define FLASH_STATUS_VPENS 0x08
+#define FLASH_STATUS_PSS 0x04
+#define FLASH_STATUS_DPS 0x02
+#define FLASH_STATUS_R 0x01
+#define FLASH_STATUS_PROTECT 0x01
+
+#define FLASH_OFFSET_CFI 0x55
+#define FLASH_OFFSET_CFI_RESP 0x10
+#define FLASH_OFFSET_WTOUT 0x1F
+#define FLASH_OFFSET_WBTOUT 0x20
+#define FLASH_OFFSET_ETOUT 0x21
+#define FLASH_OFFSET_CETOUT 0x22
+#define FLASH_OFFSET_WMAX_TOUT 0x23
+#define FLASH_OFFSET_WBMAX_TOUT 0x24
+#define FLASH_OFFSET_EMAX_TOUT 0x25
+#define FLASH_OFFSET_CEMAX_TOUT 0x26
+#define FLASH_OFFSET_SIZE 0x27
+#define FLASH_OFFSET_INTERFACE 0x28
+#define FLASH_OFFSET_BUFFER_SIZE 0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
+#define FLASH_OFFSET_ERASE_REGIONS 0x2D
+#define FLASH_OFFSET_PROTECT 0x02
+#define FLASH_OFFSET_USER_PROTECTION 0x85
+#define FLASH_OFFSET_INTEL_PROTECTION 0x81
+
+#define FLASH_MAN_CFI 0x01000000
+
+typedef union {
+ unsigned char c;
+ unsigned short w;
+ unsigned long l;
+} cfiword_t;
+
+typedef union {
+ unsigned char *cp;
+ unsigned short *wp;
+ unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
+ uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset,
+ uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size(ulong base, int banknum);
+static int flash_write_cfiword(flash_info_t * info, ulong dest,
+ cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector,
+ ulong tout, char *prompt);
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
+ int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+ return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
+}
+
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+ uchar *cp;
+ cp = flash_make_addr(info, 0, offset);
+ return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
+{
+ uchar *addr;
+
+ addr = flash_make_addr(info, sect, offset);
+ return ((addr[(2 * info->portwidth) - 1] << 8) |
+ addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
+{
+ uchar *addr;
+
+ addr = flash_make_addr(info, sect, offset);
+ return ((addr[(2 * info->portwidth) - 1] << 24) |
+ (addr[(info->portwidth) - 1] << 16) |
+ (addr[(4 * info->portwidth) - 1] << 8) |
+ addr[(3 * info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init(void)
+{
+ unsigned long size;
+ int i;
+ unsigned long address;
+
+ /* The flash is positioned back to back, with the demultiplexing of the chip
+ * based on the A24 address line.
+ *
+ */
+
+ address = CONFIG_SYS_FLASH_BASE;
+ size = 0;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ size += flash_info[i].size = flash_get_size(address, i);
+ address += CONFIG_SYS_FLASH_INCREMENT;
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf
+ ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i, flash_info[0].size, flash_info[i].size << 20);
+ }
+ }
+
+#if 0 /* test-only */
+ /* Monitor protection ON by default */
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+ for (i = 0;
+ flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1;
+ i++)
+ (void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#endif
+
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ int rcode = 0;
+ int prot;
+ int sect;
+
+ if (info->flash_id != FLASH_MAN_CFI) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+ if ((s_first < 0) || (s_first > s_last)) {
+ printf("- no sectors to erase\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+ flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+ if (flash_full_status_check
+ (info, sect, info->erase_blk_tout, "erase")) {
+ rcode = 1;
+ } else
+ printf(".");
+ }
+ }
+ printf(" done\n");
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id != FLASH_MAN_CFI) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ printf("CFI conformant FLASH (%d x %d)",
+ (info->portwidth << 3), (info->chipwidth << 3));
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+ printf
+ (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+ info->erase_blk_tout, info->write_tout, info->buffer_write_tout,
+ info->buffer_size);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf("\n");
+ printf(" %08lX%5s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong wp;
+ ulong cp;
+ int aln;
+ cfiword_t cword;
+ int i, rc;
+
+ /* get lower aligned address */
+ wp = (addr & ~(info->portwidth - 1));
+
+ /* handle unaligned start */
+ if ((aln = addr - wp) != 0) {
+ cword.l = 0;
+ cp = wp;
+ for (i = 0; i < aln; ++i, ++cp)
+ flash_add_byte(info, &cword, (*(uchar *) cp));
+
+ for (; (i < info->portwidth) && (cnt > 0); i++) {
+ flash_add_byte(info, &cword, *src++);
+ cnt--;
+ cp++;
+ }
+ for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+ flash_add_byte(info, &cword, (*(uchar *) cp));
+ if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
+ return rc;
+ wp = cp;
+ }
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+ while (cnt >= info->portwidth) {
+ i = info->buffer_size > cnt ? cnt : info->buffer_size;
+ if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
+ return rc;
+ wp += i;
+ src += i;
+ cnt -= i;
+ }
+#else
+ /* handle the aligned part */
+ while (cnt >= info->portwidth) {
+ cword.l = 0;
+ for (i = 0; i < info->portwidth; i++) {
+ flash_add_byte(info, &cword, *src++);
+ }
+ if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
+ return rc;
+ wp += info->portwidth;
+ cnt -= info->portwidth;
+ }
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ cword.l = 0;
+ for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
+ flash_add_byte(info, &cword, *src++);
+ --cnt;
+ }
+ for (; i < info->portwidth; ++i, ++cp) {
+ flash_add_byte(info, &cword, (*(uchar *) cp));
+ }
+
+ return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t * info, long sector, int prot)
+{
+ int retcode = 0;
+
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+ if (prot)
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+ else
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+ if ((retcode =
+ flash_full_status_check(info, sector, info->erase_blk_tout,
+ prot ? "protect" : "unprotect")) == 0) {
+
+ info->protect[sector] = prot;
+ /* Intel's unprotect unprotects all locking */
+ if (prot == 0) {
+ int i;
+ for (i = 0; i < info->sector_count; i++) {
+ if (info->protect[i])
+ flash_real_protect(info, i, 1);
+ }
+ }
+ }
+
+ return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ * wait for XSR.7 to be set. Time out with an error if it does not.
+ * This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout,
+ char *prompt)
+{
+ ulong start;
+
+ /* Wait for command completion */
+ start = get_timer(0);
+ while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+ if (get_timer(start) > info->erase_blk_tout) {
+ printf("Flash %s timeout at address %lx\n", prompt,
+ info->start[sector]);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+ return ERR_TIMOUT;
+ }
+ }
+ return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector,
+ ulong tout, char *prompt)
+{
+ int retcode;
+ retcode = flash_status_check(info, sector, tout, prompt);
+ if ((retcode == ERR_OK)
+ && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) {
+ retcode = ERR_INVAL;
+ printf("Flash %s error at address %lx\n", prompt,
+ info->start[sector]);
+ if (flash_isset
+ (info, sector, 0,
+ FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
+ printf("Command Sequence Error.\n");
+ } else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) {
+ printf("Block Erase Error.\n");
+ retcode = ERR_NOT_ERASED;
+ } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+ printf("Locking Error\n");
+ }
+ if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
+ printf("Block locked.\n");
+ retcode = ERR_PROTECTED;
+ }
+ if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+ printf("Vpp Low Error.\n");
+ }
+ flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+ return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c)
+{
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cword->c = c;
+ break;
+ case FLASH_CFI_16BIT:
+ cword->w = (cword->w << 8) | c;
+ break;
+ case FLASH_CFI_32BIT:
+ cword->l = (cword->l << 8) | c;
+ }
+}
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf)
+{
+ int i;
+ uchar *cp = (uchar *) cmdbuf;
+ for (i = 0; i < info->portwidth; i++)
+ *cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
+ uchar cmd)
+{
+
+ volatile cfiptr_t addr;
+ cfiword_t cword;
+ addr.cp = flash_make_addr(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ *addr.cp = cword.c;
+ break;
+ case FLASH_CFI_16BIT:
+ *addr.wp = cword.w;
+ break;
+ case FLASH_CFI_32BIT:
+ *addr.lp = cword.l;
+ break;
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+ cfiptr_t cptr;
+ cfiword_t cword;
+ int retval;
+ cptr.cp = flash_make_addr(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ retval = (cptr.cp[0] == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ retval = (cptr.wp[0] == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ retval = (cptr.lp[0] == cword.l);
+ break;
+ default:
+ retval = 0;
+ break;
+ }
+ return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+ cfiptr_t cptr;
+ cfiword_t cword;
+ int retval;
+ cptr.cp = flash_make_addr(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ retval = ((cptr.cp[0] & cword.c) == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ retval = ((cptr.wp[0] & cword.w) == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ retval = ((cptr.lp[0] & cword.l) == cword.l);
+ break;
+ default:
+ retval = 0;
+ break;
+ }
+ return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+ */
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+ for (info->portwidth = FLASH_CFI_8BIT;
+ info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
+ for (info->chipwidth = FLASH_CFI_BY8;
+ info->chipwidth <= info->portwidth;
+ info->chipwidth <<= 1) {
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+ flash_write_cmd(info, 0, FLASH_OFFSET_CFI,
+ FLASH_CMD_CFI);
+ if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
+ && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1,
+ 'R')
+ && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2,
+ 'Y'))
+ return 1;
+ }
+ }
+ return 0;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size(ulong base, int banknum)
+{
+ flash_info_t *info = &flash_info[banknum];
+ int i, j;
+ int sect_cnt;
+ unsigned long sector;
+ unsigned long tmp;
+ int size_ratio = 0;
+ uchar num_erase_regions;
+ int erase_region_size;
+ int erase_region_count;
+
+ info->start[0] = base;
+#if 0
+ invalidate_dcache_range(base, base + 0x400);
+#endif
+ if (flash_detect_cfi(info)) {
+
+ size_ratio = info->portwidth / info->chipwidth;
+ num_erase_regions =
+ flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+
+ sect_cnt = 0;
+ sector = base;
+ for (i = 0; i < num_erase_regions; i++) {
+ if (i > NUM_ERASE_REGIONS) {
+ printf("%d erase regions found, only %d used\n",
+ num_erase_regions, NUM_ERASE_REGIONS);
+ break;
+ }
+ tmp =
+ flash_read_long(info, 0,
+ FLASH_OFFSET_ERASE_REGIONS);
+ erase_region_size =
+ (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
+ tmp >>= 16;
+ erase_region_count = (tmp & 0xffff) + 1;
+ for (j = 0; j < erase_region_count; j++) {
+ info->start[sect_cnt] = sector;
+ sector += (erase_region_size * size_ratio);
+ info->protect[sect_cnt] =
+ flash_isset(info, sect_cnt,
+ FLASH_OFFSET_PROTECT,
+ FLASH_STATUS_PROTECT);
+ sect_cnt++;
+ }
+ }
+
+ info->sector_count = sect_cnt;
+ /* multiply the size by the number of chips */
+ info->size =
+ (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) *
+ size_ratio;
+ info->buffer_size =
+ (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+ info->erase_blk_tout =
+ (tmp *
+ (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+ info->buffer_write_tout =
+ (tmp *
+ (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+ info->write_tout =
+ (tmp *
+ (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) /
+ 1000;
+ info->flash_id = FLASH_MAN_CFI;
+ }
+
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+#ifdef DEBUG_FLASH
+ printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+#ifdef DEBUG_FLASH
+ printf("found %d erase regions\n", num_erase_regions);
+#endif
+#ifdef DEBUG_FLASH
+ printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
+#endif
+ return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword)
+{
+
+ cfiptr_t cptr;
+ int flag;
+
+ cptr.cp = (uchar *)dest;
+
+ /* Check if Flash is (sufficiently) erased */
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ flag = ((cptr.cp[0] & cword.c) == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ flag = ((cptr.wp[0] & cword.w) == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ flag = ((cptr.lp[0] & cword.l) == cword.l);
+ break;
+ default:
+ return 2;
+ }
+ if (!flag)
+ return 2;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cptr.cp[0] = cword.c;
+ break;
+ case FLASH_CFI_16BIT:
+ cptr.wp[0] = cword.w;
+ break;
+ case FLASH_CFI_32BIT:
+ cptr.lp[0] = cword.l;
+ break;
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t * info, ulong addr)
+{
+ int sector;
+ for (sector = info->sector_count - 1; sector >= 0; sector--) {
+ if (addr >= info->start[sector])
+ break;
+ }
+ return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
+ int len)
+{
+
+ int sector;
+ int cnt;
+ int retcode;
+ volatile cfiptr_t src;
+ volatile cfiptr_t dst;
+
+ src.cp = cp;
+ dst.cp = (uchar *) dest;
+ sector = find_sector(info, dest);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+ if ((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+ "write to buffer")) == ERR_OK) {
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cnt = len;
+ break;
+ case FLASH_CFI_16BIT:
+ cnt = len >> 1;
+ break;
+ case FLASH_CFI_32BIT:
+ cnt = len >> 2;
+ break;
+ default:
+ return ERR_INVAL;
+ break;
+ }
+ flash_write_cmd(info, sector, 0, (uchar) cnt - 1);
+ while (cnt-- > 0) {
+ switch (info->portwidth) {
+ case FLASH_CFI_8BIT:
+ *dst.cp++ = *src.cp++;
+ break;
+ case FLASH_CFI_16BIT:
+ *dst.wp++ = *src.wp++;
+ break;
+ case FLASH_CFI_32BIT:
+ *dst.lp++ = *src.lp++;
+ break;
+ default:
+ return ERR_INVAL;
+ break;
+ }
+ }
+ flash_write_cmd(info, sector, 0,
+ FLASH_CMD_WRITE_BUFFER_CONFIRM);
+ retcode =
+ flash_full_status_check(info, sector,
+ info->buffer_write_tout,
+ "buffer write");
+ }
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ return retcode;
+}
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/board/esd/cpciiser4/Kconfig b/board/esd/cpciiser4/Kconfig
new file mode 100644
index 0000000..4079b2f
--- /dev/null
+++ b/board/esd/cpciiser4/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CPCIISER4
+
+config SYS_BOARD
+ default "cpciiser4"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "CPCIISER4"
+
+endif
diff --git a/board/esd/cpciiser4/MAINTAINERS b/board/esd/cpciiser4/MAINTAINERS
new file mode 100644
index 0000000..85743db
--- /dev/null
+++ b/board/esd/cpciiser4/MAINTAINERS
@@ -0,0 +1,6 @@
+CPCIISER4 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/cpciiser4/
+F: include/configs/CPCIISER4.h
+F: configs/CPCIISER4_defconfig
diff --git a/board/esd/cpciiser4/Makefile b/board/esd/cpciiser4/Makefile
new file mode 100644
index 0000000..b8d6bea
--- /dev/null
+++ b/board/esd/cpciiser4/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = cpciiser4.o flash.o ../common/misc.o
diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c
new file mode 100644
index 0000000..e61cd5b
--- /dev/null
+++ b/board/esd/cpciiser4/cpciiser4.c
@@ -0,0 +1,165 @@
+/*
+ * (C) Copyright 2000
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "cpciiser4.h"
+#include <asm/processor.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+#if 0
+#define FPGA_DEBUG2
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+ int index, len, i;
+ int status;
+
+#ifdef FPGA_DEBUG
+ /* set up serial port with default baudrate */
+ (void) get_clocks ();
+ gd->baudrate = CONFIG_BAUDRATE;
+ serial_init ();
+ console_init_f ();
+#endif
+
+ /*
+ * Boot onboard FPGA
+ */
+ status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+ if (status != 0) {
+ /* booting FPGA failed */
+#ifndef FPGA_DEBUG
+ /* set up serial port with default baudrate */
+ (void) get_clocks ();
+ gd->baudrate = CONFIG_BAUDRATE;
+ serial_init ();
+ console_init_f ();
+#endif
+ printf ("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf ("(Timeout: DONE not high after programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = fpgadata[index];
+ printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+ index += len + 3;
+ }
+ putc ('\n');
+ /* delayed reboot */
+ for (i = 20; i > 0; i--) {
+ printf ("Rebooting in %2d seconds \r", i);
+ for (index = 0; index < 1000; index++)
+ udelay (1000);
+ }
+ putc ('\n');
+ do_reset (NULL, 0, 0, NULL);
+ }
+
+ /*
+ * Init FPGA via RESET (read access on CS3)
+ */
+ in_8((void *)0xf0200000);
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
+ /* mtdcr(UIC0PR, 0xFFFFFF81); / set int polarities */
+ mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+ int index;
+ int len;
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof (str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming AR405");
+ } else {
+ puts(str);
+ }
+
+ puts ("\nFPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = fpgadata[index];
+ printf ("%s ", &(fpgadata[index + 1]));
+ index += len + 3;
+ }
+
+ putc ('\n');
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+
+ return 0;
+}
diff --git a/board/esd/cpciiser4/cpciiser4.h b/board/esd/cpciiser4/cpciiser4.h
new file mode 100644
index 0000000..75e7950
--- /dev/null
+++ b/board/esd/cpciiser4/cpciiser4.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ * Start Address Length
+ * +-----------------------+ 0x4000_0000 Start of Flash -----------------
+ * | MON8xx code | 0x4000_0100 Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused) |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses | 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) | 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address | 0x04
+ * +-----------------------+ 0x4001_FFC0 ^
+ * | Hardware Information | 0x40 | MON8xx
+ * +=======================+ 0x4002_0000 (sector border) -----------------
+ * | Autostart Header | | Applications
+ * | ... | v
+ *
+ *****************************************************************************/
diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c
new file mode 100644
index 0000000..34bdc05
--- /dev/null
+++ b/board/esd/cpciiser4/flash.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b0 = -size_b0;
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+ /* printf("PB1CR = %x\n", pbcr); */
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -monitor_flash_len,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/cpciiser4/fpgadata.c b/board/esd/cpciiser4/fpgadata.c
new file mode 100644
index 0000000..ac6122d
--- /dev/null
+++ b/board/esd/cpciiser4/fpgadata.c
@@ -0,0 +1,4136 @@
+0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
+0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0c,
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+0x09, 0x06, 0xa1, 0xe6, 0xe5, 0x14, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x01, 0x05, 0xe5, 0x01, 0x05, 0xe5, 0x01,
+0x05, 0xe5, 0x07, 0xe5, 0x09, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x06, 0xe5, 0x01, 0x71, 0x09, 0x09, 0x09, 0x9e,
+0xe8, 0x72, 0x09, 0x09, 0x09, 0x9c, 0x03, 0x91,
+0x08, 0x93, 0x02, 0xe5, 0x2d, 0x3d, 0x09, 0x09,
+0x09, 0x04, 0x04, 0x9a, 0xe5, 0xe5, 0x66, 0x01,
+0xe5, 0x05, 0x09, 0x01, 0xe5, 0x05, 0x09, 0x12,
+0x8b, 0xe5, 0xe6, 0xe5, 0x0e, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x06, 0xe5, 0xe5, 0x06, 0x01, 0x04,
+0x02, 0x01, 0x04, 0x02, 0xe8, 0x01, 0x02, 0x01,
+0xe5, 0x02, 0x02, 0x01, 0x02, 0xe5, 0x02, 0x01,
+0x04, 0x04, 0x01, 0xe5, 0x05, 0x01, 0xe5, 0x05,
+0x01, 0xe5, 0x05, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01,
+0x08, 0x01, 0xe6, 0xe5, 0x3c, 0x35, 0x01, 0x09,
+0x0e, 0x9f, 0x01, 0xe7, 0x36, 0xe3, 0x12, 0xe5,
+0xe7, 0x46, 0x13, 0x17, 0x25, 0x8a, 0x0a, 0xe5,
+0xe5, 0x1c, 0x48, 0x0c, 0x09, 0x07, 0xe5, 0x07,
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+0x3c, 0x5b, 0x5c, 0x03, 0x0f, 0xe5, 0x08, 0x0a,
+0xe5, 0x10, 0x16, 0xe5, 0x05, 0x6d, 0x07, 0xe5,
+0x01, 0x63, 0x21, 0x13, 0x15, 0x7e, 0x02, 0xe5,
+0x61, 0x13, 0x01, 0x0c, 0x13, 0x11, 0x05, 0x7d,
+0xe5, 0xe5, 0x91, 0x06, 0x94, 0xe5, 0x01, 0x8a,
+0x0d, 0xe5, 0x93, 0x02, 0xe5, 0x61, 0x24, 0x12,
+0x06, 0x05, 0x27, 0x09, 0x57, 0xe6, 0x37, 0x32,
+0x1b, 0x1d, 0xe5, 0x24, 0x01, 0x08, 0x54, 0xe5,
+0x01, 0xe5, 0x3a, 0x49, 0x21, 0x25, 0x60, 0xe5,
+0xe6, 0x02, 0x09, 0xe7, 0x07, 0xe5, 0x07, 0xe5,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
+0x03, 0xe5, 0x01, 0xe5, 0x07, 0xe5, 0x05, 0xe7,
+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x05, 0xe7,
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+0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5,
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+0x06, 0x02, 0x06, 0x07, 0x01, 0x09, 0x07, 0x01,
+0x05, 0x03, 0x09, 0x09, 0x07, 0x01, 0x0b, 0x09,
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+0xe5, 0x11, 0xe5, 0x03, 0x03, 0x09, 0x1d, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x11, 0xe5, 0x97,
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+0xe5, 0x01, 0x0d, 0xe5, 0x05, 0x01, 0xe5, 0x07,
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+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x0b, 0x05, 0xe5, 0xe5, 0x0d, 0xe5, 0xe5,
+0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5,
+0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05,
+0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5,
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+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x0f, 0xe6, 0xe5, 0x86, 0x09, 0x15, 0x27, 0x09,
+0x4e, 0x05, 0xe5, 0x01, 0x0e, 0x09, 0x09, 0x09,
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+0x0e, 0xe7, 0x03, 0x37, 0x03, 0x05, 0x0d, 0x0f,
+0xe5, 0x33, 0x1c, 0x72, 0x03, 0xe6, 0xe5, 0x37,
+0x09, 0x13, 0x42, 0xe5, 0x8e, 0x04, 0xe7, 0x3f,
+0x13, 0x44, 0x90, 0x03, 0xe6, 0xe5, 0x8f, 0x9d,
+0x03, 0x13, 0x09, 0x09, 0x09, 0x1d, 0x09, 0x0c,
+0x06, 0x09, 0x09, 0x36, 0x06, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x15, 0x01,
+0xe5, 0x35, 0x05, 0x03, 0x05, 0x0d, 0x0f, 0x2a,
+0x97, 0x06, 0x02, 0xe5, 0x98, 0x8e, 0x05, 0x03,
+0xe3, 0x50, 0x14, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x02,
+0xe5, 0x04, 0xe6, 0x01, 0xe5, 0x04, 0x09, 0xe8,
+0x04, 0x09, 0x09, 0x09, 0x09, 0x09, 0x03, 0x05,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x03, 0x0f,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x03, 0x05, 0x09, 0x09, 0x08, 0xe5, 0x06, 0xe6,
+0x05, 0xe5, 0xe7, 0x07, 0xe5, 0x05, 0xe7, 0x08,
+0x09, 0x08, 0xe5, 0x07, 0xe5, 0x08, 0x07, 0xe6,
+0x08, 0x09, 0x09, 0x09, 0x09, 0x0f, 0x01, 0xe5,
+0x38, 0x09, 0x13, 0x0a, 0x36, 0x95, 0x02, 0x0d,
+0x09, 0x09, 0x09, 0x09, 0x04, 0x04, 0x03, 0xe5,
+0x03, 0x09, 0x03, 0x05, 0x04, 0x04, 0x09, 0x09,
+0x11, 0x09, 0x0b, 0x09, 0x09, 0x01, 0x09, 0x1d,
+0x0b, 0x07, 0x09, 0x09, 0x09, 0x09, 0x0f, 0x01,
+0xe7, 0x0a, 0x02, 0x07, 0x01, 0x07, 0x01, 0x07,
+0x01, 0x07, 0x03, 0x02, 0x02, 0x03, 0x01, 0xe5,
+0x01, 0x01, 0x07, 0x03, 0x05, 0x01, 0x04, 0x02,
+0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x02, 0x04,
+0x15, 0x04, 0x0e, 0x03, 0x07, 0x01, 0x07, 0x02,
+0x06, 0x02, 0x06, 0x01, 0x07, 0x09, 0x01, 0x07,
+0x01, 0x07, 0x01, 0x07, 0x01, 0x07, 0x01, 0x07,
+0x05, 0xe6, 0xe5, 0xe5, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+0xff, 0xff, 0xff,
diff --git a/board/esd/dp405/Kconfig b/board/esd/dp405/Kconfig
new file mode 100644
index 0000000..c0163ae
--- /dev/null
+++ b/board/esd/dp405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DP405
+
+config SYS_BOARD
+ default "dp405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "DP405"
+
+endif
diff --git a/board/esd/dp405/MAINTAINERS b/board/esd/dp405/MAINTAINERS
new file mode 100644
index 0000000..6833d8c
--- /dev/null
+++ b/board/esd/dp405/MAINTAINERS
@@ -0,0 +1,6 @@
+DP405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/dp405/
+F: include/configs/DP405.h
+F: configs/DP405_defconfig
diff --git a/board/esd/dp405/Makefile b/board/esd/dp405/Makefile
new file mode 100644
index 0000000..cfcfb66
--- /dev/null
+++ b/board/esd/dp405/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD = ../common/xilinx_jtag/lenval.o \
+ ../common/xilinx_jtag/micro.o \
+ ../common/xilinx_jtag/ports.o
+
+obj-y = dp405.o flash.o ../common/misc.o $(CPLD)
diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c
new file mode 100644
index 0000000..730ff21
--- /dev/null
+++ b/board/esd/dp405/dp405.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f (void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ */
+ mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ /*
+ * Reset CPLD via GPIO13 (CS4) pin
+ */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 13));
+ udelay(1000); /* wait 1ms */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | (0x80000000 >> 13));
+ udelay(1000); /* wait 1ms */
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+ unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
+ 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
+ unsigned char id1, id2, rev;
+
+ puts ("Board: ");
+
+ if (i == -1)
+ puts ("### No HW ID - assuming DP405");
+ else
+ puts(str);
+
+ id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f];
+ id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f];
+
+ rev = in_8((void *)0xf0001000);
+ if (rev & 0x10) /* old DP405 compatibility */
+ rev = in_8((void *)0xf0000800);
+
+ switch (rev & 0xc0) {
+ case 0x00:
+ puts(" (HW=DP405");
+ break;
+ case 0x80:
+ puts(" (HW=DP405/CO");
+ break;
+ case 0xc0:
+ puts(" (HW=DN405");
+ break;
+ }
+ printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f);
+
+ if ((rev & 0xc0) == 0xc0) {
+ printf(", C5V=%s",
+ in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on");
+ }
+ puts(")\n");
+
+ return 0;
+}
diff --git a/board/esd/dp405/flash.c b/board/esd/dp405/flash.c
new file mode 100644
index 0000000..23e8164
--- /dev/null
+++ b/board/esd/dp405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b0 = -size_b0;
+ switch (size_b0) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/du405/Kconfig b/board/esd/du405/Kconfig
new file mode 100644
index 0000000..2913fb9
--- /dev/null
+++ b/board/esd/du405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DU405
+
+config SYS_BOARD
+ default "du405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "DU405"
+
+endif
diff --git a/board/esd/du405/MAINTAINERS b/board/esd/du405/MAINTAINERS
new file mode 100644
index 0000000..5eff2a4
--- /dev/null
+++ b/board/esd/du405/MAINTAINERS
@@ -0,0 +1,6 @@
+DU405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/du405/
+F: include/configs/DU405.h
+F: configs/DU405_defconfig
diff --git a/board/esd/du405/Makefile b/board/esd/du405/Makefile
new file mode 100644
index 0000000..7914eab
--- /dev/null
+++ b/board/esd/du405/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = du405.o flash.o ../common/misc.o
diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c
new file mode 100644
index 0000000..8f5f4d0
--- /dev/null
+++ b/board/esd/du405/du405.c
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "du405.h"
+#include <asm/processor.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc4xx-i2c.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+#if 0
+#define FPGA_DEBUG2
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+ int index, len, i;
+ int status;
+
+#ifdef FPGA_DEBUG
+ /* set up serial port with default baudrate */
+ (void) get_clocks ();
+ gd->baudrate = CONFIG_BAUDRATE;
+ serial_init ();
+ console_init_f ();
+#endif
+
+ /*
+ * Boot onboard FPGA
+ */
+ status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+ if (status != 0) {
+ /* booting FPGA failed */
+#ifndef FPGA_DEBUG
+ /* set up serial port with default baudrate */
+ (void) get_clocks ();
+ gd->baudrate = CONFIG_BAUDRATE;
+ serial_init ();
+ console_init_f ();
+#endif
+ printf ("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf ("(Timeout: DONE not high after programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = fpgadata[index];
+ printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+ index += len + 3;
+ }
+ putc ('\n');
+ /* delayed reboot */
+ for (i = 20; i > 0; i--) {
+ printf ("Rebooting in %2d seconds \r", i);
+ for (index = 0; index < 1000; index++)
+ udelay (1000);
+ }
+ putc ('\n');
+ do_reset (NULL, 0, 0, NULL);
+ }
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive
+ * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive
+ * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr (UIC0PR, 0xFFFFFFB1); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 100 us
+ */
+ mtebc (EBC0_CFG, 0xb8400000);
+
+ return 0;
+}
+
+
+int misc_init_r (void)
+{
+ unsigned long CPC0_CR0Reg;
+
+ /*
+ * Setup UART1 handshaking: use CTS instead of DSR
+ */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
+
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ int index;
+ int len;
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof (str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming DU405");
+ } else {
+ puts (str);
+ }
+
+ puts ("\nFPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i = 0; i < 4; i++) {
+ len = fpgadata[index];
+ printf ("%s ", &(fpgadata[index + 1]));
+ index += len + 3;
+ }
+
+ putc ('\n');
+
+ /*
+ * Reset external DUART via FPGA
+ */
+ out_8((void *)FPGA_MODE_REG, 0xff); /* reset high active */
+ out_8((void *)FPGA_MODE_REG, 0x00); /* low again */
+
+ return 0;
+}
+
+void reset_phy(void)
+{
+#if defined(CONFIG_LXT971_NO_SLEEP)
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
diff --git a/board/esd/du405/du405.h b/board/esd/du405/du405.h
new file mode 100644
index 0000000..292f196
--- /dev/null
+++ b/board/esd/du405/du405.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ * Start Address Length
+ * +-----------------------+ 0x4000_0000 Start of Flash -----------------
+ * | MON8xx code | 0x4000_0100 Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused) |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses | 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) | 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address | 0x04
+ * +-----------------------+ 0x4001_FFC0 ^
+ * | Hardware Information | 0x40 | MON8xx
+ * +=======================+ 0x4002_0000 (sector border) -----------------
+ * | Autostart Header | | Applications
+ * | ... | v
+ *
+ *****************************************************************************/
diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c
new file mode 100644
index 0000000..5650e5e
--- /dev/null
+++ b/board/esd/du405/flash.c
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+ uint pbcr;
+ unsigned long base_b0, base_b1;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ base_b0 = FLASH_BASE0_PRELIM;
+ size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ base_b1 = FLASH_BASE1_PRELIM;
+ size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+ /* Re-do sizing to get full correct info */
+
+ if (size_b1) {
+ mtdcr (EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr (EBC0_CFGDATA);
+ mtdcr (EBC0_CFGADDR, PB0CR);
+ base_b1 = -size_b1;
+ pbcr = (pbcr & 0x0001ffff) | base_b1 |
+ (((size_b1 / 1024 / 1024) - 1) << 17);
+ mtdcr (EBC0_CFGDATA, pbcr);
+ /* printf("PB1CR = %x\n", pbcr); */
+ }
+
+ if (size_b0) {
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ pbcr = mfdcr (EBC0_CFGDATA);
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ base_b0 = base_b1 - size_b0;
+ pbcr = (pbcr & 0x0001ffff) | base_b0 |
+ (((size_b0 / 1024 / 1024) - 1) << 17);
+ mtdcr (EBC0_CFGDATA, pbcr);
+ /* printf("PB0CR = %x\n", pbcr); */
+ }
+
+ size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+ flash_get_offsets (base_b0, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ base_b0 + size_b0 - monitor_flash_len,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+
+ if (size_b1) {
+ /* Re-do sizing to get full correct info */
+ size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+ flash_get_offsets (base_b1, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ base_b1 + size_b1 - monitor_flash_len,
+ base_b1 + size_b1 - 1, &flash_info[1]);
+ /* monitor protection OFF by default (one is enough) */
+ flash_protect (FLAG_PROTECT_CLEAR,
+ base_b0 + size_b0 - monitor_flash_len,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+ } else {
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+
+ return (size_b0 + size_b1);
+}
diff --git a/board/esd/du405/fpgadata.c b/board/esd/du405/fpgadata.c
new file mode 100644
index 0000000..262f2ca
--- /dev/null
+++ b/board/esd/du405/fpgadata.c
@@ -0,0 +1,1405 @@
+0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
+0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0d,
+0x64, 0x75, 0x72, 0x61, 0x67, 0x34, 0x30, 0x35,
+0x2e, 0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b,
+0x73, 0x32, 0x30, 0x78, 0x6c, 0x74, 0x71, 0x31,
+0x34, 0x34, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30,
+0x30, 0x32, 0x2f, 0x30, 0x32, 0x2f, 0x32, 0x31,
+0x00, 0x64, 0x00, 0x09, 0x31, 0x32, 0x3a, 0x35,
+0x31, 0x3a, 0x30, 0x38, 0x00, 0x65, 0xe2, 0x01,
+0x00, 0x00, 0x2b, 0x98, 0xff, 0x30, 0xe6, 0xe5,
+0xe5, 0x02, 0x04, 0x01, 0xe6, 0x04, 0x01, 0x0d,
+0x04, 0x04, 0x02, 0x01, 0x04, 0x04, 0x03, 0x07,
+0x01, 0x03, 0x01, 0x04, 0x11, 0x01, 0x06, 0x02,
+0x15, 0x09, 0x02, 0x05, 0x07, 0x02, 0x02, 0x01,
+0x09, 0x03, 0x07, 0x01, 0x03, 0x01, 0x0b, 0x05,
+0x03, 0x01, 0x07, 0x08, 0xe5, 0xe5, 0x24, 0x05,
+0x09, 0x11, 0x01, 0x03, 0x03, 0x05, 0x0d, 0x09,
+0x0b, 0x09, 0x01, 0x1d, 0x09, 0x13, 0x03, 0x05,
+0x12, 0xe6, 0x11, 0x01, 0x03, 0x02, 0x02, 0x03,
+0x03, 0x01, 0x15, 0x01, 0x02, 0x28, 0x01, 0x05,
+0x02, 0xe5, 0xe5, 0x02, 0x02, 0x02, 0x0d, 0x02,
+0x02, 0x03, 0x02, 0xe5, 0xe5, 0x14, 0x01, 0x02,
+0xe5, 0x12, 0x0b, 0x03, 0x0f, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x04, 0x01, 0x02, 0x06, 0x02, 0x09,
+0x06, 0xe7, 0x05, 0x04, 0x06, 0x02, 0x06, 0x02,
+0x09, 0x07, 0xe6, 0x08, 0x09, 0x07, 0xe6, 0x08,
+0x09, 0x0e, 0xe5, 0xe6, 0x0d, 0x05, 0xe5, 0x01,
+0x05, 0xe5, 0x01, 0x05, 0xe5, 0x07, 0x09, 0xe5,
+0x01, 0x05, 0xe5, 0x07, 0xe6, 0xe5, 0x04, 0x03,
+0x05, 0xe8, 0x04, 0xe6, 0x02, 0x05, 0xe6, 0xe5,
+0x04, 0xe6, 0x06, 0x03, 0x05, 0xe5, 0xe6, 0x04,
+0xe5, 0x07, 0x09, 0xe5, 0xe6, 0x04, 0x09, 0x09,
+0x09, 0xe8, 0x46, 0x09, 0x14, 0xe5, 0x06, 0x0b,
+0x09, 0x15, 0x1d, 0x24, 0x02, 0xe5, 0xe5, 0x45,
+0x08, 0x15, 0x33, 0x1d, 0x28, 0x70, 0xe5, 0x09,
+0x09, 0x14, 0x42, 0x02, 0xe5, 0x30, 0x27, 0x01,
+0x15, 0x1b, 0x1d, 0x32, 0x01, 0x01, 0x5b, 0x0c,
+0x51, 0x24, 0x01, 0xe5, 0xe5, 0x28, 0xe5, 0x1c,
+0x25, 0x53, 0x19, 0xe5, 0x01, 0x2b, 0x45, 0x6c,
+0xe5, 0xe6, 0x35, 0x09, 0x07, 0x01, 0x09, 0x09,
+0x12, 0x63, 0x09, 0x02, 0x03, 0x0c, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x09, 0x07, 0x01, 0x09, 0x01,
+0x07, 0x0b, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x09, 0x09, 0x0d, 0x02, 0xe5, 0x02, 0x0c,
+0x09, 0x09, 0x09, 0x06, 0x02, 0x05, 0xe5, 0x01,
+0x07, 0x01, 0x05, 0x03, 0x07, 0x01, 0x09, 0x0b,
+0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
+0x09, 0x0d, 0xe5, 0x01, 0x05, 0x07, 0xe5, 0x05,
+0x01, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0x03,
+0x05, 0xe5, 0x07, 0x09, 0xe5, 0x07, 0x09, 0xe5,
+0x07, 0x01, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07,
+0xe5, 0x07, 0xe5, 0x04, 0x02, 0xe5, 0x12, 0x04,
+0x0b, 0x05, 0x02, 0xe5, 0x07, 0xe5, 0x08, 0x09,
+0x08, 0xe5, 0x08, 0x09, 0x09, 0x09, 0x06, 0x03,
+0xe5, 0x07, 0xe5, 0x08, 0x08, 0xe5, 0x07, 0xe5,
+0x08, 0x09, 0x04, 0x03, 0xe5, 0x08, 0x09, 0x0d,
+0x01, 0xe6, 0x05, 0x06, 0xe5, 0x07, 0xe5, 0xe5,
+0x05, 0xe5, 0xe5, 0x01, 0x03, 0xe5, 0x14, 0x06,
+0x09, 0x13, 0xe5, 0x09, 0xe5, 0xe5, 0x05, 0xe5,
+0xe5, 0x05, 0xe5, 0x07, 0xe5, 0xe5, 0x05, 0xe5,
+0xe5, 0x05, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0xe5,
+0x05, 0xe5, 0x07, 0xe5, 0x07, 0x02, 0x03, 0xe8,
+0x0e, 0x01, 0x09, 0x09, 0x07, 0x08, 0xe5, 0x07,
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diff --git a/board/esd/du440/Kconfig b/board/esd/du440/Kconfig
new file mode 100644
index 0000000..b4b3e6b
--- /dev/null
+++ b/board/esd/du440/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DU440
+
+config SYS_BOARD
+ default "du440"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "DU440"
+
+endif
diff --git a/board/esd/du440/MAINTAINERS b/board/esd/du440/MAINTAINERS
new file mode 100644
index 0000000..ba26948
--- /dev/null
+++ b/board/esd/du440/MAINTAINERS
@@ -0,0 +1,6 @@
+DU440 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/du440/
+F: include/configs/DU440.h
+F: configs/DU440_defconfig
diff --git a/board/esd/du440/Makefile b/board/esd/du440/Makefile
new file mode 100644
index 0000000..ef41d94
--- /dev/null
+++ b/board/esd/du440/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = du440.o
+extra-y += init.o
diff --git a/board/esd/du440/config.mk b/board/esd/du440/config.mk
new file mode 100644
index 0000000..9cb071e
--- /dev/null
+++ b/board/esd/du440/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2002-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
new file mode 100644
index 0000000..b168b24
--- /dev/null
+++ b/board/esd/du440/du440.c
@@ -0,0 +1,882 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/ppc440.h>
+#include "du440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+extern ulong flash_get_size (ulong base, int banknum);
+
+int usbhub_init(void);
+int dvi_init(void);
+int eeprom_write_enable (unsigned dev_addr, int state);
+int board_revision(void);
+
+static int du440_post_errors;
+
+int board_early_init_f(void)
+{
+ u32 sdr0_cust0;
+ u32 sdr0_pfc1, sdr0_pfc2;
+ u32 reg;
+
+ mtdcr(EBC0_CFGADDR, EBC0_CFG);
+ mtdcr(EBC0_CFGDATA, 0xb8400000);
+
+ /*
+ * Setup the GPIO pins
+ */
+ out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_OSRL, 0x50055400);
+ out_be32((void*)GPIO0_OSRH, 0x55005000);
+ out_be32((void*)GPIO0_TSRL, 0x50055400);
+ out_be32((void*)GPIO0_TSRH, 0x55005000);
+ out_be32((void*)GPIO0_ISR1L, 0x50000000);
+ out_be32((void*)GPIO0_ISR1H, 0x00000000);
+ out_be32((void*)GPIO0_ISR2L, 0x00000000);
+ out_be32((void*)GPIO0_ISR2H, 0x00000000);
+ out_be32((void*)GPIO0_ISR3L, 0x00000000);
+ out_be32((void*)GPIO0_ISR3H, 0x00000000);
+
+ out_be32((void*)GPIO1_OR, 0x00000000);
+ out_be32((void*)GPIO1_TCR, 0xc2000000 |
+ CONFIG_SYS_GPIO1_IORSTN |
+ CONFIG_SYS_GPIO1_IORST2N |
+ CONFIG_SYS_GPIO1_LEDUSR1 |
+ CONFIG_SYS_GPIO1_LEDUSR2 |
+ CONFIG_SYS_GPIO1_LEDPOST |
+ CONFIG_SYS_GPIO1_LEDDU);
+ out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU);
+ out_be32((void*)GPIO1_OSRL, 0x0c280000);
+ out_be32((void*)GPIO1_OSRH, 0x00000000);
+ out_be32((void*)GPIO1_TSRL, 0xcc000000);
+ out_be32((void*)GPIO1_TSRH, 0x00000000);
+ out_be32((void*)GPIO1_ISR1L, 0x00005550);
+ out_be32((void*)GPIO1_ISR1H, 0x00000000);
+ out_be32((void*)GPIO1_ISR2L, 0x00050000);
+ out_be32((void*)GPIO1_ISR2H, 0x00000000);
+ out_be32((void*)GPIO1_ISR3L, 0x01400000);
+ out_be32((void*)GPIO1_ISR3H, 0x00000000);
+
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ /*
+ * UIC1:
+ * bit30: ext. Irq 1: PLD : int 32+30
+ */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xfffffffd);
+ mtdcr(UIC1TR, 0x00000000);
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ /*
+ * UIC2
+ * bit3: ext. Irq 2: DCF77 : int 64+3
+ */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ /* select Ethernet pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+
+ /* setup EMAC bridge interface */
+ if (board_revision() == 0) {
+ /* 1 x MII */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_1_2;
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_1_2;
+ } else {
+ /* 2 x SMII */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_6;
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_6;
+ }
+
+ /* enable 2nd IIC */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /* PCI arbiter enabled */
+ mfsdr(SDR0_PCI0, reg);
+ mtsdr(SDR0_PCI0, 0x80000000 | reg);
+
+ /* setup NAND FLASH */
+ mfsdr(SDR0_CUST0, sdr0_cust0);
+ sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ (0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) |
+ (0x80000000 >> (28 + CONFIG_SYS_NAND1_CS));
+ mtsdr(SDR0_CUST0, sdr0_cust0);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ uint pbcr;
+ int size_val = 0;
+ u32 reg;
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1;
+ unsigned long sdr0_srst0, sdr0_srst1;
+ int i, j;
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ size_val = ffs(gd->bd->bi_flashsize) - 21;
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+ /*
+ * USB suff...
+ */
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+
+ /* An 8-bit/60MHz interface is the only possible alternative
+ when connecting the Device to the PHY */
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
+
+ /* To enable the USB 2.0 Device function through the UTMI interface */
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /*
+ * Take USB out of reset:
+ * -Initial status = all cores are in reset
+ * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
+ * -wait 1 ms
+ * -deassert reset to PHY
+ * -wait 1 ms
+ * -deassert reset to HOST
+ * -wait 4 ms
+ * -deassert all other resets
+ */
+ mfsdr(SDR0_SRST1, sdr0_srst1);
+ sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
+ SDR0_SRST1_P4OPB0 | \
+ SDR0_SRST1_OPBA2 | \
+ SDR0_SRST1_PLB42OPB1 | \
+ SDR0_SRST1_OPB2PLB40);
+ mtsdr(SDR0_SRST1, sdr0_srst1);
+ udelay(1000);
+
+ mfsdr(SDR0_SRST1, sdr0_srst1);
+ sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
+ mtsdr(SDR0_SRST1, sdr0_srst1);
+ udelay(1000);
+
+ mfsdr(SDR0_SRST0, sdr0_srst0);
+ sdr0_srst0 &= ~SDR0_SRST0_USB2H;
+ mtsdr(SDR0_SRST0, sdr0_srst0);
+ udelay(4000);
+
+ /* finally all the other resets */
+ mtsdr(SDR0_SRST1, 0x00000000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host(int phy)\n");
+
+ /*
+ * Clear PLB4A0_ACR[WRP]
+ * This fix will make the MAL burst disabling patch for the Linux
+ * EMAC driver obsolete.
+ */
+ reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+ mtdcr(PLB4A0_ACR, reg);
+
+ /*
+ * release IO-RST#
+ * We have to wait at least 560ms until we may call usbhub_init
+ */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
+ CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N);
+
+ /*
+ * flash USR1/2 LEDs (600ms)
+ * This results in the necessary delay from IORST# until
+ * calling usbhub_init will succeed
+ */
+ for (j = 0; j < 3; j++) {
+ out_be32((void*)GPIO1_OR,
+ (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) |
+ CONFIG_SYS_GPIO1_LEDUSR1);
+
+ for (i = 0; i < 100; i++)
+ udelay(1000);
+
+ out_be32((void*)GPIO1_OR,
+ (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) |
+ CONFIG_SYS_GPIO1_LEDUSR2);
+
+ for (i = 0; i < 100; i++)
+ udelay(1000);
+ }
+
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
+ ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2));
+
+ if (usbhub_init())
+ du440_post_errors++;
+
+ if (dvi_init())
+ du440_post_errors++;
+
+ return 0;
+}
+
+int pld_revision(void)
+{
+ out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00);
+ return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
+}
+
+int board_revision(void)
+{
+ int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK)
+ >> CONFIG_SYS_GPIO1_HWVER_SHIFT);
+
+ return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
+ ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
+}
+
+#if defined(CONFIG_SHOW_ACTIVITY)
+void board_show_activity (ulong timestamp)
+{
+ if ((timestamp % 100) == 0)
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1);
+}
+
+void show_activity(int arg)
+{
+}
+#endif /* CONFIG_SHOW_ACTIVITY */
+
+int du440_phy_addr(int devnum)
+{
+ if (board_revision() == 0)
+ return devnum;
+
+ return devnum + 1;
+}
+
+int checkboard(void)
+{
+ char serno[32];
+
+ puts("Board: DU440");
+
+ if (getenv_f("serial#", serno, sizeof(serno)) > 0) {
+ puts(", serial# ");
+ puts(serno);
+ }
+
+ printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
+ board_revision(), pld_revision());
+ return (0);
+}
+
+int last_stage_init(void)
+{
+ int e, i;
+
+ /* everyting is ok: turn on POST-LED */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
+
+ /* slowly blink on errors and finally keep LED off */
+ for (e = 0; e < du440_post_errors; e++) {
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
+
+ for (i = 0; i < 500; i++)
+ udelay(1000);
+
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST);
+
+ for (i = 0; i < 500; i++)
+ udelay(1000);
+ }
+
+ return 0;
+}
+
+/*
+ * read field strength from I2C ADC
+ */
+int dcf77_status(void)
+{
+ unsigned int oldbus;
+ uchar u[2];
+ int mv;
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(1);
+
+ if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
+ I2C_SET_BUS(oldbus);
+ return -1;
+ }
+
+ mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
+
+ I2C_SET_BUS(oldbus);
+ return mv;
+}
+
+int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int mv;
+ u32 pin, pinold;
+ unsigned long long t1, t2;
+ bd_t *bd = gd->bd;
+
+ printf("DCF77: ");
+ mv = dcf77_status();
+ if (mv > 0)
+ printf("signal=%d mV\n", mv);
+ else
+ printf("ERROR - no signal\n");
+
+ t1 = t2 = 0;
+ pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
+ while (!ctrlc()) {
+ pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
+ if (pin && !pinold) { /* bit start */
+ t1 = get_ticks();
+ if (t2 && ((unsigned int)(t1 - t2) /
+ (bd->bi_procfreq / 1000) >= 1800))
+ printf("Start of minute\n");
+
+ t2 = t1;
+ }
+ if (t1 && !pin && pinold) { /* bit end */
+ printf("%5d\n", (unsigned int)(get_ticks() - t1) /
+ (bd->bi_procfreq / 1000));
+ }
+ pinold = pin;
+ }
+
+ printf("Abort\n");
+ return 0;
+}
+U_BOOT_CMD(
+ dcf77, 1, 1, do_dcf77,
+ "Check DCF77 receiver",
+ ""
+);
+
+/*
+ * initialize USB hub via I2C1
+ */
+int usbhub_init(void)
+{
+ int reg;
+ int ret = 0;
+ unsigned int oldbus;
+ uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
+ 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
+ 0x32};
+ uchar stcd;
+
+ printf("Hub: ");
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(1);
+
+ for (reg = 0; reg < sizeof(u); reg++)
+ if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
+ ret = -1;
+ break;
+ }
+
+ if (ret == 0) {
+ stcd = 0x03;
+ if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
+ ret = -1;
+ }
+
+ if (ret == 0)
+ printf("initialized\n");
+ else
+ printf("failed - cannot initialize USB hub\n");
+
+ I2C_SET_BUS(oldbus);
+ return ret;
+}
+
+int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ usbhub_init();
+ return 0;
+}
+U_BOOT_CMD(
+ hubinit, 1, 1, do_hubinit,
+ "Initialize USB hub",
+ ""
+);
+
+#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
+int boot_eeprom_write (unsigned dev_addr,
+ unsigned offset,
+ uchar *buffer,
+ unsigned cnt)
+{
+ unsigned end = offset + cnt;
+ unsigned blk_off;
+ int rcode = 0;
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 1);
+#endif
+ /*
+ * Write data until done or would cross a write page boundary.
+ * We must write the address again when changing pages
+ * because the address counter only increments within a page.
+ */
+
+ while (offset < end) {
+ unsigned alen, len;
+ unsigned maxlen;
+
+ uchar addr[2];
+
+ blk_off = offset & 0xFF; /* block offset */
+
+ addr[0] = offset >> 8; /* block number */
+ addr[1] = blk_off; /* block offset */
+ alen = 2;
+ addr[0] |= dev_addr; /* insert device address */
+
+ len = end - offset;
+
+ /*
+ * For a FRAM device there is no limit on the number of the
+ * bytes that can be ccessed with the single read or write
+ * operation.
+ */
+#if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
+
+#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
+
+ maxlen = BOOT_EEPROM_PAGE_SIZE -
+ BOOT_EEPROM_PAGE_OFFSET(blk_off);
+#else
+ maxlen = 0x100 - blk_off;
+#endif
+ if (maxlen > I2C_RXTX_LEN)
+ maxlen = I2C_RXTX_LEN;
+
+ if (len > maxlen)
+ len = maxlen;
+
+ if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
+ rcode = 1;
+
+ buffer += len;
+ offset += len;
+
+#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
+ udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+ }
+#if defined(CONFIG_SYS_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 0);
+#endif
+ return rcode;
+}
+
+int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong sdsdp[4];
+
+ if (argc > 1) {
+ if (!strcmp(argv[1], "533")) {
+ printf("Bootstrapping for 533MHz\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+ sdsdp[1] = 0x095fa030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ } else if (!strcmp(argv[1], "533-66")) {
+ printf("Bootstrapping for 533MHz (66MHz PCI)\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
+ sdsdp[1] = 0x0957a030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ } else if (!strcmp(argv[1], "667")) {
+ printf("Bootstrapping for 667MHz\n");
+ sdsdp[0] = 0x8778a256;
+ /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
+ sdsdp[1] = 0x0947a030;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
+ * -> not working when overclocking 533MHz chips
+ * -> untested on 667MHz chips */
+ /* sdsdp[1]=0x095fa030; */
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ } else if (!strcmp(argv[1], "667-166")) {
+ printf("Bootstrapping for 667-166MHz\n");
+ sdsdp[0] = 0x8778a252;
+ sdsdp[1] = 0x09d7a030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ }
+ } else {
+ printf("Bootstrapping for 533MHz (default)\n");
+ sdsdp[0] = 0x87788252;
+ /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
+ sdsdp[1] = 0x095fa030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
+ }
+
+ printf("Writing boot EEPROM ...\n");
+ if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
+ 0, (uchar*)sdsdp, 16) != 0)
+ printf("boot_eeprom_write failed\n");
+ else
+ printf("done (dump via 'i2c md 52 0.1 10')\n");
+
+ return 0;
+}
+U_BOOT_CMD(
+ sbe, 2, 0, do_setup_boot_eeprom,
+ "setup boot eeprom",
+ ""
+);
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/*
+ * Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
+ (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr))
+ return -1;
+ else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO_SINT2. */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO_SINT2. */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void*)GPIO0_OR) &
+ CONFIG_SYS_GPIO0_EP_EEP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+ if (state < 0)
+ puts ("Query of write access state failed.\n");
+ else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0)
+ puts ("Setup of write access state failed.\n");
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "Enable / disable / query EEPROM write access",
+ ""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+static int got_pldirq;
+
+static int pld_interrupt(u32 arg)
+{
+ int rc = -1; /* not for us */
+ u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE);
+
+ /* check for PLD interrupt */
+ if (status & PWR_INT_FLAG) {
+ /* reset this int */
+ out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
+ rc = 0;
+ got_pldirq = 1; /* trigger backend */
+ }
+
+ return rc;
+}
+
+int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ got_pldirq = 0;
+
+ /* clear any pending interrupt */
+ out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
+
+ irq_install_handler(CPLD_IRQ,
+ (interrupt_handler_t *)pld_interrupt, 0);
+
+ printf("Waiting ...\n");
+ while(!got_pldirq) {
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ break;
+ }
+ }
+ if (got_pldirq) {
+ printf("Got interrupt!\n");
+ printf("Power %sready!\n",
+ in_8((void *)CONFIG_SYS_CPLD_BASE) &
+ PWR_RDY ? "":"NOT ");
+ }
+
+ irq_free_handler(CPLD_IRQ);
+ return 0;
+}
+U_BOOT_CMD(
+ wpi, 1, 1, do_waitpwrirq,
+ "Wait for power change interrupt",
+ ""
+);
+
+/*
+ * initialize DVI panellink transmitter
+ */
+int dvi_init(void)
+{
+ int i;
+ int ret = 0;
+ unsigned int oldbus;
+ uchar u[] = {0x08, 0x34,
+ 0x09, 0x20,
+ 0x0a, 0x90,
+ 0x0c, 0x89,
+ 0x08, 0x35};
+
+ printf("DVI: ");
+
+ oldbus = I2C_GET_BUS();
+ I2C_SET_BUS(0);
+
+ for (i = 0; i < sizeof(u); i += 2)
+ if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
+ ret = -1;
+ break;
+ }
+
+ if (ret == 0)
+ printf("initialized\n");
+ else
+ printf("failed - cannot initialize DVI transmitter\n");
+
+ I2C_SET_BUS(oldbus);
+ return ret;
+}
+
+int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ dvi_init();
+ return 0;
+}
+U_BOOT_CMD(
+ dviinit, 1, 1, do_dviinit,
+ "Initialize DVI Panellink transmitter",
+ ""
+);
+
+/*
+ * TODO: 'time' command might be useful for others as well.
+ * Move to 'common' directory.
+ */
+int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned long long start, end;
+ char c, cmd[CONFIG_SYS_CBSIZE];
+ char *p, *d = cmd;
+ int ret, i;
+ ulong us;
+
+ for (i = 1; i < argc; i++) {
+ p = argv[i];
+
+ if (i > 1)
+ *d++ = ' ';
+
+ while ((c = *p++) != '\0') {
+ *d++ = c;
+ }
+ }
+ *d = '\0';
+
+ start = get_ticks();
+ ret = run_command(cmd, 0);
+ end = get_ticks();
+
+ printf("ticks=%ld\n", (ulong)(end - start));
+ us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
+ printf("usec=%ld\n", us);
+
+ return ret;
+}
+U_BOOT_CMD(
+ time, CONFIG_SYS_MAXARGS, 1, do_time,
+ "run command and output execution time",
+ ""
+);
+
+extern void video_hw_rectfill (
+ unsigned int bpp, /* bytes per pixel */
+ unsigned int dst_x, /* dest pos x */
+ unsigned int dst_y, /* dest pos y */
+ unsigned int dim_x, /* frame width */
+ unsigned int dim_y, /* frame height */
+ unsigned int color /* fill color */
+ );
+
+/*
+ * graphics demo
+ * draw rectangles using pseudorandom number generator
+ * (see http://www.embedded.com/columns/technicalinsights/20900500)
+ */
+unsigned int rprime = 9972;
+static unsigned int r;
+static unsigned int Y;
+
+unsigned int prng(unsigned int max)
+{
+ if (r == 0 || r == 1 || r == -1)
+ r = rprime; /* keep from getting stuck */
+
+ r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
+ Y = (r >> 16) % max; /* choose upper bits and reduce */
+ return Y;
+}
+
+int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int color;
+ unsigned int x, y, dx, dy;
+
+ while (!ctrlc()) {
+ x = prng(1280 - 1);
+ y = prng(1024 - 1);
+ dx = prng(1280- x - 1);
+ dy = prng(1024 - y - 1);
+ color = prng(0x10000);
+ video_hw_rectfill(2, x, y, dx, dy, color);
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo,
+ "demo",
+ ""
+);
diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h
new file mode 100644
index 0000000..df065ba
--- /dev/null
+++ b/board/esd/du440/du440.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDR0_USB0 0x0320 /* USB Control Register */
+
+#define CONFIG_SYS_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */
+#define CONFIG_SYS_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
+
+#define CONFIG_SYS_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
+#define CONFIG_SYS_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */
+
+#define CONFIG_SYS_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
+#define CONFIG_SYS_GPIO1_HWVER_SHIFT 4
+#define CONFIG_SYS_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */
+#define CONFIG_SYS_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */
+#define CONFIG_SYS_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */
+#define CONFIG_SYS_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */
+
+#define CPLD_VERSION_MASK 0x0f
+#define PWR_INT_FLAG 0x80
+#define PWR_RDY 0x10
+
+#define CPLD_IRQ (32+30)
diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S
new file mode 100644
index 0000000..ab4b6ce
--- /dev/null
+++ b/board/esd/du440/init.S
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ */
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
+
+ /* TLB-entry for PCI IO */
+ tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_RW | SA_IG )
+
+ /* TLB-entries for EBC: CPLD, DUMEM, DUIO */
+ tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_RWX | SA_IG )
+
+ /* TLB-entry for NAND */
+ tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_RWX | SA_IG )
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
+
+ /* TLB-entry PCI registers */
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
+
+ /* TLB-entry for peripherals */
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
+
+ tlbtab_end
diff --git a/board/esd/hh405/Kconfig b/board/esd/hh405/Kconfig
new file mode 100644
index 0000000..8a8623a
--- /dev/null
+++ b/board/esd/hh405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_HH405
+
+config SYS_BOARD
+ default "hh405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "HH405"
+
+endif
diff --git a/board/esd/hh405/MAINTAINERS b/board/esd/hh405/MAINTAINERS
new file mode 100644
index 0000000..b695c7b
--- /dev/null
+++ b/board/esd/hh405/MAINTAINERS
@@ -0,0 +1,6 @@
+HH405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/hh405/
+F: include/configs/HH405.h
+F: configs/HH405_defconfig
diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile
new file mode 100644
index 0000000..fba21a3
--- /dev/null
+++ b/board/esd/hh405/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = hh405.o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
+ ../common/auto_update.o
diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c
new file mode 100644
index 0000000..23e8164
--- /dev/null
+++ b/board/esd/hh405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b0 = -size_b0;
+ switch (size_b0) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/hh405/fpgadata.c b/board/esd/hh405/fpgadata.c
new file mode 100644
index 0000000..620c714
--- /dev/null
+++ b/board/esd/hh405/fpgadata.c
@@ -0,0 +1,5034 @@
+0x1f, 0x8b, 0x08, 0x08, 0x7a, 0x8e, 0xc6, 0x43,
+0x00, 0x03, 0x68, 0x68, 0x34, 0x30, 0x35, 0x5f,
+0x31, 0x5f, 0x30, 0x36, 0x2e, 0x62, 0x69, 0x74,
+0x00, 0xec, 0xfd, 0x7f, 0x7c, 0x14, 0x55, 0x9a,
+0x2f, 0x8e, 0x3f, 0x75, 0xaa, 0x12, 0x4e, 0xba,
+0x3a, 0xe9, 0x22, 0x09, 0x4e, 0x54, 0xc4, 0x4a,
+0x27, 0x30, 0x4d, 0xec, 0x84, 0xa6, 0x83, 0x21,
+0x42, 0x48, 0x2a, 0x9d, 0xe8, 0x44, 0x40, 0xe9,
+0x71, 0xdc, 0x59, 0x76, 0xae, 0x77, 0xb6, 0x65,
+0x98, 0xbd, 0x99, 0xb9, 0xe8, 0x46, 0xc7, 0xbb,
+0x97, 0xf1, 0xce, 0x8f, 0x93, 0x4e, 0x80, 0x4e,
+0x82, 0xd0, 0x20, 0x33, 0x46, 0x87, 0x71, 0x9b,
+0x10, 0x35, 0x2a, 0x33, 0xdb, 0x04, 0x94, 0xf0,
+0x63, 0xb0, 0x12, 0xa3, 0x36, 0x10, 0x20, 0x32,
+0xdc, 0x19, 0x54, 0x46, 0x1b, 0x8c, 0x4c, 0xd4,
+0xe8, 0x04, 0x44, 0x4d, 0xf8, 0xf9, 0x7d, 0x4e,
+0x75, 0xa7, 0xbb, 0x1a, 0x77, 0xf7, 0xce, 0xfd,
+0xdc, 0xd7, 0xf7, 0xf3, 0xda, 0xd7, 0xeb, 0x73,
+0xb3, 0x7f, 0xec, 0x99, 0xea, 0x43, 0x59, 0x75,
+0xea, 0x9c, 0xe7, 0x79, 0x3f, 0xbf, 0xde, 0x0f,
+0x64, 0xd8, 0x46, 0x63, 0xff, 0x07, 0x20, 0xdc,
+0x0f, 0xb6, 0xfa, 0xfa, 0x39, 0xae, 0x5b, 0xff,
+0x7e, 0xf6, 0xdf, 0xbb, 0xca, 0x4a, 0x1e, 0xfc,
+0xde, 0x72, 0x58, 0x06, 0xb2, 0xfb, 0x47, 0xb7,
+0xba, 0xbe, 0xff, 0xc8, 0x43, 0xb3, 0xe7, 0xcc,
+0x81, 0xef, 0xe1, 0xff, 0x72, 0xb9, 0xca, 0x66,
+0xb9, 0x66, 0xcf, 0x9a, 0xed, 0x86, 0xe5, 0x90,
+0x31, 0xbb, 0x7c, 0xde, 0xec, 0x39, 0xf3, 0x4a,
+0x6f, 0x85, 0xef, 0x83, 0x50, 0xda, 0x79, 0x15,
+0xff, 0x5e, 0x78, 0xf2, 0x6f, 0xfe, 0xc1, 0x05,
+0x4c, 0x00, 0x80, 0x49, 0x2e, 0xc1, 0xc7, 0xff,
+0xbf, 0xec, 0x12, 0x54, 0x01, 0x58, 0x55, 0xb1,
+0x0b, 0x74, 0xfe, 0xbf, 0x21, 0xfe, 0x7b, 0x86,
+0x0b, 0x54, 0xf3, 0xff, 0x16, 0x5c, 0xa0, 0x81,
+0x17, 0xb4, 0xb5, 0x6a, 0x36, 0xfc, 0x15, 0x7f,
+0x92, 0xc4, 0x26, 0x86, 0x7f, 0xd5, 0x7c, 0x48,
+0xcc, 0xbf, 0x7a, 0x90, 0xfd, 0x9b, 0x93, 0x92,
+0x7f, 0x55, 0xe7, 0x42, 0xf1, 0x91, 0x4a, 0x5c,
+0xff, 0xeb, 0xe9, 0x42, 0x2d, 0x4c, 0xdc, 0xf5,
+0xbd, 0xb7, 0xff, 0x9a, 0xfb, 0xcf, 0xff, 0x62,
+0xe2, 0xfe, 0xff, 0xbb, 0xf3, 0x41, 0xf9, 0x2b,
+0xa6, 0xe3, 0xfb, 0x4e, 0x0c, 0xde, 0x53, 0x04,
+0x1f, 0xe4, 0xc1, 0x75, 0x90, 0xc6, 0x80, 0x0f,
+0xd2, 0x41, 0xf8, 0x57, 0x06, 0xf3, 0xfb, 0x27,
+0xe6, 0xeb, 0x8d, 0xfb, 0xe0, 0x08, 0x2b, 0x55,
+0xad, 0x11, 0xd1, 0x0d, 0xef, 0xe5, 0x57, 0x45,
+0x96, 0x9c, 0xcb, 0xd9, 0xd7, 0x7c, 0xf5, 0x7b,
+0x73, 0x23, 0xb6, 0x73, 0x62, 0x39, 0x3b, 0x09,
+0x3f, 0x1a, 0xb5, 0x8e, 0xe5, 0x8c, 0x4a, 0x0d,
+0x13, 0xf3, 0xe9, 0x08, 0x6d, 0x65, 0xee, 0x7c,
+0x1a, 0x90, 0xed, 0x70, 0x48, 0x29, 0x19, 0x92,
+0x1b, 0x49, 0xd1, 0xd2, 0x3d, 0xd9, 0x25, 0x47,
+0x6c, 0xfb, 0x48, 0x97, 0x16, 0x90, 0xca, 0x22,
+0x96, 0x1e, 0x31, 0x2c, 0x4d, 0xac, 0x62, 0x44,
+0x5a, 0xbb, 0xa5, 0x55, 0x98, 0xa1, 0x65, 0x30,
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+0x22, 0x28, 0x5e, 0xe2, 0x58, 0x18, 0x22, 0x2e,
+0x28, 0x12, 0xe4, 0x43, 0xda, 0x9b, 0x8a, 0x50,
+0x6f, 0x7f, 0x27, 0xc3, 0x88, 0x85, 0x1d, 0xa5,
+0x91, 0x54, 0xfb, 0xb7, 0xae, 0xd1, 0x3d, 0x13,
+0xe5, 0x66, 0x57, 0xbb, 0xe3, 0xf5, 0x4f, 0x86,
+0x39, 0x16, 0xae, 0x41, 0xba, 0x23, 0xc2, 0xc4,
+0x58, 0xb3, 0x9f, 0x27, 0x98, 0x01, 0x71, 0x24,
+0xe9, 0x2c, 0x5e, 0x9e, 0x28, 0xd6, 0xf9, 0x30,
+0x05, 0x47, 0x49, 0x4f, 0xf9, 0x89, 0x09, 0x86,
+0x85, 0x4b, 0x0e, 0x94, 0xc7, 0x38, 0x1f, 0xb6,
+0x09, 0x74, 0xb4, 0xce, 0x7a, 0xeb, 0x05, 0xec,
+0xb7, 0x31, 0x91, 0x0f, 0xa9, 0x32, 0x45, 0x4a,
+0xf6, 0x26, 0x5e, 0x8d, 0x92, 0x2e, 0x7b, 0x97,
+0xd1, 0x52, 0x50, 0xa6, 0x45, 0x22, 0x2a, 0xe0,
+0x91, 0xc5, 0xf8, 0xc1, 0x00, 0x9e, 0xb0, 0x53,
+0xa5, 0xe8, 0x6c, 0xf1, 0x43, 0x34, 0x2b, 0x4b,
+0xd1, 0x14, 0x39, 0x2a, 0x8e, 0xb8, 0x66, 0x22,
+0x9a, 0xc2, 0xf5, 0xaa, 0xb7, 0x87, 0x7c, 0x49,
+0x79, 0x21, 0xdd, 0xac, 0xe6, 0x70, 0xcf, 0x53,
+0xfa, 0x48, 0x27, 0xe4, 0x6c, 0xed, 0xb2, 0xd2,
+0x07, 0x9d, 0x30, 0x62, 0xeb, 0x97, 0xf9, 0x91,
+0x11, 0x9b, 0x38, 0xbe, 0xf8, 0xd9, 0x06, 0xa5,
+0xcb, 0x6a, 0x5f, 0x68, 0x0c, 0xde, 0xc0, 0x52,
+0xaf, 0x5d, 0x84, 0x4d, 0x17, 0xc3, 0xc2, 0x02,
+0x99, 0x16, 0x7c, 0x58, 0xf0, 0xe5, 0x1f, 0x1a,
+0x09, 0x29, 0xc6, 0x09, 0xce, 0x87, 0xaf, 0x56,
+0x90, 0x06, 0xab, 0x22, 0x7e, 0xec, 0x06, 0x3e,
+0xf4, 0xc5, 0x1b, 0xcd, 0x87, 0x14, 0x5a, 0x4e,
+0x1a, 0x79, 0xfc, 0x5e, 0x28, 0xc5, 0xb2, 0x86,
+0x46, 0xcf, 0x41, 0xf1, 0x88, 0x66, 0x58, 0xaa,
+0x1e, 0xe6, 0x47, 0x2c, 0x95, 0x80, 0x6f, 0x7e,
+0xb0, 0xa4, 0x74, 0x92, 0x66, 0x24, 0x6e, 0x8f,
+0x1a, 0xe0, 0x24, 0xab, 0x24, 0x4e, 0xb0, 0xbd,
+0xcd, 0x8e, 0x30, 0xc3, 0x5f, 0x22, 0xd4, 0xfb,
+0xbe, 0x60, 0xd6, 0x30, 0x05, 0x1f, 0x02, 0x0d,
+0x61, 0xfe, 0xe1, 0xf5, 0xa9, 0xcb, 0x87, 0x6a,
+0x52, 0x98, 0x41, 0x7f, 0xfc, 0x0c, 0xad, 0x6a,
+0x61, 0x7c, 0x98, 0xb0, 0x43, 0x59, 0xcc, 0x43,
+0xab, 0xd2, 0xdd, 0x6a, 0x53, 0x9d, 0x0f, 0xeb,
+0xc6, 0xf6, 0x8d, 0x87, 0xd0, 0x0a, 0xcf, 0x3f,
+0x24, 0x6d, 0x1f, 0x45, 0xa3, 0xf2, 0x7a, 0x88,
+0xa5, 0x65, 0x61, 0xd8, 0x4b, 0xa1, 0xdd, 0xbe,
+0xcf, 0x4b, 0xe8, 0x7b, 0x7b, 0xe1, 0x18, 0x64,
+0x07, 0x63, 0x53, 0x93, 0x25, 0x38, 0xd6, 0x94,
+0x65, 0xf7, 0x67, 0xb9, 0x89, 0xc8, 0x35, 0xa1,
+0x98, 0xb7, 0x5e, 0x14, 0xd7, 0xab, 0x8f, 0x34,
+0xe3, 0x32, 0xd9, 0x55, 0xd7, 0xb0, 0xf5, 0x6a,
+0x30, 0x65, 0xcd, 0x5b, 0xaf, 0x22, 0x7e, 0xbc,
+0x47, 0x9c, 0xe6, 0xfd, 0xe1, 0xe3, 0xf6, 0x07,
+0x86, 0xc9, 0x7e, 0xdd, 0x5e, 0x81, 0x2b, 0xe0,
+0x9a, 0x33, 0x75, 0xe3, 0xcb, 0x3f, 0x98, 0x59,
+0x7b, 0x69, 0xa2, 0x18, 0x2e, 0x22, 0x3d, 0xf6,
+0xd0, 0x04, 0x0d, 0x6f, 0x87, 0x4b, 0x0c, 0x2c,
+0x8b, 0xe1, 0x24, 0x33, 0x94, 0x9b, 0xb3, 0xbe,
+0xf9, 0xc9, 0x29, 0xa5, 0xc1, 0xd4, 0x7e, 0x5c,
+0xdf, 0xc3, 0x4a, 0xe9, 0x4c, 0xca, 0x1c, 0x8e,
+0xeb, 0x37, 0x9b, 0x86, 0xf9, 0x11, 0x7c, 0xc8,
+0x2e, 0x46, 0xf2, 0x8b, 0x85, 0xec, 0x8a, 0x70,
+0xc3, 0xe5, 0xc3, 0x86, 0x4b, 0x85, 0x94, 0x14,
+0x2c, 0xc1, 0x87, 0x36, 0xa7, 0x41, 0x34, 0x3e,
+0x2c, 0x64, 0x66, 0x26, 0x97, 0x6e, 0xcc, 0x3f,
+0xd6, 0xf6, 0xf6, 0xb6, 0x68, 0x3e, 0xa7, 0x25,
+0xf7, 0x32, 0x3e, 0xcc, 0x63, 0xc6, 0xb1, 0xb8,
+0xe1, 0xf9, 0x07, 0xcd, 0x20, 0x1a, 0x5f, 0xfc,
+0xf0, 0x48, 0x0c, 0xb9, 0x29, 0x50, 0x9b, 0x8c,
+0x18, 0xa4, 0xc0, 0x62, 0x6a, 0x92, 0x5f, 0x3b,
+0xd9, 0x26, 0x0c, 0xf8, 0x84, 0x10, 0xe8, 0x40,
+0x15, 0xba, 0xa1, 0x09, 0xf8, 0xed, 0xf2, 0xc2,
+0xf8, 0xf9, 0xb0, 0xbb, 0x21, 0xff, 0x8c, 0x87,
+0x1f, 0xa3, 0x95, 0x0b, 0xe9, 0xf5, 0xf6, 0xf8,
+0xaa, 0x56, 0xfa, 0x0d, 0x1a, 0x75, 0x3c, 0xd4,
+0x4a, 0x2f, 0x5e, 0xe8, 0x5d, 0x9f, 0x18, 0x0f,
+0x85, 0xb9, 0x89, 0xfb, 0xc6, 0x43, 0x0a, 0x15,
+0xdc, 0xf4, 0xa7, 0x70, 0xf7, 0x3f, 0xcf, 0xf8,
+0x10, 0x5c, 0xc3, 0x79, 0xe0, 0x3b, 0xd7, 0x24,
+0x1d, 0xdf, 0x78, 0x38, 0x16, 0x32, 0x3e, 0x5c,
+0x3a, 0x3a, 0xea, 0xe7, 0xc3, 0xf7, 0xeb, 0x7c,
+0xb8, 0xb7, 0x91, 0x0f, 0x39, 0x7d, 0x31, 0x3e,
+0xdc, 0x78, 0x68, 0x8b, 0x9f, 0x0f, 0xaf, 0xdf,
+0x25, 0x3e, 0xe4, 0x58, 0xf8, 0xdb, 0x54, 0x6d,
+0x61, 0xe0, 0x4f, 0x01, 0x8a, 0x07, 0xbb, 0xde,
+0x65, 0x58, 0x38, 0xf5, 0xd6, 0xc2, 0xea, 0x9a,
+0x6b, 0xfc, 0xed, 0xf9, 0xd9, 0xff, 0xb8, 0x8a,
+0xed, 0xff, 0x12, 0xa0, 0xb8, 0xb0, 0xf1, 0x10,
+0xc3, 0xc2, 0xab, 0xd7, 0x16, 0x36, 0xd6, 0x5c,
+0xd3, 0xd0, 0xbe, 0xd3, 0xe5, 0xc3, 0x4c, 0xe7,
+0xe6, 0x5f, 0xa6, 0x7b, 0x90, 0x0f, 0x33, 0x2f,
+0x6f, 0x3e, 0xc7, 0x09, 0x33, 0xc3, 0x51, 0xb3,
+0x72, 0xed, 0x3f, 0x8c, 0xdf, 0x04, 0x83, 0xb0,
+0xdb, 0x33, 0x4c, 0xc8, 0xc5, 0xef, 0xbc, 0x17,
+0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29,
+0x29, 0x29, 0xa9, 0xff, 0xbb, 0x78, 0xed, 0xa0,
+0xc8, 0xda, 0x41, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0xea, 0xd6, 0xe2,
+0xb5, 0x43, 0x54, 0xd6, 0x0e, 0x52, 0x52, 0x52,
+0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x52, 0x52,
+0xb7, 0x16, 0xaf, 0x1d, 0x54, 0x5e, 0x3b, 0xe0,
+0x5f, 0x91, 0xbe, 0x27, 0x77, 0xd3, 0x81, 0xfe,
+0x97, 0x76, 0x07, 0x74, 0xb6, 0xee, 0x73, 0xf0,
+0x00, 0xcd, 0x58, 0xd0, 0x70, 0x13, 0xda, 0x5d,
+0x94, 0xd2, 0xf4, 0xcc, 0x31, 0x7b, 0x69, 0xdb,
+0x97, 0x85, 0x60, 0xba, 0x87, 0x81, 0x39, 0x36,
+0x7e, 0x0a, 0x03, 0x4e, 0x30, 0xfd, 0x2b, 0xc6,
+0xcc, 0x09, 0x67, 0xe5, 0xc5, 0xd7, 0x5f, 0x09,
+0xa6, 0x7b, 0x30, 0xe7, 0xcc, 0xdf, 0x69, 0x66,
+0xbf, 0x63, 0x3a, 0xc1, 0xf4, 0x9f, 0x78, 0xf8,
+0xe0, 0x11, 0xa7, 0xe3, 0x93, 0xa7, 0xb7, 0x04,
+0xd3, 0x3d, 0xce, 0xbf, 0x18, 0x7f, 0x50, 0xf3,
+0x1f, 0x5f, 0x73, 0xdc, 0x86, 0x47, 0x57, 0x54,
+0x83, 0x9b, 0xff, 0x65, 0x18, 0x3f, 0x5b, 0x20,
+0xa8, 0xf9, 0x6f, 0xce, 0x9e, 0x9e, 0x87, 0x7b,
+0x76, 0x7c, 0xbe, 0x29, 0x98, 0xee, 0x71, 0xfe,
+0xc5, 0xf8, 0x03, 0x8b, 0xff, 0xb5, 0x6d, 0x1f,
+0xd3, 0xa5, 0xcf, 0xcf, 0xa8, 0xb7, 0x6f, 0x7a,
+0x47, 0x32, 0xe7, 0x06, 0x30, 0x7e, 0x0e, 0x05,
+0x17, 0xff, 0x1a, 0xd9, 0x00, 0xab, 0x63, 0xf7,
+0x06, 0x17, 0xff, 0x62, 0xfc, 0x41, 0xcd, 0x7f,
+0x22, 0x6d, 0x0d, 0xc3, 0xba, 0xeb, 0xd9, 0xa0,
+0xe2, 0xc7, 0xac, 0x39, 0x2c, 0x7f, 0x9a, 0xf3,
+0x4e, 0x30, 0xfd, 0x2b, 0xea, 0x81, 0x37, 0x9d,
+0x0d, 0x9f, 0xce, 0x04, 0x96, 0xff, 0xdd, 0xf1,
+0xdf, 0xfc, 0xcb, 0x04, 0x77, 0x47, 0x4a, 0x66,
+0xe6, 0x94, 0x93, 0x59, 0x31, 0x1d, 0x58, 0xfe,
+0xa9, 0xcd, 0xb3, 0xfc, 0x39, 0x1f, 0xd4, 0xfc,
+0x2f, 0xeb, 0xff, 0xf5, 0x9a, 0xd3, 0xfb, 0xe3,
+0xe3, 0x73, 0xc1, 0x74, 0x8f, 0xf3, 0x2f, 0xc6,
+0x1f, 0xd8, 0xfc, 0xf7, 0xbf, 0xf6, 0x8e, 0xfd,
+0xd0, 0x8a, 0x93, 0xb1, 0xdb, 0x37, 0xbd, 0x23,
+0x99, 0xb5, 0x39, 0x96, 0x3f, 0x03, 0x8b, 0xff,
+0x68, 0xe7, 0xa9, 0x67, 0xed, 0xec, 0x57, 0x3f,
+0x59, 0xc1, 0x74, 0x8f, 0xf3, 0x2f, 0xc6, 0x1f,
+0xd8, 0xfc, 0xaf, 0xde, 0xf1, 0x05, 0x18, 0x6d,
+0x6f, 0x07, 0x97, 0x7f, 0x6a, 0x2c, 0x7f, 0x06,
+0x17, 0xff, 0x2b, 0x23, 0x69, 0xda, 0x7f, 0x32,
+0xf1, 0x7d, 0x30, 0xdd, 0xb3, 0x1f, 0x39, 0xe1,
+0xe3, 0x0f, 0x66, 0xfe, 0x4d, 0xf6, 0x7c, 0x1c,
+0xbc, 0xd8, 0x6a, 0x82, 0xcd, 0x9e, 0x5a, 0x09,
+0x9b, 0x40, 0xff, 0xf5, 0xff, 0x13, 0xdc, 0xf7,
+0x46, 0x4c, 0xa8, 0x12, 0xaf, 0xcf, 0x2b, 0x7b,
+0x6e, 0x6c, 0xf7, 0x37, 0xea, 0xe7, 0xba, 0x8f,
+0xf0, 0x33, 0x01, 0x00,
diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c
new file mode 100644
index 0000000..8bd4223
--- /dev/null
+++ b/board/esd/hh405/hh405.c
@@ -0,0 +1,895 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006-2007
+ * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <pci.h>
+#include <sm501.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* FPGA internal regs */
+#define FPGA_CTRL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000))
+#define FPGA_STATUS ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002))
+#define FPGA_CTR ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004))
+#define FPGA_BL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006))
+
+/* FPGA Control Reg */
+#define FPGA_CTRL_REV0 0x0001
+#define FPGA_CTRL_REV1 0x0002
+#define FPGA_CTRL_VGA0_BL 0x0004
+#define FPGA_CTRL_VGA0_BL_MODE 0x0008
+#define FPGA_CTRL_CF_RESET 0x0040
+#define FPGA_CTRL_PS2_PWR 0x0080
+#define FPGA_CTRL_CF_PWRN 0x0100 /* low active */
+#define FPGA_CTRL_CF_BUS_EN 0x0200
+#define FPGA_CTRL_LCD_CLK 0x7000 /* mask for lcd clock */
+#define FPGA_CTRL_OW_ENABLE 0x8000
+
+#define FPGA_STATUS_CF_DETECT 0x8000
+
+#ifdef CONFIG_VIDEO_SM501
+
+#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
+ (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
+
+#ifdef CONFIG_VIDEO_SM501_8BPP
+#error CONFIG_VIDEO_SM501_8BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_8BPP */
+
+#ifdef CONFIG_VIDEO_SM501_16BPP
+#define BPP 16
+
+/*
+ * 800x600 display B084SN03: PCLK = 40MHz
+ * => 2*PCLK = 80MHz
+ * 336/4 = 84MHz
+ * => PCLK = 84MHz
+ */
+static const SMI_REGS init_regs_800x600 [] =
+{
+#if 1 /* test-only */
+ {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
+#else
+ {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
+#endif
+ {0x00004, SWAP32(0x00000000)},
+ /* clocks for pm1... */
+ {0x00048, SWAP32(0x00021807)},
+ {0x0004C, SWAP32(0x221a0a01)},
+ {0x00054, SWAP32(0x00000001)},
+ /* clocks for pm0... */
+ {0x00040, SWAP32(0x00021807)},
+ {0x00044, SWAP32(0x221a0a01)},
+ {0x00054, SWAP32(0x00000000)},
+ /* GPIO */
+ {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
+ /* panel control regs... */
+ {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
+ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+ {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
+ {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
+ {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
+ {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
+ {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+ {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
+ {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
+ {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
+ {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
+ {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
+ {0x80200, SWAP32(0x00010000)}, /* crt display control */
+ {0, 0}
+};
+
+/*
+ * 1024x768 display G150XG02: PCLK = 65MHz
+ * => 2*PCLK = 130MHz
+ * 288/2 = 144MHz
+ * => PCLK = 72MHz
+ */
+static const SMI_REGS init_regs_1024x768 [] =
+{
+ {0x00004, SWAP32(0x00000000)},
+ /* clocks for pm1... */
+ {0x00048, SWAP32(0x00021807)},
+ {0x0004C, SWAP32(0x011a0a01)},
+ {0x00054, SWAP32(0x00000001)},
+ /* clocks for pm0... */
+ {0x00040, SWAP32(0x00021807)},
+ {0x00044, SWAP32(0x011a0a01)},
+ {0x00054, SWAP32(0x00000000)},
+ /* GPIO */
+ {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
+ /* panel control regs... */
+ {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
+ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+ {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
+ {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
+ {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
+ {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
+ {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+ {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
+ {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
+ {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
+ {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
+ {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
+ {0x80200, SWAP32(0x00010000)}, /* crt display control */
+ {0, 0}
+};
+
+#endif /* CONFIG_VIDEO_SM501_16BPP */
+
+#ifdef CONFIG_VIDEO_SM501_32BPP
+#define BPP 32
+
+/*
+ * 800x600 display B084SN03: PCLK = 40MHz
+ * => 2*PCLK = 80MHz
+ * 336/4 = 84MHz
+ * => PCLK = 84MHz
+ */
+static const SMI_REGS init_regs_800x600 [] =
+{
+#if 0 /* test-only */
+ {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
+#else
+ {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
+#endif
+ {0x00004, SWAP32(0x00000000)},
+ /* clocks for pm1... */
+ {0x00048, SWAP32(0x00021807)},
+ {0x0004C, SWAP32(0x221a0a01)},
+ {0x00054, SWAP32(0x00000001)},
+ /* clocks for pm0... */
+ {0x00040, SWAP32(0x00021807)},
+ {0x00044, SWAP32(0x221a0a01)},
+ {0x00054, SWAP32(0x00000000)},
+ /* GPIO */
+ {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
+ /* panel control regs... */
+ {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
+ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+ {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
+ {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
+ {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
+ {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
+ {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+ {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
+ {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
+ {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
+ {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
+ {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
+ {0x80200, SWAP32(0x00010000)}, /* crt display control */
+ {0, 0}
+};
+
+/*
+ * 1024x768 display G150XG02: PCLK = 65MHz
+ * => 2*PCLK = 130MHz
+ * 288/2 = 144MHz
+ * => PCLK = 72MHz
+ */
+static const SMI_REGS init_regs_1024x768 [] =
+{
+ {0x00004, SWAP32(0x00000000)},
+ /* clocks for pm1... */
+ {0x00048, SWAP32(0x00021807)},
+ {0x0004C, SWAP32(0x011a0a01)},
+ {0x00054, SWAP32(0x00000001)},
+ /* clocks for pm0... */
+ {0x00040, SWAP32(0x00021807)},
+ {0x00044, SWAP32(0x011a0a01)},
+ {0x00054, SWAP32(0x00000000)},
+ /* GPIO */
+ {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
+ /* panel control regs... */
+ {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
+ {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+ {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
+ {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
+ {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
+ {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
+ {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+ {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
+ {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
+ {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
+ {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
+ {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
+ {0x80200, SWAP32(0x00010000)}, /* crt display control */
+ {0, 0}
+};
+
+#endif /* CONFIG_VIDEO_SM501_32BPP */
+
+#endif /* CONFIG_VIDEO_SM501 */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp_320[] =
+{
+#include "logo_320_240_4bpp.c"
+};
+
+unsigned char logo_bmp_320_8bpp[] =
+{
+#include "logo_320_240_8bpp.c"
+};
+
+unsigned char logo_bmp_640[] =
+{
+#include "logo_640_480_24bpp.c"
+};
+
+unsigned char logo_bmp_1024[] =
+{
+#include "logo_1024_768_8bpp.c"
+};
+
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+
+#include "../common/s1d13704_320_240_4bpp.h"
+#include "../common/s1d13705_320_240_8bpp.h"
+#include "../common/s1d13806_640_480_16bpp.h"
+#include "../common/s1d13806_1024_768_8bpp.h"
+
+
+/*
+ * include common auto-update code (for esd boards)
+ */
+#include "../common/auto_update.h"
+
+au_image_t au_image[] = {
+ {"hh405/preinst.img", 0, -1, AU_SCRIPT},
+ {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
+ {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
+ {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
+ {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
+ {"hh405/postinst.img", 0, 0, AU_SCRIPT},
+};
+
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+
+
+/*
+ * Get version of HH405 board from GPIO's
+ */
+int board_revision(void)
+{
+ unsigned long osrh_reg;
+ unsigned long isr1h_reg;
+ unsigned long tcr_reg;
+ unsigned long value;
+
+ /*
+ * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
+ */
+ osrh_reg = in_be32((void *)GPIO0_OSRH);
+ isr1h_reg = in_be32((void *)GPIO0_ISR1H);
+ tcr_reg = in_be32((void *)GPIO0_TCR);
+ out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */
+ out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */
+ out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */
+
+ udelay(1000); /* wait some time before reading input */
+ value = in_be32((void *)GPIO0_IR) & 0x80400000; /* get config bits */
+
+ /*
+ * Restore GPIO settings
+ */
+ out_be32((void *)GPIO0_OSRH, osrh_reg); /* output select */
+ out_be32((void *)GPIO0_ISR1H, isr1h_reg); /* input select */
+ out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
+
+ if (value & 0x80000000) {
+ /* Revision 1.0 or 1.1 detected */
+ return 1;
+ } else {
+ if (value & 0x00400000) {
+ /* unused */
+ return 3;
+ } else {
+ return 2;
+ }
+ }
+}
+
+
+int board_early_init_f (void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ */
+ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ return 0;
+}
+
+int cf_enable(void)
+{
+ int i;
+
+ if (gd->board_type >= 2) {
+ if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) {
+ if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) {
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN);
+
+ for (i=0; i<300; i++)
+ udelay(1000);
+
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN);
+
+ for (i=0; i<20; i++)
+ udelay(1000);
+ }
+ } else {
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN);
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN);
+ }
+ }
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ unsigned char *dst;
+ ulong len = sizeof(fpgadata);
+ int status;
+ int index;
+ int i;
+ char *str;
+ unsigned long contrast0 = 0xffffffff;
+
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ printf ("GUNZIP ERROR - must RESET board to recover\n");
+ do_reset (NULL, 0, 0, NULL);
+ }
+
+ status = fpga_boot(dst, len);
+ if (status != 0) {
+ printf("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf("(Timeout: DONE not high after programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("FPGA: %s\n", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+ /* delayed reboot */
+ for (i=20; i>0; i--) {
+ printf("Rebooting in %2d seconds \r",i);
+ for (index=0;index<1000;index++)
+ udelay(1000);
+ }
+ putc ('\n');
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ puts("FPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("%s ", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+
+ free(dst);
+
+ /*
+ * Reset FPGA via FPGA_INIT pin
+ */
+ /* setup FPGA_INIT as output */
+ out_be32((void *)GPIO0_TCR,
+ in_be32((void *)GPIO0_TCR) | FPGA_INIT);
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~FPGA_INIT); /* reset low */
+ udelay(1000); /* wait 1ms */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | FPGA_INIT); /* reset high */
+ udelay(1000); /* wait 1ms */
+
+ /*
+ * Write Board revision into FPGA
+ */
+ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003));
+
+ /*
+ * Setup and enable EEPROM write protection
+ */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+
+ /*
+ * Reset touch-screen controller
+ */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
+ udelay(1000);
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
+
+ /*
+ * Enable power on PS/2 interface (with reset)
+ */
+ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR);
+ for (i=0;i<500;i++)
+ udelay(1000);
+ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR);
+
+ /*
+ * Get contrast value from environment variable
+ */
+ str = getenv("contrast0");
+ if (str) {
+ contrast0 = simple_strtol(str, NULL, 16);
+ if (contrast0 > 255) {
+ printf("ERROR: contrast0 value too high (0x%lx)!\n",
+ contrast0);
+ contrast0 = 0xffffffff;
+ }
+ }
+
+ /*
+ * Init lcd interface and display logo
+ */
+
+ str = getenv("bd_type");
+ if (strcmp(str, "ppc230") == 0) {
+ /*
+ * Switch backlight on
+ */
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL);
+ out_be16(FPGA_BL, 0x0000);
+
+ lcd_setup(1, 0);
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+ regs_13806_1024_768_8bpp,
+ sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
+ logo_bmp_1024, sizeof(logo_bmp_1024));
+ } else if (strcmp(str, "ppc220") == 0) {
+ /*
+ * Switch backlight on
+ */
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL);
+ out_be16(FPGA_BL, 0x0000);
+
+ lcd_setup(1, 0);
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+ regs_13806_640_480_16bpp,
+ sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
+ logo_bmp_640, sizeof(logo_bmp_640));
+ } else if (strcmp(str, "ppc215") == 0) {
+ /*
+ * Set default display contrast voltage
+ */
+ if (contrast0 == 0xffffffff) {
+ out_be16(FPGA_CTR, 0x0082);
+ } else {
+ out_be16(FPGA_CTR, contrast0);
+ }
+ out_be16(FPGA_BL, 0xffff);
+ /*
+ * Switch backlight on
+ */
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) |
+ FPGA_CTRL_VGA0_BL |
+ FPGA_CTRL_VGA0_BL_MODE);
+ /*
+ * Set lcd clock (small epson)
+ */
+ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250);
+ udelay(100); /* wait for 100 us */
+
+ lcd_setup(0, 1);
+ lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+ regs_13705_320_240_8bpp,
+ sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
+ logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
+ } else if (strcmp(str, "ppc210") == 0) {
+ /*
+ * Set default display contrast voltage
+ */
+ if (contrast0 == 0xffffffff) {
+ out_be16(FPGA_CTR, 0x0060);
+ } else {
+ out_be16(FPGA_CTR, contrast0);
+ }
+ out_be16(FPGA_BL, 0xffff);
+ /*
+ * Switch backlight on
+ */
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) |
+ FPGA_CTRL_VGA0_BL |
+ FPGA_CTRL_VGA0_BL_MODE);
+ /*
+ * Set lcd clock (small epson), enable 1-wire interface
+ */
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) |
+ LCD_CLK_08330 |
+ FPGA_CTRL_OW_ENABLE);
+
+ lcd_setup(0, 1);
+ lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+ regs_13704_320_240_4bpp,
+ sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+ logo_bmp_320, sizeof(logo_bmp_320));
+#ifdef CONFIG_VIDEO_SM501
+ } else {
+ pci_dev_t devbusfn;
+
+ /*
+ * Is SM501 connected (ppc221/ppc231)?
+ */
+ devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+ if (devbusfn != -1) {
+ puts("VGA: SM501 with 8 MB ");
+ if (strcmp(str, "ppc221") == 0) {
+ printf("(800*600, %dbpp)\n", BPP);
+ out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */
+ } else if (strcmp(str, "ppc231") == 0) {
+ printf("(1024*768, %dbpp)\n", BPP);
+ out_be16(FPGA_BL, 0x0000);
+ } else {
+ printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+ return 0;
+ }
+ } else {
+ printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+ return 0;
+ }
+#endif /* CONFIG_VIDEO_SM501 */
+ }
+
+ cf_enable();
+
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming HH405");
+ } else {
+ puts(str);
+ }
+
+ if (getenv_f("bd_type", str, sizeof(str)) != -1) {
+ printf(" (%s", str);
+ } else {
+ puts(" (Missing bd_type!");
+ }
+
+ gd->board_type = board_revision();
+ printf(", Rev %ld.x)\n", gd->board_type);
+
+ return 0;
+}
+
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+ if (((gd->board_type >= 2) &&
+ (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) ||
+ (gd->board_type < 2)) {
+ /*
+ * Assert or deassert CompactFlash Reset Pin
+ */
+ if (on) { /* assert RESET */
+ cf_enable();
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) &
+ ~FPGA_CTRL_CF_RESET);
+ } else { /* release RESET */
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) |
+ FPGA_CTRL_CF_RESET);
+ }
+ }
+}
+#endif /* CONFIG_IDE_RESET */
+
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO_SINT2. */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO_SINT2. */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void *)GPIO0_OR) &
+ CONFIG_SYS_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts ("Query of write access state failed.\n");
+ } else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0) {
+ puts ("Setup of write access state failed.\n");
+ }
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "Enable / disable / query EEPROM write access",
+ ""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+
+#ifdef CONFIG_VIDEO_SM501
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+ char str[64];
+ char str2[64];
+ int i = getenv_f("serial#", str2, sizeof(str));
+
+ if (line_number == 1) {
+ sprintf(str, " Board: ");
+
+ if (i == -1) {
+ strcat(str, "### No HW ID - assuming HH405");
+ } else {
+ strcat(str, str2);
+ }
+
+ if (getenv_f("bd_type", str2, sizeof(str2)) != -1) {
+ strcat(str, " (");
+ strcat(str, str2);
+ } else {
+ strcat(str, " (Missing bd_type!");
+ }
+
+ sprintf(str2, ", Rev %ld.x)", gd->board_type);
+ strcat(str, str2);
+ strcpy(info, str);
+ } else {
+ info [0] = '\0';
+ }
+}
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
+
+/*
+ * Returns SM501 register base address. First thing called in the driver.
+ */
+unsigned int board_video_init (void)
+{
+ pci_dev_t devbusfn;
+ u32 addr;
+
+ /*
+ * Is SM501 connected (ppc221/ppc231)?
+ */
+ devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+ if (devbusfn != -1) {
+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
+ return (addr & 0xfffffffe);
+ }
+
+ return 0;
+}
+
+/*
+ * Returns SM501 framebuffer address
+ */
+unsigned int board_video_get_fb (void)
+{
+ pci_dev_t devbusfn;
+ u32 addr;
+
+ /*
+ * Is SM501 connected (ppc221/ppc231)?
+ */
+ devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+ if (devbusfn != -1) {
+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
+ addr &= 0xfffffffe;
+#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
+ addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
+#endif
+ return addr;
+ }
+
+ return 0;
+}
+
+/*
+ * Called after initializing the SM501 and before clearing the screen.
+ */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/*
+ * Return a pointer to the initialization sequence.
+ */
+const SMI_REGS *board_get_regs (void)
+{
+ char *str;
+
+ str = getenv("bd_type");
+ if (strcmp(str, "ppc221") == 0) {
+ return init_regs_800x600;
+ } else {
+ return init_regs_1024x768;
+ }
+}
+
+int board_get_width (void)
+{
+ char *str;
+
+ str = getenv("bd_type");
+ if (strcmp(str, "ppc221") == 0) {
+ return 800;
+ } else {
+ return 1024;
+ }
+}
+
+int board_get_height (void)
+{
+ char *str;
+
+ str = getenv("bd_type");
+ if (strcmp(str, "ppc221") == 0) {
+ return 600;
+ } else {
+ return 768;
+ }
+}
+
+#endif /* CONFIG_VIDEO_SM501 */
+
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
diff --git a/board/esd/hh405/logo_1024_768_8bpp.c b/board/esd/hh405/logo_1024_768_8bpp.c
new file mode 100644
index 0000000..331540f
--- /dev/null
+++ b/board/esd/hh405/logo_1024_768_8bpp.c
@@ -0,0 +1,5087 @@
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diff --git a/board/esd/hh405/logo_320_240_4bpp.c b/board/esd/hh405/logo_320_240_4bpp.c
new file mode 100644
index 0000000..52989de
--- /dev/null
+++ b/board/esd/hh405/logo_320_240_4bpp.c
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diff --git a/board/esd/hh405/logo_320_240_8bpp.c b/board/esd/hh405/logo_320_240_8bpp.c
new file mode 100644
index 0000000..7500448
--- /dev/null
+++ b/board/esd/hh405/logo_320_240_8bpp.c
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diff --git a/board/esd/hh405/logo_640_480_24bpp.c b/board/esd/hh405/logo_640_480_24bpp.c
new file mode 100644
index 0000000..3f8bb9e
--- /dev/null
+++ b/board/esd/hh405/logo_640_480_24bpp.c
@@ -0,0 +1,8417 @@
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+0x76, 0x7f, 0x7d, 0xb3, 0xfd, 0xf2, 0x7d, 0x7b,
+0xfb, 0xf3, 0x7e, 0x7d, 0xb7, 0x4d, 0xb6, 0xfe,
+0x73, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x6b, 0xbf,
+0x00, 0xff, 0xcf, 0xfd, 0x4c, 0x36, 0x10, 0x0e,
+0x00,
diff --git a/board/esd/hub405/Kconfig b/board/esd/hub405/Kconfig
new file mode 100644
index 0000000..2b9556a
--- /dev/null
+++ b/board/esd/hub405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_HUB405
+
+config SYS_BOARD
+ default "hub405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "HUB405"
+
+endif
diff --git a/board/esd/hub405/MAINTAINERS b/board/esd/hub405/MAINTAINERS
new file mode 100644
index 0000000..e84a1d9
--- /dev/null
+++ b/board/esd/hub405/MAINTAINERS
@@ -0,0 +1,6 @@
+HUB405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/hub405/
+F: include/configs/HUB405.h
+F: configs/HUB405_defconfig
diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile
new file mode 100644
index 0000000..99e18b5
--- /dev/null
+++ b/board/esd/hub405/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = hub405.o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c
new file mode 100644
index 0000000..23e8164
--- /dev/null
+++ b/board/esd/hub405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b0 = -size_b0;
+ switch (size_b0) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c
new file mode 100644
index 0000000..1423744
--- /dev/null
+++ b/board/esd/hub405/hub405.c
@@ -0,0 +1,208 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+int board_revision(void)
+{
+ unsigned long osrl_reg;
+ unsigned long isr1l_reg;
+ unsigned long tcr_reg;
+ unsigned long value;
+
+ /*
+ * Get version of HUB405 board from GPIO's
+ */
+
+ /*
+ * Setup GPIO pin(s) (IRQ6/GPIO23)
+ */
+ osrl_reg = in_be32((void *)GPIO0_OSRH);
+ isr1l_reg = in_be32((void *)GPIO0_ISR1H);
+ tcr_reg = in_be32((void *)GPIO0_TCR);
+ out_be32((void *)GPIO0_OSRH, osrl_reg & ~0x00030000); /* output select */
+ out_be32((void *)GPIO0_ISR1H, isr1l_reg | 0x00030000); /* input select */
+ out_be32((void *)GPIO0_TCR, tcr_reg & ~0x00000100); /* select input */
+
+ udelay(1000); /* wait some time before reading input */
+ value = in_be32((void *)GPIO0_IR) & 0x00000100; /* get config bits */
+
+ /*
+ * Restore GPIO settings
+ */
+ out_be32((void *)GPIO0_OSRH, osrl_reg); /* output select */
+ out_be32((void *)GPIO0_ISR1H, isr1l_reg); /* input select */
+ out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
+
+ if (value & 0x00000100) {
+ /* Revision 1.1 or 1.2 detected */
+ return 1;
+ }
+
+ /* Revision 1.0 */
+ return 0;
+}
+
+
+int board_early_init_f (void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ */
+ mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ return 0;
+}
+
+#define LED_REG (DUART0_BA + 0x20)
+int misc_init_r (void)
+{
+ unsigned long val;
+ int delay, flashcnt;
+ char *str;
+ char hw_rev[4];
+
+ /*
+ * Enable interrupts in exar duart mcr[3]
+ */
+ out_8((void *)(DUART0_BA + 4), 0x08);
+ out_8((void *)(DUART1_BA + 4), 0x08);
+ out_8((void *)(DUART2_BA + 4), 0x08);
+ out_8((void *)(DUART3_BA + 4), 0x08);
+
+ /*
+ * Set RS232/RS422 control (RS232 = high on GPIO)
+ */
+ val = in_be32((void *)GPIO0_OR);
+ val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 |
+ CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232);
+
+ str = getenv("phys0");
+ if (!str || (str && (str[0] == '0')))
+ val |= CONFIG_SYS_UART2_RS232;
+
+ str = getenv("phys1");
+ if (!str || (str && (str[0] == '0')))
+ val |= CONFIG_SYS_UART3_RS232;
+
+ str = getenv("phys2");
+ if (!str || (str && (str[0] == '0')))
+ val |= CONFIG_SYS_UART4_RS232;
+
+ str = getenv("phys3");
+ if (!str || (str && (str[0] == '0')))
+ val |= CONFIG_SYS_UART5_RS232;
+
+ out_be32((void *)GPIO0_OR, val);
+
+ /*
+ * check board type and setup AP power
+ */
+ str = getenv("bd_type"); /* this is only set on non prototype hardware */
+ if (str != NULL) {
+ if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) {
+ unsigned char led_reg_default = 0;
+ str = getenv("ap_pwr");
+ if (!str || (str && (str[0] == '1')))
+ led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */
+
+ /*
+ * Flash LEDs
+ */
+ for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+ /* LED_A..D off */
+ out_8((void *)LED_REG, led_reg_default);
+ for (delay = 0; delay < 100; delay++)
+ udelay(1000);
+ /* LED_A..D on */
+ out_8((void *)LED_REG, led_reg_default | 0xf0);
+ for (delay = 0; delay < 50; delay++)
+ udelay(1000);
+ }
+ out_8((void *)LED_REG, led_reg_default);
+ }
+ }
+
+ /*
+ * Reset external DUARTs
+ */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
+ udelay(10); /* wait 10us */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
+ udelay(1000); /* wait 1ms */
+
+ /*
+ * Store hardware revision in environment for further processing
+ */
+ sprintf(hw_rev, "1.%ld", gd->board_type);
+ setenv("hw_rev", hw_rev);
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming HUB405");
+ } else {
+ puts(str);
+ }
+
+ if (getenv_f("bd_type", str, sizeof(str)) != -1) {
+ printf(" (%s", str);
+ } else {
+ puts(" (Missing bd_type!");
+ }
+
+ gd->board_type = board_revision();
+ printf(", Rev 1.%ld)\n", gd->board_type);
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+
+ return 0;
+}
diff --git a/board/esd/mecp5123/Kconfig b/board/esd/mecp5123/Kconfig
new file mode 100644
index 0000000..3f2a411
--- /dev/null
+++ b/board/esd/mecp5123/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MECP5123
+
+config SYS_BOARD
+ default "mecp5123"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "mecp5123"
+
+endif
diff --git a/board/esd/mecp5123/MAINTAINERS b/board/esd/mecp5123/MAINTAINERS
new file mode 100644
index 0000000..ae5fcea
--- /dev/null
+++ b/board/esd/mecp5123/MAINTAINERS
@@ -0,0 +1,6 @@
+MECP5123 BOARD
+M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+S: Maintained
+F: board/esd/mecp5123/
+F: include/configs/mecp5123.h
+F: configs/mecp5123_defconfig
diff --git a/board/esd/mecp5123/Makefile b/board/esd/mecp5123/Makefile
new file mode 100644
index 0000000..f5ebb01
--- /dev/null
+++ b/board/esd/mecp5123/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mecp5123.o
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
new file mode 100644
index 0000000..cda1d7b
--- /dev/null
+++ b/board/esd/mecp5123/mecp5123.c
@@ -0,0 +1,208 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
+ return -1;
+
+ if (state == 0)
+ setbits_be32(&im->gpio.gpdat, 0x00100000);
+ else
+ clrbits_be32(&im->gpio.gpdat, 0x00100000);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ int i;
+
+ /*
+ * Initialize Local Window for boot access
+ */
+ out_be32(&im->sysconf.lpbaw,
+ CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
+ sync_law(&im->sysconf.lpbaw);
+
+ /*
+ * Configure MSCAN clocks
+ */
+ for (i=0; i<4; ++i) {
+ out_be32(&im->clk.msccr[i], 0x00300000);
+ out_be32(&im->clk.msccr[i], 0x00310000);
+ }
+
+ /*
+ * Configure GPIO's
+ */
+ clrbits_be32(&im->gpio.gpodr, 0x000000e0);
+ clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
+ setbits_be32(&im->gpio.gpdir, 0x001000e0);
+ setbits_be32(&im->gpio.gpdat, 0x00100000);
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
+}
+
+int misc_init_r(void)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 val;
+
+ /*
+ * Optimize access to profibus chip (VPC3) on the local bus
+ */
+
+ /*
+ * Select 1:1 for LPC_DIV
+ */
+ val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
+ out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
+
+ /*
+ * Configure LPC Chips Select Deadcycle Control Register
+ * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
+ * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
+ */
+ clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
+ setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
+
+ /*
+ * Configure LPC Chips Select Holdcycle Control Register
+ * CS0 - data is valid 2 clock cycle(s) after CS deassertion
+ * CS1 - data is valid 1 clock cycle(s) after CS deassertion
+ */
+ clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
+ setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
+
+ return 0;
+}
+
+static iopin_t ioregs_init[] = {
+ /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+ {
+ offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+ {
+ offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=SELECT LPC_CS1 */
+ {
+ offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC5_2 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC5_3 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC7_3 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC9_0 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC10_0 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC10_3 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC11_0 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC0=SELECT IRQ0 */
+ {
+ offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ }
+};
+
+static iopin_t rev2_silicon_pci_ioregs_init[] = {
+ /* FUNC0=PCI Sets next 54 to PCI pads */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
+ }
+};
+
+int checkboard(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 spridr;
+
+ puts("Board: MECP_5123\n");
+
+ /*
+ * Initialize function mux & slew rate IO inter alia on IO
+ * Pins
+ */
+ iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+ spridr = in_be32(&im->sysconf.spridr);
+ if (SVR_MJREV(spridr) >= 2)
+ iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/esd/mecp5200/Kconfig b/board/esd/mecp5200/Kconfig
new file mode 100644
index 0000000..cfd5307
--- /dev/null
+++ b/board/esd/mecp5200/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MECP5200
+
+config SYS_BOARD
+ default "mecp5200"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "mecp5200"
+
+endif
diff --git a/board/esd/mecp5200/MAINTAINERS b/board/esd/mecp5200/MAINTAINERS
new file mode 100644
index 0000000..05b7824
--- /dev/null
+++ b/board/esd/mecp5200/MAINTAINERS
@@ -0,0 +1,6 @@
+MECP5200 BOARD
+M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+S: Maintained
+F: board/esd/mecp5200/
+F: include/configs/mecp5200.h
+F: configs/mecp5200_defconfig
diff --git a/board/esd/mecp5200/Makefile b/board/esd/mecp5200/Makefile
new file mode 100644
index 0000000..3d66c9f
--- /dev/null
+++ b/board/esd/mecp5200/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = mecp5200.o
diff --git a/board/esd/mecp5200/mecp5200.c b/board/esd/mecp5200/mecp5200.c
new file mode 100644
index 0000000..17a70a9
--- /dev/null
+++ b/board/esd/mecp5200/mecp5200.c
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * pf5200.c - main board support/init for the esd pf5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+#include <netdev.h>
+
+#include "mt46v16m16-75.h"
+
+void init_power_switch(void);
+
+static void sdram_start(int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register: extended mode */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+ /* set tap delay */
+ *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
+
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+ 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
+ } else {
+#if 0
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
+#else
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+ 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
+#endif
+ }
+
+#if 0
+ /* find RAM size using SDRAM CS1 only */
+ sdram_start(0);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ sdram_start(1);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ sdram_start(0);
+#endif
+ /* set SDRAM CS1 size according to the amount of RAM found */
+
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+
+ init_power_switch();
+ return (dramsize);
+}
+
+int checkboard(void)
+{
+ puts("Board: esd CPX CPU5200 (mecp5200)\n");
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+ if (size == CONFIG_SYS_FLASH_SIZE) {
+ /* adjust mapping */
+ *(vu_long *) MPC5XXX_BOOTCS_START =
+ *(vu_long *) MPC5XXX_CS0_START =
+ START_REG(CONFIG_SYS_BOOTCS_START | size);
+ *(vu_long *) MPC5XXX_BOOTCS_STOP =
+ *(vu_long *) MPC5XXX_CS0_STOP =
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+ }
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4 0x01000000UL
+
+void init_ide_reset(void)
+{
+ debug("init_ide_reset\n");
+
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+ debug("ide_reset(%d)\n", idereset);
+
+ if (idereset)
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+ else
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+}
+#endif
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6 0x40000000UL
+#define GPIO_USB0 0x00010000UL
+#define GPIO_USB9 0x08000000UL
+#define GPIO_USB9S 0x00080000UL
+
+void init_power_switch(void)
+{
+ debug("init_power_switch\n");
+
+ /* Configure GPIO_WU6 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+ __asm__ volatile ("sync");
+
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+ __asm__ volatile ("sync");
+
+ *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+ *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+ __asm__ volatile ("sync");
+
+ if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+ __asm__ volatile ("sync");
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
diff --git a/board/esd/mecp5200/mt46v16m16-75.h b/board/esd/mecp5200/mt46v16m16-75.h
new file mode 100644
index 0000000..63a4032
--- /dev/null
+++ b/board/esd/mecp5200/mt46v16m16-75.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x705f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/esd/meesc/Kconfig b/board/esd/meesc/Kconfig
new file mode 100644
index 0000000..5041041
--- /dev/null
+++ b/board/esd/meesc/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MEESC
+
+config SYS_BOARD
+ default "meesc"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "meesc"
+
+endif
diff --git a/board/esd/meesc/MAINTAINERS b/board/esd/meesc/MAINTAINERS
new file mode 100644
index 0000000..9403699
--- /dev/null
+++ b/board/esd/meesc/MAINTAINERS
@@ -0,0 +1,7 @@
+MEESC BOARD
+M: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+S: Maintained
+F: board/esd/meesc/
+F: include/configs/meesc.h
+F: configs/meesc_defconfig
+F: configs/meesc_dataflash_defconfig
diff --git a/board/esd/meesc/Makefile b/board/esd/meesc/Makefile
new file mode 100644
index 0000000..5d16738
--- /dev/null
+++ b/board/esd/meesc/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += meesc.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
new file mode 100644
index 0000000..c5994e0
--- /dev/null
+++ b/board/esd/meesc/meesc.c
@@ -0,0 +1,271 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2009-2011
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static int hw_rev = -1; /* hardware revision */
+
+int get_hw_rev(void)
+{
+ if (hw_rev >= 0)
+ return hw_rev;
+
+ hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
+ hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
+ hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
+ hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
+
+ if (hw_rev == 15)
+ hw_rev = 0;
+
+ return hw_rev;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void meesc_nand_hw_init(void)
+{
+ unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
+ at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa[0]);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(12),
+ &smc->cs[3].mode);
+
+ /* Configure RDY/BSY */
+ gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+ /* Enable NandFlash */
+ gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif /* CONFIG_CMD_NAND */
+
+#ifdef CONFIG_MACB
+static void meesc_macb_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ /* Enable clock */
+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+ at91_macb_hw_init();
+}
+#endif
+
+/*
+ * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
+ * controller debugging
+ * The ET1100 is located at physical address 0x70000000
+ * Its process memory is located at physical address 0x70001000
+ */
+static void meesc_ethercat_hw_init(void)
+{
+ at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
+
+ /* Configure SMC EBI1_CS0 for EtherCAT */
+ writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc1->cs[0].setup);
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
+ AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
+ &smc1->cs[0].pulse);
+ writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
+ &smc1->cs[0].cycle);
+ /*
+ * Configure behavior at external wait signal, byte-select mode, 16 bit
+ * data bus width, none data float wait states and TDF optimization
+ */
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
+ AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
+ AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
+
+ /* Configure RDY/BSY */
+ at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
+
+int checkboard(void)
+{
+ char str[32];
+ u_char hw_type; /* hardware type */
+
+ /* read the "Type" register of the ET1100 controller */
+ hw_type = readb(CONFIG_ET1100_BASE);
+
+ switch (hw_type) {
+ case 0x11:
+ case 0x3F:
+ /* ET1100 present, arch number of MEESC-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_MEESC;
+ puts("Board: CAN-EtherCAT Gateway");
+ break;
+ case 0xFF:
+ /* no ET1100 present, arch number of EtherCAN/2-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
+ puts("Board: EtherCAN/2 Gateway");
+ /* switch on LED1D */
+ at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
+ break;
+ default:
+ /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
+ printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
+ puts("Board: EtherCAN/2 Gateway");
+ break;
+ }
+ if (getenv_f("serial#", str, sizeof(str)) > 0) {
+ puts(", serial# ");
+ puts(str);
+ }
+ printf("\nHardware-revision: 1.%d\n", get_hw_rev());
+ printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *str;
+
+ char *serial = getenv("serial#");
+ if (serial) {
+ str = strchr(serial, '_');
+ if (str && (strlen(str) >= 4)) {
+ serialnr->high = (*(str + 1) << 8) | *(str + 2);
+ serialnr->low = simple_strtoul(str + 3, NULL, 16);
+ }
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+ return hw_rev | 0x100;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ char *str;
+ char buf[32];
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ /*
+ * Normally the processor clock has a divisor of 2.
+ * In some cases this this needs to be set to 4.
+ * Check the user has set environment mdiv to 4 to change the divisor.
+ */
+ if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) {
+ writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
+ AT91SAM9_PMC_MDIV_4, &pmc->mckr);
+ at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+ serial_setbrg();
+ /* Notify the user that the clock is not default */
+ printf("Setting master clock to %s MHz\n",
+ strmhz(buf, get_mck_clk_rate()));
+ }
+
+ return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+int board_early_init_f(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ /* enable all clocks */
+ writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP),
+ &pmc->pcer);
+
+ at91_seriald_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* initialize ET1100 Controller */
+ meesc_ethercat_hw_init();
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ meesc_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+ meesc_macb_hw_init();
+#endif
+#ifdef CONFIG_AT91_CAN
+ at91_can_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+ at91_uhp_hw_init();
+#endif
+ return 0;
+}
diff --git a/board/esd/meesc/partition.c b/board/esd/meesc/partition.c
new file mode 100644
index 0000000..b6afafc
--- /dev/null
+++ b/board/esd/meesc/partition.c
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+};
+
+/* define the area offsets */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+};
diff --git a/board/esd/ocrtc/Kconfig b/board/esd/ocrtc/Kconfig
new file mode 100644
index 0000000..44b402d
--- /dev/null
+++ b/board/esd/ocrtc/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OCRTC
+
+config SYS_BOARD
+ default "ocrtc"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "OCRTC"
+
+endif
diff --git a/board/esd/ocrtc/MAINTAINERS b/board/esd/ocrtc/MAINTAINERS
new file mode 100644
index 0000000..85c1a12
--- /dev/null
+++ b/board/esd/ocrtc/MAINTAINERS
@@ -0,0 +1,6 @@
+OCRTC BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/ocrtc/
+F: include/configs/OCRTC.h
+F: configs/OCRTC_defconfig
diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile
new file mode 100644
index 0000000..44b7d5d
--- /dev/null
+++ b/board/esd/ocrtc/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ocrtc.o flash.o ../common/misc.o cmd_ocrtc.o
diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c
new file mode 100644
index 0000000..6dcbd8b
--- /dev/null
+++ b/board/esd/ocrtc/cmd_ocrtc.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <asm/4xx_pci.h>
+
+
+#if defined(CONFIG_CMD_BSP)
+
+/*
+ * Set device number on pci board
+ */
+int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int idx = 1; /* start at 1 (skip device 0) */
+ pci_dev_t bdf = 0;
+ u32 addr;
+
+ while (bdf >= 0) {
+ if ((bdf = pci_find_device(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_405GP, idx++)) < 0) {
+ break;
+ }
+ printf("Found device nr %d at %x!\n", idx-1, bdf);
+ pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr);
+ addr &= ~0xf;
+ *(u32 *)addr = (bdf & 0x0000f800) >> 11;
+ printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr);
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ setdevice, 1, 1, do_setdevice,
+ "Set device number on pci adapter boards",
+ ""
+);
+
+
+/*
+ * Get device number on pci board
+ */
+int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 device;
+ char str[32];
+
+ device = *(u32 *)0x0;
+ device = 0x16 - device; /* calculate vxworks bp slot id */
+ sprintf(str, "%d", device);
+ setenv("slot", str);
+ printf("Variabel slot set to %x\n", device);
+
+ return 0;
+}
+U_BOOT_CMD(
+ getdevice, 1, 1, do_getdevice,
+ "Get device number and set slot env variable",
+ ""
+);
+
+#endif
diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c
new file mode 100644
index 0000000..279746e
--- /dev/null
+++ b/board/esd/ocrtc/flash.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+ uint pbcr;
+ unsigned long base_b0, base_b1;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ base_b0 = FLASH_BASE0_PRELIM;
+ size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ base_b1 = FLASH_BASE1_PRELIM;
+ size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+ /* Re-do sizing to get full correct info */
+
+ if (size_b1) {
+ mtdcr (EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr (EBC0_CFGDATA);
+ mtdcr (EBC0_CFGADDR, PB0CR);
+ base_b1 = -size_b1;
+ switch (size_b1) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17);
+ mtdcr (EBC0_CFGDATA, pbcr);
+ /* printf("PB1CR = %x\n", pbcr); */
+ }
+
+ if (size_b0) {
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ pbcr = mfdcr (EBC0_CFGDATA);
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ base_b0 = base_b1 - size_b0;
+ switch (size_b1) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr (EBC0_CFGDATA, pbcr);
+ /* printf("PB0CR = %x\n", pbcr); */
+ }
+
+ size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+ flash_get_offsets (base_b0, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ base_b0 + size_b0 - monitor_flash_len,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+
+ if (size_b1) {
+ /* Re-do sizing to get full correct info */
+ size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+ flash_get_offsets (base_b1, &flash_info[1]);
+
+ /* monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ base_b1 + size_b1 - monitor_flash_len,
+ base_b1 + size_b1 - 1, &flash_info[1]);
+ /* monitor protection OFF by default (one is enough) */
+ flash_protect (FLAG_PROTECT_CLEAR,
+ base_b0 + size_b0 - monitor_flash_len,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+ } else {
+ flash_info[1].flash_id = FLASH_UNKNOWN;
+ flash_info[1].sector_count = -1;
+ }
+
+ flash_info[0].size = size_b0;
+ flash_info[1].size = size_b1;
+
+ return (size_b0 + size_b1);
+}
diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c
new file mode 100644
index 0000000..b815961
--- /dev/null
+++ b/board/esd/ocrtc/ocrtc.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "ocrtc.h"
+#include <asm/processor.h>
+#include <i2c.h>
+#include <command.h>
+
+
+extern void lxt971_no_sleep(void);
+
+
+int board_early_init_f (void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: clear EBTC -> high-Z ebc signals between
+ * transfers, set device-paced timeout to 256 cycles
+ */
+ mtebc (EBC0_CFG, 0x20400000);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof (str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+#ifdef CONFIG_OCRTC
+ puts ("### No HW ID - assuming OCRTC");
+#endif
+#ifdef CONFIG_ORSG
+ puts ("### No HW ID - assuming ORSG");
+#endif
+ } else {
+ puts (str);
+ }
+
+ putc ('\n');
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+
+ return (0);
+}
diff --git a/board/esd/ocrtc/ocrtc.h b/board/esd/ocrtc/ocrtc.h
new file mode 100644
index 0000000..029e27e
--- /dev/null
+++ b/board/esd/ocrtc/ocrtc.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ * Start Address Length
+ * +-----------------------+ 0x4000_0000 Start of Flash -----------------
+ * | MON8xx code | 0x4000_0100 Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused) |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses | 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) | 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address | 0x04
+ * +-----------------------+ 0x4001_FFC0 ^
+ * | Hardware Information | 0x40 | MON8xx
+ * +=======================+ 0x4002_0000 (sector border) -----------------
+ * | Autostart Header | | Applications
+ * | ... | v
+ *
+ *****************************************************************************/
diff --git a/board/esd/otc570/Kconfig b/board/esd/otc570/Kconfig
new file mode 100644
index 0000000..55a2f70
--- /dev/null
+++ b/board/esd/otc570/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_OTC570
+
+config SYS_BOARD
+ default "otc570"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "otc570"
+
+endif
diff --git a/board/esd/otc570/MAINTAINERS b/board/esd/otc570/MAINTAINERS
new file mode 100644
index 0000000..a7e165d
--- /dev/null
+++ b/board/esd/otc570/MAINTAINERS
@@ -0,0 +1,7 @@
+OTC570 BOARD
+M: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+S: Maintained
+F: board/esd/otc570/
+F: include/configs/otc570.h
+F: configs/otc570_defconfig
+F: configs/otc570_dataflash_defconfig
diff --git a/board/esd/otc570/Makefile b/board/esd/otc570/Makefile
new file mode 100644
index 0000000..740bb0a
--- /dev/null
+++ b/board/esd/otc570/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += otc570.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c
new file mode 100644
index 0000000..4751d0a
--- /dev/null
+++ b/board/esd/otc570/otc570.c
@@ -0,0 +1,372 @@
+/*
+ * (C) Copyright 2010-2011
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <netdev.h>
+#ifdef CONFIG_LCD
+# include <atmel_lcdc.h>
+# include <lcd.h>
+# ifdef CONFIG_LCD_INFO
+# include <nand.h>
+# include <version.h>
+# endif
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static int hw_rev = -1; /* hardware revision */
+
+int get_hw_rev(void)
+{
+ if (hw_rev >= 0)
+ return hw_rev;
+
+ hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
+ hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
+ hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
+ hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
+
+ if (hw_rev == 15)
+ hw_rev = 0;
+
+ return hw_rev;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void otc570_nand_hw_init(void)
+{
+ unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
+ at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa[0]);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(12),
+ &smc->cs[3].mode);
+
+ /* Configure RDY/BSY */
+ gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+ /* Enable NandFlash */
+ gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif /* CONFIG_CMD_NAND */
+
+#ifdef CONFIG_MACB
+static void otc570_macb_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ /* Enable clock */
+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+ at91_macb_hw_init();
+}
+#endif
+
+/*
+ * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
+ * controller debugging
+ * The ET1100 is located at physical address 0x70000000
+ * Its process memory is located at physical address 0x70001000
+ */
+static void otc570_ethercat_hw_init(void)
+{
+ at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
+
+ /* Configure SMC EBI1_CS0 for EtherCAT */
+ writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc1->cs[0].setup);
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
+ AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
+ &smc1->cs[0].pulse);
+ writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
+ &smc1->cs[0].cycle);
+ /*
+ * Configure behavior at external wait signal, byte-select mode, 16 bit
+ * data bus width, none data float wait states and TDF optimization
+ */
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
+ AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
+ AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
+
+ /* Configure RDY/BSY */
+ at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
+}
+
+#ifdef CONFIG_LCD
+/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
+vidinfo_t panel_info = {
+ .vl_col = 640,
+ .vl_row = 480,
+ .vl_clk = 25175000,
+ .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+
+ .vl_bpix = LCD_BPP,/* Bits per pixel, 0 = 1bit, 3 = 8bit */
+ .vl_tft = 1, /* 0 = passive, 1 = TFT */
+ .vl_vsync_len = 1, /* Length of vertical sync in NOL */
+ .vl_upper_margin = 35, /* Idle lines at the frame start */
+ .vl_lower_margin = 5, /* Idle lines at the end of the frame */
+ .vl_hsync_len = 5, /* Width of the LCDHSYNC pulse */
+ .vl_left_margin = 112, /* Idle cycles at the line beginning */
+ .vl_right_margin = 1, /* Idle cycles at the end of the line */
+
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+ at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */
+}
+
+static void otc570_lcd_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
+ at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
+ at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
+ at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
+ at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
+ at91_set_pio_output(AT91_PIO_PORTA, 30, 1); /* PCI */
+
+ writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size;
+ int i;
+ char temp[32];
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+
+ lcd_printf("\n%s\n", U_BOOT_VERSION);
+ lcd_printf("CPU at %s MHz\n", strmhz(temp, get_cpu_clk_rate()));
+ lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
+ dram_size >> 20,
+ nand_size >> 20 );
+ lcd_printf(" Board : esd ARM9 HMI Panel - OTC570\n");
+ lcd_printf(" Hardware-revision: 1.%d\n", get_hw_rev());
+ lcd_printf(" Mach-type : %lu\n", gd->bd->bi_arch_number);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
+
+int checkboard(void)
+{
+ char str[32];
+
+ puts("Board : esd ARM9 HMI Panel - OTC570");
+ if (getenv_f("serial#", str, sizeof(str)) > 0) {
+ puts(", serial# ");
+ puts(str);
+ }
+ printf("\n");
+ printf("Hardware-revision: 1.%d\n", get_hw_rev());
+ printf("Mach-type : %lu\n", gd->bd->bi_arch_number);
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *str;
+
+ char *serial = getenv("serial#");
+ if (serial) {
+ str = strchr(serial, '_');
+ if (str && (strlen(str) >= 4)) {
+ serialnr->high = (*(str + 1) << 8) | *(str + 2);
+ serialnr->low = simple_strtoul(str + 3, NULL, 16);
+ }
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+ return hw_rev | 0x100;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ char str[64];
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
+ at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */
+ writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+ /* Set USART_MODE = 1 (RS485) */
+ writel(1, 0xFFF8C004);
+
+ printf("USART0: ");
+
+ if (getenv_f("usart0", str, sizeof(str)) == -1) {
+ printf("No entry - assuming 1-wire\n");
+ /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
+ at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
+ } else {
+ if (strcmp(str, "1-wire") == 0) {
+ printf("%s\n", str);
+ at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
+ } else if (strcmp(str, "rs485") == 0) {
+ printf("%s\n", str);
+ at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
+ } else {
+ printf("Wrong entry - assuming 1-wire ");
+ printf("(valid values are '1-wire' or 'rs485')\n");
+ at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
+ }
+ }
+#ifdef CONFIG_LCD
+ printf("Display memory address: 0x%08lX\n", gd->fb_base);
+#endif
+
+ return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+int board_early_init_f(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ /* enable all clocks */
+ writel((1 << ATMEL_ID_PIOA) |
+ (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOCDE) |
+ (1 << ATMEL_ID_TWI) |
+ (1 << ATMEL_ID_SPI0) |
+#ifdef CONFIG_LCD
+ (1 << ATMEL_ID_LCDC) |
+#endif
+ (1 << ATMEL_ID_UHP),
+ &pmc->pcer);
+
+ at91_seriald_hw_init();
+
+ /* arch number of OTC570-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_OTC570;
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* initialize ET1100 Controller */
+ otc570_ethercat_hw_init();
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ otc570_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+ otc570_macb_hw_init();
+#endif
+#ifdef CONFIG_AT91_CAN
+ at91_can_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+ at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ otc570_lcd_hw_init();
+#endif
+ return 0;
+}
diff --git a/board/esd/otc570/partition.c b/board/esd/otc570/partition.c
new file mode 100644
index 0000000..b6afafc
--- /dev/null
+++ b/board/esd/otc570/partition.c
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+};
+
+/* define the area offsets */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+};
diff --git a/board/esd/pci405/Kconfig b/board/esd/pci405/Kconfig
new file mode 100644
index 0000000..0a6524d
--- /dev/null
+++ b/board/esd/pci405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PCI405
+
+config SYS_BOARD
+ default "pci405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "PCI405"
+
+endif
diff --git a/board/esd/pci405/MAINTAINERS b/board/esd/pci405/MAINTAINERS
new file mode 100644
index 0000000..cf9c1c9
--- /dev/null
+++ b/board/esd/pci405/MAINTAINERS
@@ -0,0 +1,6 @@
+PCI405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/pci405/
+F: include/configs/PCI405.h
+F: configs/PCI405_defconfig
diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile
new file mode 100644
index 0000000..9e659c7
--- /dev/null
+++ b/board/esd/pci405/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = pci405.o flash.o ../common/misc.o cmd_pci405.o
+obj-y += writeibm.o
diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c
new file mode 100644
index 0000000..29c688a
--- /dev/null
+++ b/board/esd/pci405/cmd_pci405.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2002-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <asm/4xx_pci.h>
+#include <asm/processor.h>
+
+#include "pci405.h"
+
+#if defined(CONFIG_CMD_BSP)
+
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int *ptr;
+ int count = 0;
+ int count2 = 0;
+ int i;
+ char addr[16];
+ char str[] = "\\|/-";
+ char *local_args[2];
+
+ /*
+ * Mark sync address
+ */
+ ptr = 0;
+ /* cppcheck-suppress nullPointer */
+ *ptr = 0xffffffff;
+ puts("\nWaiting for image from pci host -");
+
+ /*
+ * Wait for host to write the start address
+ */
+ /* cppcheck-suppress nullPointer */
+ while (*ptr == 0xffffffff) {
+ count++;
+ if (!(count % 100)) {
+ count2++;
+ putc(0x08); /* backspace */
+ putc(str[count2 % 4]);
+ }
+
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return 0;
+ }
+
+ udelay(1000);
+ }
+
+ if (*ptr == PCI_RECONFIG_MAGIC) {
+ /*
+ * Save own pci configuration in PRAM
+ */
+ memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN);
+ ptr = (unsigned int *)PCI_REGS_ADDR + 1;
+ for (i=0; i<0x40; i+=4) {
+ pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
+ }
+ ptr = (unsigned int *)PCI_REGS_ADDR;
+ *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
+
+ printf("\nStoring PCI Configuration Regs...\n");
+ } else {
+ sprintf(addr, "%08x", *ptr);
+
+ /*
+ * Boot image via bootm
+ */
+ printf("\nBooting Image at addr 0x%s ...\n", addr);
+ setenv("loadaddr", addr);
+
+ local_args[0] = argv[0];
+ local_args[1] = NULL;
+ do_bootm (cmdtp, 0, 1, local_args);
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ loadpci, 1, 1, do_loadpci,
+ "Wait for pci-image and boot it",
+ ""
+);
+#endif
diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c
new file mode 100644
index 0000000..113111d
--- /dev/null
+++ b/board/esd/pci405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b0 = -size_b0;
+ switch (size_b0) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -monitor_flash_len,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/pci405/fpgadata.c b/board/esd/pci405/fpgadata.c
new file mode 100644
index 0000000..d145826
--- /dev/null
+++ b/board/esd/pci405/fpgadata.c
@@ -0,0 +1,1492 @@
+0x1f, 0x8b, 0x08, 0x08, 0xcd, 0x78, 0x61, 0x3f,
+0x00, 0x03, 0x70, 0x63, 0x69, 0x34, 0x30, 0x35,
+0x5f, 0x31, 0x5f, 0x30, 0x34, 0x2e, 0x62, 0x69,
+0x74, 0x00, 0xed, 0x9c, 0x7f, 0x78, 0x14, 0xc7,
+0x99, 0xe7, 0xdf, 0xae, 0xee, 0x11, 0x2d, 0xcd,
+0x88, 0x69, 0x89, 0x11, 0x1e, 0x3b, 0x32, 0xdb,
+0x1a, 0x09, 0x3c, 0xc1, 0x23, 0x69, 0x18, 0x61,
+0x85, 0x60, 0x79, 0xd4, 0x8c, 0x04, 0x19, 0x1b,
+0xd9, 0x4c, 0x6c, 0x27, 0x61, 0xf3, 0xf8, 0xc9,
+0x8e, 0x1d, 0x92, 0x23, 0x59, 0x92, 0x47, 0x90,
+0xdc, 0x2e, 0x49, 0x9c, 0x6c, 0x8d, 0x24, 0xd0,
+0x00, 0xb2, 0x19, 0x30, 0x97, 0xb0, 0x59, 0xce,
+0x3b, 0x60, 0x12, 0x0b, 0x9b, 0x64, 0x07, 0x61,
+0x1b, 0x61, 0x88, 0xdd, 0x92, 0x85, 0x23, 0x40,
+0x06, 0x85, 0xf5, 0x79, 0xb1, 0xcd, 0xe2, 0xc1,
+0x91, 0xbd, 0xb2, 0x23, 0x63, 0x19, 0xb3, 0x8e,
+0x00, 0x19, 0xdd, 0x5b, 0xdd, 0x3d, 0xdd, 0x2d,
+0xe1, 0xfd, 0x71, 0xb7, 0xf7, 0xdc, 0xde, 0xf3,
+0x9c, 0xdb, 0x7f, 0xb8, 0x50, 0xa9, 0xba, 0xab,
+0xab, 0xde, 0xfa, 0xd4, 0xf7, 0x7d, 0xdf, 0x6a,
+0x41, 0xbe, 0x7b, 0x54, 0xff, 0x0f, 0x80, 0xbb,
+0x1f, 0xa4, 0xe6, 0xaf, 0x7f, 0x6b, 0x7e, 0xf0,
+0x96, 0x3f, 0x9b, 0xf7, 0x67, 0xc1, 0xf9, 0x55,
+0xdf, 0xfd, 0xfa, 0x0a, 0x78, 0x00, 0x0a, 0x42,
+0xdf, 0x9b, 0x77, 0xcb, 0xf7, 0x57, 0xcf, 0x9b,
+0x3f, 0x1f, 0xbe, 0x0e, 0xce, 0x50, 0x30, 0x58,
+0x53, 0x1d, 0x5c, 0x50, 0x1d, 0xba, 0x05, 0x56,
+0x40, 0xfe, 0xbc, 0x05, 0x0b, 0x83, 0xb7, 0x2c,
+0x9c, 0x57, 0x03, 0xdf, 0x00, 0x88, 0x27, 0x27,
+0xf0, 0x7a, 0xe2, 0xaf, 0xbf, 0xf4, 0xcd, 0x20,
+0x50, 0x0e, 0x00, 0xa6, 0x05, 0xb9, 0x38, 0xfb,
+0x7f, 0x5e, 0x90, 0x93, 0x39, 0xa0, 0xf5, 0x95,
+0x41, 0x50, 0xd9, 0xbf, 0xc1, 0xa8, 0xcf, 0x0f,
+0x82, 0x6c, 0xff, 0x37, 0x17, 0x04, 0x05, 0x62,
+0xe0, 0xf9, 0x0e, 0x14, 0x4b, 0x30, 0xe5, 0xe2,
+0x14, 0x81, 0xea, 0xa5, 0x7f, 0xad, 0x8e, 0x4c,
+0xad, 0x62, 0xd7, 0xbf, 0xa3, 0xae, 0xf8, 0x13,
+0xaa, 0x84, 0xff, 0x58, 0xdd, 0x84, 0x04, 0x71,
+0xf0, 0x42, 0x1e, 0x70, 0xd4, 0x2c, 0xd4, 0xf7,
+0xe9, 0x75, 0xaa, 0x63, 0x5c, 0x7e, 0xbd, 0x68,
+0x46, 0x9f, 0xbb, 0x9f, 0x8c, 0xd3, 0x93, 0x05,
+0x3e, 0xa5, 0x70, 0x8c, 0x0f, 0x42, 0xb3, 0xde,
+0x23, 0xe9, 0x3d, 0xba, 0x59, 0x29, 0xff, 0x47,
+0x67, 0x92, 0x5c, 0x8d, 0x6c, 0x96, 0x7d, 0x59,
+0x31, 0x58, 0x20, 0x0b, 0x41, 0xad, 0x2e, 0xe9,
+0x18, 0x96, 0x1f, 0x89, 0x77, 0xf6, 0x3b, 0x81,
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+0x52, 0x2a, 0xdd, 0x24, 0xe4, 0x5b, 0xef, 0x20,
+0x98, 0x9c, 0x77, 0xac, 0xe6, 0x74, 0xce, 0x9b,
+0x75, 0x1a, 0xe7, 0xe3, 0xc5, 0x5e, 0x61, 0xbd,
+0xc9, 0x79, 0xab, 0x5d, 0xfc, 0x7e, 0xed, 0xef,
+0xa9, 0x08, 0x16, 0xaf, 0xad, 0x31, 0x13, 0xd6,
+0x24, 0x4a, 0xd5, 0x2f, 0xc8, 0x45, 0xfd, 0xc2,
+0x1a, 0xae, 0x94, 0x62, 0xc1, 0xba, 0x27, 0x00,
+0xb6, 0x93, 0xf3, 0x44, 0xdb, 0x1f, 0x64, 0x31,
+0x6b, 0x24, 0x61, 0x0e, 0x97, 0x4f, 0x23, 0xcd,
+0xd2, 0xcf, 0x85, 0xd9, 0x9c, 0x48, 0x19, 0xe7,
+0xcd, 0xba, 0x32, 0x58, 0x9a, 0x28, 0x4e, 0x37,
+0x76, 0x16, 0x55, 0x09, 0x51, 0xaa, 0x15, 0xcc,
+0xa7, 0xa9, 0x55, 0xb8, 0x66, 0x3d, 0xd4, 0x11,
+0xe4, 0xee, 0x82, 0x7b, 0x70, 0xcd, 0x62, 0xc1,
+0xd8, 0x52, 0xd9, 0x81, 0x5a, 0xe1, 0x16, 0x28,
+0x52, 0x84, 0xe5, 0x9c, 0x07, 0xbe, 0x40, 0xd9,
+0x82, 0xe2, 0x8c, 0x6d, 0x1a, 0xdb, 0x29, 0x44,
+0x62, 0xa7, 0xde, 0xd8, 0x01, 0x32, 0x30, 0x0a,
+0x56, 0x9d, 0xc0, 0x00, 0x88, 0xcb, 0x80, 0x62,
+0x61, 0x3b, 0x5b, 0x0f, 0xd4, 0xa8, 0x93, 0x38,
+0x05, 0x55, 0xc7, 0x76, 0x98, 0x03, 0xf9, 0x94,
+0x3c, 0x80, 0xef, 0x80, 0x85, 0x16, 0xe3, 0x71,
+0xca, 0xe2, 0xbb, 0xf3, 0xe2, 0xc8, 0xf9, 0x06,
+0x51, 0xea, 0x15, 0x82, 0x7a, 0x21, 0xc7, 0x10,
+0x05, 0x6f, 0x2f, 0x1b, 0x78, 0xc7, 0xe7, 0x18,
+0x05, 0xa3, 0x1d, 0x38, 0x21, 0x48, 0xd9, 0xfe,
+0x00, 0xbd, 0x10, 0xec, 0xd1, 0x0a, 0x66, 0xdd,
+0xe2, 0x06, 0xa1, 0x19, 0x31, 0xbd, 0x44, 0x44,
+0xbe, 0xc4, 0x7b, 0xb4, 0x02, 0xcd, 0xdd, 0x93,
+0x63, 0x9c, 0x17, 0x91, 0x75, 0xc0, 0xf6, 0x29,
+0x17, 0x2b, 0xe4, 0xc6, 0x2c, 0xc6, 0x21, 0x97,
+0xcc, 0x76, 0xd8, 0x17, 0xd6, 0xce, 0xbc, 0xa7,
+0x82, 0xef, 0xe1, 0x81, 0xc5, 0x6c, 0x6c, 0x70,
+0x0b, 0x64, 0x85, 0x88, 0x71, 0xcf, 0x28, 0x4e,
+0xca, 0x22, 0x2a, 0xc5, 0x05, 0xaf, 0x90, 0x2b,
+0x98, 0xec, 0x89, 0x6a, 0xe7, 0x6c, 0x10, 0xef,
+0xa2, 0x80, 0xee, 0x9b, 0x5e, 0x00, 0xf3, 0x9e,
+0x8c, 0xf3, 0x0c, 0xef, 0xf9, 0x4b, 0x8c, 0x42,
+0xa1, 0xc9, 0x3a, 0x6e, 0x89, 0xb0, 0x3a, 0x51,
+0x1a, 0xff, 0x82, 0xb7, 0xe8, 0x45, 0x61, 0xf5,
+0xba, 0x1d, 0xac, 0x60, 0xbe, 0x1f, 0x8e, 0xf2,
+0x6a, 0xba, 0x23, 0x7e, 0x93, 0x37, 0xff, 0x45,
+0xb2, 0x9a, 0xde, 0xc7, 0x0a, 0xb9, 0xba, 0x18,
+0xe3, 0x3c, 0x6e, 0x0b, 0xb8, 0x3f, 0xbc, 0xe8,
+0x60, 0x37, 0xc0, 0x42, 0xaf, 0x39, 0x9e, 0xc5,
+0x50, 0x41, 0x6f, 0x97, 0x8b, 0xa3, 0xc2, 0x56,
+0xae, 0x82, 0x36, 0xd9, 0xed, 0x53, 0xc1, 0x77,
+0x28, 0xa3, 0xde, 0x78, 0x9e, 0x97, 0x5b, 0x0f,
+0xf7, 0x27, 0xb4, 0x82, 0x69, 0x4b, 0x8b, 0xe3,
+0x8e, 0x05, 0xdc, 0x2c, 0x34, 0x87, 0xa2, 0xac,
+0xb0, 0x56, 0x2f, 0x98, 0x73, 0xc4, 0xdd, 0x0d,
+0x2b, 0xe8, 0xf5, 0x72, 0x5e, 0x94, 0xdb, 0x8a,
+0x05, 0xc3, 0x50, 0x73, 0xfd, 0x64, 0xe3, 0xc9,
+0xf6, 0x00, 0xa9, 0x25, 0x57, 0xb0, 0xc6, 0x33,
+0x02, 0x31, 0x44, 0x7f, 0xa3, 0x58, 0x44, 0x04,
+0x85, 0x6a, 0x05, 0x30, 0xfb, 0x49, 0x20, 0x86,
+0x7b, 0x80, 0xc3, 0xc5, 0x35, 0xe4, 0x0a, 0x8a,
+0xd9, 0x4f, 0x51, 0x78, 0x00, 0x72, 0xba, 0x46,
+0x2f, 0x58, 0xe3, 0x19, 0x21, 0x40, 0x0d, 0xce,
+0x1b, 0x05, 0xf3, 0x9e, 0x9c, 0x52, 0x11, 0x77,
+0x78, 0x61, 0x92, 0x7d, 0x9a, 0xfd, 0x54, 0x80,
+0xfd, 0xa5, 0x85, 0x39, 0x4a, 0x7e, 0x8a, 0xac,
+0x80, 0x52, 0xcd, 0x50, 0xcd, 0x7b, 0xc6, 0xe7,
+0xf8, 0xb9, 0xe9, 0xd0, 0x40, 0xa5, 0xac, 0xb0,
+0x80, 0xbb, 0x81, 0x15, 0x72, 0xef, 0x1e, 0xc3,
+0xa5, 0x51, 0xa6, 0xb8, 0x62, 0xbc, 0x07, 0x8e,
+0xd0, 0x79, 0x8a, 0x28, 0xf1, 0x82, 0xcd, 0x3e,
+0x05, 0x98, 0xad, 0x14, 0x4a, 0xfc, 0xbd, 0xf0,
+0x3b, 0x98, 0xbf, 0x48, 0xfb, 0xa5, 0x5e, 0xab,
+0x9f, 0xc2, 0xfd, 0x3d, 0xde, 0xe0, 0x92, 0xd2,
+0xa2, 0x56, 0x66, 0x9f, 0xc1, 0x25, 0x2e, 0x9b,
+0x7d, 0x2a, 0x68, 0xea, 0xb6, 0xf5, 0x65, 0xe3,
+0xbc, 0xc2, 0x45, 0x1b, 0x43, 0x0c, 0xef, 0x65,
+0x45, 0x1d, 0x8d, 0x0f, 0x5c, 0xaf, 0x15, 0x6c,
+0xf6, 0xa9, 0x4a, 0x3f, 0xf0, 0xcc, 0x5a, 0x5c,
+0xb4, 0x45, 0x69, 0x8c, 0xc5, 0x3c, 0xc2, 0x62,
+0xae, 0x48, 0xb1, 0xd6, 0x11, 0x1b, 0x7a, 0x22,
+0x94, 0x25, 0xc4, 0xb8, 0xa2, 0x4f, 0x06, 0x98,
+0x57, 0x0e, 0xef, 0x42, 0x01, 0x67, 0x14, 0xac,
+0xf1, 0xbc, 0x93, 0xbf, 0x47, 0x79, 0x79, 0xf0,
+0x96, 0xf9, 0x85, 0x66, 0xc1, 0xbc, 0x27, 0x17,
+0xad, 0x58, 0x53, 0x58, 0x4a, 0xbe, 0x50, 0x56,
+0xa4, 0x36, 0xae, 0xc9, 0xdf, 0x31, 0x99, 0x59,
+0x33, 0x6c, 0x9c, 0xef, 0x29, 0x0a, 0x35, 0x36,
+0x6d, 0xb1, 0x9e, 0xf7, 0xbf, 0xcb, 0xf9, 0x4a,
+0x5b, 0xbb, 0xab, 0x53, 0x38, 0x5f, 0x63, 0xbf,
+0xe7, 0x14, 0xce, 0xdf, 0xea, 0xbd, 0xeb, 0x8d,
+0x47, 0x0e, 0x0c, 0xbd, 0x77, 0xe9, 0xd6, 0x9f,
+0xdc, 0x75, 0x76, 0x06, 0x2b, 0x58, 0x75, 0xe8,
+0xc3, 0xec, 0x04, 0xbf, 0x52, 0x50, 0xda, 0x6b,
+0x14, 0x24, 0xab, 0x4e, 0x23, 0x1f, 0x8e, 0x9d,
+0x64, 0x15, 0xac, 0x4b, 0x8b, 0x38, 0x31, 0x1a,
+0x9a, 0x85, 0x6b, 0xda, 0x95, 0xaa, 0xd7, 0xb6,
+0x63, 0xd9, 0x67, 0x48, 0xea, 0x21, 0x1f, 0xbd,
+0x60, 0xd6, 0x4c, 0x99, 0x71, 0xa3, 0x60, 0xd4,
+0x5d, 0xdb, 0xce, 0x56, 0x77, 0x4d, 0x4b, 0xeb,
+0x4f, 0x86, 0x15, 0xb4, 0x87, 0x76, 0x42, 0xa7,
+0x32, 0x57, 0x2a, 0x68, 0x23, 0x5a, 0xa1, 0xb4,
+0xd7, 0x6c, 0xa7, 0xf5, 0x73, 0x12, 0x99, 0xac,
+0x7b, 0x5e, 0xfb, 0x7e, 0x66, 0x9d, 0xc4, 0xfe,
+0x3e, 0xda, 0x40, 0xee, 0xfd, 0x06, 0xe0, 0x7b,
+0x50, 0xda, 0x6b, 0x5a, 0x8c, 0xfe, 0x27, 0x34,
+0x14, 0x52, 0xaa, 0x1a, 0x05, 0xc9, 0xea, 0x0b,
+0x11, 0x58, 0x0c, 0x96, 0x7d, 0x6f, 0x6d, 0x14,
+0xec, 0x93, 0xab, 0x3d, 0x06, 0x72, 0xcf, 0xb3,
+0xff, 0xd1, 0x33, 0x89, 0xf2, 0x41, 0x18, 0xc8,
+0xfd, 0x4b, 0x2f, 0x18, 0xbe, 0xf6, 0xbf, 0x76,
+0xd5, 0xd5, 0x5d, 0xfb, 0x33, 0xb7, 0xfb, 0xdf,
+0x6c, 0xf6, 0x1f, 0xb8, 0xea, 0x27, 0x26, 0x26,
+0xd4, 0x49, 0x85, 0xff, 0x37, 0xeb, 0x72, 0x36,
+0x2f, 0x91, 0xff, 0xf3, 0x36, 0xff, 0x49, 0xed,
+0xa6, 0xda, 0xae, 0x35, 0xb7, 0xff, 0x97, 0x6c,
+0xde, 0x6e, 0xd7, 0xd6, 0x26, 0xfc, 0xbf, 0x6c,
+0xf3, 0x80, 0xa6, 0xae, 0xbd, 0xdf, 0x54, 0x9b,
+0xff, 0x17, 0xdb, 0xc1, 0x27, 0xbc, 0x9f, 0xed,
+0xfa, 0x17, 0xde, 0x1c, 0x98, 0xcd, 0xc3, 0x35,
+0xd7, 0xa7, 0x36, 0xff, 0x1f, 0xa8, 0xfb, 0x97,
+0x2f, 0xf6, 0xb7, 0x1c, 0x89, 0xf6, 0xff, 0x45,
+0xbf, 0xfd, 0xf7, 0xb6, 0xf9, 0xf4, 0xfa, 0xf4,
+0xfa, 0xf4, 0xfa, 0xf4, 0xfa, 0xf4, 0xfa, 0xf4,
+0xfa, 0xff, 0xe5, 0xd2, 0xf6, 0x49, 0xa2, 0xed,
+0x93, 0xea, 0x7f, 0x76, 0x5f, 0x3e, 0xbd, 0x3e,
+0xbd, 0x3e, 0xbd, 0x3e, 0xbd, 0x3e, 0xbd, 0x3e,
+0xbd, 0xfe, 0x33, 0xae, 0x20, 0xfb, 0x73, 0x09,
+0x50, 0xf9, 0x6b, 0xe3, 0xef, 0xff, 0xf3, 0x41,
+0x50, 0xa6, 0xfd, 0xeb, 0xbf, 0xaf, 0xfd, 0x9e,
+0x23, 0x08, 0x69, 0xce, 0x6a, 0xbf, 0x3b, 0x35,
+0xb5, 0xaf, 0xff, 0x13, 0x87, 0x7b, 0xf6, 0xdd,
+0xd4, 0x60, 0x00, 0x00,
diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
new file mode 100644
index 0000000..566f6f7
--- /dev/null
+++ b/board/esd/pci405/pci405.c
@@ -0,0 +1,366 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+#include <pci.h>
+#include <asm/4xx_pci.h>
+#include <asm/io.h>
+
+#include "pci405.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Prototypes */
+unsigned long fpga_done_state(void);
+unsigned long fpga_init_state(void);
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* predefine these here */
+#define FPGA_DONE_STATE (fpga_done_state())
+#define FPGA_INIT_STATE (fpga_init_state())
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
+
+#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
+#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
+
+
+int board_revision(void)
+{
+ unsigned long CPC0_CR0Reg;
+ unsigned long value;
+
+ /*
+ * Get version of PCI405 board from GPIO's
+ */
+
+ /*
+ * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+ */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
+ out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
+ udelay(1000); /* wait some time before reading input */
+ value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */
+
+ /*
+ * Restore GPIO settings
+ */
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
+
+ switch (value) {
+ case 0x00100200:
+ /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
+ return 1;
+ case 0x00000200:
+ /* CS2==0 && IRQ5==1 -> version 1.2 */
+ return 2;
+ case 0x00000000:
+ /* CS2==0 && IRQ5==0 -> version 1.3 */
+ return 3;
+#if 0 /* not yet manufactured ! */
+ case 0x00100000:
+ /* CS2==1 && IRQ5==0 -> version 1.4 */
+ return 4;
+#endif
+ default:
+ /* should not be reached! */
+ return 0;
+ }
+}
+
+
+unsigned long fpga_done_state(void)
+{
+ if (gd->board_type < 2) {
+ return FPGA_DONE_STATE_V11;
+ } else {
+ return FPGA_DONE_STATE_V12;
+ }
+}
+
+
+unsigned long fpga_init_state(void)
+{
+ if (gd->board_type < 2) {
+ return FPGA_INIT_STATE_V11;
+ } else {
+ return FPGA_INIT_STATE_V12;
+ }
+}
+
+
+int board_early_init_f (void)
+{
+ unsigned long CPC0_CR0Reg;
+
+ /*
+ * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
+ */
+ out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
+ out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
+ out_be32((void*)GPIO0_OR, 0); /* pull prg low */
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
+ */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
+
+ /*
+ * Setup GPIO pins (CS6+CS7 as GPIO)
+ */
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
+ */
+ mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ unsigned char *dst;
+ ulong len = sizeof(fpgadata);
+ int status;
+ int index;
+ int i;
+ unsigned int *ptr;
+ unsigned int *magic;
+
+ /*
+ * On PCI-405 the environment is saved in eeprom!
+ * FPGA can be gzip compressed (malloc) and booted this late.
+ */
+
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ printf ("GUNZIP ERROR - must RESET board to recover\n");
+ do_reset (NULL, 0, 0, NULL);
+ }
+
+ status = fpga_boot(dst, len);
+ if (status != 0) {
+ printf("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf("(Timeout: DONE not high after programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("FPGA: %s\n", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+ /* delayed reboot */
+ for (i=20; i>0; i--) {
+ printf("Rebooting in %2d seconds \r",i);
+ for (index=0;index<1000;index++)
+ udelay(1000);
+ }
+ putc ('\n');
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ puts("FPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("%s ", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+
+ /*
+ * Reset FPGA via FPGA_DATA pin
+ */
+ SET_FPGA(FPGA_PRG | FPGA_CLK);
+ udelay(1000); /* wait 1ms */
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+ udelay(1000); /* wait 1ms */
+
+ /*
+ * Check if magic for pci reconfig is written
+ */
+ magic = (unsigned int *)0x00000004;
+ if (*magic == PCI_RECONFIG_MAGIC) {
+ /*
+ * Rewrite pci config regs (only after soft-reset with magic set)
+ */
+ ptr = (unsigned int *)PCI_REGS_ADDR;
+ if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
+ puts("Restoring PCI Configurations Regs!\n");
+ ptr = (unsigned int *)PCI_REGS_ADDR + 1;
+ for (i=0; i<0x40; i+=4) {
+ pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
+ }
+ }
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ *magic = 0; /* clear pci reconfig magic again */
+ }
+
+ /*
+ * Decrease PLB latency timeout and reduce priority of the PCI bridge master
+ */
+#define PCI0_BRDGOPT1 0x4a
+ pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
+
+ /*
+ * Enable fairness and high bus utilization
+ */
+ mtdcr(PLB0_ACR, 0x98000000);
+
+ free(dst);
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming PCI405");
+ } else {
+ puts (str);
+ }
+
+ gd->board_type = board_revision();
+ printf(" (Rev 1.%ld", gd->board_type);
+
+ if (gd->board_type >= 2) {
+ unsigned long CPC0_CR0Reg;
+ unsigned long value;
+
+ /*
+ * Setup GPIO pins (Trace/GPIO1 to GPIO)
+ */
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
+ out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
+ udelay(1000); /* wait some time before reading input */
+ value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */
+ if (value) {
+ puts(", 33 MHz PCI");
+ } else {
+ puts(", 66 MHz PCI");
+ }
+ }
+
+ puts(")\n");
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+#define UART1_MCR 0xef600404
+int wpeeprom(int wp)
+{
+ int wp_state = wp;
+
+ if (wp == 1) {
+ out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
+ } else if (wp == 0) {
+ out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
+ } else {
+ if (in_8((void *)UART1_MCR) & 0x02) {
+ wp_state = 0;
+ } else {
+ wp_state = 1;
+ }
+ }
+ return wp_state;
+}
+
+int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int wp = -1;
+ if (argc >= 2) {
+ if (argv[1][0] == '1') {
+ wp = 1;
+ } else if (argv[1][0] == '0') {
+ wp = 0;
+ }
+ }
+
+ wp = wpeeprom(wp);
+ printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
+ return 0;
+}
+
+U_BOOT_CMD(
+ wpeeprom, 2, 1, do_wpeeprom,
+ "Check/Enable/Disable I2C EEPROM write protection",
+ "wpeeprom\n"
+ " - check I2C EEPROM write protection state\n"
+ "wpeeprom 1\n"
+ " - enable I2C EEPROM write protection\n"
+ "wpeeprom 0\n"
+ " - disable I2C EEPROM write protection"
+);
diff --git a/board/esd/pci405/pci405.h b/board/esd/pci405/pci405.h
new file mode 100644
index 0000000..a62c9c2
--- /dev/null
+++ b/board/esd/pci405/pci405.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PCI405_H_
+#define _PCI405_H_
+
+#define PCI_REGS_LEN 0x100
+#define PCI_REGS_ADDR ((unsigned long)0x01000000 - PCI_REGS_LEN)
+
+#define PCI_RECONFIG_MAGIC 0x07081967
+
+#endif /* _PCI405_H_ */
diff --git a/board/esd/pci405/writeibm.S b/board/esd/pci405/writeibm.S
new file mode 100644
index 0000000..03eaf97
--- /dev/null
+++ b/board/esd/pci405/writeibm.S
@@ -0,0 +1,205 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0 IBM-pibs
+ */
+/*----------------------------------------------------------------------------- */
+/* Function: ext_bus_cntlr_init */
+/* Description: Initializes the External Bus Controller for the external */
+/* peripherals. IMPORTANT: For pass1 this code must run from */
+/* cache since you can not reliably change a peripheral banks */
+/* timing register (pbxap) while running code from that bank. */
+/* For ex., since we are running from ROM on bank 0, we can NOT */
+/* execute the code that modifies bank 0 timings from ROM, so */
+/* we run it from cache. */
+/* Bank 0 - Flash and SRAM */
+/* Bank 1 - NVRAM/RTC */
+/* Bank 2 - Keyboard/Mouse controller */
+/* Bank 3 - IR controller */
+/* Bank 4 - not used */
+/* Bank 5 - not used */
+/* Bank 6 - not used */
+/* Bank 7 - FPGA registers */
+/*----------------------------------------------------------------------------- */
+#include <asm/ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+
+ .globl write_without_sync
+write_without_sync:
+ /*
+ * Write one values to host via pci busmastering
+ * ptr = 0xc0000000 -> 0x01000000 (PCI)
+ * *ptr = 0x01234567;
+ */
+ addi r31,0,0
+ lis r31,0xc000
+
+start1:
+ lis r0,0x0123
+ ori r0,r0,0x4567
+ stw r0,0(r31)
+
+ /*
+ * Read one value back
+ * ptr = (volatile unsigned long *)addr;
+ * val = *ptr;
+ */
+
+ lwz r0,0(r31)
+
+ /*
+ * One pci config write
+ * ibmPciConfigWrite(0x2e, 2, 0x1234);
+ */
+ /* subsystem id */
+
+ li r4,0x002C
+ oris r4,r4,0x8000
+ lis r3,0xEEC0
+ stwbrx r4,0,r3
+
+ li r5,0x1234
+ ori r3,r3,0x4
+ stwbrx r5,0,r3
+
+ b start1
+
+ blr /* never reached !!!! */
+
+ .globl write_with_sync
+write_with_sync:
+ /*
+ * Write one values to host via pci busmastering
+ * ptr = 0xc0000000 -> 0x01000000 (PCI)
+ * *ptr = 0x01234567;
+ */
+ addi r31,0,0
+ lis r31,0xc000
+
+start2:
+ lis r0,0x0123
+ ori r0,r0,0x4567
+ stw r0,0(r31)
+
+ /*
+ * Read one value back
+ * ptr = (volatile unsigned long *)addr;
+ * val = *ptr;
+ */
+
+ lwz r0,0(r31)
+
+ /*
+ * One pci config write
+ * ibmPciConfigWrite(0x2e, 2, 0x1234);
+ */
+ /* subsystem id */
+
+ li r4,0x002C
+ oris r4,r4,0x8000
+ lis r3,0xEEC0
+ stwbrx r4,0,r3
+ sync
+
+ li r5,0x1234
+ ori r3,r3,0x4
+ stwbrx r5,0,r3
+ sync
+
+ b start2
+
+ blr /* never reached !!!! */
+
+ .globl write_with_less_sync
+write_with_less_sync:
+ /*
+ * Write one values to host via pci busmastering
+ * ptr = 0xc0000000 -> 0x01000000 (PCI)
+ * *ptr = 0x01234567;
+ */
+ addi r31,0,0
+ lis r31,0xc000
+
+start2b:
+ lis r0,0x0123
+ ori r0,r0,0x4567
+ stw r0,0(r31)
+
+ /*
+ * Read one value back
+ * ptr = (volatile unsigned long *)addr;
+ * val = *ptr;
+ */
+
+ lwz r0,0(r31)
+
+ /*
+ * One pci config write
+ * ibmPciConfigWrite(0x2e, 2, 0x1234);
+ */
+ /* subsystem id */
+
+ li r4,0x002C
+ oris r4,r4,0x8000
+ lis r3,0xEEC0
+ stwbrx r4,0,r3
+ sync
+
+ li r5,0x1234
+ ori r3,r3,0x4
+ stwbrx r5,0,r3
+/* sync */
+
+ b start2b
+
+ blr /* never reached !!!! */
+
+ .globl write_with_more_sync
+write_with_more_sync:
+ /*
+ * Write one values to host via pci busmastering
+ * ptr = 0xc0000000 -> 0x01000000 (PCI)
+ * *ptr = 0x01234567;
+ */
+ addi r31,0,0
+ lis r31,0xc000
+
+start3:
+ lis r0,0x0123
+ ori r0,r0,0x4567
+ stw r0,0(r31)
+ sync
+
+ /*
+ * Read one value back
+ * ptr = (volatile unsigned long *)addr;
+ * val = *ptr;
+ */
+
+ lwz r0,0(r31)
+ sync
+
+ /*
+ * One pci config write
+ * ibmPciConfigWrite(0x2e, 2, 0x1234);
+ */
+ /* subsystem id (PCIC0_SBSYSVID)*/
+
+ li r4,0x002C
+ oris r4,r4,0x8000
+ lis r3,0xEEC0
+ stwbrx r4,0,r3
+ sync
+
+ li r5,0x1234
+ ori r3,r3,0x4
+ stwbrx r5,0,r3
+ sync
+
+ b start3
+
+ blr /* never reached !!!! */
diff --git a/board/esd/pf5200/Kconfig b/board/esd/pf5200/Kconfig
new file mode 100644
index 0000000..c596e7a
--- /dev/null
+++ b/board/esd/pf5200/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PF5200
+
+config SYS_BOARD
+ default "pf5200"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "pf5200"
+
+endif
diff --git a/board/esd/pf5200/MAINTAINERS b/board/esd/pf5200/MAINTAINERS
new file mode 100644
index 0000000..b6e624e
--- /dev/null
+++ b/board/esd/pf5200/MAINTAINERS
@@ -0,0 +1,6 @@
+PF5200 BOARD
+M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+S: Maintained
+F: board/esd/pf5200/
+F: include/configs/pf5200.h
+F: configs/pf5200_defconfig
diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile
new file mode 100644
index 0000000..a54289c
--- /dev/null
+++ b/board/esd/pf5200/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Objects for Xilinx JTAG programming (CPLD)
+# CPLD = ../common/xilinx_jtag/lenval.o \
+# ../common/xilinx_jtag/micro.o \
+# ../common/xilinx_jtag/ports.o
+
+# obj-y = pf5200.o flash.o $(CPLD)
+obj-y = pf5200.o flash.o
diff --git a/board/esd/pf5200/flash.c b/board/esd/pf5200/flash.c
new file mode 100644
index 0000000..e1b13bf
--- /dev/null
+++ b/board/esd/pf5200/flash.c
@@ -0,0 +1,445 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define FLASH_ID_MASK 0x00FF
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1 0x0555
+#define FLASH_CYCLE2 0x0aaa
+#define FLASH_ID1 0x00
+#define FLASH_ID2 0x01
+#define FLASH_ID3 0x0E
+#define FLASH_ID4 0x0F
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV * addr, flash_info_t * info);
+static void flash_reset(flash_info_t * info);
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init(void)
+{
+ unsigned long size = 0;
+ int i = 0;
+ extern void flash_preinit(void);
+ extern void flash_afterinit(uint, ulong, ulong);
+
+ ulong flashbase = CONFIG_SYS_FLASH_BASE;
+
+ flash_preinit();
+
+ /* There is only ONE FLASH device */
+ memset(&flash_info[i], 0, sizeof(flash_info_t));
+ flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
+ size += flash_info[i].size;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ flash_get_info(CONFIG_SYS_MONITOR_BASE));
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+ flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+ flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
+ return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t * info) {
+ FPWV *base = (FPWV *) (info->start[0]);
+
+ /* Put FLASH back in read mode */
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ *base = (FPW) 0x00FF00FF; /* Intel Read Mode */
+ } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+ *base = (FPW) 0x00F000F0; /* AMD Read Mode */
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base) {
+ int i;
+ flash_info_t *info;
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+ info = &flash_info[i];
+ if ((info->size) && (info->start[0] <= base)
+ && (base <= info->start[0] + info->size - 1)) {
+ break;
+ }
+ }
+ return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info(flash_info_t * info) {
+ int i;
+ char *fmt;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AMLV256U:
+ fmt = "29LV256M (256 Mbit)\n";
+ break;
+ default:
+ fmt = "Unknown Chip Type\n";
+ break;
+ }
+
+ printf(fmt);
+ printf(" Size: %ld MB in %d Sectors\n", info->size >> 20,
+ info->sector_count);
+ printf(" Sector Start Addresses:");
+
+ for (i = 0; i < info->sector_count; ++i) {
+ ulong size;
+ int erased;
+ ulong *flash = (unsigned long *)info->start[i];
+
+ if ((i % 5) == 0) {
+ printf("\n ");
+ }
+
+ /*
+ * Check if whole sector is erased
+ */
+ size =
+ (i !=
+ (info->sector_count - 1)) ? (info->start[i + 1] -
+ info->start[i]) >> 2 : (info->
+ start
+ [0] +
+ info->
+ size -
+ info->
+ start
+ [i])
+ >> 2;
+
+ for (flash = (unsigned long *)info->start[i], erased = 1;
+ (flash != (unsigned long *)info->start[i] + size)
+ && erased; flash++) {
+ erased = *flash == ~0x0UL;
+ }
+ printf(" %08lX %s %s", info->start[i], erased ? "E" : " ",
+ info->protect[i] ? "(RO)" : " ");
+ }
+
+ printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size(FPWV * addr, flash_info_t * info) {
+ int i;
+
+ /* Write auto select command: read Manufacturer ID */
+ /* Write auto select command sequence and test FLASH answer */
+ addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
+ addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
+ addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */
+
+ /* The manufacturer codes are only 1 byte, so just use 1 byte. */
+ /* This works for any bus width and any FLASH device width. */
+ udelay(100);
+ switch (addr[FLASH_ID1] & 0x00ff) {
+ case (uchar) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ default:
+ printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ break;
+ }
+
+ /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ switch ((FPW) addr[FLASH_ID2]) {
+ case (FPW) AMD_ID_MIRROR:
+ /* MIRROR BIT FLASH, read more ID bytes */
+ if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2
+ && (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) {
+ /* attention: only the first 16 MB will be used in u-boot */
+ info->flash_id += FLASH_AMLV256U;
+ info->sector_count = 512;
+ info->size = 0x02000000;
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] =
+ (ulong) addr + 0x10000 * i;
+ }
+ break;
+ }
+ /* fall thru to here ! */
+ default:
+ printf("unknown AMD device=%x %x %x",
+ (FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3],
+ (FPW) addr[FLASH_ID4]);
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0x800000;
+ break;
+ }
+
+ /* Put FLASH back in read mode */
+ flash_reset(info);
+ }
+ return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last) {
+ FPWV *addr;
+ int flag, prot, sect;
+ int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+ ulong start, now, last;
+ int rcode = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AMLV256U:
+ break;
+ case FLASH_UNKNOWN:
+ default:
+ printf("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ last = get_timer(0);
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+ if (info->protect[sect] != 0) { /* protected, skip it */
+ continue;
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr = (FPWV *) (info->start[sect]);
+ if (intel) {
+ *addr = (FPW) 0x00500050; /* clear status register */
+ *addr = (FPW) 0x00200020; /* erase setup */
+ *addr = (FPW) 0x00D000D0; /* erase confirm */
+ } else {
+ /* must be AMD style if not Intel */
+ FPWV *base; /* first address in bank */
+
+ base = (FPWV *) (info->start[0]);
+ base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */
+ base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
+ *addr = (FPW) 0x00300030; /* erase sector */
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag) {
+ enable_interrupts();
+ }
+ start = get_timer(0);
+
+ /* wait at least 50us for AMD, 80us for Intel. */
+ /* Let's wait 1 ms. */
+ udelay(1000);
+
+ while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ if (intel) {
+ /* suspend erase */
+ *addr = (FPW) 0x00B000B0;
+ }
+ flash_reset(info); /* reset to read mode */
+ rcode = 1; /* failed */
+ break;
+ }
+ /* show that we're waiting */
+ if ((get_timer(last)) > CONFIG_SYS_HZ) {
+ /* every second */
+ putc('.');
+ last = get_timer(0);
+ }
+ }
+ /* show that we're waiting */
+ if ((get_timer(last)) > CONFIG_SYS_HZ) {
+ /* every second */
+ putc('.');
+ last = get_timer(0);
+ }
+ flash_reset(info); /* reset to read mode */
+ }
+ printf(" done\n");
+ return (rcode);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+ int bytes; /* number of bytes to program in current word */
+ int left; /* number of bytes left to program */
+ int i, res;
+
+ for (left = cnt, res = 0;
+ left > 0 && res == 0;
+ addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+ bytes = addr & (sizeof(data) - 1);
+ addr &= ~(sizeof(data) - 1);
+
+ /* combine source and destination data so can program
+ * an entire word of 16 or 32 bits
+ */
+ for (i = 0; i < sizeof(data); i++) {
+ data <<= 8;
+ if (i < bytes || i - bytes >= left)
+ data += *((uchar *) addr + i);
+ else
+ data += *src++;
+ }
+
+ /* write one word to the flash */
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ res = write_word_amd(info, (FPWV *) addr, data);
+ break;
+ default:
+ /* unknown flash type, error! */
+ printf("missing or unknown FLASH type\n");
+ res = 1; /* not really a timeout, but gives error */
+ break;
+ }
+ }
+ return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) {
+ ulong start;
+ int flag;
+ int res = 0; /* result, assume success */
+ FPWV *base; /* first address in flash bank */
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*dest & data) != data) {
+ return (2);
+ }
+
+ base = (FPWV *) (info->start[0]);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */
+
+ *dest = data; /* start programming the data */
+
+ /* re-enable interrupts if necessary */
+ if (flag) {
+ enable_interrupts();
+ }
+ start = get_timer(0);
+
+ /* data polling for D7 */
+ while (res == 0
+ && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ *dest = (FPW) 0x00F000F0; /* reset bank */
+ res = 1;
+ }
+ }
+ return (res);
+}
diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h
new file mode 100644
index 0000000..63a4032
--- /dev/null
+++ b/board/esd/pf5200/mt46v16m16-75.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x705f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c
new file mode 100644
index 0000000..7a9ed22
--- /dev/null
+++ b/board/esd/pf5200/pf5200.c
@@ -0,0 +1,357 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * pf5200.c - main board support/init for the esd pf5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+#include <netdev.h>
+
+#include "mt46v16m16-75.h"
+
+void init_power_switch(void);
+
+static void sdram_start(int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register: extended mode */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL =
+ SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+ /* set tap delay */
+ *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
+
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+ 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
+ } else {
+#if 0
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
+#else
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+ 0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
+#endif
+ }
+
+#if 0
+ /* find RAM size using SDRAM CS1 only */
+ sdram_start(0);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ sdram_start(1);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ sdram_start(0);
+#endif
+ /* set SDRAM CS1 size according to the amount of RAM found */
+
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+
+ init_power_switch();
+ return (dramsize);
+}
+
+int checkboard(void)
+{
+ puts("Board: esd ParaFinder (pf5200)\n");
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+ if (size == 0x02000000) {
+ /* adjust mapping */
+ *(vu_long *) MPC5XXX_BOOTCS_START =
+ *(vu_long *) MPC5XXX_CS0_START =
+ START_REG(CONFIG_SYS_BOOTCS_START | size);
+ *(vu_long *) MPC5XXX_BOOTCS_STOP =
+ *(vu_long *) MPC5XXX_CS0_STOP =
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+ }
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void) {
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset(void)
+{
+ debug("init_ide_reset\n");
+
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+ debug("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+ } else {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+ }
+}
+#endif
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6 0x40000000UL
+#define GPIO_USB0 0x00010000UL
+#define GPIO_USB9 0x08000000UL
+#define GPIO_USB9S 0x00080000UL
+
+void init_power_switch(void)
+{
+ debug("init_power_switch\n");
+
+ /* Configure GPIO_WU6 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+ __asm__ volatile ("sync");
+
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+ __asm__ volatile ("sync");
+
+ *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+ *(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+ __asm__ volatile ("sync");
+
+ if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+ __asm__ volatile ("sync");
+ }
+ *(vu_char *) CONFIG_SYS_CS1_START = 0x02; /* Red Power LED on */
+ __asm__ volatile ("sync");
+
+ *(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02; /* Disable driver for KB11 */
+ __asm__ volatile ("sync");
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+void power_set_reset(int power)
+{
+ debug("ide_set_reset(%d)\n", power);
+
+ if (power) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6;
+ *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+ } else {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
+ if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
+ 0) {
+ *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |=
+ GPIO_USB0;
+ }
+
+ }
+}
+
+int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ power_set_reset(1);
+ return (0);
+}
+
+U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", "");
+
+int phypower(int flag)
+{
+ u32 addr;
+ vu_long *reg;
+ int status;
+ pci_dev_t dev;
+
+ dev = PCI_BDF(0, 0x18, 0);
+ status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
+ if (status == 0) {
+ reg = (vu_long *) (addr + 0x00000040);
+ *reg |= 0x40000000;
+ __asm__ volatile ("sync");
+
+ reg = (vu_long *) (addr + 0x001000c);
+ *reg |= 0x20000000;
+ __asm__ volatile ("sync");
+
+ reg = (vu_long *) (addr + 0x0010004);
+ if (flag != 0) {
+ *reg &= ~0x20000000;
+ } else {
+ *reg |= 0x20000000;
+ }
+ __asm__ volatile ("sync");
+ }
+ return (status);
+}
+
+int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argv[1][0] == '0')
+ (void)phypower(0);
+ else
+ (void)phypower(1);
+
+ return (0);
+}
+
+U_BOOT_CMD(phypower, 2, 2, do_phypower,
+ "Switch power of ethernet phy", "");
+
+int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int addr;
+ unsigned int size;
+ int i;
+ volatile unsigned long *ptr;
+
+ addr = simple_strtol(argv[1], NULL, 16);
+ size = simple_strtol(argv[2], NULL, 16);
+
+ printf("\nWriting at addr %08x, size %08x.\n", addr, size);
+
+ while (1) {
+ ptr = (volatile unsigned long *)addr;
+ for (i = 0; i < (size >> 2); i++) {
+ *ptr++ = i;
+ }
+
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return 0;
+ }
+ putc('.');
+ }
+ return 0;
+}
+
+U_BOOT_CMD(writepci, 3, 1, do_writepci,
+ "Write some data to pcibus",
+ "<addr> <size>\n"
+ ""
+);
diff --git a/board/esd/plu405/Kconfig b/board/esd/plu405/Kconfig
new file mode 100644
index 0000000..b3082cb
--- /dev/null
+++ b/board/esd/plu405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PLU405
+
+config SYS_BOARD
+ default "plu405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "PLU405"
+
+endif
diff --git a/board/esd/plu405/MAINTAINERS b/board/esd/plu405/MAINTAINERS
new file mode 100644
index 0000000..ccb3658
--- /dev/null
+++ b/board/esd/plu405/MAINTAINERS
@@ -0,0 +1,6 @@
+PLU405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/plu405/
+F: include/configs/PLU405.h
+F: configs/PLU405_defconfig
diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile
new file mode 100644
index 0000000..6ffae67
--- /dev/null
+++ b/board/esd/plu405/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = plu405.o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c
new file mode 100644
index 0000000..23e8164
--- /dev/null
+++ b/board/esd/plu405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b0 = -size_b0;
+ switch (size_b0) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/plu405/fpgadata.c b/board/esd/plu405/fpgadata.c
new file mode 100644
index 0000000..485b9a2
--- /dev/null
+++ b/board/esd/plu405/fpgadata.c
@@ -0,0 +1,2358 @@
+0x1f, 0x8b, 0x08, 0x08, 0x04, 0x44, 0x9f, 0x46,
+0x00, 0x03, 0x70, 0x6c, 0x75, 0x34, 0x30, 0x35,
+0x5f, 0x31, 0x5f, 0x31, 0x2e, 0x62, 0x69, 0x74,
+0x00, 0x94, 0x9a, 0x0f, 0x70, 0x14, 0x55, 0x9e,
+0xc7, 0x7f, 0xfd, 0xba, 0x93, 0x74, 0xa6, 0x3b,
+0xe9, 0x36, 0x7f, 0x30, 0xb7, 0x08, 0xd7, 0x19,
+0x07, 0x76, 0xc4, 0x61, 0x18, 0x42, 0x80, 0x98,
+0x0d, 0x49, 0x33, 0xa4, 0xac, 0x71, 0xc9, 0x1e,
+0xf1, 0xce, 0xbb, 0xe2, 0xf6, 0xbc, 0xdd, 0x11,
+0x71, 0x8f, 0xbb, 0xe2, 0x2c, 0xd6, 0xdd, 0xb3,
+0xb8, 0x3b, 0x4b, 0x5f, 0x66, 0xa2, 0x04, 0x92,
+0x92, 0x01, 0x39, 0x37, 0xba, 0xac, 0x35, 0x40,
+0x6e, 0x8d, 0x4a, 0x59, 0x11, 0x75, 0x8d, 0x82,
+0xbb, 0x4d, 0x0c, 0x3a, 0x60, 0xd4, 0xb9, 0x94,
+0x7b, 0x8b, 0x7f, 0x8e, 0x6d, 0xd8, 0xc0, 0x46,
+0x89, 0x3a, 0xcb, 0xa2, 0x06, 0x65, 0xcd, 0xbd,
+0xd7, 0x3d, 0xdd, 0xd3, 0x99, 0x9e, 0x04, 0x37,
+0x5a, 0xc5, 0x2f, 0xaf, 0x1f, 0x8f, 0xf7, 0xfb,
+0xcd, 0xef, 0xfd, 0x7e, 0x9f, 0xfe, 0xbe, 0x81,
+0x52, 0x29, 0x63, 0xfe, 0x07, 0xc0, 0xdc, 0x06,
+0xd2, 0x96, 0xcd, 0xff, 0x56, 0x1f, 0x5a, 0xfe,
+0xfd, 0xa5, 0xdf, 0x5f, 0x1a, 0xbc, 0xf3, 0xf6,
+0x8d, 0xb0, 0x01, 0x84, 0xba, 0x1f, 0x2d, 0x0f,
+0xdd, 0xf1, 0xe3, 0x1f, 0x2e, 0xad, 0xaf, 0x87,
+0xdb, 0xc9, 0x6f, 0xa1, 0xd0, 0xca, 0x25, 0xe4,
+0xff, 0xa5, 0x37, 0xc0, 0x46, 0x28, 0x5d, 0x5a,
+0xd7, 0xb8, 0xfc, 0x86, 0xc6, 0xa5, 0x2b, 0xe1,
+0x0e, 0x60, 0x96, 0xf5, 0x4d, 0x91, 0x9f, 0x27,
+0x1f, 0xf9, 0xdb, 0x1f, 0x84, 0x00, 0x33, 0x00,
+0x50, 0x12, 0x62, 0xa2, 0xf4, 0x4f, 0x21, 0xc4,
+0x28, 0x0c, 0xe0, 0x96, 0xc5, 0x21, 0xd0, 0xe8,
+0xef, 0x90, 0x7d, 0x5e, 0x1a, 0x02, 0xc5, 0xf9,
+0x3b, 0x13, 0x02, 0x15, 0xda, 0x41, 0xed, 0x81,
+0x0a, 0x19, 0xae, 0xf8, 0xc3, 0xa8, 0x1c, 0xb6,
+0xec, 0x3f, 0x73, 0xfe, 0xd4, 0x09, 0x3c, 0xe3,
+0xb4, 0xdc, 0x4f, 0xcb, 0x85, 0xa4, 0x65, 0xa2,
+0xd0, 0xd7, 0x59, 0x1f, 0xec, 0xf5, 0xdf, 0xfd,
+0x5a, 0xeb, 0x7f, 0x66, 0xad, 0xff, 0xe7, 0xce,
+0x87, 0x8a, 0xaf, 0x31, 0x1d, 0x80, 0xb3, 0xf7,
+0x63, 0x86, 0x87, 0x03, 0x06, 0x43, 0x14, 0x64,
+0x28, 0xa6, 0x86, 0x42, 0x46, 0x10, 0x80, 0x69,
+0x18, 0xeb, 0x0f, 0x5b, 0xf3, 0x87, 0x8a, 0xbe,
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+0x41, 0x39, 0x32, 0x28, 0xe5, 0x63, 0xf8, 0xad,
+0x0e, 0x6b, 0xd6, 0x78, 0x01, 0x9a, 0xe1, 0x57,
+0xa9, 0xb1, 0x11, 0x5d, 0xe4, 0x23, 0xc6, 0xf9,
+0x70, 0xdc, 0x14, 0xf5, 0x10, 0x8b, 0xb7, 0x1e,
+0x1f, 0x4f, 0xb3, 0x74, 0x7c, 0x27, 0x1f, 0x85,
+0x1b, 0xd9, 0x80, 0x2e, 0xa2, 0x7f, 0x6a, 0x02,
+0x34, 0xb8, 0x5f, 0x64, 0xe6, 0xd2, 0xc8, 0x42,
+0x9e, 0x4f, 0x4f, 0x11, 0x0d, 0xce, 0x26, 0x9f,
+0x85, 0xa2, 0x06, 0xab, 0x86, 0x0f, 0x05, 0x45,
+0xca, 0xa6, 0x28, 0x9f, 0x1e, 0x7d, 0xa5, 0x44,
+0x67, 0xf3, 0x86, 0xc6, 0x7a, 0x41, 0x3e, 0x14,
+0xf4, 0x95, 0x3b, 0x6b, 0xb4, 0x31, 0xe0, 0xe4,
+0x73, 0x09, 0x69, 0x50, 0x27, 0xad, 0x18, 0x2e,
+0x21, 0x28, 0xbe, 0x30, 0x58, 0x98, 0xf3, 0x61,
+0x66, 0x54, 0x71, 0x7f, 0x17, 0x4b, 0x72, 0xb5,
+0x3f, 0x9b, 0x9c, 0x09, 0x83, 0xd1, 0x7f, 0x1b,
+0xe7, 0xfa, 0x23, 0x76, 0xae, 0xea, 0x47, 0xc9,
+0x61, 0x4b, 0x83, 0x64, 0x76, 0x8d, 0xf0, 0x44,
+0x66, 0x8d, 0xa9, 0xa4, 0x91, 0x62, 0x7d, 0x8c,
+0x7c, 0xd8, 0x36, 0x58, 0x28, 0x46, 0xa9, 0x99,
+0x19, 0x89, 0xd5, 0xfe, 0x6d, 0x34, 0x17, 0x33,
+0x62, 0x9c, 0xd9, 0x74, 0xea, 0x67, 0x1a, 0xc7,
+0x4c, 0xe4, 0x43, 0x25, 0xd7, 0x45, 0xa2, 0x97,
+0xed, 0x58, 0x3a, 0x87, 0xdb, 0x34, 0xdd, 0xc3,
+0x08, 0xf5, 0x1f, 0xdf, 0xed, 0x3f, 0x0a, 0xcb,
+0xf5, 0x8a, 0x0e, 0x93, 0xda, 0x03, 0xf8, 0x01,
+0xcd, 0xde, 0xa4, 0x16, 0x0a, 0xe4, 0x43, 0xed,
+0x65, 0x26, 0x24, 0x53, 0xac, 0x87, 0x6e, 0x22,
+0xaf, 0xb7, 0xa6, 0xbc, 0xc5, 0x35, 0xd8, 0x90,
+0xc7, 0xc5, 0x3e, 0x1c, 0xd5, 0x82, 0x2d, 0x79,
+0x1d, 0xcd, 0x19, 0xc7, 0x38, 0xf5, 0x2c, 0xbe,
+0x40, 0x1a, 0xf4, 0xa2, 0x0a, 0xce, 0x0b, 0x58,
+0x2d, 0x7b, 0xb0, 0x5a, 0xb0, 0xed, 0x5c, 0x25,
+0x2c, 0xec, 0x89, 0x3b, 0x19, 0x28, 0x3a, 0xf9,
+0x60, 0xfd, 0x34, 0x4d, 0x91, 0xc0, 0x2d, 0xa2,
+0xc1, 0x8d, 0xa5, 0x12, 0x1f, 0xa6, 0xc6, 0xad,
+0x9f, 0x05, 0xa9, 0x86, 0x8d, 0x66, 0xd7, 0xf3,
+0x2b, 0x32, 0xee, 0xfb, 0x68, 0x82, 0x8a, 0x54,
+0xda, 0x6f, 0x76, 0x8c, 0xe9, 0x1b, 0x03, 0xce,
+0xf5, 0xc1, 0xf7, 0xcb, 0xa0, 0x11, 0x4d, 0x78,
+0xf0, 0x4b, 0x13, 0x06, 0x8d, 0x1f, 0x45, 0x5d,
+0x2c, 0x42, 0xac, 0x31, 0x82, 0xa6, 0x19, 0x0f,
+0x8c, 0x51, 0xce, 0xf5, 0xf1, 0xa8, 0xff, 0x10,
+0x1f, 0x82, 0xc2, 0x69, 0x14, 0x70, 0x3e, 0xf5,
+0xe4, 0x82, 0xb0, 0xa0, 0xa8, 0xc6, 0xf8, 0x10,
+0xf3, 0xd9, 0x3f, 0x4d, 0x7c, 0x88, 0xcd, 0x60,
+0x3f, 0x32, 0xd9, 0x7c, 0x0b, 0xf9, 0x10, 0x52,
+0x3e, 0xcc, 0x41, 0xd1, 0xc9, 0x47, 0xec, 0xe8,
+0x3f, 0xa5, 0xb6, 0x93, 0x1b, 0xe7, 0xfa, 0xa8,
+0xca, 0x55, 0x78, 0x08, 0x35, 0xfa, 0xe2, 0x40,
+0x32, 0xf1, 0x30, 0x6b, 0x3b, 0x1e, 0x99, 0xf5,
+0xbc, 0x23, 0x39, 0xf9, 0x24, 0xb8, 0x4d, 0x53,
+0xb8, 0x4d, 0x9a, 0xf6, 0x0b, 0x37, 0x4e, 0xfb,
+0x5b, 0x70, 0x5c, 0xdc, 0xc2, 0x48, 0xbc, 0x95,
+0xfe, 0xcb, 0xe9, 0x3f, 0x31, 0x9e, 0xe0, 0x09,
+0x35, 0xf5, 0x4d, 0xf5, 0x91, 0x7e, 0xba, 0x11,
+0xa9, 0xba, 0x5f, 0x95, 0x30, 0x84, 0x48, 0x79,
+0x64, 0x7e, 0x82, 0x34, 0xe2, 0xd4, 0x33, 0xbe,
+0x53, 0x8f, 0xa9, 0xc9, 0xb8, 0x1a, 0xcb, 0xfb,
+0xd0, 0x3e, 0x3d, 0xa9, 0xaa, 0x0d, 0x5c, 0xd6,
+0x06, 0x2f, 0x46, 0xf3, 0x02, 0xda, 0xaa, 0x4e,
+0x66, 0xd3, 0xc9, 0x67, 0x51, 0x5e, 0x19, 0x86,
+0xd1, 0x52, 0x08, 0xdf, 0xcb, 0x64, 0x80, 0xa6,
+0x1e, 0xa0, 0x19, 0x1a, 0x73, 0x37, 0x33, 0x6e,
+0xff, 0x51, 0xc4, 0x87, 0x83, 0x0a, 0x3d, 0xa7,
+0xdc, 0xf9, 0xd4, 0xd0, 0x89, 0x14, 0xd7, 0xa7,
+0xd7, 0x49, 0xf6, 0x84, 0xb5, 0x25, 0xa1, 0x75,
+0xe7, 0x6b, 0x1f, 0x41, 0xb1, 0x15, 0xdc, 0xcc,
+0xb0, 0xf0, 0x81, 0x1c, 0xe3, 0x43, 0xec, 0x3f,
+0x9d, 0x8b, 0xc1, 0x8c, 0xec, 0x9e, 0xf6, 0xfd,
+0x4e, 0xec, 0x37, 0x64, 0x57, 0x04, 0xca, 0x1a,
+0x08, 0x3a, 0x32, 0x0e, 0x6c, 0xc4, 0xa9, 0x1f,
+0x2a, 0xc0, 0xfc, 0xb9, 0x83, 0xbf, 0x36, 0x81,
+0x25, 0x09, 0xb6, 0x36, 0x45, 0x6e, 0x8a, 0x7a,
+0x00, 0x69, 0xb1, 0x50, 0x95, 0xf9, 0xb0, 0x9f,
+0x19, 0x1b, 0x71, 0xeb, 0x67, 0xa5, 0x7a, 0x41,
+0xdd, 0x7b, 0xde, 0x3a, 0xaa, 0x57, 0x2a, 0x55,
+0xf5, 0xdb, 0xf3, 0x83, 0x47, 0x27, 0x57, 0xc4,
+0x05, 0x34, 0xc7, 0xd0, 0x54, 0x53, 0xe3, 0xe4,
+0x23, 0x90, 0x07, 0x90, 0x0f, 0xf1, 0xa6, 0xff,
+0xf3, 0x1c, 0xdd, 0xfd, 0x2f, 0x37, 0x0b, 0x0c,
+0x78, 0x2b, 0x0f, 0x1c, 0xc9, 0xf8, 0x70, 0xf7,
+0xd9, 0xb3, 0xc4, 0x87, 0xcf, 0xae, 0x1d, 0x31,
+0x7c, 0xf8, 0xc4, 0xf0, 0xe1, 0xef, 0x64, 0x96,
+0x9d, 0xe5, 0x70, 0x2a, 0xe3, 0xc3, 0x93, 0x37,
+0xce, 0x13, 0x1f, 0x6e, 0xbf, 0x3e, 0x65, 0xc0,
+0xec, 0x95, 0xe5, 0xc3, 0x5f, 0xb7, 0x5f, 0x6d,
+0x97, 0x78, 0xec, 0x7d, 0x65, 0xb0, 0xf0, 0xe5,
+0x3a, 0x1e, 0xf6, 0xdf, 0x14, 0x14, 0xe7, 0x1e,
+0x2f, 0x93, 0x31, 0x7c, 0x68, 0x22, 0xdf, 0xba,
+0xeb, 0x0d, 0x16, 0xfe, 0xf3, 0x37, 0xa5, 0x91,
+0x81, 0xe2, 0x0d, 0x63, 0x2c, 0x1f, 0x52, 0xa4,
+0xc4, 0xab, 0x27, 0x33, 0x3e, 0x3c, 0xb0, 0xef,
+0xdc, 0x9f, 0x77, 0xda, 0xb4, 0xfe, 0xbb, 0x73,
+0xa3, 0xcf, 0xe9, 0x85, 0x39, 0x6a, 0x7e, 0x78,
+0xf6, 0x11, 0x8e, 0x58, 0xf8, 0xb6, 0xc6, 0xbf,
+0x8b, 0xf5, 0x0f, 0x3f, 0x0a, 0x8b, 0xc5, 0x62,
+0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0xfa, 0xd4,
+0x65, 0x66, 0x07, 0xc9, 0xb3, 0x03, 0x8b, 0xc5,
+0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x7a,
+0xb7, 0xcc, 0xec, 0x50, 0xe3, 0xd9, 0x81, 0xc5,
+0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62,
+0xbd, 0x5b, 0x66, 0x76, 0xf0, 0xcc, 0xec, 0xf0,
+0xb1, 0x53, 0x61, 0xb1, 0x58, 0x2c, 0x16, 0x8b,
+0xc5, 0x62, 0xb1, 0x58, 0xff, 0xa3, 0x22, 0xfa,
+0x7d, 0x1c, 0x3c, 0xfb, 0x23, 0x02, 0x4d, 0xbf,
+0x5a, 0xa9, 0x46, 0xa0, 0xde, 0xfb, 0xf3, 0x84,
+0xf4, 0xb5, 0x13, 0x11, 0x6c, 0x88, 0xe2, 0x98,
+0x7f, 0x7d, 0xb9, 0x73, 0xdd, 0x1b, 0x3b, 0x1c,
+0x29, 0xc2, 0xf0, 0x33, 0x01, 0x00,
diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
new file mode 100644
index 0000000..03bf9c8
--- /dev/null
+++ b/board/esd/plu405/plu405.c
@@ -0,0 +1,345 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <sja1000.h>
+
+#undef FPGA_DEBUG
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+/*
+ * generate a short spike on the CAN tx line
+ * to bring the couplers in sync
+ */
+void init_coupler(u32 addr)
+{
+ struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
+
+ /* reset */
+ out_8(&ctrl->cr, CR_RR);
+
+ /* dominant */
+ out_8(&ctrl->btr0, 0x00); /* btr setup is required */
+ out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
+ out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
+ OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
+ out_8(&ctrl->cr, 0x00);
+
+ /* delay */
+ in_8(&ctrl->cr);
+ in_8(&ctrl->cr);
+ in_8(&ctrl->cr);
+ in_8(&ctrl->cr);
+
+ /* reset */
+ out_8(&ctrl->cr, CR_RR);
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to
+ * 512 ebc-clks -> ca. 15 us
+ */
+ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ unsigned char *dst;
+ unsigned char fctr;
+ ulong len = sizeof(fpgadata);
+ int status;
+ int index;
+ int i;
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
+ (uchar *)fpgadata, &len) != 0) {
+ printf("GUNZIP ERROR - must RESET board to recover\n");
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ status = fpga_boot(dst, len);
+ if (status != 0) {
+ printf("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf("(Timeout: INIT not low "
+ "after asserting PROGRAM*)\n");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf("(Timeout: INIT not high "
+ "after deasserting PROGRAM*)\n");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf("(Timeout: DONE not high "
+ "after programming FPGA)\n");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("FPGA: %s\n", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+ /* delayed reboot */
+ for (i=20; i>0; i--) {
+ printf("Rebooting in %2d seconds \r",i);
+ for (index=0;index<1000;index++)
+ udelay(1000);
+ }
+ putc('\n');
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ puts("FPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("%s ", &(dst[index+1]));
+ index += len+3;
+ }
+ putc('\n');
+
+ free(dst);
+
+ /*
+ * Reset FPGA via FPGA_DATA pin
+ */
+ SET_FPGA(FPGA_PRG | FPGA_CLK);
+ udelay(1000); /* wait 1ms */
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+ udelay(1000); /* wait 1ms */
+
+ /*
+ * Reset external DUARTs
+ */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
+ udelay(10);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
+ udelay(1000);
+
+ /*
+ * Set NAND-FLASH GPIO signals to default
+ */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) &
+ ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+
+ /*
+ * Setup EEPROM write protection
+ */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ out_be32((void*)GPIO0_TCR,
+ in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
+
+ /*
+ * Enable interrupts in exar duart mcr[3]
+ */
+ out_8((void *)DUART0_BA + 4, 0x08);
+ out_8((void *)DUART1_BA + 4, 0x08);
+
+ /*
+ * Enable auto RS485 mode in 2nd external uart
+ */
+ out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
+ fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
+ fctr |= 0x08; /* enable RS485 mode */
+ out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
+ out_8((void *)DUART1_BA + 3, 0); /* write LCR */
+
+ /*
+ * Init magnetic couplers
+ */
+ if (!getenv("noinitcoupler")) {
+ init_coupler(CAN0_BA);
+ init_coupler(CAN1_BA);
+ }
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts("Board: ");
+
+ if (i == -1)
+ puts("### No HW ID - assuming PLU405");
+ else
+ puts(str);
+
+ putc('\n');
+ return 0;
+}
+
+#ifdef CONFIG_IDE_RESET
+#define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
+void ide_set_reset(int on)
+{
+ /*
+ * Assert or deassert CompactFlash Reset Pin
+ */
+ if (on) { /* assert RESET */
+ out_be16((void *)FPGA_CTRL,
+ in_be16((void *)FPGA_CTRL) &
+ ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
+ } else { /* release RESET */
+ out_be16((void *)FPGA_CTRL,
+ in_be16((void *)FPGA_CTRL) |
+ CONFIG_SYS_FPGA_CTRL_CF_RESET);
+ }
+}
+#endif /* CONFIG_IDE_RESET */
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO0. */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) &
+ ~CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO0. */
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) |
+ CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = ((in_be32((void*)GPIO0_OR) &
+ CONFIG_SYS_EEPROM_WP) == 0);
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts("Query of write access state failed.\n");
+ } else {
+ printf("Write access for device 0x%0x is %sabled.\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if (argv[1][0] == '0') {
+ /* Disable write access. */
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
+ 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
+ 1);
+ }
+ if (state < 0)
+ puts("Setup of write access state failed.\n");
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "Enable / disable / query EEPROM write access",
+ ""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/pmc405/Kconfig b/board/esd/pmc405/Kconfig
new file mode 100644
index 0000000..3738c68
--- /dev/null
+++ b/board/esd/pmc405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PMC405
+
+config SYS_BOARD
+ default "pmc405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "PMC405"
+
+endif
diff --git a/board/esd/pmc405/MAINTAINERS b/board/esd/pmc405/MAINTAINERS
new file mode 100644
index 0000000..148a596
--- /dev/null
+++ b/board/esd/pmc405/MAINTAINERS
@@ -0,0 +1,6 @@
+PMC405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/pmc405/
+F: include/configs/PMC405.h
+F: configs/PMC405_defconfig
diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile
new file mode 100644
index 0000000..ad98207
--- /dev/null
+++ b/board/esd/pmc405/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD = ../common/xilinx_jtag/lenval.o \
+ ../common/xilinx_jtag/micro.o \
+ ../common/xilinx_jtag/ports.o
+
+obj-y = pmc405.o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)
diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
new file mode 100644
index 0000000..e67ff30
--- /dev/null
+++ b/board/esd/pmc405/pmc405.c
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2005-2009
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+int board_early_init_f (void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register:
+ * set ready timeout to 512 ebc-clks -> ca. 15 us
+ */
+ mtebc (EBC0_CFG, 0xa8400000);
+
+ /*
+ * Setup GPIO pins
+ */
+ mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT |
+ CONFIG_SYS_FPGA_DONE |
+ CONFIG_SYS_XEREADY |
+ CONFIG_SYS_NONMONARCH |
+ CONFIG_SYS_REV1_2) << 5));
+
+ if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
+ /* rev 1.2 boards */
+ mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE |
+ CONFIG_SYS_SELF_RST) << 5));
+ }
+
+ out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN);
+ /* setup for output */
+ out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
+ CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
+
+ /*
+ * - check if rev1_2 is low, then:
+ * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST
+ * in TCR to assert INTA# or SELFRST#
+ */
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /* deassert EREADY# */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY);
+ return (0);
+}
+
+ushort pmc405_pci_subsys_deviceid(void)
+{
+ ulong val;
+
+ val = in_be32((void *)GPIO0_IR);
+ if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
+ /* check monarch# signal */
+ if (val & CONFIG_SYS_NONMONARCH)
+ return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
+ return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
+ }
+ return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard (void)
+{
+ ulong val;
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1)
+ puts ("### No HW ID - assuming PMC405");
+ else
+ puts(str);
+
+ val = in_be32((void *)GPIO0_IR);
+ if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
+ puts(" rev1.2 (");
+ if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
+ puts("non-");
+ puts("monarch)");
+ } else
+ puts(" <=rev1.1");
+
+ putc ('\n');
+
+ return 0;
+}
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
diff --git a/board/esd/pmc405de/Kconfig b/board/esd/pmc405de/Kconfig
new file mode 100644
index 0000000..4b05787
--- /dev/null
+++ b/board/esd/pmc405de/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PMC405DE
+
+config SYS_BOARD
+ default "pmc405de"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "PMC405DE"
+
+endif
diff --git a/board/esd/pmc405de/MAINTAINERS b/board/esd/pmc405de/MAINTAINERS
new file mode 100644
index 0000000..a891e23
--- /dev/null
+++ b/board/esd/pmc405de/MAINTAINERS
@@ -0,0 +1,6 @@
+PMC405DE BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/pmc405de/
+F: include/configs/PMC405DE.h
+F: configs/PMC405DE_defconfig
diff --git a/board/esd/pmc405de/Makefile b/board/esd/pmc405de/Makefile
new file mode 100644
index 0000000..b3f6dcd
--- /dev/null
+++ b/board/esd/pmc405de/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = pmc405de.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+obj-y += ../common/cmd_loadpci.o
diff --git a/board/esd/pmc405de/chip_config.c b/board/esd/pmc405de/chip_config.c
new file mode 100644
index 0000000..c06a6ae
--- /dev/null
+++ b/board/esd/pmc405de/chip_config.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "133",
+ "CPU: 133 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
+ {
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x40, 0x12, 0x12, 0x42, 0x3e, 0x00, 0x00
+ }
+ },
+ {
+ "266",
+ "CPU: 266 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
+ {
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x50, 0x22, 0x2d, 0x42, 0x3e, 0x00, 0x00
+ }
+ },
+ {
+ "333",
+ "CPU: 333 PLB: 111 OPB: 55 EBC: 55 PCI: 55/111",
+ {
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x60, 0x29, 0x2d, 0x42, 0xbe, 0x00, 0x00
+ }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c
new file mode 100644
index 0000000..3e17132
--- /dev/null
+++ b/board/esd/pmc405de/pmc405de.c
@@ -0,0 +1,506 @@
+/*
+ * (C) Copyright 2009
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/4xx_pci.h>
+#include <command.h>
+#include <malloc.h>
+
+/*
+ * PMC405-DE cpld registers
+ * - all registers are 8 bit
+ * - all registers are on 32 bit addesses
+ */
+struct pmc405de_cpld {
+ /* cpld design version */
+ u8 version;
+ u8 reserved0[3];
+
+ /* misc. status lines */
+ u8 status;
+ u8 reserved1[3];
+
+ /*
+ * gated control flags
+ * gate bit(s) must be written with '1' to
+ * access control flag
+ */
+ u8 control;
+ u8 reserved2[3];
+};
+
+#define CPLD_VERSION_MASK 0x0f
+#define CPLD_CONTROL_POSTLED_N 0x01
+#define CPLD_CONTROL_POSTLED_GATE 0x02
+#define CPLD_CONTROL_RESETOUT_N 0x40
+#define CPLD_CONTROL_RESETOUT_N_GATE 0x80
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void __ft_board_setup(void *blob, bd_t *bd);
+extern void pll_write(u32 a, u32 b);
+
+static int wait_for_pci_ready_done;
+
+static int is_monarch(void);
+static int pci_is_66mhz(void);
+static int board_revision(void);
+static int cpld_revision(void);
+static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div);
+
+int board_early_init_f(void)
+{
+ u32 pllmr0, pllmr1;
+
+ /*
+ * check M66EN and patch PLB:PCI divider for 66MHz PCI
+ *
+ * fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1
+ * fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2
+ * fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2
+ * fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3
+ *
+ * calling upd_plb_pci_div() may end in calling pll_write() which will
+ * do a chip reset and never return.
+ */
+ pllmr0 = mfdcr(CPC0_PLLMR0);
+ pllmr1 = mfdcr(CPC0_PLLMR1);
+
+ if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) {
+ /* fCPU=333MHz, fPLB=111MHz */
+ if (pci_is_66mhz())
+ upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1);
+ else
+ upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
+ } else {
+ /* fCPU=133|266MHz, fPLB=133MHz */
+ if (pci_is_66mhz())
+ upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
+ else
+ upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3);
+ }
+
+ /*
+ * IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest prio */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register:
+ * - set ready timeout to 512 ebc-clks -> ca. 15 us
+ * - EBC lines are always driven
+ */
+ mtebc(EBC0_CFG, 0xa8400000);
+
+ return 0;
+}
+
+static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div)
+{
+ if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div)
+ pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1);
+}
+
+int misc_init_r(void)
+{
+ int i;
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+ struct pmc405de_cpld *cpld =
+ (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
+
+ if (!is_monarch()) {
+ /* PCI configuration done: release EREADY */
+ setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY);
+ setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY);
+ }
+
+ /* turn off POST LED */
+ out_8(&cpld->control,
+ CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE);
+
+ /* turn on LEDs: RUN, A, B */
+ clrbits_be32(&gpio0->or,
+ CONFIG_SYS_GPIO_LEDRUN_N |
+ CONFIG_SYS_GPIO_LEDA_N |
+ CONFIG_SYS_GPIO_LEDB_N);
+
+ for (i=0; i < 200; i++)
+ udelay(1000);
+
+ /* turn off LEDs: A, B */
+ setbits_be32(&gpio0->or,
+ CONFIG_SYS_GPIO_LEDA_N |
+ CONFIG_SYS_GPIO_LEDB_N);
+
+ return (0);
+}
+
+static int is_monarch(void)
+{
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+ return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0;
+}
+
+static int pci_is_66mhz(void)
+{
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+ return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN);
+}
+
+static int board_revision(void)
+{
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+ return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >>
+ CONFIG_SYS_GPIO_HWREV_SHIFT);
+}
+
+static int cpld_revision(void)
+{
+ struct pmc405de_cpld *cpld =
+ (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
+ return ((in_8(&cpld->version) & CPLD_VERSION_MASK));
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard(void)
+{
+ puts("Board: esd GmbH - PMC-CPU/405-DE");
+
+ gd->board_type = board_revision();
+ printf(", Rev 1.%ld, ", gd->board_type);
+
+ if (!is_monarch())
+ puts("non-");
+
+ printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n",
+ pci_is_66mhz() ? "66" : "33", cpld_revision());
+
+ return 0;
+}
+
+
+static void wait_for_pci_ready(void)
+{
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+ int i;
+ char *s = getenv("pcidelay");
+
+ /* only wait once */
+ if (wait_for_pci_ready_done)
+ return;
+
+ /*
+ * We have our own handling of the pcidelay variable.
+ * Using CONFIG_PCI_BOOTDELAY enables pausing for host
+ * and adapter devices. For adapter devices we do not
+ * want this.
+ */
+ if (s) {
+ int ms = simple_strtoul(s, NULL, 10);
+ printf("PCI: Waiting for %d ms\n", ms);
+ for (i=0; i<ms; i++)
+ udelay(1000);
+ }
+
+ if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) {
+ printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
+ while (1) {
+ if (ctrlc()) {
+ puts("abort\n");
+ break;
+ }
+ if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) {
+ printf("done\n");
+ break;
+ }
+ }
+ }
+
+ wait_for_pci_ready_done = 1;
+}
+
+/*
+ * Overwrite weak is_pci_host()
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+int is_pci_host(struct pci_controller *hose)
+{
+ char *s;
+
+ if (!is_monarch()) {
+ /*
+ * Overwrite PCI identification when running in
+ * non-monarch mode
+ * This should be moved into pci_target_init()
+ * when it is sometimes available for 405 CPUs
+ */
+ pci_write_config_word(PCIDEVID_405GP,
+ PCI_SUBSYSTEM_ID,
+ CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
+ pci_write_config_word(PCIDEVID_405GP,
+ PCI_CLASS_SUB_CODE,
+ CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
+ }
+
+ s = getenv("pciscan");
+ if (s == NULL) {
+ if (is_monarch()) {
+ wait_for_pci_ready();
+ return 1;
+ } else {
+ return 0;
+ }
+ } else {
+ if (!strcmp(s, "yes"))
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
+ * Overwrite weak pci_pre_init()
+ *
+ * The default implementation enables the 405EP
+ * internal PCI arbiter. We do not want that
+ * on a PMC module.
+ */
+int pci_pre_init(struct pci_controller *hose)
+{
+ return 1;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int rc;
+
+ __ft_board_setup(blob, bd);
+
+ /*
+ * Disable PCI in non-monarch mode.
+ */
+ if (!is_monarch()) {
+ rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
+ "disabled", sizeof("disabled"), 1);
+ if (rc) {
+ printf("Unable to update property status in PCI node, "
+ "err=%s\n",
+ fdt_strerror(rc));
+ }
+ }
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO0. */
+ clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO0. */
+ setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32(&gpio0->or) &
+ CONFIG_SYS_GPIO_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1);
+ if (state < 0) {
+ puts("Query of write access state failed.\n");
+ } else {
+ printf("Write access for device 0x%0x is %sabled.\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable(
+ CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable(
+ CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0)
+ puts ("Setup of write access state failed.\n");
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "Enable / disable / query EEPROM write access",
+ ""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+#if defined(CONFIG_PRAM)
+#include <environment.h>
+
+int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 pram, nextbase, base;
+ char *v;
+ u32 param;
+ ulong *lptr;
+
+ v = getenv("pram");
+ if (v)
+ pram = simple_strtoul(v, NULL, 10);
+ else {
+ printf("Error: pram undefined. Please define pram in KiB\n");
+ return 1;
+ }
+
+ base = gd->bd->bi_memsize;
+#if defined(CONFIG_LOGBUFFER)
+ base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
+#endif
+ /*
+ * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE
+ */
+ param = base - (pram << 10);
+ printf("PARAM: @%08x\n", param);
+ debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
+
+ /* clear entire PA ram */
+ memset((void*)param, 0, (pram << 10));
+
+ /* reserve 4k for pointer field */
+ nextbase = base - 4096;
+ lptr = (ulong*)(base);
+
+ /*
+ * *(--lptr) = item_size;
+ * *(--lptr) = base - item_base = distance from field top;
+ */
+
+ /* env is first (4k aligned) */
+ nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
+ memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
+ *(--lptr) = CONFIG_ENV_SIZE; /* size */
+ *(--lptr) = base - nextbase; /* offset | type=0 */
+
+ /* free section */
+ *(--lptr) = nextbase - param; /* size */
+ *(--lptr) = (base - param) | 126; /* offset | type=126 */
+
+ /* terminate pointer field */
+ *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
+ *(--lptr) = 0; /* offset=0 -> terminator */
+ return 0;
+}
+U_BOOT_CMD(
+ painit, 1, 1, do_painit,
+ "prepare PciAccess system",
+ ""
+);
+#endif /* CONFIG_PRAM */
+
+int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
+ setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N);
+ return 0;
+}
+U_BOOT_CMD(
+ selfreset, 1, 1, do_selfreset,
+ "assert self-reset# signal",
+ ""
+);
+
+int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct pmc405de_cpld *cpld =
+ (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
+
+ if (argc > 1) {
+ if (argv[1][0] == '0') {
+ /* assert */
+ printf("PMC-RESETOUT# asserted\n");
+ out_8(&cpld->control,
+ CPLD_CONTROL_RESETOUT_N_GATE);
+ } else {
+ /* deassert */
+ printf("PMC-RESETOUT# deasserted\n");
+ out_8(&cpld->control,
+ CPLD_CONTROL_RESETOUT_N |
+ CPLD_CONTROL_RESETOUT_N_GATE);
+ }
+ } else {
+ printf("PMC-RESETOUT# is %s\n",
+ (in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ?
+ "inactive" : "active");
+ }
+ return 0;
+}
+U_BOOT_CMD(
+ resetout, 2, 1, do_resetout,
+ "assert PMC-RESETOUT# signal",
+ ""
+);
diff --git a/board/esd/pmc440/Kconfig b/board/esd/pmc440/Kconfig
new file mode 100644
index 0000000..df8bd65
--- /dev/null
+++ b/board/esd/pmc440/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PMC440
+
+config SYS_BOARD
+ default "pmc440"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "PMC440"
+
+endif
diff --git a/board/esd/pmc440/MAINTAINERS b/board/esd/pmc440/MAINTAINERS
new file mode 100644
index 0000000..32fb9ba
--- /dev/null
+++ b/board/esd/pmc440/MAINTAINERS
@@ -0,0 +1,6 @@
+PMC440 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/pmc440/
+F: include/configs/PMC440.h
+F: configs/PMC440_defconfig
diff --git a/board/esd/pmc440/Makefile b/board/esd/pmc440/Makefile
new file mode 100644
index 0000000..708e9d1
--- /dev/null
+++ b/board/esd/pmc440/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = pmc440.o cmd_pmc440.o sdram.o fpga.o \
+ ../common/cmd_loadpci.o
+extra-y += init.o
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
new file mode 100644
index 0000000..40b135f
--- /dev/null
+++ b/board/esd/pmc440/cmd_pmc440.c
@@ -0,0 +1,553 @@
+/*
+ * (C) Copyright 2007-2008
+ * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/processor.h>
+#if defined(CONFIG_LOGBUFFER)
+#include <logbuff.h>
+#endif
+
+#include "pmc440.h"
+
+int is_monarch(void);
+int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
+ uchar *buffer, unsigned cnt);
+int eeprom_write_enable(unsigned dev_addr, int state);
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_BSP)
+
+static int got_fifoirq;
+static int got_hcirq;
+
+int fpga_interrupt(u32 arg)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
+ int rc = -1; /* not for us */
+ u32 status = FPGA_IN32(&fpga->status);
+
+ /* check for interrupt from fifo module */
+ if (status & STATUS_FIFO_ISF) {
+ /* disable this int source */
+ FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
+ rc = 0;
+ got_fifoirq = 1; /* trigger backend */
+ }
+
+ if (status & STATUS_HOST_ISF) {
+ FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
+ rc = 0;
+ got_hcirq = 1;
+ }
+
+ return rc;
+}
+
+int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ got_hcirq = 0;
+
+ FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
+ FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
+
+ irq_install_handler(IRQ0_FPGA,
+ (interrupt_handler_t *)fpga_interrupt,
+ fpga);
+
+ FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
+
+ while (!got_hcirq) {
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ break;
+ }
+ }
+ if (got_hcirq)
+ printf("Got interrupt!\n");
+
+ FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
+ irq_free_handler(IRQ0_FPGA);
+ return 0;
+}
+U_BOOT_CMD(
+ waithci, 1, 1, do_waithci,
+ "Wait for host control interrupt",
+ ""
+);
+
+void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
+{
+ u32 ctrl;
+
+ while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
+ printf("%5d %d %3d %08x",
+ (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
+ FPGA_IN32(&fpga->fifo[f].data));
+ if (ctrl & FIFO_OVERFLOW) {
+ printf(" OVERFLOW\n");
+ FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
+ } else
+ printf("\n");
+ }
+}
+
+int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+ int i;
+ int n = 0;
+ u32 ctrl, data, f;
+ char str[] = "\\|/-";
+ int abort = 0;
+ int count = 0;
+ int count2 = 0;
+
+ switch (argc) {
+ case 1:
+ /* print all fifos status information */
+ printf("fifo level status\n");
+ printf("______________________________\n");
+ for (i=0; i<FIFO_COUNT; i++) {
+ ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
+ printf(" %d %3d %s%s%s %s\n",
+ i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
+ ctrl & FIFO_FULL ? "FULL " : "",
+ ctrl & FIFO_EMPTY ? "EMPTY " : "",
+ ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
+ ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
+ }
+ break;
+
+ case 2:
+ /* completely read out fifo 'n' */
+ if (!strcmp(argv[1],"read")) {
+ printf(" # fifo level data\n");
+ printf("______________________________\n");
+
+ for (i=0; i<FIFO_COUNT; i++)
+ dump_fifo(fpga, i, &n);
+
+ } else if (!strcmp(argv[1],"wait")) {
+ got_fifoirq = 0;
+
+ irq_install_handler(IRQ0_FPGA,
+ (interrupt_handler_t *)fpga_interrupt,
+ fpga);
+
+ printf(" # fifo level data\n");
+ printf("______________________________\n");
+
+ /* enable all fifo interrupts */
+ FPGA_OUT32(&fpga->hostctrl,
+ HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
+ for (i=0; i<FIFO_COUNT; i++) {
+ /* enable interrupts from all fifos */
+ FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
+ }
+
+ while (1) {
+ /* wait loop */
+ while (!got_fifoirq) {
+ count++;
+ if (!(count % 100)) {
+ count2++;
+ putc(0x08); /* backspace */
+ putc(str[count2 % 4]);
+ }
+
+ /* Abort if ctrl-c was pressed */
+ if ((abort = ctrlc())) {
+ puts("\nAbort\n");
+ break;
+ }
+ udelay(1000);
+ }
+ if (abort)
+ break;
+
+ /* simple fifo backend */
+ if (got_fifoirq) {
+ for (i=0; i<FIFO_COUNT; i++)
+ dump_fifo(fpga, i, &n);
+
+ got_fifoirq = 0;
+ /* unmask global fifo irq */
+ FPGA_OUT32(&fpga->hostctrl,
+ HOSTCTRL_FIFOIE_GATE |
+ HOSTCTRL_FIFOIE_FLAG);
+ }
+ }
+
+ /* disable all fifo interrupts */
+ FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
+ for (i=0; i<FIFO_COUNT; i++)
+ FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
+
+ irq_free_handler(IRQ0_FPGA);
+
+ } else {
+ printf("Usage:\nfifo %s\n", cmdtp->help);
+ return 1;
+ }
+ break;
+
+ case 4:
+ case 5:
+ if (!strcmp(argv[1],"write")) {
+ /* get fifo number or fifo address */
+ f = simple_strtoul(argv[2], NULL, 16);
+
+ /* data paramter */
+ data = simple_strtoul(argv[3], NULL, 16);
+
+ /* get optional count parameter */
+ n = 1;
+ if (argc >= 5)
+ n = (int)simple_strtoul(argv[4], NULL, 10);
+
+ if (f < FIFO_COUNT) {
+ printf("writing %d x %08x to fifo %d\n",
+ n, data, f);
+ for (i=0; i<n; i++)
+ FPGA_OUT32(&fpga->fifo[f].data, data);
+ } else {
+ printf("writing %d x %08x to fifo port at "
+ "address %08x\n",
+ n, data, f);
+ for (i=0; i<n; i++)
+ out_be32((void *)f, data);
+ }
+ } else {
+ printf("Usage:\nfifo %s\n", cmdtp->help);
+ return 1;
+ }
+ break;
+
+ default:
+ printf("Usage:\nfifo %s\n", cmdtp->help);
+ return 1;
+ }
+ return 0;
+}
+U_BOOT_CMD(
+ fifo, 5, 1, do_fifo,
+ "Fifo module operations",
+ "wait\nfifo read\n"
+ "fifo write fifo(0..3) data [cnt=1]\n"
+ "fifo write address(>=4) data [cnt=1]\n"
+ " - without arguments: print all fifo's status\n"
+ " - with 'wait' argument: interrupt driven read from all fifos\n"
+ " - with 'read' argument: read current contents from all fifos\n"
+ " - with 'write' argument: write 'data' 'cnt' times to "
+ "'fifo' or 'address'"
+);
+
+int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong sdsdp[5];
+ ulong delay;
+ int count=16;
+
+ if (argc < 2) {
+ printf("Usage:\nsbe %s\n", cmdtp->help);
+ return -1;
+ }
+
+ if (argc > 1) {
+ if (!strcmp(argv[1], "400")) {
+ /* PLB=133MHz, PLB/PCI=3 */
+ printf("Bootstrapping for 400MHz\n");
+ sdsdp[0]=0x8678624e;
+ sdsdp[1]=0x095fa030;
+ sdsdp[2]=0x40082350;
+ sdsdp[3]=0x0d050000;
+ } else if (!strcmp(argv[1], "533")) {
+ /* PLB=133MHz, PLB/PCI=3 */
+ printf("Bootstrapping for 533MHz\n");
+ sdsdp[0]=0x87788252;
+ sdsdp[1]=0x095fa030;
+ sdsdp[2]=0x40082350;
+ sdsdp[3]=0x0d050000;
+ } else if (!strcmp(argv[1], "667")) {
+ /* PLB=133MHz, PLB/PCI=3 */
+ printf("Bootstrapping for 667MHz\n");
+ sdsdp[0]=0x8778a256;
+ sdsdp[1]=0x095fa030;
+ sdsdp[2]=0x40082350;
+ sdsdp[3]=0x0d050000;
+ } else {
+ printf("Usage:\nsbe %s\n", cmdtp->help);
+ return -1;
+ }
+ }
+
+ if (argc > 2) {
+ sdsdp[4] = 0;
+ if (argv[2][0]=='1')
+ sdsdp[4]=0x19750100;
+ else if (argv[2][0]=='0')
+ sdsdp[4]=0x19750000;
+ if (sdsdp[4])
+ count += 4;
+ }
+
+ if (argc > 3) {
+ delay = simple_strtoul(argv[3], NULL, 10);
+ if (delay > 20)
+ delay = 20;
+ sdsdp[4] |= delay;
+ }
+
+ printf("Writing boot EEPROM ...\n");
+ if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
+ 0, (uchar*)sdsdp, count) != 0)
+ printf("bootstrap_eeprom_write failed\n");
+ else
+ printf("done (dump via 'i2c md 52 0.1 14')\n");
+
+ return 0;
+}
+U_BOOT_CMD(
+ sbe, 4, 0, do_setup_bootstrap_eeprom,
+ "setup bootstrap eeprom",
+ "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
+);
+
+#if defined(CONFIG_PRAM)
+#include <environment.h>
+#include <search.h>
+#include <errno.h>
+
+int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 pram, nextbase, base;
+ char *v;
+ u32 param;
+ ulong *lptr;
+
+ env_t *envp;
+ char *res;
+ int len;
+
+ v = getenv("pram");
+ if (v)
+ pram = simple_strtoul(v, NULL, 10);
+ else {
+ printf("Error: pram undefined. Please define pram in KiB\n");
+ return 1;
+ }
+
+ base = (u32)gd->ram_size;
+#if defined(CONFIG_LOGBUFFER)
+ base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
+#endif
+ /*
+ * gd->ram_size == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
+ */
+ param = base - (pram << 10);
+ printf("PARAM: @%08x\n", param);
+ debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->ram_size, base);
+
+ /* clear entire PA ram */
+ memset((void*)param, 0, (pram << 10));
+
+ /* reserve 4k for pointer field */
+ nextbase = base - 4096;
+ lptr = (ulong*)(base);
+
+ /*
+ * *(--lptr) = item_size;
+ * *(--lptr) = base - item_base = distance from field top;
+ */
+
+ /* env is first (4k aligned) */
+ nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
+ envp = (env_t *)nextbase;
+ res = (char *)envp->data;
+ len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
+ if (len < 0) {
+ error("Cannot export environment: errno = %d\n", errno);
+ return 1;
+ }
+ envp->crc = crc32(0, envp->data, ENV_SIZE);
+
+ *(--lptr) = CONFIG_ENV_SIZE; /* size */
+ *(--lptr) = base - nextbase; /* offset | type=0 */
+
+ /* free section */
+ *(--lptr) = nextbase - param; /* size */
+ *(--lptr) = (base - param) | 126; /* offset | type=126 */
+
+ /* terminate pointer field */
+ *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
+ *(--lptr) = 0; /* offset=0 -> terminator */
+ return 0;
+}
+U_BOOT_CMD(
+ painit, 1, 1, do_painit,
+ "prepare PciAccess system",
+ ""
+);
+#endif /* CONFIG_PRAM */
+
+int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ in_be32((void*)CONFIG_SYS_RESET_BASE);
+ return 0;
+}
+U_BOOT_CMD(
+ selfreset, 1, 1, do_selfreset,
+ "assert self-reset# signal",
+ ""
+);
+
+int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ /* requiers bootet FPGA and PLD_IOEN_N active */
+ if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
+ printf("Error: resetout requires a bootet FPGA\n");
+ return -1;
+ }
+
+ if (argc > 1) {
+ if (argv[1][0] == '0') {
+ /* assert */
+ printf("PMC-RESETOUT# asserted\n");
+ FPGA_OUT32(&fpga->hostctrl,
+ HOSTCTRL_PMCRSTOUT_GATE);
+ } else {
+ /* deassert */
+ printf("PMC-RESETOUT# deasserted\n");
+ FPGA_OUT32(&fpga->hostctrl,
+ HOSTCTRL_PMCRSTOUT_GATE |
+ HOSTCTRL_PMCRSTOUT_FLAG);
+ }
+ } else {
+ printf("PMC-RESETOUT# is %s\n",
+ FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
+ "inactive" : "active");
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ resetout, 2, 1, do_resetout,
+ "assert PMC-RESETOUT# signal",
+ ""
+);
+
+int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (is_monarch()) {
+ printf("This command is only supported in non-monarch mode\n");
+ return -1;
+ }
+
+ if (argc > 1) {
+ if (argv[1][0] == '0') {
+ /* assert */
+ printf("inta# asserted\n");
+ out_be32((void*)GPIO1_TCR,
+ in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
+ } else {
+ /* deassert */
+ printf("inta# deasserted\n");
+ out_be32((void*)GPIO1_TCR,
+ in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
+ }
+ } else {
+ printf("inta# is %s\n",
+ in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
+ "active" : "inactive");
+ }
+ return 0;
+}
+U_BOOT_CMD(
+ inta, 2, 1, do_inta,
+ "Assert/Deassert or query INTA# state in non-monarch mode",
+ ""
+);
+
+/* test-only */
+int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong pciaddr;
+
+ if (argc > 1) {
+ pciaddr = simple_strtoul(argv[1], NULL, 16);
+
+ pciaddr &= 0xf0000000;
+
+ /* map PCI address at 0xc0000000 in PLB space */
+
+ /* PMM1 Mask/Attribute - disabled b4 setting */
+ out32r(PCIL0_PMM1MA, 0x00000000);
+ /* PMM1 Local Address */
+ out32r(PCIL0_PMM1LA, 0xc0000000);
+ /* PMM1 PCI Low Address */
+ out32r(PCIL0_PMM1PCILA, pciaddr);
+ /* PMM1 PCI High Address */
+ out32r(PCIL0_PMM1PCIHA, 0x00000000);
+ /* 256MB + No prefetching, and enable region */
+ out32r(PCIL0_PMM1MA, 0xf0000001);
+ } else {
+ printf("Usage:\npmm %s\n", cmdtp->help);
+ }
+ return 0;
+}
+U_BOOT_CMD(
+ pmm, 2, 1, do_pmm,
+ "Setup pmm[1] registers",
+ "<pciaddr> (pciaddr will be aligned to 256MB)"
+);
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts("Query of write access state failed.\n");
+ } else {
+ printf("Write access for device 0x%0x is %sabled.\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0) {
+ puts("Setup of write access state failed.\n");
+ }
+ }
+
+ return state;
+}
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "Enable / disable / query EEPROM write access",
+ ""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+#endif /* CONFIG_CMD_BSP */
diff --git a/board/esd/pmc440/config.mk b/board/esd/pmc440/config.mk
new file mode 100644
index 0000000..9cb071e
--- /dev/null
+++ b/board/esd/pmc440/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2002-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
new file mode 100644
index 0000000..f876da8
--- /dev/null
+++ b/board/esd/pmc440/fpga.c
@@ -0,0 +1,446 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spartan2.h>
+#include <spartan3.h>
+#include <command.h>
+#include "fpga.h"
+#include "pmc440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+#define USE_SP_CODE
+
+#ifdef USE_SP_CODE
+xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = {
+ fpga_pre_config_fn,
+ fpga_pgm_fn,
+ fpga_init_fn,
+ NULL, /* err */
+ fpga_done_fn,
+ fpga_clk_fn,
+ fpga_cs_fn,
+ fpga_wr_fn,
+ NULL, /* rdata */
+ fpga_wdata_fn,
+ fpga_busy_fn,
+ fpga_abort_fn,
+ fpga_post_config_fn,
+};
+#else
+xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = {
+ fpga_pre_config_fn,
+ fpga_pgm_fn,
+ fpga_clk_fn,
+ fpga_init_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_post_config_fn,
+};
+#endif
+
+xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
+ ngcc_fpga_pre_config_fn,
+ ngcc_fpga_pgm_fn,
+ ngcc_fpga_clk_fn,
+ ngcc_fpga_init_fn,
+ ngcc_fpga_done_fn,
+ ngcc_fpga_wr_fn,
+ ngcc_fpga_post_config_fn
+};
+
+xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+ XILINX_XC3S1200E_DESC(
+#ifdef USE_SP_CODE
+ slave_parallel,
+#else
+ slave_serial,
+#endif
+ (void *)&pmc440_fpga_fns,
+ 0),
+ XILINX_XC2S200_DESC(
+ slave_serial,
+ (void *)&ngcc_fpga_fns,
+ 0)
+};
+
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+void fpga_reset(int assert)
+{
+ debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
+ if (assert) {
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
+ debug("asserted\n");
+ } else {
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
+ debug("deasserted\n");
+ }
+}
+
+
+/*
+ * Initialize the SelectMap interface. We assume that the mode and the
+ * initial state of all of the port pins have already been set!
+ */
+void fpga_serialslave_init(void)
+{
+ debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
+ __LINE__);
+ fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
+}
+
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+ debug("%s:%d: FPGA PROGRAM ",
+ __FUNCTION__, __LINE__);
+
+ if (assert) {
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG);
+ debug("asserted\n");
+ } else {
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG);
+ debug("deasserted\n");
+ }
+ return assert;
+}
+
+
+/*
+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
+ * asserted (low).
+ */
+int fpga_init_fn(int cookie)
+{
+ if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT)
+ return 0;
+ else
+ return 1;
+}
+
+#ifdef USE_SP_CODE
+int fpga_abort_fn(int cookie)
+{
+ return 0;
+}
+
+
+int fpga_cs_fn(int assert_cs, int flush, int cookie)
+{
+ return assert_cs;
+}
+
+
+int fpga_busy_fn(int cookie)
+{
+ return 1;
+}
+#endif
+
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int fpga_done_fn(int cookie)
+{
+ if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE)
+ return 1;
+ else
+ return 0;
+}
+
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+int fpga_pre_config_fn(int cookie)
+{
+ debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+ fpga_reset(true);
+
+ /* release init# */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
+ /* disable PLD IOs */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N);
+ return 0;
+}
+
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+int fpga_post_config_fn(int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+ int rc=0;
+ char *s;
+
+ debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
+
+ /* enable PLD0..7 pins */
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
+
+ fpga_reset(true);
+ udelay (100);
+ fpga_reset(false);
+ udelay (100);
+
+ FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
+
+ /* NGCC/CANDES only: enable ledlink */
+ if ((s = getenv("bd_type")) &&
+ ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes"))))
+ FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
+
+ return rc;
+}
+
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ if (assert_clk)
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK);
+ else
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK);
+
+ return assert_clk;
+}
+
+
+int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+ if (assert_write)
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
+ else
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
+
+ return assert_write;
+}
+
+#ifdef USE_SP_CODE
+int fpga_wdata_fn(uchar data, int flush, int cookie)
+{
+ uchar val = data;
+ ulong or = in_be32((void*)GPIO1_OR);
+ int i = 7;
+ do {
+ /* Write data */
+ if (val & 0x80)
+ or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
+ else
+ or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
+
+ out_be32((void*)GPIO1_OR, or);
+
+ /* Assert the clock */
+ or |= GPIO1_FPGA_CLK;
+ out_be32((void*)GPIO1_OR, or);
+ val <<= 1;
+ i --;
+ } while (i > 0);
+
+ /* Write last data bit (the 8th clock comes from the sp_load() code */
+ if (val & 0x80)
+ or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
+ else
+ or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
+
+ out_be32((void*)GPIO1_OR, or);
+
+ return 0;
+}
+#endif
+
+#define NGCC_FPGA_PRG CLOCK_EN
+#define NGCC_FPGA_DATA RESET_OUT
+#define NGCC_FPGA_DONE CLOCK_IN
+#define NGCC_FPGA_INIT IRIGB_R_IN
+#define NGCC_FPGA_CLK CLOCK_OUT
+
+void ngcc_fpga_serialslave_init(void)
+{
+ debug("%s:%d: Initialize serial slave interface\n",
+ __FUNCTION__, __LINE__);
+
+ /* make sure program pin is inactive */
+ ngcc_fpga_pgm_fn(false, false, 0);
+}
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+void ngcc_fpga_reset(int assert)
+{
+ debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
+
+ if (assert) {
+ FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
+ debug("asserted\n");
+ } else {
+ FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
+ debug("deasserted\n");
+ }
+}
+
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+int ngcc_fpga_pgm_fn(int assert, int flush, int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
+
+ if (assert) {
+ FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG);
+ debug("asserted\n");
+ } else {
+ FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG);
+ debug("deasserted\n");
+ }
+
+ return assert;
+}
+
+
+/*
+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
+ * asserted (low).
+ */
+int ngcc_fpga_init_fn(int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
+ if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) {
+ debug("high\n");
+ return 0;
+ } else {
+ debug("low\n");
+ return 1;
+ }
+}
+
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int ngcc_fpga_done_fn(int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
+ if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) {
+ debug("DONE high\n");
+ return 1;
+ } else {
+ debug("low\n");
+ return 0;
+ }
+}
+
+
+/*
+ * FPGA pre-configuration function.
+ */
+int ngcc_fpga_pre_config_fn(int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+ debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+
+ ngcc_fpga_reset(true);
+ FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
+
+ ngcc_fpga_reset(true);
+ return 0;
+}
+
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+int ngcc_fpga_post_config_fn(int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
+
+ udelay (100);
+ ngcc_fpga_reset(false);
+
+ FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
+
+ return 0;
+}
+
+
+int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ if (assert_clk)
+ FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK);
+ else
+ FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK);
+
+ return assert_clk;
+}
+
+
+int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+ pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
+
+ if (assert_write)
+ FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA);
+ else
+ FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA);
+
+ return assert_write;
+}
+
+
+/*
+ * Initialize the fpga. Return 1 on success, 0 on failure.
+ */
+int pmc440_init_fpga(void)
+{
+ char *s;
+
+ debug("%s:%d: Initialize FPGA interface\n",
+ __FUNCTION__, __LINE__);
+ fpga_init();
+
+ fpga_serialslave_init ();
+ debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
+ fpga_add (fpga_xilinx, &fpga[0]);
+
+ /* NGCC only */
+ if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) {
+ ngcc_fpga_serialslave_init ();
+ debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__);
+ fpga_add (fpga_xilinx, &fpga[1]);
+ }
+
+ return 0;
+}
+#endif /* CONFIG_FPGA */
diff --git a/board/esd/pmc440/fpga.h b/board/esd/pmc440/fpga.h
new file mode 100644
index 0000000..3810788
--- /dev/null
+++ b/board/esd/pmc440/fpga.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+extern int pmc440_init_fpga(void);
+
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_err_fn(int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_wdata_fn (uchar data, int flush, int cookie);
+extern int fpga_read_data_fn(unsigned char *data, int cookie);
+extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
+extern int fpga_busy_fn(int cookie);
+extern int fpga_abort_fn(int cookie );
+extern int fpga_pre_config_fn(int cookie );
+extern int fpga_post_config_fn(int cookie );
+
+extern int ngcc_fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int ngcc_fpga_init_fn(int cookie);
+extern int ngcc_fpga_done_fn(int cookie);
+extern int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int ngcc_fpga_pre_config_fn(int cookie );
+extern int ngcc_fpga_post_config_fn(int cookie );
diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S
new file mode 100644
index 0000000..1f26fad
--- /dev/null
+++ b/board/esd/pmc440/init.S
@@ -0,0 +1,69 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ */
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
+
+ /* TLB entries for DDR2 SDRAM are generated dynamically */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
+
+ /* TLB-entries for EBC */
+ /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
+ * tlb entry.
+ * This dummy entry is only for convinience in order not to modify the
+ * amount of entries. Currently OS/9 relies on this :-)
+ */
+ tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG )
+
+ /* TLB-entry for NAND */
+ tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
+
+ /*TLB-entry PCI registers*/
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
+
+ /* TLB-entry for peripherals */
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
+
+ /* TLB-entry PCI IO space */
+ tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
+
+ /* TODO: what about high IO space */
+ tlbtab_end
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
new file mode 100644
index 0000000..15c3151
--- /dev/null
+++ b/board/esd/pmc440/pmc440.c
@@ -0,0 +1,905 @@
+/*
+ * (Cg) Copyright 2007-2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ * Based on board/amcc/sequoia/sequoia.c
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/ppc440.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <i2c.h>
+#ifdef CONFIG_RESET_PHY_R
+#include <miiphy.h>
+#endif
+#include <serial.h>
+#include <asm/4xx_pci.h>
+#include <usb.h>
+
+#include "fpga.h"
+#include "pmc440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+ulong flash_get_size(ulong base, int banknum);
+static int pci_is_66mhz(void);
+int is_monarch(void);
+static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
+ uchar *buffer, unsigned cnt);
+
+struct serial_device *default_serial_console(void)
+{
+ uchar buf[4];
+ ulong delay;
+ int i;
+ ulong val;
+
+ /*
+ * Use default console on P4 when strapping jumper
+ * is installed (bootstrap option != 'H').
+ */
+ mfsdr(SDR0_PINSTP, val);
+ if (((val & 0xf0000000) >> 29) != 7)
+ return &eserial2_device;
+
+ ulong scratchreg = in_be32((void *)GPIO0_ISR3L);
+ if (!(scratchreg & 0x80)) {
+ /* mark scratchreg valid */
+ scratchreg = (scratchreg & 0xffffff00) | 0x80;
+
+ i2c_init_all();
+
+ i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
+ 0x10, buf, 4);
+ if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
+ scratchreg |= buf[2];
+
+ /* bringup delay for console */
+ for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++)
+ udelay(1000);
+ } else
+ scratchreg |= 0x01;
+ out_be32((void *)GPIO0_ISR3L, scratchreg);
+ }
+
+ if (scratchreg & 0x01)
+ return &eserial2_device;
+ else
+ return &eserial1_device;
+}
+
+int board_early_init_f(void)
+{
+ u32 sdr0_cust0;
+ u32 sdr0_pfc1, sdr0_pfc2;
+ u32 reg;
+
+ /* general EBC configuration (disable EBC timeouts) */
+ mtdcr(EBC0_CFGADDR, EBC0_CFG);
+ mtdcr(EBC0_CFGDATA, 0xf8400000);
+
+ /* Setup the GPIO pins */
+ out_be32((void *)GPIO0_OR, 0x40000102);
+ out_be32((void *)GPIO0_TCR, 0x4c90011f);
+ out_be32((void *)GPIO0_OSRL, 0x28051400);
+ out_be32((void *)GPIO0_OSRH, 0x55005000);
+ out_be32((void *)GPIO0_TSRL, 0x08051400);
+ out_be32((void *)GPIO0_TSRH, 0x55005000);
+ out_be32((void *)GPIO0_ISR1L, 0x54000000);
+ out_be32((void *)GPIO0_ISR1H, 0x00000000);
+ out_be32((void *)GPIO0_ISR2L, 0x44000000);
+ out_be32((void *)GPIO0_ISR2H, 0x00000100);
+ out_be32((void *)GPIO0_ISR3L, 0x00000000);
+ out_be32((void *)GPIO0_ISR3H, 0x00000000);
+
+ out_be32((void *)GPIO1_OR, 0x80002408);
+ out_be32((void *)GPIO1_TCR, 0xd6003c08);
+ out_be32((void *)GPIO1_OSRL, 0x0a5a0000);
+ out_be32((void *)GPIO1_OSRH, 0x00000000);
+ out_be32((void *)GPIO1_TSRL, 0x00000000);
+ out_be32((void *)GPIO1_TSRH, 0x00000000);
+ out_be32((void *)GPIO1_ISR1L, 0x00005555);
+ out_be32((void *)GPIO1_ISR1H, 0x40000000);
+ out_be32((void *)GPIO1_ISR2L, 0x04010000);
+ out_be32((void *)GPIO1_ISR2H, 0x00000000);
+ out_be32((void *)GPIO1_ISR3L, 0x01400000);
+ out_be32((void *)GPIO1_ISR3H, 0x00000000);
+
+ /* patch PLB:PCI divider for 66MHz PCI */
+ mfcpr(CPR0_SPCID, reg);
+ if (pci_is_66mhz() && (reg != 0x02000000)) {
+ mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
+
+ mfcpr(CPR0_ICFG, reg);
+ reg |= CPR0_ICFG_RLI_MASK;
+ mtcpr(CPR0_ICFG, reg);
+
+ mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
+ }
+
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffff7ef);
+ mtdcr(UIC0TR, 0x00000000);
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffc7f5);
+ mtdcr(UIC1TR, 0x00000000);
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0x27ffffff);
+ mtdcr(UIC2TR, 0x00000000);
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ /* select Ethernet pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_4;
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_4;
+
+ /* enable 2nd IIC */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /* setup NAND FLASH */
+ mfsdr(SDR0_CUST0, sdr0_cust0);
+ sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
+ SDR0_CUST0_NDFC_ENABLE |
+ SDR0_CUST0_NDFC_BW_8_BIT |
+ SDR0_CUST0_NDFC_ARE_MASK |
+ (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
+ mtsdr(SDR0_CUST0, sdr0_cust0);
+
+ return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_F)
+int misc_init_f(void)
+{
+ struct pci_controller hose;
+ hose.first_busno = 0;
+ hose.last_busno = 0;
+ hose.region_count = 0;
+
+ if (getenv("pciearly") && (!is_monarch())) {
+ printf("PCI: early target init\n");
+ pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
+ pci_target_init(&hose);
+ }
+ return 0;
+}
+#endif
+
+/*
+ * misc_init_r.
+ */
+int misc_init_r(void)
+{
+ uint pbcr;
+ int size_val = 0;
+ u32 reg;
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1;
+ unsigned long sdr0_srst0, sdr0_srst1;
+ char *act = getenv("usbact");
+
+ /*
+ * FLASH stuff...
+ */
+
+ /* Re-do sizing to get full correct info */
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ size_val = ffs(gd->bd->bi_flashsize) - 21;
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ /* Env protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+ /*
+ * USB suff...
+ */
+ if ((act == NULL || strcmp(act, "host") == 0) &&
+ !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+
+ /*
+ * An 8-bit/60MHz interface is the only possible alternative
+ * when connecting the Device to the PHY
+ */
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
+
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /*
+ * Take USB out of reset:
+ * -Initial status = all cores are in reset
+ * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
+ * -wait 1 ms
+ * -deassert reset to PHY
+ * -wait 1 ms
+ * -deassert reset to HOST
+ * -wait 4 ms
+ * -deassert all other resets
+ */
+ mfsdr(SDR0_SRST1, sdr0_srst1);
+ sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
+ SDR0_SRST1_P4OPB0 | \
+ SDR0_SRST1_OPBA2 | \
+ SDR0_SRST1_PLB42OPB1 | \
+ SDR0_SRST1_OPB2PLB40);
+ mtsdr(SDR0_SRST1, sdr0_srst1);
+ udelay(1000);
+
+ mfsdr(SDR0_SRST1, sdr0_srst1);
+ sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
+ mtsdr(SDR0_SRST1, sdr0_srst1);
+ udelay(1000);
+
+ mfsdr(SDR0_SRST0, sdr0_srst0);
+ sdr0_srst0 &= ~SDR0_SRST0_USB2H;
+ mtsdr(SDR0_SRST0, sdr0_srst0);
+ udelay(4000);
+
+ /* finally all the other resets */
+ mtsdr(SDR0_SRST1, 0x00000000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
+ /* enable power on USB socket */
+ out_be32((void *)GPIO1_OR,
+ in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
+ }
+
+ printf("USB: Host\n");
+
+ } else if ((strcmp(act, "dev") == 0) ||
+ (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x672c6000);
+
+ udelay (1000);
+ mtsdr(SDR0_SRST0, 0x00000080);
+
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x60206000);
+
+ *(unsigned int *)(0xe0000350) = 0x00000001;
+
+ udelay (1000);
+ mtsdr(SDR0_SRST1, 0x60306000);
+
+ /* SDR Setting */
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
+
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
+
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
+
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /*clear resets*/
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay(1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Device\n");
+ }
+
+ /*
+ * Clear PLB4A0_ACR[WRP]
+ * This fix will make the MAL burst disabling patch for the Linux
+ * EMAC driver obsolete.
+ */
+ reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+ mtdcr(PLB4A0_ACR, reg);
+
+#ifdef CONFIG_FPGA
+ pmc440_init_fpga();
+#endif
+
+ /* turn off POST LED */
+ out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N);
+ /* turn on RUN LED */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N);
+ return 0;
+}
+
+int is_monarch(void)
+{
+ if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH)
+ return 0;
+
+ return 1;
+}
+
+static int pci_is_66mhz(void)
+{
+ if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN)
+ return 1;
+ return 0;
+}
+
+static int board_revision(void)
+{
+ return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
+}
+
+int checkboard(void)
+{
+ puts("Board: esd GmbH - PMC440");
+
+ gd->board_type = board_revision();
+ printf(", Rev 1.%ld, ", gd->board_type);
+
+ if (!is_monarch()) {
+ puts("non-");
+ }
+
+ printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
+ return (0);
+}
+
+
+#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
+/*
+ * Assign interrupts to PCI devices. Some OSs rely on this.
+ */
+void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
+
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+ int_line[PCI_DEV(dev) & 0x03]);
+}
+#endif
+
+/*
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ char *ptmla_str, *ptmms_str;
+
+ /*
+ * Set up Direct MMIO registers
+ */
+ /*
+ * PowerPC440EPX PCI Master configuration.
+ * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ * PLB address 0x80000000-0xBFFFFFFF
+ * ==> PCI address 0x80000000-0xBFFFFFFF
+ * Use byte reversed out routines to handle endianess.
+ * Make this region non-prefetchable.
+ */
+ out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
+ /* - disabled b4 setting */
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */
+ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
+ /* and enable region */
+
+ if (!is_monarch()) {
+ ptmla_str = getenv("ptm1la");
+ ptmms_str = getenv("ptm1ms");
+ if(NULL != ptmla_str && NULL != ptmms_str ) {
+ out32r(PCIL0_PTM1MS,
+ simple_strtoul(ptmms_str, NULL, 16));
+ out32r(PCIL0_PTM1LA,
+ simple_strtoul(ptmla_str, NULL, 16));
+ } else {
+ /* BAR1: default top 64MB of RAM */
+ out32r(PCIL0_PTM1MS, 0xfc000001);
+ out32r(PCIL0_PTM1LA, 0x0c000000);
+ }
+ } else {
+ /* BAR1: default: complete 256MB RAM */
+ out32r(PCIL0_PTM1MS, 0xf0000001);
+ out32r(PCIL0_PTM1LA, 0x00000000);
+ }
+
+ ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */
+ ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */
+ if(NULL != ptmla_str && NULL != ptmms_str ) {
+ out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
+ out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
+ } else {
+ /* BAR2: default: 4MB FPGA */
+ out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
+ }
+
+ if (is_monarch()) {
+ /* BAR2: map FPGA registers behind system memory at 1GB */
+ pci_hose_write_config_dword(hose, 0,
+ PCI_BASE_ADDRESS_2, 0x40000008);
+ }
+
+ /*
+ * Set up Configuration registers
+ */
+
+ /* Program the board's vendor id */
+ pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
+ CONFIG_SYS_PCI_SUBSYS_VENDORID);
+
+ /* disabled for PMC405 backward compatibility */
+ /* Configure command register as bus master */
+ /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
+
+
+ /* 240nS PCI clock */
+ pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
+
+ /* No error reporting */
+ pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
+
+ if (!is_monarch()) {
+ /* Program the board's subsystem id/classcode */
+ pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
+ CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
+ pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
+ CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
+
+ /* PCI configuration done: release ERREADY */
+ out_be32((void *)GPIO1_OR,
+ in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY);
+ out_be32((void *)GPIO1_TCR,
+ in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY);
+ } else {
+ /* Program the board's subsystem id/classcode */
+ pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
+ CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
+ pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
+ CONFIG_SYS_PCI_CLASSCODE_MONARCH);
+ }
+
+ /* enable host configuration */
+ pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
+}
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
+
+/*
+ * Override weak default pci_master_init()
+ */
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ /*
+ * Only configure the master in monach mode
+ */
+ if (is_monarch())
+ __pci_master_init(hose);
+}
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
+
+static void wait_for_pci_ready(void)
+{
+ if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) {
+ printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
+ while (1) {
+ if (ctrlc()) {
+ puts("abort\n");
+ break;
+ }
+ if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) {
+ printf("done\n");
+ break;
+ }
+ }
+ }
+}
+
+/*
+ * Override weak is_pci_host()
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ char *s = getenv("pciscan");
+ if (s == NULL)
+ if (is_monarch()) {
+ wait_for_pci_ready();
+ return 1;
+ } else
+ return 0;
+ else if (!strcmp(s, "yes"))
+ return 1;
+
+ return 0;
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_RESET_PHY_R
+static int pmc440_setup_vsc8601(char *devname, int phy_addr,
+ unsigned short behavior, unsigned short method)
+{
+ /* adjust LED behavior */
+ if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) {
+ printf("Phy%d: register write access failed\n", phy_addr);
+ return -1;
+ }
+
+ miiphy_write(devname, phy_addr, 0x11, 0x0010);
+ miiphy_write(devname, phy_addr, 0x11, behavior);
+ miiphy_write(devname, phy_addr, 0x10, method);
+ miiphy_write(devname, phy_addr, 0x1f, 0x0000);
+
+ return 0;
+}
+
+static int pmc440_setup_ksz9031(char *devname, int phy_addr)
+{
+ unsigned short id1, id2;
+
+ if (miiphy_read(devname, phy_addr, 2, &id1) ||
+ miiphy_read(devname, phy_addr, 3, &id2)) {
+ printf("Phy%d: cannot read id\n", phy_addr);
+ return -1;
+ }
+
+ if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) {
+ printf("Phy%d: unexpected id\n", phy_addr);
+ return -1;
+ }
+
+ /* MMD 2.08: adjust tx_clk pad skew */
+ miiphy_write(devname, phy_addr, 0x0d, 2);
+ miiphy_write(devname, phy_addr, 0x0e, 8);
+ miiphy_write(devname, phy_addr, 0x0d, 0x4002);
+ miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5));
+
+ return 0;
+}
+
+void reset_phy(void)
+{
+ char *s;
+ unsigned short val_method, val_behavior;
+
+ if (gd->board_type < 4) {
+ /* special LED setup for NGCC/CANDES */
+ s = getenv("bd_type");
+ if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
+ val_method = 0x0e0a;
+ val_behavior = 0x0cf2;
+ } else {
+ /* PMC440 standard type */
+ val_method = 0x0e10;
+ val_behavior = 0x0cf0;
+ }
+
+ /* boards up to rev. 1.3 use Vitesse VSC8601 phys */
+ pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR,
+ val_method, val_behavior);
+ pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR,
+ val_method, val_behavior);
+ } else {
+ /* rev. 1.4 uses a Micrel KSZ9031 */
+ pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR);
+ pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR);
+ }
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/*
+ * Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+ if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
+ (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO_SINT2. */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO_SINT2. */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void *)GPIO0_OR)
+ & GPIO0_EP_EEP));
+ break;
+ }
+ }
+ return state;
+}
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
+
+#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
+int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
+ uchar *buffer, unsigned cnt)
+{
+ unsigned end = offset + cnt;
+ unsigned blk_off;
+ int rcode = 0;
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 1);
+#endif
+ /*
+ * Write data until done or would cross a write page boundary.
+ * We must write the address again when changing pages
+ * because the address counter only increments within a page.
+ */
+ while (offset < end) {
+ unsigned alen, len;
+ unsigned maxlen;
+ uchar addr[2];
+
+ blk_off = offset & 0xFF; /* block offset */
+
+ addr[0] = offset >> 8; /* block number */
+ addr[1] = blk_off; /* block offset */
+ alen = 2;
+ addr[0] |= dev_addr; /* insert device address */
+
+ len = end - offset;
+
+#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
+
+ maxlen = BOOT_EEPROM_PAGE_SIZE -
+ BOOT_EEPROM_PAGE_OFFSET(blk_off);
+ if (maxlen > I2C_RXTX_LEN)
+ maxlen = I2C_RXTX_LEN;
+
+ if (len > maxlen)
+ len = maxlen;
+
+ if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
+ rcode = 1;
+
+ buffer += len;
+ offset += len;
+
+#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
+ udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#endif
+ }
+#if defined(CONFIG_SYS_EEPROM_WREN)
+ eeprom_write_enable(dev_addr, 0);
+#endif
+ return rcode;
+}
+
+static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
+ uchar *buffer, unsigned cnt)
+{
+ unsigned end = offset + cnt;
+ unsigned blk_off;
+ int rcode = 0;
+
+ /*
+ * Read data until done or would cross a page boundary.
+ * We must write the address again when changing pages
+ * because the next page may be in a different device.
+ */
+ while (offset < end) {
+ unsigned alen, len;
+ unsigned maxlen;
+ uchar addr[2];
+
+ blk_off = offset & 0xFF; /* block offset */
+
+ addr[0] = offset >> 8; /* block number */
+ addr[1] = blk_off; /* block offset */
+ alen = 2;
+
+ addr[0] |= dev_addr; /* insert device address */
+
+ len = end - offset;
+
+ maxlen = 0x100 - blk_off;
+ if (maxlen > I2C_RXTX_LEN)
+ maxlen = I2C_RXTX_LEN;
+ if (len > maxlen)
+ len = maxlen;
+
+ if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
+ rcode = 1;
+ buffer += len;
+ offset += len;
+ }
+
+ return rcode;
+}
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
+int board_usb_init(int index, enum usb_init_type init)
+{
+ char *act = getenv("usbact");
+ int i;
+
+ if ((act == NULL || strcmp(act, "host") == 0) &&
+ !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT))
+ /* enable power on USB socket */
+ out_be32((void *)GPIO1_OR,
+ in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
+
+ for (i=0; i<1000; i++)
+ udelay(1000);
+
+ return 0;
+}
+
+int usb_board_stop(void)
+{
+ /* disable power on USB socket */
+ out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N);
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return usb_board_stop();
+}
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int rc;
+
+ __ft_board_setup(blob, bd);
+
+ /*
+ * Disable PCI in non-monarch mode.
+ */
+ if (!is_monarch()) {
+ rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
+ "disabled", sizeof("disabled"), 1);
+ if (rc) {
+ printf("Unable to update property status in PCI node, ");
+ printf("err=%s\n", fdt_strerror(rc));
+ }
+ }
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h
new file mode 100644
index 0000000..84e0b1f
--- /dev/null
+++ b/board/esd/pmc440/pmc440.h
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2007-2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PMC440_H__
+#define __PMC440_H__
+
+/*
+ * GPIOs
+ */
+#define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */
+#define GPIO1_NONMONARCH (0x80000000 >> (63-32)) /* GPIO63 I */
+#define GPIO1_PPC_EREADY (0x80000000 >> (62-32)) /* GPIO62 I/O */
+#define GPIO1_M66EN (0x80000000 >> (61-32)) /* GPIO61 I */
+#define GPIO1_POST_N (0x80000000 >> (60-32)) /* GPIO60 O */
+#define GPIO1_IOEN_N (0x80000000 >> (50-32)) /* GPIO50 O */
+#define GPIO1_HWID_MASK (0xf0000000 >> (56-32)) /* GPIO56..59 I */
+
+#define GPIO1_USB_PWR_N (0x80000000 >> (32-32)) /* GPIO32 I */
+#define GPIO0_LED_RUN_N (0x80000000 >> 30) /* GPIO30 O */
+#define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */
+#define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */
+#define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */
+
+/*
+ * FPGA programming pin configuration
+ */
+#define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
+#define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */
+#define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */
+#define GPIO1_FPGA_DONE (0x80000000 >> (55-32)) /* FPGA done pin (ppc input) */
+#define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */
+#define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */
+
+/*
+ * FPGA interface
+ */
+#define FPGA_BA CONFIG_SYS_FPGA_BASE0
+#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
+#define FPGA_IN32(p) in_be32((void*)(p))
+#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
+#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v))
+
+struct pmc440_fifo_s {
+ u32 data;
+ u32 ctrl;
+};
+
+/* fifo ctrl register */
+#define FIFO_IE (1 << 15)
+#define FIFO_OVERFLOW (1 << 10)
+#define FIFO_EMPTY (1 << 9)
+#define FIFO_FULL (1 << 8)
+#define FIFO_LEVEL_MASK 0x000000ff
+
+#define FIFO_COUNT 4
+
+struct pmc440_fpga_s {
+ u32 ctrla;
+ u32 status;
+ u32 ctrlb;
+ u32 pad1[0x40 / sizeof(u32) - 3];
+ u32 irig_time; /* offset: 0x0040 */
+ u32 irig_tod;
+ u32 irig_cf;
+ u32 pad2;
+ u32 irig_rx_time; /* offset: 0x0050 */
+ u32 pad3[3];
+ u32 hostctrl; /* offset: 0x0060 */
+ u32 pad4[0x20 / sizeof(u32) - 1];
+ struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */
+};
+
+typedef struct pmc440_fpga_s pmc440_fpga_t;
+
+/* ctrl register */
+#define CTRL_HOST_IE (1 << 8)
+
+/* outputs */
+#define RESET_EN (1 << 31)
+#define CLOCK_EN (1 << 30)
+#define RESET_OUT (1 << 19)
+#define CLOCK_OUT (1 << 22)
+#define RESET_OUT (1 << 19)
+#define IRIGB_R_OUT (1 << 14)
+
+/* status register */
+#define STATUS_VERSION_SHIFT 24
+#define STATUS_VERSION_MASK 0xff000000
+#define STATUS_HWREV_SHIFT 20
+#define STATUS_HWREV_MASK 0x00f00000
+
+#define STATUS_CAN_ISF (1 << 11)
+#define STATUS_CSTM_ISF (1 << 10)
+#define STATUS_FIFO_ISF (1 << 9)
+#define STATUS_HOST_ISF (1 << 8)
+
+/* inputs */
+#define RESET_IN (1 << 0)
+#define CLOCK_IN (1 << 1)
+#define IRIGB_R_IN (1 << 5)
+
+/* hostctrl register */
+#define HOSTCTRL_PMCRSTOUT_GATE (1 << 17)
+#define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16)
+#define HOSTCTRL_CSTM1IE_GATE (1 << 7)
+#define HOSTCTRL_CSTM1IW_FLAG (1 << 6)
+#define HOSTCTRL_CSTM0IE_GATE (1 << 5)
+#define HOSTCTRL_CSTM0IW_FLAG (1 << 4)
+#define HOSTCTRL_FIFOIE_GATE (1 << 3)
+#define HOSTCTRL_FIFOIE_FLAG (1 << 2)
+#define HOSTCTRL_HCINT_GATE (1 << 1)
+#define HOSTCTRL_HCINT_FLAG (1 << 0)
+
+#define NGCC_CTRL_BASE (CONFIG_SYS_FPGA_BASE0 + 0x80000)
+#define NGCC_CTRL_FPGARST_N (1 << 2)
+
+/*
+ * FPGA to PPC interrupt
+ */
+#define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */
+#define IRQ1_FPGA (32+30) /* UIC1 - custom module */
+#define IRQ2_FPGA (64+ 3) /* UIC2 - custom module / CAN */
+#define IRQ_ETH0 (64+ 4) /* UIC2 */
+#define IRQ_ETH1 ( 27) /* UIC0 */
+#define IRQ_RTC (64+ 0) /* UIC2 */
+#define IRQ_PCIA (64+ 1) /* UIC2 */
+#define IRQ_PCIB (32+18) /* UIC1 */
+#define IRQ_PCIC (32+19) /* UIC1 */
+#define IRQ_PCID (32+20) /* UIC1 */
+
+#endif /* __PMC440_H__ */
diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c
new file mode 100644
index 0000000..e7f8115
--- /dev/null
+++ b/board/esd/pmc440/sdram.c
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2009
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu
+ *
+ * (C) Copyright 2006
+ * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* define DEBUG for debug output */
+#undef DEBUG
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/ppc440.h>
+
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
+
+struct sdram_conf_s {
+ ulong size;
+ int rows;
+ int banks;
+};
+
+struct sdram_conf_s sdram_conf[] = {
+ {(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */
+ {(512 << 20), 13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */
+ {(256 << 20), 13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */
+};
+
+/*
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ */
+int initdram_by_rb(int rows, int banks)
+{
+ ulong speed = get_bus_freq(0);
+
+ mtsdram(DDR0_02, 0x00000000);
+
+ mtsdram(DDR0_00, 0x0000190A);
+ mtsdram(DDR0_01, 0x01000000);
+ mtsdram(DDR0_03, 0x02030602);
+ mtsdram(DDR0_04, 0x0A020200);
+ mtsdram(DDR0_05, 0x02020308);
+ mtsdram(DDR0_06, 0x0102C812);
+ mtsdram(DDR0_07, 0x000D0100);
+ mtsdram(DDR0_08, 0x02430001);
+ mtsdram(DDR0_09, 0x00011D5F);
+ mtsdram(DDR0_10, 0x00000100);
+ mtsdram(DDR0_11, 0x0027C800);
+ mtsdram(DDR0_12, 0x00000003);
+ mtsdram(DDR0_14, 0x00000000);
+ mtsdram(DDR0_17, 0x19000000);
+ mtsdram(DDR0_18, 0x19191919);
+ mtsdram(DDR0_19, 0x19191919);
+ mtsdram(DDR0_20, 0x0B0B0B0B);
+ mtsdram(DDR0_21, 0x0B0B0B0B);
+ mtsdram(DDR0_22, 0x00267F0B);
+ mtsdram(DDR0_23, 0x00000000);
+ mtsdram(DDR0_24, 0x01010002);
+ if (speed > 133333334)
+ mtsdram(DDR0_26, 0x5B26050C);
+ else
+ mtsdram(DDR0_26, 0x5B260408);
+ mtsdram(DDR0_27, 0x0000682B);
+ mtsdram(DDR0_28, 0x00000000);
+ mtsdram(DDR0_31, 0x00000000);
+
+ mtsdram(DDR0_42,
+ DDR0_42_ADDR_PINS_DECODE(14 - rows) |
+ 0x00000006);
+ mtsdram(DDR0_43,
+ DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) |
+ 0x030A0200);
+
+ mtsdram(DDR0_44, 0x00000003);
+ mtsdram(DDR0_02, 0x00000001);
+
+ denali_wait_for_dlllock();
+
+#ifdef CONFIG_DDR_DATA_EYE
+ /*
+ * Perform data eye search if requested.
+ */
+ denali_core_search_data_eye();
+#endif
+ /*
+ * Clear possible errors resulting from data-eye-search.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t size;
+ int n;
+
+ /* go through supported memory configurations */
+ for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) {
+ size = sdram_conf[n].size;
+
+ /* program TLB entries */
+ program_tlb(0, CONFIG_SYS_SDRAM_BASE, size,
+ TLB_WORD2_I_ENABLE);
+
+ /*
+ * setup denali core
+ */
+ initdram_by_rb(sdram_conf[n].rows,
+ sdram_conf[n].banks);
+
+ /* check for suitable configuration */
+ if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size)
+ return size;
+
+ /* delete TLB entries */
+ remove_tlb(CONFIG_SYS_SDRAM_BASE, size);
+ }
+
+ return 0;
+}
diff --git a/board/esd/tasreg/Kconfig b/board/esd/tasreg/Kconfig
new file mode 100644
index 0000000..85417d4
--- /dev/null
+++ b/board/esd/tasreg/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TASREG
+
+config SYS_CPU
+ default "mcf52x2"
+
+config SYS_BOARD
+ default "tasreg"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "TASREG"
+
+endif
diff --git a/board/esd/tasreg/MAINTAINERS b/board/esd/tasreg/MAINTAINERS
new file mode 100644
index 0000000..10bc7a4
--- /dev/null
+++ b/board/esd/tasreg/MAINTAINERS
@@ -0,0 +1,6 @@
+TASREG BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/tasreg/
+F: include/configs/TASREG.h
+F: configs/TASREG_defconfig
diff --git a/board/esd/tasreg/Makefile b/board/esd/tasreg/Makefile
new file mode 100644
index 0000000..46f2550
--- /dev/null
+++ b/board/esd/tasreg/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = tasreg.o flash.o
diff --git a/board/esd/tasreg/config.mk b/board/esd/tasreg/config.mk
new file mode 100644
index 0000000..40f7570
--- /dev/null
+++ b/board/esd/tasreg/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffc00000
diff --git a/board/esd/tasreg/flash.c b/board/esd/tasreg/flash.c
new file mode 100644
index 0000000..7138881
--- /dev/null
+++ b/board/esd/tasreg/flash.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+/*#include <asm/ppc4xx.h>*/
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* test-only: todo: Re-do sizing to get full correct info */
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-1,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/tasreg/fpgadata.c b/board/esd/tasreg/fpgadata.c
new file mode 100644
index 0000000..427b1d0
--- /dev/null
+++ b/board/esd/tasreg/fpgadata.c
@@ -0,0 +1,10661 @@
+0x1f, 0x8b, 0x08, 0x08, 0x5a, 0x90, 0xc1, 0x41,
+0x00, 0x03, 0x72, 0x61, 0x73, 0x72, 0x65, 0x67,
+0x2e, 0x62, 0x69, 0x74, 0x00, 0xac, 0xfd, 0x7d,
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+0xcd, 0xcc, 0xff, 0xbc, 0x28, 0x18, 0xe6, 0xc0,
+0x55, 0x21, 0xe5, 0xf3, 0x52, 0xb1, 0xd1, 0x07,
+0x5d, 0xde, 0xcf, 0x4b, 0x5f, 0x6c, 0x6a, 0x7f,
+0x69, 0xea, 0x4c, 0x25, 0xbf, 0xf8, 0x4b, 0xc6,
+0x09, 0xf8, 0x2b, 0x7b, 0xff, 0x82, 0x79, 0x06,
+0x0f, 0x7f, 0x33, 0x3a, 0xff, 0xfd, 0xb9, 0xe8,
+0xf3, 0xff, 0xad, 0x0b, 0x17, 0xf4, 0x4f, 0x6a,
+0x01, 0x50, 0xfc, 0x39, 0x5d, 0xe8, 0x9f, 0x74,
+0x0f, 0xb9, 0x2b, 0xfe, 0x39, 0x80, 0xc9, 0x62,
+0x8b, 0xb0, 0x89, 0xfe, 0xb3, 0x6b, 0x8c, 0x69,
+0xff, 0xb0, 0x72, 0xc5, 0x30, 0xb5, 0x50, 0x3b,
+0x7a, 0x59, 0x60, 0xcc, 0x90, 0xd7, 0x0a, 0x88,
+0x97, 0x11, 0x0b, 0x2f, 0x01, 0x50, 0x6c, 0x02,
+0x82, 0xf6, 0x2e, 0x29, 0xd7, 0xa2, 0x07, 0x39,
+0x5e, 0xd6, 0x0c, 0x40, 0xd0, 0x2e, 0xbc, 0x3c,
+0xcf, 0xbe, 0x0c, 0xe0, 0xe5, 0xcf, 0x5d, 0x02,
+0xe4, 0xfb, 0x9d, 0x1f, 0xd6, 0xff, 0x61, 0xd1,
+0x85, 0x7f, 0xbb, 0x72, 0xef, 0x95, 0x67, 0xb9,
+0x01, 0xe0, 0xf1, 0xfa, 0x3f, 0x30, 0x50, 0xfc,
+0x9d, 0x4b, 0xf5, 0x68, 0x5c, 0xfe, 0x7f, 0x0b,
+0x2f, 0x4f, 0x7a, 0xfa, 0xe5, 0x17, 0x53, 0xd6,
+0xf7, 0x79, 0xf7, 0xde, 0x5d, 0xcf, 0x06, 0x7f,
+0xb5, 0xe0, 0x3e, 0x06, 0x9c, 0xa7, 0xfc, 0x6a,
+0x01, 0x22, 0xe8, 0x6f, 0xad, 0x80, 0x96, 0xfb,
+0x0f, 0xbe, 0x9a, 0xba, 0xb0, 0x22, 0x62, 0x61,
+0xea, 0xff, 0x1b, 0x8c, 0xfb, 0xd9, 0x18, 0xe7,
+0x3a, 0x35, 0x75, 0x9f, 0x7b, 0xf1, 0xdf, 0x6a,
+0xfa, 0xac, 0xeb, 0x7c, 0x78, 0xef, 0xf1, 0x67,
+0x6b, 0x6e, 0x5e, 0x78, 0x81, 0x01, 0xe7, 0xeb,
+0x6f, 0x66, 0x08, 0xfa, 0xdb, 0x67, 0xa1, 0xe5,
+0x4a, 0x71, 0xa4, 0xef, 0xe2, 0xd9, 0x7a, 0x0b,
+0x53, 0x5f, 0x02, 0xe3, 0x0a, 0x1b, 0xe3, 0x5c,
+0x67, 0xce, 0x14, 0xa3, 0xaf, 0x68, 0xc6, 0xa0,
+0x57, 0x98, 0xd3, 0xf2, 0x85, 0xe7, 0x1e, 0xd9,
+0x25, 0x9f, 0xb9, 0x65, 0x8e, 0x16, 0x7d, 0x6e,
+0xc3, 0x8c, 0xf6, 0x77, 0x47, 0x25, 0xed, 0x0b,
+0x2f, 0x14, 0xef, 0x1a, 0xcc, 0x1f, 0x85, 0xae,
+0xd7, 0x1e, 0x49, 0xb5, 0x9f, 0xf9, 0xe6, 0x9c,
+0x95, 0xd1, 0x57, 0x8b, 0x6e, 0x6e, 0x5f, 0xfb,
+0xcd, 0x39, 0xa5, 0x5f, 0x78, 0x0d, 0xc7, 0x9c,
+0x76, 0xae, 0x23, 0xb6, 0x93, 0x2d, 0x24, 0xf0,
+0x8f, 0x1e, 0x8d, 0x1b, 0x86, 0xdb, 0x58, 0x15,
+0xca, 0xb4, 0x1c, 0x75, 0x77, 0x79, 0x0f, 0xda,
+0x63, 0x9c, 0xcb, 0xb8, 0x42, 0x83, 0xcc, 0x11,
+0x23, 0xee, 0x50, 0x86, 0x65, 0x64, 0x87, 0x0f,
+0x49, 0x56, 0x97, 0x73, 0x42, 0xd6, 0x8e, 0xcc,
+0x5b, 0x06, 0x7b, 0x29, 0x4c, 0x64, 0x74, 0xb0,
+0x54, 0x2b, 0x71, 0x8c, 0xe1, 0x74, 0x11, 0x6b,
+0xe7, 0xb1, 0xbe, 0xc6, 0x3f, 0xea, 0x13, 0x7c,
+0x0d, 0x65, 0x52, 0x38, 0xd3, 0x72, 0xd4, 0xd5,
+0xe5, 0x0e, 0x70, 0x3a, 0xbf, 0x8b, 0x8e, 0x3b,
+0xf8, 0x03, 0xe3, 0xe8, 0xb8, 0x96, 0x8f, 0x33,
+0xf8, 0xef, 0xfa, 0x4f, 0x0f, 0xff, 0x63, 0x57,
+0x62, 0xd7, 0x61, 0x34, 0x77, 0x1d, 0xfc, 0x7d,
+0xc9, 0x0d, 0x36, 0xa2, 0x03, 0x46, 0x58, 0x2d,
+0xe2, 0x98, 0x2e, 0x85, 0x0d, 0x26, 0x56, 0x8b,
+0xfd, 0x99, 0xf8, 0x1f, 0x39, 0xfa, 0x9f, 0xfd,
+0x46, 0xf6, 0xf7, 0x91, 0x3d, 0xed, 0xe2, 0x16,
+0xb2, 0xdd, 0x98, 0xae, 0xfd, 0x69, 0x86, 0x28,
+0xd8, 0xbf, 0x6b, 0xfc, 0x32, 0xfd, 0xef, 0x18,
+0xce, 0xfc, 0x7c, 0xd2, 0xfd, 0xf3, 0x49, 0x06,
+0xb1, 0xef, 0x9f, 0x49, 0x21, 0xe1, 0x28, 0xf9,
+0x47, 0x32, 0xd9, 0xfc, 0x93, 0x8c, 0x83, 0xf2,
+0x7f, 0xe5, 0xfb, 0x4c, 0x36, 0xed, 0x16, 0x31,
+0x73, 0x23, 0xfe, 0x09, 0xb7, 0x8d, 0xe6, 0xb4,
+0x64, 0x3e, 0x7f, 0xca, 0xcd, 0xa7, 0x65, 0xdf,
+0x85, 0x38, 0x3f, 0xe6, 0x1f, 0x7b, 0x59, 0x7e,
+0xdc, 0xc7, 0x9b, 0xf9, 0x2b, 0x9e, 0x1f, 0x15,
+0xfa, 0x53, 0xae, 0x92, 0x75, 0x45, 0x83, 0xfd,
+0x2f, 0xa4, 0xff, 0x57, 0xaf, 0x63, 0x4d, 0xd1,
+0x24, 0xf3, 0xbf, 0x78, 0x21, 0x61, 0xf8, 0xbf,
+0x78, 0x81, 0xff, 0x43, 0x9f, 0xfa, 0x2b, 0x57,
+0xae, 0x98, 0x7f, 0xba, 0xf1, 0xe9, 0x75, 0xfe,
+0x5f, 0xbe, 0xce, 0x04, 0xdb, 0xf1, 0xff, 0x8e,
+0xe1, 0x5c, 0xe7, 0xbf, 0xf8, 0x5e, 0xcd, 0x5c,
+0x67, 0xdc, 0x9e, 0xfb, 0x31, 0x86, 0x6b, 0xa7,
+0x9e, 0xe0, 0xbd, 0x4a, 0xc8, 0x7f, 0xfe, 0x5f,
+0xb7, 0x5c, 0x08, 0x32, 0xd1, 0xbe, 0xfc, 0xdf,
+0xb2, 0x9b, 0xfe, 0xf7, 0xee, 0xcb, 0xce, 0x56,
+0x3b, 0x76, 0x83, 0xfe, 0x24, 0x23, 0xeb, 0xfb,
+0xfc, 0x89, 0x6f, 0xfa, 0xb1, 0xfb, 0x32, 0xc1,
+0x1d, 0xf6, 0xe8, 0xf6, 0x7f, 0x9c, 0x70, 0xf3,
+0x5d, 0x15, 0x86, 0x2e, 0x97, 0x31, 0xf9, 0x30,
+0xeb, 0x72, 0x0f, 0xce, 0xfc, 0xae, 0xff, 0xbe,
+0x7d, 0x59, 0xff, 0xb8, 0x5d, 0x8f, 0x4e, 0xdc,
+0x45, 0xc6, 0xdf, 0x3f, 0x0a, 0xdb, 0x97, 0xc9,
+0xb8, 0x3d, 0x97, 0xb7, 0xb0, 0x9b, 0x64, 0x7c,
+0x97, 0xc1, 0xbb, 0xfe, 0x1b, 0xf6, 0xe5, 0x8c,
+0xf1, 0x5f, 0xdb, 0x97, 0x33, 0xc6, 0x7f, 0xf3,
+0xfd, 0x4c, 0x32, 0x01, 0x91, 0x3f, 0xf1, 0xc3,
+0xf3, 0xe7, 0xff, 0xbb, 0x3e, 0x75, 0x75, 0xff,
+0xc5, 0x0b, 0xf8, 0x7c, 0xff, 0x2d, 0xdf, 0xe3,
+0xff, 0xbb, 0x9f, 0xff, 0xaf, 0xed, 0x3b, 0x9f,
+0x5e, 0xe7, 0x8f, 0x5f, 0xe7, 0xbf, 0xe7, 0x13,
+0x22, 0xba, 0x20, 0xb2, 0xff, 0x37, 0x6d, 0xf8,
+0x3f, 0x70, 0xf9, 0x4f, 0x3f, 0x9f, 0x7e, 0x3e,
+0xfd, 0x7c, 0xfa, 0xf9, 0xf4, 0xf3, 0xe9, 0xe7,
+0xd3, 0xcf, 0xa7, 0x9f, 0x4f, 0x3f, 0x9f, 0x7e,
+0x3e, 0xfd, 0x7c, 0xfa, 0xf9, 0xf4, 0xf3, 0xe9,
+0xe7, 0xd3, 0xcf, 0xa7, 0x9f, 0x4f, 0x3f, 0xff,
+0x7f, 0xf8, 0x61, 0x67, 0x4a, 0x22, 0x3b, 0x53,
+0xa2, 0xff, 0xbf, 0xfe, 0x2e, 0x9f, 0x7e, 0x3e,
+0xfd, 0x7c, 0xfa, 0xf9, 0xf4, 0xf3, 0xe9, 0xe7,
+0xd3, 0xcf, 0xa7, 0x9f, 0x4f, 0x3f, 0x9f, 0x7e,
+0x3e, 0xfd, 0x7c, 0xfa, 0xf9, 0xf4, 0xf3, 0xe9,
+0xe7, 0xd3, 0xcf, 0xa7, 0x9f, 0x4f, 0x3f, 0x9f,
+0x7e, 0xfe, 0xcf, 0x7e, 0x42, 0x04, 0x53, 0x21,
+0x3d, 0x7f, 0x15, 0x22, 0x14, 0x0b, 0x2c, 0xa4,
+0x10, 0x31, 0x8a, 0xfe, 0xfb, 0xae, 0xcd, 0xae,
+0x99, 0x13, 0x22, 0x49, 0x21, 0xf3, 0x6f, 0xcd,
+0xbe, 0x3c, 0x76, 0xdc, 0xff, 0x03, 0xe6, 0xeb,
+0xaf, 0xb2, 0x8c, 0x8c, 0x02, 0x00,
diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c
new file mode 100644
index 0000000..09a90ed
--- /dev/null
+++ b/board/esd/tasreg/tasreg.c
@@ -0,0 +1,432 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/m5249.h>
+#include <asm/io.h>
+
+
+/* Prototypes */
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
+
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* predefine these here for FPGA programming (before including fpga.c) */
+#define SET_FPGA(data) mbar2_writeLong(MCFSIM_GPIO1_OUT, data)
+#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_INIT)
+#define FPGA_PROG_ACTIVE_HIGH /* on this platform is PROG active high! */
+#define out32(a,b) /* nothing to do (gpio already configured) */
+
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int checkboard (void) {
+ ulong val;
+ uchar val8;
+
+ puts ("Board: ");
+ puts("esd TASREG");
+ val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
+ printf(" (Switch=%1X)\n", val8);
+
+ /*
+ * Set LED on
+ */
+ val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
+ mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
+
+ return 0;
+};
+
+
+phys_size_t initdram (int board_type) {
+ unsigned long junk = 0xa5a59696;
+
+ /*
+ * Note:
+ * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
+ */
+
+#ifdef CONFIG_SYS_FAST_CLK
+ /*
+ * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
+ * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
+ */
+ mbar_writeShort(MCFSIM_DCR, 0x8239);
+#elif CONFIG_SYS_PLL_BYPASS
+ /*
+ * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
+ * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
+ */
+ mbar_writeShort(MCFSIM_DCR, 0x8202);
+#else
+ /*
+ * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
+ * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
+ */
+ mbar_writeShort(MCFSIM_DCR, 0x8222);
+#endif
+
+ /*
+ * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
+ * PM=1 (continuous page mode)
+ */
+
+ /* RE=0 (keep auto-refresh disabled while setting up registers) */
+ mbar_writeLong(MCFSIM_DACR0, 0x00003324);
+
+ /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
+ mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
+
+ /** Precharge sequence **/
+ mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
+ out_be32((void *)0, junk); /* write to a memory location to init. precharge */
+ udelay(0x10); /* Allow several Precharge cycles */
+
+ /** Refresh Sequence **/
+ mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
+ udelay(0x7d0); /* Allow gobs of refresh cycles */
+
+ /** Mode Register initialization **/
+ mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
+ out_be32((void *)0x800, junk); /* Access RAM to initialize the mode register */
+
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+};
+
+
+int testdram (void) {
+ /* TODO: XXX XXX XXX */
+ printf ("DRAM test not implemented!\n");
+
+ return (0);
+}
+
+
+int misc_init_r (void)
+{
+ unsigned char *dst;
+ ulong len = sizeof(fpgadata);
+ int status;
+ int index;
+ int i;
+ uchar buf[8];
+
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ printf ("GUNZIP ERROR - must RESET board to recover\n");
+ do_reset (NULL, 0, 0, NULL);
+ }
+
+ status = fpga_boot(dst, len);
+ if (status != 0) {
+ printf("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf("(Timeout: DONE not high after programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("FPGA: %s\n", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+ /* delayed reboot */
+ for (i=20; i>0; i--) {
+ printf("Rebooting in %2d seconds \r",i);
+ for (index=0;index<1000;index++)
+ udelay(1000);
+ }
+ putc ('\n');
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ puts("FPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("%s ", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+
+ free(dst);
+
+ /*
+ *
+ */
+ buf[0] = 0x00;
+ buf[1] = 0x32;
+ buf[2] = 0x3f;
+ i2c_write(0x38, 0, 0, buf, 3);
+
+ return (0);
+}
+
+
+#if 1 /* test-only: board specific test commands */
+int i2c_probe(uchar addr);
+
+/*
+ */
+int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong addr;
+
+ if (argc < 2) {
+ puts("ERROR!\n");
+ return -1;
+ }
+
+ addr = simple_strtol (argv[1], NULL, 16);
+
+ printf("i2c probe looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
+
+ for (;;) {
+ i2c_probe(addr);
+
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return 0;
+ }
+
+ udelay(1000);
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ iploop, 2, 1, do_iploop,
+ "i2c probe loop <addr>",
+ ""
+);
+
+/*
+ */
+int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ uchar buf[8];
+
+ out_be16((void *)0xe0000000, 0x4000);
+
+ udelay(5000); /* wait for 5ms */
+
+ buf[0] = 0x10;
+ buf[1] = 0x07;
+ buf[2] = 0x03;
+ i2c_write(0x10, 0, 0, buf, 3);
+
+ buf[0] = 0x10;
+ buf[1] = 0x01;
+ buf[2] = 0x80;
+ i2c_write(0x10, 0, 0, buf, 3);
+
+ buf[0] = 0x10;
+ buf[1] = 0x02;
+ buf[2] = 0x03;
+ i2c_write(0x10, 0, 0, buf, 3);
+
+ buf[0] = 0x10;
+ buf[1] = 0x03;
+ buf[2] = 0x29;
+ i2c_write(0x10, 0, 0, buf, 3);
+
+ buf[0] = 0x10;
+ buf[1] = 0x04;
+ buf[2] = 0x00;
+ i2c_write(0x10, 0, 0, buf, 3);
+
+ buf[0] = 0x10;
+ buf[1] = 0x05;
+ buf[2] = 0x00;
+ i2c_write(0x10, 0, 0, buf, 3);
+
+ buf[0] = 0x10;
+ buf[1] = 0x07;
+ buf[2] = 0x02;
+ i2c_write(0x10, 0, 0, buf, 3);
+
+ return 0;
+}
+U_BOOT_CMD(
+ codec, 1, 1, do_codec,
+ "Enable codec",
+ ""
+);
+
+/*
+ */
+int do_saa(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong addr;
+ ulong instr;
+ ulong cntrl;
+ ulong data;
+ uchar buf[8];
+
+ if (argc < 5) {
+ puts("ERROR!\n");
+ return -1;
+ }
+
+ addr = simple_strtol (argv[1], NULL, 16);
+ instr = simple_strtol (argv[2], NULL, 16);
+ cntrl = simple_strtol (argv[3], NULL, 16);
+ data = simple_strtol (argv[4], NULL, 16);
+
+ buf[0] = (uchar)instr;
+ buf[1] = (uchar)cntrl;
+ buf[2] = (uchar)data;
+ i2c_write(addr, 0, 0, buf, 3);
+
+ return 0;
+}
+U_BOOT_CMD(
+ saa, 5, 1, do_saa,
+ "Write to SAA1064 <addr> <instr> <cntrl> <data>",
+ ""
+);
+
+/*
+ */
+int do_iwrite(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong addr;
+ ulong data0;
+ ulong data1;
+ ulong data2;
+ ulong data3;
+ uchar buf[8];
+ int cnt;
+
+ if (argc < 3) {
+ puts("ERROR!\n");
+ return -1;
+ }
+
+ addr = simple_strtol (argv[1], NULL, 16);
+ cnt = simple_strtol (argv[2], NULL, 16);
+ data0 = simple_strtol (argv[3], NULL, 16);
+ data1 = simple_strtol (argv[4], NULL, 16);
+ data2 = simple_strtol (argv[5], NULL, 16);
+ data3 = simple_strtol (argv[6], NULL, 16);
+
+ printf("Writing %d bytes to device %lx!\n", cnt, addr);
+ buf[0] = (uchar)data0;
+ buf[1] = (uchar)data1;
+ buf[2] = (uchar)data2;
+ buf[3] = (uchar)data3;
+ i2c_write(addr, 0, 0, buf, cnt);
+
+ return 0;
+}
+U_BOOT_CMD(
+ iwrite, 6, 1, do_iwrite,
+ "Write n bytes to I2C-device",
+ "addr cnt data0 ... datan"
+);
+
+/*
+ */
+int do_iread(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong addr;
+ ulong cnt;
+ uchar buf[32];
+ int i;
+
+ if (argc < 3) {
+ puts("ERROR!\n");
+ return -1;
+ }
+
+ addr = simple_strtol (argv[1], NULL, 16);
+ cnt = simple_strtol (argv[2], NULL, 16);
+
+ i2c_read(addr, 0, 0, buf, cnt);
+ printf("I2C Data:");
+ for (i=0; i<cnt; i++) {
+ printf(" %02X", buf[i]);
+ }
+ printf("\n");
+
+ return 0;
+}
+U_BOOT_CMD(
+ iread, 3, 1, do_iread,
+ "Read from I2C <addr> <cnt>",
+ ""
+);
+
+/*
+ */
+int do_ireadl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong addr;
+ uchar buf[32];
+ int cnt;
+
+ if (argc < 2) {
+ puts("ERROR!\n");
+ return -1;
+ }
+
+ addr = simple_strtol (argv[1], NULL, 16);
+ cnt = 1;
+
+ printf("iread looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
+
+ for (;;) {
+ i2c_read(addr, 0, 0, buf, cnt);
+
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return 0;
+ }
+
+ udelay(3000);
+ }
+
+ return 0;
+}
+U_BOOT_CMD(
+ ireadl, 2, 1, do_ireadl,
+ "Read-loop from I2C <addr>",
+ ""
+);
+#endif
diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds
new file mode 100644
index 0000000..7f9e41c
--- /dev/null
+++ b/board/esd/tasreg/u-boot.lds
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ .text :
+ {
+ arch/m68k/cpu/mcf52x2/start.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/esd/vme8349/Kconfig b/board/esd/vme8349/Kconfig
new file mode 100644
index 0000000..b8d9432
--- /dev/null
+++ b/board/esd/vme8349/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VME8349
+
+config SYS_BOARD
+ default "vme8349"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "vme8349"
+
+endif
diff --git a/board/esd/vme8349/MAINTAINERS b/board/esd/vme8349/MAINTAINERS
new file mode 100644
index 0000000..a88ba13
--- /dev/null
+++ b/board/esd/vme8349/MAINTAINERS
@@ -0,0 +1,7 @@
+VME8349 BOARD
+M: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+S: Maintained
+F: board/esd/vme8349/
+F: include/configs/vme8349.h
+F: configs/caddy2_defconfig
+F: configs/vme8349_defconfig
diff --git a/board/esd/vme8349/Makefile b/board/esd/vme8349/Makefile
new file mode 100644
index 0000000..fa11d5d
--- /dev/null
+++ b/board/esd/vme8349/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (c) 2009 esd gmbh hannover germany.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += vme8349.o caddy.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/esd/vme8349/caddy.c b/board/esd/vme8349/caddy.c
new file mode 100644
index 0000000..cd56bed
--- /dev/null
+++ b/board/esd/vme8349/caddy.c
@@ -0,0 +1,177 @@
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+
+#include "caddy.h"
+
+static struct caddy_interface *caddy_interface;
+
+void generate_answer(struct caddy_cmd *cmd, uint32_t status, uint32_t *result)
+{
+ struct caddy_answer *answer;
+ uint32_t ptr;
+
+ answer = &caddy_interface->answer[caddy_interface->answer_in];
+ memset((void *)answer, 0, sizeof(struct caddy_answer));
+ answer->answer = cmd->cmd;
+ answer->issue = cmd->issue;
+ answer->status = status;
+ memcpy(answer->par, result, 5 * sizeof(result[0]));
+ ptr = caddy_interface->answer_in + 1;
+ ptr = ptr & (ANSWER_SIZE - 1);
+ if (ptr != caddy_interface->answer_out)
+ caddy_interface->answer_in = ptr;
+}
+
+int do_caddy(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned long base_addr;
+ uint32_t ptr;
+ struct caddy_cmd *caddy_cmd;
+ uint32_t result[5];
+ uint16_t data16;
+ uint8_t data8;
+ uint32_t status;
+ pci_dev_t dev;
+ void *pci_ptr;
+
+ if (argc < 2) {
+ puts("Missing parameter\n");
+ return 1;
+ }
+
+ base_addr = simple_strtoul(argv[1], NULL, 16);
+ caddy_interface = (struct caddy_interface *) base_addr;
+
+ memset((void *)caddy_interface, 0, sizeof(struct caddy_interface));
+ memcpy((void *)&caddy_interface->magic[0], &CADDY_MAGIC, 16);
+
+ while (ctrlc() == 0) {
+ if (caddy_interface->cmd_in != caddy_interface->cmd_out) {
+ memset(result, 0, 5 * sizeof(result[0]));
+ status = 0;
+ caddy_cmd = &caddy_interface->cmd[caddy_interface->cmd_out];
+ pci_ptr = (void *)CONFIG_SYS_PCI1_IO_PHYS +
+ (caddy_cmd->addr & 0x001fffff);
+
+ switch (caddy_cmd->cmd) {
+ case CADDY_CMD_IO_READ_8:
+ result[0] = in_8(pci_ptr);
+ break;
+
+ case CADDY_CMD_IO_READ_16:
+ result[0] = in_be16(pci_ptr);
+ break;
+
+ case CADDY_CMD_IO_READ_32:
+ result[0] = in_be32(pci_ptr);
+ break;
+
+ case CADDY_CMD_IO_WRITE_8:
+ data8 = caddy_cmd->par[0] & 0x000000ff;
+ out_8(pci_ptr, data8);
+ break;
+
+ case CADDY_CMD_IO_WRITE_16:
+ data16 = caddy_cmd->par[0] & 0x0000ffff;
+ out_be16(pci_ptr, data16);
+ break;
+
+ case CADDY_CMD_IO_WRITE_32:
+ out_be32(pci_ptr, caddy_cmd->par[0]);
+ break;
+
+ case CADDY_CMD_CONFIG_READ_8:
+ dev = PCI_BDF(caddy_cmd->par[0],
+ caddy_cmd->par[1],
+ caddy_cmd->par[2]);
+ status = pci_read_config_byte(dev,
+ caddy_cmd->addr,
+ &data8);
+ result[0] = data8;
+ break;
+
+ case CADDY_CMD_CONFIG_READ_16:
+ dev = PCI_BDF(caddy_cmd->par[0],
+ caddy_cmd->par[1],
+ caddy_cmd->par[2]);
+ status = pci_read_config_word(dev,
+ caddy_cmd->addr,
+ &data16);
+ result[0] = data16;
+ break;
+
+ case CADDY_CMD_CONFIG_READ_32:
+ dev = PCI_BDF(caddy_cmd->par[0],
+ caddy_cmd->par[1],
+ caddy_cmd->par[2]);
+ status = pci_read_config_dword(dev,
+ caddy_cmd->addr,
+ &result[0]);
+ break;
+
+ case CADDY_CMD_CONFIG_WRITE_8:
+ dev = PCI_BDF(caddy_cmd->par[0],
+ caddy_cmd->par[1],
+ caddy_cmd->par[2]);
+ data8 = caddy_cmd->par[3] & 0x000000ff;
+ status = pci_write_config_byte(dev,
+ caddy_cmd->addr,
+ data8);
+ break;
+
+ case CADDY_CMD_CONFIG_WRITE_16:
+ dev = PCI_BDF(caddy_cmd->par[0],
+ caddy_cmd->par[1],
+ caddy_cmd->par[2]);
+ data16 = caddy_cmd->par[3] & 0x0000ffff;
+ status = pci_write_config_word(dev,
+ caddy_cmd->addr,
+ data16);
+ break;
+
+ case CADDY_CMD_CONFIG_WRITE_32:
+ dev = PCI_BDF(caddy_cmd->par[0],
+ caddy_cmd->par[1],
+ caddy_cmd->par[2]);
+ status = pci_write_config_dword(dev,
+ caddy_cmd->addr,
+ caddy_cmd->par[3]);
+ break;
+
+ default:
+ status = 0xffffffff;
+ break;
+ }
+
+ generate_answer(caddy_cmd, status, &result[0]);
+
+ ptr = caddy_interface->cmd_out + 1;
+ ptr = ptr & (CMD_SIZE - 1);
+ caddy_interface->cmd_out = ptr;
+ }
+
+ caddy_interface->heartbeat++;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ caddy, 2, 0, do_caddy,
+ "Start Caddy server.",
+ "Start Caddy server with Data structure a given addr\n"
+ );
diff --git a/board/esd/vme8349/caddy.h b/board/esd/vme8349/caddy.h
new file mode 100644
index 0000000..989f3c7
--- /dev/null
+++ b/board/esd/vme8349/caddy.h
@@ -0,0 +1,60 @@
+/*
+ * caddy.c -- esd VME8349 support for "missing" access modes in TSI148.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CADDY_H__
+#define __CADDY_H__
+
+#define CMD_SIZE 1024
+#define ANSWER_SIZE 1024
+#define CADDY_MAGIC "esd vme8349 V1.0"
+
+enum caddy_cmds {
+ CADDY_CMD_IO_READ_8,
+ CADDY_CMD_IO_READ_16,
+ CADDY_CMD_IO_READ_32,
+ CADDY_CMD_IO_WRITE_8,
+ CADDY_CMD_IO_WRITE_16,
+ CADDY_CMD_IO_WRITE_32,
+ CADDY_CMD_CONFIG_READ_8,
+ CADDY_CMD_CONFIG_READ_16,
+ CADDY_CMD_CONFIG_READ_32,
+ CADDY_CMD_CONFIG_WRITE_8,
+ CADDY_CMD_CONFIG_WRITE_16,
+ CADDY_CMD_CONFIG_WRITE_32,
+};
+
+struct caddy_cmd {
+ uint32_t cmd;
+ uint32_t issue;
+ uint32_t addr;
+ uint32_t par[5];
+};
+
+struct caddy_answer {
+ uint32_t answer;
+ uint32_t issue;
+ uint32_t status;
+ uint32_t par[5];
+};
+
+struct caddy_interface {
+ uint8_t magic[16];
+ uint32_t cmd_in;
+ uint32_t cmd_out;
+ uint32_t heartbeat;
+ uint32_t reserved1;
+ struct caddy_cmd cmd[CMD_SIZE];
+ uint32_t answer_in;
+ uint32_t answer_out;
+ uint32_t reserved2;
+ uint32_t reserved3;
+ struct caddy_answer answer[CMD_SIZE];
+};
+
+#endif /* of __CADDY_H__ */
diff --git a/board/esd/vme8349/pci.c b/board/esd/vme8349/pci.c
new file mode 100644
index 0000000..4d3b21d
--- /dev/null
+++ b/board/esd/vme8349/pci.c
@@ -0,0 +1,119 @@
+/*
+ * pci.c -- esd VME8349 PCI board support.
+ * Copyright (c) 2006 Wind River Systems, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * Based on MPC8349 PCI support but w/o PIB related code.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+#include "vme8349pin.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
+
+/*
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not supported. There is only one
+ * physical PCI slot on the board.
+ *
+ */
+void
+pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci1_regions };
+ u8 reg8;
+ int monarch = 0;
+
+ i2c_set_bus_num(1);
+ /* Read the PCI_M66EN jumper setting */
+ if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, 1) == 0) ||
+ (i2c_read(0x38 , 0, 0, ®8, 1) == 0)) {
+ if (reg8 & 0x40) {
+ clk->occr = 0xff000000; /* 66 MHz PCI */
+ printf("PCI: 66MHz\n");
+ } else {
+ clk->occr = 0xffff0003; /* 33 MHz PCI */
+ printf("PCI: 33MHz\n");
+ }
+ if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
+ monarch = 1;
+ } else {
+ clk->occr = 0xffff0003; /* 33 MHz PCI */
+ printf("PCI: 33MHz (I2C read failed)\n");
+ }
+ udelay(2000);
+
+ /*
+ * Assert/deassert VME reset
+ */
+ clrsetbits_be32(&immr->gpio[1].dat,
+ GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
+ GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N);
+ setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
+ GPIO2_TSI_POWERUP_RESET_N |
+ GPIO2_VME_RESET_N |
+ GPIO2_L_RESET_EN_N);
+ clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
+ udelay(200);
+ setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
+ udelay(200);
+ setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
+ udelay(600000);
+ clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+ udelay(2000);
+
+ if (monarch == 0) {
+ mpc83xx_pci_init(1, reg);
+ } else {
+ /*
+ * Release PCI RST Output signal
+ */
+ out_be32(&immr->pci_ctrl[0].gcr, 0);
+ udelay(2000);
+ out_be32(&immr->pci_ctrl[0].gcr, 1);
+ }
+}
diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c
new file mode 100644
index 0000000..f8f1834
--- /dev/null
+++ b/board/esd/vme8349/vme8349.c
@@ -0,0 +1,206 @@
+/*
+ * vme8349.c -- esd VME8349 board support
+ *
+ * Copyright (c) 2008-2009 esd gmbh.
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <spd.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <netdev.h>
+
+void ddr_enable_ecc(unsigned int dram_size);
+
+phys_size_t initdram(int board_type)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM - Main memory */
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+
+ msize = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+ /* Now check memory size (after ECC is initialized) */
+ msize = get_ram_size(0, msize);
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+#ifdef VME_CADDY2
+ puts("Board: esd VME-CADDY/2\n");
+#else
+ puts("Board: esd VME-CPU/8349\n");
+#endif
+
+ return 0;
+}
+
+#ifdef VME_CADDY2
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+
+ return 0;
+}
+#endif
+
+int misc_init_r()
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
+
+ return 0;
+}
+
+/*
+ * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
+ * and VME-CADDY/2) have different SDRAM configurations.
+ */
+#ifdef VME_CADDY2
+#define SMALL_RAM 0xff
+#define LARGE_RAM 0x00
+#else
+#define SMALL_RAM 0x00
+#define LARGE_RAM 0xff
+#endif
+
+#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
+
+static spd_eeprom_t default_spd_eeprom = {
+ SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
+ SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
+ SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
+ SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
+ SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
+ SPD_VAL(0x00, 0x00), /* 05 */
+ SPD_VAL(0x40, 0x40), /* 06 */
+ SPD_VAL(0x00, 0x00), /* 07 */
+ SPD_VAL(0x05, 0x05), /* 08 */
+ SPD_VAL(0x30, 0x30), /* 09 */
+ SPD_VAL(0x45, 0x45), /* 10 */
+ SPD_VAL(0x02, 0x02), /* 11 ecc used */
+ SPD_VAL(0x82, 0x82), /* 12 */
+ SPD_VAL(0x10, 0x10), /* 13 */
+ SPD_VAL(0x08, 0x08), /* 14 */
+ SPD_VAL(0x00, 0x00), /* 15 */
+ SPD_VAL(0x0c, 0x0c), /* 16 */
+ SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
+ SPD_VAL(0x38, 0x38), /* 18 */
+ SPD_VAL(0x00, 0x00), /* 19 */
+ SPD_VAL(0x02, 0x02), /* 20 */
+ SPD_VAL(0x00, 0x00), /* 21 */
+ SPD_VAL(0x03, 0x03), /* 22 */
+ SPD_VAL(0x3d, 0x3d), /* 23 */
+ SPD_VAL(0x45, 0x45), /* 24 */
+ SPD_VAL(0x50, 0x50), /* 25 */
+ SPD_VAL(0x45, 0x45), /* 26 */
+ SPD_VAL(0x3c, 0x3c), /* 27 */
+ SPD_VAL(0x28, 0x28), /* 28 */
+ SPD_VAL(0x3c, 0x3c), /* 29 */
+ SPD_VAL(0x2d, 0x2d), /* 30 */
+ SPD_VAL(0x20, 0x80), /* 31 */
+ SPD_VAL(0x20, 0x20), /* 32 */
+ SPD_VAL(0x27, 0x27), /* 33 */
+ SPD_VAL(0x10, 0x10), /* 34 */
+ SPD_VAL(0x17, 0x17), /* 35 */
+ SPD_VAL(0x3c, 0x3c), /* 36 */
+ SPD_VAL(0x1e, 0x1e), /* 37 */
+ SPD_VAL(0x1e, 0x1e), /* 38 */
+ SPD_VAL(0x00, 0x00), /* 39 */
+ SPD_VAL(0x00, 0x06), /* 40 */
+ SPD_VAL(0x37, 0x37), /* 41 */
+ SPD_VAL(0x4b, 0x7f), /* 42 */
+ SPD_VAL(0x80, 0x80), /* 43 */
+ SPD_VAL(0x18, 0x18), /* 44 */
+ SPD_VAL(0x22, 0x22), /* 45 */
+ SPD_VAL(0x00, 0x00), /* 46 */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ SPD_VAL(0x10, 0x10), /* 62 */
+ SPD_VAL(0x7e, 0x1d), /* 63 */
+ { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
+ SPD_VAL(0x00, 0x00), /* 72 */
+#ifdef VME_CADDY2
+ { "vme-caddy/2 ram " }
+#else
+ { "vme-cpu/2 ram " }
+#endif
+};
+
+int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ int old_bus = i2c_get_bus_num();
+ unsigned int l, sum;
+ int valid = 0;
+
+ i2c_set_bus_num(0);
+
+ if (i2c_read(chip, addr, alen, buffer, len) == 0)
+ if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
+ sum = 0;
+ for (l = 0; l < 63; l++)
+ sum = (sum + buffer[l]) & 0xff;
+ if (sum == buffer[63])
+ valid = 1;
+ else
+ printf("Invalid checksum in EEPROM %02x %02x\n",
+ sum, buffer[63]);
+ }
+
+ if (valid == 0) {
+ memcpy(buffer, (void *)&default_spd_eeprom, len);
+ sum = 0;
+ for (l = 0; l < 63; l++)
+ sum = (sum + buffer[l]) & 0xff;
+ if (sum != buffer[63])
+ printf("Invalid checksum in FLASH %02x %02x\n",
+ sum, buffer[63]);
+ buffer[63] = sum;
+ }
+
+ i2c_set_bus_num(old_bus);
+
+ return 0;
+}
diff --git a/board/esd/vme8349/vme8349pin.h b/board/esd/vme8349/vme8349pin.h
new file mode 100644
index 0000000..fcf6c59
--- /dev/null
+++ b/board/esd/vme8349/vme8349pin.h
@@ -0,0 +1,19 @@
+/*
+ * vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __VME8349PIN_H__
+#define __VME8349PIN_H__
+
+#define GPIO2_V_SCON 0x80000000 /* In: from tsi148 1: is syscon */
+#define GPIO2_VME_RESET_N 0x20000000 /* Out: to tsi148 */
+#define GPIO2_TSI_PLL_RESET_N 0x08000000 /* Out: to tsi148 */
+#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148 */
+#define GPIO2_L_RESET_EN_N 0x00100000 /* Out: 0:vme can assert cpu lrst*/
+
+#endif /* of ifndef __VME8349PIN_H__ */
diff --git a/board/esd/voh405/Kconfig b/board/esd/voh405/Kconfig
new file mode 100644
index 0000000..d9fe9d2
--- /dev/null
+++ b/board/esd/voh405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VOH405
+
+config SYS_BOARD
+ default "voh405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "VOH405"
+
+endif
diff --git a/board/esd/voh405/MAINTAINERS b/board/esd/voh405/MAINTAINERS
new file mode 100644
index 0000000..0039f5d
--- /dev/null
+++ b/board/esd/voh405/MAINTAINERS
@@ -0,0 +1,6 @@
+VOH405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/voh405/
+F: include/configs/VOH405.h
+F: configs/VOH405_defconfig
diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile
new file mode 100644
index 0000000..3d82399
--- /dev/null
+++ b/board/esd/voh405/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = voh405.o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c
new file mode 100644
index 0000000..23e8164
--- /dev/null
+++ b/board/esd/voh405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b0 = -size_b0;
+ switch (size_b0) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/voh405/fpgadata.c b/board/esd/voh405/fpgadata.c
new file mode 100644
index 0000000..9ad9650
--- /dev/null
+++ b/board/esd/voh405/fpgadata.c
@@ -0,0 +1,4021 @@
+0x1f, 0x8b, 0x08, 0x08, 0x38, 0x6c, 0x35, 0x42,
+0x00, 0x03, 0x76, 0x6f, 0x68, 0x34, 0x30, 0x35,
+0x5f, 0x31, 0x5f, 0x30, 0x33, 0x2e, 0x62, 0x69,
+0x74, 0x00, 0xed, 0xfd, 0x7d, 0x7c, 0x1c, 0xd5,
+0x91, 0x2f, 0x8c, 0x57, 0x9f, 0x6e, 0xc9, 0xad,
+0xe9, 0x91, 0xa6, 0xf5, 0x62, 0x22, 0x40, 0x98,
+0xd6, 0x48, 0x98, 0x41, 0x19, 0x49, 0x63, 0xc9,
+0x18, 0x63, 0xcc, 0xa8, 0x2d, 0x09, 0x22, 0x6c,
+0x07, 0x4f, 0x80, 0xcd, 0xfa, 0x66, 0xb9, 0xd9,
+0x31, 0xf1, 0x66, 0xbd, 0xfb, 0x73, 0xb8, 0x82,
+0xe4, 0xd9, 0x75, 0x72, 0xb3, 0xe4, 0x68, 0x24,
+0xdb, 0x23, 0xcb, 0xc1, 0x83, 0x71, 0x88, 0x20,
+0xde, 0xec, 0xd8, 0x78, 0x89, 0x21, 0x4e, 0xee,
+0x58, 0x36, 0x20, 0x63, 0x16, 0x5a, 0x46, 0x80,
+0x6c, 0x8c, 0x51, 0x58, 0x27, 0xeb, 0x10, 0x42,
+0xc6, 0x44, 0x21, 0x82, 0x18, 0x22, 0x8c, 0x49,
+0xe4, 0xf7, 0xe7, 0xd4, 0xe9, 0x97, 0xe9, 0x99,
+0x91, 0xd9, 0xcd, 0xbd, 0xf7, 0x79, 0xee, 0x7e,
+0x7e, 0x8f, 0x27, 0x7f, 0xa4, 0xe8, 0x39, 0x6e,
+0xf5, 0xa9, 0x39, 0x5d, 0xf5, 0x3d, 0x55, 0xdf,
+0xaa, 0x03, 0x45, 0xbe, 0x09, 0xf3, 0x7f, 0x00,
+0xc2, 0x32, 0x50, 0xff, 0xee, 0xbf, 0xad, 0x98,
+0x1d, 0xba, 0xf6, 0x2f, 0x67, 0xfd, 0x65, 0xa8,
+0xb9, 0xe1, 0xee, 0x2f, 0x2d, 0x87, 0xbb, 0x40,
+0x69, 0xfa, 0xea, 0xb5, 0xa1, 0xbf, 0xfa, 0xda,
+0x3d, 0xb3, 0x66, 0xcf, 0x86, 0x2f, 0xb1, 0xff,
+0x0a, 0x85, 0xae, 0x6d, 0x0c, 0x35, 0x37, 0xce,
+0x9a, 0x0d, 0xcb, 0xa1, 0x68, 0xd6, 0xac, 0x79,
+0xb3, 0xaf, 0x9f, 0xd7, 0x34, 0x17, 0xfe, 0x0a,
+0x84, 0xe6, 0x6d, 0xe7, 0xd9, 0xe7, 0x89, 0x87,
+0xff, 0xec, 0xcb, 0x21, 0xa0, 0x02, 0x00, 0x4c,
+0x0b, 0x09, 0x51, 0xfc, 0x7f, 0x25, 0x24, 0x68,
+0x02, 0xd0, 0x96, 0xfa, 0x10, 0x18, 0xf8, 0xdf,
+0x60, 0x7d, 0x5f, 0x14, 0x02, 0xcd, 0xfd, 0xdf,
+0x42, 0x08, 0x74, 0x88, 0x80, 0xbe, 0x5e, 0x2d,
+0x83, 0x7f, 0xff, 0x23, 0xe8, 0x12, 0xb5, 0xe5,
+0x3f, 0x71, 0xfc, 0xf9, 0x03, 0xf4, 0x82, 0xc3,
+0x32, 0x9f, 0x96, 0xe3, 0x49, 0x4b, 0x52, 0x49,
+0xe8, 0x3f, 0x72, 0x7f, 0xb0, 0xef, 0xfa, 0xfb,
+0x37, 0xfe, 0x43, 0xf7, 0xff, 0x83, 0x7d, 0xff,
+0x3f, 0x75, 0x3c, 0xa8, 0xff, 0x81, 0xe1, 0x00,
+0x92, 0xf3, 0x3c, 0xaa, 0xa0, 0x41, 0x07, 0x14,
+0x82, 0x40, 0x21, 0x0a, 0x95, 0x17, 0x10, 0x5a,
+0x86, 0xed, 0xf1, 0x86, 0x70, 0x0e, 0xce, 0xd3,
+0x96, 0x03, 0xbe, 0x81, 0xee, 0x7b, 0xe1, 0x1c,
+0x84, 0xf5, 0xe2, 0x09, 0xf1, 0x3e, 0xf5, 0x4d,
+0xb5, 0x45, 0xf3, 0xbd, 0x24, 0x1e, 0x87, 0x33,
+0xb4, 0xb9, 0xd2, 0xbb, 0x4f, 0x0c, 0x41, 0xa7,
+0x3d, 0x3e, 0xfe, 0x63, 0xd8, 0x4b, 0x1b, 0x26,
+0x94, 0x13, 0x7d, 0x7e, 0x58, 0x67, 0x34, 0xec,
+0xf3, 0x9c, 0x28, 0xab, 0xad, 0xe8, 0x8d, 0x34,
+0x68, 0x4a, 0x8c, 0xbc, 0x03, 0x83, 0xd4, 0x2f,
+0xcb, 0xb1, 0x7d, 0xa1, 0x5a, 0x5b, 0x8b, 0x23,
+0xd2, 0x7a, 0xd8, 0x05, 0x41, 0x43, 0x69, 0x22,
+0x00, 0x03, 0x0b, 0x82, 0x23, 0x97, 0xce, 0x22,
+0x2b, 0x20, 0xa1, 0xad, 0xd4, 0x94, 0x42, 0x62,
+0xc0, 0x20, 0x68, 0x95, 0x72, 0x39, 0x69, 0x02,
+0xcd, 0xbe, 0xbf, 0xb4, 0x03, 0xf6, 0x42, 0x83,
+0xa1, 0xa4, 0x88, 0x46, 0xd7, 0x91, 0x86, 0xb4,
+0x27, 0x45, 0x02, 0x6a, 0x3c, 0x7e, 0xab, 0xae,
+0xc4, 0x49, 0x5a, 0xdf, 0x43, 0xfd, 0x9a, 0xdc,
+0x4f, 0x42, 0x92, 0xfd, 0x3c, 0x37, 0x4d, 0x3f,
+0x06, 0xa7, 0xd9, 0x78, 0x5f, 0xaa, 0xcd, 0x0f,
+0xa7, 0x92, 0xe1, 0x0f, 0x8b, 0x53, 0x0b, 0x16,
+0xc3, 0x11, 0x63, 0x86, 0xe0, 0x7b, 0x44, 0x4c,
+0xc3, 0x84, 0x36, 0xb0, 0xc2, 0xbb, 0x5e, 0x54,
+0xdb, 0xed, 0xf1, 0x49, 0xe1, 0x59, 0x78, 0x1e,
+0xae, 0x64, 0xe3, 0xd9, 0x77, 0x1f, 0x24, 0xc2,
+0x86, 0x38, 0xe1, 0x3f, 0xc1, 0xee, 0xd0, 0xa2,
+0xfa, 0xa8, 0x78, 0x02, 0x35, 0x00, 0xbe, 0x44,
+0xdb, 0x38, 0xd3, 0x94, 0xf9, 0x19, 0x55, 0x77,
+0xb0, 0x6f, 0xc3, 0x86, 0x2f, 0x24, 0x26, 0xd5,
+0x53, 0xd0, 0x34, 0x5a, 0x9c, 0x12, 0x8f, 0xc1,
+0x49, 0x68, 0xea, 0xf2, 0x25, 0x6f, 0x0f, 0x56,
+0x8f, 0xab, 0xe1, 0x98, 0x77, 0x4b, 0x77, 0x48,
+0xb2, 0x9f, 0x7f, 0xa4, 0x20, 0xa8, 0xee, 0x85,
+0x46, 0x43, 0x99, 0x28, 0x9b, 0x16, 0x5f, 0x07,
+0x73, 0x0c, 0x79, 0x82, 0x1c, 0x83, 0x3d, 0x11,
+0xbf, 0xa1, 0xac, 0xf6, 0x37, 0xb0, 0xaf, 0x1a,
+0x64, 0x39, 0x41, 0xe6, 0xb0, 0xd5, 0x6f, 0xcf,
+0x77, 0x31, 0x3c, 0x08, 0xb5, 0x86, 0x12, 0x22,
+0x14, 0x06, 0x88, 0xdf, 0x90, 0x53, 0x64, 0x31,
+0x0c, 0xa8, 0x01, 0x43, 0x09, 0x10, 0x05, 0x1e,
+0x1d, 0x69, 0x48, 0xca, 0xdb, 0x0b, 0x57, 0xb1,
+0x77, 0xc5, 0xfc, 0x4c, 0xc0, 0x17, 0xe1, 0x69,
+0x5a, 0x9f, 0x56, 0x56, 0x91, 0x32, 0xf8, 0x76,
+0xe2, 0xaa, 0xb4, 0xbc, 0xaa, 0xf0, 0x67, 0xb0,
+0x1b, 0xaf, 0x2c, 0x25, 0x33, 0x54, 0xf6, 0x55,
+0x54, 0x5e, 0x4a, 0xee, 0x73, 0xee, 0xdf, 0x01,
+0x8b, 0xd5, 0x8f, 0x60, 0xbe, 0xe1, 0x9b, 0x2b,
+0x52, 0xf8, 0x50, 0x0d, 0x4d, 0x7a, 0x43, 0xe2,
+0x08, 0x9d, 0x60, 0x8a, 0xf7, 0x95, 0xf6, 0x41,
+0xf2, 0x2e, 0x98, 0xaf, 0x7b, 0x0b, 0xc5, 0xdb,
+0x88, 0xbd, 0x90, 0xf4, 0x2b, 0x9e, 0x85, 0xf3,
+0xd0, 0xc2, 0xf4, 0xd3, 0x35, 0xaa, 0x7f, 0x58,
+0x1a, 0x8e, 0x97, 0xec, 0x14, 0x27, 0xe1, 0x8c,
+0xda, 0x7c, 0x87, 0xef, 0x27, 0xe2, 0x04, 0x7e,
+0xd5, 0xbe, 0x61, 0x54, 0x4c, 0x14, 0xda, 0xfa,
+0x91, 0x81, 0xeb, 0x67, 0xcc, 0x3b, 0xd0, 0x0d,
+0xf0, 0x06, 0x0d, 0xa5, 0xbd, 0xbb, 0xbb, 0x83,
+0x6c, 0x58, 0xd3, 0x88, 0x6f, 0x42, 0x7c, 0x0f,
+0xf6, 0xb7, 0x37, 0x1a, 0xde, 0xb4, 0xe8, 0x71,
+0x7e, 0xdf, 0x91, 0xca, 0xcd, 0xf0, 0x34, 0xd4,
+0x8f, 0x14, 0xdf, 0x2b, 0x26, 0xe0, 0xa7, 0x50,
+0x6d, 0x14, 0xfc, 0x9d, 0x78, 0x07, 0xfb, 0x45,
+0xaa, 0x47, 0x94, 0x08, 0x79, 0xd3, 0xf8, 0xc1,
+0x8a, 0x46, 0x5d, 0x1e, 0x25, 0x4d, 0x8e, 0x3e,
+0x35, 0xf8, 0x3e, 0x9b, 0x6f, 0x30, 0x5d, 0xf4,
+0x0d, 0xcf, 0x57, 0xe1, 0x01, 0x5a, 0x93, 0xee,
+0x58, 0x55, 0xf8, 0x45, 0x78, 0x92, 0x56, 0x6f,
+0x63, 0x1a, 0x38, 0xb7, 0xa0, 0x27, 0x5e, 0x9f,
+0x8e, 0xaf, 0x20, 0xaa, 0x73, 0xff, 0x15, 0xd6,
+0x7a, 0x2b, 0x4a, 0x91, 0x0d, 0xf0, 0x80, 0xa0,
+0x19, 0x0f, 0xa7, 0xc8, 0x57, 0xe8, 0x9e, 0x94,
+0x96, 0x56, 0xfe, 0x91, 0x1c, 0xa4, 0x8f, 0x42,
+0xf0, 0x2e, 0xf9, 0x32, 0x4f, 0x99, 0x73, 0xff,
+0xf1, 0xe9, 0xe3, 0xc2, 0x29, 0x08, 0xd3, 0xe2,
+0xa4, 0xb8, 0x0a, 0xde, 0x92, 0x76, 0xd1, 0x91,
+0xa4, 0xf8, 0x75, 0x38, 0xa7, 0x0f, 0xc4, 0x7c,
+0x63, 0xe2, 0x7b, 0xda, 0x01, 0x68, 0x19, 0x0c,
+0xbe, 0x27, 0xce, 0x93, 0xec, 0xf9, 0x76, 0x08,
+0x49, 0x98, 0x84, 0xb0, 0xe0, 0xa3, 0x35, 0x28,
+0xdc, 0xe7, 0xf5, 0xd1, 0xdb, 0xd3, 0x15, 0x93,
+0x7a, 0x58, 0xf5, 0xad, 0xa9, 0x39, 0x5a, 0x39,
+0xd9, 0x1a, 0x86, 0x0d, 0x3d, 0xe2, 0xeb, 0x60,
+0xaf, 0x7f, 0x59, 0xdd, 0xc6, 0x56, 0x4b, 0x58,
+0xf7, 0x25, 0xca, 0x67, 0x26, 0x2d, 0xa1, 0x16,
+0xf6, 0x43, 0x53, 0x74, 0x43, 0x7f, 0x73, 0xad,
+0x7a, 0x12, 0xe6, 0x47, 0xbd, 0xa5, 0x22, 0x91,
+0xec, 0xf1, 0x54, 0x5a, 0xce, 0xc6, 0x37, 0xe8,
+0x8b, 0x12, 0xa4, 0xa7, 0xac, 0x97, 0x09, 0x25,
+0x09, 0xb2, 0x0d, 0x7a, 0x75, 0xff, 0x4b, 0x4a,
+0xbf, 0x27, 0x48, 0xf7, 0xea, 0x0d, 0x2b, 0xd8,
+0xfa, 0xd7, 0x1c, 0xb3, 0x30, 0xb7, 0xa0, 0x16,
+0x1e, 0x66, 0xc3, 0x2e, 0x4f, 0x90, 0xab, 0xc8,
+0xe3, 0x4c, 0x50, 0x12, 0x85, 0xb5, 0xd0, 0x1b,
+0xdd, 0xaa, 0x2b, 0x0f, 0x90, 0xda, 0xf8, 0x1e,
+0xda, 0x70, 0x13, 0x5b, 0x6f, 0x85, 0xce, 0x7a,
+0xd0, 0x2a, 0x24, 0xd8, 0x02, 0x41, 0x5d, 0xa9,
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diff --git a/board/esd/voh405/logo_320_240_4bpp.c b/board/esd/voh405/logo_320_240_4bpp.c
new file mode 100644
index 0000000..5dfc1f7
--- /dev/null
+++ b/board/esd/voh405/logo_320_240_4bpp.c
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diff --git a/board/esd/voh405/logo_640_480_24bpp.c b/board/esd/voh405/logo_640_480_24bpp.c
new file mode 100644
index 0000000..defa69f
--- /dev/null
+++ b/board/esd/voh405/logo_640_480_24bpp.c
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+0x1f, 0xf8, 0xf2, 0xff, 0x07, 0x66, 0x87, 0xe4,
+0x0f, 0x36, 0x10, 0x0e, 0x00,
diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c
new file mode 100644
index 0000000..3cc2206
--- /dev/null
+++ b/board/esd/voh405/voh405.c
@@ -0,0 +1,377 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp_320[] =
+{
+#include "logo_320_240_4bpp.c"
+};
+
+unsigned char logo_bmp_640[] =
+{
+#include "logo_640_480_24bpp.c"
+};
+
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+
+#include "../common/s1d13704_320_240_4bpp.h"
+#include "../common/s1d13806_320_240_4bpp.h"
+#include "../common/s1d13806_640_480_16bpp.h"
+
+
+int board_early_init_f (void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFFB5); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ */
+ mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+ unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+ unsigned short *lcd_contrast =
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
+ unsigned short *lcd_backlight =
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
+ unsigned char *dst;
+ ulong len = sizeof(fpgadata);
+ int status;
+ int index;
+ int i;
+ char *str;
+
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ printf ("GUNZIP ERROR - must RESET board to recover\n");
+ do_reset (NULL, 0, 0, NULL);
+ }
+
+ status = fpga_boot(dst, len);
+ if (status != 0) {
+ printf("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf("(Timeout: DONE not high after programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("FPGA: %s\n", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+ /* delayed reboot */
+ for (i=20; i>0; i--) {
+ printf("Rebooting in %2d seconds \r",i);
+ for (index=0;index<1000;index++)
+ udelay(1000);
+ }
+ putc ('\n');
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ puts("FPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("%s ", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+
+ free(dst);
+
+ /*
+ * Reset FPGA via FPGA_INIT pin
+ */
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */
+ udelay(1000); /* wait 1ms */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */
+ udelay(1000); /* wait 1ms */
+
+ /*
+ * Reset external DUARTs
+ */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
+ udelay(10); /* wait 10us */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
+ udelay(1000); /* wait 1ms */
+
+ /*
+ * Set NAND-FLASH GPIO signals to default
+ */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+
+ /*
+ * Setup EEPROM write protection
+ */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
+
+ /*
+ * Enable interrupts in exar duart mcr[3]
+ */
+ out_8(duart0_mcr, 0x08);
+ out_8(duart1_mcr, 0x08);
+
+ /*
+ * Init lcd interface and display logo
+ */
+ str = getenv("bd_type");
+ if (strcmp(str, "voh405_bw") == 0) {
+ lcd_setup(0, 1);
+ lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+ regs_13704_320_240_4bpp,
+ sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+ logo_bmp_320, sizeof(logo_bmp_320));
+ } else if (strcmp(str, "voh405_bwbw") == 0) {
+ lcd_setup(0, 1);
+ lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+ regs_13704_320_240_4bpp,
+ sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+ logo_bmp_320, sizeof(logo_bmp_320));
+ lcd_setup(1, 1);
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+ regs_13806_320_240_4bpp,
+ sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
+ logo_bmp_320, sizeof(logo_bmp_320));
+ } else if (strcmp(str, "voh405_bwc") == 0) {
+ lcd_setup(0, 1);
+ lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
+ regs_13704_320_240_4bpp,
+ sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+ logo_bmp_320, sizeof(logo_bmp_320));
+ lcd_setup(1, 0);
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
+ regs_13806_640_480_16bpp,
+ sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
+ logo_bmp_640, sizeof(logo_bmp_640));
+ } else {
+ printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+ return 0;
+ }
+
+ /*
+ * Set invert bit in small lcd controller
+ */
+ out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2),
+ in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01);
+
+ /*
+ * Set default contrast voltage on epson vga controller
+ */
+ out_be16(lcd_contrast, 0x4646);
+
+ /*
+ * Enable backlight
+ */
+ out_be16(lcd_backlight, 0xffff);
+
+ /*
+ * Enable external I2C bus
+ */
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON);
+
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming VOH405");
+ } else {
+ puts(str);
+ }
+
+ if (getenv_f("bd_type", str, sizeof(str)) != -1) {
+ printf(" (%s)", str);
+ } else {
+ puts(" (Missing bd_type!)");
+ }
+
+ putc ('\n');
+
+ return 0;
+}
+
+#ifdef CONFIG_IDE_RESET
+#define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
+void ide_set_reset(int on)
+{
+ /*
+ * Assert or deassert CompactFlash Reset Pin
+ */
+ if (on) { /* assert RESET */
+ out_be16((void *)FPGA_MODE,
+ in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
+ } else { /* release RESET */
+ out_be16((void *)FPGA_MODE,
+ in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
+ }
+}
+#endif /* CONFIG_IDE_RESET */
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO0. */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO0. */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts ("Query of write access state failed.\n");
+ } else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0) {
+ puts ("Setup of write access state failed.\n");
+ }
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "Enable / disable / query EEPROM write access",
+ ""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/vom405/Kconfig b/board/esd/vom405/Kconfig
new file mode 100644
index 0000000..ecdf8c9
--- /dev/null
+++ b/board/esd/vom405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VOM405
+
+config SYS_BOARD
+ default "vom405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "VOM405"
+
+endif
diff --git a/board/esd/vom405/MAINTAINERS b/board/esd/vom405/MAINTAINERS
new file mode 100644
index 0000000..385f60a
--- /dev/null
+++ b/board/esd/vom405/MAINTAINERS
@@ -0,0 +1,6 @@
+VOM405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/vom405/
+F: include/configs/VOM405.h
+F: configs/VOM405_defconfig
diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile
new file mode 100644
index 0000000..7cf5c02
--- /dev/null
+++ b/board/esd/vom405/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD = ../common/xilinx_jtag/lenval.o \
+ ../common/xilinx_jtag/micro.o \
+ ../common/xilinx_jtag/ports.o
+
+obj-y = vom405.o flash.o ../common/misc.o $(CPLD)
diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c
new file mode 100644
index 0000000..23e8164
--- /dev/null
+++ b/board/esd/vom405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b0 = -size_b0;
+ switch (size_b0) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c
new file mode 100644
index 0000000..7de6f66
--- /dev/null
+++ b/board/esd/vom405/vom405.c
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <sja1000.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void lxt971_no_sleep(void);
+
+/*
+ * generate a short spike on the CAN tx line
+ * to bring the couplers in sync
+ */
+void init_coupler(u32 addr)
+{
+ struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
+
+ /* reset */
+ out_8(&ctrl->cr, CR_RR);
+
+ /* dominant */
+ out_8(&ctrl->btr0, 0x00); /* btr setup is required */
+ out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
+ out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
+ OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
+ out_8(&ctrl->cr, 0x00);
+
+ /* delay */
+ in_8(&ctrl->cr);
+ in_8(&ctrl->cr);
+ in_8(&ctrl->cr);
+ in_8(&ctrl->cr);
+
+ /* reset */
+ out_8(&ctrl->cr, CR_RR);
+}
+
+int board_early_init_f (void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ */
+ mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ /*
+ * Reset CPLD via GPIO12 (CS3) pin
+ */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 12));
+ udelay(1000); /* wait 1ms */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | (0x80000000 >> 12));
+ udelay(1000); /* wait 1ms */
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /*
+ * Init magnetic coupler
+ */
+ if (!getenv("noinitcoupler"))
+ init_coupler(CAN_BA);
+
+ return (0);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+ int flashcnt;
+ int delay;
+ u8 *led_reg = (u8 *)(CAN_BA + 0x1000);
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming VOM405");
+ } else {
+ puts(str);
+ }
+
+ printf(" (PLD-Version=%02d)\n", in_8(led_reg));
+
+ /*
+ * Flash LEDs
+ */
+ for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+ out_8(led_reg, 0x40); /* LED_B..D off */
+ for (delay = 0; delay < 100; delay++)
+ udelay(1000);
+ out_8(led_reg, 0x47); /* LED_B..D on */
+ for (delay = 0; delay < 50; delay++)
+ udelay(1000);
+ }
+ out_8(led_reg, 0x40);
+
+ return 0;
+}
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
diff --git a/board/esd/wuh405/Kconfig b/board/esd/wuh405/Kconfig
new file mode 100644
index 0000000..8a7df4d
--- /dev/null
+++ b/board/esd/wuh405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_WUH405
+
+config SYS_BOARD
+ default "wuh405"
+
+config SYS_VENDOR
+ default "esd"
+
+config SYS_CONFIG_NAME
+ default "WUH405"
+
+endif
diff --git a/board/esd/wuh405/MAINTAINERS b/board/esd/wuh405/MAINTAINERS
new file mode 100644
index 0000000..782c72a
--- /dev/null
+++ b/board/esd/wuh405/MAINTAINERS
@@ -0,0 +1,6 @@
+WUH405 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/esd/wuh405/
+F: include/configs/WUH405.h
+F: configs/WUH405_defconfig
diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile
new file mode 100644
index 0000000..b9beeff
--- /dev/null
+++ b/board/esd/wuh405/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = wuh405.o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c
new file mode 100644
index 0000000..23e8164
--- /dev/null
+++ b/board/esd/wuh405/flash.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+ int i;
+ uint pbcr;
+ unsigned long base_b0;
+ int size_val = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0<<20);
+ }
+
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ base_b0 = -size_b0;
+ switch (size_b0) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ flash_info[0].size = size_b0;
+
+ return (size_b0);
+}
diff --git a/board/esd/wuh405/fpgadata.c b/board/esd/wuh405/fpgadata.c
new file mode 100644
index 0000000..a964f9f
--- /dev/null
+++ b/board/esd/wuh405/fpgadata.c
@@ -0,0 +1,3636 @@
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+0x5f, 0x31, 0x2e, 0x62, 0x69, 0x74, 0x00, 0xec,
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+0x41, 0x92, 0xe4, 0xc3, 0xc5, 0x5d, 0xcf, 0xac,
+0x0e, 0xd1, 0xb1, 0xd2, 0x97, 0xab, 0xf9, 0x0f,
+0xec, 0x3e, 0x7a, 0xba, 0xdc, 0x7a, 0x93, 0xfe,
+0xd2, 0xee, 0x82, 0xb1, 0x52, 0x6b, 0x35, 0xf7,
+0x81, 0xfd, 0x75, 0x2a, 0xcd, 0x9c, 0xf2, 0x76,
+0xdc, 0xac, 0xb5, 0x40, 0x1b, 0x38, 0x0f, 0x8c,
+0x8a, 0x24, 0x1d, 0xa7, 0x06, 0xbf, 0x92, 0xbb,
+0x8d, 0x53, 0x33, 0xfc, 0xc8, 0xb0, 0xe8, 0x03,
+0x35, 0x8a, 0xc9, 0x17, 0x2f, 0x60, 0x02, 0xde,
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+0x3c, 0x6a, 0x92, 0xb0, 0xcc, 0xa5, 0xc8, 0x8c,
+0x7e, 0x74, 0x7e, 0xf1, 0xf8, 0x8e, 0x5b, 0x1e,
+0x16, 0xeb, 0x22, 0x71, 0x58, 0xf2, 0x81, 0x1b,
+0x35, 0xc5, 0x93, 0xbb, 0x39, 0xab, 0x8b, 0x9a,
+0xa5, 0x18, 0x1e, 0xda, 0xd5, 0xbf, 0x3e, 0xec,
+0x32, 0xd1, 0xbb, 0x98, 0xf1, 0x6d, 0x9e, 0x68,
+0x80, 0x09, 0x0d, 0x4d, 0x3b, 0x6f, 0xf6, 0xb7,
+0x08, 0x8b, 0x05, 0xe2, 0x8b, 0x32, 0x82, 0xcc,
+0x84, 0xc1, 0xd1, 0xbb, 0x0f, 0xd3, 0xa2, 0x45,
+0xfc, 0xea, 0xf1, 0x34, 0xdc, 0x80, 0x83, 0x1e,
+0x89, 0x9e, 0x28, 0xb0, 0x3a, 0x1f, 0x66, 0x0b,
+0xb8, 0xdf, 0x49, 0x50, 0x2c, 0xe0, 0xb6, 0xe8,
+0xff, 0x58, 0x80, 0x62, 0x65, 0xb5, 0x47, 0x1e,
+0x32, 0x2b, 0xb5, 0xe6, 0xef, 0x43, 0x32, 0xf8,
+0x77, 0x3e, 0xe4, 0xac, 0x81, 0x85, 0x4d, 0xd3,
+0xfc, 0x7b, 0x11, 0x0c, 0xd3, 0xa3, 0x2f, 0x21,
+0xcd, 0x9a, 0xad, 0x1b, 0xf8, 0x90, 0xd6, 0xcd,
+0x6a, 0xd8, 0x92, 0xb2, 0x6a, 0x56, 0x14, 0x0f,
+0x13, 0xfc, 0xe6, 0x8d, 0xe0, 0x4d, 0x17, 0x06,
+0x90, 0xdf, 0x7e, 0x28, 0x2e, 0xd3, 0x93, 0xd7,
+0xcb, 0xf0, 0xd0, 0x04, 0xb5, 0x79, 0x14, 0x0f,
+0xf9, 0x2c, 0x3e, 0xf4, 0x9f, 0x69, 0xa9, 0x35,
+0x2b, 0xda, 0x22, 0x19, 0x0e, 0xcf, 0x2f, 0x78,
+0x38, 0x34, 0xb6, 0xb8, 0xf0, 0xba, 0x11, 0x2d,
+0xb8, 0xbf, 0x47, 0xf3, 0x53, 0xc4, 0x53, 0x24,
+0x0e, 0xe4, 0xd1, 0xd7, 0x8d, 0x8d, 0x37, 0xb5,
+0x6e, 0x1a, 0x87, 0x86, 0x9b, 0xfb, 0x69, 0x01,
+0x07, 0x3c, 0xc3, 0x9d, 0xc0, 0x70, 0x89, 0x58,
+0x17, 0x56, 0x40, 0x85, 0xc9, 0x3c, 0x63, 0xa2,
+0xe9, 0x53, 0x00, 0x31, 0xf3, 0x4d, 0x9c, 0x05,
+0x8e, 0x88, 0x96, 0xd5, 0x6b, 0xa5, 0x72, 0xc3,
+0x84, 0x2d, 0xa0, 0xc4, 0x33, 0x85, 0x34, 0x58,
+0x0e, 0x3a, 0x4f, 0xb9, 0x53, 0x08, 0x8a, 0x7f,
+0x0a, 0xd2, 0xae, 0xd1, 0x00, 0xc5, 0x54, 0x93,
+0x18, 0x15, 0x5e, 0x25, 0x82, 0xdf, 0x3a, 0x82,
+0xa3, 0x96, 0xb3, 0x26, 0xcd, 0x9b, 0x56, 0xfb,
+0x5a, 0xe2, 0xbb, 0x04, 0x5b, 0x8a, 0xce, 0x3a,
+0x96, 0x96, 0x1d, 0xec, 0xe8, 0xa9, 0x43, 0xca,
+0xf5, 0x92, 0x84, 0x73, 0x81, 0x77, 0x04, 0xbd,
+0x2e, 0x59, 0x8b, 0x5d, 0xe0, 0x4b, 0x68, 0x92,
+0x6b, 0x20, 0x4c, 0x1b, 0x9a, 0xd8, 0x85, 0x92,
+0x68, 0x51, 0xf2, 0x49, 0x31, 0x3f, 0x22, 0xe9,
+0xf1, 0x0d, 0xd7, 0x8c, 0xf8, 0x90, 0x0e, 0x94,
+0xcf, 0x04, 0x6d, 0xa7, 0xd2, 0x0f, 0xc9, 0x85,
+0x2b, 0x02, 0x1d, 0xed, 0xd5, 0x66, 0x3c, 0x0c,
+0xa1, 0x57, 0xa6, 0x1d, 0xe4, 0x73, 0x34, 0xa3,
+0x21, 0x16, 0xce, 0xf0, 0xdd, 0x15, 0xab, 0x12,
+0x0f, 0xce, 0x64, 0x4c, 0x32, 0x41, 0x62, 0x11,
+0x6e, 0xa1, 0xf9, 0x4a, 0x80, 0x69, 0xe7, 0x1d,
+0x2a, 0x5b, 0xd0, 0x84, 0x87, 0x5c, 0x75, 0x3f,
+0xcd, 0x07, 0x70, 0x89, 0xec, 0x87, 0xec, 0x2c,
+0x3c, 0x2a, 0x1f, 0x21, 0x07, 0x20, 0xcb, 0xed,
+0x47, 0xf4, 0x12, 0x9a, 0xa3, 0x68, 0x7a, 0x2e,
+0x81, 0x34, 0x11, 0x1f, 0x32, 0x32, 0x01, 0xde,
+0x32, 0xf2, 0x21, 0xc6, 0xc3, 0x3d, 0xde, 0xee,
+0xc7, 0x10, 0x0b, 0xf9, 0xb4, 0xc0, 0xc2, 0x02,
+0x99, 0xe7, 0x41, 0x68, 0xb8, 0x12, 0x0f, 0xce,
+0xb7, 0x9b, 0x72, 0xfe, 0xfc, 0xa4, 0x8c, 0x34,
+0x58, 0xc5, 0x32, 0x6a, 0xb6, 0xdc, 0xe0, 0xc3,
+0xb2, 0x98, 0x6f, 0x82, 0x0f, 0xd5, 0xf5, 0x45,
+0x20, 0xe3, 0xb4, 0x86, 0xf3, 0xa7, 0x64, 0x79,
+0x79, 0x13, 0x59, 0x8a, 0xa1, 0xc9, 0xa1, 0xa1,
+0xa1, 0xc9, 0x44, 0x3c, 0xc6, 0x18, 0x96, 0x94,
+0xf7, 0x1d, 0xdf, 0x30, 0x61, 0x2f, 0xae, 0x23,
+0xa7, 0x4a, 0x52, 0x24, 0xeb, 0x15, 0x6b, 0xd8,
+0x82, 0x06, 0xea, 0x86, 0x91, 0x28, 0x1e, 0x93,
+0xfa, 0xb6, 0xe4, 0x43, 0xce, 0xba, 0x30, 0xdb,
+0xc4, 0x91, 0x0f, 0x59, 0x1d, 0x0b, 0x9b, 0x06,
+0x94, 0xf5, 0x35, 0xec, 0xb5, 0x96, 0x78, 0xd5,
+0x33, 0x17, 0x63, 0x5d, 0x48, 0x83, 0x58, 0x62,
+0x0b, 0x3e, 0x9c, 0x43, 0x12, 0xdb, 0x3b, 0x87,
+0x09, 0xa3, 0x22, 0xf8, 0x70, 0x0e, 0x94, 0xf5,
+0xc5, 0xae, 0xca, 0x24, 0x83, 0x39, 0xb7, 0xec,
+0x49, 0x53, 0xc2, 0xfc, 0x63, 0xbb, 0xf0, 0x6d,
+0x62, 0xf3, 0x3f, 0x04, 0x16, 0xa2, 0x4e, 0xac,
+0x9d, 0x37, 0xd7, 0x17, 0xf6, 0xe7, 0xd3, 0xd0,
+0x0e, 0x89, 0x8c, 0x59, 0xe1, 0x01, 0xdc, 0x88,
+0x63, 0x46, 0xae, 0xc0, 0x4c, 0x1f, 0xe6, 0x9f,
+0x18, 0xa9, 0xac, 0x61, 0x8e, 0x46, 0x53, 0x52,
+0xd7, 0x57, 0xc0, 0x8e, 0xc0, 0x7e, 0x88, 0xcf,
+0xd6, 0xaa, 0xfc, 0x08, 0xd9, 0x4f, 0xb2, 0xbc,
+0xf2, 0x88, 0x9e, 0x6f, 0x11, 0x77, 0x90, 0x3f,
+0x9a, 0x3e, 0x92, 0xdc, 0x1f, 0xc7, 0x3b, 0xc8,
+0x9b, 0xe3, 0x53, 0xc4, 0xf2, 0xfb, 0x9b, 0xc1,
+0xfe, 0x53, 0xf1, 0x05, 0xf8, 0x05, 0xf8, 0x2c,
+0x65, 0xc5, 0x29, 0x7c, 0x88, 0xb9, 0x53, 0x9a,
+0x95, 0x46, 0x8b, 0x7a, 0xbf, 0x28, 0x0c, 0xb0,
+0x96, 0x62, 0x7c, 0xa2, 0xb2, 0xc0, 0xfb, 0x59,
+0x4b, 0x26, 0xee, 0xc0, 0x3d, 0xda, 0x5f, 0x48,
+0x15, 0x43, 0xc3, 0x52, 0x13, 0x71, 0xc7, 0x5a,
+0x25, 0x56, 0x33, 0x9e, 0x2c, 0x0d, 0x56, 0x5c,
+0x7f, 0xc4, 0x85, 0x1f, 0x95, 0x99, 0x30, 0xa6,
+0x7d, 0x2d, 0x6c, 0x49, 0xd9, 0xd7, 0x21, 0x58,
+0x29, 0x08, 0xc3, 0x2d, 0x65, 0x7c, 0xa0, 0x1b,
+0xb3, 0xb4, 0xfa, 0xf2, 0xe4, 0xee, 0x67, 0xbc,
+0xd7, 0x8a, 0xd6, 0x57, 0xa1, 0xc1, 0x87, 0x3c,
+0x77, 0x4e, 0x98, 0x4e, 0xeb, 0x63, 0xe4, 0x43,
+0x4b, 0x60, 0xe1, 0x22, 0x9c, 0xb3, 0xcd, 0x90,
+0x0f, 0x9b, 0xe3, 0x99, 0x67, 0xb9, 0xd7, 0xed,
+0xb4, 0x93, 0xcf, 0xf3, 0x13, 0xd3, 0x45, 0xdb,
+0x31, 0xf2, 0xc4, 0x62, 0x0c, 0xd3, 0x8e, 0x81,
+0xf9, 0x27, 0x07, 0xd8, 0x42, 0xf3, 0x40, 0xa2,
+0xf5, 0x8e, 0xf3, 0x21, 0xac, 0x8c, 0xbb, 0x64,
+0xe6, 0xb3, 0x66, 0x0d, 0x39, 0x37, 0x41, 0x14,
+0x31, 0xc4, 0xac, 0xd7, 0x0b, 0x25, 0x88, 0x78,
+0x5e, 0xf0, 0x21, 0x87, 0x2a, 0x43, 0x1a, 0xa4,
+0xb1, 0x32, 0x43, 0x50, 0xa4, 0x2a, 0x28, 0x86,
+0x26, 0xea, 0xcd, 0xf2, 0xaf, 0x91, 0x49, 0x46,
+0x1f, 0x9c, 0x7d, 0xc5, 0x6d, 0x49, 0xb4, 0xb1,
+0xf5, 0x07, 0x9d, 0x87, 0x53, 0x2d, 0xf1, 0x49,
+0x34, 0x03, 0x87, 0x8d, 0xd7, 0xea, 0x46, 0xc9,
+0x3f, 0x78, 0xbd, 0x3d, 0x17, 0x33, 0x4b, 0xc8,
+0x87, 0xef, 0xfe, 0xbe, 0x47, 0xec, 0xfe, 0x7b,
+0xbc, 0x74, 0x2d, 0x31, 0x23, 0x79, 0xa0, 0xbd,
+0x01, 0x06, 0x4a, 0xfe, 0x01, 0xf8, 0xda, 0x5b,
+0x23, 0x0f, 0xdf, 0xbd, 0xbd, 0xfc, 0x9d, 0x1b,
+0x2f, 0xbe, 0x35, 0x26, 0xf8, 0xf0, 0xfd, 0x3a,
+0x1f, 0x2e, 0x47, 0x7c, 0xb8, 0xeb, 0x19, 0xf7,
+0x50, 0xc4, 0x87, 0xc7, 0x05, 0x1f, 0xee, 0xd4,
+0xf9, 0xf0, 0x69, 0xc4, 0x87, 0xbb, 0x78, 0xec,
+0xf3, 0xea, 0xab, 0x02, 0x0b, 0xff, 0x5a, 0xd9,
+0xd9, 0x1e, 0xda, 0xaa, 0x83, 0x22, 0x12, 0xe3,
+0x73, 0xf8, 0x50, 0xfe, 0xf4, 0xbf, 0x6f, 0x62,
+0xff, 0x4f, 0x1b, 0xa0, 0x78, 0xf9, 0x79, 0x7c,
+0x38, 0xd8, 0xe0, 0xc3, 0xee, 0x03, 0xe3, 0x1b,
+0xf3, 0xfd, 0x9b, 0x4f, 0x1e, 0x0f, 0x5d, 0x7a,
+0xa6, 0xff, 0xe3, 0x2f, 0x1e, 0xbd, 0x0f, 0x1e,
+0x11, 0x2f, 0x28, 0x7c, 0xc8, 0xa6, 0xbe, 0xf8,
+0x59, 0xb4, 0xb4, 0xb4, 0xb4, 0xb4, 0xb4, 0xb4,
+0xb4, 0xb4, 0xb4, 0xb4, 0xfe, 0xdf, 0x25, 0x6b,
+0x07, 0xaa, 0x6b, 0x07, 0x2d, 0x2d, 0x2d, 0x2d,
+0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0xad, 0xe7,
+0x4b, 0xd6, 0x0e, 0x09, 0x5d, 0x3b, 0x68, 0x69,
+0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69,
+0x69, 0x3d, 0x5f, 0xb2, 0x76, 0x30, 0x65, 0xed,
+0xf0, 0xbf, 0x0e, 0x45, 0x4b, 0x4b, 0x4b, 0x4b,
+0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0xeb, 0xbf,
+0x28, 0x5f, 0xfc, 0xd1, 0x24, 0xf8, 0xe7, 0x79,
+0x1f, 0xb8, 0xf8, 0xce, 0x53, 0xdc, 0x07, 0xf6,
+0xb9, 0xdf, 0x27, 0xd4, 0x3f, 0x6b, 0xf8, 0x50,
+0x25, 0xd1, 0x39, 0x1f, 0x9f, 0x7e, 0xb6, 0xdf,
+0xbf, 0x00, 0x34, 0x34, 0xbf, 0x69, 0xee, 0x33,
+0x01, 0x00,
diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c
new file mode 100644
index 0000000..71d16e4
--- /dev/null
+++ b/board/esd/wuh405/wuh405.c
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ */
+ mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ unsigned char *dst;
+ ulong len = sizeof(fpgadata);
+ int status;
+ int index;
+ int i;
+
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ printf ("GUNZIP ERROR - must RESET board to recover\n");
+ do_reset (NULL, 0, 0, NULL);
+ }
+
+ status = fpga_boot(dst, len);
+ if (status != 0) {
+ printf("\nFPGA: Booting failed ");
+ switch (status) {
+ case ERROR_FPGA_PRG_INIT_LOW:
+ printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_INIT_HIGH:
+ printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ break;
+ case ERROR_FPGA_PRG_DONE:
+ printf("(Timeout: DONE not high after programming FPGA)\n ");
+ break;
+ }
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("FPGA: %s\n", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+ /* delayed reboot */
+ for (i=20; i>0; i--) {
+ printf("Rebooting in %2d seconds \r",i);
+ for (index=0;index<1000;index++)
+ udelay(1000);
+ }
+ putc ('\n');
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ puts("FPGA: ");
+
+ /* display infos on fpgaimage */
+ index = 15;
+ for (i=0; i<4; i++) {
+ len = dst[index];
+ printf("%s ", &(dst[index+1]));
+ index += len+3;
+ }
+ putc ('\n');
+
+ free(dst);
+
+ /*
+ * Reset FPGA via FPGA_DATA pin
+ */
+ SET_FPGA(FPGA_PRG | FPGA_CLK);
+ udelay(1000); /* wait 1ms */
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+ udelay(1000); /* wait 1ms */
+
+ /*
+ * Reset external DUARTs
+ */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
+ udelay(10); /* wait 10us */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
+ udelay(1000); /* wait 1ms */
+
+ /*
+ * Enable interrupts in exar duart mcr[3]
+ */
+ out_8((void *)(DUART0_BA + 4), 0x08);
+ out_8((void *)(DUART1_BA + 4), 0x08);
+ out_8((void *)(DUART2_BA + 4), 0x08);
+ out_8((void *)(DUART3_BA + 4), 0x08);
+
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming WUH405");
+ } else {
+ puts(str);
+ }
+
+ putc ('\n');
+
+ return 0;
+}
diff --git a/board/esg/ima3-mx53/Kconfig b/board/esg/ima3-mx53/Kconfig
new file mode 100644
index 0000000..d73238f
--- /dev/null
+++ b/board/esg/ima3-mx53/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMA3_MX53
+
+config SYS_BOARD
+ default "ima3-mx53"
+
+config SYS_VENDOR
+ default "esg"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "ima3-mx53"
+
+endif
diff --git a/board/esg/ima3-mx53/MAINTAINERS b/board/esg/ima3-mx53/MAINTAINERS
new file mode 100644
index 0000000..96de081
--- /dev/null
+++ b/board/esg/ima3-mx53/MAINTAINERS
@@ -0,0 +1,6 @@
+IMA3-MX53 BOARD
+#M: -
+S: Maintained
+F: board/esg/ima3-mx53/
+F: include/configs/ima3-mx53.h
+F: configs/ima3-mx53_defconfig
diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile
new file mode 100644
index 0000000..afb8925
--- /dev/null
+++ b/board/esg/ima3-mx53/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+#
+# Based on ti/evm/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ima3-mx53.o
diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c
new file mode 100644
index 0000000..df758ee
--- /dev/null
+++ b/board/esg/ima3-mx53/ima3-mx53.c
@@ -0,0 +1,206 @@
+/*
+ * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+
+/* NOR flash configuration */
+#define IMA3_MX53_CS0GCR1 (CSEN | DSZ(2))
+#define IMA3_MX53_CS0GCR2 0
+#define IMA3_MX53_CS0RCR1 (RCSN(2) | OEN(1) | RWSC(15))
+#define IMA3_MX53_CS0RCR2 0
+#define IMA3_MX53_CS0WCR1 (WBED1 | WCSN(2) | WEN(1) | WWSC(15))
+#define IMA3_MX53_CS0WCR2 0
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void weim_nor_settings(void)
+{
+ struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+ writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1);
+ writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2);
+ writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1);
+ writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2);
+ writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1);
+ writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2);
+ writel(0x0, &weim_regs->wcr);
+
+ set_chipselect_size(CS0_128);
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__UART4_RXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__UART4_TXD_MUX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+static void setup_iomux_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR };
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ int ret;
+
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
+
+ return ret;
+}
+
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+#define SD_CD_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | PAD_CTL_PKE)
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, SD_CD_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+ gpio_direction_input(IMX_GPIO_NR(1, 1));
+
+ esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+#endif
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
+
+static void setup_iomux_spi(void)
+{
+ static const iomux_v3_cfg_t spi_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL),
+ /* SSEL 0 */
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__GPIO5_29, SPI_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
+ gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
+}
+
+int board_early_init_f(void)
+{
+ /* configure I/O pads */
+ setup_iomux_uart();
+ setup_iomux_fec();
+
+ weim_nor_settings();
+
+ /* configure spi */
+ setup_iomux_spi();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ mxc_set_sata_internal_clock();
+
+ return 0;
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+#include <miiphy.h>
+
+void reset_phy(void)
+{
+ unsigned short reg;
+
+ /* reset the phy */
+ miiphy_reset("FEC", CONFIG_PHY_ADDR);
+
+ /* set hard link to 100Mbit, full-duplex */
+ miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, ®);
+ reg &= ~BMCR_ANENABLE;
+ reg |= (BMCR_SPEED100 | BMCR_FULLDPLX);
+ miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg);
+
+ miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, ®);
+ reg |= (1 << 5);
+ miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg);
+}
+#endif
+
+int checkboard(void)
+{
+ puts("Board: IMA3_MX53\n");
+
+ return 0;
+}
diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg
new file mode 100644
index 0000000..324a90e
--- /dev/null
+++ b/board/esg/ima3-mx53/imximage.cfg
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2012
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM nor
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/* IOMUX for RAM only */
+DATA 4 0x53fa8554 0x300020
+DATA 4 0x53fa8560 0x300020
+DATA 4 0x53fa8594 0x300020
+DATA 4 0x53fa8584 0x300020
+DATA 4 0x53fa8558 0x300040
+DATA 4 0x53fa8568 0x300040
+DATA 4 0x53fa8590 0x300040
+DATA 4 0x53fa857c 0x300040
+DATA 4 0x53fa8564 0x300040
+DATA 4 0x53fa8580 0x300040
+DATA 4 0x53fa8570 0x300220
+DATA 4 0x53fa8578 0x300220
+DATA 4 0x53fa872c 0x300000
+DATA 4 0x53fa8728 0x300000
+DATA 4 0x53fa871c 0x300000
+DATA 4 0x53fa8718 0x300000
+DATA 4 0x53fa8574 0x300020
+DATA 4 0x53fa8588 0x300020
+DATA 4 0x53fa855c 0x0
+DATA 4 0x53fa858c 0x0
+DATA 4 0x53fa856c 0x300040
+DATA 4 0x53fa86f0 0x300000
+DATA 4 0x53fa8720 0x300000
+DATA 4 0x53fa86fc 0x0
+DATA 4 0x53fa86f4 0x0
+DATA 4 0x53fa8714 0x0
+DATA 4 0x53fa8724 0x4000000
+
+/* DDR RAM */
+DATA 4 0x63fd9088 0x40404040
+DATA 4 0x63fd9090 0x40404040
+DATA 4 0x63fd907C 0x01420143
+DATA 4 0x63fd9080 0x01450146
+DATA 4 0x63fd9018 0x00111740
+DATA 4 0x63fd9000 0x84190000
+
+/* esdcfgX */
+DATA 4 0x63fd900C 0x9f5152e3
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+
+/* Read/Write command delay */
+DATA 4 0x63fd902c 0x000026d2
+
+/* Out of reset delays */
+DATA 4 0x63fd9030 0x00ff0e21
+
+/* ESDCTL ODT timing control */
+DATA 4 0x63fd9008 0x12273030
+
+/* ESDCTL power down control */
+DATA 4 0x63fd9004 0x0002002d
+
+/* Set registers in DDR memory chips */
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+
+/* ESDCTL refresh control */
+DATA 4 0x63fd9020 0x00005800
+
+/* PHY ZQ HW control */
+DATA 4 0x63fd9040 0x05380003
+
+/* PHY ODT control */
+DATA 4 0x63fd9058 0x00022222
+
+/* start DDR3 */
+DATA 4 0x63fd901c 0x00000000
diff --git a/board/espt/Kconfig b/board/espt/Kconfig
new file mode 100644
index 0000000..0294926
--- /dev/null
+++ b/board/espt/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_ESPT
+
+config SYS_BOARD
+ default "espt"
+
+config SYS_CONFIG_NAME
+ default "espt"
+
+endif
diff --git a/board/espt/MAINTAINERS b/board/espt/MAINTAINERS
new file mode 100644
index 0000000..fdbbc3e
--- /dev/null
+++ b/board/espt/MAINTAINERS
@@ -0,0 +1,6 @@
+ESPT BOARD
+#M: -
+S: Maintained
+F: board/espt/
+F: include/configs/espt.h
+F: configs/espt_defconfig
diff --git a/board/espt/Makefile b/board/espt/Makefile
new file mode 100644
index 0000000..8a8a2c9
--- /dev/null
+++ b/board/espt/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2009 Renesas Solutions Corp.
+# Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+#
+# board/espt/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := espt.o
+obj-y += lowlevel_init.o
diff --git a/board/espt/espt.c b/board/espt/espt.c
new file mode 100644
index 0000000..ee6e538
--- /dev/null
+++ b/board/espt/espt.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * board/espt/espt.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("BOARD: ESPT-GIGA\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
diff --git a/board/espt/lowlevel_init.S b/board/espt/lowlevel_init.S
new file mode 100644
index 0000000..c1d0966
--- /dev/null
+++ b/board/espt/lowlevel_init.S
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2009 Renesas Solutions Corp.
+ * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * board/espt/lowlevel_init.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ write32 WDTCSR_A, WDTCSR_D
+
+ write32 WDTST_A, WDTST_D
+
+ write32 WDTBST_A, WDTBST_D
+
+ write32 CCR_A, CCR_CACHE_ICI_D
+
+ write32 MMUCR_A, MMU_CONTROL_TI_D
+
+ write32 MSTPCR0_A, MSTPCR0_D
+
+ write32 MSTPCR1_A, MSTPCR1_D
+
+ write32 RAMCR_A, RAMCR_D
+
+ /*
+ * Setting infomation from
+ * original ESPT-GIGA bootloader register
+ */
+ write32 MMSEL_A, MMSEL_D
+
+ /* dummy */
+ mov.l @r1, r2
+ mov.l @r1, r2
+ synco
+
+ write32 BCR_A, BCR_D
+
+ write32 CS0BCR_A, CS0BCR_D
+
+ write32 CS0WCR_A, CS0WCR_D
+
+ /*
+ * DDR-SDRAM setting
+ */
+
+ /* set DDR-SDRAM dummy read */
+ write32 MMSEL_A, MMSEL_D
+
+ write32 MMSEL_A, CS0_A
+
+ /* set DDR-SDRAM bus/endian etc */
+ write32 MIM_U_A, MIM_U_D
+
+ write32 MIM_L_A, MIM_L_D0
+
+ write32 SDR_L_A, SDR_L_A_D0
+
+ write32 STR_L_A, STR_L_A_D0
+
+ /* DDR-SDRAM access control */
+ write32 MIM_L_A, MIM_L_D1
+
+ write32 SCR_L_A, SCR_L_A_D0
+
+ write32 SCR_L_A, SCR_L_A_D1
+
+ write32 EMRS_A, EMRS_D
+
+ write32 MRS1_A, MRS1_D
+
+ write32 MIM_U_A, MIM_U_D
+
+ write32 MIM_L_A, MIM_L_A_D2
+
+ write32 SCR_L_A, SCR_L_A_D2
+
+ write32 SCR_L_A, SCR_L_A_D2
+
+ write32 MRS2_A, MRS2_D
+
+ /* wait 200us */
+ wait_timer REPEAT_R3
+
+ /* GPIO setting */
+ write16 PSEL0_A, PSEL0_D
+
+ write16 PSEL1_A, PSEL1_D
+
+ write16 PSEL2_A, PSEL2_D
+
+ write16 PSEL3_A, PSEL3_D
+
+ write16 PSEL4_A, PSEL4_D
+
+ write8 PADR_A, PADR_D
+
+ write16 PACR_A, PACR_D
+
+ write8 PBDR_A, PBDR_D
+
+ write16 PBCR_A, PBCR_D
+
+ write8 PCDR_A, PCDR_D
+
+ write16 PCCR_A, PCCR_D
+
+ write8 PDDR_A, PDDR_D
+
+ write16 PDCR_A, PDCR_D
+
+ write16 PECR_A, PECR_D
+
+ write16 PFCR_A, PFCR_D
+
+ write16 PGCR_A, PGCR_D
+
+ write16 PHCR_A, PHCR_D
+
+ write16 PICR_A, PICR_D
+
+ write8 PJDR_A, PJDR_D
+
+ write16 PJCR_A, PJCR_D
+
+ /* wait 50us */
+ wait_timer REPEAT_R3
+
+ write8 PKDR_A, PKDR_D
+
+ write16 PKCR_A, PKCR_D
+
+ write16 PLCR_A, PLCR_D
+
+ write16 PMCR_A, PMCR_D
+
+ write16 PNCR_A, PNCR_D
+
+ write16 POCR_A, POCR_D
+
+
+ /* ICR0 ,ICR1 */
+ write32 ICR0_A, ICR0_D
+
+ write32 ICR1_A, ICR1_D
+
+ /* USB Host */
+ write32 USB_USBHSC_A, USB_USBHSC_D
+
+ write32 CCR_A, CCR_CACHE_D_2
+
+ rts
+ nop
+
+ .align 2
+
+/* GPIO Crontrol Register */
+PACR_A: .long 0xFFEF0000
+PBCR_A: .long 0xFFEF0002
+PCCR_A: .long 0xFFEF0004
+PDCR_A: .long 0xFFEF0006
+PECR_A: .long 0xFFEF0008
+PFCR_A: .long 0xFFEF000A
+PGCR_A: .long 0xFFEF000C
+PHCR_A: .long 0xFFEF000E
+PICR_A: .long 0xFFEF0010
+PJCR_A: .long 0xFFEF0012
+PKCR_A: .long 0xFFEF0014
+PLCR_A: .long 0xFFEF0016
+PMCR_A: .long 0xFFEF0018
+PNCR_A: .long 0xFFEF001A
+POCR_A: .long 0xFFEF001C
+
+/* GPIO Data Register */
+PADR_A: .long 0xFFEF0020
+PBDR_A: .long 0xFFEF0022
+PCDR_A: .long 0xFFEF0024
+PDDR_A: .long 0xFFEF0026
+PJDR_A: .long 0xFFEF0032
+PKDR_A: .long 0xFFEF0034
+
+/* GPIO Set data */
+PADR_D: .long 0x00000000
+PACR_D: .word 0x1400
+.align 2
+PBDR_D: .long 0x00000000
+PBCR_D: .word 0x555A
+.align 2
+PCDR_D: .long 0x00000000
+PCCR_D: .word 0x5555
+.align 2
+PDDR_D: .long 0x00000000
+PDCR_D: .word 0x0155
+PECR_D: .word 0x0000
+PFCR_D: .word 0x0000
+PGCR_D: .word 0x0000
+PHCR_D: .word 0x0000
+PICR_D: .word 0x0800
+PJDR_D: .long 0x00000006
+PJCR_D: .word 0x5A57
+.align 2
+PKDR_D: .long 0x00000000
+PKCR_D: .word 0xFFF9
+.align 2
+PLCR_D: .word 0xC330
+PMCR_D: .word 0xFFFF
+PNCR_D: .word 0x0242
+POCR_D: .word 0x0000
+
+/* Pin Select */
+PSEL0_A: .long 0xFFEF0070
+PSEL1_A: .long 0xFFEF0072
+PSEL2_A: .long 0xFFEF0074
+PSEL3_A: .long 0xFFEF0076
+PSEL4_A: .long 0xFFEF0078
+PSEL0_D: .word 0x0001
+PSEL1_D: .word 0x2400
+PSEL2_D: .word 0x0000
+PSEL3_D: .word 0x2421
+PSEL4_D: .word 0x0000
+.align 2
+
+MMSEL_A: .long 0xFE600020
+BCR_A: .long 0xFF801000
+CS0BCR_A: .long 0xFF802000
+CS0WCR_A: .long 0xFF802008
+ICR0_A: .long 0xFFD00000
+ICR1_A: .long 0xFFD0001C
+
+MMSEL_D: .long 0xA5A50000
+BCR_D: .long 0x05000000
+CS0BCR_D: .long 0x232306F0
+CS0WCR_D: .long 0x00011104
+ICR0_D: .long 0x80C00000
+ICR1_D: .long 0x00020000
+
+/* RWBT Address */
+WDTST_A: .long 0xFFCC0000
+WDTCSR_A: .long 0xFFCC0004
+WDTBST_A: .long 0xFFCC0008
+/* RWBT Data */
+WDTST_D: .long 0x5A000FFF
+WDTCSR_D: .long 0xA5000000
+WDTBST_D: .long 0x55000000
+
+/* Cache Address */
+CCR_A: .long 0xFF00001C
+MMUCR_A: .long 0xFF000010
+RAMCR_A: .long 0xFF000074
+
+/* Cache Data */
+CCR_CACHE_ICI_D:.long 0x00000800
+CCR_CACHE_D_2: .long 0x00000103
+MMU_CONTROL_TI_D:.long 0x00000004
+RAMCR_D: .long 0x00000200
+
+/* Low power mode control Address */
+MSTPCR0_A: .long 0xFFC80030
+MSTPCR1_A: .long 0xFFC80038
+/* Low power mode control Data */
+MSTPCR0_D: .long 0x00000000
+MSTPCR1_D: .long 0x00000000
+
+REPEAT0_R3: .long 0x00002000
+REPEAT_R3: .long 0x00000200
+CS0_A: .long 0xA8000000
+
+MIM_U_A: .long 0xFE800008
+MIM_L_A: .long 0xFE80000C
+SCR_U_A: .long 0xFE800010
+SCR_L_A: .long 0xFE800014
+STR_U_A: .long 0xFE800018
+STR_L_A: .long 0xFE80001C
+SDR_U_A: .long 0xFE800030
+SDR_L_A: .long 0xFE800034
+EMRS_A: .long 0xFE902000
+MRS1_A: .long 0xFE900B08
+MRS2_A: .long 0xFE900308
+
+MIM_U_D: .long 0x00000000
+MIM_L_D0: .long 0x04100008
+MIM_L_D1: .long 0x02EE0009
+MIM_L_D2: .long 0x02EE0209
+
+SDR_L_A_D0: .long 0x00000300
+STR_L_A_D0: .long 0x00010040
+MIM_L_A_D1: .long 0x04100009
+SCR_L_A_D0: .long 0x00000003
+SCR_L_A_D1: .long 0x00000002
+MIM_L_A_D2: .long 0x04100209
+SCR_L_A_D2: .long 0x00000004
+
+SCR_L_NORMAL: .long 0x00000000
+SCR_L_NOP: .long 0x00000001
+SCR_L_PALL: .long 0x00000002
+SCR_L_CKE_EN: .long 0x00000003
+SCR_L_CBR: .long 0x00000004
+
+STR_L_D: .long 0x000F3980
+SDR_L_D: .long 0x00000400
+EMRS_D: .long 0x00000000
+MRS1_D: .long 0x00000000
+MRS2_D: .long 0x00000000
+
+/* USB */
+USB_USBHSC_A: .long 0xFFEC80F0
+USB_USBHSC_D: .long 0x00000000
diff --git a/board/eukrea/cpu9260/Kconfig b/board/eukrea/cpu9260/Kconfig
new file mode 100644
index 0000000..9bd077b
--- /dev/null
+++ b/board/eukrea/cpu9260/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CPU9260
+
+config SYS_BOARD
+ default "cpu9260"
+
+config SYS_VENDOR
+ default "eukrea"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "cpu9260"
+
+endif
diff --git a/board/eukrea/cpu9260/MAINTAINERS b/board/eukrea/cpu9260/MAINTAINERS
new file mode 100644
index 0000000..fb5aee8
--- /dev/null
+++ b/board/eukrea/cpu9260/MAINTAINERS
@@ -0,0 +1,13 @@
+CPU9260 BOARD
+M: Eric Benard <eric@eukrea.com>
+S: Maintained
+F: board/eukrea/cpu9260/
+F: include/configs/cpu9260.h
+F: configs/cpu9260_defconfig
+F: configs/cpu9260_128M_defconfig
+F: configs/cpu9260_nand_defconfig
+F: configs/cpu9260_nand_128M_defconfig
+F: configs/cpu9G20_defconfig
+F: configs/cpu9G20_128M_defconfig
+F: configs/cpu9G20_nand_defconfig
+F: configs/cpu9G20_nand_128M_defconfig
diff --git a/board/eukrea/cpu9260/Makefile b/board/eukrea/cpu9260/Makefile
new file mode 100644
index 0000000..e34792a
--- /dev/null
+++ b/board/eukrea/cpu9260/Makefile
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net
+# Lead Tech Design <www.leadtechdesign.com>
+# Ilko Iliev <www.ronetix.at>
+#
+# (C) Copyright 2009
+# Eric Benard <eric@eukrea.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu9260.o
+obj-y += led.o
diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c
new file mode 100644
index 0000000..01ecccb
--- /dev/null
+++ b/board/eukrea/cpu9260/cpu9260.c
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * (C) Copyright 2009-2011
+ * Eric Benard <eric@eukrea.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hardware.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void cpu9260_nand_hw_init(void)
+{
+ unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC;
+ at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+#if defined(CONFIG_CPU9G20)
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+#elif defined(CONFIG_CPU9260)
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+#endif
+
+ writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+
+ /* Configure RDY/BSY */
+ gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+ /* Enable NandFlash */
+ gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void cpu9260_macb_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+
+ at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
+
+ at91_phy_reset();
+
+ at91_macb_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ writel((1 << ATMEL_ID_PIOA) |
+ (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOC),
+ &pmc->pcer);
+
+ at91_seriald_hw_init();
+
+ return 0;
+}
+
+
+int board_init(void)
+{
+ /* arch number of the board */
+#if defined(CONFIG_CPU9G20)
+ gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20;
+#elif defined(CONFIG_CPU9260)
+ gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
+#endif
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ cpu9260_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+ cpu9260_macb_hw_init();
+#endif
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0);
+#endif
+ return rc;
+}
diff --git a/board/eukrea/cpu9260/led.c b/board/eukrea/cpu9260/led.c
new file mode 100644
index 0000000..0cfe0a6
--- /dev/null
+++ b/board/eukrea/cpu9260/led.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ * (C) Copyright 2009
+ * Eric Benard <eric@eukrea.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+static unsigned int saved_state[4] = {STATUS_LED_OFF, STATUS_LED_OFF,
+ STATUS_LED_OFF, STATUS_LED_OFF};
+
+void coloured_LED_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+
+ at91_set_pio_output(CONFIG_RED_LED, 1);
+ at91_set_pio_output(CONFIG_GREEN_LED, 1);
+ at91_set_pio_output(CONFIG_YELLOW_LED, 1);
+ at91_set_pio_output(CONFIG_BLUE_LED, 1);
+
+ at91_set_pio_value(CONFIG_RED_LED, 1);
+ at91_set_pio_value(CONFIG_GREEN_LED, 1);
+ at91_set_pio_value(CONFIG_YELLOW_LED, 1);
+ at91_set_pio_value(CONFIG_BLUE_LED, 1);
+}
+
+void red_led_off(void)
+{
+ at91_set_pio_value(CONFIG_RED_LED, 1);
+ saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
+}
+
+void green_led_off(void)
+{
+ at91_set_pio_value(CONFIG_GREEN_LED, 1);
+ saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
+}
+
+void yellow_led_off(void)
+{
+ at91_set_pio_value(CONFIG_YELLOW_LED, 1);
+ saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
+}
+
+void blue_led_off(void)
+{
+ at91_set_pio_value(CONFIG_BLUE_LED, 1);
+ saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
+}
+
+void red_led_on(void)
+{
+ at91_set_pio_value(CONFIG_RED_LED, 0);
+ saved_state[STATUS_LED_RED] = STATUS_LED_ON;
+}
+
+void green_led_on(void)
+{
+ at91_set_pio_value(CONFIG_GREEN_LED, 0);
+ saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
+}
+
+void yellow_led_on(void)
+{
+ at91_set_pio_value(CONFIG_YELLOW_LED, 0);
+ saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
+}
+
+void blue_led_on(void)
+{
+ at91_set_pio_value(CONFIG_BLUE_LED, 0);
+ saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
+}
+
+void __led_init(led_id_t mask, int state)
+{
+ __led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+ if (STATUS_LED_BLUE == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
+ blue_led_off();
+ else
+ blue_led_on();
+ } else if (STATUS_LED_RED == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
+ red_led_off();
+ else
+ red_led_on();
+ } else if (STATUS_LED_GREEN == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
+ green_led_off();
+ else
+ green_led_on();
+ } else if (STATUS_LED_YELLOW == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW])
+ yellow_led_off();
+ else
+ yellow_led_on();
+ }
+}
+
+void __led_set(led_id_t mask, int state)
+{
+ if (STATUS_LED_BLUE == mask) {
+ if (STATUS_LED_ON == state)
+ blue_led_on();
+ else
+ blue_led_off();
+ } else if (STATUS_LED_RED == mask) {
+ if (STATUS_LED_ON == state)
+ red_led_on();
+ else
+ red_led_off();
+ } else if (STATUS_LED_GREEN == mask) {
+ if (STATUS_LED_ON == state)
+ green_led_on();
+ else
+ green_led_off();
+ } else if (STATUS_LED_YELLOW == mask) {
+ if (STATUS_LED_ON == state)
+ yellow_led_on();
+ else
+ yellow_led_off();
+ }
+}
diff --git a/board/eukrea/cpuat91/Kconfig b/board/eukrea/cpuat91/Kconfig
new file mode 100644
index 0000000..b69e4c3
--- /dev/null
+++ b/board/eukrea/cpuat91/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CPUAT91
+
+config SYS_BOARD
+ default "cpuat91"
+
+config SYS_VENDOR
+ default "eukrea"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "cpuat91"
+
+endif
diff --git a/board/eukrea/cpuat91/MAINTAINERS b/board/eukrea/cpuat91/MAINTAINERS
new file mode 100644
index 0000000..1f6bc79
--- /dev/null
+++ b/board/eukrea/cpuat91/MAINTAINERS
@@ -0,0 +1,7 @@
+CPUAT91 BOARD
+M: Eric Benard <eric@eukrea.com>
+S: Maintained
+F: board/eukrea/cpuat91/
+F: include/configs/cpuat91.h
+F: configs/cpuat91_defconfig
+F: configs/cpuat91_ram_defconfig
diff --git a/board/eukrea/cpuat91/Makefile b/board/eukrea/cpuat91/Makefile
new file mode 100644
index 0000000..59b80c2
--- /dev/null
+++ b/board/eukrea/cpuat91/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de. <http://lists.denx.de/mailman/listinfo/u-boot>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cpuat91.o
diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c
new file mode 100644
index 0000000..ec0ce0b
--- /dev/null
+++ b/board/eukrea/cpuat91/cpuat91.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2006-2010 Eukrea Electromatique <www.eukrea.com>
+ * Eric Benard <eric@eukrea.com>
+ * based on at91rm9200dk.c which is :
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* arch number of CPUAT91-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_CPUAT91;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ at91_seriald_hw_init();
+ return 0;
+}
+
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_AT91EMAC
+int board_eth_init(bd_t *bis)
+{
+ return at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_SOFT
+void i2c_init_board(void)
+{
+ u32 pin;
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+ at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
+
+ writel(1 << AT91_ID_PIOA, &pmc->pcer);
+ pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
+ writel(pin, &pio->pioa.idr);
+ writel(pin, &pio->pioa.pudr);
+ writel(pin, &pio->pioa.per);
+ writel(pin, &pio->pioa.oer);
+ writel(pin, &pio->pioa.sodr);
+}
+#endif
diff --git a/board/evb64260/64260.h b/board/evb64260/64260.h
new file mode 100644
index 0000000..d106ced
--- /dev/null
+++ b/board/evb64260/64260.h
@@ -0,0 +1,31 @@
+#ifndef __64260_H__
+#define __64260_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN (1 << 8)
+#define CPU_CONF_AACK_DELAY (1 << 11)
+#define CPU_CONF_ENDIANESS (1 << 12)
+#define CPU_CONF_PIPELINE (1 << 13)
+#define CPU_CONF_TA_DELAY (1 << 15)
+#define CPU_CONF_RD_OOO (1 << 16)
+#define CPU_CONF_STOP_RETRY (1 << 17)
+#define CPU_CONF_MULTI_DECODE (1 << 18)
+#define CPU_CONF_DP_VALID (1 << 19)
+#define CPU_CONF_PERR_PROP (1 << 22)
+#define CPU_CONF_FAST_CLK (1 << 23)
+#define CPU_CONF_AACK_DELAY_2 (1 << 25)
+#define CPU_CONF_AP_VALID (1 << 26)
+#define CPU_CONF_REMAP_WR_DIS (1 << 27)
+#define CPU_CONF_CONF_SB_DIS (1 << 28)
+#define CPU_CONF_IO_SB_DIS (1 << 29)
+#define CPU_CONF_CLK_SYNC (1 << 30)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN (1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
+
+#endif /* __64260_H__ */
diff --git a/board/evb64260/Kconfig b/board/evb64260/Kconfig
new file mode 100644
index 0000000..933e6d6
--- /dev/null
+++ b/board/evb64260/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_P3G4
+
+config SYS_BOARD
+ default "evb64260"
+
+config SYS_CONFIG_NAME
+ default "P3G4"
+
+endif
+
+if TARGET_ZUMA
+
+config SYS_BOARD
+ default "evb64260"
+
+config SYS_CONFIG_NAME
+ default "ZUMA"
+
+endif
diff --git a/board/evb64260/MAINTAINERS b/board/evb64260/MAINTAINERS
new file mode 100644
index 0000000..d50dda5
--- /dev/null
+++ b/board/evb64260/MAINTAINERS
@@ -0,0 +1,12 @@
+EVB64260 BOARD
+M: Wolfgang Denk <wd@denx.de>
+S: Maintained
+F: board/evb64260/
+F: include/configs/P3G4.h
+F: configs/P3G4_defconfig
+
+ZUMA BOARD
+#M: Nye Liu <nyet@zumanetworks.com>
+S: Orphan (since 2014-04)
+F: include/configs/ZUMA.h
+F: configs/ZUMA_defconfig
diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile
new file mode 100644
index 0000000..ae2ebed
--- /dev/null
+++ b/board/evb64260/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = misc.o
+obj-y += evb64260.o flash.o serial.o memory.o pci.o \
+ eth.o eth_addrtbl.o mpsc.o i2c.o \
+ sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o
diff --git a/board/evb64260/README b/board/evb64260/README
new file mode 100644
index 0000000..74211de
--- /dev/null
+++ b/board/evb64260/README
@@ -0,0 +1,54 @@
+This file contains status information for the port of U-Boot to the
+Galileo Evaluation Board.
+
+Author: Josh Huber <huber@mclx.com>
+ Mission Critical Linux, Inc.
+
+The support for the Galileo Evaluation board is fairly minimal now.
+It's sufficient to boot Linux, but doesn't provide too much more than
+what's required to do this.
+
+Both DUART channels are supported (to use the second one, you have to
+modify the board -- see the schematics for where to solder on the
+devices module). The ethernet ports are supported, and the MPSC is
+supported as a console driver. (keep in mind that the kernel has no
+support for this yet)
+
+There are still occaisonal lockups with the MPSC console driver due to
+(we think!) overrun problems. If you're looking for something stable
+to use for Linux development, consider sticking with the DUART console
+for now.
+
+Automatic memory sizing mostly works. We've had problems with some
+combinations of memory. Please send us email if you're having trouble
+with respect to the memory detection.
+
+Right now, only the 512k boot flash is supported. Support for the
+16MB flash on the devices module is forthcoming. Right now the flash
+is stored at the 256k boundry in flash, wasting a whole sector (64k!)
+for environment data. This isn't really a big deal since we're not
+using the 512k for anything else. (Just U-Boot and the environment)
+
+Finally, here is a sample output session:
+
+U-Boot 1.0.0-pre1 (Jun 6 2001 - 12:45:11)
+
+Initializing...
+ CPU: MPC7400 (altivec enabled) v2.9
+ Board: EVB64260
+ DRAM: 256 MB
+ FLASH: 512 kB
+ In: serial
+ Out: serial
+ Err: serial
+
+=>
+
+The default configuration should be correct for the evaluation board,
+as it's shipped from Galileo. Keep in mind that the default baudrate
+is set to 38400, 8N1.
+
+Good luck, and make sure to send any bugreports to us (or the
+u-boot-users list).
+
+Josh
diff --git a/board/evb64260/README.EVB-64260-750CX b/board/evb64260/README.EVB-64260-750CX
new file mode 100644
index 0000000..5ea38ea
--- /dev/null
+++ b/board/evb64260/README.EVB-64260-750CX
@@ -0,0 +1,7 @@
+The EVB-64260-750CX is quite similar to the EVB-64260-BP already
+supported except the following differences:
+* It has an IBM-750CXe soldiered on board instead of the slot-1 in the
+ BP.
+* It has a single PCI male connector instead of the 4 PCI female
+ connectors on the BP. It also gets power trough the PCI connector.
+* It has only a single DIMM slot instead of the 2 slots in the BP.
diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt
new file mode 100644
index 0000000..6cae9ea
--- /dev/null
+++ b/board/evb64260/bootseq.txt
@@ -0,0 +1,94 @@
+(cpu/mpc7xxx/start.S)
+
+start:
+ b boot_cold
+
+start_warm:
+ b boot_warm
+
+
+boot_cold:
+boot_warm:
+ clear bats
+ init l2 (if enabled)
+ init altivec (if enabled)
+ invalidate l2 (if enabled)
+ setup bats (from defines in config_EVB)
+ enable_addr_trans: (if MMU enabled)
+ enable MSR_IR and MSR_DR
+ jump to in_flash
+
+in_flash:
+ enable l1 dcache
+ gal_low_init: (board/evb64260/sdram_init.S)
+ config SDRAM (CFG, TIMING, DECODE)
+ init scratch regs (810 + 814)
+
+ detect DIMM0 (bank 0 only)
+ config SDRAM_PARA0 to 256/512Mbit
+ bl sdram_op_mode
+ detect bank0 width
+ write scratch reg 810
+ config SDRAM_PARA0 with results
+ config SDRAM_PARA1 with results
+
+ detect DIMM1 (bank 2 only)
+ config SDRAM_PARA2 to 256/512Mbit
+ detect bank2 width
+ write scratch reg 814
+ config SDRAM_PARA2 with results
+ config SDRAM_PARA3 with results
+
+ setup device bus timings/width
+ setup boot device timings/width
+
+ setup CPU_CONF (0x0)
+ setup cpu master control register 0x160
+ setup PCI0 TIMEOUT
+ setup PCI1 TIMEOUT
+ setup PCI0 BAR
+ setup PCI1 BAR
+
+ setup MPP control 0-3
+ setup GPP level control
+ setup Serial ports multiplex
+
+ setup stack pointer (r1)
+ setup GOT
+ call cpu_init_f
+ debug leds
+ board_init_f: (common/board.c)
+ board_early_init_f:
+ remap gt regs?
+ map PCI mem/io
+ map device space
+ clear out interrupts
+ init_timebase
+ env_init
+ serial_init
+ console_init_f
+ display_options
+ initdram: (board/evb64260/evb64260.c)
+ detect memory
+ for each bank:
+ dram_size()
+ setup PCI slave memory mappings
+ setup SCS
+ setup monitor
+ alloc board info struct
+ init bd struct
+ relocate_code: (cpu/mpc7xxx/start.S)
+ copy,got,clearbss
+ board_init_r(bd, dest_addr) (common/board.c)
+ setup bd function pointers
+ trap_init
+ flash_init: (board/evb64260/flash.c)
+ setup bd flash info
+ cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
+ nothing
+ mem_malloc_init
+ malloc_bin_reloc
+ spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
+ env_relocated
+ misc_init_r(bd): (board/evb64260/evb64260.c)
+ mpsc_init2
diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c
new file mode 100644
index 0000000..d7f63bd
--- /dev/null
+++ b/board/evb64260/eth.c
@@ -0,0 +1,805 @@
+/**************************************************************************
+Etherboot - BOOTP/TFTP Bootstrap Program
+Skeleton NIC driver for Etherboot
+***************************************************************************/
+
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This file is a modified version from the Galileo polled mode
+ * network driver for the ethernet contained within the GT64260
+ * chip. It has been modified to fit into the U-Boot framework, from
+ * the original (etherboot) setup. Also, additional cleanup and features
+ * were added.
+ *
+ * - Josh Huber <huber@mclx.com>
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <galileo/gt64260R.h>
+#include <galileo/core.h>
+#include <asm/cache.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+
+#include "eth.h"
+#include "eth_addrtbl.h"
+
+#if defined(CONFIG_CMD_NET)
+
+#define GT6426x_ETH_BUF_SIZE 1536
+
+/* if you like verbose output, turn this on! */
+#undef DEBUG
+
+/* Restart autoneg if we detect link is up on phy init. */
+
+/*
+ * The GT doc's say that after Rst is deasserted, and the PHY
+ * reports autoneg complete, it runs through its autoneg
+ * procedures. This doesn't seem to be the case for MII
+ * PHY's. To work around this check for link up && autoneg
+ * complete when initilizing the port. If they are both set,
+ * then restart PHY autoneg. Of course, it may be something
+ * completly different.
+ */
+#ifdef CONFIG_ETHER_PORT_MII
+# define RESTART_AUTONEG
+#endif
+
+/* do this if you dont want to use snooping */
+#define USE_SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef USE_SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+/* bummer - w/o flush, nothing works, even with snooping - FIXME */
+/* #define FLUSH_DCACHE(a,b) */
+#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+struct eth_dev_s {
+ eth0_tx_desc_single *eth_tx_desc;
+ eth0_rx_desc_single *eth_rx_desc;
+ char *eth_tx_buffer;
+ char *eth_rx_buffer[NR];
+ int tdn, rdn;
+ int dev;
+ unsigned int reg_base;
+};
+
+
+#ifdef CONFIG_INTEL_LXT97X
+/* for intel LXT972 */
+static const char ether_port_phy_addr[3]={0,1,2};
+#else
+static const char ether_port_phy_addr[3]={4,5,6};
+#endif
+
+/* MII PHY access routines are common for all i/f, use gal_ent0 */
+#define GT6426x_MII_DEVNAME "gal_enet0"
+
+int gt6426x_miiphy_read(const char *devname, unsigned char phy,
+ unsigned char reg, unsigned short *val);
+
+static inline unsigned short
+miiphy_read_ret(unsigned short phy, unsigned short reg)
+{
+ unsigned short val;
+ gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val);
+ return val;
+}
+
+
+/**************************************************************************
+RESET - Reset adapter
+***************************************************************************/
+void
+gt6426x_eth_reset(void *v)
+{
+ /* we should do something here...
+ struct eth_device *wp = (struct eth_device *)v;
+ struct eth_dev_s *p = wp->priv;
+ */
+
+ printf ("RESET\n");
+ /* put the card in its initial state */
+}
+
+static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
+{
+#ifdef DEBUG
+ printf("SMI interrupt: ");
+
+ if(icr&0x20000000) {
+ printf("SMI done\n");
+ }
+#endif
+
+ if(icr&0x10000000) {
+#ifdef DEBUG
+ unsigned int psr;
+
+ psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
+ printf("PHY state change:\n"
+ " GT:%s:%s:%s:%s\n",
+ psr & 1 ? "100" : " 10",
+ psr & 8 ? " Link" : "nLink",
+ psr & 2 ? "FD" : "HD",
+ psr & 4 ? " FC" : "nFC");
+
+#ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
+ {
+ unsigned short mii_11;
+ mii_11 = miiphy_read_ret(ether_port_phy_addr[p->dev], 0x11);
+
+ printf(" mii:%s:%s:%s:%s %s:%s %s\n",
+ mii_11 & (1 << 14) ? "100" : " 10",
+ mii_11 & (1 << 10) ? " Link" : "nLink",
+ mii_11 & (1 << 9) ? "FD" : "HD",
+ mii_11 & (1 << 4) ? " FC" : "nFC",
+
+ mii_11 & (1 << 7) ? "ANc" : "ANnc",
+ mii_11 & (1 << 8) ? "AN" : "Manual",
+ ""
+ );
+ }
+#endif /* CONFIG_INTEL_LXT97X */
+#endif /* DEBUG */
+ }
+}
+
+static int
+gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
+{
+ int eth_len=0;
+ char *eth_data;
+
+ eth0_rx_desc_single *rx = &p->eth_rx_desc[(p->rdn)];
+
+ INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
+
+ if (rx->command_status & 0x80000000) {
+ return 0; /* No packet received */
+ }
+
+ eth_len = (unsigned int)
+ (rx->buff_size_byte_count) & 0x0000ffff;
+ eth_data = (char *) p->eth_rx_buffer[p->rdn];
+
+#ifdef DEBUG
+ if (eth_len) {
+ printf ("%s: Recived %d byte Packet @ 0x%p\n",
+ __FUNCTION__, eth_len, eth_data);
+ }
+#endif
+ /*
+ * packet is now in:
+ * eth0_rx_buffer[RDN_ETH0];
+ */
+
+ /* let the upper layer handle the packet */
+ NetReceive ((uchar *)eth_data, eth_len);
+
+ rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
+
+
+ /* GT96100 Owner */
+ rx->command_status = 0x80000000;
+
+ FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
+
+ p->rdn ++;
+ if (p->rdn == NR) {p->rdn = 0;}
+
+ sync();
+
+ /* Start Rx*/
+ GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080);
+
+#ifdef DEBUG
+ {
+ int i;
+ for (i=0;i<12;i++) {
+ printf(" %02x", eth_data[i]);
+ }
+ }
+ printf(": %d bytes\n", eth_len);
+#endif
+ INVALIDATE_DCACHE((unsigned int)eth_data,
+ (unsigned int)eth_data+eth_len);
+ return eth_len;
+}
+
+/**************************************************************************
+POLL - look for an rx frame, handle other conditions
+***************************************************************************/
+int
+gt6426x_eth_poll(void *v)
+{
+ struct eth_device *wp = (struct eth_device *)v;
+ struct eth_dev_s *p = wp->priv;
+ unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base);
+
+ if(icr) {
+ GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0);
+#ifdef DEBUG
+ printf("poll got ICR %08x\n", icr);
+#endif
+ /* SMI done or PHY state change*/
+ if(icr&0x30000000) gt6426x_handle_SMI(p, icr);
+ }
+ /* always process. We aren't using RX interrupts */
+ return gt6426x_eth_receive(p, icr);
+}
+
+/**************************************************************************
+TRANSMIT - Transmit a frame
+***************************************************************************/
+int gt6426x_eth_transmit(void *v, char *p, unsigned int s)
+{
+ struct eth_device *wp = (struct eth_device *)v;
+ struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv;
+#ifdef DEBUG
+ unsigned int old_command_stat,old_psr;
+#endif
+ eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn];
+
+ /* wait for tx to be ready */
+ INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
+ while (tx->command_status & 0x80000000) {
+ int i;
+ for(i=0;i<1000;i++);
+ INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
+ }
+
+ GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base,
+ (unsigned int)tx);
+
+#ifdef DEBUG
+ printf("copying to tx_buffer [%p], length %x, desc = %p\n",
+ dev->eth_tx_buffer, s, dev->eth_tx_desc);
+#endif
+ memcpy(dev->eth_tx_buffer, (char *) p, s);
+
+ tx->buff_pointer = (uchar *)dev->eth_tx_buffer;
+ tx->bytecount_reserved = ((__u16)s) << 16;
+
+ /* 31 - own
+ * 22 - gencrc
+ * 18:16 - pad, last, first */
+ tx->command_status = (1<<31) | (1<<22) | (7<<16);
+#if 0
+ /* FEr #18 */
+ tx->next_desc = NULL;
+#else
+ tx->next_desc =
+ (struct eth0_tx_desc_struct *)
+ &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved;
+
+ /* cpu owned */
+ dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16); /* pad, last, first */
+#endif
+
+#ifdef DEBUG
+ old_command_stat=tx->command_status,
+ old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
+#endif
+
+ FLUSH_DCACHE((unsigned int)tx,
+ (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]);
+
+ FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s);
+
+ GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000);
+
+#ifdef DEBUG
+ {
+ unsigned int command_stat=0;
+ printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr);
+ /* wait for tx to be ready */
+ do {
+ unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
+ command_stat=tx->command_status;
+ if(command_stat!=old_command_stat || psr !=old_psr) {
+ printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr);
+ old_command_stat = command_stat;
+ old_psr = psr;
+ }
+ /* gt6426x_eth0_poll(); */
+ } while (command_stat & 0x80000000);
+
+ printf("sent %d byte frame\n", s);
+
+ if((command_stat & (3<<15)) == 3) {
+ printf("frame had error (stat=%08x)\n", command_stat);
+ }
+ }
+#endif
+ return 0;
+}
+
+/**************************************************************************
+DISABLE - Turn off ethernet interface
+***************************************************************************/
+void
+gt6426x_eth_disable(void *v)
+{
+ struct eth_device *wp = (struct eth_device *)v;
+ struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
+
+ GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000);
+}
+
+/**************************************************************************
+MII utilities - write: write to an MII register via SMI
+***************************************************************************/
+int
+gt6426x_miiphy_write(const char *devname, unsigned char phy,
+ unsigned char reg, unsigned short data)
+{
+ unsigned int temp= (reg<<21) | (phy<<16) | data;
+
+ while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */
+
+ GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
+ return 0;
+}
+
+/**************************************************************************
+MII utilities - read: read from an MII register via SMI
+***************************************************************************/
+int
+gt6426x_miiphy_read(const char *devname, unsigned char phy,
+ unsigned char reg, unsigned short *val)
+{
+ unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
+
+ while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */
+
+ GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
+
+ while(1) {
+ temp=GTREGREAD(ETHERNET_SMI_REGISTER);
+ if(temp & (1<<27)) break; /* wait for ReadValid */
+ }
+ *val = temp & 0xffff;
+
+ return 0;
+}
+
+#ifdef DEBUG
+/**************************************************************************
+MII utilities - dump mii registers
+***************************************************************************/
+static void
+gt6426x_dump_mii(bd_t *bis, unsigned short phy)
+{
+ printf("mii reg 0 - 3: %04x %04x %04x %04x\n",
+ miiphy_read_ret(phy, 0x0),
+ miiphy_read_ret(phy, 0x1),
+ miiphy_read_ret(phy, 0x2),
+ miiphy_read_ret(phy, 0x3)
+ );
+ printf(" 4 - 7: %04x %04x %04x %04x\n",
+ miiphy_read_ret(phy, 0x4),
+ miiphy_read_ret(phy, 0x5),
+ miiphy_read_ret(phy, 0x6),
+ miiphy_read_ret(phy, 0x7)
+ );
+ printf(" 8: %04x\n",
+ miiphy_read_ret(phy, 0x8)
+ );
+ printf(" 16-19: %04x %04x %04x %04x\n",
+ miiphy_read_ret(phy, 0x10),
+ miiphy_read_ret(phy, 0x11),
+ miiphy_read_ret(phy, 0x12),
+ miiphy_read_ret(phy, 0x13)
+ );
+ printf(" 20,30: %04x %04x\n",
+ miiphy_read_ret(phy, 20),
+ miiphy_read_ret(phy, 30)
+ );
+}
+#endif
+
+#ifdef RESTART_AUTONEG
+
+/* If link is up && autoneg compleate, and if
+ * GT and PHY disagree about link capabilitys,
+ * restart autoneg - something screwy with FD/HD
+ * unless we do this. */
+static void
+check_phy_state(struct eth_dev_s *p)
+{
+ int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_BMSR);
+ int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
+
+ if ((psr & 1<<3) && (bmsr & BMSR_LSTATUS)) {
+ int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_ADVERTISE) &
+ miiphy_read_ret(ether_port_phy_addr[p->dev], MII_LPA);
+ int want;
+
+ if (nego & LPA_100FULL) {
+ want = 0x3;
+ printf("MII: 100Base-TX, Full Duplex\n");
+ } else if (nego & LPA_100HALF) {
+ want = 0x1;
+ printf("MII: 100Base-TX, Half Duplex\n");
+ } else if (nego & LPA_10FULL) {
+ want = 0x2;
+ printf("MII: 10Base-T, Full Duplex\n");
+ } else if (nego & LPA_10HALF) {
+ want = 0x0;
+ printf("MII: 10Base-T, Half Duplex\n");
+ } else {
+ printf("MII: Unknown link-foo! %x\n", nego);
+ return;
+ }
+
+ if ((psr & 0x3) != want) {
+ printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
+ psr & 0x3, want);
+ miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0,
+ miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
+ udelay(10000); /* the EVB's GT takes a while to notice phy
+ went down and up */
+ }
+ }
+}
+#endif
+
+/**************************************************************************
+PROBE - Look for an adapter, this routine's visible to the outside
+***************************************************************************/
+int
+gt6426x_eth_probe(void *v, bd_t *bis)
+{
+ struct eth_device *wp = (struct eth_device *)v;
+ struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
+ int dev = p->dev;
+ unsigned int reg_base = p->reg_base;
+ unsigned long temp;
+ int i;
+
+ if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS ))
+ { /* This should never happen */
+ printf("%s: Invalid device %d\n", __FUNCTION__, dev );
+ return 0;
+ }
+
+#ifdef DEBUG
+ printf ("%s: initializing %s\n", __FUNCTION__, wp->name );
+ printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n",
+ GTREGREAD(COMM_UNIT_ARBITER_CONTROL),
+ GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER));
+#endif
+
+ /* clear MIB counters */
+ for(i=0;i<255; i++)
+ temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i);
+
+#ifdef CONFIG_INTEL_LXT97X
+ /* for intel LXT972 */
+
+ /* led 1: 0x1=txact
+ led 2: 0xc=link/rxact
+ led 3: 0x2=rxact (N/C)
+ strch: 0,2=30 ms, enable */
+ miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22);
+
+ /* 2.7ns port rise time */
+ /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
+#else
+ /* already set up in mpsc.c */
+ /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); / b400 */
+
+ /* already set up in sdram_init.S... */
+ /* MPSC0, MPSC1, RMII */
+ /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); / f010 */
+#endif
+ GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER,
+ ether_port_phy_addr[0] |
+ (ether_port_phy_addr[1]<<5) |
+ (ether_port_phy_addr[2]<<10)); /* 2000 */
+
+ /* 13:12 - 10: 4x64bit burst (cache line size = 32 bytes)
+ * 9 - 1: RIFB - interrupt on frame boundaries only
+ * 6:7 - 00: big endian rx and tx
+ * 5:2 - 1111: 15 retries */
+ GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base,
+ (2<<12) | (1<<9) | (0xf<<2) ); /* 2440 */
+
+#ifndef USE_SOFTWARE_CACHE_MANAGEMENT
+ /* enable rx/tx desc/buffer cache snoop */
+ GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
+ &temp); /* f200 */
+ temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30);
+ GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
+ temp);
+#endif
+
+ /* 31 28 27 24 23 20 19 16
+ * 0000 0000 0000 0000 [0004]
+ * 15 12 11 8 7 4 3 0
+ * 1000 1101 0000 0000 [4d00]
+ * 20 - 0=MII 1=RMII
+ * 19 - 0=speed autoneg
+ * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE)
+ * 11 - no force link pass
+ * 10 - 1=disable fctl autoneg
+ * 8 - override prio ?? */
+ temp = 0x00004d00;
+#ifndef CONFIG_ETHER_PORT_MII
+ temp |= (1<<20); /* RMII */
+#endif
+ /* set En */
+ GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base,
+ temp); /* 2408 */
+
+ /* hardcode E1 also? */
+ /* -- according to dox, this is safer due to extra pulldowns? */
+ if (dev<2) {
+ GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400,
+ temp); /* 2408 */
+ }
+
+ /* wake up MAC */ /* 2400 */
+ GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp);
+ temp |= (1<<7); /* enable port */
+#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
+ temp |= (1<<12); /* hash size 1/2k */
+#else
+ temp |= 1; /* promisc */
+#endif
+ GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp);
+ /* 2400 */
+
+#ifdef RESTART_AUTONEG
+ check_phy_state(p);
+#endif
+
+ printf("%s: Waiting for link up..\n", wp->name);
+ temp = 10 * 1000;
+ /* wait for link back up */
+ while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8)
+ && (--temp > 0)){
+ udelay(1000); /* wait 1 ms */
+ }
+ if ( temp == 0) {
+ printf("%s: Failed!\n", wp->name);
+ return (0);
+ }
+
+ printf("%s: OK!\n", wp->name);
+
+ p->tdn = 0;
+ p->rdn = 0;
+ p->eth_tx_desc[p->tdn].command_status = 0;
+
+ /* Initialize Rx Side */
+ for (temp = 0; temp < NR; temp++) {
+ p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp];
+ p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
+
+ /* GT96100 Owner */
+ p->eth_rx_desc[temp].command_status = 0x80000000;
+ p->eth_rx_desc[temp].next_desc =
+ (struct eth0_rx_desc_struct *)
+ &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count;
+ }
+
+ FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0],
+ (unsigned int)&p->eth_tx_desc[NR]);
+ FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0],
+ (unsigned int)&p->eth_rx_desc[NR]);
+
+ GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base,
+ (unsigned int) p->eth_tx_desc);
+ GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base,
+ (unsigned int) p->eth_rx_desc);
+ GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base,
+ (unsigned int) p->eth_rx_desc);
+
+#ifdef DEBUG
+ printf ("\nRx descriptor pointer is %08x %08x\n",
+ GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base),
+ GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base));
+ printf ("\n\n%08x %08x\n",
+ (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status);
+
+ printf ("Descriptor dump:\n");
+ printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status);
+ printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count);
+ printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer);
+ printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc);
+ printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0));
+ printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4));
+ printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8));
+ printf ("%08x\n\n",
+ *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc));
+#endif
+
+#ifdef DEBUG
+ gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]);
+#endif
+
+#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
+ {
+ unsigned int hashtable_base;
+ u8 *b = (u8 *)(wp->enetaddr);
+ u32 macH, macL;
+
+ /* twist the MAC up into the way the discovery wants it */
+ macH= (b[0]<<8) | b[1];
+ macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5];
+
+ /* mode 0, size 0x800 */
+ hashtable_base =initAddressTable(dev,0,1);
+
+ if(!hashtable_base) {
+ printf("initAddressTable failed\n");
+ return 0;
+ }
+
+ addAddressTableEntry(dev, macH, macL, 1, 0);
+ GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base,
+ hashtable_base);
+ }
+#endif
+
+ /* Start Rx*/
+ GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080);
+ printf("%s: gt6426x eth device %d init success \n", wp->name, dev );
+ return 1;
+}
+
+/* enter all the galileo ethernet devs into MULTI-BOOT */
+void
+gt6426x_eth_initialize(bd_t *bis)
+{
+ struct eth_device *dev;
+ struct eth_dev_s *p;
+ int devnum, x, temp;
+ char *s, *e, buf[64];
+
+#ifdef DEBUG
+ printf( "\n%s\n", __FUNCTION );
+#endif
+
+ for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) {
+ dev = calloc(sizeof(*dev), 1);
+ if (!dev) {
+ printf( "%s: gal_enet%d allocation failure, %s\n",
+ __FUNCTION__, devnum, "eth_device structure");
+ return;
+ }
+
+ /* must be less than sizeof(dev->name) */
+ sprintf(dev->name, "gal_enet%d", devnum);
+
+#ifdef DEBUG
+ printf( "Initializing %s\n", dev->name );
+#endif
+
+ /* Extract the MAC address from the environment */
+ switch (devnum)
+ {
+ case 0: s = "ethaddr"; break;
+#if (GAL_ETH_DEVS > 1)
+ case 1: s = "eth1addr"; break;
+#endif
+#if (GAL_ETH_DEVS > 2)
+ case 2: s = "eth2addr"; break;
+#endif
+ default: /* this should never happen */
+ printf( "%s: Invalid device number %d\n",
+ __FUNCTION__, devnum );
+ return;
+ }
+
+ temp = getenv_f(s, buf, sizeof(buf));
+ s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+ printf ("Setting MAC %d to %s\n", devnum, s );
+#endif
+ for (x = 0; x < 6; ++x) {
+ dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e+1 : e;
+ }
+
+ dev->init = (void*)gt6426x_eth_probe;
+ dev->halt = (void*)gt6426x_eth_reset;
+ dev->send = (void*)gt6426x_eth_transmit;
+ dev->recv = (void*)gt6426x_eth_poll;
+
+ p = calloc( sizeof(*p), 1 );
+ dev->priv = (void*)p;
+ if (!p)
+ {
+ printf( "%s: %s allocation failure, %s\n",
+ __FUNCTION__, dev->name, "Private Device Structure");
+ free(dev);
+ return;
+ }
+
+ p->dev = devnum;
+ p->tdn=0;
+ p->rdn=0;
+ p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS;
+
+ p->eth_tx_desc =
+ (eth0_tx_desc_single *)
+ (((unsigned int) malloc(sizeof (eth0_tx_desc_single) *
+ (NT+1)) & 0xfffffff0) + 0x10);
+ if (!p)
+ {
+ printf( "%s: %s allocation failure, %s\n",
+ __FUNCTION__, dev->name, "Tx Descriptor");
+ free(dev);
+ return;
+ }
+
+ p->eth_rx_desc =
+ (eth0_rx_desc_single *)
+ (((unsigned int) malloc(sizeof (eth0_rx_desc_single) *
+ (NR+1)) & 0xfffffff0) + 0x10);
+ if (!p->eth_rx_desc)
+ {
+ printf( "%s: %s allocation failure, %s\n",
+ __FUNCTION__, dev->name, "Rx Descriptor");
+ free(dev);
+ free(p);
+ return;
+ }
+
+ p->eth_tx_buffer =
+ (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
+ if (!p->eth_tx_buffer)
+ {
+ printf( "%s: %s allocation failure, %s\n",
+ __FUNCTION__, dev->name, "Tx Bufffer");
+ free(dev);
+ free(p);
+ free(p->eth_rx_desc);
+ return;
+ }
+
+ for (temp = 0 ; temp < NR ; temp ++) {
+ p->eth_rx_buffer[temp] =
+ (char *)
+ (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
+ if (!p->eth_rx_buffer[temp])
+ {
+ printf( "%s: %s allocation failure, %s\n",
+ __FUNCTION__, dev->name, "Rx Buffers");
+ free(dev);
+ free(p);
+ free(p->eth_tx_buffer);
+ free(p->eth_rx_desc);
+ free(p->eth_tx_desc);
+ while (temp >= 0)
+ free(p->eth_rx_buffer[--temp]);
+ return;
+ }
+ }
+
+
+ eth_register(dev);
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+ miiphy_register(dev->name,
+ gt6426x_miiphy_read, gt6426x_miiphy_write);
+#endif
+ }
+
+}
+#endif
diff --git a/board/evb64260/eth.h b/board/evb64260/eth.h
new file mode 100644
index 0000000..99581f0
--- /dev/null
+++ b/board/evb64260/eth.h
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __GT6426x_ETH_H__
+#define __GT6426x_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+typedef struct eth0_tx_desc_struct {
+ volatile __u32 bytecount_reserved;
+ volatile __u32 command_status;
+ volatile struct eth0_tx_desc_struct * next_desc;
+ /* Note - the following will not work for 64 bit addressing */
+ volatile unsigned char * buff_pointer;
+} __attribute__ ((packed)) eth0_tx_desc_single;
+
+typedef struct eth0_rx_desc_struct {
+ volatile __u32 buff_size_byte_count;
+ volatile __u32 command_status;
+ volatile struct eth0_rx_desc_struct * next_desc;
+ volatile unsigned char * buff_pointer;
+} __attribute__ ((packed)) eth0_rx_desc_single;
+
+#define NT 20 /* Number of Transmit buffers */
+#define NR 20 /* Number of Receive buffers */
+#define MAX_BUFF_SIZE (1536+2*CACHE_LINE_SIZE) /* 1600 */
+#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400
+
+unsigned long TDN_ETH0 , RDN_ETH0; /* Rx/Tx current Descriptor Number*/
+unsigned int EVB64260_ETH0_irq;
+
+#define CLOSED 0
+#define OPENED 1
+
+#define PORT_ETH0 0
+
+extern eth0_tx_desc_single *eth0_tx_desc;
+extern eth0_rx_desc_single *eth0_rx_desc;
+extern char *eth0_tx_buffer;
+extern char *eth0_rx_buffer[NR];
+extern char *eth_data;
+
+extern int gt6426x_eth_poll(void *v);
+extern int gt6426x_eth_transmit(void *v, char *p, unsigned int s);
+extern void gt6426x_eth_disable(void *v);
+extern int gt6426x_eth_probe(void *v, bd_t *bis);
+
+#endif /* __GT64260x_ETH_H__ */
diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c
new file mode 100644
index 0000000..8c2c17f
--- /dev/null
+++ b/board/evb64260/eth_addrtbl.c
@@ -0,0 +1,218 @@
+#include <common.h>
+#include <malloc.h>
+#include <galileo/gt64260R.h>
+#include <galileo/core.h>
+#include <asm/cache.h>
+#include "eth.h"
+#include "eth_addrtbl.h"
+
+#define PRINTF printf
+
+#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
+
+static u32 addressTableHashMode[GAL_ETH_DEVS] = { 0, };
+static u32 addressTableHashSize[GAL_ETH_DEVS] = { 0, };
+static addrTblEntry *addressTableBase[GAL_ETH_DEVS] = { 0, };
+static void *realAddrTableBase[GAL_ETH_DEVS] = { 0, };
+
+static const u32 hashLength[2] = {
+ (0x8000), /* 8K * 4 entries */
+ (0x8000 / 16), /* 512 * 4 entries */
+};
+
+/* Initialize the address table for a port, if needed */
+unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector)
+{
+ unsigned int tableBase;
+
+ if (port < 0 || port >= GAL_ETH_DEVS) {
+ printf ("%s: Invalid port number %d\n", __FUNCTION__, port);
+ return 0;
+ }
+
+ if (hashMode > 1) {
+ printf ("%s: Invalid Hash Mode %d\n", __FUNCTION__, port);
+ return 0;
+ }
+
+ if (realAddrTableBase[port] &&
+ (addressTableHashSize[port] != hashSizeSelector)) {
+ /* we have been here before,
+ * but now we want a different sized table
+ */
+ free (realAddrTableBase[port]);
+ realAddrTableBase[port] = 0;
+ addressTableBase[port] = 0;
+
+ }
+
+ tableBase = (unsigned int) addressTableBase[port];
+ /* we get called for every probe, so only do this once */
+ if (!tableBase) {
+ int bytes =
+ hashLength[hashSizeSelector] * sizeof (addrTblEntry);
+
+ realAddrTableBase[port] =
+ malloc (bytes + 64);
+ tableBase = (unsigned int)realAddrTableBase;
+
+ if (!tableBase) {
+ printf ("%s: alloc memory failed \n", __FUNCTION__);
+ return 0;
+ }
+
+ /* align to octal byte */
+ if (tableBase & 63)
+ tableBase = (tableBase + 63) & ~63;
+
+ addressTableHashMode[port] = hashMode;
+ addressTableHashSize[port] = hashSizeSelector;
+ addressTableBase[port] = (addrTblEntry *) tableBase;
+
+ memset ((void *) tableBase, 0, bytes);
+ }
+
+ return tableBase;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * This function will calculate the hash function of the address.
+ * depends on the hash mode and hash size.
+ * Inputs
+ * macH - the 2 most significant bytes of the MAC address.
+ * macL - the 4 least significant bytes of the MAC address.
+ * hashMode - hash mode 0 or hash mode 1.
+ * hashSizeSelector - indicates number of hash table entries (0=0x8000,1=0x800)
+ * Outputs
+ * return the calculated entry.
+ */
+u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
+{
+ u32 hashResult;
+ u32 addrH;
+ u32 addrL;
+ u32 addr0;
+ u32 addr1;
+ u32 addr2;
+ u32 addr3;
+ u32 addrHSwapped;
+ u32 addrLSwapped;
+
+
+ addrH = NIBBLE_SWAPPING_16_BIT (macH);
+ addrL = NIBBLE_SWAPPING_32_BIT (macL);
+
+ addrHSwapped = FLIP_4_BITS (addrH & 0xf)
+ + ((FLIP_4_BITS ((addrH >> 4) & 0xf)) << 4)
+ + ((FLIP_4_BITS ((addrH >> 8) & 0xf)) << 8)
+ + ((FLIP_4_BITS ((addrH >> 12) & 0xf)) << 12);
+
+ addrLSwapped = FLIP_4_BITS (addrL & 0xf)
+ + ((FLIP_4_BITS ((addrL >> 4) & 0xf)) << 4)
+ + ((FLIP_4_BITS ((addrL >> 8) & 0xf)) << 8)
+ + ((FLIP_4_BITS ((addrL >> 12) & 0xf)) << 12)
+ + ((FLIP_4_BITS ((addrL >> 16) & 0xf)) << 16)
+ + ((FLIP_4_BITS ((addrL >> 20) & 0xf)) << 20)
+ + ((FLIP_4_BITS ((addrL >> 24) & 0xf)) << 24)
+ + ((FLIP_4_BITS ((addrL >> 28) & 0xf)) << 28);
+
+ addrH = addrHSwapped;
+ addrL = addrLSwapped;
+
+ if (hash_mode == 0) {
+ addr0 = (addrL >> 2) & 0x03f;
+ addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2;
+ addr2 = (addrL >> 15) & 0x1ff;
+ addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8);
+ } else {
+ addr0 = FLIP_6_BITS (addrL & 0x03f);
+ addr1 = FLIP_9_BITS (((addrL >> 6) & 0x1ff));
+ addr2 = FLIP_9_BITS ((addrL >> 15) & 0x1ff);
+ addr3 = FLIP_9_BITS ((((addrL >> 24) & 0x0ff) |
+ ((addrH & 0x1) << 8)));
+ }
+
+ hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
+
+ if (HashSize == _8K_TABLE) {
+ hashResult = hashResult & 0xffff;
+ } else {
+ hashResult = hashResult & 0x07ff;
+ }
+
+ return (hashResult);
+}
+
+
+/*
+ * ----------------------------------------------------------------------------
+ * This function will add an entry to the address table.
+ * depends on the hash mode and hash size that was initialized.
+ * Inputs
+ * port - ETHERNET port number.
+ * macH - the 2 most significant bytes of the MAC address.
+ * macL - the 4 least significant bytes of the MAC address.
+ * skip - if 1, skip this address.
+ * rd - the RD field in the address table.
+ * Outputs
+ * address table entry is added.
+ * true if success.
+ * false if table full
+ */
+int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip)
+{
+ addrTblEntry *entry;
+ u32 newHi;
+ u32 newLo;
+ u32 i;
+
+ newLo = (((macH >> 4) & 0xf) << 15)
+ | (((macH >> 0) & 0xf) << 11)
+ | (((macH >> 12) & 0xf) << 7)
+ | (((macH >> 8) & 0xf) << 3)
+ | (((macL >> 20) & 0x1) << 31)
+ | (((macL >> 16) & 0xf) << 27)
+ | (((macL >> 28) & 0xf) << 23)
+ | (((macL >> 24) & 0xf) << 19)
+ | (skip << SKIP_BIT) | (rd << 2) | VALID;
+
+ newHi = (((macL >> 4) & 0xf) << 15)
+ | (((macL >> 0) & 0xf) << 11)
+ | (((macL >> 12) & 0xf) << 7)
+ | (((macL >> 8) & 0xf) << 3)
+ | (((macL >> 21) & 0x7) << 0);
+
+ /*
+ * Pick the appropriate table, start scanning for free/reusable
+ * entries at the index obtained by hashing the specified MAC address
+ */
+ entry = addressTableBase[port];
+ entry += hashTableFunction (macH, macL, addressTableHashSize[port],
+ addressTableHashMode[port]);
+ for (i = 0; i < HOP_NUMBER; i++, entry++) {
+ if (!(entry->lo & VALID) /*|| (entry->lo & SKIP) */ ) {
+ break;
+ } else { /* if same address put in same position */
+ if (((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
+ && (entry->hi == newHi)) {
+ break;
+ }
+ }
+ }
+
+ if (i == HOP_NUMBER) {
+ PRINTF ("addGT64260addressTableEntry: table section is full\n");
+ return false;
+ }
+
+ /*
+ * Update the selected entry
+ */
+ entry->hi = newHi;
+ entry->lo = newLo;
+ DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE);
+ return true;
+}
+
+#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */
diff --git a/board/evb64260/eth_addrtbl.h b/board/evb64260/eth_addrtbl.h
new file mode 100644
index 0000000..5a62c67
--- /dev/null
+++ b/board/evb64260/eth_addrtbl.h
@@ -0,0 +1,83 @@
+#ifndef _ADDRESS_TABLE_H
+#define _ADDRESS_TABLE_H 1
+
+/*
+ * ----------------------------------------------------------------------------
+ * addressTable.h - this file has all the declarations of the address table
+ */
+
+#define _8K_TABLE 0
+#define ADDRESS_TABLE_ALIGNMENT 8
+#define HASH_DEFAULT_MODE 14
+#define HASH_MODE 13
+#define HASH_SIZE 12
+#define HOP_NUMBER 12
+#define MAC_ADDRESS_STRING_SIZE 12
+#define MAC_ENTRY_SIZE sizeof(addrTblEntry)
+#define MAX_NUMBER_OF_ADDRESSES_TO_STORE 1000
+#define PROMISCUOUS_MODE 0
+#define SKIP 1<<1
+#define SKIP_BIT 1
+#define VALID 1
+
+/*
+ * ----------------------------------------------------------------------------
+ * XXX_MIKE - potential sign-extension bugs lurk here...
+ */
+#define NIBBLE_SWAPPING_32_BIT(X) ( (((X) & 0xf0f0f0f0) >> 4) \
+ | (((X) & 0x0f0f0f0f) << 4) )
+
+#define NIBBLE_SWAPPING_16_BIT(X) ( (((X) & 0x0000f0f0) >> 4) \
+ | (((X) & 0x00000f0f) << 4) )
+
+#define FLIP_4_BITS(X) ( (((X) & 0x01) << 3) | (((X) & 0x002) << 1) \
+ | (((X) & 0x04) >> 1) | (((X) & 0x008) >> 3) )
+
+#define FLIP_6_BITS(X) ( (((X) & 0x01) << 5) | (((X) & 0x020) >> 5) \
+ | (((X) & 0x02) << 3) | (((X) & 0x010) >> 3) \
+ | (((X) & 0x04) << 1) | (((X) & 0x008) >> 1) )
+
+#define FLIP_9_BITS(X) ( (((X) & 0x01) << 8) | (((X) & 0x100) >> 8) \
+ | (((X) & 0x02) << 6) | (((X) & 0x080) >> 6) \
+ | (((X) & 0x04) << 4) | (((X) & 0x040) >> 4) \
+ | ((X) & 0x10) | (((X) & 0x08) << 2) | (((X) & 0x020) >> 2) )
+
+/*
+ * V: value we're operating on
+ * O: offset of rightmost bit in field
+ * W: width of field to shift
+ * S: distance to shift left
+ */
+#define MASK( fieldWidth ) ((1 << (fieldWidth)) - 1)
+#define leftShiftedBitfield( V,O,W,S) (((V) & (MASK(W) << (O))) << (S))
+#define rightShiftedBitfield(V,O,W,S) (((u32)((V) & (MASK(W) << (O)))) >> (S))
+
+
+/*
+ * Push to main memory all cache lines associated with
+ * the specified range of virtual memory addresses
+ *
+ * A: Address of first byte in range to flush
+ * N: Number of bytes to flush
+ * Note - flush_dcache_range() does a "sync", does NOT invalidate
+ */
+#define DCACHE_FLUSH_N_SYNC( A, N ) flush_dcache_range( (A), ((A)+(N)) )
+
+
+typedef struct addressTableEntryStruct {
+ u32 hi;
+ u32 lo;
+} addrTblEntry;
+
+u32
+uncachedPages( u32 pages );
+u32
+hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode );
+
+unsigned int
+initAddressTable( u32 port, u32 hashMode, u32 hashSize );
+
+int
+addAddressTableEntry( u32 port, u32 macH, u32 macL, u32 rd, u32 skip );
+
+#endif /* #ifndef _ADDRESS_TABLE_H */
diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c
new file mode 100644
index 0000000..74f8819
--- /dev/null
+++ b/board/evb64260/evb64260.c
@@ -0,0 +1,436 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * evb64260.c - main board support/init for the Galileo Eval board.
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include <galileo/memory.h>
+#include <galileo/pci.h>
+#include <galileo/gt64260R.h>
+#include <net.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+
+#include <asm/io.h>
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64260.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ZUMA_V2
+extern void zuma_mbox_init(void);
+#endif
+
+#undef DEBUG
+#define MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void
+my_remap_gt_regs(u32 cur_loc, u32 new_loc)
+{
+ u32 temp;
+
+ /* check and see if it's already moved */
+ temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
+ if ((temp & 0xffff) == new_loc >> 20)
+ return;
+
+ temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
+ 0xffff0000) | (new_loc >> 20);
+
+ out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+ while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
+}
+
+static void
+gt_pci_config(void)
+{
+ /* move PCI stuff out of the way - NTL */
+ /* map PCI Host 0 */
+ pciMapSpace(PCI_HOST0, PCI_REGION0, CONFIG_SYS_PCI0_0_MEM_SPACE,
+ CONFIG_SYS_PCI0_0_MEM_SPACE, CONFIG_SYS_PCI0_MEM_SIZE);
+
+ pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0);
+ pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0);
+ pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0);
+
+ pciMapSpace(PCI_HOST0, PCI_IO, CONFIG_SYS_PCI0_IO_SPACE_PCI,
+ CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE);
+
+ /* map PCI Host 1 */
+ pciMapSpace(PCI_HOST1, PCI_REGION0, CONFIG_SYS_PCI1_0_MEM_SPACE,
+ CONFIG_SYS_PCI1_0_MEM_SPACE, CONFIG_SYS_PCI1_MEM_SIZE);
+
+ pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0);
+ pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0);
+ pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0);
+
+ pciMapSpace(PCI_HOST1, PCI_IO, CONFIG_SYS_PCI1_IO_SPACE_PCI,
+ CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE);
+
+ /* PCI interface settings */
+ GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff);
+ GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff);
+ GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
+ GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
+
+
+}
+
+/* Setup CPU interface paramaters */
+static void
+gt_cpu_config(void)
+{
+ cpu_t cpu = get_cpu_type();
+ ulong tmp;
+
+ /* cpu configuration register */
+ tmp = GTREGREAD(CPU_CONFIGURATION);
+
+ /* set the AACK delay bit
+ * see Res#14 */
+ tmp |= CPU_CONF_AACK_DELAY;
+ tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */
+
+ /* Galileo claims this is necessary for all busses >= 100 MHz */
+ tmp |= CPU_CONF_FAST_CLK;
+
+ if (cpu == CPU_750CX) {
+ tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */
+ tmp &= ~CPU_CONF_AP_VALID;
+ } else {
+ tmp |= CPU_CONF_DP_VALID;
+ tmp |= CPU_CONF_AP_VALID;
+ }
+
+ /* this only works with the MPX bus */
+ tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */
+ tmp |= CPU_CONF_PIPELINE;
+ tmp |= CPU_CONF_TA_DELAY;
+
+ GT_REG_WRITE(CPU_CONFIGURATION, tmp);
+
+ /* CPU master control register */
+ tmp = GTREGREAD(CPU_MASTER_CONTROL);
+
+ tmp |= CPU_MAST_CTL_ARB_EN;
+
+ if ((cpu == CPU_7400) ||
+ (cpu == CPU_7410) ||
+ (cpu == CPU_7450)) {
+
+ tmp |= CPU_MAST_CTL_CLEAN_BLK;
+ tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+ } else {
+ /* cleanblock must be cleared for CPUs
+ * that do not support this command
+ * see Res#1 */
+ tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+ tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+ }
+ GT_REG_WRITE(CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+ uchar sram_boot = 0;
+
+ /*
+ * set up the GT the way the kernel wants it
+ * the call to move the GT register space will obviously
+ * fail if it has already been done, but we're going to assume
+ * that if it's not at the power-on location, it's where we put
+ * it last time. (huber)
+ */
+ my_remap_gt_regs(CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
+
+ gt_pci_config();
+
+ /* mask all external interrupt sources */
+ GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+ GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+ GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+ GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+ GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+ GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+ GT_REG_WRITE(CPU_INT_0_MASK, 0);
+ GT_REG_WRITE(CPU_INT_1_MASK, 0);
+ GT_REG_WRITE(CPU_INT_2_MASK, 0);
+ GT_REG_WRITE(CPU_INT_3_MASK, 0);
+
+ /* now, onto the configuration */
+ GT_REG_WRITE(SDRAM_CONFIGURATION, CONFIG_SYS_SDRAM_CONFIG);
+
+ /* ----- DEVICE BUS SETTINGS ------ */
+
+ /*
+ * EVB
+ * 0 - SRAM
+ * 1 - RTC
+ * 2 - UART
+ * 3 - Flash
+ * boot - BootCS
+ *
+ * Zuma
+ * 0 - Flash
+ * boot - BootCS
+ */
+
+ /*
+ * the dual 7450 module requires burst access to the boot
+ * device, so the serial rom copies the boot device to the
+ * on-board sram on the eval board, and updates the correct
+ * registers to boot from the sram. (device0)
+ */
+#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
+ /* Zuma has no SRAM */
+ sram_boot = 0;
+#else
+ if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CONFIG_SYS_MONITOR_BASE)
+ sram_boot = 1;
+#endif
+
+ memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+
+ memoryMapDeviceSpace(DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+ memoryMapDeviceSpace(DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+ memoryMapDeviceSpace(DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
+
+ /* configure device timing */
+#ifdef CONFIG_SYS_DEV0_PAR
+ if (!sram_boot)
+ GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
+#endif
+
+#ifdef CONFIG_SYS_DEV1_PAR
+ GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
+#endif
+#ifdef CONFIG_SYS_DEV2_PAR
+ GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
+#endif
+
+#ifdef CONFIG_EVB64260
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR
+ /* detect if we are booting from the 32 bit flash */
+ if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
+ /* 32 bit boot flash */
+ GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+ GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+ } else {
+ /* 8 bit boot flash */
+ GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+ GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+ }
+#else
+ /* 8 bit boot flash only */
+ GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+#endif
+#else /* CONFIG_EVB64260 not defined */
+ /* We are booting from 16-bit flash.
+ */
+ GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_16BIT_BOOT_PAR);
+#endif
+
+ gt_cpu_config();
+
+ /* MPP setup */
+ GT_REG_WRITE(MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+ GT_REG_WRITE(MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+ GT_REG_WRITE(MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+ GT_REG_WRITE(MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
+
+ GT_REG_WRITE(GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
+ GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CONFIG_SYS_SERIAL_PORT_MUX);
+
+ return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r (void)
+{
+ icache_enable();
+#ifdef CONFIG_SYS_L2
+ l2cache_enable();
+#endif
+
+#ifdef CONFIG_MPSC
+ mpsc_init2();
+#endif
+
+#ifdef CONFIG_ZUMA_V2
+ zuma_mbox_init();
+#endif
+ return (0);
+}
+
+void
+after_reloc(ulong dest_addr)
+{
+ /* check to see if we booted from the sram. If so, move things
+ * back to the way they should be. (we're running from main
+ * memory at this point now */
+
+ if (memoryGetDeviceBaseAddress(DEVICE0) == CONFIG_SYS_MONITOR_BASE) {
+ memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+ memoryMapDeviceSpace(BOOT_DEVICE, CONFIG_SYS_FLASH_BASE, _1M);
+ }
+
+ /* now, jump to the main U-Boot board init code */
+ board_init_r ((gd_t *)gd, dest_addr);
+
+ /* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int
+checkboard (void)
+{
+ puts ("Board: " CONFIG_SYS_BOARD_NAME "\n");
+ return (0);
+}
+
+/* utility functions */
+void
+debug_led(int led, int mode)
+{
+#if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4)
+ volatile int *addr = NULL;
+ __maybe_unused int dummy;
+
+ if (mode == 1) {
+ switch (led) {
+ case 0:
+ addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x08000);
+ break;
+
+ case 1:
+ addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x0c000);
+ break;
+
+ case 2:
+ addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x10000);
+ break;
+ }
+ } else if (mode == 0) {
+ switch (led) {
+ case 0:
+ addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x14000);
+ break;
+
+ case 1:
+ addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x18000);
+ break;
+
+ case 2:
+ addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x1c000);
+ break;
+ }
+ }
+ WRITE_CHAR(addr, 0);
+ dummy = *addr;
+#endif /* CONFIG_ZUMA_V2 */
+}
+
+void
+display_mem_map(void)
+{
+ int i,j;
+ unsigned int base,size,width;
+ /* SDRAM */
+ printf("SDRAM\n");
+ for(i=0;i<=BANK3;i++) {
+ base = memoryGetBankBaseAddress(i);
+ size = memoryGetBankSize(i);
+ if(size !=0)
+ {
+ printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20);
+ }
+ }
+
+ /* CPU's PCI windows */
+ for(i=0;i<=PCI_HOST1;i++) {
+ printf("\nCPU's PCI %d windows\n", i);
+ base=pciGetSpaceBase(i,PCI_IO);
+ size=pciGetSpaceSize(i,PCI_IO);
+ printf(" IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20);
+ for(j=0;j<=PCI_REGION3;j++) {
+ base = pciGetSpaceBase(i,j);
+ size = pciGetSpaceSize(i,j);
+ printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base,
+ size>>20);
+ }
+ }
+
+ /* Devices */
+ printf("\nDEVICES\n");
+ for(i=0;i<=DEVICE3;i++) {
+ base = memoryGetDeviceBaseAddress(i);
+ size = memoryGetDeviceSize(i);
+ width= memoryGetDeviceWidth(i) * 8;
+ printf("DEV %d: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
+ i, base, size>>20, width);
+ }
+
+ /* Bootrom */
+ base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */
+ size = memoryGetDeviceSize(BOOT_DEVICE);
+ width= memoryGetDeviceWidth(BOOT_DEVICE) * 8;
+ printf(" BOOT: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
+ base, size>>20, width);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ gt6426x_eth_initialize(bis);
+ return 0;
+}
diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c
new file mode 100644
index 0000000..f3b0074
--- /dev/null
+++ b/board/evb64260/flash.c
@@ -0,0 +1,837 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * flash.c - flash support for the 512k, 8bit boot flash on the GEVB
+ * most of this file was based on the existing U-Boot
+ * flash drivers.
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <galileo/gt64260R.h>
+#include <galileo/memory.h>
+#include "intel_flash.h"
+
+#define FLASH_ROM 0xFFFD /* unknown flash type */
+#define FLASH_RAM 0xFFFE /* unknown flash type */
+#define FLASH_MAN_UNKNOWN 0xFFFF0000
+
+/* #define DEBUG */
+/* #define FLASH_ID_OVERRIDE */ /* Hack to set type to 040B if ROM emulator is installed.
+ * Can be used to program a ROM in circuit if a programmer
+ * is not available by swapping the rom out. */
+
+/* Intel flash commands */
+int flash_erase_intel(flash_info_t *info, int s_first, int s_last);
+int write_word_intel(bank_addr_t addr, bank_word_t value);
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long
+flash_init (void)
+{
+ unsigned int i;
+ unsigned long size_b0 = 0, size_b1 = 0;
+ unsigned long base, flash_size;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* the boot flash */
+ base = CONFIG_SYS_FLASH_BASE;
+#ifndef CONFIG_SYS_BOOT_FLASH_WIDTH
+#define CONFIG_SYS_BOOT_FLASH_WIDTH 1
+#endif
+ size_b0 = flash_get_size(CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *)base,
+ &flash_info[0]);
+
+#ifndef CONFIG_P3G4
+ printf("[");
+ print_size (size_b0, "");
+ printf("@%08lX] ", base);
+#endif
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n",
+ base, size_b0, size_b0<<20);
+ }
+
+ base = memoryGetDeviceBaseAddress(CONFIG_SYS_EXTRA_FLASH_DEVICE);
+ for(i=1;i<CONFIG_SYS_MAX_FLASH_BANKS;i++) {
+ unsigned long size = flash_get_size(CONFIG_SYS_EXTRA_FLASH_WIDTH, (vu_long *)base, &flash_info[i]);
+
+#ifndef CONFIG_P3G4
+ printf("[");
+ print_size (size, "");
+ printf("@%08lX] ", base);
+#endif
+
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ if(i==1) {
+ printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n",
+ base, size_b1, size_b1<<20);
+ }
+ break;
+ }
+ size_b1+=size;
+ base+=size;
+ }
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ flash_get_info(CONFIG_SYS_MONITOR_BASE));
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+ flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+ flash_size = size_b0 + size_b1;
+ return flash_size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void
+flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+ int sector_size;
+
+ if(!info->sector_count) return;
+
+ /* set up sector start address table */
+ switch(info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ case FLASH_28F128J3A:
+ case FLASH_28F640J3A:
+ case FLASH_RAM:
+ /* this chip has uniformly spaced sectors */
+ sector_size=info->size/info->sector_count;
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * sector_size);
+ break;
+ default:
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00008000;
+ info->start[2] = base + 0x0000C000;
+ info->start[3] = base + 0x00010000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000) - 0x00060000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000C000;
+ info->start[i--] = base + info->size - 0x00010000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00020000;
+ }
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+flash_info_t *flash_get_info(ulong base)
+{
+ int i;
+ flash_info_t * info;
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
+ info = & flash_info[i];
+ if (info->start[0] <= base && base <= info->start[0] + info->size - 1)
+ break;
+ }
+
+ return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ case FLASH_MAN_INTEL: printf ("INTEL "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ printf ("AM29LV040B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400B:
+ printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T:
+ printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T:
+ printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B:
+ printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T:
+ printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B:
+ printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ case FLASH_28F640J3A:
+ printf ("28F640J3A (64 Mbit)\n");
+ break;
+ case FLASH_28F128J3A:
+ printf ("28F128J3A (128 Mbit)\n");
+ break;
+ case FLASH_ROM:
+ printf ("ROM\n");
+ break;
+ case FLASH_RAM:
+ printf ("RAM\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ puts (" Size: ");
+ print_size (info->size, "");
+ printf (" in %d Sectors\n", info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static inline void flash_cmd(int width, volatile unsigned char *addr, int offset, unsigned char cmd)
+{
+ /* supports 1x8, 1x16, and 2x16 */
+ /* 2x8 and 4x8 are not supported */
+ if(width==4) {
+ /* assuming chips are in 16 bit mode */
+ /* 2x16 */
+ unsigned long cmd32=(cmd<<16)|cmd;
+ *(volatile unsigned long *)(addr+offset*2)=cmd32;
+ } else if (width == 2) {
+ /* 1x16 */
+ *(volatile unsigned short *)((unsigned short*)addr+offset)=cmd;
+ } else {
+ /* 1x8 */
+ *(volatile unsigned char *)(addr+offset)=cmd;
+ }
+}
+
+static ulong
+flash_get_size (int portwidth, vu_long *addr, flash_info_t *info)
+{
+ short i;
+ volatile unsigned char *caddr = (unsigned char *)addr;
+ volatile unsigned short *saddr = (unsigned short *)addr;
+ volatile unsigned long *laddr = (unsigned long *)addr;
+ char old[2], save;
+ ulong id, manu, base = (ulong)addr;
+
+ info->portwidth=portwidth;
+
+ save = *caddr;
+
+ flash_cmd(portwidth,caddr,0,0xf0);
+ flash_cmd(portwidth,caddr,0,0xf0);
+
+ udelay(10);
+
+ old[0] = caddr[0];
+ old[1] = caddr[1];
+
+
+ if(old[0]!=0xf0) {
+ flash_cmd(portwidth,caddr,0,0xf0);
+ flash_cmd(portwidth,caddr,0,0xf0);
+
+ udelay(10);
+
+ if(*caddr==0xf0) {
+ /* this area is ROM */
+ *caddr=save;
+#ifndef FLASH_ID_OVERRIDE
+ info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
+ info->sector_count = 8;
+ info->size = 0x80000;
+#else
+ info->flash_id = FLASH_MAN_AMD + FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x80000;
+ info->chipwidth=1;
+#endif
+ flash_get_offsets(base, info);
+ return info->size;
+ }
+ } else {
+ *caddr=0;
+
+ udelay(10);
+
+ if(*caddr==0) {
+ /* this area is RAM */
+ *caddr=save;
+ info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN;
+ info->sector_count = 8;
+ info->size = 0x80000;
+ flash_get_offsets(base, info);
+ return info->size;
+ }
+ flash_cmd(portwidth,caddr,0,0xf0);
+
+ udelay(10);
+ }
+
+ /* Write auto select command: read Manufacturer ID */
+ flash_cmd(portwidth,caddr,0x555,0xAA);
+ flash_cmd(portwidth,caddr,0x2AA,0x55);
+ flash_cmd(portwidth,caddr,0x555,0x90);
+
+ udelay(10);
+
+ if ((caddr[0] == old[0]) &&
+ (caddr[1] == old[1])) {
+
+ /* this area is ROM */
+#ifndef FLASH_ID_OVERRIDE
+ info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
+ info->sector_count = 8;
+ info->size = 0x80000;
+#else
+ info->flash_id = FLASH_MAN_AMD + FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x80000;
+ info->chipwidth=1;
+#endif
+ flash_get_offsets(base, info);
+ return info->size;
+#ifdef DEBUG
+ } else {
+ printf("%px%d: %02x:%02x -> %02x:%02x\n",
+ caddr, portwidth, old[0], old[1],
+ caddr[0], caddr[1]);
+#endif
+ }
+
+ switch(portwidth) {
+ case 1:
+ manu = caddr[0];
+ manu |= manu<<16;
+ id = caddr[1];
+ break;
+ case 2:
+ manu = saddr[0];
+ manu |= manu<<16;
+ id = saddr[1];
+ id |= id<<16;
+ break;
+ case 4:
+ manu = laddr[0];
+ id = laddr[1];
+ break;
+ default:
+ id = manu = -1;
+ break;
+ }
+
+#ifdef DEBUG
+ printf("\n%08lx:%08lx:%08lx\n", base, manu, id);
+ printf("%08lx %08lx %08lx %08lx\n",
+ laddr[0],laddr[1],laddr[2],laddr[3]);
+#endif
+
+ switch (manu) {
+ case AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ printf("Unknown Mfr [%08lx]:%08lx\n", manu, id);
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ switch (id) {
+ case AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00100000;
+ info->chipwidth=1;
+ break; /* => 1 MB */
+
+ case AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00100000;
+ info->chipwidth=1;
+ break; /* => 1 MB */
+
+ case AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ info->chipwidth=1;
+ break; /* => 2 MB */
+
+ case AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00200000;
+ info->chipwidth=1;
+ break; /* => 2 MB */
+
+ case AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00400000;
+ info->chipwidth=1;
+ break; /* => 4 MB */
+
+ case AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00400000;
+ info->chipwidth=1;
+ break; /* => 4 MB */
+#if 0 /* enable when device IDs are available */
+ case AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 67;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+
+ case AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 67;
+ info->size = 0x00800000;
+ break; /* => 8 MB */
+#endif
+ case AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x80000;
+ info->chipwidth=1;
+ break;
+
+ case INTEL_ID_28F640J3A:
+ info->flash_id += FLASH_28F640J3A;
+ info->sector_count = 64;
+ info->size = 128*1024 * 64; /* 128kbytes x 64 blocks */
+ info->chipwidth=2;
+ if(portwidth==4) info->size*=2; /* 2x16 */
+ break;
+
+ case INTEL_ID_28F128J3A:
+ info->flash_id += FLASH_28F128J3A;
+ info->sector_count = 128;
+ info->size = 128*1024 * 128; /* 128kbytes x 128 blocks */
+ info->chipwidth=2;
+ if(portwidth==4) info->size*=2; /* 2x16 */
+ break;
+
+ default:
+ printf("Unknown id %lx:[%lx]\n", manu, id);
+ info->flash_id = FLASH_UNKNOWN;
+ info->chipwidth=1;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ flash_get_offsets(base, info);
+
+#if 0
+ /* set up sector start address table */
+ if (info->flash_id & FLASH_AM040) {
+ /* this chip has uniformly spaced sectors */
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+
+ } else if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00008000;
+ info->start[2] = base + 0x0000C000;
+ info->start[3] = base + 0x00010000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000) - 0x00060000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000C000;
+ info->start[i--] = base + info->size - 0x00010000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00020000;
+ }
+ }
+#endif
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0)=0x02 */
+ /* D0 = 1 if protected */
+ caddr = (volatile unsigned char *)(info->start[i]);
+ saddr = (volatile unsigned short *)(info->start[i]);
+ laddr = (volatile unsigned long *)(info->start[i]);
+ if(portwidth==1)
+ info->protect[i] = caddr[2] & 1;
+ else if(portwidth==2)
+ info->protect[i] = saddr[2] & 1;
+ else
+ info->protect[i] = laddr[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ caddr = (volatile unsigned char *)info->start[0];
+
+ flash_cmd(portwidth,caddr,0,0xF0); /* reset bank */
+ }
+
+ return (info->size);
+}
+
+/* TODO: 2x16 unsupported */
+int
+flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ volatile unsigned char *addr = (uchar *)(info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ /* TODO: 2x16 unsupported */
+ if(info->portwidth==4) return 1;
+
+ if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1;
+ if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
+ for (sect = s_first; sect<=s_last; sect++) {
+ int sector_size=info->size/info->sector_count;
+ addr = (uchar *)(info->start[sect]);
+ memset((void *)addr, 0, sector_size);
+ }
+ return 0;
+ }
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ((info->flash_id&FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ return flash_erase_intel(info,
+ (unsigned short)s_first,
+ (unsigned short)s_last);
+ }
+
+#if 0
+ if ((info->flash_id == FLASH_UNKNOWN) ||
+ (info->flash_id > FLASH_AMD_COMP)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+#endif
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ flash_cmd(info->portwidth,addr,0x555,0xAA);
+ flash_cmd(info->portwidth,addr,0x2AA,0x55);
+ flash_cmd(info->portwidth,addr,0x555,0x80);
+ flash_cmd(info->portwidth,addr,0x555,0xAA);
+ flash_cmd(info->portwidth,addr,0x2AA,0x55);
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (uchar *)(info->start[sect]);
+ flash_cmd(info->portwidth,addr,0,0x30);
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (volatile unsigned char *)(info->start[l_sect]);
+ /* broken for 2x16: TODO */
+ while ((addr[0] & 0x80) != 0x80) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+DONE:
+ /* reset to read mode */
+ addr = (volatile unsigned char *)info->start[0];
+ flash_cmd(info->portwidth,addr,0,0xf0);
+ flash_cmd(info->portwidth,addr,0,0xf0);
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+/* broken for 2x16: TODO */
+int
+write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ if(info->portwidth==4) return 1;
+
+ if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 0;
+ if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
+ memcpy((void *)addr, src, cnt);
+ return 0;
+ }
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+/* broken for 2x16: TODO */
+static int
+write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ volatile unsigned char *addr = (uchar *)(info->start[0]);
+ ulong start;
+ int flag, i;
+
+ if(info->portwidth==4) return 1;
+
+ if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1;
+ if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
+ *(unsigned long *)dest=data;
+ return 0;
+ }
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ unsigned short low = data & 0xffff;
+ unsigned short hi = (data >> 16) & 0xffff;
+ int ret = write_word_intel((bank_addr_t)dest, hi);
+
+ if (!ret) ret = write_word_intel((bank_addr_t)(dest+2), low);
+
+ return ret;
+ }
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* first, perform an unlock bypass command to speed up flash writes */
+ addr[0x555] = 0xAA;
+ addr[0x2AA] = 0x55;
+ addr[0x555] = 0x20;
+
+ /* write each byte out */
+ for (i = 0; i < 4; i++) {
+ char *data_ch = (char *)&data;
+ addr[0] = 0xA0;
+ *(((char *)dest)+i) = data_ch[i];
+ udelay(10); /* XXX */
+ }
+
+ /* we're done, now do an unlock bypass reset */
+ addr[0] = 0x90;
+ addr[0] = 0x00;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ return (0);
+}
diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c
new file mode 100644
index 0000000..8119fce
--- /dev/null
+++ b/board/evb64260/i2c.c
@@ -0,0 +1,310 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <malloc.h>
+#include <galileo/gt64260R.h>
+#include <galileo/core.h>
+
+#define MAX_I2C_RETRYS 10
+#define I2C_DELAY 1000 /* Should be at least the # of MHz of Tclk */
+#undef DEBUG_I2C
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+static void
+i2c_init(int speed, int slaveaddr)
+{
+ unsigned int n, m, freq, margin, power;
+ unsigned int actualn = 0, actualm = 0;
+ unsigned int control, status;
+ unsigned int minmargin = 0xffffffff;
+ unsigned int tclk = 125000000;
+
+ DP(puts("i2c_init\n"));
+
+ for (n = 0 ; n < 8 ; n++) {
+ for (m = 0 ; m < 16 ; m++) {
+ power = 2 << n; /* power = 2^(n+1) */
+ freq = tclk / (10 * (m + 1) * power);
+ if (speed > freq)
+ margin = speed - freq;
+ else
+ margin = freq - speed;
+ if (margin < minmargin) {
+ minmargin = margin;
+ actualn = n;
+ actualm = m;
+ }
+ }
+ }
+
+ DP(puts("setup i2c bus\n"));
+
+ /* Setup bus */
+
+ GT_REG_WRITE(I2C_SOFT_RESET, 0);
+
+ DP(puts("udelay...\n"));
+
+ udelay(I2C_DELAY);
+
+ DP(puts("set baudrate\n"));
+
+ GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualm << 3) | actualn);
+ GT_REG_WRITE(I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
+
+ udelay(I2C_DELAY * 10);
+
+ DP(puts("read control, baudrate\n"));
+
+ GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+ GT_REG_READ(I2C_CONTROL, &control);
+}
+
+static uchar
+i2c_start(void)
+{
+ unsigned int control, status;
+ int count = 0;
+
+ DP(puts("i2c_start\n"));
+
+ /* Set the start bit */
+
+ GT_REG_READ(I2C_CONTROL, &control);
+ control |= (0x1 << 5);
+ GT_REG_WRITE(I2C_CONTROL, control);
+
+ GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+
+ count = 0;
+ while ((status & 0xff) != 0x08) {
+ udelay(I2C_DELAY);
+ if (count > 20) {
+ GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+ return status;
+ }
+ GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+ count++;
+ }
+
+ return 0;
+}
+
+static uchar
+i2c_select_device(uchar dev_addr, uchar read, int ten_bit)
+{
+ unsigned int status, data, bits = 7;
+ int count = 0;
+
+ DP(puts("i2c_select_device\n"));
+
+ /* Output slave address */
+
+ if (ten_bit)
+ bits = 10;
+
+ data = (dev_addr << 1);
+ /* set the read bit */
+ data |= read;
+ GT_REG_WRITE(I2C_DATA, data);
+ /* assert the address */
+ RESET_REG_BITS(I2C_CONTROL, BIT3);
+
+ udelay(I2C_DELAY);
+
+ GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+ count = 0;
+ while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
+ udelay(I2C_DELAY);
+ if (count > 20) {
+ GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+ return status;
+ }
+ GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+ count++;
+ }
+
+ if (bits == 10) {
+ printf("10 bit I2C addressing not yet implemented\n");
+ return 0xff;
+ }
+
+ return 0;
+}
+
+static uchar
+i2c_get_data(uchar *return_data, int len) {
+
+ unsigned int data, status = 0;
+ int count = 0;
+
+ DP(puts("i2c_get_data\n"));
+
+ while (len) {
+
+ /* Get and return the data */
+
+ RESET_REG_BITS(I2C_CONTROL, (0x1 << 3));
+
+ udelay(I2C_DELAY * 5);
+
+ GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+ count++;
+ while ((status & 0xff) != 0x50) {
+ udelay(I2C_DELAY);
+ if (count > 2) {
+ GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+ return 0;
+ }
+ GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+ count++;
+ }
+ GT_REG_READ(I2C_DATA, &data);
+ len--;
+ *return_data = (uchar)data;
+ return_data++;
+ }
+ RESET_REG_BITS(I2C_CONTROL, BIT2|BIT3);
+ while ((status & 0xff) != 0x58) {
+ udelay(I2C_DELAY);
+ if (count > 200) {
+ GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+ return status;
+ }
+ GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+ count++;
+ }
+ GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /* stop */
+
+ return 0;
+}
+
+static uchar
+i2c_write_data(unsigned int data, int len)
+{
+ unsigned int status;
+ int count = 0;
+
+ DP(puts("i2c_write_data\n"));
+
+ if (len > 4)
+ return -1;
+
+ while (len) {
+ /* Set and assert the data */
+
+ GT_REG_WRITE(I2C_DATA, (unsigned int)data);
+ RESET_REG_BITS(I2C_CONTROL, (0x1 << 3));
+
+ udelay(I2C_DELAY);
+
+ GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+ count++;
+ while ((status & 0xff) != 0x28) {
+ udelay(I2C_DELAY);
+ if (count > 20) {
+ GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+ return status;
+ }
+ GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+ count++;
+ }
+ len--;
+ }
+ GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4));
+ GT_REG_WRITE(I2C_CONTROL, (0x1 << 4));
+
+ udelay(I2C_DELAY * 10);
+
+ return 0;
+}
+
+static uchar
+i2c_set_dev_offset(uchar dev_addr, unsigned int offset, int ten_bit)
+{
+ uchar status;
+
+ DP(puts("i2c_set_dev_offset\n"));
+
+ status = i2c_select_device(dev_addr, 0, ten_bit);
+ if (status) {
+#ifdef DEBUG_I2C
+ printf("Failed to select device setting offset: 0x%02x\n",
+ status);
+#endif
+ return status;
+ }
+
+ status = i2c_write_data(offset, 1);
+ if (status) {
+#ifdef DEBUG_I2C
+ printf("Failed to write data: 0x%02x\n", status);
+#endif
+ return status;
+ }
+
+ return 0;
+}
+
+uchar
+i2c_read(uchar dev_addr, unsigned int offset, int len, uchar *data,
+ int ten_bit)
+{
+ uchar status = 0;
+ unsigned int i2cfreq = 400000;
+
+ DP(puts("i2c_read\n"));
+
+ i2c_init(i2cfreq, 0);
+
+ status = i2c_start();
+
+ if (status) {
+#ifdef DEBUG_I2C
+ printf("Transaction start failed: 0x%02x\n", status);
+#endif
+ return status;
+ }
+
+ status = i2c_set_dev_offset(dev_addr, 0, 0);
+ if (status) {
+#ifdef DEBUG_I2C
+ printf("Failed to set offset: 0x%02x\n", status);
+#endif
+ return status;
+ }
+
+ i2c_init(i2cfreq, 0);
+
+ status = i2c_start();
+ if (status) {
+#ifdef DEBUG_I2C
+ printf("Transaction restart failed: 0x%02x\n", status);
+#endif
+ return status;
+ }
+
+ status = i2c_select_device(dev_addr, 1, ten_bit);
+ if (status) {
+#ifdef DEBUG_I2C
+ printf("Address not acknowledged: 0x%02x\n", status);
+#endif
+ return status;
+ }
+
+ status = i2c_get_data(data, len);
+ if (status) {
+#ifdef DEBUG_I2C
+ printf("Data not received: 0x%02x\n", status);
+#endif
+ return status;
+ }
+
+ return 0;
+}
diff --git a/board/evb64260/i2c.h b/board/evb64260/i2c.h
new file mode 100644
index 0000000..9c21992
--- /dev/null
+++ b/board/evb64260/i2c.h
@@ -0,0 +1,7 @@
+#ifndef __I2C_H__
+#define __I2C_H__
+
+/* function declarations */
+uchar i2c_read(uchar, unsigned int, int, uchar*, int);
+
+#endif
diff --git a/board/evb64260/intel_flash.c b/board/evb64260/intel_flash.c
new file mode 100644
index 0000000..9acc3a0
--- /dev/null
+++ b/board/evb64260/intel_flash.c
@@ -0,0 +1,260 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ * Hacked for the Hymod board by Murray.Jensen@cmst.csiro.au, 20-Oct-00
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <galileo/gt64260R.h>
+#include <galileo/memory.h>
+#include "intel_flash.h"
+
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET 0x01
+#define FLAG_PROTECT_CLEAR 0x02
+
+static void
+bank_reset(flash_info_t *info, int sect)
+{
+ bank_addr_t addrw, eaddrw;
+
+ addrw = (bank_addr_t)info->start[sect];
+ eaddrw = BANK_ADDR_NEXT_WORD(addrw);
+
+ while (addrw < eaddrw) {
+#ifdef FLASH_DEBUG
+ printf(" writing reset cmd to addr 0x%08lx\n",
+ (unsigned long)addrw);
+#endif
+ *addrw = BANK_CMD_RST;
+ addrw++;
+ }
+}
+
+static void
+bank_erase_init(flash_info_t *info, int sect)
+{
+ bank_addr_t addrw, saddrw, eaddrw;
+ int flag;
+
+#ifdef FLASH_DEBUG
+ printf("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG);
+ printf("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1);
+ printf("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2);
+ printf("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT);
+ printf("0x%08x BANK_CMD_RST\n", BANK_CMD_RST);
+ printf("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY);
+ printf("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR);
+#endif
+
+ saddrw = (bank_addr_t)info->start[sect];
+ eaddrw = BANK_ADDR_NEXT_WORD(saddrw);
+
+#ifdef FLASH_DEBUG
+ printf("erasing sector %d, start addr = 0x%08lx "
+ "(bank next word addr = 0x%08lx)\n", sect,
+ (unsigned long)saddrw, (unsigned long)eaddrw);
+#endif
+
+ /* Disable intrs which might cause a timeout here */
+ flag = disable_interrupts();
+
+ for (addrw = saddrw; addrw < eaddrw; addrw++) {
+#ifdef FLASH_DEBUG
+ printf(" writing erase cmd to addr 0x%08lx\n",
+ (unsigned long)addrw);
+#endif
+ *addrw = BANK_CMD_ERASE1;
+ *addrw = BANK_CMD_ERASE2;
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+}
+
+static int
+bank_erase_poll(flash_info_t *info, int sect)
+{
+ bank_addr_t addrw, saddrw, eaddrw;
+ int sectdone, haderr;
+
+ saddrw = (bank_addr_t)info->start[sect];
+ eaddrw = BANK_ADDR_NEXT_WORD(saddrw);
+
+ sectdone = 1;
+ haderr = 0;
+
+ for (addrw = saddrw; addrw < eaddrw; addrw++) {
+ bank_word_t stat = *addrw;
+
+#ifdef FLASH_DEBUG
+ printf(" checking status at addr "
+ "0x%08x [0x%08x]\n",
+ (unsigned long)addrw, stat);
+#endif
+ if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY)
+ sectdone = 0;
+ else if ((stat & BANK_STAT_ERR) != 0) {
+ printf(" failed on sector %d "
+ "(stat = 0x%08x) at "
+ "address 0x%p\n",
+ sect, stat, addrw);
+ *addrw = BANK_CMD_CLR_STAT;
+ haderr = 1;
+ }
+ }
+
+ if (haderr)
+ return (-1);
+ else
+ return (sectdone);
+}
+
+int
+write_word_intel(bank_addr_t addr, bank_word_t value)
+{
+ bank_word_t stat;
+ ulong start;
+ int flag, retval;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ *addr = BANK_CMD_PROG;
+
+ *addr = value;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ retval = 0;
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ do {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ retval = 1;
+ goto done;
+ }
+ stat = *addr;
+ } while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
+
+ if ((stat & BANK_STAT_ERR) != 0) {
+ printf("flash program failed (stat = 0x%08lx) "
+ "at address 0x%08lx\n", (ulong)stat, (ulong)addr);
+ *addr = BANK_CMD_CLR_STAT;
+ retval = 3;
+ }
+
+done:
+ /* reset to read mode */
+ *addr = BANK_CMD_RST;
+
+ return (retval);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase_intel(flash_info_t *info, int s_first, int s_last)
+{
+ int prot, sect, haderr;
+ ulong start, now, last;
+
+#ifdef FLASH_DEBUG
+ printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
+ " Bank # %d: ", s_last - s_first + 1, s_first, s_last,
+ (info - flash_info) + 1);
+ flash_print_info(info);
+#endif
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sector%s will not be erased!\n",
+ prot, (prot > 1 ? "s" : ""));
+ }
+
+ start = get_timer (0);
+ last = 0;
+ haderr = 0;
+
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ ulong estart;
+ int sectdone;
+
+ bank_erase_init(info, sect);
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ estart = get_timer(start);
+
+ do {
+ now = get_timer(start);
+
+ if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout (sect %d)\n", sect);
+ haderr = 1;
+ break;
+ }
+
+#ifndef FLASH_DEBUG
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+#endif
+
+ sectdone = bank_erase_poll(info, sect);
+
+ if (sectdone < 0) {
+ haderr = 1;
+ break;
+ }
+
+ } while (!sectdone);
+
+ if (haderr)
+ break;
+ }
+ }
+
+ if (haderr > 0)
+ printf (" failed\n");
+ else
+ printf (" done\n");
+
+ /* reset to read mode */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ bank_reset(info, sect);
+ }
+ }
+ return haderr;
+}
diff --git a/board/evb64260/intel_flash.h b/board/evb64260/intel_flash.h
new file mode 100644
index 0000000..cc3a339
--- /dev/null
+++ b/board/evb64260/intel_flash.h
@@ -0,0 +1,160 @@
+/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
+
+/*
+ * acceptable chips types are:
+ *
+ * 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
+ */
+
+/* register addresses, valid only following an CHIP_CMD_RD_ID command */
+#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */
+#define CHIP_ADDR_REG_DEV 0x000001 /* device id */
+#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */
+#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */
+
+/* Commands */
+#define CHIP_CMD_RST 0xFF /* reset flash */
+#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */
+#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */
+#define CHIP_CMD_RD_STAT 0x70 /* read the status register */
+#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */
+#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */
+#define CHIP_CMD_PROG 0x40 /* program word command */
+#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */
+#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */
+#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */
+#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */
+#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */
+#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */
+#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */
+
+/* status register bits */
+#define CHIP_STAT_DPS 0x02 /* Device Protect Status */
+#define CHIP_STAT_VPPS 0x08 /* VPP Status */
+#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */
+#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */
+#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */
+#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */
+
+#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \
+ CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
+
+/* ID and Lock Configuration */
+#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */
+#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */
+#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID
+
+/* dimensions */
+#define CHIP_WIDTH 2 /* chips are in 16 bit mode */
+#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */
+#define CHIP_NBLOCKS 128
+#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */
+#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS)
+
+/********************** DEFINES for Hymod Flash ******************************/
+
+/*
+ * The hymod board has 2 x 28F320J5 chips running in
+ * 16 bit mode, for a 32 bit wide bank.
+ */
+
+typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */
+typedef volatile bank_word_t *bank_addr_t;
+typedef unsigned long bank_size_t; /* want this big - >= 32 bit */
+
+#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */
+#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */
+
+#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH)
+#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT)
+#define BANK_NBLOCKS CHIP_NBLOCKS
+#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH)
+#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH)
+
+#define MAX_BANKS 1 /* only one bank possible */
+
+/* align bank addresses and sizes to bank word boundaries */
+#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
+ & ~(BANK_WIDTH - 1)))
+#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \
+ (bank_size_t)(s) + (BANK_WIDTH - 1)))
+
+/* align bank addresses and sizes to bank block boundaries */
+#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
+ & ~(BANK_BLKSZ - 1)))
+#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \
+ (bank_size_t)(s) + (BANK_BLKSZ - 1)))
+
+/* align bank addresses and sizes to bank boundaries */
+#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \
+ & ~(BANK_SIZE - 1)))
+#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \
+ (bank_size_t)(s) + (BANK_SIZE - 1)))
+
+/* add an offset to a bank address */
+#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \
+ (bank_size_t)(o))
+
+/* get base address of bank b, given flash base address a */
+#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+ (bank_size_t)(b) * BANK_SIZE)
+
+/* adjust a bank address to start of next word, block or bank */
+#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
+ BANK_WIDTH)
+#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
+ BANK_BLKSZ)
+#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+ BANK_SIZE)
+
+/* get bank address of chip register r given a bank base address a */
+#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+ ((bank_size_t)(r) << BANK_WSHIFT))
+
+/* make a bank address for each chip register address */
+
+#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
+#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
+#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
+#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
+
+/*
+ * replicate a chip cmd/stat/rd value into each byte position within a word
+ * so that multiple chips are accessed in a single word i/o operation
+ *
+ * this must be as wide as the bank_word_t type, and take into account the
+ * chip width and bank layout
+ */
+
+#define BANK_FILL_WORD(o) ((bank_word_t)(o))
+
+/* make a bank word value for each chip cmd/stat/rd value */
+
+/* Commands */
+#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST)
+#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID)
+#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT)
+#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
+#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1)
+#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2)
+#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG)
+#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK)
+#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
+#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
+#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS)
+#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS)
+#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS)
+#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS)
+#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS)
+#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS)
+#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY)
+
+#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR)
+
+/* ID and Lock Configuration */
+#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK)
+#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN)
+#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV)
diff --git a/board/evb64260/local.h b/board/evb64260/local.h
new file mode 100644
index 0000000..8a3f4b2
--- /dev/null
+++ b/board/evb64260/local.h
@@ -0,0 +1,62 @@
+/*
+ * include/local.h - local configuration options, board specific
+ */
+
+#ifndef __LOCAL_H
+#define __LOCAL_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* This tells U-Boot that the config options are compiled in */
+/* #undef ENV_IS_EMBEDDED */
+/* Don't touch this! U-Boot figures this out based on other
+ * magic. */
+
+/* Uncomment and define any of the below options */
+
+/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */
+ /* Note: If you defined CONFIG_EVB64260_750CX this */
+ /* gets defined automatically. */
+
+/* These want string arguments */
+/* #define CONFIG_BOOTARGS */
+/* #define CONFIG_BOOTCOMMAND */
+/* #define CONFIG_RAMBOOTCOMMAND */
+/* #define CONFIG_NFSBOOTCOMMAND */
+/* #define CONFIG_SYS_AUTOLOAD */
+/* #define CONFIG_PREBOOT */
+
+/* These don't */
+
+/* #define CONFIG_BOOTDELAY */
+/* #define CONFIG_BAUDRATE */
+/* #define CONFIG_LOADS_ECHO */
+/* #define CONFIG_ETHADDR */
+/* #define CONFIG_ETH2ADDR */
+/* #define CONFIG_ETH3ADDR */
+/* #define CONFIG_IPADDR */
+/* #define CONFIG_SERVERIP */
+/* #define CONFIG_ROOTPATH */
+/* #define CONFIG_GATEWAYIP */
+/* #define CONFIG_NETMASK */
+/* #define CONFIG_HOSTNAME */
+/* #define CONFIG_BOOTFILE */
+/* #define CONFIG_LOADADDR */
+
+/* these hardware addresses are pretty bogus, please change them to
+ suit your needs */
+
+/* first ethernet */
+#define CONFIG_ETHADDR 00:11:22:33:44:55
+
+/* next two ethernet hwaddrs */
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:11:22:33:44:66
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR 00:11:22:33:44:77
+
+#define CONFIG_ENV_OVERWRITE
+#endif /* __CONFIG_H */
diff --git a/board/evb64260/memory.c b/board/evb64260/memory.c
new file mode 100644
index 0000000..e339854
--- /dev/null
+++ b/board/evb64260/memory.c
@@ -0,0 +1,457 @@
+/* Memory.c - Memory mappings and remapping functions */
+
+/* Copyright - Galileo technology. */
+
+/* modified by Josh Huber to clean some things up, and
+ * fit it into the U-Boot framework */
+
+#include <galileo/core.h>
+#include <galileo/memory.h>
+
+/********************************************************************
+* memoryGetBankBaseAddress - Gets the base address of a memory bank
+* - If the memory bank size is 0 then this base address has no meaning!!!
+*
+*
+* INPUTS: MEMORY_BANK bank - The bank we ask for its base Address.
+* OUTPUT: N/A
+* RETURNS: Memory bank base address.
+*********************************************************************/
+static unsigned long memoryGetBankRegOffset(MEMORY_BANK bank)
+{
+ switch (bank)
+ {
+ case BANK0:
+ return SCS_0_LOW_DECODE_ADDRESS;
+ case BANK1:
+ return SCS_1_LOW_DECODE_ADDRESS;
+ case BANK2:
+ return SCS_2_LOW_DECODE_ADDRESS;
+ case BANK3:
+ return SCS_3_LOW_DECODE_ADDRESS;
+ }
+ return SCS_0_LOW_DECODE_ADDRESS; /* default value */
+}
+
+unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank)
+{
+ unsigned int base;
+ unsigned int regOffset=memoryGetBankRegOffset(bank);
+
+ GT_REG_READ(regOffset,&base);
+ base = base << 20;
+ return base;
+}
+
+/********************************************************************
+* memoryGetDeviceBaseAddress - Gets the base address of a device.
+* - If the device size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT: DEVICE device - The device we ask for its base address.
+* OUTPUT: N/A
+* RETURNS: Device base address.
+*********************************************************************/
+static unsigned int memoryGetDeviceRegOffset(DEVICE device)
+{
+ switch (device)
+ {
+ case DEVICE0:
+ return CS_0_LOW_DECODE_ADDRESS;
+ case DEVICE1:
+ return CS_1_LOW_DECODE_ADDRESS;
+ case DEVICE2:
+ return CS_2_LOW_DECODE_ADDRESS;
+ case DEVICE3:
+ return CS_3_LOW_DECODE_ADDRESS;
+ case BOOT_DEVICE:
+ return BOOTCS_LOW_DECODE_ADDRESS;
+ }
+ return CS_0_LOW_DECODE_ADDRESS; /* default value */
+}
+
+unsigned int memoryGetDeviceBaseAddress(DEVICE device)
+{
+ unsigned int regBase;
+ unsigned int regEnd;
+ unsigned int regOffset=memoryGetDeviceRegOffset(device);
+
+ GT_REG_READ(regOffset, ®Base);
+ GT_REG_READ(regOffset+8, ®End);
+
+ if(regEnd<=regBase) return 0xffffffff; /* ERROR !!! */
+
+ regBase = regBase << 20;
+ return regBase;
+}
+
+/********************************************************************
+* memoryGetBankSize - Returns the size of a memory bank.
+*
+*
+* INPUT: MEMORY_BANK bank - The bank we ask for its size.
+* OUTPUT: N/A
+* RETURNS: Memory bank size.
+*********************************************************************/
+unsigned int memoryGetBankSize(MEMORY_BANK bank)
+{
+ unsigned int size,base;
+ unsigned int highValue;
+ unsigned int highAddress=memoryGetBankRegOffset(bank)+8;
+
+ base = memoryGetBankBaseAddress(bank);
+ GT_REG_READ(highAddress,&highValue);
+ highValue = (highValue + 1) << 20;
+ if(base > highValue)
+ size=0;
+ else
+ size = highValue - base;
+ return size;
+}
+
+/********************************************************************
+* memoryGetDeviceSize - Returns the size of a device memory space
+*
+*
+* INPUT: DEVICE device - The device we ask for its base address.
+* OUTPUT: N/A
+* RETURNS: Size of a device memory space.
+*********************************************************************/
+unsigned int memoryGetDeviceSize(DEVICE device)
+{
+ unsigned int size,base;
+ unsigned int highValue;
+ unsigned int highAddress=memoryGetDeviceRegOffset(device)+8;
+
+ base = memoryGetDeviceBaseAddress(device);
+ GT_REG_READ(highAddress,&highValue);
+ if (highValue == 0xfff)
+ {
+ size = (~base) + 1; /* what the heck is this? */
+ return size;
+ }
+ else
+ highValue = (highValue + 1) << 20;
+
+ if(base > highValue)
+ size=0;
+ else
+ size = highValue - base;
+ return size;
+}
+
+/********************************************************************
+* memoryGetDeviceWidth - A device can be with: 1,2,4 or 8 Bytes data width.
+* The width is determine in registers: 'Device Parameters'
+* registers (0x45c, 0x460, 0x464, 0x468, 0x46c - for each device.
+* at bits: [21:20].
+*
+* INPUT: DEVICE device - Device number
+* OUTPUT: N/A
+* RETURNS: Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
+*********************************************************************/
+unsigned int memoryGetDeviceWidth(DEVICE device)
+{
+ unsigned int width;
+ unsigned int regValue;
+
+ GT_REG_READ(DEVICE_BANK0PARAMETERS + device*4,®Value);
+ width = (regValue & 0x00300000) >> 20;
+ switch (width)
+ {
+ case 0:
+ return 1;
+ case 1:
+ return 2;
+ case 2:
+ return 4;
+ case 3:
+ return 8;
+ default:
+ return 0;
+ }
+}
+
+bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength)
+{
+ unsigned int low=0xfff;
+ unsigned int high=0x0;
+ unsigned int regOffset=memoryGetBankRegOffset(bank);
+
+ if(bankLength!=0) {
+ low = (bankBase >> 20) & 0xffff;
+ high=((bankBase+bankLength)>>20)-1;
+ }
+
+#ifdef DEBUG
+ {
+ unsigned int oldLow, oldHigh;
+ GT_REG_READ(regOffset,&oldLow);
+ GT_REG_READ(regOffset+8,&oldHigh);
+
+ printf("b%d %x-%x->%x-%x\n", bank, oldLow, oldHigh, low, high);
+ }
+#endif
+
+ GT_REG_WRITE(regOffset,low);
+ GT_REG_WRITE(regOffset+8,high);
+
+ return true;
+}
+bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength)
+{
+ /* TODO: what are appropriate "unmapped" values? */
+ unsigned int low=0xfff;
+ unsigned int high=0x0;
+ unsigned int regOffset=memoryGetDeviceRegOffset(device);
+
+ if(deviceLength != 0) {
+ low=deviceBase>>20;
+ high=((deviceBase+deviceLength)>>20)-1;
+ } else {
+ /* big problems in here... */
+ /* this will HANG */
+ }
+
+ GT_REG_WRITE(regOffset,low);
+ GT_REG_WRITE(regOffset+8,high);
+
+ return true;
+}
+
+
+/********************************************************************
+* memoryMapInternalRegistersSpace - Sets new base address for the internals
+* registers.
+*
+* INPUTS: unsigned int internalRegBase - The new base address.
+* RETURNS: true on success, false on failure
+*********************************************************************/
+bool memoryMapInternalRegistersSpace(unsigned int internalRegBase)
+{
+ unsigned int currentValue;
+ unsigned int internalValue = internalRegBase;
+
+ internalRegBase = (internalRegBase >> 20);
+ GT_REG_READ(INTERNAL_SPACE_DECODE,¤tValue);
+ internalRegBase = (currentValue & 0xffff0000) | internalRegBase;
+ GT_REG_WRITE(INTERNAL_SPACE_DECODE,internalRegBase);
+ INTERNAL_REG_BASE_ADDR = internalValue;
+ return true;
+}
+
+/********************************************************************
+* memoryGetInternalRegistersSpace - Gets internal registers Base Address.
+*
+* INPUTS: unsigned int internalRegBase - The new base address.
+* RETURNS: true on success, false on failure
+*********************************************************************/
+unsigned int memoryGetInternalRegistersSpace(void)
+{
+ return INTERNAL_REG_BASE_ADDR;
+}
+
+/********************************************************************
+* memorySetProtectRegion - This function modifys one of the 8 regions with
+* one of the three protection mode.
+* - Be advised to check the spec before modifying them.
+*
+*
+* Inputs: CPU_PROTECT_REGION - one of the eight regions.
+* CPU_ACCESS - general access.
+* CPU_WRITE - read only access.
+* CPU_CACHE_PROTECT - chache access.
+* we defining CPU because there is another protect from the pci SIDE.
+* Returns: false if one of the parameters is wrong and true else
+*********************************************************************/
+bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
+ MEMORY_ACCESS memAccess,
+ MEMORY_ACCESS_WRITE memWrite,
+ MEMORY_CACHE_PROTECT cacheProtection,
+ unsigned int baseAddress,
+ unsigned int regionLength)
+{
+ unsigned int protectHigh = baseAddress + regionLength;
+
+ if(regionLength == 0) /* closing the region */
+ {
+ GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,0x0000ffff);
+ GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,0);
+ return true;
+ }
+ baseAddress = (baseAddress & 0xfff00000) >> 20;
+ baseAddress = baseAddress | memAccess << 16 | memWrite << 17
+ | cacheProtection << 18;
+ GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,baseAddress);
+ protectHigh = (protectHigh & 0xfff00000) >> 20;
+ GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,protectHigh - 1);
+ return true;
+}
+
+/********************************************************************
+* memorySetRegionSnoopMode - This function modifys one of the 4 regions which
+* supports Cache Coherency.
+*
+*
+* Inputs: SNOOP_REGION region - One of the four regions.
+* SNOOP_TYPE snoopType - There is four optional Types:
+* 1. No Snoop.
+* 2. Snoop to WT region.
+* 3. Snoop to WB region.
+* 4. Snoop & Invalidate to WB region.
+* unsigned int baseAddress - Base Address of this region.
+* unsigned int topAddress - Top Address of this region.
+* Returns: false if one of the parameters is wrong and true else
+*********************************************************************/
+bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
+ MEMORY_SNOOP_TYPE snoopType,
+ unsigned int baseAddress,
+ unsigned int regionLength)
+{
+ unsigned int snoopXbaseAddress;
+ unsigned int snoopXtopAddress;
+ unsigned int data;
+ unsigned int snoopHigh = baseAddress + regionLength;
+
+ if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
+ return false;
+ snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
+ snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
+ if(regionLength == 0) /* closing the region */
+ {
+ GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
+ GT_REG_WRITE(snoopXtopAddress,0);
+ return true;
+ }
+ baseAddress = baseAddress & 0xffff0000;
+ data = (baseAddress >> 16) | snoopType << 16;
+ GT_REG_WRITE(snoopXbaseAddress,data);
+ snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+ GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
+ return true;
+}
+
+/********************************************************************
+* memoryRemapAddress - This fubction used for address remapping.
+*
+*
+* Inputs: regOffset: remap register
+* remapValue :
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue)
+{
+ unsigned int valueForReg;
+ valueForReg = (remapValue & 0xfff00000) >> 20;
+ GT_REG_WRITE(remapReg, valueForReg);
+ return true;
+}
+
+/********************************************************************
+* memoryGetDeviceParam - This function used for getting device parameters from
+* DEVICE BANK PARAMETERS REGISTER
+*
+*
+* Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK
+* PARAMETERS REGISTER
+* - deviceNum : number of device
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum)
+{
+ unsigned int valueOfReg;
+ unsigned int calcData;
+
+ GT_REG_READ(DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
+ calcData = (0x7 & valueOfReg) + ((0x400000 & valueOfReg) >> 19);
+ deviceParam -> turnOff = calcData; /* Turn Off */
+
+ calcData = ((0x78 & valueOfReg) >> 3) + ((0x800000 & valueOfReg) >> 19);
+ deviceParam -> acc2First = calcData; /* Access To First */
+
+ calcData = ((0x780 & valueOfReg) >> 7) + ((0x1000000 & valueOfReg) >> 20);
+ deviceParam -> acc2Next = calcData; /* Access To Next */
+
+ calcData = ((0x3800 & valueOfReg) >> 11) + ((0x2000000 & valueOfReg) >> 22);
+ deviceParam -> ale2Wr = calcData; /* Ale To Write */
+
+ calcData = ((0x1c000 & valueOfReg) >> 14) + ((0x4000000 & valueOfReg) >> 23);
+ deviceParam -> wrLow = calcData; /* Write Active */
+
+ calcData = ((0xe0000 & valueOfReg) >> 17) + ((0x8000000 & valueOfReg) >> 24);
+ deviceParam -> wrHigh = calcData; /* Write High */
+
+ calcData = ((0x300000 & valueOfReg) >> 20);
+ switch (calcData)
+ {
+ case 0:
+ deviceParam -> deviceWidth = 1; /* one Byte - 8-bit */
+ break;
+ case 1:
+ deviceParam -> deviceWidth = 2; /* two Bytes - 16-bit */
+ break;
+ case 2:
+ deviceParam -> deviceWidth = 4; /* four Bytes - 32-bit */
+ break;
+ case 3:
+ deviceParam -> deviceWidth = 8; /* eight Bytes - 64-bit */
+ break;
+ default:
+ deviceParam -> deviceWidth = 1;
+ break;
+ }
+ return true;
+}
+
+/********************************************************************
+* memorySetDeviceParam - This function used for setting device parameters to
+* DEVICE BANK PARAMETERS REGISTER
+*
+*
+* Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK
+* PARAMETERS REGISTER
+* - deviceNum : number of device
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum)
+{
+ unsigned int valueForReg;
+
+ if((deviceParam -> turnOff >= 0xf) || (deviceParam -> acc2First >= 0x1f) ||
+ (deviceParam -> acc2Next >= 0x1f) || (deviceParam -> ale2Wr >= 0xf) ||
+ (deviceParam -> wrLow >= 0xf) || (deviceParam -> wrHigh >= 0xf))
+ return false;
+ valueForReg = (((deviceParam -> turnOff) & 0x7) |
+ (((deviceParam -> turnOff) & 0x8) << 19) |
+ (((deviceParam -> acc2First) & 0xf) << 3) |
+ (((deviceParam -> acc2First) & 0x10) << 19) |
+ (((deviceParam -> acc2Next) & 0xf) << 7) |
+ (((deviceParam -> acc2Next) & 0x10) << 20) |
+ (((deviceParam -> ale2Wr) & 0x7) << 11) |
+ (((deviceParam -> ale2Wr) & 0xf) << 22) |
+ (((deviceParam -> wrLow) & 0x7) << 14) |
+ (((deviceParam -> wrLow) & 0xf) << 23) |
+ (((deviceParam -> wrHigh) & 0x7) << 17) |
+ (((deviceParam -> wrHigh) & 0xf) << 24));
+ /* insert the device width: */
+ switch(deviceParam->deviceWidth)
+ {
+ case 1:
+ valueForReg = valueForReg | _8BIT;
+ break;
+ case 2:
+ valueForReg = valueForReg | _16BIT;
+ break;
+ case 4:
+ valueForReg = valueForReg | _32BIT;
+ break;
+ case 8:
+ valueForReg = valueForReg | _64BIT;
+ break;
+ default:
+ valueForReg = valueForReg | _8BIT;
+ break;
+ }
+ GT_REG_WRITE(DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
+ return true;
+}
diff --git a/board/evb64260/misc.S b/board/evb64260/misc.S
new file mode 100644
index 0000000..f09528d
--- /dev/null
+++ b/board/evb64260/misc.S
@@ -0,0 +1,182 @@
+#include <config.h>
+#include <74xx_7xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include <galileo/gt64260R.h>
+
+#ifdef CONFIG_ECC
+ /* Galileo specific asm code for initializing ECC */
+ .globl board_relocate_rom
+board_relocate_rom:
+ mflr r7
+ /* update the location of the GT registers */
+ lis r11, CONFIG_SYS_GT_REGS@h
+ /* if we're using ECC, we must use the DMA engine to copy ourselves */
+ bl start_idma_transfer_0
+ bl wait_for_idma_0
+ bl stop_idma_engine_0
+
+ mtlr r7
+ blr
+
+ .globl board_init_ecc
+board_init_ecc:
+ mflr r7
+ /* NOTE: r10 still contains the location we've been relocated to
+ * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
+
+ /* now that we're running from ram, init the rest of main memory
+ * for ECC use */
+ lis r8, CONFIG_SYS_MONITOR_LEN@h
+ ori r8, r8, CONFIG_SYS_MONITOR_LEN@l
+
+ divw r3, r10, r8
+
+ /* set up the counter, and init the starting address */
+ mtctr r3
+ li r12, 0
+
+ /* bytes per transfer */
+ mr r5, r8
+about_to_init_ecc:
+1: mr r3, r12
+ mr r4, r12
+ bl start_idma_transfer_0
+ bl wait_for_idma_0
+ bl stop_idma_engine_0
+ add r12, r12, r8
+ bdnz 1b
+
+ mtlr r7
+ blr
+
+ /* r3: dest addr
+ * r4: source addr
+ * r5: byte count
+ * r11: gt regbase
+ * trashes: r6, r5
+ */
+start_idma_transfer_0:
+ /* set the byte count, including the OWN bit */
+ mr r6, r11
+ ori r6, r6, CHANNEL0_DMA_BYTE_COUNT
+ stwbrx r5, 0, (r6)
+
+ /* set the source address */
+ mr r6, r11
+ ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
+ stwbrx r4, 0, (r6)
+
+ /* set the dest address */
+ mr r6, r11
+ ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
+ stwbrx r3, 0, (r6)
+
+ /* set the next record pointer */
+ li r5, 0
+ mr r6, r11
+ ori r6, r6, CHANNEL0NEXT_RECORD_POINTER
+ stwbrx r5, 0, (r6)
+
+ /* set the low control register */
+ /* bit 9 is NON chained mode, bit 31 is new style descriptors.
+ bit 12 is channel enable */
+ ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
+ /* 15 shifted by 16 (oris) == bit 31 */
+ oris r5, r5, (1 << 15)
+ mr r6, r11
+ ori r6, r6, CHANNEL0CONTROL
+ stwbrx r5, 0, (r6)
+
+ blr
+
+ /* this waits for the bytecount to return to zero, indicating
+ * that the trasfer is complete */
+wait_for_idma_0:
+ mr r5, r11
+ lis r6, 0xff
+ ori r6, r6, 0xffff
+ ori r5, r5, CHANNEL0_DMA_BYTE_COUNT
+1: lwbrx r4, 0, (r5)
+ and. r4, r4, r6
+ bne 1b
+
+ blr
+
+ /* this turns off channel 0 of the idma engine */
+stop_idma_engine_0:
+ /* shut off the DMA engine */
+ li r5, 0
+ mr r6, r11
+ ori r6, r6, CHANNEL0CONTROL
+ stwbrx r5, 0, (r6)
+
+ blr
+#endif
+
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
+ /* NOTE: trashes r3-r7 */
+ .globl board_asm_init
+board_asm_init:
+ /* just move the GT registers to where they belong */
+ lis r3, CONFIG_SYS_DFL_GT_REGS@h
+ ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+ lis r4, CONFIG_SYS_GT_REGS@h
+ ori r4, r4, CONFIG_SYS_GT_REGS@l
+ li r5, INTERNAL_SPACE_DECODE
+
+ /* test to see if we've already moved */
+ lwbrx r6, r5, r4
+ andi. r6, r6, 0xffff
+ rlwinm r7, r4, 12, 16, 31
+ cmp cr0, r7, r6
+ beqlr
+
+ /* nope, have to move the registers */
+ lwbrx r6, r5, r3
+ andis. r6, r6, 0xffff
+ or r6, r6, r7
+ stwbrx r6, r5, r3
+
+ /* now, poll for the change */
+1: lwbrx r7, r5, r4
+ cmp cr0, r7, r6
+ bne 1b
+
+ /* done! */
+ blr
+#endif
+
+/* For use of the debug LEDs */
+ .global led_on0
+led_on0:
+ xor r18, r18, r18
+ lis r18, 0x1c80
+ ori r18, r18, 0x8000
+ stw r18, 0x0(r18)
+ sync
+ blr
+
+ .global led_on1
+led_on1:
+ xor r18, r18, r18
+ lis r18, 0x1c80
+ ori r18, r18, 0xc000
+ stw r18, 0x0(r18)
+ sync
+ blr
+
+ .global led_on2
+led_on2:
+ xor r18, r18, r18
+ lis r18, 0x1c81
+ ori r18, r18, 0x0000
+ stw r18, 0x0(r18)
+ sync
+ blr
diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c
new file mode 100644
index 0000000..c9da57c
--- /dev/null
+++ b/board/evb64260/mpsc.c
@@ -0,0 +1,838 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * mpsc.c - driver for console over the MPSC.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/cache.h>
+
+#include <malloc.h>
+#include "mpsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int (*mpsc_putchar)(char ch) = mpsc_putchar_early;
+
+static volatile unsigned int *rx_desc_base=NULL;
+static unsigned int rx_desc_index=0;
+static volatile unsigned int *tx_desc_base=NULL;
+static unsigned int tx_desc_index=0;
+
+/* local function declarations */
+static int galmpsc_connect(int channel, int connect);
+static int galmpsc_route_serial(int channel, int connect);
+static int galmpsc_route_rx_clock(int channel, int brg);
+static int galmpsc_route_tx_clock(int channel, int brg);
+static int galmpsc_write_config_regs(int mpsc, int mode);
+static int galmpsc_config_channel_regs(int mpsc);
+static int galmpsc_set_char_length(int mpsc, int value);
+static int galmpsc_set_stop_bit_length(int mpsc, int value);
+static int galmpsc_set_parity(int mpsc, int value);
+static int galmpsc_enter_hunt(int mpsc);
+static int galmpsc_set_brkcnt(int mpsc, int value);
+static int galmpsc_set_tcschar(int mpsc, int value);
+static int galmpsc_set_snoop(int mpsc, int value);
+static int galmpsc_shutdown(int mpsc);
+
+static int galsdma_set_RFT(int channel);
+static int galsdma_set_SFM(int channel);
+static int galsdma_set_rxle(int channel);
+static int galsdma_set_txle(int channel);
+static int galsdma_set_burstsize(int channel, unsigned int value);
+static int galsdma_set_RC(int channel, unsigned int value);
+
+static int galbrg_set_CDV(int channel, int value);
+static int galbrg_enable(int channel);
+static int galbrg_disable(int channel);
+static int galbrg_set_clksrc(int channel, int value);
+static int galbrg_set_CUV(int channel, int value);
+
+static void galsdma_enable_rx(void);
+
+/* static int galbrg_reset(int channel); */
+
+#define SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+#define FLUSH_DCACHE(a,b)
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+
+
+/* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */
+#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->arch.mirror_hack[0]))
+
+#define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);}
+#define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M)
+
+#define GT_REG_WRITE_MIRROR(a,i,g,d) {MIRROR_HACK->a ## _M[i] = d; GT_REG_WRITE(a + (i*g),d);}
+#define GTREGREAD_MIRROR(a,i,g) (MIRROR_HACK->a ## _M[i])
+
+/* make sure this isn't bigger than 16 long words (u-boot.h) */
+struct _tag_mirror_hack {
+ unsigned GALMPSC_PROTOCONF_REG_M[2]; /* 8008 */
+ unsigned GALMPSC_CHANNELREG_1_M[2]; /* 800c */
+ unsigned GALMPSC_CHANNELREG_2_M[2]; /* 8010 */
+ unsigned GALBRG_0_CONFREG_M[2]; /* b200 */
+
+ unsigned GALMPSC_ROUTING_REGISTER_M; /* b400 */
+ unsigned GALMPSC_RxC_ROUTE_M; /* b404 */
+ unsigned GALMPSC_TxC_ROUTE_M; /* b408 */
+
+ unsigned int baudrate; /* current baudrate, for tsc delay calc */
+};
+
+/* static struct _tag_mirror_hack *mh = NULL; */
+
+/* special function for running out of flash. doesn't modify any
+ * global variables [josh] */
+int
+mpsc_putchar_early(char ch)
+{
+ int mpsc=CHANNEL;
+ int temp=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
+ galmpsc_set_tcschar(mpsc,ch);
+ GT_REG_WRITE(GALMPSC_CHANNELREG_2+(mpsc*GALMPSC_REG_GAP), temp|0x200);
+
+#define MAGIC_FACTOR (10*1000000)
+
+ udelay(MAGIC_FACTOR / MIRROR_HACK->baudrate);
+ return 0;
+}
+
+/* This is used after relocation, see serial.c and mpsc_init2 */
+static int
+mpsc_putchar_sdma(char ch)
+{
+ volatile unsigned int *p;
+ unsigned int temp;
+
+
+ /* align the descriptor */
+ p = tx_desc_base;
+ memset((void *)p, 0, 8 * sizeof(unsigned int));
+
+ /* fill one 64 bit buffer */
+ /* word swap, pad with 0 */
+ p[4] = 0; /* x */
+ p[5] = (unsigned int)ch; /* x */
+
+ /* CHANGED completely according to GT64260A dox - NTL */
+ p[0] = 0x00010001; /* 0 */
+ p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* 4 */
+ p[2] = 0; /* 8 */
+ p[3] = (unsigned int)&p[4]; /* c */
+
+#if 0
+ p[9] = DESC_FIRST | DESC_LAST;
+ p[10] = (unsigned int)&p[0];
+ p[11] = (unsigned int)&p[12];
+#endif
+
+ FLUSH_DCACHE(&p[0], &p[8]);
+
+ GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF),
+ (unsigned int)&p[0]);
+ GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF),
+ (unsigned int)&p[0]);
+
+ temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF));
+ temp |= (TX_DEMAND | TX_STOP);
+ GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp);
+
+ INVALIDATE_DCACHE(&p[1], &p[2]);
+
+ while(p[1] & DESC_OWNER) {
+ udelay(100);
+ INVALIDATE_DCACHE(&p[1], &p[2]);
+ }
+
+ return 0;
+}
+
+char mpsc_getchar (void)
+{
+ static unsigned int done = 0;
+ volatile char ch;
+ unsigned int len = 0, idx = 0, temp;
+
+ volatile unsigned int *p;
+
+
+ do {
+ p = &rx_desc_base[rx_desc_index * 8];
+
+ INVALIDATE_DCACHE (&p[0], &p[1]);
+ /* Wait for character */
+ while (p[1] & DESC_OWNER) {
+ udelay (100);
+ INVALIDATE_DCACHE (&p[0], &p[1]);
+ }
+
+ /* Handle error case */
+ if (p[1] & (1 << 15)) {
+ printf ("oops, error: %08x\n", p[1]);
+
+ temp = GTREGREAD_MIRROR (GALMPSC_CHANNELREG_2,
+ CHANNEL, GALMPSC_REG_GAP);
+ temp |= (1 << 23);
+ GT_REG_WRITE_MIRROR (GALMPSC_CHANNELREG_2, CHANNEL,
+ GALMPSC_REG_GAP, temp);
+
+ /* Can't poll on abort bit, so we just wait. */
+ udelay (100);
+
+ galsdma_enable_rx ();
+ }
+
+ /* Number of bytes left in this descriptor */
+ len = p[0] & 0xffff;
+
+ if (len) {
+ /* Where to look */
+ idx = 5;
+ if (done > 3)
+ idx = 4;
+ if (done > 7)
+ idx = 7;
+ if (done > 11)
+ idx = 6;
+
+ INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
+ ch = p[idx] & 0xff;
+ done++;
+ }
+
+ if (done < len) {
+ /* this descriptor has more bytes still
+ * shift down the char we just read, and leave the
+ * buffer in place for the next time around
+ */
+ p[idx] = p[idx] >> 8;
+ FLUSH_DCACHE (&p[idx], &p[idx + 1]);
+ }
+
+ if (done == len) {
+ /* nothing left in this descriptor.
+ * go to next one
+ */
+ p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST;
+ p[0] = 0x00100000;
+ FLUSH_DCACHE (&p[0], &p[1]);
+ /* Next descriptor */
+ rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+ done = 0;
+ }
+ } while (len == 0); /* galileo bug.. len might be zero */
+
+ return ch;
+}
+
+int
+mpsc_test_char(void)
+{
+ volatile unsigned int *p = &rx_desc_base[rx_desc_index*8];
+
+ INVALIDATE_DCACHE(&p[1], &p[2]);
+
+ if (p[1] & DESC_OWNER) return 0;
+ else return 1;
+}
+
+int
+mpsc_init(int baud)
+{
+ memset(MIRROR_HACK, 0, sizeof(struct _tag_mirror_hack));
+ MIRROR_HACK->GALMPSC_ROUTING_REGISTER_M=0x3fffffff;
+
+ /* BRG CONFIG */
+ galbrg_set_baudrate(CHANNEL, baud);
+#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
+ galbrg_set_clksrc(CHANNEL,0x8); /* connect TCLK -> BRG */
+#else
+ galbrg_set_clksrc(CHANNEL,0);
+#endif
+ galbrg_set_CUV(CHANNEL, 0);
+ galbrg_enable(CHANNEL);
+
+ /* Set up clock routing */
+ galmpsc_connect(CHANNEL, GALMPSC_CONNECT);
+ galmpsc_route_serial(CHANNEL, GALMPSC_CONNECT);
+ galmpsc_route_rx_clock(CHANNEL, CHANNEL);
+ galmpsc_route_tx_clock(CHANNEL, CHANNEL);
+
+ /* reset MPSC state */
+ galmpsc_shutdown(CHANNEL);
+
+ /* SDMA CONFIG */
+ galsdma_set_burstsize(CHANNEL, L1_CACHE_BYTES/8); /* in 64 bit words (8 bytes) */
+ galsdma_set_txle(CHANNEL);
+ galsdma_set_rxle(CHANNEL);
+ galsdma_set_RC(CHANNEL, 0xf);
+ galsdma_set_SFM(CHANNEL);
+ galsdma_set_RFT(CHANNEL);
+
+ /* MPSC CONFIG */
+ galmpsc_write_config_regs(CHANNEL, GALMPSC_UART);
+ galmpsc_config_channel_regs(CHANNEL);
+ galmpsc_set_char_length(CHANNEL, GALMPSC_CHAR_LENGTH_8); /* 8 */
+ galmpsc_set_parity(CHANNEL, GALMPSC_PARITY_NONE); /* N */
+ galmpsc_set_stop_bit_length(CHANNEL, GALMPSC_STOP_BITS_1); /* 1 */
+
+ /* COMM_MPSC CONFIG */
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+ galmpsc_set_snoop(CHANNEL, 0); /* disable snoop */
+#else
+ galmpsc_set_snoop(CHANNEL, 1); /* enable snoop */
+#endif
+
+ return 0;
+}
+
+void
+mpsc_init2(void)
+{
+ int i;
+
+ mpsc_putchar = mpsc_putchar_sdma;
+
+ /* RX descriptors */
+ rx_desc_base = (unsigned int *)malloc(((RX_DESC+1)*8) *
+ sizeof(unsigned int));
+
+ /* align descriptors */
+ rx_desc_base = (unsigned int *)
+ (((unsigned int)rx_desc_base+32) & 0xFFFFFFF0);
+
+ rx_desc_index = 0;
+
+ memset((void *)rx_desc_base, 0, (RX_DESC*8)*sizeof(unsigned int));
+
+ for (i = 0; i < RX_DESC; i++) {
+ rx_desc_base[i*8 + 3] = (unsigned int)&rx_desc_base[i*8 + 4]; /* Buffer */
+ rx_desc_base[i*8 + 2] = (unsigned int)&rx_desc_base[(i+1)*8]; /* Next descriptor */
+ rx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST; /* Command & control */
+ rx_desc_base[i*8] = 0x00100000;
+ }
+ rx_desc_base[(i-1)*8 + 2] = (unsigned int)&rx_desc_base[0];
+
+ FLUSH_DCACHE(&rx_desc_base[0], &rx_desc_base[RX_DESC*8]);
+ GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR+(CHANNEL*GALSDMA_REG_DIFF),
+ (unsigned int)&rx_desc_base[0]);
+
+ /* TX descriptors */
+ tx_desc_base = (unsigned int *)malloc(((TX_DESC+1)*8) *
+ sizeof(unsigned int));
+
+ /* align descriptors */
+ tx_desc_base = (unsigned int *)
+ (((unsigned int)tx_desc_base+32) & 0xFFFFFFF0);
+
+ tx_desc_index = -1;
+
+ memset((void *)tx_desc_base, 0, (TX_DESC*8)*sizeof(unsigned int));
+
+ for (i = 0; i < TX_DESC; i++) {
+ tx_desc_base[i*8 + 5] = (unsigned int)0x23232323;
+ tx_desc_base[i*8 + 4] = (unsigned int)0x23232323;
+ tx_desc_base[i*8 + 3] = (unsigned int)&tx_desc_base[i*8 + 4];
+ tx_desc_base[i*8 + 2] = (unsigned int)&tx_desc_base[(i+1)*8];
+ tx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST;
+
+ /* set sbytecnt and shadow byte cnt to 1 */
+ tx_desc_base[i*8] = 0x00010001;
+ }
+ tx_desc_base[(i-1)*8 + 2] = (unsigned int)&tx_desc_base[0];
+
+ FLUSH_DCACHE(&tx_desc_base[0], &tx_desc_base[TX_DESC*8]);
+
+ udelay(100);
+
+ galsdma_enable_rx();
+
+ return;
+}
+
+int
+galbrg_set_baudrate(int channel, int rate)
+{
+ int clock;
+
+ galbrg_disable(channel);
+
+#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
+ /* from tclk */
+ clock = (CONFIG_SYS_BUS_CLK/(16*rate)) - 1;
+#else
+ clock = (3686400/(16*rate)) - 1;
+#endif
+
+ galbrg_set_CDV(channel, clock);
+
+ galbrg_enable(channel);
+
+ MIRROR_HACK->baudrate = rate;
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+/* Below are all the private functions that no one else needs */
+
+static int
+galbrg_set_CDV(int channel, int value)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
+ temp &= 0xFFFF0000;
+ temp |= (value & 0x0000FFFF);
+ GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel,GALBRG_REG_GAP, temp);
+
+ return 0;
+}
+
+static int
+galbrg_enable(int channel)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
+ temp |= 0x00010000;
+ GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp);
+
+ return 0;
+}
+
+static int
+galbrg_disable(int channel)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
+ temp &= 0xFFFEFFFF;
+ GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp);
+
+ return 0;
+}
+
+static int
+galbrg_set_clksrc(int channel, int value)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP);
+ temp &= 0xFF83FFFF;
+ temp |= (value << 18);
+ GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP,temp);
+
+ return 0;
+}
+
+static int
+galbrg_set_CUV(int channel, int value)
+{
+ GT_REG_WRITE(GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
+
+ return 0;
+}
+
+#if 0
+static int
+galbrg_reset(int channel)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+ temp |= 0x20000;
+ GT_REG_WRITE(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+ return 0;
+}
+#endif
+
+static int
+galsdma_set_RFT(int channel)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+ temp |= 0x00000001;
+ GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+ return 0;
+}
+
+static int
+galsdma_set_SFM(int channel)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+ temp |= 0x00000002;
+ GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+ return 0;
+}
+
+static int
+galsdma_set_rxle(int channel)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+ temp |= 0x00000040;
+ GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+ return 0;
+}
+
+static int
+galsdma_set_txle(int channel)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+ temp |= 0x00000080;
+ GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+ return 0;
+}
+
+static int
+galsdma_set_RC(int channel, unsigned int value)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+ temp &= ~0x0000003c;
+ temp |= (value << 2);
+ GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+ return 0;
+}
+
+static int
+galsdma_set_burstsize(int channel, unsigned int value)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+ temp &= 0xFFFFCFFF;
+ switch (value) {
+ case 8:
+ GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
+ (temp | (0x3 << 12)));
+ break;
+
+ case 4:
+ GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
+ (temp | (0x2 << 12)));
+ break;
+
+ case 2:
+ GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
+ (temp | (0x1 << 12)));
+ break;
+
+ case 1:
+ GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
+ (temp | (0x0 << 12)));
+ break;
+
+ default:
+ return -1;
+ break;
+ }
+
+ return 0;
+}
+
+static int
+galmpsc_connect(int channel, int connect)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER);
+
+ if ((channel == 0) && connect)
+ temp &= ~0x00000007;
+ else if ((channel == 1) && connect)
+ temp &= ~(0x00000007 << 6);
+ else if ((channel == 0) && !connect)
+ temp |= 0x00000007;
+ else
+ temp |= (0x00000007 << 6);
+
+ /* Just in case... */
+ temp &= 0x3fffffff;
+
+ GT_REG_WRITE_MIRROR_G(GALMPSC_ROUTING_REGISTER, temp);
+
+ return 0;
+}
+
+static int
+galmpsc_route_serial(int channel, int connect)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD(GALMPSC_SERIAL_MULTIPLEX);
+
+ if ((channel == 0) && connect)
+ temp |= 0x00000100;
+ else if ((channel == 1) && connect)
+ temp |= 0x00001000;
+ else if ((channel == 0) && !connect)
+ temp &= ~0x00000100;
+ else
+ temp &= ~0x00001000;
+
+ GT_REG_WRITE(GALMPSC_SERIAL_MULTIPLEX,temp);
+
+ return 0;
+}
+
+static int
+galmpsc_route_rx_clock(int channel, int brg)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE);
+
+ if (channel == 0)
+ temp |= brg;
+ else
+ temp |= (brg << 8);
+
+ GT_REG_WRITE_MIRROR_G(GALMPSC_RxC_ROUTE,temp);
+
+ return 0;
+}
+
+static int
+galmpsc_route_tx_clock(int channel, int brg)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE);
+
+ if (channel == 0)
+ temp |= brg;
+ else
+ temp |= (brg << 8);
+
+ GT_REG_WRITE_MIRROR_G(GALMPSC_TxC_ROUTE,temp);
+
+ return 0;
+}
+
+static int
+galmpsc_write_config_regs(int mpsc, int mode)
+{
+ if (mode == GALMPSC_UART) {
+ /* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
+ GT_REG_WRITE(GALMPSC_MCONF_LOW + (mpsc*GALMPSC_REG_GAP),
+ 0x000004c4);
+
+ /* Main config reg High (32x Rx/Tx clock mode, width=8bits */
+ GT_REG_WRITE(GALMPSC_MCONF_HIGH +(mpsc*GALMPSC_REG_GAP),
+ 0x024003f8);
+ /* 22 2222 1111 */
+ /* 54 3210 9876 */
+ /* 0000 0010 0000 0000 */
+ /* 1 */
+ /* 098 7654 3210 */
+ /* 0000 0011 1111 1000 */
+ } else
+ return -1;
+
+ return 0;
+}
+
+static int
+galmpsc_config_channel_regs(int mpsc)
+{
+ GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0);
+ GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0);
+ GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1);
+ GT_REG_WRITE(GALMPSC_CHANNELREG_4+(mpsc*GALMPSC_REG_GAP), 0);
+ GT_REG_WRITE(GALMPSC_CHANNELREG_5+(mpsc*GALMPSC_REG_GAP), 0);
+ GT_REG_WRITE(GALMPSC_CHANNELREG_6+(mpsc*GALMPSC_REG_GAP), 0);
+ GT_REG_WRITE(GALMPSC_CHANNELREG_7+(mpsc*GALMPSC_REG_GAP), 0);
+ GT_REG_WRITE(GALMPSC_CHANNELREG_8+(mpsc*GALMPSC_REG_GAP), 0);
+ GT_REG_WRITE(GALMPSC_CHANNELREG_9+(mpsc*GALMPSC_REG_GAP), 0);
+ GT_REG_WRITE(GALMPSC_CHANNELREG_10+(mpsc*GALMPSC_REG_GAP), 0);
+
+ galmpsc_set_brkcnt(mpsc, 0x3);
+ galmpsc_set_tcschar(mpsc, 0xab);
+
+ return 0;
+}
+
+static int
+galmpsc_set_brkcnt(int mpsc, int value)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
+ temp &= 0x0000FFFF;
+ temp |= (value << 16);
+ GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp);
+
+ return 0;
+}
+
+static int
+galmpsc_set_tcschar(int mpsc, int value)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
+ temp &= 0xFFFF0000;
+ temp |= value;
+ GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp);
+
+ return 0;
+}
+
+static int
+galmpsc_set_char_length(int mpsc, int value)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
+ temp &= 0xFFFFCFFF;
+ temp |= (value << 12);
+ GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP, temp);
+
+ return 0;
+}
+
+static int
+galmpsc_set_stop_bit_length(int mpsc, int value)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
+ temp |= (value << 14);
+ GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP,temp);
+
+ return 0;
+}
+
+static int
+galmpsc_set_parity(int mpsc, int value)
+{
+ unsigned int temp;
+
+ temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
+ if (value != -1) {
+ temp &= 0xFFF3FFF3;
+ temp |= ((value << 18) | (value << 2));
+ temp |= ((value << 17) | (value << 1));
+ } else {
+ temp &= 0xFFF1FFF1;
+ }
+
+ GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp);
+
+ return 0;
+}
+
+static int
+galmpsc_enter_hunt(int mpsc)
+{
+ int temp;
+
+ temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
+ temp |= 0x80000000;
+ GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp);
+
+ /* Should Poll on Enter Hunt bit, but the register is write-only */
+ /* errata suggests pausing 100 system cycles */
+ udelay(100);
+
+ return 0;
+}
+
+
+static int
+galmpsc_shutdown(int mpsc)
+{
+#if 0
+ unsigned int temp;
+
+ /* cause RX abort (clears RX) */
+ temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
+ temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
+ temp &= ~MPSC_ENTER_HUNT;
+ GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP,temp);
+#endif
+
+ GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, 0);
+ GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF,
+ SDMA_TX_ABORT | SDMA_RX_ABORT);
+
+ /* shut down the MPSC */
+ GT_REG_WRITE(GALMPSC_MCONF_LOW, 0);
+ GT_REG_WRITE(GALMPSC_MCONF_HIGH, 0);
+ GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG, mpsc, GALMPSC_REG_GAP,0);
+
+ udelay(100);
+
+ /* shut down the sdma engines. */
+ /* reset config to default */
+ GT_REG_WRITE(GALSDMA_0_CONF_REG + CHANNEL * GALSDMA_REG_DIFF,
+ 0x000000fc);
+
+ udelay(100);
+
+ /* clear the SDMA current and first TX and RX pointers */
+ GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
+ GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
+ GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
+
+ udelay(100);
+
+ return 0;
+}
+
+static void
+galsdma_enable_rx(void)
+{
+ int temp;
+
+ /* Enable RX processing */
+ temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF));
+ temp |= RX_ENABLE;
+ GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp);
+
+ galmpsc_enter_hunt(CHANNEL);
+}
+
+static int
+galmpsc_set_snoop(int mpsc, int value)
+{
+ int reg = mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : MPSC_0_ADDRESS_CONTROL_LOW;
+ int temp=GTREGREAD(reg);
+ if(value)
+ temp |= (1<< 6) | (1<<14) | (1<<22) | (1<<30);
+ else
+ temp &= ~((1<< 6) | (1<<14) | (1<<22) | (1<<30));
+ GT_REG_WRITE(reg, temp);
+ return 0;
+}
diff --git a/board/evb64260/mpsc.h b/board/evb64260/mpsc.h
new file mode 100644
index 0000000..0747477
--- /dev/null
+++ b/board/evb64260/mpsc.h
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include <galileo/gt64260R.h>
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_init2(void);
+char mpsc_getchar(void);
+int mpsc_test_char(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+extern int (*mpsc_putchar)(char ch);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC 5
+#define RX_DESC 20
+
+#define DESC_FIRST 0x00010000
+#define DESC_LAST 0x00020000
+#define DESC_OWNER 0x80000000
+
+#define TX_DEMAND 0x00800000
+#define TX_STOP 0x00010000
+#define RX_ENABLE 0x00000080
+
+#define SDMA_RX_ABORT (1 << 15)
+#define SDMA_TX_ABORT (1 << 31)
+#define MPSC_TX_ABORT (1 << 7)
+#define MPSC_RX_ABORT (1 << 23)
+#define MPSC_ENTER_HUNT (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT 0x1
+#define GALMPSC_DISCONNECT 0x0
+
+#define GALMPSC_UART 0x1
+
+#define GALMPSC_STOP_BITS_1 0x0
+#define GALMPSC_STOP_BITS_2 0x1
+#define GALMPSC_CHAR_LENGTH_8 0x3
+#define GALMPSC_CHAR_LENGTH_7 0x2
+
+#define GALMPSC_PARITY_ODD 0x0
+#define GALMPSC_PARITY_EVEN 0x2
+#define GALMPSC_PARITY_MARK 0x3
+#define GALMPSC_PARITY_SPACE 0x1
+#define GALMPSC_PARITY_NONE -1
+
+#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
+#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
+#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
+#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
+
+#define GALMPSC_REG_GAP 0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
+#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
+#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
+#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
+#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
+#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
+#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
+#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
+#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
+#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
+#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST (1 << 16)
+#define GALSDMA_COMMAND_LAST (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO (1 << 30)
+#define GALSDMA_COMMAND_OWNER (1 << 31)
+
+#define GALSDMA_RX 0
+#define GALSDMA_TX 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
+#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
+#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
+#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
+#define GALSDMA_REG_DIFF 0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
+
+#define GALSDMA_MODE_UART 0
+#define GALSDMA_MODE_BISYNC 1
+#define GALSDMA_MODE_HDLC 2
+#define GALSDMA_MODE_TRANSPARENT 3
+
+#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
+#define GALBRG_REG_GAP 0x0008
+#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
+
+#endif /* __MPSC_H__ */
diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c
new file mode 100644
index 0000000..582f24c
--- /dev/null
+++ b/board/evb64260/pci.c
@@ -0,0 +1,760 @@
+/* PCI.c - PCI functions */
+
+/* Copyright - Galileo technology. */
+
+#include <common.h>
+#include <pci.h>
+
+#include <galileo/pci.h>
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+#ifdef CONFIG_ZUMA_V2
+ {0, 0, 0, 0, 0, 0, 0, 29,[8 ... PCI_MAX_DEVICES - 1] = 0},
+ {0, 0, 0, 0, 0, 0, 0, 28,[8 ... PCI_MAX_DEVICES - 1] = 0}
+#else /* EVB??? This is a guess */
+ {0, 0, 0, 0, 0, 0, 0, 27, 27,[9 ... PCI_MAX_DEVICES - 1] = 0},
+ {0, 0, 0, 0, 0, 0, 0, 29, 29,[9 ... PCI_MAX_DEVICES - 1] = 0}
+#endif
+};
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+ PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+ PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+ PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+ PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+ PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+ PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+ PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+ PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+ PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+ PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+ {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+ PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+ {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+ PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+ PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static unsigned int local_buses[] = { 0, 0 };
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+* - Make sure the GT is configured as a master before writing
+* to another device on the PCI.
+* - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
+* (or any other PCI device spec)
+* pciDevNum: The device number needs to be addressed.
+*
+* Configuration Address 0xCF8:
+*
+* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
+* |congif|Reserved| Bus |Device|Function|Register|00|
+* |Enable| |Number|Number| Number | Number | | <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+ unsigned int pciDevNum, unsigned int data)
+{
+ volatile unsigned int DataForAddrReg;
+ unsigned int functionNum;
+ unsigned int busNum = PCI_BUS (pciDevNum);
+ unsigned int addr;
+
+ if (pciDevNum > 32) /* illegal device Number */
+ return;
+ if (pciDevNum == SELF) { /* configure our configuration space. */
+ pciDevNum =
+ (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+ 0x1f;
+ busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+ 0xff0000;
+ }
+ functionNum = regOffset & 0x00000700;
+ pciDevNum = pciDevNum << 11;
+ regOffset = regOffset & 0xfc;
+ DataForAddrReg =
+ (regOffset | pciDevNum | functionNum | busNum) | BIT31;
+ GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+ GT_REG_READ (pci_configuration_address[host], &addr);
+ if (addr != DataForAddrReg)
+ return;
+ GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg - Read from a PCI0 configuration register
+* - Make sure the GT is configured as a master before reading
+* from another device on the PCI.
+* - The function takes care of Big/Little endian conversion.
+* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
+* spec)
+* pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+* cause register to make sure the data is valid
+*
+* Configuration Address 0xCF8:
+*
+* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
+* |congif|Reserved| Bus |Device|Function|Register|00|
+* |Enable| |Number|Number| Number | Number | | <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+ unsigned int pciDevNum)
+{
+ volatile unsigned int DataForAddrReg;
+ unsigned int data;
+ unsigned int functionNum;
+ unsigned int busNum = PCI_BUS (pciDevNum);
+
+ if (pciDevNum > 32) /* illegal device Number */
+ return 0xffffffff;
+ if (pciDevNum == SELF) { /* configure our configuration space. */
+ pciDevNum =
+ (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+ 0x1f;
+ busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+ 0xff0000;
+ }
+ functionNum = regOffset & 0x00000700;
+ pciDevNum = pciDevNum << 11;
+ regOffset = regOffset & 0xfc;
+ DataForAddrReg =
+ (regOffset | pciDevNum | functionNum | busNum) | BIT31;
+ GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+ GT_REG_READ (pci_configuration_address[host], &data);
+ if (data != DataForAddrReg)
+ return 0xffffffff;
+ GT_REG_READ (pci_configuration_data[host], &data);
+ return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+* the agent is placed on another Bus. For more
+* information read P2P in the PCI spec.
+*
+* Inputs: unsigned int regOffset - The register offset as it apears in the
+* GT spec (or any other PCI device spec).
+* unsigned int pciDevNum - The device number needs to be addressed.
+* unsigned int busNum - On which bus does the Target agent connect
+* to.
+* unsigned int data - data to be written.
+*
+* Configuration Address 0xCF8:
+*
+* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
+* |congif|Reserved| Bus |Device|Function|Register|01|
+* |Enable| |Number|Number| Number | Number | | <=field Name
+*
+* The configuration Address is configure as type-I (bits[1:0] = '01') due to
+* PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+ unsigned int regOffset,
+ unsigned int pciDevNum,
+ unsigned int busNum, unsigned int data)
+{
+ unsigned int DataForReg;
+ unsigned int functionNum;
+
+ functionNum = regOffset & 0x00000700;
+ pciDevNum = pciDevNum << 11;
+ regOffset = regOffset & 0xff;
+ busNum = busNum << 16;
+ if (pciDevNum == SELF) { /* This board */
+ DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+ } else {
+ DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+ BIT31 | BIT0;
+ }
+ GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+ if (pciDevNum == SELF) { /* This board */
+ GT_REG_WRITE (pci_configuration_data[host], data);
+ } else { /* configuration Transaction over the pci. */
+
+ /* The PCI is working in LE Mode So it swap the Data. */
+ GT_REG_WRITE (pci_configuration_data[host], WORD_SWAP (data));
+ }
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
+* the agent target locate on another PCI bus.
+* - Make sure the GT is configured as a master
+* before reading from another device on the PCI.
+* - The function takes care of Big/Little endian
+* conversion.
+* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
+* spec). (configuration register offset.)
+* pciDevNum: The device number needs to be addressed.
+* busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+* cause register to make sure the data is valid
+*
+* Configuration Address 0xCF8:
+*
+* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
+* |congif|Reserved| Bus |Device|Function|Register|01|
+* |Enable| |Number|Number| Number | Number | | <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+ unsigned int regOffset,
+ unsigned int pciDevNum,
+ unsigned int busNum)
+{
+ unsigned int DataForReg;
+ unsigned int data;
+ unsigned int functionNum;
+
+ functionNum = regOffset & 0x00000700;
+ pciDevNum = pciDevNum << 11;
+ regOffset = regOffset & 0xff;
+ busNum = busNum << 16;
+ if (pciDevNum == SELF) { /* This board */
+ DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+ } else { /* agent on another bus */
+
+ DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+ BIT0 | BIT31;
+ }
+ GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+ if (pciDevNum == SELF) { /* This board */
+ GT_REG_READ (pci_configuration_data[host], &data);
+ return data;
+ } else { /* The PCI is working in LE Mode So it swap the Data. */
+
+ GT_REG_READ (pci_configuration_data[host], &data);
+ return WORD_SWAP (data);
+ }
+}
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT: Bus, Region - The bus and region we ask for its base address.
+* OUTPUT: N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+ switch (host) {
+ case PCI_HOST0:
+ switch (region) {
+ case PCI_IO:
+ return PCI_0I_O_LOW_DECODE_ADDRESS;
+ case PCI_REGION0:
+ return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+ case PCI_REGION1:
+ return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+ case PCI_REGION2:
+ return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+ case PCI_REGION3:
+ return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+ }
+ case PCI_HOST1:
+ switch (region) {
+ case PCI_IO:
+ return PCI_1I_O_LOW_DECODE_ADDRESS;
+ case PCI_REGION0:
+ return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+ case PCI_REGION1:
+ return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+ case PCI_REGION2:
+ return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+ case PCI_REGION3:
+ return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+ }
+ }
+ return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+ switch (host) {
+ case PCI_HOST0:
+ switch (region) {
+ case PCI_IO:
+ return PCI_0I_O_ADDRESS_REMAP;
+ case PCI_REGION0:
+ return PCI_0MEMORY0_ADDRESS_REMAP;
+ case PCI_REGION1:
+ return PCI_0MEMORY1_ADDRESS_REMAP;
+ case PCI_REGION2:
+ return PCI_0MEMORY2_ADDRESS_REMAP;
+ case PCI_REGION3:
+ return PCI_0MEMORY3_ADDRESS_REMAP;
+ }
+ case PCI_HOST1:
+ switch (region) {
+ case PCI_IO:
+ return PCI_1I_O_ADDRESS_REMAP;
+ case PCI_REGION0:
+ return PCI_1MEMORY0_ADDRESS_REMAP;
+ case PCI_REGION1:
+ return PCI_1MEMORY1_ADDRESS_REMAP;
+ case PCI_REGION2:
+ return PCI_1MEMORY2_ADDRESS_REMAP;
+ case PCI_REGION3:
+ return PCI_1MEMORY3_ADDRESS_REMAP;
+ }
+ }
+ return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+ unsigned int bankBase, unsigned int bankLength)
+{
+ unsigned int low = 0xfff;
+ unsigned int high = 0x0;
+ unsigned int regOffset = pciGetRegOffset (host, region);
+ unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+ if (bankLength != 0) {
+ low = (bankBase >> 20) & 0xfff;
+ high = ((bankBase + bankLength) >> 20) - 1;
+ }
+
+ GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
+ GT_REG_WRITE (regOffset + 8, high);
+
+ if (bankLength != 0) { /* must do AFTER writing maps */
+ GT_REG_WRITE (remapOffset, remapBase >> 20); /* sorry, 32 bits only.
+ dont support upper 32
+ in this driver */
+ }
+ return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+ unsigned int low;
+ unsigned int regOffset = pciGetRegOffset (host, region);
+
+ GT_REG_READ (regOffset, &low);
+ return (low & 0xfff) << 20;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+ unsigned int low, high;
+ unsigned int regOffset = pciGetRegOffset (host, region);
+
+ GT_REG_READ (regOffset, &low);
+ GT_REG_READ (regOffset + 8, &high);
+ high &= 0xfff;
+ low &= 0xfff;
+ if (high <= low)
+ return 0;
+ return (high + 1 - low) << 20;
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+ unsigned int pciDramBase, unsigned int pciDramSize)
+{
+ pciDramBase = pciDramBase & 0xfffff000;
+ pciDramBase = pciDramBase | (pciReadConfigReg (host,
+ PCI_SCS_0_BASE_ADDRESS
+ + 4 * bank,
+ SELF) & 0x00000fff);
+ pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + 4 * bank, SELF,
+ pciDramBase);
+ if (pciDramSize == 0)
+ pciDramSize++;
+ GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+}
+
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+* feature bits given as an input.
+* - Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+* unsigned int features - See file: pci.h there are defintion for those
+* region features.
+* unsigned int baseAddress - The region base Address.
+* unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+ unsigned int features, unsigned int baseAddress,
+ unsigned int regionLength)
+{
+ unsigned int accessLow;
+ unsigned int accessHigh;
+ unsigned int accessTop = baseAddress + regionLength;
+
+ if (regionLength == 0) { /* close the region. */
+ pciDisableAccessRegion (host, region);
+ return true;
+ }
+ /* base Address is store is bits [11:0] */
+ accessLow = (baseAddress & 0xfff00000) >> 20;
+ /* All the features are update according to the defines in pci.h (to be on
+ the safe side we disable bits: [11:0] */
+ accessLow = accessLow | (features & 0xfffff000);
+ /* write to the Low Access Region register */
+ GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+ accessLow);
+
+ accessHigh = (accessTop & 0xfff00000) >> 20;
+
+ /* write to the High Access Region register */
+ GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+ accessHigh - 1);
+ return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+* to its low Address and MIN size to its high Address.
+*
+* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns: N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+ /* writing back the registers default values. */
+ GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+ 0x01001fff);
+ GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs: N/A
+* Returns: true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+ unsigned int regData;
+
+ GT_REG_READ (pci_arbiter_control[host], ®Data);
+ GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+ return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs: N/A
+* Returns: true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+ unsigned int regData;
+
+ GT_REG_READ (pci_arbiter_control[host], ®Data);
+ GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+ return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+* disable the park on last mechanism for each agent.
+* disabling this option for all agents results parking
+* on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
+* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns: true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+ PCI_AGENT_PARK externalAgent0,
+ PCI_AGENT_PARK externalAgent1,
+ PCI_AGENT_PARK externalAgent2,
+ PCI_AGENT_PARK externalAgent3,
+ PCI_AGENT_PARK externalAgent4,
+ PCI_AGENT_PARK externalAgent5)
+{
+ unsigned int regData;
+ unsigned int writeData;
+
+ GT_REG_READ (pci_arbiter_control[host], ®Data);
+ writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+ (externalAgent1 << 16) + (externalAgent2 << 17) +
+ (externalAgent3 << 18) + (externalAgent4 << 19) +
+ (externalAgent5 << 20);
+ regData = (regData & ~(0x7f << 14)) | writeData;
+ GT_REG_WRITE (pci_arbiter_control[host], regData);
+ return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+* supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+* snoopType - There is four optional Types:
+* 1. No Snoop.
+* 2. Snoop to WT region.
+* 3. Snoop to WB region.
+* 4. Snoop & Invalidate to WB region.
+* baseAddress - Base Address of this region.
+* regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+ PCI_SNOOP_TYPE snoopType,
+ unsigned int baseAddress,
+ unsigned int regionLength)
+{
+ unsigned int snoopXbaseAddress;
+ unsigned int snoopXtopAddress;
+ unsigned int data;
+ unsigned int snoopHigh = baseAddress + regionLength;
+
+ if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+ return false;
+ snoopXbaseAddress =
+ pci_snoop_control_base_0_low[host] + 0x10 * region;
+ snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+ if (regionLength == 0) { /* closing the region */
+ GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+ GT_REG_WRITE (snoopXtopAddress, 0);
+ return true;
+ }
+ baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
+ data = (baseAddress >> 20) | snoopType << 12;
+ GT_REG_WRITE (snoopXbaseAddress, data);
+ snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+ GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+ return true;
+}
+
+/*
+ *
+ */
+
+static int gt_read_config_dword (struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 * value)
+{
+ int bus = PCI_BUS (dev);
+
+ if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+ *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+ PCI_DEV (dev));
+ } else {
+ *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
+ cfg_addr, offset,
+ PCI_DEV (dev), bus);
+ }
+ return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 value)
+{
+ int bus = PCI_BUS (dev);
+
+ if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+ pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+ PCI_DEV (dev), value);
+ } else {
+ pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+ offset, PCI_DEV (dev), value,
+ bus);
+ }
+ return 0;
+}
+
+/*
+ *
+ */
+
+static void gt_setup_ide (struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *entry)
+{
+ static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+ u32 bar_response, bar_value;
+ int bar;
+
+ for (bar = 0; bar < 6; bar++) {
+ pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+ 0x0);
+ pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+ &bar_response);
+
+ pciauto_region_allocate (bar_response &
+ PCI_BASE_ADDRESS_SPACE_IO ? hose->
+ pci_io : hose->pci_mem, ide_bar[bar],
+ &bar_value);
+
+ pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+ bar_value);
+ }
+}
+
+#ifndef CONFIG_P3G4
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char pin, irq;
+
+ pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+ if (pin == 1) { /* only allow INT A */
+ irq = pci_irq_swizzle[(PCI_HOST) hose->
+ cfg_addr][PCI_DEV (dev)];
+ if (irq)
+ pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+ }
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+
+ {}
+};
+
+struct pci_controller pci0_hose = {
+#ifndef CONFIG_P3G4
+ fixup_irq:gt_fixup_irq,
+#endif
+ config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+#ifndef CONFIG_P3G4
+ fixup_irq:gt_fixup_irq,
+#endif
+ config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+ unsigned int command;
+
+ pci0_hose.first_busno = 0;
+ pci0_hose.last_busno = 0xff;
+ local_buses[0] = pci0_hose.first_busno;
+ /* PCI memory space */
+ pci_set_region (pci0_hose.regions + 0,
+ CONFIG_SYS_PCI0_0_MEM_SPACE,
+ CONFIG_SYS_PCI0_0_MEM_SPACE,
+ CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+ /* PCI I/O space */
+ pci_set_region (pci0_hose.regions + 1,
+ CONFIG_SYS_PCI0_IO_SPACE_PCI,
+ CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
+
+ pci_set_ops (&pci0_hose,
+ pci_hose_read_config_byte_via_dword,
+ pci_hose_read_config_word_via_dword,
+ gt_read_config_dword,
+ pci_hose_write_config_byte_via_dword,
+ pci_hose_write_config_word_via_dword,
+ gt_write_config_dword);
+
+ pci0_hose.region_count = 2;
+
+ pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+ pci_register_hose (&pci0_hose);
+
+#ifndef CONFIG_P3G4
+ pciArbiterEnable (PCI_HOST0);
+ pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+#endif
+
+ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MASTER;
+ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+ pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
+
+ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MEMORY;
+ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+ pci1_hose.first_busno = pci0_hose.last_busno + 1;
+ pci1_hose.last_busno = 0xff;
+ pci1_hose.current_busno = pci0_hose.current_busno;
+ local_buses[1] = pci1_hose.first_busno;
+
+ /* PCI memory space */
+ pci_set_region (pci1_hose.regions + 0,
+ CONFIG_SYS_PCI1_0_MEM_SPACE,
+ CONFIG_SYS_PCI1_0_MEM_SPACE,
+ CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+ /* PCI I/O space */
+ pci_set_region (pci1_hose.regions + 1,
+ CONFIG_SYS_PCI1_IO_SPACE_PCI,
+ CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
+
+ pci_set_ops (&pci1_hose,
+ pci_hose_read_config_byte_via_dword,
+ pci_hose_read_config_word_via_dword,
+ gt_read_config_dword,
+ pci_hose_write_config_byte_via_dword,
+ pci_hose_write_config_word_via_dword,
+ gt_write_config_dword);
+
+ pci1_hose.region_count = 2;
+
+ pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+ pci_register_hose (&pci1_hose);
+
+#ifndef CONFIG_P3G4
+ pciArbiterEnable (PCI_HOST1);
+ pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+#endif
+
+ command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MASTER;
+ pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+ pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
+
+ command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MEMORY;
+ pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+}
diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c
new file mode 100644
index 0000000..12b1308
--- /dev/null
+++ b/board/evb64260/sdram_init.c
@@ -0,0 +1,650 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* sdram_init.c - automatic memory sizing */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include <galileo/memory.h>
+#include <galileo/pci.h>
+#include <galileo/gt64260R.h>
+#include <net.h>
+#include <linux/compiler.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64260.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* #define DEBUG */
+#define MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+#define GB (1 << 30)
+
+/* structure to store the relevant information about an sdram bank */
+typedef struct sdram_info {
+ uchar drb_size;
+ uchar registered, ecc;
+ uchar tpar;
+ uchar tras_clocks;
+ uchar burst_len;
+ uchar banks, slot;
+ int size; /* detected size, not from I2C but from dram_size() */
+} sdram_info_t;
+
+#ifdef DEBUG
+void dump_dimm_info (struct sdram_info *d)
+{
+ static const char *ecc_legend[] = { "", " Parity", " ECC" };
+
+ printf ("dimm%s %sDRAM: %dMibytes:\n",
+ ecc_legend[d->ecc],
+ d->registered ? "R" : "", (d->size >> 20));
+ printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
+ d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
+ d->banks, d->slot);
+}
+#endif
+
+static int
+memory_map_bank (unsigned int bankNo,
+ unsigned int bankBase, unsigned int bankLength)
+{
+#ifdef DEBUG
+ if (bankLength > 0) {
+ printf ("mapping bank %d at %08x - %08x\n",
+ bankNo, bankBase, bankBase + bankLength - 1);
+ } else {
+ printf ("unmapping bank %d\n", bankNo);
+ }
+#endif
+
+ memoryMapBank (bankNo, bankBase, bankLength);
+
+ return 0;
+}
+
+#ifdef MAP_PCI
+static int
+memory_map_bank_pci (unsigned int bankNo,
+ unsigned int bankBase, unsigned int bankLength)
+{
+ PCI_HOST host;
+
+ for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
+ const int features =
+ PREFETCH_ENABLE |
+ DELAYED_READ_ENABLE |
+ AGGRESSIVE_PREFETCH |
+ READ_LINE_AGGRESSIVE_PREFETCH |
+ READ_MULTI_AGGRESSIVE_PREFETCH |
+ MAX_BURST_4 | PCI_NO_SWAP;
+
+ pciMapMemoryBank (host, bankNo, bankBase, bankLength);
+
+ pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
+ bankLength);
+
+ pciSetRegionFeatures (host, bankNo, features, bankBase,
+ bankLength);
+ }
+ return 0;
+}
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/* much of this code is based on (or is) the code in the pip405 port */
+/* thanks go to the authors of said port - Josh */
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NS10to10PS (unsigned char spd_byte)
+{
+ unsigned short ns, ns10;
+
+ /* isolate upper nibble */
+ ns = (spd_byte >> 4) & 0x0F;
+ /* isolate lower nibble */
+ ns10 = (spd_byte & 0x0F);
+
+ return (ns * 100 + ns10 * 10);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NSto10PS (unsigned char spd_byte)
+{
+ return (spd_byte * 100);
+}
+
+#ifdef CONFIG_ZUMA_V2
+static int check_dimm (uchar slot, sdram_info_t * info)
+{
+ /* assume 2 dimms, 2 banks each 256M - we dont have an
+ * dimm i2c so rely on the detection routines later */
+
+ memset (info, 0, sizeof (*info));
+
+ info->slot = slot;
+ info->banks = 2; /* Detect later */
+ info->registered = 0;
+ info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit
+ but doesn't matter, both do same
+ thing in setup_sdram() */
+ info->tpar = 3;
+ info->tras_clocks = 5;
+ info->burst_len = 4;
+#ifdef CONFIG_ECC
+ info->ecc = 0; /* Detect later */
+#endif /* CONFIG_ECC */
+ return 0;
+}
+
+#elif defined(CONFIG_P3G4)
+
+static int check_dimm (uchar slot, sdram_info_t * info)
+{
+ memset (info, 0, sizeof (*info));
+
+ if (slot)
+ return 0;
+
+ info->slot = slot;
+ info->banks = 1;
+ info->registered = 0;
+ info->drb_size = 4;
+ info->tpar = 3;
+ info->tras_clocks = 6;
+ info->burst_len = 4;
+#ifdef CONFIG_ECC
+ info->ecc = 2;
+#endif
+ return 0;
+}
+
+#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */
+
+/* This code reads the SPD chip on the sdram and populates
+ * the array which is passed in with the relevant information */
+static int check_dimm (uchar slot, sdram_info_t * info)
+{
+ uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
+ int ret;
+ uchar rows, cols, sdram_banks, supp_cal, width, cal_val;
+ ulong tmemclk;
+ uchar trp_clocks, trcd_clocks;
+ uchar data[128];
+
+ get_clocks ();
+
+ tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */
+
+#ifdef CONFIG_EVB64260_750CX
+ if (0 != slot) {
+ printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
+ printf (" called with slot=%d insetad!\n", slot);
+ return 0;
+ }
+#endif
+ DP (puts ("before i2c read\n"));
+
+ ret = i2c_read (addr, 0, 128, data, 0);
+
+ DP (puts ("after i2c read\n"));
+
+ /* zero all the values */
+ memset (info, 0, sizeof (*info));
+
+ if (ret) {
+ DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
+ return 0;
+ }
+
+ /* first, do some sanity checks */
+ if (data[2] != 0x4) {
+ printf ("Not SDRAM in slot %d\n", slot);
+ return 0;
+ }
+
+ /* get various information */
+ rows = data[3];
+ cols = data[4];
+ info->banks = data[5];
+ sdram_banks = data[17];
+ width = data[13] & 0x7f;
+
+ DP (printf
+ ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
+
+ /* check if the memory is registered */
+ if (data[21] & (BIT1 | BIT4))
+ info->registered = 1;
+
+#ifdef CONFIG_ECC
+ /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
+ info->ecc = (data[11] & 2) >> 1;
+#endif
+
+ /* bit 1 is CL2, bit 2 is CL3 */
+ supp_cal = (data[18] & 0x6) >> 1;
+
+ /* compute the relevant clock values */
+ trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk;
+ trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk;
+ info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk;
+
+ DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
+ trp_clocks, trcd_clocks, info->tras_clocks));
+
+ /* try a CAS latency of 3 first... */
+ cal_val = 0;
+ if (supp_cal & 3) {
+ if (NS10to10PS (data[9]) <= tmemclk)
+ cal_val = 3;
+ }
+
+ /* then 2... */
+ if (supp_cal & 2) {
+ if (NS10to10PS (data[23]) <= tmemclk)
+ cal_val = 2;
+ }
+
+ DP (printf ("cal_val = %d\n", cal_val));
+
+ /* bummer, did't work... */
+ if (cal_val == 0) {
+ DP (printf ("Couldn't find a good CAS latency\n"));
+ return 0;
+ }
+
+ /* get the largest delay -- these values need to all be the same
+ * see Res#6 */
+ info->tpar = cal_val;
+ if (trp_clocks > info->tpar)
+ info->tpar = trp_clocks;
+ if (trcd_clocks > info->tpar)
+ info->tpar = trcd_clocks;
+
+ DP (printf ("tpar set to: %d\n", info->tpar));
+
+#ifdef CONFIG_SYS_BROKEN_CL2
+ if (info->tpar == 2) {
+ info->tpar = 3;
+ DP (printf ("tpar fixed-up to: %d\n", info->tpar));
+ }
+#endif
+ /* compute the module DRB size */
+ info->drb_size =
+ (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
+
+ DP (printf ("drb_size set to: %d\n", info->drb_size));
+
+ /* find the burst len */
+ info->burst_len = data[16] & 0xf;
+ if ((info->burst_len & 8) == 8) {
+ info->burst_len = 1;
+ } else if ((info->burst_len & 4) == 4) {
+ info->burst_len = 0;
+ } else {
+ return 0;
+ }
+
+ info->slot = slot;
+ return 0;
+}
+#endif /* ! CONFIG_ZUMA_V2 */
+
+static int setup_sdram_common (sdram_info_t info[2])
+{
+ ulong tmp;
+ int tpar = 2, tras_clocks = 5, registered = 1;
+ __maybe_unused int ecc = 2;
+
+ if (!info[0].banks && !info[1].banks)
+ return 0;
+
+ if (info[0].banks) {
+ if (info[0].tpar > tpar)
+ tpar = info[0].tpar;
+ if (info[0].tras_clocks > tras_clocks)
+ tras_clocks = info[0].tras_clocks;
+ if (!info[0].registered)
+ registered = 0;
+ if (info[0].ecc != 2)
+ ecc = 0;
+ }
+
+ if (info[1].banks) {
+ if (info[1].tpar > tpar)
+ tpar = info[1].tpar;
+ if (info[1].tras_clocks > tras_clocks)
+ tras_clocks = info[1].tras_clocks;
+ if (!info[1].registered)
+ registered = 0;
+ if (info[1].ecc != 2)
+ ecc = 0;
+ }
+
+ /* SDRAM configuration */
+ tmp = GTREGREAD (SDRAM_CONFIGURATION);
+
+ /* Turn on physical interleave if both DIMMs
+ * have even numbers of banks. */
+ if ((info[0].banks == 0 || info[0].banks == 2) &&
+ (info[1].banks == 0 || info[1].banks == 2)) {
+ /* physical interleave on */
+ tmp &= ~(1 << 15);
+ } else {
+ /* physical interleave off */
+ tmp |= (1 << 15);
+ }
+
+ tmp |= (registered << 17);
+
+ /* Use buffer 1 to return read data to the CPU
+ * See Res #12 */
+ tmp |= (1 << 26);
+
+ GT_REG_WRITE (SDRAM_CONFIGURATION, tmp);
+ DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION)));
+
+ /* SDRAM timing */
+ tmp = (((tpar == 3) ? 2 : 1) |
+ (((tpar == 3) ? 2 : 1) << 2) |
+ (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8));
+
+#ifdef CONFIG_ECC
+ /* Setup ECC */
+ if (ecc == 2)
+ tmp |= 1 << 13;
+#endif /* CONFIG_ECC */
+
+ GT_REG_WRITE (SDRAM_TIMING, tmp);
+ DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
+ GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks));
+
+ /* SDRAM address decode register */
+ /* program this with the default value */
+ GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2);
+ DP (printf ("SDRAM decode: %08x\n",
+ GTREGREAD (SDRAM_ADDRESS_DECODE)));
+
+ return 0;
+}
+
+/* sets up the GT properly with information passed in */
+static int setup_sdram (sdram_info_t * info)
+{
+ ulong tmp;
+ ulong *addr = 0;
+ __maybe_unused ulong check;
+ int i;
+
+ /* sanity checking */
+ if (!info->banks)
+ return 0;
+
+ /* ---------------------------- */
+ /* Program the GT with the discovered data */
+
+ /* bank parameters */
+ tmp = (0xf << 16); /* leave all virt bank pages open */
+
+ DP (printf ("drb_size: %d\n", info->drb_size));
+ switch (info->drb_size) {
+ case 1:
+ tmp |= (1 << 14);
+ break;
+ case 4:
+ case 8:
+ tmp |= (2 << 14);
+ break;
+ case 16:
+ case 32:
+ tmp |= (3 << 14);
+ break;
+ default:
+ printf ("Error in dram size calculation\n");
+ return 1;
+ }
+
+ /* SDRAM bank parameters */
+ /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
+ GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
+ GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
+ DP (printf
+ ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot,
+ info->slot * 2, (info->slot * 2) + 1, tmp));
+
+ /* set the SDRAM configuration for each bank */
+ for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
+ DP (printf ("*** Running a MRS cycle for bank %d ***\n", i));
+
+ /* map the bank */
+ memory_map_bank (i, 0, GB / 4);
+
+ /* set SDRAM mode */
+ GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3);
+ check = GTREGREAD (SDRAM_OPERATION_MODE);
+
+ /* dummy write */
+ *addr = 0;
+
+ /* wait for the command to complete */
+ while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0);
+
+ /* switch back to normal operation mode */
+ GT_REG_WRITE (SDRAM_OPERATION_MODE, 0);
+ check = GTREGREAD (SDRAM_OPERATION_MODE);
+
+ /* unmap the bank */
+ memory_map_bank (i, 0, 0);
+ DP (printf ("*** MRS cycle for bank %d done ***\n", i));
+ }
+
+ return 0;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+static long int dram_size (long int *base, long int maxsize)
+{
+ volatile long int *addr, *b = base;
+ long int cnt, val, save1, save2;
+
+#define STARTVAL (1<<20) /* start test at 1M */
+ for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
+ cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ save1 = *addr; /* save contents of addr */
+ save2 = *b; /* save contents of base */
+
+ *addr = cnt; /* write cnt to addr */
+ *b = 0; /* put null at base */
+
+ /* check at base address */
+ if ((*b) != 0) {
+ *addr = save1; /* restore *addr */
+ *b = save2; /* restore *b */
+ return (0);
+ }
+ val = *addr; /* read *addr */
+
+ *addr = save1;
+ *b = save2;
+
+ if (val != cnt) {
+ /* fix boundary condition.. STARTVAL means zero */
+ if (cnt == STARTVAL / sizeof (long))
+ cnt = 0;
+ return (cnt * sizeof (long));
+ }
+ }
+ return maxsize;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* U-Boot interface function to SDRAM init - this is where all the
+ * controlling logic happens */
+phys_size_t initdram (int board_type)
+{
+ ulong checkbank[4] = {[0 ... 3] = 0 };
+ int bank_no;
+ ulong total;
+ int nhr;
+ sdram_info_t dimm_info[2];
+
+
+ /* first, use the SPD to get info about the SDRAM */
+
+ /* check the NHR bit and skip mem init if it's already done */
+ nhr = get_hid0 () & (1 << 16);
+
+ if (nhr) {
+ printf ("Skipping SDRAM setup due to NHR bit being set\n");
+ } else {
+ /* DIMM0 */
+ check_dimm (0, &dimm_info[0]);
+
+ /* DIMM1 */
+#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
+ check_dimm (1, &dimm_info[1]);
+#else /* CONFIG_EVB64260_750CX */
+ memset (&dimm_info[1], 0, sizeof (sdram_info_t));
+#endif
+
+ /* unmap all banks */
+ memory_map_bank (0, 0, 0);
+ memory_map_bank (1, 0, 0);
+ memory_map_bank (2, 0, 0);
+ memory_map_bank (3, 0, 0);
+
+ /* Now, program the GT with the correct values */
+ if (setup_sdram_common (dimm_info)) {
+ printf ("Setup common failed.\n");
+ }
+
+ if (setup_sdram (&dimm_info[0])) {
+ printf ("Setup for DIMM1 failed.\n");
+ }
+
+ if (setup_sdram (&dimm_info[1])) {
+ printf ("Setup for DIMM2 failed.\n");
+ }
+
+ /* set the NHR bit */
+ set_hid0 (get_hid0 () | (1 << 16));
+ }
+ /* next, size the SDRAM banks */
+
+ total = 0;
+ if (dimm_info[0].banks > 0)
+ checkbank[0] = 1;
+ if (dimm_info[0].banks > 1)
+ checkbank[1] = 1;
+ if (dimm_info[0].banks > 2)
+ printf ("Error, SPD claims DIMM1 has >2 banks\n");
+
+ if (dimm_info[1].banks > 0)
+ checkbank[2] = 1;
+ if (dimm_info[1].banks > 1)
+ checkbank[3] = 1;
+ if (dimm_info[1].banks > 2)
+ printf ("Error, SPD claims DIMM2 has >2 banks\n");
+
+ /* Generic dram sizer: works even if we don't have i2c DIMMs,
+ * as long as the timing settings are more or less correct */
+
+ /*
+ * pass 1: size all the banks, using first bat (0-256M)
+ * limitation: we only support 256M per bank due to
+ * us only having 1 BAT for all DRAM
+ */
+ for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
+ /* skip over banks that are not populated */
+ if (!checkbank[bank_no])
+ continue;
+
+ DP (printf ("checking bank %d\n", bank_no));
+
+ memory_map_bank (bank_no, 0, GB / 4);
+ checkbank[bank_no] = dram_size (NULL, GB / 4);
+ memory_map_bank (bank_no, 0, 0);
+
+ DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no]));
+ }
+
+ /*
+ * pass 2: contiguously map each bank into physical address
+ * space.
+ */
+ dimm_info[0].banks = dimm_info[1].banks = 0;
+ for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
+ if (!checkbank[bank_no])
+ continue;
+
+ dimm_info[bank_no / 2].banks++;
+ dimm_info[bank_no / 2].size += checkbank[bank_no];
+
+ memory_map_bank (bank_no, total, checkbank[bank_no]);
+#ifdef MAP_PCI
+ memory_map_bank_pci (bank_no, total, checkbank[bank_no]);
+#endif
+ total += checkbank[bank_no];
+ }
+
+#ifdef CONFIG_ECC
+#ifdef CONFIG_ZUMA_V2
+ /*
+ * We always enable ECC when bank 2 and 3 are unpopulated
+ * If we 2 or 3 are populated, we CAN'T support ECC.
+ * (Zuma boards only support ECC in banks 0 and 1; assume that
+ * in that configuration, ECC chips are mounted, even for stacked
+ * chips)
+ */
+ if (checkbank[2] == 0 && checkbank[3] == 0) {
+ dimm_info[0].ecc = 2;
+ GT_REG_WRITE (SDRAM_TIMING,
+ GTREGREAD (SDRAM_TIMING) | (1 << 13));
+ /* TODO: do we have to run MRS cycles again? */
+ }
+#endif /* CONFIG_ZUMA_V2 */
+
+ if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) {
+ puts ("[ECC] ");
+ }
+#endif /* CONFIG_ECC */
+
+#ifdef DEBUG
+ dump_dimm_info (&dimm_info[0]);
+ dump_dimm_info (&dimm_info[1]);
+#endif
+ /* TODO: return at MOST 256M? */
+ /* return total > GB/4 ? GB/4 : total; */
+ return total;
+}
diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c
new file mode 100644
index 0000000..83a4217
--- /dev/null
+++ b/board/evb64260/serial.c
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * serial.c - serial support for the gal ev board
+ */
+
+/* supports both the 16650 duart and the MPSC */
+
+#include <common.h>
+#include <command.h>
+#include <galileo/memory.h>
+#include <serial.h>
+#include <linux/compiler.h>
+
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
+#include <ns16550.h>
+#endif
+
+#include "mpsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
+const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1,
+ (NS16550_t) CONFIG_SYS_NS16550_COM2 };
+#endif
+
+#ifdef CONFIG_MPSC
+
+static int evb64260_serial_init(void)
+{
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
+ int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
+#endif
+
+ mpsc_init(gd->baudrate);
+
+ /* init the DUART chans so that KGDB in the kernel can use them */
+#ifdef CONFIG_SYS_INIT_CHAN1
+ NS16550_reinit(COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+ NS16550_reinit(COM_PORTS[1], clock_divisor);
+#endif
+ return (0);
+}
+
+static void evb64260_serial_putc(const char c)
+{
+ if (c == '\n')
+ mpsc_putchar('\r');
+
+ mpsc_putchar(c);
+}
+
+static int evb64260_serial_getc(void)
+{
+ return mpsc_getchar();
+}
+
+static int evb64260_serial_tstc(void)
+{
+ return mpsc_test_char();
+}
+
+static void evb64260_serial_setbrg(void)
+{
+ galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate);
+}
+
+#else /* ! CONFIG_MPSC */
+
+static int evb64260_serial_init(void)
+{
+ int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
+
+#ifdef CONFIG_SYS_INIT_CHAN1
+ (void)NS16550_init(COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+ (void)NS16550_init(COM_PORTS[1], clock_divisor);
+#endif
+
+ return (0);
+}
+
+static void evb64260_serial_putc(const char c)
+{
+ if (c == '\n')
+ NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
+
+ NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
+}
+
+static int evb64260_serial_getc(void)
+{
+ return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
+}
+
+static int evb64260_serial_tstc(void)
+{
+ return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
+}
+
+static void evb64260_serial_setbrg(void)
+{
+ int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
+
+#ifdef CONFIG_SYS_INIT_CHAN1
+ NS16550_reinit(COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CONFIG_SYS_INIT_CHAN2
+ NS16550_reinit(COM_PORTS[1], clock_divisor);
+#endif
+}
+
+#endif /* CONFIG_MPSC */
+
+static struct serial_device evb64260_serial_drv = {
+ .name = "evb64260_serial",
+ .start = evb64260_serial_init,
+ .stop = NULL,
+ .setbrg = evb64260_serial_setbrg,
+ .putc = evb64260_serial_putc,
+ .puts = default_serial_puts,
+ .getc = evb64260_serial_getc,
+ .tstc = evb64260_serial_tstc,
+};
+
+void evb64260_serial_initialize(void)
+{
+ serial_register(&evb64260_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &evb64260_serial_drv;
+}
+
+#if defined(CONFIG_CMD_KGDB)
+void
+kgdb_serial_init(void)
+{
+}
+
+void
+putDebugChar (int c)
+{
+ serial_putc (c);
+}
+
+void
+putDebugStr (const char *str)
+{
+ serial_puts (str);
+}
+
+int
+getDebugChar (void)
+{
+ return serial_getc();
+}
+
+void
+kgdb_interruptible (int yes)
+{
+ return;
+}
+#endif
diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds
new file mode 100644
index 0000000..712df6d
--- /dev/null
+++ b/board/evb64260/u-boot.lds
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/powerpc/cpu/74xx_7xx/start.o (.text*)
+ *(.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.ppcenv*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/evb64260/zuma_pbb.c b/board/evb64260/zuma_pbb.c
new file mode 100644
index 0000000..aa15fa0
--- /dev/null
+++ b/board/evb64260/zuma_pbb.c
@@ -0,0 +1,220 @@
+#include <common.h>
+#include <malloc.h>
+
+#if defined(CONFIG_CMD_BSP)
+#include <command.h>
+#endif
+
+#include <pci.h>
+#include <galileo/pci.h>
+#include "zuma_pbb.h"
+
+#undef DEBUG
+
+#define PAT_LO 0x00010203
+#define PAT_HI 0x04050607
+
+static PBB_DMA_REG_MAP *zuma_pbb_reg = NULL;
+static char test_buf1[2048];
+static char test_buf2[2048];
+void zuma_init_pbb(void);
+int zuma_mbox_init(void);
+int zuma_test_dma(int cmd, int size);
+
+int zuma_test_dma (int cmd, int size)
+{
+ static const char *const test_legend[] = {
+ "write", "verify",
+ "copy", "compare",
+ "write inc", "verify inc"
+ };
+ register int i, j;
+ unsigned int p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff);
+ unsigned int p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff);
+ volatile unsigned int *ps = (unsigned int *) p1;
+ volatile unsigned int *pd = (unsigned int *) p2;
+ unsigned int funct, pat_lo = PAT_LO, pat_hi = PAT_HI;
+ DMA_INT_STATUS stat;
+ int ret = 0;
+
+ if (!zuma_pbb_reg) {
+ printf ("not initted\n");
+ return -1;
+ }
+
+ if (cmd < 0 || cmd > 5) {
+ printf ("inv cmd %d\n", cmd);
+ return -1;
+ }
+
+ if (cmd == 2 || cmd == 3) {
+ /* not implemented */
+ return 0;
+ }
+
+ if (size <= 0 || size > 1024)
+ size = 1024;
+
+ size &= (~7); /* throw away bottom 3 bits */
+
+ p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff);
+ p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff);
+
+ memset ((void *) p1, 0, size);
+ memset ((void *) p2, 0, size);
+
+ for (i = 0; i < size / 4; i += 2) {
+ ps[i] = pat_lo;
+ ps[i + 1] = pat_hi;
+ if (cmd == 4 || cmd == 5) {
+ unsigned char *pl = (unsigned char *) &pat_lo;
+ unsigned char *ph = (unsigned char *) &pat_hi;
+
+ for (j = 0; j < 4; j++) {
+ pl[j] += 8;
+ ph[j] += 8;
+ }
+ }
+ }
+
+ funct = (1 << 31) | (cmd << 24) | (size);
+
+ zuma_pbb_reg->int_mask.pci_bits.chan0 =
+ EOF_RX_FLAG | EOF_TX_FLAG | EOB_TX_FLAG;
+
+ zuma_pbb_reg->debug_57 = PAT_LO; /* patl */
+ zuma_pbb_reg->debug_58 = PAT_HI; /* path */
+
+ zuma_pbb_reg->debug_54 = cpu_to_le32 (p1); /* src 0x01b0 */
+ zuma_pbb_reg->debug_55 = cpu_to_le32 (p2); /* dst 0x01b8 */
+ zuma_pbb_reg->debug_56 = cpu_to_le32 (funct); /* func, 0x01c0 */
+
+ /* give DMA time to chew on things.. dont use DRAM or PCI */
+ /* if you can avoid it. */
+ do {
+ for (i = 0; i < 1000 * 10; i++);
+ } while (le32_to_cpu (zuma_pbb_reg->debug_56) & (1 << 31));
+
+ stat.word = zuma_pbb_reg->status.word;
+ zuma_pbb_reg->int_mask.word = 0;
+
+ printf ("stat: %08x (%x)\n", stat.word, stat.pci_bits.chan0);
+
+ printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56));
+ printf ("src @%08x: %08x %08x %08x %08x\n", p1, ps[0], ps[1], ps[2],
+ ps[3]);
+ printf ("dst @%08x: %08x %08x %08x %08x\n", p2, pd[0], pd[1], pd[2],
+ pd[3]);
+ printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56));
+
+
+ if (cmd == 0 || cmd == 4) {
+ /* this is a write */
+ if (!(stat.pci_bits.chan0 & EOF_RX_FLAG) || /* not done */
+ (memcmp ((void *) ps, (void *) pd, size) != 0)) { /* cmp error */
+ for (i = 0; i < size / 4; i += 2) {
+ if ((ps[i] != pd[i]) || (ps[i + 1] != pd[i + 1])) {
+ printf ("s @%p:%08x %08x\n", &ps[i], ps[i], ps[i + 1]);
+ printf ("d @%p:%08x %08x\n", &pd[i], pd[i], pd[i + 1]);
+ }
+ }
+ ret = -1;
+ }
+ } else {
+ /* this is a verify */
+ if (!(stat.pci_bits.chan0 & EOF_TX_FLAG) || /* not done */
+ (stat.pci_bits.chan0 & EOB_TX_FLAG)) { /* cmp error */
+ printf ("%08x: %08x %08x\n",
+ le32_to_cpu (zuma_pbb_reg->debug_63),
+ zuma_pbb_reg->debug_61, zuma_pbb_reg->debug_62);
+ ret = -1;
+ }
+ }
+
+ printf ("%s cmd %d, %d bytes: %s!\n", test_legend[cmd], cmd, size,
+ (ret == 0) ? "PASSED" : "FAILED");
+ return 0;
+}
+
+void zuma_init_pbb (void)
+{
+ unsigned int iobase;
+ pci_dev_t dev =
+ pci_find_device (VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0);
+
+ if (dev == -1) {
+ printf ("no zuma pbb\n");
+ return;
+ }
+
+ pci_read_config_dword (dev, PCI_BASE_ADDRESS_0, &iobase);
+
+ iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+
+ zuma_pbb_reg = (PBB_DMA_REG_MAP *)iobase;
+
+
+ if (!zuma_pbb_reg) {
+ printf ("zuma pbb bar none! (hah hah, get it?)\n");
+ return;
+ }
+
+ zuma_pbb_reg->int_mask.word = 0;
+
+ printf ("pbb @ %p v%d.%d, timestamp %08x\n", zuma_pbb_reg,
+ zuma_pbb_reg->version.pci_bits.rev_major,
+ zuma_pbb_reg->version.pci_bits.rev_minor,
+ zuma_pbb_reg->timestamp);
+
+}
+
+#if defined(CONFIG_CMD_BSP)
+
+static int last_cmd = 4; /* write increment */
+static int last_size = 64;
+
+int
+do_zuma_init_pbb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ zuma_init_pbb ();
+ return 0;
+}
+
+int
+do_zuma_test_dma (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc > 1) {
+ last_cmd = simple_strtoul (argv[1], NULL, 10);
+ }
+ if (argc > 2) {
+ last_size = simple_strtoul (argv[2], NULL, 10);
+ }
+ zuma_test_dma (last_cmd, last_size);
+ return 0;
+}
+
+int
+do_zuma_init_mbox (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ zuma_mbox_init ();
+ return 0;
+}
+
+U_BOOT_CMD(
+ zinit, 1, 0, do_zuma_init_pbb,
+ "init zuma pbb",
+ "\n"
+);
+U_BOOT_CMD(
+ zdtest, 3, 1, do_zuma_test_dma,
+ "run dma test",
+ "[cmd [count]]\n"
+ " - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes"
+);
+U_BOOT_CMD(
+ zminit, 1, 0, do_zuma_init_mbox,
+ "init zuma mbox",
+ "\n"
+);
+
+#endif
diff --git a/board/evb64260/zuma_pbb.h b/board/evb64260/zuma_pbb.h
new file mode 100644
index 0000000..300b2fe
--- /dev/null
+++ b/board/evb64260/zuma_pbb.h
@@ -0,0 +1,346 @@
+#ifndef ZUMA_PBB_H
+#define ZUMA_PBB_H
+
+#define MAX_NUM_BUFFER_PER_RING 32
+
+#ifdef __BIG_ENDIAN
+#define cpu_bits _be_s_bits /* use with le32_to_cpu only */
+#define pci_bits _be_bits /* may contain swapped bytes,
+ but dont need le32_to_cpu */
+#endif
+
+#ifdef __LITTLE_ENDIAN
+#define cpu_bits _le_bits
+#define pci_bits _le_bits
+#endif
+
+#define VENDOR_ID_ZUMA 0x1172
+#define DEVICE_ID_ZUMA_PBB 0x0004
+
+#define RXDBP(chan) (&sip->rx_desc[chan].base) /* ch*8 */
+#define RXDP(chan) (&sip->rx_desc[chan].current) /* ch*8 + 4 */
+#define TXDBP(chan) (&sip->tx_desc[chan].base) /* ch*8 + 64 */
+#define TXDP(chan) (&sip->tx_desc[chan].current) /* ch*8 + 68 */
+
+#define PBB_DMA_OWN_BIT 0x80000000
+#define PBB_DMA_LAST_BIT 0x40000000
+
+#define EOF_RX_FLAG 1 /* bit 0 */
+#define EOB_RX_FLAG 2 /* bit 1 */
+#define EOF_TX_FLAG 4 /* bit 2 */
+#define EOB_TX_FLAG 8 /* bit 3 */
+
+#define TX_MODE(m) (((m)&7) << 16)
+
+#define RX_DESC(i) (cs->rx_desc[i])
+#define TX_DESC(i) (cs->tx_desc[i])
+
+#define RX_CONTROL(i) (RX_DESC(i).control.word)
+#define RX_CONTROL_SIZE(i) (RX_DESC(i).control.rx.size)
+#define TX_CONTROL(i) (TX_DESC(i).control.word)
+
+#define RX_DATA_P(i) (&RX_DESC(i).ptr)
+#define TX_DATA_P(i) (&TX_DESC(i).ptr)
+
+typedef volatile unsigned char V8;
+typedef volatile unsigned short V16;
+typedef volatile unsigned int V32;
+
+/* RAM descriptor layout */
+typedef struct _tag_dma_descriptor {
+ V32 ptr;
+ union {
+ struct {
+ V32 owner:1;
+ V32 last:1;
+ V32 reserved0: 10;
+ V32 tx_mode: 4;
+
+ V32 reserved1: 5;
+ V32 size: 11;
+ } tx;
+ struct {
+ V32 owner:1;
+ V32 last:1;
+ V32 reserved0: 14;
+
+ V32 reserved1: 5;
+ V32 size: 11;
+ } rx;
+ V32 word;
+ } control;
+} DMA_DESCRIPTOR;
+
+/*
+ * NOTE: DO NOT USE structure to write non-word values... all registers
+ * MUST be written 4 bytes at a time in SI version 0.
+ * Non-word writes will result in "unaccessed" bytes written as zero.
+ *
+ * Byte reads are allowed.
+ *
+ * V32 pads are because the registers are spaced every 8 bytes (64 bits)
+ *
+ */
+
+/* NOTE!!! 4 dwords */
+typedef struct _tag_dma_descriptor_ring {
+ DMA_DESCRIPTOR *base;
+ V32 pad1; /* skip high dword */
+ volatile DMA_DESCRIPTOR *current;
+ V32 pad3; /* skip high dword */
+} DMA_DESCRIPTOR_RING;
+
+/* 1 dword */
+typedef union _tag_dma_generic {
+ struct { /* byte 3 2 1 0 */
+ V32 chan7:4; /* bits 31-28 */
+ V32 chan6:4; /* bits 27-24 */
+ V32 chan5:4; /* bits 23-20 */
+ V32 chan4:4; /* bits 19-16 */
+ V32 chan3:4; /* bits 15-12 */
+ V32 chan2:4; /* bits 11-8 */
+ V32 chan1:4; /* bits 7-4 */
+ V32 chan0:4; /* bits 3-0 */
+ } _be_s_bits;
+ struct { /* byte 0 1 2 3 */
+ V32 chan1:4; /* bits 7-4 */
+ V32 chan0:4; /* bits 3-0 */
+ V32 chan3:4; /* bits 15-12 */
+ V32 chan2:4; /* bits 11-8 */
+ V32 chan5:4; /* bits 23-20 */
+ V32 chan4:4; /* bits 19-16 */
+ V32 chan7:4; /* bits 31-28 */
+ V32 chan6:4; /* bits 27-24 */
+ } _be_bits;
+ struct { /* byte 0 1 2 3 */
+ V32 chan0:4; /* bits 0-3 */
+ V32 chan1:4; /* bits 4-7 */
+ V32 chan2:4; /* bits 8-11 */
+ V32 chan3:4; /* bits 12-15 */
+ V32 chan4:4; /* bits 16-19 */
+ V32 chan5:4; /* bits 20-23 */
+ V32 chan6:4; /* bits 24-27 */
+ V32 chan7:4; /* bits 28-31 */
+ } _le_bits;
+ V8 byte[4];
+ V32 word;
+} DMA_RXTX_ENABLE, DMA_RX_DELETE,
+ DMA_INT_STATUS, DMA_INT_MASK,
+ DMA_RX_LEVEL_STATUS, DMA_RX_LEVEL_INT_MASK;
+
+/* 1 dword */
+typedef union _tag_dma_rx_timer{
+ struct {
+ V32 res0:8; /* bits 32-24 */
+ V32 res1:7; /* bits 23-17 */
+ V32 enable:1; /* bit 16 */
+ V32 value:16; /* bits 15-0 */
+ } _be_s_bits;
+ struct {
+ /* crosses byte boundary. must use swap. */
+ V32 s_value:16; /* bits 7-0,15-8 */
+ V32 enable:1; /* bit 16 */
+ V32 res1:7; /* bits 23-17 */
+ V32 res0:8; /* bits 32-24 */
+ } _be_bits;
+ struct {
+ V32 value:16; /* bits 0-15 */
+ V32 enable:1; /* bit 16 */
+ V32 res1:7; /* bits 17-23 */
+ V32 res0:8; /* bits 24-32 */
+ } _le_bits;
+ V8 byte[4];
+ V32 word;
+} DMA_RX_TIMER;
+
+/* NOTE!!!: 2 dwords */
+typedef struct _tag_dma_desc_level{
+ union {
+ struct {
+ V32 res1:8; /* bits 31-24 */
+ V32 res0:7; /* bits 23-17 */
+ V32 write:1; /* bit 16 */
+ V32 thresh:8; /* bits 15-8 */
+ V32 level:8; /* bits 7-0 */
+ } _be_s_bits;
+ struct {
+ V32 level:8; /* bits 7-0 */
+ V32 thresh:8; /* bits 15-8 */
+ V32 res0:7; /* bits 30-17 */
+ V32 write:1; /* bit 16 */
+ V32 res1:8; /* bits 31-24 */
+ } _be_bits;
+ struct {
+ V32 level:8; /* bits 0-7 */
+ V32 thresh:8; /* bits 8-15 */
+ V32 write:1; /* bit 16 */
+ V32 res0:7; /* bit 17-30 */
+ V32 res1:8; /* bits 24-31 */
+ } _le_bits;
+ V8 byte[4];
+ V32 word;
+ } desc;
+ V32 pad1;
+} DMA_DESC_LEVEL;
+
+typedef struct _tag_pbb_dma_reg_map {
+ /* 0-15 (0x000-0x078) */
+ DMA_DESCRIPTOR_RING rx_desc[8]; /* 4 dwords each, 128 bytes tot. */
+
+ /* 16-31 (0x080-0x0f8) */
+ DMA_DESCRIPTOR_RING tx_desc[8]; /* 4 dwords each, 128 bytes tot. */
+
+ /* 32/33 (0x100/0x108) */
+ V32 reserved_32;
+ V32 pad_32;
+ V32 reserved_33;
+ V32 pad_33;
+
+ /* 34 (0x110) */
+ DMA_RXTX_ENABLE rxtx_enable;
+ V32 pad_34;
+
+ /* 35 (0x118) */
+ DMA_RX_DELETE rx_delete;
+ V32 pad_35;
+
+ /* 36-38 (0x120-0x130) */
+ DMA_INT_STATUS status;
+ V32 pad_36;
+ DMA_INT_STATUS last_status;
+ V32 pad_37;
+ DMA_INT_MASK int_mask;
+ V32 pad_38;
+
+ /* 39/40 (0x138/0x140) */
+ union {
+ /* NOTE!! 4 dwords */
+ struct {
+ V32 channel_3:8;
+ V32 channel_2:8;
+ V32 channel_1:8;
+ V32 channel_0:8;
+ V32 pad1;
+ V32 channel_7:8;
+ V32 channel_6:8;
+ V32 channel_5:8;
+ V32 channel_4:8;
+ V32 pad3;
+ } _be_s_bits;
+ struct {
+ V32 channel_0:8;
+ V32 channel_1:8;
+ V32 channel_2:8;
+ V32 channel_3:8;
+ V32 pad1;
+ V32 channel_4:8;
+ V32 channel_5:8;
+ V32 channel_6:8;
+ V32 channel_7:8;
+ V32 pad3;
+ } _be_bits, _le_bits;
+ V8 byte[16];
+ V32 word[4];
+ } rx_size;
+
+ /* 41/42 (0x148/0x150) */
+ V32 reserved_41;
+ V32 pad_41;
+ V32 reserved_42;
+ V32 pad_42;
+
+ /* 43/44 (0x158/0x160) */
+ DMA_RX_LEVEL_STATUS rx_level_status;
+ V32 pad_43;
+ DMA_RX_LEVEL_INT_MASK rx_level_int_mask;
+ V32 pad_44;
+
+ /* 45 (0x168) */
+ DMA_RX_TIMER rx_timer;
+ V32 pad_45;
+
+ /* 46 (0x170) */
+ V32 reserved_46;
+ V32 pad_46;
+
+ /* 47 (0x178) */
+ V32 mbox_status;
+ V32 pad_47;
+
+ /* 48/49 (0x180/0x188) */
+ V32 mbox_out;
+ V32 pad_48;
+ V32 mbox_in;
+ V32 pad_49;
+
+ /* 50 (0x190) */
+ V32 config;
+ V32 pad_50;
+
+ /* 51/52 (0x198/0x1a0) */
+ V32 c2a_ctr;
+ V32 pad_51;
+ V32 a2c_ctr;
+ V32 pad_52;
+
+ /* 53 (0x1a8) */
+ union {
+ struct {
+ V32 rev_major:8; /* bits 31-24 */
+ V32 rev_minor:8; /* bits 23-16 */
+ V32 reserved:16; /* bits 15-0 */
+ } _be_s_bits;
+ struct {
+ V32 s_reserved:16; /* bits 7-0, 15-8 */
+ V32 rev_minor:8; /* bits 23-16 */
+ V32 rev_major:8; /* bits 31-24 */
+ } _be_bits;
+ struct {
+ V32 reserved:16; /* bits 0-15 */
+ V32 rev_minor:8; /* bits 16-23 */
+ V32 rev_major:8; /* bits 24-31 */
+ } _le_bits;
+ V8 byte[4];
+ V32 word;
+ } version;
+ V32 pad_53;
+
+ /* 54-59 (0x1b0-0x1d8) */
+ V32 debug_54;
+ V32 pad_54;
+ V32 debug_55;
+ V32 pad_55;
+ V32 debug_56;
+ V32 pad_56;
+ V32 debug_57;
+ V32 pad_57;
+ V32 debug_58;
+ V32 pad_58;
+ V32 debug_59;
+ V32 pad_59;
+
+ /* 60 (0x1e0) */
+ V32 timestamp;
+ V32 pad_60;
+
+ /* 61-63 (0x1e8-0x1f8) */
+ V32 debug_61;
+ V32 pad_61;
+ V32 debug_62;
+ V32 pad_62;
+ V32 debug_63;
+ V32 pad_63;
+
+ /* 64-71 (0x200 - 0x238) */
+ DMA_DESC_LEVEL rx_desc_level[8]; /* 2 dwords each, 32 bytes tot. */
+
+ /* 72-98 (0x240 - 0x2f8) */
+ /* reserved */
+
+ /* 96-127 (0x300 - 0x3f8) */
+ /* mirrors (0x100 - 0x1f8) */
+
+} PBB_DMA_REG_MAP;
+
+
+#endif /* ZUMA_PBB_H */
diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c
new file mode 100644
index 0000000..621c64c
--- /dev/null
+++ b/board/evb64260/zuma_pbb_mbox.c
@@ -0,0 +1,208 @@
+#include <common.h>
+#include <galileo/pci.h>
+#include <net.h>
+#include <pci.h>
+
+#include "zuma_pbb.h"
+#include "zuma_pbb_mbox.h"
+
+
+struct _zuma_mbox_dev zuma_mbox_dev;
+
+
+static int zuma_mbox_write(struct _zuma_mbox_dev *dev, unsigned int data)
+{
+ unsigned int status, count = 0, i;
+
+ status = (volatile int) le32_to_cpu(dev->sip->mbox_status);
+
+ while ((status & OUT_PENDING) && count < 1000) {
+ count++;
+ for (i = 0; i < 1000; i++)
+ ;
+ status = (volatile int) le32_to_cpu(dev->sip->mbox_status);
+ }
+ if (count < 1000) {
+ /* if SET it means msg pending */
+ /* printf("mbox real write %08x\n",data); */
+ dev->sip->mbox_out = cpu_to_le32(data);
+ return 4;
+ }
+
+ printf("mbox tx timeout\n");
+ return 0;
+}
+
+static int zuma_mbox_read(struct _zuma_mbox_dev *dev, unsigned int *data)
+{
+ unsigned int status, count = 0, i;
+
+ status = (volatile int) le32_to_cpu(dev->sip->mbox_status);
+
+ while (!(status & IN_VALID) && count < 1000) {
+ count++;
+ for (i = 0; i < 1000; i++)
+ ;
+ status = (volatile int) le32_to_cpu(dev->sip->mbox_status);
+ }
+ if (count < 1000) {
+ /* if SET it means msg pending */
+ *data = le32_to_cpu(dev->sip->mbox_in);
+ /*printf("mbox real read %08x\n", *data); */
+ return 4;
+ }
+ printf("mbox rx timeout\n");
+ return 0;
+}
+
+static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in)
+{
+ int ret;
+
+ ret = zuma_mbox_write(&zuma_mbox_dev, out);
+ /*printf("write 0x%08x (%d bytes)\n", out, ret); */
+ if (ret != 4)
+ return -1;
+ ret = zuma_mbox_read(&zuma_mbox_dev, in);
+ /*printf("read 0x%08x (%d bytes)\n", *in, ret); */
+ if (ret != 4)
+ return -1;
+ return 0;
+}
+
+
+#define RET_IF_FAILED(x) if ((x) == -1) return -1
+
+static int zuma_mbox_do_all_mailbox(void)
+{
+ unsigned int data_in;
+ unsigned short sdata_in;
+
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in));
+
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in));
+ memcpy(zuma_acc_mac + 2, &data_in, 4);
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in));
+ sdata_in = data_in & 0xffff;
+ memcpy(zuma_acc_mac, &sdata_in, 2);
+
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in));
+ zuma_ip = data_in;
+
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in));
+ zuma_slot_bac = data_in >> 3;
+
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in));
+ zuma_console_baud = data_in & 0xffff;
+ zuma_debug_baud = data_in >> 16;
+
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox
+ (ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in));
+ memcpy(zuma_prv_mac + 2, &data_in, 4);
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox
+ (ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in));
+ sdata_in = data_in & 0xffff;
+ memcpy(zuma_prv_mac, &sdata_in, 2);
+
+ RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in));
+
+ return 0;
+}
+
+
+static void zuma_mbox_dump(void)
+{
+ unsigned short s;
+ unsigned int i;
+
+ memcpy(&s, &zuma_acc_mac, sizeof(s));
+ memcpy(&i, &zuma_acc_mac[2], sizeof(i));
+ printf("ACC MAC=%04x%08x\n", s, i);
+
+ memcpy(&s, &zuma_prv_mac, sizeof(s));
+ memcpy(&s, &zuma_prv_mac[2], sizeof(i));
+ printf("PRV MAC=%04x%08x\n", s, i);
+
+ printf("slot:bac=%d:%d\n",
+ (zuma_slot_bac >> 2) & 0xf,
+ zuma_slot_bac & 0x3);
+
+ printf("BAUD1=%d BAUD2=%d\n",
+ zuma_console_baud,
+ zuma_debug_baud);
+}
+
+
+static void zuma_mbox_setenv(void)
+{
+ char *data, buf[32];
+ unsigned char save = 0;
+
+ data = getenv("baudrate");
+
+ if (!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) {
+ sprintf(buf, "%6d", zuma_console_baud);
+ setenv("baudrate", buf);
+ save = 1;
+ printf("baudrate doesn't match from mbox\n");
+ }
+
+ ip_to_string(zuma_ip, buf);
+ setenv("ipaddr", buf);
+
+ sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+ zuma_prv_mac[0],
+ zuma_prv_mac[1],
+ zuma_prv_mac[2],
+ zuma_prv_mac[3], zuma_prv_mac[4], zuma_prv_mac[5]);
+ setenv("ethaddr", buf);
+
+ sprintf(buf, "%02x", zuma_slot_bac);
+ setenv("bacslot", buf);
+
+ if (save)
+ saveenv();
+}
+
+/**
+ * zuma_mbox_init:
+ */
+
+int zuma_mbox_init(void)
+{
+ unsigned int iobase;
+
+ memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev));
+
+ zuma_mbox_dev.dev =
+ pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0);
+
+ if (zuma_mbox_dev.dev == -1) {
+ printf("no zuma pbb\n");
+ return -1;
+ }
+
+ pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase);
+
+ iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+
+ zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *) iobase;
+
+ zuma_mbox_dev.sip->int_mask.word = 0;
+
+ printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip,
+ zuma_mbox_dev.sip->version.pci_bits.rev_major,
+ zuma_mbox_dev.sip->version.pci_bits.rev_minor,
+ zuma_mbox_dev.sip->timestamp);
+
+ if (zuma_mbox_do_all_mailbox() == -1) {
+ printf("mailbox failed.. no ACC?\n");
+ return -1;
+ }
+
+ zuma_mbox_dump();
+
+ zuma_mbox_setenv();
+
+ return 0;
+}
diff --git a/board/evb64260/zuma_pbb_mbox.h b/board/evb64260/zuma_pbb_mbox.h
new file mode 100644
index 0000000..b4a4c0c
--- /dev/null
+++ b/board/evb64260/zuma_pbb_mbox.h
@@ -0,0 +1,43 @@
+#define IN_VALID 1
+#define OUT_PENDING 2
+
+enum {
+ ZUMA_MBOXMSG_DONE,
+ ZUMA_MBOXMSG_MACL,
+ ZUMA_MBOXMSG_MACH,
+ ZUMA_MBOXMSG_IP,
+ ZUMA_MBOXMSG_SLOT,
+ ZUMA_MBOXMSG_RESET,
+ ZUMA_MBOXMSG_BAUD,
+ ZUMA_MBOXMSG_START,
+ ZUMA_MBOXMSG_ENG_PRV_MACL,
+ ZUMA_MBOXMSG_ENG_PRV_MACH,
+
+ MBOXMSG_LAST
+};
+
+struct zuma_mailbox_info {
+ unsigned char acc_mac[6];
+ unsigned char prv_mac[6];
+ unsigned int ip;
+ unsigned int slot_bac;
+ unsigned int console_baud;
+ unsigned int debug_baud;
+};
+
+struct _zuma_mbox_dev {
+ pci_dev_t dev;
+ PBB_DMA_REG_MAP *sip;
+ struct zuma_mailbox_info mailbox;
+};
+
+#define zuma_prv_mac zuma_mbox_dev.mailbox.prv_mac
+#define zuma_acc_mac zuma_mbox_dev.mailbox.acc_mac
+#define zuma_ip zuma_mbox_dev.mailbox.ip
+#define zuma_slot_bac zuma_mbox_dev.mailbox.slot_bac
+#define zuma_console_baud zuma_mbox_dev.mailbox.console_baud
+#define zuma_debug_baud zuma_mbox_dev.mailbox.debug_baud
+
+
+extern struct _zuma_mbox_dev zuma_mbox_dev;
+extern int zuma_mbox_init (void);
diff --git a/board/faraday/a320evb/Kconfig b/board/faraday/a320evb/Kconfig
new file mode 100644
index 0000000..02c42cb
--- /dev/null
+++ b/board/faraday/a320evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_A320EVB
+
+config SYS_BOARD
+ default "a320evb"
+
+config SYS_VENDOR
+ default "faraday"
+
+config SYS_SOC
+ default "a320"
+
+config SYS_CONFIG_NAME
+ default "a320evb"
+
+endif
diff --git a/board/faraday/a320evb/MAINTAINERS b/board/faraday/a320evb/MAINTAINERS
new file mode 100644
index 0000000..f13b015
--- /dev/null
+++ b/board/faraday/a320evb/MAINTAINERS
@@ -0,0 +1,6 @@
+A320EVB BOARD
+M: Po-Yu Chuang <ratbert@faraday-tech.com>
+S: Maintained
+F: board/faraday/a320evb/
+F: include/configs/a320evb.h
+F: configs/a320evb_defconfig
diff --git a/board/faraday/a320evb/Makefile b/board/faraday/a320evb/Makefile
new file mode 100644
index 0000000..518ce3f
--- /dev/null
+++ b/board/faraday/a320evb/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := a320evb.o
+obj-y += lowlevel_init.o
diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c
new file mode 100644
index 0000000..c42635b
--- /dev/null
+++ b/board/faraday/a320evb/a320evb.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ ftsmc020_init(); /* initialize Flash */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_1;
+ unsigned long expected_size = PHYS_SDRAM_1_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->ram_size = actual_size;
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else
+ return 0;
+}
diff --git a/board/faraday/a320evb/lowlevel_init.S b/board/faraday/a320evb/lowlevel_init.S
new file mode 100644
index 0000000..d366260
--- /dev/null
+++ b/board/faraday/a320evb/lowlevel_init.S
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/macro.h>
+#include <faraday/ftsdmc020.h>
+
+/*
+ * parameters for the SDRAM controller
+ */
+#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
+#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
+#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
+#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
+#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
+
+#define TP0_D CONFIG_SYS_FTSDMC020_TP0
+#define TP1_D CONFIG_SYS_FTSDMC020_TP1
+#define CR_D1 FTSDMC020_CR_IPREC
+#define CR_D2 FTSDMC020_CR_ISMR
+#define CR_D3 FTSDMC020_CR_IREF
+
+#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
+ FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
+#define ACR_D FTSDMC020_ACR_TOC(0x18)
+
+/*
+ * numeric 7 segment display
+ */
+.macro led, num
+ write32 CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+.macro wait_sdram
+ ldr r0, =CONFIG_FTSDMC020_BASE
+1:
+ ldr r1, [r0, #FTSDMC020_OFFSET_CR]
+ cmp r1, #0
+ bne 1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+ mov r11, lr
+
+ led 0x0
+
+ bl init_sdmc
+
+ led 0x1
+
+ /* everything is fine now */
+ mov lr, r11
+ mov pc, lr
+
+/*
+ * memory initialization
+ */
+init_sdmc:
+ led 0x10
+
+ /* set SDRAM register */
+
+ write32 TP0_A, TP0_D
+ led 0x11
+
+ write32 TP1_A, TP1_D
+ led 0x12
+
+ /* set to precharge */
+ write32 CR_A, CR_D1
+ led 0x13
+
+ wait_sdram
+ led 0x14
+
+ /* set mode register */
+ write32 CR_A, CR_D2
+ led 0x15
+
+ wait_sdram
+ led 0x16
+
+ /* set to refresh */
+ write32 CR_A, CR_D3
+ led 0x17
+
+ wait_sdram
+ led 0x18
+
+ write32 B0_BSR_A, B0_BSR_D
+ led 0x19
+
+ write32 ACR_A, ACR_D
+ led 0x1a
+
+ mov pc, lr
diff --git a/board/freescale/b4860qds/Kconfig b/board/freescale/b4860qds/Kconfig
new file mode 100644
index 0000000..c7aab75
--- /dev/null
+++ b/board/freescale/b4860qds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_B4860QDS
+
+config SYS_BOARD
+ default "b4860qds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "B4860QDS"
+
+endif
diff --git a/board/freescale/b4860qds/MAINTAINERS b/board/freescale/b4860qds/MAINTAINERS
new file mode 100644
index 0000000..ac02bb7
--- /dev/null
+++ b/board/freescale/b4860qds/MAINTAINERS
@@ -0,0 +1,17 @@
+B4860QDS BOARD
+#M: -
+S: Maintained
+F: board/freescale/b4860qds/
+F: include/configs/B4860QDS.h
+F: configs/B4420QDS_defconfig
+F: configs/B4420QDS_NAND_defconfig
+F: configs/B4420QDS_SPIFLASH_defconfig
+F: configs/B4860QDS_defconfig
+F: configs/B4860QDS_NAND_defconfig
+F: configs/B4860QDS_SPIFLASH_defconfig
+F: configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+
+B4860QDS_SECURE_BOOT BOARD
+M: Aneesh Bansal <aneesh.bansal@freescale.com>
+S: Maintained
+F: configs/B4860QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
new file mode 100644
index 0000000..0acd2a9
--- /dev/null
+++ b/board/freescale/b4860qds/Makefile
@@ -0,0 +1,17 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += b4860qds.o
+obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o
+obj-$(CONFIG_PCI) += pci.o
+endif
+
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
new file mode 100644
index 0000000..6a8fca6
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -0,0 +1,1273 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/errno.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include <hwconfig.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "../common/idt8t49n222a_serdes_clk.h"
+#include "../common/zm7300.h"
+#include "b4860qds.h"
+#include "b4860qds_qixis.h"
+#include "b4860qds_crossbar_con.h"
+
+#define CLK_MUX_SEL_MASK 0x4
+#define ETH_PHY_CLK_OUT 0x4
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ char buf[64];
+ u8 sw;
+ struct cpu_type *cpu = gd->arch.cpu;
+ static const char *const freq[] = {"100", "125", "156.25", "161.13",
+ "122.88", "122.88", "122.88"};
+ int clock;
+
+ printf("Board: %sQDS, ", cpu->name);
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
+ QIXIS_READ(id), QIXIS_READ(arch));
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw >= 0x8 && sw <= 0xE)
+ puts("NAND\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
+ /*
+ * Display the actual SERDES reference clocks as configured by the
+ * dip switches on the board. Note that the SWx registers could
+ * technically be set to force the reference clocks to match the
+ * values that the SERDES expects (or vice versa). For now, however,
+ * we just display both values and hope the user notices when they
+ * don't match.
+ */
+ puts("SERDES Reference Clocks: ");
+ sw = QIXIS_READ(brdcfg[2]);
+ clock = (sw >> 5) & 7;
+ printf("Bank1=%sMHz ", freq[clock]);
+ sw = QIXIS_READ(brdcfg[4]);
+ clock = (sw >> 6) & 3;
+ printf("Bank2=%sMHz\n", freq[clock]);
+
+ return 0;
+}
+
+int select_i2c_ch_pca(u8 ch)
+{
+ int ret;
+
+ /* Selecting proper channel via PCA*/
+ ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
+ if (ret) {
+ printf("PCA: failed to select proper channel.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for 532us befor another reading
+ */
+#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
+#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
+
+static inline int read_voltage(void)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+
+ for (i = 0; i < NUM_READINGS; i++) {
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
+ if (ret) {
+ printf("VID: failed to read core voltage\n");
+ return ret;
+ }
+ if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+ /* LSB = 4mv */
+ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ return voltage_read;
+}
+
+static int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid;
+ int vdd_target, vdd_last;
+ int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
+ int ret;
+ unsigned int orig_i2c_speed;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.9875V */
+ 9750,
+ 9625,
+ 9500,
+ 9375,
+ 9250,
+ 9125,
+ 9000,
+ 8875,
+ 8750,
+ 8625,
+ 8500,
+ 8375,
+ 8250,
+ 8125,
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ printf("VID: I2c failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_be32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_VID_MASK;
+ if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+ }
+ vdd_target = vdd[vid];
+ debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
+ vid, vdd_target/10);
+
+ /* check override variable for overriding VDD */
+ vdd_string = getenv("b4qds_vdd_mv");
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+ if (vdd_override >= 819 && vdd_override <= 1212) {
+ vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+ debug("VDD override is %lu\n", vdd_override);
+ } else if (vdd_override != 0) {
+ printf("Invalid value.\n");
+ }
+
+ if (vdd_target == 0) {
+ printf("VID: VID not used\n");
+ ret = 0;
+ goto exit;
+ }
+
+ /*
+ * Read voltage monitor to check real voltage.
+ * Voltage monitor LSB is 4mv.
+ */
+ vdd_last = read_voltage();
+ if (vdd_last < 0) {
+ printf("VID: abort VID adjustment\n");
+ ret = -1;
+ goto exit;
+ }
+
+ debug("VID: Core voltage is at %d mV\n", vdd_last);
+ ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
+ if (ret) {
+ printf("VID: I2c failed to switch channel to DPM\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* Round up to the value of step of Voltage regulator */
+ voltage = roundup(vdd_target, ZM_STEP);
+ debug("VID: rounded up voltage = %d\n", voltage);
+
+ /* lower the speed to 100kHz to access ZM7300 device */
+ debug("VID: Setting bus speed to 100KHz if not already set\n");
+ orig_i2c_speed = i2c_get_bus_speed();
+ if (orig_i2c_speed != 100000)
+ i2c_set_bus_speed(100000);
+
+ /* Read the existing level on board, if equal to requsted one,
+ no need to re-set */
+ existing_voltage = zm_read_voltage();
+
+ /* allowing the voltage difference of one step 0.0125V acceptable */
+ if ((existing_voltage >= voltage) &&
+ (existing_voltage < (voltage + ZM_STEP))) {
+ debug("VID: voltage already set as requested,returning\n");
+ ret = existing_voltage;
+ goto out;
+ }
+ debug("VID: Changing voltage for board from %dmV to %dmV\n",
+ existing_voltage/10, voltage/10);
+
+ if (zm_disable_wp() < 0) {
+ ret = -1;
+ goto out;
+ }
+ /* Change Voltage: the change is done through all the steps in the
+ way, to avoid reset to the board due to power good signal fail
+ in big voltage change gap jump.
+ */
+ if (existing_voltage > voltage) {
+ temp_voltage = existing_voltage - ZM_STEP;
+ while (temp_voltage >= voltage) {
+ ret = zm_write_voltage(temp_voltage);
+ if (ret == temp_voltage) {
+ temp_voltage -= ZM_STEP;
+ } else {
+ /* ZM7300 device failed to set
+ * the voltage */
+ printf
+ ("VID:Stepping down vol failed:%dmV\n",
+ temp_voltage/10);
+ ret = -1;
+ goto out;
+ }
+ }
+ } else {
+ temp_voltage = existing_voltage + ZM_STEP;
+ while (temp_voltage < (voltage + ZM_STEP)) {
+ ret = zm_write_voltage(temp_voltage);
+ if (ret == temp_voltage) {
+ temp_voltage += ZM_STEP;
+ } else {
+ /* ZM7300 device failed to set
+ * the voltage */
+ printf
+ ("VID:Stepping up vol failed:%dmV\n",
+ temp_voltage/10);
+ ret = -1;
+ goto out;
+ }
+ }
+ }
+
+ if (zm_enable_wp() < 0)
+ ret = -1;
+
+ /* restore the speed to 400kHz */
+out: debug("VID: Restore the I2C bus speed to %dKHz\n",
+ orig_i2c_speed/1000);
+ i2c_set_bus_speed(orig_i2c_speed);
+ if (ret < 0)
+ goto exit;
+
+ ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ printf("VID: I2c failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+ vdd_last = read_voltage();
+ select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+ if (vdd_last > 0)
+ printf("VID: Core voltage %d mV\n", vdd_last);
+ else
+ ret = -1;
+
+exit:
+ if (re_enable)
+ enable_interrupts();
+ return ret;
+}
+
+int configure_vsc3316_3308(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ unsigned int num_vsc16_con, num_vsc08_con;
+ u32 serdes1_prtcl, serdes2_prtcl;
+ int ret;
+ char buffer[HWCONFIG_BUFFER_SIZE];
+ char *buf = NULL;
+
+ serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ if (!serdes1_prtcl) {
+ printf("SERDES1 is not enabled\n");
+ return 0;
+ }
+ serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
+
+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ if (!serdes2_prtcl) {
+ printf("SERDES2 is not enabled\n");
+ return 0;
+ }
+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+ switch (serdes1_prtcl) {
+ case 0x29:
+ case 0x2a:
+ case 0x2C:
+ case 0x2D:
+ case 0x2E:
+ /*
+ * Configuration:
+ * SERDES: 1
+ * Lanes: A,B: SGMII
+ * Lanes: C,D,E,F,G,H: CPRI
+ */
+ debug("Configuring crossbar to use onboard SGMII PHYs:"
+ "srds_prctl:%x\n", serdes1_prtcl);
+ num_vsc16_con = NUM_CON_VSC3316;
+ /* Configure VSC3316 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+ if (!ret) {
+ ret = vsc3316_config(VSC3316_TX_ADDRESS,
+ vsc16_tx_4sfp_sgmii_12_56,
+ num_vsc16_con);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_RX_ADDRESS,
+ vsc16_rx_4sfp_sgmii_12_56,
+ num_vsc16_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+
+ case 0x01:
+ case 0x02:
+ case 0x04:
+ case 0x05:
+ case 0x06:
+ case 0x07:
+ case 0x08:
+ case 0x09:
+ case 0x0A:
+ case 0x0B:
+ case 0x0C:
+ case 0x2F:
+ case 0x30:
+ case 0x32:
+ case 0x33:
+ case 0x34:
+ case 0x39:
+ case 0x3A:
+ case 0x3C:
+ case 0x3D:
+ case 0x5C:
+ case 0x5D:
+ /*
+ * Configuration:
+ * SERDES: 1
+ * Lanes: A,B: AURORA
+ * Lanes: C,d: SGMII
+ * Lanes: E,F,G,H: CPRI
+ */
+ debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
+ " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
+ num_vsc16_con = NUM_CON_VSC3316;
+ /* Configure VSC3316 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+ if (!ret) {
+ ret = vsc3316_config(VSC3316_TX_ADDRESS,
+ vsc16_tx_sfp_sgmii_aurora,
+ num_vsc16_con);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_RX_ADDRESS,
+ vsc16_rx_sfp_sgmii_aurora,
+ num_vsc16_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+
+#ifdef CONFIG_PPC_B4420
+ case 0x17:
+ case 0x18:
+ /*
+ * Configuration:
+ * SERDES: 1
+ * Lanes: A,B,C,D: SGMII
+ * Lanes: E,F,G,H: CPRI
+ */
+ debug("Configuring crossbar to use onboard SGMII PHYs:"
+ "srds_prctl:%x\n", serdes1_prtcl);
+ num_vsc16_con = NUM_CON_VSC3316;
+ /* Configure VSC3316 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+ if (!ret) {
+ ret = vsc3316_config(VSC3316_TX_ADDRESS,
+ vsc16_tx_sgmii_lane_cd, num_vsc16_con);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_RX_ADDRESS,
+ vsc16_rx_sgmii_lane_cd, num_vsc16_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+#endif
+
+ case 0x3E:
+ case 0x0D:
+ case 0x0E:
+ case 0x12:
+ num_vsc16_con = NUM_CON_VSC3316;
+ /* Configure VSC3316 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+ if (!ret) {
+ ret = vsc3316_config(VSC3316_TX_ADDRESS,
+ vsc16_tx_sfp, num_vsc16_con);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_RX_ADDRESS,
+ vsc16_rx_sfp, num_vsc16_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+ default:
+ printf("WARNING:VSC crossbars programming not supported for:%x"
+ " SerDes1 Protocol.\n", serdes1_prtcl);
+ return -1;
+ }
+
+ num_vsc08_con = NUM_CON_VSC3308;
+ /* Configure VSC3308 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3308);
+ switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+ case 0x9d:
+#endif
+ case 0x9E:
+ case 0x9A:
+ case 0x98:
+ case 0x48:
+ case 0x49:
+ case 0x4E:
+ case 0x79:
+ case 0x7A:
+ if (!ret) {
+ ret = vsc3308_config(VSC3308_TX_ADDRESS,
+ vsc08_tx_amc, num_vsc08_con);
+ if (ret)
+ return ret;
+ ret = vsc3308_config(VSC3308_RX_ADDRESS,
+ vsc08_rx_amc, num_vsc08_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+ case 0x80:
+ case 0x81:
+ case 0x82:
+ case 0x83:
+ case 0x84:
+ case 0x85:
+ case 0x86:
+ case 0x87:
+ case 0x88:
+ case 0x89:
+ case 0x8a:
+ case 0x8b:
+ case 0x8c:
+ case 0x8d:
+ case 0x8e:
+ case 0xb1:
+ case 0xb2:
+ if (!ret) {
+ /*
+ * Extract hwconfig from environment since environment
+ * is not setup properly yet
+ */
+ getenv_f("hwconfig", buffer, sizeof(buffer));
+ buf = buffer;
+
+ if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
+ "sfp_amc", "sfp", buf)) {
+#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+ /* change default VSC3308 for XFI erratum */
+ ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS,
+ vsc08_tx_sfp, num_vsc08_con);
+ if (ret)
+ return ret;
+
+ ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS,
+ vsc08_rx_sfp, num_vsc08_con);
+ if (ret)
+ return ret;
+#else
+ ret = vsc3308_config(VSC3308_TX_ADDRESS,
+ vsc08_tx_sfp, num_vsc08_con);
+ if (ret)
+ return ret;
+
+ ret = vsc3308_config(VSC3308_RX_ADDRESS,
+ vsc08_rx_sfp, num_vsc08_con);
+ if (ret)
+ return ret;
+#endif
+ } else {
+ ret = vsc3308_config(VSC3308_TX_ADDRESS,
+ vsc08_tx_amc, num_vsc08_con);
+ if (ret)
+ return ret;
+
+ ret = vsc3308_config(VSC3308_RX_ADDRESS,
+ vsc08_rx_amc, num_vsc08_con);
+ if (ret)
+ return ret;
+ }
+
+ } else {
+ return ret;
+ }
+ break;
+ default:
+ printf("WARNING:VSC crossbars programming not supported for: %x"
+ " SerDes2 Protocol.\n", serdes2_prtcl);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
+{
+ u32 rst_err;
+
+ /* Steps For SerDes PLLs reset and reconfiguration
+ * or PLL power-up procedure
+ */
+ debug("CALIBRATE PLL:%d\n", pll_num);
+ clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+ SRDS_RSTCTL_SDRST_B);
+ udelay(10);
+ clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
+ udelay(10);
+ setbits_be32(&srds_regs->bank[pll_num].rstctl,
+ SRDS_RSTCTL_RST);
+ setbits_be32(&srds_regs->bank[pll_num].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+ | SRDS_RSTCTL_SDRST_B));
+
+ udelay(20);
+
+ /* Check whether PLL has been locked or not */
+ rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
+ SRDS_RSTCTL_RSTERR;
+ rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
+ debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
+ if (rst_err)
+ return rst_err;
+
+ return rst_err;
+}
+
+static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
+{
+ int ret = 0;
+ u32 fcap, dcbias, bcap, pllcr1, pllcr0;
+
+ if (calibrate_pll(srds_regs, pll_num)) {
+ /* STEP 1 */
+ /* Read fcap, dcbias and bcap value */
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+ SRDS_PLLCR0_DCBIAS_OUT_EN);
+ fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
+ SRDS_PLLSR2_FCAP;
+ fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
+ bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
+ SRDS_PLLSR2_BCAP_EN;
+ bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
+ setbits_be32(&srds_regs->bank[pll_num].pllcr0,
+ SRDS_PLLCR0_DCBIAS_OUT_EN);
+ dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
+ SRDS_PLLSR2_DCBIAS;
+ dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
+ debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
+ bcap, fcap, dcbias);
+ if (fcap == 0 && bcap == 1) {
+ /* Step 3 */
+ clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+ | SRDS_RSTCTL_SDRST_B));
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BCAP_EN);
+ setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BCAP_OVD);
+ if (calibrate_pll(srds_regs, pll_num)) {
+ /*save the fcap, dcbias and bcap values*/
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+ SRDS_PLLCR0_DCBIAS_OUT_EN);
+ fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
+ & SRDS_PLLSR2_FCAP;
+ fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
+ bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
+ & SRDS_PLLSR2_BCAP_EN;
+ bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
+ setbits_be32(&srds_regs->bank[pll_num].pllcr0,
+ SRDS_PLLCR0_DCBIAS_OUT_EN);
+ dcbias = in_be32
+ (&srds_regs->bank[pll_num].pllsr2) &
+ SRDS_PLLSR2_DCBIAS;
+ dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
+
+ /* Step 4*/
+ clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+ | SRDS_RSTCTL_SDRST_B));
+ setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BYP_CAL);
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BCAP_EN);
+ setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BCAP_OVD);
+ /* change the fcap and dcbias to the saved
+ * values from Step 3 */
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_PLL_FCAP);
+ pllcr1 = (in_be32
+ (&srds_regs->bank[pll_num].pllcr1)|
+ (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ pllcr1);
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+ SRDS_PLLCR0_DCBIAS_OVRD);
+ pllcr0 = (in_be32
+ (&srds_regs->bank[pll_num].pllcr0)|
+ (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
+ out_be32(&srds_regs->bank[pll_num].pllcr0,
+ pllcr0);
+ ret = calibrate_pll(srds_regs, pll_num);
+ if (ret)
+ return ret;
+ } else {
+ goto out;
+ }
+ } else { /* Step 5 */
+ clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+ | SRDS_RSTCTL_SDRST_B));
+ udelay(10);
+ /* Change the fcap, dcbias, and bcap to the
+ * values from Step 1 */
+ setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BYP_CAL);
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_PLL_FCAP);
+ pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
+ (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ pllcr1);
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
+ SRDS_PLLCR0_DCBIAS_OVRD);
+ pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
+ (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
+ out_be32(&srds_regs->bank[pll_num].pllcr0,
+ pllcr0);
+ clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BCAP_EN);
+ setbits_be32(&srds_regs->bank[pll_num].pllcr1,
+ SRDS_PLLCR1_BCAP_OVD);
+ ret = calibrate_pll(srds_regs, pll_num);
+ if (ret)
+ return ret;
+ }
+ }
+out:
+ return 0;
+}
+
+static int check_serdes_pll_locks(void)
+{
+ serdes_corenet_t *srds1_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ serdes_corenet_t *srds2_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+ int i, ret1, ret2;
+
+ debug("\nSerDes1 Lock check\n");
+ for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
+ ret1 = check_pll_locks(srds1_regs, i);
+ if (ret1) {
+ printf("SerDes1, PLL:%d didnt lock\n", i);
+ return ret1;
+ }
+ }
+ debug("\nSerDes2 Lock check\n");
+ for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
+ ret2 = check_pll_locks(srds2_regs, i);
+ if (ret2) {
+ printf("SerDes2, PLL:%d didnt lock\n", i);
+ return ret2;
+ }
+ }
+
+ return 0;
+}
+
+int config_serdes1_refclks(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes_corenet_t *srds_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 serdes1_prtcl, lane;
+ unsigned int flag_sgmii_aurora_prtcl = 0;
+ int i;
+ int ret = 0;
+
+ serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ if (!serdes1_prtcl) {
+ printf("SERDES1 is not enabled\n");
+ return -1;
+ }
+ serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
+
+ /* To prevent generation of reset request from SerDes
+ * while changing the refclks, By setting SRDS_RST_MSK bit,
+ * SerDes reset event cannot cause a reset request
+ */
+ setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+
+ /* Reconfigure IDT idt8t49n222a device for CPRI to work
+ * For this SerDes1's Refclk1 and refclk2 need to be set
+ * to 122.88MHz
+ */
+ switch (serdes1_prtcl) {
+ case 0x29:
+ case 0x2A:
+ case 0x2C:
+ case 0x2D:
+ case 0x2E:
+ case 0x01:
+ case 0x02:
+ case 0x04:
+ case 0x05:
+ case 0x06:
+ case 0x07:
+ case 0x08:
+ case 0x09:
+ case 0x0A:
+ case 0x0B:
+ case 0x0C:
+ case 0x2F:
+ case 0x30:
+ case 0x32:
+ case 0x33:
+ case 0x34:
+ case 0x39:
+ case 0x3A:
+ case 0x3C:
+ case 0x3D:
+ case 0x5C:
+ case 0x5D:
+ debug("Configuring idt8t49n222a for CPRI SerDes clks:"
+ " for srds_prctl:%x\n", serdes1_prtcl);
+ ret = select_i2c_ch_pca(I2C_CH_IDT);
+ if (!ret) {
+ ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
+ SERDES_REFCLK_122_88,
+ SERDES_REFCLK_122_88, 0);
+ if (ret) {
+ printf("IDT8T49N222A configuration failed.\n");
+ goto out;
+ } else
+ debug("IDT8T49N222A configured.\n");
+ } else {
+ goto out;
+ }
+ select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+ /* Change SerDes1's Refclk1 to 125MHz for on board
+ * SGMIIs or Aurora to work
+ */
+ for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes_get_prtcl
+ (0, serdes1_prtcl, lane);
+ switch (lane_prtcl) {
+ case SGMII_FM1_DTSEC1:
+ case SGMII_FM1_DTSEC2:
+ case SGMII_FM1_DTSEC3:
+ case SGMII_FM1_DTSEC4:
+ case SGMII_FM1_DTSEC5:
+ case SGMII_FM1_DTSEC6:
+ case AURORA:
+ flag_sgmii_aurora_prtcl++;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (flag_sgmii_aurora_prtcl)
+ QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
+
+ /* Steps For SerDes PLLs reset and reconfiguration after
+ * changing SerDes's refclks
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
+ debug("For PLL%d reset and reconfiguration after"
+ " changing refclks\n", i+1);
+ clrbits_be32(&srds_regs->bank[i].rstctl,
+ SRDS_RSTCTL_SDRST_B);
+ udelay(10);
+ clrbits_be32(&srds_regs->bank[i].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
+ udelay(10);
+ setbits_be32(&srds_regs->bank[i].rstctl,
+ SRDS_RSTCTL_RST);
+ setbits_be32(&srds_regs->bank[i].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+ | SRDS_RSTCTL_SDRST_B));
+ }
+ break;
+ default:
+ printf("WARNING:IDT8T49N222A configuration not"
+ " supported for:%x SerDes1 Protocol.\n",
+ serdes1_prtcl);
+ }
+
+out:
+ /* Clearing SRDS_RST_MSK bit as now
+ * SerDes reset event can cause a reset request
+ */
+ clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+ return ret;
+}
+
+int config_serdes2_refclks(void)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes_corenet_t *srds2_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+ u32 serdes2_prtcl;
+ int ret = 0;
+ int i;
+
+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ if (!serdes2_prtcl) {
+ debug("SERDES2 is not enabled\n");
+ return -ENODEV;
+ }
+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+ /* To prevent generation of reset request from SerDes
+ * while changing the refclks, By setting SRDS_RST_MSK bit,
+ * SerDes reset event cannot cause a reset request
+ */
+ setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+
+ /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
+ * For this SerDes2's Refclk1 need to be set to 100MHz
+ */
+ switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+ case 0x9d:
+#endif
+ case 0x9E:
+ case 0x9A:
+ /* fallthrough */
+ case 0xb1:
+ case 0xb2:
+ debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
+ serdes2_prtcl);
+ ret = select_i2c_ch_pca(I2C_CH_IDT);
+ if (!ret) {
+ ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
+ SERDES_REFCLK_100,
+ SERDES_REFCLK_156_25, 0);
+ if (ret) {
+ printf("IDT8T49N222A configuration failed.\n");
+ goto out;
+ } else
+ debug("IDT8T49N222A configured.\n");
+ } else {
+ goto out;
+ }
+ select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+ /* Steps For SerDes PLLs reset and reconfiguration after
+ * changing SerDes's refclks
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
+ clrbits_be32(&srds2_regs->bank[i].rstctl,
+ SRDS_RSTCTL_SDRST_B);
+ udelay(10);
+ clrbits_be32(&srds2_regs->bank[i].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
+ udelay(10);
+ setbits_be32(&srds2_regs->bank[i].rstctl,
+ SRDS_RSTCTL_RST);
+ setbits_be32(&srds2_regs->bank[i].rstctl,
+ (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
+ | SRDS_RSTCTL_SDRST_B));
+
+ udelay(10);
+ }
+ break;
+ default:
+ printf("IDT configuration not supported for:%x S2 Protocol.\n",
+ serdes2_prtcl);
+ }
+
+out:
+ /* Clearing SRDS_RST_MSK bit as now
+ * SerDes reset event can cause a reset request
+ */
+ clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+ return ret;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+ int ret;
+ u32 svr = SVR_SOC_VER(get_svr());
+
+ /* Create law for MAPLE only for personalities having MAPLE */
+ if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
+ (svr == SVR_B4420) || (svr == SVR_B4220)) {
+ set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
+ LAW_TRGT_IF_MAPLE);
+ }
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+ /*
+ * Adjust core voltage according to voltage ID
+ * This function changes I2C mux to channel 2.
+ */
+ if (adjust_vdd(0) < 0)
+ printf("Warning: Adjusting core voltage failed\n");
+
+ /* SerDes1 refclks need to be set again, as default clks
+ * are not suitable for CPRI and onboard SGMIIs to work
+ * simultaneously.
+ * This function will set SerDes1's Refclk1 and refclk2
+ * as per SerDes1 protocols
+ */
+ if (config_serdes1_refclks())
+ printf("SerDes1 Refclks couldn't set properly.\n");
+ else
+ printf("SerDes1 Refclks have been set.\n");
+
+ /* SerDes2 refclks need to be set again, as default clks
+ * are not suitable for PCIe SATA to work
+ * This function will set SerDes2's Refclk1 and refclk2
+ * for SerDes2 protocols having PCIe in them
+ * for PCIe SATA to work
+ */
+ ret = config_serdes2_refclks();
+ if (!ret)
+ printf("SerDes2 Refclks have been set.\n");
+ else if (ret == -ENODEV)
+ printf("SerDes disable, Refclks couldn't change.\n");
+ else
+ printf("SerDes2 Refclk reconfiguring failed.\n");
+
+#if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
+ defined(CONFIG_SYS_FSL_ERRATUM_A006475)
+ /* Rechecking the SerDes locks after all SerDes configurations
+ * are done, As SerDes PLLs may not lock reliably at 5 G VCO
+ * and at cold temperatures.
+ * Following sequence ensure the proper locking of SerDes PLLs.
+ */
+ if (SVR_MAJ(get_svr()) == 1) {
+ if (check_serdes_pll_locks())
+ printf("SerDes plls still not locked properly.\n");
+ else
+ printf("SerDes plls have been locked well.\n");
+ }
+#endif
+
+ /* Configure VSC3316 and VSC3308 crossbar switches */
+ if (configure_vsc3316_3308())
+ printf("VSC:failed to configure VSC3316/3308.\n");
+ else
+ printf("VSC:VSC3316/3308 successfully configured.\n");
+
+ select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((sysclk_conf & 0x0C) >> 2) {
+ case QIXIS_CLK_100:
+ return 100000000;
+ case QIXIS_CLK_125:
+ return 125000000;
+ case QIXIS_CLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (ddrclk_conf & 0x03) {
+ case QIXIS_CLK_100:
+ return 100000000;
+ case QIXIS_CLK_125:
+ return 125000000;
+ case QIXIS_CLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+static int serdes_refclock(u8 sw, u8 sdclk)
+{
+ unsigned int clock;
+ int ret = -1;
+ u8 brdcfg4;
+
+ if (sdclk == 1) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
+ return SRDS_PLLCR0_RFCK_SEL_125;
+ else
+ clock = (sw >> 5) & 7;
+ } else
+ clock = (sw >> 6) & 3;
+
+ switch (clock) {
+ case 0:
+ ret = SRDS_PLLCR0_RFCK_SEL_100;
+ break;
+ case 1:
+ ret = SRDS_PLLCR0_RFCK_SEL_125;
+ break;
+ case 2:
+ ret = SRDS_PLLCR0_RFCK_SEL_156_25;
+ break;
+ case 3:
+ ret = SRDS_PLLCR0_RFCK_SEL_161_13;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ ret = SRDS_PLLCR0_RFCK_SEL_122_88;
+ break;
+ default:
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
+#define NUM_SRDS_BANKS 2
+
+int misc_init_r(void)
+{
+ u8 sw;
+ serdes_corenet_t *srds_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 actual[NUM_SRDS_BANKS];
+ unsigned int i;
+ int clock;
+
+ sw = QIXIS_READ(brdcfg[2]);
+ clock = serdes_refclock(sw, 1);
+ if (clock >= 0)
+ actual[0] = clock;
+ else
+ printf("Warning: SDREFCLK1 switch setting is unsupported\n");
+
+ sw = QIXIS_READ(brdcfg[4]);
+ clock = serdes_refclock(sw, 2);
+ if (clock >= 0)
+ actual[1] = clock;
+ else
+ printf("Warning: SDREFCLK2 switch setting unsupported\n");
+
+ for (i = 0; i < NUM_SRDS_BANKS; i++) {
+ u32 pllcr0 = srds_regs->bank[i].pllcr0;
+ u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+ if (expected != actual[i]) {
+ printf("Warning: SERDES bank %u expects reference clock"
+ " %sMHz, but actual is %sMHz\n", i + 1,
+ serdes_clock_to_string(expected),
+ serdes_clock_to_string(actual[i]));
+ }
+ }
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
+
+/*
+ * Dump board switch settings.
+ * The bits that cannot be read/sampled via some FPGA or some
+ * registers, they will be displayed as
+ * underscore in binary format. mask[] has those bits.
+ * Some bits are calculated differently than the actual switches
+ * if booting with overriding by FPGA.
+ */
+void qixis_dump_switch(void)
+{
+ int i;
+ u8 sw[5];
+
+ /*
+ * Any bit with 1 means that bit cannot be reverse engineered.
+ * It will be displayed as _ in binary format.
+ */
+ static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
+ char buf[10];
+ u8 brdcfg[16], dutcfg[16];
+
+ for (i = 0; i < 16; i++) {
+ brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+ dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+ }
+
+ sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
+ (brdcfg[9] & 0x08);
+ sw[1] = ((dutcfg[1] & 0x01) << 7) | \
+ ((dutcfg[2] & 0x07) << 4) | \
+ ((dutcfg[6] & 0x10) >> 1) | \
+ ((dutcfg[6] & 0x80) >> 5) | \
+ ((dutcfg[1] & 0x40) >> 5) | \
+ (dutcfg[6] & 0x01);
+ sw[2] = dutcfg[0];
+ sw[3] = 0;
+ sw[4] = ((brdcfg[1] & 0x30) << 2) | \
+ ((brdcfg[1] & 0xc0) >> 2) | \
+ (brdcfg[1] & 0x0f);
+
+ puts("DIP switch settings:\n");
+ for (i = 0; i < 5; i++) {
+ printf("SW%d = 0b%s (0x%02x)\n",
+ i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
+ }
+}
diff --git a/board/freescale/b4860qds/b4860qds.h b/board/freescale/b4860qds/b4860qds.h
new file mode 100644
index 0000000..f7cb5cd
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
new file mode 100644
index 0000000..fcccb8f
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CROSSBAR_CONNECTIONS_H__
+#define __CROSSBAR_CONNECTIONS_H__
+
+#define NUM_CON_VSC3316 8
+#define NUM_CON_VSC3308 4
+
+static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
+ {5, 11}, {4, 5}, {2, 6}, {12, 9} };
+
+static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
+ {7, 8}, {9, 0}, {2, 14}, {12, 15},
+ {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
+ {7, 8}, {9, 0}, {5, 14}, {4, 15},
+ {-1, -1}, {-1, -1} };
+
+static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
+ {7, 8}, {9, 0}, {5, 14},
+ {4, 15}, {2, 12}, {12, 13} };
+
+#ifdef CONFIG_PPC_B4420
+static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+#endif
+
+static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
+ {11, 11}, {5, 10}, {6, 3}, {9, 12} };
+
+static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
+ {7, 8}, {1, 9}, {14, 3}, {15, 12},
+ {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
+ {7, 8}, {1, 9}, {14, 11}, {15, 10},
+ {-1, -1}, {-1, -1} };
+
+static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
+ {7, 8}, {1, 9}, {14, 11},
+ {15, 10}, {13, 3}, {12, 12} };
+
+#ifdef CONFIG_PPC_B4420
+static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+#endif
+
+static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
+
+static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };
+
+static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
+
+static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };
+
+#endif
diff --git a/board/freescale/b4860qds/b4860qds_qixis.h b/board/freescale/b4860qds/b4860qds_qixis.h
new file mode 100644
index 0000000..272afc1
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds_qixis.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __B4860QDS_QIXIS_H__
+#define __B4860QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for B4860QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xE0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* CLK */
+#define QIXIS_CLK_66 0x0
+#define QIXIS_CLK_100 0x1
+#define QIXIS_CLK_125 0x2
+#define QIXIS_CLK_133 0x3
+
+#define QIXIS_SRDS1CLK_122 0x5a
+#define QIXIS_SRDS1CLK_125 0x5e
+
+/* SGMII */
+#define PHY_BASE_ADDR 0x18
+#define PORT_NUM 0x04
+#define REGNUM 0x00
+#endif
diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg
new file mode 100644
index 0000000..05377ba
--- /dev/null
+++ b/board/freescale/b4860qds/b4_pbi.cfg
@@ -0,0 +1,30 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg
new file mode 100644
index 0000000..597d391
--- /dev/null
+++ b/board/freescale/b4860qds/b4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x2A_0x98
+140e0018 0f001218 00000000 00000000
+54980000 9000a000 e8104000 a9000000
+01000000 00000000 00000000 0001b1f8
+00000000 14000020 00000000 00000011
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
new file mode 100644
index 0000000..2c17156
--- /dev/null
+++ b/board/freescale/b4860qds/ddr.c
@@ -0,0 +1,265 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <fsl_ddr.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 2,
+ .rank_density = 2147483648u,
+ .capacity = 4294967296u,
+ .primary_sdram_width = 64,
+ .ec_sdram_width = 8,
+ .registered_dimm = 0,
+ .mirrored_dimm = 1,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 2, /* ECC */
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1071,
+ .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
+ .taa_ps = 13910,
+ .twr_ps = 15000,
+ .trcd_ps = 13910,
+ .trrd_ps = 6000,
+ .trp_ps = 13910,
+ .tras_ps = 34000,
+ .trc_ps = 48910,
+ .trfc_ps = 260000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 35000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "RAW timing DDR";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
+ {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
+ {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
+ {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
+ {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
+ {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twot_en = pbsp->force_2t;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->twot_en = pbsp_highest->force_2t;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+#else
+ dram_size = fsl_ddr_sdram_size();
+#endif
+ return dram_size;
+}
+
+unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
+ unsigned int dbw_cap_adj[])
+{
+ int i, j;
+ unsigned long long total_mem, current_mem_base, total_ctlr_mem;
+ unsigned long long rank_density, ctlr_density = 0;
+
+ current_mem_base = 0ull;
+ total_mem = 0;
+ /*
+ * This board has soldered DDR chips. DDRC1 has two rank.
+ * DDRC2 has only one rank.
+ * Assigning DDRC2 to lower address and DDRC1 to higher address.
+ */
+ if (pinfo->memctl_opts[0].memctl_interleaving) {
+ rank_density = pinfo->dimm_params[0][0].rank_density >>
+ dbw_cap_adj[0];
+ ctlr_density = rank_density;
+
+ debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
+ rank_density, ctlr_density);
+ for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+ switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
+ case FSL_DDR_CACHE_LINE_INTERLEAVING:
+ case FSL_DDR_PAGE_INTERLEAVING:
+ case FSL_DDR_BANK_INTERLEAVING:
+ case FSL_DDR_SUPERBANK_INTERLEAVING:
+ total_ctlr_mem = 2 * ctlr_density;
+ break;
+ default:
+ panic("Unknown interleaving mode");
+ }
+ pinfo->common_timing_params[i].base_address =
+ current_mem_base;
+ pinfo->common_timing_params[i].total_mem =
+ total_ctlr_mem;
+ total_mem = current_mem_base + total_ctlr_mem;
+ debug("ctrl %d base 0x%llx\n", i, current_mem_base);
+ debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
+ }
+ } else {
+ /*
+ * Simple linear assignment if memory
+ * controllers are not interleaved.
+ */
+ for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+ total_ctlr_mem = 0;
+ pinfo->common_timing_params[i].base_address =
+ current_mem_base;
+ for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+ /* Compute DIMM base addresses. */
+ unsigned long long cap =
+ pinfo->dimm_params[i][j].capacity;
+ pinfo->dimm_params[i][j].base_address =
+ current_mem_base;
+ debug("ctrl %d dimm %d base 0x%llx\n",
+ i, j, current_mem_base);
+ current_mem_base += cap;
+ total_ctlr_mem += cap;
+ }
+ debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
+ pinfo->common_timing_params[i].total_mem =
+ total_ctlr_mem;
+ total_mem += total_ctlr_mem;
+ }
+ }
+ debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
+
+ return total_mem;
+}
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
new file mode 100644
index 0000000..501d4b3
--- /dev/null
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -0,0 +1,453 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Author: Sandeep Kumar Singh <sandeep@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
+
+/*
+ * This file handles the board muxing between the Fman Ethernet MACs and
+ * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
+ * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
+ * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
+ * one Fman device on B4860. The SERDES configuration is used to determine
+ * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
+ * to which PHYs. So for a given Fman MAC, there is one and only PHY it
+ * connects to. MACs cannot be routed to PHYs dynamically. This configuration
+ * is done at boot time by reading SERDES protocol from RCW.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fdt_support.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/ngpixis.h"
+#include "../common/fman.h"
+#include "../common/qixis.h"
+#include "b4860qds_qixis.h"
+
+#define EMI_NONE 0xFFFFFFFF
+
+#ifdef CONFIG_FMAN_ENET
+
+/*
+ * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
+ * lane at index is mapped to slot number n. A value of '0' will mean
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot
+ */
+static u8 lane_to_slot[] = {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0
+};
+
+/*
+ * This function initializes the lane_to_slot[] array. It reads RCW to check
+ * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
+ * lane_to_slot[] accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+ unsigned int serdes2_prtcl;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ debug("Initializing lane to slot: Serdes2 protocol: %x\n",
+ serdes2_prtcl);
+
+ switch (serdes2_prtcl) {
+ case 0x17:
+ case 0x18:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: SGMII
+ * Lanes: E,F: Aur
+ * Lanes: G,H: SRIO
+ */
+ case 0x91:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B: SGMII
+ * Lanes: C,D: SRIO2
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0x93:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: SGMII
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0x98:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: XAUI2
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0x9a:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B: PCI
+ * Lanes: C,D: SGMII
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0x9e:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: PCI
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0xb1:
+ case 0xb2:
+ case 0x8c:
+ case 0x8d:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: PCI
+ * Lanes: E,F: SGMII 3&4
+ * Lanes: G,H: XFI
+ */
+ case 0xc2:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B: SGMII
+ * Lanes: C,D: SRIO2
+ * Lanes: E,F,G,H: XAUI2
+ */
+ lane_to_slot[12] = 2;
+ lane_to_slot[13] = lane_to_slot[12];
+ lane_to_slot[14] = lane_to_slot[12];
+ lane_to_slot[15] = lane_to_slot[12];
+ break;
+
+ default:
+ printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
+ serdes2_prtcl);
+ break;
+ }
+ return;
+}
+
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct memac_mdio_info memac_mdio_info;
+ struct memac_mdio_info tg_memac_mdio_info;
+ unsigned int i;
+ unsigned int serdes1_prtcl, serdes2_prtcl;
+ int qsgmii;
+ struct mii_dev *bus;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ if (!serdes1_prtcl) {
+ printf("SERDES1 is not enabled\n");
+ return 0;
+ }
+ serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
+
+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ if (!serdes2_prtcl) {
+ printf("SERDES2 is not enabled\n");
+ return 0;
+ }
+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+ printf("Initializing Fman\n");
+
+ initialize_lane_to_slot();
+
+ memac_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the real 1G MDIO bus */
+ fm_memac_mdio_init(bis, &memac_mdio_info);
+
+ tg_memac_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the real 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tg_memac_mdio_info);
+
+ /*
+ * Program the two on board DTSEC PHY addresses assuming that they are
+ * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
+ * 6 to on board SGMII phys
+ */
+ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
+
+ switch (serdes1_prtcl) {
+ case 0x29:
+ case 0x2a:
+ /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
+ debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5,
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
+ break;
+#ifdef CONFIG_PPC_B4420
+ case 0x17:
+ case 0x18:
+ /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
+ debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
+ /* Fixing Serdes clock by programming FPGA register */
+ QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
+ break;
+#endif
+ default:
+ printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ break;
+ }
+ switch (serdes2_prtcl) {
+ case 0x17:
+ case 0x18:
+ debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1,
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4,
+ CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
+ break;
+ case 0x48:
+ case 0x49:
+ debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1,
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
+ break;
+ case 0xb1:
+ case 0xb2:
+ case 0x8c:
+ case 0x8d:
+ debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4,
+ CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+ /*
+ * XFI does not need a PHY to work, but to make U-boot
+ * happy, assign a fake PHY address for a XFI port.
+ */
+ fm_info_set_phy_address(FM1_10GEC1, 0);
+ fm_info_set_phy_address(FM1_10GEC2, 1);
+ break;
+ case 0x98:
+ /* XAUI in Slot1 and Slot2 */
+ debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
+ CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC1,
+ CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+ debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
+ CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2,
+ CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+ break;
+ case 0x9E:
+ /* XAUI in Slot2 */
+ debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
+ CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2,
+ CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+ break;
+ default:
+ printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
+ serdes2_prtcl);
+ break;
+ }
+
+ /*set PHY address for QSGMII Riser Card on slot2*/
+ bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
+
+ if (qsgmii) {
+ switch (serdes2_prtcl) {
+ case 0xb2:
+ case 0x8d:
+ fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
+ break;
+ default:
+ printf("Fman1: DTSEC%u set to unknown interface %i\n",
+ idx + 1, fm_info_get_enet_if(i));
+ fm_info_set_phy_address(i, 0);
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ int idx = i - FM1_10GEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name
+ (DEFAULT_FM_TGEC_MDIO_NAME));
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
+ break;
+ default:
+ printf("Fman1: TGEC%u set to unknown interface %i\n",
+ idx + 1, fm_info_get_enet_if(i));
+ fm_info_set_phy_address(i, 0);
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ int phy;
+ char alias[32];
+ struct fixed_link f_link;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+ prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ phy = fm_info_get_phy_address(port);
+
+ sprintf(alias, "phy_sgmii_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, alias);
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+ /* check if it's XFI interface for 10g */
+ switch (prtcl2) {
+ case 0x80:
+ case 0x81:
+ case 0x82:
+ case 0x83:
+ case 0x84:
+ case 0x85:
+ case 0x86:
+ case 0x87:
+ case 0x88:
+ case 0x89:
+ case 0x8a:
+ case 0x8b:
+ case 0x8c:
+ case 0x8d:
+ case 0x8e:
+ case 0xb1:
+ case 0xb2:
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link,
+ sizeof(f_link));
+ break;
+ case 0x98: /* XAUI interface */
+ sprintf(alias, "phy_xaui_slot1");
+ fdt_status_okay_by_alias(fdt, alias);
+
+ sprintf(alias, "phy_xaui_slot2");
+ fdt_status_okay_by_alias(fdt, alias);
+ break;
+ case 0x9e: /* XAUI interface */
+ case 0x9a:
+ case 0x93:
+ case 0x91:
+ sprintf(alias, "phy_xaui_slot1");
+ fdt_status_okay_by_alias(fdt, alias);
+ break;
+ case 0x97: /* XAUI interface */
+ case 0xc3:
+ sprintf(alias, "phy_xaui_slot2");
+ fdt_status_okay_by_alias(fdt, alias);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+/*
+ * Set status to disabled for unused ethernet node
+ */
+void fdt_fixup_board_enet(void *fdt)
+{
+ int i;
+ char alias[32];
+
+ for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_NONE:
+ sprintf(alias, "ethernet%u", i);
+ fdt_status_disabled_by_alias(fdt, alias);
+ break;
+ default:
+ break;
+ }
+ }
+}
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c
new file mode 100644
index 0000000..047c3cb
--- /dev/null
+++ b/board/freescale/b4860qds/law.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+ SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/b4860qds/pci.c b/board/freescale/b4860qds/pci.c
new file mode 100644
index 0000000..d9ccac7
--- /dev/null
+++ b/board/freescale/b4860qds/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
new file mode 100644
index 0000000..3aa5a78
--- /dev/null
+++ b/board/freescale/b4860qds/spl.c
@@ -0,0 +1,114 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/spl.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include "../common/qixis.h"
+#include "b4860qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((sysclk_conf & 0x0C) >> 2) {
+ case QIXIS_CLK_100:
+ return 100000000;
+ case QIXIS_CLK_125:
+ return 125000000;
+ case QIXIS_CLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (ddrclk_conf & 0x03) {
+ case QIXIS_CLK_100:
+ return 100000000;
+ case QIXIS_CLK_125:
+ return 125000000;
+ case QIXIS_CLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, uart_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("" : : : "memory");
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ uart_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ uart_clk / 16 / CONFIG_BAUDRATE);
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+ env_init();
+ env_relocate();
+#else
+ /* relocate environment function pointers etc. */
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+#endif
+
+ i2c_init_all();
+
+ puts("\n\n");
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
new file mode 100644
index 0000000..7b55b86
--- /dev/null
+++ b/board/freescale/b4860qds/tlb.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+ * space is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_64K, 1),
+#endif
+ SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_4K, 1),
+
+ /*
+ * *I*G - SRIO
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for SRIO2.
+ */
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
+ /* *I*G* - SRIO1 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_256M, 1),
+#endif
+#ifdef CONFIG_SYS_SRIO2_MEM_PHYS
+ /* *I*G* - SRIO2 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_256M, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+ * fetching ucode and ENV from master
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 17, BOOKE_PAGESZ_1M, 1),
+#endif
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 17, BOOKE_PAGESZ_2G, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/bsc9131rdb/Kconfig b/board/freescale/bsc9131rdb/Kconfig
new file mode 100644
index 0000000..dd9f765
--- /dev/null
+++ b/board/freescale/bsc9131rdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BSC9131RDB
+
+config SYS_BOARD
+ default "bsc9131rdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "BSC9131RDB"
+
+endif
diff --git a/board/freescale/bsc9131rdb/MAINTAINERS b/board/freescale/bsc9131rdb/MAINTAINERS
new file mode 100644
index 0000000..7cd8134
--- /dev/null
+++ b/board/freescale/bsc9131rdb/MAINTAINERS
@@ -0,0 +1,9 @@
+BSC9131RDB BOARD
+M: Poonam Aggrwal <poonam.aggrwal@freescale.com>
+S: Maintained
+F: board/freescale/bsc9131rdb/
+F: include/configs/BSC9131RDB.h
+F: configs/BSC9131RDB_NAND_defconfig
+F: configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+F: configs/BSC9131RDB_SPIFLASH_defconfig
+F: configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile
new file mode 100644
index 0000000..b26d3a1
--- /dev/null
+++ b/board/freescale/bsc9131rdb/Makefile
@@ -0,0 +1,27 @@
+#
+# Copyright 2011-2012 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y += spl_minimal.o tlb.o law.o
+
+else
+
+obj-y += bsc9131rdb.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
+#obj-y += bsc9131rdb_mux.o
+
+endif
diff --git a/board/freescale/bsc9131rdb/README b/board/freescale/bsc9131rdb/README
new file mode 100644
index 0000000..4902b98
--- /dev/null
+++ b/board/freescale/bsc9131rdb/README
@@ -0,0 +1,151 @@
+Overview
+--------
+- BSC9131 is integrated device that targets Femto base station market.
+ It combines Power Architecture e500v2 and DSP StarCore SC3850 core
+ technologies with MAPLE-B2F baseband acceleration processing elements.
+- It's MAPLE disabled personality is called 9231.
+
+The BSC9131 SoC includes the following function and features:
+. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
+ L2 cache
+. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
+. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
+ Processing (MAPLE-B2F)
+. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
+ Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
+ and CRC algorithms
+. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
+ Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
+ operations
+. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
+ ECC, up to 400-MHz clock/800 MHz data rate
+. Dedicated security engine featuring trusted boot
+. DMA controller
+. OCNDMA with four bidirectional channels
+. Interfaces
+. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
+ including IEEE 1588. v2 hardware support and virtualization (eTSEC)
+. eTSEC 1 supports RGMII/RMII
+. eTSEC 2 supports RGMII
+. High-speed USB 2.0 host and device controller with ULPI interface
+. Enhanced secure digital (SD/MMC) host controller (eSDHC)
+. Antenna interface controller (AIC), supporting three industry standard
+ JESD207/three custom ADI RF interfaces (two dual port and one single port)
+ and three MAXIM's MaxPHY serial interfaces
+. ADI lanes support both full duplex FDD support and half duplex TDD support
+. Universal Subscriber Identity Module (USIM) interface that facilitates
+ communication to SIM cards or Eurochip pre-paid phone cards
+. TDM with one TDM port
+. Two DUART, four eSPI, and two I2C controllers
+. Integrated Flash memory controller (IFC)
+. TDM with 256 channels
+. GPIO
+. Sixteen 32-bit timers
+
+The e500 core subsystem within the Power Architecture consists of the following:
+. 32-Kbyte L1 instruction cache
+. 32-Kbyte L1 data cache
+. 256-Kbyte L2 cache/L2 memory/L2 stash
+. programmable interrupt controller (PIC)
+. Debug support
+. Timers
+
+The SC3850 core subsystem consists of the following:
+. 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
+. 32 Kbyte 8-way level 1 data cache (L1 DCache)
+. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
+. Memory management unit (MMU)
+. Enhanced programmable interrupt controller (EPIC)
+. Debug and profiling unit (DPU)
+. Two 32-bit timers
+
+BSC9131RDB board Overview
+-------------------------
+ 1Gbyte DDR3 (on board DDR)
+ 128Mbyte 2K page size NAND Flash
+ 256 Kbit M24256 I2C EEPROM
+ 128 Mbit SPI Flash memory
+ USB-ULPI
+ eTSEC1: Connected to RGMII PHY
+ eTSEC2: Connected to RGMII PHY
+ DUART interface: supports one UARTs up to 115200 bps for console display
+ USIM connector
+
+Frequency Combinations Supported
+--------------------------------
+Core MHz/CCB MHz/DDR(MT/s)
+1. 1000/500/800
+2. 800/400/667
+
+Boot Methods Supported
+-----------------------
+1. NAND Flash
+2. SPI Flash
+
+Default Boot Method
+--------------------
+NAND boot
+
+Building U-boot
+--------------
+To build the u-boot for BSC9131RDB:
+1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
+ make BSC9131RDB_NAND
+2. NAND Flash with sysclk 100MHz(J16 on RDB open)
+ make BSC9131RDB_NAND_SYSCLK100
+3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
+ make BSC9131RDB_SPIFLASH
+4. SPI Flash with sysclk 100MHz(J16 on RDB open)
+ make BSC9131RDB_SPIFLASH_SYSCLK100
+
+Memory map
+-----------
+ 0x0000_0000 0x7FFF_FFFF DDR 1G cacheable
+ 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
+ 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
+ 0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K
+ 0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K
+ 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
+ 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
+ 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
+ 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
+ 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
+
+DDR Memory map
+---------------
+ 0x0000_0000 0x36FF_FFFF Memory passed onto Linux
+ 0x3700_0000 0x37FF_FFFF PowerPC-DSP shared control area
+ 0x3800_0000 0x4FFF_FFFF DSP Private area
+
+ Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
+ data communcation between PowerPC and DSP core.
+ Rest is PowerPC private area.
+
+Flashing Images
+---------------
+To place a new u-boot image in the NAND flash and then boot
+with that new image temporarily, use this:
+ tftp 1000000 u-boot-nand.bin
+ nand erase 0 100000
+ nand write 1000000 0 100000
+ reset
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
+
+Booting Linux
+-------------
+Place a linux uImage in the TFTP disk area.
+
+ tftp 1000000 uImage
+ tftp 2000000 rootfs.ext2.gz.uboot
+ tftp c00000 bsc9131rdb.dtb
+ bootm 1000000 2000000 c00000
diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c
new file mode 100644
index 0000000..75e1142
--- /dev/null
+++ b/board/freescale/bsc9131rdb/bsc9131rdb.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+#include <flash.h>
+#include <netdev.h>
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
+ setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
+
+ clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
+ setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
+ MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
+ setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
+ clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
+ MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
+ MPC85xx_PMUXCR_IFC_AD_GPIO |
+ MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ struct cpu_type *cpu;
+
+ cpu = gd->arch.cpu;
+ printf("Board: %sRDB\n", cpu->name);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+struct node_info nodes[] = {
+ { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
+};
+#endif
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+
+ fdt_fixup_dr_usb(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c
new file mode 100644
index 0000000..339c576
--- /dev/null
+++ b/board/freescale/bsc9131rdb/ddr.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_DRAM_SIZE 1024
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+ {750, 850, &ddr_cfg_regs_800},
+ {0, 0, NULL}
+};
+
+unsigned long get_sdram_size(void)
+{
+ return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
+}
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+phys_size_t fixed_sdram(void)
+{
+ int i;
+ char buf[32];
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
+ phys_size_t ddr_size;
+ ulong ddr_freq, ddr_freq_mhz;
+
+ ddr_freq = get_ddr_freq(0);
+ ddr_freq_mhz = ddr_freq / 1000000;
+
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+ if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+ (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+ memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
+ sizeof(ddr_cfg_regs));
+ break;
+ }
+ }
+
+ if (fixed_ddr_parm_0[i].max_freq == 0) {
+ panic("Unsupported DDR data rate %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+ }
+
+ ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
+ LAW_TRGT_IF_DDR_1) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+
+ return ddr_size;
+}
+
+#else /* CONFIG_SYS_DDR_RAW_TIMING */
+/* Micron MT41J256M8HX-15E */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 1073741824u,
+ .capacity = 1073741824u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1870,
+ .caslat_x = 0x1e << 4, /* 5,6,7,8 */
+ .taa_ps = 13125,
+ .twr_ps = 15000,
+ .trcd_ps = 13125,
+ .trrd_ps = 7500,
+ .trp_ps = 13125,
+ .tras_ps = 37500,
+ .trc_ps = 50625,
+ .trfc_ps = 160000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ int i;
+ popts->clk_adjust = 6;
+ popts->cpo_override = 0x1f;
+ popts->write_data_delay = 2;
+ popts->half_strength_driver_enable = 1;
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x8;
+ popts->trwt_override = 1;
+ popts->trwt = 0;
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+ popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+ }
+}
+
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c
new file mode 100644
index 0000000..19b7430
--- /dev/null
+++ b/board/freescale/bsc9131rdb/law.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
+ LAW_TRGT_IF_DSP_CCSR),
+ SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M,
+ LAW_TRGT_IF_OCN_DSP),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c
new file mode 100644
index 0000000..bd8560b
--- /dev/null
+++ b/board/freescale/bsc9131rdb/spl_minimal.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+static void sdram_init(void)
+{
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+ __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+ __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
+ __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
+#endif
+ __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
+
+ __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
+ __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
+
+ __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
+ __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+ __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
+
+ __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+ __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+
+ /* Set, but do not enable the memory */
+ __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
+
+ asm volatile("sync;isync");
+ udelay(500);
+
+ /* Let the controller go */
+ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+ set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* Initialize the DDR3 */
+ sdram_init();
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c
new file mode 100644
index 0000000..c8ecf5d
--- /dev/null
+++ b/board/freescale/bsc9131rdb/tlb.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_BOOT
+ SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR (PA) */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* CCSRBAR (DSP) */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
+ CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1M, 1)
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/bsc9132qds/Kconfig b/board/freescale/bsc9132qds/Kconfig
new file mode 100644
index 0000000..db3a1f1
--- /dev/null
+++ b/board/freescale/bsc9132qds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BSC9132QDS
+
+config SYS_BOARD
+ default "bsc9132qds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "BSC9132QDS"
+
+endif
diff --git a/board/freescale/bsc9132qds/MAINTAINERS b/board/freescale/bsc9132qds/MAINTAINERS
new file mode 100644
index 0000000..3de62d3
--- /dev/null
+++ b/board/freescale/bsc9132qds/MAINTAINERS
@@ -0,0 +1,25 @@
+BSC9132QDS BOARD
+M: Naveen Burmi <NaveenBurmi@freescale.com>
+S: Maintained
+F: board/freescale/bsc9132qds/
+F: include/configs/BSC9132QDS.h
+F: configs/BSC9132QDS_NAND_DDRCLK100_defconfig
+F: configs/BSC9132QDS_NAND_DDRCLK133_defconfig
+F: configs/BSC9132QDS_NOR_DDRCLK100_defconfig
+F: configs/BSC9132QDS_NOR_DDRCLK133_defconfig
+F: configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
+F: configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
+F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
+F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
+
+BSC9132QDS_NAND_DDRCLK100_SECURE BOARD
+M: Aneesh Bansal <aneesh.bansal@freescale.com>
+S: Maintained
+F: configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
+F: configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
+F: configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
+F: configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
+F: configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
+F: configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
+F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
+F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile
new file mode 100644
index 0000000..2e4170f
--- /dev/null
+++ b/board/freescale/bsc9132qds/Makefile
@@ -0,0 +1,26 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y += spl_minimal.o tlb.o law.o
+
+else
+
+obj-y += bsc9132qds.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
+
+endif
diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README
new file mode 100644
index 0000000..f8377c9
--- /dev/null
+++ b/board/freescale/bsc9132qds/README
@@ -0,0 +1,150 @@
+Overview
+--------
+ The BSC9132 is a highly integrated device that targets the evolving
+ Microcell, Picocell, and Enterprise-Femto base station market subsegments.
+
+ The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
+ core technologies with MAPLE-B2P baseband acceleration processing elements
+ to address the need for a high performance, low cost, integrated solution
+ that handles all required processing layers without the need for an
+ external device except for an RF transceiver or, in a Micro base station
+ configuration, a host device that handles the L3/L4 and handover between
+ sectors.
+
+ The BSC9132 SoC includes the following function and features:
+ - Power Architecture subsystem including two e500 processors with
+ 512-Kbyte shared L2 cache
+ - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
+ cache
+ - 32 Kbyte of shared M3 memory
+ - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
+ Processing (MAPLE-B2P)
+ - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
+ ECC), up to 1333 MHz data rate
+ - Dedicated security engine featuring trusted boot
+ - Two DMA controllers
+ - OCNDMA with four bidirectional channels
+ - SysDMA with sixteen bidirectional channels
+ - Interfaces
+ - Four-lane SerDes PHY
+ - PCI Express controller complies with the PEX Specification-Rev 2.0
+ - Two Common Public Radio Interface (CPRI) controller lanes
+ - High-speed USB 2.0 host and device controller with ULPI interface
+ - Enhanced secure digital (SD/MMC) host controller (eSDHC)
+ - Antenna interface controller (AIC), supporting four industry
+ standard JESD207/four custom ADI RF interfaces
+ - ADI lanes support both full duplex FDD support & half duplex TDD
+ - Universal Subscriber Identity Module (USIM) interface that
+ facilitates communication to SIM cards or Eurochip pre-paid phone
+ cards
+ - Two DUART, two eSPI, and two I2C controllers
+ - Integrated Flash memory controller (IFC)
+ - GPIO
+ - Sixteen 32-bit timers
+
+The SC3850 core subsystem consists of the following:
+ - 32 KB, 8-way, level 1 instruction cache (L1 ICache)
+ - 32 KB, 8-way, level 1 data cache (L1 DCache)
+ - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
+ - Memory management unit (MMU)
+ - Global interrupt controller ( GIC)
+ - Debug and profiling unit (DPU)
+ - Two 32-bit quad timers
+
+BSC9132QDS board Overview
+-------------------------
+ 2Gbyte DDR3 (on board DDR), Dual Ranki
+ 32Mbyte 16bit NOR flash
+ 128Mbyte 2K page size NAND Flash
+ 256 Kbit M24256 I2C EEPROM
+ 128 Mbit SPI Flash memory
+ SD slot
+ USB-ULPI
+ eTSEC1: Connected to SGMII PHY
+ eTSEC2: Connected to SGMII PHY
+ PCIe
+ CPRI
+ SerDes
+ I2C RTC
+ DUART interface: supports one UARTs up to 115200 bps for console display
+
+Frequency Combinations Supported
+--------------------------------
+Core MHz/CCB MHz/DDR(MT/s)
+1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
+ (SYSCLK = 100MHz, DDRCLK = 100MHz)
+2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
+ (SYSCLK = 100MHz, DDRCLK = 133MHz)
+
+Boot Methods Supported
+-----------------------
+1. NOR Flash
+2. NAND Flash
+3. SD Card
+4. SPI flash
+
+Default Boot Method
+--------------------
+NOR boot
+
+Building U-boot
+--------------
+To build the u-boot for BSC9132QDS:
+1. NOR Flash
+ make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
+ make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
+2. NAND Flash : It is currently not supported
+3. SPI Flash
+ make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
+ make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
+4. SD Card
+ make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
+ make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
+
+Memory map
+-----------
+ 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable
+ 0x8000_0000 0x8FFF_FFFF NOR Flash 256M
+ 0x9000_0000 0x9FFF_FFFF PCIe Memory 256M
+ 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M
+ 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M
+ 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M
+ 0xC000_0000 0xC000_7FFF M3 Memory 32K
+ 0xC001_0000 0xC001_FFFF PCI Express I/O 64K
+ 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
+ 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K
+ 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K
+ 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
+ 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
+ 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
+ 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
+ 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
+
+Flashing Images
+---------------
+To place a new u-boot image in the NAND flash and then boot
+with that new image temporarily, use this:
+ tftp 1000000 u-boot-nand.bin
+ nand erase 0 100000
+ nand write 1000000 0 100000
+ reset
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts
+
+Booting Linux
+-------------
+Place a linux uImage in the TFTP disk area.
+
+ tftp 1000000 uImage
+ tftp 2000000 rootfs.ext2.gz.uboot
+ tftp c00000 bsc9132qds.dtb
+ bootm 1000000 2000000 c00000
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
new file mode 100644
index 0000000..36a68db
--- /dev/null
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -0,0 +1,429 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <fsl_ddr_sdram.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+#include <flash.h>
+
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#endif
+
+#include "../common/qixis.h"
+DECLARE_GLOBAL_DATA_PTR;
+
+
+int board_early_init_f(void)
+{
+ struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+ return 0;
+}
+
+void board_config_serdes_mux(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+
+ switch (srds_cfg) {
+ /* PEX(1) PEX(2) CPRI 2 CPRI 1 */
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 22:
+ case 23:
+ case 24:
+ case 25:
+ case 26:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x03);
+ break;
+
+ /* PEX(1) PEX(2) SGMII1 CPRI 1 */
+ case 6:
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ case 27:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x01);
+ break;
+
+ /* PEX(1) PEX(2) SGMII1 SGMII2 */
+ case 11:
+ case 32:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x00);
+ break;
+
+ /* PEX(1) SGMII2 CPRI 2 CPRI 1 */
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ case 33:
+ case 34:
+ case 35:
+ case 36:
+ case 37:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x07);
+ break;
+
+ /* PEX(1) SGMII2 SGMII1 CPRI 1 */
+ case 17:
+ case 18:
+ case 19:
+ case 20:
+ case 21:
+ case 38:
+ case 39:
+ case 40:
+ case 41:
+ case 42:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x05);
+ break;
+
+ /* SGMII1 SGMII2 CPRI 2 CPRI 1 */
+ case 43:
+ case 44:
+ case 45:
+ case 46:
+ case 47:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
+ break;
+
+
+ default:
+ break;
+ }
+}
+
+/* Configure DSP DDR controller */
+void dsp_ddr_configure(void)
+{
+ /*
+ *There are separate DDR-controllers for DSP and PowerPC side DDR.
+ *copy the ddr controller settings from PowerPC side DDR controller
+ *to the DSP DDR controller as connected DDR memories are similar.
+ */
+ struct ccsr_ddr __iomem *pa_ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr temp_ddr;
+ struct ccsr_ddr __iomem *dsp_ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
+
+ memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
+ temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
+ temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
+ memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
+ dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
+}
+
+int board_early_init_r(void)
+{
+#ifndef CONFIG_SYS_NO_FLASH
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_64M, 1);
+
+ set_tlb(1, flashbase + 0x4000000,
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
+#endif
+ board_config_serdes_mux();
+ dsp_ddr_configure();
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif /* ifdef CONFIG_PCI */
+
+int checkboard(void)
+{
+ struct cpu_type *cpu;
+ u8 sw;
+
+ cpu = gd->arch.cpu;
+ printf("Board: %sQDS\n", cpu->name);
+
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
+ QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ printf("IFC chip select:");
+ switch (sw) {
+ case 0:
+ printf("NOR\n");
+ break;
+ case 2:
+ printf("Promjet\n");
+ break;
+ case 4:
+ printf("NAND\n");
+ break;
+ default:
+ printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+ break;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+
+#endif
+
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+ tsec_eth_init(bis, tsec_info, num);
+
+ #ifdef CONFIG_PCI
+ pci_eth_init(bis);
+ #endif
+
+ return 0;
+}
+#endif
+
+#define USBMUX_SEL_MASK 0xc0
+#define USBMUX_SEL_UART2 0xc0
+#define USBMUX_SEL_USB 0x40
+#define SPIMUX_SEL_UART3 0x80
+#define GPS_MUX_SEL_GPS 0x40
+
+#define TSEC_1588_CLKIN_MASK 0x03
+#define CON_XCVR_REF_CLK 0x00
+
+int misc_init_r(void)
+{
+ u8 val;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 porbmsr = in_be32(&gur->porbmsr);
+ u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
+
+ /*Configure 1588 clock-in source from RF Card*/
+ val = QIXIS_READ_I2C(brdcfg[5]);
+ QIXIS_WRITE_I2C(brdcfg[5],
+ (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
+
+ if (hwconfig("uart2") && hwconfig("usb1")) {
+ printf("UART2 and USB cannot work together on the board\n");
+ printf("Remove one from hwconfig and reset\n");
+ } else {
+ if (hwconfig("uart2")) {
+ val = QIXIS_READ_I2C(brdcfg[5]);
+ QIXIS_WRITE_I2C(brdcfg[5],
+ (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
+ clrbits_be32(&gur->pmuxcr3,
+ MPC85xx_PMUXCR3_USB_SEL_MASK);
+ setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
+ } else {
+ /* By default USB should be selected.
+ * Programming FPGA to select USB. */
+ val = QIXIS_READ_I2C(brdcfg[5]);
+ QIXIS_WRITE_I2C(brdcfg[5],
+ (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
+ }
+
+ }
+
+ if (hwconfig("sim")) {
+ if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+ romloc == PORBMSR_ROMLOC_NOR ||
+ romloc == PORBMSR_ROMLOC_SPI) {
+
+ val = QIXIS_READ_I2C(brdcfg[3]);
+ QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
+ clrbits_be32(&gur->pmuxcr,
+ MPC85xx_PMUXCR0_SIM_SEL_MASK);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
+ }
+ }
+
+ if (hwconfig("uart3")) {
+ if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+ romloc == PORBMSR_ROMLOC_NOR ||
+ romloc == PORBMSR_ROMLOC_SDHC) {
+
+ /* UART3 and SPI1 (Flashes) are muxed together */
+ val = QIXIS_READ_I2C(brdcfg[3]);
+ QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
+ clrbits_be32(&gur->pmuxcr3,
+ MPC85xx_PMUXCR3_UART3_SEL_MASK);
+ setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
+
+ /* MUX to select UART3 connection to J24 header
+ * or to GPS */
+ val = QIXIS_READ_I2C(brdcfg[6]);
+ if (hwconfig("gps"))
+ QIXIS_WRITE_I2C(brdcfg[6],
+ (val | GPS_MUX_SEL_GPS));
+ else
+ QIXIS_WRITE_I2C(brdcfg[6],
+ (val & ~(GPS_MUX_SEL_GPS)));
+ }
+ }
+ return 0;
+}
+
+void fdt_del_node_compat(void *blob, const char *compatible)
+{
+ int err;
+ int off = fdt_node_offset_by_compatible(blob, -1, compatible);
+ if (off < 0) {
+ printf("WARNING: could not find compatible node %s: %s.\n",
+ compatible, fdt_strerror(off));
+ return;
+ }
+ err = fdt_del_node(blob, off);
+ if (err < 0) {
+ printf("WARNING: could not remove %s: %s.\n",
+ compatible, fdt_strerror(err));
+ }
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+struct node_info nodes[] = {
+ { "cfi-flash", MTD_DEV_TYPE_NOR, },
+ { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
+};
+#endif
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ #if defined(CONFIG_PCI)
+ FT_FSL_PCI_SETUP;
+ #endif
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 porbmsr = in_be32(&gur->porbmsr);
+ u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
+
+ if (!(hwconfig("uart2") && hwconfig("usb1"))) {
+ /* If uart2 is there in hwconfig remove usb node from
+ * device tree */
+
+ if (hwconfig("uart2")) {
+ /* remove dts usb node */
+ fdt_del_node_compat(blob, "fsl-usb2-dr");
+ } else {
+ fdt_fixup_dr_usb(blob, bd);
+ fdt_del_node_and_alias(blob, "serial2");
+ }
+ }
+
+ if (hwconfig("uart3")) {
+ if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+ romloc == PORBMSR_ROMLOC_NOR ||
+ romloc == PORBMSR_ROMLOC_SDHC)
+ /* Delete SPI node from the device tree */
+ fdt_del_node_and_alias(blob, "spi1");
+ } else
+ fdt_del_node_and_alias(blob, "serial3");
+
+ if (hwconfig("sim")) {
+ if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+ romloc == PORBMSR_ROMLOC_NOR ||
+ romloc == PORBMSR_ROMLOC_SPI) {
+
+ /* remove dts sdhc node */
+ fdt_del_node_compat(blob, "fsl,esdhc");
+ } else if (romloc == PORBMSR_ROMLOC_SDHC) {
+
+ /* remove dts sim node */
+ fdt_del_node_compat(blob, "fsl,sim-v1.0");
+ printf("SIM & SDHC can't work together on the board");
+ printf("\nRemove sim from hwconfig and reset\n");
+ }
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
new file mode 100644
index 0000000..43f163a
--- /dev/null
+++ b/board/freescale/bsc9132qds/ddr.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+ {750, 850, &ddr_cfg_regs_800},
+ {1060, 1333, &ddr_cfg_regs_1333},
+ {0, 0, NULL}
+};
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+phys_size_t fixed_sdram(void)
+{
+ int i;
+ char buf[32];
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
+ phys_size_t ddr_size;
+ ulong ddr_freq, ddr_freq_mhz;
+
+ ddr_freq = get_ddr_freq(0);
+ ddr_freq_mhz = ddr_freq / 1000000;
+
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+ if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+ (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+ memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
+ sizeof(ddr_cfg_regs));
+ break;
+ }
+ }
+
+ if (fixed_ddr_parm_0[i].max_freq == 0)
+ panic("Unsupported DDR data rate %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
+ LAW_TRGT_IF_DDR_1) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+
+ return ddr_size;
+}
+
+#else /* CONFIG_SYS_DDR_RAW_TIMING */
+/* Micron MT41J512M8_187E */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 1073741824u,
+ .capacity = 1073741824u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1870,
+ .caslat_x = 0x1e << 4, /* 5,6,7,8 */
+ .taa_ps = 13125,
+ .twr_ps = 15000,
+ .trcd_ps = 13125,
+ .trrd_ps = 7500,
+ .trp_ps = 13125,
+ .tras_ps = 37500,
+ .trc_ps = 50625,
+ .trfc_ps = 160000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ int i;
+ popts->clk_adjust = 6;
+ popts->cpo_override = 0x1f;
+ popts->write_data_delay = 2;
+ popts->half_strength_driver_enable = 1;
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x8;
+ popts->trwt_override = 1;
+ popts->trwt = 0;
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+ popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+ }
+}
+
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c
new file mode 100644
index 0000000..e10de9a
--- /dev/null
+++ b/board/freescale/bsc9132qds/law.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_FPGA_BASE_PHYS
+ SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+#endif
+ SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
+ LAW_TRGT_IF_DSP_CCSR),
+ SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M,
+ LAW_TRGT_IF_OCN_DSP),
+ SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K,
+ LAW_TRGT_IF_CLASS_DSP),
+ SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G,
+ LAW_TRGT_IF_CLASS_DSP)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c
new file mode 100644
index 0000000..8f71431
--- /dev/null
+++ b/board/freescale/bsc9132qds/spl_minimal.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_init(void)
+{
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+#if CONFIG_DDR_CLK_FREQ == 100000000
+ __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+ __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+ __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
+ __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+
+ __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
+ __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
+ __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
+ __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
+ __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
+
+ __raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5);
+ __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+#elif CONFIG_DDR_CLK_FREQ == 133000000
+ __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+ __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+ __raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
+ __raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+
+ __raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode);
+ __raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2);
+ __raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval);
+ __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl);
+ __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl);
+
+ __raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5);
+ __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+#else
+ puts("Not a valid DDR Freq Found! Please Reset\n");
+#endif
+ asm volatile("sync;isync");
+ udelay(500);
+
+ /* Let the controller go */
+ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+ set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* Initialize the DDR3 */
+ sdram_init();
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
new file mode 100644
index 0000000..07febc2
--- /dev/null
+++ b/board/freescale/bsc9132qds/tlb.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_BOOT
+ SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR (PA) */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* CCSRBAR (DSP) */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
+ CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR,
+ MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_64M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000,
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_PCI
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_64K, 1),
+#endif
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_SYS_FPGA_BASE
+ /* *I*G - Board FPGA */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_1M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/c29xpcie/Kconfig b/board/freescale/c29xpcie/Kconfig
new file mode 100644
index 0000000..17369b8
--- /dev/null
+++ b/board/freescale/c29xpcie/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_C29XPCIE
+
+config SYS_BOARD
+ default "c29xpcie"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "C29XPCIE"
+
+endif
diff --git a/board/freescale/c29xpcie/MAINTAINERS b/board/freescale/c29xpcie/MAINTAINERS
new file mode 100644
index 0000000..db2e5e3
--- /dev/null
+++ b/board/freescale/c29xpcie/MAINTAINERS
@@ -0,0 +1,8 @@
+C29XPCIE BOARD
+M: Po Liu <po.liu@freescale.com>
+S: Maintained
+F: board/freescale/c29xpcie/
+F: include/configs/C29XPCIE.h
+F: configs/C29XPCIE_defconfig
+F: configs/C29XPCIE_NAND_defconfig
+F: configs/C29XPCIE_SPIFLASH_defconfig
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
new file mode 100644
index 0000000..818484a
--- /dev/null
+++ b/board/freescale/c29xpcie/Makefile
@@ -0,0 +1,25 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+MINIMAL=
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+obj-y += spl_minimal.o tlb.o law.o
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
+obj-y += c29xpcie.o
+obj-y += cpld.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
+endif
diff --git a/board/freescale/c29xpcie/README b/board/freescale/c29xpcie/README
new file mode 100644
index 0000000..3bc396b
--- /dev/null
+++ b/board/freescale/c29xpcie/README
@@ -0,0 +1,100 @@
+Overview
+=========
+C29XPCIE board is a series of Freescale PCIe add-in cards to perform
+as public key crypto accelerator or secure key management module.
+It includes C293PCIE board, C293PCIE board and C291PCIE board.
+The Freescale C29x family is a high performance crypto co-processor.
+It combines a single e500v2 core with necessary SEC engines.
+(maximum core frequency 1000/1200 MHz).
+
+The C29xPCIE board features are as follows:
+Memory subsystem:
+ - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+ - 64 Mbyte NOR flash single-chip memory
+ - 4 Gbyte NAND flash memory
+ - 1 Mbit AT24C1024 I2C EEPROM
+ - 16 Mbyte SPI memory
+
+Interfaces:
+ - 10/100/1000 BaseT Ethernet ports:
+ - eTSEC1, RGMII: one 10/100/1000 port
+ - eTSEC2, RGMII: one 10/100/1000 port
+ - DUART interface:
+ - DUART interface: supports two UARTs up to 115200 bps for
+ console display
+
+Board connectors:
+ - Mini-ITX power supply connector
+ - JTAG/COP for debugging
+
+Physical Memory Map on C29xPCIE
+===============================
+Address Start Address End Memory type
+0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR
+0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory
+0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash
+0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM
+0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO
+0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD
+0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR
+
+Serial Port Configuration on C29xPCIE
+=====================================
+Configure the serial port of the attached computer with the following values:
+ -Data rate: 115200 bps
+ -Number of data bits: 8
+ -Parity: None
+ -Number of Stop bits: 1
+ -Flow Control: Hardware/None
+
+Settings of DIP-switch
+======================
+ SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
+ SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
+Note: 1 stands for 'off', 0 stands for 'on'
+
+Build and program u-boot to NOR flash
+==================================
+1. Build u-boot.bin image example:
+ export ARCH=powerpc
+ export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+ make C293PCIE
+
+2. Program u-boot.bin into NOR flash
+ => tftp $loadaddr $uboot
+ => protect off eff40000 +$filesize
+ => erase eff40000 +$filesize
+ => cp.b $loadaddr eff40000 $filesize
+
+3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
+
+Alternate NOR bank
+==================
+There are four banks in C29XPCIE board, example to change bank booting:
+1. Program u-boot.bin into alternate NOR bank
+ => tftp $loadaddr $uboot
+ => protect off e9f40000 +$filesize
+ => erase e9f40000 +$filesize
+ => cp.b $loadaddr e9f40000 $filesize
+
+2. Switch to alternate NOR bank
+ => cpld_cmd reset altbank [bank]
+ - [bank] bank value select 1-4
+ - bank 1 on the flash 0x0000000~0x0ffffff
+ - bank 2 on the flash 0x1000000~0x1ffffff
+ - bank 3 on the flash 0x2000000~0x2ffffff
+ - bank 4 on the flash 0x3000000~0x3ffffff
+ or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
+
+Build and program u-boot to SPI flash
+==================================
+1. Build u-boot-spi.bin image
+ make C29xPCIE_SPIFLASH_config; make
+ Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
+
+2. Program u-boot-spi.bin into SPI flash
+ => tftp $loadaddr $uboot-spi
+ => sf erase 0 100000
+ => sf write $loadaddr 0 $filesize
+
+3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
new file mode 100644
index 0000000..d757709
--- /dev/null
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <pci.h>
+#include <fsl_ifc.h>
+#include <asm/fsl_pci.h>
+
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ printf("Board: %sPCIe, ", cpu->name);
+ printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+ /* Clock configuration to access CPLD using IFC(GPCM) */
+ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 1; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_64M, 1);
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif /* ifdef CONFIG_PCI */
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[2];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+ /* Register 1G MDIO bus */
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void fdt_del_sec(void *blob, int offset)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
+ CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
+ + offset * 0x20000)) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ offset++;
+ }
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+ struct cpu_type *cpu;
+
+ cpu = gd->arch.cpu;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+#if defined(CONFIG_PCI)
+ FT_FSL_PCI_SETUP;
+#endif
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+ if (cpu->soc_ver == SVR_C291)
+ fdt_del_sec(blob, 1);
+ else if (cpu->soc_ver == SVR_C292)
+ fdt_del_sec(blob, 2);
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c
new file mode 100644
index 0000000..37722da
--- /dev/null
+++ b/board/freescale/c29xpcie/cpld.c
@@ -0,0 +1,133 @@
+/**
+ * Copyright 2013 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.hu@freescale.com>
+ * Po Liu <Po.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the board-specific CPLD used on some Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
+ * CPLD register map
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "cpld.h"
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(u8 banksel)
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ u8 reg11;
+
+ reg11 = in_8(&cpld_data->flhcsr);
+
+ switch (banksel) {
+ case 1:
+ out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+ | CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);
+ break;
+ case 2:
+ out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+ | CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);
+ break;
+ case 3:
+ out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+ | CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);
+ break;
+ case 4:
+ out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
+ | CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);
+ break;
+ default:
+ printf("Invalid value! [1-4]\n");
+ return;
+ }
+
+ udelay(100);
+ do_reset(NULL, 0, 0, NULL);
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+ cpld_set_altbank(4);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ printf("chipid1 = 0x%02x\n", in_8(&cpld_data->chipid1));
+ printf("chipid2 = 0x%02x\n", in_8(&cpld_data->chipid2));
+ printf("hwver = 0x%02x\n", in_8(&cpld_data->hwver));
+ printf("cpldver = 0x%02x\n", in_8(&cpld_data->cpldver));
+ printf("rstcon = 0x%02x\n", in_8(&cpld_data->rstcon));
+ printf("flhcsr = 0x%02x\n", in_8(&cpld_data->flhcsr));
+ printf("wdcsr = 0x%02x\n", in_8(&cpld_data->wdcsr));
+ printf("wdkick = 0x%02x\n", in_8(&cpld_data->wdkick));
+ printf("fancsr = 0x%02x\n", in_8(&cpld_data->fancsr));
+ printf("ledcsr = 0x%02x\n", in_8(&cpld_data->ledcsr));
+ printf("misc = 0x%02x\n", in_8(&cpld_data->misccsr));
+ printf("bootor = 0x%02x\n", in_8(&cpld_data->bootor));
+ printf("bootcfg1 = 0x%02x\n", in_8(&cpld_data->bootcfg1));
+ printf("bootcfg2 = 0x%02x\n", in_8(&cpld_data->bootcfg2));
+ printf("bootcfg3 = 0x%02x\n", in_8(&cpld_data->bootcfg3));
+ printf("bootcfg4 = 0x%02x\n", in_8(&cpld_data->bootcfg4));
+ putc('\n');
+}
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+ unsigned char value;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (!strcmp(argv[2], "altbank") && argv[3]) {
+ value = (u8)simple_strtoul(argv[3], NULL, 16);
+ cpld_set_altbank(value);
+ } else if (!argv[2])
+ cpld_set_defbank();
+ else
+ cmd_usage(cmdtp);
+#ifdef DEBUG
+ } else if (strcmp(argv[1], "dump") == 0) {
+ cpld_dump_regs();
+#endif
+ } else
+ rc = cmd_usage(cmdtp);
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
+ "Reset the board using the CPLD sequencer",
+ "reset - hard reset to default bank 4\n"
+ "cpld_cmd reset altbank [bank]- reset to alternate bank\n"
+ " - [bank] bank value select 1-4\n"
+ " - bank 1 on the flash 0x0000000~0x0ffffff\n"
+ " - bank 2 on the flash 0x1000000~0x1ffffff\n"
+ " - bank 3 on the flash 0x2000000~0x2ffffff\n"
+ " - bank 4 on the flash 0x3000000~0x3ffffff\n"
+#ifdef DEBUG
+ "cpld_cmd dump - display the CPLD registers\n"
+#endif
+ );
+#endif
diff --git a/board/freescale/c29xpcie/cpld.h b/board/freescale/c29xpcie/cpld.h
new file mode 100644
index 0000000..20862a3
--- /dev/null
+++ b/board/freescale/c29xpcie/cpld.h
@@ -0,0 +1,40 @@
+/**
+ * Copyright 2013 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.Hu@freescale.com>
+ * Po Liu <Po.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/*
+ * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
+ */
+struct cpld_data {
+ u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */
+ u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */
+ u8 hwver; /* 0x2 - Hardware Version Register */
+ u8 cpldver; /* 0x3 - Software Version Register */
+ u8 res[12];
+ u8 rstcon; /* 0x10 - Reset control register */
+ u8 flhcsr; /* 0x11 - Flash control and status Register */
+ u8 wdcsr; /* 0x12 - Watchdog control and status Register */
+ u8 wdkick; /* 0x13 - Watchdog kick Register */
+ u8 fancsr; /* 0x14 - Fan control and status Register */
+ u8 ledcsr; /* 0x15 - LED control and status Register */
+ u8 misccsr; /* 0x16 - Misc control and status Register */
+ u8 bootor; /* 0x17 - Boot configure override Register */
+ u8 bootcfg1; /* 0x18 - Boot configure 1 Register */
+ u8 bootcfg2; /* 0x19 - Boot configure 2 Register */
+ u8 bootcfg3; /* 0x1a - Boot configure 3 Register */
+ u8 bootcfg4; /* 0x1b - Boot configure 4 Register */
+};
+
+#define CPLD_BANKSEL_EN 0x02
+#define CPLD_BANKSEL_MASK 0x3f
+#define CPLD_SELECT_BANK1 0xc0
+#define CPLD_SELECT_BANK2 0x80
+#define CPLD_SELECT_BANK3 0x40
+#define CPLD_SELECT_BANK4 0x00
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
new file mode 100644
index 0000000..7c915b0
--- /dev/null
+++ b/board/freescale/c29xpcie/ddr.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+#include "cpld.h"
+
+#define C29XPCIE_HARDWARE_REVA 0x40
+/*
+ * Micron MT41J128M16HA-15E
+ * */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 536870912u,
+ .capacity = 536870912u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 8,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 14,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 2,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1650,
+ .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
+ .taa_ps = 14050,
+ .twr_ps = 15000,
+ .trcd_ps = 13500,
+ .trrd_ps = 75000,
+ .trp_ps = 13500,
+ .tras_ps = 40000,
+ .trc_ps = 49500,
+ .trfc_ps = 160000,
+ .twtr_ps = 75000,
+ .trtp_ps = 75000,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 30000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ int i;
+
+ popts->clk_adjust = 4;
+ popts->cpo_override = 0x1f;
+ popts->write_data_delay = 4;
+ popts->half_strength_driver_enable = 1;
+ popts->bstopre = 0x3cf;
+ popts->quad_rank_present = 1;
+ popts->rtt_override = 1;
+ popts->rtt_override_value = 1;
+ popts->dynamic_power = 1;
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x4;
+ popts->trwt_override = 1;
+ popts->trwt = 0;
+
+ if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
+ popts->ecc_mode = 0;
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+ popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+ }
+}
+
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+ int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd,
+ sizeof(generic_spd_eeprom_t));
+
+ if (ret) {
+ printf("DDR: failed to read SPD from address %u\n",
+ i2c_address);
+ memset(spd, 0, sizeof(generic_spd_eeprom_t));
+ }
+}
diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c
new file mode 100644
index 0000000..80e5fff
--- /dev/null
+++ b/board/freescale/c29xpcie/law.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
+ LAW_TRGT_IF_PLATFORM_SRAM),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
new file mode 100644
index 0000000..2111711
--- /dev/null
+++ b/board/freescale/c29xpcie/spl.c
@@ -0,0 +1,77 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+ /* relocate environment function pointers etc. */
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("TPL\n");
+#else
+ puts("SPL\n");
+#endif
+
+ nand_boot();
+}
diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c
new file mode 100644
index 0000000..8f96b67
--- /dev/null
+++ b/board/freescale/c29xpcie/spl_minimal.c
@@ -0,0 +1,63 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot...\n");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("SPL\n");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
new file mode 100644
index 0000000..c5abed0
--- /dev/null
+++ b/board/freescale/c29xpcie/tlb.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_PCI
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256K, 1),
+#endif
+#endif
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_64K, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64K, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
+ CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
+ CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
+ CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
new file mode 100644
index 0000000..14af660
--- /dev/null
+++ b/board/freescale/common/Makefile
@@ -0,0 +1,75 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-$(CONFIG_FSL_CADMUS) += cadmus.o
+obj-$(CONFIG_FSL_VIA) += cds_via.o
+obj-$(CONFIG_FMAN_ENET) += fman.o
+obj-$(CONFIG_FSL_PIXIS) += pixis.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
+obj-$(CONFIG_VID) += vid.o
+endif
+obj-$(CONFIG_FSL_QIXIS) += qixis.o
+obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
+endif
+obj-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o
+ifndef CONFIG_RAMBOOT_PBL
+obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o
+endif
+
+obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o
+
+ifdef CONFIG_ARM
+obj-$(CONFIG_DEEP_SLEEP) += arm_sleep.o
+else
+obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o
+endif
+
+obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o
+
+obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
+obj-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
+obj-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
+
+obj-$(CONFIG_MPC8536DS) += ics307_clk.o
+obj-$(CONFIG_MPC8572DS) += ics307_clk.o
+obj-$(CONFIG_P1022DS) += ics307_clk.o
+obj-$(CONFIG_P2020DS) += ics307_clk.o
+obj-$(CONFIG_P3041DS) += ics307_clk.o
+obj-$(CONFIG_P4080DS) += ics307_clk.o
+obj-$(CONFIG_P5020DS) += ics307_clk.o
+obj-$(CONFIG_P5040DS) += ics307_clk.o
+obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
+obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
+obj-$(CONFIG_ZM7300) += zm7300.o
+obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
+
+obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
+
+# deal with common files for P-series corenet based devices
+obj-$(CONFIG_P2041RDB) += p_corenet/
+obj-$(CONFIG_P3041DS) += p_corenet/
+obj-$(CONFIG_P4080DS) += p_corenet/
+obj-$(CONFIG_P5020DS) += p_corenet/
+obj-$(CONFIG_P5040DS) += p_corenet/
+
+obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o
+endif
diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
new file mode 100644
index 0000000..8edf878
--- /dev/null
+++ b/board/freescale/common/arm_sleep.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT)
+#error " Deep sleep needs non-secure mode support. "
+#else
+#include <asm/secure.h>
+#endif
+#include <asm/armv7.h>
+#include <asm/cache.h>
+
+#if defined(CONFIG_LS102XA)
+#include <asm/arch/immap_ls102xa.h>
+#endif
+
+#include "sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __weak board_mem_sleep_setup(void)
+{
+}
+
+void __weak board_sleep_prepare(void)
+{
+}
+
+bool is_warm_boot(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
+ return 1;
+
+ return 0;
+}
+
+void fsl_dp_disable_console(void)
+{
+ gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+}
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR training which corrupts the data
+ * in there. This function will restore them.
+ */
+static void dp_ddr_restore(void)
+{
+ u64 *src, *dst;
+ int i;
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ /* get the address of ddr date from SPARECR3 */
+ src = (u64 *)in_le32(&scfg->sparecr[2]);
+ dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+
+ for (i = 0; i < DDR_BUFF_LEN / 8; i++)
+ *dst++ = *src++;
+
+ flush_dcache_all();
+}
+
+static void dp_resume_prepare(void)
+{
+ dp_ddr_restore();
+ board_sleep_prepare();
+ armv7_init_nonsec();
+ cleanup_before_linux();
+}
+
+int fsl_dp_resume(void)
+{
+ u32 start_addr;
+ void (*kernel_resume)(void);
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ if (!is_warm_boot())
+ return 0;
+
+ dp_resume_prepare();
+
+ /* Get the entry address and jump to kernel */
+ start_addr = in_le32(&scfg->sparecr[1]);
+ debug("Entry address is 0x%08x\n", start_addr);
+ kernel_resume = (void (*)(void))start_addr;
+ secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
+
+ return 0;
+}
diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c
new file mode 100644
index 0000000..dad6847
--- /dev/null
+++ b/board/freescale/common/cadmus.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+
+
+/*
+ * CADMUS Board System Registers
+ */
+#ifndef CONFIG_SYS_CADMUS_BASE_REG
+#define CONFIG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
+#endif
+
+typedef struct cadmus_reg {
+ u_char cm_ver; /* Board version */
+ u_char cm_csr; /* General control/status */
+ u_char cm_rst; /* Reset control */
+ u_char cm_hsclk; /* High speed clock */
+ u_char cm_hsxclk; /* High speed clock extended */
+ u_char cm_led; /* LED data */
+ u_char cm_pci; /* PCI control/status */
+ u_char cm_dma; /* DMA control */
+ u_char cm_reserved[248]; /* Total 256 bytes */
+} cadmus_reg_t;
+
+
+unsigned int
+get_board_version(void)
+{
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+
+ return cadmus->cm_ver;
+}
+
+
+unsigned long
+get_clock_freq(void)
+{
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+
+ uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
+
+ if (pci1_speed == 0) {
+ return 33333333;
+ } else if (pci1_speed == 1) {
+ return 66666666;
+ } else {
+ /* Really, unknown. Be safe? */
+ return 33333333;
+ }
+}
+
+
+unsigned int
+get_pci_slot(void)
+{
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+
+ /*
+ * PCI slot in USER bits CSR[6:7] by convention.
+ */
+ return ((cadmus->cm_csr >> 6) & 0x3) + 1;
+}
+
+
+unsigned int
+get_pci_dual(void)
+{
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
+
+ /*
+ * PCI DUAL in CM_PCI[3]
+ */
+ return cadmus->cm_pci & 0x10;
+}
diff --git a/board/freescale/common/cadmus.h b/board/freescale/common/cadmus.h
new file mode 100644
index 0000000..7867192
--- /dev/null
+++ b/board/freescale/common/cadmus.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CADMUS_H_
+#define __CADMUS_H_
+
+
+/*
+ * CADMUS Board System Register interface.
+ */
+
+/*
+ * Returns board version register.
+ */
+extern unsigned int get_board_version(void);
+
+/*
+ * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
+ */
+extern unsigned long get_clock_freq(void);
+
+
+/*
+ * Returns 1 - 4, as found in the USER CSR[6:7] bits.
+ */
+extern unsigned int get_pci_slot(void);
+
+
+/*
+ * Returns PCI DUAL as found in CM_PCI[3].
+ */
+extern unsigned int get_pci_dual(void);
+
+
+#endif /* __CADMUS_H_ */
diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c
new file mode 100644
index 0000000..571dfbb
--- /dev/null
+++ b/board/freescale/common/cds_pci_ft.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include "cadmus.h"
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+static void cds_pci_fixup(void *blob)
+{
+ int node;
+ const char *path;
+ int len, slot, i;
+ u32 *map = NULL, *piccells = NULL;
+ int off, cells;
+
+ node = fdt_path_offset(blob, "/aliases");
+ if (node >= 0) {
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ node = fdt_path_offset(blob, path);
+ if (node >= 0) {
+ map = fdt_getprop_w(blob, node, "interrupt-map", &len);
+ }
+ /* Each item in "interrupt-map" property is translated with
+ * following cells:
+ * PCI #address-cells, PCI #interrupt-cells,
+ * PIC address, PIC #address-cells, PIC #interrupt-cells.
+ */
+ cells = fdt_getprop_u32_default(blob, path, "#address-cells", 1);
+ cells += fdt_getprop_u32_default(blob, path, "#interrupt-cells", 1);
+ off = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*(map+cells)));
+ if (off <= 0)
+ return;
+ cells += 1;
+ piccells = (u32 *)fdt_getprop(blob, off, "#address-cells", NULL);
+ if (piccells == NULL)
+ return;
+ cells += *piccells;
+ piccells = (u32 *)fdt_getprop(blob, off, "#interrupt-cells", NULL);
+ if (piccells == NULL)
+ return;
+ cells += *piccells;
+ }
+ }
+
+ if (map) {
+ len /= sizeof(u32);
+
+ slot = get_pci_slot();
+
+ for (i=0;i<len;i+=cells) {
+ /* We rotate the interrupt pins so that the mapping
+ * changes depending on the slot the carrier card is in.
+ */
+ map[3] = ((map[3] + slot - 2) % 4) + 1;
+ map+=cells;
+ }
+ }
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+ cds_pci_fixup(blob);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/common/cds_via.c b/board/freescale/common/cds_via.c
new file mode 100644
index 0000000..028b093
--- /dev/null
+++ b/board/freescale/common/cds_via.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+
+/* Config the VIA chip */
+void mpc85xx_config_via(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pci_dev_t bridge;
+ unsigned int cmdstat;
+
+ /* Enable USB and IDE functions */
+ pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
+
+ pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+ cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
+ pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+
+ /*
+ * Force the backplane P2P bridge to have a window
+ * open from 0x00000000-0x00001fff in PCI I/O space.
+ * This allows legacy I/O (i8259, etc) on the VIA
+ * southbridge to be accessed.
+ */
+ bridge = PCI_BDF(0,BRIDGE_ID,0);
+ pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
+ pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
+ pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
+ pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
+}
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+ /*
+ * Since the P2P window was forced to cover the fixed
+ * legacy I/O addresses, it is necessary to manually
+ * place the base addresses for the IDE and USB functions
+ * within this window.
+ */
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
+}
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
+}
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
+}
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
+}
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
+}
diff --git a/board/freescale/common/dcu_sii9022a.c b/board/freescale/common/dcu_sii9022a.c
new file mode 100644
index 0000000..2da627e
--- /dev/null
+++ b/board/freescale/common/dcu_sii9022a.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include <i2c.h>
+#include <linux/fb.h>
+
+#define PIXEL_CLK_LSB_REG 0x00
+#define PIXEL_CLK_MSB_REG 0x01
+#define VERT_FREQ_LSB_REG 0x02
+#define VERT_FREQ_MSB_REG 0x03
+#define TOTAL_PIXELS_LSB_REG 0x04
+#define TOTAL_PIXELS_MSB_REG 0x05
+#define TOTAL_LINES_LSB_REG 0x06
+#define TOTAL_LINES_MSB_REG 0x07
+#define TPI_INBUS_FMT_REG 0x08
+#define TPI_INPUT_FMT_REG 0x09
+#define TPI_OUTPUT_FMT_REG 0x0A
+#define TPI_SYS_CTRL_REG 0x1A
+#define TPI_PWR_STAT_REG 0x1E
+#define TPI_AUDIO_HANDING_REG 0x25
+#define TPI_AUDIO_INTF_REG 0x26
+#define TPI_AUDIO_FREQ_REG 0x27
+#define TPI_SET_PAGE_REG 0xBC
+#define TPI_SET_OFFSET_REG 0xBD
+#define TPI_RW_ACCESS_REG 0xBE
+#define TPI_TRANS_MODE_REG 0xC7
+
+#define TPI_INBUS_CLOCK_RATIO_1 (1 << 6)
+#define TPI_INBUS_FULL_PIXEL_WIDE (1 << 5)
+#define TPI_INBUS_RISING_EDGE (1 << 4)
+#define TPI_INPUT_CLR_DEPTH_8BIT (0 << 6)
+#define TPI_INPUT_VRANGE_EXPAN_AUTO (0 << 2)
+#define TPI_INPUT_CLR_RGB (0 << 0)
+#define TPI_OUTPUT_CLR_DEPTH_8BIT (0 << 6)
+#define TPI_OUTPUT_VRANGE_COMPRE_AUTO (0 << 2)
+#define TPI_OUTPUT_CLR_HDMI_RGB (0 << 0)
+#define TPI_SYS_TMDS_OUTPUT (0 << 4)
+#define TPI_SYS_AV_NORAML (0 << 3)
+#define TPI_SYS_AV_MUTE (1 << 3)
+#define TPI_SYS_DVI_MODE (0 << 0)
+#define TPI_SYS_HDMI_MODE (1 << 0)
+#define TPI_PWR_STAT_MASK (3 << 0)
+#define TPI_PWR_STAT_D0 (0 << 0)
+#define TPI_AUDIO_PASS_BASIC (0 << 0)
+#define TPI_AUDIO_INTF_I2S (2 << 6)
+#define TPI_AUDIO_INTF_NORMAL (0 << 4)
+#define TPI_AUDIO_TYPE_PCM (1 << 0)
+#define TPI_AUDIO_SAMP_SIZE_16BIT (1 << 6)
+#define TPI_AUDIO_SAMP_FREQ_44K (2 << 3)
+#define TPI_SET_PAGE_SII9022A 0x01
+#define TPI_SET_OFFSET_SII9022A 0x82
+#define TPI_RW_EN_SRC_TERMIN (1 << 0)
+#define TPI_TRANS_MODE_ENABLE (0 << 7)
+
+/* Programming of Silicon SIi9022a HDMI Transmitter */
+int dcu_set_dvi_encoder(struct fb_videomode *videomode)
+{
+ u8 temp;
+ u16 temp1, temp2;
+ u32 temp3;
+
+ i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
+
+ /* Enable TPI transmitter mode */
+ temp = TPI_TRANS_MODE_ENABLE;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_TRANS_MODE_REG, 1, &temp, 1);
+
+ /* Enter into D0 state, full operation */
+ i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
+ temp &= ~TPI_PWR_STAT_MASK;
+ temp |= TPI_PWR_STAT_D0;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
+
+ /* Enable source termination */
+ temp = TPI_SET_PAGE_SII9022A;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_PAGE_REG, 1, &temp, 1);
+ temp = TPI_SET_OFFSET_SII9022A;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_OFFSET_REG, 1, &temp, 1);
+
+ i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
+ temp |= TPI_RW_EN_SRC_TERMIN;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
+
+ /* Set TPI system control */
+ temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SYS_CTRL_REG, 1, &temp, 1);
+
+ /* Set pixel clock */
+ temp1 = PICOS2KHZ(videomode->pixclock) / 10;
+ temp = (u8)(temp1 & 0xFF);
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_LSB_REG, 1, &temp, 1);
+ temp = (u8)(temp1 >> 8);
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_MSB_REG, 1, &temp, 1);
+
+ /* Set total pixels per line */
+ temp1 = videomode->hsync_len + videomode->left_margin +
+ videomode->xres + videomode->right_margin;
+ temp = (u8)(temp1 & 0xFF);
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_LSB_REG, 1, &temp, 1);
+ temp = (u8)(temp1 >> 8);
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_MSB_REG, 1, &temp, 1);
+
+ /* Set total lines */
+ temp2 = videomode->vsync_len + videomode->upper_margin +
+ videomode->yres + videomode->lower_margin;
+ temp = (u8)(temp2 & 0xFF);
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_LSB_REG, 1, &temp, 1);
+ temp = (u8)(temp2 >> 8);
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_MSB_REG, 1, &temp, 1);
+
+ /* Set vertical frequency in Hz */
+ temp3 = temp1 * temp2;
+ temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3;
+ temp1 = (u16)temp3 * 100;
+ temp = (u8)(temp1 & 0xFF);
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_LSB_REG, 1, &temp, 1);
+ temp = (u8)(temp1 >> 8);
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_MSB_REG, 1, &temp, 1);
+
+ /* Set TPI input bus and pixel repetition data */
+ temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE |
+ TPI_INBUS_RISING_EDGE;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INBUS_FMT_REG, 1, &temp, 1);
+
+ /* Set TPI AVI Input format data */
+ temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO |
+ TPI_INPUT_CLR_RGB;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INPUT_FMT_REG, 1, &temp, 1);
+
+ /* Set TPI AVI Output format data */
+ temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO |
+ TPI_OUTPUT_CLR_HDMI_RGB;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_OUTPUT_FMT_REG, 1, &temp, 1);
+
+ /* Set TPI audio configuration write data */
+ temp = TPI_AUDIO_PASS_BASIC;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_HANDING_REG, 1, &temp, 1);
+
+ temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL |
+ TPI_AUDIO_TYPE_PCM;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_INTF_REG, 1, &temp, 1);
+
+ temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_FREQ_REG, 1, &temp, 1);
+
+ return 0;
+}
diff --git a/board/freescale/common/dcu_sii9022a.h b/board/freescale/common/dcu_sii9022a.h
new file mode 100644
index 0000000..de76733
--- /dev/null
+++ b/board/freescale/common/dcu_sii9022a.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DCU_HDMI_SII9022A__
+#define __DCU_HDMI_SII9022A__
+
+/* Programming of Silicon SII9022A connector HDMI Transmitter*/
+int dcu_set_dvi_encoder(struct fb_videomode *videomode);
+
+#endif
diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c
new file mode 100644
index 0000000..82ce870
--- /dev/null
+++ b/board/freescale/common/diu_ch7301.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
+ * Wang Dongsheng <dongsheng.wang@freescale.com>
+ *
+ * This file is copied and modified from the original t1040qds/diu.c.
+ * Encoder can be used in T104x and LSx Platform.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <stdio_dev.h>
+#include <i2c.h>
+
+#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
+#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33
+#define I2C_DVI_PLL_DIVIDER_REG 0x34
+#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35
+#define I2C_DVI_PLL_FILTER_REG 0x36
+#define I2C_DVI_TEST_PATTERN_REG 0x48
+#define I2C_DVI_POWER_MGMT_REG 0x49
+#define I2C_DVI_LOCK_STATE_REG 0x4D
+#define I2C_DVI_SYNC_POLARITY_REG 0x56
+
+/*
+ * Set VSYNC/HSYNC to active high. This is polarity of sync signals
+ * from DIU->DVI. The DIU default is active igh, so DVI is set to
+ * active high.
+ */
+#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
+
+#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
+#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
+#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
+#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
+#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
+#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
+
+/* Clear test pattern */
+#define I2C_DVI_TEST_PATTERN_VAL 0x18
+/* Exit Power-down mode */
+#define I2C_DVI_POWER_MGMT_VAL 0xC0
+
+/* Monitor polarity is handled via DVI Sync Polarity Register */
+#define I2C_DVI_SYNC_POLARITY_VAL 0x00
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock)
+{
+ int ret;
+ u8 temp;
+
+ temp = I2C_DVI_TEST_PATTERN_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
+ &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select proper dvi test pattern\n");
+ return ret;
+ }
+ temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
+ 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi input data format\n");
+ return ret;
+ }
+
+ /* Set Sync polarity register */
+ temp = I2C_DVI_SYNC_POLARITY_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
+ &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi syc polarity\n");
+ return ret;
+ }
+
+ /* Set PLL registers based on pixel clock rate*/
+ if (pixclock > 65000000) {
+ temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll charge_cntl\n");
+ return ret;
+ }
+ temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll divider\n");
+ return ret;
+ }
+ temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll filter\n");
+ return ret;
+ }
+ } else {
+ temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll charge_cntl\n");
+ return ret;
+ }
+ temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll divider\n");
+ return ret;
+ }
+ temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll filter\n");
+ return ret;
+ }
+ }
+
+ temp = I2C_DVI_POWER_MGMT_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
+ &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi power mgmt\n");
+ return ret;
+ }
+
+ udelay(500);
+
+ return 0;
+}
diff --git a/board/freescale/common/diu_ch7301.h b/board/freescale/common/diu_ch7301.h
new file mode 100644
index 0000000..8b6ead0
--- /dev/null
+++ b/board/freescale/common/diu_ch7301.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DIU_HDMI_CH7301__
+#define __DIU_HDMI_CH7301__
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock);
+
+#endif
diff --git a/board/freescale/common/eeprom.h b/board/freescale/common/eeprom.h
new file mode 100644
index 0000000..efdba4e
--- /dev/null
+++ b/board/freescale/common/eeprom.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EEPROM_H_
+#define __EEPROM_H_
+
+
+/*
+ * EEPROM Board System Register interface.
+ */
+
+
+/*
+ * CPU Board Revision
+ */
+#define MPC85XX_CPU_BOARD_REV(maj, min) ((((maj)&0xff) << 8) | ((min) & 0xff))
+#define MPC85XX_CPU_BOARD_MAJOR(rev) (((rev) >> 8) & 0xff)
+#define MPC85XX_CPU_BOARD_MINOR(rev) ((rev) & 0xff)
+
+#define MPC85XX_CPU_BOARD_REV_UNKNOWN MPC85XX_CPU_BOARD_REV(0,0)
+#define MPC85XX_CPU_BOARD_REV_1_0 MPC85XX_CPU_BOARD_REV(1,0)
+#define MPC85XX_CPU_BOARD_REV_1_1 MPC85XX_CPU_BOARD_REV(1,1)
+
+/*
+ * Returns CPU board revision register as a 16-bit value with
+ * the Major in the high byte, and Minor in the low byte.
+ */
+extern unsigned int get_cpu_board_revision(void);
+
+
+#endif /* __CADMUS_H_ */
diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c
new file mode 100644
index 0000000..9dc5402
--- /dev/null
+++ b/board/freescale/common/fman.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <libfdt_env.h>
+#include <fdt_support.h>
+
+#include <fm_eth.h>
+#include <asm/fsl_serdes.h>
+
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) The name of an alias that points to the ethernet-phy node (usually inside
+ * a virtual MDIO node)
+ *
+ * ... update that Ethernet node's phy-handle property to point to the
+ * ethernet-phy node. This is how we link an Ethernet node to its PHY, so each
+ * PHY in a virtual MDIO node must have an alias.
+ *
+ * Returns 0 on success, or a negative FDT error code on error.
+ */
+int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
+ const char *alias)
+{
+ int offset;
+ unsigned int ph;
+ const char *path;
+
+ /* Get a path to the node that 'alias' points to */
+ path = fdt_get_alias(fdt, alias);
+ if (!path)
+ return -FDT_ERR_BADPATH;
+
+ /* Get the offset of that node */
+ offset = fdt_path_offset(fdt, path);
+ if (offset < 0)
+ return offset;
+
+ ph = fdt_create_phandle(fdt, offset);
+ if (!ph)
+ return -FDT_ERR_BADPHANDLE;
+
+ offset = fdt_node_offset_by_compat_reg(fdt, compat, addr);
+ if (offset < 0)
+ return offset;
+
+ return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph));
+}
+
+/*
+ * Return the SerDes device enum for a given Fman port
+ *
+ * This function just maps the fm_port namespace to the srds_prtcl namespace.
+ */
+enum srds_prtcl serdes_device_from_fm_port(enum fm_port port)
+{
+ static const enum srds_prtcl srds_table[] = {
+ [FM1_DTSEC1] = SGMII_FM1_DTSEC1,
+ [FM1_DTSEC2] = SGMII_FM1_DTSEC2,
+ [FM1_DTSEC3] = SGMII_FM1_DTSEC3,
+ [FM1_DTSEC4] = SGMII_FM1_DTSEC4,
+ [FM1_DTSEC5] = SGMII_FM1_DTSEC5,
+ [FM1_10GEC1] = XAUI_FM1,
+ [FM2_DTSEC1] = SGMII_FM2_DTSEC1,
+ [FM2_DTSEC2] = SGMII_FM2_DTSEC2,
+ [FM2_DTSEC3] = SGMII_FM2_DTSEC3,
+ [FM2_DTSEC4] = SGMII_FM2_DTSEC4,
+ [FM2_DTSEC5] = SGMII_FM2_DTSEC5,
+ [FM2_10GEC1] = XAUI_FM2,
+ };
+
+ if ((port < FM1_DTSEC1) || (port > FM2_10GEC1))
+ return NONE;
+ else
+ return srds_table[port];
+}
diff --git a/board/freescale/common/fman.h b/board/freescale/common/fman.h
new file mode 100644
index 0000000..ff819c4
--- /dev/null
+++ b/board/freescale/common/fman.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FMAN_BOARD_HELPER__
+#define __FMAN_BOARD_HELPER__
+
+int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
+ const char *alias);
+
+enum srds_prtcl serdes_device_from_fm_port(enum fm_port port);
+
+#endif
diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c
new file mode 100644
index 0000000..e683be3
--- /dev/null
+++ b/board/freescale/common/ics307_clk.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "ics307_clk.h"
+
+#if defined(CONFIG_FSL_NGPIXIS)
+#include "ngpixis.h"
+#define fpga_reg pixis
+#elif defined(CONFIG_FSL_QIXIS)
+#include "qixis.h"
+#define fpga_reg ((struct qixis *)QIXIS_BASE)
+#else
+#include "pixis.h"
+#define fpga_reg pixis
+#endif
+
+/* define for SYS CLK or CLK1Frequency */
+#define TTL 1
+#define CLK2 0
+#define CRYSTAL 0
+#define MAX_VDW (511 + 8)
+#define MAX_RDW (127 + 2)
+#define MIN_VDW (4 + 8)
+#define MIN_RDW (1 + 2)
+#define NUM_OD_SETTING 8
+/*
+ * These defines cover the industrial temperature range part,
+ * for commercial, change below to 400000 and 55000, respectively
+ */
+#define MAX_VCO 360000
+#define MIN_VCO 60000
+
+/* decode S[0-2] to Output Divider (OD) */
+static u8 ics307_s_to_od[] = {
+ 10, 2, 8, 4, 5, 7, 3, 6
+};
+
+/*
+ * Find one solution to generate required frequency for SYSCLK
+ * out_freq: KHz, required frequency to the SYSCLK
+ * the result will be retuned with component RDW, VDW, OD, TTL,
+ * CLK2 and crystal
+ */
+unsigned long ics307_sysclk_calculator(unsigned long out_freq)
+{
+ const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
+ unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
+ unsigned long tmp_out, diff, result = 0;
+ int found = 0;
+
+ for (odp = 0; odp < NUM_OD_SETTING; odp++) {
+ od = ics307_s_to_od[odp];
+ if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
+ continue;
+ for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
+ /* Calculate the VDW */
+ vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
+ if (vdw > MAX_VDW)
+ vdw = MAX_VDW;
+ if (vdw < MIN_VDW)
+ continue;
+ /* Calculate the temp out frequency */
+ tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
+ diff = max(out_freq, tmp_out) - min(out_freq, tmp_out);
+ /*
+ * calculate the percent, the precision is 1/1000
+ * If greater than 1/1000, continue
+ * otherwise, we think the solution is we required
+ */
+ if (diff * 1000 / out_freq > 1)
+ continue;
+ else {
+ s_vdw = vdw;
+ s_rdw = rdw;
+ s_odp = odp;
+ found = 1;
+ break;
+ }
+ }
+ }
+
+ if (found)
+ result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
+ CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
+
+ debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
+ ics307_s_to_od[s_odp]);
+ return result;
+}
+
+/*
+ * Calculate frequency being generated by ICS307-02 clock chip based upon
+ * the control bytes being programmed into it.
+ */
+static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
+{
+ const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
+ unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
+ unsigned long rdw = cw2 & 0x7F;
+ unsigned long od = ics307_s_to_od[cw0 & 0x7];
+ unsigned long freq;
+
+ /*
+ * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
+ *
+ * cw0: C1 C0 TTL F1 F0 S2 S1 S0
+ * cw1: V8 V7 V6 V5 V4 V3 V2 V1
+ * cw2: V0 R6 R5 R4 R3 R2 R1 R0
+ *
+ * R6:R0 = Reference Divider Word (RDW)
+ * V8:V0 = VCO Divider Word (VDW)
+ * S2:S0 = Output Divider Select (OD)
+ * F1:F0 = Function of CLK2 Output
+ * TTL = duty cycle
+ * C1:C0 = internal load capacitance for cyrstal
+ *
+ */
+
+ freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
+
+ debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
+ freq);
+ return freq;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return ics307_clk_freq(
+ in_8(&fpga_reg->sclk[0]),
+ in_8(&fpga_reg->sclk[1]),
+ in_8(&fpga_reg->sclk[2]));
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return ics307_clk_freq(
+ in_8(&fpga_reg->dclk[0]),
+ in_8(&fpga_reg->dclk[1]),
+ in_8(&fpga_reg->dclk[2]));
+}
diff --git a/board/freescale/common/ics307_clk.h b/board/freescale/common/ics307_clk.h
new file mode 100644
index 0000000..4c8a1c8
--- /dev/null
+++ b/board/freescale/common/ics307_clk.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ICS_CLK_H_
+#define __ICS_CLK_H_ 1
+
+#ifndef __ASSEMBLY__
+
+extern unsigned long get_board_sys_clk(void);
+extern unsigned long get_board_ddr_clk(void);
+extern unsigned long ics307_sysclk_calculator(unsigned long out_freq);
+#endif
+
+#endif /* __ICS_CLK_H_ */
diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.c b/board/freescale/common/idt8t49n222a_serdes_clk.c
new file mode 100644
index 0000000..d347162
--- /dev/null
+++ b/board/freescale/common/idt8t49n222a_serdes_clk.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Shaveta Leekha <shaveta@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "idt8t49n222a_serdes_clk.h"
+
+#define DEVICE_ID_REG 0x00
+
+static int check_pll_status(u8 idt_addr)
+{
+ u8 val = 0;
+ int ret;
+
+ ret = i2c_read(idt_addr, 0x17, 1, &val, 1);
+ if (ret < 0) {
+ printf("IDT:0x%x could not read status register from device.\n",
+ idt_addr);
+ return ret;
+ }
+
+ if (val & 0x04) {
+ debug("idt8t49n222a PLL is LOCKED: %x\n", val);
+ } else {
+ printf("idt8t49n222a PLL is not LOCKED: %x\n", val);
+ return -1;
+ }
+
+ return 0;
+}
+
+int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
+ enum serdes_refclk refclk1,
+ enum serdes_refclk refclk2, u8 feedback)
+{
+ u8 dev_id = 0;
+ int i, ret;
+
+ debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n",
+ idt_addr);
+
+ ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1);
+ if (ret < 0) {
+ debug("IDT:0x%x could not read DEV_ID from device.\n",
+ idt_addr);
+ return ret;
+ }
+
+ if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) {
+ debug("IDT: device at address 0x%x is not idt8t49n222a.\n",
+ idt_addr);
+ }
+
+ if (serdes_num != 1 && serdes_num != 2) {
+ debug("serdes_num should be 1 for SerDes1 and"
+ " 2 for SerDes2.\n");
+ return -1;
+ }
+
+ if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88)
+ || (refclk1 != SERDES_REFCLK_122_88
+ && refclk2 == SERDES_REFCLK_122_88)) {
+ debug("Only one refclk at 122.88MHz is not supported."
+ " Please set both refclk1 & refclk2 to 122.88MHz"
+ " or both not to 122.88MHz.\n");
+ return -1;
+ }
+
+ if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88
+ && refclk1 != SERDES_REFCLK_125
+ && refclk1 != SERDES_REFCLK_156_25) {
+ debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz"
+ " or 156.25MHz.\n");
+ return -1;
+ }
+
+ if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88
+ && refclk2 != SERDES_REFCLK_125
+ && refclk2 != SERDES_REFCLK_156_25) {
+ debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz"
+ " or 156.25MHz.\n");
+ return -1;
+ }
+
+ if (feedback != 0 && feedback != 1) {
+ debug("valid values for feedback are 0(default) or 1.\n");
+ return -1;
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
+ */
+ if (refclk1 == SERDES_REFCLK_122_88 &&
+ refclk2 == SERDES_REFCLK_122_88) {
+ printf("Setting refclk1:122.88 and refclk2:122.88\n");
+ for (i = 0; i < NUM_IDT_REGS; i++)
+ i2c_reg_write(idt_addr, idt_conf_122_88[i][0],
+ idt_conf_122_88[i][1]);
+
+ if (feedback) {
+ for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++)
+ i2c_reg_write(idt_addr,
+ idt_conf_122_88_feedback[i][0],
+ idt_conf_122_88_feedback[i][1]);
+ }
+ }
+
+ if (refclk1 != SERDES_REFCLK_122_88 &&
+ refclk2 != SERDES_REFCLK_122_88) {
+ for (i = 0; i < NUM_IDT_REGS; i++)
+ i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0],
+ idt_conf_not_122_88[i][1]);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 100MHz Refclk2 = 125MHz
+ */
+ if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) {
+ printf("Setting refclk1:100 and refclk2:125\n");
+ i2c_reg_write(idt_addr, 0x11, 0x10);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 125MHz Refclk2 = 125MHz
+ */
+ if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) {
+ printf("Setting refclk1:125 and refclk2:125\n");
+ i2c_reg_write(idt_addr, 0x10, 0x10);
+ i2c_reg_write(idt_addr, 0x11, 0x10);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 125MHz Refclk2 = 100MHz
+ */
+ if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) {
+ printf("Setting refclk1:125 and refclk2:100\n");
+ i2c_reg_write(idt_addr, 0x10, 0x10);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 156.25MHz Refclk2 = 156.25MHz
+ */
+ if (refclk1 == SERDES_REFCLK_156_25 &&
+ refclk2 == SERDES_REFCLK_156_25) {
+ printf("Setting refclk1:156.25 and refclk2:156.25\n");
+ for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+ i2c_reg_write(idt_addr, idt_conf_156_25[i][0],
+ idt_conf_156_25[i][1]);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 100MHz Refclk2 = 156.25MHz
+ */
+ if (refclk1 == SERDES_REFCLK_100 &&
+ refclk2 == SERDES_REFCLK_156_25) {
+ printf("Setting refclk1:100 and refclk2:156.25\n");
+ for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+ i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0],
+ idt_conf_100_156_25[i][1]);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 125MHz Refclk2 = 156.25MHz
+ */
+ if (refclk1 == SERDES_REFCLK_125 &&
+ refclk2 == SERDES_REFCLK_156_25) {
+ printf("Setting refclk1:125 and refclk2:156.25\n");
+ for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+ i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0],
+ idt_conf_125_156_25[i][1]);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 156.25MHz Refclk2 = 100MHz
+ */
+ if (refclk1 == SERDES_REFCLK_156_25 &&
+ refclk2 == SERDES_REFCLK_100) {
+ printf("Setting refclk1:156.25 and refclk2:100\n");
+ for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+ i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0],
+ idt_conf_156_25_100[i][1]);
+ }
+
+ /* Configuring IDT for output refclks as
+ * Refclk1 = 156.25MHz Refclk2 = 125MHz
+ */
+ if (refclk1 == SERDES_REFCLK_156_25 &&
+ refclk2 == SERDES_REFCLK_125) {
+ printf("Setting refclk1:156.25 and refclk2:125\n");
+ for (i = 0; i < NUM_IDT_REGS_156_25; i++)
+ i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0],
+ idt_conf_156_25_125[i][1]);
+ }
+
+ /* waiting for maximum of 1 second if PLL doesn'r get locked
+ * initially. then check the status again.
+ */
+ if (check_pll_status(idt_addr)) {
+ mdelay(1000);
+ if (check_pll_status(idt_addr))
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.h b/board/freescale/common/idt8t49n222a_serdes_clk.h
new file mode 100644
index 0000000..787bdd9
--- /dev/null
+++ b/board/freescale/common/idt8t49n222a_serdes_clk.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Shaveta Leekha <shaveta@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IDT8T49N222A_SERDES_CLK_H_
+#define __IDT8T49N222A_SERDES_CLK_H_ 1
+
+#include <common.h>
+#include <i2c.h>
+#include "qixis.h"
+#include "../b4860qds/b4860qds_qixis.h"
+#include <errno.h>
+
+#define NUM_IDT_REGS 23
+#define NUM_IDT_REGS_FEEDBACK 12
+#define NUM_IDT_REGS_156_25 11
+
+/* CLK */
+enum serdes_refclk {
+ SERDES_REFCLK_100, /* refclk 100Mhz */
+ SERDES_REFCLK_122_88, /* refclk 122.88Mhz */
+ SERDES_REFCLK_125, /* refclk 125Mhz */
+ SERDES_REFCLK_156_25, /* refclk 156.25Mhz */
+ SERDES_REFCLK_NONE = -1,
+};
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
+ */
+static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
+ {0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00},
+ {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
+ {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
+ {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12},
+ {0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
+ {0x16, 0xA0} };
+
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
+ */
+static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
+ {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00},
+ {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
+ {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
+ {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14},
+ {0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
+ {0x16, 0xA0} };
+
+/* Reconfiguration values for some of IDT registers for
+ * Output Refclks:
+ * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
+ * and with feedback as 1
+ */
+static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
+ {0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07},
+ {0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B},
+ {0x14, 0x00}, {0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
+ */
+static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+ {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+ {0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
+ {0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 100MHz Refclk2 : 156.25MHz
+ */
+static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+ {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+ {0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
+ {0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 125MHz Refclk2 : 156.25MHz
+ */
+static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+ {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+ {0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
+ {0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 156.25MHz Refclk2 : 100MHz
+ */
+static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+ {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+ {0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C},
+ {0x15, 0xE8} };
+
+/* configuration values for IDT registers for Output Refclks:
+ * Refclk1 : 156.25MHz Refclk2 : 125MHz
+ */
+static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03},
+ {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
+ {0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C},
+ {0x15, 0xE8} };
+
+int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
+ enum serdes_refclk refclk1,
+ enum serdes_refclk refclk2, u8 feedback);
+
+#endif /*__IDT8T49N222A_SERDES_CLK_H_ */
diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c
new file mode 100644
index 0000000..6154c9c
--- /dev/null
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ls102xa_stream_id.h>
+
+void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
+{
+ uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
+ int i;
+
+ for (i = 0; i < num; i++)
+ out_be32(scfg + id[i].offset, id[i].stream_id);
+}
diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c
new file mode 100644
index 0000000..f924e7f
--- /dev/null
+++ b/board/freescale/common/mpc85xx_sleep.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/immap_85xx.h>
+#include "sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __weak board_mem_sleep_setup(void)
+{
+}
+
+void __weak board_sleep_prepare(void)
+{
+}
+
+bool is_warm_boot(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
+ return 1;
+
+ return 0;
+}
+
+void fsl_dp_disable_console(void)
+{
+ gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+}
+
+/*
+ * When wakeup from deep sleep, the first 128 bytes space
+ * will be used to do DDR training which corrupts the data
+ * in there. This function will restore them.
+ */
+static void dp_ddr_restore(void)
+{
+ volatile u64 *src, *dst;
+ int i;
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+ /* get the address of ddr date from SPARECR3 */
+ src = (u64 *)in_be32(&scfg->sparecr[2]);
+ dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+
+ for (i = 0; i < DDR_BUFF_LEN / 8; i++)
+ *dst++ = *src++;
+
+ flush_dcache();
+}
+
+static void dp_resume_prepare(void)
+{
+ dp_ddr_restore();
+
+ board_sleep_prepare();
+
+ l2cache_init();
+#if defined(CONFIG_RAMBOOT_PBL)
+ disable_cpc_sram();
+#endif
+ enable_cpc();
+}
+
+int fsl_dp_resume(void)
+{
+ u32 start_addr;
+ void (*kernel_resume)(void);
+ struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+
+ if (!is_warm_boot())
+ return 0;
+
+ dp_resume_prepare();
+
+ /* Get the entry address and jump to kernel */
+ start_addr = in_be32(&scfg->sparecr[1]);
+ debug("Entry address is 0x%08x\n", start_addr);
+ kernel_resume = (void (*)(void))start_addr;
+ kernel_resume();
+
+ return 0;
+}
diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c
new file mode 100644
index 0000000..0cb076a
--- /dev/null
+++ b/board/freescale/common/ngpixis.c
@@ -0,0 +1,250 @@
+/**
+ * Copyright 2010-2011 Freescale Semiconductor
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ *
+ * A "switch" is black rectangular block on the motherboard. It contains
+ * eight "bits". The ngPIXIS has a set of memory-mapped registers (SWx) that
+ * shadow the actual physical switches. There is also another set of
+ * registers (ENx) that tell the ngPIXIS which bits of SWx should actually be
+ * used to override the values of the bits in the physical switches.
+ *
+ * The following macros need to be defined:
+ *
+ * PIXIS_BASE - The virtual address of the base of the PIXIS register map
+ *
+ * PIXIS_LBMAP_SWITCH - The switch number (i.e. the "x" in "SWx"). This value
+ * is used in the PIXIS_SW() macro to determine which offset in
+ * the PIXIS register map corresponds to the physical switch that controls
+ * the boot bank.
+ *
+ * PIXIS_LBMAP_MASK - A bit mask the defines which bits in SWx to use.
+ *
+ * PIXIS_LBMAP_SHIFT - The shift value that corresponds to PIXIS_LBMAP_MASK.
+ *
+ * PIXIS_LBMAP_ALTBANK - The value to program into SWx to tell the ngPIXIS to
+ * boot from the alternate bank.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "ngpixis.h"
+
+static u8 __pixis_read(unsigned int reg)
+{
+ void *p = (void *)PIXIS_BASE;
+
+ return in_8(p + reg);
+}
+u8 pixis_read(unsigned int reg) __attribute__((weak, alias("__pixis_read")));
+
+static void __pixis_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)PIXIS_BASE;
+
+ out_8(p + reg, value);
+}
+void pixis_write(unsigned int reg, u8 value)
+ __attribute__((weak, alias("__pixis_write")));
+
+/*
+ * Reset the board. This ignores the ENx registers.
+ */
+void __pixis_reset(void)
+{
+ PIXIS_WRITE(rst, 0);
+
+ while (1);
+}
+void pixis_reset(void) __attribute__((weak, alias("__pixis_reset")));
+
+/*
+ * Reset the board. Like pixis_reset(), but it honors the ENx registers.
+ */
+void __pixis_bank_reset(void)
+{
+ PIXIS_WRITE(vctl, 0);
+ PIXIS_WRITE(vctl, 1);
+
+ while (1);
+}
+void pixis_bank_reset(void) __attribute__((weak, alias("__pixis_bank_reset")));
+
+/**
+ * Set the boot bank to the power-on default bank
+ */
+void __clear_altbank(void)
+{
+ u8 reg;
+
+ /* Tell the ngPIXIS to use this the bits in the physical switch for the
+ * boot bank value, instead of the SWx register. We need to be careful
+ * only to set the bits in SWx that correspond to the boot bank.
+ */
+ reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en);
+ reg &= ~PIXIS_LBMAP_MASK;
+ PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg);
+}
+void clear_altbank(void) __attribute__((weak, alias("__clear_altbank")));
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void __set_altbank(void)
+{
+ u8 reg;
+
+ /* Program the alternate bank number into the SWx register.
+ */
+ reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].sw);
+ reg = (reg & ~PIXIS_LBMAP_MASK) | PIXIS_LBMAP_ALTBANK;
+ PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].sw, reg);
+
+ /* Tell the ngPIXIS to use this the bits in the SWx register for the
+ * boot bank value, instead of the physical switch. We need to be
+ * careful only to set the bits in SWx that correspond to the boot bank.
+ */
+ reg = PIXIS_READ(s[PIXIS_LBMAP_SWITCH - 1].en);
+ reg |= PIXIS_LBMAP_MASK;
+ PIXIS_WRITE(s[PIXIS_LBMAP_SWITCH - 1].en, reg);
+}
+void set_altbank(void) __attribute__((weak, alias("__set_altbank")));
+
+#ifdef DEBUG
+static void pixis_dump_regs(void)
+{
+ unsigned int i;
+
+ printf("id=%02x\n", PIXIS_READ(id));
+ printf("arch=%02x\n", PIXIS_READ(arch));
+ printf("scver=%02x\n", PIXIS_READ(scver));
+ printf("csr=%02x\n", PIXIS_READ(csr));
+ printf("rst=%02x\n", PIXIS_READ(rst));
+ printf("aux=%02x\n", PIXIS_READ(aux));
+ printf("spd=%02x\n", PIXIS_READ(spd));
+ printf("brdcfg0=%02x\n", PIXIS_READ(brdcfg0));
+ printf("brdcfg1=%02x\n", PIXIS_READ(brdcfg1));
+ printf("addr=%02x\n", PIXIS_READ(addr));
+ printf("data=%02x\n", PIXIS_READ(data));
+ printf("led=%02x\n", PIXIS_READ(led));
+ printf("vctl=%02x\n", PIXIS_READ(vctl));
+ printf("vstat=%02x\n", PIXIS_READ(vstat));
+ printf("vcfgen0=%02x\n", PIXIS_READ(vcfgen0));
+ printf("ocmcsr=%02x\n", PIXIS_READ(ocmcsr));
+ printf("ocmmsg=%02x\n", PIXIS_READ(ocmmsg));
+ printf("gmdbg=%02x\n", PIXIS_READ(gmdbg));
+ printf("sclk=%02x%02x%02x\n",
+ PIXIS_READ(sclk[0]), PIXIS_READ(sclk[1]), PIXIS_READ(sclk[2]));
+ printf("dclk=%02x%02x%02x\n",
+ PIXIS_READ(dclk[0]), PIXIS_READ(dclk[1]), PIXIS_READ(dclk[2]));
+ printf("watch=%02x\n", PIXIS_READ(watch));
+
+ for (i = 0; i < 8; i++) {
+ printf("SW%u=%02x/%02x ", i + 1,
+ PIXIS_READ(s[i].sw), PIXIS_READ(s[i].en));
+ }
+ putc('\n');
+}
+#endif
+
+void pixis_sysclk_set(unsigned long sysclk)
+{
+ unsigned long freq_word;
+ u8 sclk0, sclk1, sclk2;
+
+ freq_word = ics307_sysclk_calculator(sysclk);
+ sclk2 = freq_word & 0xff;
+ sclk1 = (freq_word >> 8) & 0xff;
+ sclk0 = (freq_word >> 16) & 0xff;
+
+ /* set SYSCLK enable bit */
+ PIXIS_WRITE(vcfgen0, 0x01);
+
+ /* SYSCLK to required frequency */
+ PIXIS_WRITE(sclk[0], sclk0);
+ PIXIS_WRITE(sclk[1], sclk1);
+ PIXIS_WRITE(sclk[2], sclk2);
+}
+
+int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int i;
+ unsigned long sysclk;
+ char *p_altbank = NULL;
+#ifdef DEBUG
+ char *p_dump = NULL;
+#endif
+ char *unknown_param = NULL;
+
+ /* No args is a simple reset request.
+ */
+ if (argc <= 1)
+ pixis_reset();
+
+ for (i = 1; i < argc; i++) {
+ if (strcmp(argv[i], "altbank") == 0) {
+ p_altbank = argv[i];
+ continue;
+ }
+
+#ifdef DEBUG
+ if (strcmp(argv[i], "dump") == 0) {
+ p_dump = argv[i];
+ continue;
+ }
+#endif
+ if (strcmp(argv[i], "sysclk") == 0) {
+ sysclk = simple_strtoul(argv[i + 1], NULL, 0);
+ i += 1;
+ pixis_sysclk_set(sysclk);
+ continue;
+ }
+
+ unknown_param = argv[i];
+ }
+
+ if (unknown_param) {
+ printf("Invalid option: %s\n", unknown_param);
+ return 1;
+ }
+
+#ifdef DEBUG
+ if (p_dump) {
+ pixis_dump_regs();
+
+ /* 'dump' ignores other commands */
+ return 0;
+ }
+#endif
+
+ if (p_altbank)
+ set_altbank();
+ else
+ clear_altbank();
+
+ pixis_bank_reset();
+
+ /* Shouldn't be reached. */
+ return 0;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char pixis_help_text[] =
+ "- hard reset to default bank\n"
+ "pixis_reset altbank - reset to alternate bank\n"
+#ifdef DEBUG
+ "pixis_reset dump - display the PIXIS registers\n"
+#endif
+ "pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n";
+#endif
+
+U_BOOT_CMD(
+ pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
+ "Reset the board using the FPGA sequencer", pixis_help_text
+ );
diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h
new file mode 100644
index 0000000..364e749
--- /dev/null
+++ b/board/freescale/common/ngpixis.h
@@ -0,0 +1,61 @@
+/**
+ * Copyright 2010-2011 Freescale Semiconductor
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/* ngPIXIS register set. Hopefully, this won't change too much over time.
+ * Feel free to add board-specific #ifdefs where necessary.
+ */
+typedef struct ngpixis {
+ u8 id;
+ u8 arch;
+ u8 scver;
+ u8 csr;
+ u8 rst;
+ u8 serclk;
+ u8 aux;
+ u8 spd;
+ u8 brdcfg0;
+ u8 brdcfg1; /* On some boards, this register is called 'dma' */
+ u8 addr;
+ u8 brdcfg2;
+ u8 gpiodir;
+ u8 data;
+ u8 led;
+ u8 tag;
+ u8 vctl;
+ u8 vstat;
+ u8 vcfgen0;
+ u8 res4;
+ u8 ocmcsr;
+ u8 ocmmsg;
+ u8 gmdbg;
+ u8 res5[2];
+ u8 sclk[3];
+ u8 dclk[3];
+ u8 watch;
+ struct {
+ u8 sw;
+ u8 en;
+ } s[9]; /* s[0]..s[7] is SW1..SW8, and s[8] is SW11 */
+} __attribute__ ((packed)) ngpixis_t;
+
+/* Pointer to the PIXIS register set */
+#define pixis ((ngpixis_t *)PIXIS_BASE)
+
+/* The PIXIS SW register that corresponds to board switch X, where x >= 1 */
+#define PIXIS_SW(x) (pixis->s[(x) - 1].sw)
+
+/* The PIXIS EN register that corresponds to board switch X, where x >= 1 */
+#define PIXIS_EN(x) (pixis->s[(x) - 1].en)
+
+u8 pixis_read(unsigned int reg);
+void pixis_write(unsigned int reg, u8 value);
+
+#define PIXIS_READ(reg) pixis_read(offsetof(ngpixis_t, reg))
+#define PIXIS_WRITE(reg, value) pixis_write(offsetof(ngpixis_t, reg), value)
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
new file mode 100644
index 0000000..d7de982
--- /dev/null
+++ b/board/freescale/common/ns_access.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ns_access.h>
+
+void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
+{
+ u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
+ u32 *reg;
+ uint32_t val;
+ int i;
+
+ for (i = 0; i < num; i++) {
+ reg = base + ns_dev[i].ind / 2;
+ val = in_be32(reg);
+ if (ns_dev[i].ind % 2 == 0) {
+ val &= 0x0000ffff;
+ val |= ns_dev[i].val << 16;
+ } else {
+ val &= 0xffff0000;
+ val |= ns_dev[i].val;
+ }
+ out_be32(reg, val);
+ }
+}
diff --git a/board/freescale/common/p_corenet/Makefile b/board/freescale/common/p_corenet/Makefile
new file mode 100644
index 0000000..1f399d2
--- /dev/null
+++ b/board/freescale/common/p_corenet/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += law.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += tlb.o
diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c
new file mode 100644
index 0000000..53af26a
--- /dev/null
+++ b/board/freescale/common/p_corenet/law.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef PIXIS_BASE_PHYS
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#endif
+#ifdef CPLD_BASE_PHYS
+ SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/common/p_corenet/pci.c b/board/freescale/common/p_corenet/pci.c
new file mode 100644
index 0000000..9f4f808
--- /dev/null
+++ b/board/freescale/common/p_corenet/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
new file mode 100644
index 0000000..8148e46
--- /dev/null
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+#ifdef CPLD_BASE
+ SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+#endif
+
+#ifdef PIXIS_BASE
+ SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+#endif
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+ * space is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+ * fetching ucode and ENV from master
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 17, BOOKE_PAGESZ_1M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
new file mode 100644
index 0000000..2cd1794
--- /dev/null
+++ b/board/freescale/common/pfuze.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+
+struct pmic *pfuze_common_init(unsigned char i2cbus)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg;
+
+ ret = power_pfuze100_init(i2cbus);
+ if (ret)
+ return NULL;
+
+ p = pmic_get("PFUZE100");
+ ret = pmic_probe(p);
+ if (ret)
+ return NULL;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ /* Set SW1AB stanby volage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
+ reg &= ~SW1x_STBY_MASK;
+ reg |= SW1x_0_975V;
+ pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+ /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PUZE_100_SW1ABCONF, ®);
+ reg &= ~SW1xCONF_DVSSPEED_MASK;
+ reg |= SW1xCONF_DVSSPEED_4US;
+ pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+ /* Set SW1C standby voltage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
+ reg &= ~SW1x_STBY_MASK;
+ reg |= SW1x_0_975V;
+ pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+ /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
+ reg &= ~SW1xCONF_DVSSPEED_MASK;
+ reg |= SW1xCONF_DVSSPEED_4US;
+ pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+ return p;
+}
diff --git a/board/freescale/common/pfuze.h b/board/freescale/common/pfuze.h
new file mode 100644
index 0000000..7a4126c
--- /dev/null
+++ b/board/freescale/common/pfuze.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PFUZE_BOARD_HELPER__
+#define __PFUZE_BOARD_HELPER__
+
+struct pmic *pfuze_common_init(unsigned char i2cbus);
+
+#endif
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
new file mode 100644
index 0000000..cbba399
--- /dev/null
+++ b/board/freescale/common/pixis.c
@@ -0,0 +1,542 @@
+/*
+ * Copyright 2006,2010 Freescale Semiconductor
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#define pixis_base (u8 *)PIXIS_BASE
+
+/*
+ * Simple board reset.
+ */
+void pixis_reset(void)
+{
+ out_8(pixis_base + PIXIS_RST, 0);
+
+ while (1);
+}
+
+/*
+ * Per table 27, page 58 of MPC8641HPCN spec.
+ */
+static int set_px_sysclk(unsigned long sysclk)
+{
+ u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
+
+ switch (sysclk) {
+ case 33:
+ sysclk_s = 0x04;
+ sysclk_r = 0x04;
+ sysclk_v = 0x07;
+ sysclk_aux = 0x00;
+ break;
+ case 40:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x20;
+ sysclk_aux = 0x01;
+ break;
+ case 50:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x2A;
+ sysclk_aux = 0x02;
+ break;
+ case 66:
+ sysclk_s = 0x01;
+ sysclk_r = 0x04;
+ sysclk_v = 0x04;
+ sysclk_aux = 0x03;
+ break;
+ case 83:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x4B;
+ sysclk_aux = 0x04;
+ break;
+ case 100:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x5C;
+ sysclk_aux = 0x05;
+ break;
+ case 134:
+ sysclk_s = 0x06;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x3B;
+ sysclk_aux = 0x06;
+ break;
+ case 166:
+ sysclk_s = 0x06;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x4B;
+ sysclk_aux = 0x07;
+ break;
+ default:
+ printf("Unsupported SYSCLK frequency.\n");
+ return 0;
+ }
+
+ vclkh = (sysclk_s << 5) | sysclk_r;
+ vclkl = sysclk_v;
+
+ out_8(pixis_base + PIXIS_VCLKH, vclkh);
+ out_8(pixis_base + PIXIS_VCLKL, vclkl);
+
+ out_8(pixis_base + PIXIS_AUX, sysclk_aux);
+
+ return 1;
+}
+
+/* Set the CFG_SYSPLL bits
+ *
+ * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
+ * read_from_px_regs() is called.
+ */
+static int set_px_mpxpll(unsigned long mpxpll)
+{
+ switch (mpxpll) {
+ case 2:
+ case 4:
+ case 6:
+ case 8:
+ case 10:
+ case 12:
+ case 14:
+ case 16:
+ clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
+ return 1;
+ }
+
+ printf("Unsupported MPXPLL ratio.\n");
+ return 0;
+}
+
+static int set_px_corepll(unsigned long corepll)
+{
+ u8 val;
+
+ switch (corepll) {
+ case 20:
+ val = 0x08;
+ break;
+ case 25:
+ val = 0x0C;
+ break;
+ case 30:
+ val = 0x10;
+ break;
+ case 35:
+ val = 0x1C;
+ break;
+ case 40:
+ val = 0x14;
+ break;
+ case 45:
+ val = 0x0E;
+ break;
+ default:
+ printf("Unsupported COREPLL ratio.\n");
+ return 0;
+ }
+
+ clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
+ return 1;
+}
+
+#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
+#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
+#endif
+
+/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
+ *
+ * The PIXIS can be programmed to look at either the on-board dip switches
+ * or various other PIXIS registers to determine the values for COREPLL,
+ * MPXPLL, and SYSCLK.
+ *
+ * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
+ * register that tells the pixis to use the various PIXIS register.
+ */
+static void read_from_px_regs(int set)
+{
+ u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
+
+ if (set)
+ tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+ else
+ tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
+
+ out_8(pixis_base + PIXIS_VCFGEN0, tmp);
+}
+
+/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
+ * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
+ */
+#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
+#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
+#endif
+
+/* Configure the source of the boot location
+ *
+ * The PIXIS can be programmed to look at either the on-board dip switches
+ * or the PX_VBOOT[LBMAP] register to determine where we should boot.
+ *
+ * If we want to boot from the alternate boot bank, we need to tell the PIXIS
+ * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
+ */
+static void read_from_px_regs_altbank(int set)
+{
+ u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
+
+ if (set)
+ tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+ else
+ tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
+
+ out_8(pixis_base + PIXIS_VCFGEN1, tmp);
+}
+
+/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
+ * tells the PIXIS what the alternate flash bank is.
+ *
+ * Note that it's not really a mask. It contains the actual LBMAP bits that
+ * must be set to select the alternate bank. This code assumes that the
+ * primary bank has these bits set to 0, and the alternate bank has these
+ * bits set to 1.
+ */
+#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
+#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
+#endif
+
+/* Tell the PIXIS to boot from the default flash bank
+ *
+ * Program the default flash bank into the VBOOT register. This register is
+ * used only if PX_VCFGEN1[FLASH]=1.
+ */
+static void clear_altbank(void)
+{
+ clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
+}
+
+/* Tell the PIXIS to boot from the alternate flash bank
+ *
+ * Program the alternate flash bank into the VBOOT register. This register is
+ * used only if PX_VCFGEN1[FLASH]=1.
+ */
+static void set_altbank(void)
+{
+ setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
+}
+
+/* Reset the board with watchdog disabled.
+ *
+ * This respects the altbank setting.
+ */
+static void set_px_go(void)
+{
+ /* Disable the VELA sequencer and watchdog */
+ clrbits_8(pixis_base + PIXIS_VCTL, 9);
+
+ /* Reboot by starting the VELA sequencer */
+ setbits_8(pixis_base + PIXIS_VCTL, 0x1);
+
+ while (1);
+}
+
+/* Reset the board with watchdog enabled.
+ *
+ * This respects the altbank setting.
+ */
+static void set_px_go_with_watchdog(void)
+{
+ /* Disable the VELA sequencer */
+ clrbits_8(pixis_base + PIXIS_VCTL, 1);
+
+ /* Enable the watchdog and reboot by starting the VELA sequencer */
+ setbits_8(pixis_base + PIXIS_VCTL, 0x9);
+
+ while (1);
+}
+
+/* Disable the watchdog
+ *
+ */
+static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ /* Disable the VELA sequencer and the watchdog */
+ clrbits_8(pixis_base + PIXIS_VCTL, 9);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ diswd, 1, 0, pixis_disable_watchdog_cmd,
+ "Disable watchdog timer",
+ ""
+);
+
+#ifdef CONFIG_PIXIS_SGMII_CMD
+
+/* Enable or disable SGMII mode for a TSEC
+ */
+static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int which_tsec = -1;
+ unsigned char mask;
+ unsigned char switch_mask;
+
+ if ((argc > 2) && (strcmp(argv[1], "all") != 0))
+ which_tsec = simple_strtoul(argv[1], NULL, 0);
+
+ switch (which_tsec) {
+#ifdef CONFIG_TSEC1
+ case 1:
+ mask = PIXIS_VSPEED2_TSEC1SER;
+ switch_mask = PIXIS_VCFGEN1_TSEC1SER;
+ break;
+#endif
+#ifdef CONFIG_TSEC2
+ case 2:
+ mask = PIXIS_VSPEED2_TSEC2SER;
+ switch_mask = PIXIS_VCFGEN1_TSEC2SER;
+ break;
+#endif
+#ifdef CONFIG_TSEC3
+ case 3:
+ mask = PIXIS_VSPEED2_TSEC3SER;
+ switch_mask = PIXIS_VCFGEN1_TSEC3SER;
+ break;
+#endif
+#ifdef CONFIG_TSEC4
+ case 4:
+ mask = PIXIS_VSPEED2_TSEC4SER;
+ switch_mask = PIXIS_VCFGEN1_TSEC4SER;
+ break;
+#endif
+ default:
+ mask = PIXIS_VSPEED2_MASK;
+ switch_mask = PIXIS_VCFGEN1_MASK;
+ break;
+ }
+
+ /* Toggle whether the switches or FPGA control the settings */
+ if (!strcmp(argv[argc - 1], "switch"))
+ clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
+ else
+ setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
+
+ /* If it's not the switches, enable or disable SGMII, as specified */
+ if (!strcmp(argv[argc - 1], "on"))
+ clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
+ else if (!strcmp(argv[argc - 1], "off"))
+ setbits_8(pixis_base + PIXIS_VSPEED2, mask);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
+ "pixis_set_sgmii"
+ " - Enable or disable SGMII mode for a given TSEC \n",
+ "\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
+ " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
+ " on - enables SGMII\n"
+ " off - disables SGMII\n"
+ " switch - use switch settings"
+);
+
+#endif
+
+/*
+ * This function takes the non-integral cpu:mpx pll ratio
+ * and converts it to an integer that can be used to assign
+ * FPGA register values.
+ * input: strptr i.e. argv[2]
+ */
+static unsigned long strfractoint(char *strptr)
+{
+ int i, j;
+ int mulconst;
+ int no_dec = 0;
+ unsigned long intval = 0, decval = 0;
+ char intarr[3], decarr[3];
+
+ /* Assign the integer part to intarr[]
+ * If there is no decimal point i.e.
+ * if the ratio is an integral value
+ * simply create the intarr.
+ */
+ i = 0;
+ while (strptr[i] != '.') {
+ if (strptr[i] == 0) {
+ no_dec = 1;
+ break;
+ }
+ intarr[i] = strptr[i];
+ i++;
+ }
+
+ intarr[i] = '\0';
+
+ if (no_dec) {
+ /* Currently needed only for single digit corepll ratios */
+ mulconst = 10;
+ decval = 0;
+ } else {
+ j = 0;
+ i++; /* Skipping the decimal point */
+ while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
+ decarr[j] = strptr[i];
+ i++;
+ j++;
+ }
+
+ decarr[j] = '\0';
+
+ mulconst = 1;
+ for (i = 0; i < j; i++)
+ mulconst *= 10;
+ decval = simple_strtoul(decarr, NULL, 10);
+ }
+
+ intval = simple_strtoul(intarr, NULL, 10);
+ intval = intval * mulconst;
+
+ return intval + decval;
+}
+
+static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int i;
+ char *p_cf = NULL;
+ char *p_cf_sysclk = NULL;
+ char *p_cf_corepll = NULL;
+ char *p_cf_mpxpll = NULL;
+ char *p_altbank = NULL;
+ char *p_wd = NULL;
+ int unknown_param = 0;
+
+ /*
+ * No args is a simple reset request.
+ */
+ if (argc <= 1) {
+ pixis_reset();
+ /* not reached */
+ }
+
+ for (i = 1; i < argc; i++) {
+ if (strcmp(argv[i], "cf") == 0) {
+ p_cf = argv[i];
+ if (i + 3 >= argc) {
+ break;
+ }
+ p_cf_sysclk = argv[i+1];
+ p_cf_corepll = argv[i+2];
+ p_cf_mpxpll = argv[i+3];
+ i += 3;
+ continue;
+ }
+
+ if (strcmp(argv[i], "altbank") == 0) {
+ p_altbank = argv[i];
+ continue;
+ }
+
+ if (strcmp(argv[i], "wd") == 0) {
+ p_wd = argv[i];
+ continue;
+ }
+
+ unknown_param = 1;
+ }
+
+ /*
+ * Check that cf has all required parms
+ */
+ if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
+ || unknown_param) {
+#ifdef CONFIG_SYS_LONGHELP
+ puts(cmdtp->help);
+ putc('\n');
+#endif
+ return 1;
+ }
+
+ /*
+ * PIXIS seems to be sensitive to the ordering of
+ * the registers that are touched.
+ */
+ read_from_px_regs(0);
+
+ if (p_altbank)
+ read_from_px_regs_altbank(0);
+
+ clear_altbank();
+
+ /*
+ * Clock configuration specified.
+ */
+ if (p_cf) {
+ unsigned long sysclk;
+ unsigned long corepll;
+ unsigned long mpxpll;
+
+ sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
+ corepll = strfractoint(p_cf_corepll);
+ mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
+
+ if (!(set_px_sysclk(sysclk)
+ && set_px_corepll(corepll)
+ && set_px_mpxpll(mpxpll))) {
+#ifdef CONFIG_SYS_LONGHELP
+ puts(cmdtp->help);
+ putc('\n');
+#endif
+ return 1;
+ }
+ read_from_px_regs(1);
+ }
+
+ /*
+ * Altbank specified
+ *
+ * NOTE CHANGE IN BEHAVIOR: previous code would default
+ * to enabling watchdog if altbank is specified.
+ * Now the watchdog must be enabled explicitly using 'wd'.
+ */
+ if (p_altbank) {
+ set_altbank();
+ read_from_px_regs_altbank(1);
+ }
+
+ /*
+ * Reset with watchdog specified.
+ */
+ if (p_wd)
+ set_px_go_with_watchdog();
+ else
+ set_px_go();
+
+ /*
+ * Shouldn't be reached.
+ */
+ return 0;
+}
+
+
+U_BOOT_CMD(
+ pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
+ "Reset the board using the FPGA sequencer",
+ " pixis_reset\n"
+ " pixis_reset [altbank]\n"
+ " pixis_reset altbank wd\n"
+ " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
+ " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
+);
diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h
new file mode 100644
index 0000000..9328404
--- /dev/null
+++ b/board/freescale/common/pixis.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __PIXIS_H_
+#define __PIXIS_H_ 1
+
+/* PIXIS register set. */
+#if defined(CONFIG_MPC8536DS)
+typedef struct pixis {
+ u8 id;
+ u8 ver;
+ u8 pver;
+ u8 csr;
+ u8 rst;
+ u8 rst2;
+ u8 aux1;
+ u8 spd;
+ u8 aux2;
+ u8 csr2;
+ u8 watch;
+ u8 led;
+ u8 pwr;
+ u8 res[3];
+ u8 vctl;
+ u8 vstat;
+ u8 vcfgen0;
+ u8 vcfgen1;
+ u8 vcore0;
+ u8 res1;
+ u8 vboot;
+ u8 vspeed[3];
+ u8 sclk[3];
+ u8 dclk[3];
+ u8 i2cdacr;
+ u8 vcoreacc[4];
+ u8 vcorecnt[3];
+ u8 vcoremax[2];
+ u8 vplatacc[4];
+ u8 vplatcnt[3];
+ u8 vplatmax[2];
+ u8 vtempacc[4];
+ u8 vtempcnt[3];
+ u8 vtempmax[2];
+ u8 res2[4];
+} __attribute__ ((packed)) pixis_t;
+
+#elif defined(CONFIG_MPC8544DS)
+typedef struct pixis {
+ u8 id;
+ u8 ver;
+ u8 pver;
+ u8 csr;
+ u8 rst;
+ u8 pwr;
+ u8 aux1;
+ u8 spd;
+ u8 res[8];
+ u8 vctl;
+ u8 vstat;
+ u8 vcfgen0;
+ u8 vcfgen1;
+ u8 vcore0;
+ u8 res1;
+ u8 vboot;
+ u8 vspeed[2];
+ u8 vclkh;
+ u8 vclkl;
+ u8 watch;
+ u8 led;
+ u8 vspeed2;
+ u8 res2[34];
+} __attribute__ ((packed)) pixis_t;
+
+#elif defined(CONFIG_MPC8572DS)
+typedef struct pixis {
+ u8 id;
+ u8 ver;
+ u8 pver;
+ u8 csr;
+ u8 rst;
+ u8 pwr1;
+ u8 aux1;
+ u8 spd;
+ u8 aux2;
+ u8 res[7];
+ u8 vctl;
+ u8 vstat;
+ u8 vcfgen0;
+ u8 vcfgen1;
+ u8 vcore0;
+ u8 res1;
+ u8 vboot;
+ u8 vspeed[3];
+ u8 res2[2];
+ u8 sclk[3];
+ u8 dclk[3];
+ u8 res3[2];
+ u8 watch;
+ u8 led;
+ u8 res4[25];
+} __attribute__ ((packed)) pixis_t;
+
+#elif defined(CONFIG_MPC8610HPCD)
+typedef struct pixis {
+ u8 id;
+ u8 ver; /* also called arch */
+ u8 pver;
+ u8 csr;
+ u8 rst;
+ u8 pwr;
+ u8 aux;
+ u8 spd;
+ u8 brdcfg0;
+ u8 brdcfg1;
+ u8 res[4];
+ u8 led;
+ u8 serno;
+ u8 vctl;
+ u8 vstat;
+ u8 vcfgen0;
+ u8 vcfgen1;
+ u8 vcore0;
+ u8 res1;
+ u8 vboot;
+ u8 vspeed[2];
+ u8 res2;
+ u8 sclk[3];
+ u8 res3;
+ u8 watch;
+ u8 res4[33];
+} __attribute__ ((packed)) pixis_t;
+
+#elif defined(CONFIG_MPC8641HPCN)
+typedef struct pixis {
+ u8 id;
+ u8 ver;
+ u8 pver;
+ u8 csr;
+ u8 rst;
+ u8 pwr;
+ u8 aux;
+ u8 spd;
+ u8 res[8];
+ u8 vctl;
+ u8 vstat;
+ u8 vcfgen0;
+ u8 vcfgen1;
+ u8 vcore0;
+ u8 res1;
+ u8 vboot;
+ u8 vspeed[2];
+ u8 vclkh;
+ u8 vclkl;
+ u8 watch;
+ u8 res3[36];
+} __attribute__ ((packed)) pixis_t;
+#else
+#error Need to define pixis_t for this board
+#endif
+
+/* Pointer to the PIXIS register set */
+#define pixis ((pixis_t *)PIXIS_BASE)
+
+#endif /* __PIXIS_H_ */
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
new file mode 100644
index 0000000..5f7a67d
--- /dev/null
+++ b/board/freescale/common/pq-mds-pib.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Tony Li <tony.li@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#include "pq-mds-pib.h"
+
+int pib_init(void)
+{
+ u8 val8;
+ u8 orig_i2c_bus;
+
+ /* Switch temporarily to I2C bus #2 */
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ val8 = 0;
+#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE)
+ /* Assign PIB PMC slot to desired PCI bus */
+ i2c_write(0x23, 0x6, 1, &val8, 1);
+ i2c_write(0x23, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x23, 0x2, 1, &val8, 1);
+ i2c_write(0x23, 0x3, 1, &val8, 1);
+
+ val8 = 0;
+ i2c_write(0x26, 0x6, 1, &val8, 1);
+ val8 = 0x34;
+ i2c_write(0x26, 0x7, 1, &val8, 1);
+#if defined(CONFIG_MPC832XEMDS)
+ val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
+#else
+ val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */
+#endif
+ i2c_write(0x26, 0x2, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x26, 0x3, 1, &val8, 1);
+
+ val8 = 0;
+ i2c_write(0x27, 0x6, 1, &val8, 1);
+ i2c_write(0x27, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x27, 0x2, 1, &val8, 1);
+ val8 = 0xef;
+ i2c_write(0x27, 0x3, 1, &val8, 1);
+
+ eieio();
+
+#if defined(CONFIG_MPC832XEMDS)
+ printf("PCI 32bit bus on PMC2 &PMC3\n");
+#else
+ printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
+#endif
+#endif
+
+#if defined(CONFIG_PQ_MDS_PIB_ATM)
+#if defined(CONFIG_MPC8360EMDS) || defined(CONFIG_MPC8569MDS)
+ val8 = 0;
+ i2c_write(0x20, 0x6, 1, &val8, 1);
+ i2c_write(0x20, 0x7, 1, &val8, 1);
+
+ val8 = 0xdf;
+ i2c_write(0x20, 0x2, 1, &val8, 1);
+ val8 = 0xf7;
+ i2c_write(0x20, 0x3, 1, &val8, 1);
+
+ eieio();
+
+ printf("QOC3 ATM card on PMC0\n");
+#elif defined(CONFIG_MPC832XEMDS)
+ val8 = 0;
+ i2c_write(0x26, 0x7, 1, &val8, 1);
+ val8 = 0xf7;
+ i2c_write(0x26, 0x3, 1, &val8, 1);
+
+ val8 = 0;
+ i2c_write(0x21, 0x6, 1, &val8, 1);
+ i2c_write(0x21, 0x7, 1, &val8, 1);
+
+ val8 = 0xdf;
+ i2c_write(0x21, 0x2, 1, &val8, 1);
+ val8 = 0xef;
+ i2c_write(0x21, 0x3, 1, &val8, 1);
+
+ eieio();
+
+ printf("QOC3 ATM card on PMC1\n");
+#endif
+#endif
+ /* Reset to original I2C bus */
+ i2c_set_bus_num(orig_i2c_bus);
+ return 0;
+}
diff --git a/board/freescale/common/pq-mds-pib.h b/board/freescale/common/pq-mds-pib.h
new file mode 100644
index 0000000..67066fd
--- /dev/null
+++ b/board/freescale/common/pq-mds-pib.h
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+extern int pib_init(void);
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
new file mode 100644
index 0000000..a49e300
--- /dev/null
+++ b/board/freescale/common/qixis.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright 2011 Freescale Semiconductor
+ * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the QIXIS of some Freescale reference boards.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <linux/time.h>
+#include <i2c.h>
+#include "qixis.h"
+
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+u8 qixis_read_i2c(unsigned int reg)
+{
+ return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
+}
+
+void qixis_write_i2c(unsigned int reg, u8 value)
+{
+ u8 val = value;
+ i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
+}
+#endif
+
+u8 qixis_read(unsigned int reg)
+{
+ void *p = (void *)QIXIS_BASE;
+
+ return in_8(p + reg);
+}
+
+void qixis_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)QIXIS_BASE;
+
+ out_8(p + reg, value);
+}
+
+u16 qixis_read_minor(void)
+{
+ u16 minor;
+
+ /* this data is in little endian */
+ QIXIS_WRITE(tagdata, 5);
+ minor = QIXIS_READ(tagdata);
+ QIXIS_WRITE(tagdata, 6);
+ minor += QIXIS_READ(tagdata) << 8;
+
+ return minor;
+}
+
+char *qixis_read_time(char *result)
+{
+ time_t time = 0;
+ int i;
+
+ /* timestamp is in 32-bit big endian */
+ for (i = 8; i <= 11; i++) {
+ QIXIS_WRITE(tagdata, i);
+ time = (time << 8) + QIXIS_READ(tagdata);
+ }
+
+ return ctime_r(&time, result);
+}
+
+char *qixis_read_tag(char *buf)
+{
+ int i;
+ char tag, *ptr = buf;
+
+ for (i = 16; i <= 63; i++) {
+ QIXIS_WRITE(tagdata, i);
+ tag = QIXIS_READ(tagdata);
+ *(ptr++) = tag;
+ if (!tag)
+ break;
+ }
+ if (i > 63)
+ *ptr = '\0';
+
+ return buf;
+}
+
+/*
+ * return the string of binary of u8 in the format of
+ * 1010 10_0. The masked bit is filled as underscore.
+ */
+const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
+{
+ char *ptr;
+ int i;
+
+ ptr = buf;
+ for (i = 0x80; i > 0x08 ; i >>= 1, ptr++)
+ *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
+ *(ptr++) = ' ';
+ for (i = 0x08; i > 0 ; i >>= 1, ptr++)
+ *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
+
+ *ptr = '\0';
+
+ return buf;
+}
+
+#ifdef QIXIS_RST_FORCE_MEM
+void board_assert_mem_reset(void)
+{
+ u8 rst;
+
+ rst = QIXIS_READ(rst_frc[0]);
+ if (!(rst & QIXIS_RST_FORCE_MEM))
+ QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM);
+}
+
+void board_deassert_mem_reset(void)
+{
+ u8 rst;
+
+ rst = QIXIS_READ(rst_frc[0]);
+ if (rst & QIXIS_RST_FORCE_MEM)
+ QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM);
+}
+#endif
+
+void qixis_reset(void)
+{
+ QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
+}
+
+void qixis_bank_reset(void)
+{
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
+}
+
+/* Set the boot bank to the power-on default bank */
+void clear_altbank(void)
+{
+ u8 reg;
+
+ reg = QIXIS_READ(brdcfg[0]);
+ reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK;
+ QIXIS_WRITE(brdcfg[0], reg);
+}
+
+/* Set the boot bank to the alternate bank */
+void set_altbank(void)
+{
+ u8 reg;
+
+ reg = QIXIS_READ(brdcfg[0]);
+ reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK;
+ QIXIS_WRITE(brdcfg[0], reg);
+}
+
+static void qixis_dump_regs(void)
+{
+ int i;
+
+ printf("id = %02x\n", QIXIS_READ(id));
+ printf("arch = %02x\n", QIXIS_READ(arch));
+ printf("scver = %02x\n", QIXIS_READ(scver));
+ printf("model = %02x\n", QIXIS_READ(model));
+ printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl));
+ printf("aux = %02x\n", QIXIS_READ(aux));
+ for (i = 0; i < 16; i++)
+ printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
+ for (i = 0; i < 16; i++)
+ printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
+ printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]),
+ QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
+ printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]),
+ QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
+ printf("aux = %02x\n", QIXIS_READ(aux));
+ printf("watch = %02x\n", QIXIS_READ(watch));
+ printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys));
+ printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
+ printf("present = %02x\n", QIXIS_READ(present));
+ printf("present2 = %02x\n", QIXIS_READ(present2));
+ printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
+ printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
+ printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
+ printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
+}
+
+static void __qixis_dump_switch(void)
+{
+ puts("Reverse engineering switch is not implemented for this board\n");
+}
+
+void qixis_dump_switch(void)
+ __attribute__((weak, alias("__qixis_dump_switch")));
+
+int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i;
+
+ if (argc <= 1) {
+ clear_altbank();
+ qixis_reset();
+ } else if (strcmp(argv[1], "altbank") == 0) {
+ set_altbank();
+ qixis_bank_reset();
+ } else if (strcmp(argv[1], "watchdog") == 0) {
+ static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
+ "1min", "2min", "4min", "8min"};
+ u8 rcfg = QIXIS_READ(rcfg_ctl);
+
+ if (argv[2] == NULL) {
+ printf("qixis watchdog <watchdog_period>\n");
+ return 0;
+ }
+ for (i = 0; i < ARRAY_SIZE(period); i++) {
+ if (strcmp(argv[2], period[i]) == 0) {
+ /* disable watchdog */
+ QIXIS_WRITE(rcfg_ctl,
+ rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
+ QIXIS_WRITE(watch, ((i<<2) - 1));
+ QIXIS_WRITE(rcfg_ctl, rcfg);
+ return 0;
+ }
+ }
+ } else if (strcmp(argv[1], "dump") == 0) {
+ qixis_dump_regs();
+ return 0;
+ } else if (strcmp(argv[1], "switch") == 0) {
+ qixis_dump_switch();
+ return 0;
+ } else {
+ printf("Invalid option: %s\n", argv[1]);
+ return 1;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
+ "Reset the board using the FPGA sequencer",
+ "- hard reset to default bank\n"
+ "qixis_reset altbank - reset to alternate bank\n"
+ "qixis watchdog <watchdog_period> - set the watchdog period\n"
+ " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
+ "qixis_reset dump - display the QIXIS registers\n"
+ "qixis_reset switch - display switch\n"
+ );
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
new file mode 100644
index 0000000..52d2021
--- /dev/null
+++ b/board/freescale/common/qixis.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2011 Freescale Semiconductor
+ * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the QIXIS of some Freescale reference boards.
+ */
+
+#ifndef __QIXIS_H_
+#define __QIXIS_H_
+
+struct qixis {
+ u8 id; /* ID value uniquely identifying each QDS board type */
+ u8 arch; /* Board version information */
+ u8 scver; /* QIXIS Version Register */
+ u8 model; /* Information of software programming model version */
+ u8 tagdata;
+ u8 ctl_sys;
+ u8 aux; /* Auxiliary Register,0x06 */
+ u8 clk_spd;
+ u8 stat_dut;
+ u8 stat_sys;
+ u8 stat_alrm;
+ u8 present;
+ u8 present2; /* Presence Status Register 2,0x0c */
+ u8 rcw_ctl;
+ u8 ctl_led;
+ u8 i2cblk;
+ u8 rcfg_ctl; /* Reconfig Control Register,0x10 */
+ u8 rcfg_st;
+ u8 dcm_ad;
+ u8 dcm_da;
+ u8 dcmd;
+ u8 dmsg;
+ u8 gdc;
+ u8 gdd; /* DCM Debug Data Register,0x17 */
+ u8 dmack;
+ u8 res1[6];
+ u8 watch; /* Watchdog Register,0x1F */
+ u8 pwr_ctl[2]; /* Power Control Register,0x20 */
+ u8 res2[2];
+ u8 pwr_stat[4]; /* Power Status Register,0x24 */
+ u8 res3[8];
+ u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */
+ u8 res4[2];
+ u8 sclk[3]; /* Clock Configuration Registers,0x34 */
+ u8 res5;
+ u8 dclk[3];
+ u8 res6;
+ u8 clk_dspd[3];
+ u8 res7;
+ u8 rst_ctl; /* Reset Control Register,0x40 */
+ u8 rst_stat; /* Reset Status Register */
+ u8 rst_rsn; /* Reset Reason Register */
+ u8 rst_frc[2]; /* Reset Force Registers,0x43 */
+ u8 res8[11];
+ u8 brdcfg[16]; /* Board Configuration Register,0x50 */
+ u8 dutcfg[16];
+ u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */
+ u8 rcw_data;
+ u8 res9[5];
+ u8 post_ctl;
+ u8 post_stat;
+ u8 post_dat[2];
+ u8 pi_d[4];
+ u8 gpio_io[4];
+ u8 gpio_dir[4];
+ u8 res10[20];
+ u8 rjtag_ctl;
+ u8 rjtag_dat;
+ u8 res11[2];
+ u8 trig_src[4];
+ u8 trig_dst[4];
+ u8 trig_stat;
+ u8 res12[3];
+ u8 trig_ctr[4];
+ u8 res13[16];
+ u8 clk_freq[6]; /* Clock Measurement Registers */
+ u8 res_c6[8];
+ u8 clk_base[2]; /* Clock Frequency Base Reg */
+ u8 res_d0[8];
+ u8 cms[2]; /* Core Management Space Address Register, 0xD8 */
+ u8 res_c0[6];
+ u8 aux2[4]; /* Auxiliary Registers,0xE0 */
+ u8 res14[10];
+ u8 aux_ad;
+ u8 aux_da;
+ u8 res15[16];
+};
+
+u8 qixis_read(unsigned int reg);
+void qixis_write(unsigned int reg, u8 value);
+u16 qixis_read_minor(void);
+char *qixis_read_time(char *result);
+char *qixis_read_tag(char *buf);
+const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+u8 qixis_read_i2c(unsigned int reg);
+void qixis_write_i2c(unsigned int reg, u8 value);
+#endif
+
+#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR)
+#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
+#define QIXIS_WRITE(reg, value) \
+ qixis_write_i2c(offsetof(struct qixis, reg), value)
+#else
+#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
+#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
+#endif
+
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
+#define QIXIS_WRITE_I2C(reg, value) \
+ qixis_write_i2c(offsetof(struct qixis, reg), value)
+#endif
+
+#endif
diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c
new file mode 100644
index 0000000..022f38b
--- /dev/null
+++ b/board/freescale/common/sdhc_boot.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <malloc.h>
+
+/*
+ * The environment variables are written to just after the u-boot image
+ * on SDCard, so we must read the MBR to get the start address and code
+ * length of the u-boot image, then calculate the address of the env.
+ */
+#define ESDHC_BOOT_IMAGE_SIZE 0x48
+#define ESDHC_BOOT_IMAGE_ADDR 0x50
+
+#define ESDHC_DEFAULT_ENVADDR 0x400
+
+int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
+{
+ u8 *tmp_buf;
+ u32 blklen, code_offset, code_len, n;
+
+ blklen = mmc->read_bl_len;
+ tmp_buf = malloc(blklen);
+ if (!tmp_buf)
+ return 1;
+
+ /* read out the first block, get the config data information */
+ n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf);
+ if (!n) {
+ free(tmp_buf);
+ return 1;
+ }
+
+ /* Get the Source Address, from offset 0x50 */
+ code_offset = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_ADDR);
+
+ /* Get the code size from offset 0x48 */
+ code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
+
+#ifdef CONFIG_ESDHC_HC_BLK_ADDR
+ /*
+ * On soc BSC9131, BSC9132:
+ * In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
+ * code length of these soc specify the memory address in block address
+ * format. Block length is fixed to 512 bytes as per the SD High
+ * Capacity specification.
+ */
+ u64 tmp;
+
+ if (mmc->high_capacity) {
+ tmp = (u64)code_offset * blklen;
+ tmp += code_len * blklen;
+ } else
+ tmp = code_offset + code_len;
+
+ if ((tmp + CONFIG_ENV_SIZE > mmc->capacity) ||
+ (tmp > 0xFFFFFFFFU))
+ *env_addr = ESDHC_DEFAULT_ENVADDR;
+ else
+ *env_addr = tmp;
+
+ free(tmp_buf);
+
+ return 0;
+#endif
+
+ *env_addr = code_offset + code_len;
+
+ free(tmp_buf);
+
+ return 0;
+}
diff --git a/board/freescale/common/sgmii_riser.c b/board/freescale/common/sgmii_riser.c
new file mode 100644
index 0000000..5c3c593
--- /dev/null
+++ b/board/freescale/common/sgmii_riser.c
@@ -0,0 +1,129 @@
+/*
+ * Freescale SGMII Riser Card
+ *
+ * This driver supports the SGMII Riser card found on the
+ * "DS" style of development board from Freescale.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <net.h>
+#include <libfdt.h>
+#include <tsec.h>
+#include <fdt_support.h>
+
+void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ if (tsec_info[i].flags & TSEC_SGMII)
+ tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET;
+}
+
+void fsl_sgmii_riser_fdt_fixup(void *fdt)
+{
+ struct eth_device *dev;
+ int node;
+ int mdio_node;
+ int i = -1;
+ int etsec_num = 0;
+
+ node = fdt_path_offset(fdt, "/aliases");
+ if (node < 0)
+ return;
+
+ while ((dev = eth_get_dev_by_index(++i)) != NULL) {
+ struct tsec_private *priv;
+ int phy_node;
+ int enet_node;
+ uint32_t ph;
+ char sgmii_phy[16];
+ char enet[16];
+ const u32 *phyh;
+ const char *model;
+ const char *path;
+
+ if (!strstr(dev->name, "eTSEC"))
+ continue;
+
+ priv = dev->priv;
+ if (!(priv->flags & TSEC_SGMII)) {
+ etsec_num++;
+ continue;
+ }
+
+ mdio_node = fdt_node_offset_by_compatible(fdt, -1,
+ "fsl,gianfar-mdio");
+ if (mdio_node < 0)
+ return;
+
+ sprintf(sgmii_phy, "sgmii-phy@%d", etsec_num);
+ phy_node = fdt_subnode_offset(fdt, mdio_node, sgmii_phy);
+ if (phy_node > 0) {
+ fdt_increase_size(fdt, 32);
+ ph = fdt_create_phandle(fdt, phy_node);
+ if (!ph)
+ continue;
+ }
+
+ sprintf(enet, "ethernet%d", etsec_num++);
+ path = fdt_getprop(fdt, node, enet, NULL);
+ if (!path) {
+ debug("No alias for %s\n", enet);
+ continue;
+ }
+
+ enet_node = fdt_path_offset(fdt, path);
+ if (enet_node < 0)
+ continue;
+
+ model = fdt_getprop(fdt, enet_node, "model", NULL);
+
+ /*
+ * We only want to do this to eTSECs. On some platforms
+ * there are more than one type of gianfar-style ethernet
+ * controller, and as we are creating an implicit connection
+ * between ethernet nodes and eTSEC devices, it is best to
+ * make the connection use as much explicit information
+ * as exists.
+ */
+ if (!strstr(model, "TSEC"))
+ continue;
+
+ if (phy_node < 0) {
+ /*
+ * This part is only for old device tree without
+ * sgmii_phy nodes. It's kept just for compatible
+ * reason. Soon to be deprecated if all device tree
+ * get updated.
+ */
+ phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL);
+ if (!phyh)
+ continue;
+
+ phy_node = fdt_node_offset_by_phandle(fdt,
+ fdt32_to_cpu(*phyh));
+
+ priv = dev->priv;
+
+ if (priv->flags & TSEC_SGMII)
+ fdt_setprop_cell(fdt, phy_node, "reg",
+ priv->phyaddr);
+ } else {
+ fdt_setprop(fdt, enet_node, "phy-handle", &ph,
+ sizeof(ph));
+ fdt_setprop_string(fdt, enet_node,
+ "phy-connection-type",
+ phy_string_for_interface(
+ PHY_INTERFACE_MODE_SGMII));
+ }
+ }
+}
diff --git a/board/freescale/common/sgmii_riser.h b/board/freescale/common/sgmii_riser.h
new file mode 100644
index 0000000..e1fcc85
--- /dev/null
+++ b/board/freescale/common/sgmii_riser.h
@@ -0,0 +1,16 @@
+/*
+ * Freescale SGMII Riser Card
+ *
+ * This driver supports the SGMII Riser card found on the
+ * "DS" style of development board from Freescale.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ */
+
+void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num);
+void fsl_sgmii_riser_fdt_fixup(void *fdt);
diff --git a/board/freescale/common/sleep.h b/board/freescale/common/sleep.h
new file mode 100644
index 0000000..c26c542
--- /dev/null
+++ b/board/freescale/common/sleep.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SLEEP_H
+#define __SLEEP_H
+
+#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
+#define DDR_BUFF_LEN 128
+
+/* determine if it is a wakeup from deep sleep */
+bool is_warm_boot(void);
+
+/* disable console output */
+void fsl_dp_disable_console(void);
+
+/* clean up everything and jump to kernel */
+int fsl_dp_resume(void);
+#endif
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
new file mode 100644
index 0000000..5cb7570
--- /dev/null
+++ b/board/freescale/common/sys_eeprom.c
@@ -0,0 +1,543 @@
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun@freescale.com)
+ * Haiying Wang (haiying.wang@freescale.com)
+ * Timur Tabi (timur@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
+#include "../common/eeprom.h"
+#define MAX_NUM_PORTS 8
+#endif
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+/* some boards with non-256-bytes EEPROM have special define */
+/* for MAX_NUM_PORTS in board-specific file */
+#ifndef MAX_NUM_PORTS
+#define MAX_NUM_PORTS 16
+#endif
+#define NXID_VERSION 1
+#endif
+
+/**
+ * static eeprom: EEPROM layout for CCID or NXID formats
+ *
+ * See application note AN3638 for details.
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
+ u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'CCID' */
+ u8 major; /* 0x04 Board revision, major */
+ u8 minor; /* 0x05 Board revision, minor */
+ u8 sn[10]; /* 0x06 - 0x0F Serial Number*/
+ u8 errata[2]; /* 0x10 - 0x11 Errata Level */
+ u8 date[6]; /* 0x12 - 0x17 Build Date */
+ u8 res_0[40]; /* 0x18 - 0x3f Reserved */
+ u8 mac_count; /* 0x40 Number of MAC addresses */
+ u8 mac_flag; /* 0x41 MAC table flags */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
+ u32 crc; /* 0x72 CRC32 checksum */
+#endif
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+ u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */
+ u8 sn[12]; /* 0x04 - 0x0F Serial Number */
+ u8 errata[5]; /* 0x10 - 0x14 Errata Level */
+ u8 date[6]; /* 0x15 - 0x1a Build Date */
+ u8 res_0; /* 0x1b Reserved */
+ u32 version; /* 0x1c - 0x1f NXID Version */
+ u8 tempcal[8]; /* 0x20 - 0x27 Temperature Calibration Factors */
+ u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */
+ u8 tempcalflags; /* 0x2a Temperature Calibration Flags */
+ u8 res_1[21]; /* 0x2b - 0x3f Reserved */
+ u8 mac_count; /* 0x40 Number of MAC addresses */
+ u8 mac_flag; /* 0x41 MAC table flags */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0xa1 MAC addresses */
+ u8 res_2[90]; /* 0xa2 - 0xfb Reserved */
+ u32 crc; /* 0xfc - 0xff CRC32 checksum */
+#endif
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read = 0;
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+/* Is this a valid NXID EEPROM? */
+#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \
+ (e.id[2] == 'I') || (e.id[3] == 'D'))
+#endif
+
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
+/* Is this a valid CCID EEPROM? */
+#define is_valid ((e.id[0] == 'C') || (e.id[1] == 'C') || \
+ (e.id[2] == 'I') || (e.id[3] == 'D'))
+#endif
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+ int i;
+ unsigned int crc;
+
+ /* EEPROM tag ID, either CCID or NXID */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+ printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
+ e.version);
+#else
+ printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
+#endif
+
+ /* Serial number */
+ printf("SN: %s\n", e.sn);
+
+ /* Errata level. */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+ printf("Errata: %s\n", e.errata);
+#else
+ printf("Errata: %c%c\n",
+ e.errata[0] ? e.errata[0] : '.',
+ e.errata[1] ? e.errata[1] : '.');
+#endif
+
+ /* Build date, BCD date values, as YYMMDDhhmmss */
+ printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+ e.date[0], e.date[1], e.date[2],
+ e.date[3] & 0x7F, e.date[4], e.date[5],
+ e.date[3] & 0x80 ? "PM" : "");
+
+ /* Show MAC addresses */
+ for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
+
+ u8 *p = e.mac[i];
+
+ printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i,
+ p[0], p[1], p[2], p[3], p[4], p[5]);
+ }
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+ if (crc == be32_to_cpu(e.crc))
+ printf("CRC: %08x\n", be32_to_cpu(e.crc));
+ else
+ printf("CRC: %08x (should be %08x)\n",
+ be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+ printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+ for (i = 0; i < sizeof(e); i++) {
+ if ((i % 16) == 0)
+ printf("%02X: ", i);
+ printf("%02X ", ((u8 *)&e)[i]);
+ if (((i % 16) == 15) || (i == sizeof(e) - 1))
+ printf("\n");
+ }
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
+{
+ int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ if (has_been_read)
+ return 0;
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ (void *)&e, sizeof(e));
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+#ifdef DEBUG
+ show_eeprom();
+#endif
+
+ has_been_read = (ret == 0) ? 1 : 0;
+
+ return ret;
+}
+
+/**
+ * update_crc - update the CRC
+ *
+ * This function should be called after each update to the EEPROM structure,
+ * to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+ u32 crc;
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+ e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+ int ret = 0;
+ int i;
+ void *p;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ /* Set the reserved values to 0xFF */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+ e.res_0 = 0xFF;
+ memset(e.res_1, 0xFF, sizeof(e.res_1));
+#else
+ memset(e.res_0, 0xFF, sizeof(e.res_0));
+#endif
+ update_crc();
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ /*
+ * The AT24C02 datasheet says that data can only be written in page
+ * mode, which means 8 bytes at a time, and it takes up to 5ms to
+ * complete a given write.
+ */
+ for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
+ ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ p, min((int)(sizeof(e) - i), 8));
+ if (ret)
+ break;
+ udelay(5000); /* 5ms write cycle timing */
+ }
+
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct eeprom e2;
+
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2));
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+ if (ret) {
+ printf("Programming failed.\n");
+ has_been_read = 0;
+ return -1;
+ }
+
+ printf("Programming passed.\n");
+ return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+ if ((p >= '0') && (p <= '9'))
+ return p - '0';
+
+ if ((p >= 'A') && (p <= 'F'))
+ return (p - 'A') + 10;
+
+ if ((p >= 'a') && (p <= 'f'))
+ return (p - 'a') + 10;
+
+ return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+ unsigned int i;
+
+ if (strlen(string) != 12) {
+ printf("Usage: mac date YYMMDDhhmmss\n");
+ return;
+ }
+
+ for (i = 0; i < 6; i++)
+ e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+ update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in one of the MAC address fields of the EEPROM local copy.
+ */
+static void set_mac_address(unsigned int index, const char *string)
+{
+ char *p = (char *) string;
+ unsigned int i;
+
+ if ((index >= MAX_NUM_PORTS) || !string) {
+ printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
+ return;
+ }
+
+ for (i = 0; *p && (i < 6); i++) {
+ e.mac[index][i] = simple_strtoul(p, &p, 16);
+ if (*p == ':')
+ p++;
+ }
+
+ update_crc();
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char cmd;
+
+ if (argc == 1) {
+ show_eeprom();
+ return 0;
+ }
+
+ cmd = argv[1][0];
+
+ if (cmd == 'r') {
+ read_eeprom();
+ return 0;
+ }
+
+ if (cmd == 'i') {
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+ memcpy(e.id, "NXID", sizeof(e.id));
+ e.version = NXID_VERSION;
+#else
+ memcpy(e.id, "CCID", sizeof(e.id));
+#endif
+ update_crc();
+ return 0;
+ }
+
+ if (!is_valid) {
+ printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n");
+ return 0;
+ }
+
+ if (argc == 2) {
+ switch (cmd) {
+ case 's': /* save */
+ prog_eeprom();
+ break;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+ }
+
+ /* We know we have at least one parameter */
+
+ switch (cmd) {
+ case 'n': /* serial number */
+ memset(e.sn, 0, sizeof(e.sn));
+ strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+ update_crc();
+ break;
+ case 'e': /* errata */
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+ memset(e.errata, 0, 5);
+ strncpy((char *)e.errata, argv[2], 4);
+#else
+ e.errata[0] = argv[2][0];
+ e.errata[1] = argv[2][1];
+#endif
+ update_crc();
+ break;
+ case 'd': /* date BCD format YYMMDDhhmmss */
+ set_date(argv[2]);
+ break;
+ case 'p': /* MAC table size */
+ e.mac_count = simple_strtoul(argv[2], NULL, 16);
+ update_crc();
+ break;
+ case '0' ... '9': /* "mac 0" through "mac 22" */
+ set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]);
+ break;
+ case 'h': /* help */
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+/**
+ * mac_read_from_eeprom - read the MAC addresses from EEPROM
+ *
+ * This function reads the MAC addresses from EEPROM and sets the
+ * appropriate environment variables for each one read.
+ *
+ * The environment variables are only set if they haven't been set already.
+ * This ensures that any user-saved variables are never overwritten.
+ *
+ * This function must be called after relocation.
+ *
+ * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0
+ * format. In a v0 EEPROM, there are only eight MAC addresses and the CRC is
+ * located at a different offset.
+ */
+int mac_read_from_eeprom(void)
+{
+ unsigned int i;
+ u32 crc, crc_offset = offsetof(struct eeprom, crc);
+ u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+ puts("EEPROM: ");
+
+ if (read_eeprom()) {
+ printf("Read failed.\n");
+ return 0;
+ }
+
+ if (!is_valid) {
+ printf("Invalid ID (%02x %02x %02x %02x)\n",
+ e.id[0], e.id[1], e.id[2], e.id[3]);
+ return 0;
+ }
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+ /*
+ * If we've read an NXID v0 EEPROM, then we need to set the CRC offset
+ * to where it is in v0.
+ */
+ if (e.version == 0)
+ crc_offset = 0x72;
+#endif
+
+ crc = crc32(0, (void *)&e, crc_offset);
+ crcp = (void *)&e + crc_offset;
+ if (crc != be32_to_cpu(*crcp)) {
+ printf("CRC mismatch (%08x != %08x)\n", crc, be32_to_cpu(e.crc));
+ return 0;
+ }
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+ /*
+ * MAC address #9 in v1 occupies the same position as the CRC in v0.
+ * Erase it so that it's not mistaken for a MAC address. We'll
+ * update the CRC later.
+ */
+ if (e.version == 0)
+ memset(e.mac[8], 0xff, 6);
+#endif
+
+ for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
+ if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
+ memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+ char ethaddr[18];
+ char enetvar[9];
+
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ e.mac[i][0],
+ e.mac[i][1],
+ e.mac[i][2],
+ e.mac[i][3],
+ e.mac[i][4],
+ e.mac[i][5]);
+ sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv(enetvar))
+ setenv(enetvar, ethaddr);
+ }
+ }
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+ printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
+ e.version);
+#else
+ printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
+#endif
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
+ /*
+ * Now we need to upconvert the data into v1 format. We do this last so
+ * that at boot time, U-Boot will still say "NXID v0".
+ */
+ if (e.version == 0) {
+ e.version = NXID_VERSION;
+ update_crc();
+ }
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
+
+/**
+ * get_cpu_board_revision - get the CPU board revision on 85xx boards
+ *
+ * Read the EEPROM to determine the board revision.
+ *
+ * This function is called before relocation, so we need to read a private
+ * copy of the EEPROM into a local variable on the stack.
+ *
+ * Also, we assume that CONFIG_SYS_EEPROM_BUS_NUM == CONFIG_SYS_SPD_BUS_NUM. The global
+ * variable i2c_bus_num must be compile-time initialized to CONFIG_SYS_SPD_BUS_NUM,
+ * so that the SPD code will work. This means that all pre-relocation I2C
+ * operations can only occur on the CONFIG_SYS_SPD_BUS_NUM bus. So if
+ * CONFIG_SYS_EEPROM_BUS_NUM != CONFIG_SYS_SPD_BUS_NUM, then we can't read the EEPROM when
+ * this function is called. Oh well.
+ */
+unsigned int get_cpu_board_revision(void)
+{
+ struct board_eeprom {
+ u32 id; /* 0x00 - 0x03 EEPROM Tag 'CCID' */
+ u8 major; /* 0x04 Board revision, major */
+ u8 minor; /* 0x05 Board revision, minor */
+ } be;
+
+ i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ (void *)&be, sizeof(be));
+
+ if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
+ return MPC85XX_CPU_BOARD_REV(0, 0);
+
+ if ((be.major == 0xff) && (be.minor == 0xff))
+ return MPC85XX_CPU_BOARD_REV(0, 0);
+
+ return MPC85XX_CPU_BOARD_REV(be.major, be.minor);
+}
+#endif
diff --git a/board/freescale/common/via.h b/board/freescale/common/via.h
new file mode 100644
index 0000000..77cfacc
--- /dev/null
+++ b/board/freescale/common/via.h
@@ -0,0 +1,18 @@
+#ifndef _MPC85xx_VIA_H
+void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+#endif /* _MPC85xx_VIA_H */
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
new file mode 100644
index 0000000..6b8af14
--- /dev/null
+++ b/board/freescale/common/vid.c
@@ -0,0 +1,491 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/immap_85xx.h>
+#include "vid.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int __weak i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return 0;
+}
+
+/*
+ * Compensate for a board specific voltage drop between regulator and SoC
+ * return a value in mV
+ */
+int __weak board_vdd_drop_compensation(void)
+{
+ return 0;
+}
+
+/*
+ * Get the i2c address configuration for the IR regulator chip
+ *
+ * There are some variance in the RDB HW regarding the I2C address configuration
+ * for the IR regulator chip, which is likely a problem of external resistor
+ * accuracy. So we just check each address in a hopefully non-intrusive mode
+ * and use the first one that seems to work
+ *
+ * The IR chip can show up under the following addresses:
+ * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
+ * 0x09 (Verified on T1040RDB-PA)
+ * 0x38 (Verified on T2080QDS, T2081QDS)
+ */
+static int find_ir_chip_on_i2c(void)
+{
+ int i2caddress;
+ int ret;
+ u8 byte;
+ int i;
+ const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
+
+ /* Check all the address */
+ for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
+ i2caddress = ir_i2c_addr[i];
+ ret = i2c_read(i2caddress,
+ IR36021_MFR_ID_OFFSET, 1, (void *)&byte,
+ sizeof(byte));
+ if ((ret >= 0) && (byte == IR36021_MFR_ID))
+ return i2caddress;
+ }
+ return -1;
+}
+
+/* Maximum loop count waiting for new voltage to take effect */
+#define MAX_LOOP_WAIT_NEW_VOL 100
+/* Maximum loop count waiting for the voltage to be stable */
+#define MAX_LOOP_WAIT_VOL_STABLE 100
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for WAIT_FOR_ADC before
+ * another reading
+ */
+#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
+
+/* If an INA220 chip is available, we can use it to read back the voltage
+ * as it may have a higher accuracy than the IR chip for the same purpose
+ */
+#ifdef CONFIG_VOL_MONITOR_INA220
+#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
+#define ADC_MIN_ACCURACY 4
+#else
+#define WAIT_FOR_ADC 138 /* wait for 138 microseconds for ADC */
+#define ADC_MIN_ACCURACY 4
+#endif
+
+#ifdef CONFIG_VOL_MONITOR_INA220
+static int read_voltage_from_INA220(int i2caddress)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+ u8 buf[2];
+
+ for (i = 0; i < NUM_READINGS; i++) {
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ I2C_VOL_MONITOR_BUS_V_OFFSET, 1,
+ (void *)&buf, 2);
+ if (ret) {
+ printf("VID: failed to read core voltage\n");
+ return ret;
+ }
+ vol_mon = (buf[0] << 8) | buf[1];
+ if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+ /* LSB = 4mv */
+ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ return voltage_read;
+}
+#endif
+
+/* read voltage from IR */
+#ifdef CONFIG_VOL_MONITOR_IR36021_READ
+static int read_voltage_from_IR(int i2caddress)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+ u8 buf;
+
+ for (i = 0; i < NUM_READINGS; i++) {
+ ret = i2c_read(i2caddress,
+ IR36021_LOOP1_VOUT_OFFSET,
+ 1, (void *)&buf, 1);
+ if (ret) {
+ printf("VID: failed to read vcpu\n");
+ return ret;
+ }
+ vol_mon = buf;
+ if (!vol_mon) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%02x\n", vol_mon);
+ /* Resolution is 1/128V. We scale up here to get 1/128mV
+ * and divide at the end
+ */
+ voltage_read += vol_mon * 1000;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* Scale down to the real mV as IR resolution is 1/128V, rounding up */
+ voltage_read = DIV_ROUND_UP(voltage_read, 128);
+
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ /* Compensate for a board specific voltage drop between regulator and
+ * SoC before converting into an IR VID value
+ */
+ voltage_read -= board_vdd_drop_compensation();
+
+ return voltage_read;
+}
+#endif
+
+static int read_voltage(int i2caddress)
+{
+ int voltage_read;
+#ifdef CONFIG_VOL_MONITOR_INA220
+ voltage_read = read_voltage_from_INA220(i2caddress);
+#elif defined CONFIG_VOL_MONITOR_IR36021_READ
+ voltage_read = read_voltage_from_IR(i2caddress);
+#else
+ return -1;
+#endif
+ return voltage_read;
+}
+
+/*
+ * We need to calculate how long before the voltage stops to drop
+ * or increase. It returns with the loop count. Each loop takes
+ * several readings (WAIT_FOR_ADC)
+ */
+static int wait_for_new_voltage(int vdd, int i2caddress)
+{
+ int timeout, vdd_current;
+
+ vdd_current = read_voltage(i2caddress);
+ /* wait until voltage starts to reach the target. Voltage slew
+ * rates by typical regulators will always lead to stable readings
+ * within each fairly long ADC interval in comparison to the
+ * intended voltage delta change until the target voltage is
+ * reached. The fairly small voltage delta change to any target
+ * VID voltage also means that this function will always complete
+ * within few iterations. If the timeout was ever reached, it would
+ * point to a serious failure in the regulator system.
+ */
+ for (timeout = 0;
+ abs(vdd - vdd_current) > (IR_VDD_STEP_UP + IR_VDD_STEP_DOWN) &&
+ timeout < MAX_LOOP_WAIT_NEW_VOL; timeout++) {
+ vdd_current = read_voltage(i2caddress);
+ }
+ if (timeout >= MAX_LOOP_WAIT_NEW_VOL) {
+ printf("VID: Voltage adjustment timeout\n");
+ return -1;
+ }
+ return timeout;
+}
+
+/*
+ * this function keeps reading the voltage until it is stable or until the
+ * timeout expires
+ */
+static int wait_for_voltage_stable(int i2caddress)
+{
+ int timeout, vdd_current, vdd;
+
+ vdd = read_voltage(i2caddress);
+ udelay(NUM_READINGS * WAIT_FOR_ADC);
+
+ /* wait until voltage is stable */
+ vdd_current = read_voltage(i2caddress);
+ /* The maximum timeout is
+ * MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC
+ */
+ for (timeout = MAX_LOOP_WAIT_VOL_STABLE;
+ abs(vdd - vdd_current) > ADC_MIN_ACCURACY &&
+ timeout > 0; timeout--) {
+ vdd = vdd_current;
+ udelay(NUM_READINGS * WAIT_FOR_ADC);
+ vdd_current = read_voltage(i2caddress);
+ }
+ if (timeout == 0)
+ return -1;
+ return vdd_current;
+}
+
+#ifdef CONFIG_VOL_MONITOR_IR36021_SET
+/* Set the voltage to the IR chip */
+static int set_voltage_to_IR(int i2caddress, int vdd)
+{
+ int wait, vdd_last;
+ int ret;
+ u8 vid;
+
+ /* Compensate for a board specific voltage drop between regulator and
+ * SoC before converting into an IR VID value
+ */
+ vdd += board_vdd_drop_compensation();
+ vid = DIV_ROUND_UP(vdd - 245, 5);
+
+ ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
+ 1, (void *)&vid, sizeof(vid));
+ if (ret) {
+ printf("VID: failed to write VID\n");
+ return -1;
+ }
+ wait = wait_for_new_voltage(vdd, i2caddress);
+ if (wait < 0)
+ return -1;
+ debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
+
+ vdd_last = wait_for_voltage_stable(i2caddress);
+ if (vdd_last < 0)
+ return -1;
+ debug("VID: Current voltage is %d mV\n", vdd_last);
+ return vdd_last;
+}
+#endif
+
+static int set_voltage(int i2caddress, int vdd)
+{
+ int vdd_last = -1;
+
+#ifdef CONFIG_VOL_MONITOR_IR36021_SET
+ vdd_last = set_voltage_to_IR(i2caddress, vdd);
+#else
+ #error Specific voltage monitor must be defined
+#endif
+ return vdd_last;
+}
+
+int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid;
+ int vdd_target, vdd_current, vdd_last;
+ int ret, i2caddress;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.9875V */
+ 9750,
+ 9625,
+ 9500,
+ 9375,
+ 9250,
+ 9125,
+ 9000,
+ 8875,
+ 8750,
+ 8625,
+ 8500,
+ 8375,
+ 8250,
+ 8125,
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ debug("VID: I2C failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+ ret = find_ir_chip_on_i2c();
+ if (ret < 0) {
+ printf("VID: Could not find voltage regulator on I2C.\n");
+ ret = -1;
+ goto exit;
+ } else {
+ i2caddress = ret;
+ debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
+ }
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_be32(&gur->dcfg_fusesr);
+ /*
+ * VID is used according to the table below
+ * ---------------------------------------
+ * | DA_V |
+ * |-------------------------------------|
+ * | 5b00000 | 5b00001-5b11110 | 5b11111 |
+ * ---------------+---------+-----------------+---------|
+ * | D | 5b00000 | NO VID | VID = DA_V | NO VID |
+ * | A |----------+---------+-----------------+---------|
+ * | _ | 5b00001 |VID = | VID = |VID = |
+ * | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT|
+ * | _ | 5b11110 | | | |
+ * | A |----------+---------+-----------------+---------|
+ * | L | 5b11111 | No VID | VID = DA_V | NO VID |
+ * | T | | | | |
+ * ------------------------------------------------------
+ */
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+ if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) {
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_VID_MASK;
+ }
+ vdd_target = vdd[vid];
+
+ /* check override variable for overriding VDD */
+ vdd_string = getenv(CONFIG_VID_FLS_ENV);
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+ if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
+ vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+ debug("VDD override is %lu\n", vdd_override);
+ } else if (vdd_override != 0) {
+ printf("Invalid value.\n");
+ }
+ if (vdd_target == 0) {
+ debug("VID: VID not used\n");
+ ret = 0;
+ goto exit;
+ } else {
+ /* divide and round up by 10 to get a value in mV */
+ vdd_target = DIV_ROUND_UP(vdd_target, 10);
+ debug("VID: vid = %d mV\n", vdd_target);
+ }
+
+ /*
+ * Read voltage monitor to check real voltage.
+ */
+ vdd_last = read_voltage(i2caddress);
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjustment\n");
+ ret = -1;
+ goto exit;
+ }
+ vdd_current = vdd_last;
+ debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+ /*
+ * Adjust voltage to at or one step above target.
+ * As measurements are less precise than setting the values
+ * we may run through dummy steps that cancel each other
+ * when stepping up and then down.
+ */
+ while (vdd_last > 0 &&
+ vdd_last < vdd_target) {
+ vdd_current += IR_VDD_STEP_UP;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+ while (vdd_last > 0 &&
+ vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
+ vdd_current -= IR_VDD_STEP_DOWN;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+
+ if (vdd_last > 0)
+ printf("VID: Core voltage after adjustment is at %d mV\n",
+ vdd_last);
+ else
+ ret = -1;
+exit:
+ if (re_enable)
+ enable_interrupts();
+ return ret;
+}
+
+static int print_vdd(void)
+{
+ int vdd_last, ret, i2caddress;
+
+ ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ debug("VID : I2c failed to switch channel\n");
+ return -1;
+ }
+ ret = find_ir_chip_on_i2c();
+ if (ret < 0) {
+ printf("VID: Could not find voltage regulator on I2C.\n");
+ return -1;
+ } else {
+ i2caddress = ret;
+ debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
+ }
+
+ /*
+ * Read voltage monitor to check real voltage.
+ */
+ vdd_last = read_voltage(i2caddress);
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjustment\n");
+ return -1;
+ }
+ printf("VID: Core voltage is at %d mV\n", vdd_last);
+
+ return 0;
+}
+
+static int do_vdd_override(cmd_tbl_t *cmdtp,
+ int flag, int argc,
+ char * const argv[])
+{
+ ulong override;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (!strict_strtoul(argv[1], 10, &override))
+ adjust_vdd(override); /* the value is checked by callee */
+ else
+ return CMD_RET_USAGE;
+ return 0;
+}
+
+static int do_vdd_read(cmd_tbl_t *cmdtp,
+ int flag, int argc,
+ char * const argv[])
+{
+ if (argc < 1)
+ return CMD_RET_USAGE;
+ print_vdd();
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ vdd_override, 2, 0, do_vdd_override,
+ "override VDD",
+ " - override with the voltage specified in mV, eg. 1050"
+);
+
+U_BOOT_CMD(
+ vdd_read, 1, 0, do_vdd_read,
+ "read VDD",
+ " - Read the voltage specified in mV"
+)
diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h
new file mode 100644
index 0000000..a9c7bb4
--- /dev/null
+++ b/board/freescale/common/vid.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __VID_H_
+#define __VID_H_
+
+#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A
+#define IR36021_LOOP1_VOUT_OFFSET 0x9A
+#define IR36021_MFR_ID_OFFSET 0x92
+#define IR36021_MFR_ID 0x43
+
+/* step the IR regulator in 5mV increments */
+#define IR_VDD_STEP_DOWN 5
+#define IR_VDD_STEP_UP 5
+int adjust_vdd(ulong vdd_override);
+
+#endif /* __VID_H_ */
diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c
new file mode 100644
index 0000000..dd9c37e
--- /dev/null
+++ b/board/freescale/common/vsc3316_3308.c
@@ -0,0 +1,276 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "vsc3316_3308.h"
+
+#define REVISION_ID_REG 0x7E
+#define INTERFACE_MODE_REG 0x79
+#define CURRENT_PAGE_REGISTER 0x7F
+#define CONNECTION_CONFIG_PAGE 0x00
+#define INPUT_STATE_REG 0x13
+#define GLOBAL_INPUT_ISE1 0x51
+#define GLOBAL_INPUT_ISE2 0x52
+#define GLOBAL_INPUT_GAIN 0x53
+#define GLOBAL_INPUT_LOS 0x55
+#define GLOBAL_OUTPUT_PE1 0x56
+#define GLOBAL_OUTPUT_PE2 0x57
+#define GLOBAL_OUTPUT_LEVEL 0x58
+#define GLOBAL_OUTPUT_TERMINATION 0x5A
+#define GLOBAL_CORE_CNTRL 0x5D
+#define OUTPUT_MODE_PAGE 0x23
+#define CORE_CONTROL_PAGE 0x25
+#define CORE_CONFIG_REG 0x75
+
+int vsc_if_enable(unsigned int vsc_addr)
+{
+ u8 data;
+
+ debug("VSC:Configuring VSC at I2C address 0x%2x"
+ " for 2-wire interface\n", vsc_addr);
+
+ /* enable 2-wire Serial InterFace (I2C) */
+ data = 0x02;
+ return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1);
+}
+
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
+ unsigned int num_con)
+{
+ unsigned int i;
+ u8 rev_id = 0;
+ int ret;
+
+ debug("VSC:Initializing VSC3316 at I2C address 0x%2x"
+ " for Tx\n", vsc_addr);
+
+ ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
+ if (ret < 0) {
+ printf("VSC:0x%x could not read REV_ID from device.\n",
+ vsc_addr);
+ return ret;
+ }
+
+ if (rev_id != 0xab) {
+ printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+ vsc_addr);
+ return -ENODEV;
+ }
+
+ ret = vsc_if_enable(vsc_addr);
+ if (ret) {
+ printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+ vsc_addr);
+ return ret;
+ }
+
+ /* config connections - page 0x00 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+ /* Making crosspoint connections, by connecting required
+ * input to output */
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
+
+ /* input state - page 0x13 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+ /* Configuring the required input of the switch */
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][0], 0x80);
+
+ /* Setting Global Input LOS threshold value */
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60);
+
+ /* config output mode - page 0x23 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+ /* Turn ON the Output driver correspond to required output*/
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][1], 0);
+
+ /* configure global core control register, Turn on Global core power */
+ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
+
+ vsc_wp_config(vsc_addr);
+
+ return 0;
+}
+
+#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
+ unsigned int num_con)
+{
+ unsigned int i;
+ u8 rev_id = 0;
+ int ret;
+
+ debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n",
+ vsc_addr);
+
+ ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
+ if (ret < 0) {
+ printf("VSC:0x%x could not read REV_ID from device.\n",
+ vsc_addr);
+ return ret;
+ }
+
+ if (rev_id != 0xab) {
+ printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+ vsc_addr);
+ return -ENODEV;
+ }
+
+ ret = vsc_if_enable(vsc_addr);
+ if (ret) {
+ printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+ vsc_addr);
+ return ret;
+ }
+
+ /* config connections - page 0x00 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+ /* Configure Global Input ISE */
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0);
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0);
+
+ /* Configure Tx/Rx Global Output PE1 */
+ i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE1, 0);
+
+ /* Configure Tx/Rx Global Output PE2 */
+ i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE2, 0);
+
+ /* Configure Tx/Rx Global Input GAIN */
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_GAIN, 0x3F);
+
+ /* Setting Global Input LOS threshold value */
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0xE0);
+
+ /* Setting Global output termination */
+ i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_TERMINATION, 0);
+
+ /* Configure Tx/Rx Global Output level */
+ if (vsc_addr == VSC3308_TX_ADDRESS)
+ i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 4);
+ else
+ i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 2);
+
+ /* Making crosspoint connections, by connecting required
+ * input to output */
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
+
+ /* input state - page 0x13 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+ /* Turning off all the required input of the switch */
+ for (i = 0; i < num_con; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][0], 1);
+
+ /* only turn on specific Tx/Rx requested by the XFI erratum */
+ if (vsc_addr == VSC3308_TX_ADDRESS) {
+ i2c_reg_write(vsc_addr, 2, 0);
+ i2c_reg_write(vsc_addr, 3, 0);
+ } else {
+ i2c_reg_write(vsc_addr, 0, 0);
+ i2c_reg_write(vsc_addr, 1, 0);
+ }
+
+ /* config output mode - page 0x23 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+ /* Turn off the Output driver correspond to required output*/
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][1], 1);
+
+ /* only turn on specific Tx/Rx requested by the XFI erratum */
+ if (vsc_addr == VSC3308_TX_ADDRESS) {
+ i2c_reg_write(vsc_addr, 0, 0);
+ i2c_reg_write(vsc_addr, 1, 0);
+ } else {
+ i2c_reg_write(vsc_addr, 3, 0);
+ i2c_reg_write(vsc_addr, 4, 0);
+ }
+
+ /* configure global core control register, Turn on Global core power */
+ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
+
+ vsc_wp_config(vsc_addr);
+
+ return 0;
+}
+#endif
+
+int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+ unsigned int num_con)
+{
+ unsigned int i;
+ u8 rev_id = 0;
+ int ret;
+
+ debug("VSC:Initializing VSC3308 at I2C address 0x%x"
+ " for Tx\n", vsc_addr);
+
+ ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
+ if (ret < 0) {
+ printf("VSC:0x%x could not read REV_ID from device.\n",
+ vsc_addr);
+ return ret;
+ }
+
+ if (rev_id != 0xab) {
+ printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+ vsc_addr);
+ return -ENODEV;
+ }
+
+ ret = vsc_if_enable(vsc_addr);
+ if (ret) {
+ printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+ vsc_addr);
+ return ret;
+ }
+
+ /* config connections - page 0x00 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+ /* Making crosspoint connections, by connecting required
+ * input to output */
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
+
+ /*Configure Global Input ISE and gain */
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0x12);
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0x12);
+
+ /* input state - page 0x13 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+ /* Turning ON the required input of the switch */
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][0], 0);
+
+ /* Setting Global Input LOS threshold value */
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60);
+
+ /* config output mode - page 0x23 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+ /* Turn ON the Output driver correspond to required output*/
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][1], 0);
+
+ /* configure global core control register, Turn on Global core power */
+ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
+
+ vsc_wp_config(vsc_addr);
+
+ return 0;
+}
+
+void vsc_wp_config(unsigned int vsc_addr)
+{
+ debug("VSC:Configuring VSC at address:0x%x for WP\n", vsc_addr);
+
+ /* For new crosspoint configuration to occur, WP bit of
+ * CORE_CONFIG_REG should be set 1 and then reset to 0 */
+ i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01);
+ i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0);
+}
diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h
new file mode 100644
index 0000000..d722ea3
--- /dev/null
+++ b/board/freescale/common/vsc3316_3308.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __VSC_CROSSBAR_H_
+#define __VSC_CROSSBAR_H 1_
+
+#include <common.h>
+#include <i2c.h>
+#include <errno.h>
+
+int vsc_if_enable(unsigned int vsc_addr);
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
+ unsigned int num_con);
+#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
+ unsigned int num_con);
+#endif
+int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+ unsigned int num_con);
+void vsc_wp_config(unsigned int vsc_addr);
+
+#endif /* __VSC_CROSSBAR_H_ */
diff --git a/board/freescale/common/zm7300.c b/board/freescale/common/zm7300.c
new file mode 100644
index 0000000..be5953a
--- /dev/null
+++ b/board/freescale/common/zm7300.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Power-One ZM7300 DPM */
+#include "zm7300.h"
+
+#define DPM_WP 0x96
+#define WRP_OPCODE 0x01
+#define WRM_OPCODE 0x02
+#define RRP_OPCODE 0x11
+
+#define DPM_SUCCESS 0x01
+#define DPM_EXEC_FAIL 0x00
+
+static const uint16_t hex_to_1_10mv[] = {
+ 5000,
+ 5125,
+ 5250,
+ 5375,
+ 5500,
+ 5625,
+ 5750,
+ 5875,
+ 6000,
+ 6125,
+ 6250,
+ 6375,
+ 6500,
+ 6625,
+ 6750,
+ 6875,
+ 7000,
+ 7125,
+ 7250,
+ 7375,
+ 7500,
+ 7625,
+ 7750,
+ 7875,
+ 8000,
+ 8125,
+ 8250,
+ 8375,
+ 8500,
+ 8625,
+ 8750,
+ 8875,
+ 9000,
+ 9125,
+ 9250,
+ 9375,
+ 9500, /* 0.95mV */
+ 9625,
+ 9750,
+ 9875,
+ 10000, /* 1.0V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 11125,
+ 11250,
+ 11375,
+ 11500,
+ 11625,
+ 11750,
+ 11875,
+ 12000,
+ 12125,
+ 12250,
+ 12375,
+ 0, /* reserved */
+};
+
+
+/* Read Data d from Register r of POL p */
+u8 dpm_rrp(uchar r)
+{
+ u8 ret[5];
+
+ ret[0] = RRP_OPCODE;
+ /* POL is 0 */
+ ret[1] = 0;
+ ret[2] = r;
+ i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2);
+ if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("RRP_OPCODE returned success data is %x\n", ret[0]);
+ return ret[0];
+ } else {
+ return -1;
+ }
+}
+
+/* Write Data d into DPM register r (RAM) */
+int dpm_wrm(u8 r, u8 d)
+{
+ u8 ret[5];
+
+ ret[0] = WRM_OPCODE;
+ ret[1] = r;
+ ret[2] = d;
+ i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1);
+ if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("WRM_OPCODE returned success data is %x\n", ret[0]);
+ return ret[0];
+ } else {
+ return -1;
+ }
+}
+
+/* Write Data d into Register r of POL(s) a */
+int dpm_wrp(u8 r, u8 d)
+{
+ u8 ret[7];
+
+ ret[0] = WRP_OPCODE;
+ /* only POL0 is present */
+ ret[1] = 0x01;
+ ret[2] = 0x00;
+ ret[3] = 0x00;
+ ret[4] = 0x00;
+ ret[5] = r;
+ ret[6] = d;
+ i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1);
+ if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("WRP_OPCODE returned success data is %x\n", ret[0]);
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+/* Uses the DPM command RRP */
+u8 zm_read(uchar reg)
+{
+ u8 d;
+ d = dpm_rrp(reg);
+ return d;
+}
+
+/* ZM_write --
+ Steps:
+ a. Write data to the register
+ b. Read data from register and compare to written value
+ c. Return return_code & voltage_read
+*/
+u8 zm_write(u8 reg, u8 data)
+{
+ u8 d;
+
+ /* write data to register */
+ dpm_wrp(reg, data);
+
+ /* read register and compare to written value */
+ d = dpm_rrp(reg);
+ if (d != data) {
+ printf("zm_write : Comparison register data failed\n");
+ return -1;
+ }
+
+ return d;
+}
+
+/* zm_write_out_voltage
+ * voltage in 1/10 mV
+ */
+int zm_write_voltage(int voltage)
+{
+ u8 reg = 0x7, vid;
+ uint16_t voltage_read;
+ u8 ret;
+
+ vid = (voltage - 5000) / ZM_STEP;
+
+ ret = zm_write(reg, vid);
+ if (ret != -1) {
+ voltage_read = hex_to_1_10mv[ret];
+ debug("voltage set to %dmV\n", voltage_read/10);
+ return voltage_read;
+ }
+ return -1;
+}
+
+/* zm_read_out_voltage
+ * voltage in 1/10 mV
+ */
+int zm_read_voltage(void)
+{
+ u8 reg = 0x7;
+ u8 ret;
+ int voltage;
+
+ ret = zm_read(reg);
+ if (ret != -1) {
+ voltage = hex_to_1_10mv[ret];
+ debug("Voltage read is %dmV\n", voltage/10);
+ return voltage;
+ } else {
+ return -1;
+ }
+}
+
+int zm_disable_wp()
+{
+ u8 new_wp_value;
+
+ /* Disable using Write-Protect register 0x96 */
+ new_wp_value = 0x8;
+ if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) {
+ printf("Disable Write-Protect register failed\n");
+ return -1;
+ }
+ return 0;
+}
+
+int zm_enable_wp()
+{
+ u8 orig_wp_value;
+ orig_wp_value = 0x0;
+
+ /* Enable using Write-Protect register 0x96 */
+ if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) {
+ printf("Enable Write-Protect register failed\n");
+ return -1;
+ }
+ return 0;
+}
+
diff --git a/board/freescale/common/zm7300.h b/board/freescale/common/zm7300.h
new file mode 100644
index 0000000..6b4d035
--- /dev/null
+++ b/board/freescale/common/zm7300.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ZM7300_H_
+#define __ZM7300_H 1_
+
+#include <common.h>
+#include <i2c.h>
+#include <errno.h>
+#include <asm/io.h>
+
+#define ZM_STEP 125
+int zm7300_set_voltage(int voltage_1_10mv);
+int zm_write_voltage(int voltage);
+int zm_read_voltage(void);
+int zm_disable_wp(void);
+int zm_enable_wp(void);
+
+#endif /* __ZM7300_H_ */
diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig
new file mode 100644
index 0000000..433f539
--- /dev/null
+++ b/board/freescale/corenet_ds/Kconfig
@@ -0,0 +1,51 @@
+if TARGET_P3041DS
+
+config SYS_BOARD
+ default "corenet_ds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "P3041DS"
+
+endif
+
+if TARGET_P4080DS
+
+config SYS_BOARD
+ default "corenet_ds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "P4080DS"
+
+endif
+
+if TARGET_P5020DS
+
+config SYS_BOARD
+ default "corenet_ds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "P5020DS"
+
+endif
+
+if TARGET_P5040DS
+
+config SYS_BOARD
+ default "corenet_ds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "P5040DS"
+
+endif
diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
new file mode 100644
index 0000000..c8ca674
--- /dev/null
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -0,0 +1,29 @@
+CORENET_DS BOARD
+#M: -
+S: Maintained
+F: board/freescale/corenet_ds/
+F: include/configs/P3041DS.h
+F: configs/P3041DS_defconfig
+F: configs/P3041DS_NAND_defconfig
+F: configs/P3041DS_SDCARD_defconfig
+F: configs/P3041DS_SECURE_BOOT_defconfig
+F: configs/P3041DS_SPIFLASH_defconfig
+F: configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+F: include/configs/P4080DS.h
+F: configs/P4080DS_defconfig
+F: configs/P4080DS_SDCARD_defconfig
+F: configs/P4080DS_SECURE_BOOT_defconfig
+F: configs/P4080DS_SPIFLASH_defconfig
+F: configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+F: include/configs/P5020DS.h
+F: configs/P5020DS_defconfig
+F: configs/P5020DS_NAND_defconfig
+F: configs/P5020DS_SDCARD_defconfig
+F: configs/P5020DS_SECURE_BOOT_defconfig
+F: configs/P5020DS_SPIFLASH_defconfig
+F: configs/P5020DS_SRIO_PCIE_BOOT_defconfig
+F: include/configs/P5040DS.h
+F: configs/P5040DS_defconfig
+F: configs/P5040DS_NAND_defconfig
+F: configs/P5040DS_SDCARD_defconfig
+F: configs/P5040DS_SPIFLASH_defconfig
diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile
new file mode 100644
index 0000000..9ade947
--- /dev/null
+++ b/board/freescale/corenet_ds/Makefile
@@ -0,0 +1,18 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += corenet_ds.o
+obj-y += ddr.o
+obj-$(CONFIG_P3041DS) += eth_hydra.o
+obj-$(CONFIG_P4080DS) += eth_p4080.o
+obj-$(CONFIG_P5020DS) += eth_hydra.o
+obj-$(CONFIG_P5040DS) += eth_superhydra.o
+obj-$(CONFIG_P3041DS) += p3041ds_ddr.o
+obj-$(CONFIG_P4080DS) += p4080ds_ddr.o
+obj-$(CONFIG_P5020DS) += p5020ds_ddr.o
+obj-$(CONFIG_P5040DS) += p5040ds_ddr.o
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
new file mode 100644
index 0000000..6f0fea1
--- /dev/null
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/ngpixis.h"
+#include "corenet_ds.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard (void)
+{
+ u8 sw;
+ struct cpu_type *cpu = gd->arch.cpu;
+#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \
+ defined(CONFIG_P5040DS)
+ unsigned int i;
+#endif
+ static const char * const freq[] = {"100", "125", "156.25", "212.5" };
+
+ printf("Board: %sDS, ", cpu->name);
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
+
+ sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+ sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw == 0x8)
+ puts("Promjet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else
+ printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
+
+ /* Display the actual SERDES reference clocks as configured by the
+ * dip switches on the board. Note that the SWx registers could
+ * technically be set to force the reference clocks to match the
+ * values that the SERDES expects (or vice versa). For now, however,
+ * we just display both values and hope the user notices when they
+ * don't match.
+ */
+ puts("SERDES Reference Clocks: ");
+#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
+ || defined(CONFIG_P5040DS)
+ sw = in_8(&PIXIS_SW(5));
+ for (i = 0; i < 3; i++) {
+ unsigned int clock = (sw >> (6 - (2 * i))) & 3;
+
+ printf("Bank%u=%sMhz ", i+1, freq[clock]);
+ }
+#ifdef CONFIG_P5040DS
+ /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
+ sw = in_8(&PIXIS_SW(9));
+ printf("Bank4=%sMhz ", freq[sw & 3]);
+#endif
+ puts("\n");
+#else
+ sw = in_8(&PIXIS_SW(3));
+ /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */
+ /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */
+ /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */
+ printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
+ printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
+ printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
+#endif
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ /*
+ * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3
+ * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
+ * the noise introduced by these unterminated and unused clock pairs.
+ */
+ setbits_be32(&gur->ddrclkdr, 0x001B001B);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+#define NUM_SRDS_BANKS 3
+
+int misc_init_r(void)
+{
+ serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 actual[NUM_SRDS_BANKS];
+ unsigned int i;
+ u8 sw;
+
+#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
+ || defined(CONFIG_P5040DS)
+ sw = in_8(&PIXIS_SW(5));
+ for (i = 0; i < 3; i++) {
+ unsigned int clock = (sw >> (6 - (2 * i))) & 3;
+ switch (clock) {
+ case 0:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+ break;
+ case 1:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+ break;
+ case 2:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
+ break;
+ default:
+ printf("Warning: SDREFCLK%u switch setting of '11' is "
+ "unsupported\n", i + 1);
+ break;
+ }
+ }
+#else
+ /* Warn if the expected SERDES reference clocks don't match the
+ * actual reference clocks. This needs to be done after calling
+ * p4080_erratum_serdes8(), since that function may modify the clocks.
+ */
+ sw = in_8(&PIXIS_SW(3));
+ actual[0] = (sw & 0x40) ?
+ SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100;
+ actual[1] = (sw & 0x20) ?
+ SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
+ actual[2] = (sw & 0x10) ?
+ SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125;
+#endif
+
+ for (i = 0; i < NUM_SRDS_BANKS; i++) {
+ u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+ if (expected != actual[i]) {
+ printf("Warning: SERDES bank %u expects reference clock"
+ " %sMHz, but actual is %sMHz\n", i + 1,
+ serdes_clock_to_string(expected),
+ serdes_clock_to_string(actual[i]));
+ }
+ }
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
diff --git a/board/freescale/corenet_ds/corenet_ds.h b/board/freescale/corenet_ds/corenet_ds.h
new file mode 100644
index 0000000..ca4986e
--- /dev/null
+++ b/board/freescale/corenet_ds/corenet_ds.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
new file mode 100644
index 0000000..e7e893a
--- /dev/null
+++ b/board/freescale/corenet_ds/ddr.c
@@ -0,0 +1,284 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+extern fixed_ddr_parm_t fixed_ddr_parm_0[];
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+extern fixed_ddr_parm_t fixed_ddr_parm_1[];
+#endif
+
+phys_size_t fixed_sdram(void)
+{
+ int i;
+ char buf[32];
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
+ phys_size_t ddr_size;
+ unsigned int lawbar1_target_id;
+ ulong ddr_freq, ddr_freq_mhz;
+
+ ddr_freq = get_ddr_freq(0);
+ ddr_freq_mhz = ddr_freq / 1000000;
+
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+ if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+ (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+ memcpy(&ddr_cfg_regs,
+ fixed_ddr_parm_0[i].ddr_settings,
+ sizeof(ddr_cfg_regs));
+ break;
+ }
+ }
+
+ if (fixed_ddr_parm_0[i].max_freq == 0)
+ panic("Unsupported DDR data rate %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+ memcpy(&ddr_cfg_regs,
+ fixed_ddr_parm_1[i].ddr_settings,
+ sizeof(ddr_cfg_regs));
+ ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0);
+#endif
+
+ /*
+ * setup laws for DDR. If not interleaving, presuming half memory on
+ * DDR1 and the other half on DDR2
+ */
+ if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size,
+ LAW_TRGT_IF_DDR_INTRLV) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+ } else {
+#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+ /* We require both controllers have identical DIMMs */
+ lawbar1_target_id = LAW_TRGT_IF_DDR_1;
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size / 2,
+ lawbar1_target_id) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+ lawbar1_target_id = LAW_TRGT_IF_DDR_2;
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
+ ddr_size / 2,
+ lawbar1_target_id) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+#else
+ lawbar1_target_id = LAW_TRGT_IF_DDR_1;
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size,
+ lawbar1_target_id) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+#endif
+ }
+ return ddr_size;
+}
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | |delay |
+ */
+ {4, 850, 4, 6, 0xff, 2, 0},
+ {4, 950, 5, 7, 0xff, 2, 0},
+ {4, 1050, 5, 8, 0xff, 2, 0},
+ {4, 1250, 5, 10, 0xff, 2, 0},
+ {4, 1350, 5, 11, 0xff, 2, 0},
+ {4, 1666, 5, 12, 0xff, 2, 0},
+ {2, 850, 5, 6, 0xff, 2, 0},
+ {2, 1050, 5, 7, 0xff, 2, 0},
+ {2, 1250, 4, 6, 0xff, 2, 0},
+ {2, 1350, 5, 7, 0xff, 2, 0},
+ {2, 1666, 5, 8, 0xff, 2, 0},
+ {1, 1250, 4, 6, 0xff, 2, 0},
+ {1, 1335, 4, 7, 0xff, 2, 0},
+ {1, 1666, 4, 8, 0xff, 2, 0},
+ {}
+};
+
+/*
+ * The two slots have slightly different timing. The center values are good
+ * for both slots. We use identical speed tables for them. In future use, if
+ * DIMMs have fewer center values that require two separated tables, copy the
+ * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
+ */
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+ udimm0,
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | |delay |
+ */
+ {4, 850, 4, 6, 0xff, 2, 0},
+ {4, 950, 5, 7, 0xff, 2, 0},
+ {4, 1050, 5, 8, 0xff, 2, 0},
+ {4, 1250, 5, 10, 0xff, 2, 0},
+ {4, 1350, 5, 11, 0xff, 2, 0},
+ {4, 1666, 5, 12, 0xff, 2, 0},
+ {2, 850, 4, 6, 0xff, 2, 0},
+ {2, 1050, 4, 7, 0xff, 2, 0},
+ {2, 1666, 4, 8, 0xff, 2, 0},
+ {1, 850, 4, 5, 0xff, 2, 0},
+ {1, 950, 4, 7, 0xff, 2, 0},
+ {1, 1666, 4, 8, 0xff, 2, 0},
+ {}
+};
+
+/*
+ * The two slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+ rdimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[ctrl_num];
+ else
+ pbsp = udimms[ctrl_num];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->twot_en = pbsp->force_2t;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->twot_en = pbsp_highest->force_2t;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 60 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....");
+
+ if (fsl_use_spd()) {
+ puts("using SPD\n");
+ dram_size = fsl_ddr_sdram();
+ } else {
+ puts("using fixed parameters\n");
+ dram_size = fixed_sdram();
+ }
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ debug(" DDR: ");
+ return dram_size;
+}
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c
new file mode 100644
index 0000000..396103f
--- /dev/null
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -0,0 +1,520 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This file handles the board muxing between the Fman Ethernet MACs and
+ * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference
+ * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
+ * provided by the standard Freescale four-port SGMII riser card. The 10Gb
+ * XGMII PHY is provided via the XAUI riser card. Since there is only one
+ * Fman device on a P3041 and P5020, we only support one SGMII card and one
+ * RGMII card.
+ *
+ * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
+ * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
+ * always the same (0). The value for SGMII depends on which slot the riser is
+ * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
+ * the value is based on which slot the XAUI is inserted in.
+ *
+ * The SERDES configuration is used to determine where the SGMII and XAUI cards
+ * exist, and also which Fman MACs are routed to which PHYs. So for a given
+ * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
+ * to PHYs dynamically.
+ *
+ *
+ * This file also updates the device tree in three ways:
+ *
+ * 1) The status of each virtual MDIO node that is referenced by an Ethernet
+ * node is set to "okay".
+ *
+ * 2) The phy-handle property of each active Ethernet MAC node is set to the
+ * appropriate PHY node.
+ *
+ * 3) The "mux value" for each virtual MDIO node is set to the correct value,
+ * if necessary. Some virtual MDIO nodes do not have configurable mux
+ * values, so those values are hard-coded in the DTS. On the HYDRA board,
+ * the virtual MDIO node for the SGMII card needs to be updated.
+ *
+ * For all this to work, the device tree needs to have the following:
+ *
+ * 1) An alias for each PHY node that an Ethernet node could be routed to.
+ *
+ * 2) An alias for each real and virtual MDIO node that is disabled by default
+ * and might need to be enabled, and also might need to have its mux-value
+ * updated.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fdt_support.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/ngpixis.h"
+#include "../common/fman.h"
+
+#ifdef CONFIG_FMAN_ENET
+
+#define BRDCFG1_EMI1_SEL_MASK 0x78
+#define BRDCFG1_EMI1_SEL_SLOT1 0x10
+#define BRDCFG1_EMI1_SEL_SLOT2 0x20
+#define BRDCFG1_EMI1_SEL_SLOT5 0x30
+#define BRDCFG1_EMI1_SEL_SLOT6 0x40
+#define BRDCFG1_EMI1_SEL_SLOT7 0x50
+#define BRDCFG1_EMI1_SEL_RGMII 0x00
+#define BRDCFG1_EMI1_EN 0x08
+#define BRDCFG1_EMI2_SEL_MASK 0x06
+#define BRDCFG1_EMI2_SEL_SLOT1 0x00
+#define BRDCFG1_EMI2_SEL_SLOT2 0x02
+
+#define BRDCFG2_REG_GPIO_SEL 0x20
+
+#define PHY_BASE_ADDR 0x00
+
+/*
+ * BRDCFG1 mask and value for each MAC
+ *
+ * This array contains the BRDCFG1 values (in mask/val format) that route the
+ * MDIO bus to a particular RGMII or SGMII PHY.
+ */
+struct {
+ u8 mask;
+ u8 val;
+} mdio_mux[NUM_FM_PORTS];
+
+/*
+ * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot
+ */
+static u8 lane_to_slot[] = {
+ 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
+};
+
+/*
+ * Set the board muxing for a given MAC
+ *
+ * The MDIO layer calls this function every time it wants to talk to a PHY.
+ */
+void hydra_mux_mdio(u8 mask, u8 val)
+{
+ clrsetbits_8(&pixis->brdcfg1, mask, val);
+}
+
+struct hydra_mdio {
+ u8 mask;
+ u8 val;
+ struct mii_dev *realbus;
+};
+
+static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct hydra_mdio *priv = bus->priv;
+
+ hydra_mux_mdio(priv->mask, priv->val);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct hydra_mdio *priv = bus->priv;
+
+ hydra_mux_mdio(priv->mask, priv->val);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int hydra_mdio_reset(struct mii_dev *bus)
+{
+ struct hydra_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static void hydra_mdio_set_mux(char *name, u8 mask, u8 val)
+{
+ struct mii_dev *bus = miiphy_get_dev_by_name(name);
+ struct hydra_mdio *priv = bus->priv;
+
+ priv->mask = mask;
+ priv->val = val;
+}
+
+static int hydra_mdio_init(char *realbusname, char *fakebusname)
+{
+ struct hydra_mdio *hmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate Hydra MDIO bus\n");
+ return -1;
+ }
+
+ hmdio = malloc(sizeof(*hmdio));
+ if (!hmdio) {
+ printf("Failed to allocate Hydra private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = hydra_mdio_read;
+ bus->write = hydra_mdio_write;
+ bus->reset = hydra_mdio_reset;
+ sprintf(bus->name, fakebusname);
+
+ hmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!hmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(hmdio);
+ return -1;
+ }
+
+ bus->priv = hmdio;
+
+ return mdio_register(bus);
+}
+
+/*
+ * Given an alias or a path for a node, set the mux value of that node.
+ *
+ * If 'alias' is not a valid alias, then it is treated as a full path to the
+ * node. No error checking is performed.
+ *
+ * This function is normally called to set the fsl,hydra-mdio-muxval property
+ * of a virtual MDIO node.
+ */
+static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
+{
+ const char *path = fdt_get_alias(fdt, alias);
+
+ if (!path)
+ path = alias;
+
+ do_fixup_by_path(fdt, path, "reg",
+ &mux, sizeof(mux), 1);
+ do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
+ &mux, sizeof(mux), 1);
+}
+
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) An Fman port
+ *
+ * ... update the phy-handle property of the Ethernet node to point to the
+ * right PHY. This assumes that we already know the PHY for each port. That
+ * information is stored in mdio_mux[].
+ *
+ * The offset of the Fman Ethernet node is also passed in for convenience, but
+ * it is not used, and we recalculate the offset anyway.
+ *
+ * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
+ * Inside the Fman, "ports" are things that connect to MACs. We only call them
+ * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
+ * and ports are the same thing.
+ *
+ * Note that this code would be cleaner if had a function called
+ * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[]
+ * array. That's because all we're doing is figuring out the PHY address for
+ * a given Fman MAC and writing it to the device tree. Well, we already did
+ * the hard work to figure that out in board_eth_init(), so it's silly to
+ * repeat that here.
+ */
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask;
+ char phy[16];
+
+ if (port == FM1_10GEC1) {
+ /* XAUI */
+ int lane = serdes_get_first_lane(XAUI_FM1);
+ if (lane >= 0) {
+ /* The XAUI PHY is identified by the slot */
+ sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
+ fdt_set_phy_handle(fdt, compat, addr, phy);
+ }
+ return;
+ }
+
+ if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) {
+ /* RGMII */
+ /* The RGMII PHY is identified by the MAC connected to it */
+ sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
+ fdt_set_phy_handle(fdt, compat, addr, phy);
+ return;
+ }
+
+ /* If it's not RGMII or XGMII, it must be SGMII */
+ if (mux) {
+ /* The SGMII PHY is identified by the MAC connected to it */
+ sprintf(phy, "phy_sgmii_%x",
+ CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1));
+ fdt_set_phy_handle(fdt, compat, addr, phy);
+ }
+}
+
+#define PIXIS_SW2_LANE_23_SEL 0x80
+#define PIXIS_SW2_LANE_45_SEL 0x40
+#define PIXIS_SW2_LANE_67_SEL_MASK 0x30
+#define PIXIS_SW2_LANE_67_SEL_5 0x00
+#define PIXIS_SW2_LANE_67_SEL_6 0x20
+#define PIXIS_SW2_LANE_67_SEL_7 0x10
+#define PIXIS_SW2_LANE_8_SEL 0x08
+#define PIXIS_SW2_LANE_1617_SEL 0x04
+
+/*
+ * Initialize the lane_to_slot[] array.
+ *
+ * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
+ * slots is hard-coded. On the Hydra board, however, the mapping is controlled
+ * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
+ * initialized.
+ */
+static void initialize_lane_to_slot(void)
+{
+ u8 sw2 = in_8(&PIXIS_SW(2));
+
+ lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
+ lane_to_slot[3] = lane_to_slot[2];
+
+ lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
+ lane_to_slot[5] = lane_to_slot[4];
+
+ switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
+ case PIXIS_SW2_LANE_67_SEL_5:
+ lane_to_slot[6] = 5;
+ break;
+ case PIXIS_SW2_LANE_67_SEL_6:
+ lane_to_slot[6] = 6;
+ break;
+ case PIXIS_SW2_LANE_67_SEL_7:
+ lane_to_slot[6] = 7;
+ break;
+ }
+ lane_to_slot[7] = lane_to_slot[6];
+
+ lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
+
+ lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
+ lane_to_slot[17] = lane_to_slot[16];
+}
+
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+/*
+ * Configure the status for the virtual MDIO nodes
+ *
+ * Rather than create the virtual MDIO nodes from scratch for each active
+ * virtual MDIO, we expect the DTS to have the nodes defined already, and we
+ * only enable the ones that are actually active.
+ *
+ * We assume that the DTS already hard-codes the status for all the
+ * virtual MDIO nodes to "disabled", so all we need to do is enable the
+ * active ones.
+ *
+ * For SGMII, we also need to set the mux value in the node.
+ */
+void fdt_fixup_board_enet(void *fdt)
+{
+#ifdef CONFIG_FMAN_ENET
+ unsigned int i;
+ int lane;
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+ if (lane >= 0) {
+ fdt_status_okay_by_alias(fdt, "emi1_sgmii");
+ /* Also set the MUX value */
+ fdt_set_mdio_mux(fdt, "emi1_sgmii",
+ mdio_mux[i].val);
+ }
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ fdt_status_okay_by_alias(fdt, "emi1_rgmii");
+ break;
+ default:
+ break;
+ }
+ }
+
+ lane = serdes_get_first_lane(XAUI_FM1);
+ if (lane >= 0)
+ fdt_status_okay_by_alias(fdt, "emi2_xgmii");
+#endif
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct fsl_pq_mdio_info dtsec_mdio_info;
+ struct tgec_mdio_info tgec_mdio_info;
+ unsigned int i, slot;
+ int lane;
+ struct mii_dev *bus;
+
+ printf("Initializing Fman\n");
+
+ initialize_lane_to_slot();
+
+ /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
+ setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
+
+ memset(mdio_mux, 0, sizeof(mdio_mux));
+
+ dtsec_mdio_info.regs =
+ (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the real 1G MDIO bus */
+ fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the real 10G MDIO bus */
+ fm_tgec_mdio_init(bis, &tgec_mdio_info);
+
+ /* Register the three virtual MDIO front-ends */
+ hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO");
+ hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO");
+
+ /*
+ * Program the DTSEC PHY addresses assuming that they are all SGMII.
+ * For any DTSEC that's RGMII, we'll override its PHY address later.
+ * We assume that DTSEC5 is only used for RGMII.
+ */
+ fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot[lane];
+ mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
+ switch (slot) {
+ case 1:
+ /* Always DTSEC5 on Bank 3 */
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 2:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 5:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 6:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 7:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
+ BRDCFG1_EMI1_EN;
+ break;
+ };
+
+ hydra_mdio_set_mux("HYDRA_SGMII_MDIO",
+ mdio_mux[i].mask, mdio_mux[i].val);
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ /*
+ * If DTSEC4 is RGMII, then it's routed via via EC1 to
+ * the first on-board RGMII port. If DTSEC5 is RGMII,
+ * then it's routed via via EC2 to the second on-board
+ * RGMII port. The other DTSECs cannot be routed to
+ * RGMII.
+ */
+ fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1);
+ mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
+ BRDCFG1_EMI1_EN;
+ hydra_mdio_set_mux("HYDRA_RGMII_MDIO",
+ mdio_mux[i].mask, mdio_mux[i].val);
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
+ break;
+ default:
+ printf("Fman1: DTSEC%u set to unknown interface %i\n",
+ idx + 1, fm_info_get_enet_if(i));
+ fm_info_set_phy_address(i, 0);
+ break;
+ }
+ }
+
+ bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
+ set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
+
+ /*
+ * For 10G, we only support one XAUI card per Fman. If present, then we
+ * force its routing and never touch those bits again, which removes the
+ * need for Linux to do any muxing. This works because of the way
+ * BRDCFG1 is defined, but it's a bit hackish.
+ *
+ * The PHY address for the XAUI card depends on which slot it's in. The
+ * macros we use imply that the PHY address is based on which FM, but
+ * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
+ * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
+ * check the actual slot and just use the macros as-is, even though
+ * the P3041 and P5020 only have one Fman.
+ */
+ lane = serdes_get_first_lane(XAUI_FM1);
+ if (lane >= 0) {
+ slot = lane_to_slot[lane];
+ if (slot == 1) {
+ /* XAUI card is in slot 1 */
+ clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
+ BRDCFG1_EMI2_SEL_SLOT1);
+ fm_info_set_phy_address(FM1_10GEC1,
+ CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+ } else {
+ /* XAUI card is in slot 2 */
+ clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
+ BRDCFG1_EMI2_SEL_SLOT2);
+ fm_info_set_phy_address(FM1_10GEC1,
+ CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
+ }
+ }
+
+ fm_info_set_mdio(FM1_10GEC1,
+ miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
+
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
new file mode 100644
index 0000000..5cbec7f
--- /dev/null
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -0,0 +1,481 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+
+#include "../common/ngpixis.h"
+#include "../common/fman.h"
+#include <asm/fsl_dtsec.h>
+
+#define EMI_NONE 0xffffffff
+#define EMI_MASK 0xf0000000
+#define EMI1_RGMII 0x0
+#define EMI1_SLOT3 0x80000000 /* bank1 EFGH */
+#define EMI1_SLOT4 0x40000000 /* bank2 ABCD */
+#define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */
+#define EMI2_SLOT4 0x10000000 /* bank2 ABCD */
+#define EMI2_SLOT5 0x30000000 /* bank3 ABCD */
+#define EMI1_MASK 0xc0000000
+#define EMI2_MASK 0x30000000
+
+#define PHY_BASE_ADDR 0x00
+#define PHY_BASE_ADDR_SLOT5 0x10
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static char *mdio_names[16] = {
+ "P4080DS_MDIO0",
+ "P4080DS_MDIO1",
+ NULL,
+ "P4080DS_MDIO3",
+ "P4080DS_MDIO4",
+ NULL, NULL, NULL,
+ "P4080DS_MDIO8",
+ NULL, NULL, NULL,
+ "P4080DS_MDIO12",
+ NULL, NULL, NULL,
+};
+
+/*
+ * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot.
+ */
+static u8 lane_to_slot[] = {
+ 1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
+};
+
+static char *p4080ds_mdio_name_for_muxval(u32 muxval)
+{
+ return mdio_names[(muxval & EMI_MASK) >> 28];
+}
+
+struct mii_dev *mii_dev_for_muxval(u32 muxval)
+{
+ struct mii_dev *bus;
+ char *name = p4080ds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS)
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ if (phydev->drv->uid == PHY_UID_TN2020) {
+ unsigned long timeout = 1 * 1000; /* 1 seconds */
+ enum srds_prtcl device;
+
+ /*
+ * Wait for the XAUI to come out of reset. This is when it
+ * starts transmitting alignment signals.
+ */
+ while (--timeout) {
+ int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1);
+ if (reg < 0) {
+ printf("TN2020: Error reading from PHY at "
+ "address %u\n", phydev->addr);
+ break;
+ }
+ /*
+ * Note that we've never actually seen
+ * MDIO_CTRL1_RESET set to 1.
+ */
+ if ((reg & MDIO_CTRL1_RESET) == 0)
+ break;
+ udelay(1000);
+ }
+
+ if (!timeout) {
+ printf("TN2020: Timeout waiting for PHY at address %u "
+ " to reset.\n", phydev->addr);
+ }
+
+ switch (phydev->addr) {
+ case CONFIG_SYS_FM1_10GEC1_PHY_ADDR:
+ device = XAUI_FM1;
+ break;
+ case CONFIG_SYS_FM2_10GEC1_PHY_ADDR:
+ device = XAUI_FM2;
+ break;
+ default:
+ device = NONE;
+ }
+
+ serdes_reset_rx(device);
+ }
+
+ return 0;
+}
+#endif
+
+struct p4080ds_mdio {
+ u32 muxval;
+ struct mii_dev *realbus;
+};
+
+static void p4080ds_mux_mdio(u32 muxval)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
+ gpioval |= muxval;
+
+ out_be32(&pgpio->gpdat, gpioval);
+}
+
+static int p4080ds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct p4080ds_mdio *priv = bus->priv;
+
+ p4080ds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int p4080ds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct p4080ds_mdio *priv = bus->priv;
+
+ p4080ds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int p4080ds_mdio_reset(struct mii_dev *bus)
+{
+ struct p4080ds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int p4080ds_mdio_init(char *realbusname, u32 muxval)
+{
+ struct p4080ds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate P4080DS MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate P4080DS private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = p4080ds_mdio_read;
+ bus->write = p4080ds_mdio_write;
+ bus->reset = p4080ds_mdio_reset;
+ sprintf(bus->name, p4080ds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+
+ return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
+ enum fm_port port, int offset)
+{
+ if (mdio_mux[port] == EMI1_RGMII)
+ fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
+
+ if (mdio_mux[port] == EMI1_SLOT3) {
+ int idx = port - FM2_DTSEC1 + 5;
+ char phy[16];
+
+ sprintf(phy, "phy%d_slot3", idx);
+
+ fdt_set_phy_handle(blob, prop, pa, phy);
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int i;
+
+ /*
+ * P4080DS can be configured in many different ways, supporting a number
+ * of combinations of ethernet devices and phy types. In order to
+ * have just one device tree for all of those configurations, we fix up
+ * the tree here. By default, the device tree configures FM1 and FM2
+ * for SGMII, and configures XAUI on both 10G interfaces. So we have
+ * a number of different variables to track:
+ *
+ * 1) Whether the device is configured at all. Whichever devices are
+ * not enabled should be disabled by setting the "status" property
+ * to "disabled".
+ * 2) What the PHY interface is. If this is an RGMII connection,
+ * we should change the "phy-connection-type" property to
+ * "rgmii"
+ * 3) Which PHY is being used. Because the MDIO buses are muxed,
+ * we need to redirect the "phy-handle" property to point at the
+ * PHY on the right slot/bus.
+ */
+
+ /* We've got six MDIO nodes that may or may not need to exist */
+ fdt_status_disabled_by_alias(fdt, "emi1_slot3");
+ fdt_status_disabled_by_alias(fdt, "emi1_slot4");
+ fdt_status_disabled_by_alias(fdt, "emi1_slot5");
+ fdt_status_disabled_by_alias(fdt, "emi2_slot4");
+ fdt_status_disabled_by_alias(fdt, "emi2_slot5");
+
+ for (i = 0; i < NUM_FM_PORTS; i++) {
+ switch (mdio_mux[i]) {
+ case EMI1_SLOT3:
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ break;
+ case EMI1_SLOT4:
+ fdt_status_okay_by_alias(fdt, "emi1_slot4");
+ break;
+ case EMI1_SLOT5:
+ fdt_status_okay_by_alias(fdt, "emi1_slot5");
+ break;
+ case EMI2_SLOT4:
+ fdt_status_okay_by_alias(fdt, "emi2_slot4");
+ break;
+ case EMI2_SLOT5:
+ fdt_status_okay_by_alias(fdt, "emi2_slot5");
+ break;
+ }
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ int i;
+ struct fsl_pq_mdio_info dtsec_mdio_info;
+ struct tgec_mdio_info tgec_mdio_info;
+ struct mii_dev *bus;
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ /* The first 4 GPIOs are outputs to control MDIO bus muxing */
+ out_be32(&pgpio->gpdir, EMI_MASK);
+
+ dtsec_mdio_info.regs =
+ (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_tgec_mdio_init(bis, &tgec_mdio_info);
+
+ /* Register the 6 muxing front-ends to the MDIO buses */
+ p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
+ p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+ p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+ p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+ p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
+ p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
+
+ fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
+#endif
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1, lane, slot;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot[lane];
+ switch (slot) {
+ case 3:
+ mdio_mux[i] = EMI1_SLOT3;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 4:
+ mdio_mux[i] = EMI1_SLOT4;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 5:
+ mdio_mux[i] = EMI1_SLOT5;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ };
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ fm_info_set_phy_address(i, 0);
+ mdio_mux[i] = EMI1_RGMII;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+ bus = mii_dev_for_muxval(EMI1_SLOT5);
+ set_sgmii_phy(bus, FM1_DTSEC1,
+ CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5);
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ int idx = i - FM1_10GEC1, lane, slot;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ lane = serdes_get_first_lane(XAUI_FM1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot[lane];
+ switch (slot) {
+ case 4:
+ mdio_mux[i] = EMI2_SLOT4;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 5:
+ mdio_mux[i] = EMI2_SLOT5;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ };
+ break;
+ default:
+ break;
+ }
+ }
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+ int idx = i - FM2_DTSEC1, lane, slot;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot[lane];
+ switch (slot) {
+ case 3:
+ mdio_mux[i] = EMI1_SLOT3;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 4:
+ mdio_mux[i] = EMI1_SLOT4;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 5:
+ mdio_mux[i] = EMI1_SLOT5;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ };
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ fm_info_set_phy_address(i, 0);
+ mdio_mux[i] = EMI1_RGMII;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ bus = mii_dev_for_muxval(EMI1_SLOT3);
+ set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
+ bus = mii_dev_for_muxval(EMI1_SLOT4);
+ set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
+
+ for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+ int idx = i - FM2_10GEC1, lane, slot;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ lane = serdes_get_first_lane(XAUI_FM2 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot[lane];
+ switch (slot) {
+ case 4:
+ mdio_mux[i] = EMI2_SLOT4;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 5:
+ mdio_mux[i] = EMI2_SLOT5;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ };
+ break;
+ default:
+ break;
+ }
+ }
+#endif
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c
new file mode 100644
index 0000000..ad1bffd
--- /dev/null
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -0,0 +1,770 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This file handles the board muxing between the Fman Ethernet MACs and
+ * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference
+ * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
+ * provided by the standard Freescale four-port SGMII riser card. The 10Gb
+ * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans
+ * and 5 1G interfaces and 10G interface per FMan. Based on the options in
+ * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time.
+ *
+ * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
+ * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
+ * always the same (0). The value for SGMII depends on which slot the riser is
+ * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
+ * the value is based on which slot the XAUI is inserted in.
+ *
+ * The SERDES configuration is used to determine where the SGMII and XAUI cards
+ * exist, and also which Fman's MACs are routed to which PHYs. So for a given
+ * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
+ * to PHYs dynamically.
+ *
+ *
+ * This file also updates the device tree in three ways:
+ *
+ * 1) The status of each virtual MDIO node that is referenced by an Ethernet
+ * node is set to "okay".
+ *
+ * 2) The phy-handle property of each active Ethernet MAC node is set to the
+ * appropriate PHY node.
+ *
+ * 3) The "mux value" for each virtual MDIO node is set to the correct value,
+ * if necessary. Some virtual MDIO nodes do not have configurable mux
+ * values, so those values are hard-coded in the DTS. On the HYDRA board,
+ * the virtual MDIO node for the SGMII card needs to be updated.
+ *
+ * For all this to work, the device tree needs to have the following:
+ *
+ * 1) An alias for each PHY node that an Ethernet node could be routed to.
+ *
+ * 2) An alias for each real and virtual MDIO node that is disabled by default
+ * and might need to be enabled, and also might need to have its mux-value
+ * updated.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fdt_support.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/ngpixis.h"
+#include "../common/fman.h"
+
+#ifdef CONFIG_FMAN_ENET
+
+#define BRDCFG1_EMI1_SEL_MASK 0x70
+#define BRDCFG1_EMI1_SEL_SLOT1 0x10
+#define BRDCFG1_EMI1_SEL_SLOT2 0x20
+#define BRDCFG1_EMI1_SEL_SLOT5 0x30
+#define BRDCFG1_EMI1_SEL_SLOT6 0x40
+#define BRDCFG1_EMI1_SEL_SLOT7 0x50
+#define BRDCFG1_EMI1_SEL_SLOT3 0x60
+#define BRDCFG1_EMI1_SEL_RGMII 0x00
+#define BRDCFG1_EMI1_EN 0x08
+#define BRDCFG1_EMI2_SEL_MASK 0x06
+#define BRDCFG1_EMI2_SEL_SLOT1 0x00
+#define BRDCFG1_EMI2_SEL_SLOT2 0x02
+
+#define BRDCFG2_REG_GPIO_SEL 0x20
+
+/* SGMII */
+#define PHY_BASE_ADDR 0x00
+#define REGNUM 0x00
+#define PORT_NUM_FM1 0x04
+#define PORT_NUM_FM2 0x02
+
+/*
+ * BRDCFG1 mask and value for each MAC
+ *
+ * This array contains the BRDCFG1 values (in mask/val format) that route the
+ * MDIO bus to a particular RGMII or SGMII PHY.
+ */
+static struct {
+ u8 mask;
+ u8 val;
+} mdio_mux[NUM_FM_PORTS];
+
+/*
+ * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot
+ */
+static u8 lane_to_slot[] = {
+ 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0
+};
+
+/*
+ * Set the board muxing for a given MAC
+ *
+ * The MDIO layer calls this function every time it wants to talk to a PHY.
+ */
+void super_hydra_mux_mdio(u8 mask, u8 val)
+{
+ clrsetbits_8(&pixis->brdcfg1, mask, val);
+}
+
+struct super_hydra_mdio {
+ u8 mask;
+ u8 val;
+ struct mii_dev *realbus;
+};
+
+static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct super_hydra_mdio *priv = bus->priv;
+
+ super_hydra_mux_mdio(priv->mask, priv->val);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct super_hydra_mdio *priv = bus->priv;
+
+ super_hydra_mux_mdio(priv->mask, priv->val);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int super_hydra_mdio_reset(struct mii_dev *bus)
+{
+ struct super_hydra_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val)
+{
+ struct mii_dev *bus = miiphy_get_dev_by_name(name);
+ struct super_hydra_mdio *priv = bus->priv;
+
+ priv->mask = mask;
+ priv->val = val;
+}
+
+static int super_hydra_mdio_init(char *realbusname, char *fakebusname)
+{
+ struct super_hydra_mdio *hmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate Hydra MDIO bus\n");
+ return -1;
+ }
+
+ hmdio = malloc(sizeof(*hmdio));
+ if (!hmdio) {
+ printf("Failed to allocate Hydra private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = super_hydra_mdio_read;
+ bus->write = super_hydra_mdio_write;
+ bus->reset = super_hydra_mdio_reset;
+ sprintf(bus->name, fakebusname);
+
+ hmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!hmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(hmdio);
+ return -1;
+ }
+
+ bus->priv = hmdio;
+
+ return mdio_register(bus);
+}
+
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) An Fman port
+ *
+ * ... update the phy-handle property of the Ethernet node to point to the
+ * right PHY. This assumes that we already know the PHY for each port. That
+ * information is stored in mdio_mux[].
+ *
+ * The offset of the Fman Ethernet node is also passed in for convenience, but
+ * it is not used.
+ *
+ * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
+ * Inside the Fman, "ports" are things that connect to MACs. We only call them
+ * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
+ * and ports are the same thing.
+ */
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ enum srds_prtcl device;
+ int lane, slot, phy;
+ char alias[32];
+
+ /* RGMII and XGMII are already mapped correctly in the DTS */
+
+ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ device = serdes_device_from_fm_port(port);
+ lane = serdes_get_first_lane(device);
+ slot = lane_to_slot[lane];
+ phy = fm_info_get_phy_address(port);
+
+ sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ }
+}
+
+#define PIXIS_SW2_LANE_23_SEL 0x80
+#define PIXIS_SW2_LANE_45_SEL 0x40
+#define PIXIS_SW2_LANE_67_SEL_MASK 0x30
+#define PIXIS_SW2_LANE_67_SEL_5 0x00
+#define PIXIS_SW2_LANE_67_SEL_6 0x20
+#define PIXIS_SW2_LANE_67_SEL_7 0x10
+#define PIXIS_SW2_LANE_8_SEL 0x08
+#define PIXIS_SW2_LANE_1617_SEL 0x04
+#define PIXIS_SW11_LANE_9_SEL 0x04
+/*
+ * Initialize the lane_to_slot[] array.
+ *
+ * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
+ * slots is hard-coded. On the Hydra board, however, the mapping is controlled
+ * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
+ * initialized.
+ */
+static void initialize_lane_to_slot(void)
+{
+ u8 sw2 = in_8(&PIXIS_SW(2));
+ /* SW11 appears in the programming model as SW9 */
+ u8 sw11 = in_8(&PIXIS_SW(9));
+
+ lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
+ lane_to_slot[3] = lane_to_slot[2];
+
+ lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
+ lane_to_slot[5] = lane_to_slot[4];
+
+ switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
+ case PIXIS_SW2_LANE_67_SEL_5:
+ lane_to_slot[6] = 5;
+ break;
+ case PIXIS_SW2_LANE_67_SEL_6:
+ lane_to_slot[6] = 6;
+ break;
+ case PIXIS_SW2_LANE_67_SEL_7:
+ lane_to_slot[6] = 7;
+ break;
+ }
+ lane_to_slot[7] = lane_to_slot[6];
+
+ lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
+ lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3;
+
+ lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
+ lane_to_slot[17] = lane_to_slot[16];
+}
+
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+/*
+ * Configure the status for the virtual MDIO nodes
+ *
+ * Rather than create the virtual MDIO nodes from scratch for each active
+ * virtual MDIO, we expect the DTS to have the nodes defined already, and we
+ * only enable the ones that are actually active.
+ *
+ * We assume that the DTS already hard-codes the status for all the
+ * virtual MDIO nodes to "disabled", so all we need to do is enable the
+ * active ones.
+ */
+void fdt_fixup_board_enet(void *fdt)
+{
+#ifdef CONFIG_FMAN_ENET
+ enum fm_port i;
+ int lane, slot;
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+ if (lane >= 0) {
+ char alias[32];
+
+ slot = lane_to_slot[lane];
+ sprintf(alias, "hydra_sg_slot%u", slot);
+ fdt_status_okay_by_alias(fdt, alias);
+ debug("Enabled MDIO node %s (slot %i)\n",
+ alias, slot);
+ }
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ fdt_status_okay_by_alias(fdt, "hydra_rg");
+ debug("Enabled MDIO node hydra_rg\n");
+ break;
+ default:
+ break;
+ }
+ }
+
+ lane = serdes_get_first_lane(XAUI_FM1);
+ if (lane >= 0) {
+ char alias[32];
+
+ slot = lane_to_slot[lane];
+ sprintf(alias, "hydra_xg_slot%u", slot);
+ fdt_status_okay_by_alias(fdt, alias);
+ debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
+ }
+
+#if CONFIG_SYS_NUM_FMAN == 2
+ for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+ int idx = i - FM2_DTSEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
+ if (lane >= 0) {
+ char alias[32];
+
+ slot = lane_to_slot[lane];
+ sprintf(alias, "hydra_sg_slot%u", slot);
+ fdt_status_okay_by_alias(fdt, alias);
+ debug("Enabled MDIO node %s (slot %i)\n",
+ alias, slot);
+ }
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ fdt_status_okay_by_alias(fdt, "hydra_rg");
+ debug("Enabled MDIO node hydra_rg\n");
+ break;
+ default:
+ break;
+ }
+ }
+
+ lane = serdes_get_first_lane(XAUI_FM2);
+ if (lane >= 0) {
+ char alias[32];
+
+ slot = lane_to_slot[lane];
+ sprintf(alias, "hydra_xg_slot%u", slot);
+ fdt_status_okay_by_alias(fdt, alias);
+ debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
+ }
+#endif /* CONFIG_SYS_NUM_FMAN == 2 */
+#endif /* CONFIG_FMAN_ENET */
+}
+
+/*
+ * Mapping of SerDes Protocol to MDIO MUX value and PHY address.
+ *
+ * Fman 1:
+ * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
+ * Mux Phy | Mux Phy | Mux Phy | Mux Phy
+ * Value Addr | Value Addr | Value Addr | Value Addr
+ * 0x00 2 1c | 2 1d | 2 1e | 2 1f
+ * 0x01 | | 6 1c |
+ * 0x02 | | 3 1c | 3 1d
+ * 0x03 2 1c | 2 1d | 2 1e | 2 1f
+ * 0x04 2 1c | 2 1d | 2 1e | 2 1f
+ * 0x05 | | 3 1c | 3 1d
+ * 0x06 2 1c | 2 1d | 2 1e | 2 1f
+ * 0x07 | | 6 1c |
+ * 0x11 2 1c | 2 1d | 2 1e | 2 1f
+ * 0x2a 2 | | 2 1e | 2 1f
+ * 0x34 6 1c | 6 1d | 4 1e | 4 1f
+ * 0x35 | | 3 1c | 3 1d
+ * 0x36 6 1c | 6 1d | 4 1e | 4 1f
+ * | | |
+ * Fman 2: | | |
+ * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
+ * EMI1 | EMI1 | EMI1 | EMI1
+ * Mux Phy | Mux Phy | Mux Phy | Mux Phy
+ * Value Addr | Value Addr | Value Addr | Value Addr
+ * 0x00 | | 6 1c | 6 1d
+ * 0x01 | | |
+ * 0x02 | | 6 1c | 6 1d
+ * 0x03 3 1c | 3 1d | 6 1c | 6 1d
+ * 0x04 3 1c | 3 1d | 6 1c | 6 1d
+ * 0x05 | | 6 1c | 6 1d
+ * 0x06 | | 6 1c | 6 1d
+ * 0x07 | | |
+ * 0x11 | | |
+ * 0x2a | | |
+ * 0x34 | | |
+ * 0x35 | | |
+ * 0x36 | | |
+ */
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct fsl_pq_mdio_info dtsec_mdio_info;
+ struct tgec_mdio_info tgec_mdio_info;
+ unsigned int i, slot;
+ int lane;
+ struct mii_dev *bus;
+ int qsgmii;
+ int phy_real_addr;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+ printf("Initializing Fman\n");
+
+ initialize_lane_to_slot();
+
+ /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
+ setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
+
+ memset(mdio_mux, 0, sizeof(mdio_mux));
+
+ dtsec_mdio_info.regs =
+ (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the real 1G MDIO bus */
+ fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the real 10G MDIO bus */
+ fm_tgec_mdio_init(bis, &tgec_mdio_info);
+
+ /* Register the three virtual MDIO front-ends */
+ super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
+ "SUPER_HYDRA_RGMII_MDIO");
+ super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
+ "SUPER_HYDRA_FM1_SGMII_MDIO");
+ super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
+ "SUPER_HYDRA_FM2_SGMII_MDIO");
+ super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
+ "SUPER_HYDRA_FM3_SGMII_MDIO");
+ super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
+ "SUPER_HYDRA_FM1_TGEC_MDIO");
+ super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
+ "SUPER_HYDRA_FM2_TGEC_MDIO");
+
+ /*
+ * Program the DTSEC PHY addresses assuming that they are all SGMII.
+ * For any DTSEC that's RGMII, we'll override its PHY address later.
+ * We assume that DTSEC5 is only used for RGMII.
+ */
+ fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+#endif
+
+ switch (srds_prtcl) {
+ case 0:
+ case 3:
+ case 4:
+ case 6:
+ case 0x11:
+ case 0x2a:
+ case 0x34:
+ case 0x36:
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4,
+ CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+ break;
+ case 1:
+ case 2:
+ case 5:
+ case 7:
+ case 0x35:
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4,
+ CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+ break;
+ default:
+ printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl);
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot[lane];
+ mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
+ debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ switch (slot) {
+ case 1:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 2:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 3:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 5:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 6:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 7:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
+ BRDCFG1_EMI1_EN;
+ break;
+ };
+
+ super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO",
+ mdio_mux[i].mask, mdio_mux[i].val);
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ /*
+ * FM1 DTSEC5 is routed via EC1 to the first on-board
+ * RGMII port. FM2 DTSEC5 is routed via EC2 to the
+ * second on-board RGMII port. The other DTSECs cannot
+ * be routed to RGMII.
+ */
+ debug("FM1@DTSEC%u is RGMII at address %u\n",
+ idx + 1, 0);
+ fm_info_set_phy_address(i, 0);
+ mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
+ BRDCFG1_EMI1_EN;
+ super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
+ mdio_mux[i].mask, mdio_mux[i].val);
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
+ break;
+ default:
+ printf("Fman1: DTSEC%u set to unknown interface %i\n",
+ idx + 1, fm_info_get_enet_if(i));
+ fm_info_set_phy_address(i, 0);
+ break;
+ }
+ }
+
+ bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO");
+ qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM);
+
+ if (qsgmii) {
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) {
+ if (fm_info_get_enet_if(i) ==
+ PHY_INTERFACE_MODE_SGMII) {
+ phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1;
+ fm_info_set_phy_address(i, phy_real_addr);
+ }
+ }
+ switch (srds_prtcl) {
+ case 0x00:
+ case 0x03:
+ case 0x04:
+ case 0x06:
+ case 0x11:
+ case 0x2a:
+ case 0x34:
+ case 0x36:
+ fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2);
+ fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3);
+ break;
+ case 0x01:
+ case 0x02:
+ case 0x05:
+ case 0x07:
+ case 0x35:
+ fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0);
+ fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
+ break;
+ default:
+ break;
+ }
+ }
+
+ /*
+ * For 10G, we only support one XAUI card per Fman. If present, then we
+ * force its routing and never touch those bits again, which removes the
+ * need for Linux to do any muxing. This works because of the way
+ * BRDCFG1 is defined, but it's a bit hackish.
+ *
+ * The PHY address for the XAUI card depends on which slot it's in. The
+ * macros we use imply that the PHY address is based on which FM, but
+ * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
+ * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
+ * check the actual slot and just use the macros as-is, even though
+ * the P3041 and P5020 only have one Fman.
+ */
+ lane = serdes_get_first_lane(XAUI_FM1);
+ if (lane >= 0) {
+ debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
+ mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
+ mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2;
+ super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO",
+ mdio_mux[i].mask, mdio_mux[i].val);
+ }
+
+ fm_info_set_mdio(FM1_10GEC1,
+ miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO"));
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+ int idx = i - FM2_DTSEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot[lane];
+ mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
+ debug("FM2@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ switch (slot) {
+ case 1:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 2:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 3:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 5:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 6:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
+ BRDCFG1_EMI1_EN;
+ break;
+ case 7:
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
+ BRDCFG1_EMI1_EN;
+ break;
+ };
+
+ if (i == FM2_DTSEC1 || i == FM2_DTSEC2) {
+ super_hydra_mdio_set_mux(
+ "SUPER_HYDRA_FM3_SGMII_MDIO",
+ mdio_mux[i].mask,
+ mdio_mux[i].val);
+ fm_info_set_mdio(i, miiphy_get_dev_by_name(
+ "SUPER_HYDRA_FM3_SGMII_MDIO"));
+ } else {
+ super_hydra_mdio_set_mux(
+ "SUPER_HYDRA_FM2_SGMII_MDIO",
+ mdio_mux[i].mask,
+ mdio_mux[i].val);
+ fm_info_set_mdio(i, miiphy_get_dev_by_name(
+ "SUPER_HYDRA_FM2_SGMII_MDIO"));
+ }
+
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ /*
+ * FM1 DTSEC5 is routed via EC1 to the first on-board
+ * RGMII port. FM2 DTSEC5 is routed via EC2 to the
+ * second on-board RGMII port. The other DTSECs cannot
+ * be routed to RGMII.
+ */
+ debug("FM2@DTSEC%u is RGMII at address %u\n",
+ idx + 1, 1);
+ fm_info_set_phy_address(i, 1);
+ mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
+ mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
+ BRDCFG1_EMI1_EN;
+ super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
+ mdio_mux[i].mask, mdio_mux[i].val);
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
+ break;
+ default:
+ printf("Fman2: DTSEC%u set to unknown interface %i\n",
+ idx + 1, fm_info_get_enet_if(i));
+ fm_info_set_phy_address(i, 0);
+ break;
+ }
+ }
+
+ bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO");
+ set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR);
+ bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO");
+ set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR);
+
+ /*
+ * For 10G, we only support one XAUI card per Fman. If present, then we
+ * force its routing and never touch those bits again, which removes the
+ * need for Linux to do any muxing. This works because of the way
+ * BRDCFG1 is defined, but it's a bit hackish.
+ *
+ * The PHY address for the XAUI card depends on which slot it's in. The
+ * macros we use imply that the PHY address is based on which FM, but
+ * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
+ * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
+ * check the actual slot and just use the macros as-is, even though
+ * the P3041 and P5020 only have one Fman.
+ */
+ lane = serdes_get_first_lane(XAUI_FM2);
+ if (lane >= 0) {
+ debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
+ mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
+ mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1;
+ super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO",
+ mdio_mux[i].mask, mdio_mux[i].val);
+ }
+
+ fm_info_set_mdio(FM2_10GEC1,
+ miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO"));
+
+#endif
+
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c
new file mode 100644
index 0000000..4dead9c
--- /dev/null
+++ b/board/freescale/corenet_ds/p3041ds_ddr.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+ {0, 0, NULL}
+};
diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c
new file mode 100644
index 0000000..d572a5f
--- /dev/null
+++ b/board/freescale/corenet_ds/p4080ds_ddr.c
@@ -0,0 +1,350 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
+#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
+#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
+#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
+#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
+#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
+#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
+#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
+#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
+#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
+#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
+#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
+#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
+#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
+#define CONFIG_SYS_DDR_MODE_1_900 0x00441620
+#define CONFIG_SYS_DDR_MODE_2_900 0x00080000
+#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
+#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
+
+#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
+#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
+#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
+#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
+#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
+#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
+#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
+#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
+#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
+#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
+#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
+#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
+#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
+#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
+#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
+#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
+#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
+#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
+#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
+#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
+#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
+#define CONFIG_SYS_DDR_TIMING_4 0x00000001
+#define CONFIG_SYS_DDR_TIMING_5 0x02401400
+#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
+#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
+#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
+#define CONFIG_SYS_DDR_RCW_1 0x00000000
+#define CONFIG_SYS_DDR_RCW_2 0x00000000
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800_2nd = {
+ .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_900_2nd = {
+ .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1000_2nd = {
+ .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
+ .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
+ .cs[1].bnds = CONFIG_SYS_DDR2_CS1_BNDS,
+ .cs[2].bnds = CONFIG_SYS_DDR2_CS2_BNDS,
+ .cs[3].bnds = CONFIG_SYS_DDR2_CS3_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR2_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .cs[1].config = CONFIG_SYS_DDR2_CS1_CONFIG,
+ .cs[2].config = CONFIG_SYS_DDR2_CS2_CONFIG,
+ .cs[3].config = CONFIG_SYS_DDR2_CS3_CONFIG,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+ {750, 850, &ddr_cfg_regs_800},
+ {850, 950, &ddr_cfg_regs_900},
+ {950, 1050, &ddr_cfg_regs_1000},
+ {1050, 1250, &ddr_cfg_regs_1200},
+ {0, 0, NULL}
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_1[] = {
+ {750, 850, &ddr_cfg_regs_800_2nd},
+ {850, 950, &ddr_cfg_regs_900_2nd},
+ {950, 1050, &ddr_cfg_regs_1000_2nd},
+ {1050, 1250, &ddr_cfg_regs_1200_2nd},
+ {0, 0, NULL}
+};
diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c
new file mode 100644
index 0000000..9aaf6db
--- /dev/null
+++ b/board/freescale/corenet_ds/p5020ds_ddr.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+ {0, 0, NULL}
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_1[] = {
+ {0, 0, NULL}
+};
diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c
new file mode 100644
index 0000000..9aaf6db
--- /dev/null
+++ b/board/freescale/corenet_ds/p5040ds_ddr.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+ {0, 0, NULL}
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_1[] = {
+ {0, 0, NULL}
+};
diff --git a/board/freescale/corenet_ds/pbi.cfg b/board/freescale/corenet_ds/pbi.cfg
new file mode 100644
index 0000000..1a2e098
--- /dev/null
+++ b/board/freescale/corenet_ds/pbi.cfg
@@ -0,0 +1,35 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1 as 1MB SRAM
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+09010100 00000000
+09010104 fff0000b
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff00000
+09000d08 81000013
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/corenet_ds/rcw_p2041rdb.cfg b/board/freescale/corenet_ds/rcw_p2041rdb.cfg
new file mode 100644
index 0000000..8df19dd
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p2041rdb.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P2041RDB.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+12600000 00000000 241C0000 00000000
+649FA0C1 C3C02000 58000000 40000000
+00000000 00000000 00000000 D0030F07
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/corenet_ds/rcw_p3041ds.cfg b/board/freescale/corenet_ds/rcw_p3041ds.cfg
new file mode 100644
index 0000000..8813156
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p3041ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P3041DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+12600000 00000000 241C0000 00000000
+D8984A01 03002000 58000000 41000000
+00000000 00000000 00000000 10070000
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/corenet_ds/rcw_p4080ds.cfg b/board/freescale/corenet_ds/rcw_p4080ds.cfg
new file mode 100644
index 0000000..6a26339
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p4080ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P4080DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+105a0000 00000000 1e1e181e 0000cccc
+58400000 3c3c2000 58000000 e1000000
+00000000 00000000 00000000 008b6000
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/corenet_ds/rcw_p5020ds.cfg b/board/freescale/corenet_ds/rcw_p5020ds.cfg
new file mode 100644
index 0000000..b09e409
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p5020ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P5020DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+0C540000 00000000 1E120000 00000000
+D8984A01 03002000 58000000 41000000
+00000000 00000000 00000000 10070000
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/corenet_ds/rcw_p5040ds.cfg b/board/freescale/corenet_ds/rcw_p5040ds.cfg
new file mode 100644
index 0000000..82fa741
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p5040ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P5040DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+0c580000 00000000 22121200 00000000
+089c4400 00283000 58000000 61000000
+00000000 00000000 00000000 10070000
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig
new file mode 100644
index 0000000..119b955
--- /dev/null
+++ b/board/freescale/ls1021aqds/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1021AQDS
+
+config SYS_BOARD
+ default "ls1021aqds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "ls102xa"
+
+config SYS_CONFIG_NAME
+ default "ls1021aqds"
+
+endif
diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS
new file mode 100644
index 0000000..638833d
--- /dev/null
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -0,0 +1,11 @@
+LS1021AQDS BOARD
+M: Alison Wang <alison.wang@freescale.com>
+S: Maintained
+F: board/freescale/ls1021aqds/
+F: include/configs/ls1021aqds.h
+F: configs/ls1021aqds_nor_defconfig
+F: configs/ls1021aqds_ddr4_nor_defconfig
+F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+F: configs/ls1021aqds_sdcard_defconfig
+F: configs/ls1021aqds_qspi_defconfig
+F: configs/ls1021aqds_nand_defconfig
diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile
new file mode 100644
index 0000000..3b6903c
--- /dev/null
+++ b/board/freescale/ls1021aqds/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1021aqds.o
+obj-y += ddr.o
+obj-y += eth.o
diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README
new file mode 100644
index 0000000..c561776
--- /dev/null
+++ b/board/freescale/ls1021aqds/README
@@ -0,0 +1,112 @@
+Overview
+--------
+The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC.
+
+LS1021A SoC Overview
+------------------
+The QorIQ LS1 family, which includes the LS1021A communications processor,
+is built on Layerscape architecture, the industry's first software-aware,
+core-agnostic networking architecture to offer unprecedented efficiency
+and scale.
+
+A member of the value-performance tier, the QorIQ LS1021A processor provides
+extensive integration and power efficiency for fanless, small form factor
+enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
+running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
+performance of over 6,000, as well as virtualization support, advanced
+security features and the broadest array of high-speed interconnects and
+optimized peripheral features ever offered in a sub-3 W processor.
+
+The QorIQ LS1021A processor features an integrated LCD controller,
+CAN controller for implementing industrial protocols, DDR3L/4 running
+up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
+protection on both L1 and L2 caches. The LS1021A processor is pin- and
+software-compatible with the QorIQ LS1020A and LS1022A processors.
+
+The LS1021A SoC includes the following function and features:
+
+ - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
+ - Dual high-preformance ARM Cortex-A7 cores, each core includes:
+ - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)
+ - 512 Kbyte shared coherent L2 Cache (with ECC protection)
+ - NEON Co-processor (per core)
+ - 40-bit physical addressing
+ - Vector floating-point support
+ - ARM Core-Link CCI-400 Cache Coherent Interconnect
+ - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
+ supporting speeds up to 1600Mtps
+ - ECC and interleaving support
+ - VeTSEC Ethernet complex
+ - Up to 3x virtualized 10/100/1000 Ethernet controllers
+ - MII, RMII, RGMII, and SGMII support
+ - QoS, lossless flow control, and IEEE 1588 support
+ - 4-lane 6GHz SerDes
+ - High speed interconnect (4 SerDes lanes with are muxed for these protocol)
+ - Two PCI Express Gen2 controllers running at up to 5 GHz
+ - One Serial ATA 3.0 supporting 6 GT/s operation
+ - Two SGMII interfaces supporting 1000 Mbps
+ - Additional peripheral interfaces
+ - One high-speed USB 3.0 controller with integrated PHY and one high-speed
+ USB 2.00 controller with ULPI
+ - Integrated flash controller (IFC) with 16-bit interface
+ - Quad SPI NOR Flash
+ - One enhanced Secure digital host controller
+ - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface)
+ - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power
+ UARTs
+ - Three I2C controllers
+ - Eight FlexTimers four supporting PWM and four FlexCAN ports
+ - Four GPIO controllers supporting up to 109 general purpose I/O signals
+ - Integrated advanced audio block:
+ - Four synchronous audio interfaces (SAI)
+ - Sony/Philips Digital Interconnect Format (SPDIF)
+ - Asynchronous Sample Rate Converter (ASRC)
+ - Hardware based crypto offload engine
+ - IPSec forwarding at up to 1Gbps
+ - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported
+ - Public key hardware accelerator
+ - True Random Number Generator (NIST Certified)
+ - Advanced Encryption Standard Accelerators (AESA)
+ - Data Encryption Standard Accelerators
+ - QUICC Engine ULite block
+ - Two universal communication controllers (TDM and HDLC) supporting 64
+ multichannels, each running at 64 Kbps
+ - Support for 256 channels of HDLC
+ - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported
+
+LS1021AQDS board Overview
+-------------------------
+ - DDR Controller
+ - Supports rates of up to 1600 MHz data-rate
+ - Supports one DDR3LP UDIMM, of single-, dual- types.
+ - IFC/Local Bus
+ - NAND flash: 512M 8-bit NAND flash
+ - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+ - Three on-board RGMII 10/100/1G ethernet ports.
+ - FPGA
+ - Clocks
+ - System and DDR clock (SYSCLK, DDRCLK)
+ - SERDES clocks
+ - Power Supplies
+ - SDHC
+ - SDHC/SDXC connector
+ - Other IO
+ - Two Serial ports
+ - Three I2C ports
+
+Memory map
+-----------
+The addresses in brackets are physical addresses.
+
+Start Address End Address Description Size
+0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
+0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
+0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
+0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
+0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB
+0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
+0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
+0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
+0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
new file mode 100644
index 0000000..a539ff9
--- /dev/null
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 3) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->cpo_override = pbsp->cpo_override;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for %lu MT/s\n",
+ ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+
+ /* force DDR bus width to 32 bits */
+ popts->data_bus_width = 1;
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+#else
+ popts->cswl_override = DDR_CSWL_CS0;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+}
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 1073741824u,
+ .capacity = 1073741824u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1071,
+ .caslat_x = 0xfe << 4, /* 5,6,7,8 */
+ .taa_ps = 13125,
+ .twr_ps = 15000,
+ .trcd_ps = 13125,
+ .trrd_ps = 7500,
+ .trp_ps = 13125,
+ .tras_ps = 37500,
+ .trc_ps = 50625,
+ .trfc_ps = 160000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ static const char dimm_model[] = "Fixed DDR on board";
+
+ if (((controller_number == 0) && (dimm_number == 0)) ||
+ ((controller_number == 1) && (dimm_number == 0))) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+#endif
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
+ puts("Initializing DDR....using SPD\n");
+ dram_size = fsl_ddr_sdram();
+#else
+ dram_size = fsl_ddr_sdram_size();
+#endif
+ return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h
new file mode 100644
index 0000000..f819c99
--- /dev/null
+++ b/board/freescale/ls1021aqds/ddr.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo_override;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+#ifdef CONFIG_SYS_FSL_DDR4
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,},
+ {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
+ {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
+ {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
+ {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
+ {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+ {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
+#else
+#error DDR type not defined
+#endif
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+#endif
diff --git a/board/freescale/ls1021aqds/eth.c b/board/freescale/ls1021aqds/eth.c
new file mode 100644
index 0000000..be351be
--- /dev/null
+++ b/board/freescale/ls1021aqds/eth.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file handles the board muxing between the RGMII/SGMII PHYs on
+ * Freescale LS1021AQDS board. The RGMII PHYs are the three on-board 1Gb
+ * ports. The SGMII PHYs are provided by the standard Freescale four-port
+ * SGMII riser card.
+ *
+ * Muxing is handled via the PIXIS BRDCFG4 register. The EMI1 bits control
+ * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII depends
+ * on which port is used. The value for SGMII depends on which slot the riser
+ * is inserted in.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <malloc.h>
+
+#include "../common/sgmii_riser.h"
+#include "../common/qixis.h"
+
+#define EMI1_MASK 0x1f
+#define EMI1_RGMII0 1
+#define EMI1_RGMII1 2
+#define EMI1_RGMII2 3
+#define EMI1_SGMII1 0x1c
+#define EMI1_SGMII2 0x1d
+
+struct ls1021a_mdio {
+ struct mii_dev *realbus;
+};
+
+static void ls1021a_mux_mdio(int addr)
+{
+ u8 brdcfg4;
+
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= EMI1_MASK;
+
+ switch (addr) {
+ case EMI1_RGMII0:
+ brdcfg4 |= 0;
+ break;
+ case EMI1_RGMII1:
+ brdcfg4 |= 0x20;
+ break;
+ case EMI1_RGMII2:
+ brdcfg4 |= 0x40;
+ break;
+ case EMI1_SGMII1:
+ brdcfg4 |= 0x60;
+ break;
+ case EMI1_SGMII2:
+ brdcfg4 |= 0x80;
+ break;
+ default:
+ brdcfg4 |= 0xa0;
+ break;
+ }
+
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+}
+
+static int ls1021a_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct ls1021a_mdio *priv = bus->priv;
+
+ ls1021a_mux_mdio(addr);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1021a_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct ls1021a_mdio *priv = bus->priv;
+
+ ls1021a_mux_mdio(addr);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls1021a_mdio_reset(struct mii_dev *bus)
+{
+ struct ls1021a_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int ls1021a_mdio_init(char *realbusname, char *fakebusname)
+{
+ struct ls1021a_mdio *lsmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate LS102xA MDIO bus\n");
+ return -1;
+ }
+
+ lsmdio = malloc(sizeof(*lsmdio));
+ if (!lsmdio) {
+ printf("Failed to allocate LS102xA private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = ls1021a_mdio_read;
+ bus->write = ls1021a_mdio_write;
+ bus->reset = ls1021a_mdio_reset;
+ sprintf(bus->name, fakebusname);
+
+ lsmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!lsmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(lsmdio);
+ return -1;
+ }
+
+ bus->priv = lsmdio;
+
+ return mdio_register(bus);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[3];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ if (is_serdes_configured(SGMII_TSEC1)) {
+ puts("eTSEC1 is in sgmii mode\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO";
+ } else {
+ tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO";
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ if (is_serdes_configured(SGMII_TSEC2)) {
+ puts("eTSEC2 is in sgmii mode\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO";
+ } else {
+ tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO";
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO";
+ num++;
+#endif
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_init(tsec_info, num);
+#endif
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ /* Register the virtual MDIO front-ends */
+ ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_RGMII_MDIO");
+ ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_SGMII_MDIO");
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
new file mode 100644
index 0000000..f08e54f
--- /dev/null
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -0,0 +1,534 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ns_access.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/pcie_layerscape.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include <fsl_sec.h>
+#include <spl.h>
+
+#include "../common/qixis.h"
+#include "ls1021aqds_qixis.h"
+#ifdef CONFIG_U_QE
+#include "../../../drivers/qe/qe.h"
+#endif
+
+#define PIN_MUX_SEL_CAN 0x03
+#define PIN_MUX_SEL_IIC2 0xa0
+#define PIN_MUX_SEL_RGMII 0x00
+#define PIN_MUX_SEL_SAI 0x0c
+#define PIN_MUX_SEL_SDHC 0x00
+
+#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
+#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ MUX_TYPE_CAN,
+ MUX_TYPE_IIC2,
+ MUX_TYPE_RGMII,
+ MUX_TYPE_SAI,
+ MUX_TYPE_SDHC,
+ MUX_TYPE_SD_PCI4,
+ MUX_TYPE_SD_PC_SA_SG_SG,
+ MUX_TYPE_SD_PC_SA_PC_SG,
+ MUX_TYPE_SD_PC_SG_SG,
+};
+
+int checkboard(void)
+{
+#ifndef CONFIG_QSPI_BOOT
+ char buf[64];
+#endif
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
+ u8 sw;
+#endif
+
+ puts("Board: LS1021AQDS\n");
+
+#ifdef CONFIG_SD_BOOT
+ puts("SD\n");
+#elif CONFIG_QSPI_BOOT
+ puts("QSPI\n");
+#else
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw == 0x8)
+ puts("PromJet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else if (sw == 0x15)
+ printf("IFCCard\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+#ifndef CONFIG_QSPI_BOOT
+ printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
+ QIXIS_READ(id), QIXIS_READ(arch));
+
+ printf("FPGA: v%d (%s), build %d\n",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+#endif
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0f) {
+ case QIXIS_SYSCLK_64:
+ return 64000000;
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /*
+ * When resuming from deep sleep, the I2C channel may not be
+ * in the default channel. So, switch to the default channel
+ * before accessing DDR SPD.
+ */
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ gd->ram_size = initdram(0);
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+ {CONFIG_SYS_FSL_ESDHC_ADDR},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+#ifdef CONFIG_TSEC_ENET
+ out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+#endif
+
+#ifdef CONFIG_FSL_IFC
+ init_early_memctl_regs();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+ out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
+ /* Workaround for the issue that DDR could not respond to
+ * barrier transaction which is generated by executing DSB/ISB
+ * instruction. Set CCI-400 control override register to
+ * terminate the barrier transaction. After DDR is initialized,
+ * allow barrier transaction to DDR again */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+#ifdef CONFIG_NAND_BOOT
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 porsr1, pinctl;
+
+ /*
+ * There is LS1 SoC issue where NOR, FPGA are inaccessible during
+ * NAND boot because IFC signals > IFC_AD7 are not enabled.
+ * This workaround changes RCW source to make all signals enabled.
+ */
+ porsr1 = in_be32(&gur->porsr1);
+ pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
+ DCFG_CCSR_PORSR1_RCW_SRC_I2C);
+ out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+ pinctl);
+#endif
+
+ /* Set global data pointer */
+ gd = &gdata;
+
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_FSL_IFC
+ init_early_memctl_regs();
+#endif
+
+ get_clocks();
+
+ preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+ i2c_init_all();
+#endif
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+ dram_init();
+
+ board_init_r(NULL, 0);
+}
+#endif
+
+int config_board_mux(int ctrl_type)
+{
+ u8 reg12, reg14;
+
+ reg12 = QIXIS_READ(brdcfg[12]);
+ reg14 = QIXIS_READ(brdcfg[14]);
+
+ switch (ctrl_type) {
+ case MUX_TYPE_CAN:
+ reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
+ break;
+ case MUX_TYPE_IIC2:
+ reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
+ break;
+ case MUX_TYPE_RGMII:
+ reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
+ break;
+ case MUX_TYPE_SAI:
+ reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
+ break;
+ case MUX_TYPE_SDHC:
+ reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
+ break;
+ case MUX_TYPE_SD_PCI4:
+ reg12 = 0x38;
+ break;
+ case MUX_TYPE_SD_PC_SA_SG_SG:
+ reg12 = 0x01;
+ break;
+ case MUX_TYPE_SD_PC_SA_PC_SG:
+ reg12 = 0x01;
+ break;
+ case MUX_TYPE_SD_PC_SG_SG:
+ reg12 = 0x21;
+ break;
+ default:
+ printf("Wrong mux interface type\n");
+ return -1;
+ }
+
+ QIXIS_WRITE(brdcfg[12], reg12);
+ QIXIS_WRITE(brdcfg[14], reg14);
+
+ return 0;
+}
+
+int config_serdes_mux(void)
+{
+ struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 cfg;
+
+ cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
+ cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ switch (cfg) {
+ case 0x0:
+ config_board_mux(MUX_TYPE_SD_PCI4);
+ break;
+ case 0x30:
+ config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
+ break;
+ case 0x60:
+ config_board_mux(MUX_TYPE_SD_PC_SG_SG);
+ break;
+ case 0x70:
+ config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
+ break;
+ default:
+ printf("SRDS1 prtcl:0x%x\n", cfg);
+ break;
+ }
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ int conflict_flag;
+
+ /* some signals can not enable simultaneous*/
+ conflict_flag = 0;
+ if (hwconfig("sdhc"))
+ conflict_flag++;
+ if (hwconfig("iic2"))
+ conflict_flag++;
+ if (conflict_flag > 1) {
+ printf("WARNING: pin conflict !\n");
+ return 0;
+ }
+
+ conflict_flag = 0;
+ if (hwconfig("rgmii"))
+ conflict_flag++;
+ if (hwconfig("can"))
+ conflict_flag++;
+ if (hwconfig("sai"))
+ conflict_flag++;
+ if (conflict_flag > 1) {
+ printf("WARNING: pin conflict !\n");
+ return 0;
+ }
+
+ if (hwconfig("can"))
+ config_board_mux(MUX_TYPE_CAN);
+ else if (hwconfig("rgmii"))
+ config_board_mux(MUX_TYPE_RGMII);
+ else if (hwconfig("sai"))
+ config_board_mux(MUX_TYPE_SAI);
+
+ if (hwconfig("iic2"))
+ config_board_mux(MUX_TYPE_IIC2);
+ else if (hwconfig("sdhc"))
+ config_board_mux(MUX_TYPE_SDHC);
+
+#ifdef CONFIG_FSL_CAAM
+ return sec_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+static struct csu_ns_dev ns_dev[] = {
+ { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+ { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+ { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM, CSU_ALL_RW },
+ { CSU_CSLX_GIC, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+ { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+ { CSU_CSLX_PCIE2, CSU_ALL_RW },
+ { CSU_CSLX_SATA, CSU_ALL_RW },
+ { CSU_CSLX_USB3, CSU_ALL_RW },
+ { CSU_CSLX_SERDES, CSU_ALL_RW },
+ { CSU_CSLX_QDMA, CSU_ALL_RW },
+ { CSU_CSLX_LPUART2, CSU_ALL_RW },
+ { CSU_CSLX_LPUART1, CSU_ALL_RW },
+ { CSU_CSLX_LPUART4, CSU_ALL_RW },
+ { CSU_CSLX_LPUART3, CSU_ALL_RW },
+ { CSU_CSLX_LPUART6, CSU_ALL_RW },
+ { CSU_CSLX_LPUART5, CSU_ALL_RW },
+ { CSU_CSLX_DSPI2, CSU_ALL_RW },
+ { CSU_CSLX_DSPI1, CSU_ALL_RW },
+ { CSU_CSLX_QSPI, CSU_ALL_RW },
+ { CSU_CSLX_ESDHC, CSU_ALL_RW },
+ { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+ { CSU_CSLX_IFC, CSU_ALL_RW },
+ { CSU_CSLX_I2C1, CSU_ALL_RW },
+ { CSU_CSLX_USB2, CSU_ALL_RW },
+ { CSU_CSLX_I2C3, CSU_ALL_RW },
+ { CSU_CSLX_I2C2, CSU_ALL_RW },
+ { CSU_CSLX_DUART2, CSU_ALL_RW },
+ { CSU_CSLX_DUART1, CSU_ALL_RW },
+ { CSU_CSLX_WDT2, CSU_ALL_RW },
+ { CSU_CSLX_WDT1, CSU_ALL_RW },
+ { CSU_CSLX_EDMA, CSU_ALL_RW },
+ { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+ { CSU_CSLX_DDR, CSU_ALL_RW },
+ { CSU_CSLX_QUICC, CSU_ALL_RW },
+ { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+ { CSU_CSLX_SFP, CSU_ALL_RW },
+ { CSU_CSLX_TMU, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+ { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO1, CSU_ALL_RW },
+ { CSU_CSLX_GPIO4, CSU_ALL_RW },
+ { CSU_CSLX_GPIO3, CSU_ALL_RW },
+ { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+ { CSU_CSLX_CSU, CSU_ALL_RW },
+ { CSU_CSLX_ASRC, CSU_ALL_RW },
+ { CSU_CSLX_SPDIF, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+ { CSU_CSLX_SAI2, CSU_ALL_RW },
+ { CSU_CSLX_SAI1, CSU_ALL_RW },
+ { CSU_CSLX_SAI4, CSU_ALL_RW },
+ { CSU_CSLX_SAI3, CSU_ALL_RW },
+ { CSU_CSLX_FTM2, CSU_ALL_RW },
+ { CSU_CSLX_FTM1, CSU_ALL_RW },
+ { CSU_CSLX_FTM4, CSU_ALL_RW },
+ { CSU_CSLX_FTM3, CSU_ALL_RW },
+ { CSU_CSLX_FTM6, CSU_ALL_RW },
+ { CSU_CSLX_FTM5, CSU_ALL_RW },
+ { CSU_CSLX_FTM8, CSU_ALL_RW },
+ { CSU_CSLX_FTM7, CSU_ALL_RW },
+ { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+ { CSU_CSLX_EPU, CSU_ALL_RW },
+ { CSU_CSLX_GDI, CSU_ALL_RW },
+ { CSU_CSLX_DDI, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+ { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
+#endif
+
+struct smmu_stream_id dev_stream_id[] = {
+ { 0x100, 0x01, "ETSEC MAC1" },
+ { 0x104, 0x02, "ETSEC MAC2" },
+ { 0x108, 0x03, "ETSEC MAC3" },
+ { 0x10c, 0x04, "PEX1" },
+ { 0x110, 0x05, "PEX2" },
+ { 0x114, 0x06, "qDMA" },
+ { 0x118, 0x07, "SATA" },
+ { 0x11c, 0x08, "USB3" },
+ { 0x120, 0x09, "QE" },
+ { 0x124, 0x0a, "eSDHC" },
+ { 0x128, 0x0b, "eMA" },
+ { 0x14c, 0x0c, "2D-ACE" },
+ { 0x150, 0x0d, "USB2" },
+ { 0x18c, 0x0e, "DEBUG" },
+};
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+ /* Set CCI-400 control override register to
+ * enable barrier transaction */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+ /*
+ * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
+ * All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+#ifndef CONFIG_SYS_FSL_NO_SERDES
+ fsl_serdes_init();
+ config_serdes_mux();
+#endif
+
+ ls102xa_config_smmu_stream_id(dev_stream_id,
+ ARRAY_SIZE(dev_stream_id));
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+
+#ifdef CONFIG_U_QE
+ u_qe_init();
+#endif
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCIE_LAYERSCAPE
+ ft_pcie_setup(blob, bd);
+#endif
+
+ return 0;
+}
+
+u8 flash_read8(void *addr)
+{
+ return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+ u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+ __raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+ u16 val = __raw_readw(addr);
+
+ return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
diff --git a/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/board/freescale/ls1021aqds/ls1021aqds_qixis.h
new file mode 100644
index 0000000..09b3be2
--- /dev/null
+++ b/board/freescale/ls1021aqds/ls1021aqds_qixis.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LS1021AQDS_QIXIS_H__
+#define __LS1021AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1021AQDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xe0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+#define QIXIS_SYSCLK_64 0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+#define QIXIS_SRDS1CLK_100 0x0
+
+#endif
diff --git a/board/freescale/ls1021aqds/ls102xa_pbi.cfg b/board/freescale/ls1021aqds/ls102xa_pbi.cfg
new file mode 100644
index 0000000..f1a1b63
--- /dev/null
+++ b/board/freescale/ls1021aqds/ls102xa_pbi.cfg
@@ -0,0 +1,12 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
new file mode 100644
index 0000000..222c71d
--- /dev/null
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0608000a 00000000 00000000 00000000
+60000000 00407900 e0106a00 21046000
+00000000 00000000 00000000 00038000
+00000000 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
new file mode 100644
index 0000000..9d99bd8
--- /dev/null
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
@@ -0,0 +1,14 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+0608000a 00000000 00000000 00000000
+60000000 00407900 60040a00 21046000
+00000000 00000000 00000000 00038000
+00000000 001b7200 00000000 00000000
+
+#disable IFC, enable QSPI and DSPI
+#0608000a 00000000 00000000 00000000
+#60000000 00407900 60040a00 21046000
+#00000000 00000000 00000000 00038000
+#20024800 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig
new file mode 100644
index 0000000..bc50b8d
--- /dev/null
+++ b/board/freescale/ls1021atwr/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1021ATWR
+
+config SYS_BOARD
+ default "ls1021atwr"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "ls102xa"
+
+config SYS_CONFIG_NAME
+ default "ls1021atwr"
+
+endif
diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS
new file mode 100644
index 0000000..9176706
--- /dev/null
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -0,0 +1,9 @@
+LS1021ATWR BOARD
+M: Alison Wang <alison.wang@freescale.com>
+S: Maintained
+F: board/freescale/ls1021atwr/
+F: include/configs/ls1021atwr.h
+F: configs/ls1021atwr_nor_defconfig
+F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+F: configs/ls1021atwr_sdcard_defconfig
+F: configs/ls1021atwr_qspi_defconfig
diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile
new file mode 100644
index 0000000..01296c0
--- /dev/null
+++ b/board/freescale/ls1021atwr/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls1021atwr.o
+obj-$(CONFIG_FSL_DCU_FB) += dcu.o
diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README
new file mode 100644
index 0000000..d2821cb
--- /dev/null
+++ b/board/freescale/ls1021atwr/README
@@ -0,0 +1,109 @@
+Overview
+--------
+The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC.
+
+LS1021A SoC Overview
+------------------
+The QorIQ LS1 family, which includes the LS1021A communications processor,
+is built on Layerscape architecture, the industry's first software-aware,
+core-agnostic networking architecture to offer unprecedented efficiency
+and scale.
+
+A member of the value-performance tier, the QorIQ LS1021A processor provides
+extensive integration and power efficiency for fanless, small form factor
+enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
+running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
+performance of over 6,000, as well as virtualization support, advanced
+security features and the broadest array of high-speed interconnects and
+optimized peripheral features ever offered in a sub-3 W processor.
+
+The QorIQ LS1021A processor features an integrated LCD controller,
+CAN controller for implementing industrial protocols, DDR3L/4 running
+up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
+protection on both L1 and L2 caches. The LS1021A processor is pin- and
+software-compatible with the QorIQ LS1020A and LS1022A processors.
+
+The LS1021A SoC includes the following function and features:
+
+ - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
+ - Dual high-preformance ARM Cortex-A7 cores, each core includes:
+ - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)
+ - 512 Kbyte shared coherent L2 Cache (with ECC protection)
+ - NEON Co-processor (per core)
+ - 40-bit physical addressing
+ - Vector floating-point support
+ - ARM Core-Link CCI-400 Cache Coherent Interconnect
+ - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
+ supporting speeds up to 1600Mtps
+ - ECC and interleaving support
+ - VeTSEC Ethernet complex
+ - Up to 3x virtualized 10/100/1000 Ethernet controllers
+ - MII, RMII, RGMII, and SGMII support
+ - QoS, lossless flow control, and IEEE 1588 support
+ - 4-lane 6GHz SerDes
+ - High speed interconnect (4 SerDes lanes with are muxed for these protocol)
+ - Two PCI Express Gen2 controllers running at up to 5 GHz
+ - One Serial ATA 3.0 supporting 6 GT/s operation
+ - Two SGMII interfaces supporting 1000 Mbps
+ - Additional peripheral interfaces
+ - One high-speed USB 3.0 controller with integrated PHY and one high-speed
+ USB 2.00 controller with ULPI
+ - Integrated flash controller (IFC) with 16-bit interface
+ - Quad SPI NOR Flash
+ - One enhanced Secure digital host controller
+ - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface)
+ - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power
+ UARTs
+ - Three I2C controllers
+ - Eight FlexTimers four supporting PWM and four FlexCAN ports
+ - Four GPIO controllers supporting up to 109 general purpose I/O signals
+ - Integrated advanced audio block:
+ - Four synchronous audio interfaces (SAI)
+ - Sony/Philips Digital Interconnect Format (SPDIF)
+ - Asynchronous Sample Rate Converter (ASRC)
+ - Hardware based crypto offload engine
+ - IPSec forwarding at up to 1Gbps
+ - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported
+ - Public key hardware accelerator
+ - True Random Number Generator (NIST Certified)
+ - Advanced Encryption Standard Accelerators (AESA)
+ - Data Encryption Standard Accelerators
+ - QUICC Engine ULite block
+ - Two universal communication controllers (TDM and HDLC) supporting 64
+ multichannels, each running at 64 Kbps
+ - Support for 256 channels of HDLC
+ - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported
+
+LS1021ATWR board Overview
+-------------------------
+ - DDR Controller
+ - Supports rates of up to 1600 MHz data-rate
+ - Supports one DDR3LP SDRAM.
+ - IFC/Local Bus
+ - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+ - Three on-board RGMII 10/100/1G ethernet ports.
+ - CPLD
+ - Clocks
+ - System and DDR clock (SYSCLK, DDRCLK)
+ - SERDES clocks
+ - Power Supplies
+ - SDHC
+ - SDHC/SDXC connector
+ - Other IO
+ - One Serial port
+ - Three I2C ports
+
+Memory map
+-----------
+The addresses in brackets are physical addresses.
+
+Start Address End Address Description Size
+0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
+0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
+0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
+0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
+0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
+0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB
+0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
+0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
diff --git a/board/freescale/ls1021atwr/dcu.c b/board/freescale/ls1021atwr/dcu.c
new file mode 100644
index 0000000..8fe4ccb
--- /dev/null
+++ b/board/freescale/ls1021atwr/dcu.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+#include "../common/dcu_sii9022a.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+ unsigned long long div;
+
+ div = (unsigned long long)(gd->bus_clk / 1000);
+ div *= (unsigned long long)pixclock;
+ do_div(div, 1000000000);
+
+ return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+ const char *port,
+ struct fb_videomode *dcu_fb_videomode)
+{
+ const char *name;
+ unsigned int pixel_format;
+
+ if (strncmp(port, "twr_lcd", 4) == 0) {
+ name = "TWR_LCD_RGB card";
+ } else {
+ name = "HDMI";
+ dcu_set_dvi_encoder(dcu_fb_videomode);
+ }
+
+ printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+
+ pixel_format = 32;
+ fsl_dcu_init(xres, yres, pixel_format);
+
+ return 0;
+}
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
new file mode 100644
index 0000000..8ab229d
--- /dev/null
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -0,0 +1,664 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ns_access.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
+#include <asm/pcie_layerscape.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include <netdev.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <fsl_sec.h>
+#include <spl.h>
+#ifdef CONFIG_U_QE
+#include "../../../drivers/qe/qe.h"
+#endif
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define VERSION_MASK 0x00FF
+#define BANK_MASK 0x0001
+#define CONFIG_RESET 0x1
+#define INIT_RESET 0x1
+
+#define CPLD_SET_MUX_SERDES 0x20
+#define CPLD_SET_BOOT_BANK 0x40
+
+#define BOOT_FROM_UPPER_BANK 0x0
+#define BOOT_FROM_LOWER_BANK 0x1
+
+#define LANEB_SATA (0x01)
+#define LANEB_SGMII1 (0x02)
+#define LANEC_SGMII1 (0x04)
+#define LANEC_PCIEX1 (0x08)
+#define LANED_PCIEX2 (0x10)
+#define LANED_SGMII2 (0x20)
+
+#define MASK_LANE_B 0x1
+#define MASK_LANE_C 0x2
+#define MASK_LANE_D 0x4
+#define MASK_SGMII 0x8
+
+#define KEEP_STATUS 0x0
+#define NEED_RESET 0x1
+
+struct cpld_data {
+ u8 cpld_ver; /* cpld revision */
+ u8 cpld_ver_sub; /* cpld sub revision */
+ u8 pcba_ver; /* pcb revision number */
+ u8 system_rst; /* reset system by cpld */
+ u8 soft_mux_on; /* CPLD override physical switches Enable */
+ u8 cfg_rcw_src1; /* Reset config word 1 */
+ u8 cfg_rcw_src2; /* Reset config word 2 */
+ u8 vbank; /* Flash bank selection Control */
+ u8 gpio; /* GPIO for TWR-ELEV */
+ u8 i2c3_ifc_mux;
+ u8 mux_spi2;
+ u8 can3_usb2_mux; /* CAN3 and USB2 Selection */
+ u8 qe_lcd_mux; /* QE and LCD Selection */
+ u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */
+ u8 global_rst; /* reset with init CPLD reg to default */
+ u8 rev1; /* Reserved */
+ u8 rev2; /* Reserved */
+};
+
+#ifndef CONFIG_QSPI_BOOT
+static void convert_serdes_mux(int type, int need_reset);
+
+void cpld_show(void)
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
+ in_8(&cpld_data->cpld_ver) & VERSION_MASK,
+ in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
+ in_8(&cpld_data->pcba_ver) & VERSION_MASK,
+ in_8(&cpld_data->vbank) & BANK_MASK);
+
+#ifdef CONFIG_DEBUG
+ printf("soft_mux_on =%x\n",
+ in_8(&cpld_data->soft_mux_on));
+ printf("cfg_rcw_src1 =%x\n",
+ in_8(&cpld_data->cfg_rcw_src1));
+ printf("cfg_rcw_src2 =%x\n",
+ in_8(&cpld_data->cfg_rcw_src2));
+ printf("vbank =%x\n",
+ in_8(&cpld_data->vbank));
+ printf("gpio =%x\n",
+ in_8(&cpld_data->gpio));
+ printf("i2c3_ifc_mux =%x\n",
+ in_8(&cpld_data->i2c3_ifc_mux));
+ printf("mux_spi2 =%x\n",
+ in_8(&cpld_data->mux_spi2));
+ printf("can3_usb2_mux =%x\n",
+ in_8(&cpld_data->can3_usb2_mux));
+ printf("qe_lcd_mux =%x\n",
+ in_8(&cpld_data->qe_lcd_mux));
+ printf("serdes_mux =%x\n",
+ in_8(&cpld_data->serdes_mux));
+#endif
+}
+#endif
+
+int checkboard(void)
+{
+ puts("Board: LS1021ATWR\n");
+#ifndef CONFIG_QSPI_BOOT
+ cpld_show();
+#endif
+
+ return 0;
+}
+
+void ddrmc_init(void)
+{
+ struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+
+ out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
+
+ out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
+ out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
+
+ out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
+ out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
+ out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
+ out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
+ out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
+ out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
+
+ out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+
+ out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
+ out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
+
+ out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
+
+ out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
+
+ out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
+ out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
+
+ out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
+ out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
+
+ out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
+ out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
+
+ out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
+ udelay(1);
+ out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
+}
+
+int dram_init(void)
+{
+#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+ ddrmc_init();
+#endif
+
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+ {CONFIG_SYS_FSL_ESDHC_ADDR},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ if (is_serdes_configured(SGMII_TSEC1)) {
+ puts("eTSEC1 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ if (is_serdes_configured(SGMII_TSEC2)) {
+ puts("eTSEC2 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ num++;
+#endif
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+#endif
+
+#ifndef CONFIG_QSPI_BOOT
+int config_serdes_mux(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
+
+ protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
+ switch (protocol) {
+ case 0x10:
+ convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
+ convert_serdes_mux(LANED_PCIEX2 |
+ LANEC_PCIEX1, KEEP_STATUS);
+ break;
+ case 0x20:
+ convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
+ convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
+ convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
+ break;
+ case 0x30:
+ convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
+ convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
+ convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
+ break;
+ case 0x70:
+ convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
+ convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
+ convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
+ break;
+ }
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_TSEC_ENET
+ out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+#endif
+
+#ifdef CONFIG_FSL_IFC
+ init_early_memctl_regs();
+#endif
+
+#ifdef CONFIG_FSL_DCU_FB
+ out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+ out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ /* Set global data pointer */
+ gd = &gdata;
+
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ get_clocks();
+
+ preloader_console_init();
+
+ dram_init();
+
+ board_init_r(NULL, 0);
+}
+#endif
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+static struct csu_ns_dev ns_dev[] = {
+ { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+ { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+ { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM, CSU_ALL_RW },
+ { CSU_CSLX_GIC, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+ { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+ { CSU_CSLX_PCIE2, CSU_ALL_RW },
+ { CSU_CSLX_SATA, CSU_ALL_RW },
+ { CSU_CSLX_USB3, CSU_ALL_RW },
+ { CSU_CSLX_SERDES, CSU_ALL_RW },
+ { CSU_CSLX_QDMA, CSU_ALL_RW },
+ { CSU_CSLX_LPUART2, CSU_ALL_RW },
+ { CSU_CSLX_LPUART1, CSU_ALL_RW },
+ { CSU_CSLX_LPUART4, CSU_ALL_RW },
+ { CSU_CSLX_LPUART3, CSU_ALL_RW },
+ { CSU_CSLX_LPUART6, CSU_ALL_RW },
+ { CSU_CSLX_LPUART5, CSU_ALL_RW },
+ { CSU_CSLX_DSPI2, CSU_ALL_RW },
+ { CSU_CSLX_DSPI1, CSU_ALL_RW },
+ { CSU_CSLX_QSPI, CSU_ALL_RW },
+ { CSU_CSLX_ESDHC, CSU_ALL_RW },
+ { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+ { CSU_CSLX_IFC, CSU_ALL_RW },
+ { CSU_CSLX_I2C1, CSU_ALL_RW },
+ { CSU_CSLX_USB2, CSU_ALL_RW },
+ { CSU_CSLX_I2C3, CSU_ALL_RW },
+ { CSU_CSLX_I2C2, CSU_ALL_RW },
+ { CSU_CSLX_DUART2, CSU_ALL_RW },
+ { CSU_CSLX_DUART1, CSU_ALL_RW },
+ { CSU_CSLX_WDT2, CSU_ALL_RW },
+ { CSU_CSLX_WDT1, CSU_ALL_RW },
+ { CSU_CSLX_EDMA, CSU_ALL_RW },
+ { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+ { CSU_CSLX_DDR, CSU_ALL_RW },
+ { CSU_CSLX_QUICC, CSU_ALL_RW },
+ { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+ { CSU_CSLX_SFP, CSU_ALL_RW },
+ { CSU_CSLX_TMU, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+ { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO1, CSU_ALL_RW },
+ { CSU_CSLX_GPIO4, CSU_ALL_RW },
+ { CSU_CSLX_GPIO3, CSU_ALL_RW },
+ { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+ { CSU_CSLX_CSU, CSU_ALL_RW },
+ { CSU_CSLX_ASRC, CSU_ALL_RW },
+ { CSU_CSLX_SPDIF, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+ { CSU_CSLX_SAI2, CSU_ALL_RW },
+ { CSU_CSLX_SAI1, CSU_ALL_RW },
+ { CSU_CSLX_SAI4, CSU_ALL_RW },
+ { CSU_CSLX_SAI3, CSU_ALL_RW },
+ { CSU_CSLX_FTM2, CSU_ALL_RW },
+ { CSU_CSLX_FTM1, CSU_ALL_RW },
+ { CSU_CSLX_FTM4, CSU_ALL_RW },
+ { CSU_CSLX_FTM3, CSU_ALL_RW },
+ { CSU_CSLX_FTM6, CSU_ALL_RW },
+ { CSU_CSLX_FTM5, CSU_ALL_RW },
+ { CSU_CSLX_FTM8, CSU_ALL_RW },
+ { CSU_CSLX_FTM7, CSU_ALL_RW },
+ { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+ { CSU_CSLX_EPU, CSU_ALL_RW },
+ { CSU_CSLX_GDI, CSU_ALL_RW },
+ { CSU_CSLX_DDI, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+ { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED2, CSU_ALL_RW },
+};
+#endif
+
+struct smmu_stream_id dev_stream_id[] = {
+ { 0x100, 0x01, "ETSEC MAC1" },
+ { 0x104, 0x02, "ETSEC MAC2" },
+ { 0x108, 0x03, "ETSEC MAC3" },
+ { 0x10c, 0x04, "PEX1" },
+ { 0x110, 0x05, "PEX2" },
+ { 0x114, 0x06, "qDMA" },
+ { 0x118, 0x07, "SATA" },
+ { 0x11c, 0x08, "USB3" },
+ { 0x120, 0x09, "QE" },
+ { 0x124, 0x0a, "eSDHC" },
+ { 0x128, 0x0b, "eMA" },
+ { 0x14c, 0x0c, "2D-ACE" },
+ { 0x150, 0x0d, "USB2" },
+ { 0x18c, 0x0e, "DEBUG" },
+};
+
+int board_init(void)
+{
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+ /*
+ * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
+ * All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
+#ifndef CONFIG_SYS_FSL_NO_SERDES
+ fsl_serdes_init();
+#ifndef CONFIG_QSPI_BOOT
+ config_serdes_mux();
+#endif
+#endif
+
+ ls102xa_config_smmu_stream_id(dev_stream_id,
+ ARRAY_SIZE(dev_stream_id));
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+
+#ifdef CONFIG_U_QE
+ u_qe_init();
+#endif
+
+ return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#ifdef CONFIG_FSL_CAAM
+ return sec_init();
+#endif
+}
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCIE_LAYERSCAPE
+ ft_pcie_setup(blob, bd);
+#endif
+
+ return 0;
+}
+
+u8 flash_read8(void *addr)
+{
+ return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+ u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+ __raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+ u16 val = __raw_readw(addr);
+
+ return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
+
+#ifndef CONFIG_QSPI_BOOT
+static void convert_flash_bank(char bank)
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ printf("Now switch to boot from flash bank %d.\n", bank);
+ cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
+ cpld_data->vbank = bank;
+
+ printf("Reset board to enable configuration.\n");
+ cpld_data->system_rst = CONFIG_RESET;
+}
+
+static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (argc != 2)
+ return CMD_RET_USAGE;
+ if (strcmp(argv[1], "0") == 0)
+ convert_flash_bank(BOOT_FROM_UPPER_BANK);
+ else if (strcmp(argv[1], "1") == 0)
+ convert_flash_bank(BOOT_FROM_LOWER_BANK);
+ else
+ return CMD_RET_USAGE;
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ boot_bank, 2, 0, flash_bank_cmd,
+ "Flash bank Selection Control",
+ "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
+);
+
+static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ if (argc > 2)
+ return CMD_RET_USAGE;
+ if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
+ cpld_data->system_rst = CONFIG_RESET;
+ else if (strcmp(argv[1], "init") == 0)
+ cpld_data->global_rst = INIT_RESET;
+ else
+ return CMD_RET_USAGE;
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ cpld_reset, 2, 0, cpld_reset_cmd,
+ "Reset via CPLD",
+ "conf\n"
+ " -reset with current CPLD configuration\n"
+ "init\n"
+ " -reset and initial CPLD configuration with default value"
+
+);
+
+static void convert_serdes_mux(int type, int need_reset)
+{
+ char current_serdes;
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ current_serdes = cpld_data->serdes_mux;
+
+ switch (type) {
+ case LANEB_SATA:
+ current_serdes &= ~MASK_LANE_B;
+ break;
+ case LANEB_SGMII1:
+ current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
+ break;
+ case LANEC_SGMII1:
+ current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
+ break;
+ case LANED_SGMII2:
+ current_serdes |= MASK_LANE_D;
+ break;
+ case LANEC_PCIEX1:
+ current_serdes |= MASK_LANE_C;
+ break;
+ case (LANED_PCIEX2 | LANEC_PCIEX1):
+ current_serdes |= MASK_LANE_C;
+ current_serdes &= ~MASK_LANE_D;
+ break;
+ default:
+ printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
+ return;
+ }
+
+ cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
+ cpld_data->serdes_mux = current_serdes;
+
+ if (need_reset == 1) {
+ printf("Reset board to enable configuration\n");
+ cpld_data->system_rst = CONFIG_RESET;
+ }
+}
+
+void print_serdes_mux(void)
+{
+ char current_serdes;
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ current_serdes = cpld_data->serdes_mux;
+
+ printf("Serdes Lane B: ");
+ if ((current_serdes & MASK_LANE_B) == 0)
+ printf("SATA,\n");
+ else
+ printf("SGMII 1,\n");
+
+ printf("Serdes Lane C: ");
+ if ((current_serdes & MASK_LANE_C) == 0)
+ printf("SGMII 1,\n");
+ else
+ printf("PCIe,\n");
+
+ printf("Serdes Lane D: ");
+ if ((current_serdes & MASK_LANE_D) == 0)
+ printf("PCIe,\n");
+ else
+ printf("SGMII 2,\n");
+
+ printf("SGMII 1 is on lane ");
+ if ((current_serdes & MASK_SGMII) == 0)
+ printf("C.\n");
+ else
+ printf("B.\n");
+}
+
+static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (argc != 2)
+ return CMD_RET_USAGE;
+ if (strcmp(argv[1], "sata") == 0) {
+ printf("Set serdes lane B to SATA.\n");
+ convert_serdes_mux(LANEB_SATA, NEED_RESET);
+ } else if (strcmp(argv[1], "sgmii1b") == 0) {
+ printf("Set serdes lane B to SGMII 1.\n");
+ convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
+ } else if (strcmp(argv[1], "sgmii1c") == 0) {
+ printf("Set serdes lane C to SGMII 1.\n");
+ convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
+ } else if (strcmp(argv[1], "sgmii2") == 0) {
+ printf("Set serdes lane D to SGMII 2.\n");
+ convert_serdes_mux(LANED_SGMII2, NEED_RESET);
+ } else if (strcmp(argv[1], "pciex1") == 0) {
+ printf("Set serdes lane C to PCIe X1.\n");
+ convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
+ } else if (strcmp(argv[1], "pciex2") == 0) {
+ printf("Set serdes lane C & lane D to PCIe X2.\n");
+ convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
+ } else if (strcmp(argv[1], "show") == 0) {
+ print_serdes_mux();
+ } else {
+ return CMD_RET_USAGE;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ lane_bank, 2, 0, serdes_mux_cmd,
+ "Multiplexed function setting for SerDes Lanes",
+ "sata\n"
+ " -change lane B to sata\n"
+ "lane_bank sgmii1b\n"
+ " -change lane B to SGMII1\n"
+ "lane_bank sgmii1c\n"
+ " -change lane C to SGMII1\n"
+ "lane_bank sgmii2\n"
+ " -change lane D to SGMII2\n"
+ "lane_bank pciex1\n"
+ " -change lane C to PCIeX1\n"
+ "lane_bank pciex2\n"
+ " -change lane C & lane D to PCIeX2\n"
+ "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
+);
+#endif
diff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/board/freescale/ls1021atwr/ls102xa_pbi.cfg
new file mode 100644
index 0000000..f1a1b63
--- /dev/null
+++ b/board/freescale/ls1021atwr/ls102xa_pbi.cfg
@@ -0,0 +1,12 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
new file mode 100644
index 0000000..9c3e3b0
--- /dev/null
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
@@ -0,0 +1,14 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+0608000a 00000000 00000000 00000000
+20000000 00407900 60040a00 21046000
+00000000 00000000 00000000 00038000
+00080000 881b7340 00000000 00000000
+
+#disable IFC, enable QSPI and DSPI
+#0608000a 00000000 00000000 00000000
+#20000000 00407900 60040a00 21046000
+#00000000 00000000 00000000 00038000
+#20084800 881b7340 00000000 00000000
diff --git a/board/freescale/ls2085a/Kconfig b/board/freescale/ls2085a/Kconfig
new file mode 100644
index 0000000..f51afc8
--- /dev/null
+++ b/board/freescale/ls2085a/Kconfig
@@ -0,0 +1,31 @@
+if TARGET_LS2085A_EMU
+
+config SYS_BOARD
+ default "ls2085a"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-lsch3"
+
+config SYS_CONFIG_NAME
+ default "ls2085a_emu"
+
+endif
+
+if TARGET_LS2085A_SIMU
+
+config SYS_BOARD
+ default "ls2085a"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-lsch3"
+
+config SYS_CONFIG_NAME
+ default "ls2085a_simu"
+
+endif
diff --git a/board/freescale/ls2085a/MAINTAINERS b/board/freescale/ls2085a/MAINTAINERS
new file mode 100644
index 0000000..572c4b8
--- /dev/null
+++ b/board/freescale/ls2085a/MAINTAINERS
@@ -0,0 +1,9 @@
+LS2085A BOARD
+M: York Sun <yorksun@freescale.com>
+S: Maintained
+F: board/freescale/ls2085a/
+F: include/configs/ls2085a_emu.h
+F: configs/ls2085a_emu_defconfig
+F: configs/ls2085a_emu_D4_defconfig
+F: include/configs/ls2085a_simu.h
+F: configs/ls2085a_simu_defconfig
diff --git a/board/freescale/ls2085a/Makefile b/board/freescale/ls2085a/Makefile
new file mode 100644
index 0000000..701b35c
--- /dev/null
+++ b/board/freescale/ls2085a/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2014 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ls2085a.o
+obj-y += ddr.o
diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2085a/README
new file mode 100644
index 0000000..b7023e1
--- /dev/null
+++ b/board/freescale/ls2085a/README
@@ -0,0 +1,16 @@
+Freescale ls2085a_emu
+
+This is a emulator target with limited peripherals.
+
+Memory map from core's view
+
+0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
+0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
+0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
+0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
+0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
+0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
+0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
+
+Other addresses are either reserved, or not used directly by u-boot.
+This list should be updated when more addresses are used.
diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2085a/ddr.c
new file mode 100644
index 0000000..b4a3fc9
--- /dev/null
+++ b/board/freescale/ls2085a/ddr.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 3) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[ctrl_num];
+ else
+ pbsp = udimms[ctrl_num];
+
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for data rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ if (ctrl_num == CONFIG_DP_DDR_CTRL) {
+ /* force DDR bus width to 32 bits */
+ popts->data_bus_width = 1;
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+ }
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+#else
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+}
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 2,
+ .rank_density = 1073741824u,
+ .capacity = 2147483648,
+ .primary_sdram_width = 64,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 14,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 937,
+ .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */
+ .taa_ps = 13090,
+ .twr_ps = 15000,
+ .trcd_ps = 13090,
+ .trrd_ps = 5000,
+ .trp_ps = 13090,
+ .tras_ps = 33000,
+ .trc_ps = 46090,
+ .trfc_ps = 160000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 25000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if (((controller_number == 0) && (dimm_number == 0)) ||
+ ((controller_number == 1) && (dimm_number == 0))) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+#endif
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing DDR....");
+
+ puts("using SPD\n");
+ dram_size = fsl_ddr_sdram();
+
+ return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+ phys_size_t dp_ddr_size;
+#endif
+
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
+ gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+ gd->bd->bi_dram[1].size = gd->ram_size -
+ CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+ } else {
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ }
+
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+ /* initialize DP-DDR here */
+ puts("DP-DDR: ");
+ /*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+ dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+ CONFIG_DP_DDR_CTRL,
+ CONFIG_DP_DDR_NUM_CTRLS,
+ CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
+ NULL, NULL, NULL);
+ if (dp_ddr_size) {
+ gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+ gd->bd->bi_dram[2].size = dp_ddr_size;
+ } else {
+ puts("Not detected");
+ }
+#endif
+}
diff --git a/board/freescale/ls2085a/ddr.h b/board/freescale/ls2085a/ddr.h
new file mode 100644
index 0000000..9958a68
--- /dev/null
+++ b/board/freescale/ls2085a/ddr.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 2140, 0, 4, 4, 0x0, 0x0},
+ {1, 2140, 0, 4, 4, 0x0, 0x0},
+ {}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters udimm2[] = {
+ /*
+ * memory controller 2
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 2140, 0, 4, 4, 0x0, 0x0},
+ {1, 2140, 0, 4, 4, 0x0, 0x0},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {4, 2140, 0, 5, 4, 0x0, 0x0},
+ {2, 2140, 0, 5, 4, 0x0, 0x0},
+ {1, 2140, 0, 4, 4, 0x0, 0x0},
+ {}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters rdimm2[] = {
+ /*
+ * memory controller 2
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {4, 2140, 0, 5, 4, 0x0, 0x0},
+ {2, 2140, 0, 5, 4, 0x0, 0x0},
+ {1, 2140, 0, 4, 4, 0x0, 0x0},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+ udimm0,
+ udimm2,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+ rdimm0,
+ rdimm2,
+};
+
+
+#endif
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
new file mode 100644
index 0000000..163a4c4
--- /dev/null
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <fsl_mc.h>
+#include <environment.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ init_final_memctl_regs();
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ init_early_memctl_regs(); /* tighten IFC timing */
+
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ puts("\nDDR ");
+ print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_ddr_info(0);
+ if (gd->bd->bi_dram[2].size) {
+ puts("\nDP-DDR ");
+ print_size(gd->bd->bi_dram[2].size, "");
+ print_ddr_info(CONFIG_DP_DDR_CTRL);
+ }
+}
+
+int dram_init(void)
+{
+ gd->ram_size = initdram(0);
+
+ return 0;
+}
+
+int timer_init(void)
+{
+ u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+
+ out_le32(cltbenr, 0x1); /* enable cluster0 timebase */
+ out_le32(cntcr, 0x1); /* enable clock for timer */
+
+ return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int error = 0;
+
+#ifdef CONFIG_SMC91111
+ error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+ error = cpu_eth_init(bis);
+#endif
+ return error;
+}
+
+#ifdef CONFIG_FSL_MC_ENET
+void fdt_fixup_board_enet(void *fdt)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+ if (get_mc_boot_status() == 0)
+ fdt_status_okay(fdt, offset);
+ else
+ fdt_status_fail(fdt, offset);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ /* limit the memory size to bank 1 until Linux can handle 40-bit PA */
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_FSL_MC_ENET
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/m5208evbe/Kconfig b/board/freescale/m5208evbe/Kconfig
new file mode 100644
index 0000000..9b416af
--- /dev/null
+++ b/board/freescale/m5208evbe/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5208EVBE
+
+config SYS_CPU
+ default "mcf52x2"
+
+config SYS_BOARD
+ default "m5208evbe"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M5208EVBE"
+
+endif
diff --git a/board/freescale/m5208evbe/MAINTAINERS b/board/freescale/m5208evbe/MAINTAINERS
new file mode 100644
index 0000000..c9c3c88
--- /dev/null
+++ b/board/freescale/m5208evbe/MAINTAINERS
@@ -0,0 +1,6 @@
+M5208EVBE BOARD
+#M: -
+S: Maintained
+F: board/freescale/m5208evbe/
+F: include/configs/M5208EVBE.h
+F: configs/M5208EVBE_defconfig
diff --git a/board/freescale/m5208evbe/Makefile b/board/freescale/m5208evbe/Makefile
new file mode 100644
index 0000000..1cb17fe
--- /dev/null
+++ b/board/freescale/m5208evbe/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m5208evbe.o
diff --git a/board/freescale/m5208evbe/config.mk b/board/freescale/m5208evbe/config.mk
new file mode 100644
index 0000000..c15a9cf
--- /dev/null
+++ b/board/freescale/m5208evbe/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c
new file mode 100644
index 0000000..1df128b
--- /dev/null
+++ b/board/freescale/m5208evbe/m5208evbe.c
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale M5208EVBe\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+ u32 dramsize, i;
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+#ifdef CONFIG_SYS_SDRAM_BASE1
+ out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
+#endif
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+ udelay(500);
+
+ /* Issue PALL */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ asm("nop");
+
+ /* Perform two refresh cycles */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ asm("nop");
+
+ /* Issue LEMR */
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ asm("nop");
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ asm("nop");
+
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ asm("nop");
+
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
+ asm("nop");
+
+ udelay(100);
+
+ return dramsize;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/freescale/m5208evbe/u-boot.lds b/board/freescale/m5208evbe/u-boot.lds
new file mode 100644
index 0000000..8b1a59d
--- /dev/null
+++ b/board/freescale/m5208evbe/u-boot.lds
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf52x2/start.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.sbss*)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m52277evb/Kconfig b/board/freescale/m52277evb/Kconfig
new file mode 100644
index 0000000..c427892
--- /dev/null
+++ b/board/freescale/m52277evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M52277EVB
+
+config SYS_CPU
+ default "mcf5227x"
+
+config SYS_BOARD
+ default "m52277evb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M52277EVB"
+
+endif
diff --git a/board/freescale/m52277evb/MAINTAINERS b/board/freescale/m52277evb/MAINTAINERS
new file mode 100644
index 0000000..390f041
--- /dev/null
+++ b/board/freescale/m52277evb/MAINTAINERS
@@ -0,0 +1,7 @@
+M52277EVB BOARD
+M: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+S: Maintained
+F: board/freescale/m52277evb/
+F: include/configs/M52277EVB.h
+F: configs/M52277EVB_defconfig
+F: configs/M52277EVB_stmicro_defconfig
diff --git a/board/freescale/m52277evb/Makefile b/board/freescale/m52277evb/Makefile
new file mode 100644
index 0000000..6b3b8ae
--- /dev/null
+++ b/board/freescale/m52277evb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m52277evb.o
diff --git a/board/freescale/m52277evb/README b/board/freescale/m52277evb/README
new file mode 100644
index 0000000..3178d49
--- /dev/null
+++ b/board/freescale/m52277evb/README
@@ -0,0 +1,231 @@
+Freescale MCF52277EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created Jan 8, 2008
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m52277evb/m52277evb.c Dram setup
+- board/freescale/m52277evb/Makefile Makefile
+- board/freescale/m52277evb/config.mk config make
+- board/freescale/m52277evb/u-boot.lds Linker description
+
+- arch/m68k/cpu/mcf5227x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf5227x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
+- arch/m68k/cpu/mcf5227x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf5227x/speed.c system, flexbus, and cpu clock
+- arch/m68k/cpu/mcf5227x/Makefile Makefile
+- arch/m68k/cpu/mcf5227x/config.mk config make
+- arch/m68k/cpu/mcf5227x/start.S start up assembly code
+
+- doc/README.m52277evb This readme file
+
+- drivers/serial/mcfuart.c ColdFire common UART driver
+- drivers/rtc/mcfrtc.c Realtime clock Driver
+
+- include/asm-m68k/bitops.h Bit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/crossbar.h CrossBar structure and definition
+- include/asm-m68k/dspi.h DSPI structure and definition
+- include/asm-m68k/edma.h eDMA structure and definition
+- include/asm-m68k/flexbus.h FlexBus structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5227x.h mcf5227x specific header file
+- include/asm-m68k/io.h io functions
+- include/asm-m68k/lcd.h LCD structure and definition
+- include/asm-m68k/m5227x.h mcf5227x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h header file
+- include/asm-m68k/ptrace.h Exception structure
+- include/asm-m68k/rtc.h Realtime clock header file
+- include/asm-m68k/ssi.h SSI structure and definition
+- include/asm-m68k/string.h String function export
+- include/asm-m68k/timer.h Timer structure and definition
+- include/asm-m68k/types.h Data types definition
+- include/asm-m68k/uart.h Uart structure and definition
+- include/asm-m68k/u-boot.h u-boot structure
+
+- include/configs/M52277EVB.h Board specific configuration file
+
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c Exception init code
+
+1 MCF52277 specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in this coldfire family
+
+1.2 Configuration settings for M52277EVB Development Board
+CONFIG_MCF5227x -- define for all MCF5227x CPUs
+CONFIG_M52277 -- define for all Freescale MCF52277 CPUs
+CONFIG_M52277EVB -- define for M52277EVB board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_MCFRTC -- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
+RTC_DEBUG -- define to show RTC debug message
+CONFIG_CMD_DATE -- enable to use date feature in u-boot
+
+CONFIG_MCFTMR -- define to use DMA timer
+CONFIG_MCFPIT -- define to use PIT timer
+
+CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
+CONFIG_HARD_I2C -- define for I2C hardware support
+CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED -- define for I2C speed
+CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
+CONFIG_SYS_IMMR -- define for MBAR offset
+
+CONFIG_SYS_MBAR -- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF52277 internal SRAM
+
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+
+CONFIG_LCD and CONFIG_CMD_USB are not supported in this current u-boot,
+update will be provided at later time
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ Flash: 0x00000000-0x3FFFFFFF (1024MB)
+ DDR: 0x40000000-0x7FFFFFFF (1024MB)
+ SRAM: 0x80000000-0x8FFFFFFF (256MB)
+ IP: 0xF0000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ Flash0: 0x00000000-0x00FFFFFF (16MB)
+
+ DDR: 0x40000000-0x4FFFFFFF (64MB)
+ SRAM: 0x80000000-0x80007FFF (32KB)
+ IP: 0xFC000000-0xFC0FFFFF (64KB)
+
+3. COMPILATION
+==============
+3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or
+uClinux version) from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix
+ cd u-boot-1.x.x
+ make distclean
+ make M52277EVB_config
+ make
+
+4. SCREEN DUMP
+==============
+4.1 M52277EVB Development board
+ (NOTE: May not show exactly the same)
+
+U-Boot 1.3.1 (Jan 8 2008 - 12:44:08)
+
+CPU: Freescale MCF52277 (Mask:6c Version:0)
+ CPU CLK 160 Mhz BUS CLK 80 Mhz FLB CLK 80 MHZ
+ INP CLK 16 Mhz VCO CLK 480 Mhz
+Board: Freescale 52277 EVB
+I2C: ready
+DRAM: 64 MB
+FLASH: 16 MB
+In: serial
+Out: serial
+Err: serial
+-> print
+baudrate=115200
+hostname=M52277EVB
+inpclk=16000000
+loadaddr=(0x40000000 + 0x10000)
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save
+u-boot=u-boot.bin
+stdin=serial
+stdout=serial
+stderr=serial
+mem=65024k
+
+Environment size: 280/32764 bytes
+-> bdinfo
+memstart = 0x40000000
+memsize = 0x04000000
+flashstart = 0x00000000
+flashsize = 0x01000000
+flashoffset = 0x00000000
+sramstart = 0x80000000
+sramsize = 0x00008000
+mbar = 0xFC000000
+busfreq = 80 MHz
+flbfreq = 80 Mhz
+inpfreq = 16 Mhz
+vcofreq = 480 Mhz
+
+baudrate = 115200 bps
+->
+-> help
+? - alias for 'help'
+base - print or set address offset
+bdinfo - print Board Info structure
+boot - boot default, i.e., run 'bootcmd'
+bootd - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm - boot application image from memory
+bootp - boot image via network using BootP/TFTP protocol
+bootvx - Boot vxWorks from an ELF image
+cmp - memory compare
+coninfo - print console devices and information
+cp - memory copy
+crc32 - checksum calculation
+date - get/set/reset date & time
+dcache - enable or disable data cache
+echo - echo args to console
+erase - erase FLASH memory
+flinfo - print FLASH memory information
+go - start application at address 'addr'
+help - print online help
+i2c - I2C sub-system
+icache - enable or disable instruction cache
+iminfo - print header information for application image
+imls - list all images found in flash
+itest - return true/false on integer compare
+loadb - load binary file over serial line (kermit mode)
+loads - load S-Record file over serial line
+loady - load binary file over serial line (ymodem mode)
+loop - infinite loop on address range
+ls - list files in a directory (default /)
+md - memory display
+mm - memory modify (auto-incrementing)
+mtest - simple RAM test
+mw - memory write (fill)
+nm - memory modify (constant address)
+ping - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+reset - Perform RESET of the CPU
+run - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv - set environment variables
+sleep - delay execution for some time
+source - run script from memory
+version - print monitor version
+->
diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c
new file mode 100644
index 0000000..a1127e5
--- /dev/null
+++ b/board/freescale/m52277evb/m52277evb.c
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale M52277 EVB\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ u32 dramsize;
+
+#ifdef CONFIG_CF_SBF
+ /*
+ * Serial Boot: The dram is already initialized in start.S
+ * only require to return DRAM size
+ */
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+ u32 i;
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
+
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
+
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
+
+ /* Issue PALL */
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
+ __asm__("nop");
+
+ /* Issue LEMR */
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
+ __asm__("nop");
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD);
+ __asm__("nop");
+
+ udelay(1000);
+
+ /* Issue PALL */
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
+ __asm__("nop");
+
+ /* Perform two refresh cycles */
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+ __asm__("nop");
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+ __asm__("nop");
+
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+
+ udelay(100);
+#endif
+ return (dramsize);
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds
new file mode 100644
index 0000000..70121d9
--- /dev/null
+++ b/board/freescale/m52277evb/u-boot.lds
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf5227x/start.o (.text*)
+ arch/m68k/cpu/mcf5227x/built-in.o (.text*)
+ arch/m68k/lib/built-in.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.sbss*)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m5235evb/Kconfig b/board/freescale/m5235evb/Kconfig
new file mode 100644
index 0000000..fc83419
--- /dev/null
+++ b/board/freescale/m5235evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5235EVB
+
+config SYS_CPU
+ default "mcf523x"
+
+config SYS_BOARD
+ default "m5235evb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M5235EVB"
+
+endif
diff --git a/board/freescale/m5235evb/MAINTAINERS b/board/freescale/m5235evb/MAINTAINERS
new file mode 100644
index 0000000..f44422e
--- /dev/null
+++ b/board/freescale/m5235evb/MAINTAINERS
@@ -0,0 +1,7 @@
+M5235EVB BOARD
+M: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+S: Maintained
+F: board/freescale/m5235evb/
+F: include/configs/M5235EVB.h
+F: configs/M5235EVB_defconfig
+F: configs/M5235EVB_Flash32_defconfig
diff --git a/board/freescale/m5235evb/Makefile b/board/freescale/m5235evb/Makefile
new file mode 100644
index 0000000..e77d9d9
--- /dev/null
+++ b/board/freescale/m5235evb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m5235evb.o
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
new file mode 100644
index 0000000..68c1631
--- /dev/null
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale M5235 EVB\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+ u32 dramsize, i, dramclk;
+
+ /*
+ * When booting from external Flash, the port-size is less than
+ * the port-size of SDRAM. In this case it is necessary to enable
+ * Data[15:0] on Port Address/Data.
+ */
+ out_8(&gpio->par_ad,
+ GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
+ GPIO_PAR_AD_DATAL);
+
+ /* Initialize PAR to enable SDRAM signals */
+ out_8(&gpio->par_sdram,
+ GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
+ GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
+ GPIO_PAR_SDRAM_SDCS(3));
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
+ dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
+
+ /* Initialize DRAM Control Register: DCR */
+ out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
+ SDRAMC_DCR_RTIM_6CLKS |
+ SDRAMC_DCR_RC((15 * dramclk) >> 4));
+
+ /* Initialize DACR0 */
+ out_be32(&sdram->dacr0,
+ SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
+ SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
+ SDRAMC_DARCn_PS_32);
+ asm("nop");
+
+ /* Initialize DMR0 */
+ out_be32(&sdram->dmr0,
+ ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
+ asm("nop");
+
+ /* Set IP (bit 3) in DACR */
+ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
+
+ /* Wait 30ns to allow banks to precharge */
+ for (i = 0; i < 5; i++) {
+ asm("nop");
+ }
+
+ /* Write to this block to initiate precharge */
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+
+ /* Set RE (bit 15) in DACR */
+ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
+
+ /* Wait for at least 8 auto refresh cycles to occur */
+ for (i = 0; i < 0x2000; i++) {
+ asm("nop");
+ }
+
+ /* Finish the configuration by issuing the MRS. */
+ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
+ asm("nop");
+
+ /* Write to the SDRAM Mode Register */
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+ }
+
+ return dramsize;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/freescale/m5235evb/u-boot.lds b/board/freescale/m5235evb/u-boot.lds
new file mode 100644
index 0000000..ccfb5d6
--- /dev/null
+++ b/board/freescale/m5235evb/u-boot.lds
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ .text :
+ {
+ arch/m68k/cpu/mcf523x/start.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m5249evb/Kconfig b/board/freescale/m5249evb/Kconfig
new file mode 100644
index 0000000..0f62477
--- /dev/null
+++ b/board/freescale/m5249evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5249EVB
+
+config SYS_CPU
+ default "mcf52x2"
+
+config SYS_BOARD
+ default "m5249evb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M5249EVB"
+
+endif
diff --git a/board/freescale/m5249evb/MAINTAINERS b/board/freescale/m5249evb/MAINTAINERS
new file mode 100644
index 0000000..c2273c3
--- /dev/null
+++ b/board/freescale/m5249evb/MAINTAINERS
@@ -0,0 +1,6 @@
+M5249EVB BOARD
+#M: -
+S: Maintained
+F: board/freescale/m5249evb/
+F: include/configs/M5249EVB.h
+F: configs/M5249EVB_defconfig
diff --git a/board/freescale/m5249evb/Makefile b/board/freescale/m5249evb/Makefile
new file mode 100644
index 0000000..4267633
--- /dev/null
+++ b/board/freescale/m5249evb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m5249evb.o
diff --git a/board/freescale/m5249evb/config.mk b/board/freescale/m5249evb/config.mk
new file mode 100644
index 0000000..1af25e1
--- /dev/null
+++ b/board/freescale/m5249evb/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffe00000
diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c
new file mode 100644
index 0000000..7ae842c
--- /dev/null
+++ b/board/freescale/m5249evb/m5249evb.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/immap.h>
+
+int checkboard (void) {
+ ulong val;
+ uchar val8;
+
+ puts ("Board: ");
+ puts("Freescale M5249EVB");
+ val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
+ printf(" (Switch=%1X)\n", val8);
+
+ /*
+ * Set LED on
+ */
+ val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
+ mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
+
+ return 0;
+};
+
+
+phys_size_t initdram (int board_type) {
+ unsigned long junk = 0xa5a59696;
+
+ /*
+ * Note:
+ * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
+ */
+
+#ifdef CONFIG_SYS_FAST_CLK
+ /*
+ * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
+ * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
+ */
+ mbar_writeShort(MCFSIM_DCR, 0x8239);
+#elif CONFIG_SYS_PLL_BYPASS
+ /*
+ * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
+ * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
+ */
+ mbar_writeShort(MCFSIM_DCR, 0x8202);
+#else
+ /*
+ * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
+ * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
+ */
+ mbar_writeShort(MCFSIM_DCR, 0x8222);
+#endif
+
+ /*
+ * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
+ * PM=1 (continuous page mode)
+ */
+
+ /* RE=0 (keep auto-refresh disabled while setting up registers) */
+ mbar_writeLong(MCFSIM_DACR0, 0x00003324);
+
+ /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
+ mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
+
+ /** Precharge sequence **/
+ mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
+ *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
+ udelay(0x10); /* Allow several Precharge cycles */
+
+ /** Refresh Sequence **/
+ mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
+ udelay(0x7d0); /* Allow gobs of refresh cycles */
+
+ /** Mode Register initialization **/
+ mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
+ *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
+
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+};
+
+
+int testdram (void) {
+ /* TODO: XXX XXX XXX */
+ printf ("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds
new file mode 100644
index 0000000..e91b7e1
--- /dev/null
+++ b/board/freescale/m5249evb/u-boot.lds
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ .text :
+ {
+ arch/m68k/cpu/mcf52x2/start.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m5253demo/Kconfig b/board/freescale/m5253demo/Kconfig
new file mode 100644
index 0000000..303d29b
--- /dev/null
+++ b/board/freescale/m5253demo/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5253DEMO
+
+config SYS_CPU
+ default "mcf52x2"
+
+config SYS_BOARD
+ default "m5253demo"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M5253DEMO"
+
+endif
diff --git a/board/freescale/m5253demo/MAINTAINERS b/board/freescale/m5253demo/MAINTAINERS
new file mode 100644
index 0000000..abe065e
--- /dev/null
+++ b/board/freescale/m5253demo/MAINTAINERS
@@ -0,0 +1,6 @@
+M5253DEMO BOARD
+M: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+S: Maintained
+F: board/freescale/m5253demo/
+F: include/configs/M5253DEMO.h
+F: configs/M5253DEMO_defconfig
diff --git a/board/freescale/m5253demo/Makefile b/board/freescale/m5253demo/Makefile
new file mode 100644
index 0000000..62f3146
--- /dev/null
+++ b/board/freescale/m5253demo/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m5253demo.o flash.o
diff --git a/board/freescale/m5253demo/config.mk b/board/freescale/m5253demo/config.mk
new file mode 100644
index 0000000..4547465
--- /dev/null
+++ b/board/freescale/m5253demo/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xFF800000
diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c
new file mode 100644
index 0000000..071701d
--- /dev/null
+++ b/board/freescale/m5253demo/flash.c
@@ -0,0 +1,451 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/immap.h>
+
+#ifndef CONFIG_SYS_FLASH_CFI
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1 0x5555
+#define FLASH_CYCLE2 0x2aaa
+
+#define SYNC __asm__("nop")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+ulong flash_get_size(FPWV * addr, flash_info_t * info);
+int flash_get_offsets(ulong base, flash_info_t * info);
+int write_word(flash_info_t * info, FPWV * dest, u16 data);
+void inline spin_wheel(void);
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+ulong flash_init(void)
+{
+ ulong size = 0;
+ ulong fbase = 0;
+
+ fbase = (ulong) CONFIG_SYS_FLASH_BASE;
+ flash_get_size((FPWV *) fbase, &flash_info[0]);
+ flash_get_offsets((ulong) fbase, &flash_info[0]);
+ fbase += flash_info[0].size;
+ size += flash_info[0].size;
+
+ /* Protect monitor and environment sectors */
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+ return size;
+}
+
+int flash_get_offsets(ulong base, flash_info_t * info)
+{
+ int i;
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+
+ info->start[0] = base;
+ info->protect[0] = 0;
+ for (i = 1; i < CONFIG_SYS_SST_SECT; i++) {
+ info->start[i] = info->start[i - 1]
+ + CONFIG_SYS_SST_SECTSZ;
+ info->protect[i] = 0;
+ }
+ }
+
+ return ERR_OK;
+}
+
+void flash_print_info(flash_info_t * info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_SST:
+ printf("SST ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_SST6401B:
+ printf("SST39VF6401B\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ return;
+ }
+
+ if (info->size > 0x100000) {
+ int remainder;
+
+ printf(" Size: %ld", info->size >> 20);
+
+ remainder = (info->size % 0x100000);
+ if (remainder) {
+ remainder >>= 10;
+ remainder = (int)((float)
+ (((float)remainder / (float)1024) *
+ 10000));
+ printf(".%d ", remainder);
+ }
+
+ printf("MB in %d Sectors\n", info->sector_count);
+ } else
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size(FPWV * addr, flash_info_t * info)
+{
+ u16 value;
+
+ addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
+ addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
+ addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
+
+ switch (addr[0] & 0xffff) {
+ case (u8) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ value = addr[1];
+ break;
+ default:
+ printf("Unknown Flash\n");
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+
+ *addr = (FPW) 0x00F000F0;
+ return (0); /* no or unknown flash */
+ }
+
+ switch (value) {
+ case (u16) SST_ID_xF6401B:
+ info->flash_id += FLASH_SST6401B;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ break;
+ }
+
+ info->sector_count = 0;
+ info->size = 0;
+ info->sector_count = CONFIG_SYS_SST_SECT;
+ info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ;
+
+ /* reset ID mode */
+ *addr = (FPWV) 0x00F000F0;
+
+ if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+ printf("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ }
+
+ return (info->size);
+}
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ FPWV *addr;
+ int flag, prot, sect, count;
+ ulong type, start;
+ int rcode = 0, flashtype = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
+ return 1;
+ }
+
+ type = (info->flash_id & FLASH_VENDMASK);
+
+ switch (type) {
+ case FLASH_MAN_SST:
+ flashtype = 1;
+ break;
+ default:
+ type = (info->flash_id & FLASH_VENDMASK);
+ printf("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ else
+ printf("\n");
+
+ flag = disable_interrupts();
+
+ start = get_timer(0);
+
+ if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) {
+ if (prot == 0) {
+ addr = (FPWV *) info->start[0];
+
+ addr[FLASH_CYCLE1] = 0x00AA; /* unlock */
+ addr[FLASH_CYCLE2] = 0x0055; /* unlock */
+ addr[FLASH_CYCLE1] = 0x0080; /* erase mode */
+ addr[FLASH_CYCLE1] = 0x00AA; /* unlock */
+ addr[FLASH_CYCLE2] = 0x0055; /* unlock */
+ *addr = 0x0030; /* erase chip */
+
+ count = 0;
+ start = get_timer(0);
+
+ while ((*addr & 0x0080) != 0x0080) {
+ if (count++ > 0x10000) {
+ spin_wheel();
+ count = 0;
+ }
+
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ *addr = 0x00F0; /* reset to read mode */
+
+ return 1;
+ }
+ }
+
+ *addr = 0x00F0; /* reset to read mode */
+
+ printf("\b. done\n");
+
+ if (flag)
+ enable_interrupts();
+
+ return 0;
+ } else if (prot == CONFIG_SYS_SST_SECT) {
+ return 1;
+ }
+ }
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+
+ addr = (FPWV *) (info->start[sect]);
+
+ printf(".");
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ switch (flashtype) {
+ case 1:
+ {
+ FPWV *base; /* first address in bank */
+
+ flag = disable_interrupts();
+
+ base = (FPWV *) (CONFIG_SYS_FLASH_BASE); /* First sector */
+
+ base[FLASH_CYCLE1] = 0x00AA; /* unlock */
+ base[FLASH_CYCLE2] = 0x0055; /* unlock */
+ base[FLASH_CYCLE1] = 0x0080; /* erase mode */
+ base[FLASH_CYCLE1] = 0x00AA; /* unlock */
+ base[FLASH_CYCLE2] = 0x0055; /* unlock */
+ *addr = 0x0050; /* erase sector */
+
+ if (flag)
+ enable_interrupts();
+
+ while ((*addr & 0x0080) != 0x0080) {
+ if (get_timer(start) >
+ CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ *addr = 0x00F0; /* reset to read mode */
+
+ rcode = 1;
+ break;
+ }
+ }
+
+ *addr = 0x00F0; /* reset to read mode */
+ break;
+ }
+ } /* switch (flashtype) */
+ }
+ }
+ printf(" done\n");
+
+ if (flag)
+ enable_interrupts();
+
+ return rcode;
+}
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong wp, count;
+ u16 data;
+ int rc;
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return 4;
+
+ /* get lower word aligned address */
+ wp = addr;
+
+ /* handle unaligned start bytes */
+ if (wp & 1) {
+ data = *((FPWV *) wp);
+ data = (data << 8) | *src;
+
+ if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+ return (rc);
+
+ wp++;
+ cnt -= 1;
+ src++;
+ }
+
+ while (cnt >= 2) {
+ /*
+ * handle word aligned part
+ */
+ count = 0;
+ data = *((FPWV *) src);
+
+ if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+ return (rc);
+
+ wp += 2;
+ src += 2;
+ cnt -= 2;
+
+ if (count++ > 0x800) {
+ spin_wheel();
+ count = 0;
+ }
+ }
+ /* handle word aligned part */
+ if (cnt) {
+ /* handle word aligned part */
+ count = 0;
+ data = *((FPWV *) wp);
+
+ data = (data & 0x00FF) | (*src << 8);
+
+ if ((rc = write_word(info, (FPWV *) wp, data)) != 0)
+ return (rc);
+
+ wp++;
+ src++;
+ cnt -= 1;
+ if (count++ > 0x800) {
+ spin_wheel();
+ count = 0;
+ }
+ }
+
+ if (cnt == 0)
+ return ERR_OK;
+
+ return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash
+ * A word is 16 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_word(flash_info_t * info, FPWV * dest, u16 data)
+{
+ ulong start;
+ int flag;
+ int res = 0; /* result, assume success */
+ FPWV *base; /* first address in flash bank */
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*dest & (u8) data) != (u8) data) {
+ return (2);
+ }
+
+ base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */
+
+ *dest = data; /* start programming the data */
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer(0);
+
+ /* data polling for D7 */
+ while (res == 0
+ && (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ *dest = (u8) 0x00F000F0; /* reset bank */
+ res = 1;
+ }
+ }
+
+ *dest++ = (u8) 0x00F000F0; /* reset bank */
+
+ return (res);
+}
+
+void inline spin_wheel(void)
+{
+ static int p = 0;
+ static char w[] = "\\/-";
+
+ printf("\010%c", w[p]);
+ (++p == 3) ? (p = 0) : 0;
+}
+
+#endif
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
new file mode 100644
index 0000000..7e516bf
--- /dev/null
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale MCF5253 DEMO\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ u32 dramsize = 0;
+
+ /*
+ * Check to see if the SDRAM has already been initialized
+ * by a run control tool
+ */
+ if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
+ u32 RC, temp;
+
+ RC = (CONFIG_SYS_CLK / 1000000) >> 1;
+ RC = (RC * 15) >> 4;
+
+ /* Initialize DRAM Control Register: DCR */
+ mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
+ __asm__("nop");
+
+ mbar_writeLong(MCFSIM_DACR0, 0x00003224);
+ __asm__("nop");
+
+ /* Initialize DMR0 */
+ dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
+ temp = (dramsize - 1) & 0xFFFC0000;
+ mbar_writeLong(MCFSIM_DMR0, temp | 1);
+ __asm__("nop");
+
+ mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
+ mb();
+ __asm__("nop");
+
+ /* Write to this block to initiate precharge */
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+ mb();
+ __asm__("nop");
+
+ /* Set RE bit in DACR */
+ mbar_writeLong(MCFSIM_DACR0,
+ mbar_readLong(MCFSIM_DACR0) | 0x8000);
+ __asm__("nop");
+
+ /* Wait for at least 8 auto refresh cycles to occur */
+ udelay(500);
+
+ /* Finish the configuration by issuing the MRS */
+ mbar_writeLong(MCFSIM_DACR0,
+ mbar_readLong(MCFSIM_DACR0) | 0x0040);
+ __asm__("nop");
+
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+ mb();
+ }
+
+ return dramsize;
+}
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
+
+#ifdef CONFIG_CMD_IDE
+#include <ata.h>
+int ide_preinit(void)
+{
+ return (0);
+}
+
+void ide_set_reset(int idereset)
+{
+ atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+ long period;
+ /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
+ int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
+ {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
+ {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
+ {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
+ {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
+ };
+
+ if (idereset) {
+ /* control reset */
+ out_8(&ata->cr, 0);
+ udelay(100);
+ } else {
+ mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
+
+#define CALC_TIMING(t) (t + period - 1) / period
+ period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
+
+ /*ata->ton = CALC_TIMING (180); */
+ out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+ out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+ out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+ out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+ out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+ /* IORDY enable */
+ out_8(&ata->cr, 0x40);
+ udelay(2000);
+ /* IORDY enable */
+ setbits_8(&ata->cr, 0x01);
+ }
+}
+#endif /* CONFIG_CMD_IDE */
+
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
diff --git a/board/freescale/m5253demo/u-boot.lds b/board/freescale/m5253demo/u-boot.lds
new file mode 100644
index 0000000..cd3d70a
--- /dev/null
+++ b/board/freescale/m5253demo/u-boot.lds
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf52x2/start.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss*)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m5253evbe/Kconfig b/board/freescale/m5253evbe/Kconfig
new file mode 100644
index 0000000..d97b87c
--- /dev/null
+++ b/board/freescale/m5253evbe/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5253EVBE
+
+config SYS_CPU
+ default "mcf52x2"
+
+config SYS_BOARD
+ default "m5253evbe"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M5253EVBE"
+
+endif
diff --git a/board/freescale/m5253evbe/MAINTAINERS b/board/freescale/m5253evbe/MAINTAINERS
new file mode 100644
index 0000000..74acd1e
--- /dev/null
+++ b/board/freescale/m5253evbe/MAINTAINERS
@@ -0,0 +1,6 @@
+M5253EVBE BOARD
+#M: Hayden Fraser <Hayden.Fraser@freescale.com>
+S: Orphan (since 2014-06)
+F: board/freescale/m5253evbe/
+F: include/configs/M5253EVBE.h
+F: configs/M5253EVBE_defconfig
diff --git a/board/freescale/m5253evbe/Makefile b/board/freescale/m5253evbe/Makefile
new file mode 100644
index 0000000..8c55075
--- /dev/null
+++ b/board/freescale/m5253evbe/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m5253evbe.o
diff --git a/board/freescale/m5253evbe/README b/board/freescale/m5253evbe/README
new file mode 100644
index 0000000..f51609f
--- /dev/null
+++ b/board/freescale/m5253evbe/README
@@ -0,0 +1,103 @@
+Freescale Amadeus Plus M5253EVBE board
+======================================
+
+Hayden Fraser(Hayden.Fraser@freescale.com)
+Created 06/05/2007
+===========================================
+
+
+1. SWITCH SETTINGS
+==================
+1.1 N/A
+
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ SDR: 0x00000000-0x00ffffff
+ SRAM0: 0x20010000-0x20017fff
+ SRAM1: 0x20000000-0x2000ffff
+ MBAR1: 0x10000000-0x4fffffff
+ MBAR2: 0x80000000-0xCfffffff
+ Flash: 0xffe00000-0xffffffff
+
+3. DEFINITIONS AND COMPILATION
+==============================
+3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h
+ CONFIG_MCF52x2 Processor family
+ CONFIG_MCF5253 MCF5253 specific
+ CONFIG_M5253EVBE Amadeus Plus board specific
+ CONFIG_SYS_CLK Define Amadeus Plus CPU Clock
+ CONFIG_SYS_MBAR MBAR base address
+ CONFIG_SYS_MBAR2 MBAR2 base address
+
+3.2 Compilation
+ export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf-
+ cd u-boot-1-2-x
+ make distclean
+ make M5253EVBE_config
+ make
+
+
+4. SCREEN DUMP
+==============
+4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00)
+
+CPU: Freescale Coldfire MCF5253 at 62 MHz
+Board: Freescale MCF5253 EVBE
+DRAM: 16 MB
+FLASH: 2 MB
+In: serial
+Out: serial
+Err: serial
+=> flinfo
+
+Bank # 1: CFI conformant FLASH (16 x 16) Size: 2 MB in 35 Sectors
+ AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49
+ Erase timeout: 16384 ms, write timeout: 1 ms
+
+ Sector Start Addresses:
+ FFE00000 RO FFE04000 RO FFE06000 RO FFE08000 RO FFE10000 RO
+ FFE20000 FFE30000 FFE40000 FFE50000 FFE60000
+ FFE70000 FFE80000 FFE90000 FFEA0000 FFEB0000
+ FFEC0000 FFED0000 FFEE0000 FFEF0000 FFF00000
+ FFF10000 FFF20000 FFF30000 FFF40000 FFF50000
+ FFF60000 FFF70000 FFF80000 FFF90000 FFFA0000
+ FFFB0000 FFFC0000 FFFD0000 FFFE0000 FFFF0000
+
+=> bdinfo
+boot_params = 0x00F62F90
+memstart = 0x00000000
+memsize = 0x01000000
+flashstart = 0xFFE00000
+flashsize = 0x00200000
+flashoffset = 0x00000000
+baudrate = 19200 bps
+
+=> printenv
+bootdelay=5
+baudrate=19200
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 134/8188 bytes
+=> saveenv
+Saving Environment to Flash...
+Un-Protected 1 sectors
+Erasing Flash...
+. done
+Erased 1 sectors
+Writing to Flash... done
+Protected 1 sectors
+=>
+
+5. COMPILER
+-----------
+To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture
+compiler set (freescale-coldfire-4.1-elf) from www.codesourcery.com was used.
+You can download it from:http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
+codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
diff --git a/board/freescale/m5253evbe/config.mk b/board/freescale/m5253evbe/config.mk
new file mode 100644
index 0000000..1af25e1
--- /dev/null
+++ b/board/freescale/m5253evbe/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffe00000
diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c
new file mode 100644
index 0000000..15ff755
--- /dev/null
+++ b/board/freescale/m5253evbe/m5253evbe.c
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale MCF5253 EVBE\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ /*
+ * Check to see if the SDRAM has already been initialized
+ * by a run control tool
+ */
+ if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
+ u32 RC, dramsize;
+
+ RC = (CONFIG_SYS_CLK / 1000000) >> 1;
+ RC = (RC * 15) >> 4;
+
+ /* Initialize DRAM Control Register: DCR */
+ mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
+ asm("nop");
+
+ mbar_writeLong(MCFSIM_DACR0, 0x00002320);
+ asm("nop");
+
+ /* Initialize DMR0 */
+ dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
+ mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
+ asm("nop");
+
+ mbar_writeLong(MCFSIM_DACR0, 0x00002328);
+ asm("nop");
+
+ /* Write to this block to initiate precharge */
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+ asm("nop");
+
+ /* Set RE bit in DACR */
+ mbar_writeLong(MCFSIM_DACR0,
+ mbar_readLong(MCFSIM_DACR0) | 0x8000);
+ asm("nop");
+
+ /* Wait for at least 8 auto refresh cycles to occur */
+ udelay(500);
+
+ /* Finish the configuration by issuing the MRS */
+ mbar_writeLong(MCFSIM_DACR0,
+ mbar_readLong(MCFSIM_DACR0) | 0x0040);
+ asm("nop");
+
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+ }
+
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
+
+#ifdef CONFIG_CMD_IDE
+#include <ata.h>
+int ide_preinit(void)
+{
+ return (0);
+}
+
+void ide_set_reset(int idereset)
+{
+ atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+ long period;
+ /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
+ int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
+ {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
+ {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
+ {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
+ {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
+ };
+
+ if (idereset) {
+ /* control reset */
+ out_8(&ata->cr, 0);
+ udelay(100);
+ } else {
+ mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
+
+#define CALC_TIMING(t) (t + period - 1) / period
+ period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
+
+ /*ata->ton = CALC_TIMING (180); */
+ out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+ out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+ out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+ out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+ out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+ /* IORDY enable */
+ out_8(&ata->cr, 0x40);
+ udelay(2000);
+ /* IORDY enable */
+ setbits_8(&ata->cr, 0x01);
+ }
+}
+#endif /* CONFIG_CMD_IDE */
diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds
new file mode 100644
index 0000000..e91b7e1
--- /dev/null
+++ b/board/freescale/m5253evbe/u-boot.lds
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ .text :
+ {
+ arch/m68k/cpu/mcf52x2/start.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m5272c3/Kconfig b/board/freescale/m5272c3/Kconfig
new file mode 100644
index 0000000..aee0b23
--- /dev/null
+++ b/board/freescale/m5272c3/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5272C3
+
+config SYS_CPU
+ default "mcf52x2"
+
+config SYS_BOARD
+ default "m5272c3"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M5272C3"
+
+endif
diff --git a/board/freescale/m5272c3/MAINTAINERS b/board/freescale/m5272c3/MAINTAINERS
new file mode 100644
index 0000000..e586630
--- /dev/null
+++ b/board/freescale/m5272c3/MAINTAINERS
@@ -0,0 +1,6 @@
+M5272C3 BOARD
+#M: -
+S: Maintained
+F: board/freescale/m5272c3/
+F: include/configs/M5272C3.h
+F: configs/M5272C3_defconfig
diff --git a/board/freescale/m5272c3/Makefile b/board/freescale/m5272c3/Makefile
new file mode 100644
index 0000000..10a45f1
--- /dev/null
+++ b/board/freescale/m5272c3/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m5272c3.o
diff --git a/board/freescale/m5272c3/config.mk b/board/freescale/m5272c3/config.mk
new file mode 100644
index 0000000..1af25e1
--- /dev/null
+++ b/board/freescale/m5272c3/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffe00000
diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c
new file mode 100644
index 0000000..3ed4a7d
--- /dev/null
+++ b/board/freescale/m5272c3/m5272c3.c
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+
+int checkboard (void) {
+ puts ("Board: ");
+ puts ("Freescale MCF5272C3 EVB\n");
+ return 0;
+ };
+
+phys_size_t initdram (int board_type) {
+ sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
+
+ out_be16(&sdp->sdram_sdtr, 0xf539);
+ out_be16(&sdp->sdram_sdcr, 0x4211);
+
+ /* Dummy write to start SDRAM */
+ *((volatile unsigned long *)0) = 0;
+
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ };
+
+int testdram (void) {
+ /* TODO: XXX XXX XXX */
+ printf ("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/freescale/m5272c3/u-boot.lds b/board/freescale/m5272c3/u-boot.lds
new file mode 100644
index 0000000..e91b7e1
--- /dev/null
+++ b/board/freescale/m5272c3/u-boot.lds
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ .text :
+ {
+ arch/m68k/cpu/mcf52x2/start.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m5275evb/Kconfig b/board/freescale/m5275evb/Kconfig
new file mode 100644
index 0000000..5a6de9c
--- /dev/null
+++ b/board/freescale/m5275evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5275EVB
+
+config SYS_CPU
+ default "mcf52x2"
+
+config SYS_BOARD
+ default "m5275evb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M5275EVB"
+
+endif
diff --git a/board/freescale/m5275evb/MAINTAINERS b/board/freescale/m5275evb/MAINTAINERS
new file mode 100644
index 0000000..4e6dbb1
--- /dev/null
+++ b/board/freescale/m5275evb/MAINTAINERS
@@ -0,0 +1,6 @@
+M5275EVB BOARD
+#M: -
+S: Maintained
+F: board/freescale/m5275evb/
+F: include/configs/M5275EVB.h
+F: configs/M5275EVB_defconfig
diff --git a/board/freescale/m5275evb/Makefile b/board/freescale/m5275evb/Makefile
new file mode 100644
index 0000000..d285c14
--- /dev/null
+++ b/board/freescale/m5275evb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m5275evb.o
diff --git a/board/freescale/m5275evb/config.mk b/board/freescale/m5275evb/config.mk
new file mode 100644
index 0000000..1af25e1
--- /dev/null
+++ b/board/freescale/m5275evb/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffe00000
diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
new file mode 100644
index 0000000..16083d1
--- /dev/null
+++ b/board/freescale/m5275evb/m5275evb.c
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+#define PERIOD 13 /* system bus period in ns */
+#define SDRAM_TREFI 7800 /* in ns */
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale MCF5275 EVB\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
+ gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+
+ /* Enable SDRAM */
+ out_be16(&gpio_reg->par_sdram, 0x3FF);
+
+ /* Set up chip select */
+ out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
+
+ /* Set up timing */
+ out_be32(&sdp->sdcfg1, 0x83711630);
+ out_be32(&sdp->sdcfg2, 0x46770000);
+
+ /* Enable clock */
+ out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
+
+ /* Set precharge */
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+
+ /* Dummy write to start SDRAM */
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+ /* Send LEMR */
+ setbits_be32(&sdp->sdmr,
+ MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
+ MCF_SDRAMC_SDMR_CMD);
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+ /* Send LMR */
+ out_be32(&sdp->sdmr, 0x058d0000);
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop sending commands */
+ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
+
+ /* Set precharge */
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop manual precharge, send 2 IREF */
+ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+
+ out_be32(&sdp->sdmr, 0x018d0000);
+ *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+
+ /* Stop sending commands */
+ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
+ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
+
+ /* Turn on auto refresh, lock SDMR */
+ out_be32(&sdp->sdcr,
+ MCF_SDRAMC_SDCR_CKE
+ | MCF_SDRAMC_SDCR_REF
+ | MCF_SDRAMC_SDCR_MUX(1)
+ /* 1 added to round up */
+ | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
+ | MCF_SDRAMC_SDCR_DQS_OE(0x3));
+
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/freescale/m5275evb/u-boot.lds b/board/freescale/m5275evb/u-boot.lds
new file mode 100644
index 0000000..3112cbe
--- /dev/null
+++ b/board/freescale/m5275evb/u-boot.lds
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ .text :
+ {
+ arch/m68k/cpu/mcf52x2/start.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m5282evb/Kconfig b/board/freescale/m5282evb/Kconfig
new file mode 100644
index 0000000..2ffdd52
--- /dev/null
+++ b/board/freescale/m5282evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5282EVB
+
+config SYS_CPU
+ default "mcf52x2"
+
+config SYS_BOARD
+ default "m5282evb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M5282EVB"
+
+endif
diff --git a/board/freescale/m5282evb/MAINTAINERS b/board/freescale/m5282evb/MAINTAINERS
new file mode 100644
index 0000000..305e748
--- /dev/null
+++ b/board/freescale/m5282evb/MAINTAINERS
@@ -0,0 +1,6 @@
+M5282EVB BOARD
+#M: -
+S: Maintained
+F: board/freescale/m5282evb/
+F: include/configs/M5282EVB.h
+F: configs/M5282EVB_defconfig
diff --git a/board/freescale/m5282evb/Makefile b/board/freescale/m5282evb/Makefile
new file mode 100644
index 0000000..dab8f72
--- /dev/null
+++ b/board/freescale/m5282evb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m5282evb.o
diff --git a/board/freescale/m5282evb/config.mk b/board/freescale/m5282evb/config.mk
new file mode 100644
index 0000000..e2ac27e
--- /dev/null
+++ b/board/freescale/m5282evb/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xFFE00000
diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c
new file mode 100644
index 0000000..39f12fb
--- /dev/null
+++ b/board/freescale/m5282evb/m5282evb.c
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard (void)
+{
+ puts ("Board: Freescale M5282EVB Evaluation Board\n");
+ return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+ u32 dramsize, i, dramclk;
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
+ {
+ dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
+
+ /* Initialize DRAM Control Register: DCR */
+ MCFSDRAMC_DCR = (0
+ | MCFSDRAMC_DCR_RTIM_6
+ | MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
+ asm("nop");
+
+ /* Initialize DACR0 */
+ MCFSDRAMC_DACR0 = (0
+ | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
+ | MCFSDRAMC_DACR_CASL(1)
+ | MCFSDRAMC_DACR_CBM(3)
+ | MCFSDRAMC_DACR_PS_32);
+ asm("nop");
+
+ /* Initialize DMR0 */
+ MCFSDRAMC_DMR0 = (0
+ | ((dramsize - 1) & 0xFFFC0000)
+ | MCFSDRAMC_DMR_V);
+ asm("nop");
+
+ /* Set IP (bit 3) in DACR */
+ MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
+ asm("nop");
+
+ /* Wait 30ns to allow banks to precharge */
+ for (i = 0; i < 5; i++) {
+ asm ("nop");
+ }
+
+ /* Write to this block to initiate precharge */
+ *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+ asm("nop");
+
+ /* Set RE (bit 15) in DACR */
+ MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
+ asm("nop");
+
+ /* Wait for at least 8 auto refresh cycles to occur */
+ for (i = 0; i < 2000; i++) {
+ asm(" nop");
+ }
+
+ /* Finish the configuration by issuing the IMRS. */
+ MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
+ asm("nop");
+
+ /* Write to the SDRAM Mode Register */
+ *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+ }
+ return dramsize;
+}
diff --git a/board/freescale/m5282evb/u-boot.lds b/board/freescale/m5282evb/u-boot.lds
new file mode 100644
index 0000000..ce62ee9
--- /dev/null
+++ b/board/freescale/m5282evb/u-boot.lds
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ .text :
+ {
+ arch/m68k/cpu/mcf52x2/start.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m53017evb/Kconfig b/board/freescale/m53017evb/Kconfig
new file mode 100644
index 0000000..8ab89e5
--- /dev/null
+++ b/board/freescale/m53017evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M53017EVB
+
+config SYS_CPU
+ default "mcf532x"
+
+config SYS_BOARD
+ default "m53017evb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M53017EVB"
+
+endif
diff --git a/board/freescale/m53017evb/MAINTAINERS b/board/freescale/m53017evb/MAINTAINERS
new file mode 100644
index 0000000..700b6f7
--- /dev/null
+++ b/board/freescale/m53017evb/MAINTAINERS
@@ -0,0 +1,6 @@
+M53017EVB BOARD
+M: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+S: Maintained
+F: board/freescale/m53017evb/
+F: include/configs/M53017EVB.h
+F: configs/M53017EVB_defconfig
diff --git a/board/freescale/m53017evb/Makefile b/board/freescale/m53017evb/Makefile
new file mode 100644
index 0000000..bc4bf4a
--- /dev/null
+++ b/board/freescale/m53017evb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m53017evb.o
diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README
new file mode 100644
index 0000000..84fc1ec
--- /dev/null
+++ b/board/freescale/m53017evb/README
@@ -0,0 +1,180 @@
+Freescale MCF53017EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created 10/22/08
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m53017evb/m53017evb.c Dram setup
+- board/freescale/m53017evb/mii.c Mii access
+- board/freescale/m53017evb/Makefile Makefile
+- board/freescale/m53017evb/config.mk config make
+- board/freescale/m53017evb/u-boot.lds Linker description
+
+- arch/m68k/cpu/mcf532x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
+- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf532x/speed.c system, flexbus, and cpu clock
+- arch/m68k/cpu/mcf532x/Makefile Makefile
+- arch/m68k/cpu/mcf532x/config.mk config make
+- arch/m68k/cpu/mcf532x/start.S start up assembly code
+
+- doc/README.m53017evb This readme file
+
+- drivers/net/mcffec.c ColdFire common FEC driver
+- drivers/net/mcfmii.c ColdFire common Mii driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+- drivers/rtc/mcfrtc.c Realtime clock Driver
+
+- include/asm-m68k/bitops.h Bit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/fec.h FEC structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5301x.h mcf5301x specific header file
+- include/asm-m68k/io.h io functions
+- include/asm-m68k/m532x.h mcf5301x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h header file
+- include/asm-m68k/ptrace.h Exception structure
+- include/asm-m68k/rtc.h Realtime clock header file
+- include/asm-m68k/string.h String function export
+- include/asm-m68k/timer.h Timer structure and definition
+- include/asm-m68k/types.h Data types definition
+- include/asm-m68k/uart.h Uart structure and definition
+- include/asm-m68k/u-boot.h u-boot structure
+
+- include/configs/M53017EVB.h Board specific configuration file
+
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c Exception init code
+
+1 MCF5301x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M53017EVB Development Board
+CONFIG_MCF5301x -- define for all MCF5301x CPUs
+CONFIG_M53015 -- define for MCF53015 CPUs
+CONFIG_M53017EVB -- define for M53017EVB board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_MCFRTC -- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
+RTC_DEBUG -- define to show RTC debug message
+CONFIG_CMD_DATE -- enable to use date feature in u-boot
+
+CONFIG_MCFFEC -- define to use common CF FEC driver
+CONFIG_MII -- enable to use MII driver
+CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN --
+CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP -- set FEC timeout loop
+
+CONFIG_MCFTMR -- define to use DMA timer
+CONFIG_MCFPIT -- define to use PIT timer
+
+CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
+CONFIG_HARD_I2C -- define for I2C hardware support
+CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED -- define for I2C speed
+CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
+CONFIG_SYS_IMMR -- define for MBAR offset
+
+CONFIG_SYS_MBAR -- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM
+
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ Flash: 0x00000000-0x3FFFFFFF (1024MB)
+ DDR: 0x40000000-0x7FFFFFFF (1024MB)
+ SRAM: 0x80000000-0x8FFFFFFF (256MB)
+ IP: 0xFC000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ Flash0: 0x00000000-0x00FFFFFF (16MB)
+ DDR: 0x40000000-0x4FFFFFFF (256MB)
+ SRAM: 0x80000000-0x80007FFF (32KB)
+ IP: 0xFC000000-0xFC0FFFFF (64KB)
+
+3. COMPILATION
+==============
+3.1 To create U-Boot the gcc-4.x-xx compiler set (ColdFire ELF or
+uClinux version) from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix
+ cd u-boot
+ make distclean
+ make M53017EVB_config
+ make
+
+4. SCREEN DUMP
+==============
+4.1 M53017EVB Development board
+ (NOTE: May not show exactly the same)
+
+U-Boot 2008.10 (Oct 22 2007 - 11:07:57)
+
+CPU: Freescale MCF53015 (Mask:76 Version:0)
+ CPU CLK 240 Mhz BUS CLK 80 Mhz
+Board: Freescale M53017EVB
+I2C: ready
+DRAM: 64 MB
+FLASH: 16 MB
+In: serial
+Out: serial
+Err: serial
+NAND: 16 MiB
+Net: FEC0, FEC1
+-> print
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+hostname=M53017EVB
+netdev=eth0
+loadaddr=40010000
+u-boot=u-boot.bin
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 3ffff;era 0 3ffff;cp.b ${loadaddr} 0 ${filesize};save
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=65024k
+
+Environment size: 437/4092 bytes
+->
diff --git a/board/freescale/m53017evb/config.mk b/board/freescale/m53017evb/config.mk
new file mode 100644
index 0000000..c15a9cf
--- /dev/null
+++ b/board/freescale/m53017evb/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c
new file mode 100644
index 0000000..dbe886b
--- /dev/null
+++ b/board/freescale/m53017evb/m53017evb.c
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale M53017EVB\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+ u32 dramsize, i;
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+#ifdef CONFIG_SYS_SDRAM_BASE1
+ out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
+#endif
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+ udelay(500);
+
+ /* Issue PALL */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ asm("nop");
+
+ /* Perform two refresh cycles */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ asm("nop");
+
+ /* Issue LEMR */
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ asm("nop");
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ asm("nop");
+
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ asm("nop");
+
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+ asm("nop");
+
+ udelay(100);
+
+ return dramsize;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds
new file mode 100644
index 0000000..de8d09b
--- /dev/null
+++ b/board/freescale/m53017evb/u-boot.lds
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf532x/start.o (.text*)
+ arch/m68k/cpu/mcf532x/built-in.o (.text*)
+ arch/m68k/lib/built-in.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.sbss*)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m5329evb/Kconfig b/board/freescale/m5329evb/Kconfig
new file mode 100644
index 0000000..930fbba
--- /dev/null
+++ b/board/freescale/m5329evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5329EVB
+
+config SYS_CPU
+ default "mcf532x"
+
+config SYS_BOARD
+ default "m5329evb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M5329EVB"
+
+endif
diff --git a/board/freescale/m5329evb/MAINTAINERS b/board/freescale/m5329evb/MAINTAINERS
new file mode 100644
index 0000000..f4f103a
--- /dev/null
+++ b/board/freescale/m5329evb/MAINTAINERS
@@ -0,0 +1,7 @@
+M5329EVB BOARD
+M: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+S: Maintained
+F: board/freescale/m5329evb/
+F: include/configs/M5329EVB.h
+F: configs/M5329AFEE_defconfig
+F: configs/M5329BFEE_defconfig
diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile
new file mode 100644
index 0000000..d8dbafa
--- /dev/null
+++ b/board/freescale/m5329evb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m5329evb.o nand.o
diff --git a/board/freescale/m5329evb/config.mk b/board/freescale/m5329evb/config.mk
new file mode 100644
index 0000000..c15a9cf
--- /dev/null
+++ b/board/freescale/m5329evb/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c
new file mode 100644
index 0000000..1f77adf
--- /dev/null
+++ b/board/freescale/m5329evb/m5329evb.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale FireEngine 5329 EVB\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+ u32 dramsize, i;
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+ /* Issue PALL */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+ /* Issue LEMR */
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+
+ udelay(500);
+
+ /* Issue PALL */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+ /* Perform two refresh cycles */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+
+ udelay(100);
+
+ return dramsize;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
new file mode 100644
index 0000000..8d88bc0
--- /dev/null
+++ b/board/freescale/m5329evb/nand.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NAND)
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+
+#define SET_CLE 0x10
+#define SET_ALE 0x08
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+ IO_ADDR_W &= ~(SET_ALE | SET_CLE);
+
+ if (ctrl & NAND_NCE)
+ *nCE &= 0xFFFB;
+ else
+ *nCE |= 0x0004;
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= SET_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= SET_ALE;
+
+ this->IO_ADDR_W = (void *)IO_ADDR_W;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ /*
+ * set up pin configuration - enabled 2nd output buffer's signals
+ * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
+ * to use nCE signal
+ */
+ clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+ setbits_8(&gpio->pddr_timer, 0x08);
+ setbits_8(&gpio->ppd_timer, 0x08);
+ out_8(&gpio->pclrr_timer, 0);
+ out_8(&gpio->podr_timer, 0);
+
+ nand->chip_delay = 60;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = nand_hwcontrol;
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds
new file mode 100644
index 0000000..097ac2e
--- /dev/null
+++ b/board/freescale/m5329evb/u-boot.lds
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf532x/start.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.sbss*)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m5373evb/Kconfig b/board/freescale/m5373evb/Kconfig
new file mode 100644
index 0000000..67d049d
--- /dev/null
+++ b/board/freescale/m5373evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5373EVB
+
+config SYS_CPU
+ default "mcf532x"
+
+config SYS_BOARD
+ default "m5373evb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M5373EVB"
+
+endif
diff --git a/board/freescale/m5373evb/MAINTAINERS b/board/freescale/m5373evb/MAINTAINERS
new file mode 100644
index 0000000..5db0b34
--- /dev/null
+++ b/board/freescale/m5373evb/MAINTAINERS
@@ -0,0 +1,6 @@
+M5373EVB BOARD
+M: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+S: Maintained
+F: board/freescale/m5373evb/
+F: include/configs/M5373EVB.h
+F: configs/M5373EVB_defconfig
diff --git a/board/freescale/m5373evb/Makefile b/board/freescale/m5373evb/Makefile
new file mode 100644
index 0000000..d34e327
--- /dev/null
+++ b/board/freescale/m5373evb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m5373evb.o nand.o
diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README
new file mode 100644
index 0000000..52eac7b
--- /dev/null
+++ b/board/freescale/m5373evb/README
@@ -0,0 +1,326 @@
+Freescale MCF5373EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created 11/08/07
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m5373evb/m5373evb.c Dram setup
+- board/freescale/m5373evb/mii.c Mii access
+- board/freescale/m5373evb/Makefile Makefile
+- board/freescale/m5373evb/config.mk config make
+- board/freescale/m5373evb/u-boot.lds Linker description
+
+- arch/m68k/cpu/mcf532x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs
+- arch/m68k/cpu/mcf532x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf532x/Makefile Makefile
+- arch/m68k/cpu/mcf532x/config.mk config make
+- arch/m68k/cpu/mcf532x/start.S start up assembly code
+
+- doc/README.m5373evb This readme file
+
+- drivers/net/mcffec.c ColdFire common FEC driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+- drivers/rtc/mcfrtc.c Realtime clock Driver
+
+- include/asm-m68k/bitops.h Bit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/fec.h FEC structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and driver macros
+- include/asm-m68k/immap_532x.h mcf532x specific header file
+- include/asm-m68k/io.h io functions
+- include/asm-m68k/m532x.h mcf532x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h header file
+- include/asm-m68k/ptrace.h Exception structure
+- include/asm-m68k/rtc.h Realtime clock header file
+- include/asm-m68k/string.h String function export
+- include/asm-m68k/timer.h Timer structure and definition
+- include/asm-m68k/types.h Data types definition
+- include/asm-m68k/uart.h Uart structure and definition
+- include/asm-m68k/u-boot.h u-boot structure
+
+- include/configs/M5373EVB.h Board specific configuration file
+
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c Exception init code
+
+1 MCF5373 specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M5373EVB Development Board
+CONFIG_MCF532x -- define for all MCF532x CPUs
+CONFIG_M5373 -- define for all Freescale MCF5373 CPUs
+CONFIG_M5373EVB -- define for M5373EVB board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_MCFRTC -- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
+RTC_DEBUG -- define to show RTC debug message
+CONFIG_CMD_DATE -- enable to use date feature in u-boot
+
+CONFIG_MCFFEC -- define to use common CF FEC driver
+CONFIG_MII -- enable to use MII driver
+CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
+CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP -- set FEC timeout loop
+
+CONFIG_MCFTMR -- define to use DMA timer
+CONFIG_MCFPIT -- define to use PIT timer
+
+CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
+CONFIG_HARD_I2C -- define for I2C hardware support
+CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED -- define for I2C speed
+CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
+CONFIG_SYS_IMMR -- define for MBAR offset
+
+CONFIG_SYS_MBAR -- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM
+
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ Flash: 0x00000000-0x3FFFFFFF (1024MB)
+ DDR: 0x40000000-0x7FFFFFFF (1024MB)
+ SRAM: 0x80000000-0x8FFFFFFF (256MB)
+ IP: 0xF0000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ Flash0: 0x00000000-0x00FFFFFF (16MB)
+
+ DDR: 0x40000000-0x4FFFFFFF (256MB)
+ SRAM: 0x80000000-0x80007FFF (32KB)
+ IP: 0xFC000000-0xFC0FFFFF (64KB)
+
+3. COMPILATION
+==============
+3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or
+uClinux version) from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix
+ cd u-boot-1.x.x
+ make distclean
+ make M5373EVB_config
+ make
+
+4. SCREEN DUMP
+==============
+4.1 M5373EVB Development board
+ (NOTE: May not show exactly the same)
+
+U-Boot 1.3.0 (Nov 8 2007 - 12:44:08)
+
+CPU: Freescale MCF5373 (Mask:65 Version:1)
+ CPU CLK 240 Mhz BUS CLK 80 Mhz
+Board: Freescale FireEngine 5373 EVB
+I2C: ready
+DRAM: 32 MB
+FLASH: 2 MB
+In: serial
+Out: serial
+Err: serial
+NAND: 16 MiB
+Net: FEC0
+-> print
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+hostname=M5373EVB
+netdev=eth0
+loadaddr=40010000
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
+ethact=FEC0
+u-boot=u-boot.bin
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=261632k
+
+Environment size: 401/8188 bytes
+-> bdinfo
+memstart = 0x40000000
+memsize = 0x02000000
+flashstart = 0x00000000
+flashsize = 0x00200000
+flashoffset = 0x00000000
+sramstart = 0x80000000
+sramsize = 0x00008000
+mbar = 0xFC000000
+busfreq = 80 MHz
+ethaddr = 00:E0:0C:BC:E5:60
+ip_addr = 192.168.1.3
+baudrate = 115200 bps
+->
+-> help
+? - alias for 'help'
+base - print or set address offset
+bdinfo - print Board Info structure
+boot - boot default, i.e., run 'bootcmd'
+bootd - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm - boot application image from memory
+bootp - boot image via network using BootP/TFTP protocol
+bootvx - Boot vxWorks from an ELF image
+cmp - memory compare
+coninfo - print console devices and information
+cp - memory copy
+crc32 - checksum calculation
+date - get/set/reset date & time
+dcache - enable or disable data cache
+echo - echo args to console
+erase - erase FLASH memory
+flinfo - print FLASH memory information
+go - start application at address 'addr'
+help - print online help
+i2c - I2C sub-system
+icache - enable or disable instruction cache
+iminfo - print header information for application image
+imls - list all images found in flash
+itest - return true/false on integer compare
+loadb - load binary file over serial line (kermit mode)
+loads - load S-Record file over serial line
+loady - load binary file over serial line (ymodem mode)
+loop - infinite loop on address range
+ls - list files in a directory (default /)
+md - memory display
+mii - MII utility commands
+mm - memory modify (auto-incrementing)
+mtest - simple RAM test
+mw - memory write (fill)
+nand - NAND sub-system
+nboot - boot from NAND device
+nfs - boot image via network using NFS protocol
+nm - memory modify (constant address)
+ping - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset - Perform RESET of the CPU
+run - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv - set environment variables
+sleep - delay execution for some time
+source - run script from memory
+tftpboot- boot image via network using TFTP protocol
+version - print monitor version
+-> tftp 0x40800000 uImage
+Using FEC0 device
+TFTP from server 192.168.1.3; our IP address is 192.168.1.3 Filename 'uImage'.
+Load address: 0x40800000
+Loading: #################################################################
+ #################################################################
+ ##########
+done
+Bytes transferred = 2053270 (1f5496 hex)
+-> bootm 0x40800000
+## Booting image at 40800000 ...
+ Image Name: Linux Kernel Image
+ Created: 2007-11-07 20:33:08 UTC
+ Image Type: M68K Linux Kernel Image (gzip compressed)
+ Data Size: 2053206 Bytes = 2 MB
+ Load Address: 40020000
+ Entry Point: 40020000
+ Verifying Checksum ... OK
+ Uncompressing Kernel Image ... OK
+Linux version 2.6.22-uc1 (mattw@loa) (gcc version 4.2.1 (Sourcery G++ Lite 4.2-7
+
+
+uClinux/COLDFIRE(m537x)
+COLDFIRE port done by Greg Ungerer, gerg@snapgear.com Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne Built 1 zonelists. Total pages: 8128 Kernel command line: rootfstype=romfs PID hash table entries: 128 (order: 7, 512 bytes) Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory available: 28092k/32768k RAM, (1788k kernel code, 244k data) Mount-cache hash table entries: 512
+NET: Registered protocol family 16
+USB-MCF537x: (HOST module) EHCI device is registered
+USB-MCF537x: (OTG module) EHCI device is registered
+USB-MCF537x: (OTG module) UDC device is registered
+usbcore: registered new interface driver usbfs
+usbcore: registered new interface driver hub
+usbcore: registered new device driver usb
+NET: Registered protocol family 2
+IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
+TCP: Hash tables configured (established 1024 bind 1024) TCP reno registered
+JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
+io scheduler noop registered
+io scheduler cfq registered (default)
+ColdFire internal UART serial driver version 1.00 ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
+ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
+ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+loop: module loaded
+nbd: registered device at major 43
+usbcore: registered new interface driver ub FEC ENET Version 0.2
+fec: PHY @ 0x1, ID 0x20005c90 -- DP83848
+eth0: ethernet 00:e0:0c:bc:e5:60
+uclinux[mtd]: RAM probe address=0x4021c22c size=0x22b000 Creating 1 MTD partitions on "RAM":
+0x00000000-0x0022b000 : "ROMfs"
+uclinux[mtd]: set ROMfs to be root filesystem NAND device: Manufacturer ID: 0x20, Chip ID: 0x73 (ST Micro NAND 16MiB 3,3V 8-b) Scanning device for bad blocks Creating 1 MTD partitions on "NAND 16MiB 3,3V 8-bit":
+0x00000000-0x01000000 : "M53xx flash partition 1"
+QSPI: spi->max_speed_hz 300000
+QSPI: Baud set to 255
+SPI: Coldfire master initialized
+M537x - Disable UART1 when using Audio
+udc: Freescale MCF53xx UDC driver version 27 October 2006 init
+udc: MCF53xx USB Device is found. ID=0x5 Rev=0x41 i2c /dev entries driver
+usbcore: registered new interface driver usbhid
+drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 17
+VFS: Mounted root (romfs filesystem) readonly.
+Freeing unused kernel memory: 64k freed (0x401f5000 - 0x40204000) init started: BusyBox v1.00 (2007.11.07-19:57+0000) multi-call binary?Setting e Mounting filesystems
+mount: Mounting devpts on /dev/pts failed: No such device
+mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory Starting syslogd and klogd Setting up networking on loopback device:
+Setting up networking on eth0:
+info, udhcpc (v0.9.9-pre) started
+eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
+debug, Sending discover...
+debug, Sending discover...
+debug, Sending select for 172.27.0.130...
+info, Lease of 172.27.0.130 obtained, lease time 43200 deleting routers
+route: SIOC[ADD|DEL]RT: No such process
+adding dns 172.27.0.1
+Starting the boa webserver:
+Setting time from ntp server: ntp.cs.strath.ac.uk
+ntp.cs.strath.ac.uk: Unknown host
+
+
+BusyBox v1.00 (2007.11.07-19:57+0000) Built-in shell (msh) Enter 'help' for a list of built-in commands.
+
+#
diff --git a/board/freescale/m5373evb/config.mk b/board/freescale/m5373evb/config.mk
new file mode 100644
index 0000000..c15a9cf
--- /dev/null
+++ b/board/freescale/m5373evb/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0
diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
new file mode 100644
index 0000000..bfcc4b2
--- /dev/null
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale FireEngine 5373 EVB\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+ u32 dramsize, i;
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+ /* Issue PALL */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+ /* Issue LEMR */
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+
+ udelay(500);
+
+ /* Issue PALL */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+ /* Perform two refresh cycles */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+
+ udelay(100);
+
+ return dramsize;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
new file mode 100644
index 0000000..92cef2a
--- /dev/null
+++ b/board/freescale/m5373evb/nand.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NAND)
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+
+#define SET_CLE 0x10
+#define SET_ALE 0x08
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtdinfo->priv;
+ volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+ IO_ADDR_W &= ~(SET_ALE | SET_CLE);
+
+ if (ctrl & NAND_NCE)
+ *nCE &= 0xFFFB;
+ else
+ *nCE |= 0x0004;
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= SET_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= SET_ALE;
+
+ this->IO_ADDR_W = (void *)IO_ADDR_W;
+
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+ clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
+
+ /*
+ * set up pin configuration - enabled 2nd output buffer's signals
+ * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
+ * to use nCE signal
+ */
+ clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+ setbits_8(&gpio->pddr_timer, 0x08);
+ setbits_8(&gpio->ppd_timer, 0x08);
+ out_8(&gpio->pclrr_timer, 0);
+ out_8(&gpio->podr_timer, 0);
+
+ nand->chip_delay = 60;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = nand_hwcontrol;
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/m5373evb/u-boot.lds b/board/freescale/m5373evb/u-boot.lds
new file mode 100644
index 0000000..8ef0620
--- /dev/null
+++ b/board/freescale/m5373evb/u-boot.lds
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf532x/start.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss*)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m54418twr/Kconfig b/board/freescale/m54418twr/Kconfig
new file mode 100644
index 0000000..4199a3f
--- /dev/null
+++ b/board/freescale/m54418twr/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M54418TWR
+
+config SYS_CPU
+ default "mcf5445x"
+
+config SYS_BOARD
+ default "m54418twr"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M54418TWR"
+
+endif
diff --git a/board/freescale/m54418twr/MAINTAINERS b/board/freescale/m54418twr/MAINTAINERS
new file mode 100644
index 0000000..f88aed9
--- /dev/null
+++ b/board/freescale/m54418twr/MAINTAINERS
@@ -0,0 +1,11 @@
+M54418TWR BOARD
+#M: -
+S: Maintained
+F: board/freescale/m54418twr/
+F: include/configs/M54418TWR.h
+F: configs/M54418TWR_defconfig
+F: configs/M54418TWR_nand_mii_defconfig
+F: configs/M54418TWR_nand_rmii_defconfig
+F: configs/M54418TWR_nand_rmii_lowfreq_defconfig
+F: configs/M54418TWR_serial_mii_defconfig
+F: configs/M54418TWR_serial_rmii_defconfig
diff --git a/board/freescale/m54418twr/Makefile b/board/freescale/m54418twr/Makefile
new file mode 100644
index 0000000..371c04a
--- /dev/null
+++ b/board/freescale/m54418twr/Makefile
@@ -0,0 +1,7 @@
+# Copyright 2010-2012 Freescale Semiconductor, Inc.
+# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m54418twr.o
diff --git a/board/freescale/m54418twr/config.mk b/board/freescale/m54418twr/config.mk
new file mode 100644
index 0000000..07f52e0
--- /dev/null
+++ b/board/freescale/m54418twr/config.mk
@@ -0,0 +1,7 @@
+# Copyright 2010-2012 Freescale Semiconductor, Inc.
+# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/m54418twr/m54418twr.c b/board/freescale/m54418twr/m54418twr.c
new file mode 100644
index 0000000..5375d16
--- /dev/null
+++ b/board/freescale/m54418twr/m54418twr.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ /*
+ * need to to:
+ * Check serial flash size. if 2mb evb, else 8mb demo
+ */
+ puts("Board: ");
+ puts("Freescale MCF54418 Tower System\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ u32 dramsize;
+
+#if defined(CONFIG_SERIAL_BOOT)
+ /*
+ * Serial Boot: The dram is already initialized in start.S
+ * only require to return DRAM size
+ */
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ ccm_t *ccm = (ccm_t *)MMAP_CCM;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ pm_t *pm = (pm_t *) MMAP_PM;
+ u32 i;
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+
+ out_8(&pm->pmcr0, 0x2E);
+ out_8(&gpio->mscr_sdram, 1);
+
+ clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF);
+ setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK);
+
+ out_be32(&sdram->rcrcr, 0x40000000);
+ out_be32(&sdram->padcr, 0x01030203);
+
+ out_be32(&sdram->cr00, 0x01010101);
+ out_be32(&sdram->cr01, 0x00000101);
+ out_be32(&sdram->cr02, 0x01010100);
+ out_be32(&sdram->cr03, 0x01010000);
+ out_be32(&sdram->cr04, 0x00010101);
+ out_be32(&sdram->cr06, 0x00010100);
+ out_be32(&sdram->cr07, 0x00000001);
+ out_be32(&sdram->cr08, 0x01000001);
+ out_be32(&sdram->cr09, 0x00000100);
+ out_be32(&sdram->cr10, 0x00010001);
+ out_be32(&sdram->cr11, 0x00000200);
+ out_be32(&sdram->cr12, 0x01000002);
+ out_be32(&sdram->cr13, 0x00000000);
+ out_be32(&sdram->cr14, 0x00000100);
+ out_be32(&sdram->cr15, 0x02000100);
+ out_be32(&sdram->cr16, 0x02000407);
+ out_be32(&sdram->cr17, 0x02030007);
+ out_be32(&sdram->cr18, 0x02000100);
+ out_be32(&sdram->cr19, 0x0A030203);
+ out_be32(&sdram->cr20, 0x00020708);
+ out_be32(&sdram->cr21, 0x00050008);
+ out_be32(&sdram->cr22, 0x04030002);
+ out_be32(&sdram->cr23, 0x00000004);
+ out_be32(&sdram->cr24, 0x020A0000);
+ out_be32(&sdram->cr25, 0x0C00000E);
+ out_be32(&sdram->cr26, 0x00002004);
+ out_be32(&sdram->cr28, 0x00100010);
+ out_be32(&sdram->cr29, 0x00100010);
+ out_be32(&sdram->cr31, 0x07990000);
+ out_be32(&sdram->cr40, 0x00000000);
+ out_be32(&sdram->cr41, 0x00C80064);
+ out_be32(&sdram->cr42, 0x44520002);
+ out_be32(&sdram->cr43, 0x00C80023);
+ out_be32(&sdram->cr45, 0x0000C350);
+ out_be32(&sdram->cr56, 0x04000000);
+ out_be32(&sdram->cr57, 0x03000304);
+ out_be32(&sdram->cr58, 0x40040000);
+ out_be32(&sdram->cr59, 0xC0004004);
+ out_be32(&sdram->cr60, 0x0642C000);
+ out_be32(&sdram->cr61, 0x00000642);
+ asm("tpf");
+
+ out_be32(&sdram->cr09, 0x01000100);
+
+ udelay(100);
+#endif
+ return dramsize;
+};
+
+int testdram(void)
+{
+ return 0;
+}
diff --git a/board/freescale/m54418twr/u-boot.lds b/board/freescale/m54418twr/u-boot.lds
new file mode 100644
index 0000000..5679d49
--- /dev/null
+++ b/board/freescale/m54418twr/u-boot.lds
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf5445x/start.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m54451evb/Kconfig b/board/freescale/m54451evb/Kconfig
new file mode 100644
index 0000000..f460e51
--- /dev/null
+++ b/board/freescale/m54451evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M54451EVB
+
+config SYS_CPU
+ default "mcf5445x"
+
+config SYS_BOARD
+ default "m54451evb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M54451EVB"
+
+endif
diff --git a/board/freescale/m54451evb/MAINTAINERS b/board/freescale/m54451evb/MAINTAINERS
new file mode 100644
index 0000000..52a2681
--- /dev/null
+++ b/board/freescale/m54451evb/MAINTAINERS
@@ -0,0 +1,7 @@
+M54451EVB BOARD
+#M: -
+S: Maintained
+F: board/freescale/m54451evb/
+F: include/configs/M54451EVB.h
+F: configs/M54451EVB_defconfig
+F: configs/M54451EVB_stmicro_defconfig
diff --git a/board/freescale/m54451evb/Makefile b/board/freescale/m54451evb/Makefile
new file mode 100644
index 0000000..700ea2a
--- /dev/null
+++ b/board/freescale/m54451evb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m54451evb.o
diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
new file mode 100644
index 0000000..d2ad42c
--- /dev/null
+++ b/board/freescale/m54451evb/m54451evb.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ /*
+ * need to to:
+ * Check serial flash size. if 2mb evb, else 8mb demo
+ */
+ puts("Board: ");
+ puts("Freescale M54451 EVB\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ u32 dramsize;
+#ifdef CONFIG_CF_SBF
+ /*
+ * Serial Boot: The dram is already initialized in start.S
+ * only require to return DRAM size
+ */
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+ u32 i;
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+ if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
+ (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
+ return dramsize;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
+
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
+
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
+
+ udelay(200);
+
+ /* Issue PALL */
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
+ __asm__("nop");
+
+ /* Perform two refresh cycles */
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+ __asm__("nop");
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+ __asm__("nop");
+
+ /* Issue LEMR */
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
+ __asm__("nop");
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
+ __asm__("nop");
+
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
+
+ udelay(100);
+#endif
+ return (dramsize);
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/freescale/m54451evb/u-boot.lds b/board/freescale/m54451evb/u-boot.lds
new file mode 100644
index 0000000..413ca53
--- /dev/null
+++ b/board/freescale/m54451evb/u-boot.lds
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf5445x/start.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m54455evb/Kconfig b/board/freescale/m54455evb/Kconfig
new file mode 100644
index 0000000..096bce8
--- /dev/null
+++ b/board/freescale/m54455evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M54455EVB
+
+config SYS_CPU
+ default "mcf5445x"
+
+config SYS_BOARD
+ default "m54455evb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M54455EVB"
+
+endif
diff --git a/board/freescale/m54455evb/MAINTAINERS b/board/freescale/m54455evb/MAINTAINERS
new file mode 100644
index 0000000..3788f5f
--- /dev/null
+++ b/board/freescale/m54455evb/MAINTAINERS
@@ -0,0 +1,10 @@
+M54455EVB BOARD
+M: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+S: Maintained
+F: board/freescale/m54455evb/
+F: include/configs/M54455EVB.h
+F: configs/M54455EVB_defconfig
+F: configs/M54455EVB_a66_defconfig
+F: configs/M54455EVB_i66_defconfig
+F: configs/M54455EVB_intel_defconfig
+F: configs/M54455EVB_stm33_defconfig
diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile
new file mode 100644
index 0000000..1c775fa
--- /dev/null
+++ b/board/freescale/m54455evb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m54455evb.o
diff --git a/board/freescale/m54455evb/README b/board/freescale/m54455evb/README
new file mode 100644
index 0000000..c70c4c5
--- /dev/null
+++ b/board/freescale/m54455evb/README
@@ -0,0 +1,409 @@
+Freescale MCF54455EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created 4/08/07
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init
+- board/freescale/m54455evb/flash.c Atmel and INTEL flash support
+- board/freescale/m54455evb/Makefile Makefile
+- board/freescale/m54455evb/config.mk config make
+- board/freescale/m54455evb/u-boot.lds Linker description
+
+- common/cmd_bdinfo.c Clock frequencies output
+- common/cmd_mii.c mii support
+
+- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf5445x/Makefile Makefile
+- arch/m68k/cpu/mcf5445x/config.mk config make
+- arch/m68k/cpu/mcf5445x/start.S start up assembly code
+
+- doc/README.m54455evb This readme file
+
+- drivers/net/mcffec.c ColdFire common FEC driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+
+- include/asm-m68k/bitops.h Bit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/fec.h FEC structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and driver macros
+- include/asm-m68k/immap_5445x.h mcf5445x specific header file
+- include/asm-m68k/io.h io functions
+- include/asm-m68k/m5445x.h mcf5445x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h header file
+- include/asm-m68k/ptrace.h Exception structure
+- include/asm-m68k/rtc.h Realtime clock header file
+- include/asm-m68k/string.h String function export
+- include/asm-m68k/timer.h Timer structure and definition
+- include/asm-m68k/types.h Data types definition
+- include/asm-m68k/uart.h Uart structure and definition
+- include/asm-m68k/u-boot.h u-boot structure
+
+- include/configs/M54455EVB.h Board specific configuration file
+
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c Exception init code
+
+- rtc/mcfrtc.c Realtime clock Driver
+
+1 MCF5445x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M54455EVB Development Board
+CONFIG_MCF5445x -- define for all MCF5445x CPUs
+CONFIG_M54455 -- define for all Freescale MCF54455 CPUs
+CONFIG_M54455EVB -- define for M54455EVB board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_MCFRTC -- define to use common CF RTC driver
+CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h
+CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency
+RTC_DEBUG -- define to show RTC debug message
+CONFIG_CMD_DATE -- enable to use date feature in u-boot
+
+CONFIG_MCFFEC -- define to use common CF FEC driver
+CONFIG_MII -- enable to use MII driver
+CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
+CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
+CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
+CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP -- set FEC timeout loop
+CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot
+
+CONFIG_ISO_PARTITION -- enable ISO read/write
+CONFIG_DOS_PARTITION -- enable DOS read/write
+CONFIG_IDE_RESET -- define ide_reset()
+CONFIG_IDE_PREINIT -- define ide_preinit()
+CONFIG_ATAPI -- define ATAPI support
+CONFIG_LBA48 -- define LBA48 (larger than 120GB) support
+CONFIG_SYS_IDE_MAXBUS -- define max channel
+CONFIG_SYS_IDE_MAXDEVICE -- define max devices per channel
+CONFIG_SYS_ATA_BASE_ADDR -- define ATA base address
+CONFIG_SYS_ATA_IDE0_OFFSET -- define ATA IDE0 offset
+CONFIG_SYS_ATA_DATA_OFFSET -- define ATA data IO
+CONFIG_SYS_ATA_REG_OFFSET -- define for normal register accesses
+CONFIG_SYS_ATA_ALT_OFFSET -- define for alternate registers
+CONFIG_SYS_ATA_STRIDE -- define for Interval between registers
+_IO_BASE -- define for IO base address
+
+CONFIG_MCFTMR -- define to use DMA timer
+CONFIG_MCFPIT -- define to use PIT timer
+
+CONFIG_SYS_FSL_I2C -- define to use FSL common I2C driver
+CONFIG_HARD_I2C -- define for I2C hardware support
+CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED -- define for I2C speed
+CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
+CONFIG_SYS_IMMR -- define for MBAR offset
+
+CONFIG_PCI -- define for PCI support
+CONFIG_PCI_PNP -- define for Plug n play support
+CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset
+CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset
+CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size
+CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset
+CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset
+CONFIG_SYS_PCI_IO_SIZE -- PCI IO size
+CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset
+CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset
+CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size
+
+CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
+
+CONFIG_SYS_MBAR -- define MBAR offset
+
+CONFIG_SYS_ATMEL_BOOT -- To determine the u-boot is booted from Atmel or Intel
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM
+
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+
+CONFIG_SYS_ATMEL_BASE -- defines the Atmel Flash base
+CONFIG_SYS_INTEL_BASE -- defines the Intel Flash base
+
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+CONFIG_SYS_SDRAM_BASE1 -- defines the DRAM Base 1
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ Flash: 0x00000000-0x3FFFFFFF (1024MB)
+ DDR: 0x40000000-0x7FFFFFFF (1024MB)
+ SRAM: 0x80000000-0x8FFFFFFF (256MB)
+ ATA: 0x90000000-0x9FFFFFFF (256MB)
+ PCI: 0xA0000000-0xBFFFFFFF (512MB)
+ FlexBus: 0xC0000000-0xDFFFFFFF (512MB)
+ IP: 0xF0000000-0xFFFFFFFF (256MB)
+
+2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ Atmel boot:
+ Flash0: 0x00000000-0x0007FFFF (512KB)
+ Flash1: 0x04000000-0x05FFFFFF (32MB)
+ Intel boot:
+ Flash0: 0x00000000-0x01FFFFFF (32MB)
+ Flash1: 0x04000000-0x0407FFFF (512KB)
+
+ CPLD: 0x08000000-0x08FFFFFF (16MB)
+ FPGA: 0x09000000-0x09FFFFFF (16MB)
+ DDR: 0x40000000-0x4FFFFFFF (256MB)
+ SRAM: 0x80000000-0x80007FFF (32KB)
+ IP: 0xFC000000-0xFC0FFFFF (64KB)
+
+3. SWITCH SETTINGS
+==================
+3.1 SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
+ SW1 Pin4: 0 - ULPI chip not in reset state or 1 - ULPI chip in reset state
+ SW1 Pin5: 0 - Full ATA Bus enabled, FEC Phy1 powered down
+ 1 - Upper 8 bits ATA data bus disabled, FEC PHY1 active
+ SW1 Pin6: 0 - FEC Phy0 active or 1 - FEC Phy0 powered down
+ SW1 Pin3: 0 - Boot from Atmel or 1 - INTEL
+
+4. COMPILATION
+==============
+4.1 To create U-Boot the gcc-4.1-32 compiler set (ColdFire ELF version)
+from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+4.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix
+ cd u-boot-1.x.x
+ make distclean
+ make M54455EVB_config, or - default to atmel 33Mhz input clock
+ make M54455EVB_atmel_config, or - default to atmel 33Mhz input clock
+ make M54455EVB_a33_config, or - default to atmel 33Mhz input clock
+ make M54455EVB_a66_config, or - default to atmel 66Mhz input clock
+ make M54455EVB_intel_config, or - default to intel 33Mhz input clock
+ make M54455EVB_i33_config, or - default to intel 33Mhz input clock
+ make M54455EVB_i66_config, or - default to intel 66Mhz input clock
+ make
+
+5. SCREEN DUMP
+==============
+5.1 M54455EVB Development board
+ Boot from Atmel (NOTE: May not show exactly the same)
+
+U-Boot 1.2.0-g98c80b46-dirty (Jul 26 2007 - 12:44:08)
+
+CPU: Freescale MCF54455 (Mask:48 Version:1)
+ CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 66 Mhz
+ PCI CLK 33 Mhz INP CLK 33 Mhz VCO CLK 533 Mhz
+Board: Freescale M54455 EVB
+I2C: ready
+DRAM: 256 MB
+FLASH: 16.5 MB
+In: serial
+Out: serial
+Err: serial
+Net: FEC0, FEC1
+IDE: Bus 0: not available
+-> print
+bootargs=root=/dev/ram rw
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+eth1addr=00:e0:0c:bc:e5:61
+hostname=M54455EVB
+netdev=eth0
+inpclk=33333333
+loadaddr=40010000
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save
+ethact=FEC0
+mtdids=nor0=M54455EVB-1
+mtdparts=M54455EVB-1:16m(user)
+u-boot=u-boot54455.bin
+filesize=292b4
+fileaddr=40010000
+gatewayip=192.168.1.1
+netmask=255.255.255.0
+ipaddr=192.168.1.3
+serverip=192.168.1.2
+stdin=serial
+stdout=serial
+stderr=serial
+mem=261632k
+
+Environment size: 563/8188 bytes
+-> bdinfo
+memstart = 0x40000000
+memsize = 0x10000000
+flashstart = 0x00000000
+flashsize = 0x01080000
+flashoffset = 0x00000000
+sramstart = 0x80000000
+sramsize = 0x00008000
+mbar = 0xFC000000
+busfreq = 133.333 MHz
+pcifreq = 33.333 MHz
+flbfreq = 66.666 MHz
+inpfreq = 33.333 MHz
+vcofreq = 533.333 MHz
+ethaddr = 00:E0:0C:BC:E5:60
+eth1addr = 00:E0:0C:BC:E5:61
+ip_addr = 192.168.1.3
+baudrate = 115200 bps
+->
+-> help
+? - alias for 'help'
+base - print or set address offset
+bdinfo - print Board Info structure
+boot - boot default, i.e., run 'bootcmd'
+bootd - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm - boot application image from memory
+bootp - boot image via network using BootP/TFTP protocol
+bootvx - Boot vxWorks from an ELF image
+cmp - memory compare
+coninfo - print console devices and information
+cp - memory copy
+crc32 - checksum calculation
+date - get/set/reset date & time
+dcache - enable or disable data cache
+diskboot- boot from IDE device
+echo - echo args to console
+erase - erase FLASH memory
+ext2load- load binary file from a Ext2 filesystem
+ext2ls - list files in a directory (default /)
+fatinfo - print information about filesystem
+fatload - load binary file from a dos filesystem
+fatls - list files in a directory (default /)
+flinfo - print FLASH memory information
+fsinfo - print information about filesystems
+fsload - load binary file from a filesystem image
+go - start application at address 'addr'
+help - print online help
+i2c - I2C sub-system
+icache - enable or disable instruction cache
+ide - IDE sub-system
+iminfo - print header information for application image
+imls - list all images found in flash
+itest - return true/false on integer compare
+loadb - load binary file over serial line (kermit mode)
+loads - load S-Record file over serial line
+loady - load binary file over serial line (ymodem mode)
+loop - infinite loop on address range
+ls - list files in a directory (default /)
+md - memory display
+mii - MII utility commands
+mm - memory modify (auto-incrementing)
+mtest - simple RAM test
+mw - memory write (fill)
+nfs - boot image via network using NFS protocol
+nm - memory modify (constant address)
+pci - list and access PCI Configuration Space
+ping - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset - Perform RESET of the CPU
+run - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv - set environment variables
+sleep - delay execution for some time
+source - run script from memory
+tftpboot- boot image via network using TFTP protocol
+version - print monitor version
+->bootm 4000000
+
+## Booting image at 04000000 ...
+ Image Name: Linux Kernel Image
+ Created: 2007-08-14 15:13:00 UTC
+ Image Type: M68K Linux Kernel Image (uncompressed)
+ Data Size: 2301952 Bytes = 2.2 MB
+ Load Address: 40020000
+ Entry Point: 40020000
+ Verifying Checksum ... OK
+OK
+Linux version 2.6.20-gfe5136d6-dirty (mattw@kea) (gcc version 4.2.0 20070318 (pr
+erelease) (Sourcery G++ Lite 4.2-20)) #108 Mon Aug 13 13:00:13 MDT 2007
+starting up linux startmem 0xc0254000, endmem 0xcfffffff, size 253MB
+Built 1 zonelists. Total pages: 32624
+Kernel command line: root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=ph
+ysmap-flash.0:5M(kernel)ro,-(jffs2)
+PID hash table entries: 1024 (order: 10, 4096 bytes)
+Console: colour dummy device 80x25
+Dentry cache hash table entries: 32768 (order: 4, 131072 bytes)
+Inode-cache hash table entries: 16384 (order: 3, 65536 bytes)
+Memory: 257496k/262136k available (1864k kernel code, 2440k data, 88k init)
+Mount-cache hash table entries: 1024
+NET: Registered protocol family 16
+SCSI subsystem initialized
+NET: Registered protocol family 2
+IP route cache hash table entries: 2048 (order: 0, 8192 bytes)
+TCP established hash table entries: 8192 (order: 2, 32768 bytes)
+TCP bind hash table entries: 4096 (order: 1, 16384 bytes)
+TCP: Hash tables configured (established 8192 bind 4096)
+TCP reno registered
+JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc.
+io scheduler noop registered
+io scheduler anticipatory registered
+io scheduler deadline registered
+io scheduler cfq registered (default)
+ColdFire internal UART serial driver version 1.00
+ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART
+ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART
+ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART
+RAMDISK driver initialized: 16 RAM disks of 64000K size 1024 blocksize
+loop: loaded (max 8 devices)
+FEC ENET Version 0.2
+fec: PHY @ 0x0, ID 0x20005ca2 -- DP83849
+eth0: ethernet 00:08:ee:00:e4:19
+physmap platform flash device: 01000000 at 04000000
+physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank
+ Intel/Sharp Extended Query Table at 0x0031
+Using buffer write method
+cfi_cmdset_0001: Erase suspend on write enabled
+2 cmdlinepart partitions found on MTD device physmap-flash.0
+Creating 2 MTD partitions on "physmap-flash.0":
+0x00000000-0x00500000 : "kernel"
+mtd: Giving out device 0 to kernel
+0x00500000-0x01000000 : "jffs2"
+mtd: Giving out device 1 to jffs2
+mice: PS/2 mouse device common for all mice
+i2c /dev entries driver
+TCP cubic registered
+NET: Registered protocol family 1
+NET: Registered protocol family 17
+NET: Registered protocol family 15
+VFS: Mounted root (jffs2 filesystem).
+Setting the hostname to freescale
+Mounting filesystems
+mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory
+Starting syslogd and klogd
+Setting up networking on loopback device:
+Setting up networking on eth0:
+eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX.
+Adding static route for default gateway to 172.27.255.254:
+Setting nameserver to 172.27.0.1 in /etc/resolv.conf:
+Starting inetd:
+/ #
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c
new file mode 100644
index 0000000..76b4322
--- /dev/null
+++ b/board/freescale/m54455evb/m54455evb.c
@@ -0,0 +1,213 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale M54455 EVB\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ u32 dramsize;
+#ifdef CONFIG_CF_SBF
+ /*
+ * Serial Boot: The dram is already initialized in start.S
+ * only require to return DRAM size
+ */
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
+#else
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+ u32 i;
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
+
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
+
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
+
+ /* Issue PALL */
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
+
+ /* Issue LEMR */
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
+
+ udelay(500);
+
+ /* Issue PALL */
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
+
+ /* Perform two refresh cycles */
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
+
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+
+ udelay(100);
+#endif
+ return (dramsize << 1);
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
+
+#if defined(CONFIG_CMD_IDE)
+#include <ata.h>
+
+int ide_preinit(void)
+{
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ u32 tmp;
+
+ tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
+ setbits_8(&gpio->par_fec, tmp);
+ tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
+ (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
+ setbits_be16(&gpio->par_feci2c, tmp);
+
+ setbits_be16(&gpio->par_ata,
+ GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
+ GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
+ GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
+ GPIO_PAR_ATA_IORDY_IORDY);
+ setbits_be16(&gpio->par_pci,
+ GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
+
+ return (0);
+}
+
+void ide_set_reset(int idereset)
+{
+ atac_t *ata = (atac_t *) MMAP_ATA;
+ long period;
+ /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
+ int piotms[5][9] = {
+ {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
+ {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
+ {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
+ {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
+ {25, 70, 20, 10, 20, 5, 10, 0, 35}
+ }; /* PIO 4 */
+
+ if (idereset) {
+ /* control reset */
+ out_8(&ata->cr, 0);
+ udelay(10000);
+ } else {
+#define CALC_TIMING(t) (t + period - 1) / period
+ period = 1000000000 / gd->bus_clk; /* period in ns */
+
+ /*ata->ton = CALC_TIMING (180); */
+ out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+ out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+ out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+ out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+ out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+ /* IORDY enable */
+ out_8(&ata->cr, 0x40);
+ udelay(200000);
+ /* IORDY enable */
+ setbits_8(&ata->cr, 0x01);
+ }
+}
+#endif
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+extern void pci_mcf5445x_init(struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+ pci_mcf5445x_init(&hose);
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_FLASH_CFI_LEGACY)
+#include <flash.h>
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+ int sect[] = CONFIG_SYS_ATMEL_SECT;
+ int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
+ int i, j, k;
+
+ if (base != CONFIG_SYS_ATMEL_BASE)
+ return 0;
+
+ info->flash_id = 0x01000000;
+ info->portwidth = 1;
+ info->chipwidth = 1;
+ info->buffer_size = 1;
+ info->erase_blk_tout = 16384;
+ info->write_tout = 2;
+ info->buffer_write_tout = 5;
+ info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
+ info->cmd_reset = 0x00F0;
+ info->interface = FLASH_CFI_X8;
+ info->legacy_unlock = 0;
+ info->manufacturer_id = (u16) ATM_MANUFACT;
+ info->device_id = ATM_ID_LV040;
+ info->device_id2 = 0;
+
+ info->ext_addr = 0;
+ info->cfi_version = 0x3133;
+ info->cfi_offset = 0x0000;
+ info->addr_unlock1 = 0x00000555;
+ info->addr_unlock2 = 0x000002AA;
+ info->name = "CFI conformant";
+
+ info->size = 0;
+ info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
+ info->start[0] = base;
+ for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
+ info->size += sect[i] * sectsz[i];
+
+ for (j = 0; j < sect[i]; j++, k++) {
+ info->start[k + 1] = info->start[k] + sectsz[i];
+ info->protect[k] = 0;
+ }
+ }
+
+ return 1;
+}
+#endif /* CONFIG_SYS_FLASH_CFI */
diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m54455evb/u-boot.lds
new file mode 100644
index 0000000..5679d49
--- /dev/null
+++ b/board/freescale/m54455evb/u-boot.lds
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf5445x/start.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m547xevb/Kconfig b/board/freescale/m547xevb/Kconfig
new file mode 100644
index 0000000..8cfe20a
--- /dev/null
+++ b/board/freescale/m547xevb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5475EVB
+
+config SYS_CPU
+ default "mcf547x_8x"
+
+config SYS_BOARD
+ default "m547xevb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M5475EVB"
+
+endif
diff --git a/board/freescale/m547xevb/MAINTAINERS b/board/freescale/m547xevb/MAINTAINERS
new file mode 100644
index 0000000..9a8408d
--- /dev/null
+++ b/board/freescale/m547xevb/MAINTAINERS
@@ -0,0 +1,12 @@
+M547XEVB BOARD
+M: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+S: Maintained
+F: board/freescale/m547xevb/
+F: include/configs/M5475EVB.h
+F: configs/M5475AFE_defconfig
+F: configs/M5475BFE_defconfig
+F: configs/M5475CFE_defconfig
+F: configs/M5475DFE_defconfig
+F: configs/M5475EFE_defconfig
+F: configs/M5475FFE_defconfig
+F: configs/M5475GFE_defconfig
diff --git a/board/freescale/m547xevb/Makefile b/board/freescale/m547xevb/Makefile
new file mode 100644
index 0000000..8169177
--- /dev/null
+++ b/board/freescale/m547xevb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m547xevb.o
diff --git a/board/freescale/m547xevb/README b/board/freescale/m547xevb/README
new file mode 100644
index 0000000..ce497c0
--- /dev/null
+++ b/board/freescale/m547xevb/README
@@ -0,0 +1,272 @@
+Freescale MCF5475EVB ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created Jan 08, 2008
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI init
+- board/freescale/m547xevb/mii.c MII init
+- board/freescale/m547xevb/Makefile Makefile
+- board/freescale/m547xevb/config.mk config make
+- board/freescale/m547xevb/u-boot.lds Linker description
+
+- arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support
+- arch/m68k/cpu/mcf547x_8x/speed.c system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf547x_8x/Makefile Makefile
+- arch/m68k/cpu/mcf547x_8x/config.mk config make
+- arch/m68k/cpu/mcf547x_8x/start.S start up assembly code
+
+- doc/README.m5475evb This readme file
+
+- drivers/dma/MCD_dmaApi.c DMA API functions
+- drivers/dma/MCD_tasks.c DMA Tasks
+- drivers/dma/MCD_tasksInit.c DMA Tasks Init
+- drivers/net/fsl_mcdmafec.c ColdFire common DMA FEC driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+
+- include/MCD_dma.h DMA header file
+- include/MCD_progCheck.h DMA header file
+- include/MCD_tasksInit.h DMA header file
+- include/asm-m68k/bitops.h Bit operation function export
+- include/asm-m68k/byteorder.h Byte order functions
+- include/asm-m68k/errno.h Error Number definition
+- include/asm-m68k/fec.h FEC structure and definition
+- include/asm-m68k/fsl_i2c.h I2C structure and definition
+- include/asm-m68k/fsl_mcddmafec.h DMA FEC structure and definition
+- include/asm-m68k/global_data.h Global data structure
+- include/asm-m68k/immap.h ColdFire specific header file and driver macros
+- include/asm-m68k/immap_547x_8x.h mcf547x_8x specific header file
+- include/asm-m68k/io.h io functions
+- include/asm-m68k/m547x_8x.h mcf547x_8x specific header file
+- include/asm-m68k/posix_types.h Posix
+- include/asm-m68k/processor.h header file
+- include/asm-m68k/ptrace.h Exception structure
+- include/asm-m68k/rtc.h Realtime clock header file
+- include/asm-m68k/string.h String function export
+- include/asm-m68k/timer.h Timer structure and definition
+- include/asm-m68k/types.h Data types definition
+- include/asm-m68k/uart.h Uart structure and definition
+- include/asm-m68k/u-boot.h u-boot structure
+
+- include/configs/M5475EVB.h Board specific configuration file
+
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts Coldfire common interrupt functions
+- arch/m68k/lib/m68k_linux.c
+- arch/m68k/lib/traps.c Exception init code
+
+1 MCF547x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M5475EVB Development Board
+CONFIG_MCF547x_8x -- define for all MCF547x_8x CPUs
+CONFIG_M547x -- define for all Freescale MCF547x CPUs
+CONFIG_M5475 -- define for M5475EVB board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_FSLDMAFEC -- define to use common dma FEC driver
+CONFIG_MII -- enable to use MII driver
+CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c
+CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN--
+CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
+CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
+CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP -- set FEC timeout loop
+CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot
+
+CONFIG_CMD_USB -- enable USB commands
+CONFIG_USB_OHCI_NEW -- enable USB OHCI driver
+CONFIG_USB_STORAGE -- enable USB Storage device
+CONFIG_DOS_PARTITION -- enable DOS read/write
+
+CONFIG_SLTTMR -- define to use SLT timer
+
+CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
+CONFIG_HARD_I2C -- define for I2C hardware support
+CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
+CONFIG_SYS_I2C_SPEED -- define for I2C speed
+CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
+CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
+CONFIG_SYS_IMMR -- define for MBAR offset
+
+CONFIG_PCI -- define for PCI support
+CONFIG_PCI_PNP -- define for Plug n play support
+CONFIG_SKIPPCI_HOSTBRIDGE -- SKIP PCI Host bridge
+CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset
+CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset
+CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size
+CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset
+CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset
+CONFIG_SYS_PCI_IO_SIZE -- PCI IO size
+CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset
+CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset
+CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size
+
+CONFIG_SYS_MBAR -- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF547x internal SRAM
+
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ Flash: 0xFF800000-0xFFFFFFFF (8MB)
+ DDR: 0x00000000-0x3FFFFFFF (1024MB)
+ SRAM: 0xF2000000-0xF2000FFF (4KB)
+ PCI: 0x70000000-0x8FFFFFFF (512MB)
+ IP: 0xF0000000-0xFFFFFFFF (256MB)
+
+3. COMPILATION
+==============
+3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF or uclinux
+ version) from codesourcery.com was used. Download it from:
+ http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix
+ cd u-boot-1.x.x
+ make distclean
+ make M5475AFE_config, or - boot 2MB, RAM 64MB
+ make M5475BFE_config, or - boot 2MB, code 16MB, RAM 64MB
+ make M5475CFE_config, or - boot 2MB, code 16MB, Video, USB, RAM 64MB
+ make M5475DFE_config, or - boot 2MB, USB, RAM 64MB
+ make M5475EFE_config, or - boot 2MB, Video, USB, RAM 64MB
+ make M5475FFE_config, or - boot 2MB, code 32MB, Video, USB, RAM 128MB
+ make M5475GFE_config, or - boot 2MB, RAM 64MB
+ make
+
+5. SCREEN DUMP
+==============
+5.1
+
+U-Boot 1.3.1 (Jan 8 2008 - 12:47:44)
+
+CPU: Freescale MCF5475
+ CPU CLK 266 Mhz BUS CLK 133 Mhz
+Board: Freescale FireEngine 5475 EVB
+I2C: ready
+DRAM: 64 MB
+FLASH: 18 MB
+In: serial
+Out: serial
+Err: serial
+Net: FEC0, FEC1
+-> pri
+bootdelay=1
+baudrate=115200
+ethaddr=00:e0:0c:bc:e5:60
+eth1addr=00:e0:0c:bc:e5:61
+ipaddr=192.162.1.2
+serverip=192.162.1.1
+gatewayip=192.162.1.1
+netmask=255.255.255.0
+hostname=M547xEVB
+netdev=eth0
+loadaddr=10000
+u-boot=u-boot.bin
+load=tftp ${loadaddr) ${u-boot}
+upd=run load; run prog
+prog=prot off bank 1;era ff800000 ff82ffff;cp.b ${loadaddr} ff800000 ${filesize};save
+stdin=serial
+stdout=serial
+stderr=serial
+ethact=FEC0
+mem=65024k
+
+Environment size: 433/8188 bytes
+-> bdin
+memstart = 0x00000000
+memsize = 0x04000000
+flashstart = 0xFF800000
+flashsize = 0x01200000
+flashoffset = 0x00000000
+sramstart = 0xF2000000
+sramsize = 0x00001000
+mbar = 0xF0000000
+busfreq = 133.333 MHz
+pcifreq = 0 MHz
+ethaddr = 00:E0:0C:BC:E5:60
+eth1addr = 00:E0:0C:BC:E5:61
+ip_addr = 192.162.1.2
+baudrate = 115200 bps
+-> ?
+? - alias for 'help'
+base - print or set address offset
+bdinfo - print Board Info structure
+boot - boot default, i.e., run 'bootcmd'
+bootd - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm - boot application image from memory
+bootp - boot image via network using BootP/TFTP protocol
+bootvx - Boot vxWorks from an ELF image
+cmp - memory compare
+coninfo - print console devices and information
+cp - memory copy
+crc32 - checksum calculation
+dcache - enable or disable data cache
+echo - echo args to console
+erase - erase FLASH memory
+flinfo - print FLASH memory information
+go - start application at address 'addr'
+help - print online help
+i2c - I2C sub-system
+icache - enable or disable instruction cache
+iminfo - print header information for application image
+imls - list all images found in flash
+itest - return true/false on integer compare
+loadb - load binary file over serial line (kermit mode)
+loads - load S-Record file over serial line
+loady - load binary file over serial line (ymodem mode)
+loop - infinite loop on address range
+md - memory display
+mii - MII utility commands
+mm - memory modify (auto-incrementing)
+mtest - simple RAM test
+mw - memory write (fill)
+nfs - boot image via network using NFS protocol
+nm - memory modify (constant address)
+pci - list and access PCI Configuration Space
+ping - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset - Perform RESET of the CPU
+run - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv - set environment variables
+sleep - delay execution for some time
+source - run script from memory
+tftpboot- boot image via network using TFTP protocol
+usb - USB sub-system
+usbboot - boot from USB device
+version - print monitor version
+-> usb start
+(Re)start USB...
+USB: OHCI pci controller (1131, 1561) found @(0:17:0)
+OHCI regs address 0x80000000
+scanning bus for devices... 2 USB Device(s) found
+ scanning bus for storage devices... 1 Storage Device(s) found
+->
diff --git a/board/freescale/m547xevb/config.mk b/board/freescale/m547xevb/config.mk
new file mode 100644
index 0000000..4547465
--- /dev/null
+++ b/board/freescale/m547xevb/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xFF800000
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
new file mode 100644
index 0000000..1e3cb61
--- /dev/null
+++ b/board/freescale/m547xevb/m547xevb.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <pci.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale FireEngine 5475 EVB\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ siu_t *siu = (siu_t *) (MMAP_SIU);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+ u32 dramsize, i;
+#ifdef CONFIG_SYS_DRAMSZ1
+ u32 temp;
+#endif
+
+ out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
+
+ dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+ out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
+
+#ifdef CONFIG_SYS_DRAMSZ1
+ temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
+ for (i = 0x13; i < 0x20; i++) {
+ if (temp == (1 << i))
+ break;
+ }
+ i--;
+ dramsize += temp;
+ out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
+#endif
+
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+ /* Issue PALL */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+ /* Issue LEMR */
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+
+ udelay(500);
+
+ /* Issue PALL */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+ /* Perform two refresh cycles */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
+
+ udelay(100);
+
+ return dramsize;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+extern void pci_mcf547x_8x_init(struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+ pci_mcf547x_8x_init(&hose);
+}
+#endif /* CONFIG_PCI */
diff --git a/board/freescale/m547xevb/u-boot.lds b/board/freescale/m547xevb/u-boot.lds
new file mode 100644
index 0000000..e2ffae4
--- /dev/null
+++ b/board/freescale/m547xevb/u-boot.lds
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf547x_8x/start.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m548xevb/Kconfig b/board/freescale/m548xevb/Kconfig
new file mode 100644
index 0000000..da924e3
--- /dev/null
+++ b/board/freescale/m548xevb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M5485EVB
+
+config SYS_CPU
+ default "mcf547x_8x"
+
+config SYS_BOARD
+ default "m548xevb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "M5485EVB"
+
+endif
diff --git a/board/freescale/m548xevb/MAINTAINERS b/board/freescale/m548xevb/MAINTAINERS
new file mode 100644
index 0000000..82ad9fd
--- /dev/null
+++ b/board/freescale/m548xevb/MAINTAINERS
@@ -0,0 +1,13 @@
+M548XEVB BOARD
+M: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+S: Maintained
+F: board/freescale/m548xevb/
+F: include/configs/M5485EVB.h
+F: configs/M5485AFE_defconfig
+F: configs/M5485BFE_defconfig
+F: configs/M5485CFE_defconfig
+F: configs/M5485DFE_defconfig
+F: configs/M5485EFE_defconfig
+F: configs/M5485FFE_defconfig
+F: configs/M5485GFE_defconfig
+F: configs/M5485HFE_defconfig
diff --git a/board/freescale/m548xevb/Makefile b/board/freescale/m548xevb/Makefile
new file mode 100644
index 0000000..4483d15
--- /dev/null
+++ b/board/freescale/m548xevb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = m548xevb.o
diff --git a/board/freescale/m548xevb/config.mk b/board/freescale/m548xevb/config.mk
new file mode 100644
index 0000000..4547465
--- /dev/null
+++ b/board/freescale/m548xevb/config.mk
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xFF800000
diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c
new file mode 100644
index 0000000..0536155
--- /dev/null
+++ b/board/freescale/m548xevb/m548xevb.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <pci.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts("Freescale FireEngine 5485 EVB\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ siu_t *siu = (siu_t *) (MMAP_SIU);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+ u32 dramsize, i;
+#ifdef CONFIG_SYS_DRAMSZ1
+ u32 temp;
+#endif
+
+ out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
+
+ dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+ i--;
+ out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
+
+#ifdef CONFIG_SYS_DRAMSZ1
+ temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
+ for (i = 0x13; i < 0x20; i++) {
+ if (temp == (1 << i))
+ break;
+ }
+ i--;
+ dramsize += temp;
+ out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
+#endif
+
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+ /* Issue PALL */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+ /* Issue LEMR */
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+
+ udelay(500);
+
+ /* Issue PALL */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+
+ /* Perform two refresh cycles */
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
+
+ udelay(100);
+
+ return dramsize;
+};
+
+int testdram(void)
+{
+ /* TODO: XXX XXX XXX */
+ printf("DRAM test not implemented!\n");
+
+ return (0);
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+extern void pci_mcf547x_8x_init(struct pci_controller *hose);
+
+void pci_init_board(void)
+{
+ pci_mcf547x_8x_init(&hose);
+}
+#endif /* CONFIG_PCI */
diff --git a/board/freescale/m548xevb/u-boot.lds b/board/freescale/m548xevb/u-boot.lds
new file mode 100644
index 0000000..cd6aed6
--- /dev/null
+++ b/board/freescale/m548xevb/u-boot.lds
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf547x_8x/start.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/mpc5121ads/Kconfig b/board/freescale/mpc5121ads/Kconfig
new file mode 100644
index 0000000..f125f9e
--- /dev/null
+++ b/board/freescale/mpc5121ads/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC5121ADS
+
+config SYS_BOARD
+ default "mpc5121ads"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mpc5121ads"
+
+endif
diff --git a/board/freescale/mpc5121ads/MAINTAINERS b/board/freescale/mpc5121ads/MAINTAINERS
new file mode 100644
index 0000000..d4aab8f
--- /dev/null
+++ b/board/freescale/mpc5121ads/MAINTAINERS
@@ -0,0 +1,7 @@
+MPC5121ADS BOARD
+#M: -
+S: Maintained
+F: board/freescale/mpc5121ads/
+F: include/configs/mpc5121ads.h
+F: configs/mpc5121ads_defconfig
+F: configs/mpc5121ads_rev2_defconfig
diff --git a/board/freescale/mpc5121ads/Makefile b/board/freescale/mpc5121ads/Makefile
new file mode 100644
index 0000000..67cf555
--- /dev/null
+++ b/board/freescale/mpc5121ads/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mpc5121ads.o
diff --git a/board/freescale/mpc5121ads/README b/board/freescale/mpc5121ads/README
new file mode 100644
index 0000000..741bc40
--- /dev/null
+++ b/board/freescale/mpc5121ads/README
@@ -0,0 +1,7 @@
+To configure for the current (Rev 3.x) ADS5121
+ make mpc5121ads_config
+This will automatically include PCI, the Real Time CLock, add backup flash
+ability and set the correct frequency and memory configuration.
+
+To configure for the older Rev 2 ADS5121 type (this will not have PCI)
+ make mpc5121ads_rev2_config
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
new file mode 100644
index 0000000..40bd55d
--- /dev/null
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -0,0 +1,284 @@
+/*
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+#include <net.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
+
+/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
+extern int mpc5121_nfc_chip;
+
+/* Control chips select signal on MPC5121ADS board */
+void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
+{
+ unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
+ u8 v;
+
+ v = in_8(csreg);
+ v |= 0x0F;
+
+ if (chip >= 0) {
+ __mpc5121_nfc_select_chip(mtd, 0);
+ v &= ~(1 << mpc5121_nfc_chip);
+ } else {
+ __mpc5121_nfc_select_chip(mtd, -1);
+ }
+
+ out_8(csreg, v);
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
+ *
+ * Without this the flash identification routine fails, as it needs to issue
+ * write commands in order to establish the device ID.
+ */
+
+#ifdef CONFIG_MPC5121ADS_REV2
+ out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
+#else
+ if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
+ out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
+ } else {
+ /* running from Backup flash */
+ out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
+ }
+#endif
+ return 0;
+}
+
+int is_micron(void){
+
+ ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
+ uchar macaddr[6];
+ u32 brddate, macchk, ismicron;
+
+ /*
+ * MAC address has serial number with date of manufacture
+ * Boards made before Nov-08 #1180 use Micron memory;
+ * 001e59 is the STx vendor #
+ * Default is Elpida since it works for both but is slightly slower
+ */
+ ismicron = 0;
+ if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
+ brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
+ macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
+ debug("brddate = %d\n\t", brddate);
+
+ if (macchk == 0x001e59 && brddate <= 8111180)
+ ismicron = 1;
+ } else if (brd_rev < 0x400) {
+ ismicron = 1;
+ }
+ debug("Using %s Memory settings\n\t",
+ ismicron ? "Micron" : "Elpida");
+ return(ismicron);
+}
+
+phys_size_t initdram(int board_type)
+{
+ u32 msize = 0;
+ /*
+ * Elpida MDDRC and initialization settings are an alternative
+ * to the Default Micron ones for all but the earliest Rev 4 boards
+ */
+ ddr512x_config_t elpida_mddrc_config = {
+ .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
+ .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
+ .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
+ .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
+ };
+
+ u32 elpida_init_sequence[] = {
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_EM2,
+ CONFIG_SYS_DDRCMD_EM3,
+ CONFIG_SYS_DDRCMD_EN_DLL,
+ CONFIG_SYS_ELPIDA_RES_DLL,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_ELPIDA_INIT_DEV_OP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_OCD_DEFAULT,
+ CONFIG_SYS_ELPIDA_OCD_EXIT,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP
+ };
+
+ if (is_micron()) {
+ msize = fixed_sdram(NULL, NULL, 0);
+ } else {
+ msize = fixed_sdram(&elpida_mddrc_config,
+ elpida_init_sequence,
+ sizeof(elpida_init_sequence)/sizeof(u32));
+ }
+
+ return msize;
+}
+
+int misc_init_r(void)
+{
+ u8 tmp_val;
+
+ /* Using this for DIU init before the driver in linux takes over
+ * Enable the TFP410 Encoder (I2C address 0x38)
+ */
+
+ i2c_set_bus_num(2);
+ tmp_val = 0xBF;
+ i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+ /* Verify if enabled */
+ tmp_val = 0;
+ i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+ debug("DVI Encoder Read: 0x%02x\n", tmp_val);
+
+ tmp_val = 0x10;
+ i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+ /* Verify if enabled */
+ tmp_val = 0;
+ i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+ debug("DVI Encoder Read: 0x%02x\n", tmp_val);
+
+ return 0;
+}
+
+static iopin_t ioregs_init[] = {
+ /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+ {
+ offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* Set highest Slew on 9 PATA pins */
+ {
+ offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+ {
+ offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=SPDIF_TXCLK */
+ {
+ offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+ /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
+ {
+ offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIU CLK */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIU_HSYNC */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ }
+};
+
+static iopin_t rev2_silicon_pci_ioregs_init[] = {
+ /* FUNC0=PCI Sets next 54 to PCI pads */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
+ }
+};
+
+int checkboard (void)
+{
+ ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
+ uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 spridr = in_be32(&im->sysconf.spridr);
+
+ printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
+ brd_rev, cpld_rev);
+
+ /* initialize function mux & slew rate IO inter alia on IO Pins */
+ iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+ if (SVR_MJREV (spridr) >= 2)
+ iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/freescale/mpc7448hpc2/Kconfig b/board/freescale/mpc7448hpc2/Kconfig
new file mode 100644
index 0000000..3e7f6e8
--- /dev/null
+++ b/board/freescale/mpc7448hpc2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC7448HPC2
+
+config SYS_BOARD
+ default "mpc7448hpc2"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "mpc7448hpc2"
+
+endif
diff --git a/board/freescale/mpc7448hpc2/MAINTAINERS b/board/freescale/mpc7448hpc2/MAINTAINERS
new file mode 100644
index 0000000..9966b55
--- /dev/null
+++ b/board/freescale/mpc7448hpc2/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC7448HPC2 BOARD
+M: Roy Zang <tie-fei.zang@freescale.com>
+S: Maintained
+F: board/freescale/mpc7448hpc2/
+F: include/configs/mpc7448hpc2.h
+F: configs/mpc7448hpc2_defconfig
diff --git a/board/freescale/mpc7448hpc2/Makefile b/board/freescale/mpc7448hpc2/Makefile
new file mode 100644
index 0000000..2cc211b
--- /dev/null
+++ b/board/freescale/mpc7448hpc2/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mpc7448hpc2.o tsi108_init.o
+obj-y += asm_init.o
diff --git a/board/freescale/mpc7448hpc2/README b/board/freescale/mpc7448hpc2/README
new file mode 100644
index 0000000..cbb043e
--- /dev/null
+++ b/board/freescale/mpc7448hpc2/README
@@ -0,0 +1,184 @@
+Freescale MPC7448hpc2 (Taiga) board
+===================================
+
+Created 08/11/2006 Roy Zang
+--------------------------
+MPC7448hpc2 (Taiga) board is a high-performance PowerPC server reference
+design, which is optimized for high speed throughput between the processor and
+the memory, disk drive and Ethernet port subsystems.
+
+MPC7448hpc2(Taiga) is designed to the micro-ATX chassis, allowing it to be
+used in 1U or 2U rack-mount chassis¡¯, as well as in standard ATX/Micro-ATX
+chassis.
+
+Building U-Boot
+------------------
+The mpc7448hpc2 code base is known to compile using:
+ Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
+
+ $ make mpc7448hpc2_config
+ Configuring for mpc7448hpc2 board...
+
+ $ make
+
+Memory Map
+----------
+
+The memory map is setup for Linux to operate properly.
+
+The mapping is:
+
+ Range Start Range End Definition Size
+
+ 0x0000_0000 0x7fff_ffff DDR 2G
+ 0xe000_0000 0xe7ff_ffff PCI Memory 128M
+ 0xfa00_0000 0xfaff_ffff PCI IO 16M
+ 0xfb00_0000 0xfbff_ffff PCI Config 16M
+ 0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M
+ 0xfe00_0000 0xfeff_ffff PromJet 16M
+ 0xff00_0000 0xff80_0000 FLASH (boot flash) 8M
+ 0xff80_0000 0xffff_ffff FLASH (second half flash) 8M
+
+Using Flash
+-----------
+
+The MPC7448hpc2 board has two "banks" of flash, each 8MB in size
+(2^23 = 0x00800000).
+
+Note: the "bank" here refers to half of the flash. In fact, there is only one
+bank of flash, which is divided into low and high half. Each is controlled by
+the most significant bit of the address bus. The so called "bank" is only for
+convenience.
+
+There is a switch which allows the "bank" to be selected. The switch
+settings for updating flash are given below.
+
+The u-boot commands for copying the boot-bank into the secondary bank are
+as follows:
+
+ erase ff800000 ff880000
+ cp.b ff000000 ff800000 80000
+
+U-boot commands for downloading an image via tftp and flashing
+it into the secondary bank:
+
+ tftp 10000 <u-boot.bin.image>
+ erase ff000000 ff080000
+ cp.b 10000 ff000000 80000
+
+After copying the image into the second bank of flash, be sure to toggle
+SW3[4] on board before resetting the board in order to set the
+secondary bank as the boot-bank.
+
+Board Switches
+----------------------
+
+Most switches on the board should not be changed. The most frequent
+user-settable switches on the board are used to configure
+the flash banks and determining the PCI frequency.
+
+SW1[1-5]: Processor core voltage
+
+ 12345 Core Voltage
+ -----
+ SW1=01111 1.000V.
+ SW1=01101 1.100V.
+ SW1=01011 1.200V.
+ SW1=01001 1.300V only for MPC7447A.
+
+
+SW2[1-6]: CPU core frequency
+
+ CPU Core Frequency (MHz)
+ Bus Frequency
+ 123456 100 133 167 200 Ratio
+
+ ------
+ SW2=101100 500 667 833 1000 5x
+ SW2=100100 550 733 917 1100 5.5x
+ SW2=110100 600 800 1000 1200 6x
+ SW2=010100 650 866 1083 1300 6.5x
+ SW2=001000 700 930 1167 1400 7x
+ SW2=000100 750 1000 1250 1500 7.5x
+ SW2=110000 800 1066 1333 1600 8x
+ SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A
+ SW2=011110 900 1200 1500 1800 9x
+
+This table shows only a subset of available frequency options; see the CPU
+hardware specifications for more information.
+
+SW2[7-8]: Bus Protocol and CPU Reset Option
+
+ 7
+ -
+ SW2=0 System bus uses MPX bus protocol
+ SW2=1 System bus uses 60x bus protocol
+
+ 8
+ -
+ SW2=0 TSI108 can cause CPU reset
+ SW2=1 TSI108 can not cause CPU reset
+
+SW3[1-8] system options
+
+ 123
+ ---
+ SW3=xxx Connected to GPIO[0:2] on TSI108
+
+ 4
+ -
+ SW3=0 CPU boots from low half of flash
+ SW3=1 CPU boots from high half of flash
+
+ 5
+ -
+ SW3=0 SATA and slot2 connected to PCI bus
+ SW3=1 Only slot1 connected to PCI bus
+
+ 6
+ -
+ SW3=0 USB connected to PCI bus
+ SW3=1 USB disconnected from PCI bus
+
+ 7
+ -
+ SW3=0 Flash is write protected
+ SW3=1 Flash is NOT write protected
+
+ 8
+ -
+ SW3=0 CPU will boot from flash
+ SW3=1 CPU will boot from PromJet
+
+SW4[1-3]: System bus frequency
+
+ Bus Frequency (MHz)
+ ---
+ SW4=010 183
+ SW4=011 100
+ SW4=100 133
+ SW4=101 166 only for MPC7447A
+ SW4=110 200 only for MPC7448
+ others reserved
+
+SW4[4-6]: DDR2 SDRAM frequency
+
+ Bus Frequency (MHz)
+ ---
+ SW4=000 external clock
+ SW4=011 system clock
+ SW4=100 133
+ SW4=101 166
+ SW4=110 200
+ others reserved
+
+SW4[7-8]: PCI/PCI-X frequency control
+ 7
+ -
+ SW4=0 PCI/PCI-X bus operates normally
+ SW4=1 PCI bus forced to PCI-33 mode
+
+ 8
+ -
+ SW4=0 PCI-X mode at 133 MHz allowed
+ SW4=1 PCI-X mode limited to 100 MHz
diff --git a/board/freescale/mpc7448hpc2/asm_init.S b/board/freescale/mpc7448hpc2/asm_init.S
new file mode 100644
index 0000000..70315c3
--- /dev/null
+++ b/board/freescale/mpc7448hpc2/asm_init.S
@@ -0,0 +1,905 @@
+/*
+ * (C) Copyright 2004-05; Tundra Semiconductor Corp.
+ *
+ * Added automatic detect of SDC settings
+ * Copyright (c) 2005 Freescale Semiconductor, Inc.
+ * Maintainer tie-fei.zang@freescale.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * FILENAME: asm_init.s
+ *
+ * Originator: Alex Bounine
+ *
+ * DESCRIPTION:
+ * Initialization code for the Tundra Tsi108 bridge chip
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/processor.h>
+
+#include <tsi108.h>
+
+/*
+ * Build Configuration Options
+ */
+
+/* #define DISABLE_PBM disables usage of PB Master */
+/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */
+/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */
+
+/*
+ * Hardcoded SDC settings
+ */
+
+#ifdef SDC_HARDCODED_INIT
+
+/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */
+
+#define VAL_SD_REFRESH (0x61A)
+#define VAL_SD_TIMING (0x0308336b)
+#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */
+#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */
+#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */
+#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */
+
+#endif /* SDC_HARDCODED_INIT */
+
+/*
+ CPU Configuration:
+
+ CPU Address and Data Parity enables.
+
+#define CPU_AP
+#define CPU_DP
+*/
+
+/*
+ * Macros
+ * !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
+ * expected to work correctly for the CSR space within 32KB range.
+ *
+ * LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
+ * These macros are absolutely identical except their names. This difference
+ * is provided intentionally for better readable code.
+ */
+
+#define LOAD_PTR(reg,const32) \
+ addis reg,r0,const32@h; ori reg,reg,const32@l
+
+#define LOAD_U32(reg,const32) \
+ addis reg,r0,const32@h; ori reg,reg,const32@l
+
+/* LOADMEM initializes a register with the contents of a specified 32-bit
+ * memory location, usually a CSR value.
+ */
+
+#define LOAD_MEM(reg,addr32) \
+ addis reg,r0,addr32@ha; lwz reg,addr32@l(reg)
+
+#ifndef SDC_HARDCODED_INIT
+sdc_clk_sync:
+ /* MHz: 0,0,183,100,133,167,200,233 */
+ .long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */
+#endif
+
+/*
+ * board_asm_init() - early initialization function. Coded to be portable to
+ * dual-CPU configuration.
+ * Checks CPU number and performs board HW initialization if called for CPU0.
+ * Registers used: r3,r4,r5,r6,r19,r29
+ *
+ * NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
+ * and the rest of the board. Current implementation demonstrates two
+ * possible ways to identify CPU number:
+ * - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
+ * - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
+ */
+
+ .globl board_asm_init
+board_asm_init:
+ mflr r19 /* Save LR to be able return later. */
+ bl icache_enable /* Enable icache to reduce reads from flash. */
+
+/* Initialize pointer to Tsi108 register space */
+
+ LOAD_PTR(r29,CONFIG_SYS_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
+ ori r4,r29,TSI108_PB_REG_OFFSET
+
+/* Check Processor Version Number */
+
+ mfspr r3, PVR
+ rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */
+
+ cmpli 0,0,r3,0x8000 /* MPC74xx */
+ bne cont_brd_init
+
+ /*
+ * For MPC744x/5x enable extended BATs[4-7]
+ * Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
+ * to disable prefetch
+ */
+
+ mfspr r5, HID0
+ oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */
+ ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */
+ mtspr HID0, r5
+ isync
+ sync
+
+ /* Adding code to disable external interventions in MPX bus mode */
+ mfspr r3, 1014
+ oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */
+ mtspr 1014, r3
+ isync
+ sync
+
+ /* Sri: code to enable FP unit */
+ mfmsr r3
+ ori r3, r3, 0x2000
+ mtmsr r3
+ isync
+ sync
+
+ /* def CONFIG_DUAL_CPU
+ * For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
+ */
+#if(1)
+ mfspr r3,1014 /* read MSSCR0 */
+ rlwinm. r3,r3,27,31,31 /* get processor ID number */
+ mtspr SPRN_PIR,r3 /* Save CPU ID */
+ sync
+ bne init_done
+ b do_tsi108_init
+
+cont_brd_init:
+
+ /* An alternative method of checking the processor number (in addition
+ * to configuration using MSSCR0[ID] bit on MPC74xx).
+ * Good for IBM PPC750FX/GX.
+ */
+
+ lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */
+ rlwinm. r3,r3,24,31,31 /* get processor ID number */
+ bne init_done
+#else
+
+cont_brd_init:
+
+#endif /* CONFIG_DUAL_CPU */
+
+ /* Initialize Tsi108 chip */
+
+do_tsi108_init:
+
+ /*
+ * Adjust HLP/Flash parameters. By default after reset the HLP port is
+ * set to support slow devices. Better performance can be achived when
+ * an optimal parameters are used for specific EPROM device.
+ * NOTE: This should be performed ASAP for the emulation platform
+ * because it has 5MHz HLP clocking.
+ */
+
+#ifdef CONFIG_TSI108EMU
+ ori r4,r29,TSI108_HLP_REG_OFFSET
+ LOAD_U32(r5,0x434422c0)
+ stw r5,0x08(r4) /* set HLP B0_CTRL0 */
+ sync
+ LOAD_U32(r5,0xd0012000)
+ stw r5,0x0c(r4) /* set HLP B0_CTRL1 */
+ sync
+#endif
+
+ /* Initialize PB interface. */
+
+ ori r4,r29,TSI108_PB_REG_OFFSET
+
+#if (CONFIG_SYS_TSI108_CSR_BASE != CONFIG_SYS_TSI108_CSR_RST_BASE)
+ /* Relocate (if required) Tsi108 registers. Set new value for
+ * PB_REG_BAR:
+ * Note we are in the 32-bit address mode.
+ */
+ LOAD_U32(r5,(CONFIG_SYS_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
+ stw r5,PB_REG_BAR(r4)
+ andis. r29,r5,0xFFFF
+ sync
+ ori r4,r29,TSI108_PB_REG_OFFSET
+#endif
+
+ /* Set PB Slave configuration register */
+
+ LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */
+ lwz r3, PB_RSR(r4) /* get PB bus mode */
+ xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */
+ rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */
+ stw r5,PB_SCR(r4)
+ sync
+
+ /* Configure PB Arbiter */
+
+ lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
+ li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */
+#ifdef DISABLE_PBM
+ ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */
+#endif
+ andc r5,r5,r3 /* Clear the masked bit fields */
+ ori r5,r5,0x0001 /* Set pipeline depth */
+ stw r5,PB_ARB_CTRL(r4)
+
+#if (0) /* currently using the default settings for PBM after reset */
+ LOAD_U32(r5,0x) /* value for PB_MCR */
+ stw r5,PB_MCR(r4)
+ sync
+
+ LOAD_U32(r5,0x) /* value for PB_MCMD */
+ stw r5,PB_MCMD(r4)
+ sync
+#endif
+
+ /* Disable or enable PVT based on processor bus frequency
+ * 1. Read CG_PWRUP_STATUS register field bits 18,17,16
+ * 2. See if the value is < or > 133mhz (18:16 = 100)
+ * 3. If > enable PVT
+ */
+
+ LOAD_U32(r3,0xC0002234)
+ lwz r3,0(r3)
+ rlwinm r3,r3,16,29,31
+
+ cmpi 0,0,r3,0x0004
+ bgt sdc_init
+
+#ifndef CONFIG_TSI108EMU
+ /* FIXME: Disable PB calibration control for any real Tsi108 board */
+ li r5,0x0101 /* disable calibration control */
+ stw r5,PB_PVT_CTRL2(r4)
+ sync
+#endif
+
+ /* Initialize SDRAM controller. */
+
+sdc_init:
+
+#ifndef SDC_HARDCODED_INIT
+ /* get SDC clock prior doing sdram controller autoconfig */
+ ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */
+ lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */
+ rlwinm r3,r3,12,29,31 /* r3 - SD clk */
+ lis r5,sdc_clk_sync@h
+ ori r5,r5,sdc_clk_sync@l
+ /* Sri: At this point check if r3 = 001. If yes,
+ * the memory frequency should be same as the
+ * MPX bus frequency
+ */
+ cmpi 0,0,r3,0x0001
+ bne get_nsec
+ lwz r6, CG_PWRUP_STATUS(r4)
+ rlwinm r6,r6,16,29,31
+ mr r3,r6
+
+get_nsec:
+ rlwinm r3,r3,2,0,31
+ lwzx r9,r5,r3 /* get SD clk rate in nSec */
+ /* ATTN: r9 will be used by SPD routine */
+#endif /* !SDC_HARDCODED_INIT */
+
+ ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */
+
+ /* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */
+
+ LOAD_U32(r5,0x00)
+ stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */
+#ifdef ENABLE_SDRAM_ECC
+ li r5, 0x01
+#endif /* ENABLE_SDRAM_ECC */
+ stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */
+ sync
+
+#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */
+
+ /* First read the CG_PWRUP_STATUS register to get the
+ * memory speed from bits 22,21,20
+ */
+
+ LOAD_U32(r3,0xC0002234)
+ lwz r3,0(r3)
+ rlwinm r3,r3,12,29,31
+
+ /* Now first check for 166, then 200, or default */
+
+ cmpi 0,0,r3,0x0005
+ bne check_for_200mhz
+
+ /* set values for 166 Mhz memory speed
+ * Set refresh rate and timing parameters
+ */
+ LOAD_U32(r5,0x00000515)
+ stw r5,SD_REFRESH(r4)
+ LOAD_U32(r5,0x03073368)
+ stw r5,SD_TIMING(r4)
+ sync
+
+ /* Initialize DIMM0 control and BAR registers */
+ LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+ oris r5,r5,0x0001 /* set auto precharge EN bit */
+#endif
+ stw r5,SD_D0_CTRL(r4)
+ LOAD_U32(r5,VAL_SD_D0_BAR)
+ stw r5,SD_D0_BAR(r4)
+ sync
+
+ /* Initialize DIMM1 control and BAR registers
+ * (same as dimm 0, next 512MB, disabled)
+ */
+ LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+ oris r5,r5,0x0001 /* set auto precharge EN bit */
+#endif
+ stw r5,SD_D1_CTRL(r4)
+ LOAD_U32(r5,VAL_SD_D1_BAR)
+ stw r5,SD_D1_BAR(r4)
+ sync
+
+ b sdc_init_done
+
+check_for_200mhz:
+
+ cmpi 0,0,r3,0x0006
+ bne set_default_values
+
+ /* set values for 200Mhz memory speed
+ * Set refresh rate and timing parameters
+ */
+ LOAD_U32(r5,0x0000061a)
+ stw r5,SD_REFRESH(r4)
+ LOAD_U32(r5,0x03083348)
+ stw r5,SD_TIMING(r4)
+ sync
+
+ /* Initialize DIMM0 control and BAR registers */
+ LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+ oris r5,r5,0x0001 /* set auto precharge EN bit */
+#endif
+ stw r5,SD_D0_CTRL(r4)
+ LOAD_U32(r5,VAL_SD_D0_BAR)
+ stw r5,SD_D0_BAR(r4)
+ sync
+
+ /* Initialize DIMM1 control and BAR registers
+ * (same as dimm 0, next 512MB, disabled)
+ */
+ LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+ oris r5,r5,0x0001 /* set auto precharge EN bit */
+#endif
+ stw r5,SD_D1_CTRL(r4)
+ LOAD_U32(r5,VAL_SD_D1_BAR)
+ stw r5,SD_D1_BAR(r4)
+ sync
+
+ b sdc_init_done
+
+set_default_values:
+
+ /* Set refresh rate and timing parameters */
+ LOAD_U32(r5,VAL_SD_REFRESH)
+ stw r5,SD_REFRESH(r4)
+ LOAD_U32(r5,VAL_SD_TIMING)
+ stw r5,SD_TIMING(r4)
+ sync
+
+ /* Initialize DIMM0 control and BAR registers */
+ LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+ oris r5,r5,0x0001 /* set auto precharge EN bit */
+#endif
+ stw r5,SD_D0_CTRL(r4)
+ LOAD_U32(r5,VAL_SD_D0_BAR)
+ stw r5,SD_D0_BAR(r4)
+ sync
+
+ /* Initialize DIMM1 control and BAR registers
+ * (same as dimm 0, next 512MB, disabled)
+ */
+ LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
+#ifdef SDC_AUTOPRECH_EN
+ oris r5,r5,0x0001 /* set auto precharge EN bit */
+#endif
+ stw r5,SD_D1_CTRL(r4)
+ LOAD_U32(r5,VAL_SD_D1_BAR)
+ stw r5,SD_D1_BAR(r4)
+ sync
+#else /* !SDC_HARDCODED_INIT */
+ bl tsi108_sdram_spd /* automatically detect SDC settings */
+#endif /* SDC_HARDCODED_INIT */
+
+sdc_init_done:
+
+#ifdef DISABLE_PBM
+ LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */
+#else
+ LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */
+#endif /* DISABLE_PBM */
+
+#ifdef CONFIG_TSI108EMU
+ oris r5,r5,0x0010 /* set EMULATION_MODE bit */
+#endif
+
+ stw r5,SD_CTRL(r4)
+ eieio
+ sync
+
+ /* Enable SDRAM access */
+
+ oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */
+ stw r5,SD_CTRL(r4)
+ sync
+
+wait_init_complete:
+ lwz r5,SD_STATUS(r4)
+ andi. r5,r5,0x0001
+ /* wait until SDRAM initialization is complete */
+ beq wait_init_complete
+
+ /* Map SDRAM into the processor bus address space */
+
+ ori r4,r29,TSI108_PB_REG_OFFSET
+
+ /* Setup BARs associated with direct path PB<->SDRAM */
+
+ /* PB_SDRAM_BAR1:
+ * provides a direct path to the main system memory (cacheable SDRAM)
+ */
+
+ /* BA=0,Size=512MB, ENable, No Addr.Translation */
+ LOAD_U32(r5, 0x00000011)
+ stw r5,PB_SDRAM_BAR1(r4)
+ sync
+
+ /* Make sure that PB_SDRAM_BAR1 decoder is set
+ * (to allow following immediate read from SDRAM)
+ */
+ lwz r5,PB_SDRAM_BAR1(r4)
+ sync
+
+ /* PB_SDRAM_BAR2:
+ * provides non-cacheable alias (via the direct path) to main
+ * system memory.
+ * Size = 512MB, ENable, Addr.Translation - ON,
+ * BA = 0x0_40000000, TA = 0x0_00000000
+ */
+
+ LOAD_U32(r5, 0x40010011)
+ stw r5,PB_SDRAM_BAR2(r4)
+ sync
+
+ /* Make sure that PB_SDRAM_BAR2 decoder is set
+ * (to allow following immediate read from SDRAM)
+ */
+ lwz r5,PB_SDRAM_BAR2(r4)
+ sync
+
+init_done:
+
+ /* All done. Restore LR and return. */
+ mtlr r19
+ blr
+
+#if (0)
+ /*
+ * init_cpu1
+ * This routine enables CPU1 on the dual-processor system.
+ * Now there is only one processor in the system
+ */
+
+ .global enable_cpu1
+enable_cpu1:
+
+ lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */
+ addi r3,r3,Tsi108_Base@l
+ lwz r3,0(r3) /* R3 = CSR Base Addr */
+ ori r4,r3,TSI108_PB_REG_OFFSET
+ lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
+ ori r3,r3,0x0200 /* Set M1_EN bit */
+ stw r3,PB_ARB_CTRL(r4)
+
+ blr
+#endif
+
+ /*
+ * enable_EI
+ * Enable CPU core external interrupt
+ */
+
+ .global enable_EI
+enable_EI:
+ mfmsr r3
+ ori r3,r3,0x8000 /* set EE bit */
+ mtmsr r3
+ blr
+
+ /*
+ * disable_EI
+ * Disable CPU core external interrupt
+ */
+
+ .global disable_EI
+disable_EI:
+ mfmsr r3
+ li r4,-32768 /* aka "li r4,0x8000" */
+ andc r3,r3,r4 /* clear EE bit */
+ mtmsr r3
+ blr
+
+#ifdef ENABLE_SDRAM_ECC
+ /* enables SDRAM ECC */
+
+ .global enable_ECC
+enable_ECC:
+ ori r4,r29,TSI108_SD_REG_OFFSET
+ lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */
+ ori r3,r3,0x0001 /* Set ECC_EN bit */
+ stw r3,SD_ECC_CTRL(r4)
+ blr
+
+ /*
+ * clear_ECC_err
+ * Clears all pending SDRAM ECC errors
+ * (normally after SDRAM scrubbing/initialization)
+ */
+
+ .global clear_ECC_err
+clear_ECC_err:
+ ori r4,r29,TSI108_SD_REG_OFFSET
+ ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */
+ stw r3,SD_INT_STATUS(r4)
+ blr
+
+#endif /* ENABLE_SDRAM_ECC */
+
+#ifndef SDC_HARDCODED_INIT
+
+ /* SDRAM SPD Support */
+#define SD_I2C_CTRL1 (0x400)
+#define SD_I2C_CTRL2 (0x404)
+#define SD_I2C_RD_DATA (0x408)
+#define SD_I2C_WR_DATA (0x40C)
+
+ /*
+ * SDRAM SPD Support Macros
+ */
+
+#define SPD_DIMM0 (0x00000100)
+#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */
+
+#define SPD_RDIMM (0x01)
+#define SPD_UDIMM (0x02)
+
+#define SPD_CAS_3 0x8
+#define SPD_CAS_4 0x10
+#define SPD_CAS_5 0x20
+
+#define ERR_NO_DIMM_FOUND (0xdb0)
+#define ERR_TRAS_FAIL (0xdb1)
+#define ERR_TRCD_FAIL (0xdb2)
+#define ERR_TRP_FAIL (0xdb3)
+#define ERR_TWR_FAIL (0xdb4)
+#define ERR_UNKNOWN_PART (0xdb5)
+#define ERR_NRANK_INVALID (0xdb6)
+#define ERR_DIMM_SIZE (0xdb7)
+#define ERR_ADDR_MODE (0xdb8)
+#define ERR_RFRSH_RATE (0xdb9)
+#define ERR_DIMM_TYPE (0xdba)
+#define ERR_CL_VALUE (0xdbb)
+#define ERR_TRFC_FAIL (0xdbc)
+
+/* READ_SPD requirements:
+ * byte - byte address in SPD device (0 - 255)
+ * r3 = will return data read from I2C Byte location
+ * r4 - unchanged (SDC base addr)
+ * r5 - clobbered in routine (I2C status)
+ * r10 - number of DDR slot where first SPD device is detected
+ */
+
+#define READ_SPD(byte_num) \
+ addis r3, 0, byte_num@l; \
+ or r3, r3, r10; \
+ ori r3, r3, 0x0A; \
+ stw r3, SD_I2C_CTRL1(r4); \
+ li r3, I2C_CNTRL2_START; \
+ stw r3, SD_I2C_CTRL2(r4); \
+ eieio; \
+ sync; \
+ li r3, 0x100; \
+1:; \
+ addic. r3, r3, -1; \
+ bne 1b; \
+2:; \
+ lwz r5, SD_I2C_CTRL2(r4); \
+ rlwinm. r3,r5,0,23,23; \
+ bne 2b; \
+ rlwinm. r3,r5,0,3,3; \
+ lwz r3,SD_I2C_RD_DATA(r4)
+
+#define SPD_MIN_RFRSH (0x80)
+#define SPD_MAX_RFRSH (0x85)
+
+refresh_rates: /* in nSec */
+ .long 15625 /* Normal (0x80) */
+ .long 3900 /* Reduced 0.25x (0x81) */
+ .long 7800 /* Reduced 0.5x (0x82) */
+ .long 31300 /* Extended 2x (0x83) */
+ .long 62500 /* Extended 4x (0x84) */
+ .long 125000 /* Extended 8x (0x85) */
+
+/*
+ * tsi108_sdram_spd
+ *
+ * Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data
+ * Uses registers: r4 - SDC base address (not changed)
+ * r9 - SDC clocking period in nSec
+ * Changes registers: r3,r5,r6,r7,r8,r10,r11
+ */
+
+tsi108_sdram_spd:
+
+ li r10,SPD_DIMM0
+ xor r11,r11,r11 /* DIMM Base Address: starts from 0 */
+
+do_first_dimm:
+
+ /* Program Refresh Rate Register */
+
+ READ_SPD(12) /* get Refresh Rate */
+ beq check_next_slot
+ li r5, ERR_RFRSH_RATE
+ cmpi 0,0,r3,SPD_MIN_RFRSH
+ ble spd_fail
+ cmpi 0,0,r3,SPD_MAX_RFRSH
+ bgt spd_fail
+ addi r3,r3,-SPD_MIN_RFRSH
+ rlwinm r3,r3,2,0,31
+ lis r5,refresh_rates@h
+ ori r5,r5,refresh_rates@l
+ lwzx r5,r5,r3 /* get refresh rate in nSec */
+ divwu r5,r5,r9 /* calculate # of SDC clocks */
+ stw r5,SD_REFRESH(r4) /* Set refresh rate */
+ sync
+
+ /* Program SD Timing Register */
+
+ li r7, 0 /* clear r7 prior parameter collection */
+
+ READ_SPD(20) /* get DIMM type: Registered or Unbuffered */
+ beq spd_read_fail
+ li r5, ERR_DIMM_TYPE
+ cmpi 0,0,r3,SPD_UDIMM
+ beq do_cl
+ cmpi 0,0,r3,SPD_RDIMM
+ bne spd_fail
+ oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */
+
+do_cl:
+ READ_SPD(18) /* Get CAS Latency */
+ beq spd_read_fail
+ li r5,ERR_CL_VALUE
+ andi. r6,r3,SPD_CAS_3
+ beq cl_4
+ li r6,3
+ b set_cl
+cl_4:
+ andi. r6,r3,SPD_CAS_4
+ beq cl_5
+ li r6,4
+ b set_cl
+cl_5:
+ andi. r6,r3,SPD_CAS_5
+ beq spd_fail
+ li r6,5
+set_cl:
+ rlwimi r7,r6,24,5,7
+
+ READ_SPD(30) /* Get tRAS */
+ beq spd_read_fail
+ divwu r6,r3,r9
+ mullw r8,r6,r9
+ subf. r8,r8,r3
+ beq set_tras
+ addi r6,r6,1
+set_tras:
+ li r5,ERR_TRAS_FAIL
+ cmpi 0,0,r6,0x0F /* max supported value */
+ bgt spd_fail
+ rlwimi r7,r6,16,12,15
+
+ READ_SPD(29) /* Get tRCD */
+ beq spd_read_fail
+ /* right shift tRCD by 2 bits as per DDR2 spec */
+ rlwinm r3,r3,30,2,31
+ divwu r6,r3,r9
+ mullw r8,r6,r9
+ subf. r8,r8,r3
+ beq set_trcd
+ addi r6,r6,1
+set_trcd:
+ li r5,ERR_TRCD_FAIL
+ cmpi 0,0,r6,0x07 /* max supported value */
+ bgt spd_fail
+ rlwimi r7,r6,12,17,19
+
+ READ_SPD(27) /* Get tRP value */
+ beq spd_read_fail
+ rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */
+ divwu r6,r3,r9
+ mullw r8,r6,r9
+ subf. r8,r8,r3
+ beq set_trp
+ addi r6,r6,1
+set_trp:
+ li r5,ERR_TRP_FAIL
+ cmpi 0,0,r6,0x07 /* max supported value */
+ bgt spd_fail
+ rlwimi r7,r6,8,21,23
+
+ READ_SPD(36) /* Get tWR value */
+ beq spd_read_fail
+ rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */
+ divwu r6,r3,r9
+ mullw r8,r6,r9
+ subf. r8,r8,r3
+ beq set_twr
+ addi r6,r6,1
+set_twr:
+ addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */
+ li r5,ERR_TWR_FAIL
+ cmpi 0,0,r6,0x07 /* max supported value */
+ bgt spd_fail
+ rlwimi r7,r6,5,24,26
+
+ READ_SPD(42) /* Get tRFC */
+ beq spd_read_fail
+ li r5, ERR_TRFC_FAIL
+ /* Tsi108 spec: tRFC=(tRFC + 1)/2 */
+ addi r3,r3,1
+ rlwinm. r3,r3,31,1,31 /* divide by 2 */
+ beq spd_fail
+ divwu r6,r3,r9
+ mullw r8,r6,r9
+ subf. r8,r8,r3
+ beq set_trfc
+ addi r6,r6,1
+set_trfc:
+ cmpi 0,0,r6,0x1F /* max supported value */
+ bgt spd_fail
+ rlwimi r7,r6,0,27,31
+
+ stw r7,SD_TIMING(r4)
+ sync
+
+ /*
+ * The following two registers are set on per-DIMM basis.
+ * The SD_REFRESH and SD_TIMING settings are common for both DIMMS
+ */
+
+do_each_dimm:
+
+ /* Program SDRAM DIMM Control Register */
+
+ li r7, 0 /* clear r7 prior parameter collection */
+
+ READ_SPD(13) /* Get Primary SDRAM Width */
+ beq spd_read_fail
+ cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */
+ beq do_nbank
+ oris r7,r7,0x0010 /* Set MEM_WIDTH bit */
+
+do_nbank:
+ READ_SPD(17) /* Get Number of banks on SDRAM device */
+ beq spd_read_fail
+ /* Grendel only distinguish betw. 4 or 8-bank memory parts */
+ li r5,ERR_UNKNOWN_PART /* non-supported memory part */
+ cmpi 0,0,r3,4
+ beq do_nrank
+ cmpi 0,0,r3,8
+ bne spd_fail
+ ori r7,r7,0x1000
+
+do_nrank:
+ READ_SPD(5) /* Get # of Ranks */
+ beq spd_read_fail
+ li r5,ERR_NRANK_INVALID
+ andi. r6,r3,0x7 /* Use bits [2..0] only */
+ beq do_addr_mode
+ cmpi 0,0,r6,1
+ bgt spd_fail
+ rlwimi r7,r6,8,23,23
+
+do_addr_mode:
+ READ_SPD(4) /* Get # of Column Addresses */
+ beq spd_read_fail
+ li r5, ERR_ADDR_MODE
+ andi. r3,r3,0x0f /* cut off reserved bits */
+ cmpi 0,0,r3,8
+ ble spd_fail
+ cmpi 0,0,r3,15
+ bgt spd_fail
+ addi r6,r3,-8 /* calculate ADDR_MODE parameter */
+ rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */
+
+set_dimm_ctrl:
+#ifdef SDC_AUTOPRECH_EN
+ oris r7,r7,0x0001 /* set auto precharge EN bit */
+#endif
+ ori r7,r7,1 /* set ENABLE bit */
+ cmpi 0,0,r10,SPD_DIMM0
+ bne 1f
+ stw r7,SD_D0_CTRL(r4)
+ sync
+ b set_dimm_bar
+1:
+ stw r7,SD_D1_CTRL(r4)
+ sync
+
+
+ /* Program SDRAM DIMMx Base Address Register */
+
+set_dimm_bar:
+ READ_SPD(5) /* get # of Ranks */
+ beq spd_read_fail
+ andi. r7,r3,0x7
+ addi r7,r7,1
+ READ_SPD(31) /* Read DIMM rank density */
+ beq spd_read_fail
+ rlwinm r5,r3,27,29,31
+ rlwinm r6,r3,3,24,28
+ or r5,r6,r5 /* r5 = Normalized Rank Density byte */
+ lis r8, 0x0080 /* 128MB >> 4 */
+ mullw r8,r8,r5 /* r8 = (rank_size >> 4) */
+ mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */
+ neg r7,r8
+ rlwinm r7,r7,28,4,31
+ or r7,r7,r11 /* set ADDR field */
+ rlwinm r8,r8,12,20,31
+ add r11,r11,r8 /* set Base Addr for next DIMM */
+
+ cmpi 0,0,r10,SPD_DIMM0
+ bne set_dimm1_size
+ stw r7,SD_D0_BAR(r4)
+ sync
+ li r10,SPD_DIMM1
+ READ_SPD(0)
+ bne do_each_dimm
+ b spd_done
+
+set_dimm1_size:
+ stw r7,SD_D1_BAR(r4)
+ sync
+spd_done:
+ blr
+
+check_next_slot:
+ cmpi 0,0,r10,SPD_DIMM1
+ beq spd_read_fail
+ li r10,SPD_DIMM1
+ b do_first_dimm
+spd_read_fail:
+ ori r3,r0,0xdead
+ b err_hung
+spd_fail:
+ li r3,0x0bad
+ sync
+err_hung: /* hang here for debugging */
+ nop
+ nop
+ b err_hung
+
+#endif /* !SDC_HARDCODED_INIT */
diff --git a/board/freescale/mpc7448hpc2/config.mk b/board/freescale/mpc7448hpc2/config.mk
new file mode 100644
index 0000000..b2d6f76
--- /dev/null
+++ b/board/freescale/mpc7448hpc2/config.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2005 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -maltivec -mabi=altivec -msoft-float
diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
new file mode 100644
index 0000000..11747ca
--- /dev/null
+++ b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2005 Freescale Semiconductor, Inc.
+ *
+ * Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * modifications for the Tsi108 Emul Board by avb@Tundra
+ */
+
+/*
+ * board support/init functions for the
+ * Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform).
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include <fdt_support.h>
+#include <netdev.h>
+
+#undef DEBUG
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void tsi108_init_f (void);
+
+int display_mem_map (void);
+
+void after_reloc (ulong dest_addr)
+{
+ /*
+ * Jump to the main U-Boot board init code
+ */
+ board_init_r ((gd_t *) gd, dest_addr);
+ /* NOTREACHED */
+}
+
+/*
+ * Check Board Identity:
+ * report board type
+ */
+
+int checkboard (void)
+{
+ int l_type = 0;
+
+ printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
+ return (l_type);
+}
+
+/*
+ * Read Processor ID:
+ *
+ * report calling processor number
+ */
+
+int read_pid (void)
+{
+ return 0; /* we are on single CPU platform for a while */
+}
+
+long int dram_size (int board_type)
+{
+ return 0x20000000; /* 256M bytes */
+}
+
+phys_size_t initdram (int board_type)
+{
+ return dram_size (board_type);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+
+ return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#if defined(CONFIG_TSI108_ETH)
+ rc = tsi108_eth_initialize(bis);
+#endif
+ return rc;
+}
diff --git a/board/freescale/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c
new file mode 100644
index 0000000..9a1e407
--- /dev/null
+++ b/board/freescale/mpc7448hpc2/tsi108_init.c
@@ -0,0 +1,652 @@
+/*****************************************************************************
+ * (C) Copyright 2003; Tundra Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *****************************************************************************/
+
+/*----------------------------------------------------------------------------
+ * FILENAME: tsi108_init.c
+ *
+ * Originator: Alex Bounine
+ *
+ * DESCRIPTION:
+ * Initialization code for the Tundra Tsi108 bridge chip
+ *---------------------------------------------------------------------------*/
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <tsi108.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void mpicInit (int verbose);
+
+/*
+ * Configuration Options
+ */
+
+typedef struct {
+ ulong upper;
+ ulong lower;
+} PB2OCN_LUT_ENTRY;
+
+PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
+ /* 0 - 7 */
+ {0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
+
+ /* 8 - 15 */
+ {0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
+
+ /* 16 - 23 */
+ {0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
+ /* 24 - 31 */
+ {0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
+ {0x00000000, 0x00000241}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap + Translate) */
+ {0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */
+
+ {0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
+ {0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
+ {0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
+ {0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
+};
+
+#ifdef CONFIG_SYS_CLK_SPREAD
+typedef struct {
+ ulong ctrl0;
+ ulong ctrl1;
+} PLL_CTRL_SET;
+
+/*
+ * Clock Generator SPLL0 initialization values
+ * PLL0 configuration table for various PB_CLKO freq.
+ * Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
+ * Fout depends on required PB_CLKO. Based on Fref = 33 MHz
+ */
+
+static PLL_CTRL_SET pll0_config[8] = {
+ {0x00000000, 0x00000000}, /* 0: bypass */
+ {0x00000000, 0x00000000}, /* 1: reserved */
+ {0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */
+ {0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */
+ {0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */
+ {0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */
+ {0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */
+ {0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */
+};
+#endif /* CONFIG_SYS_CLK_SPREAD */
+
+/*
+ * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
+ * (based on recommended Tsi108 reference clock 33MHz)
+ */
+static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
+
+/*
+ * get_board_bus_clk ()
+ *
+ * returns the bus clock in Hz.
+ */
+unsigned long get_board_bus_clk (void)
+{
+ ulong i;
+
+ /* Detect PB clock freq. */
+ i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
+ i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
+
+ return pb_clk_sel[i] * 1000000;
+}
+
+/*
+ * board_early_init_f ()
+ *
+ * board-specific initialization executed from flash
+ */
+
+int board_early_init_f (void)
+{
+ ulong i;
+
+ gd->mem_clk = 0;
+ i = in32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
+ CG_PWRUP_STATUS);
+ i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
+ switch (i) {
+ case 0: /* external clock */
+ printf ("Using external clock\n");
+ break;
+ case 1: /* system clock */
+ gd->mem_clk = gd->bus_clk;
+ break;
+ case 4: /* 133 MHz */
+ case 5: /* 166 MHz */
+ case 6: /* 200 MHz */
+ gd->mem_clk = pb_clk_sel[i] * 1000000;
+ break;
+ default:
+ printf ("Invalid DDR2 clock setting\n");
+ return -1;
+ }
+ printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000);
+ printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
+ return 0;
+}
+
+/*
+ * board_early_init_r() - Tsi108 initialization function executed right after
+ * relocation. Contains code that cannot be executed from flash.
+ */
+
+int board_early_init_r (void)
+{
+ ulong temp, i;
+ ulong reg_val;
+ volatile ulong *reg_ptr;
+
+ reg_ptr =
+ (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
+
+ for (i = 0; i < 32; i++) {
+ *reg_ptr++ = 0x00000201; /* SWAP ENABLED */
+ *reg_ptr++ = 0x00;
+ }
+
+ __asm__ __volatile__ ("eieio");
+ __asm__ __volatile__ ("sync");
+
+ /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
+ 0x80000001);
+ __asm__ __volatile__ ("sync");
+
+ /* Make sure that OCN_BAR2 decoder is set (to allow following immediate
+ * read from SDRAM)
+ */
+
+ temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
+ __asm__ __volatile__ ("sync");
+
+ /*
+ * Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
+ * processor bus address space. Immediately after reset LUT and address
+ * translation are disabled for this BAR. Now we have to initialize LUT
+ * and switch from the BOOT mode to the normal operation mode.
+ *
+ * The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
+ * and covers 512MB of address space. To allow larger aperture we also
+ * have to relocate register window of Tsi108
+ *
+ * Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
+ * mode.
+ *
+ * initialize pointer to LUT associated with PB_OCN_BAR1
+ */
+ reg_ptr =
+ (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
+
+ for (i = 0; i < 32; i++) {
+ *reg_ptr++ = pb2ocn_lut1[i].lower;
+ *reg_ptr++ = pb2ocn_lut1[i].upper;
+ }
+
+ __asm__ __volatile__ ("sync");
+
+ /* Base addresses for CS0, CS1, CS2, CS3 */
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
+ 0x00000000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
+ 0x00100000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
+ 0x00200000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
+ 0x00300000);
+ __asm__ __volatile__ ("sync");
+
+ /* Masks for HLP banks */
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
+ 0xFFF00000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
+ 0xFFF00000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
+ 0xFFF00000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
+ 0xFFF00000);
+ __asm__ __volatile__ ("sync");
+
+ /* Set CTRL0 values for banks */
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
+ 0x7FFC44C2);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
+ 0x7FFC44C0);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
+ 0x7FFC44C0);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
+ 0x7FFC44C2);
+ __asm__ __volatile__ ("sync");
+
+ /* Set banks to latched mode, enabled, and other default settings */
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
+ 0x7C0F2000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
+ 0x7C0F2000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
+ 0x7C0F2000);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
+ 0x7C0F2000);
+ __asm__ __volatile__ ("sync");
+
+ /*
+ * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
+ * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
+ */
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
+ 0xE0000011);
+ __asm__ __volatile__ ("sync");
+
+ /* Make sure that OCN_BAR2 decoder is set (to allow following
+ * immediate read from SDRAM)
+ */
+
+ temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
+ __asm__ __volatile__ ("sync");
+
+ /*
+ * SRI: At this point we have enabled the HLP banks. That means we can
+ * now read from the NVRAM and initialize the environment variables.
+ * We will over-ride the env_init called in board_init_f
+ * This is really a work-around because, the HLP bank 1
+ * where NVRAM resides is not visible during board_init_f
+ * (arch/powerpc/lib/board.c)
+ * Alternatively, we could use the I2C EEPROM at start-up to configure
+ * and enable all HLP banks and not just HLP 0 as is being done for
+ * Taiga Rev. 2.
+ */
+
+ env_init ();
+
+#ifndef DISABLE_PBM
+
+ /*
+ * For IBM processors we have to set Address-Only commands generated
+ * by PBM that are different from ones set after reset.
+ */
+
+ temp = get_cpu_type ();
+
+ if ((CPU_750FX == temp) || (CPU_750GX == temp))
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
+ 0x00009955);
+#endif /* DISABLE_PBM */
+
+#ifdef CONFIG_PCI
+ /*
+ * Initialize PCI/X block
+ */
+
+ /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
+ PCI_PFAB_BAR0_UPPER, 0);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
+ 0xFB000001);
+ __asm__ __volatile__ ("sync");
+
+ /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
+
+ temp = in32(CONFIG_SYS_TSI108_CSR_BASE +
+ TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
+
+ temp &= ~0xFF00; /* Clear the BUS_NUM field */
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
+ temp);
+
+ /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
+ 0);
+ __asm__ __volatile__ ("sync");
+
+ /* This register is on the PCI side to interpret the address it receives
+ * and maps it as a IO address.
+ */
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
+ 0x00000001);
+ __asm__ __volatile__ ("sync");
+
+ /*
+ * Map PCI/X Memory Space
+ *
+ * Transactions directed from OCM to PCI Memory Space are directed
+ * from PB to PCI
+ * unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
+ * If address remapping is required the corresponding PCI_PFAB_MEM32
+ * and PCI_PFAB_PFMx register groups have to be configured.
+ *
+ * Map the path from the PCI/X bus into the system memory
+ *
+ * The memory mapped window assotiated with PCI P2O_BAR2 provides
+ * access to the system memory without address remapping.
+ * All system memory is opened for accesses initiated by PCI/X bus
+ * masters.
+ *
+ * Initialize LUT associated with PCI P2O_BAR2
+ *
+ * set pointer to LUT associated with PCI P2O_BAR2
+ */
+
+ reg_ptr =
+ (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
+
+#ifdef DISABLE_PBM
+
+ /* In case when PBM is disabled (no HW supported cache snoopng on PB)
+ * P2O_BAR2 is directly mapped into the system memory without address
+ * translation.
+ */
+
+ reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */
+
+ for (i = 0; i < 32; i++) {
+ *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
+ *reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */
+ }
+
+ /* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
+ reg_val = 0x00007500;
+#else
+
+ reg_val = 0x00000002; /* Destination port = PBM */
+
+ for (i = 0; i < 32; i++) {
+ *reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
+/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
+ *reg_ptr++ = 0x40000000;
+/* offset = 16MB, address translation is enabled to allow byte swapping */
+ reg_val += 0x01000000;
+ }
+
+/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
+ reg_val = 0x00007100;
+#endif
+
+ __asm__ __volatile__ ("eieio");
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
+ reg_val);
+ __asm__ __volatile__ ("sync");
+
+ /* Set 64-bit PCI bus address for system memory
+ * ( 0 is the best choice for easy mapping)
+ */
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
+ 0x00000000);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
+ 0x00000000);
+ __asm__ __volatile__ ("sync");
+
+#ifndef DISABLE_PBM
+ /*
+ * The memory mapped window assotiated with PCI P2O_BAR3 provides
+ * access to the system memory using SDRAM OCN port and address
+ * translation. This is alternative way to access SDRAM from PCI
+ * required for Tsi108 emulation testing.
+ * All system memory is opened for accesses initiated by
+ * PCI/X bus masters.
+ *
+ * Initialize LUT associated with PCI P2O_BAR3
+ *
+ * set pointer to LUT associated with PCI P2O_BAR3
+ */
+ reg_ptr =
+ (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
+
+ reg_val = 0x00000004; /* Destination port = SDC */
+
+ for (i = 0; i < 32; i++) {
+ *reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */
+
+/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
+ *reg_ptr++ = 0;
+
+/* offset = 16MB, address translation is enabled to allow byte swapping */
+ reg_val += 0x01000000;
+ }
+
+ __asm__ __volatile__ ("eieio");
+ __asm__ __volatile__ ("sync");
+
+ /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
+
+ reg_val =
+ in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
+ PCI_P2O_PAGE_SIZES);
+ reg_val &= ~0x00FF;
+ reg_val |= 0x0071;
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
+ reg_val);
+ __asm__ __volatile__ ("sync");
+
+ /* Set 64-bit base PCI bus address for window (0x20000000) */
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
+ 0x00000000);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
+ 0x20000000);
+ __asm__ __volatile__ ("sync");
+
+#endif /* !DISABLE_PBM */
+
+#ifdef ENABLE_PCI_CSR_BAR
+ /* open if required access to Tsi108 CSRs from the PCI/X bus */
+ /* enable BAR0 on the PCI/X bus */
+ reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE +
+ TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
+ reg_val |= 0x02;
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
+ reg_val);
+ __asm__ __volatile__ ("sync");
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
+ 0x00000000);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
+ CONFIG_SYS_TSI108_CSR_BASE);
+ __asm__ __volatile__ ("sync");
+
+#endif
+
+ /*
+ * Finally enable PCI/X Bus Master and Memory Space access
+ */
+
+ reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
+ reg_val |= 0x06;
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
+ __asm__ __volatile__ ("sync");
+
+#endif /* CONFIG_PCI */
+
+ /*
+ * Initialize MPIC outputs (interrupt pins):
+ * Interrupt routing on the Grendel Emul. Board:
+ * PB_INT[0] -> INT (CPU0)
+ * PB_INT[1] -> INT (CPU1)
+ * PB_INT[2] -> MCP (CPU0)
+ * PB_INT[3] -> MCP (CPU1)
+ * Set interrupt controller outputs as Level_Sensitive/Active_Low
+ */
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
+ __asm__ __volatile__ ("sync");
+
+ /*
+ * Ensure that Machine Check exception is enabled
+ * We need it to support PCI Bus probing (configuration reads)
+ */
+
+ reg_val = mfmsr ();
+ mtmsr(reg_val | MSR_ME);
+
+ return 0;
+}
+
+/*
+ * Needed to print out L2 cache info
+ * used in the misc_init_r function
+ */
+
+unsigned long get_l2cr (void)
+{
+ unsigned long l2controlreg;
+ asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
+ return l2controlreg;
+}
+
+/*
+ * misc_init_r()
+ *
+ * various things to do after relocation
+ *
+ */
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_SYS_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
+ ulong i;
+
+ /* Ensure that Spread-Spectrum is disabled */
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
+
+ /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
+ * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
+ */
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
+ 0x002e0044); /* D = 0.25% */
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
+ 0x00000039); /* BWADJ */
+
+ /* Initialize PLL0: CG_PB_CLKO */
+ /* Detect PB clock freq. */
+ i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
+ i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
+
+ out32 (CONFIG_SYS_TSI108_CSR_BASE +
+ TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE +
+ TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
+
+ /* Wait and set SSEN for both PLL0 and 1 */
+ udelay (1000);
+ out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
+ 0x802e0044); /* D=0.25% */
+ out32 (CONFIG_SYS_TSI108_CSR_BASE +
+ TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
+ 0x80000000 | pll0_config[i].ctrl0);
+#endif /* CONFIG_SYS_CLK_SPREAD */
+
+#ifdef CONFIG_SYS_L2
+ l2cache_enable ();
+#endif
+ printf ("BUS: %lu MHz\n", gd->bus_clk / 1000000);
+ printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
+
+ /*
+ * All the information needed to print the cache details is avaiblable
+ * at this point i.e. above call to l2cache_enable is the very last
+ * thing done with regards to enabling diabling the cache.
+ * So this seems like a good place to print all this information
+ */
+
+ printf ("CACHE: ");
+ switch (get_cpu_type()) {
+ case CPU_7447A:
+ printf ("L1 Instruction cache - 32KB 8-way");
+ (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
+ printf (" DISABLED\n");
+ printf ("L1 Data cache - 32KB 8-way");
+ (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
+ printf (" DISABLED\n");
+ printf ("Unified L2 cache - 512KB 8-way");
+ (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
+ printf (" DISABLED\n");
+ printf ("\n");
+ break;
+
+ case CPU_7448:
+ printf ("L1 Instruction cache - 32KB 8-way");
+ (get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
+ printf (" DISABLED\n");
+ printf ("L1 Data cache - 32KB 8-way");
+ (get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
+ printf (" DISABLED\n");
+ printf ("Unified L2 cache - 1MB 8-way");
+ (get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
+ printf (" DISABLED\n");
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
diff --git a/board/freescale/mpc8308rdb/Kconfig b/board/freescale/mpc8308rdb/Kconfig
new file mode 100644
index 0000000..48d25e5
--- /dev/null
+++ b/board/freescale/mpc8308rdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8308RDB
+
+config SYS_BOARD
+ default "mpc8308rdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8308RDB"
+
+endif
diff --git a/board/freescale/mpc8308rdb/MAINTAINERS b/board/freescale/mpc8308rdb/MAINTAINERS
new file mode 100644
index 0000000..07ff2abd
--- /dev/null
+++ b/board/freescale/mpc8308rdb/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8308RDB BOARD
+M: Ilya Yanok <yanok@emcraft.com>
+S: Maintained
+F: board/freescale/mpc8308rdb/
+F: include/configs/MPC8308RDB.h
+F: configs/MPC8308RDB_defconfig
diff --git a/board/freescale/mpc8308rdb/Makefile b/board/freescale/mpc8308rdb/Makefile
new file mode 100644
index 0000000..ec2b85d
--- /dev/null
+++ b/board/freescale/mpc8308rdb/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010
+# Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mpc8308rdb.o sdram.o
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
new file mode 100644
index 0000000..93e1c50
--- /dev/null
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <spi.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <vsc7385.h>
+#include <netdev.h>
+#include <fsl_esdhc.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+
+#define SPI_CS_MASK 0x00400000
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /* active low */
+ clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /* inactive high */
+ setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+}
+#endif /* CONFIG_MPC8XXX_SPI */
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
+static u8 read_board_info(void)
+{
+ u8 val8;
+ i2c_set_bus_num(0);
+
+ if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
+ return val8;
+ else
+ return 0;
+}
+
+int checkboard(void)
+{
+ static const char * const rev_str[] = {
+ "1.0",
+ "<reserved>",
+ "<reserved>",
+ "<reserved>",
+ "<unknown>",
+ };
+ u8 info;
+ int i;
+
+ info = read_board_info();
+ i = (!info) ? 4 : info & 0x03;
+
+ printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
+
+ return 0;
+}
+
+static struct pci_region pcie_regions_0[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE1_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+ .size = CONFIG_SYS_PCIE1_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+void pci_init_board(void)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+ law83xx_t *pcie_law = sysconf->pcielaw;
+ struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+ /* Deassert the resets in the control register */
+ out_be32(&sysconf->pecr1, 0xE0008000);
+ udelay(2000);
+
+ /* Configure PCI Express Local Access Windows */
+ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ mpc83xx_pcie_init(1, pcie_reg);
+}
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+#ifdef CONFIG_MPC8XXX_SPI
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+
+ /*
+ * Set proper bits in SICRH to allow SPI on header J8
+ *
+ * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
+ * switch. The pinmux configuration does not have a fine enough
+ * granularity to support both simultaneously.
+ */
+ clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
+ puts("WARNING: SPI enabled, TSEC2 support is broken\n");
+
+ /* Set header J8 SPI chip select output, disabled */
+ setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
+ setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+#endif
+
+#ifdef CONFIG_VSC7385_IMAGE
+ if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+ CONFIG_VSC7385_IMAGE_SIZE)) {
+ puts("Failure uploading VSC7385 microcode.\n");
+ return 1;
+ }
+#endif
+
+ return 0;
+}
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
+
+ return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, num_if = 0;
+
+ /* Initialize TSECs first */
+ rv = cpu_eth_init(bis);
+ if (rv >= 0)
+ num_if += rv;
+ else
+ printf("ERROR: failed to initialize TSECs.\n");
+
+ rv = pci_eth_init(bis);
+ if (rv >= 0)
+ num_if += rv;
+ else
+ printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+ return num_if;
+}
diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c
new file mode 100644
index 0000000..89b665e
--- /dev/null
+++ b/board/freescale/mpc8308rdb/sdram.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * Authors: Nick.Spence@freescale.com
+ * Wilson.Lo@freescale.com
+ * scottwood@freescale.com
+ *
+ * This files is mostly identical to the original from
+ * board\freescale\mpc8315erdb\sdram.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+ u32 msize_log2 = __ilog2(msize);
+
+ out_be32(&im->sysconf.ddrlaw[0].bar,
+ CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
+ out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+ out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+ out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+ out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+ /* Currently we use only one CS, so disable the other bank. */
+ out_be32(&im->ddr.cs_config[1], 0);
+
+ out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+ out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+ out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+ out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+ out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+ out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+ out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+ sync();
+
+ /* enable DDR controller */
+ setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+ sync();
+
+ return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+}
+
+phys_size_t initdram(int board_type)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize;
+
+ if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM */
+ msize = fixed_sdram();
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize;
+}
diff --git a/board/freescale/mpc8313erdb/Kconfig b/board/freescale/mpc8313erdb/Kconfig
new file mode 100644
index 0000000..145608f
--- /dev/null
+++ b/board/freescale/mpc8313erdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8313ERDB
+
+config SYS_BOARD
+ default "mpc8313erdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8313ERDB"
+
+endif
diff --git a/board/freescale/mpc8313erdb/MAINTAINERS b/board/freescale/mpc8313erdb/MAINTAINERS
new file mode 100644
index 0000000..807fb0b
--- /dev/null
+++ b/board/freescale/mpc8313erdb/MAINTAINERS
@@ -0,0 +1,9 @@
+MPC8313ERDB BOARD
+#M: -
+S: Maintained
+F: board/freescale/mpc8313erdb/
+F: include/configs/MPC8313ERDB.h
+F: configs/MPC8313ERDB_33_defconfig
+F: configs/MPC8313ERDB_66_defconfig
+F: configs/MPC8313ERDB_NAND_33_defconfig
+F: configs/MPC8313ERDB_NAND_66_defconfig
diff --git a/board/freescale/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile
new file mode 100644
index 0000000..77fad75
--- /dev/null
+++ b/board/freescale/mpc8313erdb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mpc8313erdb.o sdram.o
diff --git a/board/freescale/mpc8313erdb/README b/board/freescale/mpc8313erdb/README
new file mode 100644
index 0000000..be7ef32
--- /dev/null
+++ b/board/freescale/mpc8313erdb/README
@@ -0,0 +1,111 @@
+Freescale MPC8313ERDB Board
+-----------------------------------------
+
+1. Board Switches and Jumpers
+
+ S3 is used to set CONFIG_SYS_RESET_SOURCE.
+
+ To boot the image at 0xFE000000 in NOR flash, use these DIP
+ switch settings for S3 S4:
+
+ +------+ +------+
+ | | | **** |
+ | **** | | |
+ +------+ ON +------+ ON
+ 4321 4321
+ (where the '*' indicates the position of the tab of the switch.)
+
+ To boot the image at the beginning of NAND flash, use these
+ DIP switch settings for S3 S4:
+
+ +------+ +------+
+ | * | | *** |
+ | *** | | * |
+ +------+ ON +------+ ON
+ 4321 4321
+ (where the '*' indicates the position of the tab of the switch.)
+
+ When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
+
+2. Memory Map
+ The memory map looks like this:
+
+ 0x0000_0000 0x07ff_ffff DDR 128M
+ 0x8000_0000 0x8fff_ffff PCI MEM 256M
+ 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
+ 0xe000_0000 0xe00f_ffff IMMR 1M
+ 0xe200_0000 0xe20f_ffff PCI IO 16M
+ 0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K
+ 0xf000_0000 0xf001_ffff VSC7385 (CS2) 128K
+ 0xfa00_0000 0xfa00_7fff Board Status/ 32K
+ LED Control (CS3)
+ 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
+
+ When booting from NAND, NAND flash is CS0 and NOR flash
+ is CS1.
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+ include/configs/MPC8313ERDB.h
+
+ CONFIG_MPC83xx MPC83xx family
+ CONFIG_MPC831x MPC831x specific
+ CONFIG_MPC8313ERDB MPC8313ERDB board specific
+
+4. Compilation
+
+ Assuming you're using BASH (or similar) as your shell:
+
+ export CROSS_COMPILE=your-cross-compiler-prefix-
+ make distclean
+ make MPC8313ERDB_XXX_config
+ (where XXX is:
+ 33 - 33 MHz oscillator, boot from NOR flash
+ 66 - 66 MHz oscillator, boot from NOR flash
+ NAND_33 - 33 MHz oscillator, boot from NAND flash
+ NAND_66 - 66 MHz oscillator, boot from NAND flash)
+ make
+
+5. Downloading and Flashing Images
+
+5.1 Reflash U-boot Image using U-boot
+
+ NOR flash:
+
+ =>run tftpflash
+
+ You may want to try
+ =>tftpboot $loadaddr $uboot
+ first, to make sure that the TFTP load will succeed before it
+ goes ahead and wipes out your current firmware. And of course,
+ have an alternate means of programming the flash available
+ if the new u-boot doesn't boot.
+
+ NAND flash:
+
+ =>tftpboot $loadaddr <filename>
+ =>nand erase 0 0x80000
+ =>nand write $loadaddr 0 0x80000
+
+ ...where 0x80000 is the filesize rounded up to
+ the next 0x20000 increment.
+
+5.2 Downloading and Booting Linux Kernel
+
+ Ensure that all networking-related environment variables are set
+ properly (including ipaddr, serverip, gatewayip (if needed),
+ netmask, ethaddr, eth1addr, rootpath (if using NFS root),
+ fdtfile, and bootfile).
+
+ Then, do one of the following, depending on whether you
+ want an NFS root or a ramdisk root:
+
+ =>run nfsboot
+ or
+ =>run ramboot
+
+6 Notes
+
+ The console baudrate for MPC8313ERDB is 115200bps.
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
new file mode 100644
index 0000000..eac193e
--- /dev/null
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <pci.h>
+#include <mpc83xx.h>
+#include <vsc7385.h>
+#include <ns16550.h>
+#include <nand.h>
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
+#include <asm/gpio.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+ gd->flags |= GD_FLG_SILENT;
+#endif
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
+ mpc83xx_gpio_init_f();
+#endif
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
+ mpc83xx_gpio_init_r();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Freescale MPC8313ERDB\n");
+ return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static struct pci_region pci_regions[] = {
+ {
+ .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
+ .size = CONFIG_SYS_PCI1_MEM_SIZE,
+ .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
+ .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
+ .size = CONFIG_SYS_PCI1_MMIO_SIZE,
+ .flags = PCI_REGION_MEM
+ },
+ {
+ .bus_start = CONFIG_SYS_PCI1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
+ .size = CONFIG_SYS_PCI1_IO_SIZE,
+ .flags = PCI_REGION_IO
+ }
+};
+
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci_regions };
+
+ /* Enable all 3 PCI_CLK_OUTPUTs. */
+ clk->occr |= 0xe0000000;
+
+ /*
+ * Configure PCI Local Access Windows
+ */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+ mpc83xx_pci_init(1, reg);
+}
+
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+ int rc = 0;
+
+#ifdef CONFIG_VSC7385_IMAGE
+ if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+ CONFIG_VSC7385_IMAGE_SIZE)) {
+ puts("Failure uploading VSC7385 microcode.\n");
+ rc = 1;
+ }
+#endif
+
+ return rc;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+
+ return 0;
+}
+#endif
+#else /* CONFIG_SPL_BUILD */
+void board_init_f(ulong bootflag)
+{
+ board_early_init_f();
+ NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+ puts("NAND boot... ");
+ init_timebase();
+ initdram(0);
+ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
+ CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (gd->flags & GD_FLG_SILENT)
+ return;
+
+ if (c == '\n')
+ NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
+
+ NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
+}
+#endif
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
new file mode 100644
index 0000000..6282c3d
--- /dev/null
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ *
+ * Authors: Nick.Spence@freescale.com
+ * Wilson.Lo@freescale.com
+ * scottwood@freescale.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spd_sdram.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+static void resume_from_sleep(void)
+{
+ u32 magic = *(u32 *)0;
+
+ typedef void (*func_t)(void);
+ func_t resume = *(func_t *)4;
+
+ if (magic == 0xf5153ae5)
+ resume();
+
+ gd->flags &= ~GD_FLG_SILENT;
+ puts("\nResume from sleep failed: bad magic word\n");
+}
+#endif
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ u32 msize_log2 = __ilog2(msize);
+
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+ im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+
+ /*
+ * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+ * or the DDR2 controller may fail to initialize correctly.
+ */
+ __udelay(50000);
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[0].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+ CSBNDS_EA);
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+
+ /* Currently we use only one CS, so disable the other bank. */
+ im->ddr.cs_config[1] = 0;
+
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+ if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+ im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
+ else
+#endif
+ im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
+
+ im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
+
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ sync();
+
+ /* enable DDR controller */
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+#endif
+
+ return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile fsl_lbc_t *lbc = &im->im_lbc;
+ u32 msize;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ msize = fixed_sdram();
+
+ /* Local Bus setup lbcr and mrtpr */
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ sync();
+
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+ if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+ resume_from_sleep();
+#endif
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize;
+}
diff --git a/board/freescale/mpc8315erdb/Kconfig b/board/freescale/mpc8315erdb/Kconfig
new file mode 100644
index 0000000..f76b0d1
--- /dev/null
+++ b/board/freescale/mpc8315erdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8315ERDB
+
+config SYS_BOARD
+ default "mpc8315erdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8315ERDB"
+
+endif
diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS
new file mode 100644
index 0000000..938c152
--- /dev/null
+++ b/board/freescale/mpc8315erdb/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8315ERDB BOARD
+M: Dave Liu <daveliu@freescale.com>
+S: Maintained
+F: board/freescale/mpc8315erdb/
+F: include/configs/MPC8315ERDB.h
+F: configs/MPC8315ERDB_defconfig
diff --git a/board/freescale/mpc8315erdb/Makefile b/board/freescale/mpc8315erdb/Makefile
new file mode 100644
index 0000000..fbb68c5
--- /dev/null
+++ b/board/freescale/mpc8315erdb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mpc8315erdb.o sdram.o
diff --git a/board/freescale/mpc8315erdb/README b/board/freescale/mpc8315erdb/README
new file mode 100644
index 0000000..b32132d
--- /dev/null
+++ b/board/freescale/mpc8315erdb/README
@@ -0,0 +1,105 @@
+Freescale MPC8315ERDB Board
+-----------------------------------------
+
+1. Board Switches and Jumpers
+
+ S3 is used to set CONFIG_SYS_RESET_SOURCE.
+
+ To boot the image at 0xFE000000 in NOR flash, use these DIP
+ switch settings for S3 S4:
+
+ +------+ +------+
+ | | | **** |
+ | **** | | |
+ +------+ ON +------+ ON
+ 4321 4321
+ (where the '*' indicates the position of the tab of the switch.)
+
+ To boot the image at the beginning of NAND flash, use these
+ DIP switch settings for S3 S4:
+
+ +------+ +------+
+ | * | | *** |
+ | *** | | * |
+ +------+ ON +------+ ON
+ 4321 4321
+ (where the '*' indicates the position of the tab of the switch.)
+
+ When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
+
+2. Memory Map
+ The memory map looks like this:
+
+ 0x0000_0000 0x07ff_ffff DDR 128M
+ 0x8000_0000 0x8fff_ffff PCI MEM 256M
+ 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
+ 0xe000_0000 0xe00f_ffff IMMR 1M
+ 0xe030_0000 0xe03f_ffff PCI IO 1M
+ 0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
+ 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
+
+ When booting from NAND, NAND flash is CS0 and NOR flash
+ is CS1.
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+ include/configs/MPC8315ERDB.h
+
+ CONFIG_MPC83xx MPC83xx family
+ CONFIG_MPC831x MPC831x specific
+ CONFIG_MPC8315 MPC8315 specific
+ CONFIG_MPC8315ERDB MPC8315ERDB board specific
+
+4. Compilation
+
+ Assuming you're using BASH (or similar) as your shell:
+
+ export CROSS_COMPILE=your-cross-compiler-prefix-
+ make distclean
+ make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
+ make all
+
+5. Downloading and Flashing Images
+
+5.1 Reflash U-boot Image using U-boot
+
+ NOR flash:
+
+ tftp 40000 u-boot.bin
+ protect off all
+ erase fe000000 fe1fffff
+
+ cp.b 40000 fe000000 xxxx
+ protect on all
+
+ You have to supply the correct byte count with 'xxxx'
+ from the TFTP result log.
+
+ NAND flash:
+
+ =>tftpboot $loadaddr <filename>
+ =>nand erase 0 0x80000
+ =>nand write $loadaddr 0 0x80000
+
+ ...where 0x80000 is the filesize rounded up to
+ the next 0x20000 increment.
+
+5.2 Downloading and Booting Linux Kernel
+
+ Ensure that all networking-related environment variables are set
+ properly (including ipaddr, serverip, gatewayip (if needed),
+ netmask, ethaddr, eth1addr, rootpath (if using NFS root),
+ fdtfile, and bootfile).
+
+ Then, do one of the following, depending on whether you
+ want an NFS root or a ramdisk root:
+
+ =>run nfsboot
+ or
+ =>run ramboot
+
+6 Notes
+
+ The console baudrate for MPC8315ERDB is 115200bps.
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
new file mode 100644
index 0000000..ed611c5
--- /dev/null
+++ b/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -0,0 +1,246 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+ gd->flags |= GD_FLG_SILENT;
+
+ return 0;
+}
+
+#ifndef CONFIG_NAND_SPL
+
+static u8 read_board_info(void)
+{
+ u8 val8;
+ i2c_set_bus_num(0);
+
+ if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
+ return val8;
+ else
+ return 0;
+}
+
+int checkboard(void)
+{
+ static const char * const rev_str[] = {
+ "0.0",
+ "0.1",
+ "1.0",
+ "1.1",
+ "<unknown>",
+ };
+ u8 info;
+ int i;
+
+ info = read_board_info();
+ i = (!info) ? 4: info & 0x03;
+
+ printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
+
+ return 0;
+}
+
+static struct pci_region pci_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+ size: CONFIG_SYS_PCI_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+ size: CONFIG_SYS_PCI_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+ {
+ bus_start: CONFIG_SYS_PCI_IO_BASE,
+ phys_start: CONFIG_SYS_PCI_IO_PHYS,
+ size: CONFIG_SYS_PCI_IO_SIZE,
+ flags: PCI_REGION_IO
+ }
+};
+
+static struct pci_region pcie_regions_0[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE1_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+ .size = CONFIG_SYS_PCIE1_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+static struct pci_region pcie_regions_1[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE2_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+ .size = CONFIG_SYS_PCIE2_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile sysconf83xx_t *sysconf = &immr->sysconf;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ volatile law83xx_t *pcie_law = sysconf->pcielaw;
+ struct pci_region *reg[] = { pci_regions };
+ struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+
+ /* Enable all 3 PCI_CLK_OUTPUTs. */
+ clk->occr |= 0xe0000000;
+
+ /*
+ * Configure PCI Local Access Windows
+ */
+ pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+ pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+ mpc83xx_pci_init(1, reg);
+
+ /* Configure the clock for PCIE controller */
+ clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+ SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+ /* Deassert the resets in the control register */
+ out_be32(&sysconf->pecr1, 0xE0008000);
+ out_be32(&sysconf->pecr2, 0xE0008000);
+ udelay(2000);
+
+ /* Configure PCI Express Local Access Windows */
+ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ mpc83xx_pcie_init(2, pcie_reg);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void fdt_tsec1_fixup(void *fdt, bd_t *bd)
+{
+ const char disabled[] = "disabled";
+ const char *path;
+ int ret;
+
+ if (hwconfig_arg_cmp("board_type", "tsec1")) {
+ return;
+ } else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
+ printf("NOTICE: No or unknown board_type hwconfig specified.\n"
+ " Assuming board with TSEC1.\n");
+ return;
+ }
+
+ ret = fdt_path_offset(fdt, "/aliases");
+ if (ret < 0) {
+ printf("WARNING: can't find /aliases node\n");
+ return;
+ }
+
+ path = fdt_getprop(fdt, ret, "ethernet0", NULL);
+ if (!path) {
+ printf("WARNING: can't find ethernet0 alias\n");
+ return;
+ }
+
+ do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+ fdt_fixup_dr_usb(blob, bd);
+ fdt_tsec1_fixup(blob, bd);
+
+ return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Initialize TSECs first */
+ return pci_eth_init(bis);
+}
+
+#else /* CONFIG_NAND_SPL */
+
+int checkboard(void)
+{
+ puts("Board: Freescale MPC8315ERDB\n");
+ return 0;
+}
+
+void board_init_f(ulong bootflag)
+{
+ board_early_init_f();
+ NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
+ CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+ puts("NAND boot... ");
+ init_timebase();
+ initdram(0);
+ relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+ CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (gd->flags & GD_FLG_SILENT)
+ return;
+
+ if (c == '\n')
+ NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
+
+ NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
+}
+
+#endif /* CONFIG_NAND_SPL */
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
new file mode 100644
index 0000000..6c94312
--- /dev/null
+++ b/board/freescale/mpc8315erdb/sdram.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Authors: Nick.Spence@freescale.com
+ * Wilson.Lo@freescale.com
+ * scottwood@freescale.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spd_sdram.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void resume_from_sleep(void)
+{
+ u32 magic = *(u32 *)0;
+
+ typedef void (*func_t)(void);
+ func_t resume = *(func_t *)4;
+
+ if (magic == 0xf5153ae5)
+ resume();
+
+ gd->flags &= ~GD_FLG_SILENT;
+ puts("\nResume from sleep failed: bad magic word\n");
+}
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+static long fixed_sdram(void)
+{
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+ u32 msize_log2 = __ilog2(msize);
+
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+ im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+
+ /*
+ * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+ * or the DDR2 controller may fail to initialize correctly.
+ */
+ __udelay(50000);
+
+ im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+
+ /* Currently we use only one CS, so disable the other bank. */
+ im->ddr.cs_config[1] = 0;
+
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+
+ if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
+ else
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ sync();
+
+ /* enable DDR controller */
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+ sync();
+
+ return msize;
+}
+#else
+static long fixed_sdram(void)
+{
+ return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+}
+#endif /* CONFIG_SYS_RAMBOOT */
+
+phys_size_t initdram(int board_type)
+{
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ u32 msize;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM */
+ msize = fixed_sdram();
+
+ if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
+ resume_from_sleep();
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize;
+}
diff --git a/board/freescale/mpc8323erdb/Kconfig b/board/freescale/mpc8323erdb/Kconfig
new file mode 100644
index 0000000..acf8122
--- /dev/null
+++ b/board/freescale/mpc8323erdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8323ERDB
+
+config SYS_BOARD
+ default "mpc8323erdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8323ERDB"
+
+endif
diff --git a/board/freescale/mpc8323erdb/MAINTAINERS b/board/freescale/mpc8323erdb/MAINTAINERS
new file mode 100644
index 0000000..05057c0
--- /dev/null
+++ b/board/freescale/mpc8323erdb/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8323ERDB BOARD
+M: Michael Barkowski <michael.barkowski@freescale.com>
+S: Maintained
+F: board/freescale/mpc8323erdb/
+F: include/configs/MPC8323ERDB.h
+F: configs/MPC8323ERDB_defconfig
diff --git a/board/freescale/mpc8323erdb/Makefile b/board/freescale/mpc8323erdb/Makefile
new file mode 100644
index 0000000..f2e7497
--- /dev/null
+++ b/board/freescale/mpc8323erdb/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mpc8323erdb.o
diff --git a/board/freescale/mpc8323erdb/README b/board/freescale/mpc8323erdb/README
new file mode 100644
index 0000000..6f89829
--- /dev/null
+++ b/board/freescale/mpc8323erdb/README
@@ -0,0 +1,71 @@
+Freescale MPC8323ERDB Board
+-----------------------------------------
+
+1. Memory Map
+ The memory map looks like this:
+
+ 0x0000_0000 0x03ff_ffff DDR 64M
+ 0x8000_0000 0x8fff_ffff PCI MEM 256M
+ 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
+ 0xe000_0000 0xe00f_ffff IMMR 1M
+ 0xd000_0000 0xd3ff_ffff PCI IO 64M
+ 0xfe00_0000 0xfeff_ffff NOR FLASH (CS0) 16M
+
+2. Compilation
+
+ Assuming you're using BASH (or similar) as your shell:
+
+ export CROSS_COMPILE=your-cross-compiler-prefix-
+ make distclean
+ make MPC8323ERDB_config
+ make
+
+3. Downloading and Flashing Images
+
+3.1 Reflash U-boot Image using U-boot
+
+ N.b, have an alternate means of programming
+ the flash available if the new u-boot doesn't boot.
+
+ First try a:
+
+ tftpboot $loadaddr $uboot
+
+ to make sure that the TFTP load will succeed before
+ an erase goes ahead and wipes out your current firmware.
+ Then do a:
+
+ run tftpflash
+
+ which is a shorter version of the manual sequence:
+
+ tftp $loadaddr u-boot.bin
+ protect off fe000000 +$filesize
+ erase fe000000 +$filesize
+ cp.b $loadaddr fe000000 $filesize
+
+ To keep your old u-boot's environment variables, do a:
+
+ saveenv
+
+ prior to resetting the board.
+
+3.2 Downloading and Booting Linux Kernel
+
+ Ensure that all networking-related environment variables are set
+ properly (including ipaddr, serverip, gatewayip (if needed),
+ netmask, ethaddr, eth1addr, rootpath (if using NFS root),
+ fdtfile, and bootfile).
+
+ Then, do one of the following, depending on whether you
+ want an NFS root or a ramdisk root:
+
+ run nfsboot
+
+ or
+
+ run ramboot
+
+4 Notes
+
+ The console baudrate for MPC8323ERDB is 115200bps.
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
new file mode 100644
index 0000000..0a0152a
--- /dev/null
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Michael Barkowski <michael.barkowski@freescale.com>
+ * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <command.h>
+#include <libfdt.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#include <asm/mmu.h>
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* UCC3 */
+ {1, 0, 1, 0, 1}, /* TxD0 */
+ {1, 1, 1, 0, 1}, /* TxD1 */
+ {1, 2, 1, 0, 1}, /* TxD2 */
+ {1, 3, 1, 0, 1}, /* TxD3 */
+ {1, 9, 1, 0, 1}, /* TxER */
+ {1, 12, 1, 0, 1}, /* TxEN */
+ {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
+
+ {1, 4, 2, 0, 1}, /* RxD0 */
+ {1, 5, 2, 0, 1}, /* RxD1 */
+ {1, 6, 2, 0, 1}, /* RxD2 */
+ {1, 7, 2, 0, 1}, /* RxD3 */
+ {1, 8, 2, 0, 1}, /* RxER */
+ {1, 10, 2, 0, 1}, /* RxDV */
+ {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
+ {1, 11, 2, 0, 1}, /* COL */
+ {1, 13, 2, 0, 1}, /* CRS */
+
+ /* UCC2 */
+ {0, 18, 1, 0, 1}, /* TxD0 */
+ {0, 19, 1, 0, 1}, /* TxD1 */
+ {0, 20, 1, 0, 1}, /* TxD2 */
+ {0, 21, 1, 0, 1}, /* TxD3 */
+ {0, 27, 1, 0, 1}, /* TxER */
+ {0, 30, 1, 0, 1}, /* TxEN */
+ {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
+
+ {0, 22, 2, 0, 1}, /* RxD0 */
+ {0, 23, 2, 0, 1}, /* RxD1 */
+ {0, 24, 2, 0, 1}, /* RxD2 */
+ {0, 25, 2, 0, 1}, /* RxD3 */
+ {0, 26, 1, 0, 1}, /* RxER */
+ {0, 28, 2, 0, 1}, /* Rx_DV */
+ {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
+ {0, 29, 2, 0, 1}, /* COL */
+ {0, 31, 2, 0, 1}, /* CRS */
+
+ {3, 4, 3, 0, 2}, /* MDIO */
+ {3, 5, 1, 0, 2}, /* MDC */
+
+ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+int fixed_sdram(void);
+
+phys_size_t initdram(int board_type)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+
+ msize = fixed_sdram();
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return (msize * 1024 * 1024);
+}
+
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = 0;
+ u32 ddr_size;
+ u32 ddr_size_log2;
+
+ msize = CONFIG_SYS_DDR_SIZE;
+ for (ddr_size = msize << 20, ddr_size_log2 = 0;
+ (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
+ if (ddr_size & 1) {
+ return -1;
+ }
+ }
+ im->sysconf.ddrlaw[0].ar =
+ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+ im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ __asm__ __volatile__ ("sync");
+ udelay(200);
+
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+ __asm__ __volatile__ ("sync");
+ return msize;
+}
+
+int checkboard(void)
+{
+ puts("Board: Freescale MPC8323ERDB\n");
+ return 0;
+}
+
+static struct pci_region pci_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ }
+};
+
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci_regions };
+
+ /* Enable all 3 PCI_CLK_OUTPUTs. */
+ clk->occr |= 0xe0000000;
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+ mpc83xx_pci_init(1, reg);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
+int mac_read_from_eeprom(void)
+{
+ uchar buf[28];
+ char str[18];
+ int i = 0;
+ unsigned int crc = 0;
+ unsigned char enetvar[32];
+
+ /* Read MAC addresses from EEPROM */
+ if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
+ printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR);
+ } else {
+ uint32_t crc_buf;
+
+ memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
+
+ if (crc32(crc, buf, 24) == crc_buf) {
+ printf("Reading MAC from EEPROM\n");
+ for (i = 0; i < 4; i++) {
+ if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
+ sprintf(str,
+ "%02X:%02X:%02X:%02X:%02X:%02X",
+ buf[i * 6], buf[i * 6 + 1],
+ buf[i * 6 + 2], buf[i * 6 + 3],
+ buf[i * 6 + 4], buf[i * 6 + 5]);
+ sprintf((char *)enetvar,
+ i ? "eth%daddr" : "ethaddr", i);
+ setenv((char *)enetvar, str);
+ }
+ }
+ }
+ }
+ return 0;
+}
+#endif /* CONFIG_I2C_MAC_OFFSET */
diff --git a/board/freescale/mpc832xemds/Kconfig b/board/freescale/mpc832xemds/Kconfig
new file mode 100644
index 0000000..e4cfa15
--- /dev/null
+++ b/board/freescale/mpc832xemds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC832XEMDS
+
+config SYS_BOARD
+ default "mpc832xemds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC832XEMDS"
+
+endif
diff --git a/board/freescale/mpc832xemds/MAINTAINERS b/board/freescale/mpc832xemds/MAINTAINERS
new file mode 100644
index 0000000..56d7073
--- /dev/null
+++ b/board/freescale/mpc832xemds/MAINTAINERS
@@ -0,0 +1,10 @@
+MPC832XEMDS BOARD
+M: Dave Liu <daveliu@freescale.com>
+S: Maintained
+F: board/freescale/mpc832xemds/
+F: include/configs/MPC832XEMDS.h
+F: configs/MPC832XEMDS_defconfig
+F: configs/MPC832XEMDS_ATM_defconfig
+F: configs/MPC832XEMDS_HOST_33_defconfig
+F: configs/MPC832XEMDS_HOST_66_defconfig
+F: configs/MPC832XEMDS_SLAVE_defconfig
diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile
new file mode 100644
index 0000000..6676351
--- /dev/null
+++ b/board/freescale/mpc832xemds/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc832xemds.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc832xemds/README b/board/freescale/mpc832xemds/README
new file mode 100644
index 0000000..4142aa9
--- /dev/null
+++ b/board/freescale/mpc832xemds/README
@@ -0,0 +1,128 @@
+Freescale MPC832XEMDS Board
+-----------------------------------------
+1. Board Switches and Jumpers
+1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
+ For some reason, the HW designers describe the switch settings
+ in terms of 0 and 1, and then map that to physical switches where
+ the label "On" refers to logic 0 and "Off" is logic 1.
+
+ Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
+ bits may contribute to signals that are numbered based at 0,
+ and some of those signals may be high-bit-number-0 too. Heed
+ well the names and labels and do not get confused.
+
+ "Off" == 1
+ "On" == 0
+
+ SW3 is switch 18 as silk-screened onto the board.
+ SW4[8] is the bit labeled 8 on Switch 4.
+ SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
+ SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
+ SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
+ and bits labeled 8 is set as "Off".
+
+1.1 For the MPC832XEMDS PROTO Board
+
+ First, make sure the board default setting is consistent with the document
+ shipped with your board. Then apply the following setting:
+ SW3[1-8]= 0000_1000 (core PLL setting, core enable)
+ SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
+ SW5[1-8]= 0010_0110 (Boot from high end)
+ SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus)
+ SW7[1-8]= 1000_0011 (QE PLL setting)
+
+ ENET3/4 MII mode settings:
+ J1 1-2 (ETH3_TXER)
+ J2 2-3 (MII mode)
+ J3 2-3 (MII mode)
+ J4 2-3 (ADSL clockOscillator)
+ J5 1-2 (ETH4_TXER)
+ J6 2-3 (ClockOscillator)
+ JP1 removed (don't force PORESET)
+ JP2 mounted (ETH4/2 MII)
+ JP3 mounted (ETH3 MII)
+ JP4 mounted (HRCW from BCSR)
+
+ ENET3/4 RMII mode settings:
+ J1 1-2 (ETH3_TXER)
+ J2 1-2 (RMII mode)
+ J3 1-2 (RMII mode)
+ J4 2-3 (ADSL clockOscillator)
+ J5 1-2 (ETH4_TXER)
+ J6 2-3 (ClockOscillator)
+ JP1 removed (don't force PORESET)
+ JP2 removed (ETH4/2 RMII)
+ JP3 removed (ETH3 RMII)
+ JP4 removed (HRCW from FLASH)
+
+ on board Oscillator: 66M
+
+
+2. Memory Map
+
+2.1 The memory map should look pretty much like this:
+
+ 0x0000_0000 0x7fff_ffff DDR 2G
+ 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
+ 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
+ 0xc000_0000 0xdfff_ffff Empty 512M
+ 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
+ 0xe020_0000 0xe02f_ffff Empty 1M
+ 0xe030_0000 0xe03f_ffff PCI IO 1M
+ 0xe040_0000 0xefff_ffff Empty 252M
+ 0xf400_0000 0xf7ff_ffff Empty 64M
+ 0xf800_0000 0xf800_7fff BCSR on CS1 32K
+ 0xf800_8000 0xf800_ffff PIB CS2 32K
+ 0xf801_0000 0xf801_7fff PIB CS3 32K
+ 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
+
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+ include/configs/MPC832XEPB.h
+
+ CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x
+ CONFIG_MPC832x MPC832x specific
+ CONFIG_MPC832XEMDS MPC832XEMDS board specific
+
+4. Compilation
+
+ Assuming you're using BASH shell:
+
+ export CROSS_COMPILE=your-cross-compile-prefix
+ cd u-boot
+ make distclean
+ make MPC832XEMDS_config
+ make
+
+ MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI:
+
+ 1)Make sure the DIP SW support PCI mode as described in Section 1.1.
+
+ 2)To Make U-Boot image support PCI 33MHz, use
+ Make MPC832XEMDS_HOST_33_config
+
+ 3)To Make U-Boot image support PCI 66MHz, use
+ Make MPC832XEMDS_HOST_66M_config
+
+5. Downloading and Flashing Images
+
+5.0 Download over network:
+
+ tftp 10000 u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+ tftp 20000 u-boot.bin
+ protect off fe000000 fe0fffff
+ erase fe000000 fe0fffff
+ cp.b 20000 fe000000 xxxx
+
+You have to supply the correct byte count with 'xxxx' from the TFTP result log.
+Maybe 3ffff will work too, that corresponds to the erased sectors.
+
+
+6. Notes
+ 1) The console baudrate for MPC832XEMDS is 115200bps.
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
new file mode 100644
index 0000000..adf4254
--- /dev/null
+++ b/board/freescale/mpc832xemds/mpc832xemds.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <command.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#include <asm/mmu.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
+#endif
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* ETH3 */
+ {1, 0, 1, 0, 1}, /* TxD0 */
+ {1, 1, 1, 0, 1}, /* TxD1 */
+ {1, 2, 1, 0, 1}, /* TxD2 */
+ {1, 3, 1, 0, 1}, /* TxD3 */
+ {1, 9, 1, 0, 1}, /* TxER */
+ {1, 12, 1, 0, 1}, /* TxEN */
+ {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
+
+ {1, 4, 2, 0, 1}, /* RxD0 */
+ {1, 5, 2, 0, 1}, /* RxD1 */
+ {1, 6, 2, 0, 1}, /* RxD2 */
+ {1, 7, 2, 0, 1}, /* RxD3 */
+ {1, 8, 2, 0, 1}, /* RxER */
+ {1, 10, 2, 0, 1}, /* RxDV */
+ {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
+ {1, 11, 2, 0, 1}, /* COL */
+ {1, 13, 2, 0, 1}, /* CRS */
+
+ /* ETH4 */
+ {1, 18, 1, 0, 1}, /* TxD0 */
+ {1, 19, 1, 0, 1}, /* TxD1 */
+ {1, 20, 1, 0, 1}, /* TxD2 */
+ {1, 21, 1, 0, 1}, /* TxD3 */
+ {1, 27, 1, 0, 1}, /* TxER */
+ {1, 30, 1, 0, 1}, /* TxEN */
+ {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */
+
+ {1, 22, 2, 0, 1}, /* RxD0 */
+ {1, 23, 2, 0, 1}, /* RxD1 */
+ {1, 24, 2, 0, 1}, /* RxD2 */
+ {1, 25, 2, 0, 1}, /* RxD3 */
+ {1, 26, 1, 0, 1}, /* RxER */
+ {1, 28, 2, 0, 1}, /* Rx_DV */
+ {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
+ {1, 29, 2, 0, 1}, /* COL */
+ {1, 31, 2, 0, 1}, /* CRS */
+
+ {3, 4, 3, 0, 2}, /* MDIO */
+ {3, 5, 1, 0, 2}, /* MDC */
+
+ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+int board_early_init_f(void)
+{
+ volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
+
+ /* Enable flash write */
+ bcsr[9] &= ~0x08;
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_PQ_MDS_PIB
+ pib_init();
+#endif
+ return 0;
+}
+
+int fixed_sdram(void);
+
+phys_size_t initdram(int board_type)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+
+ msize = fixed_sdram();
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return (msize * 1024 * 1024);
+}
+
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = 0;
+ u32 ddr_size;
+ u32 ddr_size_log2;
+
+ msize = CONFIG_SYS_DDR_SIZE;
+ for (ddr_size = msize << 20, ddr_size_log2 = 0;
+ (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
+ if (ddr_size & 1) {
+ return -1;
+ }
+ }
+ im->sysconf.ddrlaw[0].ar =
+ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+#if (CONFIG_SYS_DDR_SIZE != 128)
+#warning Currenly any ddr size other than 128 is not supported
+#endif
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+ im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ __asm__ __volatile__ ("sync");
+ udelay(200);
+
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+ __asm__ __volatile__ ("sync");
+ return msize;
+}
+
+int checkboard(void)
+{
+ puts("Board: Freescale MPC832XEMDS\n");
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
new file mode 100644
index 0000000..e8b2b11
--- /dev/null
+++ b/board/freescale/mpc832xemds/pci.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * PCI Configuration space access support for MPC83xx PCI Bridge
+ */
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+#include "../common/pq-mds-pib.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
+
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+ size: CONFIG_SYS_PCI2_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_IO_BASE,
+ phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+ size: CONFIG_SYS_PCI2_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+ size: CONFIG_SYS_PCI2_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
+#endif
+
+void pci_init_board(void)
+#ifdef CONFIG_PCISLAVE
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
+ struct pci_region *reg[] = { pci1_regions };
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+ mpc83xx_pci_init(1, reg);
+
+ /*
+ * Configure PCI Inbound Translation Windows
+ */
+ pci_ctrl[0].pitar0 = 0x0;
+ pci_ctrl[0].pibar0 = 0x0;
+ pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
+ PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
+
+ pci_ctrl[0].pitar1 = 0x0;
+ pci_ctrl[0].pibar1 = 0x0;
+ pci_ctrl[0].piebar1 = 0x0;
+ pci_ctrl[0].piwar1 &= ~PIWAR_EN;
+
+ pci_ctrl[0].pitar2 = 0x0;
+ pci_ctrl[0].pibar2 = 0x0;
+ pci_ctrl[0].piebar2 = 0x0;
+ pci_ctrl[0].piwar2 &= ~PIWAR_EN;
+
+ /* Unlock the configuration bit */
+ mpc83xx_pcislave_unlock(0);
+ printf("PCI: Agent mode enabled\n");
+}
+#else
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+ struct pci_region *reg[] = { pci1_regions };
+#else
+ struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
+
+ /* initialize the PCA9555PW IO expander on the PIB board */
+ pib_init();
+
+#if defined(CONFIG_PCI_66M)
+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+ printf("PCI clock is 66MHz\n");
+#elif defined(CONFIG_PCI_33M)
+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
+ OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
+ printf("PCI clock is 33MHz\n");
+#else
+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+ printf("PCI clock is 66MHz\n");
+#endif
+ udelay(2000);
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
+
+ udelay(2000);
+
+#ifndef CONFIG_MPC83XX_PCI2
+ mpc83xx_pci_init(1, reg);
+#else
+ mpc83xx_pci_init(2, reg);
+#endif
+}
+#endif /* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig
new file mode 100644
index 0000000..51f0b34
--- /dev/null
+++ b/board/freescale/mpc8349emds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8349EMDS
+
+config SYS_BOARD
+ default "mpc8349emds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8349EMDS"
+
+endif
diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS
new file mode 100644
index 0000000..141e77a
--- /dev/null
+++ b/board/freescale/mpc8349emds/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8349EMDS BOARD
+M: Kim Phillips <kim.phillips@freescale.com>
+S: Maintained
+F: board/freescale/mpc8349emds/
+F: include/configs/MPC8349EMDS.h
+F: configs/MPC8349EMDS_defconfig
diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile
new file mode 100644
index 0000000..5c315f9
--- /dev/null
+++ b/board/freescale/mpc8349emds/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8349emds.o
+obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c
new file mode 100644
index 0000000..aae003d
--- /dev/null
+++ b/board/freescale/mpc8349emds/ddr.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
+ */
+ {2, 300, 4, 4, 2, 0},
+ {2, 365, 4, 6, 2, 0},
+ {2, 450, 4, 7, 2, 0},
+ {2, 850, 4, 31, 2, 0},
+ {1, 300, 4, 4, 2, 0},
+ {1, 365, 4, 6, 2, 0},
+ {1, 450, 4, 7, 2, 0},
+ {1, 850, 4, 31, 2, 0},
+ {}
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ unsigned int i;
+ ulong ddr_freq;
+
+ if (ctrl_num != 0) /* we have only one controller */
+ return;
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (pdimm[i].n_ranks)
+ break;
+ }
+ if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
+ return;
+
+ pbsp = udimm0;
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm[i].n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->twot_en = pbsp->force_2t;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->twot_en = pbsp_highest->force_2t;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+
+found:
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ popts->dqs_config = 0; /* only true DQS signal is used on board */
+}
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
new file mode 100644
index 0000000..02b5040
--- /dev/null
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -0,0 +1,285 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spi.h>
+#include <miiphy.h>
+#ifdef CONFIG_SYS_FSL_DDR2
+#include <fsl_ddr_sdram.h>
+#else
+#include <spd_sdram.h>
+#endif
+
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+int fixed_sdram(void);
+void sdram_init(void);
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+int board_early_init_f (void)
+{
+ volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
+
+ /* Enable flash write */
+ bcsr[1] &= ~0x01;
+
+#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
+ /* Use USB PHY on SYS board */
+ bcsr[5] |= 0x02;
+#endif
+
+ return 0;
+}
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
+
+phys_size_t initdram (int board_type)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ phys_size_t msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+#ifndef CONFIG_SYS_FSL_DDR2
+ msize = spd_sdram() * 1024 * 1024;
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ ddr_enable_ecc(msize);
+#endif
+#else
+ msize = fsl_ddr_sdram();
+#endif
+#else
+ msize = fixed_sdram() * 1024 * 1024;
+#endif
+ /*
+ * Initialize SDRAM if it is on local bus.
+ */
+ sdram_init();
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE;
+ u32 ddr_size = msize << 20; /* DDR size in bytes */
+ u32 ddr_size_log2 = __ilog2(ddr_size);
+
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
+#if (CONFIG_SYS_DDR_SIZE != 256)
+#warning Currenly any ddr size other than 256 is not supported
+#endif
+#ifdef CONFIG_DDR_II
+ im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
+ im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+#else
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[2].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+ im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
+
+ /* currently we use only one CS, so disable the other banks */
+ im->ddr.cs_config[0] = 0;
+ im->ddr.cs_config[1] = 0;
+ im->ddr.cs_config[3] = 0;
+
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+
+ im->ddr.sdram_cfg =
+ SDRAM_CFG_SREN
+#if defined(CONFIG_DDR_2T_TIMING)
+ | SDRAM_CFG_2T_EN
+#endif
+ | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+#if defined (CONFIG_DDR_32BIT)
+ /* for 32-bit mode burst length is 8 */
+ im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+#endif
+ udelay(200);
+
+ /* enable DDR controller */
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+ return msize;
+}
+#endif/*!CONFIG_SYS_SPD_EEPROM*/
+
+
+int checkboard (void)
+{
+ /*
+ * Warning: do not read the BCSR registers here
+ *
+ * There is a timing bug in the 8349E and 8349EA BCSR code
+ * version 1.2 (read from BCSR 11) that will cause the CFI
+ * flash initialization code to overwrite BCSR 0, disabling
+ * the serial ports and gigabit ethernet
+ */
+
+ puts("Board: Freescale MPC8349EMDS\n");
+ return 0;
+}
+
+/*
+ * if MPC8349EMDS is soldered with SDRAM
+ */
+#if defined(CONFIG_SYS_BR2_PRELIM) \
+ && defined(CONFIG_SYS_OR2_PRELIM) \
+ && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
+ && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void sdram_init(void)
+{
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile fsl_lbc_t *lbc = &immap->im_lbc;
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+
+ /*
+ * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+ */
+
+ /* setup mtrpt, lsrt and lbcr for LB bus */
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ asm("sync");
+
+ /*
+ * Configure the SDRAM controller Machine Mode Register.
+ */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+ asm("sync");
+ /*1 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*2 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*3 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*4 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*5 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*6 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*7 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*8 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ /* 0x58636733; mode register write operation */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+}
+#else
+void sdram_init(void)
+{
+}
+#endif
+
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+
+#define SPI_CS_MASK 0x80000000
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+
+ iopd->dat &= ~SPI_CS_MASK;
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+
+ iopd->dat |= SPI_CS_MASK;
+}
+#endif /* CONFIG_HARD_SPI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
new file mode 100644
index 0000000..9f7324f
--- /dev/null
+++ b/board/freescale/mpc8349emds/pci.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
+
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+ size: CONFIG_SYS_PCI2_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_IO_BASE,
+ phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+ size: CONFIG_SYS_PCI2_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+ size: CONFIG_SYS_PCI2_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
+#endif
+
+#ifndef CONFIG_PCISLAVE
+void pib_init(void)
+{
+ u8 val8, orig_i2c_bus;
+ /*
+ * Assign PIB PMC slot to desired PCI bus
+ */
+ /* Switch temporarily to I2C bus #2 */
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ val8 = 0;
+ i2c_write(0x23, 0x6, 1, &val8, 1);
+ i2c_write(0x23, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x23, 0x2, 1, &val8, 1);
+ i2c_write(0x23, 0x3, 1, &val8, 1);
+
+ val8 = 0;
+ i2c_write(0x26, 0x6, 1, &val8, 1);
+ val8 = 0x34;
+ i2c_write(0x26, 0x7, 1, &val8, 1);
+#if defined(PCI_64BIT)
+ val8 = 0xf4; /* PMC2:PCI1/64-bit */
+#elif defined(PCI_ALL_PCI1)
+ val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
+#elif defined(PCI_ONE_PCI1)
+ val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
+#else
+ val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
+#endif
+ i2c_write(0x26, 0x2, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x26, 0x3, 1, &val8, 1);
+ val8 = 0;
+ i2c_write(0x27, 0x6, 1, &val8, 1);
+ i2c_write(0x27, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x27, 0x2, 1, &val8, 1);
+ val8 = 0xef;
+ i2c_write(0x27, 0x3, 1, &val8, 1);
+ asm("eieio");
+
+#if defined(PCI_64BIT)
+ printf("PCI1: 64-bit on PMC2\n");
+#elif defined(PCI_ALL_PCI1)
+ printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
+#elif defined(PCI_ONE_PCI1)
+ printf("PCI1: 32-bit on PMC1\n");
+ printf("PCI2: 32-bit on PMC2, PMC3\n");
+#else
+ printf("PCI1: 32-bit on PMC1, PMC2\n");
+ printf("PCI2: 32-bit on PMC3\n");
+#endif
+ /* Reset to original I2C bus */
+ i2c_set_bus_num(orig_i2c_bus);
+}
+
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+ struct pci_region *reg[] = { pci1_regions };
+#else
+ struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
+
+ /* initialize the PCA9555PW IO expander on the PIB board */
+ pib_init();
+
+ /* Enable all 8 PCI_CLK_OUTPUTS */
+ clk->occr = 0xff000000;
+ udelay(2000);
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+ udelay(2000);
+
+#ifndef CONFIG_MPC83XX_PCI2
+ mpc83xx_pci_init(1, reg);
+#else
+ mpc83xx_pci_init(2, reg);
+#endif
+}
+
+#else
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
+ struct pci_region *reg[] = { pci1_regions };
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+ mpc83xx_pci_init(1, reg);
+
+ /* Configure PCI Inbound Translation Windows (3 1MB windows) */
+ pci_ctrl->pitar0 = 0x0;
+ pci_ctrl->pibar0 = 0x0;
+ pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+ PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
+
+ pci_ctrl->pitar1 = 0x0;
+ pci_ctrl->pibar1 = 0x0;
+ pci_ctrl->piebar1 = 0x0;
+ pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+ PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
+
+ pci_ctrl->pitar2 = 0x0;
+ pci_ctrl->pibar2 = 0x0;
+ pci_ctrl->piebar2 = 0x0;
+ pci_ctrl->piwar2 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+ PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
+
+ /* Unlock the configuration bit */
+ mpc83xx_pcislave_unlock(0);
+ printf("PCI: Agent mode enabled\n");
+}
+#endif /* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc8349itx/Kconfig b/board/freescale/mpc8349itx/Kconfig
new file mode 100644
index 0000000..ce3fffd
--- /dev/null
+++ b/board/freescale/mpc8349itx/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8349ITX
+
+config SYS_BOARD
+ default "mpc8349itx"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8349ITX"
+
+endif
diff --git a/board/freescale/mpc8349itx/MAINTAINERS b/board/freescale/mpc8349itx/MAINTAINERS
new file mode 100644
index 0000000..d0388ad
--- /dev/null
+++ b/board/freescale/mpc8349itx/MAINTAINERS
@@ -0,0 +1,8 @@
+MPC8349ITX BOARD
+#M: -
+S: Maintained
+F: board/freescale/mpc8349itx/
+F: include/configs/MPC8349ITX.h
+F: configs/MPC8349ITX_defconfig
+F: configs/MPC8349ITX_LOWBOOT_defconfig
+F: configs/MPC8349ITXGP_defconfig
diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile
new file mode 100644
index 0000000..e9092ad
--- /dev/null
+++ b/board/freescale/mpc8349itx/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) Freescale Semiconductor, Inc. 2006.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8349itx.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc8349itx/README b/board/freescale/mpc8349itx/README
new file mode 100644
index 0000000..48bbd50
--- /dev/null
+++ b/board/freescale/mpc8349itx/README
@@ -0,0 +1,187 @@
+Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
+---------------------------------------------------
+
+1. Board Description
+
+ The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring
+ the Freescale MPC8349E processor in a Mini-ITX form factor.
+
+ The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences:
+
+ A) One 8MB on-board flash EEPROM chip, instead of two.
+ B) No SATA controller
+ C) No Compact Flash slot
+ D) No Mini-PCI slot
+ E) No Vitesse 7385 5-port Ethernet switch
+ F) No 4-port USB Type-A interface
+
+2. Board Switches and Jumpers
+
+2.0 Descriptions for all of the board jumpers can be found in the User
+ Guide. Of particular interest to U-Boot developers is jumper J22:
+
+ Pos. Name Default Description
+ -----------------------------------------------------------------------
+ A LGPL0 ON (0) HRCW source, bit 0
+ B LGPL1 ON (0) HRCW source, bit 1
+ C LGPL3 ON (0) HRCW source, bit 2
+ D LGPL5 OFF (1) PCI_SYNC_OUT frequency
+ E BOOT1 ON (0) Flash EEPROM boot device
+ F PCI_M66EN ON (0) PCI 66MHz enable
+ G I2C-WP ON (0) I2C EEPROM write protection
+ H F_WP OFF (1) Flash EEPROM write protection
+
+ Jumper J22.E is only for the ITX, and it decides the configuration
+ of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip
+ U4 is located at address FE000000 and flash chip U7 is at FE800000.
+ If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000.
+
+ For U-Boot development, J22.E can be used to switch back-and-forth
+ between two U-Boot images.
+
+3. Memory Map
+
+3.1. The memory map should look pretty much like this:
+
+ 0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB)
+ 0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB)
+ 0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB)
+ 0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB)
+ 0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB)
+ 0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB)
+ 0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only)
+ 0xF001_0000 - 0xF001_FFFF Local bus expansion slot
+ 0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only)
+ 0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory
+ 0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only)
+
+3.2 Flash EEPROM layout.
+
+ On the ITX, jumper J22.E is used to determine which flash chips are
+ at which address. When J22.E is switched, addresses from FE000000
+ to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF.
+
+ On the ITX, at the normal boot address (aka HIGHBOOT):
+
+ FE00_0000 HRCW
+ FE70_0000 Alternative U-Boot image
+ FE80_0000 Alternative HRCW
+ FEF0_0000 U-Boot image
+ FEFF_FFFF End of flash
+
+ On the ITX, at the low boot address (LOWBOOT)
+
+ FE00_0000 HRCW and U-Boot image
+ FE04_0000 U-Boot environment variables
+ FE80_0000 Alternative HRCW and U-Boot image
+ FEFF_FFFF End of flash
+
+ On the ITX-GP, the only option is LOWBOOT and there is only one chip
+
+ FE00_0000 HRCW and U-Boot image
+ FE04_0000 U-Boot environment variables
+ F7FF_FFFF End of flash
+
+4. Definitions
+
+4.1 Explanation of NEW definitions in:
+
+ include/configs/MPC8349ITX.h
+
+ CONFIG_MPC83xx MPC83xx family
+ CONFIG_MPC8349 MPC8349 specific
+ CONFIG_MPC8349ITX MPC8349E-mITX
+ CONFIG_MPC8349ITXGP MPC8349E-mITX-GP
+
+5. Compilation
+
+ Assuming you're using BASH shell:
+
+ export CROSS_COMPILE=your-cross-compile-prefix
+ cd u-boot
+ make distclean
+
+ make MPC8349ITX_config
+ or:
+ make MPC8349ITXGP_config
+ or:
+ make MPC8349ITX_LOWBOOT_config
+
+ make
+
+6. Downloading and Flashing Images
+
+6.1 Download via tftp:
+
+ tftp $loadaddr <uboot>
+
+ where "<uboot>" is the path and filename, on the TFTP server, of
+ the U-Boot image.
+
+6.1 Reflash U-Boot Image using U-Boot
+
+ setenv uboot <uboot>
+ run tftpflash
+
+ where "<uboot>" is the path and filename, on the TFTP server, of
+ the U-Boot image.
+
+6.2 Using the HRCW to switch between two different U-Boot images on the ITX
+
+ Because the ITX has 16MB of flash, it is possible to keep two U-Boot
+ images in flash, and use the HRCW to specify which one is to be used
+ when the board boots. This trick is especially effective with a
+ hardware debugger that can override the HRCW, such as the BDI-2000.
+
+ When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image
+ at address FE000000. When the BMS bit is 1, the ITX will boot the
+ image at address FEF00000.
+
+ Therefore, just put a U-Boot image at both FE000000 and FEF00000 and
+ change the BMS bit whenever you want to boot the other image.
+
+ Step-by-step instructions:
+
+ 1) Build an ITX image to be loaded at FEF00000
+
+ make distclean
+ make MPC8349ITX_config
+ make
+
+ 2) Take the u-boot.bin image and flash it at FEF00000.
+
+ tftp $loadaddr u-boot.bin
+ protect off all
+ erase FEF00000 +$filesize
+ cp.b $loadaddr FEF00000 $filesize
+
+ 3) Build an ITX image to be loaded at FE000000
+
+ make distclean
+ make MPC8349ITX_LOWBOOT_config
+ make
+
+ 4) Take the u-boot.bin image and flash it at FE000000.
+
+ tftp $loadaddr u-boot.bin
+ protect off FE000000 +$filesize
+ erase FE000000 +$filesize
+ cp.b $loadaddr FE000000 $filesize
+
+ The HRCW in flash is currently set to boot the image at FE000000.
+
+ If you have a hardware debugger, configure it to set the HRCW to
+ B460A000 04040000 if you want to boot the image at FEF00000, or set
+ it to B060A000 04040000 if you want to boot the image at FE000000.
+
+ To change the HRCW in flash to boot the image at FEF00000, use these
+ U-Boot commands:
+
+ cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000
+ mw.b 1020 b4 8 ; modify BMS bit
+ protect off FE000000 +10000
+ erase FE000000 +10000
+ cp.b 1000 FE000000 10000
+
+7. Notes
+ 1) The console baudrate for MPC8349EITX is 115200bps.
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
new file mode 100644
index 0000000..22a1d99
--- /dev/null
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -0,0 +1,390 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <vsc7385.h>
+#ifdef CONFIG_PCI
+#include <asm/mpc8349_pci.h>
+#include <pci.h>
+#endif
+#include <spd_sdram.h>
+#include <asm/mmu.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+#ifndef CONFIG_SPD_EEPROM
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ /* The size of RAM, in bytes */
+ u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
+ u32 ddr_size_log2 = __ilog2(ddr_size);
+
+ im->sysconf.ddrlaw[0].ar =
+ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[0].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+
+ /* Only one CS for DDR */
+ im->ddr.cs_config[1] = 0;
+ im->ddr.cs_config[2] = 0;
+ im->ddr.cs_config[3] = 0;
+
+ debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
+ debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
+
+ debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
+ debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
+
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
+ im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
+ im->ddr.sdram_mode =
+ (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
+ im->ddr.sdram_interval =
+ (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
+ SDRAM_INTERVAL_BSTOPRE_SHIFT);
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+
+ udelay(200);
+
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+ debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
+ debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
+ debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
+ debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
+ debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
+
+ return CONFIG_SYS_DDR_SIZE;
+}
+#endif
+
+#ifdef CONFIG_PCI
+/*
+ * Initialize PCI Devices, report devices found
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
+ {
+ PCI_ANY_ID,
+ PCI_ANY_ID,
+ PCI_ANY_ID,
+ PCI_ANY_ID,
+ 0x0f,
+ PCI_ANY_ID,
+ pci_cfgfunc_config_device,
+ {
+ PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
+ },
+ {}
+}
+#endif
+
+volatile static struct pci_controller hose[] = {
+ {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc83xxmitx_config_table,
+#endif
+ },
+ {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc83xxmitx_config_table,
+#endif
+ }
+};
+#endif /* CONFIG_PCI */
+
+phys_size_t initdram(int board_type)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = 0;
+#ifdef CONFIG_DDR_ECC
+ volatile ddr83xx_t *ddr = &im->ddr;
+#endif
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+#ifdef CONFIG_SPD_EEPROM
+ msize = spd_sdram();
+#else
+ msize = fixed_sdram();
+#endif
+
+#ifdef CONFIG_DDR_ECC
+ if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
+ /* Unlike every other board, on the 83xx spd_sdram() returns
+ megabytes instead of just bytes. That's why we need to
+ multiple by 1MB when calling ddr_enable_ecc(). */
+ ddr_enable_ecc(msize * 1048576);
+#endif
+
+ /* return total bus RAM size(bytes) */
+ return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_MPC8349ITX
+ puts("Board: Freescale MPC8349E-mITX\n");
+#else
+ puts("Board: Freescale MPC8349E-mITX-GP\n");
+#endif
+
+ return 0;
+}
+
+/*
+ * Implement a work-around for a hardware problem with compact
+ * flash.
+ *
+ * Program the UPM if compact flash is enabled.
+ */
+int misc_init_f(void)
+{
+#ifdef CONFIG_VSC7385_ENET
+ volatile u32 *vsc7385_cpuctrl;
+
+ /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
+ default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
+ means it is 0 when the IRQ is not active. This makes the wire-AND
+ logic always assert IRQ7 to CPU even if there is no request from the
+ switch. Since the compact flash and the switch share the same IRQ,
+ the Linux kernel will think that the compact flash is requesting irq
+ and get stuck when it tries to clear the IRQ. Thus we need to set
+ the L2_IRQ0 and L2_IRQ1 to active low.
+
+ The following code sets the L1_IRQ and L2_IRQ polarity to active low.
+ Without this code, compact flash will not work in Linux because
+ unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
+ don't enable compact flash for U-Boot.
+ */
+
+ vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
+ *vsc7385_cpuctrl |= 0x0c;
+#endif
+
+#ifdef CONFIG_COMPACT_FLASH
+ /* UPM Table Configuration Code */
+ static uint UPMATable[] = {
+ 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
+ 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+ 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
+ 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
+ };
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+ set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+ set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
+
+ /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
+ GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
+ */
+ immap->im_lbc.mamr = 0x08404440;
+
+ upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
+
+ puts("UPMA: Configured for compact flash\n");
+#endif
+
+ return 0;
+}
+
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * Make sure the EEPROM has the HRCW correctly programmed.
+ * Make sure the RTC is correctly programmed.
+ *
+ * The MPC8349E-mITX can be configured to load the HRCW from
+ * EEPROM instead of flash. This is controlled via jumpers
+ * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
+ * jumpered), but if they're set to 001 or 010, then the HRCW is
+ * read from the "I2C EEPROM".
+ *
+ * This function makes sure that the I2C EEPROM is programmed
+ * correctly.
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+ */
+int misc_init_r(void)
+{
+ int rc = 0;
+
+#if defined(CONFIG_SYS_I2C)
+ unsigned int orig_bus = i2c_get_bus_num();
+ u8 i2c_data;
+
+#ifdef CONFIG_SYS_I2C_RTC_ADDR
+ u8 ds1339_data[17];
+#endif
+
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
+ static u8 eeprom_data[] = /* HRCW data */
+ {
+ 0xAA, 0x55, 0xAA, /* Preamble */
+ 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
+ 0x02, 0x40, /* RCWL ADDR=0x0_0900 */
+ (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
+ (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
+ (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
+ CONFIG_SYS_HRCW_LOW & 0xFF,
+ 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
+ 0x02, 0x41, /* RCWH ADDR=0x0_0904 */
+ (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
+ (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
+ (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
+ CONFIG_SYS_HRCW_HIGH & 0xFF
+ };
+
+ u8 data[sizeof(eeprom_data)];
+#endif
+
+ printf("Board revision: ");
+ i2c_set_bus_num(1);
+ if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+ printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
+ else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+ printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
+ else {
+ printf("Unknown\n");
+ rc = 1;
+ }
+
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
+ i2c_set_bus_num(0);
+
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
+ if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
+ if (i2c_write
+ (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
+ sizeof(eeprom_data)) != 0) {
+ puts("Failure writing the HRCW to EEPROM via I2C.\n");
+ rc = 1;
+ }
+ }
+ } else {
+ puts("Failure reading the HRCW from EEPROM via I2C.\n");
+ rc = 1;
+ }
+#endif
+
+#ifdef CONFIG_SYS_I2C_RTC_ADDR
+ i2c_set_bus_num(1);
+
+ if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
+ == 0) {
+
+ /* Work-around for MPC8349E-mITX bug #13601.
+ If the RTC does not contain valid register values, the DS1339
+ Linux driver will not work.
+ */
+
+ /* Make sure status register bits 6-2 are zero */
+ ds1339_data[0x0f] &= ~0x7c;
+
+ /* Check for a valid day register value */
+ ds1339_data[0x03] &= ~0xf8;
+ if (ds1339_data[0x03] == 0) {
+ ds1339_data[0x03] = 1;
+ }
+
+ /* Check for a valid date register value */
+ ds1339_data[0x04] &= ~0xc0;
+ if ((ds1339_data[0x04] == 0) ||
+ ((ds1339_data[0x04] & 0x0f) > 9) ||
+ (ds1339_data[0x04] >= 0x32)) {
+ ds1339_data[0x04] = 1;
+ }
+
+ /* Check for a valid month register value */
+ ds1339_data[0x05] &= ~0x60;
+
+ if ((ds1339_data[0x05] == 0) ||
+ ((ds1339_data[0x05] & 0x0f) > 9) ||
+ ((ds1339_data[0x05] >= 0x13)
+ && (ds1339_data[0x05] <= 0x19))) {
+ ds1339_data[0x05] = 1;
+ }
+
+ /* Enable Oscillator and rate select */
+ ds1339_data[0x0e] = 0x1c;
+
+ /* Work-around for MPC8349E-mITX bug #13330.
+ Ensure that the RTC control register contains the value 0x1c.
+ This affects SATA performance.
+ */
+
+ if (i2c_write
+ (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
+ sizeof(ds1339_data))) {
+ puts("Failure writing to the RTC via I2C.\n");
+ rc = 1;
+ }
+ } else {
+ puts("Failure reading from the RTC via I2C.\n");
+ rc = 1;
+ }
+#endif
+
+ i2c_set_bus_num(orig_bus);
+#endif
+
+#ifdef CONFIG_VSC7385_IMAGE
+ if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+ CONFIG_VSC7385_IMAGE_SIZE)) {
+ puts("Failure uploading VSC7385 microcode.\n");
+ rc = 1;
+ }
+#endif
+
+ return rc;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c
new file mode 100644
index 0000000..afc9df0
--- /dev/null
+++ b/board/freescale/mpc8349itx/pci.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
+
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+ size: CONFIG_SYS_PCI2_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_IO_BASE,
+ phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+ size: CONFIG_SYS_PCI2_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+ size: CONFIG_SYS_PCI2_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
+#endif
+
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+ struct pci_region *reg[] = { pci1_regions };
+#else
+ struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
+ u8 reg8;
+
+#if defined(CONFIG_SYS_I2C)
+ i2c_set_bus_num(1);
+ /* Read the PCI_M66EN jumper setting */
+ if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
+ (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) {
+ if (reg8 & I2C_8574_PCI66)
+ clk->occr = 0xff000000; /* 66 MHz PCI */
+ else
+ clk->occr = 0xff600001; /* 33 MHz PCI */
+ } else {
+ clk->occr = 0xff600001; /* 33 MHz PCI */
+ }
+#else
+ clk->occr = 0xff000000; /* 66 MHz PCI */
+#endif
+ udelay(2000);
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
+
+ udelay(2000);
+
+#ifndef CONFIG_MPC83XX_PCI2
+ mpc83xx_pci_init(1, reg);
+#else
+ mpc83xx_pci_init(2, reg);
+#endif
+}
diff --git a/board/freescale/mpc8360emds/Kconfig b/board/freescale/mpc8360emds/Kconfig
new file mode 100644
index 0000000..3f4f95c
--- /dev/null
+++ b/board/freescale/mpc8360emds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8360EMDS
+
+config SYS_BOARD
+ default "mpc8360emds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8360EMDS"
+
+endif
diff --git a/board/freescale/mpc8360emds/MAINTAINERS b/board/freescale/mpc8360emds/MAINTAINERS
new file mode 100644
index 0000000..91ff2ef
--- /dev/null
+++ b/board/freescale/mpc8360emds/MAINTAINERS
@@ -0,0 +1,15 @@
+MPC8360EMDS BOARD
+M: Dave Liu <daveliu@freescale.com>
+S: Maintained
+F: board/freescale/mpc8360emds/
+F: include/configs/MPC8360EMDS.h
+F: configs/MPC8360EMDS_33_defconfig
+F: configs/MPC8360EMDS_33_ATM_defconfig
+F: configs/MPC8360EMDS_33_HOST_33_defconfig
+F: configs/MPC8360EMDS_33_HOST_66_defconfig
+F: configs/MPC8360EMDS_33_SLAVE_defconfig
+F: configs/MPC8360EMDS_66_defconfig
+F: configs/MPC8360EMDS_66_ATM_defconfig
+F: configs/MPC8360EMDS_66_HOST_33_defconfig
+F: configs/MPC8360EMDS_66_HOST_66_defconfig
+F: configs/MPC8360EMDS_66_SLAVE_defconfig
diff --git a/board/freescale/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile
new file mode 100644
index 0000000..e8332ce
--- /dev/null
+++ b/board/freescale/mpc8360emds/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8360emds.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc8360emds/README b/board/freescale/mpc8360emds/README
new file mode 100644
index 0000000..6afa753
--- /dev/null
+++ b/board/freescale/mpc8360emds/README
@@ -0,0 +1,155 @@
+Freescale MPC8360EMDS Board
+-----------------------------------------
+1. Board Switches and Jumpers
+1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
+ For some reason, the HW designers describe the switch settings
+ in terms of 0 and 1, and then map that to physical switches where
+ the label "On" refers to logic 0 and "Off" is logic 1.
+
+ Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
+ bits may contribute to signals that are numbered based at 0,
+ and some of those signals may be high-bit-number-0 too. Heed
+ well the names and labels and do not get confused.
+
+ "Off" == 1
+ "On" == 0
+
+ SW18 is switch 18 as silk-screened onto the board.
+ SW4[8] is the bit labeled 8 on Switch 4.
+ SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
+ SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
+ SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
+ and bits labeled 8 is set as "Off".
+
+1.1 There are three type boards for MPC8360E silicon up to now, They are
+
+ * MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE)
+ * MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT)
+ * MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE)
+
+1.2 For all the MPC8360EMDS Board
+
+ First, make sure the board default setting is consistent with the
+ document shipped with your board. Then apply the following setting:
+ SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus)
+ SW4[1-8]= 0011_0000 (Flash boot on local bus)
+ SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH)
+ SW10[1-8]= 0000_1000 (core PLL setting)
+ SW11[1-8]= 0000_0100 (SW11 is on the another side of the board)
+ JP6 1-2
+ on board Oscillator: 66M
+
+1.3 Since different board/chip rev. combinations have AC timing issues,
+ u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default
+ by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers).
+
+ When the rev2.x silicon mount on these boards, and if you are using
+ u-boot version after this patch, to make the ethernet interfaces usable,
+ and to enable RGMII-ID on your board, you have to setup the jumpers
+ correctly.
+
+ * MPC8360E-MDS-PB PROTO
+ nothing to do
+ * MPC8360E-MDS-PB PILOT
+ JP9 and JP8 should be ON
+ * MPC8360EA-MDS-PB PROTO
+ JP2 and JP3 should be ON
+
+2. Memory Map
+
+2.1. The memory map should look pretty much like this:
+
+ 0x0000_0000 0x7fff_ffff DDR 2G
+ 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
+ 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
+ 0xc000_0000 0xdfff_ffff Empty 512M
+ 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
+ 0xe020_0000 0xe02f_ffff Empty 1M
+ 0xe030_0000 0xe03f_ffff PCI IO 1M
+ 0xe040_0000 0xefff_ffff Empty 252M
+ 0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M
+ 0xf400_0000 0xf7ff_ffff Empty 64M
+ 0xf800_0000 0xf800_7fff BCSR on CS1 32K
+ 0xf800_8000 0xf800_ffff PIB CS4 32K
+ 0xf801_0000 0xf801_7fff PIB CS5 32K
+ 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
+
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+ include/configs/MPC8360EMDS.h
+
+ CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
+ CONFIG_MPC8360 MPC8360 specific
+ CONFIG_MPC8360EMDS MPC8360EMDS board specific
+
+4. Compilation
+
+ MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip).
+
+ Assuming you're using BASH shell:
+
+ export CROSS_COMPILE=your-cross-compile-prefix
+ cd u-boot
+ make distclean
+ make MPC8360EMDS_XX_config
+ make
+
+ MPC8360EMDS support ATM, PCI in host and slave mode.
+
+ To make u-boot support ATM :
+ 1) Make MPC8360EMDS_XX_ATM_config
+
+ To make u-boot support PCI host 66M :
+ 1) DIP SW support PCI mode as described in Section 1.1.
+ 2) Make MPC8360EMDS_XX_HOST_66_config
+
+ To make u-boot support PCI host 33M :
+ 1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1
+ 2) Make MPC8360EMDS_XX_HOST_33_config
+
+ To make u-boot support PCI slave 66M :
+ 1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1
+ 2) Make MPC8360EMDS_XX_SLAVE_config
+
+ (where XX is:
+ 33 - 33.33MHz oscillator
+ 66 - 66MHz oscillator)
+
+5. Downloading and Flashing Images
+
+5.0 Download over serial line using Kermit:
+
+ loadb
+ [Drop to kermit:
+ ^\c
+ send <u-boot-bin-image>
+ c
+ ]
+
+
+ Or via tftp:
+
+ tftp 10000 u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+ tftp 20000 u-boot.bin
+ protect off fef00000 fef3ffff
+ erase fef00000 fef3ffff
+
+ cp.b 20000 fef00000 xxxx
+
+ or
+
+ cp.b 20000 fef00000 3ffff
+
+
+You have to supply the correct byte count with 'xxxx' from the TFTP result log.
+Maybe 3ffff will work too, that corresponds to the erased sectors.
+
+
+6. Notes
+ 1) The console baudrate for MPC8360EMDS is 115200bps.
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
new file mode 100644
index 0000000..f0a55f8
--- /dev/null
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -0,0 +1,453 @@
+/*
+ * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fsl_mdio.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#include <spd_sdram.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#include <hwconfig.h>
+#include <fdt_support.h>
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
+#endif
+#include "../../../drivers/qe/uec.h"
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* GETH1 */
+ {0, 3, 1, 0, 1}, /* TxD0 */
+ {0, 4, 1, 0, 1}, /* TxD1 */
+ {0, 5, 1, 0, 1}, /* TxD2 */
+ {0, 6, 1, 0, 1}, /* TxD3 */
+ {1, 6, 1, 0, 3}, /* TxD4 */
+ {1, 7, 1, 0, 1}, /* TxD5 */
+ {1, 9, 1, 0, 2}, /* TxD6 */
+ {1, 10, 1, 0, 2}, /* TxD7 */
+ {0, 9, 2, 0, 1}, /* RxD0 */
+ {0, 10, 2, 0, 1}, /* RxD1 */
+ {0, 11, 2, 0, 1}, /* RxD2 */
+ {0, 12, 2, 0, 1}, /* RxD3 */
+ {0, 13, 2, 0, 1}, /* RxD4 */
+ {1, 1, 2, 0, 2}, /* RxD5 */
+ {1, 0, 2, 0, 2}, /* RxD6 */
+ {1, 4, 2, 0, 2}, /* RxD7 */
+ {0, 7, 1, 0, 1}, /* TX_EN */
+ {0, 8, 1, 0, 1}, /* TX_ER */
+ {0, 15, 2, 0, 1}, /* RX_DV */
+ {0, 16, 2, 0, 1}, /* RX_ER */
+ {0, 0, 2, 0, 1}, /* RX_CLK */
+ {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
+ {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
+ /* GETH2 */
+ {0, 17, 1, 0, 1}, /* TxD0 */
+ {0, 18, 1, 0, 1}, /* TxD1 */
+ {0, 19, 1, 0, 1}, /* TxD2 */
+ {0, 20, 1, 0, 1}, /* TxD3 */
+ {1, 2, 1, 0, 1}, /* TxD4 */
+ {1, 3, 1, 0, 2}, /* TxD5 */
+ {1, 5, 1, 0, 3}, /* TxD6 */
+ {1, 8, 1, 0, 3}, /* TxD7 */
+ {0, 23, 2, 0, 1}, /* RxD0 */
+ {0, 24, 2, 0, 1}, /* RxD1 */
+ {0, 25, 2, 0, 1}, /* RxD2 */
+ {0, 26, 2, 0, 1}, /* RxD3 */
+ {0, 27, 2, 0, 1}, /* RxD4 */
+ {1, 12, 2, 0, 2}, /* RxD5 */
+ {1, 13, 2, 0, 3}, /* RxD6 */
+ {1, 11, 2, 0, 2}, /* RxD7 */
+ {0, 21, 1, 0, 1}, /* TX_EN */
+ {0, 22, 1, 0, 1}, /* TX_ER */
+ {0, 29, 2, 0, 1}, /* RX_DV */
+ {0, 30, 2, 0, 1}, /* RX_ER */
+ {0, 31, 2, 0, 1}, /* RX_CLK */
+ {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
+ {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
+
+ {0, 1, 3, 0, 2}, /* MDIO */
+ {0, 2, 1, 0, 1}, /* MDC */
+
+ {5, 0, 1, 0, 2}, /* UART2_SOUT */
+ {5, 1, 2, 0, 3}, /* UART2_CTS */
+ {5, 2, 1, 0, 1}, /* UART2_RTS */
+ {5, 3, 2, 0, 2}, /* UART2_SIN */
+
+ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
+static int board_handle_erratum2(void)
+{
+ const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
+ REVID_MINOR(immr->sysconf.spridr) == 1;
+}
+
+int board_early_init_f(void)
+{
+ const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
+
+ /* Enable flash write */
+ bcsr[0xa] &= ~0x04;
+
+ /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
+ if (REVID_MAJOR(immr->sysconf.spridr) == 2)
+ bcsr[0xe] = 0x30;
+
+ /* Enable second UART */
+ bcsr[0x9] &= ~0x01;
+
+ if (board_handle_erratum2()) {
+ void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);
+
+ /*
+ * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
+ * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
+ */
+ setbits_be32(immap, 0x0c003000);
+
+ /*
+ * IMMR + 0x14AC[20:27] = 10101010
+ * (data delay for both UCC's)
+ */
+ clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
+ }
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ gd_t *gd;
+#ifdef CONFIG_PQ_MDS_PIB
+ pib_init();
+#endif
+ /*
+ * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
+ * So re-setup PCI MEM space used BAT5 after relocated to DDR
+ */
+ gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+ if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
+ write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
+ write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_UEC_ETH
+static uec_info_t uec_info[] = {
+#ifdef CONFIG_UEC_ETH1
+ STD_UEC_INFO(1),
+#endif
+#ifdef CONFIG_UEC_ETH2
+ STD_UEC_INFO(2),
+#endif
+};
+
+int board_eth_init(bd_t *bd)
+{
+ if (board_handle_erratum2()) {
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(uec_info); i++) {
+ uec_info[i].enet_interface_type =
+ PHY_INTERFACE_MODE_RGMII_RXID;
+ uec_info[i].speed = SPEED_1000;
+ }
+ }
+ return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
+}
+#endif /* CONFIG_UEC_ETH */
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+int fixed_sdram(void);
+static int sdram_init(unsigned int base);
+
+phys_size_t initdram(int board_type)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = 0;
+ u32 lbc_sdram_size;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+ msize = spd_sdram();
+#else
+ msize = fixed_sdram();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize DDR ECC byte
+ */
+ ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+ /*
+ * Initialize SDRAM if it is on local bus.
+ */
+ lbc_sdram_size = sdram_init(msize * 1024 * 1024);
+ if (!msize)
+ msize = lbc_sdram_size;
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE;
+ u32 ddr_size = msize << 20;
+ u32 ddr_size_log2 = __ilog2(ddr_size);
+ u32 half_ddr_size = ddr_size >> 1;
+
+ im->sysconf.ddrlaw[0].bar =
+ CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].ar =
+ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+#if (CONFIG_SYS_DDR_SIZE != 256)
+#warning Currenly any ddr size other than 256 is not supported
+#endif
+#ifdef CONFIG_DDR_II
+ im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+#else
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[0].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+ im->ddr.csbnds[1].csbnds =
+ (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
+ CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
+
+ im->ddr.cs_config[2] = 0;
+ im->ddr.cs_config[3] = 0;
+
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+#endif
+ udelay(200);
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+ return msize;
+}
+#endif /*!CONFIG_SYS_SPD_EEPROM */
+
+int checkboard(void)
+{
+ puts("Board: Freescale MPC8360EMDS\n");
+ return 0;
+}
+
+/*
+ * if MPC8360EMDS is soldered with SDRAM
+ */
+#ifdef CONFIG_SYS_LB_SDRAM
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+static int sdram_init(unsigned int base)
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
+ int rem = base % sdram_size;
+ uint *sdram_addr;
+
+ /* window base address should be aligned to the window size */
+ if (rem)
+ base = base - rem + sdram_size;
+
+ /*
+ * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
+ * After relocated to DDR, reuse BAT5 for PCI MEM space
+ */
+ if (base > CONFIG_MAX_MEM_MAPPED) {
+ unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE;
+ unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP;
+
+ /* Setup the BAT6 for SDRAM */
+ write_bat(DBAT6, batu, batl);
+ write_bat(IBAT6, batu, batl);
+ }
+
+ sdram_addr = (uint *)base;
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ set_lbc_br(2, base | CONFIG_SYS_BR2);
+ set_lbc_or(2, CONFIG_SYS_OR2);
+ immap->sysconf.lblaw[2].bar = base;
+ immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
+
+ /*setup mtrpt, lsrt and lbcr for LB bus */
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ asm("sync");
+
+ /*
+ * Configure the SDRAM controller Machine Mode Register.
+ */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ /*
+ * We need do 8 times auto refresh operation.
+ */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
+ asm("sync");
+ *sdram_addr = 0xff; /* 1 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 2 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 3 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 4 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 5 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 6 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 7 times */
+ udelay(100);
+ *sdram_addr = 0xff; /* 8 times */
+ udelay(100);
+
+ /* Mode register write operation */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+ asm("sync");
+ *(sdram_addr + 0xcc) = 0xff;
+ udelay(100);
+
+ /* Normal operation */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ /*
+ * In non-aligned case we don't [normally] use that memory because
+ * there is a hole.
+ */
+ if (rem)
+ return 0;
+ return CONFIG_SYS_LBC_SDRAM_SIZE;
+}
+#else
+static int sdram_init(unsigned int base) { return 0; }
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
+{
+ if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
+ return;
+
+ do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
+ "peripheral", sizeof("peripheral"), 1);
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+ ft_board_fixup_qe_usb(blob, bd);
+ /*
+ * mpc8360ea pb mds errata 2: RGMII timing
+ * if on mpc8360ea rev. 2.1,
+ * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
+ */
+ if (board_handle_erratum2()) {
+ int nodeoffset;
+ const char *prop;
+ int path;
+
+ nodeoffset = fdt_path_offset(blob, "/aliases");
+ if (nodeoffset >= 0) {
+#if defined(CONFIG_HAS_ETH0)
+ /* fixup UCC 1 if using rgmii-id mode */
+ prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
+ if (prop) {
+ path = fdt_path_offset(blob, prop);
+ prop = fdt_getprop(blob, path,
+ "phy-connection-type", 0);
+ if (prop && (strcmp(prop, "rgmii-id") == 0))
+ fdt_fixup_phy_connection(blob, path,
+ PHY_INTERFACE_MODE_RGMII_RXID);
+ }
+#endif
+#if defined(CONFIG_HAS_ETH1)
+ /* fixup UCC 2 if using rgmii-id mode */
+ prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
+ if (prop) {
+ path = fdt_path_offset(blob, prop);
+ prop = fdt_getprop(blob, path,
+ "phy-connection-type", 0);
+ if (prop && (strcmp(prop, "rgmii-id") == 0))
+ fdt_fixup_phy_connection(blob, path,
+ PHY_INTERFACE_MODE_RGMII_RXID);
+ }
+#endif
+ }
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c
new file mode 100644
index 0000000..71244df
--- /dev/null
+++ b/board/freescale/mpc8360emds/pci.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * PCI Configuration space access support for MPC83xx PCI Bridge
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+#include "../common/pq-mds-pib.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
+
+#ifdef CONFIG_MPC83XX_PCI2
+static struct pci_region pci2_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+ size: CONFIG_SYS_PCI2_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_IO_BASE,
+ phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+ size: CONFIG_SYS_PCI2_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+ size: CONFIG_SYS_PCI2_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
+#endif
+
+void pci_init_board(void)
+#ifdef CONFIG_PCISLAVE
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
+ struct pci_region *reg[] = { pci1_regions };
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
+
+ mpc83xx_pci_init(1, reg);
+
+ /*
+ * Configure PCI Inbound Translation Windows
+ */
+ pci_ctrl[0].pitar0 = 0x0;
+ pci_ctrl[0].pibar0 = 0x0;
+ pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
+ PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
+
+ pci_ctrl[0].pitar1 = 0x0;
+ pci_ctrl[0].pibar1 = 0x0;
+ pci_ctrl[0].piebar1 = 0x0;
+ pci_ctrl[0].piwar1 &= ~PIWAR_EN;
+
+ pci_ctrl[0].pitar2 = 0x0;
+ pci_ctrl[0].pibar2 = 0x0;
+ pci_ctrl[0].piebar2 = 0x0;
+ pci_ctrl[0].piwar2 &= ~PIWAR_EN;
+
+ /* Unlock the configuration bit */
+ mpc83xx_pcislave_unlock(0);
+ printf("PCI: Agent mode enabled\n");
+}
+#else
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+#ifndef CONFIG_MPC83XX_PCI2
+ struct pci_region *reg[] = { pci1_regions };
+#else
+ struct pci_region *reg[] = { pci1_regions, pci2_regions };
+#endif
+
+ /* initialize the PCA9555PW IO expander on the PIB board */
+ pib_init();
+
+#if defined(CONFIG_PCI_66M)
+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+ printf("PCI clock is 66MHz\n");
+#elif defined(CONFIG_PCI_33M)
+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
+ OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
+ printf("PCI clock is 33MHz\n");
+#else
+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+ printf("PCI clock is 66MHz\n");
+#endif
+ udelay(2000);
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
+
+ udelay(2000);
+
+#ifndef CONFIG_MPC83XX_PCI2
+ mpc83xx_pci_init(1, reg);
+#else
+ mpc83xx_pci_init(2, reg);
+#endif
+}
+#endif /* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc8360erdk/Kconfig b/board/freescale/mpc8360erdk/Kconfig
new file mode 100644
index 0000000..5c9be7c
--- /dev/null
+++ b/board/freescale/mpc8360erdk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8360ERDK
+
+config SYS_BOARD
+ default "mpc8360erdk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8360ERDK"
+
+endif
diff --git a/board/freescale/mpc8360erdk/MAINTAINERS b/board/freescale/mpc8360erdk/MAINTAINERS
new file mode 100644
index 0000000..e5b5995
--- /dev/null
+++ b/board/freescale/mpc8360erdk/MAINTAINERS
@@ -0,0 +1,7 @@
+MPC8360ERDK BOARD
+#M: Anton Vorontsov <avorontsov@ru.mvista.com>
+S: Orphan (since 2014-03)
+F: board/freescale/mpc8360erdk/
+F: include/configs/MPC8360ERDK.h
+F: configs/MPC8360ERDK_defconfig
+F: configs/MPC8360ERDK_33_defconfig
diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile
new file mode 100644
index 0000000..e2235c2
--- /dev/null
+++ b/board/freescale/mpc8360erdk/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8360erdk.o
+obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c
new file mode 100644
index 0000000..478f820
--- /dev/null
+++ b/board/freescale/mpc8360erdk/mpc8360erdk.c
@@ -0,0 +1,350 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <pci.h>
+#include <libfdt.h>
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* MDIO */
+ {0, 1, 3, 0, 2}, /* MDIO */
+ {0, 2, 1, 0, 1}, /* MDC */
+
+ /* UCC1 - UEC (Gigabit) */
+ {0, 3, 1, 0, 1}, /* TxD0 */
+ {0, 4, 1, 0, 1}, /* TxD1 */
+ {0, 5, 1, 0, 1}, /* TxD2 */
+ {0, 6, 1, 0, 1}, /* TxD3 */
+ {0, 9, 2, 0, 1}, /* RxD0 */
+ {0, 10, 2, 0, 1}, /* RxD1 */
+ {0, 11, 2, 0, 1}, /* RxD2 */
+ {0, 12, 2, 0, 1}, /* RxD3 */
+ {0, 7, 1, 0, 1}, /* TX_EN */
+ {0, 8, 1, 0, 1}, /* TX_ER */
+ {0, 15, 2, 0, 1}, /* RX_DV */
+ {0, 0, 2, 0, 1}, /* RX_CLK */
+ {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
+ {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
+
+ /* UCC2 - UEC (Gigabit) */
+ {0, 17, 1, 0, 1}, /* TxD0 */
+ {0, 18, 1, 0, 1}, /* TxD1 */
+ {0, 19, 1, 0, 1}, /* TxD2 */
+ {0, 20, 1, 0, 1}, /* TxD3 */
+ {0, 23, 2, 0, 1}, /* RxD0 */
+ {0, 24, 2, 0, 1}, /* RxD1 */
+ {0, 25, 2, 0, 1}, /* RxD2 */
+ {0, 26, 2, 0, 1}, /* RxD3 */
+ {0, 21, 1, 0, 1}, /* TX_EN */
+ {0, 22, 1, 0, 1}, /* TX_ER */
+ {0, 29, 2, 0, 1}, /* RX_DV */
+ {0, 31, 2, 0, 1}, /* RX_CLK */
+ {2, 2, 1, 0, 2}, /* GTX_CLK - CLK10 */
+ {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
+
+ /* UCC7 - UEC */
+ {4, 0, 1, 0, 1}, /* TxD0 */
+ {4, 1, 1, 0, 1}, /* TxD1 */
+ {4, 2, 1, 0, 1}, /* TxD2 */
+ {4, 3, 1, 0, 1}, /* TxD3 */
+ {4, 6, 2, 0, 1}, /* RxD0 */
+ {4, 7, 2, 0, 1}, /* RxD1 */
+ {4, 8, 2, 0, 1}, /* RxD2 */
+ {4, 9, 2, 0, 1}, /* RxD3 */
+ {4, 4, 1, 0, 1}, /* TX_EN */
+ {4, 5, 1, 0, 1}, /* TX_ER */
+ {4, 12, 2, 0, 1}, /* RX_DV */
+ {4, 13, 2, 0, 1}, /* RX_ER */
+ {4, 10, 2, 0, 1}, /* COL */
+ {4, 11, 2, 0, 1}, /* CRS */
+ {2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */
+ {2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */
+
+ /* UCC4 - UEC */
+ {1, 14, 1, 0, 1}, /* TxD0 */
+ {1, 15, 1, 0, 1}, /* TxD1 */
+ {1, 16, 1, 0, 1}, /* TxD2 */
+ {1, 17, 1, 0, 1}, /* TxD3 */
+ {1, 20, 2, 0, 1}, /* RxD0 */
+ {1, 21, 2, 0, 1}, /* RxD1 */
+ {1, 22, 2, 0, 1}, /* RxD2 */
+ {1, 23, 2, 0, 1}, /* RxD3 */
+ {1, 18, 1, 0, 1}, /* TX_EN */
+ {1, 19, 1, 0, 2}, /* TX_ER */
+ {1, 26, 2, 0, 1}, /* RX_DV */
+ {1, 27, 2, 0, 1}, /* RX_ER */
+ {1, 24, 2, 0, 1}, /* COL */
+ {1, 25, 2, 0, 1}, /* CRS */
+ {2, 6, 2, 0, 1}, /* TX_CLK - CLK7 */
+ {2, 7, 2, 0, 1}, /* RX_CLK - CLK8 */
+
+ /* PCI1 */
+ {5, 4, 2, 0, 3}, /* PCI_M66EN */
+ {5, 5, 1, 0, 3}, /* PCI_INTA */
+ {5, 6, 1, 0, 3}, /* PCI_RSTO */
+ {5, 7, 3, 0, 3}, /* PCI_C_BE0 */
+ {5, 8, 3, 0, 3}, /* PCI_C_BE1 */
+ {5, 9, 3, 0, 3}, /* PCI_C_BE2 */
+ {5, 10, 3, 0, 3}, /* PCI_C_BE3 */
+ {5, 11, 3, 0, 3}, /* PCI_PAR */
+ {5, 12, 3, 0, 3}, /* PCI_FRAME */
+ {5, 13, 3, 0, 3}, /* PCI_TRDY */
+ {5, 14, 3, 0, 3}, /* PCI_IRDY */
+ {5, 15, 3, 0, 3}, /* PCI_STOP */
+ {5, 16, 3, 0, 3}, /* PCI_DEVSEL */
+ {5, 17, 0, 0, 0}, /* PCI_IDSEL */
+ {5, 18, 3, 0, 3}, /* PCI_SERR */
+ {5, 19, 3, 0, 3}, /* PCI_PERR */
+ {5, 20, 3, 0, 3}, /* PCI_REQ0 */
+ {5, 21, 2, 0, 3}, /* PCI_REQ1 */
+ {5, 22, 2, 0, 3}, /* PCI_GNT2 */
+ {5, 23, 3, 0, 3}, /* PCI_GNT0 */
+ {5, 24, 1, 0, 3}, /* PCI_GNT1 */
+ {5, 25, 1, 0, 3}, /* PCI_GNT2 */
+ {5, 26, 0, 0, 0}, /* PCI_CLK0 */
+ {5, 27, 0, 0, 0}, /* PCI_CLK1 */
+ {5, 28, 0, 0, 0}, /* PCI_CLK2 */
+ {5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */
+ {6, 0, 3, 0, 3}, /* PCI_AD0 */
+ {6, 1, 3, 0, 3}, /* PCI_AD1 */
+ {6, 2, 3, 0, 3}, /* PCI_AD2 */
+ {6, 3, 3, 0, 3}, /* PCI_AD3 */
+ {6, 4, 3, 0, 3}, /* PCI_AD4 */
+ {6, 5, 3, 0, 3}, /* PCI_AD5 */
+ {6, 6, 3, 0, 3}, /* PCI_AD6 */
+ {6, 7, 3, 0, 3}, /* PCI_AD7 */
+ {6, 8, 3, 0, 3}, /* PCI_AD8 */
+ {6, 9, 3, 0, 3}, /* PCI_AD9 */
+ {6, 10, 3, 0, 3}, /* PCI_AD10 */
+ {6, 11, 3, 0, 3}, /* PCI_AD11 */
+ {6, 12, 3, 0, 3}, /* PCI_AD12 */
+ {6, 13, 3, 0, 3}, /* PCI_AD13 */
+ {6, 14, 3, 0, 3}, /* PCI_AD14 */
+ {6, 15, 3, 0, 3}, /* PCI_AD15 */
+ {6, 16, 3, 0, 3}, /* PCI_AD16 */
+ {6, 17, 3, 0, 3}, /* PCI_AD17 */
+ {6, 18, 3, 0, 3}, /* PCI_AD18 */
+ {6, 19, 3, 0, 3}, /* PCI_AD19 */
+ {6, 20, 3, 0, 3}, /* PCI_AD20 */
+ {6, 21, 3, 0, 3}, /* PCI_AD21 */
+ {6, 22, 3, 0, 3}, /* PCI_AD22 */
+ {6, 23, 3, 0, 3}, /* PCI_AD23 */
+ {6, 24, 3, 0, 3}, /* PCI_AD24 */
+ {6, 25, 3, 0, 3}, /* PCI_AD25 */
+ {6, 26, 3, 0, 3}, /* PCI_AD26 */
+ {6, 27, 3, 0, 3}, /* PCI_AD27 */
+ {6, 28, 3, 0, 3}, /* PCI_AD28 */
+ {6, 29, 3, 0, 3}, /* PCI_AD29 */
+ {6, 30, 3, 0, 3}, /* PCI_AD30 */
+ {6, 31, 3, 0, 3}, /* PCI_AD31 */
+
+ /* NAND */
+ {4, 18, 2, 0, 0}, /* NAND_RYnBY */
+
+ /* DUART - UART2 */
+ {5, 0, 1, 0, 2}, /* UART2_SOUT */
+ {5, 2, 1, 0, 1}, /* UART2_RTS */
+ {5, 3, 2, 0, 2}, /* UART2_SIN */
+ {5, 1, 2, 0, 3}, /* UART2_CTS */
+
+ /* UCC5 - UART3 */
+ {3, 0, 1, 0, 1}, /* UART3_TX */
+ {3, 4, 1, 0, 1}, /* UART3_RTS */
+ {3, 6, 2, 0, 1}, /* UART3_RX */
+ {3, 12, 2, 0, 0}, /* UART3_CTS */
+ {3, 13, 2, 0, 0}, /* UCC5_CD */
+
+ /* UCC6 - UART4 */
+ {3, 14, 1, 0, 1}, /* UART4_TX */
+ {3, 18, 1, 0, 1}, /* UART4_RTS */
+ {3, 20, 2, 0, 1}, /* UART4_RX */
+ {3, 26, 2, 0, 0}, /* UART4_CTS */
+ {3, 27, 2, 0, 0}, /* UCC6_CD */
+
+ /* Fujitsu MB86277 (MINT) graphics controller */
+ {0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */
+ {1, 5, 1, 0, 0}, /* nXRST_GRAPHICS */
+ {1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */
+ {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */
+
+ /* AD7843 ADC/Touchscreen controller */
+ {4, 14, 1, 0, 0}, /* SPI_nCS0 */
+ {4, 28, 3, 0, 3}, /* SPI_MOSI */
+ {4, 29, 3, 0, 3}, /* SPI_MISO */
+ {4, 30, 3, 0, 3}, /* SPI_CLK */
+
+ /* Freescale QUICC Engine USB Host Controller (FHCI) */
+ {1, 2, 1, 0, 3}, /* USBOE */
+ {1, 3, 1, 0, 3}, /* USBTP */
+ {1, 8, 1, 0, 1}, /* USBTN */
+ {1, 9, 2, 1, 3}, /* USBRP */
+ {1, 10, 2, 0, 3}, /* USBRXD */
+ {1, 11, 2, 1, 3}, /* USBRN */
+ {2, 20, 2, 0, 1}, /* CLK21 */
+ {4, 20, 1, 0, 0}, /* SPEED */
+ {4, 21, 1, 0, 0}, /* SUSPND */
+
+ /* END of table */
+ {0, 0, 0, 0, QE_IOP_TAB_END},
+};
+
+int board_early_init_r(void)
+{
+ void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
+ u32 val;
+
+ /*
+ * Because of errata in the UCCs, we have to write to the reserved
+ * registers to slow the clocks down.
+ */
+ val = in_be32(reg);
+ /* UCC1 */
+ val |= 0x00003000;
+ /* UCC2 */
+ val |= 0x0c000000;
+ out_be32(reg, val);
+
+ return 0;
+}
+
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = 0;
+ u32 ddr_size;
+ u32 ddr_size_log2;
+
+ msize = CONFIG_SYS_DDR_SIZE;
+ for (ddr_size = msize << 20, ddr_size_log2 = 0;
+ (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
+ if (ddr_size & 1)
+ return -1;
+ }
+
+ im->sysconf.ddrlaw[0].ar =
+ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
+ im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+ udelay(200);
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+ return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+ msize = fixed_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize DDR ECC byte
+ */
+ ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return (msize * 1024 * 1024);
+}
+
+int checkboard(void)
+{
+ puts("Board: Freescale/Logic MPC8360ERDK\n");
+ return 0;
+}
+
+static struct pci_region pci_regions[] = {
+ {
+ .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
+ .size = CONFIG_SYS_PCI1_MEM_SIZE,
+ .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
+ .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
+ .size = CONFIG_SYS_PCI1_MMIO_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCI1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
+ .size = CONFIG_SYS_PCI1_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci_regions, };
+
+#if defined(CONFIG_PCI_33M)
+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
+ OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
+ printf("PCI clock is 33MHz\n");
+#else
+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
+ printf("PCI clock is 66MHz\n");
+#endif
+
+ udelay(2000);
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+ mpc83xx_pci_init(1, reg);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ ft_pci_setup(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c
new file mode 100644
index 0000000..237c0c4
--- /dev/null
+++ b/board/freescale/mpc8360erdk/nand.c
@@ -0,0 +1,89 @@
+/*
+ * MPC8360E-RDK support for the NAND on FSL UPM
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_83xx.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/fsl_upm.h>
+#include <nand.h>
+
+static struct immap *im = (struct immap *)CONFIG_SYS_IMMR;
+
+static const u32 upm_array[] = {
+ 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */
+ 0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */
+ 0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */
+ 0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */
+ 0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */
+ 0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */
+ 0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */
+ 0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */
+ 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */
+ 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */
+ 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */
+ 0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */
+ 0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */
+};
+
+static void upm_setup(struct fsl_upm *upm)
+{
+ int i;
+
+ /* write upm array */
+ out_be32(upm->mxmr, MxMR_OP_WARR);
+
+ for (i = 0; i < 64; i++) {
+ out_be32(upm->mdr, upm_array[i]);
+ out_8(upm->io_addr, 0x0);
+ }
+
+ /* normal operation */
+ out_be32(upm->mxmr, MxMR_OP_NORM);
+ while (in_be32(upm->mxmr) != MxMR_OP_NORM)
+ eieio();
+}
+
+static int dev_ready(int chip_nr)
+{
+ if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) {
+ debug("nand ready\n");
+ return 1;
+ }
+
+ debug("nand busy\n");
+ return 0;
+}
+
+static struct fsl_upm_nand fun = {
+ .upm = {
+ .io_addr = (void *)CONFIG_SYS_NAND_BASE,
+ },
+ .width = 8,
+ .upm_cmd_offset = 8,
+ .upm_addr_offset = 16,
+ .dev_ready = dev_ready,
+ .wait_flags = FSL_UPM_WAIT_RUN_PATTERN,
+ .chip_delay = 50,
+};
+
+int board_nand_init(struct nand_chip *nand)
+{
+ fun.upm.mxmr = &im->im_lbc.mamr;
+ fun.upm.mdr = &im->im_lbc.mdr;
+ fun.upm.mar = &im->im_lbc.mar;
+
+ upm_setup(&fun.upm);
+
+ return fsl_upm_nand_init(nand, &fun);
+}
diff --git a/board/freescale/mpc837xemds/Kconfig b/board/freescale/mpc837xemds/Kconfig
new file mode 100644
index 0000000..20d29db
--- /dev/null
+++ b/board/freescale/mpc837xemds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC837XEMDS
+
+config SYS_BOARD
+ default "mpc837xemds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC837XEMDS"
+
+endif
diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS
new file mode 100644
index 0000000..6ff1346
--- /dev/null
+++ b/board/freescale/mpc837xemds/MAINTAINERS
@@ -0,0 +1,7 @@
+MPC837XEMDS BOARD
+M: Dave Liu <daveliu@freescale.com>
+S: Maintained
+F: board/freescale/mpc837xemds/
+F: include/configs/MPC837XEMDS.h
+F: configs/MPC837XEMDS_defconfig
+F: configs/MPC837XEMDS_HOST_defconfig
diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile
new file mode 100644
index 0000000..70b2147
--- /dev/null
+++ b/board/freescale/mpc837xemds/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc837xemds.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc837xemds/README b/board/freescale/mpc837xemds/README
new file mode 100644
index 0000000..faf21c9
--- /dev/null
+++ b/board/freescale/mpc837xemds/README
@@ -0,0 +1,104 @@
+Freescale MPC837xEMDS Board
+-----------------------------------------
+1. Board Switches and Jumpers
+1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
+ For some reason, the HW designers describe the switch settings
+ in terms of 0 and 1, and then map that to physical switches where
+ the label "On" refers to logic 0 and "Off" is logic 1.
+
+ Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
+ bits may contribute to signals that are numbered based at 0,
+ and some of those signals may be high-bit-number-0 too. Heed
+ well the names and labels and do not get confused.
+
+ "Off" == 1
+ "On" == 0
+
+ SW4[8] is the bit labeled 8 on Switch 4.
+ SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
+ SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
+ and bits labeled 8 is set as "Off".
+
+1.1 For the MPC837xEMDS Processor Board
+
+ First, make sure the board default setting is consistent with the
+ document shipped with your board. Then apply the following setting:
+ SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting)
+ SW4[1-8]= 0000_0110 (core PLL setting)
+ SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash)
+ SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH)
+ SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII)
+ J3 2-3, TSEC1 LVDD1 with 2.5V
+ J6 2-3, TSEC2 LVDD2 with 2.5V
+ J9 2-3, CLKIN from osc on board
+ J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
+ J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND)
+ mounted, HRCW load from BCSR.
+
+ on board Oscillator: 66M
+
+2. Memory Map
+
+2.1. The memory map should look pretty much like this:
+
+ 0x0000_0000 0x7fff_ffff DDR 2G
+ 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
+ 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
+ 0xc000_0000 0xdfff_ffff Empty 512M
+ 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M
+ 0xe010_0000 0xe02f_ffff Empty 2M
+ 0xe030_0000 0xe03f_ffff PCI IO 1M
+ 0xe040_0000 0xe05f_ffff Empty 2M
+ 0xe060_0000 0xe060_7fff NAND Flash 32K
+ 0xf400_0000 0xf7ff_ffff Empty 64M
+ 0xf800_0000 0xf800_7fff BCSR on CS1 32K
+ 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+ include/configs/MPC837XEMDS.h
+
+ CONFIG_MPC83xx MPC83xx family for both MPC837x and MPC8360
+ CONFIG_MPC837x MPC837x specific
+ CONFIG_MPC837XEMDS MPC837XEMDS board specific
+
+4. Compilation
+
+ Assuming you're using BASH shell:
+
+ export CROSS_COMPILE=your-cross-compile-prefix
+ cd u-boot
+ make distclean
+ make MPC837XEMDS_config
+ make
+
+5. Downloading and Flashing Images
+
+5.0 Download over serial line using Kermit:
+
+ loadb
+ [Drop to kermit:
+ ^\c
+ send <u-boot-bin-image>
+ c
+ ]
+
+
+ Or via tftp:
+
+ tftp 40000 u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+ tftp 40000 u-boot.bin
+ protect off fe000000 fe1fffff
+ erase fe000000 fe1fffff
+
+ cp.b 40000 fe000000 xxxx
+
+You have to supply the correct byte count with 'xxxx' from the TFTP result log.
+
+6. Notes
+ 1) The console baudrate for MPC837XEMDS is 115200bps.
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
new file mode 100644
index 0000000..572913c
--- /dev/null
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+#include <spd_sdram.h>
+#include <tsec.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <fsl_mdio.h>
+#include <phy.h>
+#include "pci.h"
+#include "../common/pq-mds-pib.h"
+
+int board_early_init_f(void)
+{
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
+
+ /* Enable flash write */
+ bcsr[0x9] &= ~0x04;
+ /* Clear all of the interrupt of BCSR */
+ bcsr[0xe] = 0xff;
+
+#ifdef CONFIG_FSL_SERDES
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ u32 spridr = in_be32(&immr->sysconf.spridr);
+
+ /* we check only part num, and don't look for CPU revisions */
+ switch (PARTID_NO_E(spridr)) {
+ case SPR_8377:
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ break;
+ case SPR_8378:
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
+ FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
+ break;
+ case SPR_8379:
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ break;
+ default:
+ printf("serdes not configured: unknown CPU part number: "
+ "%04x\n", spridr >> 16);
+ break;
+ }
+#endif /* CONFIG_FSL_SERDES */
+ return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
+
+ if (!hwconfig("esdhc"))
+ return 0;
+
+ /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
+ bcsr[0xc] |= 0x4c;
+
+ /* Set proper bits in SICR to allow SD signals through */
+ clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
+ clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
+ SICRH_GPIO2_E_SD | SICRH_SPI_SD);
+
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
+#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
+int board_eth_init(bd_t *bd)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[2];
+ struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+ u32 rcwh = in_be32(&im->reset.rcwh);
+ u32 tsec_mode;
+ int num = 0;
+
+ /* New line after Net: */
+ printf("\n");
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+
+ printf(CONFIG_TSEC1_NAME ": ");
+
+ tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
+ if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
+ printf("RGMII\n");
+ /* this is default, no need to fixup */
+ } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
+ printf("SGMII\n");
+ tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
+ tsec_info[num].flags = TSEC_GIGABIT;
+ } else {
+ printf("unsupported PHY type\n");
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+
+ printf(CONFIG_TSEC2_NAME ": ");
+
+ tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
+ if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
+ printf("RGMII\n");
+ /* this is default, no need to fixup */
+ } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
+ printf("SGMII\n");
+ tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
+ tsec_info[num].flags = TSEC_GIGABIT;
+ } else {
+ printf("unsupported PHY type\n");
+ }
+ num++;
+#endif
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bd, &mdio_info);
+
+ return tsec_eth_init(bd, tsec_info, num);
+}
+
+static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
+ int phy_addr)
+{
+ const u32 *ph;
+ int off;
+ int err;
+
+ off = fdt_path_offset(blob, alias);
+ if (off < 0) {
+ printf("WARNING: could not find %s alias: %s.\n", alias,
+ fdt_strerror(off));
+ return;
+ }
+
+ err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII);
+
+ if (err) {
+ printf("WARNING: could not set phy-connection-type for %s: "
+ "%s.\n", alias, fdt_strerror(err));
+ return;
+ }
+
+ ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
+ if (!ph) {
+ printf("WARNING: could not get phy-handle for %s.\n",
+ alias);
+ return;
+ }
+
+ off = fdt_node_offset_by_phandle(blob, *ph);
+ if (off < 0) {
+ printf("WARNING: could not get phy node for %s: %s\n", alias,
+ fdt_strerror(off));
+ return;
+ }
+
+ phy_addr = cpu_to_fdt32(phy_addr);
+ err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
+ if (err < 0) {
+ printf("WARNING: could not set phy node's reg for %s: "
+ "%s.\n", alias, fdt_strerror(err));
+ return;
+ }
+}
+
+static void ft_tsec_fixup(void *blob, bd_t *bd)
+{
+ struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+ u32 rcwh = in_be32(&im->reset.rcwh);
+ u32 tsec_mode;
+
+#ifdef CONFIG_TSEC1
+ tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
+ if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
+ __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
+#endif
+
+#ifdef CONFIG_TSEC2
+ tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
+ if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
+ __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
+#endif
+}
+#else
+static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
+#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_PQ_MDS_PIB
+ pib_init();
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+int fixed_sdram(void);
+
+phys_size_t initdram(int board_type)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+ return -1;
+
+#if defined(CONFIG_SPD_EEPROM)
+ msize = spd_sdram();
+#else
+ msize = fixed_sdram();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /* Initialize DDR ECC byte */
+ ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+ /* return total bus DDR size(bytes) */
+ return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+ u32 msize_log2 = __ilog2(msize);
+
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+
+#if (CONFIG_SYS_DDR_SIZE != 512)
+#warning Currenly any ddr size other than 512 is not supported
+#endif
+ im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+ udelay(50000);
+
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+ udelay(1000);
+
+ im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ udelay(1000);
+
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ __asm__ __volatile__("sync");
+ udelay(1000);
+
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+ udelay(2000);
+ return CONFIG_SYS_DDR_SIZE;
+}
+#endif /*!CONFIG_SYS_SPD_EEPROM */
+
+int checkboard(void)
+{
+ puts("Board: Freescale MPC837xEMDS\n");
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+int board_pci_host_broken(void)
+{
+ struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+ const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
+
+ /* It's always OK in case of external arbiter. */
+ if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
+ return 0;
+
+ if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
+ return 1;
+
+ return 0;
+}
+
+static void ft_pci_fixup(void *blob, bd_t *bd)
+{
+ const char *status = "broken (no arbiter)";
+ int off;
+ int err;
+
+ off = fdt_path_offset(blob, "pci0");
+ if (off < 0) {
+ printf("WARNING: could not find pci0 alias: %s.\n",
+ fdt_strerror(off));
+ return;
+ }
+
+ err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
+ if (err) {
+ printf("WARNING: could not set status for pci0: %s.\n",
+ fdt_strerror(err));
+ return;
+ }
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ ft_tsec_fixup(blob, bd);
+ fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+ if (board_pci_host_broken())
+ ft_pci_fixup(blob, bd);
+ ft_pcie_fixup(blob, bd);
+#endif
+
+ return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c
new file mode 100644
index 0000000..39c40e5
--- /dev/null
+++ b/board/freescale/mpc837xemds/pci.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/fsl_i2c.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+static struct pci_region pci_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+ size: CONFIG_SYS_PCI_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+ size: CONFIG_SYS_PCI_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+ {
+ bus_start: CONFIG_SYS_PCI_IO_BASE,
+ phys_start: CONFIG_SYS_PCI_IO_PHYS,
+ size: CONFIG_SYS_PCI_IO_SIZE,
+ flags: PCI_REGION_IO
+ }
+};
+
+static struct pci_region pcie_regions_0[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE1_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+ .size = CONFIG_SYS_PCIE1_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+static struct pci_region pcie_regions_1[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE2_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+ .size = CONFIG_SYS_PCIE2_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+static int is_pex_x2(void)
+{
+ const char *pex_x2 = getenv("pex_x2");
+
+ if (pex_x2 && !strcmp(pex_x2, "yes"))
+ return 1;
+ return 0;
+}
+
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile sysconf83xx_t *sysconf = &immr->sysconf;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ volatile law83xx_t *pcie_law = sysconf->pcielaw;
+ struct pci_region *reg[] = { pci_regions };
+ struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+ u32 spridr = in_be32(&immr->sysconf.spridr);
+ int pex2 = is_pex_x2();
+
+ if (board_pci_host_broken())
+ goto skip_pci;
+
+ /* Enable all 5 PCI_CLK_OUTPUTS */
+ clk->occr |= 0xf8000000;
+ udelay(2000);
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+ pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+ udelay(2000);
+
+ mpc83xx_pci_init(1, reg);
+skip_pci:
+ /* There is no PEX in MPC8379 parts. */
+ if (PARTID_NO_E(spridr) == SPR_8379)
+ return;
+
+ if (pex2)
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ else
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+ /* Configure the clock for PCIE controller */
+ clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+ SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+ /* Deassert the resets in the control register */
+ out_be32(&sysconf->pecr1, 0xE0008000);
+ if (!pex2)
+ out_be32(&sysconf->pecr2, 0xE0008000);
+ udelay(2000);
+
+ /* Configure PCI Express Local Access Windows */
+ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
+}
+
+void ft_pcie_fixup(void *blob, bd_t *bd)
+{
+ const char *status = "disabled (PCIE1 is x2)";
+
+ if (!is_pex_x2())
+ return;
+
+ do_fixup_by_path(blob, "pci2", "status", status,
+ strlen(status) + 1, 1);
+}
diff --git a/board/freescale/mpc837xemds/pci.h b/board/freescale/mpc837xemds/pci.h
new file mode 100644
index 0000000..fd7a916
--- /dev/null
+++ b/board/freescale/mpc837xemds/pci.h
@@ -0,0 +1,6 @@
+#ifndef __BOARD_MPC837XEMDS_PCI_H
+#define __BOARD_MPC837XEMDS_PCI_H
+
+extern void ft_pcie_fixup(void *blob, bd_t *bd);
+
+#endif /* __BOARD_MPC837XEMDS_PCI_H */
diff --git a/board/freescale/mpc837xerdb/Kconfig b/board/freescale/mpc837xerdb/Kconfig
new file mode 100644
index 0000000..03415f9
--- /dev/null
+++ b/board/freescale/mpc837xerdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC837XERDB
+
+config SYS_BOARD
+ default "mpc837xerdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC837XERDB"
+
+endif
diff --git a/board/freescale/mpc837xerdb/MAINTAINERS b/board/freescale/mpc837xerdb/MAINTAINERS
new file mode 100644
index 0000000..8592a2c
--- /dev/null
+++ b/board/freescale/mpc837xerdb/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC837XERDB BOARD
+#M: Joe D'Abbraccio <ljd015@freescale.com>
+S: Orphan (since 2014-06)
+F: board/freescale/mpc837xerdb/
+F: include/configs/MPC837XERDB.h
+F: configs/MPC837XERDB_defconfig
diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile
new file mode 100644
index 0000000..c2d0bc4
--- /dev/null
+++ b/board/freescale/mpc837xerdb/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc837xerdb.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc837xerdb/README b/board/freescale/mpc837xerdb/README
new file mode 100644
index 0000000..cfb6efa
--- /dev/null
+++ b/board/freescale/mpc837xerdb/README
@@ -0,0 +1,97 @@
+Freescale MPC837xE-RDB Board
+-----------------------------------------
+
+1. Board Description
+
+ The MPC837xE-RDB are reference boards featuring the Freescale MPC8377E,
+ MPC8378E, and the MPC8379E processors in a Mini-ITX form factor.
+
+ The MPC837xE-RDB's have the following common features:
+
+ A) 256-MBytes on-board DDR2 unbuffered SDRAM
+ B) 8-Mbytes NOR Flash
+ C) 32-MBytes NAND Flash
+ D) 1 Secure Digital High Speed Card (SDHC) Interface
+ E) 1 Gigabit Ethernet
+ F) 5-port Ethernet switch (Vitesse 7385)
+ G) 1 32-bit, 3.3 V, PCI slot
+ H) 1 32-bit, 3.3 V, Mini-PCI slot
+ I) 4-port USB 2.0 Hub
+ J) 1-port OTG USB
+ K) 2 serial ports (top main console)
+ L) on board Oscillator: 66M
+
+ The MPC837xE-RDB's have the following differences:
+
+ MPC8377E-RDB MPC8378E-RDB MPC8379E-RDB
+ SATA controllers 2 0 4
+ PCI-Express (mini) 2 2 0
+ SGMII Ports 0 2 0
+
+
+2. Memory Map
+
+2.1. The memory map should look pretty much like this:
+
+ Address Range Device Size Port Size
+ (Bytes) (Bits)
+ =========================== ================= ======= =========
+ 0x0000_0000 0x0fff_ffff DDR 256M 64
+ 0x1000_0000 0x7fff_ffff Empty 1.75G -
+ 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 32
+ 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 32
+ 0xe030_0000 0xe03f_ffff PCI I/O space 1M 32
+ 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M -
+ 0xe060_0000 0xe060_7fff NAND Flash 32K 8
+ 0xfe00_0000 0xfe7f_ffff NOR Flash on CS0 8M 16
+
+
+3. Definitions
+
+3.1 Explanation of NEW definitions in:
+
+ include/configs/MPC837XERDB.h
+
+ CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
+ CONFIG_MPC837x MPC837x specific
+ CONFIG_MPC837XERDB MPC837xE-RDB board specific
+
+
+4. Compilation
+
+ Assuming you're using BASH shell:
+
+ export CROSS_COMPILE=your-cross-compile-prefix
+ cd u-boot
+ make distclean
+ make MPC837XERDB_config
+ make
+
+
+5. Downloading and Flashing Images
+
+5.0 Download over serial line using Kermit:
+
+ loadb $loadaddr
+ [Drop to kermit:
+ ^\c
+ send <u-boot-bin-image>
+ c
+ ]
+
+
+ Or via tftp:
+
+ tftp $loadaddr u-boot.bin
+
+5.1 Reflash U-boot Image using U-boot
+
+ tftp $loadaddr u-boot.bin
+ protect off fe000000 fe0fffff
+ erase fe000000 fe0fffff
+ cp.b $loadaddr fe000000 $filesize
+
+
+6. Additional Notes:
+ 1) The console is connected to the top RS-232 connector and the
+ baudrate for MPC837XE-RDB is 115200bps.
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
new file mode 100644
index 0000000..e0a1031
--- /dev/null
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Kevin Lam <kevin.lam@freescale.com>
+ * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+#include <fdt_support.h>
+#include <spd_sdram.h>
+#include <vsc7385.h>
+#include <fsl_esdhc.h>
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+ uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CONFIG_SYS_MEMTEST_START,
+ CONFIG_SYS_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+int fixed_sdram(void);
+
+phys_size_t initdram(int board_type)
+{
+ immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+ return -1;
+
+#if defined(CONFIG_SPD_EEPROM)
+ msize = spd_sdram();
+#else
+ msize = fixed_sdram();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /* Initialize DDR ECC byte */
+ ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+ /* return total bus DDR size(bytes) */
+ return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+ immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+ u32 msize_log2 = __ilog2(msize);
+
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+
+ im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
+ udelay(50000);
+
+ im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+ udelay(1000);
+
+ im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+ udelay(1000);
+
+ im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+ im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ sync();
+ udelay(1000);
+
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+ udelay(2000);
+ return CONFIG_SYS_DDR_SIZE;
+}
+#endif /*!CONFIG_SYS_SPD_EEPROM */
+
+int checkboard(void)
+{
+ puts("Board: Freescale MPC837xERDB\n");
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_FSL_SERDES
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ u32 spridr = in_be32(&immr->sysconf.spridr);
+
+ /* we check only part num, and don't look for CPU revisions */
+ switch (PARTID_NO_E(spridr)) {
+ case SPR_8377:
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ break;
+ case SPR_8378:
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ break;
+ case SPR_8379:
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ break;
+ default:
+ printf("serdes not configured: unknown CPU part number: "
+ "%04x\n", spridr >> 16);
+ break;
+ }
+#endif /* CONFIG_FSL_SERDES */
+ return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+
+ if (!hwconfig("esdhc"))
+ return 0;
+
+ clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
+ clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
+
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+ int rc = 0;
+
+#ifdef CONFIG_VSC7385_IMAGE
+ if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+ CONFIG_VSC7385_IMAGE_SIZE)) {
+ puts("Failure uploading VSC7385 microcode.\n");
+ rc = 1;
+ }
+#endif
+
+ return rc;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
+
+ return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c
new file mode 100644
index 0000000..8f50c93
--- /dev/null
+++ b/board/freescale/mpc837xerdb/pci.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <asm/io.h>
+
+static struct pci_region pci_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+ size: CONFIG_SYS_PCI_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+ size: CONFIG_SYS_PCI_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+ {
+ bus_start: CONFIG_SYS_PCI_IO_BASE,
+ phys_start: CONFIG_SYS_PCI_IO_PHYS,
+ size: CONFIG_SYS_PCI_IO_SIZE,
+ flags: PCI_REGION_IO
+ }
+};
+
+static struct pci_region pcie_regions_0[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE1_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+ .size = CONFIG_SYS_PCIE1_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+static struct pci_region pcie_regions_1[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE2_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+ .size = CONFIG_SYS_PCIE2_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile sysconf83xx_t *sysconf = &immr->sysconf;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ volatile law83xx_t *pcie_law = sysconf->pcielaw;
+ struct pci_region *reg[] = { pci_regions };
+ struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+ u32 spridr = in_be32(&immr->sysconf.spridr);
+
+ /* Enable all 5 PCI_CLK_OUTPUTS */
+ clk->occr |= 0xf8000000;
+ udelay(2000);
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+ pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+ mpc83xx_pci_init(1, reg);
+
+ /* There is no PEX in MPC8379 parts. */
+ if (PARTID_NO_E(spridr) == SPR_8379)
+ return;
+
+ /* Configure the clock for PCIE controller */
+ clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+ SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+ /* Deassert the resets in the control register */
+ out_be32(&sysconf->pecr1, 0xE0008000);
+ out_be32(&sysconf->pecr2, 0xE0008000);
+ udelay(2000);
+
+ /* Configure PCI Express Local Access Windows */
+ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ mpc83xx_pcie_init(2, pcie_reg);
+}
diff --git a/board/freescale/mpc8536ds/Kconfig b/board/freescale/mpc8536ds/Kconfig
new file mode 100644
index 0000000..1a6a9d4
--- /dev/null
+++ b/board/freescale/mpc8536ds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8536DS
+
+config SYS_BOARD
+ default "mpc8536ds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8536DS"
+
+endif
diff --git a/board/freescale/mpc8536ds/MAINTAINERS b/board/freescale/mpc8536ds/MAINTAINERS
new file mode 100644
index 0000000..953072c
--- /dev/null
+++ b/board/freescale/mpc8536ds/MAINTAINERS
@@ -0,0 +1,9 @@
+MPC8536DS BOARD
+#M: -
+S: Maintained
+F: board/freescale/mpc8536ds/
+F: include/configs/MPC8536DS.h
+F: configs/MPC8536DS_defconfig
+F: configs/MPC8536DS_36BIT_defconfig
+F: configs/MPC8536DS_SDCARD_defconfig
+F: configs/MPC8536DS_SPIFLASH_defconfig
diff --git a/board/freescale/mpc8536ds/Makefile b/board/freescale/mpc8536ds/Makefile
new file mode 100644
index 0000000..e36492f
--- /dev/null
+++ b/board/freescale/mpc8536ds/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2008 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8536ds.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/mpc8536ds/README b/board/freescale/mpc8536ds/README
new file mode 100644
index 0000000..2a38bd6
--- /dev/null
+++ b/board/freescale/mpc8536ds/README
@@ -0,0 +1,127 @@
+Overview:
+=========
+
+The MPC8536E integrates a PowerPC processor core with system logic
+required for imaging, networking, and communications applications.
+
+Boot from NAND:
+===============
+
+The MPC8536E is capable of booting from NAND flash which uses the image
+u-boot-nand.bin. This image contains two parts: a first stage image(also
+call 4K NAND loader and a second stage image. The former is appended to
+the latter to produce u-boot-nand.bin.
+
+The bootup process can be divided into two stages: the first stage will
+configure the L2SRAM, then copy the second stage image to L2SRAM and jump
+to it. The second stage image is to configure all the hardware and boot up
+to U-Boot command line.
+
+The 4K NAND loader's code comes from the corresponding nand_spl directory,
+along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL
+is mainly used to shrink the code size to the 4K size limitation.
+
+The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
+second stage image. It's set in the board config file when boot from NAND
+is selected.
+
+Build and boot steps
+--------------------
+
+1. Building image
+ make MPC8536DS_NAND_config
+ make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
+
+2. Change dip-switch
+ SW2[5-8] = 1011
+ SW9[1-3] = 101
+ Note: 1 stands for 'on', 0 stands for 'off'
+
+3. Flash image
+ tftp 1000000 u-boot-nand.bin
+ nand erase 0 a0000
+ nand write 1000000 0 a0000
+
+Boot from On-chip ROM:
+======================
+
+The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC
+and boot from eSPI. When power on, the porcessor excutes the ROM code to
+initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from
+the memory device that interfaced to the controller, such as the SDCard or
+SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it.
+
+The memory device should contain a specific data structure with control word
+and config word at the fixed address. The config word direct the process how
+to config the memory device, and the control word direct the processor where
+to find the image on the memory device, or where copy the main image to. The
+user can use any method to store the data structure to the memory device, only
+if store it on the assigned address.
+
+Build and boot steps
+--------------------
+
+For boot from eSDHC:
+1. Build image
+ make MPC8536DS_SDCARD_config
+ make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
+
+2. Change dip-switch
+ SW2[5-8] = 0111
+ SW3[1] = 0
+ SW8[7] = 0 - The on-board SD/MMC slot is active
+ SW8[7] = 1 - The externel SD/MMC slot is active
+
+3. Put image to SDCard
+ Put the follwing info at the assigned address on the SDCard:
+
+ Offset | Data | Description
+ --------------------------------------------------------
+ | 0x40-0x43 | 0x424F4F54 | BOOT signature |
+ --------------------------------------------------------
+ | 0x48-0x4B | 0x00080000 | u-boot.bin's size |
+ --------------------------------------------------------
+ | 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard |
+ --------------------------------------------------------
+ | 0x58-0x5B | 0xF8F80000 | Target Address |
+ -------------------------------------------------------
+ | 0x60-0x63 | 0xF8FFF000 | Execution Starting Address |
+ --------------------------------------------------------
+ | 0x68-0x6B | 0x6 | Number of Config Addr/Data |
+ --------------------------------------------------------
+ | 0x80-0x83 | 0xFF720100 | Config Addr 1 |
+ | 0x84-0x87 | 0xF8F80000 | Config Data 1 |
+ --------------------------------------------------------
+ | 0x88-0x8b | 0xFF720e44 | Config Addr 2 |
+ | 0x8c-0x8f | 0x0000000C | Config Data 2 |
+ --------------------------------------------------------
+ | 0x90-0x93 | 0xFF720000 | Config Addr 3 |
+ | 0x94-0x97 | 0x80010000 | Config Data 3 |
+ --------------------------------------------------------
+ | 0x98-0x9b | 0xFF72e40c | Config Addr 4 |
+ | 0x9c-0x9f | 0x00000040 | Config Data 4 |
+ --------------------------------------------------------
+ | 0xa0-0xa3 | 0x40000001 | Config Addr 5 |
+ | 0xa4-0xa7 | 0x00000100 | Config Data 5 |
+ --------------------------------------------------------
+ | 0xa8-0xab | 0x80000001 | Config Addr 6 |
+ | 0xac-0xaf | 0x80000001 | Config Data 6 |
+ --------------------------------------------------------
+ | ...... |
+ --------------------------------------------------------
+ | 0x???????? | u-boot.bin |
+ --------------------------------------------------------
+
+ then insert the SDCard to the active slot to boot up.
+
+For boot from eSPI:
+1. Build image
+ make MPC8536DS_SPIFLASH_config
+ make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
+
+2. Change dip-switch
+ SW2[5-8] = 0110
+
+3. Put image to SPI flash
+ Put the info in the above table onto the SPI flash, then
+ boot up.
diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c
new file mode 100644
index 0000000..ebe3ba4
--- /dev/null
+++ b/board/freescale/mpc8536ds/ddr.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 10;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+
+ /*
+ * For wake up arp feature, we need enable auto self refresh
+ */
+ popts->auto_self_refresh_en = 1;
+ popts->sr_it = 0x6;
+}
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
new file mode 100644
index 0000000..f804bae
--- /dev/null
+++ b/board/freescale/mpc8536ds/law.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
new file mode 100644
index 0000000..7b0f461
--- /dev/null
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <spd_sdram.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <netdev.h>
+#include <sata.h>
+
+#include "../common/sgmii_riser.h"
+
+int board_early_init_f (void)
+{
+#ifdef CONFIG_MMC
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->pmuxcr,
+ (MPC85xx_PMUXCR_SDHC_CD |
+ MPC85xx_PMUXCR_SDHC_WP));
+
+ /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
+ * however, this erratum only applies to MPC8536 Rev1.0.
+ * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
+ if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
+ (SVR_MIN(get_svr()) >= 0x1))
+ || (SVR_MAJ(get_svr() & 0x7) > 0x1))
+ setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
+#endif
+ return 0;
+}
+
+int checkboard (void)
+{
+ u8 vboot;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ printf("Board: MPC8536DS Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+ in_8(pixis_base + PIXIS_PVER));
+
+ vboot = in_8(pixis_base + PIXIS_VBOOT);
+ switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
+ case PIXIS_VBOOT_LBMAP_NOR0:
+ puts ("vBank: 0\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_NOR1:
+ puts ("vBank: 1\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_NOR2:
+ puts ("vBank: 2\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_NOR3:
+ puts ("vBank: 3\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_PJET:
+ puts ("Promjet\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_NAND:
+ puts ("NAND\n");
+ break;
+ }
+
+ return 0;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram (void)
+{
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
+ uint d_init;
+
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+
+ ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+ ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+ ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
+
+#if defined (CONFIG_DDR_ECC)
+ ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
+ ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
+ ddr->err_sbe = CONFIG_SYS_DDR_SBE;
+#endif
+ asm("sync;isync");
+
+ udelay(500);
+
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ d_init = 1;
+ debug("DDR - 1st controller: memory initializing\n");
+ /*
+ * Poll until memory is initialized.
+ * 512 Meg at 400 might hit this 200 times or so.
+ */
+ while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+ udelay(1000);
+ }
+ debug("DDR: memory initialized\n\n");
+ asm("sync; isync");
+ udelay(500);
+#endif
+
+ return 512 * 1024 * 1024;
+}
+
+#endif
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct fsl_pci_info pci_info;
+ u32 devdisr, pordevsr;
+ u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+ int first_free_busno;
+
+ first_free_busno = fsl_pcie_init_board(0);
+
+#ifdef CONFIG_PCI1
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ porpllsr = in_be32(&gur->porpllsr);
+
+ pci_speed = 66666000;
+ pci_32 = 1;
+ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info, 1);
+ set_next_law(pci_info.mem_phys,
+ law_size_bits(pci_info.mem_size), pci_info.law);
+ set_next_law(pci_info.io_phys,
+ law_size_bits(pci_info.io_size), pci_info.law);
+
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+ printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter",
+ pci_info.regs);
+
+ first_free_busno = fsl_pci_init_port(&pci_info,
+ &pci1_hose, first_free_busno);
+ } else {
+ printf("PCI: disabled\n");
+ }
+
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
+#endif
+}
+#endif
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 1; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_TSEC_ENET
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[2];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ if (is_serdes_configured(SGMII_TSEC1)) {
+ puts("eTSEC1 is in sgmii mode.\n");
+ tsec_info[num].phyaddr = 0;
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ if (is_serdes_configured(SGMII_TSEC3)) {
+ puts("eTSEC3 is in sgmii mode.\n");
+ tsec_info[num].phyaddr = 1;
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+#ifdef CONFIG_FSL_SGMII_RISER
+ if (is_serdes_configured(SGMII_TSEC1) ||
+ is_serdes_configured(SGMII_TSEC3)) {
+ fsl_sgmii_riser_init(tsec_info, num);
+ }
+#endif
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+#endif
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_fdt_fixup(blob);
+#endif
+
+#ifdef CONFIG_HAS_FSL_MPH_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
new file mode 100644
index 0000000..3f4685f
--- /dev/null
+++ b/board/freescale/mpc8536ds/tlb.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+
+ /* W**G* - Flash/promjet, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256K, 1),
+
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8540ads/Kconfig b/board/freescale/mpc8540ads/Kconfig
new file mode 100644
index 0000000..35a8545
--- /dev/null
+++ b/board/freescale/mpc8540ads/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8540ADS
+
+config SYS_BOARD
+ default "mpc8540ads"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8540ADS"
+
+endif
diff --git a/board/freescale/mpc8540ads/MAINTAINERS b/board/freescale/mpc8540ads/MAINTAINERS
new file mode 100644
index 0000000..acc4821
--- /dev/null
+++ b/board/freescale/mpc8540ads/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8540ADS BOARD
+#M: Kumar Gala <kumar.gala@freescale.com>
+S: Orphan (since 2014-06)
+F: board/freescale/mpc8540ads/
+F: include/configs/MPC8540ADS.h
+F: configs/MPC8540ADS_defconfig
diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile
new file mode 100644
index 0000000..6f82c7f
--- /dev/null
+++ b/board/freescale/mpc8540ads/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8540ads.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
new file mode 100644
index 0000000..41d4cfe
--- /dev/null
+++ b/board/freescale/mpc8540ads/ddr.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 0;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /* 2T timing enable */
+ popts->twot_en = 1;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c
new file mode 100644
index 0000000..41f2e02
--- /dev/null
+++ b/board/freescale/mpc8540ads/law.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff BCSR 1M
+ * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#endif
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ /* This is not so much the SDRAM map as it is the whole localbus map. */
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
new file mode 100644
index 0000000..1069e2c
--- /dev/null
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <fsl_ddr_sdram.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+void local_bus_init(void);
+
+int checkboard (void)
+{
+ puts("Board: ADS\n");
+
+#ifdef CONFIG_PCI
+ printf("PCI1: 32 bit, %d MHz (compiled)\n",
+ CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+ printf("PCI1: disabled\n");
+#endif
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init();
+
+ return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ /*
+ * Errata LBC11.
+ * Fix Local Bus clock glitch when DLL is enabled.
+ *
+ * If localbus freq is < 66MHz, DLL bypass mode must be used.
+ * If localbus freq is > 133MHz, DLL can be safely enabled.
+ * Between 66 and 133, the DLL is enabled with an override workaround.
+ */
+
+ get_sys_info(&sysinfo);
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
+ lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
+
+ if (lbc_hz < 66) {
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
+
+ } else if (lbc_hz >= 133) {
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
+
+ } else {
+ /*
+ * On REV1 boards, need to change CLKDIV before enable DLL.
+ * Default CLKDIV is 8, change it to 4 temporarily.
+ */
+ uint pvr = get_pvr();
+ uint temp_lbcdll = 0;
+
+ if (pvr == PVR_85xx_REV1) {
+ /* FIXME: Justify the high bit here. */
+ lbc->lcrr = 0x10000004;
+ }
+
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
+ udelay(200);
+
+ /*
+ * Sample LBC DLL ctrl reg, upshift it to set the
+ * override bits.
+ */
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+ asm("sync;isync;msync");
+ }
+}
+
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+
+ puts("LBC SDRAM: ");
+ print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+ "\n ");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ asm("msync");
+
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ asm("sync");
+
+ /*
+ * Configure the SDRAM controller.
+ */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+phys_size_t fixed_sdram(void)
+{
+ #ifndef CONFIG_SYS_RAMBOOT
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ #if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000000D;
+ ddr->err_sbe = 0x00ff0000;
+ #endif
+ asm("sync;isync;msync");
+ udelay(500);
+ #if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
+ #else
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+ #endif
+ asm("sync; isync; msync");
+ udelay(500);
+ #endif
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+
+static struct pci_controller hose;
+
+#endif /* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ ft_cpu_setup(blob, bd);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose.last_busno - hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c
new file mode 100644
index 0000000..d5ee791
--- /dev/null
+++ b/board/freescale/mpc8540ads/tlb.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_16M, 1),
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xc0000000 256M Rapid IO MEM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xd0000000 256M Rapid IO MEM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 7: 16K Non-cacheable, guarded
+ * 0xf8000000 16K BCSR registers
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_16K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8541cds/Kconfig b/board/freescale/mpc8541cds/Kconfig
new file mode 100644
index 0000000..034eab2
--- /dev/null
+++ b/board/freescale/mpc8541cds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8541CDS
+
+config SYS_BOARD
+ default "mpc8541cds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8541CDS"
+
+endif
diff --git a/board/freescale/mpc8541cds/MAINTAINERS b/board/freescale/mpc8541cds/MAINTAINERS
new file mode 100644
index 0000000..d421b12
--- /dev/null
+++ b/board/freescale/mpc8541cds/MAINTAINERS
@@ -0,0 +1,7 @@
+MPC8541CDS BOARD
+#M: Kumar Gala <kumar.gala@freescale.com>
+S: Orphan (since 2014-06)
+F: board/freescale/mpc8541cds/
+F: include/configs/MPC8541CDS.h
+F: configs/MPC8541CDS_defconfig
+F: configs/MPC8541CDS_legacy_defconfig
diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile
new file mode 100644
index 0000000..78af4b8
--- /dev/null
+++ b/board/freescale/mpc8541cds/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8541cds.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c
new file mode 100644
index 0000000..d2ac6c4
--- /dev/null
+++ b/board/freescale/mpc8541cds/ddr.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 6;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 0;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c
new file mode 100644
index 0000000..39df3f1
--- /dev/null
+++ b/board/freescale/mpc8541cds/law.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
new file mode 100644
index 0000000..7b264dd
--- /dev/null
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -0,0 +1,427 @@
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <fsl_ddr_sdram.h>
+#include <ioports.h>
+#include <spd_sdram.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+void local_bus_init(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+int checkboard (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ char buf[32];
+
+ /* PCI slot in USER bits CSR[6:7] by convention. */
+ uint pci_slot = get_pci_slot ();
+
+ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
+ uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
+ uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
+ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
+
+ uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+
+ uint cpu_board_rev = get_cpu_board_revision ();
+
+ printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+ get_board_version (), pci_slot);
+
+ printf ("CPU Board Revision %d.%d (0x%04x)\n",
+ MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+ MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+ printf("PCI1: %d bit, %s MHz, %s\n",
+ (pci1_32) ? 32 : 64,
+ strmhz(buf, pci1_speed),
+ pci1_clk_sel ? "sync" : "async");
+
+ if (pci_dual) {
+ printf("PCI2: 32 bit, 66 MHz, %s\n",
+ pci2_clk_sel ? "sync" : "async");
+ } else {
+ printf("PCI2: disabled\n");
+ }
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+ uint temp_lbcdll;
+
+ /*
+ * Errata LBC11.
+ * Fix Local Bus clock glitch when DLL is enabled.
+ *
+ * If localbus freq is < 66MHz, DLL bypass mode must be used.
+ * If localbus freq is > 133MHz, DLL can be safely enabled.
+ * Between 66 and 133, the DLL is enabled with an override workaround.
+ */
+
+ get_sys_info(&sysinfo);
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
+ lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
+
+ if (lbc_hz < 66) {
+ lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
+
+ } else if (lbc_hz >= 133) {
+ lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
+
+ } else {
+ lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
+ udelay(200);
+
+ /*
+ * Sample LBC DLL ctrl reg, upshift it to set the
+ * override bits.
+ */
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+ asm("sync;isync;msync");
+ }
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+
+ uint idx;
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+ uint cpu_board_rev;
+ uint lsdmr_common;
+
+ puts("LBC SDRAM: ");
+ print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+ "\n ");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ asm("msync");
+
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * Determine which address lines to use baed on CPU board rev.
+ */
+ cpu_board_rev = get_cpu_board_revision();
+ lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+ if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+ lsdmr_common |= LSDMR_BSMA1617;
+ } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+ lsdmr_common |= LSDMR_BSMA1516;
+ } else {
+ /*
+ * Assume something unable to identify itself is
+ * really old, and likely has lines 16/17 mapped.
+ */
+ lsdmr_common |= LSDMR_BSMA1617;
+ }
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CONFIG_PCI)
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it.
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+ mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+ mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
+ {},
+};
+
+static struct pci_controller hose[] = {
+ { config_table: pci_mpc85xxcds_config_table,},
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init(hose);
+#endif
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose[0].last_busno - hose[0].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = hose[1].last_busno - hose[1].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c
new file mode 100644
index 0000000..fff3b4a
--- /dev/null
+++ b/board/freescale/mpc8541cds/tlb.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_16M, 1),
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xa0000000 256M PCI2 MEM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xb0000000 256M PCI2 MEM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ * 0xe300_0000 16M PCI2 IO
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 7: 1M Non-cacheable, guarded
+ * 0xf8000000 1M CADMUS registers
+ */
+ SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_1M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8544ds/Kconfig b/board/freescale/mpc8544ds/Kconfig
new file mode 100644
index 0000000..c3e25b8
--- /dev/null
+++ b/board/freescale/mpc8544ds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8544DS
+
+config SYS_BOARD
+ default "mpc8544ds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8544DS"
+
+endif
diff --git a/board/freescale/mpc8544ds/MAINTAINERS b/board/freescale/mpc8544ds/MAINTAINERS
new file mode 100644
index 0000000..328be7f
--- /dev/null
+++ b/board/freescale/mpc8544ds/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8544DS BOARD
+#M: -
+S: Maintained
+F: board/freescale/mpc8544ds/
+F: include/configs/MPC8544DS.h
+F: configs/MPC8544DS_defconfig
diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile
new file mode 100644
index 0000000..3359eea
--- /dev/null
+++ b/board/freescale/mpc8544ds/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8544ds.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/mpc8544ds/README b/board/freescale/mpc8544ds/README
new file mode 100644
index 0000000..b49c3c0
--- /dev/null
+++ b/board/freescale/mpc8544ds/README
@@ -0,0 +1,122 @@
+Overview
+--------
+The MPC8544DS system is similar to the 85xx CDS systems such
+as the MPC8548CDS due to the similar E500 core. However, it
+is placed on the same board as the 8641 HPCN system.
+
+
+Flash Banks
+-----------
+Like the 85xx CDS systems, the 8544 DS board has two flash banks.
+They are both present on boot, but there locations can be swapped
+using the dip-switch SW10, bit 2.
+
+However, unlike the CDS systems, but similar to the 8641 HPCN
+board, a runtime reset through the FPGA can also affect a swap
+on the flash bank mappings for the next reset cycle.
+
+Irrespective of the switch SW10[2], booting is always from the
+boot bank at 0xfff8_0000.
+
+
+Memory Map
+----------
+
+0xff80_0000 - 0xffbf_ffff Alternate bank 4MB
+0xffc0_0000 - 0xffff_ffff Boot bank 4MB
+
+0xffb8_0000 Alternate image start 512KB
+0xfff8_0000 Boot image start 512KB
+
+
+Flashing Images
+---------------
+
+For example, to place a new image in the alternate flash bank
+and then reset with that new image temporarily, use this:
+
+ tftp 1000000 u-boot.bin.8544ds
+ erase ffb80000 ffbfffff
+ cp.b 1000000 ffb80000 80000
+ pixis_reset altbank
+
+
+To overwrite the image in the boot flash bank:
+
+ tftp 1000000 u-boot.bin.8544ds
+ protect off all
+ erase fff80000 ffffffff
+ cp.b 1000000 fff80000 80000
+
+Other example U-Boot image and flash manipulations examples
+can be found in the README.mpc85xxcds file as well.
+
+
+The pixis_reset command
+-----------------------
+A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
+using the FPGA sequencer. When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+ pixis_reset
+ pixis_reset altbank
+ pixis_reset altbank wd
+ pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+ pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples;
+
+ /* reset to current bank, like "reset" command */
+ pixis_reset
+
+ /* reset board but use the to alternate flash bank */
+ pixis_reset altbank
+
+ /* reset board, use alternate flash bank with watchdog timer enabled*/
+ pixis_reset altbank wd
+
+ /* reset board to alternate bank with frequency changed.
+ * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
+ */
+ pixis-reset altbank cf 40 2.5 10
+
+Valid clock choices are in the 8641 Reference Manuals.
+
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts
+
+After placing the DTB file in your TFTP disk area,
+you can download that dtb file using a command like:
+
+ tftp 900000 mpc8544ds.dtb
+
+Burn it to flash if you want.
+
+
+Booting Linux
+-------------
+
+Place a linux uImage in the TFTP disk area too.
+
+ tftp 1000000 uImage.8544
+ tftp 900000 mpc8544ds.dtb
+ bootm 1000000 - 900000
+
+Watch your ethact, netdev and bootargs U-Boot environment variables.
+You may want to do something like this too:
+
+ setenv ethact eTSEC3
+ setenv netdev eth1
diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c
new file mode 100644
index 0000000..aa30cab
--- /dev/null
+++ b/board/freescale/mpc8544ds/ddr.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 10;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /* 2T timing enable */
+ popts->twot_en = 1;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c
new file mode 100644
index 0000000..e72a1f4
--- /dev/null
+++ b/board/freescale/mpc8544ds/law.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
new file mode 100644
index 0000000..66fb228
--- /dev/null
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -0,0 +1,320 @@
+/*
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <netdev.h>
+
+#include "../common/sgmii_riser.h"
+
+int checkboard (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ u8 vboot;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ if ((uint)&gur->porpllsr != 0xe00e0000) {
+ printf("immap size error %lx\n",(ulong)&gur->porpllsr);
+ }
+ printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+ in_8(pixis_base + PIXIS_PVER));
+
+ vboot = in_8(pixis_base + PIXIS_VBOOT);
+ if (vboot & PIXIS_VBOOT_FMAP)
+ printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
+ else
+ puts ("Promjet\n");
+
+ lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
+ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
+ ecm->eedr = 0xffffffff; /* Clear ecm errors */
+ ecm->eeer = 0xffffffff; /* Enable ecm errors */
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
+
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+void pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct fsl_pci_info pci_info;
+ u32 devdisr, pordevsr, io_sel;
+ u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+ int first_free_busno = 0;
+
+ int pcie_ep, pcie_configured;
+
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ porpllsr = in_be32(&gur->porpllsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
+
+ puts("\n");
+
+#ifdef CONFIG_PCIE3
+ pcie_configured = is_serdes_configured(PCIE3);
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+ /* contains both PCIE3 MEM & IO space */
+ set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
+ LAW_TRGT_IF_PCIE_3);
+ SET_STD_PCIE_INFO(pci_info, 3);
+ pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
+
+ /* outbound memory */
+ pci_set_region(&pcie3_hose.regions[0],
+ CONFIG_SYS_PCIE3_MEM_BUS2,
+ CONFIG_SYS_PCIE3_MEM_PHYS2,
+ CONFIG_SYS_PCIE3_MEM_SIZE2,
+ PCI_REGION_MEM);
+
+ pcie3_hose.region_count = 1;
+
+ printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info.regs);
+ first_free_busno = fsl_pci_init_port(&pci_info,
+ &pcie3_hose, first_free_busno);
+
+ /*
+ * Activate ULI1575 legacy chip by performing a fake
+ * memory access. Needed to make ULI RTC work.
+ */
+ in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
+ } else {
+ printf("PCIE3: disabled\n");
+ }
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE1
+ SET_STD_PCIE_INFO(pci_info, 1);
+ first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
+#else
+ setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE2
+ SET_STD_PCIE_INFO(pci_info, 2);
+ first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
+#else
+ setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
+#endif
+
+#ifdef CONFIG_PCI1
+ pci_speed = 66666000;
+ pci_32 = 1;
+ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info, 1);
+ set_next_law(pci_info.mem_phys,
+ law_size_bits(pci_info.mem_size), pci_info.law);
+ set_next_law(pci_info.io_phys,
+ law_size_bits(pci_info.io_size), pci_info.law);
+
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+ printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter",
+ pci_info.regs);
+
+ first_free_busno = fsl_pci_init_port(&pci_info,
+ &pci1_hose, first_free_busno);
+ } else {
+ printf("PCI: disabled\n");
+ }
+
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
+#endif
+}
+
+int last_stage_init(void)
+{
+ return 0;
+}
+
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+ u8 i, go_bit, rd_clks;
+ ulong val = 0;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ go_bit = in_8(pixis_base + PIXIS_VCTL);
+ go_bit &= 0x01;
+
+ rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
+ rd_clks &= 0x1C;
+
+ /*
+ * Only if both go bit and the SCLK bit in VCFGEN0 are set
+ * should we be using the AUX register. Remember, we also set the
+ * GO bit to boot from the alternate bank on the on-board flash
+ */
+
+ if (go_bit) {
+ if (rd_clks == 0x1c)
+ i = in_8(pixis_base + PIXIS_AUX);
+ else
+ i = in_8(pixis_base + PIXIS_SPD);
+ } else {
+ i = in_8(pixis_base + PIXIS_SPD);
+ }
+
+ i &= 0x07;
+
+ switch (i) {
+ case 0:
+ val = 33333333;
+ break;
+ case 1:
+ val = 40000000;
+ break;
+ case 2:
+ val = 50000000;
+ break;
+ case 3:
+ val = 66666666;
+ break;
+ case 4:
+ val = 83000000;
+ break;
+ case 5:
+ val = 100000000;
+ break;
+ case 6:
+ val = 133333333;
+ break;
+ case 7:
+ val = 166666666;
+ break;
+ }
+
+ return val;
+}
+
+
+#define MIIM_CIS8204_SLED_CON 0x1b
+#define MIIM_CIS8204_SLEDCON_INIT 0x1115
+/*
+ * Hack to write all 4 PHYs with the LED values
+ */
+int board_phy_config(struct phy_device *phydev)
+{
+ static int do_once;
+ uint phyid;
+ struct mii_dev *bus = phydev->bus;
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ if (do_once)
+ return 0;
+
+ for (phyid = 0; phyid < 4; phyid++)
+ bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
+ MIIM_CIS8204_SLEDCON_INIT);
+
+ do_once = 1;
+
+ return 0;
+}
+
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_TSEC_ENET
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[2];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ if (is_serdes_configured(SGMII_TSEC1)) {
+ puts("eTSEC1 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ if (is_serdes_configured(SGMII_TSEC3)) {
+ puts("eTSEC3 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+
+ return 0;
+ }
+
+ if (is_serdes_configured(SGMII_TSEC1) ||
+ is_serdes_configured(SGMII_TSEC3)) {
+ fsl_sgmii_riser_init(tsec_info, num);
+ }
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+#endif
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_fdt_fixup(blob);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c
new file mode 100644
index 0000000..24aa4ec
--- /dev/null
+++ b/board/freescale/mpc8544ds/tlb.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ /*
+ * TLB 0: 64M Non-cacheable, guarded
+ * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_64M, 1),
+ /*
+ * TLB 1: 1G Non-cacheable, guarded
+ * 0x80000000 1G PCIE 8,9,a,b
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1G, 1),
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 4: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe100_0000 255M PCI IO range
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig
new file mode 100644
index 0000000..09f3b0b
--- /dev/null
+++ b/board/freescale/mpc8548cds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8548CDS
+
+config SYS_BOARD
+ default "mpc8548cds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8548CDS"
+
+endif
diff --git a/board/freescale/mpc8548cds/MAINTAINERS b/board/freescale/mpc8548cds/MAINTAINERS
new file mode 100644
index 0000000..6f22922
--- /dev/null
+++ b/board/freescale/mpc8548cds/MAINTAINERS
@@ -0,0 +1,8 @@
+MPC8548CDS BOARD
+#M: -
+S: Maintained
+F: board/freescale/mpc8548cds/
+F: include/configs/MPC8548CDS.h
+F: configs/MPC8548CDS_defconfig
+F: configs/MPC8548CDS_36BIT_defconfig
+F: configs/MPC8548CDS_legacy_defconfig
diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile
new file mode 100644
index 0000000..f797df2
--- /dev/null
+++ b/board/freescale/mpc8548cds/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8548cds.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c
new file mode 100644
index 0000000..b31ea34
--- /dev/null
+++ b/board/freescale/mpc8548cds/ddr.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 10;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
new file mode 100644
index 0000000..5578fc2
--- /dev/null
+++ b/board/freescale/mpc8548cds/law.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ /* LBC window - maps 256M */
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
new file mode 100644
index 0000000..ca9b43c
--- /dev/null
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <fsl_mdio.h>
+#include <netdev.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+void local_bus_init(void);
+
+int checkboard (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+ /* PCI slot in USER bits CSR[6:7] by convention. */
+ uint pci_slot = get_pci_slot ();
+
+ uint cpu_board_rev = get_cpu_board_revision ();
+
+ puts("Board: MPC8548CDS");
+ printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
+ get_board_version(), pci_slot);
+ printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
+ MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+ MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ /*
+ * Hack TSEC 3 and 4 IO voltages.
+ */
+ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
+
+ ecm->eedr = 0xffffffff; /* clear ecm errors */
+ ecm->eeer = 0xffffffff; /* enable ecm errors */
+ return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ uint clkdiv;
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+
+ gur->lbiuiplldcr1 = 0x00078080;
+ if (clkdiv == 16) {
+ gur->lbiuiplldcr0 = 0x7c0f1bf0;
+ } else if (clkdiv == 8) {
+ gur->lbiuiplldcr0 = 0x6c0f1bf0;
+ } else if (clkdiv == 4) {
+ gur->lbiuiplldcr0 = 0x5c0f1bf0;
+ }
+
+ lbc->lcrr |= 0x00030000;
+
+ asm("sync;isync;msync");
+
+ lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
+ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+
+ uint idx;
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+ uint lsdmr_common;
+
+ puts("LBC SDRAM: ");
+ print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+ "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ asm("msync");
+
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * MPC8548 uses "new" 15-16 style addressing.
+ */
+ lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+ lsdmr_common |= LSDMR_BSMA1516;
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it.
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+ mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+ mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
+ {},
+};
+
+static struct pci_controller pci1_hose;
+#endif /* CONFIG_PCI */
+
+void pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct fsl_pci_info pci_info;
+ u32 devdisr, pordevsr, io_sel;
+ u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+ int first_free_busno = 0;
+ char buf[32];
+
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ porpllsr = in_be32(&gur->porpllsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
+
+#ifdef CONFIG_PCI1
+ pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+ pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
+ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info, 1);
+ set_next_law(pci_info.mem_phys,
+ law_size_bits(pci_info.mem_size), pci_info.law);
+ set_next_law(pci_info.io_phys,
+ law_size_bits(pci_info.io_size), pci_info.law);
+
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+ printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+ (pci_32) ? 32 : 64,
+ strmhz(buf, pci_speed),
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter",
+ pci_info.regs);
+
+ pci1_hose.config_table = pci_mpc85xxcds_config_table;
+ first_free_busno = fsl_pci_init_port(&pci_info,
+ &pci1_hose, first_free_busno);
+
+#ifdef CONFIG_PCIX_CHECK
+ if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
+ /* PCI-X init */
+ if (CONFIG_SYS_CLK_FREQ < 66000000)
+ printf("PCI-X will only work at 66 MHz\n");
+
+ reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
+ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+ pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
+ }
+#endif
+ } else {
+ printf("PCI1: disabled\n");
+ }
+
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
+#endif
+
+#ifdef CONFIG_PCI2
+{
+ uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
+ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
+ if (pci_dual) {
+ printf("PCI2: 32 bit, 66 MHz, %s\n",
+ pci2_clk_sel ? "sync" : "async");
+ } else {
+ printf("PCI2: disabled\n");
+ }
+}
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
+#endif /* CONFIG_PCI2 */
+
+ fsl_pcie_init_board(first_free_busno);
+}
+
+void configure_rgmii(void)
+{
+ unsigned short temp;
+
+ /* Change the resistors for the PHY */
+ /* This is needed to get the RGMII working for the 1.3+
+ * CDS cards */
+ if (get_board_version() == 0x13) {
+ miiphy_write(DEFAULT_MII_NAME,
+ TSEC1_PHY_ADDR, 29, 18);
+
+ miiphy_read(DEFAULT_MII_NAME,
+ TSEC1_PHY_ADDR, 30, &temp);
+
+ temp = (temp & 0xf03f);
+ temp |= 2 << 9; /* 36 ohm */
+ temp |= 2 << 6; /* 39 ohm */
+
+ miiphy_write(DEFAULT_MII_NAME,
+ TSEC1_PHY_ADDR, 30, temp);
+
+ miiphy_write(DEFAULT_MII_NAME,
+ TSEC1_PHY_ADDR, 29, 3);
+
+ miiphy_write(DEFAULT_MII_NAME,
+ TSEC1_PHY_ADDR, 30, 0x8000);
+ }
+
+ return;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
+ if (get_board_version() >= 0x13) {
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
+ num++;
+ }
+#endif
+#ifdef CONFIG_TSEC4
+ /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
+ if (get_board_version() >= 0x13) {
+ SET_STD_TSEC_INFO(tsec_info[num], 4);
+ tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
+ num++;
+ }
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+
+ return 0;
+ }
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+ configure_rgmii();
+
+ return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
+#endif
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
new file mode 100644
index 0000000..363e043
--- /dev/null
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /*
+ * Entry 0:
+ * FLASH(cover boot page) 16M Non-cacheable, guarded
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_16M, 1),
+
+ /*
+ * Entry 1:
+ * CCSRBAR 1M Non-cacheable, guarded
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /*
+ * Entry 2:
+ * LBC SDRAM 64M Cacheable, non-guarded
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
+ CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 2, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * Entry 3:
+ * CADMUS registers 1M Non-cacheable, guarded
+ */
+ SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1M, 1),
+
+ /*
+ * Entry 4:
+ * PCI and PCIe MEM 1G Non-cacheable, guarded
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_1G, 1),
+
+ /*
+ * Entry 5:
+ * PCI1 IO 1M Non-cacheable, guarded
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_1M, 1),
+
+ /*
+ * Entry 6:
+ * PCIe IO 1M Non-cacheable, guarded
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_1M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8555cds/Kconfig b/board/freescale/mpc8555cds/Kconfig
new file mode 100644
index 0000000..04bd572
--- /dev/null
+++ b/board/freescale/mpc8555cds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8555CDS
+
+config SYS_BOARD
+ default "mpc8555cds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8555CDS"
+
+endif
diff --git a/board/freescale/mpc8555cds/MAINTAINERS b/board/freescale/mpc8555cds/MAINTAINERS
new file mode 100644
index 0000000..1ef6690
--- /dev/null
+++ b/board/freescale/mpc8555cds/MAINTAINERS
@@ -0,0 +1,7 @@
+MPC8555CDS BOARD
+#M: Kumar Gala <kumar.gala@freescale.com>
+S: Orphan (since 2014-06)
+F: board/freescale/mpc8555cds/
+F: include/configs/MPC8555CDS.h
+F: configs/MPC8555CDS_defconfig
+F: configs/MPC8555CDS_legacy_defconfig
diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile
new file mode 100644
index 0000000..d32d005
--- /dev/null
+++ b/board/freescale/mpc8555cds/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8555cds.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c
new file mode 100644
index 0000000..d2ac6c4
--- /dev/null
+++ b/board/freescale/mpc8555cds/ddr.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 6;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 0;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c
new file mode 100644
index 0000000..39df3f1
--- /dev/null
+++ b/board/freescale/mpc8555cds/law.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
new file mode 100644
index 0000000..de5f566
--- /dev/null
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -0,0 +1,428 @@
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <fsl_ddr_sdram.h>
+#include <ioports.h>
+#include <spd_sdram.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+void local_bus_init(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+int checkboard (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ char buf[32];
+
+ /* PCI slot in USER bits CSR[6:7] by convention. */
+ uint pci_slot = get_pci_slot ();
+
+ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
+ uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
+ uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
+ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
+
+ uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+
+ uint cpu_board_rev = get_cpu_board_revision ();
+
+ printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+ get_board_version (), pci_slot);
+
+ printf ("CPU Board Revision %d.%d (0x%04x)\n",
+ MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+ MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+ printf("PCI1: %d bit, %s MHz, %s\n",
+ (pci1_32) ? 32 : 64,
+ strmhz(buf, pci1_speed),
+ pci1_clk_sel ? "sync" : "async");
+
+ if (pci_dual) {
+ printf("PCI2: 32 bit, 66 MHz, %s\n",
+ pci2_clk_sel ? "sync" : "async");
+ } else {
+ printf("PCI2: disabled\n");
+ }
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+ uint temp_lbcdll;
+
+ /*
+ * Errata LBC11.
+ * Fix Local Bus clock glitch when DLL is enabled.
+ *
+ * If localbus freq is < 66MHz, DLL bypass mode must be used.
+ * If localbus freq is > 133MHz, DLL can be safely enabled.
+ * Between 66 and 133, the DLL is enabled with an override workaround.
+ */
+
+ get_sys_info(&sysinfo);
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
+ lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
+
+ if (lbc_hz < 66) {
+ lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
+
+ } else if (lbc_hz >= 133) {
+ lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
+
+ } else {
+ lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
+ udelay(200);
+
+ /*
+ * Sample LBC DLL ctrl reg, upshift it to set the
+ * override bits.
+ */
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+ asm("sync;isync;msync");
+ }
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+
+ uint idx;
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+ uint cpu_board_rev;
+ uint lsdmr_common;
+
+ puts("LBC SDRAM: ");
+ print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+ "\n ");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ asm("msync");
+
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * Determine which address lines to use baed on CPU board rev.
+ */
+ cpu_board_rev = get_cpu_board_revision();
+ lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+ if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+ lsdmr_common |= LSDMR_BSMA1617;
+ } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+ lsdmr_common |= LSDMR_BSMA1516;
+ } else {
+ /*
+ * Assume something unable to identify itself is
+ * really old, and likely has lines 16/17 mapped.
+ */
+ lsdmr_common |= LSDMR_BSMA1617;
+ }
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#ifdef CONFIG_PCI
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+ mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+ mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
+ {},
+};
+
+
+static struct pci_controller hose[] = {
+ {
+ config_table: pci_mpc85xxcds_config_table,
+ },
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
+#endif
+};
+
+#endif
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init(hose);
+#endif
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose[0].last_busno - hose[0].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = hose[1].last_busno - hose[1].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c
new file mode 100644
index 0000000..fff3b4a
--- /dev/null
+++ b/board/freescale/mpc8555cds/tlb.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_16M, 1),
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xa0000000 256M PCI2 MEM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xb0000000 256M PCI2 MEM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ * 0xe300_0000 16M PCI2 IO
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 7: 1M Non-cacheable, guarded
+ * 0xf8000000 1M CADMUS registers
+ */
+ SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_1M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8560ads/Kconfig b/board/freescale/mpc8560ads/Kconfig
new file mode 100644
index 0000000..828c068
--- /dev/null
+++ b/board/freescale/mpc8560ads/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8560ADS
+
+config SYS_BOARD
+ default "mpc8560ads"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8560ADS"
+
+endif
diff --git a/board/freescale/mpc8560ads/MAINTAINERS b/board/freescale/mpc8560ads/MAINTAINERS
new file mode 100644
index 0000000..96e6da2
--- /dev/null
+++ b/board/freescale/mpc8560ads/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8560ADS BOARD
+#M: Kumar Gala <kumar.gala@freescale.com>
+S: Orphan (since 2014-06)
+F: board/freescale/mpc8560ads/
+F: include/configs/MPC8560ADS.h
+F: configs/MPC8560ADS_defconfig
diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile
new file mode 100644
index 0000000..685168e
--- /dev/null
+++ b/board/freescale/mpc8560ads/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8560ads.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c
new file mode 100644
index 0000000..41d4cfe
--- /dev/null
+++ b/board/freescale/mpc8560ads/ddr.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 0;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /* 2T timing enable */
+ popts->twot_en = 1;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c
new file mode 100644
index 0000000..41f2e02
--- /dev/null
+++ b/board/freescale/mpc8560ads/law.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff BCSR 1M
+ * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#endif
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ /* This is not so much the SDRAM map as it is the whole localbus map. */
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
new file mode 100644
index 0000000..f99d639
--- /dev/null
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -0,0 +1,462 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <fsl_ddr_sdram.h>
+#include <ioports.h>
+#include <spd_sdram.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_lbc.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+
+void local_bus_init(void);
+
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+
+/*
+ * MPC8560ADS Board Status & Control Registers
+ */
+typedef struct bcsr_ {
+ volatile unsigned char bcsr0;
+ volatile unsigned char bcsr1;
+ volatile unsigned char bcsr2;
+ volatile unsigned char bcsr3;
+ volatile unsigned char bcsr4;
+ volatile unsigned char bcsr5;
+} bcsr_t;
+
+void reset_phy (void)
+{
+#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
+ volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR;
+#endif
+ /* reset Giga bit Ethernet port if needed here */
+
+ /* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+ bcsr->bcsr2 &= ~FETH2_RST;
+ udelay(2);
+ bcsr->bcsr2 |= FETH2_RST;
+ udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+ bcsr->bcsr3 &= ~FETH3_RST;
+ udelay(2);
+ bcsr->bcsr3 |= FETH3_RST;
+ udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+ /* reset PHY */
+ miiphy_reset("FCC1", 0x0);
+
+ /* change PHY address to 0x02 */
+ bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
+
+ bb_miiphy_write(NULL, 0x02, MII_BMCR,
+ BMCR_ANENABLE | BMCR_ANRESTART);
+#endif /* CONFIG_MII */
+}
+
+
+int checkboard (void)
+{
+ puts("Board: ADS\n");
+
+#ifdef CONFIG_PCI
+ printf("PCI1: 32 bit, %d MHz (compiled)\n",
+ CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+ printf("PCI1: disabled\n");
+#endif
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init();
+
+ return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ /*
+ * Errata LBC11.
+ * Fix Local Bus clock glitch when DLL is enabled.
+ *
+ * If localbus freq is < 66MHz, DLL bypass mode must be used.
+ * If localbus freq is > 133MHz, DLL can be safely enabled.
+ * Between 66 and 133, the DLL is enabled with an override workaround.
+ */
+
+ get_sys_info(&sysinfo);
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
+ lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
+
+ if (lbc_hz < 66) {
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
+
+ } else if (lbc_hz >= 133) {
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
+
+ } else {
+ /*
+ * On REV1 boards, need to change CLKDIV before enable DLL.
+ * Default CLKDIV is 8, change it to 4 temporarily.
+ */
+ uint pvr = get_pvr();
+ uint temp_lbcdll = 0;
+
+ if (pvr == PVR_85xx_REV1) {
+ /* FIXME: Justify the high bit here. */
+ lbc->lcrr = 0x10000004;
+ }
+
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */
+ udelay(200);
+
+ /*
+ * Sample LBC DLL ctrl reg, upshift it to set the
+ * override bits.
+ */
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+ asm("sync;isync;msync");
+ }
+}
+
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+
+ puts("LBC SDRAM: ");
+ print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+ "\n ");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ asm("msync");
+
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ asm("sync");
+
+ /*
+ * Configure the SDRAM controller.
+ */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+phys_size_t fixed_sdram(void)
+{
+ #ifndef CONFIG_SYS_RAMBOOT
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
+
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ #if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000000D;
+ ddr->err_sbe = 0x00ff0000;
+ #endif
+ asm("sync;isync;msync");
+ udelay(500);
+ #if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
+ #else
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+ #endif
+ asm("sync; isync; msync");
+ udelay(500);
+ #endif
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+ } },
+ { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table: pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ ft_cpu_setup(blob, bd);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose.last_busno - hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c
new file mode 100644
index 0000000..d5ee791
--- /dev/null
+++ b/board/freescale/mpc8560ads/tlb.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_16M, 1),
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xc0000000 256M Rapid IO MEM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xd0000000 256M Rapid IO MEM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 7: 16K Non-cacheable, guarded
+ * 0xf8000000 16K BCSR registers
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_16K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8568mds/Kconfig b/board/freescale/mpc8568mds/Kconfig
new file mode 100644
index 0000000..4e178c5
--- /dev/null
+++ b/board/freescale/mpc8568mds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8568MDS
+
+config SYS_BOARD
+ default "mpc8568mds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8568MDS"
+
+endif
diff --git a/board/freescale/mpc8568mds/MAINTAINERS b/board/freescale/mpc8568mds/MAINTAINERS
new file mode 100644
index 0000000..379d8cc
--- /dev/null
+++ b/board/freescale/mpc8568mds/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8568MDS BOARD
+#M: -
+S: Maintained
+F: board/freescale/mpc8568mds/
+F: include/configs/MPC8568MDS.h
+F: configs/MPC8568MDS_defconfig
diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile
new file mode 100644
index 0000000..612fb51
--- /dev/null
+++ b/board/freescale/mpc8568mds/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2004-2007 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8568mds.o
+obj-y += bcsr.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c
new file mode 100644
index 0000000..4a6105c
--- /dev/null
+++ b/board/freescale/mpc8568mds/bcsr.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "bcsr.h"
+
+void enable_8568mds_duart(void)
+{
+ volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060);
+ volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070);
+ volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
+
+ *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */
+ *devices = 0; /* Enable all peripheral devices */
+ bcsr[5] |= 0x01; /* Enable Duart in BCSR*/
+}
+
+void enable_8568mds_flash_write(void)
+{
+ volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
+
+ bcsr[9] |= 0x01;
+}
+
+void disable_8568mds_flash_write(void)
+{
+ volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
+
+ bcsr[9] &= ~(0x01);
+}
+
+void enable_8568mds_qe_mdio(void)
+{
+ u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
+
+ bcsr[7] |= 0x01;
+}
+
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+void reset_8568mds_uccs(void)
+{
+ volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
+
+ /* Turn off UCC1 & UCC2 */
+ out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN);
+ out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN);
+
+ /* Mode is RGMII, all bits clear */
+ out_8(&bcsr[11], in_8(&bcsr[11]) & ~(BCSR_UCC1_MODE_MSK |
+ BCSR_UCC2_MODE_MSK));
+
+ /* Turn UCC1 & UCC2 on */
+ out_8(&bcsr[8], in_8(&bcsr[8]) | BCSR_UCC1_GETH_EN);
+ out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN);
+}
+#endif
diff --git a/board/freescale/mpc8568mds/bcsr.h b/board/freescale/mpc8568mds/bcsr.h
new file mode 100644
index 0000000..215534e
--- /dev/null
+++ b/board/freescale/mpc8568mds/bcsr.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BCSR_H_
+#define __BCSR_H_
+
+#include <common.h>
+
+/* BCSR Bit definitions
+ * BCSR 0 *
+ 0:3 ccb sys pll
+ 4:6 cfg core pll
+ 7 cfg boot seq
+
+ * BCSR 1 *
+ 0:2 cfg rom lock
+ 3:5 cfg host agent
+ 6 PCI IO
+ 7 cfg RIO size
+
+ * BCSR 2 *
+ 0:4 QE PLL
+ 5 QE clock
+ 6 cfg PCI arbiter
+
+ * BCSR 3 *
+ 0 TSEC1 reduce
+ 1 TSEC2 reduce
+ 2:3 TSEC1 protocol
+ 4:5 TSEC2 protocol
+ 6 PHY1 slave
+ 7 PHY2 slave
+
+ * BCSR 4 *
+ 4 clock enable
+ 5 boot EPROM
+ 6 GETH transactive reset
+ 7 BRD write potect
+
+ * BCSR 5 *
+ 1:3 Leds 1-3
+ 4 UPC1 enable
+ 5 UPC2 enable
+ 6 UPC2 pos
+ 7 RS232 enable
+
+ * BCSR 6 *
+ 0 CFG ver 0
+ 1 CFG ver 1
+ 6 Register config led
+ 7 Power on reset
+
+ * BCSR 7 *
+ 2 board host mode indication
+ 5 enable TSEC1 PHY
+ 6 enable TSEC2 PHY
+
+ * BCSR 8 *
+ 0 UCC GETH1 enable
+ 1 UCC GMII enable
+ 3 UCC TBI enable
+ 5 UCC MII enable
+ 7 Real time clock reset
+
+ * BCSR 9 *
+ 0 UCC2 GETH enable
+ 1 UCC2 GMII enable
+ 3 UCC2 TBI enable
+ 5 UCC2 MII enable
+ 6 Ready only - indicate flash ready after burning
+ 7 Flash write protect
+*/
+
+#define BCSR_UCC1_GETH_EN (0x1 << 7)
+#define BCSR_UCC2_GETH_EN (0x1 << 7)
+#define BCSR_UCC1_MODE_MSK (0x3 << 4)
+#define BCSR_UCC2_MODE_MSK (0x3 << 0)
+
+/*BCSR Utils functions*/
+
+void enable_8568mds_duart(void);
+void enable_8568mds_flash_write(void);
+void disable_8568mds_flash_write(void);
+void enable_8568mds_qe_mdio(void);
+
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+void reset_8568mds_uccs(void);
+#endif
+
+#endif /* __BCSR_H_ */
diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c
new file mode 100644
index 0000000..6db92ef
--- /dev/null
+++ b/board/freescale/mpc8568mds/ddr.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 6;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 10;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
new file mode 100644
index 0000000..ae06966
--- /dev/null
+++ b/board/freescale/mpc8568mds/law.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *0) 0x0000_0000 0x7fff_ffff DDR 2G
+ *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB
+ *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
+ *-) 0xe000_0000 0xe00f_ffff CCSR 1M
+ *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M
+ *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
+ *5) 0xc000_0000 0xdfff_ffff SRIO 512MB
+ *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
+ *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
+ *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
+ *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
+ *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB
+ *
+ *Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ */
+
+struct law_entry law_table[] = {
+ /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
new file mode 100644
index 0000000..a5c5d9d
--- /dev/null
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -0,0 +1,356 @@
+/*
+ * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "bcsr.h"
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* GETH1 */
+ {4, 10, 1, 0, 2}, /* TxD0 */
+ {4, 9, 1, 0, 2}, /* TxD1 */
+ {4, 8, 1, 0, 2}, /* TxD2 */
+ {4, 7, 1, 0, 2}, /* TxD3 */
+ {4, 23, 1, 0, 2}, /* TxD4 */
+ {4, 22, 1, 0, 2}, /* TxD5 */
+ {4, 21, 1, 0, 2}, /* TxD6 */
+ {4, 20, 1, 0, 2}, /* TxD7 */
+ {4, 15, 2, 0, 2}, /* RxD0 */
+ {4, 14, 2, 0, 2}, /* RxD1 */
+ {4, 13, 2, 0, 2}, /* RxD2 */
+ {4, 12, 2, 0, 2}, /* RxD3 */
+ {4, 29, 2, 0, 2}, /* RxD4 */
+ {4, 28, 2, 0, 2}, /* RxD5 */
+ {4, 27, 2, 0, 2}, /* RxD6 */
+ {4, 26, 2, 0, 2}, /* RxD7 */
+ {4, 11, 1, 0, 2}, /* TX_EN */
+ {4, 24, 1, 0, 2}, /* TX_ER */
+ {4, 16, 2, 0, 2}, /* RX_DV */
+ {4, 30, 2, 0, 2}, /* RX_ER */
+ {4, 17, 2, 0, 2}, /* RX_CLK */
+ {4, 19, 1, 0, 2}, /* GTX_CLK */
+ {1, 31, 2, 0, 3}, /* GTX125 */
+
+ /* GETH2 */
+ {5, 10, 1, 0, 2}, /* TxD0 */
+ {5, 9, 1, 0, 2}, /* TxD1 */
+ {5, 8, 1, 0, 2}, /* TxD2 */
+ {5, 7, 1, 0, 2}, /* TxD3 */
+ {5, 23, 1, 0, 2}, /* TxD4 */
+ {5, 22, 1, 0, 2}, /* TxD5 */
+ {5, 21, 1, 0, 2}, /* TxD6 */
+ {5, 20, 1, 0, 2}, /* TxD7 */
+ {5, 15, 2, 0, 2}, /* RxD0 */
+ {5, 14, 2, 0, 2}, /* RxD1 */
+ {5, 13, 2, 0, 2}, /* RxD2 */
+ {5, 12, 2, 0, 2}, /* RxD3 */
+ {5, 29, 2, 0, 2}, /* RxD4 */
+ {5, 28, 2, 0, 2}, /* RxD5 */
+ {5, 27, 2, 0, 3}, /* RxD6 */
+ {5, 26, 2, 0, 2}, /* RxD7 */
+ {5, 11, 1, 0, 2}, /* TX_EN */
+ {5, 24, 1, 0, 2}, /* TX_ER */
+ {5, 16, 2, 0, 2}, /* RX_DV */
+ {5, 30, 2, 0, 2}, /* RX_ER */
+ {5, 17, 2, 0, 2}, /* RX_CLK */
+ {5, 19, 1, 0, 2}, /* GTX_CLK */
+ {1, 31, 2, 0, 3}, /* GTX125 */
+ {4, 6, 3, 0, 2}, /* MDIO */
+ {4, 5, 1, 0, 2}, /* MDC */
+
+ /* UART1 */
+ {2, 0, 1, 0, 2}, /* UART_SOUT1 */
+ {2, 1, 1, 0, 2}, /* UART_RTS1 */
+ {2, 2, 2, 0, 2}, /* UART_CTS1 */
+ {2, 3, 2, 0, 2}, /* UART_SIN1 */
+
+ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+void local_bus_init(void);
+
+int board_early_init_f (void)
+{
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ enable_8568mds_duart();
+ enable_8568mds_flash_write();
+#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
+ reset_8568mds_uccs();
+#endif
+#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
+ enable_8568mds_qe_mdio();
+#endif
+
+#ifdef CONFIG_SYS_I2C2_OFFSET
+ /* Enable I2C2_SCL and I2C2_SDA */
+ volatile struct par_io *port_c;
+ port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
+ port_c->cpdir2 |= 0x0f000000;
+ port_c->cppar2 &= ~0x0f000000;
+ port_c->cppar2 |= 0x0a000000;
+#endif
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ printf ("Board: 8568 MDS\n");
+
+ return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ uint clkdiv;
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+
+ gur->lbiuiplldcr1 = 0x00078080;
+ if (clkdiv == 16) {
+ gur->lbiuiplldcr0 = 0x7c0f1bf0;
+ } else if (clkdiv == 8) {
+ gur->lbiuiplldcr0 = 0x6c0f1bf0;
+ } else if (clkdiv == 4) {
+ gur->lbiuiplldcr0 = 0x5c0f1bf0;
+ }
+
+ lbc->lcrr |= 0x00030000;
+
+ asm("sync;isync;msync");
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+
+ uint idx;
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+ uint lsdmr_common;
+
+ puts("LBC SDRAM: ");
+ print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
+ "\n ");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+ asm("msync");
+
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ asm("msync");
+
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * MPC8568 uses "new" 15-16 style addressing.
+ */
+ lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+ lsdmr_common |= LSDMR_BSMA1516;
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CONFIG_PCI)
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc8568mds_config_table[] = {
+ {
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ pci_cfgfunc_config_device,
+ {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
+ },
+ {}
+};
+#endif
+
+static struct pci_controller pci1_hose;
+#endif /* CONFIG_PCI */
+
+/*
+ * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
+ */
+void
+pib_init(void)
+{
+ u8 val8, orig_i2c_bus;
+ /*
+ * Assign PIB PMC2/3 to PCI bus
+ */
+
+ /*switch temporarily to I2C bus #2 */
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ val8 = 0x00;
+ i2c_write(0x23, 0x6, 1, &val8, 1);
+ i2c_write(0x23, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x23, 0x2, 1, &val8, 1);
+ i2c_write(0x23, 0x3, 1, &val8, 1);
+
+ val8 = 0x00;
+ i2c_write(0x26, 0x6, 1, &val8, 1);
+ val8 = 0x34;
+ i2c_write(0x26, 0x7, 1, &val8, 1);
+ val8 = 0xf9;
+ i2c_write(0x26, 0x2, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x26, 0x3, 1, &val8, 1);
+
+ val8 = 0x00;
+ i2c_write(0x27, 0x6, 1, &val8, 1);
+ i2c_write(0x27, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x27, 0x2, 1, &val8, 1);
+ val8 = 0xef;
+ i2c_write(0x27, 0x3, 1, &val8, 1);
+
+ asm("eieio");
+ i2c_set_bus_num(orig_i2c_bus);
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int first_free_busno = 0;
+#ifdef CONFIG_PCI1
+ struct fsl_pci_info pci_info;
+ u32 devdisr, pordevsr, io_sel;
+ u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ porpllsr = in_be32(&gur->porpllsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
+
+ pci_speed = 66666000;
+ pci_32 = 1;
+ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info, 1);
+ set_next_law(pci_info.mem_phys,
+ law_size_bits(pci_info.mem_size), pci_info.law);
+ set_next_law(pci_info.io_phys,
+ law_size_bits(pci_info.io_size), pci_info.law);
+
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+ printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter",
+ pci_info.regs);
+
+#ifndef CONFIG_PCI_PNP
+ pci1_hose.config_table = pci_mpc8568mds_config_table;
+#endif
+ first_free_busno = fsl_pci_init_port(&pci_info,
+ &pci1_hose, first_free_busno);
+ } else {
+ printf("PCI: disabled\n");
+ }
+
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
+#endif
+
+ fsl_pcie_init_board(first_free_busno);
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ FT_FSL_PCI_SETUP;
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c
new file mode 100644
index 0000000..b5e2fec
--- /dev/null
+++ b/board/freescale/mpc8568mds/tlb.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 Initializations */
+ /*
+ * TLBe 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH (upper half)
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_16M, 1),
+
+ /*
+ * TLBe 1: 16M Non-cacheable, guarded
+ * 0xfe000000 16M FLASH (lower half)
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /*
+ * TLBe 2: 1G Non-cacheable, guarded
+ * 0x80000000 512M PCI1 MEM
+ * 0xa0000000 512M PCIe MEM
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1G, 1),
+
+ /*
+ * TLBe 3: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 8M PCI1 IO
+ * 0xe280_0000 8M PCIe IO
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLBe 4: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 4, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLBe 5: 256K Non-cacheable, guarded
+ * 0xf8000000 32K BCSR
+ * 0xf8008000 32K PIB (CS4)
+ * 0xf8010000 32K PIB (CS5)
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8569mds/Kconfig b/board/freescale/mpc8569mds/Kconfig
new file mode 100644
index 0000000..4871857
--- /dev/null
+++ b/board/freescale/mpc8569mds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8569MDS
+
+config SYS_BOARD
+ default "mpc8569mds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8569MDS"
+
+endif
diff --git a/board/freescale/mpc8569mds/MAINTAINERS b/board/freescale/mpc8569mds/MAINTAINERS
new file mode 100644
index 0000000..c181407
--- /dev/null
+++ b/board/freescale/mpc8569mds/MAINTAINERS
@@ -0,0 +1,7 @@
+MPC8569MDS BOARD
+#M: -
+S: Maintained
+F: board/freescale/mpc8569mds/
+F: include/configs/MPC8569MDS.h
+F: configs/MPC8569MDS_defconfig
+F: configs/MPC8569MDS_ATM_defconfig
diff --git a/board/freescale/mpc8569mds/Makefile b/board/freescale/mpc8569mds/Makefile
new file mode 100644
index 0000000..5f6e021
--- /dev/null
+++ b/board/freescale/mpc8569mds/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2004-2009 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8569mds.o
+obj-y += bcsr.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/mpc8569mds/README b/board/freescale/mpc8569mds/README
new file mode 100644
index 0000000..3d12a96
--- /dev/null
+++ b/board/freescale/mpc8569mds/README
@@ -0,0 +1,77 @@
+Overview
+--------
+MPC8569MDS is composed of two boards - PB (Processor Board) and PIB (Platform
+I/O Board). The mpc8569 PowerTM processor is mounted on PB board.
+
+Building U-boot
+-----------
+ make MPC8569MDS_config
+ make
+
+Memory Map
+----------
+0x0000_0000 0x7fff_ffff DDR 2G
+0xa000_0000 0xbfff_ffff PCIe MEM 512MB
+0xe000_0000 0xe00f_ffff CCSRBAR 1M
+0xe280_0000 0xe2ff_ffff PCIe I/O 8M
+0xc000_0000 0xdfff_ffff SRIO 512MB
+0xf000_0000 0xf3ff_ffff SDRAM 64MB
+0xf800_0000 0xf800_7fff BCSR 32KB
+0xf800_8000 0xf800_ffff PIB (CS4) 32KB
+0xf801_0000 0xf801_7fff PIB (CS5) 32KB
+0xfe00_0000 0xffff_ffff Flash 32MB
+
+
+Flashing u-boot Images
+---------------
+
+Use the following commands to program u-boot image into flash:
+
+ => tftp 1000000 u-boot.bin
+ => protect off all
+ => erase fff80000 ffffffff
+ => cp.b 1000000 fff80000 80000
+
+
+Setting the correct MAC addresses
+-----------------------
+The command - "mac", is introduced to set on-board system EEPROM in the format
+defined in board/freescale/common/sys_eeprom.c. we must set all 8 MAC
+addresses for the MPC8569MDS's 8 Ethernet ports and save it by "mac save" when
+we first get the board. The commands are as follows:
+ => mac i NXID /* Set NXID to this EEPROM */
+ => mac e 01 /* Set Errata, this value is not defined by hardware
+ designer, we can set whatever we want */
+ => mac n a0 /* Set Serial Number. This is not defined by hardware
+ designer, we can set whatever we want */
+ => mac date 090512080000 /* Set the date in YYMMDDhhmmss format */
+
+ => mac p 8 /* Set the number of mac ports, it should be 8 */
+ => mac 0 xx:xx:xx:xx:xx:xx /* xx:xx:xx:xx:xx:xx should be the real mac
+ address, you can refer to the value on
+ the sticker of the rear side of the board
+ */
+ .....
+ => mac 7 xx:xx:xx:xx:xx:xx
+ => mac read
+ => mac save
+
+After resetting the board, the ethxaddrs will be filled with the mac addresses
+if such environment variables are blank(never been set before). If the ethxaddr
+has been set but we want to update it, we can use the following commands:
+ => setenv ethxaddr /* x = "none",1,2,3,4,5,6,7 */
+ => save
+ => reset
+
+
+Programming the ucode to flash
+---------------------------------
+MPC8569 doesn't have ROM in QE, so we must upload the microcode(ucode) to QE's
+IRAM so that the QE can work. The ucode binary can be downloaded from
+http://opensource.freescale.com/firmware/, and it must be programmed to
+the address 0xfff0000 in the flash. Otherwise, the QE can't work and uboot
+hangs at "Net:"
+
+
+Please note the above two steps(setting mac addresses and programming ucode) are
+very important to get the board booting up and working properly.
diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c
new file mode 100644
index 0000000..178d9f8
--- /dev/null
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "bcsr.h"
+
+void enable_8569mds_flash_write(void)
+{
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
+}
+
+void disable_8569mds_flash_write(void)
+{
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
+}
+
+void enable_8569mds_qe_uec(void)
+{
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
+ BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
+ BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+ BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+ BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+ /* Set UCC1-4 working at RMII mode */
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
+ BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
+ BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+ BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+ BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
+#endif
+}
+
+void disable_8569mds_brd_eeprom_write_protect(void)
+{
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
+}
diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h
new file mode 100644
index 0000000..6f4d139
--- /dev/null
+++ b/board/freescale/mpc8569mds/bcsr.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BCSR_H_
+#define __BCSR_H_
+
+#include <common.h>
+
+/* BCSR Bit definitions*/
+/****************************************/
+/* BCSR defines */
+/****************************************/
+#define BCSR6_UPC1_EN 0x80
+#define BCSR6_UPC1_POS_EN 0x40
+#define BCSR6_UPC1_ADDR_EN 0x20
+#define BCSR6_UPC1_DEV2 0x10
+#define BCSR6_SD_CARD_1BIT 0x08
+#define BCSR6_SD_CARD_4BITS 0x04
+#define BCSR6_TDM2G_EN 0x02
+#define BCSR6_UCC7_RMII_EN 0x01
+
+#define BCSR7_UCC1_GETH_EN 0x80
+#define BCSR7_UCC1_RGMII_EN 0x40
+#define BCSR7_UCC1_RTBI_EN 0x20
+#define BCSR7_GETHRST_MRVL 0x04
+#define BCSR7_BRD_WRT_PROTECT 0x02
+
+#define BCSR8_UCC2_GETH_EN 0x80
+#define BCSR8_UCC2_RGMII_EN 0x40
+#define BCSR8_UCC2_RTBI_EN 0x20
+#define BCSR8_UEM_MARVEL_RESET 0x02
+
+#define BCSR9_UCC3_GETH_EN 0x80
+#define BCSR9_UCC3_RGMII_EN 0x40
+#define BCSR9_UCC3_RTBI_EN 0x20
+#define BCSR9_UCC3_RMII_EN 0x10
+#define BCSR9_UCC3_UEM_MICREL 0x01
+
+#define BCSR10_UCC4_GETH_EN 0x80
+#define BCSR10_UCC4_RGMII_EN 0x40
+#define BCSR10_UCC4_RTBI_EN 0x20
+
+#define BCSR11_LED0 0x40
+#define BCSR11_LED1 0x20
+#define BCSR11_LED2 0x10
+
+#define BCSR12_UCC6_RMII_EN 0x20
+#define BCSR12_UCC8_RMII_EN 0x20
+
+#define BCSR15_SMII6_DIS 0x08
+#define BCSR15_SMII8_DIS 0x04
+#define BCSR15_QEUART_EN 0x01
+
+#define BCSR16_UPC1_DEV2 0x02
+
+#define BCSR17_nUSBEN 0x80
+#define BCSR17_nUSBLOWSPD 0x40
+#define BCSR17_USBVCC 0x20
+#define BCSR17_USBMODE 0x10
+#define BCSR17_FLASH_nWP 0x01
+
+/*BCSR Utils functions*/
+
+void enable_8569mds_flash_write(void);
+void disable_8569mds_flash_write(void);
+void enable_8569mds_qe_uec(void);
+void disable_8569mds_brd_eeprom_write_protect(void);
+
+#endif /* __BCSR_H_ */
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
new file mode 100644
index 0000000..ef404b1
--- /dev/null
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 4;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 0xff;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 2;
+
+ /*
+ * Enable half drive strength
+ */
+ popts->half_strength_driver_enable = 1;
+
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xa;
+ popts->wrlvl_start = 0x4;
+
+ /* Rtt and Rtt_W override */
+ popts->rtt_override = 1;
+ popts->rtt_override_value = DDR3_RTT_60_OHM;
+ popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
+}
diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c
new file mode 100644
index 0000000..a388ad1
--- /dev/null
+++ b/board/freescale/mpc8569mds/law.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *0) 0x0000_0000 0x7fff_ffff DDR 2G
+ *1) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
+ *-) 0xe000_0000 0xe00f_ffff CCSR 1M
+ *2) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
+ *3) 0xc000_0000 0xdfff_ffff SRIO 512MB
+ *4.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
+ *4.b) 0xf800_0000 0xf800_7fff BCSR 32KB
+ *4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
+ *4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
+ *4.e) 0xfe00_0000 0xffff_ffff Flash 32MB
+ *
+ *Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
+#endif
+ SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
new file mode 100644
index 0000000..836578f
--- /dev/null
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -0,0 +1,585 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <phy.h>
+
+#include "bcsr.h"
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
+#endif
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {2, 31, 1, 0, 1}, /* QE_MUX_MDC */
+
+ /* QE_MUX_MDIO */
+ {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
+
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+ /* UCC_1_RGMII */
+ {2, 11, 2, 0, 1}, /* CLK12 */
+ {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
+ {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
+ {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
+ {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
+
+ /* UCC_2_RGMII */
+ {2, 16, 2, 0, 3}, /* CLK17 */
+ {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
+ {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
+ {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
+ {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
+ {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
+ {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
+ {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
+ {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
+ {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
+ {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
+ {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
+ {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
+
+ /* UCC_3_RGMII */
+ {2, 11, 2, 0, 1}, /* CLK12 */
+ {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
+ {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
+ {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
+ {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
+ {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
+ {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
+ {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
+ {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
+ {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
+ {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
+ {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
+ {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
+
+ /* UCC_4_RGMII */
+ {2, 16, 2, 0, 3}, /* CLK17 */
+ {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
+ {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
+ {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
+ {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
+ {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
+ {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
+ {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
+ {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
+ {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
+ {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
+ {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
+ {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
+
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+ /* UCC_1_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
+ {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
+
+ /* UCC_2_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
+ {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
+ {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
+ {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
+ {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
+ {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
+
+ /* UCC_3_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
+ {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
+ {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
+ {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
+ {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
+ {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
+
+ /* UCC_4_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
+ {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
+ {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
+ {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
+ {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
+ {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
+#endif
+
+ /* UART1 is muxed with QE PortF bit [9-12].*/
+ {5, 12, 2, 0, 3}, /* UART1_SIN */
+ {5, 9, 1, 0, 3}, /* UART1_SOUT */
+ {5, 10, 2, 0, 3}, /* UART1_CTS_B */
+ {5, 11, 1, 0, 2}, /* UART1_RTS_B */
+
+ /* QE UART */
+ {0, 19, 1, 0, 2}, /* QEUART_TX */
+ {1, 17, 2, 0, 3}, /* QEUART_RX */
+ {0, 25, 1, 0, 1}, /* QEUART_RTS */
+ {1, 23, 2, 0, 1}, /* QEUART_CTS */
+
+ /* QE USB */
+ {5, 3, 1, 0, 1}, /* USB_OE */
+ {5, 4, 1, 0, 2}, /* USB_TP */
+ {5, 5, 1, 0, 2}, /* USB_TN */
+ {5, 6, 2, 0, 2}, /* USB_RP */
+ {5, 7, 2, 0, 1}, /* USB_RX */
+ {5, 8, 2, 0, 1}, /* USB_RN */
+ {2, 4, 2, 0, 2}, /* CLK5 */
+
+ /* SPI Flash, M25P40 */
+ {4, 27, 3, 0, 1}, /* SPI_MOSI */
+ {4, 28, 3, 0, 1}, /* SPI_MISO */
+ {4, 29, 3, 0, 1}, /* SPI_CLK */
+ {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+
+void local_bus_init(void);
+
+int board_early_init_f (void)
+{
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ enable_8569mds_flash_write();
+
+#ifdef CONFIG_QE
+ enable_8569mds_qe_uec();
+#endif
+
+#if CONFIG_SYS_I2C2_OFFSET
+ /* Enable I2C2 signals instead of SD signals */
+ volatile struct ccsr_gur *gur;
+ gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
+ gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
+ gur->plppar1 |= PLPPAR1_I2C2_VAL;
+ gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
+ gur->plpdir1 |= PLPDIR1_I2C2_VAL;
+
+ disable_8569mds_brd_eeprom_write_protect();
+#endif
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
+ const u8 flash_esel = 0;
+
+ /*
+ * Remap Boot flash to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, /* ts, esel */
+ BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ printf ("Board: 8569 MDS\n");
+
+ return 0;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+phys_size_t fixed_sdram(void)
+{
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+ uint d_init;
+
+ out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+ out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+ out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+ out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+ out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
+ out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
+ out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
+ out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
+ out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
+ out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+ out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
+ out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
+ out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
+ out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
+ out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
+#if defined (CONFIG_DDR_ECC)
+ out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
+ out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
+ out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
+#endif
+ udelay(500);
+
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ d_init = 1;
+ debug("DDR - 1st controller: memory initializing\n");
+ /*
+ * Poll until memory is initialized.
+ * 512 Meg at 400 might hit this 200 times or so.
+ */
+ while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+ udelay(1000);
+ }
+ debug("DDR: memory initialized\n\n");
+ udelay(500);
+#endif
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ uint clkdiv;
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+
+ out_be32(&gur->lbiuiplldcr1, 0x00078080);
+ if (clkdiv == 16)
+ out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
+ else if (clkdiv == 8)
+ out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
+ else if (clkdiv == 4)
+ out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
+
+ out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
+}
+
+static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
+{
+ const char *status = "disabled";
+ int off;
+ int err;
+
+ off = fdt_path_offset(blob, alias);
+ if (off < 0) {
+ printf("WARNING: could not find %s alias: %s.\n", alias,
+ fdt_strerror(off));
+ return;
+ }
+
+ err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
+ if (err) {
+ printf("WARNING: could not set status for serial0: %s.\n",
+ fdt_strerror(err));
+ return;
+ }
+}
+
+/*
+ * Because of an erratum in prototype boards it is impossible to use eSDHC
+ * without disabling UART0 (which makes it quite easy to 'brick' the board
+ * by simply issung 'setenv hwconfig esdhc', and not able to interact with
+ * U-Boot anylonger).
+ *
+ * So, but default we assume that the board is a prototype, which is a most
+ * safe assumption. There is no way to determine board revision from a
+ * register, so we use hwconfig.
+ */
+
+static int prototype_board(void)
+{
+ if (hwconfig_subarg("board", "rev", NULL))
+ return hwconfig_subarg_cmp("board", "rev", "prototype");
+ return 1;
+}
+
+static int esdhc_disables_uart0(void)
+{
+ return prototype_board() ||
+ hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
+}
+
+static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
+{
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
+ const char *devtype = "serial";
+ const char *compat = "ucc_uart";
+ const char *clk = "brg9";
+ u32 portnum = 0;
+ int off = -1;
+
+ if (!hwconfig("qe_uart"))
+ return;
+
+ if (hwconfig("esdhc") && esdhc_disables_uart0()) {
+ printf("QE UART: won't enable with esdhc.\n");
+ return;
+ }
+
+ fdt_board_disable_serial(blob, bd, "serial1");
+
+ while (1) {
+ const u32 *idx;
+ int len;
+
+ off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
+ if (off < 0) {
+ printf("WARNING: unable to fixup device tree for "
+ "QE UART\n");
+ return;
+ }
+
+ idx = fdt_getprop(blob, off, "cell-index", &len);
+ if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
+ continue;
+ break;
+ }
+
+ fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
+ fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
+ fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
+ fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
+ fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
+
+ setbits_8(&bcsr[15], BCSR15_QEUART_EN);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+
+int board_mmc_init(bd_t *bd)
+{
+ struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
+ u8 bcsr6 = BCSR6_SD_CARD_1BIT;
+
+ if (!hwconfig("esdhc"))
+ return 0;
+
+ printf("Enabling eSDHC...\n"
+ " For eSDHC to function, I2C2 ");
+ if (esdhc_disables_uart0()) {
+ printf("and UART0 should be disabled.\n");
+ printf(" Redirecting stderr, stdout and stdin to UART1...\n");
+ console_assign(stderr, "eserial1");
+ console_assign(stdout, "eserial1");
+ console_assign(stdin, "eserial1");
+ printf("Switched to UART1 (initial log has been printed to "
+ "UART0).\n");
+
+ clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
+ PLPPAR1_ESDHC_4BITS_VAL);
+ clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
+ PLPDIR1_ESDHC_4BITS_VAL);
+ bcsr6 |= BCSR6_SD_CARD_4BITS;
+ } else {
+ printf("should be disabled.\n");
+ }
+
+ /* Assign I2C2 signals to eSDHC. */
+ clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
+ PLPPAR1_ESDHC_VAL);
+ clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
+ PLPDIR1_ESDHC_VAL);
+
+ /* Mux I2C2 (and optionally UART0) signals to eSDHC. */
+ setbits_8(&bcsr[6], bcsr6);
+
+ return fsl_esdhc_mmc_init(bd);
+}
+
+static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
+{
+ const char *status = "disabled";
+ int off = -1;
+
+ if (!hwconfig("esdhc"))
+ return;
+
+ if (esdhc_disables_uart0())
+ fdt_board_disable_serial(blob, bd, "serial0");
+
+ while (1) {
+ const u32 *idx;
+ int len;
+
+ off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
+ if (off < 0)
+ break;
+
+ idx = fdt_getprop(blob, off, "cell-index", &len);
+ if (!idx || len != sizeof(*idx))
+ continue;
+
+ if (*idx == 1) {
+ fdt_setprop(blob, off, "status", status,
+ strlen(status) + 1);
+ break;
+ }
+ }
+
+ if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
+ if (off < 0) {
+ printf("WARNING: could not find esdhc node\n");
+ return;
+ }
+ fdt_delprop(blob, off, "sdhci,1-bit-only");
+ }
+}
+#else
+static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
+#endif
+
+static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
+{
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
+
+ if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
+ clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
+ else
+ setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
+
+ if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
+ clrbits_8(&bcsr[17], BCSR17_USBVCC);
+ clrbits_8(&bcsr[17], BCSR17_USBMODE);
+ do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
+ "peripheral", sizeof("peripheral"), 1);
+ } else {
+ setbits_8(&bcsr[17], BCSR17_USBVCC);
+ setbits_8(&bcsr[17], BCSR17_USBMODE);
+ }
+
+ clrbits_8(&bcsr[17], BCSR17_nUSBEN);
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+#if defined(CONFIG_PQ_MDS_PIB)
+ pib_init();
+#endif
+
+ fsl_pcie_init_board(0);
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#if defined(CONFIG_SYS_UCC_RMII_MODE)
+ int nodeoff, off, err;
+ unsigned int val;
+ const u32 *ph;
+ const u32 *index;
+
+ /* fixup device tree for supporting rmii mode */
+ nodeoff = -1;
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
+ "ucc_geth")) >= 0) {
+ err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
+ "clk16");
+ if (err < 0) {
+ printf("WARNING: could not set tx-clock-name %s.\n",
+ fdt_strerror(err));
+ break;
+ }
+
+ err = fdt_fixup_phy_connection(blob, nodeoff,
+ PHY_INTERFACE_MODE_RMII);
+
+ if (err < 0) {
+ printf("WARNING: could not set phy-connection-type "
+ "%s.\n", fdt_strerror(err));
+ break;
+ }
+
+ index = fdt_getprop(blob, nodeoff, "cell-index", 0);
+ if (index == NULL) {
+ printf("WARNING: could not get cell-index of ucc\n");
+ break;
+ }
+
+ ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
+ if (ph == NULL) {
+ printf("WARNING: could not get phy-handle of ucc\n");
+ break;
+ }
+
+ off = fdt_node_offset_by_phandle(blob, *ph);
+ if (off < 0) {
+ printf("WARNING: could not get phy node %s.\n",
+ fdt_strerror(err));
+ break;
+ }
+
+ val = 0x7 + *index; /* RMII phy address starts from 0x8 */
+
+ err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
+ if (err < 0) {
+ printf("WARNING: could not set reg for phy-handle "
+ "%s.\n", fdt_strerror(err));
+ break;
+ }
+ }
+#endif
+ ft_cpu_setup(blob, bd);
+
+ FT_FSL_PCI_SETUP;
+
+ fdt_board_fixup_esdhc(blob, bd);
+ fdt_board_fixup_qe_uart(blob, bd);
+ fdt_board_fixup_qe_usb(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
new file mode 100644
index 0000000..1328a58
--- /dev/null
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 Initializations */
+ /*
+ * TLBe 0: 64M write-through, guarded
+ * Out of reset this entry is only 4K.
+ * 0xfc000000 32MB NAND FLASH (CS3)
+ * 0xfe000000 32MB NOR FLASH (CS0)
+ */
+#ifdef CONFIG_NAND_SPL
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_64M, 1),
+#endif
+ /*
+ * TLBe 1: 256KB Non-cacheable, guarded
+ * 0xf8000000 32K BCSR
+ * 0xf8008000 32K PIB (CS4)
+ * 0xf8010000 32K PIB (CS5)
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_256K, 1),
+
+ /*
+ * TLBe 2: 256M Non-cacheable, guarded
+ * 0xa00000000 256M PCIe MEM (lower half)
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLBe 3: 256M Non-cacheable, guarded
+ * 0xb00000000 256M PCIe MEM (higher half)
+ */
+ SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
+ (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLBe 4: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe280_0000 8M PCIe IO
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_64M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8572ds/Kconfig b/board/freescale/mpc8572ds/Kconfig
new file mode 100644
index 0000000..38132cf
--- /dev/null
+++ b/board/freescale/mpc8572ds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8572DS
+
+config SYS_BOARD
+ default "mpc8572ds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8572DS"
+
+endif
diff --git a/board/freescale/mpc8572ds/MAINTAINERS b/board/freescale/mpc8572ds/MAINTAINERS
new file mode 100644
index 0000000..4c9b968
--- /dev/null
+++ b/board/freescale/mpc8572ds/MAINTAINERS
@@ -0,0 +1,7 @@
+MPC8572DS BOARD
+M: York Sun <yorksun@freescale.com>
+S: Maintained
+F: board/freescale/mpc8572ds/
+F: include/configs/MPC8572DS.h
+F: configs/MPC8572DS_defconfig
+F: configs/MPC8572DS_36BIT_defconfig
diff --git a/board/freescale/mpc8572ds/Makefile b/board/freescale/mpc8572ds/Makefile
new file mode 100644
index 0000000..902c900
--- /dev/null
+++ b/board/freescale/mpc8572ds/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8572ds.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/mpc8572ds/README b/board/freescale/mpc8572ds/README
new file mode 100644
index 0000000..57fd2ad
--- /dev/null
+++ b/board/freescale/mpc8572ds/README
@@ -0,0 +1,166 @@
+Overview
+--------
+MPC8572DS is a high-performance computing, evaluation and development platform
+supporting the mpc8572 PowerTM processor.
+
+Building U-boot
+-----------
+ make MPC8572DS_config
+ make
+
+Flash Banks
+-----------
+MPC8572DS board has two flash banks. They are both present on boot, but their
+locations can be swapped using the dip-switch SW9[1:2].
+
+Booting is always from the boot bank at 0xec00_0000.
+
+
+Memory Map
+----------
+
+0xe800_0000 - 0xebff_ffff Alternate bank 64MB
+0xec00_0000 - 0xefff_ffff Boot bank 64MB
+
+0xebf8_0000 - 0xebff_ffff Alternate u-boot address 512KB
+0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB
+
+
+Flashing Images
+---------------
+
+To place a new u-boot image in the alternate flash bank and then reset with that
+ new image temporarily, use this:
+
+ tftp 1000000 u-boot.bin
+ erase ebf80000 ebffffff
+ cp.b 1000000 ebf80000 80000
+ pixis_reset altbank
+
+
+To program the image in the boot flash bank:
+
+ tftp 1000000 u-boot.bin
+ protect off all
+ erase eff80000 ffffffff
+ cp.b 1000000 eff80000 80000
+
+
+The pixis_reset command
+-----------------------
+The command - "pixis_reset", is introduced to reset mpc8572ds board
+using the FPGA sequencer. When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+ pixis_reset
+ pixis_reset altbank
+ pixis_reset altbank wd
+ pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+ pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples:
+
+ /* reset to current bank, like "reset" command */
+ pixis_reset
+
+ /* reset board but use the to alternate flash bank */
+ pixis_reset altbank
+
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts
+
+
+Booting Linux
+-------------
+
+Place a linux uImage in the TFTP disk area.
+
+ tftp 1000000 uImage.8572
+ tftp c00000 mpc8572ds.dtb
+ bootm 1000000 - c00000
+
+
+Implementing AMP(Asymmetric MultiProcessing)
+-------------
+1. Build kernel image for core0:
+
+ a. $ make 85xx/mpc8572_ds_defconfig
+
+ b. $ make menuconfig
+ - un-select "Processor support"->"Symetric multi-processing support"
+
+ c. $ make uImage
+
+ d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
+
+2. Build kernel image for core1:
+
+ a. $ make 85xx/mpc8572_ds_defconfig
+
+ b. $ make menuconfig
+ - Un-select "Processor support"->"Symetric multi-processing support"
+ - Select "Advanced setup" -> " Prompt for advanced kernel
+ configuration options"
+ - Select "Set physical address where the kernel is loaded" and
+ set it to 0x20000000, assuming core1 will start from 512MB.
+ - Select "Set custom page offset address"
+ - Select "Set custom kernel base address"
+ - Select "Set maximum low memory"
+ - "Exit" and save the selection.
+
+ c. $ make uImage
+
+ d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
+
+3. Create dtb for core0:
+
+ $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
+
+4. Create dtb for core1:
+
+ $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
+
+5. Bring up two cores separately:
+
+ a. Power on the board, under u-boot prompt:
+ => setenv <serverip>
+ => setenv <ipaddr>
+ => setenv bootargs root=/dev/ram rw console=ttyS0,115200
+ b. Bring up core1's kernel first:
+ => setenv bootm_low 0x20000000
+ => setenv bootm_size 0x10000000
+ => tftp 21000000 8572/uImage.core1
+ => tftp 22000000 8572/ramdiskfile
+ => tftp 20c00000 8572/mpc8572ds_core1.dtb
+ => interrupts off
+ => bootm start 21000000 22000000 20c00000
+ => bootm loados
+ => bootm ramdisk
+ => bootm fdt
+ => fdt boardsetup
+ => fdt chosen $initrd_start $initrd_end
+ => bootm prep
+ => cpu 1 release $bootm_low - $fdtaddr -
+ c. Bring up core0's kernel(on the same u-boot console):
+ => setenv bootm_low 0
+ => setenv bootm_size 0x20000000
+ => tftp 1000000 8572/uImage.core0
+ => tftp 2000000 8572/ramdiskfile
+ => tftp c00000 8572/mpc8572ds_core0.dtb
+ => bootm 1000000 2000000 c00000
+
+Please note only core0 will run u-boot, core1 starts kernel directly after
+"cpu release" command is issued.
diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
new file mode 100644
index 0000000..2bfc1a1
--- /dev/null
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ *
+ * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
+ * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
+ * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
+ * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
+ * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
+ *
+ * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
+ */
+ {2, 333, 8, 7, 5, 0},
+ {2, 400, 8, 9, 5, 0},
+ {2, 549, 8, 11, 5, 0},
+ {2, 680, 8, 10, 5, 0},
+ {2, 850, 8, 12, 5, 1},
+ {1, 333, 6, 7, 3, 0},
+ {1, 400, 6, 9, 3, 0},
+ {1, 549, 6, 11, 3, 0},
+ {1, 680, 1, 10, 5, 0},
+ {1, 850, 1, 12, 5, 0},
+ {}
+};
+
+static const struct board_specific_parameters udimm1[] = {
+ /*
+ * memory controller 1
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
+ */
+ {2, 333, 8, 7, 5, 0},
+ {2, 400, 8, 9, 5, 0},
+ {2, 549, 8, 11, 5, 0},
+ {2, 680, 8, 11, 5, 0},
+ {2, 850, 8, 13, 5, 1},
+ {1, 333, 6, 7, 3, 0},
+ {1, 400, 6, 9, 3, 0},
+ {1, 549, 6, 11, 3, 0},
+ {1, 680, 1, 11, 6, 0},
+ {1, 850, 1, 13, 6, 0},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+ udimm1,
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
+ */
+ {2, 333, 4, 7, 3, 0},
+ {2, 400, 4, 9, 3, 0},
+ {2, 549, 4, 11, 3, 0},
+ {2, 680, 4, 10, 3, 0},
+ {2, 850, 4, 12, 3, 1},
+ {}
+};
+
+static const struct board_specific_parameters rdimm1[] = {
+ /*
+ * memory controller 1
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
+ */
+ {2, 333, 4, 7, 3, 0},
+ {2, 400, 4, 9, 3, 0},
+ {2, 549, 4, 11, 3, 0},
+ {2, 680, 4, 11, 3, 0},
+ {2, 850, 4, 13, 3, 1},
+ {}
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+ rdimm1,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[ctrl_num];
+ else
+ pbsp = udimms[ctrl_num];
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->twot_en = pbsp->force_2t;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay = pbsp->write_data_delay;
+ popts->twot_en = pbsp->force_2t;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+
+found:
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c
new file mode 100644
index 0000000..ab44add
--- /dev/null
+++ b/board/freescale/mpc8572ds/law.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2008, 2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
new file mode 100644
index 0000000..3f68cf4
--- /dev/null
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <fsl_mdio.h>
+#include <netdev.h>
+
+#include "../common/sgmii_riser.h"
+
+int checkboard (void)
+{
+ u8 vboot;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ printf("Board: MPC8572DS Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+ in_8(pixis_base + PIXIS_PVER));
+
+ vboot = in_8(pixis_base + PIXIS_VBOOT);
+ switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
+ case PIXIS_VBOOT_LBMAP_NOR0:
+ puts ("vBank: 0\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_PJET:
+ puts ("Promjet\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_NAND:
+ puts ("NAND\n");
+ break;
+ case PIXIS_VBOOT_LBMAP_NOR1:
+ puts ("vBank: 1\n");
+ break;
+ }
+
+ return 0;
+}
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram (void)
+{
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
+ uint d_init;
+
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+
+ ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+ ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+ ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
+
+#if defined (CONFIG_DDR_ECC)
+ ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
+ ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
+ ddr->err_sbe = CONFIG_SYS_DDR_SBE;
+#endif
+ asm("sync;isync");
+
+ udelay(500);
+
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ d_init = 1;
+ debug("DDR - 1st controller: memory initializing\n");
+ /*
+ * Poll until memory is initialized.
+ * 512 Meg at 400 might hit this 200 times or so.
+ */
+ while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+ udelay(1000);
+ }
+ debug("DDR: memory initialized\n\n");
+ asm("sync; isync");
+ udelay(500);
+#endif
+
+ return 512 * 1024 * 1024;
+}
+
+#endif
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ struct pci_controller *hose;
+
+ fsl_pcie_init_board(0);
+
+ hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
+
+ if (hose) {
+ u32 temp32;
+ u8 uli_busno = hose->first_busno + 2;
+
+ /*
+ * Activate ULI1575 legacy chip by performing a fake
+ * memory access. Needed to make ULI RTC work.
+ * Device 1d has the first on-board memory BAR.
+ */
+ pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
+ PCI_BASE_ADDRESS_1, &temp32);
+
+ if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
+ void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
+ temp32, 4, 0);
+ debug(" uli1572 read to %p\n", p);
+ in_be32(p);
+ }
+ }
+}
+#endif
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
+
+ return 0;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ if (is_serdes_configured(SGMII_TSEC1)) {
+ puts("eTSEC1 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ if (is_serdes_configured(SGMII_TSEC2)) {
+ puts("eTSEC2 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ if (is_serdes_configured(SGMII_TSEC3)) {
+ puts("eTSEC3 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC4
+ SET_STD_TSEC_INFO(tsec_info[num], 4);
+ if (is_serdes_configured(SGMII_TSEC4)) {
+ puts("eTSEC4 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+
+ return 0;
+ }
+
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_init(tsec_info, num);
+#endif
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_fdt_fixup(blob);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c
new file mode 100644
index 0000000..577878c
--- /dev/null
+++ b/board/freescale/mpc8572ds/tlb.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* W**G* - Flash/promjet, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_NAND_SPL
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
+
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_1M, 1),
+
+ SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_4K, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_256K, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8610hpcd/Kconfig b/board/freescale/mpc8610hpcd/Kconfig
new file mode 100644
index 0000000..8f713be
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8610HPCD
+
+config SYS_BOARD
+ default "mpc8610hpcd"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8610HPCD"
+
+endif
diff --git a/board/freescale/mpc8610hpcd/MAINTAINERS b/board/freescale/mpc8610hpcd/MAINTAINERS
new file mode 100644
index 0000000..de6ab89
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8610HPCD BOARD
+#M: -
+S: Maintained
+F: board/freescale/mpc8610hpcd/
+F: include/configs/MPC8610HPCD.h
+F: configs/MPC8610HPCD_defconfig
diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile
new file mode 100644
index 0000000..2613004
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/Makefile
@@ -0,0 +1,9 @@
+# Copyright 2007 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8610hpcd.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
+obj-y += law.o
+obj-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o
diff --git a/board/freescale/mpc8610hpcd/README b/board/freescale/mpc8610hpcd/README
new file mode 100644
index 0000000..31a9af3
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/README
@@ -0,0 +1,73 @@
+Freescale MPC8610HPCD board
+===========================
+
+
+Building U-Boot
+---------------
+
+ $ make MPC8610HPCD_config
+ Configuring for MPC8610HPCD board...
+
+ $ make
+
+
+Flashing U-Boot
+---------------
+The flash is 128M starting at 0xF800_0000.
+
+The alternate image is at 0xFBF0_0000
+The boot image is at 0xFFF0_0000.
+
+
+To Flash U-Boot into the booting bank:
+
+ tftp 1000000 u-boot.bin
+ protect off all
+ erase fff00000 +$filesize
+ cp.b 1000000 fff00000 $filesize
+
+
+To Flash U-boot into the alternate bank
+
+ tftp 1000000 u-boot.bin
+ erase fbf00000 +$filesize
+ cp.b 1000000 fbf00000 $filesize
+
+
+pixis_reset command
+-------------------
+A new command, "pixis_reset", is introduced to reset mpc8610hpcd board
+using the FPGA sequencer. When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+ pixis_reset
+ pixis_reset altbank
+ pixis_reset altbank wd
+ pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+ pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples;
+
+ /* reset to current bank, like "reset" command */
+ pixis_reset
+
+ /* reset board but use the to alternate flash bank */
+ pixis_reset altbank
+
+ /* reset board, use alternate flash bank with watchdog timer enabled*/
+ pixis_reset altbank wd
+
+ /* reset board to alternate bank with frequency changed.
+ * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
+ */
+ pixis-reset altbank cf 40 2.5 10
+
+
+DIP Switch Settings
+-------------------
+To manually switch the flash banks using the DIP switch
+settings, toggle both SW6:1 and SW6:2.
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
new file mode 100644
index 0000000..aa30cab
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/ddr.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 10;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /* 2T timing enable */
+ popts->twot_en = 1;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c
new file mode 100644
index 0000000..20b8fed
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/law.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2008,2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#if !defined(CONFIG_SPD_EEPROM)
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
+#endif
+ SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
new file mode 100644
index 0000000..95e398c
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <spd_sdram.h>
+#include <netdev.h>
+
+void sdram_init(void);
+phys_size_t fixed_sdram(void);
+int mpc8610hpcd_diu_init(void);
+
+
+/* called before any console output */
+int board_early_init_f(void)
+{
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+
+ gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u8 tmp_val, version;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ /*Do not use 8259PIC*/
+ tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
+ out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
+
+ /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
+ version = in_8(pixis_base + PIXIS_PVER);
+ if(version >= 0x07) {
+ tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
+ out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
+ }
+
+ /* Using this for DIU init before the driver in linux takes over
+ * Enable the TFP410 Encoder (I2C address 0x38)
+ */
+
+ tmp_val = 0xBF;
+ i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+ /* Verify if enabled */
+ tmp_val = 0;
+ i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+ debug("DVI Encoder Read: 0x%02x\n", tmp_val);
+
+ tmp_val = 0x10;
+ i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+ /* Verify if enabled */
+ tmp_val = 0;
+ i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+ debug("DVI Encoder Read: 0x%02x\n", tmp_val);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+ in_8(pixis_base + PIXIS_PVER));
+
+ /*
+ * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
+ * bank and LBMAP=00 is the alternate bank. However, the pixis
+ * altbank code can only set bits, not clear them, so we treat 00 as
+ * the normal bank and 11 as the alternate.
+ */
+ switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
+ case 0:
+ puts("vBank: Standard\n");
+ break;
+ case 0x40:
+ puts("Promjet\n");
+ break;
+ case 0x80:
+ puts("NAND\n");
+ break;
+ case 0xC0:
+ puts("vBank: Alternate\n");
+ break;
+ }
+
+ mcm->abcr |= 0x00010000; /* 0 */
+ mcm->hpmr3 = 0x80000008; /* 4c */
+ mcm->hpmr0 = 0;
+ mcm->hpmr1 = 0;
+ mcm->hpmr2 = 0;
+ mcm->hpmr4 = 0;
+ mcm->hpmr5 = 0;
+
+ return 0;
+}
+
+
+phys_size_t
+initdram(int board_type)
+{
+ phys_size_t dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = fsl_ddr_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+
+ setup_ddr_bat(dram_size);
+
+ debug(" DDR: ");
+ return dram_size;
+}
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram(void)
+{
+#if !defined(CONFIG_SYS_RAMBOOT)
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
+ uint d_init;
+
+ ddr->cs0_bnds = 0x0000001f;
+ ddr->cs0_config = 0x80010202;
+
+ ddr->timing_cfg_3 = 0x00000000;
+ ddr->timing_cfg_0 = 0x00260802;
+ ddr->timing_cfg_1 = 0x3935d322;
+ ddr->timing_cfg_2 = 0x14904cc8;
+ ddr->sdram_mode = 0x00480432;
+ ddr->sdram_mode_2 = 0x00000000;
+ ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
+ ddr->sdram_data_init = 0xDEADBEEF;
+ ddr->sdram_clk_cntl = 0x03800000;
+ ddr->sdram_cfg_2 = 0x04400010;
+
+#if defined(CONFIG_DDR_ECC)
+ ddr->err_int_en = 0x0000000d;
+ ddr->err_disable = 0x00000000;
+ ddr->err_sbe = 0x00010000;
+#endif
+ asm("sync;isync");
+
+ udelay(500);
+
+ ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
+
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ d_init = 1;
+ debug("DDR - 1st controller: memory initializing\n");
+ /*
+ * Poll until memory is initialized.
+ * 512 Meg at 400 might hit this 200 times or so.
+ */
+ while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
+ udelay(1000);
+
+ debug("DDR: memory initialized\n\n");
+ asm("sync; isync");
+ udelay(500);
+#endif
+
+ return 512 * 1024 * 1024;
+#endif
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+
+#endif
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_fsl86xxads_config_table[] = {
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
+ {}
+};
+#endif
+
+
+static struct pci_controller pci1_hose;
+#endif /* CONFIG_PCI */
+
+void pci_init_board(void)
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ struct fsl_pci_info pci_info;
+ u32 devdisr;
+ int first_free_busno;
+ int pci_agent;
+
+ devdisr = in_be32(&gur->devdisr);
+
+ first_free_busno = fsl_pcie_init_board(0);
+
+#ifdef CONFIG_PCI1
+ if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info, 1);
+ set_next_law(pci_info.mem_phys,
+ law_size_bits(pci_info.mem_size), pci_info.law);
+ set_next_law(pci_info.io_phys,
+ law_size_bits(pci_info.io_size), pci_info.law);
+
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+ printf("PCI: connected to PCI slots as %s" \
+ " (base address %lx)\n",
+ pci_agent ? "Agent" : "Host",
+ pci_info.regs);
+#ifndef CONFIG_PCI_PNP
+ pci1_hose.config_table = pci_mpc86xxcts_config_table;
+#endif
+ first_free_busno = fsl_pci_init_port(&pci_info,
+ &pci1_hose, first_free_busno);
+ } else {
+ printf("PCI: disabled\n");
+ }
+
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
+#endif
+
+ fsl_pcie_init_board(first_free_busno);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ FT_FSL_PCI_SETUP;
+
+ return 0;
+}
+#endif
+
+/*
+ * get_board_sys_clk
+ * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+ u8 i;
+ ulong val = 0;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ i = in_8(pixis_base + PIXIS_SPD);
+ i &= 0x07;
+
+ switch (i) {
+ case 0:
+ val = 33333000;
+ break;
+ case 1:
+ val = 39999600;
+ break;
+ case 2:
+ val = 49999500;
+ break;
+ case 3:
+ val = 66666000;
+ break;
+ case 4:
+ val = 83332500;
+ break;
+ case 5:
+ val = 99999000;
+ break;
+ case 6:
+ val = 133332000;
+ break;
+ case 7:
+ val = 166665000;
+ break;
+ }
+
+ return val;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+void board_reset(void)
+{
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ out_8(pixis_base + PIXIS_RST, 0);
+
+ while (1)
+ ;
+}
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
new file mode 100644
index 0000000..8f4183b
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ * Authors: York Sun <yorksun@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <fsl_diu_fb.h>
+#include "../common/pixis.h"
+
+#define PX_BRDCFG0_DLINK 0x10
+#define PX_BRDCFG0_DVISEL 0x08
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
+ unsigned long speed_ccb, temp, pixval;
+
+ speed_ccb = get_bus_freq(0);
+ temp = 1000000000/pixclock;
+ temp *= 1000;
+ pixval = speed_ccb / temp;
+ debug("DIU pixval = %lu\n", pixval);
+
+ /* Modify PXCLK in GUTS CLKDVDR */
+ debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
+ temp = *guts_clkdvdr & 0x2000FFFF;
+ *guts_clkdvdr = temp; /* turn off clock */
+ *guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
+ debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+ const char *name;
+ int gamma_fix = 0;
+ u32 pixel_format = 0x88883316;
+ u8 temp;
+
+ temp = in_8(&pixis->brdcfg0);
+
+ if (strncmp(port, "dlvds", 5) == 0) {
+ /* Dual link LVDS */
+ gamma_fix = 1;
+ temp &= ~(PX_BRDCFG0_DLINK | PX_BRDCFG0_DVISEL);
+ name = "Dual-Link LVDS";
+ } else if (strncmp(port, "lvds", 4) == 0) {
+ /* Single link LVDS */
+ temp = (temp & ~PX_BRDCFG0_DVISEL) | PX_BRDCFG0_DLINK;
+ name = "Single-Link LVDS";
+ } else {
+ /* DVI */
+ if (in_8(&pixis->ver) == 1) /* Board version */
+ pixel_format = 0x88882317;
+ temp |= PX_BRDCFG0_DVISEL;
+ name = "DVI";
+ }
+
+ printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+ out_8(&pixis->brdcfg0, temp);
+
+ return fsl_diu_init(xres, yres, pixel_format, gamma_fix);
+}
diff --git a/board/freescale/mpc8641hpcn/Kconfig b/board/freescale/mpc8641hpcn/Kconfig
new file mode 100644
index 0000000..ae45d63
--- /dev/null
+++ b/board/freescale/mpc8641hpcn/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MPC8641HPCN
+
+config SYS_BOARD
+ default "mpc8641hpcn"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "MPC8641HPCN"
+
+endif
diff --git a/board/freescale/mpc8641hpcn/MAINTAINERS b/board/freescale/mpc8641hpcn/MAINTAINERS
new file mode 100644
index 0000000..9790247
--- /dev/null
+++ b/board/freescale/mpc8641hpcn/MAINTAINERS
@@ -0,0 +1,7 @@
+MPC8641HPCN BOARD
+#M: Kumar Gala <kumar.gala@freescale.com>
+S: Orphan (since 2014-06)
+F: board/freescale/mpc8641hpcn/
+F: include/configs/MPC8641HPCN.h
+F: configs/MPC8641HPCN_defconfig
+F: configs/MPC8641HPCN_36BIT_defconfig
diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile
new file mode 100644
index 0000000..86c70bc
--- /dev/null
+++ b/board/freescale/mpc8641hpcn/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mpc8641hpcn.o
+obj-y += law.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/freescale/mpc8641hpcn/README b/board/freescale/mpc8641hpcn/README
new file mode 100644
index 0000000..d8fe0a4
--- /dev/null
+++ b/board/freescale/mpc8641hpcn/README
@@ -0,0 +1,186 @@
+Freescale MPC8641HPCN board
+===========================
+
+Created 05/24/2006 Haiying Wang
+-------------------------------
+
+1. Building U-Boot
+------------------
+The 86xx HPCN code base is known to compile using:
+ Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
+
+ $ make MPC8641HPCN_config
+ Configuring for MPC8641HPCN board...
+
+ $ make
+
+
+2. Switch and Jumper Setting
+----------------------------
+Jumpers:
+ J14 Pins 1-2 (near plcc32 socket)
+
+Switches:
+ SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1
+ 01100 :: CORE = 2.5:1
+ 10000 :: CORE = 3:1
+ 11100 :: CORE = 3.5:1
+ 10100 :: CORE = 4:1
+ 01110 :: CORE = 4.5:1
+ SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz
+ 001 :: SYSCLK = 40MHz
+
+ SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X
+ 0100 :: 4X
+ 0110 :: 6X
+ 1000 :: 8X
+ 1010 :: 10X
+ 1100 :: 12X
+ 1110 :: 14X
+ 0000 :: 16X
+ SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus
+
+ SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V
+ 0100000 :: VCORE = 1.11V
+ SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
+ 1 :: VCC_PLAT = 1.0V
+
+ SW4(1-2) = 11 CONFIG_SYS_HOSTMODE = 11 :: both prots host/root
+ SW4(3-4) = 11 CONFIG_SYS_BOOTSEQ = 11 :: no boot seq
+ SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX
+
+ SW5(1) = 1 CONFIG_SYS_FLASHMAP = 1 :: boot from flash
+ 0 :: boot from PromJet
+ SW5(2) = 1 CONFIG_SYS_FLASHBANK = 1 :: swap upper/lower
+ halves (virtual banks)
+ 0 :: normal
+ SW5(3) = 0 CONFIG_SYS_FLASHWP = 0 :: not protected
+ SW5(4) = 0 CONFIG_SYS_PORTDIV = 1 :: 2:1 for PD4
+ 1:1 for PD6
+ SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined
+ SW5(7-8) = 11 CONFIG_SYS_LADOPT = 11 :: s/w determined
+
+ SW6(1) = 1 CONFIG_SYS_CPUBOOT = 1 :: no boot holdoff
+ SW6(2) = 1 CONFIG_SYS_BOOTADDR = 1 :: no traslation
+ SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ
+ SW6(6) = 1 CONFIG_SYS_SERROM_ADDR= 1 ::
+ SW6(7) = 1 CONFIG_SYS_MEMDEBUG = 1 ::
+ SW6(8) = 1 CONFIG_SYS_DDRDEBUG = 1 ::
+
+ SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
+ SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
+ SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
+ SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
+ SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
+ SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
+ SW8(7) = 1 ACPWR = 1 :: non-battery
+ SW8(8) = 0 CONFIG_SYS_IDWP = 0 :: write enable
+
+
+3. Flash U-Boot
+---------------
+The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
+It is possible to use either half to boot using u-boot. Switch 5 bit 2
+is used for this purpose.
+
+0xEF800000 to 0xEFBFFFFF - 4MB
+0xEFC00000 to 0xEFFFFFFF - 4MB
+When this bit is 0, U-Boot is at 0xEFF00000.
+When this bit is 1, U-Boot is at 0xEFB00000.
+
+Use the above mentioned flash commands to program the other half, and
+use switch 5, bit 2 to alternate between the halves. Note: The booting
+version of U-Boot will always be at 0xEFF00000.
+
+To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
+
+ tftp 1000000 u-boot.bin
+ protect off all
+ erase eff00000 +$filesize
+ cp.b 1000000 eff00000 $filesize
+
+or use tftpflash command:
+ run tftpflash
+
+To Flash U-boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
+
+ tftp 1000000 u-boot.bin
+ erase efb00000 +$filesize
+ cp.b 1000000 efb00000 $filesize
+
+
+4. Memory Map
+-------------
+NOTE: RIO and PCI are mutually exclusive, so they share an address
+
+For 32-bit u-boot, devices are mapped so that the virtual address ==
+the physical address, and the map looks liks this:
+
+ Memory Range Device Size
+ ------------ ------ ----
+ 0x0000_0000 0x7fff_ffff DDR 2G
+ 0x8000_0000 0x9fff_ffff RIO MEM 512M
+ 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
+ 0xa000_0000 0xbfff_ffff PCI2/PEX2 MEM 512M
+ 0xffe0_0000 0xffef_ffff CCSR 1M
+ 0xffdf_0000 0xffdf_7fff PIXIS 8K
+ 0xffdf_8000 0xffdf_ffff CF 8K
+ 0xf840_0000 0xf840_3fff Stack space 32K
+ 0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K
+ 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K
+ 0xef80_0000 0xefff_ffff Flash 8M
+
+For 36-bit-enabled u-boot, the virtual map is the same as for 32-bit.
+However, the physical map is altered to reside in 36-bit space, as follows.
+Addresses are no longer mapped with VA == PA. All accesses from
+software use the VA; the PA is only used for setting up windows
+and mappings. Note that with the exception of PCI MEM and RIO, the low
+ 32 bits are the same as the VA above; only the top 4 bits vary:
+
+ Memory Range Device Size
+ ------------ ------ ----
+ 0x0_0000_0000 0x0_7fff_ffff DDR 2G
+ 0xc_0000_0000 0xc_1fff_ffff RIO MEM 512M
+ 0xc_0000_0000 0xc_1fff_ffff PCI1/PEX1 MEM 512M
+ 0xc_2000_0000 0xc_3fff_ffff PCI2/PEX2 MEM 512M
+ 0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M
+ 0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K
+ 0xf_ffdf_8000 0xf_ffdf_ffff CF 8K
+ 0x0_f840_0000 0xf_f840_3fff Stack space 32K
+ 0xf_ffc0_0000 0xf_ffc0_ffff PCI1/PEX1 IO 64K
+ 0xf_ffc1_0000 0xf_ffc1_ffff PCI2/PEX2 IO 64K
+ 0xf_ef80_0000 0xf_efff_ffff Flash 8M
+
+5. pixis_reset command
+--------------------
+A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
+using the FPGA sequencer. When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+ pixis_reset
+ pixis_reset altbank
+ pixis_reset altbank wd
+ pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+ pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples;
+
+ /* reset to current bank, like "reset" command */
+ pixis_reset
+
+ /* reset board but use the to alternate flash bank */
+ pixis_reset altbank
+
+ /* reset board, use alternate flash bank with watchdog timer enabled*/
+ pixis_reset altbank wd
+
+ /* reset board to alternate bank with frequency changed.
+ * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
+ */
+ pixis-reset altbank cf 40 2.5 10
+
+Valid clock choices are in the 8641 Reference Manuals.
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
new file mode 100644
index 0000000..7cd0395
--- /dev/null
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2008,2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust;
+ u32 cpo;
+ u32 write_data_delay;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+const struct board_specific_parameters dimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
+ */
+ {4, 333, 7, 7, 3},
+ {4, 549, 7, 9, 3},
+ {4, 650, 7, 10, 4},
+ {2, 333, 7, 7, 3},
+ {2, 549, 7, 9, 3},
+ {2, 650, 7, 10, 4},
+ {1, 333, 7, 7, 3},
+ {1, 549, 7, 9, 3},
+ {1, 650, 7, 10, 4},
+ {}
+};
+
+/*
+ * The two slots have slightly different timing. The center values are good
+ * for both slots. We use identical speed tables for them. In future use, if
+ * DIMMs have fewer center values that require two separated tables, copy the
+ * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
+ */
+const struct board_specific_parameters *dimms[] = {
+ dimm0,
+ dimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ unsigned int i;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (pdimm[i].n_ranks)
+ break;
+ }
+ if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
+ return;
+
+ pbsp = dimms[ctrl_num];
+
+ /* Get clk_adjust, cpo, write_data_delay, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm[i].n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+
+found:
+ /* 2T timing enable */
+ popts->twot_en = 1;
+}
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
new file mode 100644
index 0000000..6d25c76
--- /dev/null
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
+ * 0x8000_0000 0x9fff_ffff PCIE1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCIE2 MEM 512M
+ * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
+ * 0x8000_0000 0x9fff_ffff RapidIO 512M
+ * endif
+ * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
+ * 0xffc0_0000 0xffc0_ffff PCIE1 IO 64K
+ * 0xffc1_0000 0xffc1_ffff PCIE2 IO 64K
+ * 0xffe0_0000 0xffef_ffff CCSRBAR 1M
+ * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K
+ * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR doesn't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#if !defined(CONFIG_SPD_EEPROM)
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
+#endif
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
new file mode 100644
index 0000000..94633b5
--- /dev/null
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+
+phys_size_t fixed_sdram(void);
+
+int checkboard(void)
+{
+ u8 vboot;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+ in_8(pixis_base + PIXIS_PVER));
+
+ vboot = in_8(pixis_base + PIXIS_VBOOT);
+ if (vboot & PIXIS_VBOOT_FMAP)
+ printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
+ else
+ puts ("Promjet\n");
+
+ return 0;
+}
+
+phys_size_t
+initdram(int board_type)
+{
+ phys_size_t dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = fsl_ddr_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+
+ setup_ddr_bat(dram_size);
+
+ debug(" DDR: ");
+ return dram_size;
+}
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+phys_size_t
+fixed_sdram(void)
+{
+#if !defined(CONFIG_SYS_RAMBOOT)
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
+
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+ ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+ ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+ ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
+ ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
+
+#if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000008D;
+ ddr->err_sbe = 0x00ff0000;
+#endif
+ asm("sync;isync");
+
+ udelay(500);
+
+#if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
+#else
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+ ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
+#endif
+ asm("sync; isync");
+
+ udelay(500);
+#endif
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+
+#ifdef CONFIG_PCIE1
+ /*
+ * Activate ULI1575 legacy chip by performing a fake
+ * memory access. Needed to make ULI RTC work.
+ */
+ in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
+ + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
+#endif /* CONFIG_PCIE1 */
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int off;
+ u64 *tmp;
+ int addrcells;
+
+ ft_cpu_setup(blob, bd);
+
+ FT_FSL_PCI_SETUP;
+
+ /*
+ * Warn if it looks like the device tree doesn't match u-boot.
+ * This is just an estimation, based on the location of CCSR,
+ * which is defined by the "reg" property in the soc node.
+ */
+ off = fdt_path_offset(blob, "/soc8641");
+ addrcells = fdt_address_cells(blob, 0);
+ tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
+
+ if (tmp) {
+ u64 addr;
+
+ if (addrcells == 1)
+ addr = *(u32 *)tmp;
+ else
+ addr = *tmp;
+
+ if (addr != CONFIG_SYS_CCSRBAR_PHYS)
+ printf("WARNING: The CCSRBAR address in your .dts "
+ "does not match the address of the CCSR "
+ "in u-boot. This means your .dts might "
+ "be old.\n");
+ }
+
+ return 0;
+}
+#endif
+
+
+/*
+ * get_board_sys_clk
+ * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+ u8 i, go_bit, rd_clks;
+ ulong val = 0;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ go_bit = in_8(pixis_base + PIXIS_VCTL);
+ go_bit &= 0x01;
+
+ rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
+ rd_clks &= 0x1C;
+
+ /*
+ * Only if both go bit and the SCLK bit in VCFGEN0 are set
+ * should we be using the AUX register. Remember, we also set the
+ * GO bit to boot from the alternate bank on the on-board flash
+ */
+
+ if (go_bit) {
+ if (rd_clks == 0x1c)
+ i = in_8(pixis_base + PIXIS_AUX);
+ else
+ i = in_8(pixis_base + PIXIS_SPD);
+ } else {
+ i = in_8(pixis_base + PIXIS_SPD);
+ }
+
+ i &= 0x07;
+
+ switch (i) {
+ case 0:
+ val = 33000000;
+ break;
+ case 1:
+ val = 40000000;
+ break;
+ case 2:
+ val = 50000000;
+ break;
+ case 3:
+ val = 66000000;
+ break;
+ case 4:
+ val = 83000000;
+ break;
+ case 5:
+ val = 100000000;
+ break;
+ case 6:
+ val = 134000000;
+ break;
+ case 7:
+ val = 166000000;
+ break;
+ }
+
+ return val;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ /* Initialize TSECs */
+ cpu_eth_init(bis);
+ return pci_eth_init(bis);
+}
+
+void board_reset(void)
+{
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
+
+ out_8(pixis_base + PIXIS_RST, 0);
+
+ while (1)
+ ;
+}
diff --git a/board/freescale/mx23evk/Kconfig b/board/freescale/mx23evk/Kconfig
new file mode 100644
index 0000000..51a8f9f
--- /dev/null
+++ b/board/freescale/mx23evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX23EVK
+
+config SYS_BOARD
+ default "mx23evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mxs"
+
+config SYS_CONFIG_NAME
+ default "mx23evk"
+
+endif
diff --git a/board/freescale/mx23evk/MAINTAINERS b/board/freescale/mx23evk/MAINTAINERS
new file mode 100644
index 0000000..b03ad6a
--- /dev/null
+++ b/board/freescale/mx23evk/MAINTAINERS
@@ -0,0 +1,6 @@
+MX23EVK BOARD
+M: Otavio Salvador <otavio@ossystems.com.br>
+S: Maintained
+F: board/freescale/mx23evk/
+F: include/configs/mx23evk.h
+F: configs/mx23evk_defconfig
diff --git a/board/freescale/mx23evk/Makefile b/board/freescale/mx23evk/Makefile
new file mode 100644
index 0000000..c3a79ee
--- /dev/null
+++ b/board/freescale/mx23evk/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := mx23evk.o
+else
+obj-y := spl_boot.o
+endif
diff --git a/board/freescale/mx23evk/mx23evk.c b/board/freescale/mx23evk/mx23evk.c
new file mode 100644
index 0000000..9428182
--- /dev/null
+++ b/board/freescale/mx23evk/mx23evk.c
@@ -0,0 +1,78 @@
+/*
+ * Freescale MX23EVK board
+ *
+ * (C) Copyright 2013 O.S. Systems Software LTDA.
+ *
+ * Author: Otavio Salvador <otavio@ossystems.com.br>
+ *
+ * Based on m28evk.c:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+ /* Power on LCD */
+ gpio_direction_output(MX23_PAD_LCD_RESET__GPIO_1_18, 1);
+
+ /* Set contrast to maximum */
+ gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+static int mx23evk_mmc_wp(int id)
+{
+ if (id != 0) {
+ printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
+ return 1;
+ }
+
+ return gpio_get_value(MX23_PAD_PWM4__GPIO_1_30);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ /* Configure WP as input */
+ gpio_direction_input(MX23_PAD_PWM4__GPIO_1_30);
+
+ /* Configure MMC0 Power Enable */
+ gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0);
+
+ return mxsmmc_initialize(bis, 0, mx23evk_mmc_wp, NULL);
+}
+#endif
diff --git a/board/freescale/mx23evk/spl_boot.c b/board/freescale/mx23evk/spl_boot.c
new file mode 100644
index 0000000..603f4dc
--- /dev/null
+++ b/board/freescale/mx23evk/spl_boot.c
@@ -0,0 +1,135 @@
+/*
+ * Freescale MX23EVK Boot setup
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_SSP1 (MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_LCD (MXS_PAD_4MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* DUART */
+ MX23_PAD_PWM0__DUART_RX,
+ MX23_PAD_PWM1__DUART_TX,
+
+ /* EMI */
+ MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
+
+ MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+
+ MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+
+ /* MMC 0 */
+ MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP1,
+ MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP1,
+ MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP1,
+ MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP1,
+ MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP1,
+ MX23_PAD_SSP1_DETECT__SSP1_DETECT | MUX_CONFIG_SSP1,
+ (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_SSP1_SCK__SSP1_SCK |
+ (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ /* Write Protect Pin */
+ MX23_PAD_PWM4__GPIO_1_30 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ /* Slot Power Enable */
+ MX23_PAD_PWM3__GPIO_1_29 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ /* LCD */
+ MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+ MX23_PAD_GPMI_D08__LCD_D18 | MUX_CONFIG_LCD,
+ MX23_PAD_GPMI_D09__LCD_D19 | MUX_CONFIG_LCD,
+ MX23_PAD_GPMI_D10__LCD_D20 | MUX_CONFIG_LCD,
+ MX23_PAD_GPMI_D11__LCD_D21 | MUX_CONFIG_LCD,
+ MX23_PAD_GPMI_D12__LCD_D22 | MUX_CONFIG_LCD,
+ MX23_PAD_GPMI_D13__LCD_D23 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_DOTCK__LCD_DOTCK | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD, /* LCD power */
+ MX23_PAD_PWM2__GPIO_1_28 | MUX_CONFIG_LCD, /* LCD contrast */
+};
+
+#define HW_DRAM_CTL14 (0x38 >> 2)
+#define CS_MAP 0x3
+#define INTAREF 0x2
+#define HW_DRAM_CTL14_CONFIG (INTAREF << 8 | CS_MAP)
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG;
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/freescale/mx25pdk/Kconfig b/board/freescale/mx25pdk/Kconfig
new file mode 100644
index 0000000..af06b4c
--- /dev/null
+++ b/board/freescale/mx25pdk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX25PDK
+
+config SYS_BOARD
+ default "mx25pdk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx25"
+
+config SYS_CONFIG_NAME
+ default "mx25pdk"
+
+endif
diff --git a/board/freescale/mx25pdk/MAINTAINERS b/board/freescale/mx25pdk/MAINTAINERS
new file mode 100644
index 0000000..6322176
--- /dev/null
+++ b/board/freescale/mx25pdk/MAINTAINERS
@@ -0,0 +1,6 @@
+MX25PDK BOARD
+M: Fabio Estevam <fabio.estevam@freescale.com>
+S: Maintained
+F: board/freescale/mx25pdk/
+F: include/configs/mx25pdk.h
+F: configs/mx25pdk_defconfig
diff --git a/board/freescale/mx25pdk/Makefile b/board/freescale/mx25pdk/Makefile
new file mode 100644
index 0000000..0b288f2
--- /dev/null
+++ b/board/freescale/mx25pdk/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx25pdk.o
+obj-y += lowlevel_init.o
diff --git a/board/freescale/mx25pdk/imximage.cfg b/board/freescale/mx25pdk/imximage.cfg
new file mode 100644
index 0000000..3c8d6df
--- /dev/null
+++ b/board/freescale/mx25pdk/imximage.cfg
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/* EIM config-CS5 init -- CPLD */
+DATA 4 0xB8002050 0x0000D843
+DATA 4 0xB8002054 0x22252521
+DATA 4 0xB8002058 0x22220A00
+
+/* DDR2 init */
+DATA 4 0xB8001004 0x0076E83A
+DATA 4 0xB8001010 0x00000204
+DATA 4 0xB8001000 0x92210000
+DATA 4 0x80000f00 0x12344321
+DATA 4 0xB8001000 0xB2210000
+DATA 1 0x82000000 0xda
+DATA 1 0x83000000 0xda
+DATA 1 0x81000400 0xda
+DATA 1 0x80000333 0xda
+
+DATA 4 0xB8001000 0x92210000
+DATA 1 0x80000400 0x12345678
+
+DATA 4 0xB8001000 0xA2210000
+DATA 4 0x80000000 0x87654321
+DATA 4 0x80000000 0x87654321
+
+DATA 4 0xB8001000 0xB2210000
+DATA 1 0x80000233 0xda
+DATA 1 0x81000780 0xda
+DATA 1 0x81000400 0xda
+DATA 4 0xB8001000 0x82216080
+DATA 4 0x43FAC454 0x00001000
+
+DATA 4 0x53F80008 0x20034000
+
+/* Enable the clocks */
+DATA 4 0x53f8000c 0x1fffffff
+DATA 4 0x53f80010 0xffffffff
+DATA 4 0x53f80014 0xfdfff
diff --git a/board/freescale/mx25pdk/lowlevel_init.S b/board/freescale/mx25pdk/lowlevel_init.S
new file mode 100644
index 0000000..8c581b5
--- /dev/null
+++ b/board/freescale/mx25pdk/lowlevel_init.S
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2011 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov pc, lr
diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
new file mode 100644
index 0000000..71a395c
--- /dev/null
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx25.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc34704.h>
+
+#define FEC_RESET_B IMX_GPIO_NR(4, 8)
+#define FEC_ENABLE_B IMX_GPIO_NR(2, 3)
+#define CARD_DETECT IMX_GPIO_NR(2, 1)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+ {IMX_MMC_SDHC1_BASE},
+};
+#endif
+
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ * 0 for no pull
+ * or:
+ * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define FEC_OUT_PAD_CTRL 0
+
+#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_ODE)
+
+static void mx25pdk_fec_init(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+ NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
+ MX25_PAD_FEC_MDIO__FEC_MDIO,
+ MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+ NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
+
+ NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */
+ NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */
+ };
+
+ static const iomux_v3_cfg_t i2c_pads[] = {
+ NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+
+ /* Assert RESET and ENABLE low */
+ gpio_direction_output(FEC_RESET_B, 0);
+ gpio_direction_output(FEC_ENABLE_B, 0);
+
+ udelay(10);
+
+ /* Deassert RESET and ENABLE */
+ gpio_set_value(FEC_RESET_B, 1);
+ gpio_set_value(FEC_ENABLE_B, 1);
+
+ /* Setup I2C pins so that PMIC can turn on PHY supply */
+ imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+/*
+ * Set up input pins with hysteresis and 100-k pull-ups
+ */
+#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ * 0 for no pull
+ * or:
+ * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define UART1_OUT_PAD_CTRL 0
+
+static void mx25pdk_uart1_init(void)
+{
+ static const iomux_v3_cfg_t uart1_pads[] = {
+ NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+int board_early_init_f(void)
+{
+ mx25pdk_uart1_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ struct pmic *p;
+ int ret;
+
+ mx25pdk_fec_init();
+
+ ret = pmic_init(I2C_0);
+ if (ret)
+ return ret;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ /* Turn on Ethernet PHY supply */
+ pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* Set up the Card Detect pin. */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0));
+
+ gpio_direction_input(CARD_DETECT);
+ return !gpio_get_value(CARD_DETECT);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sdhc1_pads[] = {
+ NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+ return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+int checkboard(void)
+{
+ puts("Board: MX25PDK\n");
+
+ return 0;
+}
diff --git a/board/freescale/mx28evk/Kconfig b/board/freescale/mx28evk/Kconfig
new file mode 100644
index 0000000..39777bd
--- /dev/null
+++ b/board/freescale/mx28evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX28EVK
+
+config SYS_BOARD
+ default "mx28evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mxs"
+
+config SYS_CONFIG_NAME
+ default "mx28evk"
+
+endif
diff --git a/board/freescale/mx28evk/MAINTAINERS b/board/freescale/mx28evk/MAINTAINERS
new file mode 100644
index 0000000..1caf5fb
--- /dev/null
+++ b/board/freescale/mx28evk/MAINTAINERS
@@ -0,0 +1,9 @@
+MX28EVK BOARD
+M: Fabio Estevam <fabio.estevam@freescale.com>
+S: Maintained
+F: board/freescale/mx28evk/
+F: include/configs/mx28evk.h
+F: configs/mx28evk_defconfig
+F: configs/mx28evk_auart_console_defconfig
+F: configs/mx28evk_nand_defconfig
+F: configs/mx28evk_spi_defconfig
diff --git a/board/freescale/mx28evk/Makefile b/board/freescale/mx28evk/Makefile
new file mode 100644
index 0000000..5956d34
--- /dev/null
+++ b/board/freescale/mx28evk/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := mx28evk.o
+else
+obj-y := iomux.o
+endif
diff --git a/board/freescale/mx28evk/README b/board/freescale/mx28evk/README
new file mode 100644
index 0000000..f9d6324
--- /dev/null
+++ b/board/freescale/mx28evk/README
@@ -0,0 +1,62 @@
+FREESCALE MX28EVK
+==================
+
+Supported hardware: MX28EVK rev C and D are supported in U-boot.
+
+Files of the MX28EVK port
+--------------------------
+
+arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28
+arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28
+board/freescale/mx28evk/ - MX28EVK board specific files
+include/configs/mx28evk.h - MX28EVK configuration file
+
+Jumper configuration
+---------------------
+
+To boot MX28EVK from an SD card, set the boot mode DIP switches as:
+
+ * Boot Mode Select: 1 0 0 1 (Boot from SD card Slot 0 - U42)
+ * JTAG PSWITCH RESET: To the right (reset disabled)
+ * Battery Source: Down
+ * Wall 5V: Up
+ * VDD 5V: To the left (off)
+ * Hold Button: Down (off)
+
+To boot MX28EVK from SPI NOR flash, set the boot mode DIP switches as:
+
+ * Boot Mode Select: 0 0 1 0 (Boot from SSP2)
+ * JTAG PSWITCH RESET: To the right (reset disabled)
+ * Battery Source: Down
+ * Wall 5V: Up
+ * VDD 5V: To the left (off)
+ * Hold Button: Down (off)
+
+Environment Storage
+-------------------
+
+There are three targets for mx28evk:
+
+"make mx28evk_config" - store environment variables into MMC
+
+or
+
+"make mx28evk_nand_config" - store environment variables into NAND flash
+
+or
+
+"make mx28evk_spi_config" - store enviroment variables into SPI NOR flash
+
+Choose the target accordingly.
+
+Note: The mx28evk board does not come with a NAND flash populated from the
+factory. It comes with an empty slot (U23), which allows the insertion of a
+48-pin TSOP flash device.
+
+mx28evk does not come with SPI NOR flash populated from the factory either.
+It is possible to solder a SOIC memory on U49 or use a DIP8 on J89.
+To get SPI communication to work R320, R321,R322 and C178 need to be populated.
+Look in the schematics for the proper component values.
+
+Follow the instructions from doc/README.mxs to generate a bootable SD card or
+to generate a binary to be flashed into SPI NOR.
diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
new file mode 100644
index 0000000..97c2376
--- /dev/null
+++ b/board/freescale/mx28evk/iomux.c
@@ -0,0 +1,206 @@
+/*
+ * Freescale MX28EVK IOMUX setup
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* DUART */
+ MX28_PAD_PWM0__DUART_RX,
+ MX28_PAD_PWM1__DUART_TX,
+
+ /* MMC0 */
+ MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+ (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_SSP0_SCK__SSP0_SCK |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ /* write protect */
+ MX28_PAD_SSP1_SCK__GPIO_2_12,
+ /* MMC0 slot power enable */
+ MX28_PAD_PWM3__GPIO_3_28 |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+#ifdef CONFIG_NAND_MXS
+ /* GPMI NAND */
+ MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+ MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+#endif
+
+ /* FEC0 */
+ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+ /* FEC0 Enable */
+ MX28_PAD_SSP1_DATA3__GPIO_2_15 |
+ (MXS_PAD_12MA | MXS_PAD_3V3),
+ /* FEC0 Reset */
+ MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+ /* FEC1 */
+ MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+
+ /* EMI */
+ MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+ /* SPI2 (for SPI flash) */
+ MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_SS0__SSP2_D3 |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+ /* LCD */
+ MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD,
+ MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, /* LCD power */
+ MX28_PAD_PWM2__GPIO_3_18 | MUX_CONFIG_LCD, /* LCD contrast */
+};
+
+#define HW_DRAM_CTL29 (0x74 >> 2)
+#define CS_MAP 0xf
+#define COLUMN_SIZE 0x2
+#define ADDR_PINS 0x1
+#define APREBIT 0xa
+
+#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \
+ ADDR_PINS << 8 | APREBIT)
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c
new file mode 100644
index 0000000..5005fe2
--- /dev/null
+++ b/board/freescale/mx28evk/mx28evk.c
@@ -0,0 +1,148 @@
+/*
+ * Freescale MX28EVK board
+ *
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Based on m28evk.c:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+ /* SSP2 clock at 160MHz */
+ mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
+
+#ifdef CONFIG_CMD_USB
+ mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
+ mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
+ MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
+ gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
+#endif
+
+ /* Power on LCD */
+ gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1);
+
+ /* Set contrast to maximum */
+ gpio_direction_output(MX28_PAD_PWM2__GPIO_3_18, 1);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+static int mx28evk_mmc_wp(int id)
+{
+ if (id != 0) {
+ printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
+ return 1;
+ }
+
+ return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ /* Configure WP as input */
+ gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12);
+
+ /* Configure MMC0 Power Enable */
+ gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+
+ return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL);
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+
+int board_eth_init(bd_t *bis)
+{
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct eth_device *dev;
+ int ret;
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ return ret;
+
+ /* MX28EVK uses ENET_CLK PAD to drive FEC clock */
+ writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
+ &clkctrl_regs->hw_clkctrl_enet);
+
+ /* Power-on FECs */
+ gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
+
+ /* Reset FEC PHYs */
+ gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
+ udelay(200);
+ gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
+
+ ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+ if (ret) {
+ puts("FEC MXS: Unable to init FEC0\n");
+ return ret;
+ }
+
+ ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
+ if (ret) {
+ puts("FEC MXS: Unable to init FEC1\n");
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC0");
+ if (!dev) {
+ puts("FEC MXS: Unable to get FEC0 device entry\n");
+ return -EINVAL;
+ }
+
+ dev = eth_get_dev_by_name("FEC1");
+ if (!dev) {
+ puts("FEC MXS: Unable to get FEC1 device entry\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+#endif
diff --git a/board/freescale/mx31ads/Kconfig b/board/freescale/mx31ads/Kconfig
new file mode 100644
index 0000000..eeeb6f4
--- /dev/null
+++ b/board/freescale/mx31ads/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX31ADS
+
+config SYS_BOARD
+ default "mx31ads"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx31"
+
+config SYS_CONFIG_NAME
+ default "mx31ads"
+
+endif
diff --git a/board/freescale/mx31ads/MAINTAINERS b/board/freescale/mx31ads/MAINTAINERS
new file mode 100644
index 0000000..5f6ec26
--- /dev/null
+++ b/board/freescale/mx31ads/MAINTAINERS
@@ -0,0 +1,6 @@
+MX31ADS BOARD
+#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+S: Orphan (since 2013-09)
+F: board/freescale/mx31ads/
+F: include/configs/mx31ads.h
+F: configs/mx31ads_defconfig
diff --git a/board/freescale/mx31ads/Makefile b/board/freescale/mx31ads/Makefile
new file mode 100644
index 0000000..5e1440d
--- /dev/null
+++ b/board/freescale/mx31ads/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx31ads.o
+obj-y += lowlevel_init.o
diff --git a/board/freescale/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S
new file mode 100644
index 0000000..fcb5549
--- /dev/null
+++ b/board/freescale/mx31ads/lowlevel_init.S
@@ -0,0 +1,268 @@
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/imx-regs.h>
+
+.macro REG reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ strb r3, [r2]
+.endm
+
+.macro DELAY loops
+ ldr r2, =\loops
+1:
+ subs r2, r2, #1
+ nop
+ bcs 1b
+.endm
+
+/* RedBoot: AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =0x43F00000
+ ldr r1, =0x77777777
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, =0x53F00000
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+ ldr r0, =0x43F00000
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+
+ ldr r0, =0x53F00000
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+.endm /* init_aips */
+
+/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+ ldr r0, =0x43F04000
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+ ldr r1, =0x00302154
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =0x10
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =0x0
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ str r1, [r0, #0xD00] /* for M5 */
+.endm /* init_max */
+
+/* RedBoot: M3IF setup */
+.macro init_m3if
+ /* Configure M3IF registers */
+ ldr r1, =0xB8003000
+ /*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+ ldr r0, =0x00000040
+ str r0, [r1] /* M3IF control reg */
+.endm /* init_m3if */
+
+/* RedBoot: To support 133MHz DDR */
+.macro init_drive_strength
+ /*
+ * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+ * in SW_PAD_CTL registers
+ */
+
+ /* SDCLK */
+ ldr r1, =0x43FAC200
+ ldr r0, [r1, #0x6C]
+ bic r0, r0, #(1 << 12)
+ str r0, [r1, #0x6C]
+
+ /* CAS */
+ ldr r0, [r1, #0x70]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x70]
+
+ /* RAS */
+ ldr r0, [r1, #0x74]
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x74]
+
+ /* CS2 (CSD0) */
+ ldr r0, [r1, #0x7C]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x7C]
+
+ /* DQM3 */
+ ldr r0, [r1, #0x84]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x84]
+
+ /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+ ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+ ldr r0, [r1, #0x88]
+ bic r0, r0, #(1 << 22)
+ bic r0, r0, #(1 << 12)
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x88]
+ add r1, r1, #4
+ subs r2, r2, #0x1
+ bne pad_loop
+.endm /* init_drive_strength */
+
+/* CPLD on CS4 setup */
+.macro init_cs4
+ ldr r0, =WEIM_BASE
+ ldr r1, =0x0000D843
+ str r1, [r0, #0x40]
+ ldr r1, =0x22252521
+ str r1, [r0, #0x44]
+ ldr r1, =0x22220A00
+ str r1, [r0, #0x48]
+.endm /* init_cs4 */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* Redboot initializes very early AIPS, what for?
+ * Then it also initializes Multi-Layer AHB Crossbar Switch,
+ * M3IF */
+ /* Also setup the Peripheral Port Remap register inside the core */
+ ldr r0, =0x40000015 /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ init_drive_strength
+
+ init_cs4
+
+ /* Image Processing Unit: */
+ /* Too early to switch display on? */
+ REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */
+ /* Clock Control Module: */
+ REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
+
+ DELAY 0x40000
+
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */
+
+ /* PBC CPLD on CS4 */
+ mov r1, #CS4_BASE
+ ldrh r1, [r1, #0x2]
+ /* Is 27MHz switch set? */
+ ands r1, r1, #0x10
+
+ /* 532-133-66.5 */
+ ldr r0, =CCM_BASE
+ ldr r1, =0xFF871D58
+ /* PDR0 */
+ str r1, [r0, #0x4]
+ ldreq r1, MPCTL_PARAM_532
+ ldrne r1, MPCTL_PARAM_532_27
+ /* MPCTL */
+ str r1, [r0, #0x10]
+
+ /* Set UPLL=240MHz, USB=60MHz */
+ ldr r1, =0x49FCFE7F
+ /* PDR1 */
+ str r1, [r0, #0x8]
+ ldreq r1, UPCTL_PARAM_240
+ ldrne r1, UPCTL_PARAM_240_27
+ /* UPCTL */
+ str r1, [r0, #0x14]
+ /* default CLKO to 1/8 of the ARM core */
+ mov r1, #0x000002C0
+ add r1, r1, #0x00000006
+ /* COSR */
+ str r1, [r0, #0x1c]
+
+ /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
+/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
+
+ /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
+/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
+ /* Default: 1, 4, 12, 1 */
+ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+ /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
+ REG 0xB8001010, 0x00000004
+ REG 0xB8001004, 0x006ac73a
+ REG 0xB8001000, 0x92100000
+ REG 0x80000f00, 0x12344321
+ REG 0xB8001000, 0xa2100000
+ REG 0x80000000, 0x12344321
+ REG 0x80000000, 0x12344321
+ REG 0xB8001000, 0xb2100000
+ REG8 0x80000033, 0xda
+ REG8 0x81000000, 0xff
+ REG 0xB8001000, 0x82226080
+ REG 0x80000000, 0xDEADBEEF
+ REG 0xB8001010, 0x0000000c
+
+ mov pc, lr
+
+MPCTL_PARAM_532:
+ .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
+MPCTL_PARAM_532_27:
+ .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
+UPCTL_PARAM_240:
+ .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
+UPCTL_PARAM_240_27:
+ .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c
new file mode 100644
index 0000000..ad89cb0
--- /dev/null
+++ b/board/freescale/mx31ads/mx31ads.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ int i;
+
+ /* CS0: Nor Flash */
+ /*
+ * CS0L and CS0A values are from the RedBoot sources by Freescale
+ * and are also equal to those used by Sascha Hauer for the Phytec
+ * i.MX31 board. CS0U is just a slightly optimized hardware default:
+ * the only non-zero field "Wait State Control" is set to half the
+ * default value.
+ */
+ static const struct mxc_weimcs cs0 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(0, &cs0);
+
+ /* setup pins for UART1 */
+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+ mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+ /* SPI2 */
+ mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+ mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+ mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+ mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+ mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+ mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+ mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
+
+ /* start SPI2 clock */
+ __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
+
+ /* PBC setup */
+ /* Enable UART transceivers also reset the Ethernet/external UART */
+ readw(CS4_BASE + 4);
+
+ writew(0x8023, CS4_BASE + 4);
+
+ /* RedBoot also has an empty loop with 100000 iterations here -
+ * clock doesn't run yet */
+ for (i = 0; i < 100000; i++)
+ ;
+
+ /* Clear the reset, toggle the LEDs */
+ writew(0xDF, CS4_BASE + 6);
+
+ /* clock still doesn't run */
+ for (i = 0; i < 100000; i++)
+ ;
+
+ /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
+ readb(CS4_BASE + 8);
+ readb(CS4_BASE + 7);
+ readb(CS4_BASE + 8);
+ readb(CS4_BASE + 7);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: MX31ADS\n");
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_CS8900
+ rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
new file mode 100644
index 0000000..8a4a8a2
--- /dev/null
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -0,0 +1,110 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.__image_copy_start)
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ * (.vectors)
+ arch/arm/cpu/arm1136/start.o (.text*)
+ board/freescale/mx31ads/built-in.o (.text*)
+ arch/arm/lib/built-in.o (.text*)
+ net/built-in.o (.text*)
+ drivers/mtd/built-in.o (.text*)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o(.text*)
+
+ *(.text*)
+ }
+ . = ALIGN(4);
+ .rodata : { *(.rodata*) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ .hash : { *(.hash*) }
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ .dynsym _image_binary_end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .gnu.hash : { *(.gnu.hash) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
+}
diff --git a/board/freescale/mx31pdk/Kconfig b/board/freescale/mx31pdk/Kconfig
new file mode 100644
index 0000000..055545c
--- /dev/null
+++ b/board/freescale/mx31pdk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX31PDK
+
+config SYS_BOARD
+ default "mx31pdk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx31"
+
+config SYS_CONFIG_NAME
+ default "mx31pdk"
+
+endif
diff --git a/board/freescale/mx31pdk/MAINTAINERS b/board/freescale/mx31pdk/MAINTAINERS
new file mode 100644
index 0000000..ec2a320
--- /dev/null
+++ b/board/freescale/mx31pdk/MAINTAINERS
@@ -0,0 +1,6 @@
+MX31PDK BOARD
+M: Magnus Lilja <lilja.magnus@gmail.com>
+S: Maintained
+F: board/freescale/mx31pdk/
+F: include/configs/mx31pdk.h
+F: configs/mx31pdk_defconfig
diff --git a/board/freescale/mx31pdk/Makefile b/board/freescale/mx31pdk/Makefile
new file mode 100644
index 0000000..754b3ea
--- /dev/null
+++ b/board/freescale/mx31pdk/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += lowlevel_init.o
+endif
+obj-y += mx31pdk.o
diff --git a/board/freescale/mx31pdk/lowlevel_init.S b/board/freescale/mx31pdk/lowlevel_init.S
new file mode 100644
index 0000000..de43555
--- /dev/null
+++ b/board/freescale/mx31pdk/lowlevel_init.S
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Also setup the Peripheral Port Remap register inside the core */
+ ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+
+ write32 IPU_CONF, IPU_CONF_DI_EN
+ write32 CCM_CCMR, CCM_CCMR_SETUP
+
+ wait_timer 0x40000
+
+ write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
+ write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
+
+ /* Set up clock to 532MHz */
+ write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ
+ write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
+
+ write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+ /* Set up MX31 DDR pins */
+ write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
+ write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
+ write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
+ write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
+ write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
+ write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
+ write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
+ write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
+ write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
+ write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
+ write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
+ write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
+ write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
+ write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
+ write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
+ write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
+ write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
+ write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
+ write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
+ write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
+ write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
+ write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
+ write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
+ write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
+ write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
+ write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
+ write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
+
+ /* Set up MX31 DDR Memory Controller */
+ write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP
+ write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
+
+ /* Perform DDR init sequence */
+ write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE
+ write32 CSD0_BASE | 0x0f00, 0x12344321
+ write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
+ write32 CSD0_BASE, 0x12344321
+ write32 CSD0_BASE, 0x12344321
+ write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG
+ write8 CSD0_BASE | 0x00000033, 0xda
+ write8 CSD0_BASE | 0x01000000, 0xff
+ write32 WEIM_ESDCTL0, ESDCTL_RW
+ write32 CSD0_BASE, 0xDEADBEEF
+ write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
+
+ mov pc, lr
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
new file mode 100644
index 0000000..13b9d51
--- /dev/null
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -0,0 +1,118 @@
+/*
+ *
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <watchdog.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong bootflag)
+{
+ /*
+ * copy ourselves from where we are running to where we were
+ * linked at. Use ulong pointers as all addresses involved
+ * are 4-byte-aligned.
+ */
+ ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
+ asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
+ asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
+ asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
+ asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
+ for (dst = start_ptr; dst < end_ptr; dst++)
+ *dst = *(dst+(run_ptr-link_ptr));
+ /*
+ * branch to nand_boot's link-time address.
+ */
+ asm volatile("ldr pc, =nand_boot");
+}
+#endif
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /* CS5: CPLD incl. network controller */
+ static const struct mxc_weimcs cs5 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(5, &cs5);
+
+ /* Setup UART1 and SPI2 pins */
+ mx31_uart1_hw_init();
+ mx31_spi2_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ u32 val;
+ struct pmic *p;
+ int ret;
+
+ ret = pmic_init(CONFIG_FSL_PMIC_BUS);
+ if (ret)
+ return ret;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return -ENODEV;
+ /* Enable RTC battery */
+ pmic_reg_read(p, REG_POWER_CTL0, &val);
+ pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
+ pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
+#ifdef CONFIG_HW_WATCHDOG
+ hw_watchdog_init();
+#endif
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: MX31PDK\n");
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/freescale/mx35pdk/Kconfig b/board/freescale/mx35pdk/Kconfig
new file mode 100644
index 0000000..021d19e
--- /dev/null
+++ b/board/freescale/mx35pdk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX35PDK
+
+config SYS_BOARD
+ default "mx35pdk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx35"
+
+config SYS_CONFIG_NAME
+ default "mx35pdk"
+
+endif
diff --git a/board/freescale/mx35pdk/MAINTAINERS b/board/freescale/mx35pdk/MAINTAINERS
new file mode 100644
index 0000000..540e943
--- /dev/null
+++ b/board/freescale/mx35pdk/MAINTAINERS
@@ -0,0 +1,6 @@
+MX35PDK BOARD
+M: Stefano Babic <sbabic@denx.de>
+S: Maintained
+F: board/freescale/mx35pdk/
+F: include/configs/mx35pdk.h
+F: configs/mx35pdk_defconfig
diff --git a/board/freescale/mx35pdk/Makefile b/board/freescale/mx35pdk/Makefile
new file mode 100644
index 0000000..5fa1219
--- /dev/null
+++ b/board/freescale/mx35pdk/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx35pdk.o
+obj-y += lowlevel_init.o
diff --git a/board/freescale/mx35pdk/README b/board/freescale/mx35pdk/README
new file mode 100644
index 0000000..7232b53
--- /dev/null
+++ b/board/freescale/mx35pdk/README
@@ -0,0 +1,114 @@
+Overview
+--------------
+
+mx35pdk (known als as mx35_3stack) is a development board by Freescale.
+It consists of three pluggable board:
+ - CPU module, with CPU, RAM, flash
+ - Personality board, with most interfaces (USB, Network,..)
+ - Debug board with JTAG header.
+
+The board is usually delivered with redboot. This howto explains how to boot
+a linux kernel and how to replace the original bootloader with U-Boot.
+
+The board is delivered with Redboot on the NAND flash. It is possible to
+switch the boot device with the switches SW1-SW2 on the Personality board,
+and with SW5-SW10 on the Debug board.
+
+Delivered Redboot script to start the kernel
+---------------------------------------------------
+
+In redboot the following script is stored:
+
+fis load kernel
+exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76"
+
+Kernel is taken from flash. The image is in zImage format.
+
+Booting from NET, rootfs on NFS:
+-----------------------------------
+
+To change the script in redboot:
+
+load -r -b 0x100000 <path_to_zImage>
+exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp"
+
+If the ip address is not set, you can set it with :
+
+ip_address -l <board_ip/netmask> -h <server_ip>
+
+Linux partitions:
+---------------------------
+
+As default, the board is shipped with these partition tables for NAND
+and for NOR:
+
+Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit":
+0x00000000-0x00100000 : "nand.bootloader"
+0x00100000-0x00600000 : "nand.kernel"
+0x00600000-0x06600000 : "nand.rootfs"
+0x06600000-0x06e00000 : "nand.configure"
+0x06e00000-0x80000000 : "nand.userfs"
+
+Creating 6 MTD partitions on "mxc_nor_flash.0":
+0x00000000-0x00080000 : "Bootloader"
+0x00080000-0x00480000 : "nor.Kernel"
+0x00480000-0x02280000 : "nor.userfs"
+0x02280000-0x03e80000 : "nor.rootfs"
+0x01fe0000-0x01fe3000 : "FIS directory"
+0x01fff000-0x04000000 : "Redboot config"
+
+NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS.
+For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2.
+
+However, the setup in redboot is not correct and does not use the whole flash.
+
+Better solution is to use the kernel parameter mtdparts.
+Here the resulting script to be defined in RedBoot with fconfig:
+
+load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37
+exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
+
+Flashing U-Boot
+--------------------------------
+
+U-boot should be stored on the NOR flash.
+
+The boot storage can be select using the switches on the personality board
+(SW1-SW2) and on the DEBUG board (SW4-SW10).
+
+If something goes wrong flashing the bootloader, it is always possible to
+recover the board booting from the other device.
+
+Saving U-Boot in the NOR flash
+---------------------------------
+
+Check the partition for boot in the NOR flash. Setting the mtdparts as reported,
+the boot partition should be /dev/mtd0.
+
+Creating 6 MTD partitions on "mxc_nor_flash.0":
+0x00000000-0x00080000 : "Bootloader"
+0x00080000-0x00480000 : "nor.Kernel"
+0x00480000-0x02280000 : "nor.userfs"
+0x02280000-0x03e80000 : "nor.rootfs"
+0x01fe0000-0x01fe3000 : "FIS directory"
+0x01fff000-0x04000000 : "Redboot config"
+
+To erase the whole partition:
+$ flash_eraseall /dev/mtd0
+
+Writing u-boot:
+dd if=u-boot.bin of=/dev/mtd0
+
+To boot from NOR, you have to select the switches as follows:
+
+Personality board
+ SW2 all off
+ SW1 all off
+
+Debug Board:
+ SW5 0
+ SW6 0
+ SW7 0
+ SW8 1
+ SW9 1
+ SW10 0
diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S
new file mode 100644
index 0000000..5dc3cb0
--- /dev/null
+++ b/board/freescale/mx35pdk/lowlevel_init.S
@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+#include "mx35pdk.h"
+#include <asm/arch/lowlevel_macro.S>
+
+/*
+ * return soc version
+ * 0x10: TO1
+ * 0x20: TO2
+ * 0x30: TO3
+ */
+.macro check_soc_version ret, tmp
+ ldr \tmp, =IIM_BASE_ADDR
+ ldr \ret, [\tmp, #IIM_SREV]
+ cmp \ret, #0x00
+ moveq \tmp, #ROMPATCH_REV
+ ldreq \ret, [\tmp]
+ moveq \ret, \ret, lsl #4
+ addne \ret, \ret, #0x10
+.endm
+
+/* CPLD on CS5 setup */
+.macro init_debug_board
+ ldr r0, =DBG_BASE_ADDR
+ ldr r1, =DBG_CSCR_U_CONFIG
+ str r1, [r0, #0x00]
+ ldr r1, =DBG_CSCR_L_CONFIG
+ str r1, [r0, #0x04]
+ ldr r1, =DBG_CSCR_A_CONFIG
+ str r1, [r0, #0x08]
+.endm
+
+/* clock setup */
+.macro init_clock
+ ldr r0, =CCM_BASE_ADDR
+
+ /* default CLKO to 1/32 of the ARM core*/
+ ldr r1, [r0, #CLKCTL_COSR]
+ bic r1, r1, #0x00000FF00
+ bic r1, r1, #0x0000000FF
+ mov r2, #0x00006C00
+ add r2, r2, #0x67
+ orr r1, r1, r2
+ str r1, [r0, #CLKCTL_COSR]
+
+ ldr r2, =CCM_CCMR_CONFIG
+ str r2, [r0, #CLKCTL_CCMR]
+
+ check_soc_version r1, r2
+ cmp r1, #CHIP_REV_2_0
+ ldrhs r3, =CCM_MPLL_532_HZ
+ bhs 1f
+ ldr r2, [r0, #CLKCTL_PDR0]
+ tst r2, #CLKMODE_CONSUMER
+ ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
+ ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
+1:
+ str r3, [r0, #CLKCTL_MPCTL]
+
+ ldr r1, =CCM_PPLL_300_HZ
+ str r1, [r0, #CLKCTL_PPCTL]
+
+ ldr r1, =CCM_PDR0_CONFIG
+ bic r1, r1, #0x800000
+ str r1, [r0, #CLKCTL_PDR0]
+
+ ldr r1, [r0, #CLKCTL_CGR0]
+ orr r1, r1, #0x0C300000
+ str r1, [r0, #CLKCTL_CGR0]
+
+ ldr r1, [r0, #CLKCTL_CGR1]
+ orr r1, r1, #0x00000C00
+ orr r1, r1, #0x00000003
+ str r1, [r0, #CLKCTL_CGR1]
+
+ ldr r1, [r0, #CLKCTL_CGR2]
+ orr r1, r1, #0x00C00000
+ str r1, [r0, #CLKCTL_CGR2]
+.endm
+
+.macro setup_sdram
+ ldr r0, =ESDCTL_BASE_ADDR
+ mov r3, #0x2000
+ str r3, [r0, #0x0]
+ str r3, [r0, #0x8]
+
+ /*ip(r12) has used to save lr register in upper calling*/
+ mov fp, lr
+
+ mov r5, #0x00
+ mov r2, #0x00
+ mov r1, #CSD0_BASE_ADDR
+ bl setup_sdram_bank
+
+ mov r5, #0x00
+ mov r2, #0x00
+ mov r1, #CSD1_BASE_ADDR
+ bl setup_sdram_bank
+
+ mov lr, fp
+
+1:
+ ldr r3, =ESDCTL_DELAY_LINE5
+ str r3, [r0, #0x30]
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+ mov r10, lr
+
+ core_init
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ init_clock
+ init_debug_board
+
+ cmp pc, #PHYS_SDRAM_1
+ blo init_sdram_start
+ cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+ blo skip_sdram_setup
+
+init_sdram_start:
+ /*init_sdram*/
+ setup_sdram
+
+skip_sdram_setup:
+ mov lr, r10
+ mov pc, lr
+
+
+/*
+ * r0: ESDCTL control base, r1: sdram slot base
+ * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
+ */
+setup_sdram_bank:
+ mov r3, #0xE
+ tst r2, #0x1
+ orreq r3, r3, #0x300 /*DDR2*/
+ str r3, [r0, #0x10]
+ bic r3, r3, #0x00A
+ str r3, [r0, #0x10]
+ beq 2f
+
+ mov r3, #0x20000
+1: subs r3, r3, #1
+ bne 1b
+
+2: tst r2, #0x1
+ ldreq r3, =ESDCTL_DDR2_CONFIG
+ ldrne r3, =ESDCTL_MDDR_CONFIG
+ cmp r1, #CSD1_BASE_ADDR
+ strlo r3, [r0, #0x4]
+ strhs r3, [r0, #0xC]
+
+ ldr r3, =ESDCTL_0x92220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, =ESDCTL_PRECHARGE
+ strb r3, [r1, r4]
+
+ tst r2, #0x1
+ bne skip_set_mode
+
+ cmp r1, #CSD1_BASE_ADDR
+ ldr r3, =ESDCTL_0xB2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, =ESDCTL_DDR2_EMR2
+ strb r3, [r1, r4]
+ ldr r4, =ESDCTL_DDR2_EMR3
+ strb r3, [r1, r4]
+ ldr r4, =ESDCTL_DDR2_EN_DLL
+ strb r3, [r1, r4]
+ ldr r4, =ESDCTL_DDR2_RESET_DLL
+ strb r3, [r1, r4]
+
+ ldr r3, =ESDCTL_0x92220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ ldr r4, =ESDCTL_PRECHARGE
+ strb r3, [r1, r4]
+
+skip_set_mode:
+ cmp r1, #CSD1_BASE_ADDR
+ ldr r3, =ESDCTL_0xA2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ mov r3, #0xDA
+ strb r3, [r1]
+ strb r3, [r1]
+
+ ldr r3, =ESDCTL_0xB2220000
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+ tst r2, #0x1
+ ldreq r4, =ESDCTL_DDR2_MR
+ ldrne r4, =ESDCTL_MDDR_MR
+ mov r3, #0xDA
+ strb r3, [r1, r4]
+ ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
+ streqb r3, [r1, r4]
+ ldreq r4, =ESDCTL_DDR2_EN_DLL
+ ldrne r4, =ESDCTL_MDDR_EMR
+ strb r3, [r1, r4]
+
+ cmp r1, #CSD1_BASE_ADDR
+ ldr r3, =ESDCTL_0x82228080
+ strlo r3, [r0, #0x0]
+ strhs r3, [r0, #0x8]
+
+ tst r2, #0x1
+ moveq r4, #0x20000
+ movne r4, #0x200
+1: subs r4, r4, #1
+ bne 1b
+
+ str r3, [r1, #0x100]
+ ldr r4, [r1, #0x100]
+ cmp r3, r4
+ movne r3, #1
+ moveq r3, #0
+
+ mov pc, lr
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
new file mode 100644
index 0000000..12467a9
--- /dev/null
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx35.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <mc9sdz60.h>
+#include <mc13892.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef CONFIG_BOARD_LATE_INIT
+#error "CONFIG_BOARD_LATE_INIT must be set for this board"
+#endif
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ u32 size1, size2;
+
+ size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+ gd->ram_size = size1 + size2;
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+ static const iomux_v3_cfg_t i2c1_pads[] = {
+ NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
+ };
+
+ /* setup pins for I2C1 */
+ imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
+}
+
+
+static void setup_iomux_spi(void)
+{
+ static const iomux_v3_cfg_t spi_pads[] = {
+ MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
+ MX35_PAD_CSPI1_MISO__CSPI1_MISO,
+ MX35_PAD_CSPI1_SS0__CSPI1_SS0,
+ MX35_PAD_CSPI1_SS1__CSPI1_SS1,
+ MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
+}
+
+#define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
+#define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
+
+static void setup_iomux_usbotg(void)
+{
+ static const iomux_v3_cfg_t usbotg_pads[] = {
+ NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
+ USBOTG_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
+ USBOTG_IN_PAD_CTRL),
+ };
+
+ /* Set up pins for USBOTG. */
+ imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
+}
+
+#define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
+
+static void setup_iomux_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
+ NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
+ };
+
+ /* setup pins for FEC */
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+int board_early_init_f(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDIO_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_IPU_MASK,
+ &ccm->cgr1);
+
+ /* Setup NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ setup_iomux_i2c();
+ setup_iomux_usbotg();
+ setup_iomux_fec();
+ setup_iomux_spi();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+static inline int pmic_detect(void)
+{
+ unsigned int id;
+ struct pmic *p = pmic_get("FSL_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ pmic_reg_read(p, REG_IDENTIFICATION, &id);
+
+ id = (id >> 6) & 0x7;
+ if (id == 0x7)
+ return 1;
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ int rev;
+
+ rev = pmic_detect();
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+int board_late_init(void)
+{
+ u8 val;
+ u32 pmic_val;
+ struct pmic *p;
+ int ret;
+
+ ret = pmic_init(I2C_0);
+ if (ret)
+ return ret;
+
+ if (pmic_detect()) {
+ p = pmic_get("FSL_PMIC");
+ imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
+
+ pmic_reg_read(p, REG_SETTING_0, &pmic_val);
+ pmic_reg_write(p, REG_SETTING_0,
+ pmic_val | VO_1_30V | VO_1_50V);
+ pmic_reg_read(p, REG_MODE_0, &pmic_val);
+ pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
+
+ imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
+
+ gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
+ }
+
+ val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
+ mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
+ mdelay(200);
+
+ val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
+ mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
+ mdelay(200);
+
+ val |= 0x80;
+ mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
+
+ /* Print board revision */
+ printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_SMC911X)
+ int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ if (rc)
+ return rc;
+#endif
+ return cpu_eth_init(bis);
+}
+
+#if defined(CONFIG_FSL_ESDHC)
+
+struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sdhc1_pads[] = {
+ MX35_PAD_SD1_CMD__ESDHC1_CMD,
+ MX35_PAD_SD1_CLK__ESDHC1_CLK,
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+ };
+
+ /* configure pins for SDHC1 only */
+ imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
+
+ esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+ return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
+}
+#endif
diff --git a/board/freescale/mx35pdk/mx35pdk.h b/board/freescale/mx35pdk/mx35pdk.h
new file mode 100644
index 0000000..f552a1d
--- /dev/null
+++ b/board/freescale/mx35pdk/mx35pdk.h
@@ -0,0 +1,42 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BOARD_MX35_3STACK_H
+#define __BOARD_MX35_3STACK_H
+
+#define DBG_BASE_ADDR WEIM_CTRL_CS5
+#define DBG_CSCR_U_CONFIG 0x0000D843
+#define DBG_CSCR_L_CONFIG 0x22252521
+#define DBG_CSCR_A_CONFIG 0x22220A00
+
+#define CCM_CCMR_CONFIG 0x003F4208
+#define CCM_PDR0_CONFIG 0x00801000
+
+/* MEMORY SETTING */
+#define ESDCTL_0x92220000 0x92220000
+#define ESDCTL_0xA2220000 0xA2220000
+#define ESDCTL_0xB2220000 0xB2220000
+#define ESDCTL_0x82228080 0x82228080
+
+#define ESDCTL_PRECHARGE 0x00000400
+
+#define ESDCTL_MDDR_CONFIG 0x007FFC3F
+#define ESDCTL_MDDR_MR 0x00000033
+#define ESDCTL_MDDR_EMR 0x02000000
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+#define ESDCTL_DDR2_EMR2 0x04000000
+#define ESDCTL_DDR2_EMR3 0x06000000
+#define ESDCTL_DDR2_EN_DLL 0x02000400
+#define ESDCTL_DDR2_RESET_DLL 0x00000333
+#define ESDCTL_DDR2_MR 0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+#define ESDCTL_DELAY_LINE5 0x00F49F00
+#endif /* __BOARD_MX35_3STACK_H */
diff --git a/board/freescale/mx51evk/Kconfig b/board/freescale/mx51evk/Kconfig
new file mode 100644
index 0000000..f9b69cb
--- /dev/null
+++ b/board/freescale/mx51evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX51EVK
+
+config SYS_BOARD
+ default "mx51evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "mx51evk"
+
+endif
diff --git a/board/freescale/mx51evk/MAINTAINERS b/board/freescale/mx51evk/MAINTAINERS
new file mode 100644
index 0000000..0e5f22c
--- /dev/null
+++ b/board/freescale/mx51evk/MAINTAINERS
@@ -0,0 +1,6 @@
+MX51EVK BOARD
+M: Stefano Babic <sbabic@denx.de>
+S: Maintained
+F: board/freescale/mx51evk/
+F: include/configs/mx51evk.h
+F: configs/mx51evk_defconfig
diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile
new file mode 100644
index 0000000..b2de2d8
--- /dev/null
+++ b/board/freescale/mx51evk/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mx51evk.o
+obj-$(CONFIG_VIDEO) += mx51evk_video.o
diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg
new file mode 100644
index 0000000..a3b8593
--- /dev/null
+++ b/board/freescale/mx51evk/imximage.cfg
@@ -0,0 +1,109 @@
+/*
+ * (C Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Setting IOMUXC */
+DATA 4 0x73FA88a0 0x200
+DATA 4 0x73FA850c 0x20c5
+DATA 4 0x73FA8510 0x20c5
+DATA 4 0x73FA883c 0x2
+DATA 4 0x73FA8848 0x2
+DATA 4 0x73FA84b8 0xe7
+DATA 4 0x73FA84bc 0x45
+DATA 4 0x73FA84c0 0x45
+DATA 4 0x73FA84c4 0x45
+DATA 4 0x73FA84c8 0x45
+DATA 4 0x73FA8820 0x0
+DATA 4 0x73FA84a4 0x3
+DATA 4 0x73FA84a8 0x3
+DATA 4 0x73FA84ac 0xe3
+DATA 4 0x73FA84b0 0xe3
+DATA 4 0x73FA84b4 0xe3
+DATA 4 0x73FA84cc 0xe3
+DATA 4 0x73FA84d0 0xe2
+
+DATA 4 0x73FA882c 0x6
+DATA 4 0x73FA88a4 0x6
+DATA 4 0x73FA88ac 0x6
+DATA 4 0x73FA88b8 0x6
+
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
+DATA 4 0x83FD9000 0x82a20000
+/* ESDCTL_ESDCTL1 */
+DATA 4 0x83FD9008 0x82a20000
+/* ESDCTL_ESDMISC */
+DATA 4 0x83FD9010 0x000ad0d0
+/* ESDCTL_ESDCFG0 */
+DATA 4 0x83FD9004 0x333574aa
+/* ESDCTL_ESDCFG1 */
+DATA 4 0x83FD900C 0x333574aa
+
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
+DATA 4 0x83FD9014 0x04008008
+DATA 4 0x83FD9014 0x0000801a
+DATA 4 0x83FD9014 0x0000801b
+DATA 4 0x83FD9014 0x00448019
+DATA 4 0x83FD9014 0x07328018
+DATA 4 0x83FD9014 0x04008008
+DATA 4 0x83FD9014 0x00008010
+DATA 4 0x83FD9014 0x00008010
+DATA 4 0x83FD9014 0x06328018
+DATA 4 0x83FD9014 0x03808019
+DATA 4 0x83FD9014 0x00408019
+DATA 4 0x83FD9014 0x00008000
+
+/* Init DRAM on CS1 */
+DATA 4 0x83FD9014 0x0400800c
+DATA 4 0x83FD9014 0x0000801e
+DATA 4 0x83FD9014 0x0000801f
+DATA 4 0x83FD9014 0x0000801d
+DATA 4 0x83FD9014 0x0732801c
+DATA 4 0x83FD9014 0x0400800c
+DATA 4 0x83FD9014 0x00008014
+DATA 4 0x83FD9014 0x00008014
+DATA 4 0x83FD9014 0x0632801c
+DATA 4 0x83FD9014 0x0380801d
+DATA 4 0x83FD9014 0x0040801d
+DATA 4 0x83FD9014 0x00008004
+
+/* Write to CTL0 */
+DATA 4 0x83FD9000 0xb2a20000
+/* Write to CTL1 */
+DATA 4 0x83FD9008 0xb2a20000
+/* ESDMISC */
+DATA 4 0x83FD9010 0x000ad6d0
+/* ESDCTL_ESDCDLYGD */
+DATA 4 0x83FD9034 0x90000000
+DATA 4 0x83FD9014 0x00000000
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
new file mode 100644
index 0000000..c7c21f3
--- /dev/null
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -0,0 +1,399 @@
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx51.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/imx-common/mx5_video.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC2_BASE_ADDR},
+};
+#endif
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ u32 rev = get_cpu_rev();
+ if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
+ rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
+ return rev;
+}
+
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart_pads[] = {
+ MX51_PAD_UART1_RXD__UART1_RXD,
+ MX51_PAD_UART1_TXD__UART1_TXD,
+ NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+static void setup_iomux_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ MX51_PAD_NANDF_CS3__FEC_MDC,
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
+ MX51_PAD_NANDF_D9__FEC_RDATA0,
+ MX51_PAD_NANDF_CS6__FEC_TDATA3,
+ MX51_PAD_NANDF_CS5__FEC_TDATA2,
+ MX51_PAD_NANDF_CS4__FEC_TDATA1,
+ MX51_PAD_NANDF_D8__FEC_TDATA0,
+ MX51_PAD_NANDF_CS7__FEC_TX_EN,
+ MX51_PAD_NANDF_CS2__FEC_TX_ER,
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
+ MX51_PAD_EIM_CS5__FEC_CRS,
+ MX51_PAD_EIM_CS4__FEC_RX_ER,
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_MXC_SPI
+static void setup_iomux_spi(void)
+{
+ static const iomux_v3_cfg_t spi_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
+ MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX5
+#define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7)
+#define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27)
+#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 1)
+#define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5)
+
+static void setup_usb_h1(void)
+{
+ static const iomux_v3_cfg_t usb_h1_pads[] = {
+ MX51_PAD_USBH1_CLK__USBH1_CLK,
+ MX51_PAD_USBH1_DIR__USBH1_DIR,
+ MX51_PAD_USBH1_STP__USBH1_STP,
+ MX51_PAD_USBH1_NXT__USBH1_NXT,
+ MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+ MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+ MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+ MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+ MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+ MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+ MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+ MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
+ MX51_PAD_EIM_D17__GPIO2_1,
+ MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
+ };
+
+ imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
+}
+
+int board_ehci_hcd_init(int port)
+{
+ /* Set USBH1_STP to GPIO and toggle it */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
+ MX51_USBH_PAD_CTRL));
+
+ gpio_direction_output(MX51EVK_USBH1_STP, 0);
+ gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
+ mdelay(10);
+ gpio_set_value(MX51EVK_USBH1_STP, 1);
+
+ /* Set back USBH1_STP to be function */
+ imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
+
+ /* De-assert USB PHY RESETB */
+ gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
+
+ /* Drive USB_CLK_EN_B line low */
+ gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
+
+ /* Reset USB hub */
+ gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
+ mdelay(2);
+ gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
+ return 0;
+}
+#endif
+
+static void power_init(void)
+{
+ unsigned int val;
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ struct pmic *p;
+ int ret;
+
+ ret = pmic_init(CONFIG_FSL_PMIC_BUS);
+ if (ret)
+ return;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return;
+
+ /* Write needed to Power Gate 2 register */
+ pmic_reg_read(p, REG_POWER_MISC, &val);
+ val &= ~PWGT2SPIEN;
+ pmic_reg_write(p, REG_POWER_MISC, val);
+
+ /* Externally powered */
+ pmic_reg_read(p, REG_CHARGE, &val);
+ val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+ pmic_reg_write(p, REG_CHARGE, val);
+
+ /* power up the system first */
+ pmic_reg_write(p, REG_POWER_MISC, PWUP);
+
+ /* Set core voltage to 1.1V */
+ pmic_reg_read(p, REG_SW_0, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
+ pmic_reg_write(p, REG_SW_0, val);
+
+ /* Setup VCC (SW2) to 1.25 */
+ pmic_reg_read(p, REG_SW_1, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(p, REG_SW_1, val);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.25 */
+ pmic_reg_read(p, REG_SW_2, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(p, REG_SW_2, val);
+ udelay(50);
+
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, &mxc_ccm->cacrr);
+
+ /* Set switchers in Auto in NORMAL mode & STANDBY mode */
+ /* Setup the switcher mode for SW1 & SW2*/
+ pmic_reg_read(p, REG_SW_4, &val);
+ val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+ pmic_reg_write(p, REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ pmic_reg_read(p, REG_SW_5, &val);
+ val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
+ (SWMODE_MASK << SWMODE4_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
+ pmic_reg_write(p, REG_SW_5, val);
+
+ /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
+ pmic_reg_read(p, REG_SETTING_0, &val);
+ val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
+ val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
+ pmic_reg_write(p, REG_SETTING_0, val);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
+ pmic_reg_read(p, REG_SETTING_1, &val);
+ val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+ val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
+ pmic_reg_write(p, REG_SETTING_1, val);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = VGEN3CONFIG | VCAMCONFIG;
+ pmic_reg_write(p, REG_MODE_1, val);
+ udelay(200);
+
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+ VVIDEOEN | VAUDIOEN | VSDEN;
+ pmic_reg_write(p, REG_MODE_1, val);
+
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
+ NO_PAD_CTRL));
+ gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
+
+ udelay(500);
+
+ gpio_set_value(IMX_GPIO_NR(2, 14), 1);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret;
+
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
+ NO_PAD_CTRL));
+ gpio_direction_input(IMX_GPIO_NR(1, 0));
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
+ NO_PAD_CTRL));
+ gpio_direction_input(IMX_GPIO_NR(1, 6));
+
+ if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
+ else
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
+ };
+
+ static const iomux_v3_cfg_t sd2_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
+ };
+
+ u32 index;
+ int ret;
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
+ index++) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(sd1_pads,
+ ARRAY_SIZE(sd1_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(sd2_pads,
+ ARRAY_SIZE(sd2_pads));
+ break;
+ default:
+ printf("Warning: you configured more ESDHC controller"
+ "(%d) as supported by the board(2)\n",
+ CONFIG_SYS_FSL_ESDHC_NUM);
+ return -EINVAL;
+ }
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+#ifdef CONFIG_USB_EHCI_MX5
+ setup_usb_h1();
+#endif
+ setup_iomux_lcd();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_MXC_SPI
+ setup_iomux_spi();
+ power_init();
+#endif
+
+ return 0;
+}
+#endif
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX51EVK\n");
+
+ return 0;
+}
diff --git a/board/freescale/mx51evk/mx51evk_video.c b/board/freescale/mx51evk/mx51evk_video.c
new file mode 100644
index 0000000..86ec750
--- /dev/null
+++ b/board/freescale/mx51evk/mx51evk_video.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/list.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx51.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+#define MX51EVK_LCD_3V3 IMX_GPIO_NR(4, 9)
+#define MX51EVK_LCD_5V IMX_GPIO_NR(4, 10)
+#define MX51EVK_LCD_BACKLIGHT IMX_GPIO_NR(3, 4)
+
+static struct fb_videomode const claa_wvga = {
+ .name = "CLAA07LC0ACW",
+ .refresh = 57,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 37037,
+ .left_margin = 40,
+ .right_margin = 60,
+ .upper_margin = 10,
+ .lower_margin = 10,
+ .hsync_len = 20,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+static struct fb_videomode const dvi = {
+ .name = "DVI panel",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+void setup_iomux_lcd(void)
+{
+ /* DI2_PIN15 */
+ imx_iomux_v3_setup_pad(MX51_PAD_DI_GP4__DI2_PIN15);
+
+ /* Pad settings for DI2_DISP_CLK */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK,
+ PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW));
+
+ /* Turn on 3.3V voltage for LCD */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D12__GPIO4_9,
+ NO_PAD_CTRL));
+ gpio_direction_output(MX51EVK_LCD_3V3, 1);
+
+ /* Turn on 5V voltage for LCD */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D13__GPIO4_10,
+ NO_PAD_CTRL));
+ gpio_direction_output(MX51EVK_LCD_5V, 1);
+
+ /* Turn on GPIO backlight */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4,
+ NO_PAD_CTRL));
+ gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
+}
+
+int board_video_skip(void)
+{
+ int ret;
+ char const *e = getenv("panel");
+
+ if (e) {
+ if (strcmp(e, "claa") == 0) {
+ ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
+ if (ret)
+ printf("claa cannot be configured: %d\n", ret);
+ return ret;
+ }
+ }
+
+ /*
+ * 'panel' env variable not found or has different value than 'claa'
+ * Defaulting to dvi output.
+ */
+ ret = ipuv3_fb_init(&dvi, 0, IPU_PIX_FMT_RGB24);
+ if (ret)
+ printf("dvi cannot be configured: %d\n", ret);
+ return ret;
+}
diff --git a/board/freescale/mx53ard/Kconfig b/board/freescale/mx53ard/Kconfig
new file mode 100644
index 0000000..41f46a0
--- /dev/null
+++ b/board/freescale/mx53ard/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX53ARD
+
+config SYS_BOARD
+ default "mx53ard"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "mx53ard"
+
+endif
diff --git a/board/freescale/mx53ard/MAINTAINERS b/board/freescale/mx53ard/MAINTAINERS
new file mode 100644
index 0000000..7cc0e5e
--- /dev/null
+++ b/board/freescale/mx53ard/MAINTAINERS
@@ -0,0 +1,6 @@
+MX53ARD BOARD
+M: Fabio Estevam <fabio.estevam@freescale.com>
+S: Maintained
+F: board/freescale/mx53ard/
+F: include/configs/mx53ard.h
+F: configs/mx53ard_defconfig
diff --git a/board/freescale/mx53ard/Makefile b/board/freescale/mx53ard/Makefile
new file mode 100644
index 0000000..0b7d839
--- /dev/null
+++ b/board/freescale/mx53ard/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx53ard.o
diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg
new file mode 100644
index 0000000..247c1f3
--- /dev/null
+++ b/board/freescale/mx53ard/imximage_dd3.cfg
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x53fa8554 0x00300000
+DATA 4 0x53fa8558 0x00300040
+DATA 4 0x53fa8560 0x00300000
+DATA 4 0x53fa8564 0x00300040
+DATA 4 0x53fa8568 0x00300040
+DATA 4 0x53fa8570 0x00300000
+DATA 4 0x53fa8574 0x00300000
+DATA 4 0x53fa8578 0x00300000
+DATA 4 0x53fa857c 0x00300040
+DATA 4 0x53fa8580 0x00300040
+DATA 4 0x53fa8584 0x00300000
+DATA 4 0x53fa8588 0x00300000
+DATA 4 0x53fa8590 0x00300040
+DATA 4 0x53fa8594 0x00300000
+DATA 4 0x53fa86f0 0x00300000
+DATA 4 0x53fa86f4 0x00000000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8718 0x00300000
+DATA 4 0x53fa871c 0x00300000
+DATA 4 0x53fa8720 0x00300000
+DATA 4 0x53fa8724 0x04000000
+DATA 4 0x53fa8728 0x00300000
+DATA 4 0x53fa872c 0x00300000
+DATA 4 0x63fd9088 0x35343535
+DATA 4 0x63fd9090 0x4d444c44
+DATA 4 0x63fd907c 0x01370138
+DATA 4 0x63fd9080 0x013b013c
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd900c 0x9f5152e3
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x05208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9040 0x05380003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901C 0x00000000
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c
new file mode 100644
index 0000000..8ba2728
--- /dev/null
+++ b/board/freescale/mx53ard/mx53ard.c
@@ -0,0 +1,315 @@
+/*
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+
+#define ETHERNET_INT IMX_GPIO_NR(2, 31)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ u32 size1, size2;
+
+ size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+ gd->ram_size = size1 + size2;
+
+ return 0;
+}
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+#ifdef CONFIG_NAND_MXC
+static void setup_iomux_nand(void)
+{
+ static const iomux_v3_cfg_t nand_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
+ PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
+ PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
+ PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ };
+
+ u32 i, reg;
+
+ reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
+ reg &= ~M4IF_GENP_WEIM_MM_MASK;
+ __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
+ for (i = 0x4; i < 0x94; i += 0x18) {
+ reg = __raw_readl(WEIM_BASE_ADDR + i);
+ reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
+ __raw_writel(reg, WEIM_BASE_ADDR + i);
+ }
+
+ imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+}
+#else
+static void setup_iomux_nand(void)
+{
+}
+#endif
+
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret;
+
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+ gpio_direction_input(IMX_GPIO_NR(1, 1));
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
+ gpio_direction_input(IMX_GPIO_NR(1, 4));
+
+ if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
+ else
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
+
+ return ret;
+}
+
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ };
+
+ static const iomux_v3_cfg_t sd2_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
+ };
+
+ u32 index;
+ int ret;
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(sd1_pads,
+ ARRAY_SIZE(sd1_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(sd2_pads,
+ ARRAY_SIZE(sd2_pads));
+ break;
+ default:
+ printf("Warning: you configured more ESDHC controller"
+ "(%d) as supported by the board(2)\n",
+ CONFIG_SYS_FSL_ESDHC_NUM);
+ return -EINVAL;
+ }
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+static void weim_smc911x_iomux(void)
+{
+ static const iomux_v3_cfg_t weim_smc911x_pads[] = {
+ /* Data bus */
+ NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+
+ /* Address lines */
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
+ PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
+
+ /* other EIM signals for ethernet */
+ MX53_PAD_EIM_OE__EMI_WEIM_OE,
+ MX53_PAD_EIM_RW__EMI_WEIM_RW,
+ MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
+ };
+
+ /* ETHERNET_INT as GPIO2_31 */
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
+ gpio_direction_input(ETHERNET_INT);
+
+ /* WEIM bus */
+ imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
+ ARRAY_SIZE(weim_smc911x_pads));
+}
+
+static void weim_cs1_settings(void)
+{
+ struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+ writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
+ writel(0x0, &weim_regs->cs1gcr2);
+ writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
+ writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
+ writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
+ writel(0x0, &weim_regs->cs1wcr2);
+ writel(0x0, &weim_regs->wcr);
+
+ set_chipselect_size(CS0_64M_CS1_64M);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_nand();
+ setup_iomux_uart();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+ weim_smc911x_iomux();
+ weim_cs1_settings();
+
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX53ARD\n");
+
+ return 0;
+}
diff --git a/board/freescale/mx53evk/Kconfig b/board/freescale/mx53evk/Kconfig
new file mode 100644
index 0000000..c226c1c
--- /dev/null
+++ b/board/freescale/mx53evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX53EVK
+
+config SYS_BOARD
+ default "mx53evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "mx53evk"
+
+endif
diff --git a/board/freescale/mx53evk/MAINTAINERS b/board/freescale/mx53evk/MAINTAINERS
new file mode 100644
index 0000000..5c5f747
--- /dev/null
+++ b/board/freescale/mx53evk/MAINTAINERS
@@ -0,0 +1,6 @@
+MX53EVK BOARD
+M: Jason Liu <r64343@freescale.com>
+S: Maintained
+F: board/freescale/mx53evk/
+F: include/configs/mx53evk.h
+F: configs/mx53evk_defconfig
diff --git a/board/freescale/mx53evk/Makefile b/board/freescale/mx53evk/Makefile
new file mode 100644
index 0000000..e03ac79
--- /dev/null
+++ b/board/freescale/mx53evk/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2010 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx53evk.o
diff --git a/board/freescale/mx53evk/imximage.cfg b/board/freescale/mx53evk/imximage.cfg
new file mode 100644
index 0000000..384d2ae
--- /dev/null
+++ b/board/freescale/mx53evk/imximage.cfg
@@ -0,0 +1,98 @@
+/*
+ * (C Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/* Setting IOMUXC */
+DATA 4 0x53fa8554 0x00200000
+DATA 4 0x53fa8560 0x00200000
+DATA 4 0x53fa8594 0x00200000
+DATA 4 0x53fa8584 0x00200000
+DATA 4 0x53fa8558 0x00200040
+DATA 4 0x53fa8568 0x00200040
+DATA 4 0x53fa8590 0x00200040
+DATA 4 0x53fa857c 0x00200040
+DATA 4 0x53fa8564 0x00200040
+DATA 4 0x53fa8580 0x00200040
+DATA 4 0x53fa8570 0x00200000
+DATA 4 0x53fa8578 0x00200000
+DATA 4 0x53fa872c 0x00200000
+DATA 4 0x53fa8728 0x00200000
+DATA 4 0x53fa871c 0x00200000
+DATA 4 0x53fa8718 0x00200000
+DATA 4 0x53fa8574 0x00280000
+DATA 4 0x53fa8588 0x00280000
+DATA 4 0x53fa86f0 0x00280000
+DATA 4 0x53fa8720 0x00280000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa86f4 0x00000200
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8724 0x06000000
+DATA 4 0x63fd9088 0x34333936
+DATA 4 0x63fd9090 0x49434942
+DATA 4 0x63fd90F8 0x00000800
+DATA 4 0x63fd907c 0x01350138
+DATA 4 0x63fd9080 0x01380139
+DATA 4 0x63fd9018 0x00001710
+DATA 4 0x63fd9000 0xc4110000
+DATA 4 0x63fd900C 0x4d5122d2
+DATA 4 0x63fd9010 0x92d18a22
+DATA 4 0x63fd9014 0x00c70092
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f000e
+DATA 4 0x63fd9008 0x12272000
+DATA 4 0x63fd9004 0x00030012
+DATA 4 0x63fd901c 0x04008010
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00008031
+DATA 4 0x63fd901c 0x0b5280b0
+DATA 4 0x63fd901c 0x04008010
+DATA 4 0x63fd901c 0x00008020
+DATA 4 0x63fd901c 0x00008020
+DATA 4 0x63fd901c 0x0a528030
+DATA 4 0x63fd901c 0x03c68031
+DATA 4 0x63fd901c 0x00448031
+DATA 4 0x63fd901c 0x04008018
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00008039
+DATA 4 0x63fd901c 0x0b528138
+DATA 4 0x63fd901c 0x04008018
+DATA 4 0x63fd901c 0x00008028
+DATA 4 0x63fd901c 0x00008028
+DATA 4 0x63fd901c 0x0a528038
+DATA 4 0x63fd901c 0x03c68039
+DATA 4 0x63fd901c 0x00448039
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9058 0x00033335
+DATA 4 0x63fd901c 0x00000000
+DATA 4 0x63fd9040 0x05380003
+DATA 4 0x53fa8004 0x00194005
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
new file mode 100644
index 0000000..6ee6d73
--- /dev/null
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/errno.h>
+#include <asm/imx-common/boot_mode.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <asm/gpio.h>
+#include <mc13892.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_HYS | PAD_CTL_ODE)
+
+static void setup_i2c(unsigned int port_number)
+{
+ static const iomux_v3_cfg_t i2c1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
+ };
+
+ static const iomux_v3_cfg_t i2c2_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL),
+ };
+
+ switch (port_number) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(i2c1_pads,
+ ARRAY_SIZE(i2c1_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(i2c2_pads,
+ ARRAY_SIZE(i2c2_pads));
+ break;
+ default:
+ printf("Warning: Wrong I2C port number\n");
+ break;
+ }
+}
+
+void power_init(void)
+{
+ unsigned int val;
+ struct pmic *p;
+ int ret;
+
+ ret = pmic_init(I2C_0);
+ if (ret)
+ return;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return;
+
+ /* Set VDDA to 1.25V */
+ pmic_reg_read(p, REG_SW_2, &val);
+ val &= ~SWX_OUT_MASK;
+ val |= SWX_OUT_1_25;
+ pmic_reg_write(p, REG_SW_2, val);
+
+ /*
+ * Need increase VCC and VDDA to 1.3V
+ * according to MX53 IC TO2 datasheet.
+ */
+ if (is_soc_rev(CHIP_REV_2_0) == 0) {
+ /* Set VCC to 1.3V for TO2 */
+ pmic_reg_read(p, REG_SW_1, &val);
+ val &= ~SWX_OUT_MASK;
+ val |= SWX_OUT_1_30;
+ pmic_reg_write(p, REG_SW_1, val);
+
+ /* Set VDDA to 1.3V for TO2 */
+ pmic_reg_read(p, REG_SW_2, &val);
+ val &= ~SWX_OUT_MASK;
+ val |= SWX_OUT_1_30;
+ pmic_reg_write(p, REG_SW_2, val);
+ }
+}
+
+static void setup_iomux_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret;
+
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
+ gpio_direction_input(IMX_GPIO_NR(3, 11));
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
+ gpio_direction_input(IMX_GPIO_NR(3, 13));
+
+ if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+ ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
+ else
+ ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
+
+ return ret;
+}
+
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA13__GPIO3_13,
+ };
+
+ static const iomux_v3_cfg_t sd2_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+ SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA11__GPIO3_11,
+ };
+
+ u32 index;
+ int ret;
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+ for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(sd1_pads,
+ ARRAY_SIZE(sd1_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(sd2_pads,
+ ARRAY_SIZE(sd2_pads));
+ break;
+ default:
+ printf("Warning: you configured more ESDHC controller"
+ "(%d) as supported by the board(2)\n",
+ CONFIG_SYS_FSL_ESDHC_NUM);
+ return -EINVAL;
+ }
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
+ {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+ setup_i2c(1);
+ power_init();
+
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX53EVK\n");
+
+ return 0;
+}
diff --git a/board/freescale/mx53loco/Kconfig b/board/freescale/mx53loco/Kconfig
new file mode 100644
index 0000000..5ca1672
--- /dev/null
+++ b/board/freescale/mx53loco/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX53LOCO
+
+config SYS_BOARD
+ default "mx53loco"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "mx53loco"
+
+endif
diff --git a/board/freescale/mx53loco/MAINTAINERS b/board/freescale/mx53loco/MAINTAINERS
new file mode 100644
index 0000000..73b113e
--- /dev/null
+++ b/board/freescale/mx53loco/MAINTAINERS
@@ -0,0 +1,6 @@
+MX53LOCO BOARD
+M: Jason Liu <r64343@freescale.com>
+S: Maintained
+F: board/freescale/mx53loco/
+F: include/configs/mx53loco.h
+F: configs/mx53loco_defconfig
diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile
new file mode 100644
index 0000000..70ac6db
--- /dev/null
+++ b/board/freescale/mx53loco/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+# Jason Liu <r64343@freescale.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mx53loco.o
+obj-$(CONFIG_VIDEO) += mx53loco_video.o
diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg
new file mode 100644
index 0000000..d1c1931
--- /dev/null
+++ b/board/freescale/mx53loco/imximage.cfg
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x53fa8554 0x00300000
+DATA 4 0x53fa8558 0x00300040
+DATA 4 0x53fa8560 0x00300000
+DATA 4 0x53fa8564 0x00300040
+DATA 4 0x53fa8568 0x00300040
+DATA 4 0x53fa8570 0x00300000
+DATA 4 0x53fa8574 0x00300000
+DATA 4 0x53fa8578 0x00300000
+DATA 4 0x53fa857c 0x00300040
+DATA 4 0x53fa8580 0x00300040
+DATA 4 0x53fa8584 0x00300000
+DATA 4 0x53fa8588 0x00300000
+DATA 4 0x53fa8590 0x00300040
+DATA 4 0x53fa8594 0x00300000
+DATA 4 0x53fa86f0 0x00300000
+DATA 4 0x53fa86f4 0x00000000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8718 0x00300000
+DATA 4 0x53fa871c 0x00300000
+DATA 4 0x53fa8720 0x00300000
+DATA 4 0x53fa8724 0x04000000
+DATA 4 0x53fa8728 0x00300000
+DATA 4 0x53fa872c 0x00300000
+DATA 4 0x63fd9088 0x35343535
+DATA 4 0x63fd9090 0x4d444c44
+DATA 4 0x63fd907c 0x01370138
+DATA 4 0x63fd9080 0x013b013c
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd900c 0x9f5152e3
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x05208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9040 0x05380003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
new file mode 100644
index 0000000..efcf4b3
--- /dev/null
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -0,0 +1,418 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <asm/errno.h>
+#include <asm/imx-common/mx5_video.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+#include <power/pmic.h>
+#include <dialog_pmic.h>
+#include <fsl_pmic.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uint32_t mx53_dram_size[2];
+
+phys_size_t get_effective_memsize(void)
+{
+ /*
+ * WARNING: We must override get_effective_memsize() function here
+ * to report only the size of the first DRAM bank. This is to make
+ * U-Boot relocator place U-Boot into valid memory, that is, at the
+ * end of the first DRAM bank. If we did not override this function
+ * like so, U-Boot would be placed at the address of the first DRAM
+ * bank + total DRAM size - sizeof(uboot), which in the setup where
+ * each DRAM bank contains 512MiB of DRAM would result in placing
+ * U-Boot into invalid memory area close to the end of the first
+ * DRAM bank.
+ */
+ return mx53_dram_size[0];
+}
+
+int dram_init(void)
+{
+ mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+ mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+
+ gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = mx53_dram_size[0];
+
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = mx53_dram_size[1];
+}
+
+u32 get_board_rev(void)
+{
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ struct fuse_bank *bank = &iim->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+
+ int rev = readl(&fuse->gp[6]);
+
+ if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
+ rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+ /* request VBUS power enable pin, GPIO7_8 */
+ imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
+ gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
+ return 0;
+}
+#endif
+
+static void setup_iomux_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret;
+
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
+ gpio_direction_input(IMX_GPIO_NR(3, 11));
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
+ gpio_direction_input(IMX_GPIO_NR(3, 13));
+
+ if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+ ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
+ else
+ ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
+
+ return ret;
+}
+
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA13__GPIO3_13,
+ };
+
+ static const iomux_v3_cfg_t sd2_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+ SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA11__GPIO3_11,
+ };
+
+ u32 index;
+ int ret;
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+ for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(sd1_pads,
+ ARRAY_SIZE(sd1_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(sd2_pads,
+ ARRAY_SIZE(sd2_pads));
+ break;
+ default:
+ printf("Warning: you configured more ESDHC controller"
+ "(%d) as supported by the board(2)\n",
+ CONFIG_SYS_FSL_ESDHC_NUM);
+ return -EINVAL;
+ }
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+ static const iomux_v3_cfg_t i2c1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
+}
+
+static int power_init(void)
+{
+ unsigned int val;
+ int ret;
+ struct pmic *p;
+
+ if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
+ ret = pmic_dialog_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("DIALOG_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ setenv("fdt_file", "imx53-qsb.dtb");
+
+ /* Set VDDA to 1.25V */
+ val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
+ ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
+ if (ret) {
+ printf("Writing to BUCKCORE_REG failed: %d\n", ret);
+ return ret;
+ }
+
+ pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
+ val |= DA9052_SUPPLY_VBCOREGO;
+ ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+ if (ret) {
+ printf("Writing to SUPPLY_REG failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Set Vcc peripheral to 1.30V */
+ ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
+ if (ret) {
+ printf("Writing to BUCKPRO_REG failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
+ if (ret) {
+ printf("Writing to SUPPLY_REG failed: %d\n", ret);
+ return ret;
+ }
+
+ return ret;
+ }
+
+ if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
+ ret = pmic_init(I2C_0);
+ if (ret)
+ return ret;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ setenv("fdt_file", "imx53-qsrb.dtb");
+
+ /* Set VDDGP to 1.25V for 1GHz on SW1 */
+ pmic_reg_read(p, REG_SW_0, &val);
+ val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
+ ret = pmic_reg_write(p, REG_SW_0, val);
+ if (ret) {
+ printf("Writing to REG_SW_0 failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Set VCC as 1.30V on SW2 */
+ pmic_reg_read(p, REG_SW_1, &val);
+ val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
+ ret = pmic_reg_write(p, REG_SW_1, val);
+ if (ret) {
+ printf("Writing to REG_SW_1 failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Set global reset timer to 4s */
+ pmic_reg_read(p, REG_POWER_CTL2, &val);
+ val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
+ ret = pmic_reg_write(p, REG_POWER_CTL2, val);
+ if (ret) {
+ printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Set VUSBSEL and VUSBEN for USB PHY supply*/
+ pmic_reg_read(p, REG_MODE_0, &val);
+ val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
+ ret = pmic_reg_write(p, REG_MODE_0, val);
+ if (ret) {
+ printf("Writing to REG_MODE_0 failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Set SWBST to 5V in auto mode */
+ val = SWBST_AUTO;
+ ret = pmic_reg_write(p, SWBST_CTRL, val);
+ if (ret) {
+ printf("Writing to SWBST_CTRL failed: %d\n", ret);
+ return ret;
+ }
+
+ return ret;
+ }
+
+ return -1;
+}
+
+static void clock_1GHz(void)
+{
+ int ret;
+ u32 ref_clk = MXC_HCLK;
+ /*
+ * After increasing voltage to 1.25V, we can switch
+ * CPU clock to 1GHz and DDR to 400MHz safely
+ */
+ ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+ if (ret)
+ printf("CPU: Switch CPU clock to 1GHZ failed\n");
+
+ ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+ ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+ if (ret)
+ printf("CPU: Switch DDR clock to 400MHz failed\n");
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+ setup_iomux_lcd();
+
+ return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+ printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
+ (cpurev & 0xFF000) >> 12,
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ printf("Reset cause: %s\n", get_reset_cause());
+ return 0;
+}
+#endif
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ mxc_set_sata_internal_clock();
+ setup_iomux_i2c();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ if (!power_init())
+ clock_1GHz();
+ print_cpuinfo();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX53 LOCO\n");
+
+ return 0;
+}
diff --git a/board/freescale/mx53loco/mx53loco_video.c b/board/freescale/mx53loco/mx53loco_video.c
new file mode 100644
index 0000000..bc5e8a9
--- /dev/null
+++ b/board/freescale/mx53loco/mx53loco_video.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/list.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx53.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
+
+static struct fb_videomode const claa_wvga = {
+ .name = "CLAA07LC0ACW",
+ .refresh = 57,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 37037,
+ .left_margin = 40,
+ .right_margin = 60,
+ .upper_margin = 10,
+ .lower_margin = 10,
+ .hsync_len = 20,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+static struct fb_videomode const seiko_wvga = {
+ .name = "Seiko-43WVF1G",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 29851, /* picosecond (33.5 MHz) */
+ .left_margin = 89,
+ .right_margin = 164,
+ .upper_margin = 23,
+ .lower_margin = 10,
+ .hsync_len = 10,
+ .vsync_len = 10,
+ .sync = 0,
+};
+
+void setup_iomux_lcd(void)
+{
+ static const iomux_v3_cfg_t lcd_pads[] = {
+ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+ /* Turn on GPIO backlight */
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_D24__GPIO3_24);
+ gpio_direction_output(MX53LOCO_LCD_POWER, 1);
+
+ /* Turn on display contrast */
+ imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+ gpio_direction_output(IMX_GPIO_NR(1, 1), 1);
+}
+
+int board_video_skip(void)
+{
+ int ret;
+ char const *e = getenv("panel");
+
+ if (e) {
+ if (strcmp(e, "seiko") == 0) {
+ ret = ipuv3_fb_init(&seiko_wvga, 0, IPU_PIX_FMT_RGB24);
+ if (ret)
+ printf("Seiko cannot be configured: %d\n", ret);
+ return ret;
+ }
+ }
+
+ /*
+ * 'panel' env variable not found or has different value than 'seiko'
+ * Defaulting to claa lcd.
+ */
+ ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
+ if (ret)
+ printf("CLAA cannot be configured: %d\n", ret);
+ return ret;
+}
diff --git a/board/freescale/mx53smd/Kconfig b/board/freescale/mx53smd/Kconfig
new file mode 100644
index 0000000..1195d33
--- /dev/null
+++ b/board/freescale/mx53smd/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX53SMD
+
+config SYS_BOARD
+ default "mx53smd"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "mx53smd"
+
+endif
diff --git a/board/freescale/mx53smd/MAINTAINERS b/board/freescale/mx53smd/MAINTAINERS
new file mode 100644
index 0000000..8830321
--- /dev/null
+++ b/board/freescale/mx53smd/MAINTAINERS
@@ -0,0 +1,6 @@
+MX53SMD BOARD
+M: Fabio Estevam <fabio.estevam@freescale.com>
+S: Maintained
+F: board/freescale/mx53smd/
+F: include/configs/mx53smd.h
+F: configs/mx53smd_defconfig
diff --git a/board/freescale/mx53smd/Makefile b/board/freescale/mx53smd/Makefile
new file mode 100644
index 0000000..5da34c0
--- /dev/null
+++ b/board/freescale/mx53smd/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx53smd.o
diff --git a/board/freescale/mx53smd/imximage.cfg b/board/freescale/mx53smd/imximage.cfg
new file mode 100644
index 0000000..247c1f3
--- /dev/null
+++ b/board/freescale/mx53smd/imximage.cfg
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x53fa8554 0x00300000
+DATA 4 0x53fa8558 0x00300040
+DATA 4 0x53fa8560 0x00300000
+DATA 4 0x53fa8564 0x00300040
+DATA 4 0x53fa8568 0x00300040
+DATA 4 0x53fa8570 0x00300000
+DATA 4 0x53fa8574 0x00300000
+DATA 4 0x53fa8578 0x00300000
+DATA 4 0x53fa857c 0x00300040
+DATA 4 0x53fa8580 0x00300040
+DATA 4 0x53fa8584 0x00300000
+DATA 4 0x53fa8588 0x00300000
+DATA 4 0x53fa8590 0x00300040
+DATA 4 0x53fa8594 0x00300000
+DATA 4 0x53fa86f0 0x00300000
+DATA 4 0x53fa86f4 0x00000000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8718 0x00300000
+DATA 4 0x53fa871c 0x00300000
+DATA 4 0x53fa8720 0x00300000
+DATA 4 0x53fa8724 0x04000000
+DATA 4 0x53fa8728 0x00300000
+DATA 4 0x53fa872c 0x00300000
+DATA 4 0x63fd9088 0x35343535
+DATA 4 0x63fd9090 0x4d444c44
+DATA 4 0x63fd907c 0x01370138
+DATA 4 0x63fd9080 0x013b013c
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd900c 0x9f5152e3
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x05208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9040 0x05380003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901C 0x00000000
diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c
new file mode 100644
index 0000000..0963fd7
--- /dev/null
+++ b/board/freescale/mx53smd/mx53smd.c
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ u32 size1, size2;
+
+ size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+ gd->ram_size = size1 + size2;
+
+ return 0;
+}
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+static void setup_iomux_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+ {MMC_SDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
+ gpio_direction_input(IMX_GPIO_NR(3, 13));
+ return !gpio_get_value(IMX_GPIO_NR(3, 13));
+}
+
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA13__GPIO3_13,
+ };
+
+ u32 index;
+ int ret;
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(sd1_pads,
+ ARRAY_SIZE(sd1_pads));
+ break;
+
+ default:
+ printf("Warning: you configured more ESDHC controller"
+ "(%d) as supported by the board(1)\n",
+ CONFIG_SYS_FSL_ESDHC_NUM);
+ return -EINVAL;
+ }
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_fec();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX53SMD\n");
+
+ return 0;
+}
diff --git a/board/freescale/mx6qarm2/Kconfig b/board/freescale/mx6qarm2/Kconfig
new file mode 100644
index 0000000..4af33af
--- /dev/null
+++ b/board/freescale/mx6qarm2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX6QARM2
+
+config SYS_BOARD
+ default "mx6qarm2"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "mx6qarm2"
+
+endif
diff --git a/board/freescale/mx6qarm2/MAINTAINERS b/board/freescale/mx6qarm2/MAINTAINERS
new file mode 100644
index 0000000..52cf7f9
--- /dev/null
+++ b/board/freescale/mx6qarm2/MAINTAINERS
@@ -0,0 +1,10 @@
+MX6QARM2 BOARD
+M: Jason Liu <r64343@freescale.com>
+M: Ye Li <b37916@freescale.com>
+S: Maintained
+F: board/freescale/mx6qarm2/
+F: include/configs/mx6qarm2.h
+F: configs/mx6qarm2_defconfig
+F: configs/mx6dlarm2_defconfig
+F: configs/mx6qarm2_lpddr2_defconfig
+F: configs/mx6dlarm2_lpddr2_defconfig
diff --git a/board/freescale/mx6qarm2/Makefile b/board/freescale/mx6qarm2/Makefile
new file mode 100644
index 0000000..79401f4
--- /dev/null
+++ b/board/freescale/mx6qarm2/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6qarm2.o
diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
new file mode 100644
index 0000000..c85bde5
--- /dev/null
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -0,0 +1,338 @@
+/*
+ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+#ifdef CONFIG_MX6DQ_LPDDR2
+/* DCD */
+DATA 4 0x020C4018 0x60324
+
+DATA 4 0x020E05a8 0x00003038
+DATA 4 0x020E05b0 0x00003038
+DATA 4 0x020E0524 0x00003038
+DATA 4 0x020E051c 0x00003038
+
+DATA 4 0x020E0518 0x00003038
+DATA 4 0x020E050c 0x00003038
+DATA 4 0x020E05b8 0x00003038
+DATA 4 0x020E05c0 0x00003038
+
+DATA 4 0x020E05ac 0x00000038
+DATA 4 0x020E05b4 0x00000038
+DATA 4 0x020E0528 0x00000038
+DATA 4 0x020E0520 0x00000038
+
+DATA 4 0x020E0514 0x00000038
+DATA 4 0x020E0510 0x00000038
+DATA 4 0x020E05bc 0x00000038
+DATA 4 0x020E05c4 0x00000038
+
+DATA 4 0x020E056c 0x00000038
+DATA 4 0x020E0578 0x00000038
+DATA 4 0x020E0588 0x00000038
+DATA 4 0x020E0594 0x00000038
+
+DATA 4 0x020E057c 0x00000038
+DATA 4 0x020E0590 0x00000038
+DATA 4 0x020E0598 0x00000038
+DATA 4 0x020E058c 0x00000000
+
+DATA 4 0x020E059c 0x00000038
+DATA 4 0x020E05a0 0x00000038
+DATA 4 0x020E0784 0x00000038
+DATA 4 0x020E0788 0x00000038
+
+DATA 4 0x020E0794 0x00000038
+DATA 4 0x020E079c 0x00000038
+DATA 4 0x020E07a0 0x00000038
+DATA 4 0x020E07a4 0x00000038
+
+DATA 4 0x020E07a8 0x00000038
+DATA 4 0x020E0748 0x00000038
+DATA 4 0x020E074c 0x00000038
+DATA 4 0x020E0750 0x00020000
+
+DATA 4 0x020E0758 0x00000000
+DATA 4 0x020E0774 0x00020000
+DATA 4 0x020E078c 0x00000038
+DATA 4 0x020E0798 0x00080000
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b401c 0x00008000
+
+DATA 4 0x021b085c 0x1b5f01ff
+DATA 4 0x021b485c 0x1b5f01ff
+
+DATA 4 0x021b0800 0xa1390000
+DATA 4 0x021b4800 0xa1390000
+
+DATA 4 0x021b0890 0x00400000
+DATA 4 0x021b4890 0x00400000
+
+DATA 4 0x021b48bc 0x00055555
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b0834 0xf3333333
+DATA 4 0x021b0838 0xf3333333
+DATA 4 0x021b482c 0xf3333333
+DATA 4 0x021b4830 0xf3333333
+DATA 4 0x021b4834 0xf3333333
+DATA 4 0x021b4838 0xf3333333
+
+DATA 4 0x021b0848 0x49383b39
+DATA 4 0x021b0850 0x30364738
+DATA 4 0x021b4848 0x3e3c3846
+DATA 4 0x021b4850 0x4c294b35
+
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x0
+DATA 4 0x021b483c 0x20000000
+DATA 4 0x021b4840 0x0
+
+DATA 4 0x021b0858 0xf00
+DATA 4 0x021b4858 0xf00
+
+DATA 4 0x021b08b8 0x800
+DATA 4 0x021b48b8 0x800
+
+DATA 4 0x021b000c 0x555a61a5
+DATA 4 0x021b0004 0x20036
+DATA 4 0x021b0010 0x160e83
+DATA 4 0x021b0014 0xdd
+DATA 4 0x021b0018 0x8174c
+DATA 4 0x021b002c 0xf9f26d2
+DATA 4 0x021b0030 0x20e
+DATA 4 0x021b0038 0x200aac
+DATA 4 0x021b0008 0x0
+
+DATA 4 0x021b0040 0x5f
+
+DATA 4 0x021b0000 0xc3010000
+
+DATA 4 0x021b400c 0x555a61a5
+DATA 4 0x021b4004 0x20036
+DATA 4 0x021b4010 0x160e83
+DATA 4 0x021b4014 0xdd
+DATA 4 0x021b4018 0x8174c
+DATA 4 0x021b402c 0xf9f26d2
+DATA 4 0x021b4030 0x20e
+DATA 4 0x021b4038 0x200aac
+DATA 4 0x021b4008 0x0
+
+DATA 4 0x021b4040 0x3f
+DATA 4 0x021b4000 0xc3010000
+
+DATA 4 0x021b001c 0x3f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0xc2018030
+DATA 4 0x021b001c 0x6028030
+DATA 4 0x021b001c 0x2038030
+
+DATA 4 0x021b401c 0x3f8030
+DATA 4 0x021b401c 0xff0a8030
+DATA 4 0x021b401c 0xc2018030
+DATA 4 0x021b401c 0x6028030
+DATA 4 0x021b401c 0x2038030
+
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b4800 0xa1390003
+
+DATA 4 0x021b0020 0x7800
+DATA 4 0x021b4020 0x7800
+
+DATA 4 0x021b0818 0x0
+DATA 4 0x021b4818 0x0
+
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b4800 0xa1390003
+
+DATA 4 0x021b08b8 0x800
+DATA 4 0x021b48b8 0x800
+
+DATA 4 0x021b001c 0x0
+DATA 4 0x021b401c 0x0
+
+DATA 4 0x021b0404 0x00011006
+
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+#else
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+
+DATA 4 0x020e05ac 0x00020030
+DATA 4 0x020e05b4 0x00020030
+DATA 4 0x020e0528 0x00020030
+DATA 4 0x020e0520 0x00020030
+
+DATA 4 0x020e0514 0x00020030
+DATA 4 0x020e0510 0x00020030
+DATA 4 0x020e05bc 0x00020030
+DATA 4 0x020e05c4 0x00020030
+
+DATA 4 0x020e056c 0x00020030
+DATA 4 0x020e0578 0x00020030
+DATA 4 0x020e0588 0x00020030
+DATA 4 0x020e0594 0x00020030
+
+DATA 4 0x020e057c 0x00020030
+DATA 4 0x020e0590 0x00003000
+DATA 4 0x020e0598 0x00003000
+DATA 4 0x020e058c 0x00000000
+
+DATA 4 0x020e059c 0x00003030
+DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0750 0x00020000
+
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0798 0x000C0000
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b0018 0x00081740
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b000c 0x555A7975
+DATA 4 0x021b0010 0xFF538E64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b002c 0x000026D2
+
+DATA 4 0x021b0030 0x005B0E21
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0xC31A0000
+
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x0408803A
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x0000803B
+DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x00428039
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x09408038
+
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b001c 0x04008048
+DATA 4 0x021b0800 0xA1380003
+DATA 4 0x021b4800 0xA1380003
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b4818 0x00022227
+
+DATA 4 0x021b083c 0x434B0350
+DATA 4 0x021b0840 0x034C0359
+DATA 4 0x021b483c 0x434B0350
+DATA 4 0x021b4840 0x03650348
+DATA 4 0x021b0848 0x4436383B
+DATA 4 0x021b4848 0x39393341
+DATA 4 0x021b0850 0x35373933
+DATA 4 0x021b4850 0x48254A36
+
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+
+DATA 4 0x021b480c 0x00440044
+DATA 4 0x021b4810 0x00440044
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b001c 0x00000000
+DATA 4 0x021b0404 0x00011006
+
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+#endif /* CONFIG_MX6DQ_LPDDR2 */
diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg
new file mode 100644
index 0000000..ae8dcc6
--- /dev/null
+++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg
@@ -0,0 +1,462 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+
+
+#ifdef CONFIG_MX6DL_LPDDR2
+
+/* IOMUX SETTINGS */
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
+DATA 4 0x020E04bc 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
+DATA 4 0x020E04c0 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
+DATA 4 0x020E04c4 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
+DATA 4 0x020E04c8 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
+DATA 4 0x020E04cc 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
+DATA 4 0x020E04d0 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
+DATA 4 0x020E04d4 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
+DATA 4 0x020E04d8 0x00003028
+
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
+DATA 4 0x020E0470 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
+DATA 4 0x020E0474 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
+DATA 4 0x020E0478 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
+DATA 4 0x020E047c 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
+DATA 4 0x020E0480 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
+DATA 4 0x020E0484 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
+DATA 4 0x020E0488 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
+DATA 4 0x020E048c 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
+DATA 4 0x020E0464 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
+DATA 4 0x020E0490 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
+DATA 4 0x020E04ac 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
+DATA 4 0x020E04b0 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
+DATA 4 0x020E0494 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */
+DATA 4 0x020E04a4 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */
+DATA 4 0x020E04a8 0x00000038
+/*
+ * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
+ * DSE can be configured using Group Control Register:
+ * IOMUXC_SW_PAD_CTL_GRP_CTLDS
+ */
+DATA 4 0x020E04a0 0x00000000
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
+DATA 4 0x020E04b4 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
+DATA 4 0x020E04b8 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B0DS */
+DATA 4 0x020E0764 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B1DS */
+DATA 4 0x020E0770 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B2DS */
+DATA 4 0x020E0778 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B3DS */
+DATA 4 0x020E077c 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B4DS */
+DATA 4 0x020E0780 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B5DS */
+DATA 4 0x020E0784 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B6DS */
+DATA 4 0x020E078c 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B7DS */
+DATA 4 0x020E0748 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
+DATA 4 0x020E074c 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+DATA 4 0x020E076c 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
+DATA 4 0x020E0750 0x00020000
+/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
+DATA 4 0x020E0754 0x00000000
+/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
+DATA 4 0x020E0760 0x00020000
+/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
+DATA 4 0x020E0774 0x00080000
+
+/*
+ * DDR Controller Registers
+ *
+ * Manufacturer: Mocron
+ * Device Part Number: MT42L64M64D2KH-18
+ * Clock Freq.: 528MHz
+ * MMDC channels: Both MMDC0, MMDC1
+ *Density per CS in Gb: 256M
+ * Chip Selects used: 2
+ * Number of Banks: 8
+ * Row address: 14
+ * Column address: 9
+ * Data bus width 32
+ */
+
+/* MMDC_P0_BASE_ADDR = 0x021b0000 */
+/* MMDC_P1_BASE_ADDR = 0x021b4000 */
+
+/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
+DATA 4 0x021b001c 0x00008000
+
+/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
+DATA 4 0x021b401c 0x00008000
+
+/*LPDDR2 ZQ params */
+DATA 4 0x021b085c 0x1b5f01ff
+DATA 4 0x021b485c 0x1b5f01ff
+
+/* Calibration setup. */
+/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */
+DATA 4 0x021b0800 0xa1390003
+
+/*ca bus abs delay */
+DATA 4 0x021b0890 0x00400000
+/*ca bus abs delay */
+DATA 4 0x021b4890 0x00400000
+/* values of 20,40,50,60,7f tried. no difference seen */
+
+/* DDR_PHY_P1_MPWRCADL */
+DATA 4 0x021b48bc 0x00055555
+
+/*frc_msr.*/
+DATA 4 0x021b08b8 0x00000800
+/*frc_msr.*/
+DATA 4 0x021b48b8 0x00000800
+
+/* DDR_PHY_P0_MPREDQBY0DL3 */
+DATA 4 0x021b081c 0x33333333
+/* DDR_PHY_P0_MPREDQBY1DL3 */
+DATA 4 0x021b0820 0x33333333
+/* DDR_PHY_P0_MPREDQBY2DL3 */
+DATA 4 0x021b0824 0x33333333
+/* DDR_PHY_P0_MPREDQBY3DL3 */
+DATA 4 0x021b0828 0x33333333
+/* DDR_PHY_P1_MPREDQBY0DL3 */
+DATA 4 0x021b481c 0x33333333
+/* DDR_PHY_P1_MPREDQBY1DL3 */
+DATA 4 0x021b4820 0x33333333
+/* DDR_PHY_P1_MPREDQBY2DL3 */
+DATA 4 0x021b4824 0x33333333
+/* DDR_PHY_P1_MPREDQBY3DL3 */
+DATA 4 0x021b4828 0x33333333
+
+/*
+ * Read and write data delay, per byte.
+ * For optimized DDR operation it is recommended to run mmdc_calibration
+ * on your board, and replace 4 delay register assigns with resulted values
+ * Note:
+ * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
+ * should be skipped, or the write/read calibration comming after that
+ * will stall
+ * b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
+ */
+
+DATA 4 0x021b0848 0x4b4b524f
+DATA 4 0x021b4848 0x494f4c44
+
+DATA 4 0x021b0850 0x3c3d303c
+DATA 4 0x021b4850 0x3c343d38
+
+/*dqs gating dis */
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x0
+DATA 4 0x021b483c 0x20000000
+DATA 4 0x021b4840 0x0
+
+/*clk delay */
+DATA 4 0x021b0858 0xa00
+/*clk delay */
+DATA 4 0x021b4858 0xa00
+
+/*frc_msr */
+DATA 4 0x021b08b8 0x00000800
+/*frc_msr */
+DATA 4 0x021b48b8 0x00000800
+/* Calibration setup end */
+
+/* Channel0 - startng address 0x80000000 */
+/* MMDC0_MDCFG0 */
+DATA 4 0x021b000c 0x34386145
+
+/* MMDC0_MDPDC */
+DATA 4 0x021b0004 0x00020036
+/* MMDC0_MDCFG1 */
+DATA 4 0x021b0010 0x00100c83
+/* MMDC0_MDCFG2 */
+DATA 4 0x021b0014 0x000000Dc
+/* MMDC0_MDMISC */
+DATA 4 0x021b0018 0x0000174C
+/* MMDC0_MDRWD;*/
+DATA 4 0x021b002c 0x0f9f26d2
+/* MMDC0_MDOR */
+DATA 4 0x021b0030 0x0000020e
+/* MMDC0_MDCFG3LP */
+DATA 4 0x021b0038 0x00190778
+/* MMDC0_MDOTC */
+DATA 4 0x021b0008 0x00000000
+
+/* CS0_END */
+DATA 4 0x021b0040 0x0000005f
+/* ROC */
+DATA 4 0x021b0404 0x0000000f
+
+/* MMDC0_MDCTL */
+DATA 4 0x021b0000 0xc3010000
+
+/* Channel1 - starting address 0x10000000 */
+/* MMDC1_MDCFG0 */
+DATA 4 0x021b400c 0x34386145
+
+/* MMDC1_MDPDC */
+DATA 4 0x021b4004 0x00020036
+/* MMDC1_MDCFG1 */
+DATA 4 0x021b4010 0x00100c83
+/* MMDC1_MDCFG2 */
+DATA 4 0x021b4014 0x000000Dc
+/* MMDC1_MDMISC */
+DATA 4 0x021b4018 0x0000174C
+/* MMDC1_MDRWD;*/
+DATA 4 0x021b402c 0x0f9f26d2
+/* MMDC1_MDOR */
+DATA 4 0x021b4030 0x0000020e
+/* MMDC1_MDCFG3LP */
+DATA 4 0x021b4038 0x00190778
+/* MMDC1_MDOTC */
+DATA 4 0x021b4008 0x00000000
+
+/* CS0_END */
+DATA 4 0x021b4040 0x0000003f
+
+/* MMDC1_MDCTL */
+DATA 4 0x021b4000 0xc3010000
+
+/* Channel0 : Configure DDR device:*/
+/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
+DATA 4 0x021b001c 0x003f8030
+/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
+DATA 4 0x021b001c 0xff0a8030
+/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
+DATA 4 0x021b001c 0xa2018030
+/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
+DATA 4 0x021b001c 0x06028030
+/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
+DATA 4 0x021b001c 0x01038030
+
+/* Channel1 : Configure DDR device:*/
+/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
+DATA 4 0x021b401c 0x003f8030
+/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
+DATA 4 0x021b401c 0xff0a8030
+/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
+DATA 4 0x021b401c 0xa2018030
+/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
+DATA 4 0x021b401c 0x06028030
+/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
+DATA 4 0x021b401c 0x01038030
+
+/* MMDC0_MDREF */
+DATA 4 0x021b0020 0x00005800
+/* MMDC1_MDREF */
+DATA 4 0x021b4020 0x00005800
+
+/* DDR_PHY_P0_MPODTCTRL */
+DATA 4 0x021b0818 0x0
+/* DDR_PHY_P1_MPODTCTRL */
+DATA 4 0x021b4818 0x0
+
+/*
+ * calibration values based on calibration compare of 0x00ffff00:
+ * Note, these calibration values are based on Freescale's board
+ * May need to run calibration on target board to fine tune these
+ */
+
+/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */
+DATA 4 0x021b0800 0xa1310003
+
+/* DDR_PHY_P0_MPMUR0, frc_msr */
+DATA 4 0x021b08b8 0x00000800
+/* DDR_PHY_P1_MPMUR0, frc_msr */
+DATA 4 0x021b48b8 0x00000800
+
+/*
+ * MMDC0_MDSCR, clear this register
+ * (especially the configuration bit as initialization is complete)
+ */
+DATA 4 0x021b001c 0x00000000
+/*
+ * MMDC0_MDSCR, clear this register
+ * (especially the configuration bit as initialization is complete)
+ */
+DATA 4 0x021b401c 0x00000000
+
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+DATA 4 0x020e0010 0xF00000CF
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+#else /* CONFIG_MX6DL_LPDDR2 */
+
+DATA 4 0x020e0798 0x000c0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e0590 0x00003000
+DATA 4 0x020e0598 0x00003000
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00003030
+DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b4800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x00370037
+DATA 4 0x021b4810 0x00370037
+DATA 4 0x021b083c 0x422f0220
+DATA 4 0x021b0840 0x021f0219
+DATA 4 0x021b483C 0x422f0220
+DATA 4 0x021b4840 0x022d022f
+DATA 4 0x021b0848 0x47494b49
+DATA 4 0x021b4848 0x48484c47
+DATA 4 0x021b0850 0x39382b2f
+DATA 4 0x021b4850 0x2f35312c
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333030
+
+DATA 4 0x021b000c 0x40445323
+DATA 4 0x021b0010 0xb66e8c63
+
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00081740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x00440e21
+#ifdef CONFIG_DDR_32BIT
+DATA 4 0x021b0040 0x00000017
+DATA 4 0x021b0000 0xc3190000
+#else
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0xc31a0000
+#endif
+DATA 4 0x021b001c 0x04008032
+DATA 4 0x021b001c 0x0400803a
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x0000803b
+DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x00428039
+DATA 4 0x021b001c 0x07208030
+DATA 4 0x021b001c 0x07208038
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b001c 0x04008048
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00000007
+DATA 4 0x021b4818 0x00000007
+DATA 4 0x021b0004 0x0002556d
+DATA 4 0x021b4004 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+DATA 4 0x020e0010 0xF00000CF
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+#endif /* CONFIG_MX6DL_LPDDR2 */
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
new file mode 100644
index 0000000..98ccdb7
--- /dev/null
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -0,0 +1,283 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/clock.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+#if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
+ defined(CONFIG_DDR_32BIT)
+ gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
+#else
+ gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
+#endif
+
+ return 0;
+}
+
+iomux_v3_cfg_t const uart4_pads[] = {
+ MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret;
+
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
+ gpio_direction_input(IMX_GPIO_NR(6, 11));
+ ret = !gpio_get_value(IMX_GPIO_NR(6, 11));
+ } else /* Don't have the CD GPIO pin on board */
+ ret = 1;
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ u32 index = 0;
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif
+
+#define MII_MMD_ACCESS_CTRL_REG 0xd
+#define MII_MMD_ACCESS_ADDR_DATA_REG 0xe
+#define MII_DBG_PORT_REG 0x1d
+#define MII_DBG_PORT2_REG 0x1e
+
+int fecmxc_mii_postcall(int phy)
+{
+ unsigned short val;
+
+ /*
+ * Due to the i.MX6Q Armadillo2 board HW design,there is
+ * no 125Mhz clock input from SOC. In order to use RGMII,
+ * We need enable AR8031 ouput a 125MHz clk from CLK_25M
+ */
+ miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
+ miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
+ miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
+ miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
+ val &= 0xffe3;
+ val |= 0x18;
+ miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
+
+ /* For the RGMII phy, we need enable tx clock delay */
+ miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
+ miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
+ val |= 0x0100;
+ miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
+
+ miiphy_write("FEC", phy, MII_BMCR, 0xa100);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct eth_device *dev;
+ int ret = cpu_eth_init(bis);
+
+ if (ret)
+ return ret;
+
+ dev = eth_get_dev_by_name("FEC");
+ if (!dev) {
+ printf("FEC MXC: Unable to get FEC device entry\n");
+ return -EINVAL;
+ }
+
+ ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+ if (ret) {
+ printf("FEC MXC: Unable to register FEC mii postcall\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+
+ /*
+ * set daisy chain for otg_pin_id on 6q.
+ * for 6dl, this bit is reserved
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 1);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 0)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_enet();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_MX6DL
+ puts("Board: MX6DL-Armadillo2\n");
+#else
+ puts("Board: MX6Q-Armadillo2\n");
+#endif
+
+ return 0;
+}
diff --git a/board/freescale/mx6qsabreauto/Kconfig b/board/freescale/mx6qsabreauto/Kconfig
new file mode 100644
index 0000000..cc2a140
--- /dev/null
+++ b/board/freescale/mx6qsabreauto/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX6QSABREAUTO
+
+config SYS_BOARD
+ default "mx6qsabreauto"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "mx6qsabreauto"
+
+endif
diff --git a/board/freescale/mx6qsabreauto/MAINTAINERS b/board/freescale/mx6qsabreauto/MAINTAINERS
new file mode 100644
index 0000000..fb65ce4
--- /dev/null
+++ b/board/freescale/mx6qsabreauto/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6QSABREAUTO BOARD
+M: Fabio Estevam <fabio.estevam@freescale.com>
+S: Maintained
+F: board/freescale/mx6qsabreauto/
+F: include/configs/mx6qsabreauto.h
+F: configs/mx6dlsabreauto_defconfig
+F: configs/mx6qsabreauto_defconfig
diff --git a/board/freescale/mx6qsabreauto/Makefile b/board/freescale/mx6qsabreauto/Makefile
new file mode 100644
index 0000000..ac5bc81
--- /dev/null
+++ b/board/freescale/mx6qsabreauto/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6qsabreauto.o
diff --git a/board/freescale/mx6qsabreauto/imximage.cfg b/board/freescale/mx6qsabreauto/imximage.cfg
new file mode 100644
index 0000000..16bf473
--- /dev/null
+++ b/board/freescale/mx6qsabreauto/imximage.cfg
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00000028
+DATA 4 0x020e05b0 0x00000028
+DATA 4 0x020e0524 0x00000028
+DATA 4 0x020e051c 0x00000028
+DATA 4 0x020e0518 0x00000028
+DATA 4 0x020e050c 0x00000028
+DATA 4 0x020e05b8 0x00000028
+DATA 4 0x020e05c0 0x00000028
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000028
+DATA 4 0x020e0788 0x00000028
+DATA 4 0x020e0794 0x00000028
+DATA 4 0x020e079c 0x00000028
+DATA 4 0x020e07a0 0x00000028
+DATA 4 0x020e07a4 0x00000028
+DATA 4 0x020e07a8 0x00000028
+DATA 4 0x020e0748 0x00000028
+DATA 4 0x020e05ac 0x00000028
+DATA 4 0x020e05b4 0x00000028
+DATA 4 0x020e0528 0x00000028
+DATA 4 0x020e0520 0x00000028
+DATA 4 0x020e0514 0x00000028
+DATA 4 0x020e0510 0x00000028
+DATA 4 0x020e05bc 0x00000028
+DATA 4 0x020e05c4 0x00000028
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+DATA 4 0x021b083c 0x43260335
+DATA 4 0x021b0840 0x031A030B
+DATA 4 0x021b483c 0x4323033B
+DATA 4 0x021b4840 0x0323026F
+DATA 4 0x021b0848 0x483D4545
+DATA 4 0x021b4848 0x44433E48
+DATA 4 0x021b0850 0x41444840
+DATA 4 0x021b4850 0x4835483E
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b000c 0x8A8F7955
+DATA 4 0x021b0010 0xFF328F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x008F1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0xFFFFF300
+DATA 4 0x020c407c 0x0F0000F3
+DATA 4 0x020c4080 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6qsabreauto/mx6dl.cfg b/board/freescale/mx6qsabreauto/mx6dl.cfg
new file mode 100644
index 0000000..89078e5
--- /dev/null
+++ b/board/freescale/mx6qsabreauto/mx6dl.cfg
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x020e0774 0x000C0000
+DATA 4 0x020e0754 0x00000000
+DATA 4 0x020e04ac 0x00000030
+DATA 4 0x020e04b0 0x00000030
+DATA 4 0x020e0464 0x00000030
+DATA 4 0x020e0490 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0494 0x00000030
+DATA 4 0x020e04a0 0x00000000
+DATA 4 0x020e04b4 0x00000030
+DATA 4 0x020e04b8 0x00000030
+DATA 4 0x020e076c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e04bc 0x00000028
+DATA 4 0x020e04c0 0x00000028
+DATA 4 0x020e04c4 0x00000028
+DATA 4 0x020e04c8 0x00000028
+DATA 4 0x020e04cc 0x00000028
+DATA 4 0x020e04d0 0x00000028
+DATA 4 0x020e04d4 0x00000028
+DATA 4 0x020e04d8 0x00000028
+DATA 4 0x020e0760 0x00020000
+DATA 4 0x020e0764 0x00000028
+DATA 4 0x020e0770 0x00000028
+DATA 4 0x020e0778 0x00000028
+DATA 4 0x020e077c 0x00000028
+DATA 4 0x020e0780 0x00000028
+DATA 4 0x020e0784 0x00000028
+DATA 4 0x020e078c 0x00000028
+DATA 4 0x020e0748 0x00000028
+DATA 4 0x020e0470 0x00000028
+DATA 4 0x020e0474 0x00000028
+DATA 4 0x020e0478 0x00000028
+DATA 4 0x020e047c 0x00000028
+DATA 4 0x020e0480 0x00000028
+DATA 4 0x020e0484 0x00000028
+DATA 4 0x020e0488 0x00000028
+DATA 4 0x020e048c 0x00000028
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+DATA 4 0x021b083c 0x42190217
+DATA 4 0x021b0840 0x017B017B
+DATA 4 0x021b483c 0x4176017B
+DATA 4 0x021b4840 0x015F016C
+DATA 4 0x021b0848 0x4C4C4D4C
+DATA 4 0x021b4848 0x4A4D4C48
+DATA 4 0x021b0850 0x3F3F3F40
+DATA 4 0x021b4850 0x3538382E
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020025
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676B5313
+DATA 4 0x021b0010 0xB66E8B63
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006B1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x021b001c 0x04008032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x05208030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025565
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0xFFFFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
new file mode 100644
index 0000000..59387ff
--- /dev/null
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -0,0 +1,615 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/spi.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/imx-common/video.h>
+#include <asm/arch/crm_regs.h>
+#include <pca953x.h>
+#include <power/pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+ PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC 1
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+#ifndef CONFIG_SYS_FLASH_CFI
+/*
+ * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
+ * Compass Sensor, Accelerometer, Res Touch
+ */
+static struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+#endif
+
+static iomux_v3_cfg_t const i2c3_pads[] = {
+ MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const port_exp[] = {
+ MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/*Define for building port exp gpio, pin starts from 0*/
+#define PORTEXP_IO_NR(chip, pin) \
+ ((chip << 5) + pin)
+
+/*Get the chip addr from a ioexp gpio*/
+#define PORTEXP_IO_TO_CHIP(gpio_nr) \
+ (gpio_nr >> 5)
+
+/*Get the pin number from a ioexp gpio*/
+#define PORTEXP_IO_TO_PIN(gpio_nr) \
+ (gpio_nr & 0x1f)
+
+static int port_exp_direction_output(unsigned gpio, int value)
+{
+ int ret;
+
+ i2c_set_bus_num(2);
+ ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (value << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const eimnor_pads[] = {
+ MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
+ MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+ MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void eimnor_cs_setup(void)
+{
+ struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+ writel(0x00020181, &weim_regs->cs0gcr1);
+ writel(0x00000001, &weim_regs->cs0gcr2);
+ writel(0x0a020000, &weim_regs->cs0rcr1);
+ writel(0x0000c000, &weim_regs->cs0rcr2);
+ writel(0x0804a240, &weim_regs->cs0wcr1);
+ writel(0x00000120, &weim_regs->wcr);
+
+ set_chipselect_size(CS0_128);
+}
+
+static void setup_iomux_eimnor(void)
+{
+ imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
+
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+
+ eimnor_cs_setup();
+}
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ gpio_direction_input(IMX_GPIO_NR(6, 15));
+ return !gpio_get_value(IMX_GPIO_NR(6, 15));
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t gpmi_pads[] = {
+ MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
+ MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+ /* gate ENFC_CLK_ROOT clock first,before clk source switch */
+ clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+ clrbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+ /* config gpmi and bch clock to 100 MHz */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+ /* enable ENFC_CLK_ROOT clock */
+ setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+
+ return cpu_eth_init(bis);
+}
+
+#define BOARD_REV_B 0x200
+#define BOARD_REV_A 0x100
+
+static int mx6sabre_rev(void)
+{
+ /*
+ * Get Board ID information from OCOTP_GP1[15:8]
+ * i.MX6Q ARD RevA: 0x01
+ * i.MX6Q ARD RevB: 0x02
+ */
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[4];
+ struct fuse_bank4_regs *fuse =
+ (struct fuse_bank4_regs *)bank->fuse_regs;
+ int reg = readl(&fuse->gp1);
+ int ret;
+
+ switch (reg >> 8 & 0x0F) {
+ case 0x02:
+ ret = BOARD_REV_B;
+ break;
+ case 0x01:
+ default:
+ ret = BOARD_REV_A;
+ break;
+ }
+
+ return ret;
+}
+
+u32 get_board_rev(void)
+{
+ int rev = mx6sabre_rev();
+
+ return (get_cpu_rev() & ~(0xF << 8)) | rev;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED,
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+#ifdef CONFIG_VIDEO_IPUV3
+ setup_display();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ /* I2C 3 Steer */
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
+ imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
+#ifndef CONFIG_SYS_FLASH_CFI
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+#endif
+ gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+ imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
+
+ setup_iomux_eimnor();
+ return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
+int power_init_board(void)
+{
+ struct pmic *p;
+
+ p = pfuze_common_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ int rev = mx6sabre_rev();
+ char *revname;
+
+ switch (rev) {
+ case BOARD_REV_B:
+ revname = "B";
+ break;
+ case BOARD_REV_A:
+ default:
+ revname = "A";
+ break;
+ }
+
+ printf("Board: MX6Q-Sabreauto rev%s\n", revname);
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
+#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
+
+iomux_v3_cfg_t const usb_otg_pads[] = {
+ MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+ switch (port) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+
+ /*
+ * Set daisy chain for otg_pin_id on 6q.
+ * For 6dl, this bit is reserved.
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 0);
+ break;
+ case 1:
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ switch (port) {
+ case 0:
+ if (on)
+ port_exp_direction_output(USB_OTG_PWR, 1);
+ else
+ port_exp_direction_output(USB_OTG_PWR, 0);
+ break;
+ case 1:
+ if (on)
+ port_exp_direction_output(USB_HOST1_PWR, 1);
+ else
+ port_exp_direction_output(USB_HOST1_PWR, 0);
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/mx6sabresd/Kconfig b/board/freescale/mx6sabresd/Kconfig
new file mode 100644
index 0000000..fa6ddb2
--- /dev/null
+++ b/board/freescale/mx6sabresd/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX6SABRESD
+
+config SYS_BOARD
+ default "mx6sabresd"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "mx6sabresd"
+
+endif
diff --git a/board/freescale/mx6sabresd/MAINTAINERS b/board/freescale/mx6sabresd/MAINTAINERS
new file mode 100644
index 0000000..0011ec7
--- /dev/null
+++ b/board/freescale/mx6sabresd/MAINTAINERS
@@ -0,0 +1,8 @@
+MX6SABRESD BOARD
+M: Fabio Estevam <fabio.estevam@freescale.com>
+S: Maintained
+F: board/freescale/mx6sabresd/
+F: include/configs/mx6sabresd.h
+F: configs/mx6dlsabresd_defconfig
+F: configs/mx6qsabresd_defconfig
+F: configs/mx6sabresd_spl_defconfig
diff --git a/board/freescale/mx6sabresd/Makefile b/board/freescale/mx6sabresd/Makefile
new file mode 100644
index 0000000..cfca2ef
--- /dev/null
+++ b/board/freescale/mx6sabresd/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6sabresd.o
diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
new file mode 100644
index 0000000..f35f22e
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x020e0774 0x000C0000
+DATA 4 0x020e0754 0x00000000
+DATA 4 0x020e04ac 0x00000030
+DATA 4 0x020e04b0 0x00000030
+DATA 4 0x020e0464 0x00000030
+DATA 4 0x020e0490 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0494 0x00000030
+DATA 4 0x020e04a0 0x00000000
+DATA 4 0x020e04b4 0x00000030
+DATA 4 0x020e04b8 0x00000030
+DATA 4 0x020e076c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e04bc 0x00000030
+DATA 4 0x020e04c0 0x00000030
+DATA 4 0x020e04c4 0x00000030
+DATA 4 0x020e04c8 0x00000030
+DATA 4 0x020e04cc 0x00000030
+DATA 4 0x020e04d0 0x00000030
+DATA 4 0x020e04d4 0x00000030
+DATA 4 0x020e04d8 0x00000030
+DATA 4 0x020e0760 0x00020000
+DATA 4 0x020e0764 0x00000030
+DATA 4 0x020e0770 0x00000030
+DATA 4 0x020e0778 0x00000030
+DATA 4 0x020e077c 0x00000030
+DATA 4 0x020e0780 0x00000030
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e0470 0x00000030
+DATA 4 0x020e0474 0x00000030
+DATA 4 0x020e0478 0x00000030
+DATA 4 0x020e047c 0x00000030
+DATA 4 0x020e0480 0x00000030
+DATA 4 0x020e0484 0x00000030
+DATA 4 0x020e0488 0x00000030
+DATA 4 0x020e048c 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+DATA 4 0x021b083c 0x4220021F
+DATA 4 0x021b0840 0x0207017E
+DATA 4 0x021b483c 0x4201020C
+DATA 4 0x021b4840 0x01660172
+DATA 4 0x021b0848 0x4A4D4E4D
+DATA 4 0x021b4848 0x4A4F5049
+DATA 4 0x021b0850 0x3F3C3D31
+DATA 4 0x021b4850 0x3238372B
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x0002002D
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x3F435313
+DATA 4 0x021b0010 0xB66E8B63
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x00431023
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0x831A0000
+DATA 4 0x021b001c 0x04008032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x05208030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x0002556D
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
new file mode 100644
index 0000000..bb6c60b
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+
+DATA 4 0x020e05ac 0x00020030
+DATA 4 0x020e05b4 0x00020030
+DATA 4 0x020e0528 0x00020030
+DATA 4 0x020e0520 0x00020030
+
+DATA 4 0x020e0514 0x00020030
+DATA 4 0x020e0510 0x00020030
+DATA 4 0x020e05bc 0x00020030
+DATA 4 0x020e05c4 0x00020030
+
+DATA 4 0x020e056c 0x00020030
+DATA 4 0x020e0578 0x00020030
+DATA 4 0x020e0588 0x00020030
+DATA 4 0x020e0594 0x00020030
+
+DATA 4 0x020e057c 0x00020030
+DATA 4 0x020e0590 0x00003000
+DATA 4 0x020e0598 0x00003000
+DATA 4 0x020e058c 0x00000000
+
+DATA 4 0x020e059c 0x00003030
+DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0750 0x00020000
+
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0798 0x000C0000
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b0018 0x00081740
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b000c 0x555A7974
+DATA 4 0x021b0010 0xDB538F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b002c 0x000026D2
+
+DATA 4 0x021b0030 0x005A1023
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0x831A0000
+
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x0408803A
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x0000803B
+DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x00428039
+DATA 4 0x021b001c 0x19308030
+DATA 4 0x021b001c 0x19308038
+
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b001c 0x04008048
+DATA 4 0x021b0800 0xA1380003
+DATA 4 0x021b4800 0xA1380003
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b4818 0x00022227
+
+DATA 4 0x021b083c 0x434B0350
+DATA 4 0x021b0840 0x034C0359
+DATA 4 0x021b483c 0x434B0350
+DATA 4 0x021b4840 0x03650348
+DATA 4 0x021b0848 0x4436383B
+DATA 4 0x021b4848 0x39393341
+DATA 4 0x021b0850 0x35373933
+DATA 4 0x021b4850 0x48254A36
+
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+
+DATA 4 0x021b480c 0x00440044
+DATA 4 0x021b4810 0x00440044
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b001c 0x00000000
+DATA 4 0x021b0404 0x00011006
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4 0x020c4060 0x000000fb
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
new file mode 100644
index 0000000..2f7198d
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -0,0 +1,851 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <asm/arch/mx6-ddr.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC 1
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* AR8031 PHY Reset */
+ MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* Reset AR8031 PHY */
+ gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
+ udelay(500);
+ gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+}
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+ MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
+ gpio_direction_output(DISP0_PWR_EN, 1);
+}
+
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+
+iomux_v3_cfg_t const pcie_pads[] = {
+ MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
+};
+
+static void setup_pcie(void)
+{
+ imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
+iomux_v3_cfg_t const di0_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC2_BASE_ADDR},
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = 1; /* eMMC/uSDHC4 is always present */
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifndef CONFIG_SPL_BUILD
+ int ret;
+ int i;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 SD2
+ * mmc1 SD3
+ * mmc2 eMMC
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+#else
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned reg = readl(&psrc->sbmr1) >> 11;
+ /*
+ * Upon reading BOOT_CFG register the following map is done:
+ * Bit 11 and 12 of BOOT_CFG register can determine the current
+ * mmc port
+ * 0x1 SD1
+ * 0x2 SD2
+ * 0x3 SD4
+ */
+
+ switch (reg & 0x3) {
+ case 0x1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ case 0x2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ case 0x3:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ }
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+#endif
+}
+#endif
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static void disable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ int reg = readl(&iomux->gpr[2]);
+
+ reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+ IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+
+ writel(reg, &iomux->gpr[2]);
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ disable_lvds(dev);
+ imx_enable_hdmi_phy();
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)
+ IOMUXC_BASE_ADDR;
+ u32 reg = readl(&iomux->gpr[2]);
+ reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
+ writel(reg, &iomux->gpr[2]);
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = NULL,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "Hannstar-XGA",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 0,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "SEIKO-WVGA",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 29850,
+ .left_margin = 89,
+ .right_margin = 164,
+ .upper_margin = 23,
+ .lower_margin = 10,
+ .hsync_len = 10,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
+ imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
+ reg = readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+ | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+ | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
+ | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+ | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+ | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+ | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
+ | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
+ | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+ setup_pcie();
+
+ return cpu_eth_init(bis);
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usb_hc1_pads[] = {
+ MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+
+ /*
+ * set daisy chain for otg_pin_id on 6q.
+ * for 6dl, this bit is reserved
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 0);
+
+ imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
+ ARRAY_SIZE(usb_hc1_pads));
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ switch (port) {
+ case 0:
+ break;
+ case 1:
+ if (on)
+ gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
+ else
+ gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_MXC_SPI
+ setup_spi();
+#endif
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
+ return 0;
+}
+
+int power_init_board(void)
+{
+ struct pmic *p;
+ unsigned int reg;
+
+ p = pfuze_common_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
+
+ /* Increase VGEN3 from 2.5 to 2.8V */
+ pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
+ reg &= ~LDO_VOL_MASK;
+ reg |= LDOB_2_80V;
+ pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
+
+ /* Increase VGEN5 from 2.8 to 3V */
+ pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
+ reg &= ~LDO_VOL_MASK;
+ reg |= LDOB_3_00V;
+ pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+
+ return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ /* 8 bit bus width */
+ {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6-SabreSD\n");
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+
+const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_sdclk_0 = 0x00020030,
+ .dram_sdclk_1 = 0x00020030,
+ .dram_cas = 0x00020030,
+ .dram_ras = 0x00020030,
+ .dram_reset = 0x00020030,
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = 0x00003030,
+ .dram_sdodt1 = 0x00003030,
+ .dram_sdqs0 = 0x00000030,
+ .dram_sdqs1 = 0x00000030,
+ .dram_sdqs2 = 0x00000030,
+ .dram_sdqs3 = 0x00000030,
+ .dram_sdqs4 = 0x00000030,
+ .dram_sdqs5 = 0x00000030,
+ .dram_sdqs6 = 0x00000030,
+ .dram_sdqs7 = 0x00000030,
+ .dram_dqm0 = 0x00020030,
+ .dram_dqm1 = 0x00020030,
+ .dram_dqm2 = 0x00020030,
+ .dram_dqm3 = 0x00020030,
+ .dram_dqm4 = 0x00020030,
+ .dram_dqm5 = 0x00020030,
+ .dram_dqm6 = 0x00020030,
+ .dram_dqm7 = 0x00020030,
+};
+
+const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_ddr_type = 0x000C0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_b2ds = 0x00000030,
+ .grp_b3ds = 0x00000030,
+ .grp_b4ds = 0x00000030,
+ .grp_b5ds = 0x00000030,
+ .grp_b6ds = 0x00000030,
+ .grp_b7ds = 0x00000030,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x001F001F,
+ .p0_mpwldectrl1 = 0x001F001F,
+ .p1_mpwldectrl0 = 0x00440044,
+ .p1_mpwldectrl1 = 0x00440044,
+ .p0_mpdgctrl0 = 0x434B0350,
+ .p0_mpdgctrl1 = 0x034C0359,
+ .p1_mpdgctrl0 = 0x434B0350,
+ .p1_mpdgctrl1 = 0x03650348,
+ .p0_mprddlctl = 0x4436383B,
+ .p1_mprddlctl = 0x39393341,
+ .p0_mpwrdlctl = 0x35373933,
+ .p1_mpwrdlctl = 0x48254A36,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 64,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
+/*
+ * This section requires the differentiation between iMX6 Sabre boards, but
+ * for now, it will configure only for the mx6q variant.
+ */
+static void spl_dram_init(void)
+{
+ struct mx6_ddr_sysinfo sysinfo = {
+ /* width of data bus:0=16,1=32,2=64 */
+ .dsize = mem_ddr.width/32,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32, /* 32Gb per CS */
+ /* single chip select */
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
+#ifdef RTT_NOM_120OHM
+ .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
+#else
+ .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
+#endif
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ };
+
+ mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+ gpr_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
+#endif
diff --git a/board/freescale/mx6slevk/Kconfig b/board/freescale/mx6slevk/Kconfig
new file mode 100644
index 0000000..d32da90
--- /dev/null
+++ b/board/freescale/mx6slevk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX6SLEVK
+
+config SYS_BOARD
+ default "mx6slevk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "mx6slevk"
+
+endif
diff --git a/board/freescale/mx6slevk/MAINTAINERS b/board/freescale/mx6slevk/MAINTAINERS
new file mode 100644
index 0000000..18d31a8
--- /dev/null
+++ b/board/freescale/mx6slevk/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6SLEVK BOARD
+M: Fabio Estevam <fabio.estevam@freescale.com>
+S: Maintained
+F: board/freescale/mx6slevk/
+F: include/configs/mx6slevk.h
+F: configs/mx6slevk_defconfig
+F: configs/mx6slevk_spinor_defconfig
diff --git a/board/freescale/mx6slevk/Makefile b/board/freescale/mx6slevk/Makefile
new file mode 100644
index 0000000..6e1971e
--- /dev/null
+++ b/board/freescale/mx6slevk/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6slevk.o
diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg
new file mode 100644
index 0000000..16ea597
--- /dev/null
+++ b/board/freescale/mx6slevk/imximage.cfg
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x020c4018 0x00260324
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020e0344 0x00003030
+DATA 4 0x020e0348 0x00003030
+DATA 4 0x020e034c 0x00003030
+DATA 4 0x020e0350 0x00003030
+DATA 4 0x020e030c 0x00000030
+DATA 4 0x020e0310 0x00000030
+DATA 4 0x020e0314 0x00000030
+DATA 4 0x020e0318 0x00000030
+DATA 4 0x020e0300 0x00000030
+DATA 4 0x020e031c 0x00000030
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e0320 0x00000030
+DATA 4 0x020e032c 0x00000000
+DATA 4 0x020e033c 0x00000008
+DATA 4 0x020e0340 0x00000008
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x020e05cc 0x00000030
+DATA 4 0x020e05d4 0x00000030
+DATA 4 0x020e05d8 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05c8 0x00000030
+DATA 4 0x020e05b0 0x00020000
+DATA 4 0x020e05b4 0x00000000
+DATA 4 0x020e05c0 0x00020000
+DATA 4 0x020e05d0 0x00080000
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b085c 0x1b4700c7
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b0890 0x00300000
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b0834 0xf3333333
+DATA 4 0x021b0838 0xf3333333
+DATA 4 0x021b0848 0x4241444a
+DATA 4 0x021b0850 0x3030312b
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x00000000
+DATA 4 0x021b08c0 0x24911492
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b000c 0x33374133
+DATA 4 0x021b0004 0x00020024
+DATA 4 0x021b0010 0x00100A82
+DATA 4 0x021b0014 0x00000093
+DATA 4 0x021b0018 0x00001688
+DATA 4 0x021b002c 0x0f9f26d2
+DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0038 0x00190778
+DATA 4 0x021b0008 0x00000000
+DATA 4 0x021b0040 0x0000004f
+DATA 4 0x021b0000 0xc3110000
+DATA 4 0x021b001c 0x003f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0x82018030
+DATA 4 0x021b001c 0x04028030
+DATA 4 0x021b001c 0x02038030
+DATA 4 0x021b001c 0xff0a8038
+DATA 4 0x021b001c 0x82018038
+DATA 4 0x021b001c 0x04028038
+DATA 4 0x021b001c 0x02038038
+DATA 4 0x021b0800 0xa1310003
+DATA 4 0x021b0020 0x00001800
+DATA 4 0x021b0818 0x00000000
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b0004 0x00025564
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
new file mode 100644
index 0000000..838ea6c
--- /dev/null
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/spi.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ /* 8 bit SD */
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /*CD pin*/
+ MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /*CD pin*/
+ MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /*CD pin*/
+ MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec_pads[] = {
+ MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_MXC_SPI
+static iomux_v3_cfg_t ecspi1_pads[] = {
+ MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
+}
+
+static void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static void setup_iomux_fec(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+
+ /* Reset LAN8720 PHY */
+ gpio_direction_output(ETH_PHY_RESET , 0);
+ udelay(1000);
+ gpio_set_value(ETH_PHY_RESET, 1);
+}
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
+#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC1_BASE_ADDR},
+ {USDHC2_BASE_ADDR, 0, 4},
+ {USDHC3_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ * mmc2 USDHC3
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize "
+ "mmc dev %d\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_fec();
+
+ return cpu_eth_init(bis);
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* clear gpr1[14], gpr1[18:17] to select anatop clock */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
+
+ return enable_fec_anatop_clock(ENET_50MHZ);
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ /* OTG1 */
+ MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG2 */
+ MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+#ifdef CONFIG_MXC_SPI
+ setup_spi();
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6SLEVK\n");
+
+ return 0;
+}
diff --git a/board/freescale/mx6sxsabresd/Kconfig b/board/freescale/mx6sxsabresd/Kconfig
new file mode 100644
index 0000000..940983e
--- /dev/null
+++ b/board/freescale/mx6sxsabresd/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX6SXSABRESD
+
+config SYS_BOARD
+ default "mx6sxsabresd"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "mx6sxsabresd"
+
+endif
diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS b/board/freescale/mx6sxsabresd/MAINTAINERS
new file mode 100644
index 0000000..f52f300
--- /dev/null
+++ b/board/freescale/mx6sxsabresd/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6SXSABRESD BOARD
+M: Fabio Estevam <fabio.estevam@freescale.com>
+S: Maintained
+F: board/freescale/mx6sxsabresd/
+F: include/configs/mx6sxsabresd.h
+F: configs/mx6sxsabresd_defconfig
diff --git a/board/freescale/mx6sxsabresd/Makefile b/board/freescale/mx6sxsabresd/Makefile
new file mode 100644
index 0000000..97dbfda
--- /dev/null
+++ b/board/freescale/mx6sxsabresd/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6sxsabresd.o
diff --git a/board/freescale/mx6sxsabresd/imximage.cfg b/board/freescale/mx6sxsabresd/imximage.cfg
new file mode 100644
index 0000000..c862617
--- /dev/null
+++ b/board/freescale/mx6sxsabresd/imximage.cfg
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+
+/* Clock */
+DATA 4 0x020e032c 0x00000030
+
+/* Address */
+DATA 4 0x020e0300 0x00000020
+DATA 4 0x020e02fc 0x00000020
+DATA 4 0x020e05f4 0x00000020
+
+/* Control */
+DATA 4 0x020e0340 0x00000020
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000020
+DATA 4 0x020e0314 0x00000020
+DATA 4 0x020e0614 0x00000020
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000028
+DATA 4 0x020e0334 0x00000028
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e033c 0x00000028
+
+/* Data */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000028
+DATA 4 0x020e0610 0x00000028
+DATA 4 0x020e061c 0x00000028
+DATA 4 0x020e0620 0x00000028
+DATA 4 0x020e02ec 0x00000028
+DATA 4 0x020e02f0 0x00000028
+DATA 4 0x020e02f4 0x00000028
+DATA 4 0x020e02f8 0x00000028
+
+/* Calibrations - ZQ */
+DATA 4 0x021b0800 0xa1390003
+
+/* Write leveling */
+DATA 4 0x021b080c 0x00290025
+DATA 4 0x021b0810 0x00220022
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x41480144
+DATA 4 0x021b0840 0x01340130
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x3C3E4244
+DATA 4 0x021b0850 0x34363638
+
+/* Read data bit delay */
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676b52f3
+DATA 4 0x021b0010 0xb66d8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000005f
+DATA 4 0x021b0000 0x84190000
+
+/* Initialize MT41K256M16HA-125 - MR2 */
+DATA 4 0x021b001c 0x04008032
+/* MR3 */
+DATA 4 0x021b001c 0x00008033
+/* MR1 */
+DATA 4 0x021b001c 0x00048031
+/* MR0 */
+DATA 4 0x021b001c 0x05208030
+/* DDR device ZQ calibration */
+DATA 4 0x021b001c 0x04008040
+
+/* Final DDR setup, before operation start */
+DATA 4 0x021b0020 0x00000800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b001c 0x00000000
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
new file mode 100644
index 0000000..5cc58ac
--- /dev/null
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -0,0 +1,436 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-fsl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /* CD pin */
+ MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* RST_B, used for power reset cycle */
+ MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+ MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const peri_3v3_pads[] = {
+ MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const phy_control_pads[] = {
+ /* 25MHz Ethernet PHY Clock */
+ MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+
+ /* ENET PHY Power */
+ MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* AR8031 PHY Reset */
+ MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ int reg;
+
+ /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
+
+ imx_iomux_v3_setup_multiple_pads(phy_control_pads,
+ ARRAY_SIZE(phy_control_pads));
+
+ /* Enable the ENET power, active low */
+ gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
+
+ /* Reset AR8031 PHY */
+ gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
+ udelay(500);
+ gpio_set_value(IMX_GPIO_NR(2, 7), 1);
+
+ reg = readl(&anatop->pll_enet);
+ reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
+ writel(reg, &anatop->pll_enet);
+
+ return enable_fec_anatop_clock(ENET_125MHZ);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+ setup_fec();
+
+ return cpu_eth_init(bis);
+}
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+ .gp = IMX_GPIO_NR(1, 0),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+ .gp = IMX_GPIO_NR(1, 1),
+ },
+};
+
+int power_init_board(void)
+{
+ struct pmic *p;
+ unsigned int reg;
+
+ p = pfuze_common_init(I2C_PMIC);
+ if (!p)
+ return -ENODEV;
+
+ /* Enable power of VGEN5 3V3, needed for SD3 */
+ pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
+ reg &= ~LDO_VOL_MASK;
+ reg |= (LDOB_3_30V | (1 << LDO_EN));
+ pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET 0x800
+#define UCTRL_PWR_POL (1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+ /* OGT1 */
+ MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG2 */
+ MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+ if (port == 1)
+ return USB_INIT_HOST;
+ else
+ return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ u32 *usbnc_usb_ctrl;
+
+ if (port > 1)
+ return -EINVAL;
+
+ usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+ port * 4);
+
+ /* Set Power polarity */
+ setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+ return 0;
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /*
+ * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+ * Phy control debug reg 0
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ /* rgmii tx clock delay enable */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
+ imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
+ ARRAY_SIZE(peri_3v3_pads));
+
+ /* Active high for ncp692 */
+ gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
+
+#ifdef CONFIG_USB_EHCI_MX6
+ setup_usb();
+#endif
+
+ return 0;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC2_BASE_ADDR, 0, 4},
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
+#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = 1; /* Assume uSDHC2 is always present */
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = !gpio_get_value(USDHC4_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC2
+ * mmc1 USDHC3
+ * mmc2 USDHC4
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ gpio_direction_output(USDHC3_PWR_GPIO, 1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ gpio_direction_input(USDHC4_CD_GPIO);
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize mmc dev %d\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+ MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA07__QSPI2_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+ /* Set the iomux */
+ imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+ ARRAY_SIZE(quadspi_pads));
+
+ /* Set the clock */
+ enable_qspi_clk(1);
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_MXC
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+ board_qspi_init();
+#endif
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6SX SABRE SDB\n");
+
+ return 0;
+}
diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig
new file mode 100644
index 0000000..b0a7a8d
--- /dev/null
+++ b/board/freescale/p1010rdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P1010RDB
+
+config SYS_BOARD
+ default "p1010rdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "P1010RDB"
+
+endif
diff --git a/board/freescale/p1010rdb/MAINTAINERS b/board/freescale/p1010rdb/MAINTAINERS
new file mode 100644
index 0000000..db00143
--- /dev/null
+++ b/board/freescale/p1010rdb/MAINTAINERS
@@ -0,0 +1,33 @@
+P1010RDB BOARD
+#M: -
+S: Maintained
+F: board/freescale/p1010rdb/
+F: include/configs/P1010RDB.h
+F: configs/P1010RDB-PA_36BIT_NAND_defconfig
+F: configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+F: configs/P1010RDB-PA_36BIT_NOR_defconfig
+F: configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+F: configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+F: configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+F: configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+F: configs/P1010RDB-PA_NAND_defconfig
+F: configs/P1010RDB-PA_NAND_SECBOOT_defconfig
+F: configs/P1010RDB-PA_NOR_defconfig
+F: configs/P1010RDB-PA_NOR_SECBOOT_defconfig
+F: configs/P1010RDB-PA_SDCARD_defconfig
+F: configs/P1010RDB-PA_SPIFLASH_defconfig
+F: configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
+F: configs/P1010RDB-PB_36BIT_NAND_defconfig
+F: configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+F: configs/P1010RDB-PB_36BIT_NOR_defconfig
+F: configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+F: configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+F: configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+F: configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+F: configs/P1010RDB-PB_NAND_defconfig
+F: configs/P1010RDB-PB_NAND_SECBOOT_defconfig
+F: configs/P1010RDB-PB_NOR_defconfig
+F: configs/P1010RDB-PB_NOR_SECBOOT_defconfig
+F: configs/P1010RDB-PB_SDCARD_defconfig
+F: configs/P1010RDB-PB_SPIFLASH_defconfig
+F: configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
new file mode 100644
index 0000000..660d1bb
--- /dev/null
+++ b/board/freescale/p1010rdb/Makefile
@@ -0,0 +1,30 @@
+#
+# Copyright 2010-2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y += spl_minimal.o tlb.o law.o
+
+else
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
+obj-y += p1010rdb.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
+
+endif
diff --git a/board/freescale/p1010rdb/README.P1010RDB-PA b/board/freescale/p1010rdb/README.P1010RDB-PA
new file mode 100644
index 0000000..cde246d
--- /dev/null
+++ b/board/freescale/p1010rdb/README.P1010RDB-PA
@@ -0,0 +1,208 @@
+Overview
+=========
+The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
+
+The P1010 is a cost-effective, low-power, highly integrated host processor
+based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
+that addresses the requirements of several routing, gateways, storage, consumer,
+and industrial applications. Applications of interest include the main CPUs and
+I/O processors in network attached storage (NAS), the voice over IP (VoIP)
+router/gateway, and wireless LAN (WLAN) and industrial controllers.
+
+The P1010RDB board features are as follows:
+Memory subsystem:
+ - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+ - 32 Mbyte NOR flash single-chip memory
+ - 32 Mbyte NAND flash memory
+ - 256 Kbit M24256 I2C EEPROM
+ - 16 Mbyte SPI memory
+ - I2C Board EEPROM 128x8 bit memory
+ - SD/MMC connector to interface with the SD memory card
+Interfaces:
+ - PCIe:
+ - Lane0: x1 mini-PCIe slot
+ - Lane1: x1 PCIe standard slot
+ - SATA:
+ - 1 internal SATA connector to 2.5” 160G SATA2 HDD
+ - 1 eSATA connector to rear panel
+ - 10/100/1000 BaseT Ethernet ports:
+ - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
+ - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
+ - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
+ - USB 2.0 port:
+ - x1 USB2.0 port via an external ULPI PHY to micro-AB connector
+ - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector
+ - FlexCAN ports:
+ - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
+ interface;
+ - DUART interface:
+ - DUART interface: supports two UARTs up to 115200 bps for
+ console display
+ - RJ45 connectors are used for these 2 UART ports.
+ - TDM
+ - 2 FXS ports connected via an external SLIC to the TDM interface.
+ SLIC is controllled via SPI.
+ - 1 FXO port connected via a relay to FXS for switchover to POTS
+Board connectors:
+ - Mini-ITX power supply connector
+ - JTAG/COP for debugging
+IEEE Std. 1588 signals for test and measurement
+Real-time clock on I2C bus
+POR
+ - support critical POR setting changed via switch on board
+PCB
+ - 6-layer routing (4-layer signals, 2-layer power and ground)
+
+
+Physical Memory Map on P1010RDB
+===============================
+Address Start Address End Memory type Attributes
+0x0000_0000 0x3fff_ffff DDR 1G Cacheable
+0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
+0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
+0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
+0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
+0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
+0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
+0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+
+
+Serial Port Configuration on P1010RDB
+=====================================
+Configure the serial port of the attached computer with the following values:
+ -Data rate: 115200 bps
+ -Number of data bits: 8
+ -Parity: None
+ -Number of Stop bits: 1
+ -Flow Control: Hardware/None
+
+
+Settings of DIP-switch
+======================
+ SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
+ SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
+ SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
+Note: 1 stands for 'on', 0 stands for 'off'
+
+
+Setting of hwconfig
+===================
+If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
+"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
+setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
+By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
+is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
+instead of to CAN/UART1.
+
+
+Build and burn u-boot to NOR flash
+==================================
+1. Build u-boot.bin image
+ export ARCH=powerpc
+ export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+ make P1010RDB_NOR
+
+2. Burn u-boot.bin into NOR flash
+ => tftp $loadaddr $uboot
+ => protect off eff40000 +$filesize
+ => erase eff40000 +$filesize
+ => cp.b $loadaddr eff40000 $filesize
+
+3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
+
+
+Alternate NOR bank
+==================
+1. Burn u-boot.bin into alternate NOR bank
+ => tftp $loadaddr $uboot
+ => protect off eef40000 +$filesize
+ => erase eef40000 +$filesize
+ => cp.b $loadaddr eef40000 $filesize
+
+2. Switch to alternate NOR bank
+ => mw.b ffb00009 1
+ => reset
+ or set SW1[8]= ON
+
+SW1[8]= OFF: Upper bank used for booting start
+SW1[8]= ON: Lower bank used for booting start
+CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
+0 - boot from upper 4 sectors
+1 - boot from lower 4 sectors
+
+
+Build and burn u-boot to NAND flash
+===================================
+1. Build u-boot.bin image
+ export ARCH=powerpc
+ export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+ make P1010RDB_NAND
+
+2. Burn u-boot-nand.bin into NAND flash
+ => tftp $loadaddr $uboot-nand
+ => nand erase 0 $filesize
+ => nand write $loadaddr 0 $filesize
+
+3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
+
+
+Build and burn u-boot to SPI flash
+==================================
+1. Build u-boot-spi.bin image
+ make P1010RDB_SPIFLASH_config; make
+ Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
+ Download u-boot.bin to linux and you can find some config files
+ under /usr/share such as config_xx.dat. Do below command:
+ boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
+ u-boot-spi.bin
+ to generate u-boot-spi.bin.
+
+2. Burn u-boot-spi.bin into SPI flash
+ => tftp $loadaddr $uboot-spi
+ => sf erase 0 100000
+ => sf write $loadaddr 0 $filesize
+
+3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
+
+
+CPLD POR setting registers
+==========================
+1. Set POR switch selection register (addr 0xFFB00011) to 0.
+2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
+ proper values.
+ If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
+ switch command by I2C.
+3. Send reset command.
+ After reset, the new POR setting will be implemented.
+
+Two examples are given in below:
+Switch from NOR to NAND boot with default frequency:
+ => i2c dev 0
+ => i2c mw 18 1 f9
+ => i2c mw 18 3 f0
+ => mw.b ffb00011 0
+ => mw.b ffb00017 1
+ => reset
+Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
+ => i2c dev 0
+ => i2c mw 18 1 f1
+ => i2c mw 18 3 f0
+ => mw.b ffb00011 0
+ => mw.b ffb00014 2
+ => mw.b ffb00015 5
+ => mw.b ffb00016 3
+ => mw.b ffb00017 f
+ => reset
+
+
+Boot Linux from network using TFTP on P1010RDB
+==============================================
+Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
+ => tftp 1000000 uImage
+ => tftp 2000000 p1010rdb.dtb
+ => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
+ => bootm 1000000 3000000 2000000
+
+
+For more details, please refer to P1010RDB User Guide and access website
+www.freescale.com
diff --git a/board/freescale/p1010rdb/README.P1010RDB-PB b/board/freescale/p1010rdb/README.P1010RDB-PB
new file mode 100644
index 0000000..c5d1419
--- /dev/null
+++ b/board/freescale/p1010rdb/README.P1010RDB-PB
@@ -0,0 +1,188 @@
+Overview
+=========
+The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
+P1010RDB-PB is a variation of previous P1010RDB-PA board.
+
+The P1010 is a cost-effective, low-power, highly integrated host processor
+based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
+addresses the requirements of several routing, gateways, storage, consumer,
+and industrial applications. Applications of interest include the main CPUs and
+I/O processors in network attached storage (NAS), the voice over IP (VoIP)
+router/gateway, and wireless LAN (WLAN) and industrial controllers.
+
+The P1010RDB-PB board features are as following:
+Memory subsystem:
+ - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+ - 32M bytes NOR flash single-chip memory
+ - 2G bytes NAND flash memory
+ - 16M bytes SPI memory
+ - 256K bit M24256 I2C EEPROM
+ - I2C Board EEPROM 128x8 bit memory
+ - SD/MMC connector to interface with the SD memory card
+Interfaces:
+ - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
+ - PCIe 2.0: two x1 mini-PCIe slots
+ - SATA 2.0: two SATA interfaces
+ - USB 2.0: one USB interface
+ - FlexCAN: two FlexCAN interfaces (revision 2.0B)
+ - UART: one USB-to-Serial interface
+ - TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
+ 1 FXO port connected via a relay to FXS for switchover to POTS
+
+Board connectors:
+ - Mini-ITX power supply connector
+ - JTAG/COP for debugging
+
+POR: support critical POR setting changed via switch on board
+PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
+
+Physical Memory Map on P1010RDB
+===============================
+Address Start Address End Memory type Attributes
+0x0000_0000 0x3fff_ffff DDR 1G Cacheable
+0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
+0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
+0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
+0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
+0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
+0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
+0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+
+
+Serial Port Configuration on P1010RDB
+=====================================
+Configure the serial port of the attached computer with the following values:
+ -Data rate: 115200 bps
+ -Number of data bits: 8
+ -Parity: None
+ -Number of Stop bits: 1
+ -Flow Control: Hardware/None
+
+
+P1010RDB-PB default DIP-switch settings
+=======================================
+SW1[1:8]= 10101010
+SW2[1:8]= 11011000
+SW3[1:8]= 10010000
+SW4[1:4]= 1010
+SW5[1:8]= 11111010
+
+
+P1010RDB-PB boot mode settings via DIP-switch
+=============================================
+SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
+SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
+SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
+SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
+Note: 1 stands for 'on', 0 stands for 'off'
+
+
+Switch P1010RDB-PB boot mode via software without setting DIP-switch
+====================================================================
+=> run boot_bank0 (boot from NOR bank0)
+=> run boot_bank1 (boot from NOR bank1)
+=> run boot_nand (boot from NAND flash)
+=> run boot_spi (boot from SPI flash)
+=> run boot_sd (boot from SD card)
+
+
+Frequency combination support on P1010RDB-PB
+=============================================
+SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
+0101 1 1010 0 800 400 800
+1001 1 1010 0 800 400 667
+1010 1 1100 0 667 333 667
+1000 0 1010 0 533 266 667
+0101 1 1010 1 1000 400 800
+1001 1 1010 1 1000 400 667
+
+
+Setting of pin mux
+==================
+Since pins multiplexing, TDM and CAN are muxed with SPI flash.
+SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
+
+To enable TDM:
+=> setenv hwconfig fsl_p1010mux:tdm_can=tdm
+=> save;reset
+
+To enable FlexCAN:
+=> setenv hwconfig fsl_p1010mux:tdm_can=can
+=> save;reset
+
+To enable SDHC in case of NOR/NAND/SPI boot
+ a) For temporary use case in runtime without reboot system
+ run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC.
+
+ b) For long-term use case
+ set 'esdhc' in hwconfig and save it.
+
+To enable IFC in case of SD boot
+ a) For temporary use case in runtime without reboot system
+ run 'mux ifc' in u-boot to validate IFC with invalidating SDHC.
+
+ b) For long-term use case
+ set 'ifc' in hwconfig and save it.
+
+
+Build images for different boot mode
+====================================
+First setup cross compile environment on build host
+ $ export ARCH=powerpc
+ $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
+
+1. For NOR boot
+ $ make P1010RDB-PB_NOR
+
+2. For NAND boot
+ $ make P1010RDB-PB_NAND
+
+3. For SPI boot
+ $ make P1010RDB-PB_SPIFLASH
+
+4. For SD boot
+ $ make P1010RDB-PB_SDCARD
+
+
+Steps to program images to flash for different boot mode
+========================================================
+1. NOR boot
+ => tftp 1000000 u-boot.bin
+ For bank0
+ => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+ set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
+
+ For bank1
+ => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize
+ set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
+
+2. NAND boot
+ => tftp 1000000 u-boot-nand.bin
+ => nand erase 0 $filesize; nand write $loadaddr 0 $filesize
+ Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
+
+3. SPI boot
+ 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin
+ 2) => tftp 1000000 u-boot-spi-combined.bin
+ 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000
+ set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
+
+4. SD boot
+ 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin
+ 2) => tftp 1000000 u-boot-sd-combined.bin
+ 3) => mux sdhc
+ 4) => mmc write 1000000 0 1050
+ set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
+
+
+Boot Linux from network using TFTP on P1010RDB-PB
+=================================================
+Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path.
+ => tftp 1000000 uImage
+ => tftp 2000000 p1010rdb.dtb
+ => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
+ => bootm 1000000 3000000 2000000
+
+
+For more details, please refer to P1010RDB-PB User Guide and access website
+www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
new file mode 100644
index 0000000..b0d95ea
--- /dev/null
+++ b/board/freescale/p1010rdb/ddr.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_DRAM_SIZE 1024
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_667,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+ {750, 850, &ddr_cfg_regs_800},
+ {607, 749, &ddr_cfg_regs_667},
+ {0, 0, NULL}
+};
+
+unsigned long get_sdram_size(void)
+{
+ struct cpu_type *cpu;
+ phys_size_t ddr_size;
+
+ cpu = gd->arch.cpu;
+ /* P1014 and it's derivatives support max 16it DDR width */
+ if (cpu->soc_ver == SVR_P1014)
+ ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
+ else
+ ddr_size = CONFIG_SYS_DRAM_SIZE;
+
+ return ddr_size;
+}
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+phys_size_t fixed_sdram(void)
+{
+ int i;
+ char buf[32];
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
+ phys_size_t ddr_size;
+ ulong ddr_freq, ddr_freq_mhz;
+ struct cpu_type *cpu;
+
+#if defined(CONFIG_SYS_RAMBOOT)
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+#endif
+
+ ddr_freq = get_ddr_freq(0);
+ ddr_freq_mhz = ddr_freq / 1000000;
+
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+ if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+ (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+ memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
+ sizeof(ddr_cfg_regs));
+ break;
+ }
+ }
+
+ if (fixed_ddr_parm_0[i].max_freq == 0)
+ panic("Unsupported DDR data rate %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ cpu = gd->arch.cpu;
+ /* P1014 and it's derivatives support max 16bit DDR width */
+ if (cpu->soc_ver == SVR_P1014) {
+ ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
+ ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
+ /* divide SA and EA by two and then mask the rest so we don't
+ * write to reserved fields */
+ ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff;
+ }
+
+ ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
+ LAW_TRGT_IF_DDR_1) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+
+ return ddr_size;
+}
+
+#else /* CONFIG_SYS_DDR_RAW_TIMING */
+/*
+ * Samsung K4B2G0846C-HCF8
+ * The following timing are for "downshift"
+ * i.e. to use CL9 part as CL7
+ * otherwise, tAA, tRCD, tRP will be 13500ps
+ * and tRC will be 49500ps
+ */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 1073741824u,
+ .capacity = 1073741824u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1875,
+ .caslat_x = 0x1e << 4, /* 5,6,7,8 */
+ .taa_ps = 13125,
+ .twr_ps = 15000,
+ .trcd_ps = 13125,
+ .trrd_ps = 7500,
+ .trp_ps = 13125,
+ .tras_ps = 37500,
+ .trc_ps = 50625,
+ .trfc_ps = 160000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ struct cpu_type *cpu;
+ int i;
+ popts->clk_adjust = 6;
+ popts->cpo_override = 0x1f;
+ popts->write_data_delay = 2;
+ popts->half_strength_driver_enable = 1;
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x8;
+ popts->trwt_override = 1;
+ popts->trwt = 0;
+
+ cpu = gd->arch.cpu;
+ /* P1014 and it's derivatives support max 16it DDR width */
+ if (cpu->soc_ver == SVR_P1014)
+ popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+ popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+ }
+}
+
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c
new file mode 100644
index 0000000..ed41a05
--- /dev/null
+++ b/board/freescale/p1010rdb/law.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
new file mode 100644
index 0000000..1cf0ab7
--- /dev/null
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -0,0 +1,572 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <pci.h>
+#include <asm/fsl_serdes.h>
+#include <fsl_ifc.h>
+#include <asm/fsl_pci.h>
+#include <hwconfig.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO4_PCIE_RESET_SET 0x08000000
+#define MUX_CPLD_CAN_UART 0x00
+#define MUX_CPLD_TDM 0x01
+#define MUX_CPLD_SPICS0_FLASH 0x00
+#define MUX_CPLD_SPICS0_SLIC 0x02
+#define PMUXCR1_IFC_MASK 0x00ffff00
+#define PMUXCR1_SDHC_MASK 0x00fff000
+#define PMUXCR1_SDHC_ENABLE 0x00555000
+
+enum {
+ MUX_TYPE_IFC,
+ MUX_TYPE_SDHC,
+ MUX_TYPE_SPIFLASH,
+ MUX_TYPE_TDM,
+ MUX_TYPE_CAN,
+ MUX_TYPE_CS0_NOR,
+ MUX_TYPE_CS0_NAND,
+};
+
+enum {
+ I2C_READ_BANK,
+ I2C_READ_PCB_VER,
+};
+
+static uint sd_ifc_mux;
+
+struct cpld_data {
+ u8 cpld_ver; /* cpld revision */
+#if defined(CONFIG_P1010RDB_PA)
+ u8 pcba_ver; /* pcb revision number */
+ u8 twindie_ddr3;
+ u8 res1[6];
+ u8 bank_sel; /* NOR Flash bank */
+ u8 res2[5];
+ u8 usb2_sel;
+ u8 res3[1];
+ u8 porsw_sel;
+ u8 tdm_can_sel;
+ u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
+ u8 por0; /* POR Options */
+ u8 por1; /* POR Options */
+ u8 por2; /* POR Options */
+ u8 por3; /* POR Options */
+#elif defined(CONFIG_P1010RDB_PB)
+ u8 rom_loc;
+#endif
+};
+
+int board_early_init_f(void)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+ /* Clock configuration to access CPLD using IFC(GPCM) */
+ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+ /*
+ * Reset PCIe slots via GPIO4
+ */
+ setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
+ setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_16M, 1);
+
+ set_tlb(1, flashbase + 0x1000000,
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif /* ifdef CONFIG_PCI */
+
+int config_board_mux(int ctrl_type)
+{
+ ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u8 tmp;
+
+#if defined(CONFIG_P1010RDB_PA)
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ switch (ctrl_type) {
+ case MUX_TYPE_IFC:
+ i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+ tmp = 0xf0;
+ i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
+ tmp = 0x01;
+ i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
+ sd_ifc_mux = MUX_TYPE_IFC;
+ clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+ break;
+ case MUX_TYPE_SDHC:
+ i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+ tmp = 0xf0;
+ i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
+ tmp = 0x05;
+ i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
+ sd_ifc_mux = MUX_TYPE_SDHC;
+ clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+ PMUXCR1_SDHC_ENABLE);
+ break;
+ case MUX_TYPE_SPIFLASH:
+ out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
+ break;
+ case MUX_TYPE_TDM:
+ out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
+ out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
+ break;
+ case MUX_TYPE_CAN:
+ out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
+ break;
+ default:
+ break;
+ }
+#elif defined(CONFIG_P1010RDB_PB)
+ uint orig_bus = i2c_get_bus_num();
+ i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+
+ switch (ctrl_type) {
+ case MUX_TYPE_IFC:
+ i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+ clrbits_8(&tmp, 0x04);
+ i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+ i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ clrbits_8(&tmp, 0x04);
+ i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ sd_ifc_mux = MUX_TYPE_IFC;
+ clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
+ break;
+ case MUX_TYPE_SDHC:
+ i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+ setbits_8(&tmp, 0x04);
+ i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+ i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ clrbits_8(&tmp, 0x04);
+ i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ sd_ifc_mux = MUX_TYPE_SDHC;
+ clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
+ PMUXCR1_SDHC_ENABLE);
+ break;
+ case MUX_TYPE_SPIFLASH:
+ i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+ clrbits_8(&tmp, 0x80);
+ i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+ i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ clrbits_8(&tmp, 0x80);
+ i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ break;
+ case MUX_TYPE_TDM:
+ i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+ setbits_8(&tmp, 0x82);
+ i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+ i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ clrbits_8(&tmp, 0x82);
+ i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ break;
+ case MUX_TYPE_CAN:
+ i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+ clrbits_8(&tmp, 0x02);
+ i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+ i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ clrbits_8(&tmp, 0x02);
+ i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ break;
+ case MUX_TYPE_CS0_NOR:
+ i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+ clrbits_8(&tmp, 0x08);
+ i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+ i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ clrbits_8(&tmp, 0x08);
+ i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ break;
+ case MUX_TYPE_CS0_NAND:
+ i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
+ setbits_8(&tmp, 0x08);
+ i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
+ i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ clrbits_8(&tmp, 0x08);
+ i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
+ break;
+ default:
+ break;
+ }
+ i2c_set_bus_num(orig_bus);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_P1010RDB_PB
+int i2c_pca9557_read(int type)
+{
+ u8 val;
+
+ i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+ i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
+
+ switch (type) {
+ case I2C_READ_BANK:
+ val = (val & 0x10) >> 4;
+ break;
+ case I2C_READ_PCB_VER:
+ val = ((val & 0x60) >> 5) + 1;
+ break;
+ default:
+ break;
+ }
+
+ return val;
+}
+#endif
+
+int checkboard(void)
+{
+ struct cpu_type *cpu;
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ u8 val;
+
+ cpu = gd->arch.cpu;
+#if defined(CONFIG_P1010RDB_PA)
+ printf("Board: %sRDB-PA, ", cpu->name);
+#elif defined(CONFIG_P1010RDB_PB)
+ printf("Board: %sRDB-PB, ", cpu->name);
+ i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
+ i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
+ val = 0x0; /* no polarity inversion */
+ i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
+#endif
+
+#ifdef CONFIG_SDCARD
+ /* switch to IFC to read info from CPLD */
+ config_board_mux(MUX_TYPE_IFC);
+#endif
+
+#if defined(CONFIG_P1010RDB_PA)
+ val = (in_8(&cpld_data->pcba_ver) & 0xf);
+ printf("PCB: v%x.0\n", val);
+#elif defined(CONFIG_P1010RDB_PB)
+ val = in_8(&cpld_data->cpld_ver);
+ printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
+ printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
+ val = in_8(&cpld_data->rom_loc) & 0xf;
+ puts("Boot from: ");
+ switch (val) {
+ case 0xf:
+ config_board_mux(MUX_TYPE_CS0_NOR);
+ printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
+ break;
+ case 0xe:
+ puts("SDHC\n");
+ val = 0x60; /* set pca9557 pin input/output */
+ i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
+ break;
+ case 0x5:
+ config_board_mux(MUX_TYPE_IFC);
+ config_board_mux(MUX_TYPE_CS0_NAND);
+ puts("NAND\n");
+ break;
+ case 0x6:
+ config_board_mux(MUX_TYPE_IFC);
+ puts("SPI\n");
+ break;
+ default:
+ puts("unknown\n");
+ break;
+ }
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ struct cpu_type *cpu;
+ int num = 0;
+
+ cpu = gd->arch.cpu;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ /* P1014 and it's derivatives do not support eTSEC3 */
+ if (cpu->soc_ver != SVR_P1014) {
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ num++;
+ }
+#endif
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void fdt_del_flexcan(void *blob)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "fsl,p1010-flexcan")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+}
+
+void fdt_del_spi_flash(void *blob)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "spansion,s25sl12801")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+}
+
+void fdt_del_spi_slic(void *blob)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "zarlink,le88266")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+}
+
+void fdt_del_tdm(void *blob)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "fsl,starlite-tdm")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+}
+
+void fdt_del_sdhc(void *blob)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "fsl,esdhc")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+}
+
+void fdt_del_ifc(void *blob)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "fsl,ifc")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+}
+
+void fdt_disable_uart1(void *blob)
+{
+ int nodeoff;
+
+ nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
+ CONFIG_SYS_NS16550_COM2);
+
+ if (nodeoff > 0) {
+ fdt_status_disabled(blob, nodeoff);
+ } else {
+ printf("WARNING unable to set status for fsl,ns16550 "
+ "uart1: %s\n", fdt_strerror(nodeoff));
+ }
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+ struct cpu_type *cpu;
+
+ cpu = gd->arch.cpu;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+#if defined(CONFIG_PCI)
+ FT_FSL_PCI_SETUP;
+#endif
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+ /* P1014 and it's derivatives don't support CAN and eTSEC3 */
+ if (cpu->soc_ver == SVR_P1014) {
+ fdt_del_flexcan(blob);
+ fdt_del_node_and_alias(blob, "ethernet2");
+ }
+
+ /* Delete IFC node as IFC pins are multiplexing with SDHC */
+ if (sd_ifc_mux != MUX_TYPE_IFC)
+ fdt_del_ifc(blob);
+ else
+ fdt_del_sdhc(blob);
+
+ if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
+ fdt_del_tdm(blob);
+ fdt_del_spi_slic(blob);
+ } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
+ fdt_del_flexcan(blob);
+ fdt_del_spi_flash(blob);
+ fdt_disable_uart1(blob);
+ } else {
+ /*
+ * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
+ * explicitly, defaultly spi_cs_sel to spi-flash instead of
+ * to tdm/slic.
+ */
+ fdt_del_tdm(blob);
+ fdt_del_flexcan(blob);
+ fdt_disable_uart1(blob);
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SDCARD
+int board_mmc_init(bd_t *bis)
+{
+ config_board_mux(MUX_TYPE_SDHC);
+ return -1;
+}
+#else
+void board_reset(void)
+{
+ /* mux to IFC to enable CPLD for reset */
+ if (sd_ifc_mux != MUX_TYPE_IFC)
+ config_board_mux(MUX_TYPE_IFC);
+}
+#endif
+
+
+int misc_init_r(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
+ MPC85xx_PMUXCR_CAN1_UART |
+ MPC85xx_PMUXCR_CAN2_TDM |
+ MPC85xx_PMUXCR_CAN2_UART);
+ config_board_mux(MUX_TYPE_CAN);
+ } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
+ MPC85xx_PMUXCR_CAN1_UART);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
+ MPC85xx_PMUXCR_CAN1_TDM);
+ clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
+ setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
+ config_board_mux(MUX_TYPE_TDM);
+ } else {
+ /* defaultly spi_cs_sel to flash */
+ config_board_mux(MUX_TYPE_SPIFLASH);
+ }
+
+ if (hwconfig("esdhc"))
+ config_board_mux(MUX_TYPE_SDHC);
+ else if (hwconfig("ifc"))
+ config_board_mux(MUX_TYPE_IFC);
+
+#ifdef CONFIG_P1010RDB_PB
+ setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+#endif
+ return 0;
+}
+
+static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (argc < 2)
+ return CMD_RET_USAGE;
+ if (strcmp(argv[1], "ifc") == 0)
+ config_board_mux(MUX_TYPE_IFC);
+ else if (strcmp(argv[1], "sdhc") == 0)
+ config_board_mux(MUX_TYPE_SDHC);
+ else
+ return CMD_RET_USAGE;
+ return 0;
+}
+
+U_BOOT_CMD(
+ mux, 2, 0, pin_mux_cmd,
+ "configure multiplexing pin for IFC/SDHC bus in runtime",
+ "bus_type (e.g. mux sdhc)"
+);
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
new file mode 100644
index 0000000..11bd9cf
--- /dev/null
+++ b/board/freescale/p1010rdb/spl.c
@@ -0,0 +1,108 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+ console_init_f();
+
+ /* Clock configuration to access CPLD using IFC(GPCM) */
+ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+#ifdef CONFIG_P1010RDB_PB
+ setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI Flash boot...\n");
+#endif
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+ env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+#else
+ env_relocate();
+#endif
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("\nTertiary program loader running in sram...");
+#else
+ puts("\nSecond program loader running in sram...");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
new file mode 100644
index 0000000..6079570
--- /dev/null
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_law.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("\nSecond program loader running in sram...");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
new file mode 100644
index 0000000..af40f97
--- /dev/null
+++ b/board/freescale/p1010rdb/tlb.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_BOOT
+ SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_16M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_16M, 1),
+
+#ifdef CONFIG_PCI
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+#endif
+#endif
+
+ /* *I*G - Board CPLD */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1022ds/Kconfig b/board/freescale/p1022ds/Kconfig
new file mode 100644
index 0000000..f1792de
--- /dev/null
+++ b/board/freescale/p1022ds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P1022DS
+
+config SYS_BOARD
+ default "p1022ds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "P1022DS"
+
+endif
diff --git a/board/freescale/p1022ds/MAINTAINERS b/board/freescale/p1022ds/MAINTAINERS
new file mode 100644
index 0000000..86aac36
--- /dev/null
+++ b/board/freescale/p1022ds/MAINTAINERS
@@ -0,0 +1,13 @@
+P1022DS BOARD
+M: Timur Tabi <timur@freescale.com>
+S: Maintained
+F: board/freescale/p1022ds/
+F: include/configs/P1022DS.h
+F: configs/P1022DS_defconfig
+F: configs/P1022DS_36BIT_defconfig
+F: configs/P1022DS_36BIT_NAND_defconfig
+F: configs/P1022DS_36BIT_SDCARD_defconfig
+F: configs/P1022DS_36BIT_SPIFLASH_defconfig
+F: configs/P1022DS_NAND_defconfig
+F: configs/P1022DS_SDCARD_defconfig
+F: configs/P1022DS_SPIFLASH_defconfig
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
new file mode 100644
index 0000000..a582127
--- /dev/null
+++ b/board/freescale/p1022ds/Makefile
@@ -0,0 +1,29 @@
+#
+# Copyright 2010 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y += spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+obj-y += p1022ds.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
+
+obj-$(CONFIG_FSL_DIU_FB) += diu.o
+endif
diff --git a/board/freescale/p1022ds/README b/board/freescale/p1022ds/README
new file mode 100644
index 0000000..04d9197
--- /dev/null
+++ b/board/freescale/p1022ds/README
@@ -0,0 +1,23 @@
+Overview
+--------
+P1022ds is a Low End Dual core platform supporting the P1022 processor
+of QorIQ series. P1022 is an e500 based dual core SOC.
+
+
+Pin Multiplex(hwconfig setting)
+-------------------------------
+Add the environment 'usb2', 'audclk' and 'tdm' to support pin multiplex
+via hwconfig, i.e:
+'setenv hwconfig usb2' to enable USB2 and disable eTsec2
+'setenv hwconfig tdm' to enable TDM and disable Audio
+'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz)
+ and disable TDM
+'setenv hwconfig 'usb2;tdm' to enable USB2 and TDM, disable eTsec2 and Audio
+'setenv hwconfig 'usb2;audclk:11' to enable USB2 and Audio(codec clock sources
+ is 11MHz), disable eTsec2 and TDM
+
+Warning: TDM and AUDIO can not enable simultaneous !
+and AUDIO codec clock sources only setting as 11MHz or 12MHz !
+'setenv hwconfig 'audclk:12;tdm' --- error !
+'setenv hwconfig 'audclk:11;tdm' --- error !
+'setenv hwconfig 'audclk:10' --- error !
diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c
new file mode 100644
index 0000000..09212bc
--- /dev/null
+++ b/board/freescale/p1022ds/ddr.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust; /* Range: 0-8 */
+ u32 cpo; /* Range: 2-31 */
+ u32 write_data_delay; /* Range: 0-6 */
+ u32 force_2t;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters dimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
+ */
+ {1, 549, 5, 31, 3, 0},
+ {1, 850, 5, 31, 5, 0},
+ {2, 549, 5, 31, 3, 0},
+ {2, 850, 5, 31, 5, 0},
+ {}
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ unsigned long ddr_freq;
+ unsigned int i;
+
+
+ if (ctrl_num) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /* set odt_rd_cfg and odt_wr_cfg. */
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 1;
+ }
+
+ pbsp = dimm0;
+ /*
+ * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->twot_en = pbsp->force_2t;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay = pbsp->write_data_delay;
+ popts->twot_en = pbsp->force_2t;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+
+found:
+ popts->half_strength_driver_enable = 1;
+
+ /* Per AN4039, enable ZQ calibration. */
+ popts->zq_en = 1;
+
+ /*
+ * For wake-up on ARP, we need auto self refresh enabled
+ */
+ popts->auto_self_refresh_en = 1;
+ popts->sr_it = 0xb;
+}
diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c
new file mode 100644
index 0000000..6fd4d95
--- /dev/null
+++ b/board/freescale/p1022ds/diu.c
@@ -0,0 +1,477 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Authors: Timur Tabi <timur@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <video_fb.h>
+#include "../common/ngpixis.h"
+#include <fsl_diu_fb.h>
+
+/* The CTL register is called 'csr' in the ngpixis_t structure */
+#define PX_CTL_ALTACC 0x80
+
+#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
+#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
+#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
+#define PX_BRDCFG0_ELBC_DIU 0x02
+
+#define PX_BRDCFG1_DVIEN 0x80
+#define PX_BRDCFG1_DFPEN 0x40
+#define PX_BRDCFG1_BACKLIGHT 0x20
+
+#define PMUXCR_ELBCDIU_MASK 0xc0000000
+#define PMUXCR_ELBCDIU_NOR16 0x80000000
+#define PMUXCR_ELBCDIU_DIU 0x40000000
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register. So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F 0x10000000
+#define AD_ALPHA_C_SHIFT 25
+#define AD_BLUE_C_SHIFT 23
+#define AD_GREEN_C_SHIFT 21
+#define AD_RED_C_SHIFT 19
+#define AD_PIXEL_S_SHIFT 16
+#define AD_COMP_3_SHIFT 12
+#define AD_COMP_2_SHIFT 8
+#define AD_COMP_1_SHIFT 4
+#define AD_COMP_0_SHIFT 0
+
+/*
+ * Variables used by the DIU/LBC switching code. It's safe to makes these
+ * global, because the DIU requires DDR, so we'll only run this code after
+ * relocation.
+ */
+static u8 px_brdcfg0;
+static u32 pmuxcr;
+static void *lbc_lcs0_ba;
+static void *lbc_lcs1_ba;
+static u32 old_br0, old_or0, old_br1, old_or1;
+static u32 new_br0, new_or0, new_br1, new_or1;
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ unsigned long speed_ccb, temp;
+ u32 pixval;
+
+ speed_ccb = get_bus_freq(0);
+ temp = 1000000000 / pixclock;
+ temp *= 1000;
+ pixval = speed_ccb / temp;
+ debug("DIU pixval = %u\n", pixval);
+
+ /* Modify PXCLK in GUTS CLKDVDR */
+ temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
+ out_be32(&gur->clkdvdr, temp); /* turn off clock */
+ out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ const char *name;
+ u32 pixel_format;
+ u8 temp;
+ phys_addr_t phys0, phys1; /* BR0/BR1 physical addresses */
+
+ /*
+ * Indirect mode requires both BR0 and BR1 to be set to "GPCM",
+ * otherwise writes to these addresses won't actually appear on the
+ * local bus, and so the PIXIS won't see them.
+ *
+ * In FCM mode, writes go to the NAND controller, which does not pass
+ * them to the localbus directly. So we force BR0 and BR1 into GPCM
+ * mode, since we don't care about what's behind the localbus any
+ * more. However, we save those registers first, so that we can
+ * restore them when necessary.
+ */
+ new_br0 = old_br0 = get_lbc_br(0);
+ new_br1 = old_br1 = get_lbc_br(1);
+ new_or0 = old_or0 = get_lbc_or(0);
+ new_or1 = old_or1 = get_lbc_or(1);
+
+ /*
+ * Use the existing BRx/ORx values if it's already GPCM. Otherwise,
+ * force the values to simple 32KB GPCM windows with the most
+ * conservative timing.
+ */
+ if ((old_br0 & BR_MSEL) != BR_MS_GPCM) {
+ new_br0 = (get_lbc_br(0) & BR_BA) | BR_V;
+ new_or0 = OR_AM_32KB | 0xFF7;
+ set_lbc_br(0, new_br0);
+ set_lbc_or(0, new_or0);
+ }
+ if ((old_br1 & BR_MSEL) != BR_MS_GPCM) {
+ new_br1 = (get_lbc_br(1) & BR_BA) | BR_V;
+ new_or1 = OR_AM_32KB | 0xFF7;
+ set_lbc_br(1, new_br1);
+ set_lbc_or(1, new_or1);
+ }
+
+ /*
+ * Determine the physical addresses for Chip Selects 0 and 1. The
+ * BR0/BR1 registers contain the truncated physical addresses for the
+ * chip selects, mapped via the localbus LAW. Since the BRx registers
+ * only contain the lower 32 bits of the address, we have to determine
+ * the upper 4 bits some other way. The proper way is to scan the LAW
+ * table looking for a matching localbus address. Instead, we cheat.
+ * We know that the upper bits are 0 for 32-bit addressing, or 0xF for
+ * 36-bit addressing.
+ */
+#ifdef CONFIG_PHYS_64BIT
+ phys0 = 0xf00000000ULL | (old_br0 & old_or0 & BR_BA);
+ phys1 = 0xf00000000ULL | (old_br1 & old_or1 & BR_BA);
+#else
+ phys0 = old_br0 & old_or0 & BR_BA;
+ phys1 = old_br1 & old_or1 & BR_BA;
+#endif
+
+ /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
+ lbc_lcs0_ba = map_physmem(phys0, 1, 0);
+ lbc_lcs1_ba = map_physmem(phys1, 1, 0);
+
+ pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+ (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+ (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+ (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+ (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+ temp = in_8(&pixis->brdcfg1);
+
+ if (strncmp(port, "lvds", 4) == 0) {
+ /* Single link LVDS */
+ temp &= ~PX_BRDCFG1_DVIEN;
+ /*
+ * LVDS also needs backlight enabled, otherwise the display
+ * will be blank.
+ */
+ temp |= (PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
+ name = "Single-Link LVDS";
+ } else { /* DVI */
+ /* Enable the DVI port, disable the DFP and the backlight */
+ temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
+ temp |= PX_BRDCFG1_DVIEN;
+ name = "DVI";
+ }
+
+ printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+ out_8(&pixis->brdcfg1, temp);
+
+ /*
+ * Enable PIXIS indirect access mode. This is a hack that allows us to
+ * access PIXIS registers even when the LBC pins have been muxed to the
+ * DIU.
+ */
+ setbits_8(&pixis->csr, PX_CTL_ALTACC);
+
+ /*
+ * Route the LAD pins to the DIU. This will disable access to the eLBC,
+ * which means we won't be able to read/write any NOR flash addresses!
+ */
+ out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
+ px_brdcfg0 = in_8(lbc_lcs1_ba);
+ out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
+ in_8(lbc_lcs1_ba);
+
+ /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
+ clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
+ pmuxcr = in_be32(&gur->pmuxcr);
+
+ return fsl_diu_init(xres, yres, pixel_format, 0);
+}
+
+/*
+ * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
+ *
+ * On the Freescale P1022, the DIU video signal and the LBC address/data lines
+ * share the same pins, which means that when the DIU is active (e.g. the
+ * console is on the DVI display), NOR flash cannot be accessed. So we use the
+ * weak accessor feature of the CFI flash code to temporarily switch the pin
+ * mux from DIU to LBC whenever we want to read or write flash. This has a
+ * significant performance penalty, but it's the only way to make it work.
+ *
+ * There are two muxes: one on the chip, and one on the board. The chip mux
+ * controls whether the pins are used for the DIU or the LBC, and it is
+ * set via PMUXCR. The board mux controls whether those signals go to
+ * the video connector or the NOR flash chips, and it is set via the ngPIXIS.
+ */
+static int set_mux_to_lbc(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Switch the muxes only if they're currently set to DIU mode */
+ if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
+ PMUXCR_ELBCDIU_NOR16) {
+ /*
+ * In DIU mode, the PIXIS can only be accessed indirectly
+ * since we can't read/write the LBC directly.
+ */
+ /* Set the board mux to LBC. This will disable the display. */
+ out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
+ out_8(lbc_lcs1_ba, px_brdcfg0);
+ in_8(lbc_lcs1_ba);
+
+ /* Disable indirect PIXIS mode */
+ out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
+ clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
+
+ /* Set the chip mux to LBC mode, so that writes go to flash. */
+ out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
+ PMUXCR_ELBCDIU_NOR16);
+ in_be32(&gur->pmuxcr);
+
+ /* Restore the BR0 and BR1 settings */
+ set_lbc_br(0, old_br0);
+ set_lbc_or(0, old_or0);
+ set_lbc_br(1, old_br1);
+ set_lbc_or(1, old_or1);
+
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
+ * set_mux_to_diu - re-enable the DIU muxing
+ *
+ * This function restores the chip and board muxing to point to the DIU.
+ */
+static void set_mux_to_diu(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Set BR0 and BR1 to GPCM mode */
+ set_lbc_br(0, new_br0);
+ set_lbc_or(0, new_or0);
+ set_lbc_br(1, new_br1);
+ set_lbc_or(1, new_or1);
+
+ /* Enable indirect PIXIS mode */
+ setbits_8(&pixis->csr, PX_CTL_ALTACC);
+
+ /* Set the board mux to DIU. This will enable the display. */
+ out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
+ out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
+ in_8(lbc_lcs1_ba);
+
+ /* Set the chip mux to DIU mode. */
+ out_be32(&gur->pmuxcr, pmuxcr);
+ in_be32(&gur->pmuxcr);
+}
+
+/*
+ * pixis_read - board-specific function to read from the PIXIS
+ *
+ * This function overrides the generic pixis_read() function, so that it can
+ * use PIXIS indirect mode if necessary.
+ */
+u8 pixis_read(unsigned int reg)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Use indirect mode if the mux is currently set to DIU mode */
+ if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
+ PMUXCR_ELBCDIU_NOR16) {
+ out_8(lbc_lcs0_ba, reg);
+ return in_8(lbc_lcs1_ba);
+ } else {
+ void *p = (void *)PIXIS_BASE;
+
+ return in_8(p + reg);
+ }
+}
+
+/*
+ * pixis_write - board-specific function to write to the PIXIS
+ *
+ * This function overrides the generic pixis_write() function, so that it can
+ * use PIXIS indirect mode if necessary.
+ */
+void pixis_write(unsigned int reg, u8 value)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Use indirect mode if the mux is currently set to DIU mode */
+ if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
+ PMUXCR_ELBCDIU_NOR16) {
+ out_8(lbc_lcs0_ba, reg);
+ out_8(lbc_lcs1_ba, value);
+ /* Do a read-back to ensure the write completed */
+ in_8(lbc_lcs1_ba);
+ } else {
+ void *p = (void *)PIXIS_BASE;
+
+ out_8(p + reg, value);
+ }
+}
+
+void pixis_bank_reset(void)
+{
+ /*
+ * For some reason, a PIXIS bank reset does not work if the PIXIS is
+ * in indirect mode, so switch to direct mode first.
+ */
+ set_mux_to_lbc();
+
+ out_8(&pixis->vctl, 0);
+ out_8(&pixis->vctl, 1);
+
+ while (1);
+}
+
+#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+
+void flash_write8(u8 value, void *addr)
+{
+ int sw = set_mux_to_lbc();
+
+ __raw_writeb(value, addr);
+ if (sw) {
+ /*
+ * To ensure the post-write is completed to eLBC, software must
+ * perform a dummy read from one valid address from eLBC space
+ * before changing the eLBC_DIU from NOR mode to DIU mode.
+ * set_mux_to_diu() includes a sync that will ensure the
+ * __raw_readb() completes before it switches the mux.
+ */
+ __raw_readb(addr);
+ set_mux_to_diu();
+ }
+}
+
+void flash_write16(u16 value, void *addr)
+{
+ int sw = set_mux_to_lbc();
+
+ __raw_writew(value, addr);
+ if (sw) {
+ /*
+ * To ensure the post-write is completed to eLBC, software must
+ * perform a dummy read from one valid address from eLBC space
+ * before changing the eLBC_DIU from NOR mode to DIU mode.
+ * set_mux_to_diu() includes a sync that will ensure the
+ * __raw_readb() completes before it switches the mux.
+ */
+ __raw_readb(addr);
+ set_mux_to_diu();
+ }
+}
+
+void flash_write32(u32 value, void *addr)
+{
+ int sw = set_mux_to_lbc();
+
+ __raw_writel(value, addr);
+ if (sw) {
+ /*
+ * To ensure the post-write is completed to eLBC, software must
+ * perform a dummy read from one valid address from eLBC space
+ * before changing the eLBC_DIU from NOR mode to DIU mode.
+ * set_mux_to_diu() includes a sync that will ensure the
+ * __raw_readb() completes before it switches the mux.
+ */
+ __raw_readb(addr);
+ set_mux_to_diu();
+ }
+}
+
+void flash_write64(u64 value, void *addr)
+{
+ int sw = set_mux_to_lbc();
+ uint32_t *p = addr;
+
+ /*
+ * There is no __raw_writeq(), so do the write manually. We don't trust
+ * the compiler, so we use inline assembly.
+ */
+ __asm__ __volatile__(
+ "stw%U0%X0 %2,%0;\n"
+ "stw%U1%X1 %3,%1;\n"
+ : "=m" (*p), "=m" (*(p + 1))
+ : "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
+
+ if (sw) {
+ /*
+ * To ensure the post-write is completed to eLBC, software must
+ * perform a dummy read from one valid address from eLBC space
+ * before changing the eLBC_DIU from NOR mode to DIU mode. We
+ * read addr+4 because we just wrote to addr+4, so that's how we
+ * maintain execution order. set_mux_to_diu() includes a sync
+ * that will ensure the __raw_readb() completes before it
+ * switches the mux.
+ */
+ __raw_readb(addr + 4);
+ set_mux_to_diu();
+ }
+}
+
+u8 flash_read8(void *addr)
+{
+ u8 ret;
+
+ int sw = set_mux_to_lbc();
+
+ ret = __raw_readb(addr);
+ if (sw)
+ set_mux_to_diu();
+
+ return ret;
+}
+
+u16 flash_read16(void *addr)
+{
+ u16 ret;
+
+ int sw = set_mux_to_lbc();
+
+ ret = __raw_readw(addr);
+ if (sw)
+ set_mux_to_diu();
+
+ return ret;
+}
+
+u32 flash_read32(void *addr)
+{
+ u32 ret;
+
+ int sw = set_mux_to_lbc();
+
+ ret = __raw_readl(addr);
+ if (sw)
+ set_mux_to_diu();
+
+ return ret;
+}
+
+u64 flash_read64(void *addr)
+{
+ u64 ret;
+
+ int sw = set_mux_to_lbc();
+
+ /* There is no __raw_readq(), so do the read manually */
+ ret = *(volatile u64 *)addr;
+ if (sw)
+ set_mux_to_diu();
+
+ return ret;
+}
+
+#endif
diff --git a/board/freescale/p1022ds/law.c b/board/freescale/p1022ds/law.c
new file mode 100644
index 0000000..3a95072
--- /dev/null
+++ b/board/freescale/p1022ds/law.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
new file mode 100644
index 0000000..d7dd478
--- /dev/null
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -0,0 +1,362 @@
+/*
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <asm/fsl_law.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <hwconfig.h>
+
+#include "../common/ngpixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Set pmuxcr to allow both i2c1 and i2c2 */
+ setbits_be32(&gur->pmuxcr, 0x1000);
+#ifdef CONFIG_SYS_RAMBOOT
+ setbits_be32(&gur->pmuxcr,
+ in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+ /* Read back the register to synchronize the write. */
+ in_be32(&gur->pmuxcr);
+
+ /* Set the pin muxing to enable ETSEC2. */
+ clrbits_be32(&gur->pmuxcr2, 0x001F8000);
+
+ /* Enable the SPI */
+ clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ u8 sw;
+
+ printf("Board: P1022DS Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
+
+ sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+
+ switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
+ case 0:
+ printf ("vBank: %u\n", ((sw & 0x30) >> 4));
+ break;
+ case 1:
+ printf ("NAND\n");
+ break;
+ case 2:
+ case 3:
+ puts ("Promjet\n");
+ break;
+ }
+
+ return 0;
+}
+
+#define CONFIG_TFP410_I2C_ADDR 0x38
+
+/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
+
+/* Route the I2C1 pins to the SSI port instead. */
+#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
+
+/* Choose the 12.288Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
+
+/* Choose the 11.2896Mhz codec reference clock */
+#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
+
+/* Connect to USB2 */
+#define CONFIG_PIXIS_BRDCFG0_USB2 0x10
+/* Connect to TFM bus */
+#define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
+/* Connect to SPI */
+#define CONFIG_PIXIS_BRDCFG0_SPI 0x80
+
+int misc_init_r(void)
+{
+ u8 temp;
+ const char *audclk;
+ size_t arglen;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ /* For DVI, enable the TFP410 Encoder. */
+
+ temp = 0xBF;
+ if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
+ return -1;
+ if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
+ return -1;
+ debug("DVI Encoder Read: 0x%02x\n", temp);
+
+ temp = 0x10;
+ if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
+ return -1;
+ if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
+ return -1;
+ debug("DVI Encoder Read: 0x%02x\n",temp);
+
+ /* Enable the USB2 in PMUXCR2 and FGPA */
+ if (hwconfig("usb2")) {
+ clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
+ MPC85xx_PMUXCR2_USB);
+ setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
+ }
+
+ /* tdm and audio can not enable simultaneous*/
+ if (hwconfig("tdm") && hwconfig("audclk")){
+ printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
+ return -1;
+ }
+
+ /* Enable the TDM in PMUXCR and FGPA */
+ if (hwconfig("tdm")) {
+ clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
+ MPC85xx_PMUXCR_TDM);
+ setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
+ /* TDM need some configration option by SPI */
+ clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
+ MPC85xx_PMUXCR_SPI);
+ setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
+ }
+
+ /*
+ * Enable the reference clock for the WM8776 codec, and route the MUX
+ * pins for SSI. The default is the 12.288 MHz clock
+ */
+
+ if (hwconfig("audclk")) {
+ temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
+ CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
+ temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
+
+ audclk = hwconfig_arg("audclk", &arglen);
+ /* Check the first two chars only */
+ if (audclk && (strncmp(audclk, "11", 2) == 0))
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
+ else
+ temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
+ setbits_8(&pixis->brdcfg1, temp);
+ }
+
+ return 0;
+}
+
+/*
+ * A list of PCI and SATA slots
+ */
+enum slot_id {
+ SLOT_PCIE1 = 1,
+ SLOT_PCIE2,
+ SLOT_PCIE3,
+ SLOT_PCIE4,
+ SLOT_PCIE5,
+ SLOT_SATA1,
+ SLOT_SATA2
+};
+
+/*
+ * This array maps the slot identifiers to their names on the P1022DS board.
+ */
+static const char *slot_names[] = {
+ [SLOT_PCIE1] = "Slot 1",
+ [SLOT_PCIE2] = "Slot 2",
+ [SLOT_PCIE3] = "Slot 3",
+ [SLOT_PCIE4] = "Slot 4",
+ [SLOT_PCIE5] = "Mini-PCIe",
+ [SLOT_SATA1] = "SATA 1",
+ [SLOT_SATA2] = "SATA 2",
+};
+
+/*
+ * This array maps a given SERDES configuration and SERDES device to the PCI or
+ * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
+ */
+static u8 serdes_dev_slot[][SATA2 + 1] = {
+ [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
+ [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+ [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
+ [PCIE2] = SLOT_PCIE5 },
+ [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
+ [PCIE2] = SLOT_PCIE3,
+ [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+ [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
+ [PCIE2] = SLOT_PCIE3 },
+ [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
+ [PCIE2] = SLOT_PCIE3,
+ [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+ [0x1c] = { [PCIE1] = SLOT_PCIE1,
+ [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+ [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
+ [0x1f] = { [PCIE1] = SLOT_PCIE1 },
+};
+
+
+/*
+ * Returns the name of the slot to which the PCIe or SATA controller is
+ * connected
+ */
+const char *board_serdes_name(enum srds_prtcl device)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ enum slot_id slot = serdes_dev_slot[srds_cfg][device];
+ const char *name = slot_names[slot];
+
+ if (name)
+ return name;
+ else
+ return "Nothing";
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ return 0;
+}
+
+/*
+ * Initialize on-board and/or PCI Ethernet devices
+ *
+ * Returns:
+ * <0, error
+ * 0, no ethernet devices found
+ * >0, number of ethernet devices initialized
+ */
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[2];
+ unsigned int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+/**
+ * ft_codec_setup - fix up the clock-frequency property of the codec node
+ *
+ * Update the clock-frequency property based on the value of the 'audclk'
+ * hwconfig option. If audclk is not specified, then don't write anything
+ * to the device tree, because it means that the codec clock is disabled.
+ */
+static void ft_codec_setup(void *blob, const char *compatible)
+{
+ const char *audclk;
+ size_t arglen;
+ u32 freq;
+
+ audclk = hwconfig_arg("audclk", &arglen);
+ if (audclk) {
+ if (strncmp(audclk, "11", 2) == 0)
+ freq = 11289600;
+ else
+ freq = 12288000;
+
+ do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
+ freq, 1);
+ }
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+ FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_fdt_fixup(blob);
+#endif
+
+ /* Update the WM8776 node's clock frequency property */
+ ft_codec_setup(blob, "wlf,wm8776");
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
new file mode 100644
index 0000000..7bd9d29
--- /dev/null
+++ b/board/freescale/p1022ds/spl.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include "../common/ngpixis.h"
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const u32 sysclk_tbl[] = {
+ 66666000, 7499900, 83332500, 8999900,
+ 99999000, 11111000, 12499800, 13333200
+};
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ int px_spd;
+ u32 plat_ratio, sys_clk, bus_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* Set pmuxcr to allow both i2c1 and i2c2 */
+ setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+ setbits_be32(&gur->pmuxcr,
+ in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+ /* Enable the SPI */
+ clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
+#endif
+
+ /* Read back the register to synchronize the write. */
+ in_be32(&gur->pmuxcr);
+
+ /* initialize selected port with appropriate baud rate */
+ px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
+ sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ bus_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI Flash boot...\n");
+#endif
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+#ifndef CONFIG_SPL_NAND_BOOT
+ env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+#else
+ env_relocate();
+#endif
+
+#ifdef CONFIG_SYS_I2C
+ i2c_init_all();
+#else
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+ gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("Tertiary program loader running in sram...");
+#else
+ puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c
new file mode 100644
index 0000000..6c7e1ac
--- /dev/null
+++ b/board/freescale/p1022ds/spl_minimal.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+
+
+const static u32 sysclk_tbl[] = {
+ 66666000, 7499900, 83332500, 8999900,
+ 99999000, 11111000, 12499800, 13333200
+};
+
+void board_init_f(ulong bootflag)
+{
+ int px_spd;
+ u32 plat_ratio, sys_clk, bus_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+ /* for FPGA */
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+
+ /* initialize selected port with appropriate baud rate */
+ px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
+ sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ bus_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0,
+ CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("\nSecond program loader running in sram...");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
new file mode 100644
index 0000000..e7ae2e2
--- /dev/null
+++ b/board/freescale/p1022ds/tlb.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* W**G* - Flash/promjet, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
+
+ SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_4K, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+ /* **** - eSDHC/eSPI/NAND boot */
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+ /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_SYS_NAND_BASE
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16K, 1),
+#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1023rdb/Kconfig b/board/freescale/p1023rdb/Kconfig
new file mode 100644
index 0000000..1e4cd10
--- /dev/null
+++ b/board/freescale/p1023rdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P1023RDB
+
+config SYS_BOARD
+ default "p1023rdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "P1023RDB"
+
+endif
diff --git a/board/freescale/p1023rdb/MAINTAINERS b/board/freescale/p1023rdb/MAINTAINERS
new file mode 100644
index 0000000..c06bac6
--- /dev/null
+++ b/board/freescale/p1023rdb/MAINTAINERS
@@ -0,0 +1,6 @@
+P1023RDB BOARD
+#M: -
+S: Maintained
+F: board/freescale/p1023rdb/
+F: include/configs/P1023RDB.h
+F: configs/P1023RDB_defconfig
diff --git a/board/freescale/p1023rdb/Makefile b/board/freescale/p1023rdb/Makefile
new file mode 100644
index 0000000..e4f1edf
--- /dev/null
+++ b/board/freescale/p1023rdb/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += p1023rdb.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
new file mode 100644
index 0000000..d587df5
--- /dev/null
+++ b/board/freescale/p1023rdb/ddr.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* CONFIG_SYS_DDR_RAW_TIMING */
+/*
+ * Hynix H5TQ1G83TFR-H9C
+ */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 536870912u,
+ .capacity = 536870912u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 14,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1875,
+ .caslat_x = 0x1e << 4, /* 5,6,7,8 */
+ .taa_ps = 13125,
+ .twr_ps = 18000,
+ .trcd_ps = 13125,
+ .trrd_ps = 7500,
+ .trp_ps = 13125,
+ .tras_ps = 37500,
+ .trc_ps = 50625,
+ .trfc_ps = 160000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ int i;
+ popts->clk_adjust = 6;
+ popts->cpo_override = 0x1f;
+ popts->write_data_delay = 2;
+ popts->half_strength_driver_enable = 1;
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x8;
+ popts->trwt_override = 1;
+ popts->trwt = 0;
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+ popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+ }
+}
diff --git a/board/freescale/p1023rdb/law.c b/board/freescale/p1023rdb/law.c
new file mode 100644
index 0000000..13a4c74
--- /dev/null
+++ b/board/freescale/p1023rdb/law.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
+ LAW_TRGT_IF_DPAA_SWP_SRAM),
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
new file mode 100644
index 0000000..56f561a
--- /dev/null
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Authors: Roy Zang <tie-fei.zang@freescale.com>
+ * Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_portals.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ /* Set ABSWP to implement conversion of addresses in the LBC */
+ setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: P1023 RDB\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ setup_portals();
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ return gd->bus_clk;
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+ return gd->mem_clk;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ struct fsl_pq_mdio_info dtsec_mdio_info;
+
+ /*
+ * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
+ * is not correct.
+ */
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
+
+ dtsec_mdio_info.regs =
+ (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+ fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+
+ fm_info_set_mdio(FM1_DTSEC1,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ fm_info_set_mdio(FM1_DTSEC2,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+
+#ifdef CONFIG_FMAN_ENET
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+ fdt_fixup_fman_ethernet(blob);
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/p1023rdb/tlb.c b/board/freescale/p1023rdb/tlb.c
new file mode 100644
index 0000000..8fd178e
--- /dev/null
+++ b/board/freescale/p1023rdb/tlb.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_4M, 1),
+
+ /* W**G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_M,
+ 0, 9, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_1M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_16K, 1),
+
+#ifdef CONFIG_SYS_RAMBOOT
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
+ CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 12, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 13, BOOKE_PAGESZ_256M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1_p2_rdb/Kconfig b/board/freescale/p1_p2_rdb/Kconfig
new file mode 100644
index 0000000..d7ad35d
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P1_P2_RDB
+
+config SYS_BOARD
+ default "p1_p2_rdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "P1_P2_RDB"
+
+endif
diff --git a/board/freescale/p1_p2_rdb/MAINTAINERS b/board/freescale/p1_p2_rdb/MAINTAINERS
new file mode 100644
index 0000000..aabf587
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/MAINTAINERS
@@ -0,0 +1,37 @@
+P1_P2_RDB BOARD
+#M: -
+S: Maintained
+F: board/freescale/p1_p2_rdb/
+F: include/configs/P1_P2_RDB.h
+F: configs/P1011RDB_defconfig
+F: configs/P1011RDB_36BIT_defconfig
+F: configs/P1011RDB_36BIT_SDCARD_defconfig
+F: configs/P1011RDB_36BIT_SPIFLASH_defconfig
+F: configs/P1011RDB_NAND_defconfig
+F: configs/P1011RDB_SDCARD_defconfig
+F: configs/P1011RDB_SPIFLASH_defconfig
+F: configs/P1020RDB_defconfig
+F: configs/P1020RDB_36BIT_defconfig
+F: configs/P1020RDB_36BIT_SDCARD_defconfig
+F: configs/P1020RDB_36BIT_SPIFLASH_defconfig
+F: configs/P1020RDB_NAND_defconfig
+F: configs/P1020RDB_SDCARD_defconfig
+F: configs/P1020RDB_SPIFLASH_defconfig
+F: configs/P2010RDB_defconfig
+F: configs/P2010RDB_36BIT_defconfig
+F: configs/P2010RDB_36BIT_SDCARD_defconfig
+F: configs/P2010RDB_36BIT_SPIFLASH_defconfig
+F: configs/P2010RDB_NAND_defconfig
+F: configs/P2010RDB_SDCARD_defconfig
+F: configs/P2010RDB_SPIFLASH_defconfig
+F: configs/P2020RDB_36BIT_defconfig
+F: configs/P2020RDB_36BIT_SDCARD_defconfig
+F: configs/P2020RDB_36BIT_SPIFLASH_defconfig
+F: configs/P2020RDB_NAND_defconfig
+F: configs/P2020RDB_SDCARD_defconfig
+F: configs/P2020RDB_SPIFLASH_defconfig
+
+P2020RDB BOARD
+M: Poonam Aggrwal <poonam.aggrwal@freescale.com>
+S: Maintained
+F: configs/P2020RDB_defconfig
diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile
new file mode 100644
index 0000000..a97bf45
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/Makefile
@@ -0,0 +1,30 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y += spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += p1_p2_rdb.o
+obj-$(CONFIG_PCI) += pci.o
+endif
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
+
+endif
diff --git a/board/freescale/p1_p2_rdb/README b/board/freescale/p1_p2_rdb/README
new file mode 100644
index 0000000..cd66e58
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/README
@@ -0,0 +1,145 @@
+Overview
+--------
+P2020RDB is a Low End Dual core platform supporting the P2020 processor
+of QorIQ series. P2020 is an e500 based dual core SOC.
+
+Building U-boot
+-----------
+To build the u-boot for P2020RDB:
+ make P2020RDB_config
+ make
+
+NOR Flash Banks
+-----------
+RDB board for P2020 has two flash banks. They are both present on boot.
+
+Booting by default is always from the boot bank at 0xef00_0000.
+
+Memory Map
+----------
+0xef00_0000 - 0xef7f_ffff Alternate bank 8MB
+0xe800_0000 - 0xefff_ffff Boot bank 8MB
+
+0xef74_0000 - 0xef7f_ffff Alternate u-boot address 768KB
+0xeff4_0000 - 0xefff_ffff Boot u-boot address 768KB
+
+Switch settings to boot from the NOR flash banks
+------------------------------------------------
+SW4[8]=0 default NOR Flash bank
+SW4[8]=1 Alternate NOR Flash bank
+
+Flashing Images
+---------------
+To place a new u-boot image in the alternate flash bank and then boot
+with that new image temporarily, use this:
+ tftp 1000000 u-boot.bin
+ erase ef740000 ef7fffff
+ cp.b 1000000 ef740000 c0000
+
+Now to boot from the alternate bank change the SW4[8] from 0 to 1.
+
+To program the image in the boot flash bank:
+ tftp 1000000 u-boot.bin
+ protect off all
+ erase eff40000 ffffffff
+ cp.b 1000000 eff40000 c0000
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts
+
+Booting Linux
+-------------
+Place a linux uImage in the TFTP disk area.
+
+ tftp 1000000 uImage.p2020rdb
+ tftp 2000000 rootfs.ext2.gz.uboot
+ tftp c00000 p2020rdb.dtb
+ bootm 1000000 2000000 c00000
+
+Implementing AMP(Asymmetric MultiProcessing)
+---------------------------------------------
+1. Build kernel image for core0:
+
+ a. $ make 85xx/p1_p2_rdb_defconfig
+
+ b. $ make menuconfig
+ - un-select "Processor support"->
+ "Symetric multi-processing support"
+
+ c. $ make uImage
+
+ d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
+
+2. Build kernel image for core1:
+
+ a. $ make 85xx/p1_p2_rdb_defconfig
+
+ b. $ make menuconfig
+ - Un-select "Processor support"->
+ "Symetric multi-processing support"
+ - Select "Advanced setup" ->
+ "Prompt for advanced kernel configuration options"
+ - Select
+ "Set physical address where the kernel is loaded"
+ and set it to 0x20000000, assuming core1 will
+ start from 512MB.
+ - Select "Set custom page offset address"
+ - Select "Set custom kernel base address"
+ - Select "Set maximum low memory"
+ - "Exit" and save the selection.
+
+ c. $ make uImage
+
+ d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
+
+3. Create dtb for core0:
+
+ $ dtc -I dts -O dtb -f -b 0
+ arch/powerpc/boot/dts/p2020rdb_camp_core0.dts >
+ /tftpboot/p2020rdb_camp_core0.dtb
+
+4. Create dtb for core1:
+
+ $ dtc -I dts -O dtb -f -b 1
+ arch/powerpc/boot/dts/p2020rdb_camp_core1.dts >
+ /tftpboot/p2020rdb_camp_core1.dtb
+
+5. Bring up two cores separately:
+
+ a. Power on the board, under u-boot prompt:
+ => setenv <serverip>
+ => setenv <ipaddr>
+ => setenv bootargs root=/dev/ram rw console=ttyS0,115200
+ b. Bring up core1's kernel first:
+ => setenv bootm_low 0x20000000
+ => setenv bootm_size 0x10000000
+ => tftp 21000000 uImage.core1
+ => tftp 22000000 ramdiskfile
+ => tftp 20c00000 p2020rdb_camp_core1.dtb
+ => interrupts off
+ => bootm start 21000000 22000000 20c00000
+ => bootm loados
+ => bootm ramdisk
+ => bootm fdt
+ => fdt boardsetup
+ => fdt chosen $initrd_start $initrd_end
+ => bootm prep
+ => cpu 1 release $bootm_low - $fdtaddr -
+ c. Bring up core0's kernel(on the same u-boot console):
+ => setenv bootm_low 0
+ => setenv bootm_size 0x20000000
+ => tftp 1000000 uImage.core0
+ => tftp 2000000 ramdiskfile
+ => tftp c00000 p2020rdb_camp_core0.dtb
+ => bootm 1000000 2000000 c00000
+
+Please note only core0 will run u-boot, core1 starts kernel directly
+after "cpu release" command is issued.
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
new file mode 100644
index 0000000..98ee5f1
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -0,0 +1,221 @@
+/*
+ * Copyright 2009, 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
+#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
+#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000
+#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000
+#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
+#define CONFIG_SYS_DDR_RCW_1 0x00000000
+#define CONFIG_SYS_DDR_RCW_2 0x00000000
+#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/
+#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
+#define CONFIG_SYS_DDR_TIMING_4 0x00000000
+#define CONFIG_SYS_DDR_TIMING_5 0x00000000
+
+#define CONFIG_SYS_DDR_TIMING_3_400 0x00010000
+#define CONFIG_SYS_DDR_TIMING_0_400 0x00260802
+#define CONFIG_SYS_DDR_TIMING_1_400 0x39355322
+#define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca
+#define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000
+#define CONFIG_SYS_DDR_MODE_1_400 0x00480432
+#define CONFIG_SYS_DDR_MODE_2_400 0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_400 0x06180100
+
+#define CONFIG_SYS_DDR_TIMING_3_533 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_533 0x00260802
+#define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432
+#define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce
+#define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000
+#define CONFIG_SYS_DDR_MODE_1_533 0x00040642
+#define CONFIG_SYS_DDR_MODE_2_533 0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_533 0x08200100
+
+#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802
+#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543
+#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1
+#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
+#define CONFIG_SYS_DDR_MODE_1_667 0x00040852
+#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
+
+#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000
+#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802
+#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
+#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
+#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
+#define CONFIG_SYS_DDR_MODE_1_800 0x00040852
+#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram (void)
+{
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
+ size_t ddr_size;
+ struct cpu_type *cpu;
+ ulong ddr_freq, ddr_freq_mhz;
+
+ cpu = gd->arch.cpu;
+
+ ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+#if defined(CONFIG_SYS_RAMBOOT)
+ return ddr_size;
+#endif
+ ddr_freq = get_ddr_freq(0);
+ ddr_freq_mhz = ddr_freq / 1000000;
+
+ printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
+
+ if(ddr_freq_mhz <= 400)
+ memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
+ else if(ddr_freq_mhz <= 533)
+ memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
+ else if(ddr_freq_mhz <= 667)
+ memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
+ else if(ddr_freq_mhz <= 800)
+ memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
+ else
+ panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
+
+ /* P1020 and it's derivatives support max 32bit DDR width */
+ if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
+ ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
+ ddr_cfg_regs.cs[0].bnds = 0x0000001F;
+ }
+
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+ set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
+ return ddr_size;
+}
diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c
new file mode 100644
index 0000000..b60a27f
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/law.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
new file mode 100644
index 0000000..61ed466
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <vsc7385.h>
+#include <netdev.h>
+#include <rtc.h>
+#include <i2c.h>
+#include <hwconfig.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define VSC7385_RST_SET 0x00080000
+#define SLIC_RST_SET 0x00040000
+#define SGMII_PHY_RST_SET 0x00020000
+#define PCIE_RST_SET 0x00010000
+#define RGMII_PHY_RST_SET 0x02000000
+
+#define USB_RST_CLR 0x04000000
+#define USB2_PORT_OUT_EN 0x01000000
+
+#define GPIO_DIR 0x060f0000
+
+#define BOARD_PERI_RST_SET VSC7385_RST_SET | SLIC_RST_SET | \
+ SGMII_PHY_RST_SET | PCIE_RST_SET | \
+ RGMII_PHY_RST_SET
+
+#define SYSCLK_MASK 0x00200000
+#define BOARDREV_MASK 0x10100000
+#define BOARDREV_C 0x00100000
+#define BOARDREV_D 0x00000000
+
+#define SYSCLK_66 66666666
+#define SYSCLK_100 100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 val_gpdat, sysclk_gpio;
+
+ val_gpdat = in_be32(&pgpio->gpdat);
+ sysclk_gpio = val_gpdat & SYSCLK_MASK;
+
+ if(sysclk_gpio == 0)
+ return SYSCLK_66;
+ else
+ return SYSCLK_100;
+
+ return 0;
+}
+
+#ifdef CONFIG_MMC
+int board_early_init_f (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->pmuxcr,
+ (MPC85xx_PMUXCR_SDHC_CD |
+ MPC85xx_PMUXCR_SDHC_WP));
+ return 0;
+}
+#endif
+
+int checkboard (void)
+{
+ u32 val_gpdat, board_rev_gpio;
+ volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ char board_rev = 0;
+ struct cpu_type *cpu;
+
+ val_gpdat = in_be32(&pgpio->gpdat);
+ board_rev_gpio = val_gpdat & BOARDREV_MASK;
+ if (board_rev_gpio == BOARDREV_C)
+ board_rev = 'C';
+ else if (board_rev_gpio == BOARDREV_D)
+ board_rev = 'D';
+ else
+ panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
+
+ cpu = gd->arch.cpu;
+ printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
+
+ setbits_be32(&pgpio->gpdir, GPIO_DIR);
+
+/*
+ * Bringing the following peripherals out of reset via GPIOs
+ * 0 = reset and 1 = out of reset
+ * GPIO12 - Reset to Ethernet Switch
+ * GPIO13 - Reset to SLIC/SLAC devices
+ * GPIO14 - Reset to SGMII_PHY_N
+ * GPIO15 - Reset to PCIe slots
+ * GPIO6 - Reset to RGMII PHY
+ * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
+ */
+ clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR;
+
+ setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN);
+ setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON);
+#endif
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ unsigned int orig_bus = i2c_get_bus_num();
+ u8 i2c_data;
+
+ i2c_set_bus_num(1);
+ if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
+ 1, &i2c_data, sizeof(i2c_data)) == 0) {
+ if (i2c_data & 0x2)
+ puts("NOR Flash Bank : Secondary\n");
+ else
+ puts("NOR Flash Bank : Primary\n");
+
+ if (i2c_data & 0x1) {
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+ puts("SD/MMC : 8-bit Mode\n");
+ puts("eSPI : Disabled\n");
+ } else {
+ puts("SD/MMC : 4-bit Mode\n");
+ puts("eSPI : Enabled\n");
+ }
+ } else {
+ puts("Failed reading I2C Chip 0x18 on bus 1\n");
+ }
+ i2c_set_bus_num(orig_bus);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_16M, 1);
+ rtc_reset();
+ return 0;
+}
+
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ int num = 0;
+ char *tmp;
+ unsigned int vscfw_addr;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ if (is_serdes_configured(SGMII_TSEC3)) {
+ puts("eTSEC3 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+#ifdef CONFIG_VSC7385_ENET
+/* If a VSC7385 microcode image is present, then upload it. */
+ if ((tmp = getenv ("vscfw_addr")) != NULL) {
+ vscfw_addr = simple_strtoul (tmp, NULL, 16);
+ printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+ if (vsc7385_upload_firmware((void *) vscfw_addr,
+ CONFIG_VSC7385_IMAGE_SIZE))
+ puts("Failure uploading VSC7385 microcode.\n");
+ } else
+ puts("No address specified for VSC7385 microcode.\n");
+#endif
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_pci_board_setup(void *blob);
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ const char *soc_usb_compat = "fsl-usb2-dr";
+ int err, usb1_off, usb2_off;
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+#if defined(CONFIG_PCI)
+ ft_pci_board_setup(blob);
+#endif /* #if defined(CONFIG_PCI) */
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+ /* Delete eLBC node as it is muxed with USB2 controller */
+ if (hwconfig("usb2")) {
+ const char *soc_elbc_compat = "fsl,p1020-elbc";
+ int off = fdt_node_offset_by_compatible(blob, -1,
+ soc_elbc_compat);
+ if (off < 0) {
+ printf("WARNING: could not find compatible node %s\n",
+ soc_elbc_compat);
+ return off;
+ }
+ err = fdt_del_node(blob, off);
+ if (err < 0) {
+ printf("WARNING: could not remove %s\n",
+ soc_elbc_compat);
+ return err;
+ }
+ return 0;
+ }
+#endif
+ /* Delete USB2 node as it is muxed with eLBC */
+ usb1_off = fdt_node_offset_by_compatible(blob, -1,
+ soc_usb_compat);
+ if (usb1_off < 0) {
+ printf("WARNING: could not find compatible node %s\n",
+ soc_usb_compat);
+ return usb1_off;
+ }
+ usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
+ soc_usb_compat);
+ if (usb2_off < 0) {
+ printf("WARNING: could not find compatible node %s\n",
+ soc_usb_compat);
+ return usb2_off;
+ }
+ err = fdt_del_node(blob, usb2_off);
+ if (err < 0) {
+ printf("WARNING: could not remove %s\n", soc_usb_compat);
+ return err;
+ }
+
+ return 0;
+}
+
+#endif
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
new file mode 100644
index 0000000..745ebb1
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void ft_pci_board_setup(void *blob)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/p1_p2_rdb/spl.c b/board/freescale/p1_p2_rdb/spl.c
new file mode 100644
index 0000000..f30c5fe
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/spl.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SYSCLK_MASK 0x00200000
+#define BOARDREV_MASK 0x10100000
+
+#define SYSCLK_66 66666666
+#define SYSCLK_100 100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 val_gpdat, sysclk_gpio;
+
+ val_gpdat = in_be32(&pgpio->gpdat);
+ sysclk_gpio = val_gpdat & SYSCLK_MASK;
+
+ if (sysclk_gpio == 0)
+ return SYSCLK_66;
+ else
+ return SYSCLK_100;
+
+ return 0;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, bus_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* Set pmuxcr to allow both i2c1 and i2c2 */
+ setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+ setbits_be32(&gur->pmuxcr,
+ in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+ /* Read back the register to synchronize the write. */
+ in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ gd->bus_clk = bus_clk;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI Flash boot...\n");
+#endif
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("Tertiary program loader running in sram...");
+#else
+ puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/p1_p2_rdb/spl_minimal.c b/board/freescale/p1_p2_rdb/spl_minimal.c
new file mode 100644
index 0000000..96a4d1c
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/spl_minimal.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#define SYSCLK_MASK 0x00200000
+#define BOARDREV_MASK 0x10100000
+
+#define SYSCLK_66 66666666
+#define SYSCLK_100 100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 val_gpdat, sysclk_gpio;
+
+ val_gpdat = in_be32(&pgpio->gpdat);
+ sysclk_gpio = val_gpdat & SYSCLK_MASK;
+
+ if (sysclk_gpio == 0)
+ return SYSCLK_66;
+ else
+ return SYSCLK_100;
+
+ return 0;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("\nSecond program loader running in sram...");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
new file mode 100644
index 0000000..73f5729
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* W**G* - Flash/promjet, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_16M, 1),
+
+#if defined(CONFIG_PCI)
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+
+#endif /* #if defined(CONFIG_PCI) */
+#endif
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_1M, 1),
+
+ /* *I*G - VSC7385 Switch */
+ SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1),
+#endif
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_1G, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig
new file mode 100644
index 0000000..d3352d2
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P1_P2_RDB_PC
+
+config SYS_BOARD
+ default "p1_p2_rdb_pc"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "p1_p2_rdb_pc"
+
+endif
diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS
new file mode 100644
index 0000000..c2e9247
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS
@@ -0,0 +1,51 @@
+P1_P2_RDB_PC BOARD
+#M: -
+S: Maintained
+F: board/freescale/p1_p2_rdb_pc/
+F: include/configs/p1_p2_rdb_pc.h
+F: configs/P1020MBG-PC_defconfig
+F: configs/P1020MBG-PC_36BIT_defconfig
+F: configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+F: configs/P1020MBG-PC_SDCARD_defconfig
+F: configs/P1020RDB-PC_defconfig
+F: configs/P1020RDB-PC_36BIT_defconfig
+F: configs/P1020RDB-PC_36BIT_NAND_defconfig
+F: configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+F: configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+F: configs/P1020RDB-PC_NAND_defconfig
+F: configs/P1020RDB-PC_SDCARD_defconfig
+F: configs/P1020RDB-PC_SPIFLASH_defconfig
+F: configs/P1020RDB-PD_defconfig
+F: configs/P1020RDB-PD_NAND_defconfig
+F: configs/P1020RDB-PD_SDCARD_defconfig
+F: configs/P1020RDB-PD_SPIFLASH_defconfig
+F: configs/P1020UTM-PC_defconfig
+F: configs/P1020UTM-PC_36BIT_defconfig
+F: configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+F: configs/P1020UTM-PC_SDCARD_defconfig
+F: configs/P1021RDB-PC_defconfig
+F: configs/P1021RDB-PC_36BIT_defconfig
+F: configs/P1021RDB-PC_36BIT_NAND_defconfig
+F: configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+F: configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+F: configs/P1021RDB-PC_NAND_defconfig
+F: configs/P1021RDB-PC_SDCARD_defconfig
+F: configs/P1021RDB-PC_SPIFLASH_defconfig
+F: configs/P1024RDB_defconfig
+F: configs/P1024RDB_36BIT_defconfig
+F: configs/P1024RDB_NAND_defconfig
+F: configs/P1024RDB_SDCARD_defconfig
+F: configs/P1024RDB_SPIFLASH_defconfig
+F: configs/P1025RDB_defconfig
+F: configs/P1025RDB_36BIT_defconfig
+F: configs/P1025RDB_NAND_defconfig
+F: configs/P1025RDB_SDCARD_defconfig
+F: configs/P1025RDB_SPIFLASH_defconfig
+F: configs/P2020RDB-PC_defconfig
+F: configs/P2020RDB-PC_36BIT_defconfig
+F: configs/P2020RDB-PC_36BIT_NAND_defconfig
+F: configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+F: configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+F: configs/P2020RDB-PC_NAND_defconfig
+F: configs/P2020RDB-PC_SDCARD_defconfig
+F: configs/P2020RDB-PC_SPIFLASH_defconfig
diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
new file mode 100644
index 0000000..a2a1f92
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/Makefile
@@ -0,0 +1,29 @@
+#
+# Copyright 2010-2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+obj-y += spl_minimal.o tlb.o law.o
+
+else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
+obj-y += p1_p2_rdb_pc.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
+
+endif
diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README
new file mode 100644
index 0000000..f4cc43f
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/README
@@ -0,0 +1,47 @@
+Overview
+--------
+P1_P2_RDB_PC represents a set of boards including
+ P1020MSBG-PC
+ P1020RDB-PC
+ P1020RDB-PD
+ P1020UTM-PC
+ P1021RDB-PC
+ P1024RDB
+ P1025RDB
+ P2020RDB-PC
+
+They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
+has 64-bit DDR. All others have 32-bit DDR.
+
+Key features on these boards include:
+ * DDR3
+ * NOR flash
+ * NAND flash (on RDB's only)
+ * SPI flash (on RDB's only)
+ * SDHC/MMC card slot
+ * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
+ * PCIE slot and mini-PCIE slots
+
+As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
+is used to store SPD data. In case of absent or corrupted SPD, falling back
+to timing data embedded in the source code will be used. Raw timing data is
+extracted from DDR chip datasheet. Different speeds of DDR are supported with
+this approach. ODT option is forced to fit this set of boards, again because
+they don't have regular DIMMs.
+
+CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification
+for writing timing.
+
+VSC firmware Address is defined by default in config file for eTSEC1.
+
+SD width is based off DIP switch. DIP switch is detected on the
+board by reading i2c bus and setting the appropriate mux values.
+
+Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have
+pins multiplexing. QE function needs to be disabled to access Nor Flash and
+CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
+in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
+enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below
+
+'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
+'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
new file mode 100644
index 0000000..946d503
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -0,0 +1,294 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+#if defined(CONFIG_P1020RDB_PROTO) || \
+ defined(CONFIG_P1021RDB) || \
+ defined(CONFIG_P1020UTM)
+/* Micron MT41J256M8_187E */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 1073741824u,
+ .capacity = 1073741824u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1870,
+ .caslat_x = 0x1e << 4, /* 5,6,7,8 */
+ .taa_ps = 13125,
+ .twr_ps = 15000,
+ .trcd_ps = 13125,
+ .trrd_ps = 7500,
+ .trp_ps = 13125,
+ .tras_ps = 37500,
+ .trc_ps = 50625,
+ .trfc_ps = 160000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 37500,
+};
+#elif defined(CONFIG_P2020RDB)
+/* Micron MT41J128M16_15E */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 1073741824u,
+ .capacity = 1073741824u,
+ .primary_sdram_width = 64,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 14,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1500,
+ .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
+ .taa_ps = 13500,
+ .twr_ps = 15000,
+ .trcd_ps = 13500,
+ .trrd_ps = 6000,
+ .trp_ps = 13500,
+ .tras_ps = 36000,
+ .trc_ps = 49500,
+ .trfc_ps = 160000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 30000,
+};
+#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
+/* Micron MT41J512M8_187E */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 2,
+ .rank_density = 1073741824u,
+ .capacity = 2147483648u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1870,
+ .caslat_x = 0x1e << 4, /* 5,6,7,8 */
+ .taa_ps = 13125,
+ .twr_ps = 15000,
+ .trcd_ps = 13125,
+ .trrd_ps = 7500,
+ .trp_ps = 13125,
+ .tras_ps = 37500,
+ .trc_ps = 50625,
+ .trfc_ps = 160000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 37500,
+};
+#elif defined(CONFIG_P1020RDB_PC)
+/*
+ * Samsung K4B2G0846C-HCF8
+ * The following timing are for "downshift"
+ * i.e. to use CL9 part as CL7
+ * otherwise, tAA, tRCD, tRP will be 13500ps
+ * and tRC will be 49500ps
+ */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 1073741824u,
+ .capacity = 1073741824u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1875,
+ .caslat_x = 0x1e << 4, /* 5,6,7,8 */
+ .taa_ps = 13125,
+ .twr_ps = 15000,
+ .trcd_ps = 13125,
+ .trrd_ps = 7500,
+ .trp_ps = 13125,
+ .tras_ps = 37500,
+ .trc_ps = 50625,
+ .trfc_ps = 160000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 37500,
+};
+#elif defined(CONFIG_P1024RDB) || \
+ defined(CONFIG_P1025RDB)
+/*
+ * Samsung K4B2G0846C-HCH9
+ * The following timing are for "downshift"
+ * i.e. to use CL9 part as CL7
+ * otherwise, tAA, tRCD, tRP will be 13500ps
+ * and tRC will be 49500ps
+ */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 1073741824u,
+ .capacity = 1073741824u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1500,
+ .caslat_x = 0x3e << 4, /* 5,6,7,8,9 */
+ .taa_ps = 13125,
+ .twr_ps = 15000,
+ .trcd_ps = 13125,
+ .trrd_ps = 6000,
+ .trp_ps = 13125,
+ .tras_ps = 36000,
+ .trc_ps = 49125,
+ .trfc_ps = 160000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 30000,
+};
+#else
+#error Missing raw timing data for this board
+#endif
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
+
+#ifdef CONFIG_SYS_DDR_CS0_BNDS
+/* Fixed sdram init -- doesn't use serial presence detect. */
+phys_size_t fixed_sdram(void)
+{
+ sys_info_t sysinfo;
+ char buf[32];
+ size_t ddr_size;
+ fsl_ddr_cfg_regs_t ddr_cfg_regs = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+#endif
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+ .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+ };
+
+ get_sys_info(&sysinfo);
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, sysinfo.freq_ddrbus));
+
+ ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ };
+
+ return ddr_size;
+}
+#endif
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ int i;
+ popts->clk_adjust = 6;
+ popts->cpo_override = 0x1f;
+ popts->write_data_delay = 2;
+ popts->half_strength_driver_enable = 1;
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x8;
+ popts->trwt_override = 1;
+ popts->trwt = 0;
+
+ if (pdimm->primary_sdram_width == 64)
+ popts->data_bus_width = 0;
+ else if (pdimm->primary_sdram_width == 32)
+ popts->data_bus_width = 1;
+ else
+ printf("Error in DDR bus width configuration!\n");
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+ popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+ }
+}
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
new file mode 100644
index 0000000..90ec39f
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_VSC7385_ENET
+ SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
new file mode 100644
index 0000000..3f47cfb
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -0,0 +1,499 @@
+/*
+ * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <hwconfig.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_lbc.h>
+#include <asm/mp.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <vsc7385.h>
+#include <ioports.h>
+#include <asm/fsl_serdes.h>
+#include <netdev.h>
+
+#ifdef CONFIG_QE
+
+#define GPIO_GETH_SW_PORT 1
+#define GPIO_GETH_SW_PIN 29
+#define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN))
+
+#define GPIO_SLIC_PORT 1
+#define GPIO_SLIC_PIN 30
+#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
+
+#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
+#define GPIO_DDR_RST_PORT 1
+#define GPIO_DDR_RST_PIN 8
+#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
+
+#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
+#endif
+
+#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
+#define PCA_IOPORT_I2C_ADDR 0x23
+#define PCA_IOPORT_OUTPUT_CMD 0x2
+#define PCA_IOPORT_CFG_CMD 0x6
+#define PCA_IOPORT_QE_PIN_ENABLE 0xf8
+#define PCA_IOPORT_QE_TDM_ENABLE 0xf6
+#endif
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* GPIO */
+ {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
+#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
+ {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
+#endif
+ {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
+ {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
+ {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
+
+#ifdef CONFIG_P1025RDB
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
+
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
+ {0, 17, 2, 0, 2}, /* ENET1_CRS */
+ {0, 16, 2, 0, 2}, /* ENET1_COL */
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
+#endif
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
+struct cpld_data {
+ u8 cpld_rev_major;
+ u8 pcba_rev;
+ u8 wd_cfg;
+ u8 rst_bps_sw;
+ u8 load_default_n;
+ u8 rst_bps_wd;
+ u8 bypass_enable;
+ u8 bps_led;
+ u8 status_led; /* offset: 0x8 */
+ u8 fxo_led; /* offset: 0x9 */
+ u8 fxs_led; /* offset: 0xa */
+ u8 rev4[2];
+ u8 system_rst; /* offset: 0xd */
+ u8 bps_out;
+ u8 rev5[3];
+ u8 cpld_rev_minor;
+};
+
+#define CPLD_WD_CFG 0x03
+#define CPLD_RST_BSW 0x00
+#define CPLD_RST_BWD 0x00
+#define CPLD_BYPASS_EN 0x03
+#define CPLD_STATUS_LED 0x01
+#define CPLD_FXO_LED 0x01
+#define CPLD_FXS_LED 0x0F
+#define CPLD_SYS_RST 0x00
+
+void board_cpld_init(void)
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+
+ out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
+ out_8(&cpld_data->status_led, CPLD_STATUS_LED);
+ out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
+ out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
+ out_8(&cpld_data->system_rst, CPLD_SYS_RST);
+}
+
+void board_gpio_init(void)
+{
+#ifdef CONFIG_QE
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
+
+#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
+ /* reset DDR3 */
+ setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
+ udelay(1000);
+ clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
+ udelay(1000);
+ setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
+ /* disable CE_PB8 */
+ clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
+#endif
+ /* Enable VSC7385 switch */
+ setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
+
+ /* Enable SLIC */
+ setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
+#else
+
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+
+ /*
+ * GPIO10 DDR Reset, open drain
+ * GPIO7 LOAD_DEFAULT_N Input
+ * GPIO11 WDI (watchdog input)
+ * GPIO12 Ethernet Switch Reset
+ * GPIO13 SLIC Reset
+ */
+
+ setbits_be32(&pgpio->gpdir, 0x02130000);
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
+ /* init DDR3 reset signal */
+ setbits_be32(&pgpio->gpdir, 0x00200000);
+ setbits_be32(&pgpio->gpodr, 0x00200000);
+ clrbits_be32(&pgpio->gpdat, 0x00200000);
+ udelay(1000);
+ setbits_be32(&pgpio->gpdat, 0x00200000);
+ udelay(1000);
+ clrbits_be32(&pgpio->gpdir, 0x00200000);
+#endif
+
+#ifdef CONFIG_VSC7385_ENET
+ /* reset VSC7385 Switch */
+ setbits_be32(&pgpio->gpdir, 0x00080000);
+ setbits_be32(&pgpio->gpdat, 0x00080000);
+#endif
+
+#ifdef CONFIG_SLIC
+ /* reset SLIC */
+ setbits_be32(&pgpio->gpdir, 0x00040000);
+ setbits_be32(&pgpio->gpdat, 0x00040000);
+#endif
+#endif
+}
+
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->pmuxcr,
+ (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+ clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
+
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
+
+ board_gpio_init();
+ board_cpld_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u8 in, out, io_config, val;
+
+ printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
+ in_8(&cpld_data->cpld_rev_major) & 0x0F,
+ in_8(&cpld_data->cpld_rev_minor) & 0x0F,
+ in_8(&cpld_data->pcba_rev) & 0x0F);
+
+ /* Initialize i2c early for rom_loc and flash bank information */
+ i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
+
+ if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
+ i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
+ i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
+ printf("Error reading i2c boot information!\n");
+ return 0; /* Don't want to hang() on this error */
+ }
+
+ val = (in & io_config) | (out & (~io_config));
+
+ puts("rom_loc: ");
+ if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
+ puts("sd");
+#ifdef __SW_BOOT_SPI
+ } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
+ puts("spi");
+#endif
+#ifdef __SW_BOOT_NAND
+ } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
+ puts("nand");
+#endif
+#ifdef __SW_BOOT_PCIE
+ } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
+ puts("pcie");
+#endif
+ } else {
+ if (val & 0x2)
+ puts("nor lower bank");
+ else
+ puts("nor upper bank");
+ }
+ puts("\n");
+
+ if (val & 0x1) {
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+ puts("SD/MMC : 8-bit Mode\n");
+ puts("eSPI : Disabled\n");
+ } else {
+ puts("SD/MMC : 4-bit Mode\n");
+ puts("eSPI : Enabled\n");
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
+ 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ ccsr_gur_t *gur __attribute__((unused)) =
+ (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int num = 0;
+#ifdef CONFIG_VSC7385_ENET
+ char *tmp;
+ unsigned int vscfw_addr;
+#endif
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ if (is_serdes_configured(SGMII_TSEC2)) {
+ printf("eTSEC2 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ num++;
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+#ifdef CONFIG_VSC7385_ENET
+ /* If a VSC7385 microcode image is present, then upload it. */
+ if ((tmp = getenv("vscfw_addr")) != NULL) {
+ vscfw_addr = simple_strtoul(tmp, NULL, 16);
+ printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+ if (vsc7385_upload_firmware((void *) vscfw_addr,
+ CONFIG_VSC7385_IMAGE_SIZE))
+ puts("Failure uploading VSC7385 microcode.\n");
+ } else
+ puts("No address specified for VSC7385 microcode.\n");
+#endif
+
+ mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+#if defined(CONFIG_UEC_ETH)
+ /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
+
+ uec_standard_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_QE) && \
+ (defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB))
+static void fdt_board_fixup_qe_pins(void *blob)
+{
+ unsigned int oldbus;
+ u8 val8;
+ int node;
+ fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ if (hwconfig("qe")) {
+ /* For QE and eLBC pins multiplexing,
+ * there is a PCA9555 device on P1025RDB.
+ * It control the multiplex pins' functions,
+ * and setting the PCA9555 can switch the
+ * function between QE and eLBC.
+ */
+ oldbus = i2c_get_bus_num();
+ i2c_set_bus_num(0);
+ if (hwconfig("tdm"))
+ val8 = PCA_IOPORT_QE_TDM_ENABLE;
+ else
+ val8 = PCA_IOPORT_QE_PIN_ENABLE;
+ i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
+ 1, &val8, 1);
+ i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
+ 1, &val8, 1);
+ i2c_set_bus_num(oldbus);
+ /* if run QE TDM, Set ABSWP to implement
+ * conversion of addresses in the eLBC.
+ */
+ if (hwconfig("tdm")) {
+ set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
+ set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
+ setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+ }
+ } else {
+ node = fdt_path_offset(blob, "/qe");
+ if (node >= 0)
+ fdt_del_node(blob, node);
+ }
+
+ return;
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+ const char *soc_usb_compat = "fsl-usb2-dr";
+ int err, usb1_off, usb2_off;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_QE
+ do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
+ sizeof("okay"), 0);
+#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
+ fdt_board_fixup_qe_pins(blob);
+#endif
+#endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+ /* Delete eLBC node as it is muxed with USB2 controller */
+ if (hwconfig("usb2")) {
+ const char *soc_elbc_compat = "fsl,p1020-elbc";
+ int off = fdt_node_offset_by_compatible(blob, -1,
+ soc_elbc_compat);
+ if (off < 0) {
+ printf("WARNING: could not find compatible node %s\n",
+ soc_elbc_compat);
+ return off;
+ }
+ err = fdt_del_node(blob, off);
+ if (err < 0) {
+ printf("WARNING: could not remove %s\n",
+ soc_elbc_compat);
+ return err;
+ }
+ return 0;
+ }
+#endif
+
+/* Delete USB2 node as it is muxed with eLBC */
+ usb1_off = fdt_node_offset_by_compatible(blob, -1,
+ soc_usb_compat);
+ if (usb1_off < 0) {
+ printf("WARNING: could not find compatible node %s\n",
+ soc_usb_compat);
+ return usb1_off;
+ }
+ usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
+ soc_usb_compat);
+ if (usb2_off < 0) {
+ printf("WARNING: could not find compatible node %s\n",
+ soc_usb_compat);
+ return usb2_off;
+ }
+ err = fdt_del_node(blob, usb2_off);
+ if (err < 0) {
+ printf("WARNING: could not remove %s\n", soc_usb_compat);
+ return err;
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
new file mode 100644
index 0000000..8d0d850
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const u32 sysclk_tbl[] = {
+ 66666000, 7499900, 83332500, 8999900,
+ 99999000, 11111000, 12499800, 13333200
+};
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, bus_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* Set pmuxcr to allow both i2c1 and i2c2 */
+ setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+ setbits_be32(&gur->pmuxcr,
+ in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+ /* Read back the register to synchronize the write. */
+ in_be32(&gur->pmuxcr);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+ gd->bus_clk = bus_clk;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI Flash boot...\n");
+#endif
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+ env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+#else
+ env_relocate();
+#endif
+
+#ifdef CONFIG_SYS_I2C
+ i2c_init_all();
+#else
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+ gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("Tertiary program loader running in sram...");
+#else
+ puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
new file mode 100644
index 0000000..92437bc
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ puts("\nSecond program loader running in sram...");
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
new file mode 100644
index 0000000..1c0008b
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* W**G* - Flash/promjet, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_PCI
+ /* *I*G* - PCI memory 1.5G */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O effective: 192K */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#ifdef CONFIG_VSC7385_ENET
+ /* *I*G - VSC7385 Switch */
+ SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_1M, 1),
+#endif
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_64K, 1),
+#endif /* not SPL */
+
+#ifdef CONFIG_SYS_NAND_BASE
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_1M, 1),
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+ /* *I*G - eSDHC/eSPI/NAND boot */
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+
+#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)
+ /* 2G DDR on P1020MBG, map the second 1G */
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_1G, 1),
+#endif /* P1020MBG */
+#endif /* RAMBOOT/SPL */
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1),
+#if CONFIG_SYS_L2_SIZE >= (256 << 10)
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1_twr/Kconfig b/board/freescale/p1_twr/Kconfig
new file mode 100644
index 0000000..8f9a8d4
--- /dev/null
+++ b/board/freescale/p1_twr/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P1_TWR
+
+config SYS_BOARD
+ default "p1_twr"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "p1_twr"
+
+endif
diff --git a/board/freescale/p1_twr/MAINTAINERS b/board/freescale/p1_twr/MAINTAINERS
new file mode 100644
index 0000000..c19d436
--- /dev/null
+++ b/board/freescale/p1_twr/MAINTAINERS
@@ -0,0 +1,6 @@
+P1_TWR BOARD
+#M: -
+S: Maintained
+F: board/freescale/p1_twr/
+F: include/configs/p1_twr.h
+F: configs/TWR-P1025_defconfig
diff --git a/board/freescale/p1_twr/Makefile b/board/freescale/p1_twr/Makefile
new file mode 100644
index 0000000..70afac4
--- /dev/null
+++ b/board/freescale/p1_twr/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += p1_twr.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c
new file mode 100644
index 0000000..a2ce75a
--- /dev/null
+++ b/board/freescale/p1_twr/ddr.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+/* Fixed sdram init -- doesn't use serial presence detect. */
+phys_size_t fixed_sdram(void)
+{
+ sys_info_t sysinfo;
+ char buf[32];
+ size_t ddr_size;
+ fsl_ddr_cfg_regs_t ddr_cfg_regs = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+ .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
+ .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
+ .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
+#endif
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
+ .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+ };
+
+ get_sys_info(&sysinfo);
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, sysinfo.freq_ddrbus));
+
+ ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
+
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ };
+
+ return ddr_size;
+}
diff --git a/board/freescale/p1_twr/law.c b/board/freescale/p1_twr/law.c
new file mode 100644
index 0000000..e79d8a4
--- /dev/null
+++ b/board/freescale/p1_twr/law.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_SSD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
new file mode 100644
index 0000000..a40bea3
--- /dev/null
+++ b/board/freescale/p1_twr/p1_twr.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <hwconfig.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_lbc.h>
+#include <asm/mp.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <ioports.h>
+#include <asm/fsl_serdes.h>
+#include <netdev.h>
+
+#define SYSCLK_64 64000000
+#define SYSCLK_66 66666666
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
+ unsigned int cpdat_val = 0;
+
+ /* Set-up up pin muxing based on board switch settings */
+ cpdat_val = par_io[1].cpdat;
+
+ /* Check switch setting for SYSCLK select (PB3) */
+ if (cpdat_val & 0x10000000)
+ return SYSCLK_64;
+ else
+ return SYSCLK_66;
+
+ return 0;
+}
+
+#ifdef CONFIG_QE
+
+#define PCA_IOPORT_I2C_ADDR 0x23
+#define PCA_IOPORT_OUTPUT_CMD 0x2
+#define PCA_IOPORT_CFG_CMD 0x6
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+
+#ifdef CONFIG_TWR_P1025
+ /* GPIO */
+ {1, 0, 1, 0, 0},
+ {1, 18, 1, 0, 0},
+
+ /* GPIO for switch options */
+ {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
+ {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */
+ {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
+ {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */
+
+ /* QE_MUX_MDC */
+ {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
+
+ /* QE_MUX_MDIO */
+ {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
+
+ /* UCC_1_MII */
+ {0, 23, 2, 0, 2}, /* CLK12 */
+ {0, 24, 2, 0, 1}, /* CLK9 */
+ {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
+ {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
+ {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
+ {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
+ {0, 17, 2, 0, 2}, /* ENET1_CRS */
+ {0, 16, 2, 0, 2}, /* ENET1_COL */
+
+ /* UCC_5_RMII */
+ {1, 11, 2, 0, 1}, /* CLK13 */
+ {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
+ {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
+ {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
+ {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
+ {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
+ {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
+ {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
+
+ /* TDMA - clock option is configured in OS based on board setting */
+ {1, 23, 2, 0, 2}, /* TDMA_TXD */
+ {1, 25, 2, 0, 2}, /* TDMA_RXD */
+ {1, 26, 1, 0, 2}, /* TDMA_SYNC */
+#endif
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+#endif
+
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->pmuxcr,
+ (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+
+ /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
+ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u8 boot_status;
+
+ printf("Board: %s\n", CONFIG_BOARDNAME);
+
+ boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
+ puts("rom_loc: ");
+ if (boot_status == PORBMSR_ROMLOC_NOR)
+ puts("nor flash");
+ else if (boot_status == PORBMSR_ROMLOC_SDHC)
+ puts("sd");
+ else
+ puts("unknown");
+ puts("\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
+ 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ ccsr_gur_t *gur __attribute__((unused)) =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ if (is_serdes_configured(SGMII_TSEC2)) {
+ printf("eTSEC2 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ num++;
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+#if defined(CONFIG_UEC_ETH)
+ /* QE0 and QE3 need to be exposed for UCC1
+ * and UCC5 Eth mode (in PMUXCR register).
+ * Currently QE/LBC muxed pins assumed to be
+ * LBC for U-Boot and PMUXCR updated by OS if required */
+
+ uec_standard_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_QE)
+static void fdt_board_fixup_qe_pins(void *blob)
+{
+ int node;
+
+ if (!hwconfig("qe")) {
+ /* For QE and eLBC pins multiplexing,
+ * When don't use QE function, remove
+ * qe node from dt blob.
+ */
+ node = fdt_path_offset(blob, "/qe");
+ if (node >= 0)
+ fdt_del_node(blob, node);
+ } else {
+ /* For TWR Peripheral Modules - TWR-SER2
+ * board only can support Signal Port MII,
+ * so delete one UEC node when use MII port.
+ */
+ if (hwconfig("mii"))
+ node = fdt_path_offset(blob, "/qe/ucc@2400");
+ else
+ node = fdt_path_offset(blob, "/qe/ucc@2000");
+ if (node >= 0)
+ fdt_del_node(blob, node);
+ }
+
+ return;
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_QE
+ do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
+ sizeof("okay"), 0);
+#endif
+#if defined(CONFIG_TWR_P1025)
+ fdt_board_fixup_qe_pins(blob);
+#endif
+ fdt_fixup_dr_usb(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/p1_twr/tlb.c b/board/freescale/p1_twr/tlb.c
new file mode 100644
index 0000000..308335c
--- /dev/null
+++ b/board/freescale/p1_twr/tlb.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* W**G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_64M, 1),
+
+ /* W**G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_PCI
+ /* *I*G* - PCI memory 1.5G */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O effective: 192K */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#endif
+
+#ifdef CONFIG_SYS_RAMBOOT
+ /* *I*G - eSDHC boot */
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p2020come/Kconfig b/board/freescale/p2020come/Kconfig
new file mode 100644
index 0000000..8ce5cf1
--- /dev/null
+++ b/board/freescale/p2020come/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P2020COME
+
+config SYS_BOARD
+ default "p2020come"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "P2020COME"
+
+endif
diff --git a/board/freescale/p2020come/MAINTAINERS b/board/freescale/p2020come/MAINTAINERS
new file mode 100644
index 0000000..ab3ef94
--- /dev/null
+++ b/board/freescale/p2020come/MAINTAINERS
@@ -0,0 +1,7 @@
+P2020COME BOARD
+M: Ira W. Snyder <iws@ovro.caltech.edu>
+S: Maintained
+F: board/freescale/p2020come/
+F: include/configs/P2020COME.h
+F: configs/P2020COME_SDCARD_defconfig
+F: configs/P2020COME_SPIFLASH_defconfig
diff --git a/board/freescale/p2020come/Makefile b/board/freescale/p2020come/Makefile
new file mode 100644
index 0000000..4857136
--- /dev/null
+++ b/board/freescale/p2020come/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += p2020come.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c
new file mode 100644
index 0000000..b642e12
--- /dev/null
+++ b/board/freescale/p2020come/ddr.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2009, 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ if (ctrl_num) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * Set DDR_SDRAM_CLK_CNTL = 0x02800000
+ *
+ * Clock is launched 5/8 applied cycle after address/command
+ */
+ popts->clk_adjust = 5;
+}
diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c
new file mode 100644
index 0000000..7048a08
--- /dev/null
+++ b/board/freescale/p2020come/law.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Create a dummy LAW entry for the DDR SDRAM which will be replaced when
+ * the DDR SPD setup code runs.
+ *
+ * This table would be empty, except that it is used before the BSS section is
+ * initialized, and therefore must have at least one entry to push it into
+ * the DATA section.
+ */
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_SDRAM_BASE, LAW_SIZE_4K, LAW_TRGT_IF_DDR),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c
new file mode 100644
index 0000000..1db37e3
--- /dev/null
+++ b/board/freescale/p2020come/p2020come.c
@@ -0,0 +1,275 @@
+/*
+ * Copyright 2009,2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/mpc85xx_gpio.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <vsc7385.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <malloc.h>
+#include <i2c.h>
+
+#if defined(CONFIG_PCI)
+#include <asm/fsl_pci.h>
+#include <pci.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_PCI)
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void ft_pci_board_setup(void *blob)
+{
+ FT_FSL_PCI_SETUP;
+}
+#endif
+
+#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \
+ SGMII_PHY_RST_SET | PCIE_RST_SET | \
+ RGMII_PHY_RST_SET)
+
+#define SYSCLK_MASK 0x00200000
+#define BOARDREV_MASK 0x10100000
+#define BOARDREV_B 0x10100000
+#define BOARDREV_C 0x00100000
+#define BOARDREV_D 0x00000000
+
+#define SYSCLK_66 66666666
+#define SYSCLK_50 50000000
+#define SYSCLK_100 100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
+
+ ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+ switch (ddr_ratio) {
+ case 0x0C:
+ return SYSCLK_66;
+ case 0x0A:
+ case 0x08:
+ return SYSCLK_100;
+ default:
+ puts("ERROR: unknown DDR ratio\n");
+ return SYSCLK_100;
+ }
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
+
+ ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+ switch (ddr_ratio) {
+ case 0x0C:
+ case 0x0A:
+ return SYSCLK_66;
+ case 0x08:
+ return SYSCLK_100;
+ default:
+ puts("ERROR: unknown DDR ratio\n");
+ return SYSCLK_100;
+ }
+}
+
+#ifdef CONFIG_MMC
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->pmuxcr,
+ (MPC85xx_PMUXCR_SDHC_CD |
+ MPC85xx_PMUXCR_SDHC_WP));
+
+ /* All the device are enable except for SRIO12 */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO);
+ return 0;
+}
+#endif
+
+#define GPIO_DIR 0x0f3a0000
+#define GPIO_ODR 0x00000000
+#define GPIO_DAT 0x001a0000
+
+int checkboard(void)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
+
+ /*
+ * GPIO
+ * 0 - 3: CarryBoard Input;
+ * 4 - 7: CarryBoard Output;
+ * 8 : Mux as SDHC_CD (card detection)
+ * 9 : Mux as SDHC_WP
+ * 10 : Clear Watchdog timer
+ * 11 : LED Input
+ * 12 : Output to 1
+ * 13 : Open Drain
+ * 14 : LED Output
+ * 15 : Switch Input
+ *
+ * Set GPIOs 11, 12, 14 to 1.
+ */
+ out_be32(&pgpio->gpodr, GPIO_ODR);
+ mpc85xx_gpio_set(0xffffffff, GPIO_DIR, GPIO_DAT);
+
+ puts("Board: Freescale COM Express P2020\n");
+ return 0;
+}
+
+#define M41ST85W_I2C_BUS 1
+#define M41ST85W_I2C_ADDR 0x68
+#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
+
+static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
+{
+ u8 data;
+
+ if (i2c_read(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
+ M41ST85W_ERROR("unable to read %s bit\n", name);
+ return;
+ }
+
+ if (data & mask) {
+ data &= ~mask;
+ if (i2c_write(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
+ M41ST85W_ERROR("unable to clear %s bit\n", name);
+ return;
+ }
+ }
+}
+
+#define M41ST85W_REG_SEC2 0x01
+#define M41ST85W_REG_SEC2_ST 0x80
+
+#define M41ST85W_REG_ALHOUR 0x0c
+#define M41ST85W_REG_ALHOUR_HT 0x40
+
+/*
+ * The P2020COME board has a STMicro M41ST85W RTC/watchdog
+ * at i2c bus 1 address 0x68.
+ */
+static void start_rtc(void)
+{
+ unsigned int bus = i2c_get_bus_num();
+
+ if (i2c_set_bus_num(M41ST85W_I2C_BUS)) {
+ M41ST85W_ERROR("unable to set i2c bus\n");
+ goto out;
+ }
+
+ /* ensure ST (stop) and HT (halt update) bits are cleared */
+ m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST");
+ m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT");
+
+out:
+ /* reset the i2c bus */
+ i2c_set_bus_num(bus);
+}
+
+int board_early_init_r(void)
+{
+ start_rtc();
+ return 0;
+}
+
+#define M41ST85W_REG_WATCHDOG 0x09
+#define M41ST85W_REG_WATCHDOG_WDS 0x80
+#define M41ST85W_REG_WATCHDOG_BMB0 0x04
+
+void board_reset(void)
+{
+ u8 data = M41ST85W_REG_WATCHDOG_WDS | M41ST85W_REG_WATCHDOG_BMB0;
+
+ /* set the hardware watchdog timeout to 1/16 second, then hang */
+ i2c_set_bus_num(M41ST85W_I2C_BUS);
+ i2c_write(M41ST85W_I2C_ADDR, M41ST85W_REG_WATCHDOG, 1, &data, 1);
+
+ while (1)
+ /* hang */;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ if (is_serdes_configured(SGMII_TSEC3)) {
+ puts("eTSEC3 is in sgmii mode.");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+ if (!num) {
+ printf("No TSECs initialized\n");
+ return 0;
+ }
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+#if defined(CONFIG_PCI)
+ ft_pci_board_setup(blob);
+#endif
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c
new file mode 100644
index 0000000..08a1e34
--- /dev/null
+++ b/board/freescale/p2020come/tlb.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_PCI)
+ /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI1 0xD000,0000 - 0xDFFF,FFFF, size = 256M */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * *I*G* - PCI I/O
+ *
+ * PCI3 => 0xFFC10000
+ * PCI2 => 0xFFC2,0000
+ * PCI1 => 0xFFC3,0000
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+#endif /* #if defined(CONFIG_PCI) */
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ /* *I*G - DDR3 2G Part 1: 0 - 0x3fff,ffff , size = 1G */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* DDR3 2G Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p2020ds/Kconfig b/board/freescale/p2020ds/Kconfig
new file mode 100644
index 0000000..e527ec9
--- /dev/null
+++ b/board/freescale/p2020ds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P2020DS
+
+config SYS_BOARD
+ default "p2020ds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "P2020DS"
+
+endif
diff --git a/board/freescale/p2020ds/MAINTAINERS b/board/freescale/p2020ds/MAINTAINERS
new file mode 100644
index 0000000..cb61fc5
--- /dev/null
+++ b/board/freescale/p2020ds/MAINTAINERS
@@ -0,0 +1,10 @@
+P2020DS BOARD
+#M: -
+S: Maintained
+F: board/freescale/p2020ds/
+F: include/configs/P2020DS.h
+F: configs/P2020DS_defconfig
+F: configs/P2020DS_36BIT_defconfig
+F: configs/P2020DS_DDR2_defconfig
+F: configs/P2020DS_SDCARD_defconfig
+F: configs/P2020DS_SPIFLASH_defconfig
diff --git a/board/freescale/p2020ds/Makefile b/board/freescale/p2020ds/Makefile
new file mode 100644
index 0000000..ee00806
--- /dev/null
+++ b/board/freescale/p2020ds/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += p2020ds.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
new file mode 100644
index 0000000..debe70b
--- /dev/null
+++ b/board/freescale/p2020ds/ddr.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ *
+ * ranges for parameters:
+ * wr_data_delay = 0-6
+ * clk adjust = 0-8
+ * cpo 2-0x1E (30)
+ */
+static const struct board_specific_parameters dimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| cpo|wrdata|2T
+ * ranks| mhz|adjst| | delay|
+ */
+#ifdef CONFIG_SYS_FSL_DDR2
+ {2, 549, 4, 0x1f, 2, 0},
+ {2, 680, 4, 0x1f, 3, 0},
+ {2, 850, 4, 0x1f, 4, 0},
+ {1, 549, 4, 0x1f, 2, 0},
+ {1, 680, 4, 0x1f, 3, 0},
+ {1, 850, 4, 0x1f, 4, 0},
+#else
+ {2, 850, 6, 0x1f, 4, 0},
+ {1, 850, 4, 0x1f, 4, 0},
+#endif
+ {}
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+ int i;
+
+ if (ctrl_num) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+ * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+ * there are two dimms in the controller, set odt_rd_cfg to 3 and
+ * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+ */
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 1;
+ }
+
+ pbsp = dimm0;
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->twot_en = pbsp->force_2t;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->twot_en = pbsp_highest->force_2t;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+
+found:
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ popts->wrlvl_en = 1;
+ /* Write leveling override */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xa;
+ popts->wrlvl_start = 0x8;
+ /* Rtt and Rtt_WR override */
+ popts->rtt_override = 1;
+ popts->rtt_override_value = DDR3_RTT_120_OHM;
+ popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
+}
diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c
new file mode 100644
index 0000000..9cd4da9
--- /dev/null
+++ b/board/freescale/p2020ds/law.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
new file mode 100644
index 0000000..5d18e8d
--- /dev/null
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <asm/fsl_law.h>
+#include <netdev.h>
+
+#include "../common/ngpixis.h"
+#include "../common/sgmii_riser.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_MMC
+ ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->pmuxcr,
+ (MPC85xx_PMUXCR_SDHC_CD |
+ MPC85xx_PMUXCR_SDHC_WP));
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ u8 sw;
+
+ printf("Board: P2020DS Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
+
+ sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
+ sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ /* The lower two bits are the actual vbank number */
+ printf("vBank: %d\n", sw & 3);
+ else
+ puts("Promjet\n");
+
+ return 0;
+}
+
+#if !defined(CONFIG_DDR_SPD)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram(void)
+{
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+ uint d_init;
+
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+ ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+ ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+ ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+ ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
+ ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
+ ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
+ ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
+ ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
+ ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
+
+ if (!strcmp("performance", getenv("perf_mode"))) {
+ /* Performance Mode Values */
+
+ ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
+ ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
+
+ asm("sync;isync");
+
+ udelay(500);
+
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
+ } else {
+ /* Stable Mode Values */
+
+ ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+
+ /* ECC will be assumed in stable mode */
+ ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
+ ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
+ ddr->err_sbe = CONFIG_SYS_DDR_SBE;
+
+ asm("sync;isync");
+
+ udelay(500);
+
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+ }
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ d_init = 1;
+ debug("DDR - 1st controller: memory initializing\n");
+ /*
+ * Poll until memory is initialized.
+ * 512 Meg at 400 might hit this 200 times or so.
+ */
+ while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
+ udelay(1000);
+ debug("DDR: memory initialized\n\n");
+ asm("sync; isync");
+ udelay(500);
+#endif
+
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
+ LAW_TRGT_IF_DDR) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ };
+
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+
+#endif
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ return 0;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ if (is_serdes_configured(SGMII_TSEC2)) {
+ puts("eTSEC2 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ if (is_serdes_configured(SGMII_TSEC3)) {
+ puts("eTSEC3 is in sgmii mode.\n");
+ tsec_info[num].flags |= TSEC_SGMII;
+}
+ num++;
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+
+ return 0;
+ }
+
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_init(tsec_info, num);
+#endif
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+ FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_fdt_fixup(blob);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c
new file mode 100644
index 0000000..02da6e8
--- /dev/null
+++ b/board/freescale/p2020ds/tlb.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* W**G* - Flash/promjet, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_1M, 1),
+
+ SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_4K, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_256K, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p2041rdb/Kconfig b/board/freescale/p2041rdb/Kconfig
new file mode 100644
index 0000000..78e1121
--- /dev/null
+++ b/board/freescale/p2041rdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P2041RDB
+
+config SYS_BOARD
+ default "p2041rdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "P2041RDB"
+
+endif
diff --git a/board/freescale/p2041rdb/MAINTAINERS b/board/freescale/p2041rdb/MAINTAINERS
new file mode 100644
index 0000000..d93cb0b
--- /dev/null
+++ b/board/freescale/p2041rdb/MAINTAINERS
@@ -0,0 +1,11 @@
+P2041RDB BOARD
+#M: -
+S: Maintained
+F: board/freescale/p2041rdb/
+F: include/configs/P2041RDB.h
+F: configs/P2041RDB_defconfig
+F: configs/P2041RDB_NAND_defconfig
+F: configs/P2041RDB_SDCARD_defconfig
+F: configs/P2041RDB_SECURE_BOOT_defconfig
+F: configs/P2041RDB_SPIFLASH_defconfig
+F: configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile
new file mode 100644
index 0000000..c74f4c6
--- /dev/null
+++ b/board/freescale/p2041rdb/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2011 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += p2041rdb.o
+obj-y += cpld.o
+obj-y += ddr.o
+obj-y += eth.o
diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README
new file mode 100644
index 0000000..9b5539f
--- /dev/null
+++ b/board/freescale/p2041rdb/README
@@ -0,0 +1,123 @@
+Overview
+=========
+The P2041 Processor combines four Power Architecture processor cores
+with high-performance datapath acceleration architecture(DPAA), CoreNet
+fabric infrastructure, as well as network and peripheral bus interfaces
+required for networking, telecom/datacom, wireless infrastructure, and
+military/aerospace applications.
+
+P2041RDB board is a quad core platform supporting the P2041 processor
+of QorIQ DPAA series.
+
+Boot from NOR flash
+===================
+1. Build image
+ make P2041RDB_config
+ make all
+
+2. Program image
+ => tftp 1000000 u-boot.bin
+ => protect off all
+ => erase eff40000 efffffff
+ => cp.b 1000000 eff40000 c0000
+
+3. Program RCW
+ => tftp 1000000 rcw.bin
+ => protect off all
+ => erase e8000000 e801ffff
+ => cp.b 1000000 e8000000 50
+
+4. Program FMAN Firmware ucode
+ => tftp 1000000 ucode.bin
+ => protect off all
+ => erase eff00000 eff3ffff
+ => cp.b 1000000 eff00000 2000
+
+5. Change DIP-switch
+ SW1[1-5] = 10110
+ Note: 1 stands for 'on', 0 stands for 'off'
+
+Boot from SDCard
+===================
+1. Build image
+ make P2041RDB_SDCARD_config
+ make all
+
+2. Generate PBL imge
+ Use PE tool to produce a image used to be programed to
+ SDCard which contains RCW and U-Boot image.
+
+3. Program the PBL image to SDCard
+ => tftp 1000000 pbl_sd.bin
+ => mmcinfo
+ => mmc write 1000000 8 672
+
+4. Program FMAN Firmware ucode
+ => tftp 1000000 ucode.bin
+ => mmc write 1000000 690 10
+
+5. Change DIP-switch
+ SW1[1-5] = 01100
+ Note: 1 stands for 'on', 0 stands for 'off'
+
+Boot from SPI flash
+===================
+1. Build image
+ make P2041RDB_SPIFLASH_config
+ make all
+
+2. Generate PBL imge
+ Use PE tool to produce a image used to be programed to
+ SPI flash which contains RCW and U-Boot image.
+
+3. Program the PBL image to SPI flash
+ => tftp 1000000 pbl_spi.bin
+ => spi probe 0
+ => sf erase 0 100000
+ => sf write 1000000 0 $filesize
+
+4. Program FMAN Firmware ucode
+ => tftp 1000000 ucode.bin
+ => sf erase 110000 10000
+ => sf write 1000000 110000 $filesize
+
+5. Change DIP-switch
+ SW1[1-5] = 10100
+ Note: 1 stands for 'on', 0 stands for 'off'
+
+CPLD command
+============
+The CPLD is used to control the power sequence and some serdes lane
+mux function.
+
+cpld reset - hard reset to default bank
+cpld reset altbank - reset to alternate bank
+cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
+ lane 6: 0 -> slot1 (Default)
+ 1 -> SGMII
+ lane a: 0 -> slot2 (Default)
+ 1 -> AURORA
+ lane c: 0 -> slot2 (Default)
+ 1 -> SATA0
+ lane d: 0 -> slot2 (Default)
+ 1 -> SATA1
+
+Using the Device Tree Source File
+=================================
+To create the DTB (Device Tree Binary) image file, use a command
+similar to this:
+ dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb
+
+Or use the following command:
+ {linux-2.6}/make p2041rdb.dtb ARCH=powerpc
+
+then the dtb file will be generated under the following directory:
+ {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb
+
+Booting Linux
+=============
+Place a linux uImage in the TFTP disk area.
+ tftp 1000000 uImage
+ tftp 2000000 rootfs.ext2.gz.uboot
+ tftp 3000000 p2041rdb.dtb
+ bootm 1000000 2000000 3000000
diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c
new file mode 100644
index 0000000..34901aa
--- /dev/null
+++ b/board/freescale/p2041rdb/cpld.c
@@ -0,0 +1,158 @@
+/**
+ * Copyright 2011 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the board-specific CPLD used on some Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CPLD_BASE - The virtual address of the base of the CPLD register map
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "cpld.h"
+
+static u8 __cpld_read(unsigned int reg)
+{
+ void *p = (void *)CPLD_BASE;
+
+ return in_8(p + reg);
+}
+u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read")));
+
+static void __cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+void cpld_write(unsigned int reg, u8 value)
+ __attribute__((weak, alias("__cpld_write")));
+
+/*
+ * Reset the board. This honors the por_cfg registers.
+ */
+void __cpld_reset(void)
+{
+ CPLD_WRITE(system_rst, 1);
+}
+void cpld_reset(void) __attribute__((weak, alias("__cpld_reset")));
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void __cpld_set_altbank(void)
+{
+ u8 reg5 = CPLD_READ(sw_ctl_on);
+
+ CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE);
+ CPLD_WRITE(fbank_sel, 1);
+ CPLD_WRITE(system_rst, 1);
+}
+void cpld_set_altbank(void)
+ __attribute__((weak, alias("__cpld_set_altbank")));
+
+/**
+ * Set the boot bank to the default bank
+ */
+void __cpld_set_defbank(void)
+{
+ CPLD_WRITE(system_rst_default, 1);
+}
+void cpld_set_defbank(void)
+ __attribute__((weak, alias("__cpld_set_defbank")));
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+ printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
+ printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
+ printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver));
+ printf("system_rst = 0x%02x\n", CPLD_READ(system_rst));
+ printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on));
+ printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg));
+ printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe));
+ printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel));
+ printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk));
+ printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk));
+ printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel));
+ printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux));
+ printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2)));
+ putc('\n');
+}
+#endif
+
+int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (strcmp(argv[2], "altbank") == 0)
+ cpld_set_altbank();
+ else
+ cpld_set_defbank();
+ } else if (strcmp(argv[1], "lane_mux") == 0) {
+ u32 lane = simple_strtoul(argv[2], NULL, 16);
+ u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
+ u8 reg = CPLD_READ(serdes_mux);
+
+ switch (lane) {
+ case 0x6:
+ reg &= ~SERDES_MUX_LANE_6_MASK;
+ reg |= val << SERDES_MUX_LANE_6_SHIFT;
+ break;
+ case 0xa:
+ reg &= ~SERDES_MUX_LANE_A_MASK;
+ reg |= val << SERDES_MUX_LANE_A_SHIFT;
+ break;
+ case 0xc:
+ reg &= ~SERDES_MUX_LANE_C_MASK;
+ reg |= val << SERDES_MUX_LANE_C_SHIFT;
+ break;
+ case 0xd:
+ reg &= ~SERDES_MUX_LANE_D_MASK;
+ reg |= val << SERDES_MUX_LANE_D_SHIFT;
+ break;
+ default:
+ printf("Invalid value\n");
+ break;
+ }
+
+ CPLD_WRITE(serdes_mux, reg);
+#ifdef DEBUG
+ } else if (strcmp(argv[1], "dump") == 0) {
+ cpld_dump_regs();
+#endif
+ } else
+ rc = cmd_usage(cmdtp);
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
+ "Reset the board or pin mulexing selection using the CPLD sequencer",
+ "reset - hard reset to default bank\n"
+ "cpld_cmd reset altbank - reset to alternate bank\n"
+ "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
+ " lane 6: 0 -> slot1\n"
+ " 1 -> SGMII (Default)\n"
+ " lane a: 0 -> slot2\n"
+ " 1 -> AURORA (Default)\n"
+ " lane c: 0 -> slot2\n"
+ " 1 -> SATA0 (Default)\n"
+ " lane d: 0 -> slot2\n"
+ " 1 -> SATA1 (Default)\n"
+#ifdef DEBUG
+ "cpld_cmd dump - display the CPLD registers\n"
+#endif
+ );
diff --git a/board/freescale/p2041rdb/cpld.h b/board/freescale/p2041rdb/cpld.h
new file mode 100644
index 0000000..64487f1
--- /dev/null
+++ b/board/freescale/p2041rdb/cpld.h
@@ -0,0 +1,55 @@
+/**
+ * Copyright 2011 Freescale Semiconductor
+ * Author: Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/*
+ * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
+ */
+typedef struct cpld_data {
+ u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
+ u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
+ u8 pcba_ver; /* 0x2 - PCBA Revision Register */
+ u8 system_rst; /* 0x3 - system reset register */
+ u8 res0; /* 0x4 - not used */
+ u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */
+ u8 por_cfg; /* 0x6 - POR Control Register */
+ u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */
+ u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */
+ u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */
+ u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */
+ u8 fbank_sel; /* 0xb - Flash bank selection */
+ u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */
+ u8 sw[1]; /* 0xd - SW2 Status */
+ u8 system_rst_default; /* 0xe - system reset to default register */
+ u8 sysclk_sw1; /* 0xf - sysclk configuration register */
+} __attribute__ ((packed)) cpld_data_t;
+
+#define SERDES_MUX_LANE_6_MASK 0x2
+#define SERDES_MUX_LANE_6_SHIFT 1
+#define SERDES_MUX_LANE_A_MASK 0x1
+#define SERDES_MUX_LANE_A_SHIFT 0
+#define SERDES_MUX_LANE_C_MASK 0x4
+#define SERDES_MUX_LANE_C_SHIFT 2
+#define SERDES_MUX_LANE_D_MASK 0x8
+#define SERDES_MUX_LANE_D_SHIFT 3
+#define CPLD_SWITCH_BANK_ENABLE 0x40
+#define CPLD_SYSCLK_83 0x1 /* system clock 83.3MHz */
+#define CPLD_SYSCLK_100 0x2 /* system clock 100MHz */
+
+/* Pointer to the CPLD register set */
+#define cpld ((cpld_data_t *)CPLD_BASE)
+
+/* The CPLD SW register that corresponds to board switch X, where x >= 1 */
+#define CPLD_SW(x) (cpld->sw[(x) - 2])
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg))
+#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value)
diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c
new file mode 100644
index 0000000..b8bbcdf
--- /dev/null
+++ b/board/freescale/p2041rdb/ddr.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ *
+ * ranges for parameters:
+ * wr_data_delay = 0-6
+ * clk adjust = 0-8
+ * cpo 2-0x1E (30)
+ */
+static const struct board_specific_parameters dimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | delay|
+ */
+ {2, 750, 3, 5, 0xff, 2, 0},
+ {2, 1250, 4, 6, 0xff, 2, 0},
+ {2, 1350, 5, 7, 0xff, 2, 0},
+ {2, 1666, 5, 8, 0xff, 2, 0},
+ {}
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = dimm0;
+
+ /*
+ * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->twot_en = pbsp->force_2t;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s!\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->twot_en = pbsp_highest->force_2t;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+
+found:
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /* Write leveling override */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /* Rtt and Rtt_WR override */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 60 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size = 0;
+
+ puts("Initializing....");
+
+ if (fsl_use_spd()) {
+ puts("using SPD\n");
+ dram_size = fsl_ddr_sdram();
+ } else {
+ puts("no SPD and fixed parameters\n");
+ return dram_size;
+ }
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ debug(" DDR: ");
+ return dram_size;
+}
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
new file mode 100644
index 0000000..532eeac
--- /dev/null
+++ b/board/freescale/p2041rdb/eth.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Author: Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
+ * are provided by the three on-board PHY or by the standard Freescale
+ * four-port SGMII riser card. We need to change the phy-handle in the
+ * kernel dts file to point to the correct PHY according to serdes mux
+ * and serdes protocol selection.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/fsl_dtsec.h>
+
+#include "cpld.h"
+#include "../common/fman.h"
+
+#ifdef CONFIG_FMAN_ENET
+/*
+ * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot
+ */
+static u8 lane_to_slot[] = {
+ 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
+};
+
+static int riser_phy_addr[] = {
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
+ CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
+ CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
+ CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
+};
+
+/*
+ * Initialize the lane_to_slot[] array.
+ *
+ * On the P2040RDB board the mapping is controlled by CPLD register.
+ */
+static void initialize_lane_to_slot(void)
+{
+ u8 mux = CPLD_READ(serdes_mux);
+
+ lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1;
+ lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2;
+ lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2;
+ lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;
+}
+
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) An Fman port
+ *
+ * ... update the phy-handle property of the Ethernet node to point to the
+ * right PHY. This assumes that we already know the PHY for each port.
+ *
+ * The offset of the Fman Ethernet node is also passed in for convenience, but
+ * it is not used, and we recalculate the offset anyway.
+ *
+ * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
+ * Inside the Fman, "ports" are things that connect to MACs. We only call them
+ * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
+ * and ports are the same thing.
+ *
+ */
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ phy_interface_t intf = fm_info_get_enet_if(port);
+ char phy[16];
+
+ /* The RGMII PHY is identified by the MAC connected to it */
+ if (intf == PHY_INTERFACE_MODE_RGMII) {
+ sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
+ fdt_set_phy_handle(fdt, compat, addr, phy);
+ }
+
+ /* The SGMII PHY is identified by the MAC connected to it */
+ if (intf == PHY_INTERFACE_MODE_SGMII) {
+ int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
+ u8 slot;
+ if (lane < 0)
+ return;
+ slot = lane_to_slot[lane];
+ if (slot) {
+ sprintf(phy, "phy_sgmii_%x",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+ + (port - FM1_DTSEC1));
+ fdt_set_phy_handle(fdt, compat, addr, phy);
+ } else {
+ sprintf(phy, "phy_sgmii_%x",
+ CONFIG_SYS_FM1_DTSEC1_PHY_ADDR
+ + (port - FM1_DTSEC1));
+ fdt_set_phy_handle(fdt, compat, addr, phy);
+ }
+ }
+
+ if (intf == PHY_INTERFACE_MODE_XGMII) {
+ /* XAUI */
+ int lane = serdes_get_first_lane(XAUI_FM1);
+ if (lane >= 0) {
+ /* The XAUI PHY is identified by the slot */
+ sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
+ fdt_set_phy_handle(fdt, compat, addr, phy);
+ }
+ }
+}
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct fsl_pq_mdio_info dtsec_mdio_info;
+ struct tgec_mdio_info tgec_mdio_info;
+ unsigned int i, slot;
+ int lane;
+
+ printf("Initializing Fman\n");
+
+ initialize_lane_to_slot();
+
+ dtsec_mdio_info.regs =
+ (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the real 1G MDIO bus */
+ fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the real 10G MDIO bus */
+ fm_tgec_mdio_init(bis, &tgec_mdio_info);
+
+ /*
+ * Program the three on-board SGMII PHY addresses. If the SGMII Riser
+ * card used, we'll override the PHY address later. For any DTSEC that
+ * is RGMII, we'll also override its PHY address later. We assume that
+ * DTSEC4 and DTSEC5 are used for RGMII.
+ */
+ fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot[lane];
+ if (slot)
+ fm_info_set_phy_address(i, riser_phy_addr[i]);
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
+ fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
+ CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
+ CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+ break;
+ default:
+ printf("Fman1: DTSEC%u set to unknown interface %i\n",
+ idx + 1, fm_info_get_enet_if(i));
+ break;
+ }
+
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ }
+
+ lane = serdes_get_first_lane(XAUI_FM1);
+ if (lane >= 0) {
+ slot = lane_to_slot[lane];
+ if (slot)
+ fm_info_set_phy_address(FM1_10GEC1,
+ CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+ }
+
+ fm_info_set_mdio(FM1_10GEC1,
+ miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
new file mode 100644
index 0000000..e600bdb
--- /dev/null
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright 2011,2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+extern void pci_of_setup(void *blob, bd_t *bd);
+
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ u8 sw;
+ struct cpu_type *cpu = gd->arch.cpu;
+ unsigned int i;
+
+ printf("Board: %sRDB, ", cpu->name);
+ printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
+ CPLD_READ(cpld_ver_sub));
+
+ sw = CPLD_READ(fbank_sel);
+ printf("vBank: %d\n", sw & 0x1);
+
+ /*
+ * Display the actual SERDES reference clocks as configured by the
+ * dip switches on the board. Note that the SWx registers could
+ * technically be set to force the reference clocks to match the
+ * values that the SERDES expects (or vice versa). For now, however,
+ * we just display both values and hope the user notices when they
+ * don't match.
+ */
+ puts("SERDES Reference Clocks: ");
+ sw = in_8(&CPLD_SW(2)) >> 2;
+ for (i = 0; i < 2; i++) {
+ static const char * const freq[][3] = {{"0", "100", "125"},
+ {"100", "156.25", "125"}
+ };
+ unsigned int clock = (sw >> (2 * i)) & 3;
+
+ printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
+ }
+ puts("\n");
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
+ setbits_be32(&gur->ddrclkdr, 0x000f000f);
+
+ return 0;
+}
+
+#define CPLD_LANE_A_SEL 0x1
+#define CPLD_LANE_G_SEL 0x2
+#define CPLD_LANE_C_SEL 0x4
+#define CPLD_LANE_D_SEL 0x8
+
+void board_config_lanes_mux(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+ u8 mux = 0;
+ switch (srds_prtcl) {
+ case 0x2:
+ case 0x5:
+ case 0x9:
+ case 0xa:
+ case 0xf:
+ break;
+ case 0x8:
+ mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+ break;
+ case 0x14:
+ mux |= CPLD_LANE_A_SEL;
+ break;
+ case 0x17:
+ mux |= CPLD_LANE_G_SEL;
+ break;
+ case 0x16:
+ case 0x19:
+ case 0x1a:
+ mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+ break;
+ case 0x1c:
+ mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
+ break;
+ default:
+ printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
+ break;
+ }
+ CPLD_WRITE(serdes_mux, mux);
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+ setup_portals();
+ board_config_lanes_mux();
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(unsigned long dummy)
+{
+ u8 sysclk_conf = CPLD_READ(sysclk_sw1);
+
+ switch (sysclk_conf & 0x7) {
+ case CPLD_SYSCLK_83:
+ return 83333333;
+ case CPLD_SYSCLK_100:
+ return 100000000;
+ default:
+ return 66666666;
+ }
+}
+
+#define NUM_SRDS_BANKS 2
+
+int misc_init_r(void)
+{
+ serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 actual[NUM_SRDS_BANKS];
+ unsigned int i;
+ u8 sw;
+ static const int freq[][3] = {
+ {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
+ {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
+ SRDS_PLLCR0_RFCK_SEL_125}
+ };
+
+ sw = in_8(&CPLD_SW(2)) >> 2;
+ for (i = 0; i < NUM_SRDS_BANKS; i++) {
+ unsigned int clock = (sw >> (2 * i)) & 3;
+ if (clock == 0x3) {
+ printf("Warning: SDREFCLK%u switch setting of '11' is "
+ "unsupported\n", i + 1);
+ break;
+ }
+ if (i == 0 && clock == 0)
+ puts("Warning: SDREFCLK1 switch setting of"
+ "'00' is unsupported\n");
+ else
+ actual[i] = freq[i][clock];
+
+ /*
+ * PC board uses a different CPLD with PB board, this CPLD
+ * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
+ * board has cpld_ver_sub = 0, and pcba_ver = 4.
+ */
+ if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
+ (CPLD_READ(pcba_ver) == 5)) {
+ /* PC board bank2 frequency */
+ actual[i] = freq[i-1][clock];
+ }
+ }
+
+ for (i = 0; i < NUM_SRDS_BANKS; i++) {
+ u32 expected = in_be32(®s->bank[i].pllcr0);
+ expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
+ if (expected != actual[i]) {
+ printf("Warning: SERDES bank %u expects reference clock"
+ " %sMHz, but actual is %sMHz\n", i + 1,
+ serdes_clock_to_string(expected),
+ serdes_clock_to_string(actual[i]));
+ }
+ }
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+#endif
+
+ return 0;
+}
diff --git a/board/freescale/qemu-ppce500/Kconfig b/board/freescale/qemu-ppce500/Kconfig
new file mode 100644
index 0000000..236cd17
--- /dev/null
+++ b/board/freescale/qemu-ppce500/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_QEMU_PPCE500
+
+config SYS_BOARD
+ default "qemu-ppce500"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "qemu-ppce500"
+
+endif
diff --git a/board/freescale/qemu-ppce500/MAINTAINERS b/board/freescale/qemu-ppce500/MAINTAINERS
new file mode 100644
index 0000000..77d0a4a
--- /dev/null
+++ b/board/freescale/qemu-ppce500/MAINTAINERS
@@ -0,0 +1,6 @@
+QEMU-PPCE500 BOARD
+M: Alexander Graf <agraf@suse.de>
+S: Maintained
+F: board/freescale/qemu-ppce500/
+F: include/configs/qemu-ppce500.h
+F: configs/qemu-ppce500_defconfig
diff --git a/board/freescale/qemu-ppce500/Makefile b/board/freescale/qemu-ppce500/Makefile
new file mode 100644
index 0000000..2d27492
--- /dev/null
+++ b/board/freescale/qemu-ppce500/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += qemu-ppce500.o
diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c
new file mode 100644
index 0000000..a0fca0d
--- /dev/null
+++ b/board/freescale/qemu-ppce500/qemu-ppce500.c
@@ -0,0 +1,370 @@
+/*
+ * Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void *get_fdt_virt(void)
+{
+ return (void *)CONFIG_SYS_TMPVIRT;
+}
+
+static uint64_t get_fdt_phys(void)
+{
+ return (uint64_t)(uintptr_t)gd->fdt_blob;
+}
+
+static void map_fdt_as(int esel)
+{
+ u32 mas0, mas1, mas2, mas3, mas7;
+ uint64_t fdt_phys = get_fdt_phys();
+ unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful;
+ unsigned long fdt_virt_tlb = (ulong)get_fdt_virt() & ~0xffffful;
+
+ mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(esel);
+ mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
+ mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0);
+ mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR);
+ mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb);
+
+ write_tlb(mas0, mas1, mas2, mas3, mas7);
+}
+
+uint64_t get_phys_ccsrbar_addr_early(void)
+{
+ void *fdt = get_fdt_virt();
+ uint64_t r;
+
+ /*
+ * To be able to read the FDT we need to create a temporary TLB
+ * map for it.
+ */
+ map_fdt_as(10);
+ r = fdt_get_base_address(fdt, fdt_path_offset(fdt, "/soc"));
+ disable_tlb(10);
+
+ return r;
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ return 0;
+}
+
+static int pci_map_region(void *fdt, int pci_node, int range_id,
+ phys_size_t *ppaddr, pci_addr_t *pvaddr,
+ pci_size_t *psize, ulong *pmap_addr)
+{
+ uint64_t addr;
+ uint64_t size;
+ ulong map_addr;
+ int r;
+
+ r = fdt_read_range(fdt, pci_node, 0, NULL, &addr, &size);
+ if (r)
+ return r;
+
+ if (ppaddr)
+ *ppaddr = addr;
+ if (psize)
+ *psize = size;
+
+ if (!pmap_addr)
+ return 0;
+
+ map_addr = *pmap_addr;
+
+ /* Align map_addr */
+ map_addr += size - 1;
+ map_addr &= ~(size - 1);
+
+ if (map_addr + size >= CONFIG_SYS_PCI_MAP_END)
+ return -1;
+
+ /* Map virtual memory for range */
+ assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO));
+ *pmap_addr = map_addr + size;
+
+ if (pvaddr)
+ *pvaddr = map_addr;
+
+ return 0;
+}
+
+void pci_init_board(void)
+{
+ struct pci_controller *pci_hoses;
+ void *fdt = get_fdt_virt();
+ int pci_node = -1;
+ int pci_num = 0;
+ int pci_count = 0;
+ ulong map_addr;
+
+ puts("\n");
+
+ /* Start MMIO and PIO range maps above RAM */
+ map_addr = CONFIG_SYS_PCI_MAP_START;
+
+ /* Count and allocate PCI buses */
+ pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
+ "device_type", "pci", 4);
+ while (pci_node != -FDT_ERR_NOTFOUND) {
+ pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
+ "device_type", "pci", 4);
+ pci_count++;
+ }
+
+ if (pci_count) {
+ pci_hoses = malloc(sizeof(struct pci_controller) * pci_count);
+ } else {
+ printf("PCI: disabled\n\n");
+ return;
+ }
+
+ /* Spawn PCI buses based on device tree */
+ pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
+ "device_type", "pci", 4);
+ while (pci_node != -FDT_ERR_NOTFOUND) {
+ struct fsl_pci_info pci_info = { };
+ const fdt32_t *reg;
+ int r;
+
+ reg = fdt_getprop(fdt, pci_node, "reg", NULL);
+ pci_info.regs = fdt_translate_address(fdt, pci_node, reg);
+
+ /* Map MMIO range */
+ r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL,
+ &pci_info.mem_size, &map_addr);
+ if (r)
+ break;
+
+ /* Map PIO range */
+ r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL,
+ &pci_info.io_size, &map_addr);
+ if (r)
+ break;
+
+ /*
+ * The PCI framework finds virtual addresses for the buses
+ * through our address map, so tell it the physical addresses.
+ */
+ pci_info.mem_bus = pci_info.mem_phys;
+ pci_info.io_bus = pci_info.io_phys;
+
+ /* Instantiate */
+ pci_info.pci_num = pci_num + 1;
+
+ fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs);
+ printf("PCI: base address %lx\n", pci_info.regs);
+
+ fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num);
+
+ /* Jump to next PCI node */
+ pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
+ "device_type", "pci", 4);
+ pci_num++;
+ }
+
+ puts("\n");
+}
+
+int last_stage_init(void)
+{
+ void *fdt = get_fdt_virt();
+ int len = 0;
+ const uint64_t *prop;
+ int chosen;
+
+ chosen = fdt_path_offset(fdt, "/chosen");
+ if (chosen < 0) {
+ printf("Couldn't find /chosen node in fdt\n");
+ return -EIO;
+ }
+
+ /* -kernel boot */
+ prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len);
+ if (prop && (len >= 8))
+ setenv_hex("qemu_kernel_addr", *prop);
+
+ /* Give the user a variable for the host fdt */
+ setenv_hex("fdt_addr_r", (ulong)fdt);
+
+ return 0;
+}
+
+static uint64_t get_linear_ram_size(void)
+{
+ void *fdt = get_fdt_virt();
+ const void *prop;
+ int memory;
+ int len;
+
+ memory = fdt_path_offset(fdt, "/memory");
+ prop = fdt_getprop(fdt, memory, "reg", &len);
+
+ if (prop && len >= 16)
+ return *(uint64_t *)(prop+8);
+
+ panic("Couldn't determine RAM size");
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+
+ return 0;
+}
+#endif
+
+void print_laws(void)
+{
+ /* We don't emulate LAWs yet */
+}
+
+phys_size_t fixed_sdram(void)
+{
+ return get_linear_ram_size();
+}
+
+phys_size_t fsl_ddr_sdram_size(void)
+{
+ return get_linear_ram_size();
+}
+
+void init_tlbs(void)
+{
+ phys_size_t ram_size;
+
+ /*
+ * Create a temporary AS=1 map for the fdt
+ *
+ * We use ESEL=0 here to overwrite the previous AS=0 map for ourselves
+ * which was only 4k big. This way we don't have to clear any other maps.
+ */
+ map_fdt_as(0);
+
+ /* Fetch RAM size from the fdt */
+ ram_size = get_linear_ram_size();
+
+ /* And remove our fdt map again */
+ disable_tlb(0);
+
+ /* Create an internal map of manually created TLB maps */
+ init_used_tlb_cams();
+
+ /* Create a dynamic AS=0 CCSRBAR mapping */
+ assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ 1024 * 1024, TLB_MAP_IO));
+
+ /* Create a RAM map that spans all accessible RAM */
+ setup_ddr_tlbs(ram_size >> 20);
+
+ /* Create a map for the TLB */
+ assert(!tlb_map_range((ulong)get_fdt_virt(), get_fdt_phys(),
+ 1024 * 1024, TLB_MAP_RAM));
+}
+
+void init_laws(void)
+{
+ /* We don't emulate LAWs yet */
+}
+
+static uint32_t get_cpu_freq(void)
+{
+ void *fdt = get_fdt_virt();
+ int cpus_node = fdt_path_offset(fdt, "/cpus");
+ int cpu_node = fdt_first_subnode(fdt, cpus_node);
+ const char *prop = "clock-frequency";
+ return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
+}
+
+void get_sys_info(sys_info_t *sys_info)
+{
+ int freq = get_cpu_freq();
+
+ memset(sys_info, 0, sizeof(sys_info_t));
+ sys_info->freq_systembus = freq;
+ sys_info->freq_ddrbus = freq;
+ sys_info->freq_processor[0] = freq;
+}
+
+int get_clocks (void)
+{
+ sys_info_t sys_info;
+
+ get_sys_info(&sys_info);
+
+ gd->cpu_clk = sys_info.freq_processor[0];
+ gd->bus_clk = sys_info.freq_systembus;
+ gd->mem_clk = sys_info.freq_ddrbus;
+ gd->arch.lbc_clk = sys_info.freq_ddrbus;
+
+ return 0;
+}
+
+unsigned long get_tbclk (void)
+{
+ void *fdt = get_fdt_virt();
+ int cpus_node = fdt_path_offset(fdt, "/cpus");
+ int cpu_node = fdt_first_subnode(fdt, cpus_node);
+ const char *prop = "timebase-frequency";
+ return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
+}
+
+/********************************************
+ * get_bus_freq
+ * return system bus freq in Hz
+ *********************************************/
+ulong get_bus_freq (ulong dummy)
+{
+ sys_info_t sys_info;
+ get_sys_info(&sys_info);
+ return sys_info.freq_systembus;
+}
+
+/*
+ * Return the number of cores on this SOC.
+ */
+int cpu_numcores(void)
+{
+ /*
+ * The QEMU u-boot target only needs to drive the first core,
+ * spinning and device tree nodes get driven by QEMU itself
+ */
+ return 1;
+}
+
+/*
+ * Return a 32-bit mask indicating which cores are present on this SOC.
+ */
+u32 cpu_mask(void)
+{
+ return (1 << cpu_numcores()) - 1;
+}
diff --git a/board/freescale/t102xqds/Kconfig b/board/freescale/t102xqds/Kconfig
new file mode 100644
index 0000000..4d17798
--- /dev/null
+++ b/board/freescale/t102xqds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_T102XQDS
+
+config SYS_BOARD
+ default "t102xqds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "T102xQDS"
+
+endif
diff --git a/board/freescale/t102xqds/MAINTAINERS b/board/freescale/t102xqds/MAINTAINERS
new file mode 100644
index 0000000..1ffccc4
--- /dev/null
+++ b/board/freescale/t102xqds/MAINTAINERS
@@ -0,0 +1,12 @@
+T102XQDS BOARD
+M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+S: Maintained
+F: board/freescale/t102xqds/
+F: include/configs/T102xQDS.h
+F: configs/T1024QDS_defconfig
+F: configs/T1024QDS_NAND_defconfig
+F: configs/T1024QDS_SDCARD_defconfig
+F: configs/T1024QDS_SPIFLASH_defconfig
+F: configs/T1024QDS_D4_defconfig
+F: configs/T1024QDS_SECURE_BOOT_defconfig
+F: configs/T1024QDS_D4_SECURE_BOOT_defconfig
diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile
new file mode 100644
index 0000000..d94f230
--- /dev/null
+++ b/board/freescale/t102xqds/Makefile
@@ -0,0 +1,17 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += t102xqds.o
+obj-y += eth_t102xqds.o
+obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_FSL_DIU_FB) += ../t1040qds/diu.o
+endif
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t102xqds/README b/board/freescale/t102xqds/README
new file mode 100644
index 0000000..bb0f280
--- /dev/null
+++ b/board/freescale/t102xqds/README
@@ -0,0 +1,328 @@
+T1024 SoC Overview
+------------------
+The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
+combines two or one 64-bit Power Architecture e5500 core respectively with high
+performance datapath acceleration logic, and network peripheral bus interfaces
+required for networking and telecommunications. This processor can be used in
+applications such as enterprise WLAN access points, routers, switches, firewall
+and other packet processing intensive small enterprise and branch office appliances,
+and general-purpose embedded computing. Its high level of integration offers
+significant performance benefits and greatly helps to simplify board design.
+
+
+The T1024 SoC includes the following function and features:
+- two e5500 cores, each with a private 256 KB L2 cache
+ - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
+ - Three levels of instructions: User, supervisor, and hypervisor
+ - Independent boot and reset
+ - Secure boot capability
+- 256 KB shared L3 CoreNet platform cache (CPC)
+- Interconnect CoreNet platform
+ - CoreNet coherency manager supporting coherent and noncoherent transactions
+ with prioritization and bandwidth allocation amongst CoreNet endpoints
+ - 150 Gbps coherent read bandwidth
+- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
+- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
+ - Packet parsing, classification, and distribution
+ - Queue management for scheduling, packet sequencing, and congestion management
+ - Cryptography Acceleration (SEC 5.x)
+ - IEEE 1588 support
+ - Hardware buffer management for buffer allocation and deallocation
+ - MACSEC on DPAA-based Ethernet ports
+- Ethernet interfaces
+ - Four 1 Gbps Ethernet controllers
+- Parallel Ethernet interfaces
+ - Two RGMII interfaces
+- High speed peripheral interfaces
+ - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
+ - One SATA controller supporting 1.5 and 3.0 Gb/s operation
+ - One QSGMII interface
+ - Four SGMII interface supporting 1000 Mbps
+ - Three SGMII interfaces supporting up to 2500 Mbps
+ - 10GbE XFI or 10Base-KR interface
+- Additional peripheral interfaces
+ - Two USB 2.0 controllers with integrated PHY
+ - SD/eSDHC/eMMC
+ - eSPI controller
+ - Four I2C controllers
+ - Four UARTs
+ - Four GPIO controllers
+ - Integrated flash controller (IFC)
+ - LCD interface (DIU) with 12 bit dual data rate
+- Multicore programmable interrupt controller (PIC)
+- Two 8-channel DMA engines
+- Single source clocking implementation
+- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+- QUICC Engine block
+ - 32-bit RISC controller for flexible support of the communications peripherals
+ - Serial DMA channel for receive and transmit on all serial channels
+ - Two universal communication controllers, supporting TDM, HDLC, and UART
+
+T1023 Personality
+------------------
+T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
+unavailable deep sleep. Rest of the blocks are almost same as T1024.
+Differences between T1024 and T1023
+Feature T1024 T1023
+QUICC Engine: yes no
+DIU: yes no
+Deep Sleep: yes no
+I2C controller: 4 3
+DDR: 64-bit 32-bit
+IFC: 32-bit 28-bit
+
+
+T1024QDS board Overview
+-----------------------
+- SERDES Connections
+ 4 lanes supporting the following:
+ - PCI Express: supports Gen 1 and Gen 2
+ - SGMII 1G and SGMII 2.5G
+ - QSGMII
+ - XFI
+ - SATA 2.0
+ - High-speed multiplexers route the SerDes traffic to appropriate slots or connectors.
+ - Aurora debug with dedicated connectors.
+- DDR Controller
+ - Supports up to 1600 MTPS data-rate.
+ - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
+ - Supports Single-, dual- or quad-rank DIMMs
+ - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
+- IFC/Local Bus
+ - NAND Flash: 8-bit, async, up to 2GB
+ - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
+ - NOR devices support 8 virtual banks
+ - Socketed to allow alternate devices
+ - GASIC: Simple (minimal) target within QIXIS FPGA
+ - PromJET rapid memory download support
+ - IFC Debug/Development card
+- Ethernet
+ - Two on-board RGMII 10M/100M/1G ethernet ports.
+ - One QSGMII interface
+ - Four SGMII interface supporting 1Gbps
+ - Three SGMII interfaces supporting 2.5Gbps
+ - one 10Gbps XFI or 10Base-KR interface
+- QIXIS System Logic FPGA
+ - Manages system power and reset sequencing.
+ - Manages the configurations of DUT, board, and clock for dynamic shmoo.
+ - Collects V-I-T data in background for code/power profiling.
+ - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
+ - General fault monitoring and logging.
+ - Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off.
+- Clocks
+ - System and DDR clock (SYSCLK, DDRCLK).
+ - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
+ - Software programmable in 1 MHz increments from 1-200 MHz.
+ - SERDES clocks
+ - Provides clocks to SerDes blocks and slots.
+ - 100 MHz, 125 MHz and 156.25 MHz options.
+ - Spread-spectrum option for 100 MHz.
+- Power Supplies
+ - Dedicated PMBus regulator for VDD and VDDC.
+ - Adjustable from 0.7V to 1.3V at 35A
+ - VDD can be disabled independanty from VDDC for “deep sleep”.
+ - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
+ - VTT/MVREF automatically track operating voltage.
+ - Dedicated 2.5V VPP supply.
+ - Dedicated regulators/filters for AVDD supplies.
+ - Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD.
+- Video
+ - DIU supports video up to 1280x1024x32 bpp.
+ - Chrontel CH7201 for HDMI connection.
+ - TI DS90C387R for direct LCD connection.
+ - Raw (not encoded) video connector for testing or other encoders.
+- USB
+ - Supports two USB 2.0 ports with integrated PHYs.
+ - Two type A ports with 5V@1.5A per port.
+ - Second port can be converted to OTG mini-AB.
+- SDHC
+ For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features:
+ - upport for optional clock feedback paths.
+ - Support for optional high-speed voltage translation direction controls.
+ - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC.
+ - Support for eMMC memory devices.
+- SPI
+ -On-board support of 3 different devices and sizes.
+- Other IO
+ - Two Serial ports
+ - ProfiBus port
+ - Four I2C ports
+
+
+Memory map on T1024QDS
+----------------------
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
+0x0_0000_0000 0x0_ffff_ffff DDR 4GB
+
+
+128MB NOR Flash memory Map
+--------------------------
+Start Address End Address Definition Max size
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
+0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
+0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+SerDes clock vs DIP-switch settings
+-----------------------------------
+SRDS_PRTCL_S1 SD1_REF_CLK1 SD1_REF_CLK2 SW4[1:4]
+0x6F 100MHz 125MHz 1101
+0xD6 100MHz 100MHz 1111
+0x99 156.25MHz 100MHz 1011
+
+
+T1024 Clock frequency
+----------------------
+BIN Core DDR Platform FMan
+Bin1: 1400MHz 1600MT/s 400MHz 700MHz
+Bin2: 1200MHz 1600MT/s 400MHz 600MHz
+Bin3: 1000MHz 1600MT/s 400MHz 500MHz
+
+
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+ a. build NOR boot image
+ $ make T1024QDS_defconfig (For DDR3L, by default)
+ or make T1024QDS_D4_defconfig (For DDR4)
+ $ make
+ b. program u-boot.bin image to NOR flash
+ => tftp 1000000 u-boot.bin
+ => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+ set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
+
+ Switching between default bank0 and alternate bank4 on NOR flash
+ To change boot source to vbank4:
+ via software: run command 'qixis_reset altbank' in u-boot.
+ via DIP-switch: set SW6[1:4] = '0100'
+
+ To change boot source to vbank0:
+ via software: run command 'qixis_reset' in u-boot.
+ via DIP-Switch: set SW6[1:4] = '0000'
+
+2. NAND Boot:
+ a. build PBL image for NAND boot
+ $ make T1024QDS_NAND_defconfig
+ $ make
+ b. program u-boot-with-spl-pbl.bin to NAND flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => nand erase 0 $filesize
+ => nand write 1000000 0 $filesize
+ set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
+
+3. SPI Boot:
+ a. build PBL image for SPI boot
+ $ make T1024QDS_SPIFLASH_defconfig
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SPI flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => sf probe 0
+ => sf erase 0 f0000
+ => sf write 1000000 0 $filesize
+ set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+ a. build PBL image for SD boot
+ $ make T1024QDS_SDCARD_defconfig
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SD/MMC card
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => mmc write 1000000 8 0x800
+ => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
+ => mmc write 1000000 0x820 80
+ set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+DIU/QE-TDM/SDXC settings
+-------------------
+a) For TDM Riser: set pin_mux=tdm in hwconfig
+b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig
+c) For HDMI(DVI): set pin_mux=hdmi in hwconfig
+d) For LCD(DFP): set pin_mux=lcd in hwconfig
+e) For SDXC: set adaptor=sdxc in hwconfig
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (30KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T1024QDS
+-------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB
+0x100000 0x15FFFF u-boot env 8KB
+0x160000 0x17FFFF FMAN Ucode 128KB
+0x180000 0x19FFFF QE Firmware 128KB
+
+
+SD Card memory Map on T1024QDS
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 u-boot img 1MB
+0x800 0016 u-boot env 8KB
+0x820 0256 FMAN Ucode 128KB
+0x920 0256 QE Firmware 128KB
+
+
+SPI Flash memory Map on T1024QDS
+----------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB
+0x100000 0x101FFF u-boot env 8KB
+0x110000 0x12FFFF FMAN Ucode 128KB
+0x130000 0x14FFFF QE Firmware 128KB
+
+
+For more details, please refer to T1024QDS Reference Manual and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
new file mode 100644
index 0000000..46fc64e
--- /dev/null
+++ b/board/freescale/t102xqds/ddr.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * datarate_mhz_high values need to be in ascending order
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ */
+#if defined(CONFIG_SYS_FSL_DDR4)
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
+ {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
+ {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
+ {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
+ {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
+ {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+#else
+#error DDR type not defined
+#endif
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust according to the board ddr freqency and n_banks
+ * specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found\n");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+ debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
+ debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * rtt and rtt_wr override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+#else
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+
+ /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
+ * set DDR bus width to 32bit for T1023
+ */
+ if (cpu->soc_ver == SVR_T1023)
+ popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
+
+#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
+ /* for DDR bus 32bit test on T1024 */
+ popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
+#endif
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+#else
+ /* DDR has been initialised by first stage boot loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
+ return dram_size;
+}
diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c
new file mode 100644
index 0000000..7723f58
--- /dev/null
+++ b/board/freescale/t102xqds/eth_t102xqds.c
@@ -0,0 +1,442 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "t102xqds_qixis.h"
+
+#define EMI_NONE 0xFFFFFFFF
+#define EMI1_RGMII1 0
+#define EMI1_RGMII2 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT2 3
+#define EMI1_SLOT3 4
+#define EMI1_SLOT4 5
+#define EMI1_SLOT5 6
+#define EMI2 7
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+ "T1024QDS_MDIO_RGMII1",
+ "T1024QDS_MDIO_RGMII2",
+ "T1024QDS_MDIO_SLOT1",
+ "T1024QDS_MDIO_SLOT2",
+ "T1024QDS_MDIO_SLOT3",
+ "T1024QDS_MDIO_SLOT4",
+ "T1024QDS_MDIO_SLOT5",
+ "T1024QDS_MDIO_10GC",
+ "NULL",
+};
+
+/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
+static u8 lane_to_slot[] = {2, 3, 4, 5};
+
+static const char *t1024qds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name;
+
+ if (muxval > EMI2)
+ return NULL;
+
+ name = t1024qds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+struct t1024qds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void t1024qds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+
+ if (muxval < 7) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct t1024qds_mdio *priv = bus->priv;
+
+ t1024qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct t1024qds_mdio *priv = bus->priv;
+
+ t1024qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t1024qds_mdio_reset(struct mii_dev *bus)
+{
+ struct t1024qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int t1024qds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct t1024qds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate t1024qds MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate t1024qds private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = t1024qds_mdio_read;
+ bus->write = t1024qds_mdio_write;
+ bus->reset = t1024qds_mdio_reset;
+ sprintf(bus->name, t1024qds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+ return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ struct fixed_link f_link;
+
+ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
+ if (port == FM1_DTSEC3) {
+ fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
+ fdt_setprop(fdt, offset, "phy-connection-type",
+ "rgmii", 5);
+ fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
+ }
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ if (port == FM1_DTSEC1) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_vsc8234_phy_s5");
+ } else if (port == FM1_DTSEC2) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_vsc8234_phy_s4");
+ }
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
+ if (port == FM1_DTSEC3) {
+ fdt_set_phy_handle(fdt, compat, addr,
+ "sgmii_aqr105_phy_s3");
+ }
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
+ switch (port) {
+ case FM1_DTSEC1:
+ fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
+ break;
+ case FM1_DTSEC2:
+ fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2");
+ break;
+ case FM1_DTSEC3:
+ fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3");
+ break;
+ case FM1_DTSEC4:
+ fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4");
+ break;
+ default:
+ break;
+ }
+ fdt_delprop(fdt, offset, "phy-connection-type");
+ fdt_setprop(fdt, offset, "phy-connection-type", "qsgmii", 6);
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+ /* XFI interface */
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ /* no PHY for XFI */
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+ fdt_setprop(fdt, offset, "phy-connection-type", "xgmii", 5);
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+}
+
+/*
+ * This function reads RCW to check if Serdes1{A:D} is configured
+ * to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ switch (srds_s1) {
+ case 0x46:
+ case 0x47:
+ lane_to_slot[1] = 2;
+ break;
+ default:
+ break;
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, idx, lane, slot, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ initialize_lane_to_slot();
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Register the muxing front-ends to the MDIO buses */
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+ t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+ t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
+
+ switch (srds_s1) {
+ case 0xd5:
+ case 0xd6:
+ /* QSGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC1, 0x8);
+ fm_info_set_phy_address(FM1_DTSEC2, 0x9);
+ fm_info_set_phy_address(FM1_DTSEC3, 0xa);
+ fm_info_set_phy_address(FM1_DTSEC4, 0xb);
+ break;
+ case 0x95:
+ case 0x99:
+ /*
+ * XFI does not need a PHY to work, but to avoid U-boot use
+ * default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to XFI
+ * MAC, and should not use a real XAUI PHY address, since
+ * MDIO can access it successfully, and then MDIO thinks the
+ * XAUI card is used for the XFI MAC, which will cause error.
+ */
+ fm_info_set_phy_address(FM1_10GEC1, 4);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x6f:
+ /* SGMII in Slot3, Slot4, Slot5 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x7f:
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
+ break;
+ case 0x47:
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x77:
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
+ break;
+ case 0x5a:
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x6a:
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x5b:
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ case 0x6b:
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
+ break;
+ default:
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ idx = i - FM1_DTSEC1;
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_QSGMII:
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+ } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_2500_FM1_DTSEC1 + idx);
+ } else {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ QSGMII_FM1_A);
+ }
+
+ if (lane < 0)
+ break;
+
+ slot = lane_to_slot[lane];
+ debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+
+ switch (slot) {
+ case 2:
+ mdio_mux[i] = EMI1_SLOT2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 3:
+ mdio_mux[i] = EMI1_SLOT3;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 4:
+ mdio_mux[i] = EMI1_SLOT4;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 5:
+ mdio_mux[i] = EMI1_SLOT5;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ }
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if (i == FM1_DTSEC3)
+ mdio_mux[i] = EMI1_RGMII2;
+ else if (i == FM1_DTSEC4)
+ mdio_mux[i] = EMI1_RGMII1;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ idx = i - FM1_10GEC1;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ XFI_FM1_MAC1 + idx);
+ if (lane < 0)
+ break;
+ mdio_mux[i] = EMI2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/t102xqds/law.c b/board/freescale/t102xqds/law.c
new file mode 100644
index 0000000..b1c9d01
--- /dev/null
+++ b/board/freescale/t102xqds/law.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef QIXIS_BASE_PHYS
+ SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t102xqds/pci.c b/board/freescale/t102xqds/pci.c
new file mode 100644
index 0000000..7369289
--- /dev/null
+++ b/board/freescale/t102xqds/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c
new file mode 100644
index 0000000..08aef6e
--- /dev/null
+++ b/board/freescale/t102xqds/spl.c
@@ -0,0 +1,151 @@
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include "../common/qixis.h"
+#include "t102xqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT)
+ /*
+ * There is T1040 SoC issue where NOR, FPGA are inaccessible during
+ * NAND boot because IFC signals > IFC_AD7 are not enabled.
+ * This workaround changes RCW source to make all signals enabled.
+ */
+ u32 porsr1, pinctl;
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
+
+ porsr1 = in_be32(&gur->porsr1);
+ pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
+ out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
+#endif
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ puts("\nNAND boot...\n");
+#endif
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/t102xqds/t1024_pbi.cfg b/board/freescale/t102xqds/t1024_pbi.cfg
new file mode 100644
index 0000000..7b9e9b0
--- /dev/null
+++ b/board/freescale/t102xqds/t1024_pbi.cfg
@@ -0,0 +1,26 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
diff --git a/board/freescale/t102xqds/t1024_rcw.cfg b/board/freescale/t102xqds/t1024_rcw.cfg
new file mode 100644
index 0000000..4b8f719
--- /dev/null
+++ b/board/freescale/t102xqds/t1024_rcw.cfg
@@ -0,0 +1,10 @@
+# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
+# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
+
+# PBL preamble and RCW header for T1024QDS
+aa55aa55 010e0100
+# Serdes protocol 0x6F
+0810000e 00000000 00000000 00000000
+37800001 00000012 e8104000 21000000
+00000000 00000000 00000000 00030810
+00000000 036c5a00 00000000 00000006
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
new file mode 100644
index 0000000..f3141b5
--- /dev/null
+++ b/board/freescale/t102xqds/t102xqds.c
@@ -0,0 +1,408 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include <hwconfig.h>
+#include <asm/mpc85xx_gpio.h>
+#include "../common/qixis.h"
+#include "t102xqds.h"
+#include "t102xqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ char buf[64];
+ struct cpu_type *cpu = gd->arch.cpu;
+ static const char *const freq[] = {"100", "125", "156.25", "100.0"};
+ int clock;
+ u8 sw = QIXIS_READ(arch);
+
+ printf("Board: %sQDS, ", cpu->name);
+ printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
+ printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+#ifdef CONFIG_SDCARD
+ puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+ puts("SPI\n");
+#else
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw == 0x8)
+ puts("PromJet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else if (sw == 0x15)
+ printf("IFC Card\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
+ puts("SERDES Reference: ");
+ sw = QIXIS_READ(brdcfg[2]);
+ clock = (sw >> 6) & 3;
+ printf("Clock1=%sMHz ", freq[clock]);
+ clock = (sw >> 4) & 3;
+ printf("Clock2=%sMHz\n", freq[clock]);
+
+ return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int board_mux_lane_to_slot(void)
+{
+ ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1;
+ u8 brdcfg9;
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+
+ brdcfg9 = QIXIS_READ(brdcfg[9]);
+ QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
+
+ switch (srds_prtcl_s1) {
+ case 0:
+ /* SerDes1 is not enabled */
+ break;
+ case 0xd5:
+ case 0x5b:
+ case 0x6b:
+ case 0x77:
+ case 0x6f:
+ case 0x7f:
+ QIXIS_WRITE(brdcfg[12], 0x8c);
+ break;
+ case 0x40:
+ QIXIS_WRITE(brdcfg[12], 0xfc);
+ break;
+ case 0xd6:
+ case 0x5a:
+ case 0x6a:
+ case 0x56:
+ QIXIS_WRITE(brdcfg[12], 0x88);
+ break;
+ case 0x47:
+ QIXIS_WRITE(brdcfg[12], 0xcc);
+ break;
+ case 0x46:
+ QIXIS_WRITE(brdcfg[12], 0xc8);
+ break;
+ case 0x95:
+ case 0x99:
+ brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
+ QIXIS_WRITE(brdcfg[9], brdcfg9);
+ QIXIS_WRITE(brdcfg[12], 0x8c);
+ break;
+ case 0x116:
+ QIXIS_WRITE(brdcfg[12], 0x00);
+ break;
+ case 0x115:
+ case 0x119:
+ case 0x129:
+ case 0x12b:
+ /* Aurora, PCIe, SGMII, SATA */
+ QIXIS_WRITE(brdcfg[12], 0x04);
+ break;
+ default:
+ printf("WARNING: unsupported for SerDes Protocol %d\n",
+ srds_prtcl_s1);
+ return -1;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PPC_T1024
+static void board_mux_setup(void)
+{
+ u8 brdcfg15;
+
+ brdcfg15 = QIXIS_READ(brdcfg[15]);
+ brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
+
+ if (hwconfig_arg_cmp("pin_mux", "tdm")) {
+ /* Route QE_TDM multiplexed signals to TDM Riser slot */
+ QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
+ QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
+ QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
+ ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
+ } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
+ /* to UCC (ProfiBus) interface */
+ QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
+ } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
+ /* to DVI (HDMI) encoder */
+ QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
+ } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
+ /* to DFP (LCD) encoder */
+ QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
+ BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
+ }
+
+ if (hwconfig_arg_cmp("adaptor", "sdxc"))
+ /* Route SPI_CS multiplexed signals to SD slot */
+ QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
+ ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
+}
+#endif
+
+void board_retimer_ds125df111_init(void)
+{
+ u8 reg;
+
+ /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
+ reg = I2C_MUX_CH7;
+ i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1);
+ reg = I2C_MUX_CH5;
+ i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
+
+ /* Access to Control/Shared register */
+ reg = 0x0;
+ i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+
+ /* Read device revision and ID */
+ i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
+ debug("Retimer version id = 0x%x\n", reg);
+
+ /* Enable Broadcast */
+ reg = 0x0c;
+ i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+
+ /* Reset Channel Registers */
+ i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+ reg |= 0x4;
+ i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+
+ /* Enable override divider select and Enable Override Output Mux */
+ i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
+ reg |= 0x24;
+ i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
+
+ /* Select VCO Divider to full rate (000) */
+ i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
+ reg &= 0x8f;
+ i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
+
+ /* Select active PFD MUX input as re-timed data (001) */
+ i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
+ reg &= 0x3f;
+ reg |= 0x20;
+ i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
+
+ /* Set data rate as 10.3125 Gbps */
+ reg = 0x0;
+ i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
+ reg = 0xb2;
+ i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
+ reg = 0x90;
+ i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
+ reg = 0xb3;
+ i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
+ reg = 0xcd;
+ i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ board_mux_lane_to_slot();
+ board_retimer_ds125df111_init();
+
+ /* Increase IO drive strength to address FCS error on RGMII */
+ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_64:
+ return 64000000;
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+#define NUM_SRDS_PLL 2
+int misc_init_r(void)
+{
+#ifdef CONFIG_PPC_T1024
+ board_mux_setup();
+#endif
+ return 0;
+}
+
+void fdt_fixup_spi_mux(void *blob)
+{
+ int nodeoff = 0;
+
+ if (hwconfig_arg_cmp("pin_mux", "tdm")) {
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "eon,en25s64")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+ } else {
+ /* remove tdm node */
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "maxim,ds26522")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+ }
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+ fdt_fixup_spi_mux(blob);
+
+ return 0;
+}
+
+void qixis_dump_switch(void)
+{
+ int i, nr_of_cfgsw;
+
+ QIXIS_WRITE(cms[0], 0x00);
+ nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+ puts("DIP switch settings dump:\n");
+ for (i = 1; i <= nr_of_cfgsw; i++) {
+ QIXIS_WRITE(cms[0], i);
+ printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+ }
+}
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+ /* does not provide HW signals for power management */
+ QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
diff --git a/board/freescale/t102xqds/t102xqds.h b/board/freescale/t102xqds/t102xqds.h
new file mode 100644
index 0000000..64ff623
--- /dev/null
+++ b/board/freescale/t102xqds/t102xqds.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T102x_QDS_H__
+#define __T102x_QDS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+int select_i2c_ch_pca9547(u8 ch);
+
+#endif
diff --git a/board/freescale/t102xqds/t102xqds_qixis.h b/board/freescale/t102xqds/t102xqds_qixis.h
new file mode 100644
index 0000000..a429fb7
--- /dev/null
+++ b/board/freescale/t102xqds/t102xqds_qixis.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T1024QDS_QIXIS_H__
+#define __T1024QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T1024/T1023 QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xE0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
+#define BRDCFG5_IMX_MASK 0xC0
+#define BRDCFG5_IMX_DIU 0x80
+
+#define BRDCFG5_SPIRTE_MASK 0x07
+#define BRDCFG5_SPIRTE_TDM 0x01
+#define BRDCFG5_SPIRTE_SDHC 0x02
+#define BRDCFG9_XFI_TX_DISABLE 0x10
+
+/* BRDCFG13[0:5] TDM configuration and setup */
+#define BRDCFG13_TDM_MASK 0xfc
+#define BRDCFG13_TDM_INTERFACE 0x37
+#define BRDCFG13_HDLC_LOOPBACK 0x29
+#define BRDCFG13_TDM_LOOPBACK 0x31
+
+/* BRDCFG15[3] controls LCD Panel Powerdown */
+#define BRDCFG15_LCDFM 0x20
+#define BRDCFG15_LCDPD 0x10
+#define BRDCFG15_LCDPD_MASK 0x10
+#define BRDCFG15_LCDPD_ENABLED 0x00
+
+/* BRDCFG15[6:7] controls DIU MUX selction*/
+#define BRDCFG15_DIUSEL_MASK 0x03
+#define BRDCFG15_DIUSEL_HDMI 0x00
+#define BRDCFG15_DIUSEL_LCD 0x01
+#define BRDCFG15_DIUSEL_UCC 0x02
+#define BRDCFG15_DIUSEL_TDM 0x03
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+#define QIXIS_SYSCLK_64 0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+
+#define QIXIS_SRDS1CLK_122 0x5a
+#define QIXIS_SRDS1CLK_125 0x5e
+#endif
diff --git a/board/freescale/t102xqds/tlb.c b/board/freescale/t102xqds/tlb.c
new file mode 100644
index 0000000..409e173
--- /dev/null
+++ b/board/freescale/t102xqds/tlb.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+ * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef QIXIS_BASE
+ SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_4K, 1),
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 12, BOOKE_PAGESZ_1G, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 13, BOOKE_PAGESZ_1G, 1)
+#endif
+ /* entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so if needed more, will use entry 16 later.
+ */
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig
new file mode 100644
index 0000000..10d49f5
--- /dev/null
+++ b/board/freescale/t102xrdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_T102XRDB
+
+config SYS_BOARD
+ default "t102xrdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "T102xRDB"
+
+endif
diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS
new file mode 100644
index 0000000..dc554d4
--- /dev/null
+++ b/board/freescale/t102xrdb/MAINTAINERS
@@ -0,0 +1,10 @@
+T102XRDB BOARD
+M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+S: Maintained
+F: board/freescale/t102xrdb/
+F: include/configs/T102xRDB.h
+F: configs/T1024RDB_defconfig
+F: configs/T1024RDB_NAND_defconfig
+F: configs/T1024RDB_SDCARD_defconfig
+F: configs/T1024RDB_SPIFLASH_defconfig
+F: configs/T1024RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile
new file mode 100644
index 0000000..a0cf8f6
--- /dev/null
+++ b/board/freescale/t102xrdb/Makefile
@@ -0,0 +1,17 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += t102xrdb.o
+obj-y += cpld.o
+obj-y += eth_t102xrdb.o
+obj-$(CONFIG_PCI) += pci.o
+endif
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README
new file mode 100644
index 0000000..2b17f50
--- /dev/null
+++ b/board/freescale/t102xrdb/README
@@ -0,0 +1,258 @@
+T1024 SoC Overview
+------------------
+The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
+combines two or one 64-bit Power Architecture e5500 core respectively with high
+performance datapath acceleration logic, and network peripheral bus interfaces
+required for networking and telecommunications. This processor can be used in
+applications such as enterprise WLAN access points, routers, switches, firewall
+and other packet processing intensive small enterprise and branch office appliances,
+and general-purpose embedded computing. Its high level of integration offers
+significant performance benefits and greatly helps to simplify board design.
+
+
+The T1024 SoC includes the following function and features:
+- two e5500 cores, each with a private 256 KB L2 cache
+ - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
+ - Three levels of instructions: User, supervisor, and hypervisor
+ - Independent boot and reset
+ - Secure boot capability
+- 256 KB shared L3 CoreNet platform cache (CPC)
+- Interconnect CoreNet platform
+ - CoreNet coherency manager supporting coherent and noncoherent transactions
+ with prioritization and bandwidth allocation amongst CoreNet endpoints
+ - 150 Gbps coherent read bandwidth
+- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
+- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
+ - Packet parsing, classification, and distribution
+ - Queue management for scheduling, packet sequencing, and congestion management
+ - Cryptography Acceleration (SEC 5.x)
+ - IEEE 1588 support
+ - Hardware buffer management for buffer allocation and deallocation
+ - MACSEC on DPAA-based Ethernet ports
+- Ethernet interfaces
+ - Four 1 Gbps Ethernet controllers
+- Parallel Ethernet interfaces
+ - Two RGMII interfaces
+- High speed peripheral interfaces
+ - Three PCI Express 2.0 controllers/ports running at up to 5 GHz
+ - One SATA controller supporting 1.5 and 3.0 Gb/s operation
+ - One QSGMII interface
+ - Four SGMII interface supporting 1000 Mbps
+ - Three SGMII interfaces supporting up to 2500 Mbps
+ - 10GbE XFI or 10Base-KR interface
+- Additional peripheral interfaces
+ - Two USB 2.0 controllers with integrated PHY
+ - SD/eSDHC/eMMC
+ - eSPI controller
+ - Four I2C controllers
+ - Four UARTs
+ - Four GPIO controllers
+ - Integrated flash controller (IFC)
+ - LCD interface (DIU) with 12 bit dual data rate
+- Multicore programmable interrupt controller (PIC)
+- Two 8-channel DMA engines
+- Single source clocking implementation
+- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+- QUICC Engine block
+ - 32-bit RISC controller for flexible support of the communications peripherals
+ - Serial DMA channel for receive and transmit on all serial channels
+ - Two universal communication controllers, supporting TDM, HDLC, and UART
+
+T1023 Personality
+------------------
+T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
+unavailable deep sleep. Rest of the blocks are almost same as T1024.
+Differences between T1024 and T1023
+Feature T1024 T1023
+QUICC Engine: yes no
+DIU: yes no
+Deep Sleep: yes no
+I2C controller: 4 3
+DDR: 64-bit 32-bit
+IFC: 32-bit 28-bit
+
+
+T1024RDB board Overview
+-----------------------
+ - Ethernet
+ - Two on-board 10M/100M/1G bps RGMII ethernet ports
+ - One on-board 10G bps Base-T port.
+ - DDR Memory
+ - Supports 64-bit 4GB DDR3L DIMM
+ - PCIe
+ - One on-board PCIe slot.
+ - Two on-board PCIe Mini-PCIe connectors.
+ - IFC/Local Bus
+ - NOR: 128MB 16-bit NOR Flash
+ - NAND: 1GB 8-bit NAND flash
+ - CPLD: for system controlling with programable header on-board
+ - USB
+ - Supports two USB 2.0 ports with integrated PHYs
+ - Two type A ports with 5V@1.5A per port.
+ - SDHC
+ - one SD connector supporting 1.8V/3.3V via J53.
+ - SPI
+ - On-board 64MB SPI flash
+ - Other
+ - Two Serial ports
+ - Four I2C ports
+
+
+Memory map on T1024RDB
+----------------------
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
+0x0_0000_0000 0x0_ffff_ffff DDR 4GB
+
+
+128MB NOR Flash memory Map
+--------------------------
+Start Address End Address Definition Max size
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
+0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
+0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+T1024 Clock frequency
+---------------------
+BIN Core DDR Platform FMan
+Bin1: 1400MHz 1600MT/s 400MHz 700MHz
+Bin2: 1200MHz 1600MT/s 400MHz 600MHz
+Bin3: 1000MHz 1600MT/s 400MHz 500MHz
+
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+ a. build NOR boot image
+ $ make T1024RDB_defconfig
+ $ make
+ b. program u-boot.bin image to NOR flash
+ => tftp 1000000 u-boot.bin
+ => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+ set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+
+ Switching between default bank0 and alternate bank4 on NOR flash
+ To change boot source to vbank4:
+ via software: run command 'cpld reset altbank' in u-boot.
+ via DIP-switch: set SW3[5:7] = '100'
+
+ To change boot source to vbank0:
+ via software: run command 'cpld reset' in u-boot.
+ via DIP-Switch: set SW3[5:7] = '000'
+
+2. NAND Boot:
+ a. build PBL image for NAND boot
+ $ make T1024RDB_NAND_defconfig
+ $ make
+ b. program u-boot-with-spl-pbl.bin to NAND flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => nand erase 0 $filesize
+ => nand write 1000000 0 $filesize
+ set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot
+
+3. SPI Boot:
+ a. build PBL image for SPI boot
+ $ make T1024RDB_SPIFLASH_defconfig
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SPI flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => sf probe 0
+ => sf erase 0 f0000
+ => sf write 1000000 0 $filesize
+ set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+ a. build PBL image for SD boot
+ $ make T1024RDB_SDCARD_defconfig
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SD/MMC card
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => mmc write 1000000 8 0x800
+ => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
+ => mmc write 1000000 0x820 80
+ set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (30KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T1024RDB
+-------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB(2 block)
+0x100000 0x17FFFF u-boot env 512KB(1 block)
+0x180000 0x1FFFFF FMAN Ucode 512KB(1 block)
+0x200000 0x27FFFF QE Firmware 512KB(1 block)
+
+
+SD Card memory Map on T1024RDB
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 u-boot img 1MB
+0x800 0016 u-boot env 8KB
+0x820 0256 FMAN Ucode 128KB
+0x920 0256 QE Firmware 128KB
+
+
+SPI Flash memory Map on T1024RDB
+----------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB
+0x100000 0x101FFF u-boot env 8KB
+0x110000 0x12FFFF FMAN Ucode 128KB
+0x130000 0x14FFFF QE Firmware 128KB
+
+
+For more details, please refer to T1024RDB Reference Manual and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c
new file mode 100644
index 0000000..c03894a
--- /dev/null
+++ b/board/freescale/t102xrdb/cpld.c
@@ -0,0 +1,103 @@
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Freescale T1024RDB board-specific CPLD controlling supports.
+ *
+ * The following macros need to be defined:
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(void)
+{
+ u8 reg = CPLD_READ(flash_csr);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
+
+ CPLD_WRITE(flash_csr, reg);
+ CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+ u8 reg = CPLD_READ(flash_csr);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
+
+ CPLD_WRITE(flash_csr, reg);
+ CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+static void cpld_dump_regs(void)
+{
+ printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
+ printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
+ printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
+ printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
+ printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
+ printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
+ printf("int_status = 0x%02x\n", CPLD_READ(int_status));
+ printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr));
+ printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
+ printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
+ printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
+ printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
+ printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
+ printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
+ printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
+ putc('\n');
+}
+
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (strcmp(argv[2], "altbank") == 0)
+ cpld_set_altbank();
+ else
+ cpld_set_defbank();
+ } else if (strcmp(argv[1], "dump") == 0) {
+ cpld_dump_regs();
+ } else {
+ rc = cmd_usage(cmdtp);
+ }
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+ "Reset the board or alternate bank",
+ "reset - hard reset to default bank\n"
+ "cpld reset altbank - reset to alternate bank\n"
+ "cpld dump - display the CPLD registers\n"
+ );
diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h
new file mode 100644
index 0000000..5a3100f
--- /dev/null
+++ b/board/freescale/t102xrdb/cpld.h
@@ -0,0 +1,45 @@
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+struct cpld_data {
+ u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
+ u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
+ u8 hw_ver; /* 0x02 - Hardware Revision Register */
+ u8 sw_ver; /* 0x03 - Software Revision register */
+ u8 res0[12]; /* 0x04 - 0x0F - not used */
+ u8 reset_ctl1; /* 0x10 - Reset control Register1 */
+ u8 reset_ctl2; /* 0x11 - Reset control Register2 */
+ u8 int_status; /* 0x12 - Interrupt status Register */
+ u8 flash_csr; /* 0x13 - Flash control and status register */
+ u8 fan_ctl_status; /* 0x14 - Fan control and status register */
+ u8 led_ctl_status; /* 0x15 - LED control and status register */
+ u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
+ u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
+ u8 boot_override; /* 0x18 - Boot override register */
+ u8 boot_config1; /* 0x19 - Boot config override register*/
+ u8 boot_config2; /* 0x1A - Boot config override register*/
+} cpld_data_t;
+
+
+/* Pointer to the CPLD register set */
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value)\
+ cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_LBMAP_MASK 0x3F
+#define CPLD_BANK_SEL_MASK 0x07
+#define CPLD_BANK_OVERRIDE 0x40
+#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
+#define CPLD_LBMAP_RESET 0xFF
+#define CPLD_LBMAP_SHIFT 0x03
+#define CPLD_BOOT_SEL 0x80
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
new file mode 100644
index 0000000..a20330b
--- /dev/null
+++ b/board/freescale/t102xrdb/ddr.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * datarate_mhz_high values need to be in ascending order
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ */
+ {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
+ {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
+ {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
+ {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust according to the board ddr freqency and n_banks
+ * specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found\n");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+ debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
+ debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * rtt and rtt_wr override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
+
+ /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
+ * force DDR bus width to 32bit for T1023
+ */
+ if (cpu->soc_ver == SVR_T1023)
+ popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
+
+#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
+ /* for DDR bus 32bit test on T1024 */
+ popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
+#endif
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+#else
+ /* DDR has been initialised by first stage boot loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
+ return dram_size;
+}
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
new file mode 100644
index 0000000..2e400c4
--- /dev/null
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ struct mii_dev *dev;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
+
+ switch (srds_s1) {
+ case 0x95:
+ /* 10G XFI with Aquantia PHY */
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+ break;
+ default:
+ printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
+ srds_s1);
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+}
diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c
new file mode 100644
index 0000000..1c9235f
--- /dev/null
+++ b/board/freescale/t102xrdb/law.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c
new file mode 100644
index 0000000..ba7041a
--- /dev/null
+++ b/board/freescale/t102xrdb/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2007-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
new file mode 100644
index 0000000..dd2dec4
--- /dev/null
+++ b/board/freescale/t102xrdb/spl.c
@@ -0,0 +1,107 @@
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ puts("\nNAND boot...\n");
+#endif
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/t102xrdb/t1024_pbi.cfg b/board/freescale/t102xrdb/t1024_pbi.cfg
new file mode 100644
index 0000000..7b9e9b0
--- /dev/null
+++ b/board/freescale/t102xrdb/t1024_pbi.cfg
@@ -0,0 +1,26 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
diff --git a/board/freescale/t102xrdb/t1024_rcw.cfg b/board/freescale/t102xrdb/t1024_rcw.cfg
new file mode 100644
index 0000000..cd6f906
--- /dev/null
+++ b/board/freescale/t102xrdb/t1024_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1024RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x95
+#Core/DDR: 1400Mhz/1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+4a800003 80000012 ec027000 21000000
+00000000 00000000 00000000 00030810
+00000000 0b005a08 00000000 00000006
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
new file mode 100644
index 0000000..f5c438d
--- /dev/null
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <asm/mpc85xx_gpio.h>
+#include <fm_eth.h>
+#include "t102xrdb.h"
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+ static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
+
+ printf("Board: %sRDB, ", cpu->name);
+ printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
+ CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+
+#ifdef CONFIG_SDCARD
+ puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+ puts("SPI\n");
+#else
+ u8 reg;
+
+ reg = CPLD_READ(flash_csr);
+
+ if (reg & CPLD_BOOT_SEL) {
+ puts("NAND\n");
+ } else {
+ reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
+ printf("NOR vBank%d\n", reg);
+ }
+#endif
+
+ puts("SERDES Reference Clocks:\n");
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+ /* does not provide HW signals for power management */
+ CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h
new file mode 100644
index 0000000..2f23579
--- /dev/null
+++ b/board/freescale/t102xrdb/t102xrdb.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T1024_RDB_H__
+#define __T1024_RDB_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c
new file mode 100644
index 0000000..8269b3d
--- /dev/null
+++ b/board/freescale/t102xrdb/tlb.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+ * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 12, BOOKE_PAGESZ_1G, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 13, BOOKE_PAGESZ_1G, 1)
+#endif
+ /* entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so if needed more, will use entry 16 later.
+ */
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t1040qds/Kconfig b/board/freescale/t1040qds/Kconfig
new file mode 100644
index 0000000..1bb1684
--- /dev/null
+++ b/board/freescale/t1040qds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_T1040QDS
+
+config SYS_BOARD
+ default "t1040qds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "T1040QDS"
+
+endif
diff --git a/board/freescale/t1040qds/MAINTAINERS b/board/freescale/t1040qds/MAINTAINERS
new file mode 100644
index 0000000..83f6b3c
--- /dev/null
+++ b/board/freescale/t1040qds/MAINTAINERS
@@ -0,0 +1,12 @@
+T1040QDS BOARD
+M: Poonam Aggrwal <poonam.aggrwal@freescale.com>
+S: Maintained
+F: board/freescale/t1040qds/
+F: include/configs/T1040QDS.h
+F: configs/T1040QDS_defconfig
+F: configs/T1040QDS_D4_defconfig
+
+T1040QDS_SECURE_BOOT BOARD
+M: Aneesh Bansal <aneesh.bansal@freescale.com>
+S: Maintained
+F: configs/T1040QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile
new file mode 100644
index 0000000..19ed21b
--- /dev/null
+++ b/board/freescale/t1040qds/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += t1040qds.o
+obj-y += ddr.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += law.o
+obj-y += tlb.o
+obj-y += eth.o
+obj-y += diu.o
diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README
new file mode 100644
index 0000000..8160ca0
--- /dev/null
+++ b/board/freescale/t1040qds/README
@@ -0,0 +1,169 @@
+Overview
+--------
+The T1040QDS is a Freescale reference board that hosts the T1040 SoC
+(and variants).
+
+T1040 SoC Overview
+------------------
+The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
+processor cores with high-performance data path acceleration architecture
+and network peripheral interfaces required for networking & telecommunications.
+
+The T1040/T1042 SoC includes the following function and features:
+
+ - Four e5500 cores, each with a private 256 KB L2 cache
+ - 256 KB shared L3 CoreNet platform cache (CPC)
+ - Interconnect CoreNet platform
+ - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
+ support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ for the following functions:
+ - Packet parsing, classification, and distribution
+ - Queue management for scheduling, packet sequencing, and congestion
+ management
+ - Cryptography Acceleration (SEC 5.0)
+ - RegEx Pattern Matching Acceleration (PME 2.2)
+ - IEEE Std 1588 support
+ - Hardware buffer management for buffer allocation and deallocation
+ - Ethernet interfaces
+ - Integrated 8-port Gigabit Ethernet switch (T1040 only)
+ - Four 1 Gbps Ethernet controllers
+ - Two RGMII interfaces or one RGMII and one MII interfaces
+ - High speed peripheral interfaces
+ - Four PCI Express 2.0 controllers running at up to 5 GHz
+ - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
+ - Upto two QSGMII interface
+ - Upto six SGMII interface supporting 1000 Mbps
+ - One SGMII interface supporting upto 2500 Mbps
+ - Additional peripheral interfaces
+ - Two USB 2.0 controllers with integrated PHY
+ - SD/eSDHC/eMMC
+ - eSPI controller
+ - Four I2C controllers
+ - Four UARTs
+ - Four GPIO controllers
+ - Integrated flash controller (IFC)
+ - LCD and HDMI interface (DIU) with 12 bit dual data rate
+ - TDM interface
+ - Multicore programmable interrupt controller (PIC)
+ - Two 8-channel DMA engines
+ - Single source clocking implementation
+ - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+
+ T1040QDS board Overview
+ -----------------------
+ - SERDES Connections, 8 lanes supporting:
+ — PCI Express: supporting Gen 1 and Gen 2;
+ — SGMII
+ — QSGMII
+ — SATA 2.0
+ — Aurora debug with dedicated connectors (T1040 only)
+ - DDR Controller
+ - Supports rates of up to 1600 MHz data-rate
+ - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
+ -IFC/Local Bus
+ - NAND flash: 8-bit, async, up to 2GB.
+ - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
+ - GASIC: Simple (minimal) target within Qixis FPGA
+ - PromJET rapid memory download support
+ - Ethernet
+ - Two on-board RGMII 10/100/1G ethernet ports.
+ - PHY #0 remains powered up during deep-sleep (T1040 only)
+ - QIXIS System Logic FPGA
+ - Clocks
+ - System and DDR clock (SYSCLK, “DDRCLK”)
+ - SERDES clocks
+ - Power Supplies
+ - Video
+ - DIU supports video at up to 1280x1024x32bpp
+ - USB
+ - Supports two USB 2.0 ports with integrated PHYs
+ — Two type A ports with 5V@1.5A per port.
+ — Second port can be converted to OTG mini-AB
+ - SDHC
+ - SDHC port connects directly to an adapter card slot, featuring:
+ - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
+ — Supporting eMMC memory devices
+ - SPI
+ - On-board support of 3 different devices and sizes
+ - Other IO
+ - Two Serial ports
+ - ProfiBus port
+ - Four I2C ports
+
+Memory map on T1040QDS
+----------------------
+The addresses in brackets are physical addresses.
+
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
+0x0_0000_0000 0x0_ffff_ffff DDR 2GB
+
+
+NOR Flash memory Map on T1040QDS
+--------------------------------
+ Start End Definition Size
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+Various Software configurations/environment variables/commands
+--------------------------------------------------------------
+The below commands apply to T1040QDS
+
+1. U-boot environment variable hwconfig
+ The default hwconfig is:
+ hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
+ dr_mode=host,phy_type=utmi
+ Note: For USB gadget set "dr_mode=peripheral"
+
+2. FMAN Ucode versions
+ fsl_fman_ucode_t1040.bin
+
+3. Switching to alternate bank
+ Commands for switching to alternate bank.
+
+ 1. To change from vbank0 to vbank4
+ => qixis_reset altbank (it will boot using vbank4)
+
+ 2.To change from vbank4 to vbank0
+ => qixis reset (it will boot using vbank0)
+
+T1040 Personality
+--------------------
+
+T1022 Personality
+--------------------
+T1022 is a reduced personality of T1040 with less core/clusters.
+
+T1042 Personality
+--------------------
+T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
+Ethernet switch. Rest of the blocks are same as T1040
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
new file mode 100644
index 0000000..43f952f
--- /dev/null
+++ b/board/freescale/t1040qds/ddr.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found\n");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * rtt and rtt_wr override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+#else
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h
new file mode 100644
index 0000000..a6e1673
--- /dev/null
+++ b/board/freescale/t1040qds/ddr.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ */
+#ifdef CONFIG_SYS_FSL_DDR4
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
+ {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
+ {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
+ {2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
+ {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+ {1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
+ {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
+ {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
+#else
+#error DDR type not defined
+#endif
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+#endif
diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c
new file mode 100644
index 0000000..0214224
--- /dev/null
+++ b/board/freescale/t1040qds/diu.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <video_fb.h>
+#include <fsl_diu_fb.h>
+#include "../common/qixis.h"
+#include "../common/diu_ch7301.h"
+#include "t1040qds.h"
+#include "t1040qds_qixis.h"
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register. So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F 0x10000000
+#define AD_ALPHA_C_SHIFT 25
+#define AD_BLUE_C_SHIFT 23
+#define AD_GREEN_C_SHIFT 21
+#define AD_RED_C_SHIFT 19
+#define AD_PIXEL_S_SHIFT 16
+#define AD_COMP_3_SHIFT 12
+#define AD_COMP_2_SHIFT 8
+#define AD_COMP_1_SHIFT 4
+#define AD_COMP_0_SHIFT 0
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+ unsigned long speed_ccb, temp;
+ u32 pixval;
+ int ret = 0;
+ speed_ccb = get_bus_freq(0);
+ temp = 1000000000 / pixclock;
+ temp *= 1000;
+ pixval = speed_ccb / temp;
+
+ /* Program HDMI encoder */
+ /* Switch channel to DIU */
+ select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
+
+ /* Set dispaly encoder */
+ ret = diu_set_dvi_encoder(temp);
+ if (ret) {
+ puts("Failed to set DVI encoder\n");
+ return;
+ }
+
+ /* Switch channel to default */
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+ /* Program pixel clock */
+ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
+ ((pixval << PXCK_BITS_START) & PXCK_MASK));
+ /* enable clock*/
+ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
+ ((pixval << PXCK_BITS_START) & PXCK_MASK));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+ u32 pixel_format;
+ u8 sw;
+
+ /*Route I2C4 to DIU system as HSYNC/VSYNC*/
+ sw = QIXIS_READ(brdcfg[5]);
+ QIXIS_WRITE(brdcfg[5],
+ ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
+
+ /*Configure Display ouput port as HDMI*/
+ sw = QIXIS_READ(brdcfg[15]);
+ QIXIS_WRITE(brdcfg[15],
+ ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
+ | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
+
+ pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+ (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+ (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+ (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+ (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+ printf("DIU: Switching to monitor @ %ux%u\n", xres, yres);
+
+
+ return fsl_diu_init(xres, yres, pixel_format, 0);
+}
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
new file mode 100644
index 0000000..06d9086
--- /dev/null
+++ b/board/freescale/t1040qds/eth.c
@@ -0,0 +1,498 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * The RGMII PHYs are provided by the two on-board PHY connected to
+ * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
+ * PHY or by the standard four-port SGMII riser card (VSC).
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/fman.h"
+#include "../common/qixis.h"
+
+#include "t1040qds_qixis.h"
+
+#ifdef CONFIG_FMAN_ENET
+ /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
+ * Bank 1 -> Lanes A, B, C, D
+ * Bank 2 -> Lanes E, F, G, H
+ */
+
+ /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
+ * means that the mapping must be determined dynamically, or that the lane
+ * maps to something other than a board slot.
+ */
+static u8 lane_to_slot[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
+ * housed.
+ */
+static int riser_phy_addr[] = {
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
+ CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
+ CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
+ CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
+};
+
+/* Slot2 does not have EMI connections */
+#define EMI_NONE 0xFFFFFFFF
+#define EMI1_RGMII0 0
+#define EMI1_RGMII1 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT3 3
+#define EMI1_SLOT4 4
+#define EMI1_SLOT5 5
+#define EMI1_SLOT6 6
+#define EMI1_SLOT7 7
+#define EMI2 8
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+ "T1040_QDS_MDIO0",
+ "T1040_QDS_MDIO1",
+ "T1040_QDS_MDIO2",
+ "T1040_QDS_MDIO3",
+ "T1040_QDS_MDIO4",
+ "T1040_QDS_MDIO5",
+ "T1040_QDS_MDIO6",
+ "T1040_QDS_MDIO7",
+};
+
+struct t1040_qds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name = t1040_qds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+static void t1040_qds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+ if (muxval <= 7) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct t1040_qds_mdio *priv = bus->priv;
+
+ t1040_qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct t1040_qds_mdio *priv = bus->priv;
+
+ t1040_qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t1040_qds_mdio_reset(struct mii_dev *bus)
+{
+ struct t1040_qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct t1040_qds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate t1040_qds MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate t1040_qds private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = t1040_qds_mdio_read;
+ bus->write = t1040_qds_mdio_write;
+ bus->reset = t1040_qds_mdio_reset;
+ sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+
+ return mdio_register(bus);
+}
+
+/*
+ * Initialize the lane_to_slot[] array.
+ *
+ * On the T1040QDS board the mapping is controlled by ?? register.
+ */
+static void initialize_lane_to_slot(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
+ >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ QIXIS_WRITE(cms[0], 0x07);
+
+ switch (serdes1_prtcl) {
+ case 0x60:
+ case 0x66:
+ case 0x67:
+ case 0x69:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 6;
+ lane_to_slot[3] = 5;
+ break;
+ case 0x86:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ break;
+ case 0x87:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ lane_to_slot[7] = 7;
+ break;
+ case 0x89:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ lane_to_slot[7] = 7;
+ break;
+ case 0x8d:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ lane_to_slot[5] = 3;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0x8F:
+ case 0x85:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 6;
+ lane_to_slot[3] = 5;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0xA5:
+ lane_to_slot[1] = 7;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0xA7:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 6;
+ lane_to_slot[3] = 5;
+ lane_to_slot[7] = 7;
+ break;
+ case 0xAA:
+ lane_to_slot[1] = 7;
+ lane_to_slot[6] = 7;
+ lane_to_slot[7] = 7;
+ break;
+ case 0x40:
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ break;
+ default:
+ printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
+ serdes1_prtcl);
+ break;
+ }
+}
+
+/*
+ * Given the following ...
+ *
+ * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
+ * compatible string and 'addr' physical address)
+ *
+ * 2) An Fman port
+ *
+ * ... update the phy-handle property of the Ethernet node to point to the
+ * right PHY. This assumes that we already know the PHY for each port.
+ *
+ * The offset of the Fman Ethernet node is also passed in for convenience, but
+ * it is not used, and we recalculate the offset anyway.
+ *
+ * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
+ * Inside the Fman, "ports" are things that connect to MACs. We only call them
+ * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
+ * and ports are the same thing.
+ *
+ */
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ phy_interface_t intf = fm_info_get_enet_if(port);
+ char phy[16];
+
+ /* The RGMII PHY is identified by the MAC connected to it */
+ if (intf == PHY_INTERFACE_MODE_RGMII) {
+ sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
+ fdt_set_phy_handle(fdt, compat, addr, phy);
+ }
+
+ /* The SGMII PHY is identified by the MAC connected to it */
+ if (intf == PHY_INTERFACE_MODE_SGMII) {
+ int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
+ + port);
+ u8 slot;
+ if (lane < 0)
+ return;
+ slot = lane_to_slot[lane];
+ if (slot) {
+ /* Slot housing a SGMII riser card */
+ sprintf(phy, "phy_s%x_%02x", slot,
+ (fm_info_get_phy_address(port - FM1_DTSEC1)-
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
+ fdt_set_phy_handle(fdt, compat, addr, phy);
+ }
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int i, lane, idx;
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ idx = i - FM1_DTSEC1;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+
+ switch (mdio_mux[i]) {
+ case EMI1_SLOT3:
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ break;
+ case EMI1_SLOT5:
+ fdt_status_okay_by_alias(fdt, "emi1_slot5");
+ break;
+ case EMI1_SLOT6:
+ fdt_status_okay_by_alias(fdt, "emi1_slot6");
+ break;
+ case EMI1_SLOT7:
+ fdt_status_okay_by_alias(fdt, "emi1_slot7");
+ break;
+ }
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if (i == FM1_DTSEC4)
+ fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
+
+ if (i == FM1_DTSEC5)
+ fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
+ break;
+ default:
+ break;
+ }
+ }
+}
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+static void set_brdcfg9_for_gtx_clk(void)
+{
+ u8 brdcfg9;
+ brdcfg9 = QIXIS_READ(brdcfg[9]);
+/* Initializing EPHY2 clock to RGMII mode */
+ brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
+ brdcfg9 |= (BRDCFG9_EPHY2_VAL);
+ QIXIS_WRITE(brdcfg[9], brdcfg9);
+}
+
+void t1040_handle_phy_interface_sgmii(int i)
+{
+ int lane, idx, slot;
+ idx = i - FM1_DTSEC1;
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+
+ if (lane < 0)
+ return;
+ slot = lane_to_slot[lane];
+
+ switch (slot) {
+ case 1:
+ mdio_mux[i] = EMI1_SLOT1;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 3:
+ if (FM1_DTSEC4 == i)
+ fm_info_set_phy_address(i, riser_phy_addr[0]);
+ if (FM1_DTSEC5 == i)
+ fm_info_set_phy_address(i, riser_phy_addr[1]);
+
+ mdio_mux[i] = EMI1_SLOT3;
+
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 4:
+ mdio_mux[i] = EMI1_SLOT4;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 5:
+ /* Slot housing a SGMII riser card? */
+ fm_info_set_phy_address(i, riser_phy_addr[0]);
+ mdio_mux[i] = EMI1_SLOT5;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 6:
+ /* Slot housing a SGMII riser card? */
+ fm_info_set_phy_address(i, riser_phy_addr[0]);
+ mdio_mux[i] = EMI1_SLOT6;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 7:
+ if (FM1_DTSEC1 == i)
+ fm_info_set_phy_address(i, riser_phy_addr[0]);
+ if (FM1_DTSEC2 == i)
+ fm_info_set_phy_address(i, riser_phy_addr[1]);
+ if (FM1_DTSEC3 == i)
+ fm_info_set_phy_address(i, riser_phy_addr[2]);
+ if (FM1_DTSEC5 == i)
+ fm_info_set_phy_address(i, riser_phy_addr[3]);
+
+ mdio_mux[i] = EMI1_SLOT7;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+}
+void t1040_handle_phy_interface_rgmii(int i)
+{
+ fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
+ CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
+ CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+ mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
+ EMI1_RGMII0;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct memac_mdio_info memac_mdio_info;
+ unsigned int i;
+
+ printf("Initializing Fman\n");
+ set_brdcfg9_for_gtx_clk();
+
+ initialize_lane_to_slot();
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ memac_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the real 1G MDIO bus */
+ fm_memac_mdio_init(bis, &memac_mdio_info);
+
+ /* Register the muxing front-ends to the MDIO buses */
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
+ t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+
+ /*
+ * Program on board RGMII PHY addresses. If the SGMII Riser
+ * card used, we'll override the PHY address later. For any DTSEC that
+ * is RGMII, we'll also override its PHY address later. We assume that
+ * DTSEC4 and DTSEC5 are used for RGMII.
+ */
+ fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_QSGMII:
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ t1040_handle_phy_interface_sgmii(i);
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII:
+ /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
+ t1040_handle_phy_interface_rgmii(i);
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/t1040qds/law.c b/board/freescale/t1040qds/law.c
new file mode 100644
index 0000000..a2dc027
--- /dev/null
+++ b/board/freescale/t1040qds/law.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef QIXIS_BASE_PHYS
+ SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t1040qds/pci.c b/board/freescale/t1040qds/pci.c
new file mode 100644
index 0000000..c53e3b7
--- /dev/null
+++ b/board/freescale/t1040qds/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg
new file mode 100644
index 0000000..10b1a6d
--- /dev/null
+++ b/board/freescale/t1040qds/t1040_pbi.cfg
@@ -0,0 +1,27 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000cf0 00000000
+09000cf4 fffc0000
+09000cf8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t1040qds/t1040_rcw.cfg b/board/freescale/t1040qds/t1040_rcw.cfg
new file mode 100644
index 0000000..0d0dfa5
--- /dev/null
+++ b/board/freescale/t1040qds/t1040_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0a10000c 0c000000 00000000 00000000
+66000002 00000000 fc027000 01000000
+00000000 00000000 00000000 00030810
+00000000 03fc500f 00000000 00000000
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
new file mode 100644
index 0000000..13285be
--- /dev/null
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -0,0 +1,294 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include <hwconfig.h>
+#include <asm/mpc85xx_gpio.h>
+
+#include "../common/qixis.h"
+#include "t1040qds.h"
+#include "t1040qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ char buf[64];
+ u8 sw;
+ struct cpu_type *cpu = gd->arch.cpu;
+ static const char *const freq[] = {"100", "125", "156.25", "161.13",
+ "122.88", "122.88", "122.88"};
+ int clock;
+
+ printf("Board: %sQDS, ", cpu->name);
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
+ QIXIS_READ(id), QIXIS_READ(arch));
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw == 0x8)
+ puts("PromJet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else if (sw == 0x15)
+ printf("IFCCard\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
+ /*
+ * Display the actual SERDES reference clocks as configured by the
+ * dip switches on the board. Note that the SWx registers could
+ * technically be set to force the reference clocks to match the
+ * values that the SERDES expects (or vice versa). For now, however,
+ * we just display both values and hope the user notices when they
+ * don't match.
+ */
+ puts("SERDES Reference: ");
+ sw = QIXIS_READ(brdcfg[2]);
+ clock = (sw >> 6) & 3;
+ printf("Clock1=%sMHz ", freq[clock]);
+ clock = (sw >> 4) & 3;
+ printf("Clock2=%sMHz\n", freq[clock]);
+
+ return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static void qe_board_setup(void)
+{
+ u8 brdcfg15, brdcfg9;
+
+ if (hwconfig("qe") && hwconfig("tdm")) {
+ brdcfg15 = QIXIS_READ(brdcfg[15]);
+ /*
+ * TDMRiser uses QE-TDM
+ * Route QE_TDM signals to TDM Riser slot
+ */
+ QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
+ } else if (hwconfig("qe") && hwconfig("uart")) {
+ brdcfg15 = QIXIS_READ(brdcfg[15]);
+ brdcfg9 = QIXIS_READ(brdcfg[9]);
+ /*
+ * Route QE_TDM signals to UCC
+ * ProfiBus controlled by UCC3
+ */
+ brdcfg15 &= 0xfc;
+ QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
+ QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
+ }
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_64:
+ return 64000000;
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+#define NUM_SRDS_BANKS 2
+int misc_init_r(void)
+{
+ u8 sw;
+ serdes_corenet_t *srds_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 actual[NUM_SRDS_BANKS] = { 0 };
+ int i;
+
+ sw = QIXIS_READ(brdcfg[2]);
+ for (i = 0; i < NUM_SRDS_BANKS; i++) {
+ unsigned int clock = (sw >> (6 - 2 * i)) & 3;
+ switch (clock) {
+ case 0:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+ break;
+ case 1:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+ break;
+ case 2:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
+ break;
+ }
+ }
+
+ puts("SerDes1");
+ for (i = 0; i < NUM_SRDS_BANKS; i++) {
+ u32 pllcr0 = srds_regs->bank[i].pllcr0;
+ u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+ if (expected != actual[i]) {
+ printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
+ i + 1, serdes_clock_to_string(expected),
+ serdes_clock_to_string(actual[i]));
+ }
+ }
+
+ qe_board_setup();
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
+
+void qixis_dump_switch(void)
+{
+ int i, nr_of_cfgsw;
+
+ QIXIS_WRITE(cms[0], 0x00);
+ nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+ puts("DIP switch settings dump:\n");
+ for (i = 1; i <= nr_of_cfgsw; i++) {
+ QIXIS_WRITE(cms[0], i);
+ printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+ }
+}
+
+int board_need_mem_reset(void)
+{
+ return 1;
+}
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+ /* does not provide HW signals for power management */
+ QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h
new file mode 100644
index 0000000..5041f37
--- /dev/null
+++ b/board/freescale/t1040qds/t1040qds.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T1040_QDS_H__
+#define __T1040_QDS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+int select_i2c_ch_pca9547(u8 ch);
+
+#endif
diff --git a/board/freescale/t1040qds/t1040qds_qixis.h b/board/freescale/t1040qds/t1040qds_qixis.h
new file mode 100644
index 0000000..cef8ad0
--- /dev/null
+++ b/board/freescale/t1040qds/t1040qds_qixis.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T1040QDS_QIXIS_H__
+#define __T1040QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T1040QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xE0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
+#define BRDCFG5_IMX_MASK 0xC0
+#define BRDCFG5_IMX_DIU 0x80
+
+/* BRDCFG9[2] controls EPHY2 Clock */
+#define BRDCFG9_EPHY2_MASK 0x20
+#define BRDCFG9_EPHY2_VAL 0x00
+
+/* BRDCFG15[3] controls LCD Panel Powerdown*/
+#define BRDCFG15_LCDPD_MASK 0x10
+#define BRDCFG15_LCDPD_ENABLED 0x00
+
+/* BRDCFG15[6:7] controls DIU MUX selction*/
+#define BRDCFG15_DIUSEL_MASK 0x03
+#define BRDCFG15_DIUSEL_HDMI 0x00
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+#define QIXIS_SYSCLK_64 0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+
+#define QIXIS_SRDS1CLK_122 0x5a
+#define QIXIS_SRDS1CLK_125 0x5e
+#endif
diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c
new file mode 100644
index 0000000..412c591
--- /dev/null
+++ b/board/freescale/t1040qds/tlb.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+ * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef QIXIS_BASE
+ SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_4K, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig
new file mode 100644
index 0000000..f28728d
--- /dev/null
+++ b/board/freescale/t104xrdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_T104XRDB
+
+config SYS_BOARD
+ default "t104xrdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "T104xRDB"
+
+endif
diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS
new file mode 100644
index 0000000..b61e1c0
--- /dev/null
+++ b/board/freescale/t104xrdb/MAINTAINERS
@@ -0,0 +1,23 @@
+T104XRDB BOARD
+M: Priyanka Jain <Priyanka.Jain@freescale.com>
+S: Maintained
+F: board/freescale/t104xrdb/
+F: include/configs/T104xRDB.h
+F: configs/T1040RDB_defconfig
+F: configs/T1040RDB_NAND_defconfig
+F: configs/T1040RDB_SPIFLASH_defconfig
+F: configs/T1042RDB_defconfig
+F: configs/T1042RDB_PI_defconfig
+F: configs/T1042RDB_PI_NAND_defconfig
+F: configs/T1042RDB_PI_SPIFLASH_defconfig
+
+T1040RDB_SDCARD BOARD
+#M: -
+S: Maintained
+F: configs/T1040RDB_SDCARD_defconfig
+F: configs/T1042RDB_PI_SDCARD_defconfig
+
+T1040RDB_SECURE_BOOT BOARD
+M: Aneesh Bansal <aneesh.bansal@freescale.com>
+S: Maintained
+F: configs/T1040RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile
new file mode 100644
index 0000000..b9ef17f
--- /dev/null
+++ b/board/freescale/t104xrdb/Makefile
@@ -0,0 +1,18 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += t104xrdb.o
+obj-y += cpld.o
+obj-y += eth.o
+obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_FSL_DIU_FB)+= diu.o
+endif
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README
new file mode 100644
index 0000000..ac95b5e
--- /dev/null
+++ b/board/freescale/t104xrdb/README
@@ -0,0 +1,286 @@
+Overview
+--------
+The T1040RDB is a Freescale reference board that hosts the T1040 SoC
+(and variants). Variants inclued T1042 presonality of T1040, in which
+case T1040RDB can also be called T1042RDB.
+
+The T1042RDB is a Freescale reference board that hosts the T1042 SoC
+(and variants). The board is similar to T1040RDB, T1040 is a reduced
+personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
+
+The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
+(a personality of T1040 SoC). The board is similar to T1040RDB but is
+designed specially with low power features targeted for Printing Image Market.
+
+Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
+-------------------------------------------------------------------------
+Board Si Protocol Targeted Market
+-------------------------------------------------------------------------
+T1040RDB T1040 0x66 Networking
+T1040RDB T1042 0x86 Networking
+T1042RDB_PI T1042 0x06 Printing & Imaging
+
+
+T1040 SoC Overview
+------------------
+The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
+processor cores with high-performance data path acceleration architecture
+and network peripheral interfaces required for networking & telecommunications.
+
+The T1040/T1042 SoC includes the following function and features:
+
+ - Four e5500 cores, each with a private 256 KB L2 cache
+ - 256 KB shared L3 CoreNet platform cache (CPC)
+ - Interconnect CoreNet platform
+ - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
+ support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ for the following functions:
+ - Packet parsing, classification, and distribution
+ - Queue management for scheduling, packet sequencing, and congestion
+ management
+ - Cryptography Acceleration (SEC 5.0)
+ - RegEx Pattern Matching Acceleration (PME 2.2)
+ - IEEE Std 1588 support
+ - Hardware buffer management for buffer allocation and deallocation
+ - Ethernet interfaces
+ - Integrated 8-port Gigabit Ethernet switch (T1040 only)
+ - Four 1 Gbps Ethernet controllers
+ - Two RGMII interfaces or one RGMII and one MII interfaces
+ - High speed peripheral interfaces
+ - Four PCI Express 2.0 controllers running at up to 5 GHz
+ - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
+ - Upto two QSGMII interface
+ - Upto six SGMII interface supporting 1000 Mbps
+ - One SGMII interface supporting upto 2500 Mbps
+ - Additional peripheral interfaces
+ - Two USB 2.0 controllers with integrated PHY
+ - SD/eSDHC/eMMC
+ - eSPI controller
+ - Four I2C controllers
+ - Four UARTs
+ - Four GPIO controllers
+ - Integrated flash controller (IFC)
+ - LCD and HDMI interface (DIU) with 12 bit dual data rate
+ - TDM interface
+ - Multicore programmable interrupt controller (PIC)
+ - Two 8-channel DMA engines
+ - Single source clocking implementation
+ - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+
+T1040 SoC Personalities
+-------------------------
+
+T1022 Personality:
+T1022 is a reduced personality of T1040 with less core/clusters.
+
+T1042 Personality:
+T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
+Ethernet switch. Rest of the blocks are same as T1040
+
+
+T1040RDB board Overview
+-------------------------
+ - SERDES Connections, 8 lanes information:
+ 1: None
+ 2: SGMII
+ 3: QSGMII
+ 4: QSGMII
+ 5: PCIe1 x1 slot
+ 6: mini PCIe connector
+ 7: mini PCIe connector
+ 8: SATA connector
+ - DDR Controller
+ - Supports rates of up to 1600 MHz data-rate
+ - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
+ - IFC/Local Bus
+ - NAND flash: 1GB 8-bit NAND flash
+ - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+ - Two on-board RGMII 10/100/1G ethernet ports.
+ - CPLD
+ - Clocks
+ - System and DDR clock (SYSCLK, “DDRCLK”)
+ - SERDES clocks
+ - Power Supplies
+ - USB
+ - Supports two USB 2.0 ports with integrated PHYs
+ - Two type A ports with 5V@1.5A per port.
+ - SDHC
+ - SDHC/SDXC connector
+ - SPI
+ - On-board 64MB SPI flash
+ - Other IO
+ - Two Serial ports
+ - Four I2C ports
+
+T1042RDB_PI board Overview
+-------------------------
+ - SERDES Connections, 8 lanes information:
+ 1, 2, 3, 4 : PCIe x4 slot
+ 5: mini PCIe connector
+ 6: mini PCIe connector
+ 7: NA
+ 8: SATA connector
+ - DDR Controller
+ - Supports rates of up to 1600 MHz data-rate
+ - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
+ - IFC/Local Bus
+ - NAND flash: 1GB 8-bit NAND flash
+ - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+ - Two on-board RGMII 10/100/1G ethernet ports.
+ - CPLD
+ - Clocks
+ - System and DDR clock (SYSCLK, “DDRCLK”)
+ - SERDES clocks
+ - Video
+ - DIU supports video at up to 1280x1024x32bpp
+ - Power Supplies
+ - USB
+ - Supports two USB 2.0 ports with integrated PHYs
+ - Two type A ports with 5V@1.5A per port.
+ - SDHC
+ - SDHC/SDXC connector
+ - SPI
+ - On-board 64MB SPI flash
+ - Other IO
+ - Two Serial ports
+ - Four I2C ports
+
+Memory map
+-----------
+The addresses in brackets are physical addresses.
+
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
+0x0_0000_0000 0x0_ffff_ffff DDR 2GB
+
+
+NOR Flash memory Map
+---------------------
+ Start End Definition Size
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+Various Software configurations/environment variables/commands
+--------------------------------------------------------------
+The below commands apply to the board
+
+1. U-boot environment variable hwconfig
+ The default hwconfig is:
+ hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
+ dr_mode=host,phy_type=utmi
+ Note: For USB gadget set "dr_mode=peripheral"
+
+2. FMAN Ucode versions
+ fsl_fman_ucode_t1040.bin
+
+3. Switching to alternate bank
+ Commands for switching to alternate bank.
+
+ 1. To change from vbank0 to vbank4
+ => cpld reset altbank (it will boot using vbank4)
+
+ 2.To change from vbank4 to vbank0
+ => cpld reset (it will boot using vbank0)
+
+NAND boot with 2 Stage boot loader
+----------------------------------
+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
+SPL further initialise DDR using SPD and environment variables and copy
+u-boot(768 KB) from flash to DDR.
+Finally SPL transer control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+ Run time view of SPL framework during boot :-
+ -----------------------------------------------
+ Area | Address |
+-----------------------------------------------
+ Secure boot | 0xFFFC0000 (32KB) |
+ headers | |
+ -----------------------------------------------
+ GD, BD | 0xFFFC8000 (4KB) |
+ -----------------------------------------------
+ ENV | 0xFFFC9000 (8KB) |
+ -----------------------------------------------
+ HEAP | 0xFFFCB000 (30KB) |
+ -----------------------------------------------
+ STACK | 0xFFFD8000 (22KB) |
+ -----------------------------------------------
+ U-boot SPL | 0xFFFD8000 (160KB) |
+ -----------------------------------------------
+
+NAND Flash memory Map on T104xRDB
+------------------------------------------
+ Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB
+0x180000 0x19FFFF u-boot env 128KB
+0x280000 0x29FFFF FMAN Ucode 128KB
+0x380000 0x39FFFF QE Firmware 128KB
+
+SD Card memory Map on T104xRDB
+------------------------------------------
+ Block #blocks Definition Size
+0x008 2048 u-boot 1MB
+0x800 0024 u-boot env 8KB
+0x820 0256 FMAN Ucode 128KB
+0x920 0256 QE Firmware 128KB
+
+SPI Flash memory Map on T104xRDB
+------------------------------------------
+ Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB
+0x100000 0x101FFF u-boot env 8KB
+0x110000 0x12FFFF FMAN Ucode 128KB
+0x130000 0x14FFFF QE Firmware 128KB
+
+Please note QE Firmware is only valid for T1040RDB
+
+
+Switch Settings: (ON is 0, OFF is 1)
+===============
+NAND boot SW setting:
+SW1: 10001000
+SW2: 00111011
+SW3: 11110001
+
+SPI boot SW setting:
+SW1: 00100010
+SW2: 10111011
+SW3: 11100001
+
+SD boot SW setting:
+SW1: 00100000
+SW2: 00111011
+SW3: 11100001
diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c
new file mode 100644
index 0000000..df0e348
--- /dev/null
+++ b/board/freescale/t104xrdb/cpld.c
@@ -0,0 +1,112 @@
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the board-specific CPLD used on some Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(void)
+{
+ u8 reg = CPLD_READ(flash_ctl_status);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
+
+ CPLD_WRITE(flash_ctl_status, reg);
+ CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+ u8 reg = CPLD_READ(flash_ctl_status);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
+
+ CPLD_WRITE(flash_ctl_status, reg);
+ CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+ printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
+ printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
+ printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
+ printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
+ printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
+ printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
+ printf("int_status = 0x%02x\n", CPLD_READ(int_status));
+ printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
+ printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
+ printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
+ printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
+ printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
+ printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
+ printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
+ printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
+ putc('\n');
+}
+#endif
+
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (strcmp(argv[2], "altbank") == 0)
+ cpld_set_altbank();
+ else
+ cpld_set_defbank();
+#ifdef DEBUG
+ } else if (strcmp(argv[1], "dump") == 0) {
+ cpld_dump_regs();
+#endif
+ } else
+ rc = cmd_usage(cmdtp);
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+ "Reset the board or alternate bank",
+ "reset - hard reset to default bank\n"
+ "cpld reset altbank - reset to alternate bank\n"
+#ifdef DEBUG
+ "cpld dump - display the CPLD registers\n"
+#endif
+ );
diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h
new file mode 100644
index 0000000..0da9a01
--- /dev/null
+++ b/board/freescale/t104xrdb/cpld.h
@@ -0,0 +1,40 @@
+/**
+ * Copyright 2013 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/*
+ * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
+ */
+struct cpld_data {
+ u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
+ u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
+ u8 hw_ver; /* 0x02 - Hardware Revision Register */
+ u8 sw_ver; /* 0x03 - Software Revision register */
+ u8 res0[12]; /* 0x04 - 0x0F - not used */
+ u8 reset_ctl1; /* 0x10 - Reset control Register1 */
+ u8 reset_ctl2; /* 0x11 - Reset control Register2 */
+ u8 int_status; /* 0x12 - Interrupt status Register */
+ u8 flash_ctl_status; /* 0x13 - Flash control and status register */
+ u8 fan_ctl_status; /* 0x14 - Fan control and status register */
+ u8 led_ctl_status; /* 0x15 - LED control and status register */
+ u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
+ u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
+ u8 boot_override; /* 0x18 - Boot override register */
+ u8 boot_config1; /* 0x19 - Boot config override register*/
+ u8 boot_config2; /* 0x1A - Boot config override register*/
+} cpld_data_t;
+
+
+/* Pointer to the CPLD register set */
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value)\
+ cpld_write(offsetof(struct cpld_data, reg), value)
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
new file mode 100644
index 0000000..5aa11b1
--- /dev/null
+++ b/board/freescale/t104xrdb/ddr.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "RAW timing DDR";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found\n");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * rtt and rtt_wr override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(cpld_base + 0x17, 0x40);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+#else
+ dram_size = fsl_ddr_sdram_size();
+#endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
+ return dram_size;
+}
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
new file mode 100644
index 0000000..09b30b9
--- /dev/null
+++ b/board/freescale/t104xrdb/ddr.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 2,
+ .rank_density = 2147483648u,
+ .capacity = 4294967296u,
+ .primary_sdram_width = 64,
+ .ec_sdram_width = 8,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 2, /* ECC */
+ .burst_lengths_bitmask = 0x0c,
+ .tckmin_x_ps = 1071,
+ .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */
+ .taa_ps = 13125,
+ .twr_ps = 15000,
+ .trcd_ps = 13125,
+ .trrd_ps = 6000,
+ .trp_ps = 13125,
+ .tras_ps = 34000,
+ .trc_ps = 48125,
+ .trfc_ps = 260000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 35000,
+};
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2
+ */
+ {2, 833, 4, 4, 6, 0x06060607, 0x08080807},
+ {2, 833, 0, 4, 6, 0x06060607, 0x08080807},
+ {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
+ {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
+ {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
+ {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
+ {1, 833, 4, 4, 6, 0x06060607, 0x08080807},
+ {1, 833, 0, 4, 6, 0x06060607, 0x08080807},
+ {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
+ {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
+ {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
+ {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+#endif
diff --git a/board/freescale/t104xrdb/diu.c b/board/freescale/t104xrdb/diu.c
new file mode 100644
index 0000000..3285bef
--- /dev/null
+++ b/board/freescale/t104xrdb/diu.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <command.h>
+#include <fsl_diu_fb.h>
+#include <linux/ctype.h>
+#include <video_fb.h>
+
+#include "../common/diu_ch7301.h"
+
+#include "cpld.h"
+#include "t104xrdb.h"
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register. So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F 0x10000000
+#define AD_ALPHA_C_SHIFT 25
+#define AD_BLUE_C_SHIFT 23
+#define AD_GREEN_C_SHIFT 21
+#define AD_RED_C_SHIFT 19
+#define AD_PIXEL_S_SHIFT 16
+#define AD_COMP_3_SHIFT 12
+#define AD_COMP_2_SHIFT 8
+#define AD_COMP_1_SHIFT 4
+#define AD_COMP_0_SHIFT 0
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+ unsigned long speed_ccb, temp;
+ u32 pixval;
+ int ret;
+
+ speed_ccb = get_bus_freq(0);
+ temp = 1000000000 / pixclock;
+ temp *= 1000;
+ pixval = speed_ccb / temp;
+
+ /* Program HDMI encoder */
+ ret = diu_set_dvi_encoder(temp);
+ if (ret) {
+ puts("Failed to set DVI encoder\n");
+ return;
+ }
+
+ /* Program pixel clock */
+ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
+ ((pixval << PXCK_BITS_START) & PXCK_MASK));
+
+ /* enable clock*/
+ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
+ ((pixval << PXCK_BITS_START) & PXCK_MASK));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+ u32 pixel_format;
+ u8 sw;
+
+ /*Configure Display ouput port as HDMI*/
+ sw = CPLD_READ(sfp_ctl_status);
+ CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
+
+ pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+ (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+ (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+ (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+ (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+ printf("DIU: Switching to monitor DVI @ %ux%u\n", xres, yres);
+
+ return fsl_diu_init(xres, yres, pixel_format, 0);
+}
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
new file mode 100644
index 0000000..c8b6c67
--- /dev/null
+++ b/board/freescale/t104xrdb/eth.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/immap_85xx.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/fman.h"
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct memac_mdio_info memac_mdio_info;
+ unsigned int i;
+ int phy_addr = 0;
+ printf("Initializing Fman\n");
+
+ memac_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the real 1G MDIO bus */
+ fm_memac_mdio_init(bis, &memac_mdio_info);
+
+ /*
+ * Program on board RGMII, SGMII PHY addresses.
+ */
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+#ifdef CONFIG_T1040RDB
+ case PHY_INTERFACE_MODE_SGMII:
+ /* T1040RDB only supports SGMII on DTSEC3 */
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_SGMII1_PHY_ADDR);
+ break;
+#endif
+#ifdef CONFIG_T1042RDB
+ case PHY_INTERFACE_MODE_SGMII:
+ /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
+ if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
+ fm_info_set_phy_address(i, 0);
+ /* T1042RDB only supports SGMII on DTSEC3 */
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_SGMII1_PHY_ADDR);
+ break;
+#endif
+ case PHY_INTERFACE_MODE_RGMII:
+ if (FM1_DTSEC4 == i)
+ phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
+ if (FM1_DTSEC5 == i)
+ phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
+ fm_info_set_phy_address(i, phy_addr);
+ break;
+ case PHY_INTERFACE_MODE_QSGMII:
+ fm_info_set_phy_address(i, 0);
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
+ break;
+ default:
+ printf("Fman1: DTSEC%u set to unknown interface %i\n",
+ idx + 1, fm_info_get_enet_if(i));
+ fm_info_set_phy_address(i, 0);
+ break;
+ }
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ }
+
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c
new file mode 100644
index 0000000..2362d43
--- /dev/null
+++ b/board/freescale/t104xrdb/law.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c
new file mode 100644
index 0000000..c53e3b7
--- /dev/null
+++ b/board/freescale/t104xrdb/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
new file mode 100644
index 0000000..4e8735b
--- /dev/null
+++ b/board/freescale/t104xrdb/spl.c
@@ -0,0 +1,134 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include "../common/sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, uart_clk;
+#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
+ u32 porsr1, pinctl;
+ u32 svr = get_svr();
+#endif
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
+ if (IS_SVR_REV(svr, 1, 0)) {
+ /*
+ * There is T1040 SoC issue where NOR, FPGA are inaccessible
+ * during NAND boot because IFC signals > IFC_AD7 are not
+ * enabled. This workaround changes RCW source to make all
+ * signals enabled.
+ */
+ porsr1 = in_be32(&gur->porsr1);
+ pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
+ | 0x24800000);
+ out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
+ pinctl);
+ }
+#endif
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+#ifdef CONFIG_DEEP_SLEEP
+ /* disable the console if boot from deep sleep */
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("" : : : "memory");
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ uart_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ uart_clk / 16 / CONFIG_BAUDRATE);
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ puts("\n\n");
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/t104xrdb/t1040_rcw.cfg b/board/freescale/t104xrdb/t1040_rcw.cfg
new file mode 100644
index 0000000..3300c18
--- /dev/null
+++ b/board/freescale/t104xrdb/t1040_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 80000002 e8106000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_pi_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_rcw.cfg
new file mode 100644
index 0000000..57de89a
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042_pi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x06
+0c18000e 0e000000 00000000 00000000
+06000002 00400002 e8106000 01000000
+00000000 00000000 00000000 00030810
+00000000 01fe0a06 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_rcw.cfg b/board/freescale/t104xrdb/t1042_rcw.cfg
new file mode 100644
index 0000000..db4d52f
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 80000002 ec027000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg
new file mode 100644
index 0000000..b83b9b7
--- /dev/null
+++ b/board/freescale/t104xrdb/t104x_pbi.cfg
@@ -0,0 +1,36 @@
+#PBI commands
+#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
+09250100 00000400
+09250108 00002000
+#Software Workaround for errata A-008007 to reset PVR register
+09000010 0000000b
+09000014 c0000000
+09000018 81d00017
+89020400 a1000000
+091380c0 000f0000
+89020400 00000000
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
new file mode 100644
index 0000000..9cd5e15
--- /dev/null
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include "../common/sleep.h"
+#include "t104xrdb.h"
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+ u8 sw;
+
+ printf("Board: %sRDB\n", cpu->name);
+ printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
+ CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+
+ sw = CPLD_READ(flash_ctl_status);
+ sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
+
+ if (sw <= 7)
+ printf("vBank: %d\n", sw);
+ else
+ printf("Unsupported Bank=%x\n", sw);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+#endif
+
+ return 0;
+}
diff --git a/board/freescale/t104xrdb/t104xrdb.h b/board/freescale/t104xrdb/t104xrdb.h
new file mode 100644
index 0000000..e7cc0c7
--- /dev/null
+++ b/board/freescale/t104xrdb/t104xrdb.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T104x_RDB_H__
+#define __T104x_RDB_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
new file mode 100644
index 0000000..95c15aa
--- /dev/null
+++ b/board/freescale/t104xrdb/tlb.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+ * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1),
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 12, BOOKE_PAGESZ_1G, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 13, BOOKE_PAGESZ_1G, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig
new file mode 100644
index 0000000..4e329dd
--- /dev/null
+++ b/board/freescale/t208xqds/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_T208XQDS
+
+config SYS_BOARD
+ default "t208xqds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "T208xQDS"
+
+endif
diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS
new file mode 100644
index 0000000..deda092
--- /dev/null
+++ b/board/freescale/t208xqds/MAINTAINERS
@@ -0,0 +1,20 @@
+T208XQDS BOARD
+#M: -
+S: Maintained
+F: board/freescale/t208xqds/
+F: include/configs/T208xQDS.h
+F: configs/T2080QDS_defconfig
+F: configs/T2080QDS_NAND_defconfig
+F: configs/T2080QDS_SDCARD_defconfig
+F: configs/T2080QDS_SPIFLASH_defconfig
+F: configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+F: configs/T2081QDS_defconfig
+F: configs/T2081QDS_NAND_defconfig
+F: configs/T2081QDS_SDCARD_defconfig
+F: configs/T2081QDS_SPIFLASH_defconfig
+F: configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+
+T2080QDS_SECURE_BOOT BOARD
+M: Aneesh Bansal <aneesh.bansal@freescale.com>
+S: Maintained
+F: configs/T2080QDS_SECURE_BOOT_defconfig
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile
new file mode 100644
index 0000000..6cb72c9
--- /dev/null
+++ b/board/freescale/t208xqds/Makefile
@@ -0,0 +1,19 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-$(CONFIG_T2080QDS) += t208xqds.o
+obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
+obj-$(CONFIG_T2081QDS) += t208xqds.o
+obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
+obj-$(CONFIG_PCI) += pci.o
+endif
+
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README
new file mode 100755
index 0000000..83060c1
--- /dev/null
+++ b/board/freescale/t208xqds/README
@@ -0,0 +1,274 @@
+The T2080QDS is a high-performance computing evaluation, development and
+test platform supporting the T2080 QorIQ Power Architecture processor.
+
+T2080 SoC Overview
+------------------
+The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
+Architecture processor cores with high-performance datapath acceleration
+logic and network and peripheral bus interfaces required for networking,
+telecom/datacom, wireless infrastructure, and mil/aerospace applications.
+
+T2080 includes the following functions and features:
+ - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
+ - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
+ - Hierarchical interconnect fabric
+ - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ - 16 SerDes lanes up to 10.3125 GHz
+ - 8 Ethernet interfaces, supporting combinations of the following:
+ - Up to four 10 Gbps Ethernet MACs
+ - Up to eight 1 Gbps Ethernet MACs
+ - Up to four 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+ - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+ - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
+ - Additional peripheral interfaces
+ - Two serial ATA (SATA 2.0) controllers
+ - Two high-speed USB 2.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
+ - Enhanced serial peripheral interface (eSPI)
+ - Four I2C controllers
+ - Four 2-pin UARTs or two 4-pin UARTs
+ - Integrated Flash Controller supporting NAND and NOR flash
+ - Three eight-channel DMA engines
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ Platform's Trust Architecture 2.0
+
+Differences between T2080 and T2081
+-----------------------------------
+ Feature T2080 T2081
+ 1G Ethernet numbers: 8 6
+ 10G Ethernet numbers: 4 2
+ SerDes lanes: 16 8
+ Serial RapidIO,RMan: 2 no
+ SATA Controller: 2 no
+ Aurora: yes no
+ SoC Package: 896-pins 780-pins
+
+
+T2080QDS feature overview
+-------------------------
+Processor:
+ - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
+Memory:
+ - Single memory controller capable of supporting DDR3 and DDR3-LV devices
+ - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
+Ethernet interfaces:
+ - Two 1Gbps RGMII on-board ports
+ - Four 10Gbps XFI on-board cages
+ - 1Gbps/2.5Gbps SGMII Riser card
+ - 10Gbps XAUI Riser card
+Accelerator:
+ - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
+SerDes:
+ - 16 lanes up to 10.3125GHz
+ - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
+IFC:
+ - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
+eSPI:
+ - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
+USB:
+ - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
+PCIE:
+ - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+SATA:
+ - Two SATA 2.0 ports on-board
+SRIO:
+ - Two Serial RapidIO 2.0 ports up to 5 GHz
+eSDHC:
+ - Supports SD/SDHC/SDXC/eMMC Card
+I2C:
+ - Four I2C controllers.
+UART:
+ - Dual 4-pins UART serial ports
+System Logic:
+ - QIXIS-II FPGA system controll
+Debug Features:
+ - Support Legacy, COP/JTAG, Aurora, Event and EVT
+XFI:
+ - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
+ a on-board SFP+ cages, which to house optical module (fiber cable) or
+ direct attach cable(copper), the copper cable is used to emulate
+ 10GBASE-KR scenario.
+ So, for XFI usage, there are two scenarios, one will use fiber cable,
+ another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
+ introduced to indicate a XFI port will use copper cable, and U-boot
+ will fixup the dtb accordingly.
+ It's used as: fsl_10gkr_copper:<10g_mac_name>
+ The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
+ do not have to be coexist in hwconfig. If a MAC is listed in the env
+ "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
+ will be used by default.
+ for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
+ hwconfig, then both four XFI ports will use copper cable.
+ set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
+ XFI ports will use copper cable, the other two XFI ports will use fiber
+ cable.
+1000BASE-KX(1G-KX):
+ - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
+ runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
+ in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
+ Register 1 (PCCR1), and U-boot fixup the dtb for kernel to do proper
+ initialization.
+ Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
+ 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
+ MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
+ stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
+ For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in
+ hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
+
+System Memory map
+----------------
+
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
+0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
+0x0_0000_0000 0x0_ffff_ffff DDR 4GB
+
+
+128M NOR Flash memory Map
+-------------------------
+Start Address End Address Definition Max size
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+ a. build NOR boot image
+ $ make T2080QDS_config
+ $ make
+ b. program u-boot.bin image to NOR flash
+ => tftp 1000000 u-boot.bin
+ => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+ set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
+
+ Switching between default bank0 and alternate bank4 on NOR flash
+ To change boot source to vbank4:
+ by software: run command 'qixis_reset altbank' in u-boot.
+ by DIP-switch: set SW6[1:4] = '0100'
+
+ To change boot source to vbank0:
+ by software: run command 'qixis_reset' in u-boot.
+ by DIP-Switch: set SW6[1:4] = '0000'
+
+2. NAND Boot:
+ a. build PBL image for NAND boot
+ $ make T2080QDS_NAND_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to NAND flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => nand erase 0 $filesize
+ => nand write 1000000 0 $filesize
+ set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
+
+3. SPI Boot:
+ a. build PBL image for SPI boot
+ $ make T2080QDS_SPIFLASH_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SPI flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => sf probe 0
+ => sf erase 0 f0000
+ => sf write 1000000 0 $filesize
+ set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+ a. build PBL image for SD boot
+ $ make T2080QDS_SDCARD_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SD/MMC card
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => mmc write 1000000 8 0x800
+ => tftp 1000000 fsl_fman_ucode_T2080_xx.bin
+ => mmc write 1000000 0x820 80
+ set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (50KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T2080QDS
+--------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB (2 blocks)
+0x100000 0x17FFFF u-boot env 512KB (1 block)
+0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
+
+
+Micro SD Card memory Map on T2080QDS
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 u-boot img 1MB
+0x800 0016 u-boot env 8KB
+0x820 0128 FMAN ucode 64KB
+
+
+SPI Flash memory Map on T2080QDS
+----------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB
+0x100000 0x101FFF u-boot env 8KB
+0x110000 0x11FFFF FMAN ucode 64KB
+
+
+How to update the ucode of Freescale FMAN
+-----------------------------------------
+=> tftp 1000000 fsl_fman_ucode_t2080_xx.bin
+=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
+
+
+For more details, please refer to T2080QDS User Guide and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c
new file mode 100644
index 0000000..3348971
--- /dev/null
+++ b/board/freescale/t208xqds/ddr.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[0];
+ else
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+ puts("Initializing....using SPD\n");
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+#else
+ /* DDR has been initialised by first stage boot loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
+
+ return dram_size;
+}
diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h
new file mode 100644
index 0000000..9c26fdf
--- /dev/null
+++ b/board/freescale/t208xqds/ddr.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ */
+ {2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09},
+ {2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a},
+ {2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c},
+ {2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d},
+ {2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d},
+ {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
+ {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
+ {1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c},
+ {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ */
+ /* TODO: need tuning these parameters if RDIMM is used */
+ {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
+ {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+};
+#endif
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
new file mode 100644
index 0000000..b82e9e7
--- /dev/null
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -0,0 +1,812 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include <hwconfig.h>
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "t208xqds_qixis.h"
+
+#define EMI_NONE 0xFFFFFFFF
+#define EMI1_RGMII1 0
+#define EMI1_RGMII2 1
+#define EMI1_SLOT1 2
+#if defined(CONFIG_T2080QDS)
+#define EMI1_SLOT2 6
+#define EMI1_SLOT3 3
+#define EMI1_SLOT4 4
+#define EMI1_SLOT5 5
+#define EMI2 7
+#elif defined(CONFIG_T2081QDS)
+#define EMI1_SLOT2 3
+#define EMI1_SLOT3 4
+#define EMI1_SLOT5 5
+#define EMI1_SLOT6 6
+#define EMI1_SLOT7 7
+#define EMI2 8
+#endif
+
+#define PCCR1_SGMIIA_KX_MASK 0x00008000
+#define PCCR1_SGMIIB_KX_MASK 0x00004000
+#define PCCR1_SGMIIC_KX_MASK 0x00002000
+#define PCCR1_SGMIID_KX_MASK 0x00001000
+#define PCCR1_SGMIIE_KX_MASK 0x00000800
+#define PCCR1_SGMIIF_KX_MASK 0x00000400
+#define PCCR1_SGMIIG_KX_MASK 0x00000200
+#define PCCR1_SGMIIH_KX_MASK 0x00000100
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+#if defined(CONFIG_T2080QDS)
+ "T2080QDS_MDIO_RGMII1",
+ "T2080QDS_MDIO_RGMII2",
+ "T2080QDS_MDIO_SLOT1",
+ "T2080QDS_MDIO_SLOT3",
+ "T2080QDS_MDIO_SLOT4",
+ "T2080QDS_MDIO_SLOT5",
+ "T2080QDS_MDIO_SLOT2",
+ "T2080QDS_MDIO_10GC",
+#elif defined(CONFIG_T2081QDS)
+ "T2081QDS_MDIO_RGMII1",
+ "T2081QDS_MDIO_RGMII2",
+ "T2081QDS_MDIO_SLOT1",
+ "T2081QDS_MDIO_SLOT2",
+ "T2081QDS_MDIO_SLOT3",
+ "T2081QDS_MDIO_SLOT5",
+ "T2081QDS_MDIO_SLOT6",
+ "T2081QDS_MDIO_SLOT7",
+ "T2081QDS_MDIO_10GC",
+#endif
+};
+
+/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
+#if defined(CONFIG_T2080QDS)
+static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
+#elif defined(CONFIG_T2081QDS)
+static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
+#endif
+
+static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name = t208xqds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+struct t208xqds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void t208xqds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+ if (muxval < 8) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct t208xqds_mdio *priv = bus->priv;
+
+ t208xqds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct t208xqds_mdio *priv = bus->priv;
+
+ t208xqds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t208xqds_mdio_reset(struct mii_dev *bus)
+{
+ struct t208xqds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int t208xqds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct t208xqds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate t208xqds MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate t208xqds private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = t208xqds_mdio_read;
+ bus->write = t208xqds_mdio_write;
+ bus->reset = t208xqds_mdio_reset;
+ sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+ return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ int phy;
+ char alias[20];
+ char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
+ char buf[32] = "serdes-1,";
+ struct fixed_link f_link;
+ int media_type = 0;
+ int off;
+
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_T2080QDS
+ serdes_corenet_t *srds_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
+#endif
+ u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ phy = fm_info_get_phy_address(port);
+ switch (port) {
+#if defined(CONFIG_T2080QDS)
+ case FM1_DTSEC1:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx1");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
+ sprintf(buf, "%s%s%s", buf, "lane-c,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIH_KX_MASK);
+ break;
+ }
+ case FM1_DTSEC2:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx2");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
+ sprintf(buf, "%s%s%s", buf, "lane-d,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIG_KX_MASK);
+ break;
+ }
+ case FM1_DTSEC9:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx9");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
+ sprintf(buf, "%s%s%s", buf, "lane-a,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIE_KX_MASK);
+ break;
+ }
+ case FM1_DTSEC10:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx10");
+ fdt_status_okay_by_alias(fdt,
+ "1gkx_pcs_mdio10");
+ sprintf(buf, "%s%s%s", buf, "lane-b,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIF_KX_MASK);
+ break;
+ }
+ if (mdio_mux[port] == EMI1_SLOT2) {
+ sprintf(alias, "phy_sgmii_s2_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ } else if (mdio_mux[port] == EMI1_SLOT3) {
+ sprintf(alias, "phy_sgmii_s3_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ }
+ break;
+ case FM1_DTSEC5:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx5");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
+ sprintf(buf, "%s%s%s", buf, "lane-g,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIIC_KX_MASK);
+ break;
+ }
+ case FM1_DTSEC6:
+ if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_1gkx6");
+ fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
+ sprintf(buf, "%s%s%s", buf, "lane-h,",
+ (char *)lane_mode[0]);
+ out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
+ PCCR1_SGMIID_KX_MASK);
+ break;
+ }
+ if (mdio_mux[port] == EMI1_SLOT1) {
+ sprintf(alias, "phy_sgmii_s1_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot1");
+ } else if (mdio_mux[port] == EMI1_SLOT2) {
+ sprintf(alias, "phy_sgmii_s2_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ }
+ break;
+#elif defined(CONFIG_T2081QDS)
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ case FM1_DTSEC9:
+ case FM1_DTSEC10:
+ if (mdio_mux[port] == EMI1_SLOT2) {
+ sprintf(alias, "phy_sgmii_s2_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ } else if (mdio_mux[port] == EMI1_SLOT3) {
+ sprintf(alias, "phy_sgmii_s3_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ } else if (mdio_mux[port] == EMI1_SLOT5) {
+ sprintf(alias, "phy_sgmii_s5_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot5");
+ } else if (mdio_mux[port] == EMI1_SLOT6) {
+ sprintf(alias, "phy_sgmii_s6_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot6");
+ } else if (mdio_mux[port] == EMI1_SLOT7) {
+ sprintf(alias, "phy_sgmii_s7_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot7");
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+ if (media_type) {
+ /* set property for 1000BASE-KX in dtb */
+ off = fdt_node_offset_by_compat_reg(fdt,
+ "fsl,fman-memac-mdio", addr + 0x1000);
+ fdt_setprop_string(fdt, off, "lane-instance", buf);
+ }
+
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+ switch (srds_s1) {
+ case 0x66: /* XFI interface */
+ case 0x6b:
+ case 0x6c:
+ case 0x6d:
+ case 0x71:
+ /*
+ * if the 10G is XFI, check hwconfig to see what is the
+ * media type, there are two types, fiber or copper,
+ * fix the dtb accordingly.
+ */
+ switch (port) {
+ case FM1_10GEC1:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
+ /* it's MAC9 */
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_xfi9");
+ fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
+ sprintf(buf, "%s%s%s", buf, "lane-a,",
+ (char *)lane_mode[1]);
+ }
+ break;
+ case FM1_10GEC2:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
+ /* it's MAC10 */
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_xfi10");
+ fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
+ sprintf(buf, "%s%s%s", buf, "lane-b,",
+ (char *)lane_mode[1]);
+ }
+ break;
+ case FM1_10GEC3:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
+ /* it's MAC1 */
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_xfi1");
+ fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
+ sprintf(buf, "%s%s%s", buf, "lane-c,",
+ (char *)lane_mode[1]);
+ }
+ break;
+ case FM1_10GEC4:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
+ /* it's MAC2 */
+ media_type = 1;
+ fdt_set_phy_handle(fdt, compat, addr,
+ "phy_xfi2");
+ fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
+ sprintf(buf, "%s%s%s", buf, "lane-d,",
+ (char *)lane_mode[1]);
+ }
+ break;
+ default:
+ return;
+ }
+
+ if (!media_type) {
+ /* fixed-link is used for XFI fiber cable */
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link,
+ sizeof(f_link));
+ } else {
+ /* set property for copper cable */
+ off = fdt_node_offset_by_compat_reg(fdt,
+ "fsl,fman-memac-mdio", addr + 0x1000);
+ fdt_setprop_string(fdt, off,
+ "lane-instance", buf);
+ }
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ return;
+}
+
+/*
+ * This function reads RCW to check if Serdes1{A:H} is configured
+ * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ switch (srds_s1) {
+#if defined(CONFIG_T2080QDS)
+ case 0x51:
+ case 0x5f:
+ case 0x65:
+ case 0x6b:
+ case 0x71:
+ lane_to_slot[5] = 2;
+ lane_to_slot[6] = 2;
+ lane_to_slot[7] = 2;
+ break;
+ case 0xa6:
+ case 0x8e:
+ case 0x8f:
+ case 0x82:
+ case 0x83:
+ case 0xd3:
+ case 0xd9:
+ case 0xcb:
+ lane_to_slot[6] = 2;
+ lane_to_slot[7] = 2;
+ break;
+ case 0xda:
+ lane_to_slot[4] = 3;
+ lane_to_slot[5] = 3;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+#elif defined(CONFIG_T2081QDS)
+ case 0x6b:
+ lane_to_slot[4] = 1;
+ lane_to_slot[5] = 3;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0xca:
+ case 0xcb:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 6;
+ lane_to_slot[3] = 5;
+ lane_to_slot[5] = 3;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0xf2:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ lane_to_slot[5] = 4;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 7;
+ break;
+#endif
+ default:
+ break;
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, idx, lane, slot, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ initialize_lane_to_slot();
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Register the muxing front-ends to the MDIO buses */
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+#if defined(CONFIG_T2080QDS)
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+#endif
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+#if defined(CONFIG_T2081QDS)
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+#endif
+ t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+ if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+ FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+ else
+ fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
+
+ switch (srds_s1) {
+ case 0x1b:
+ case 0x1c:
+ case 0x95:
+ case 0xa2:
+ case 0x94:
+ /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ case 0x50:
+ case 0x51:
+ case 0x5e:
+ case 0x5f:
+ case 0x64:
+ case 0x65:
+ /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+ /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ case 0x66:
+ case 0x67:
+ /*
+ * XFI does not need a PHY to work, but to avoid U-boot use
+ * default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to XFI
+ * MAC, and should not use a real XAUI PHY address, since
+ * MDIO can access it successfully, and then MDIO thinks
+ * the XAUI card is used for the XFI MAC, which will cause
+ * error.
+ */
+ fm_info_set_phy_address(FM1_10GEC1, 4);
+ fm_info_set_phy_address(FM1_10GEC2, 5);
+ fm_info_set_phy_address(FM1_10GEC3, 6);
+ fm_info_set_phy_address(FM1_10GEC4, 7);
+ break;
+ case 0x6a:
+ case 0x6b:
+ fm_info_set_phy_address(FM1_10GEC1, 4);
+ fm_info_set_phy_address(FM1_10GEC2, 5);
+ fm_info_set_phy_address(FM1_10GEC3, 6);
+ fm_info_set_phy_address(FM1_10GEC4, 7);
+ /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ case 0x6c:
+ case 0x6d:
+ fm_info_set_phy_address(FM1_10GEC1, 4);
+ fm_info_set_phy_address(FM1_10GEC2, 5);
+ /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ case 0x70:
+ case 0x71:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ case 0xa6:
+ case 0x8e:
+ case 0x8f:
+ case 0x82:
+ case 0x83:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ case 0xa4:
+ case 0x96:
+ case 0x8a:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+#if defined(CONFIG_T2080QDS)
+ case 0xd9:
+ case 0xd3:
+ case 0xcb:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+#elif defined(CONFIG_T2081QDS)
+ case 0xca:
+ case 0xcb:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ /* SGMII in Slot5 */
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ /* SGMII in Slot6 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ /* SGMII in Slot7 */
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ break;
+#endif
+ case 0xf2:
+ /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ default:
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ idx = i - FM1_DTSEC1;
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot[lane];
+ debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+
+ switch (slot) {
+ case 1:
+ mdio_mux[i] = EMI1_SLOT1;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 2:
+ mdio_mux[i] = EMI1_SLOT2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 3:
+ mdio_mux[i] = EMI1_SLOT3;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+#if defined(CONFIG_T2081QDS)
+ case 5:
+ mdio_mux[i] = EMI1_SLOT5;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 6:
+ mdio_mux[i] = EMI1_SLOT6;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 7:
+ mdio_mux[i] = EMI1_SLOT7;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+#endif
+ }
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if (i == FM1_DTSEC3)
+ mdio_mux[i] = EMI1_RGMII1;
+ else if (i == FM1_DTSEC4 || FM1_DTSEC10)
+ mdio_mux[i] = EMI1_RGMII2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ idx = i - FM1_10GEC1;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ if (srds_s1 == 0x51) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ XAUI_FM1_MAC9 + idx);
+ } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ HIGIG_FM1_MAC9 + idx);
+ } else {
+ if (i == FM1_10GEC1 || i == FM1_10GEC2)
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ XFI_FM1_MAC9 + idx);
+ else
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ XFI_FM1_MAC1 + idx);
+ }
+
+ if (lane < 0)
+ break;
+ mdio_mux[i] = EMI2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+
+ if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
+ (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
+ (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
+ (srds_s1 == 0x71)) {
+ /* As XFI is in cage intead of a slot, so
+ * ensure doesn't disable the corresponding port
+ */
+ break;
+ }
+
+ slot = lane_to_slot[lane];
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c
new file mode 100644
index 0000000..74e2a53
--- /dev/null
+++ b/board/freescale/t208xqds/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef QIXIS_BASE_PHYS
+ SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c
new file mode 100644
index 0000000..84a89da
--- /dev/null
+++ b/board/freescale/t208xqds/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2007-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
new file mode 100644
index 0000000..a71c617
--- /dev/null
+++ b/board/freescale/t208xqds/spl.c
@@ -0,0 +1,137 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+#include "../common/qixis.h"
+#include "t208xqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ puts("\nNAND boot...\n");
+#endif
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/t208xqds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg
new file mode 100644
index 0000000..52a1652
--- /dev/null
+++ b/board/freescale/t208xqds/t2080_rcw.cfg
@@ -0,0 +1,16 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
+#12100017 15000000 00000000 00000000
+#66150002 00008400 e8104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
+0c070012 0e000000 00000000 00000000
+66150002 00000000 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2081_rcw.cfg b/board/freescale/t208xqds/t2081_rcw.cfg
new file mode 100644
index 0000000..a2d5ecf
--- /dev/null
+++ b/board/freescale/t208xqds/t2081_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t208x_pbi.cfg b/board/freescale/t208xqds/t208x_pbi.cfg
new file mode 100644
index 0000000..e200d92
--- /dev/null
+++ b/board/freescale/t208xqds/t208x_pbi.cfg
@@ -0,0 +1,41 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
new file mode 100644
index 0000000..7c89cd5
--- /dev/null
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -0,0 +1,478 @@
+/*
+ * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "../common/vid.h"
+#include "t208xqds.h"
+#include "t208xqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ char buf[64];
+ u8 sw;
+ struct cpu_type *cpu = gd->arch.cpu;
+ static const char *freq[4] = {
+ "100.00MHZ(from 8T49N222A)", "125.00MHz",
+ "156.25MHZ", "100.00MHz"
+ };
+
+ printf("Board: %sQDS, ", cpu->name);
+ sw = QIXIS_READ(arch);
+ printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
+ printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+#ifdef CONFIG_SDCARD
+ puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+ puts("SPI\n");
+#else
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank%d\n", sw);
+ else if (sw == 0x8)
+ puts("Promjet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+ printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
+ qixis_read_tag(buf), (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
+ puts("SERDES Reference Clocks:\n");
+ sw = QIXIS_READ(brdcfg[2]);
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
+ freq[(sw >> 4) & 0x3]);
+ printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
+ freq[sw & 0x3]);
+
+ return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return select_i2c_ch_pca9547(channel);
+}
+
+int brd_mux_lane_to_slot(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1;
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+#if defined(CONFIG_T2080QDS)
+ u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+#endif
+
+ switch (srds_prtcl_s1) {
+ case 0:
+ /* SerDes1 is not enabled */
+ break;
+#if defined(CONFIG_T2080QDS)
+ case 0x1b:
+ case 0x1c:
+ case 0xa2:
+ /* SD1(A:D) => SLOT3 SGMII
+ * SD1(G:H) => SLOT1 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x1a);
+ break;
+ case 0x94:
+ case 0x95:
+ /* SD1(A:B) => SLOT3 SGMII@1.25bps
+ * SD1(C:D) => SFP Module, SGMII@3.125bps
+ * SD1(E:H) => SLOT1 SGMII@1.25bps
+ */
+ case 0x96:
+ /* SD1(A:B) => SLOT3 SGMII@1.25bps
+ * SD1(C) => SFP Module, SGMII@3.125bps
+ * SD1(D) => SFP Module, SGMII@1.25bps
+ * SD1(E:H) => SLOT1 PCIe4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0x3a);
+ break;
+ case 0x50:
+ case 0x51:
+ /* SD1(A:D) => SLOT3 XAUI
+ * SD1(E) => SLOT1 PCIe4
+ * SD1(F:H) => SLOT2 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x15);
+ break;
+ case 0x66:
+ case 0x67:
+ /* SD1(A:D) => XFI cage
+ * SD1(E:H) => SLOT1 PCIe4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xfe);
+ break;
+ case 0x6a:
+ case 0x6b:
+ /* SD1(A:D) => XFI cage
+ * SD1(E) => SLOT1 PCIe4
+ * SD1(F:H) => SLOT2 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0xf1);
+ break;
+ case 0x6c:
+ case 0x6d:
+ /* SD1(A:B) => XFI cage
+ * SD1(C:D) => SLOT3 SGMII
+ * SD1(E:H) => SLOT1 PCIe4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xda);
+ break;
+ case 0x6e:
+ /* SD1(A:B) => SFP Module, XFI
+ * SD1(C:D) => SLOT3 SGMII
+ * SD1(E:F) => SLOT1 PCIe4 x2
+ * SD1(G:H) => SLOT2 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0xd9);
+ break;
+ case 0xda:
+ /* SD1(A:H) => SLOT3 PCIe3 x8
+ */
+ QIXIS_WRITE(brdcfg[12], 0x0);
+ break;
+ case 0xc8:
+ /* SD1(A) => SLOT3 PCIe3 x1
+ * SD1(B) => SFP Module, SGMII@1.25bps
+ * SD1(C:D) => SFP Module, SGMII@3.125bps
+ * SD1(E:F) => SLOT1 PCIe4 x2
+ * SD1(G:H) => SLOT2 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x79);
+ break;
+ case 0xab:
+ /* SD1(A:D) => SLOT3 PCIe3 x4
+ * SD1(E:H) => SLOT1 PCIe4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0x1a);
+ break;
+#elif defined(CONFIG_T2081QDS)
+ case 0x50:
+ case 0x51:
+ /* SD1(A:D) => SLOT2 XAUI
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F:H) => SLOT3 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x98);
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0x6a:
+ case 0x6b:
+ /* SD1(A:D) => XFI SFP Module
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F:H) => SLOT3 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x80);
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0x6c:
+ case 0x6d:
+ /* SD1(A:B) => XFI SFP Module
+ * SD1(C:D) => SLOT2 SGMII
+ * SD1(E:H) => SLOT1 PCIe4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xe8);
+ QIXIS_WRITE(brdcfg[13], 0x0);
+ break;
+ case 0xaa:
+ case 0xab:
+ /* SD1(A:D) => SLOT2 PCIe3 x4
+ * SD1(F:H) => SLOT1 SGMI4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xf8);
+ QIXIS_WRITE(brdcfg[13], 0x0);
+ break;
+ case 0xca:
+ case 0xcb:
+ /* SD1(A) => SLOT2 PCIe3 x1
+ * SD1(B) => SLOT7 SGMII
+ * SD1(C) => SLOT6 SGMII
+ * SD1(D) => SLOT5 SGMII
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F:H) => SLOT3 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x80);
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0xde:
+ case 0xdf:
+ /* SD1(A:D) => SLOT2 PCIe3 x4
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F) => SLOT4 PCIe1 x1
+ * SD1(G) => SLOT3 PCIe2 x1
+ * SD1(H) => SLOT7 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x98);
+ QIXIS_WRITE(brdcfg[13], 0x25);
+ break;
+ case 0xf2:
+ /* SD1(A) => SLOT2 PCIe3 x1
+ * SD1(B:D) => SLOT7 SGMII
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F) => SLOT4 PCIe1 x1
+ * SD1(G) => SLOT3 PCIe2 x1
+ * SD1(H) => SLOT7 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x81);
+ QIXIS_WRITE(brdcfg[13], 0xa5);
+ break;
+#endif
+ default:
+ printf("WARNING: unsupported for SerDes1 Protocol %d\n",
+ srds_prtcl_s1);
+ return -1;
+ }
+
+#ifdef CONFIG_T2080QDS
+ switch (srds_prtcl_s2) {
+ case 0:
+ /* SerDes2 is not enabled */
+ break;
+ case 0x01:
+ case 0x02:
+ /* SD2(A:H) => SLOT4 PCIe1 */
+ QIXIS_WRITE(brdcfg[13], 0x10);
+ break;
+ case 0x15:
+ case 0x16:
+ /*
+ * SD2(A:D) => SLOT4 PCIe1
+ * SD2(E:F) => SLOT5 PCIe2
+ * SD2(G:H) => SATA1,SATA2
+ */
+ QIXIS_WRITE(brdcfg[13], 0xb0);
+ break;
+ case 0x18:
+ /*
+ * SD2(A:D) => SLOT4 PCIe1
+ * SD2(E:F) => SLOT5 Aurora
+ * SD2(G:H) => SATA1,SATA2
+ */
+ QIXIS_WRITE(brdcfg[13], 0x78);
+ break;
+ case 0x1f:
+ /*
+ * SD2(A:D) => SLOT4 PCIe1
+ * SD2(E:H) => SLOT5 PCIe2
+ */
+ QIXIS_WRITE(brdcfg[13], 0xa0);
+ break;
+ case 0x29:
+ case 0x2d:
+ case 0x2e:
+ /*
+ * SD2(A:D) => SLOT4 SRIO2
+ * SD2(E:H) => SLOT5 SRIO1
+ */
+ QIXIS_WRITE(brdcfg[13], 0xa0);
+ break;
+ case 0x36:
+ /*
+ * SD2(A:D) => SLOT4 SRIO2
+ * SD2(E:F) => Aurora
+ * SD2(G:H) => SATA1,SATA2
+ */
+ QIXIS_WRITE(brdcfg[13], 0x78);
+ break;
+ default:
+ printf("WARNING: unsupported for SerDes2 Protocol %d\n",
+ srds_prtcl_s2);
+ return -1;
+ }
+#endif
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ /* Disable remote I2C connection to qixis fpga */
+ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
+
+ /*
+ * Adjust core voltage according to voltage ID
+ * This function changes I2C mux to channel 2.
+ */
+ if (adjust_vdd(0))
+ printf("Warning: Adjusting core voltage failed.\n");
+
+ brd_mux_lane_to_slot();
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+ /* use accurate clock measurement */
+ int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
+ int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+ u32 val;
+
+ val = freq * base;
+ if (val) {
+ debug("SYS Clock measurement is: %d\n", val);
+ return val;
+ } else {
+ printf("Warning: SYS clock measurement is invalid, ");
+ printf("using value from brdcfg1.\n");
+ }
+#endif
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+ /* use accurate clock measurement */
+ int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
+ int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+ u32 val;
+
+ val = freq * base;
+ if (val) {
+ debug("DDR Clock measurement is: %d\n", val);
+ return val;
+ } else {
+ printf("Warning: DDR clock measurement is invalid, ");
+ printf("using value from brdcfg1.\n");
+ }
+#endif
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
diff --git a/board/freescale/t208xqds/t208xqds.h b/board/freescale/t208xqds/t208xqds.h
new file mode 100644
index 0000000..39fcef2
--- /dev/null
+++ b/board/freescale/t208xqds/t208xqds.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t208xqds/t208xqds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h
new file mode 100644
index 0000000..bdcdc12
--- /dev/null
+++ b/board/freescale/t208xqds/t208xqds_qixis.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T208xQDS_QIXIS_H__
+#define __T208xQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T208xQDS */
+
+#define QIXIS_SRDS1CLK_122 0x5a
+#define QIXIS_SRDS1CLK_125 0x5e
+
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xE0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
+
+#define BRDCFG9_SFP_TX_EN 0x10
+
+#define BRDCFG12_SD3EN_MASK 0x20
+#define BRDCFG12_SD3MX_MASK 0x08
+#define BRDCFG12_SD3MX_SLOT5 0x08
+#define BRDCFG12_SD3MX_SLOT6 0x00
+#define BRDCFG12_SD4EN_MASK 0x04
+#define BRDCFG12_SD4MX_MASK 0x03
+#define BRDCFG12_SD4MX_SLOT7 0x02
+#define BRDCFG12_SD4MX_SLOT8 0x01
+#define BRDCFG12_SD4MX_AURO_SATA 0x00
+#endif
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
new file mode 100644
index 0000000..8d60298
--- /dev/null
+++ b/board/freescale/t208xqds/tlb.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2008-2013 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+ * space is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* *I*G* - PCIe 1, 0x80000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_512M, 1),
+
+ /* *I*G* - PCIe 2, 0xa0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCIe 3, 0xb0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+
+ /* *I*G* - PCIe 4, 0xc0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef QIXIS_BASE_PHYS
+ SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+ * fetching ucode and ENV from master
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig
new file mode 100644
index 0000000..845af3d
--- /dev/null
+++ b/board/freescale/t208xrdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_T208XRDB
+
+config SYS_BOARD
+ default "t208xrdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "T208xRDB"
+
+endif
diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS
new file mode 100644
index 0000000..1642879
--- /dev/null
+++ b/board/freescale/t208xrdb/MAINTAINERS
@@ -0,0 +1,15 @@
+T208XRDB BOARD
+#M: -
+S: Maintained
+F: board/freescale/t208xrdb/
+F: include/configs/T208xRDB.h
+F: configs/T2080RDB_defconfig
+F: configs/T2080RDB_NAND_defconfig
+F: configs/T2080RDB_SDCARD_defconfig
+F: configs/T2080RDB_SPIFLASH_defconfig
+F: configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+
+T2080RDB_SECURE_BOOT BOARD
+M: Aneesh Bansal <aneesh.bansal@freescale.com>
+S: Maintained
+F: configs/T2080RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile
new file mode 100644
index 0000000..9605f8b
--- /dev/null
+++ b/board/freescale/t208xrdb/Makefile
@@ -0,0 +1,18 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-$(CONFIG_T2080RDB) += t208xrdb.o
+obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
+obj-$(CONFIG_T2080RDB) += cpld.o
+obj-$(CONFIG_PCI) += pci.o
+endif
+
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README
new file mode 100644
index 0000000..24484cd
--- /dev/null
+++ b/board/freescale/t208xrdb/README
@@ -0,0 +1,264 @@
+T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
+It can work in two mode: standalone mode and PCIe endpoint mode.
+
+T2080 SoC Overview
+------------------
+The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
+Architecture processor cores with high-performance datapath acceleration
+logic and network and peripheral bus interfaces required for networking,
+telecom/datacom, wireless infrastructure, and mil/aerospace applications.
+
+T2080 includes the following functions and features:
+ - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
+ - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
+ - Hierarchical interconnect fabric
+ - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ - 16 SerDes lanes up to 10.3125 GHz
+ - 8 Ethernet interfaces, supporting combinations of the following:
+ - Up to four 10 Gbps Ethernet MACs
+ - Up to eight 1 Gbps Ethernet MACs
+ - Up to four 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+ - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
+ - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
+ - Additional peripheral interfaces
+ - Two serial ATA (SATA 2.0) controllers
+ - Two high-speed USB 2.0 controllers with integrated PHY
+ - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
+ - Enhanced serial peripheral interface (eSPI)
+ - Four I2C controllers
+ - Four 2-pin UARTs or two 4-pin UARTs
+ - Integrated Flash Controller supporting NAND and NOR flash
+ - Three eight-channel DMA engines
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ Platform's Trust Architecture 2.0
+
+Differences between T2080 and T2081
+-----------------------------------
+ Feature T2080 T2081
+ 1G Ethernet numbers: 8 6
+ 10G Ethernet numbers: 4 2
+ SerDes lanes: 16 8
+ Serial RapidIO,RMan: 2 no
+ SATA Controller: 2 no
+ Aurora: yes no
+ SoC Package: 896-pins 780-pins
+
+
+T2080PCIe-RDB board Overview
+----------------------------
+ - SERDES Configuration
+ - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
+ - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
+ - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
+ - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
+ - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
+ - SerDes-2 Lane G-H: to SATA1 & SATA2
+ - Ethernet
+ - Two on-board 10M/100M/1G RGMII ethernet ports
+ - Two on-board 10Gbps XFI fiber ports
+ - Two on-board 10Gbps Base-T copper ports
+ - DDR Memory
+ - Supports 72bit 4GB DDR3-LP SODIMM
+ - PCIe
+ - One PCIe x4 gold-finger
+ - One PCIe x4 connector
+ - One PCIe x2 end-point device (C293 Crypto co-processor)
+ - IFC/Local Bus
+ - NOR: 128MB 16-bit NOR Flash
+ - NAND: 1GB 8-bit NAND flash
+ - CPLD: for system controlling with programable header on-board
+ - SATA
+ - Two SATA 2.0 onnectors on-board
+ - USB
+ - Supports two USB 2.0 ports with integrated PHYs
+ - Two type A ports with 5V@1.5A per port.
+ - SDHC
+ - one TF-card connector on-board
+ - SPI
+ - On-board 64MB SPI flash
+ - Other
+ - Two Serial ports
+ - Four I2C ports
+
+
+System Memory map
+-----------------
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
+0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
+0x0_0000_0000 0x0_ffff_ffff DDR 4GB
+
+
+128M NOR Flash memory Map
+-------------------------
+Start Address End Address Definition Max size
+0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
+0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
+0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
+0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB
+0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
+0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
+0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
+0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB
+0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+T2080PCIe-RDB Ethernet Port Map
+-------------------------------
+Label In Uboot In Linux FMan Address Comments PHY
+ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315)
+ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315)
+ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202)
+ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202)
+ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E)
+ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E)
+
+
+T2080PCIe-RDB Default DIP-Switch setting
+----------------------------------------
+SW1[1:8] = '00010011'
+SW2[1:8] = '10111111'
+SW3[1:8] = '11100001'
+
+Software configurations and board settings
+------------------------------------------
+1. NOR boot:
+ a. build NOR boot image
+ $ make T2080RDB_config
+ $ make
+ b. program u-boot.bin image to NOR flash
+ => tftp 1000000 u-boot.bin
+ => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
+ set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+
+ Switching between default bank and alternate bank on NOR flash
+ To change boot source to vbank4:
+ via software: run command 'cpld reset altbank' in u-boot.
+ via DIP-switch: set SW3[5:7] = '100'
+
+ To change boot source to vbank0:
+ via software: run command 'cpld reset' in u-boot.
+ via DIP-Switch: set SW3[5:7] = '000'
+
+2. NAND Boot:
+ a. build PBL image for NAND boot
+ $ make T2080RDB_NAND_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to NAND flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => nand erase 0 d0000
+ => nand write 1000000 0 $filesize
+ set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
+
+3. SPI Boot:
+ a. build PBL image for SPI boot
+ $ make T2080RDB_SPIFLASH_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to SPI flash
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => sf probe 0
+ => sf erase 0 d0000
+ => sf write 1000000 0 $filesize
+ set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
+
+4. SD Boot:
+ a. build PBL image for SD boot
+ $ make T2080RDB_SDCARD_config
+ $ make
+ b. program u-boot-with-spl-pbl.bin to micro-SD/TF card
+ => tftp 1000000 u-boot-with-spl-pbl.bin
+ => mmc write 1000000 8 0x800
+ set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (50KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T2080RDB
+--------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB (2 blocks)
+0x100000 0x17FFFF u-boot env 512KB (1 block)
+0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
+0x200000 0x27FFFF CS4315 ucode 512KB (1 block)
+
+
+Micro SD Card memory Map on T2080RDB
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 u-boot img 1MB
+0x800 0016 u-boot env 8KB
+0x820 0128 FMAN ucode 64KB
+0x8a0 0512 CS4315 ucode 256KB
+
+
+SPI Flash memory Map on T2080RDB
+----------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB
+0x100000 0x101FFF u-boot env 8KB
+0x110000 0x11FFFF FMAN ucode 64KB
+0x120000 0x15FFFF CS4315 ucode 256KB
+
+
+How to update the ucode of Cortina CS4315/CS4340 10G PHY
+--------------------------------------------------------
+=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt
+=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize
+
+
+How to update the ucode of Freescale FMAN
+-----------------------------------------
+=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin
+=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
+
+
+For more details, please refer to T2080PCIe-RDB User Guide and access
+website www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c
new file mode 100644
index 0000000..4aa126b
--- /dev/null
+++ b/board/freescale/t208xrdb/cpld.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Freescale T2080RDB board-specific CPLD controlling supports.
+ */
+
+#include <common.h>
+#include <command.h>
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+
+/* Set the boot bank to the alternate bank */
+void cpld_set_altbank(void)
+{
+ u8 reg = CPLD_READ(flash_csr);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
+ CPLD_WRITE(flash_csr, reg);
+ CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
+}
+
+/* Set the boot bank to the default bank */
+void cpld_set_defbank(void)
+{
+ u8 reg = CPLD_READ(flash_csr);
+
+ reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
+ CPLD_WRITE(flash_csr, reg);
+ CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
+}
+
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (strcmp(argv[2], "altbank") == 0)
+ cpld_set_altbank();
+ else
+ cpld_set_defbank();
+ } else {
+ rc = cmd_usage(cmdtp);
+ }
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+ "Reset the board or alternate bank",
+ "reset: reset to default bank\n"
+ "cpld reset altbank: reset to alternate bank\n"
+);
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h
new file mode 100644
index 0000000..3f15338
--- /dev/null
+++ b/board/freescale/t208xrdb/cpld.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * CPLD register set of T2080RDB board-specific.
+ */
+struct cpld_data {
+ u8 chip_id1; /* 0x00 - Chip ID1 register */
+ u8 chip_id2; /* 0x01 - Chip ID2 register */
+ u8 hw_ver; /* 0x02 - Hardware Revision Register */
+ u8 sw_ver; /* 0x03 - Software Revision register */
+ u8 res0[12]; /* 0x04 - 0x0F - not used */
+ u8 reset_ctl; /* 0x10 - Reset control Register */
+ u8 flash_csr; /* 0x11 - Flash control and status register */
+ u8 thermal_csr; /* 0x12 - Thermal control and status register */
+ u8 led_csr; /* 0x13 - LED control and status register */
+ u8 sfp_csr; /* 0x14 - SFP+ control and status register */
+ u8 misc_csr; /* 0x15 - Misc control and status register */
+ u8 boot_or; /* 0x16 - Boot config override register */
+ u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */
+ u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */
+} cpld_data_t;
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value) \
+ cpld_write(offsetof(struct cpld_data, reg), value)
+
+/* CPLD on IFC */
+#define CPLD_LBMAP_MASK 0x3F
+#define CPLD_BANK_SEL_MASK 0x07
+#define CPLD_BANK_OVERRIDE 0x40
+#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
+#define CPLD_LBMAP_RESET 0xFF
+#define CPLD_LBMAP_SHIFT 0x03
+#define CPLD_BOOT_SEL 0x80
diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c
new file mode 100644
index 0000000..8a26276
--- /dev/null
+++ b/board/freescale/t208xrdb/ddr.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+ puts("Initializing....using SPD\n");
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+#else
+ /* DDR has been initialised by first stage boot loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
+ return dram_size;
+}
diff --git a/board/freescale/t208xrdb/ddr.h b/board/freescale/t208xrdb/ddr.h
new file mode 100644
index 0000000..b6d4062
--- /dev/null
+++ b/board/freescale/t208xrdb/ddr.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ */
+ {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
+ {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
+ {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
+ {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
+ {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+#endif
diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c
new file mode 100644
index 0000000..cbbc625
--- /dev/null
+++ b/board/freescale/t208xrdb/eth_t208xrdb.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ struct mii_dev *dev;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+ switch (srds_s1) {
+ case 0x66:
+ case 0x6b:
+ fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
+ fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
+ fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
+ break;
+ default:
+ printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
+ srds_s1);
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ return;
+}
diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c
new file mode 100644
index 0000000..eb82431
--- /dev/null
+++ b/board/freescale/t208xrdb/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c
new file mode 100644
index 0000000..ba7041a
--- /dev/null
+++ b/board/freescale/t208xrdb/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2007-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
new file mode 100644
index 0000000..9ae2b1e
--- /dev/null
+++ b/board/freescale/t208xrdb/spl.c
@@ -0,0 +1,107 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ puts("\nNAND boot...\n");
+#endif
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/t208xrdb/t2080_pbi.cfg b/board/freescale/t208xrdb/t2080_pbi.cfg
new file mode 100644
index 0000000..e200d92
--- /dev/null
+++ b/board/freescale/t208xrdb/t2080_pbi.cfg
@@ -0,0 +1,41 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg
new file mode 100644
index 0000000..59025ea
--- /dev/null
+++ b/board/freescale/t208xrdb/t2080_rcw.cfg
@@ -0,0 +1,16 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
+#120c0017 15000000 00000000 00000000
+#66150002 00008400 ec104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
+1206001b 15000000 00000000 00000000
+66150002 00000000 e8104000 c1000000
+00800000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
new file mode 100644
index 0000000..341453b
--- /dev/null
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include "t208xrdb.h"
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+ static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
+
+ printf("Board: %sRDB, ", cpu->name);
+ printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
+ CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+
+#ifdef CONFIG_SDCARD
+ puts("SD/MMC\n");
+#elif CONFIG_SPIFLASH
+ puts("SPI\n");
+#else
+ u8 reg;
+
+ reg = CPLD_READ(flash_csr);
+
+ if (reg & CPLD_BOOT_SEL) {
+ puts("NAND\n");
+ } else {
+ reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
+ printf("NOR vBank%d\n", reg);
+ }
+#endif
+
+ puts("SERDES Reference Clocks:\n");
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+ printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
diff --git a/board/freescale/t208xrdb/t208xrdb.h b/board/freescale/t208xrdb/t208xrdb.h
new file mode 100644
index 0000000..13380d0
--- /dev/null
+++ b/board/freescale/t208xrdb/t208xrdb.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
new file mode 100644
index 0000000..2ebea36
--- /dev/null
+++ b/board/freescale/t208xrdb/tlb.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+ * space is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+ /* *I*G* - PCIe 1, 0x80000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_512M, 1),
+
+ /* *I*G* - PCIe 2, 0xa0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCIe 3, 0xb0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+
+ /* *I*G* - PCIe 4, 0xc0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+ * fetching ucode and ENV from master
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t4qds/Kconfig b/board/freescale/t4qds/Kconfig
new file mode 100644
index 0000000..ab34b9e
--- /dev/null
+++ b/board/freescale/t4qds/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_T4240EMU
+
+config SYS_BOARD
+ default "t4qds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "T4240EMU"
+
+endif
+
+if TARGET_T4240QDS
+
+config SYS_BOARD
+ default "t4qds"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "T4240QDS"
+
+endif
diff --git a/board/freescale/t4qds/MAINTAINERS b/board/freescale/t4qds/MAINTAINERS
new file mode 100644
index 0000000..f88ee7d
--- /dev/null
+++ b/board/freescale/t4qds/MAINTAINERS
@@ -0,0 +1,26 @@
+T4QDS BOARD
+#M: -
+S: Maintained
+F: board/freescale/t4qds/
+F: include/configs/T4240QDS.h
+F: configs/T4160QDS_defconfig
+F: configs/T4160QDS_NAND_defconfig
+F: configs/T4160QDS_SDCARD_defconfig
+F: configs/T4160QDS_SPIFLASH_defconfig
+F: configs/T4240QDS_defconfig
+F: configs/T4240QDS_NAND_defconfig
+F: configs/T4240QDS_SDCARD_defconfig
+F: configs/T4240QDS_SPIFLASH_defconfig
+F: configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
+
+T4160QDS_SECURE_BOOT BOARD
+M: Aneesh Bansal <aneesh.bansal@freescale.com>
+S: Maintained
+F: configs/T4160QDS_SECURE_BOOT_defconfig
+F: configs/T4240QDS_SECURE_BOOT_defconfig
+
+T4240EMU BOARD
+M: York Sun <yorksun@freescale.com>
+S: Maintained
+F: include/configs/T4240EMU.h
+F: configs/T4240EMU_defconfig
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
new file mode 100644
index 0000000..4e8e5cb
--- /dev/null
+++ b/board/freescale/t4qds/Makefile
@@ -0,0 +1,17 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-$(CONFIG_T4240QDS) += t4240qds.o
+obj-$(CONFIG_T4240EMU) += t4240emu.o
+obj-$(CONFIG_T4240QDS)+= eth.o
+obj-$(CONFIG_PCI) += pci.o
+endif
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t4qds/README b/board/freescale/t4qds/README
new file mode 100644
index 0000000..3962fee
--- /dev/null
+++ b/board/freescale/t4qds/README
@@ -0,0 +1,194 @@
+Overview
+--------
+The T4240QDS is a high-performance computing evaluation, development and test
+platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is
+optimized to support the high-bandwidth DDR3 memory ports, as well as the
+highly-configurable SerDes ports. The system is lead-free and RoHS-compliant.
+
+Board Features
+ SERDES Connections
+ 32 lanes grouped into four 8-lane banks
+ Two “front side” banks dedicated to Ethernet
+ - High-speed crosspoint switch fabric on selected lanes
+ - Two PCI Express slots with side-band connector supporting
+ - SGMII
+ - XAUI
+ - HiGig
+ - I-pass connectors allow board-to-board and loopback support
+ Two “back side” banks dedicated to other protocols
+ - High-speed crosspoint switch fabric on all lanes
+ - Four PCI Express slots with side-band connector supporting
+ - PCI Express 3.0
+ - SATA 2.0
+ - SRIO 2.0
+ - Supports 4X Aurora debug with two connectors
+ DDR Controllers
+ Three independant 64-bit DDR3 controllers
+ Supports rates of 1866 up to 2133 MHz data-rate
+ Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
+ DDR power supplies 1.5V to all devices with automatic tracking of VTT.
+ Power software-switchable to 1.35V if software detects all DDR3LP devices.
+ MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and
+ 2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time
+ increases by 1 clock.
+
+ IFC/Local Bus
+ NAND flash: 8-bit, async or sync, up to 2GB.
+ NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB
+ NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
+ - NOR devices support 16 virtual banks
+ GASIC: Minimal target within Qixis FPGA
+ PromJET rapid memory download support
+ Address demultiplexing handled within FPGA.
+ - Flexible demux allows 8 or 16 bit evaluation.
+ IFC Debug/Development card
+ - Support for 32-bit devices
+ Ethernet
+ Support two on-board RGMII 10/100/1G ethernet ports.
+ SGMII and XAUI support via SERDES block (see above).
+ 1588 support via Symmetricom board.
+ QIXIS System Logic FPGA
+ Manages system power and reset sequencing
+ Manages DUT, board, clock, etc. configuration for dynamic shmoo
+ Collects V-I-T data in background for code/power profiling.
+ Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion)
+ General fault monitoring and logging
+ Runs from ATX “hot” power rails allowing operation while system is off.
+ Clocks
+ System and DDR clock (SYSCLK, “DDRCLK”)
+ - Switch selectable to one of 16 common settings in the interval 33MHz-166MHz.
+ - Software selectable in 1MHz increments from 1-200MHz.
+ SERDES clocks
+ - Provides clocks to all SerDes blocks and slots
+ - 100, 125 and 156.25 MHz
+ Power Supplies
+ Dedicated regulators for VDD
+ - Adjustable from (0.7V to 1.3V at 80A
+ - Regulators can be controlled by VID and/or software
+ Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A
+ - VTT/MVREF automatically track operating voltage
+ Dedicated regulators/filters for AVDD supplies
+ Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc.
+ USB
+ Supports two USB 2.0 ports with integrated PHYs
+ - One type A, one type micro-AB with 1.0A power per port.
+ Other IO
+ eSDHC/MMC
+ - SDHC card slot
+ eSPI port
+ - High-speed serial flash
+ Two Serial port
+ Four I2C ports
+ XFI
+ XFI is supported on T4QDS-XFI board which removed slot3 and routed
+ four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or
+ direct attach cable(copper), the copper cable is used to emulate
+ 10GBASE-KR scenario.
+ So, for XFI usage, there are two scenarios, one will use fiber cable,
+ another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
+ introduced to indicate a XFI port will use copper cable, and U-boot
+ will fixup the dtb accordingly.
+ It's used as: fsl_10gkr_copper:<10g_mac_name>
+ The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they
+ do not have to be coexist in hwconfig. If a MAC is listed in the env
+ "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
+ will be used by default.
+ for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2" in
+ hwconfig, then both four XFI ports will use copper cable.
+ set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
+ XFI ports will use copper cable, the other two XFI ports will use fiber
+ cable.
+
+Memory map
+----------
+The addresses in brackets are physical addresses.
+
+0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB)
+0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory
+0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers)
+0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan
+0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan
+0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
+0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash
+0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR
+0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS
+0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores
+
+The physical address of the last (boot page translation) varies with the actual DDR size.
+
+Voltage ID and VDD override
+--------------------
+T4240 has a VID feature. U-boot reads the VID efuses and adjust the voltage
+accordingly. The voltage can also be override by command vdd_override. The
+syntax is
+
+vdd_override <voltage in mV>, eg. 1050 is for 1.050v.
+
+Upon success, the actual voltage will be read back. The value is checked
+for safety and any invalid value will not adjust the voltage.
+
+Another way to override VDD is to use environmental variable, in case of using
+command is too late for some debugging. The syntax is
+
+setenv t4240qds_vdd_mv <voltage in mV>
+saveenv
+reset
+
+The override voltage takes effect when booting.
+
+Note: voltage adjustment needs to be done step by step. Changing voltage too
+rapidly may cause current surge. The voltage stepping is done by software.
+Users can set the final voltage directly.
+
+2-stage NAND/SD boot loader
+-------------------------------
+PBL initializes the internal SRAM and copy SPL(160K) in SRAM.
+SPL further initialise DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (50KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T4QDS
+--------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB
+0x140000 0x15FFFF u-boot env 128KB
+0x160000 0x17FFFF FMAN Ucode 128KB
+
+Micro SD Card memory Map on T4QDS
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 u-boot img 1MB
+0x800 0016 u-boot env 8KB
+0x820 0128 FMAN ucode 64KB
+
+Switch Settings: (ON is 1, OFF is 0)
+===============
+NAND boot SW setting:
+SW1[1:8] = 10000010
+SW2[1.1] = 0
+SW6[1:4] = 1001
+
+SD boot SW setting:
+SW1[1:8] = 00100000
+SW2[1.1] = 0
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
new file mode 100644
index 0000000..7abd38d
--- /dev/null
+++ b/board/freescale/t4qds/ddr.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[0];
+ else
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twot_en = pbsp->force_2t;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twot_en = pbsp_highest->force_2t;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+#else
+ /* DDR has been initialised by first stage boot loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
+ return dram_size;
+}
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
new file mode 100644
index 0000000..8183af7
--- /dev/null
+++ b/board/freescale/t4qds/ddr.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+#ifdef CONFIG_T4240QDS
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
+ {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
+ {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
+ {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
+ {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
+ {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
+ {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {}
+};
+
+#else /* CONFIG_T4240EMU */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {2, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
+ {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {4, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0},
+ {2, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0},
+ {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
+ {}
+};
+#endif /* CONFIG_T4240EMU */
+
+/*
+ * The three slots have slightly different timing. The center values are good
+ * for all slots. We use identical speed tables for them. In future use, if
+ * DIMMs require separated tables, make more entries as needed.
+ */
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+/*
+ * The three slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+};
+
+
+#endif
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
new file mode 100644
index 0000000..9b416b1
--- /dev/null
+++ b/board/freescale/t4qds/eth.c
@@ -0,0 +1,866 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include <hwconfig.h>
+#include "../common/qixis.h"
+#include "../common/fman.h"
+
+#include "t4240qds_qixis.h"
+
+#define EMI_NONE 0xFFFFFFFF
+#define EMI1_RGMII 0
+#define EMI1_SLOT1 1
+#define EMI1_SLOT2 2
+#define EMI1_SLOT3 3
+#define EMI1_SLOT4 4
+#define EMI1_SLOT5 5
+#define EMI1_SLOT7 7
+#define EMI2 8
+/* Slot6 and Slot8 do not have EMI connections */
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char *mdio_names[] = {
+ "T4240QDS_MDIO0",
+ "T4240QDS_MDIO1",
+ "T4240QDS_MDIO2",
+ "T4240QDS_MDIO3",
+ "T4240QDS_MDIO4",
+ "T4240QDS_MDIO5",
+ "NULL",
+ "T4240QDS_MDIO7",
+ "T4240QDS_10GC",
+};
+
+static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
+static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
+static u8 slot_qsgmii_phyaddr[5][4] = {
+ {0, 0, 0, 0},/* not used, to make index match slot No. */
+ {0, 1, 2, 3},
+ {4, 5, 6, 7},
+ {8, 9, 0xa, 0xb},
+ {0xc, 0xd, 0xe, 0xf},
+};
+static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
+
+static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name = t4240qds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+struct t4240qds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void t4240qds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+ if ((muxval < 6) || (muxval == 7)) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct t4240qds_mdio *priv = bus->priv;
+
+ t4240qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct t4240qds_mdio *priv = bus->priv;
+
+ t4240qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t4240qds_mdio_reset(struct mii_dev *bus)
+{
+ struct t4240qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int t4240qds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct t4240qds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate T4240QDS MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate T4240QDS private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = t4240qds_mdio_read;
+ bus->write = t4240qds_mdio_write;
+ bus->reset = t4240qds_mdio_reset;
+ sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+
+ return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
+ enum fm_port port, int offset)
+{
+ int interface = fm_info_get_enet_if(port);
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+ prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ interface == PHY_INTERFACE_MODE_QSGMII) {
+ switch (port) {
+ case FM1_DTSEC1:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy21");
+ break;
+ case FM1_DTSEC2:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy22");
+ break;
+ case FM1_DTSEC3:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy23");
+ break;
+ case FM1_DTSEC4:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy24");
+ break;
+ case FM1_DTSEC6:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy12");
+ break;
+ case FM1_DTSEC9:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy14");
+ else
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_sgmii4");
+ break;
+ case FM1_DTSEC10:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy13");
+ else
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_sgmii3");
+ break;
+ case FM2_DTSEC1:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy41");
+ break;
+ case FM2_DTSEC2:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy42");
+ break;
+ case FM2_DTSEC3:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy43");
+ break;
+ case FM2_DTSEC4:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy44");
+ break;
+ case FM2_DTSEC6:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy32");
+ break;
+ case FM2_DTSEC9:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy34");
+ else
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_sgmii12");
+ break;
+ case FM2_DTSEC10:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy33");
+ else
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_sgmii11");
+ break;
+ default:
+ break;
+ }
+ } else if (interface == PHY_INTERFACE_MODE_XGMII &&
+ ((prtcl2 == 55) || (prtcl2 == 57))) {
+ /*
+ * if the 10G is XFI, check hwconfig to see what is the
+ * media type, there are two types, fiber or copper,
+ * fix the dtb accordingly.
+ */
+ int media_type = 0;
+ struct fixed_link f_link;
+ char lane_mode[20] = {"10GBASE-KR"};
+ char buf[32] = "serdes-2,";
+ int off;
+
+ switch (port) {
+ case FM1_10GEC1:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
+ media_type = 1;
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_xfi1");
+ sprintf(buf, "%s%s%s", buf, "lane-a,",
+ (char *)lane_mode);
+ }
+ break;
+ case FM1_10GEC2:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
+ media_type = 1;
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_xfi2");
+ sprintf(buf, "%s%s%s", buf, "lane-b,",
+ (char *)lane_mode);
+ }
+ break;
+ case FM2_10GEC1:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
+ media_type = 1;
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_xfi3");
+ sprintf(buf, "%s%s%s", buf, "lane-d,",
+ (char *)lane_mode);
+ }
+ break;
+ case FM2_10GEC2:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
+ media_type = 1;
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_xfi4");
+ sprintf(buf, "%s%s%s", buf, "lane-c,",
+ (char *)lane_mode);
+ }
+ break;
+ default:
+ return;
+ }
+
+ if (!media_type) {
+ /* fixed-link is used for XFI fiber cable */
+ fdt_delprop(blob, offset, "phy-handle");
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ fdt_setprop(blob, offset, "fixed-link", &f_link,
+ sizeof(f_link));
+ } else {
+ /* set property for copper cable */
+ off = fdt_node_offset_by_compat_reg(blob,
+ "fsl,fman-memac-mdio", pa + 0x1000);
+ fdt_setprop_string(blob, off, "lane-instance", buf);
+ }
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int i;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+ prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
+ switch (mdio_mux[i]) {
+ case EMI1_SLOT1:
+ fdt_status_okay_by_alias(fdt, "emi1_slot1");
+ break;
+ case EMI1_SLOT2:
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ break;
+ case EMI1_SLOT3:
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ break;
+ case EMI1_SLOT4:
+ fdt_status_okay_by_alias(fdt, "emi1_slot4");
+ break;
+ default:
+ break;
+ }
+ break;
+ case PHY_INTERFACE_MODE_XGMII:
+ /* check if it's XFI interface for 10g */
+ if ((prtcl2 == 55) || (prtcl2 == 57)) {
+ if (i == FM1_10GEC1 && hwconfig_sub(
+ "fsl_10gkr_copper", "fm1_10g1"))
+ fdt_status_okay_by_alias(
+ fdt, "xfi_pcs_mdio1");
+ if (i == FM1_10GEC2 && hwconfig_sub(
+ "fsl_10gkr_copper", "fm1_10g2"))
+ fdt_status_okay_by_alias(
+ fdt, "xfi_pcs_mdio2");
+ if (i == FM2_10GEC1 && hwconfig_sub(
+ "fsl_10gkr_copper", "fm2_10g1"))
+ fdt_status_okay_by_alias(
+ fdt, "xfi_pcs_mdio3");
+ if (i == FM2_10GEC2 && hwconfig_sub(
+ "fsl_10gkr_copper", "fm2_10g2"))
+ fdt_status_okay_by_alias(
+ fdt, "xfi_pcs_mdio4");
+ break;
+ }
+ switch (i) {
+ case FM1_10GEC1:
+ fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
+ break;
+ case FM1_10GEC2:
+ fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
+ break;
+ case FM2_10GEC1:
+ fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
+ break;
+ case FM2_10GEC2:
+ fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+static void initialize_qsgmiiphy_fix(void)
+{
+ int i;
+ unsigned short reg;
+
+ for (i = 1; i <= 4; i++) {
+ /*
+ * Try to read if a SGMII card is used, we do it slot by slot.
+ * if a SGMII PHY address is valid on a slot, then we mark
+ * all ports on the slot, then fix the PHY address for the
+ * marked port when doing dtb fixup.
+ */
+ if (miiphy_read(mdio_names[i],
+ SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) {
+ debug("Slot%d PHY ID register 2 read failed\n", i);
+ continue;
+ }
+
+ debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
+
+ if (reg == 0xFFFF) {
+ /* No physical device present at this address */
+ continue;
+ }
+
+ switch (i) {
+ case 1:
+ qsgmiiphy_fix[FM1_DTSEC5] = 1;
+ qsgmiiphy_fix[FM1_DTSEC6] = 1;
+ qsgmiiphy_fix[FM1_DTSEC9] = 1;
+ qsgmiiphy_fix[FM1_DTSEC10] = 1;
+ slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR;
+ slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR;
+ slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR;
+ slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR;
+ break;
+ case 2:
+ qsgmiiphy_fix[FM1_DTSEC1] = 1;
+ qsgmiiphy_fix[FM1_DTSEC2] = 1;
+ qsgmiiphy_fix[FM1_DTSEC3] = 1;
+ qsgmiiphy_fix[FM1_DTSEC4] = 1;
+ slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR;
+ slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR;
+ slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR;
+ slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR;
+ break;
+ case 3:
+ qsgmiiphy_fix[FM2_DTSEC5] = 1;
+ qsgmiiphy_fix[FM2_DTSEC6] = 1;
+ qsgmiiphy_fix[FM2_DTSEC9] = 1;
+ qsgmiiphy_fix[FM2_DTSEC10] = 1;
+ slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR;
+ slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR;
+ slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR;
+ slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR;
+ break;
+ case 4:
+ qsgmiiphy_fix[FM2_DTSEC1] = 1;
+ qsgmiiphy_fix[FM2_DTSEC2] = 1;
+ qsgmiiphy_fix[FM2_DTSEC3] = 1;
+ qsgmiiphy_fix[FM2_DTSEC4] = 1;
+ slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR;
+ slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR;
+ slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR;
+ slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR;
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, idx, lane, slot, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1, srds_prtcl_s2;
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Register the muxing front-ends to the MDIO buses */
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+ t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+ initialize_qsgmiiphy_fix();
+
+ switch (srds_prtcl_s1) {
+ case 1:
+ case 2:
+ case 4:
+ /* XAUI/HiGig in Slot1 and Slot2 */
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
+ break;
+ case 27:
+ case 28:
+ case 35:
+ case 36:
+ /* SGMII in Slot1 and Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+ fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+ fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+ fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
+ fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+ fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
+ if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
+ fm_info_set_phy_address(FM1_DTSEC9,
+ slot_qsgmii_phyaddr[1][3]);
+ fm_info_set_phy_address(FM1_DTSEC10,
+ slot_qsgmii_phyaddr[1][2]);
+ }
+ break;
+ case 37:
+ case 38:
+ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+ fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+ fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+ fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
+ fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+ fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
+ if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
+ fm_info_set_phy_address(FM1_DTSEC9,
+ slot_qsgmii_phyaddr[1][2]);
+ fm_info_set_phy_address(FM1_DTSEC10,
+ slot_qsgmii_phyaddr[1][3]);
+ }
+ break;
+ case 39:
+ case 40:
+ case 45:
+ case 46:
+ case 47:
+ case 48:
+ fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+ fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
+ if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
+ fm_info_set_phy_address(FM1_DTSEC10,
+ slot_qsgmii_phyaddr[1][2]);
+ fm_info_set_phy_address(FM1_DTSEC9,
+ slot_qsgmii_phyaddr[1][3]);
+ }
+ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+ fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+ fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+ fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
+ break;
+ default:
+ puts("Invalid SerDes1 protocol for T4240QDS\n");
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ idx = i - FM1_DTSEC1;
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
+ if (interface == PHY_INTERFACE_MODE_QSGMII) {
+ if (idx <= 3)
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ QSGMII_FM1_A);
+ else
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ QSGMII_FM1_B);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm1[lane];
+ debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
+ idx + 1, slot);
+ } else {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm1[lane];
+ debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ }
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+ switch (slot) {
+ case 1:
+ mdio_mux[i] = EMI1_SLOT1;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 2:
+ mdio_mux[i] = EMI1_SLOT2;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ };
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ /* FM1 DTSEC5 routes to RGMII with EC2 */
+ debug("FM1@DTSEC%u is RGMII at address %u\n",
+ idx + 1, 2);
+ if (i == FM1_DTSEC5)
+ fm_info_set_phy_address(i, 2);
+ mdio_mux[i] = EMI1_RGMII;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ idx = i - FM1_10GEC1;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
+ /* A fake PHY address to make U-boot happy */
+ fm_info_set_phy_address(i, i);
+ } else {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ XAUI_FM1_MAC9 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm1[lane];
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+ }
+ mdio_mux[i] = EMI2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ switch (srds_prtcl_s2) {
+ case 1:
+ case 2:
+ case 4:
+ /* XAUI/HiGig in Slot3 and Slot4 */
+ fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
+ break;
+ case 6:
+ case 7:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ case 21:
+ case 22:
+ case 23:
+ case 24:
+ case 25:
+ case 26:
+ /* XAUI/HiGig in Slot3, SGMII in Slot4 */
+ fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+ break;
+ case 27:
+ case 28:
+ case 35:
+ case 36:
+ /* SGMII in Slot3 and Slot4 */
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+ fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+ fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+ fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
+ break;
+ case 37:
+ case 38:
+ /* QSGMII in Slot3 and Slot4 */
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+ fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+ fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
+ fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
+ break;
+ case 39:
+ case 40:
+ case 45:
+ case 46:
+ case 47:
+ case 48:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+ fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+ fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+ fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
+ /* QSGMII in Slot4 */
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+ break;
+ case 49:
+ case 50:
+ case 51:
+ case 52:
+ case 53:
+ case 54:
+ fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+ break;
+ case 55:
+ case 57:
+ /* XFI in Slot3, SGMII in Slot4 */
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+ break;
+ default:
+ puts("Invalid SerDes2 protocol for T4240QDS\n");
+ break;
+ }
+
+ for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+ idx = i - FM2_DTSEC1;
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
+ if (interface == PHY_INTERFACE_MODE_QSGMII) {
+ if (idx <= 3)
+ lane = serdes_get_first_lane(FSL_SRDS_2,
+ QSGMII_FM2_A);
+ else
+ lane = serdes_get_first_lane(FSL_SRDS_2,
+ QSGMII_FM2_B);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm2[lane];
+ debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
+ idx + 1, slot);
+ } else {
+ lane = serdes_get_first_lane(FSL_SRDS_2,
+ SGMII_FM2_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm2[lane];
+ debug("FM2@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ }
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+ switch (slot) {
+ case 3:
+ mdio_mux[i] = EMI1_SLOT3;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 4:
+ mdio_mux[i] = EMI1_SLOT4;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ };
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ /*
+ * If DTSEC5 is RGMII, then it's routed via via EC1 to
+ * the first on-board RGMII port. If DTSEC6 is RGMII,
+ * then it's routed via via EC2 to the second on-board
+ * RGMII port.
+ */
+ debug("FM2@DTSEC%u is RGMII at address %u\n",
+ idx + 1, i == FM2_DTSEC5 ? 1 : 2);
+ fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
+ mdio_mux[i] = EMI1_RGMII;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+ idx = i - FM2_10GEC1;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
+ /* A fake PHY address to make U-boot happy */
+ fm_info_set_phy_address(i, i);
+ } else {
+ lane = serdes_get_first_lane(FSL_SRDS_2,
+ XAUI_FM2_MAC9 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm2[lane];
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+ }
+ mdio_mux[i] = EMI2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+#endif /* CONFIG_SYS_NUM_FMAN */
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c
new file mode 100644
index 0000000..367783b
--- /dev/null
+++ b/board/freescale/t4qds/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef QIXIS_BASE_PHYS
+ SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t4qds/pci.c b/board/freescale/t4qds/pci.c
new file mode 100644
index 0000000..08d74b4
--- /dev/null
+++ b/board/freescale/t4qds/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
new file mode 100644
index 0000000..0c6156e
--- /dev/null
+++ b/board/freescale/t4qds/spl.c
@@ -0,0 +1,141 @@
+/* Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/spl.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include "../common/qixis.h"
+#include "t4240qds_qixis.h"
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, ccb_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#ifdef CONFIG_SPL_NAND_BOOT
+ u32 porsr1, pinctl;
+#endif
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ porsr1 = in_be32(&gur->porsr1);
+ pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
+ out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
+#endif
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("" : : : "memory");
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ ccb_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ puts("\nNAND boot...\n");
+#endif
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c
new file mode 100644
index 0000000..5441094
--- /dev/null
+++ b/board/freescale/t4qds/t4240emu.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ printf("Board: %sEMU\n", cpu->name);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+ return 0;
+}
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
new file mode 100644
index 0000000..4f2cccd
--- /dev/null
+++ b/board/freescale/t4qds/t4240qds.c
@@ -0,0 +1,894 @@
+/*
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "t4qds.h"
+#include "t4240qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+ {8, 8}, {9, 9}, {14, 14}, {15, 15} };
+
+static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+ {10, 10}, {11, 11}, {12, 12}, {13, 13} };
+
+static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+ {10, 11}, {11, 10}, {12, 2}, {13, 3} };
+
+static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+ {8, 9}, {9, 8}, {14, 1}, {15, 0} };
+
+int checkboard(void)
+{
+ char buf[64];
+ u8 sw;
+ struct cpu_type *cpu = gd->arch.cpu;
+ unsigned int i;
+
+ printf("Board: %sQDS, ", cpu->name);
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
+ QIXIS_READ(id), QIXIS_READ(arch));
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw == 0x8)
+ puts("Promjet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
+ /*
+ * Display the actual SERDES reference clocks as configured by the
+ * dip switches on the board. Note that the SWx registers could
+ * technically be set to force the reference clocks to match the
+ * values that the SERDES expects (or vice versa). For now, however,
+ * we just display both values and hope the user notices when they
+ * don't match.
+ */
+ puts("SERDES Reference Clocks: ");
+ sw = QIXIS_READ(brdcfg[2]);
+ for (i = 0; i < MAX_SERDES; i++) {
+ static const char * const freq[] = {
+ "100", "125", "156.25", "161.1328125"};
+ unsigned int clock = (sw >> (6 - 2 * i)) & 3;
+
+ printf("SERDES%u=%sMHz ", i+1, freq[clock]);
+ }
+ puts("\n");
+
+ return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for 532us befor another reading
+ */
+#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
+#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
+
+static inline int read_voltage(void)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+
+ for (i = 0; i < NUM_READINGS; i++) {
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
+ if (ret) {
+ printf("VID: failed to read core voltage\n");
+ return ret;
+ }
+ if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+ /* LSB = 4mv */
+ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ return voltage_read;
+}
+
+/*
+ * We need to calculate how long before the voltage starts to drop or increase
+ * It returns with the loop count. Each loop takes several readings (532us)
+ */
+static inline int wait_for_voltage_change(int vdd_last)
+{
+ int timeout, vdd_current;
+
+ vdd_current = read_voltage();
+ /* wait until voltage starts to drop */
+ for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
+ timeout < 100; timeout++) {
+ vdd_current = read_voltage();
+ }
+ if (timeout >= 100) {
+ printf("VID: Voltage adjustment timeout\n");
+ return -1;
+ }
+ return timeout;
+}
+
+/*
+ * argument 'wait' is the time we know the voltage difference can be measured
+ * this function keeps reading the voltage until it is stable
+ */
+static inline int wait_for_voltage_stable(int wait)
+{
+ int timeout, vdd_current, vdd_last;
+
+ vdd_last = read_voltage();
+ udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
+ /* wait until voltage is stable */
+ vdd_current = read_voltage();
+ for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
+ timeout < 100; timeout++) {
+ vdd_last = vdd_current;
+ udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
+ vdd_current = read_voltage();
+ }
+ if (timeout >= 100) {
+ printf("VID: Voltage adjustment timeout\n");
+ return -1;
+ }
+
+ return vdd_current;
+}
+
+static inline int set_voltage(u8 vid)
+{
+ int wait, vdd_last;
+
+ vdd_last = read_voltage();
+ QIXIS_WRITE(brdcfg[6], vid);
+ wait = wait_for_voltage_change(vdd_last);
+ if (wait < 0)
+ return -1;
+ debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
+ wait = wait ? wait : 1;
+
+ vdd_last = wait_for_voltage_stable(wait);
+ if (vdd_last < 0)
+ return -1;
+ debug("VID: Current voltage is %d mV\n", vdd_last);
+
+ return vdd_last;
+}
+
+
+static int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid, vid_current;
+ int vdd_target, vdd_current, vdd_last;
+ int ret;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.9875V */
+ 9750,
+ 9625,
+ 9500,
+ 9375,
+ 9250,
+ 9125,
+ 9000,
+ 8875,
+ 8750,
+ 8625,
+ 8500,
+ 8375,
+ 8250,
+ 8125,
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ debug("VID: I2c failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_be32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_VID_MASK;
+ if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+ }
+ vdd_target = vdd[vid];
+
+ /* check override variable for overriding VDD */
+ vdd_string = getenv("t4240qds_vdd_mv");
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+ if (vdd_override >= 819 && vdd_override <= 1212) {
+ vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+ debug("VDD override is %lu\n", vdd_override);
+ } else if (vdd_override != 0) {
+ printf("Invalid value.\n");
+ }
+
+ if (vdd_target == 0) {
+ debug("VID: VID not used\n");
+ ret = 0;
+ goto exit;
+ } else {
+ /* round up and divice by 10 to get a value in mV */
+ vdd_target = DIV_ROUND_UP(vdd_target, 10);
+ debug("VID: vid = %d mV\n", vdd_target);
+ }
+
+ /*
+ * Check current board VID setting
+ * Voltage regulator support output to 6.250mv step
+ * The highes voltage allowed for this board is (vid=0x40) 1.21250V
+ * the lowest is (vid=0x7f) 0.81875V
+ */
+ vid_current = QIXIS_READ(brdcfg[6]);
+ vdd_current = 121250 - (vid_current - 0x40) * 625;
+ debug("VID: Current vid setting is (0x%x) %d mV\n",
+ vid_current, vdd_current/100);
+
+ /*
+ * Read voltage monitor to check real voltage.
+ * Voltage monitor LSB is 4mv.
+ */
+ vdd_last = read_voltage();
+ if (vdd_last < 0) {
+ printf("VID: Could not read voltage sensor abort VID adjustment\n");
+ ret = -1;
+ goto exit;
+ }
+ debug("VID: Core voltage is at %d mV\n", vdd_last);
+ /*
+ * Adjust voltage to at or 8mV above target.
+ * Each step of adjustment is 6.25mV.
+ * Stepping down too fast may cause over current.
+ */
+ while (vdd_last > 0 && vid_current < 0x80 &&
+ vdd_last > (vdd_target + 8)) {
+ vid_current++;
+ vdd_last = set_voltage(vid_current);
+ }
+ /*
+ * Check if we need to step up
+ * This happens when board voltage switch was set too low
+ */
+ while (vdd_last > 0 && vid_current >= 0x40 &&
+ vdd_last < vdd_target + 2) {
+ vid_current--;
+ vdd_last = set_voltage(vid_current);
+ }
+ if (vdd_last > 0)
+ printf("VID: Core voltage %d mV\n", vdd_last);
+ else
+ ret = -1;
+
+exit:
+ if (re_enable)
+ enable_interrupts();
+ return ret;
+}
+
+/* Configure Crossbar switches for Front-Side SerDes Ports */
+int config_frontside_crossbar_vsc3316(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1, srds_prtcl_s2;
+ int ret;
+
+ ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
+ if (ret)
+ return ret;
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ switch (srds_prtcl_s1) {
+ case 37:
+ case 38:
+ /* swap first lane and third lane on slot1 */
+ vsc3316_fsm1_tx[0][1] = 14;
+ vsc3316_fsm1_tx[6][1] = 0;
+ vsc3316_fsm1_rx[1][1] = 2;
+ vsc3316_fsm1_rx[6][1] = 13;
+ case 39:
+ case 40:
+ case 45:
+ case 46:
+ case 47:
+ case 48:
+ /* swap first lane and third lane on slot2 */
+ vsc3316_fsm1_tx[2][1] = 8;
+ vsc3316_fsm1_tx[4][1] = 6;
+ vsc3316_fsm1_rx[2][1] = 10;
+ vsc3316_fsm1_rx[5][1] = 5;
+ default:
+ ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
+ if (ret)
+ return ret;
+ break;
+ }
+
+ srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ switch (srds_prtcl_s2) {
+ case 37:
+ case 38:
+ /* swap first lane and third lane on slot3 */
+ vsc3316_fsm2_tx[2][1] = 11;
+ vsc3316_fsm2_tx[5][1] = 4;
+ vsc3316_fsm2_rx[2][1] = 9;
+ vsc3316_fsm2_rx[4][1] = 7;
+ case 39:
+ case 40:
+ case 45:
+ case 46:
+ case 47:
+ case 48:
+ case 49:
+ case 50:
+ case 51:
+ case 52:
+ case 53:
+ case 54:
+ /* swap first lane and third lane on slot4 */
+ vsc3316_fsm2_tx[6][1] = 3;
+ vsc3316_fsm2_tx[1][1] = 12;
+ vsc3316_fsm2_rx[0][1] = 1;
+ vsc3316_fsm2_rx[6][1] = 15;
+ default:
+ ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
+ if (ret)
+ return ret;
+ break;
+ }
+
+ return 0;
+}
+
+int config_backside_crossbar_mux(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s3, srds_prtcl_s4;
+ u8 brdcfg;
+
+ srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
+ srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
+ switch (srds_prtcl_s3) {
+ case 0:
+ /* SerDes3 is not enabled */
+ break;
+ case 1:
+ case 2:
+ case 9:
+ case 10:
+ /* SD3(0:7) => SLOT5(0:7) */
+ brdcfg = QIXIS_READ(brdcfg[12]);
+ brdcfg &= ~BRDCFG12_SD3MX_MASK;
+ brdcfg |= BRDCFG12_SD3MX_SLOT5;
+ QIXIS_WRITE(brdcfg[12], brdcfg);
+ break;
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ case 11:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 20:
+ /* SD3(4:7) => SLOT6(0:3) */
+ brdcfg = QIXIS_READ(brdcfg[12]);
+ brdcfg &= ~BRDCFG12_SD3MX_MASK;
+ brdcfg |= BRDCFG12_SD3MX_SLOT6;
+ QIXIS_WRITE(brdcfg[12], brdcfg);
+ break;
+ default:
+ printf("WARNING: unsupported for SerDes3 Protocol %d\n",
+ srds_prtcl_s3);
+ return -1;
+ }
+
+ srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
+ srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
+ switch (srds_prtcl_s4) {
+ case 0:
+ /* SerDes4 is not enabled */
+ break;
+ case 1:
+ case 2:
+ /* 10b, SD4(0:7) => SLOT7(0:7) */
+ brdcfg = QIXIS_READ(brdcfg[12]);
+ brdcfg &= ~BRDCFG12_SD4MX_MASK;
+ brdcfg |= BRDCFG12_SD4MX_SLOT7;
+ QIXIS_WRITE(brdcfg[12], brdcfg);
+ break;
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ /* x1b, SD4(4:7) => SLOT8(0:3) */
+ brdcfg = QIXIS_READ(brdcfg[12]);
+ brdcfg &= ~BRDCFG12_SD4MX_MASK;
+ brdcfg |= BRDCFG12_SD4MX_SLOT8;
+ QIXIS_WRITE(brdcfg[12], brdcfg);
+ break;
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ case 18:
+ /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
+ brdcfg = QIXIS_READ(brdcfg[12]);
+ brdcfg &= ~BRDCFG12_SD4MX_MASK;
+ brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
+ QIXIS_WRITE(brdcfg[12], brdcfg);
+ break;
+ default:
+ printf("WARNING: unsupported for SerDes4 Protocol %d\n",
+ srds_prtcl_s4);
+ return -1;
+ }
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ /* Disable remote I2C connection to qixis fpga */
+ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
+
+ /*
+ * Adjust core voltage according to voltage ID
+ * This function changes I2C mux to channel 2.
+ */
+ if (adjust_vdd(0))
+ printf("Warning: Adjusting core voltage failed.\n");
+
+ /* Configure board SERDES ports crossbar */
+ config_frontside_crossbar_vsc3316();
+ config_backside_crossbar_mux();
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+ /* use accurate clock measurement */
+ int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
+ int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+ u32 val;
+
+ val = freq * base;
+ if (val) {
+ debug("SYS Clock measurement is: %d\n", val);
+ return val;
+ } else {
+ printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
+ }
+#endif
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+ /* use accurate clock measurement */
+ int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
+ int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+ u32 val;
+
+ val = freq * base;
+ if (val) {
+ debug("DDR Clock measurement is: %d\n", val);
+ return val;
+ } else {
+ printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
+ }
+#endif
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+int misc_init_r(void)
+{
+ u8 sw;
+ void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ serdes_corenet_t *srds_regs;
+ u32 actual[MAX_SERDES];
+ u32 pllcr0, expected;
+ unsigned int i;
+
+ sw = QIXIS_READ(brdcfg[2]);
+ for (i = 0; i < MAX_SERDES; i++) {
+ unsigned int clock = (sw >> (6 - 2 * i)) & 3;
+ switch (clock) {
+ case 0:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+ break;
+ case 1:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+ break;
+ case 2:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
+ break;
+ case 3:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
+ break;
+ }
+ }
+
+ for (i = 0; i < MAX_SERDES; i++) {
+ srds_regs = srds_base + i * 0x1000;
+ pllcr0 = srds_regs->bank[0].pllcr0;
+ expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+ if (expected != actual[i]) {
+ printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
+ i + 1, serdes_clock_to_string(expected),
+ serdes_clock_to_string(actual[i]));
+ }
+ }
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
+
+/*
+ * This function is called by bdinfo to print detail board information.
+ * As an exmaple for future board, we organize the messages into
+ * several sections. If applicable, the message is in the format of
+ * <name> = <value>
+ * It should aligned with normal output of bdinfo command.
+ *
+ * Voltage: Core, DDR and another configurable voltages
+ * Clock : Critical clocks which are not printed already
+ * RCW : RCW source if not printed already
+ * Misc : Other important information not in above catagories
+ */
+void board_detail(void)
+{
+ int i;
+ u8 brdcfg[16], dutcfg[16], rst_ctl;
+ int vdd, rcwsrc;
+ static const char * const clk[] = {"66.67", "100", "125", "133.33"};
+
+ for (i = 0; i < 16; i++) {
+ brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+ dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+ }
+
+ /* Voltage secion */
+ if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
+ vdd = read_voltage();
+ if (vdd > 0)
+ printf("Core voltage= %d mV\n", vdd);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ }
+
+ printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
+
+ /* clock section */
+ printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
+ clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
+
+ /* RCW section */
+ rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
+ puts("RCW source = ");
+ switch (rcwsrc) {
+ case 0x017:
+ case 0x01f:
+ puts("8-bit NOR\n");
+ break;
+ case 0x027:
+ case 0x02F:
+ puts("16-bit NOR\n");
+ break;
+ case 0x040:
+ puts("SDHC/eMMC\n");
+ break;
+ case 0x044:
+ puts("SPI 16-bit addressing\n");
+ break;
+ case 0x045:
+ puts("SPI 24-bit addressing\n");
+ break;
+ case 0x048:
+ puts("I2C normal addressing\n");
+ break;
+ case 0x049:
+ puts("I2C extended addressing\n");
+ break;
+ case 0x108:
+ case 0x109:
+ case 0x10a:
+ case 0x10b:
+ puts("8-bit NAND, 2KB\n");
+ break;
+ default:
+ if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
+ puts("Hard-coded RCW\n");
+ else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
+ puts("8-bit NAND, 4KB\n");
+ else
+ puts("unknown\n");
+ break;
+ }
+
+ /* Misc section */
+ rst_ctl = QIXIS_READ(rst_ctl);
+ puts("HRESET_REQ = ");
+ switch (rst_ctl & 0x30) {
+ case 0x00:
+ puts("Ignored\n");
+ break;
+ case 0x10:
+ puts("Assert HRESET\n");
+ break;
+ case 0x30:
+ puts("Reset system\n");
+ break;
+ default:
+ puts("N/A\n");
+ break;
+ }
+}
+
+/*
+ * Reverse engineering switch settings.
+ * Some bits cannot be figured out. They will be displayed as
+ * underscore in binary format. mask[] has those bits.
+ * Some bits are calculated differently than the actual switches
+ * if booting with overriding by FPGA.
+ */
+void qixis_dump_switch(void)
+{
+ int i;
+ u8 sw[9];
+
+ /*
+ * Any bit with 1 means that bit cannot be reverse engineered.
+ * It will be displayed as _ in binary format.
+ */
+ static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
+ char buf[10];
+ u8 brdcfg[16], dutcfg[16];
+
+ for (i = 0; i < 16; i++) {
+ brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+ dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+ }
+
+ sw[0] = dutcfg[0];
+ sw[1] = (dutcfg[1] << 0x07) |
+ ((dutcfg[12] & 0xC0) >> 1) |
+ ((dutcfg[11] & 0xE0) >> 3) |
+ ((dutcfg[6] & 0x80) >> 6) |
+ ((dutcfg[1] & 0x80) >> 7);
+ sw[2] = ((brdcfg[1] & 0x0f) << 4) |
+ ((brdcfg[1] & 0x30) >> 2) |
+ ((brdcfg[1] & 0x40) >> 5) |
+ ((brdcfg[1] & 0x80) >> 7);
+ sw[3] = brdcfg[2];
+ sw[4] = ((dutcfg[2] & 0x01) << 7) |
+ ((dutcfg[2] & 0x06) << 4) |
+ ((~QIXIS_READ(present)) & 0x10) |
+ ((brdcfg[3] & 0x80) >> 4) |
+ ((brdcfg[3] & 0x01) << 2) |
+ ((brdcfg[6] == 0x62) ? 3 :
+ ((brdcfg[6] == 0x5a) ? 2 :
+ ((brdcfg[6] == 0x5e) ? 1 : 0)));
+ sw[5] = ((brdcfg[0] & 0x0f) << 4) |
+ ((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
+ ((brdcfg[0] & 0x40) >> 5);
+ sw[6] = (brdcfg[11] & 0x20) |
+ ((brdcfg[5] & 0x02) << 3);
+ sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
+ ((brdcfg[5] & 0x10) << 2);
+ sw[8] = ((brdcfg[12] & 0x08) << 4) |
+ ((brdcfg[12] & 0x03) << 5);
+
+ puts("DIP switch (reverse-engineering)\n");
+ for (i = 0; i < 9; i++) {
+ printf("SW%d = 0b%s (0x%02x)\n",
+ i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
+ }
+}
+
+static int do_vdd_adjust(cmd_tbl_t *cmdtp,
+ int flag, int argc,
+ char * const argv[])
+{
+ ulong override;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+ if (!strict_strtoul(argv[1], 10, &override))
+ adjust_vdd(override); /* the value is checked by callee */
+ else
+ return CMD_RET_USAGE;
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ vdd_override, 2, 0, do_vdd_adjust,
+ "Override VDD",
+ "- override with the voltage specified in mV, eg. 1050"
+);
diff --git a/board/freescale/t4qds/t4240qds_qixis.h b/board/freescale/t4qds/t4240qds_qixis.h
new file mode 100644
index 0000000..5246e6f
--- /dev/null
+++ b/board/freescale/t4qds/t4240qds_qixis.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T4020QDS_QIXIS_H__
+#define __T4020QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T4020QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xE0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
+
+#define BRDCFG12_SD3EN_MASK 0x20
+#define BRDCFG12_SD3MX_MASK 0x08
+#define BRDCFG12_SD3MX_SLOT5 0x08
+#define BRDCFG12_SD3MX_SLOT6 0x00
+#define BRDCFG12_SD4EN_MASK 0x04
+#define BRDCFG12_SD4MX_MASK 0x03
+#define BRDCFG12_SD4MX_SLOT7 0x02
+#define BRDCFG12_SD4MX_SLOT8 0x01
+#define BRDCFG12_SD4MX_AURO_SATA 0x00
+#endif
diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg
new file mode 100644
index 0000000..6126266
--- /dev/null
+++ b/board/freescale/t4qds/t4_pbi.cfg
@@ -0,0 +1,22 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
new file mode 100644
index 0000000..6f09a7b
--- /dev/null
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol 1_27_5_11
+16070019 18101916 00000000 00000000
+04362858 30548c00 ec020000 f5000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4qds/t4qds.h b/board/freescale/t4qds/t4qds.h
new file mode 100644
index 0000000..f7cb5cd
--- /dev/null
+++ b/board/freescale/t4qds/t4qds.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
new file mode 100644
index 0000000..1e4d096
--- /dev/null
+++ b/board/freescale/t4qds/tlb.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+ * space is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+#ifndef CONFIG_SPL_BUILD
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef QIXIS_BASE_PHYS
+ SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+ * fetching ucode and ENV from master
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 19, BOOKE_PAGESZ_2G, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig
new file mode 100644
index 0000000..d93e453
--- /dev/null
+++ b/board/freescale/t4rdb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_T4240RDB
+
+config SYS_BOARD
+ default "t4rdb"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "T4240RDB"
+
+endif
diff --git a/board/freescale/t4rdb/MAINTAINERS b/board/freescale/t4rdb/MAINTAINERS
new file mode 100644
index 0000000..845c1b6
--- /dev/null
+++ b/board/freescale/t4rdb/MAINTAINERS
@@ -0,0 +1,7 @@
+T4RDB BOARD
+M: Chunhe Lan <Chunhe.Lan@freescale.com>
+S: Maintained
+F: board/freescale/t4rdb/
+F: include/configs/T4240RDB.h
+F: configs/T4160RDB_defconfig
+F: configs/T4240RDB_defconfig
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
new file mode 100644
index 0000000..3886e3d
--- /dev/null
+++ b/board/freescale/t4rdb/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_T4240RDB) += t4240rdb.o
+obj-y += cpld.o
+obj-y += ddr.o
+obj-y += eth.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c
new file mode 100644
index 0000000..d5f3812
--- /dev/null
+++ b/board/freescale/t4rdb/cpld.c
@@ -0,0 +1,136 @@
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the board-specific CPLD used on some Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
+ * CPLD register map
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+ void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+ out_8(p + reg, value);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(void)
+{
+ u8 val, curbank, altbank, override;
+
+ val = CPLD_READ(vbank);
+ curbank = val & CPLD_BANK_SEL_MASK;
+
+ switch (curbank) {
+ case CPLD_SELECT_BANK0:
+ altbank = CPLD_SELECT_BANK4;
+ CPLD_WRITE(vbank, altbank);
+ override = CPLD_READ(software_on);
+ CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
+ CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
+ break;
+ case CPLD_SELECT_BANK4:
+ altbank = CPLD_SELECT_BANK0;
+ CPLD_WRITE(vbank, altbank);
+ override = CPLD_READ(software_on);
+ CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
+ CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
+ break;
+ default:
+ printf("CPLD Altbank Fail: Invalid value!\n");
+ return;
+ }
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+ u8 val;
+
+ val = CPLD_DEFAULT_BANK;
+
+ CPLD_WRITE(global_reset, val);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+ printf("chip_id1 = 0x%02x\n", CPLD_READ(chip_id1));
+ printf("chip_id2 = 0x%02x\n", CPLD_READ(chip_id2));
+ printf("sw_maj_ver = 0x%02x\n", CPLD_READ(sw_maj_ver));
+ printf("sw_min_ver = 0x%02x\n", CPLD_READ(sw_min_ver));
+ printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
+ printf("software_on = 0x%02x\n", CPLD_READ(software_on));
+ printf("cfg_rcw_src = 0x%02x\n", CPLD_READ(cfg_rcw_src));
+ printf("res0 = 0x%02x\n", CPLD_READ(res0));
+ printf("vbank = 0x%02x\n", CPLD_READ(vbank));
+ printf("sw1_sysclk = 0x%02x\n", CPLD_READ(sw1_sysclk));
+ printf("sw2_status = 0x%02x\n", CPLD_READ(sw2_status));
+ printf("sw3_status = 0x%02x\n", CPLD_READ(sw3_status));
+ printf("sw4_status = 0x%02x\n", CPLD_READ(sw4_status));
+ printf("sys_reset = 0x%02x\n", CPLD_READ(sys_reset));
+ printf("global_reset = 0x%02x\n", CPLD_READ(global_reset));
+ printf("res1 = 0x%02x\n", CPLD_READ(res1));
+ putc('\n');
+}
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rc = 0;
+
+ if (argc <= 1)
+ return cmd_usage(cmdtp);
+
+ if (strcmp(argv[1], "reset") == 0) {
+ if (strcmp(argv[2], "altbank") == 0)
+ cpld_set_altbank();
+ else
+ cpld_set_defbank();
+#ifdef DEBUG
+ } else if (strcmp(argv[1], "dump") == 0) {
+ cpld_dump_regs();
+#endif
+ } else
+ rc = cmd_usage(cmdtp);
+
+ return rc;
+}
+
+U_BOOT_CMD(
+ cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+ "Reset the board or alternate bank",
+ "reset - reset to default bank\n"
+ "cpld reset altbank - reset to alternate bank\n"
+#ifdef DEBUG
+ "cpld dump - display the CPLD registers\n"
+#endif
+ );
+#endif
diff --git a/board/freescale/t4rdb/cpld.h b/board/freescale/t4rdb/cpld.h
new file mode 100644
index 0000000..0180082
--- /dev/null
+++ b/board/freescale/t4rdb/cpld.h
@@ -0,0 +1,49 @@
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/*
+ * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
+ */
+struct cpld_data {
+ u8 chip_id1; /* 0x00 - CPLD Chip ID1 Register */
+ u8 chip_id2; /* 0x01 - CPLD Chip ID2 Register */
+ u8 sw_maj_ver; /* 0x02 - CPLD Code Major Version Register */
+ u8 sw_min_ver; /* 0x03 - CPLD Code Minor Version Register */
+ u8 hw_ver; /* 0x04 - PCBA Version Register */
+ u8 software_on; /* 0x05 - Override Physical Switch Enable Register */
+ u8 cfg_rcw_src; /* 0x06 - RCW Source Location Control Register */
+ u8 res0; /* 0x07 - not used */
+ u8 vbank; /* 0x08 - Flash Bank Selection Control Register */
+ u8 sw1_sysclk; /* 0x09 - SW1 Status Read Back Register */
+ u8 sw2_status; /* 0x0a - SW2 Status Read Back Register */
+ u8 sw3_status; /* 0x0b - SW3 Status Read Back Register */
+ u8 sw4_status; /* 0x0c - SW4 Status Read Back Register */
+ u8 sys_reset; /* 0x0d - Reset System With Reserving Registers Value*/
+ u8 global_reset;/* 0x0e - Reset System With Default Registers Value */
+ u8 res1; /* 0x0f - not used */
+};
+
+#define CPLD_BANK_SEL_MASK 0x07
+#define CPLD_BANK_SEL_EN 0x04
+#define CPLD_SYSTEM_RESET 0x01
+#define CPLD_SELECT_BANK0 0x00
+#define CPLD_SELECT_BANK4 0x04
+#define CPLD_DEFAULT_BANK 0x01
+
+/* Pointer to the CPLD register set */
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value) \
+ cpld_write(offsetof(struct cpld_data, reg), value)
+
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
new file mode 100644
index 0000000..5a43c1b
--- /dev/null
+++ b/board/freescale/t4rdb/ddr.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[0];
+ else
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found for data\n"
+ "rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h
new file mode 100644
index 0000000..7b85476
--- /dev/null
+++ b/board/freescale/t4rdb/ddr.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a},
+ {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09},
+ {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b},
+ {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a},
+ {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
+ {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
+ {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a},
+ {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a},
+ {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3
+ */
+ {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
+ {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
+ {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
+ {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
+ {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
+ {}
+};
+
+/*
+ * The three slots have slightly different timing. The center values are good
+ * for all slots. We use identical speed tables for them. In future use, if
+ * DIMMs require separated tables, make more entries as needed.
+ */
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+/*
+ * The three slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+};
+
+
+#endif
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
new file mode 100644
index 0000000..142c6a8
--- /dev/null
+++ b/board/freescale/t4rdb/eth.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include <hwconfig.h>
+
+#include "../common/fman.h"
+#include "t4rdb.h"
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ struct mii_dev *dev;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1, srds_prtcl_s2;
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
+ /* SGMII */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
+ fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
+ } else {
+ puts("Invalid SerDes1 protocol for T4240RDB\n");
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ if (srds_prtcl_s2 == 56) {
+ /* SGMII && XFI */
+ fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
+ fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
+ fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
+ fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
+ } else {
+ puts("Invalid SerDes2 protocol for T4240RDB\n");
+ }
+
+ for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+#endif /* CONFIG_SYS_NUM_FMAN */
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c
new file mode 100644
index 0000000..39818fc
--- /dev/null
+++ b/board/freescale/t4rdb/law.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c
new file mode 100644
index 0000000..6387a20
--- /dev/null
+++ b/board/freescale/t4rdb/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
new file mode 100644
index 0000000..fac442b
--- /dev/null
+++ b/board/freescale/t4rdb/t4240rdb.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "t4rdb.h"
+#include "cpld.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+ u8 sw;
+
+ printf("Board: %sRDB, ", cpu->name);
+ printf("Board rev: 0x%02x CPLD ver: 0x%02x%02x, ",
+ CPLD_READ(hw_ver), CPLD_READ(sw_maj_ver), CPLD_READ(sw_min_ver));
+
+ sw = CPLD_READ(vbank);
+ sw = sw & CPLD_BANK_SEL_MASK;
+
+ if (sw <= 7)
+ printf("vBank: %d\n", sw);
+ else
+ printf("Unsupported Bank=%x\n", sw);
+
+ puts("SERDES Reference Clocks:\n");
+ printf(" SERDES1=100MHz SERDES2=156.25MHz\n"
+ " SERDES3=100MHz SERDES4=100MHz\n");
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
+
+/*
+ * This function is called by bdinfo to print detail board information.
+ * As an exmaple for future board, we organize the messages into
+ * several sections. If applicable, the message is in the format of
+ * <name> = <value>
+ * It should aligned with normal output of bdinfo command.
+ *
+ * Voltage: Core, DDR and another configurable voltages
+ * Clock : Critical clocks which are not printed already
+ * RCW : RCW source if not printed already
+ * Misc : Other important information not in above catagories
+ */
+void board_detail(void)
+{
+ int rcwsrc;
+
+ /* RCW section SW3[4] */
+ rcwsrc = 0x0;
+ puts("RCW source = ");
+ switch (rcwsrc & 0x1) {
+ case 0x1:
+ puts("SDHC/eMMC\n");
+ break;
+ default:
+ puts("I2C normal addressing\n");
+ break;
+ }
+}
diff --git a/board/freescale/t4rdb/t4_pbi.cfg b/board/freescale/t4rdb/t4_pbi.cfg
new file mode 100644
index 0000000..c9f8ced
--- /dev/null
+++ b/board/freescale/t4rdb/t4_pbi.cfg
@@ -0,0 +1,31 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#slow mdio clock
+095fc030 00008148
+095fd030 00808148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
new file mode 100644
index 0000000..fdbbe5e
--- /dev/null
+++ b/board/freescale/t4rdb/t4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol 27_56_1_9
+16070019 18101916 00000000 00000000
+6c700848 00448c00 6c020000 f5000000
+00000000 ee0000ee 00000000 000287fc
+00000000 50000000 00000000 00000028
diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h
new file mode 100644
index 0000000..fb25d43
--- /dev/null
+++ b/board/freescale/t4rdb/t4rdb.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T4RDB_H__
+#define __T4RDB_H__
+
+#undef CONFIG_SYS_NUM_FM1_DTSEC
+#undef CONFIG_SYS_NUM_FM2_DTSEC
+#define CONFIG_SYS_NUM_FM1_DTSEC 4
+#define CONFIG_SYS_NUM_FM2_DTSEC 4
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c
new file mode 100644
index 0000000..474301e
--- /dev/null
+++ b/board/freescale/t4rdb/tlb.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 512K SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_512K, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/vf610twr/Kconfig b/board/freescale/vf610twr/Kconfig
new file mode 100644
index 0000000..ef091d6
--- /dev/null
+++ b/board/freescale/vf610twr/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_VF610TWR
+
+config SYS_BOARD
+ default "vf610twr"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "vf610"
+
+config SYS_CONFIG_NAME
+ default "vf610twr"
+
+endif
diff --git a/board/freescale/vf610twr/MAINTAINERS b/board/freescale/vf610twr/MAINTAINERS
new file mode 100644
index 0000000..f2997f0
--- /dev/null
+++ b/board/freescale/vf610twr/MAINTAINERS
@@ -0,0 +1,7 @@
+VF610TWR BOARD
+M: Alison Wang <b18965@freescale.com>
+S: Maintained
+F: board/freescale/vf610twr/
+F: include/configs/vf610twr.h
+F: configs/vf610twr_defconfig
+F: configs/vf610twr_nand_defconfig
diff --git a/board/freescale/vf610twr/Makefile b/board/freescale/vf610twr/Makefile
new file mode 100644
index 0000000..20b4a6b
--- /dev/null
+++ b/board/freescale/vf610twr/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := vf610twr.o
diff --git a/board/freescale/vf610twr/imximage.cfg b/board/freescale/vf610twr/imximage.cfg
new file mode 100644
index 0000000..9c823c4
--- /dev/null
+++ b/board/freescale/vf610twr/imximage.cfg
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION 2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET FLASH_OFFSET_STANDARD
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
new file mode 100644
index 0000000..b634965
--- /dev/null
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -0,0 +1,498 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+void setup_iomux_ddr(void)
+{
+ static const iomux_v3_cfg_t ddr_pads[] = {
+ VF610_PAD_DDR_A15__DDR_A_15,
+ VF610_PAD_DDR_A14__DDR_A_14,
+ VF610_PAD_DDR_A13__DDR_A_13,
+ VF610_PAD_DDR_A12__DDR_A_12,
+ VF610_PAD_DDR_A11__DDR_A_11,
+ VF610_PAD_DDR_A10__DDR_A_10,
+ VF610_PAD_DDR_A9__DDR_A_9,
+ VF610_PAD_DDR_A8__DDR_A_8,
+ VF610_PAD_DDR_A7__DDR_A_7,
+ VF610_PAD_DDR_A6__DDR_A_6,
+ VF610_PAD_DDR_A5__DDR_A_5,
+ VF610_PAD_DDR_A4__DDR_A_4,
+ VF610_PAD_DDR_A3__DDR_A_3,
+ VF610_PAD_DDR_A2__DDR_A_2,
+ VF610_PAD_DDR_A1__DDR_A_1,
+ VF610_PAD_DDR_A0__DDR_A_0,
+ VF610_PAD_DDR_BA2__DDR_BA_2,
+ VF610_PAD_DDR_BA1__DDR_BA_1,
+ VF610_PAD_DDR_BA0__DDR_BA_0,
+ VF610_PAD_DDR_CAS__DDR_CAS_B,
+ VF610_PAD_DDR_CKE__DDR_CKE_0,
+ VF610_PAD_DDR_CLK__DDR_CLK_0,
+ VF610_PAD_DDR_CS__DDR_CS_B_0,
+ VF610_PAD_DDR_D15__DDR_D_15,
+ VF610_PAD_DDR_D14__DDR_D_14,
+ VF610_PAD_DDR_D13__DDR_D_13,
+ VF610_PAD_DDR_D12__DDR_D_12,
+ VF610_PAD_DDR_D11__DDR_D_11,
+ VF610_PAD_DDR_D10__DDR_D_10,
+ VF610_PAD_DDR_D9__DDR_D_9,
+ VF610_PAD_DDR_D8__DDR_D_8,
+ VF610_PAD_DDR_D7__DDR_D_7,
+ VF610_PAD_DDR_D6__DDR_D_6,
+ VF610_PAD_DDR_D5__DDR_D_5,
+ VF610_PAD_DDR_D4__DDR_D_4,
+ VF610_PAD_DDR_D3__DDR_D_3,
+ VF610_PAD_DDR_D2__DDR_D_2,
+ VF610_PAD_DDR_D1__DDR_D_1,
+ VF610_PAD_DDR_D0__DDR_D_0,
+ VF610_PAD_DDR_DQM1__DDR_DQM_1,
+ VF610_PAD_DDR_DQM0__DDR_DQM_0,
+ VF610_PAD_DDR_DQS1__DDR_DQS_1,
+ VF610_PAD_DDR_DQS0__DDR_DQS_0,
+ VF610_PAD_DDR_RAS__DDR_RAS_B,
+ VF610_PAD_DDR_WE__DDR_WE_B,
+ VF610_PAD_DDR_ODT1__DDR_ODT_0,
+ VF610_PAD_DDR_ODT0__DDR_ODT_1,
+ VF610_PAD_DDR_RESETB,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddr_phy_init(void)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+ writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
+ writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
+ writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
+
+ writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
+ writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
+
+ writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
+ writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
+ writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
+
+ writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
+ writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
+ writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
+
+ writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
+ writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
+ writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+
+ /* LPDDR2 only parameter */
+ writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
+
+ writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
+ &ddrmr->phy[50]);
+
+ /* Processor Pad ODT settings */
+ writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
+}
+
+void ddr_ctrl_init(void)
+{
+ struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+ writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
+ writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
+ writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]);
+
+ writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]);
+ writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
+ writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4),
+ &ddrmr->cr[13]);
+ writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
+ DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
+ writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
+ writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12),
+ &ddrmr->cr[17]);
+ writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
+
+ writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
+ writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+
+ writel(DDRMC_CR22_TDAL(12), &ddrmr->cr[22]);
+ writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
+ writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
+
+ writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
+ writel(DDRMC_CR26_TREF(3120) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
+ writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
+ writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
+
+ writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
+ writel(DDRMC_CR31_TXSNR(48) | DDRMC_CR31_TXSR(468), &ddrmr->cr[31]);
+ writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
+ writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
+
+ writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
+ writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
+ DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
+
+ writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
+ writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056),
+ &ddrmr->cr[48]);
+
+ writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]);
+ writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]);
+ writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
+
+ writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
+ writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
+
+ writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
+ DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
+ writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
+ DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
+ &ddrmr->cr[74]);
+ writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
+ DDRMC_CR75_PLEN, &ddrmr->cr[75]);
+ writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
+ DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
+ writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
+ DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
+ writel(DDRMC_CR78_Q_FULLNESS(7) | DDRMC_CR78_BUR_ON_FLY_BIT(12),
+ &ddrmr->cr[78]);
+ writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
+
+ writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
+
+ writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
+ writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
+ writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
+
+ writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
+ writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
+ writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
+ writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]);
+ writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]);
+
+ writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN,
+ &ddrmr->cr[102]);
+
+ writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]);
+ writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]);
+ writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]);
+ writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]);
+ writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]);
+
+ writel(DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0),
+ &ddrmr->cr[117]);
+ writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
+ &ddrmr->cr[118]);
+
+ writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2),
+ &ddrmr->cr[120]);
+ writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2),
+ &ddrmr->cr[121]);
+ writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+ DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
+ writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
+ DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
+ writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
+
+ writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
+ writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
+ &ddrmr->cr[132]);
+ writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
+ writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | DDRMC_CR138_PHYDRAM_CK_EN(1),
+ &ddrmr->cr[138]);
+ writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+ DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
+ &ddrmr->cr[139]);
+ writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
+ writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | DDRMC_CR143_RDLV_MXDL(128),
+ &ddrmr->cr[143]);
+ writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
+ DDRMC_CR144_PHY_RDLV_DLL(3) | DDRMC_CR144_PHY_RDLV_EN(3),
+ &ddrmr->cr[144]);
+ writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
+ writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
+ writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
+ writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
+ writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
+ DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
+
+ writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+ DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
+ DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
+ writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2),
+ &ddrmr->cr[155]);
+ writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
+ writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
+ DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
+
+ ddr_phy_init();
+
+ writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
+
+ udelay(200);
+}
+
+int dram_init(void)
+{
+ setup_iomux_ddr();
+
+ ddr_ctrl_init();
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+ static const iomux_v3_cfg_t uart1_pads[] = {
+ NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+ static const iomux_v3_cfg_t enet0_pads[] = {
+ NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
+}
+
+static void setup_iomux_i2c(void)
+{
+ static const iomux_v3_cfg_t i2c0_pads[] = {
+ VF610_PAD_PTB14__I2C0_SCL,
+ VF610_PAD_PTB15__I2C0_SDA,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
+}
+
+#ifdef CONFIG_NAND_VF610_NFC
+static void setup_iomux_nfc(void)
+{
+ static const iomux_v3_cfg_t nfc_pads[] = {
+ VF610_PAD_PTD31__NF_IO15,
+ VF610_PAD_PTD30__NF_IO14,
+ VF610_PAD_PTD29__NF_IO13,
+ VF610_PAD_PTD28__NF_IO12,
+ VF610_PAD_PTD27__NF_IO11,
+ VF610_PAD_PTD26__NF_IO10,
+ VF610_PAD_PTD25__NF_IO9,
+ VF610_PAD_PTD24__NF_IO8,
+ VF610_PAD_PTD23__NF_IO7,
+ VF610_PAD_PTD22__NF_IO6,
+ VF610_PAD_PTD21__NF_IO5,
+ VF610_PAD_PTD20__NF_IO4,
+ VF610_PAD_PTD19__NF_IO3,
+ VF610_PAD_PTD18__NF_IO2,
+ VF610_PAD_PTD17__NF_IO1,
+ VF610_PAD_PTD16__NF_IO0,
+ VF610_PAD_PTB24__NF_WE_B,
+ VF610_PAD_PTB25__NF_CE0_B,
+ VF610_PAD_PTB27__NF_RE_B,
+ VF610_PAD_PTC26__NF_RB_B,
+ VF610_PAD_PTC27__NF_ALE,
+ VF610_PAD_PTC28__NF_CLE
+ };
+
+ imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+}
+#endif
+
+
+static void setup_iomux_qspi(void)
+{
+ static const iomux_v3_cfg_t qspi0_pads[] = {
+ VF610_PAD_PTD0__QSPI0_A_QSCK,
+ VF610_PAD_PTD1__QSPI0_A_CS0,
+ VF610_PAD_PTD2__QSPI0_A_DATA3,
+ VF610_PAD_PTD3__QSPI0_A_DATA2,
+ VF610_PAD_PTD4__QSPI0_A_DATA1,
+ VF610_PAD_PTD5__QSPI0_A_DATA0,
+ VF610_PAD_PTD7__QSPI0_B_QSCK,
+ VF610_PAD_PTD8__QSPI0_B_CS0,
+ VF610_PAD_PTD9__QSPI0_B_DATA3,
+ VF610_PAD_PTD10__QSPI0_B_DATA2,
+ VF610_PAD_PTD11__QSPI0_B_DATA1,
+ VF610_PAD_PTD12__QSPI0_B_DATA0,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+ {ESDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* eSDHC1 is always present */
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t esdhc1_pads[] = {
+ NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
+ NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
+ };
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(
+ esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+static void clock_init(void)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+
+ clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+ CCM_CCGR0_UART1_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+ CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+ CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+ CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+ CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
+ CCM_CCGR2_QSPI0_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+ CCM_CCGR3_ANADIG_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+ CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+ CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+ CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+ CCM_CCGR7_SDHC1_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+ CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
+ CCM_CCGR10_NFC_CTRL_MASK);
+
+ clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
+ ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+ clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+ ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+
+ clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+ CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+ clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
+ CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
+ CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
+ CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
+ CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
+ CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
+ CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
+ clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
+ CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
+ CCM_CACRR_ARM_CLK_DIV(0));
+ clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
+ CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
+ CCM_CSCMR1_NFC_CLK_SEL(0));
+ clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
+ CCM_CSCDR1_RMII_CLK_EN);
+ clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
+ CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
+ CCM_CSCDR2_NFC_EN);
+ clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
+ CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
+ CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
+ CCM_CSCDR3_NFC_PRE_DIV(5));
+ clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
+ CCM_CSCMR2_RMII_CLK_SEL(0));
+}
+
+static void mscm_init(void)
+{
+ struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
+ int i;
+
+ for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+ writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ clock_init();
+ mscm_init();
+
+ setup_iomux_uart();
+ setup_iomux_enet();
+ setup_iomux_i2c();
+ setup_iomux_qspi();
+#ifdef CONFIG_NAND_VF610_NFC
+ setup_iomux_nfc();
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: vf610twr\n");
+
+ return 0;
+}
diff --git a/board/g2000/Kconfig b/board/g2000/Kconfig
new file mode 100644
index 0000000..031fae9
--- /dev/null
+++ b/board/g2000/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_G2000
+
+config SYS_BOARD
+ default "g2000"
+
+config SYS_CONFIG_NAME
+ default "G2000"
+
+endif
diff --git a/board/g2000/MAINTAINERS b/board/g2000/MAINTAINERS
new file mode 100644
index 0000000..8171b10
--- /dev/null
+++ b/board/g2000/MAINTAINERS
@@ -0,0 +1,6 @@
+G2000 BOARD
+M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+S: Maintained
+F: board/g2000/
+F: include/configs/G2000.h
+F: configs/G2000_defconfig
diff --git a/board/g2000/Makefile b/board/g2000/Makefile
new file mode 100644
index 0000000..74c8053
--- /dev/null
+++ b/board/g2000/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = g2000.o strataflash.o
diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c
new file mode 100644
index 0000000..a64f946
--- /dev/null
+++ b/board/g2000/g2000.c
@@ -0,0 +1,245 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+
+#define MEM_MCOPT1_INIT_VAL 0x00800000
+#define MEM_RTR_INIT_VAL 0x04070000
+#define MEM_PMIT_INIT_VAL 0x07c00000
+#define MEM_MB0CF_INIT_VAL 0x00082001
+#define MEM_MB1CF_INIT_VAL 0x04082000
+#define MEM_SDTR1_INIT_VAL 0x00854005
+#define SDRAM0_CFG_ENABLE 0x80000000
+
+#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */
+
+int board_early_init_f (void)
+{
+#if 0 /* test-only */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000010);
+ mtdcr (UIC0PR, 0xFFFF7FF0); /* set int polarities */
+ mtdcr (UIC0TR, 0x00000010); /* set int trigger levels */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+#else
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFFF0); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+#endif
+
+#if 1 /* test-only */
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ */
+ mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
+#endif
+
+ return 0;
+}
+
+
+int misc_init_f (void)
+{
+ return 0; /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+#if defined(CONFIG_CMD_NAND)
+ /*
+ * Set NAND-FLASH GPIO signals to default
+ */
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);
+#endif
+
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming G2000");
+ } else {
+ puts(str);
+ }
+
+ putc ('\n');
+
+ return 0;
+}
+
+
+/* -------------------------------------------------------------------------
+ G2000 rev B is an embeded design. we don't read for spd of this version.
+ Doing static SDRAM controller configuration in the following section.
+ ------------------------------------------------------------------------- */
+
+long int init_sdram_static_settings(void)
+{
+ /* disable memcontroller so updates work */
+ mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL);
+ mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL);
+ mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL);
+ mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL);
+ mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL);
+ mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL);
+
+ /* SDRAM have a power on delay, 500 micro should do */
+ udelay(500);
+ mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE);
+
+ return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */
+ }
+
+
+phys_size_t initdram (int board_type)
+{
+ long int ret;
+
+/* flzt, we can still turn this on in the future */
+/* #ifdef CONFIG_SPD_EEPROM
+ ret = spd_sdram ();
+#else
+ ret = init_sdram_static_settings();
+#endif
+*/
+
+ ret = init_sdram_static_settings();
+
+ return ret;
+}
+
+#if 0 /* test-only !!! */
+int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong ap, cr;
+
+ printf("\nEBC registers for PPC405GP:\n");
+ mfebc(PB0AP, ap); mfebc(PB0CR, cr);
+ printf("0: AP=%08lx CP=%08lx\n", ap, cr);
+ mfebc(PB1AP, ap); mfebc(PB1CR, cr);
+ printf("1: AP=%08lx CP=%08lx\n", ap, cr);
+ mfebc(PB2AP, ap); mfebc(PB2CR, cr);
+ printf("2: AP=%08lx CP=%08lx\n", ap, cr);
+ mfebc(PB3AP, ap); mfebc(PB3CR, cr);
+ printf("3: AP=%08lx CP=%08lx\n", ap, cr);
+ mfebc(PB4AP, ap); mfebc(PB4CR, cr);
+ printf("4: AP=%08lx CP=%08lx\n", ap, cr);
+ printf("\n");
+
+ return 0;
+}
+U_BOOT_CMD(
+ dumpebc, 1, 1, do_dumpebc,
+ "Dump all EBC registers",
+ ""
+);
+
+
+int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i;
+
+ printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
+ for (i=0; i<=0x1e0; i++) {
+ if (!(i % 0x8)) {
+ printf("\n%04x ", i);
+ }
+ printf("%08lx ", get_dcr(i));
+ }
+ printf("\n");
+
+ return 0;
+}
+U_BOOT_CMD(
+ dumpdcr, 1, 1, do_dumpdcr,
+ "Dump all DCR registers",
+ ""
+);
+
+
+int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
+ printf("\n%04x %08x ", 947, mfspr(947));
+ printf("\n%04x %08x ", 9, mfspr(9));
+ printf("\n%04x %08x ", 1014, mfspr(1014));
+ printf("\n%04x %08x ", 1015, mfspr(1015));
+ printf("\n%04x %08x ", 1010, mfspr(1010));
+ printf("\n%04x %08x ", 957, mfspr(957));
+ printf("\n%04x %08x ", 1008, mfspr(1008));
+ printf("\n%04x %08x ", 1018, mfspr(1018));
+ printf("\n%04x %08x ", 954, mfspr(954));
+ printf("\n%04x %08x ", 950, mfspr(950));
+ printf("\n%04x %08x ", 951, mfspr(951));
+ printf("\n%04x %08x ", 981, mfspr(981));
+ printf("\n%04x %08x ", 980, mfspr(980));
+ printf("\n%04x %08x ", 982, mfspr(982));
+ printf("\n%04x %08x ", 1012, mfspr(1012));
+ printf("\n%04x %08x ", 1013, mfspr(1013));
+ printf("\n%04x %08x ", 948, mfspr(948));
+ printf("\n%04x %08x ", 949, mfspr(949));
+ printf("\n%04x %08x ", 1019, mfspr(1019));
+ printf("\n%04x %08x ", 979, mfspr(979));
+ printf("\n%04x %08x ", 8, mfspr(8));
+ printf("\n%04x %08x ", 945, mfspr(945));
+ printf("\n%04x %08x ", 987, mfspr(987));
+ printf("\n%04x %08x ", 287, mfspr(287));
+ printf("\n%04x %08x ", 953, mfspr(953));
+ printf("\n%04x %08x ", 955, mfspr(955));
+ printf("\n%04x %08x ", 272, mfspr(272));
+ printf("\n%04x %08x ", 273, mfspr(273));
+ printf("\n%04x %08x ", 274, mfspr(274));
+ printf("\n%04x %08x ", 275, mfspr(275));
+ printf("\n%04x %08x ", 260, mfspr(260));
+ printf("\n%04x %08x ", 276, mfspr(276));
+ printf("\n%04x %08x ", 261, mfspr(261));
+ printf("\n%04x %08x ", 277, mfspr(277));
+ printf("\n%04x %08x ", 262, mfspr(262));
+ printf("\n%04x %08x ", 278, mfspr(278));
+ printf("\n%04x %08x ", 263, mfspr(263));
+ printf("\n%04x %08x ", 279, mfspr(279));
+ printf("\n%04x %08x ", 26, mfspr(26));
+ printf("\n%04x %08x ", 27, mfspr(27));
+ printf("\n%04x %08x ", 990, mfspr(990));
+ printf("\n%04x %08x ", 991, mfspr(991));
+ printf("\n%04x %08x ", 956, mfspr(956));
+ printf("\n%04x %08x ", 284, mfspr(284));
+ printf("\n%04x %08x ", 285, mfspr(285));
+ printf("\n%04x %08x ", 986, mfspr(986));
+ printf("\n%04x %08x ", 984, mfspr(984));
+ printf("\n%04x %08x ", 256, mfspr(256));
+ printf("\n%04x %08x ", 1, mfspr(1));
+ printf("\n%04x %08x ", 944, mfspr(944));
+ printf("\n");
+
+ return 0;
+}
+U_BOOT_CMD(
+ dumpspr, 1, 1, do_dumpspr,
+ "Dump all SPR registers",
+ ""
+);
+#endif
diff --git a/board/g2000/strataflash.c b/board/g2000/strataflash.c
new file mode 100644
index 0000000..1d29eb4
--- /dev/null
+++ b/board/g2000/strataflash.c
@@ -0,0 +1,774 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI 0x98
+#define FLASH_CMD_READ_ID 0x90
+#define FLASH_CMD_RESET 0xff
+#define FLASH_CMD_BLOCK_ERASE 0x20
+#define FLASH_CMD_ERASE_CONFIRM 0xD0
+#define FLASH_CMD_WRITE 0x40
+#define FLASH_CMD_PROTECT 0x60
+#define FLASH_CMD_PROTECT_SET 0x01
+#define FLASH_CMD_PROTECT_CLEAR 0xD0
+#define FLASH_CMD_CLEAR_STATUS 0x50
+#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
+
+#define FLASH_STATUS_DONE 0x80
+#define FLASH_STATUS_ESS 0x40
+#define FLASH_STATUS_ECLBS 0x20
+#define FLASH_STATUS_PSLBS 0x10
+#define FLASH_STATUS_VPENS 0x08
+#define FLASH_STATUS_PSS 0x04
+#define FLASH_STATUS_DPS 0x02
+#define FLASH_STATUS_R 0x01
+#define FLASH_STATUS_PROTECT 0x01
+
+#define FLASH_OFFSET_CFI 0x55
+#define FLASH_OFFSET_CFI_RESP 0x10
+#define FLASH_OFFSET_WTOUT 0x1F
+#define FLASH_OFFSET_WBTOUT 0x20
+#define FLASH_OFFSET_ETOUT 0x21
+#define FLASH_OFFSET_CETOUT 0x22
+#define FLASH_OFFSET_WMAX_TOUT 0x23
+#define FLASH_OFFSET_WBMAX_TOUT 0x24
+#define FLASH_OFFSET_EMAX_TOUT 0x25
+#define FLASH_OFFSET_CEMAX_TOUT 0x26
+#define FLASH_OFFSET_SIZE 0x27
+#define FLASH_OFFSET_INTERFACE 0x28
+#define FLASH_OFFSET_BUFFER_SIZE 0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
+#define FLASH_OFFSET_ERASE_REGIONS 0x2D
+#define FLASH_OFFSET_PROTECT 0x02
+#define FLASH_OFFSET_USER_PROTECTION 0x85
+#define FLASH_OFFSET_INTEL_PROTECTION 0x81
+
+#define FLASH_MAN_CFI 0x01000000
+
+typedef union {
+ unsigned char c;
+ unsigned short w;
+ unsigned long l;
+} cfiword_t;
+
+typedef union {
+ unsigned char * cp;
+ unsigned short *wp;
+ unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+ return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+ uchar *cp;
+ cp = flash_make_addr(info, 0, offset);
+ return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
+{
+ uchar * addr;
+
+ addr = flash_make_addr(info, sect, offset);
+ return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
+{
+ uchar * addr;
+
+ addr = flash_make_addr(info, sect, offset);
+ return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+ (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+ unsigned long size;
+ int i;
+ unsigned long address;
+
+
+ /* The flash is positioned back to back, with the demultiplexing of the chip
+ * based on the A24 address line.
+ *
+ */
+
+ address = CONFIG_SYS_FLASH_BASE;
+ size = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ size += flash_info[i].size = flash_get_size(address, i);
+ address += CONFIG_SYS_FLASH_INCREMENT;
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+ flash_info[0].size, flash_info[i].size<<20);
+ }
+ }
+
+#if 0 /* test-only */
+ /* Monitor protection ON by default */
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+ for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++)
+ (void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#else
+ /* monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ - CONFIG_SYS_MONITOR_LEN,
+ - 1, &flash_info[1]);
+#endif
+
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int rcode = 0;
+ int prot;
+ int sect;
+
+ if( info->flash_id != FLASH_MAN_CFI) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+ if ((s_first < 0) || (s_first > s_last)) {
+ printf ("- no sectors to erase\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+ flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+ if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+ rcode = 1;
+ } else
+ printf(".");
+ }
+ }
+ printf (" done\n");
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id != FLASH_MAN_CFI) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ printf("CFI conformant FLASH (%d x %d)",
+ (info->portwidth << 3 ), (info->chipwidth << 3 ));
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+ printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+ info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count-1))
+ size = info->start[i+1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k=0; k<size; k++)
+ {
+ if (*flash++ != 0xffffffff)
+ {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf ("\n ");
+ /* print empty and read-only info */
+ printf (" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " ");
+#else
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+#endif
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong wp;
+ ulong cp;
+ int aln;
+ cfiword_t cword;
+ int i, rc;
+
+ /* get lower aligned address */
+ wp = (addr & ~(info->portwidth - 1));
+
+ /* handle unaligned start */
+ if((aln = addr - wp) != 0) {
+ cword.l = 0;
+ cp = wp;
+ for(i=0;i<aln; ++i, ++cp)
+ flash_add_byte(info, &cword, (*(uchar *)cp));
+
+ for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+ flash_add_byte(info, &cword, *src++);
+ cnt--;
+ cp++;
+ }
+ for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+ flash_add_byte(info, &cword, (*(uchar *)cp));
+ if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+ return rc;
+ wp = cp;
+ }
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+ while(cnt >= info->portwidth) {
+ i = info->buffer_size > cnt? cnt: info->buffer_size;
+ if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+ return rc;
+ wp += i;
+ src += i;
+ cnt -=i;
+ }
+#else
+ /* handle the aligned part */
+ while(cnt >= info->portwidth) {
+ cword.l = 0;
+ for(i = 0; i < info->portwidth; i++) {
+ flash_add_byte(info, &cword, *src++);
+ }
+ if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+ return rc;
+ wp += info->portwidth;
+ cnt -= info->portwidth;
+ }
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ cword.l = 0;
+ for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+ flash_add_byte(info, &cword, *src++);
+ --cnt;
+ }
+ for (; i<info->portwidth; ++i, ++cp) {
+ flash_add_byte(info, & cword, (*(uchar *)cp));
+ }
+
+ return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+ int retcode = 0;
+
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+ if(prot)
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+ else
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+ if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+ prot?"protect":"unprotect")) == 0) {
+
+ info->protect[sector] = prot;
+ /* Intel's unprotect unprotects all locking */
+ if(prot == 0) {
+ int i;
+ for(i = 0 ; i<info->sector_count; i++) {
+ if(info->protect[i])
+ flash_real_protect(info, i, 1);
+ }
+ }
+ }
+
+ return retcode;
+}
+/*-----------------------------------------------------------------------
+ * wait for XSR.7 to be set. Time out with an error if it does not.
+ * This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+ ulong start;
+
+ /* Wait for command completion */
+ start = get_timer (0);
+ while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+ if (get_timer(start) > info->erase_blk_tout) {
+ printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+ return ERR_TIMOUT;
+ }
+ }
+ return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+ int retcode;
+ retcode = flash_status_check(info, sector, tout, prompt);
+ if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+ retcode = ERR_INVAL;
+ printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+ if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+ printf("Command Sequence Error.\n");
+ } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+ printf("Block Erase Error.\n");
+ retcode = ERR_NOT_ERASED;
+ } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+ printf("Locking Error\n");
+ }
+ if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+ printf("Block locked.\n");
+ retcode = ERR_PROTECTED;
+ }
+ if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+ printf("Vpp Low Error.\n");
+ }
+ flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+ return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cword->c = c;
+ break;
+ case FLASH_CFI_16BIT:
+ cword->w = (cword->w << 8) | c;
+ break;
+ case FLASH_CFI_32BIT:
+ cword->l = (cword->l << 8) | c;
+ }
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+ int i;
+ uchar *cp = (uchar *)cmdbuf;
+ for(i=0; i< info->portwidth; i++)
+ *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+ volatile cfiptr_t addr;
+ cfiword_t cword;
+ addr.cp = flash_make_addr(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ *addr.cp = cword.c;
+ break;
+ case FLASH_CFI_16BIT:
+ *addr.wp = cword.w;
+ break;
+ case FLASH_CFI_32BIT:
+ *addr.lp = cword.l;
+ break;
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+ cfiptr_t cptr;
+ cfiword_t cword;
+ int retval;
+ cptr.cp = flash_make_addr(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ retval = (cptr.cp[0] == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ retval = (cptr.wp[0] == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ retval = (cptr.lp[0] == cword.l);
+ break;
+ default:
+ retval = 0;
+ break;
+ }
+ return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+ cfiptr_t cptr;
+ cfiword_t cword;
+ int retval;
+ cptr.cp = flash_make_addr(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ retval = ((cptr.cp[0] & cword.c) == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ retval = ((cptr.wp[0] & cword.w) == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ retval = ((cptr.lp[0] & cword.l) == cword.l);
+ break;
+ default:
+ retval = 0;
+ break;
+ }
+ return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+ for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+ info->portwidth <<= 1) {
+ for(info->chipwidth =FLASH_CFI_BY8;
+ info->chipwidth <= info->portwidth;
+ info->chipwidth <<= 1) {
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+ flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+ if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+ flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+ flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+ return 1;
+ }
+ }
+ return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+ flash_info_t * info = &flash_info[banknum];
+ int i, j;
+ int sect_cnt;
+ unsigned long sector;
+ unsigned long tmp;
+ int size_ratio;
+ uchar num_erase_regions;
+ int erase_region_size;
+ int erase_region_count;
+
+ info->start[0] = base;
+
+ if(flash_detect_cfi(info)){
+#ifdef DEBUG_FLASH
+ printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+ size_ratio = info->portwidth / info->chipwidth;
+ num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+ printf("found %d erase regions\n", num_erase_regions);
+#endif
+ sect_cnt = 0;
+ sector = base;
+ for(i = 0 ; i < num_erase_regions; i++) {
+ if(i > NUM_ERASE_REGIONS) {
+ printf("%d erase regions found, only %d used\n",
+ num_erase_regions, NUM_ERASE_REGIONS);
+ break;
+ }
+ tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+ erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+ tmp >>= 16;
+ erase_region_count = (tmp & 0xffff) +1;
+ for(j = 0; j< erase_region_count; j++) {
+ info->start[sect_cnt] = sector;
+ sector += (erase_region_size * size_ratio);
+ info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+ sect_cnt++;
+ }
+ }
+
+ info->sector_count = sect_cnt;
+ /* multiply the size by the number of chips */
+ info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+ info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+ info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+ info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+ info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+ info->flash_id = FLASH_MAN_CFI;
+ }
+
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+ return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+ cfiptr_t cptr;
+ int flag;
+
+ cptr.cp = (uchar *)dest;
+
+ /* Check if Flash is (sufficiently) erased */
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ flag = ((cptr.cp[0] & cword.c) == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ flag = ((cptr.wp[0] & cword.w) == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ flag = ((cptr.lp[0] & cword.l) == cword.l);
+ break;
+ default:
+ return 2;
+ }
+ if(!flag)
+ return 2;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cptr.cp[0] = cword.c;
+ break;
+ case FLASH_CFI_16BIT:
+ cptr.wp[0] = cword.w;
+ break;
+ case FLASH_CFI_32BIT:
+ cptr.lp[0] = cword.l;
+ break;
+ }
+
+ /* re-enable interrupts if necessary */
+ if(flag)
+ enable_interrupts();
+
+ return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+ int sector;
+ for(sector = info->sector_count - 1; sector >= 0; sector--) {
+ if(addr >= info->start[sector])
+ break;
+ }
+ return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+ int sector;
+ int cnt;
+ int retcode;
+ volatile cfiptr_t src;
+ volatile cfiptr_t dst;
+
+ src.cp = cp;
+ dst.cp = (uchar *)dest;
+ sector = find_sector(info, dest);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+ if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+ "write to buffer")) == ERR_OK) {
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cnt = len;
+ break;
+ case FLASH_CFI_16BIT:
+ cnt = len >> 1;
+ if (len & 0x1) { /* test-only: unaligned size */
+ puts("\nUnalgined size!!!\n"); /* test-only */
+ cnt++;
+ }
+ break;
+ case FLASH_CFI_32BIT:
+ cnt = len >> 2;
+ break;
+ default:
+ return ERR_INVAL;
+ break;
+ }
+ flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+ while(cnt-- > 0) {
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ *dst.cp++ = *src.cp++;
+ break;
+ case FLASH_CFI_16BIT:
+ *dst.wp++ = *src.wp++;
+ break;
+ case FLASH_CFI_32BIT:
+ *dst.lp++ = *src.lp++;
+ break;
+ default:
+ return ERR_INVAL;
+ break;
+ }
+ }
+ flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+ retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+ "buffer write");
+ }
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ return retcode;
+}
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/board/gaisler/gr_cpci_ax2000/Kconfig b/board/gaisler/gr_cpci_ax2000/Kconfig
new file mode 100644
index 0000000..c12a002
--- /dev/null
+++ b/board/gaisler/gr_cpci_ax2000/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_GR_CPCI_AX2000
+
+config SYS_BOARD
+ default "gr_cpci_ax2000"
+
+config SYS_CONFIG_NAME
+ default "gr_cpci_ax2000"
+
+endif
diff --git a/board/gaisler/gr_cpci_ax2000/MAINTAINERS b/board/gaisler/gr_cpci_ax2000/MAINTAINERS
new file mode 100644
index 0000000..df55a4c
--- /dev/null
+++ b/board/gaisler/gr_cpci_ax2000/MAINTAINERS
@@ -0,0 +1,6 @@
+GR_CPCI_AX2000 BOARD
+#M: -
+S: Maintained
+F: board/gaisler/gr_cpci_ax2000/
+F: include/configs/gr_cpci_ax2000.h
+F: configs/gr_cpci_ax2000_defconfig
diff --git a/board/gaisler/gr_cpci_ax2000/Makefile b/board/gaisler/gr_cpci_ax2000/Makefile
new file mode 100644
index 0000000..a08e04d
--- /dev/null
+++ b/board/gaisler/gr_cpci_ax2000/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := gr_cpci_ax2000.o
diff --git a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
new file mode 100644
index 0000000..d26212e
--- /dev/null
+++ b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2008
+ * Daniel Hellstrom, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <config.h>
+#include <asm/leon.h>
+
+phys_size_t initdram(int board_type)
+{
+ return 1;
+}
+
+int checkboard(void)
+{
+ puts("Board: GR-CPCI-AX2000\n");
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/gaisler/gr_ep2s60/Kconfig b/board/gaisler/gr_ep2s60/Kconfig
new file mode 100644
index 0000000..f49937c
--- /dev/null
+++ b/board/gaisler/gr_ep2s60/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_GR_EP2S60
+
+config SYS_BOARD
+ default "gr_ep2s60"
+
+config SYS_CONFIG_NAME
+ default "gr_ep2s60"
+
+endif
diff --git a/board/gaisler/gr_ep2s60/MAINTAINERS b/board/gaisler/gr_ep2s60/MAINTAINERS
new file mode 100644
index 0000000..7acd5f4
--- /dev/null
+++ b/board/gaisler/gr_ep2s60/MAINTAINERS
@@ -0,0 +1,6 @@
+GR_EP2S60 BOARD
+#M: -
+S: Maintained
+F: board/gaisler/gr_ep2s60/
+F: include/configs/gr_ep2s60.h
+F: configs/gr_ep2s60_defconfig
diff --git a/board/gaisler/gr_ep2s60/Makefile b/board/gaisler/gr_ep2s60/Makefile
new file mode 100644
index 0000000..059a9c0
--- /dev/null
+++ b/board/gaisler/gr_ep2s60/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := gr_ep2s60.o
diff --git a/board/gaisler/gr_ep2s60/gr_ep2s60.c b/board/gaisler/gr_ep2s60/gr_ep2s60.c
new file mode 100644
index 0000000..98fb45f
--- /dev/null
+++ b/board/gaisler/gr_ep2s60/gr_ep2s60.c
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2008
+ * Daniel Hellstrom, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <config.h>
+#include <asm/leon.h>
+
+phys_size_t initdram(int board_type)
+{
+ return 1;
+}
+
+int checkboard(void)
+{
+ puts("Board: EP2S60 GRLIB\n");
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/gaisler/gr_xc3s_1500/Kconfig b/board/gaisler/gr_xc3s_1500/Kconfig
new file mode 100644
index 0000000..e695ba2
--- /dev/null
+++ b/board/gaisler/gr_xc3s_1500/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_GR_XC3S_1500
+
+config SYS_BOARD
+ default "gr_xc3s_1500"
+
+config SYS_CONFIG_NAME
+ default "gr_xc3s_1500"
+
+endif
diff --git a/board/gaisler/gr_xc3s_1500/MAINTAINERS b/board/gaisler/gr_xc3s_1500/MAINTAINERS
new file mode 100644
index 0000000..c4179d2
--- /dev/null
+++ b/board/gaisler/gr_xc3s_1500/MAINTAINERS
@@ -0,0 +1,6 @@
+GR_XC3S_1500 BOARD
+#M: -
+S: Maintained
+F: board/gaisler/gr_xc3s_1500/
+F: include/configs/gr_xc3s_1500.h
+F: configs/gr_xc3s_1500_defconfig
diff --git a/board/gaisler/gr_xc3s_1500/Makefile b/board/gaisler/gr_xc3s_1500/Makefile
new file mode 100644
index 0000000..302c461
--- /dev/null
+++ b/board/gaisler/gr_xc3s_1500/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := gr_xc3s_1500.o
diff --git a/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c b/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c
new file mode 100644
index 0000000..32fbbe2
--- /dev/null
+++ b/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2007
+ * Daniel Hellstrom, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/leon.h>
+
+phys_size_t initdram(int board_type)
+{
+ return 1;
+}
+
+int checkboard(void)
+{
+ puts("Board: GR-XC3S-1500\n");
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
diff --git a/board/gaisler/grsim/Kconfig b/board/gaisler/grsim/Kconfig
new file mode 100644
index 0000000..18598d3
--- /dev/null
+++ b/board/gaisler/grsim/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_GRSIM
+
+config SYS_BOARD
+ default "grsim"
+
+config SYS_CONFIG_NAME
+ default "grsim"
+
+endif
diff --git a/board/gaisler/grsim/MAINTAINERS b/board/gaisler/grsim/MAINTAINERS
new file mode 100644
index 0000000..4b3312e
--- /dev/null
+++ b/board/gaisler/grsim/MAINTAINERS
@@ -0,0 +1,6 @@
+GRSIM BOARD
+#M: -
+S: Maintained
+F: board/gaisler/grsim/
+F: include/configs/grsim.h
+F: configs/grsim_defconfig
diff --git a/board/gaisler/grsim/Makefile b/board/gaisler/grsim/Makefile
new file mode 100644
index 0000000..4c93bda
--- /dev/null
+++ b/board/gaisler/grsim/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := grsim.o
diff --git a/board/gaisler/grsim/grsim.c b/board/gaisler/grsim/grsim.c
new file mode 100644
index 0000000..fd73920
--- /dev/null
+++ b/board/gaisler/grsim/grsim.c
@@ -0,0 +1,27 @@
+/*
+ * GRSIM/TSIM board
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/leon.h>
+
+phys_size_t initdram(int board_type)
+{
+ return 1;
+}
+
+int checkboard(void)
+{
+ puts("Board: GRSIM/TSIM\n");
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
diff --git a/board/gaisler/grsim_leon2/Kconfig b/board/gaisler/grsim_leon2/Kconfig
new file mode 100644
index 0000000..0d21a0a
--- /dev/null
+++ b/board/gaisler/grsim_leon2/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_GRSIM_LEON2
+
+config SYS_BOARD
+ default "grsim_leon2"
+
+config SYS_CONFIG_NAME
+ default "grsim_leon2"
+
+endif
diff --git a/board/gaisler/grsim_leon2/MAINTAINERS b/board/gaisler/grsim_leon2/MAINTAINERS
new file mode 100644
index 0000000..bf4a950
--- /dev/null
+++ b/board/gaisler/grsim_leon2/MAINTAINERS
@@ -0,0 +1,6 @@
+GRSIM_LEON2 BOARD
+#M: -
+S: Maintained
+F: board/gaisler/grsim_leon2/
+F: include/configs/grsim_leon2.h
+F: configs/grsim_leon2_defconfig
diff --git a/board/gaisler/grsim_leon2/Makefile b/board/gaisler/grsim_leon2/Makefile
new file mode 100644
index 0000000..5468305
--- /dev/null
+++ b/board/gaisler/grsim_leon2/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := grsim_leon2.o
diff --git a/board/gaisler/grsim_leon2/grsim_leon2.c b/board/gaisler/grsim_leon2/grsim_leon2.c
new file mode 100644
index 0000000..882b0a4
--- /dev/null
+++ b/board/gaisler/grsim_leon2/grsim_leon2.c
@@ -0,0 +1,27 @@
+/*
+ * GRSIM/TSIM board
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/leon.h>
+
+phys_size_t initdram(int board_type)
+{
+ return 1;
+}
+
+int checkboard(void)
+{
+ puts("Board: GRSIM/TSIM LEON2\n");
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
diff --git a/board/galaxy5200/Kconfig b/board/galaxy5200/Kconfig
new file mode 100644
index 0000000..3103581
--- /dev/null
+++ b/board/galaxy5200/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_GALAXY5200
+
+config SYS_BOARD
+ default "galaxy5200"
+
+config SYS_CONFIG_NAME
+ default "galaxy5200"
+
+endif
diff --git a/board/galaxy5200/MAINTAINERS b/board/galaxy5200/MAINTAINERS
new file mode 100644
index 0000000..614625d
--- /dev/null
+++ b/board/galaxy5200/MAINTAINERS
@@ -0,0 +1,7 @@
+GALAXY5200 BOARD
+#M: Eric Millbrandt <emillbrandt@dekaresearch.com>
+S: Orphan (since 2014-06)
+F: board/galaxy5200/
+F: include/configs/galaxy5200.h
+F: configs/galaxy5200_defconfig
+F: configs/galaxy5200_LOWBOOT_defconfig
diff --git a/board/galaxy5200/Makefile b/board/galaxy5200/Makefile
new file mode 100644
index 0000000..e0fcd39
--- /dev/null
+++ b/board/galaxy5200/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := galaxy5200.o
diff --git a/board/galaxy5200/galaxy5200.c b/board/galaxy5200/galaxy5200.c
new file mode 100644
index 0000000..5d957b7
--- /dev/null
+++ b/board/galaxy5200/galaxy5200.c
@@ -0,0 +1,185 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2006
+ * Eric Schumann, Phytec Messtechnik GmbH
+ *
+ * (C) Copyright 2009
+ * Eric Millbrandt, DEKA Research and Development Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/io.h>
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+ volatile struct mpc5xxx_cdm *cdm =
+ (struct mpc5xxx_cdm *)MPC5XXX_CDM;
+ volatile struct mpc5xxx_sdram *sdram =
+ (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ out_be32 (&sdram->ctrl,
+ (SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
+
+ /* precharge all banks */
+ out_be32 (&sdram->ctrl,
+ (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
+
+#ifdef SDRAM_DDR
+ /* set mode register: extended mode */
+ out_be32 (&sdram->mode, (SDRAM_EMODE));
+
+ /* set mode register: reset DLL */
+ out_be32 (&sdram->mode, (SDRAM_MODE | 0x04000000));
+#endif
+
+ /* precharge all banks */
+ out_be32 (&sdram->ctrl,
+ (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
+
+ /* auto refresh */
+ out_be32 (&sdram->ctrl,
+ (SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
+
+ /* set mode register */
+ out_be32 (&sdram->mode, (SDRAM_MODE));
+
+ /* normal operation */
+ out_be32 (&sdram->ctrl,
+ (SDRAM_CONTROL | hi_addr_bit));
+
+ /* set CDM clock enable register, set MPC5200B SDRAM bus */
+ /* to reduced driver strength */
+ out_be32 (&cdm->clock_enable, (0x00CFFFFF));
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make
+ * real use of CONFIG_SYS_SDRAM_BASE. The code does not
+ * work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+ volatile struct mpc5xxx_mmap_ctl *mm =
+ (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+ volatile struct mpc5xxx_sdram *sdram =
+ (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ /* 256MB at 0x0 */
+ out_be32 (&mm->sdram0, 0x0000001b);
+ /* disabled */
+ out_be32 (&mm->sdram1, 0x10000000);
+
+ /* setup config registers */
+ out_be32 (&sdram->config1, SDRAM_CONFIG1);
+ out_be32 (&sdram->config2, SDRAM_CONFIG2);
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else
+ dramsize = test2;
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ out_be32 (&mm->sdram0,
+ (0x13 + __builtin_ffs(dramsize >> 20) - 1));
+ } else {
+ /* disabled */
+ out_be32 (&mm->sdram0, 0);
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = in_be32(&mm->sdram0) & 0xFF;
+ if (dramsize >= 0x13)
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ else
+ dramsize = 0;
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = in_be32(&mm->sdram1) & 0xFF;
+ if (dramsize2 >= 0x13)
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ else
+ dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ return dramsize + dramsize2;
+}
+
+int checkboard(void)
+{
+ puts("Board: galaxy5200\n");
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+ volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
+ debug ("init_ide_reset\n");
+
+ /* Configure TIMER_5 as GPIO output for ATA reset */
+ /* Deassert reset */
+ gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
+}
+
+void ide_set_reset (int idereset)
+{
+ volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
+ debug ("ide_reset(%d)\n", idereset);
+
+ /* Configure TIMER_5 as GPIO output for ATA reset */
+ if (idereset) {
+ gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT0 | MPC5XXX_GPT_TMS_GPIO;
+
+ /* Make a delay. MPC5200 spec says 25 usec min */
+ udelay(50);
+ } else {
+ gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
+ udelay(50);
+ }
+}
+#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
diff --git a/board/gateworks/gw_ventana/Kconfig b/board/gateworks/gw_ventana/Kconfig
new file mode 100644
index 0000000..c233e90
--- /dev/null
+++ b/board/gateworks/gw_ventana/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_GW_VENTANA
+
+config SYS_BOARD
+ default "gw_ventana"
+
+config SYS_VENDOR
+ default "gateworks"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "gw_ventana"
+
+endif
diff --git a/board/gateworks/gw_ventana/MAINTAINERS b/board/gateworks/gw_ventana/MAINTAINERS
new file mode 100644
index 0000000..b44fb4d
--- /dev/null
+++ b/board/gateworks/gw_ventana/MAINTAINERS
@@ -0,0 +1,6 @@
+GW_VENTANA BOARD
+M: Tim Harvey <tharvey@gateworks.com>
+S: Maintained
+F: board/gateworks/gw_ventana/
+F: include/configs/gw_ventana.h
+F: configs/gwventana_defconfig
diff --git a/board/gateworks/gw_ventana/Makefile b/board/gateworks/gw_ventana/Makefile
new file mode 100644
index 0000000..33a1788
--- /dev/null
+++ b/board/gateworks/gw_ventana/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
+# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Gateworks Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := gw_ventana.o gsc.o eeprom.o
+obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o
+
diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README
new file mode 100644
index 0000000..888657c
--- /dev/null
+++ b/board/gateworks/gw_ventana/README
@@ -0,0 +1,83 @@
+U-Boot for the Gateworks Ventana Product Family boards
+
+This file contains information for the port of U-Boot to the Gateworks
+Ventana Product family boards.
+
+1. Secondary Program Loader (SPL)
+---------------------------------
+
+The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading
+an executable image from various boot devices.
+
+The Gateworks Ventana board config uses an SPL build configuration. This
+will build the following artifacts from u-boot source:
+ - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program
+ Loader) boots. This detects CPU/DRAM configuration, configures
+ The DRAM controller, loads u-boot.img from the detected boot device,
+ and jumps to it. As this is booted from the PPL, it has an IVT/DCD
+ table.
+ - u-boot.img - The main u-boot core which is u-boot.bin with a image header.
+
+
+2. Build
+--------
+
+To build U-Boot for the Gateworks Ventana product family:
+
+ make gwventana_config
+ make
+
+
+3. Boot source, boot from NAND
+------------------------------
+
+The i.MX6 BOOT ROM expects some structures that provide details of NAND layout
+and bad block information (referred to as 'bootstreams') which are replicated
+multiple times in NAND. The number of replications and their spacing (referred
+to as search stride) is configurable through board strapping options and/or
+eFUSE settings (BOOT_SEARCH_COUNT / Pages in block from BOOT_CFG2). In
+addition, the i.MX6 BOOT ROM Flash Configuration Block (FCB) supports two
+copies of a bootloader in flash in the case that a bad block has corrupted one.
+The Freescale 'kobs-ng' application from the Freescale LTIB BSP, which runs
+under Linux and operates on an MTD partition, must be used to program the
+bootstream in order to setup this flash structure correctly.
+
+The Gateworks Ventana boards with NAND flash have been factory programmed
+such that their eFUSE settings expect 2 copies of the boostream (this is
+specified by providing kobs-ng with the --search_exponent=1 argument). Once in
+Linux with MTD support for the NAND on /dev/mtd0 you can program the SPL
+with:
+
+kobs-ng init -v -x --search_exponent=1 SPL
+
+The kobs-ng application uses an imximage which contains the Image Vector Table
+(IVT) and Device Configuration Data (DCD) structures that the i.MX6 BOOT ROM
+requires to boot. The kobs-ng adds the Firmware Configuration Block (FCB) and
+Discovered Bad Block Table (DBBT). The SPL build artifact from u-boot is
+an imximage.
+
+The u-boot.img, which is the non SPL u-boot binary appended to a u-boot image
+header must be programmed in the NAND flash boot device at an offset hard
+coded in the SPL. For the Ventana boards, this has been chosen to be 14MB.
+The image can be programmed from either u-boot or Linux:
+
+u-boot:
+Ventana > setenv mtdparts mtdparts=nand:14m(spl),2m(uboot),1m(env),-(rootfs)
+Ventana > tftp ${loadaddr} u-boot.img && nand erase.part uboot && \
+ nand write ${loadaddr} uboot ${filesize}
+
+Linux:
+nandwrite /dev/mtd1 u-boot.img
+
+The above assumes the default Ventana partitioning scheme which is configured
+via the mtdparts env var:
+ - spl: 14MB
+ - uboot: 2M
+ - env: 1M
+ - rootfs: the rest
+
+This information is taken from:
+ http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH
+
+More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
+
diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c
new file mode 100644
index 0000000..ab3bab8
--- /dev/null
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <asm/bitops.h>
+
+#include "gsc.h"
+#include "ventana_eeprom.h"
+
+/* read ventana EEPROM, check for validity, and return baseboard type */
+int
+read_eeprom(int bus, struct ventana_board_info *info)
+{
+ int i;
+ int chksum;
+ char baseboard;
+ int type;
+ unsigned char *buf = (unsigned char *)info;
+
+ memset(info, 0, sizeof(*info));
+
+ /*
+ * On a board with a missing/depleted backup battery for GSC, the
+ * board may be ready to probe the GSC before its firmware is
+ * running. We will wait here indefinately for the GSC/EEPROM.
+ */
+ while (1) {
+ if (0 == i2c_set_bus_num(bus) &&
+ 0 == i2c_probe(GSC_EEPROM_ADDR))
+ break;
+ mdelay(1);
+ }
+
+ /* read eeprom config section */
+ if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) {
+ puts("EEPROM: Failed to read EEPROM\n");
+ return GW_UNKNOWN;
+ }
+
+ /* sanity checks */
+ if (info->model[0] != 'G' || info->model[1] != 'W') {
+ puts("EEPROM: Invalid Model in EEPROM\n");
+ return GW_UNKNOWN;
+ }
+
+ /* validate checksum */
+ for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
+ chksum += buf[i];
+ if ((info->chksum[0] != chksum>>8) ||
+ (info->chksum[1] != (chksum&0xff))) {
+ puts("EEPROM: Failed EEPROM checksum\n");
+ return GW_UNKNOWN;
+ }
+
+ /* original GW5400-A prototype */
+ baseboard = info->model[3];
+ if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
+ baseboard = '0';
+
+ switch (baseboard) {
+ case '0': /* original GW5400-A prototype */
+ type = GW54proto;
+ break;
+ case '1':
+ type = GW51xx;
+ break;
+ case '2':
+ type = GW52xx;
+ break;
+ case '3':
+ type = GW53xx;
+ break;
+ case '4':
+ type = GW54xx;
+ break;
+ case '5':
+ type = GW552x;
+ break;
+ default:
+ printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
+ type = GW_UNKNOWN;
+ break;
+ }
+ return type;
+}
+
+/* list of config bits that the bootloader will remove from dtb if not set */
+struct ventana_eeprom_config econfig[] = {
+ { "eth0", "ethernet0", EECONFIG_ETH0 },
+ { "eth1", "ethernet1", EECONFIG_ETH1 },
+ { "sata", "ahci0", EECONFIG_SATA },
+ { "pcie", NULL, EECONFIG_PCIE},
+ { "lvds0", NULL, EECONFIG_LVDS0 },
+ { "lvds1", NULL, EECONFIG_LVDS1 },
+ { "usb0", NULL, EECONFIG_USB0 },
+ { "usb1", NULL, EECONFIG_USB1 },
+ { "mmc0", NULL, EECONFIG_SD0 },
+ { "mmc1", NULL, EECONFIG_SD1 },
+ { "mmc2", NULL, EECONFIG_SD2 },
+ { "mmc3", NULL, EECONFIG_SD3 },
+ { "uart0", NULL, EECONFIG_UART0 },
+ { "uart1", NULL, EECONFIG_UART1 },
+ { "uart2", NULL, EECONFIG_UART2 },
+ { "uart3", NULL, EECONFIG_UART3 },
+ { "uart4", NULL, EECONFIG_UART4 },
+ { "ipu0", NULL, EECONFIG_IPU0 },
+ { "ipu1", NULL, EECONFIG_IPU1 },
+ { "can0", NULL, EECONFIG_FLEXCAN },
+ { "i2c0", NULL, EECONFIG_I2C0 },
+ { "i2c1", NULL, EECONFIG_I2C1 },
+ { "i2c2", NULL, EECONFIG_I2C2 },
+ { "vpu", NULL, EECONFIG_VPU },
+ { "csi0", NULL, EECONFIG_CSI0 },
+ { "csi1", NULL, EECONFIG_CSI1 },
+ { "spi0", NULL, EECONFIG_ESPCI0 },
+ { "spi1", NULL, EECONFIG_ESPCI1 },
+ { "spi2", NULL, EECONFIG_ESPCI2 },
+ { "spi3", NULL, EECONFIG_ESPCI3 },
+ { "spi4", NULL, EECONFIG_ESPCI4 },
+ { "spi5", NULL, EECONFIG_ESPCI5 },
+ { "gps", "pps", EECONFIG_GPS },
+ { "hdmi_in", NULL, EECONFIG_HDMI_IN },
+ { "hdmi_out", NULL, EECONFIG_HDMI_OUT },
+ { "cvbs_in", NULL, EECONFIG_VID_IN },
+ { "cvbs_out", NULL, EECONFIG_VID_OUT },
+ { "nand", NULL, EECONFIG_NAND },
+ { /* Sentinel */ }
+};
+
+#ifdef CONFIG_CMD_EECONFIG
+static struct ventana_eeprom_config *get_config(const char *name)
+{
+ struct ventana_eeprom_config *cfg = econfig;
+
+ while (cfg->name) {
+ if (0 == strcmp(name, cfg->name))
+ return cfg;
+ cfg++;
+ }
+ return NULL;
+}
+
+static u8 econfig_bytes[sizeof(ventana_info.config)];
+static int econfig_init = -1;
+
+int do_econfig(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct ventana_eeprom_config *cfg;
+ struct ventana_board_info *info = &ventana_info;
+ int i;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ /* initialize */
+ if (econfig_init != 1) {
+ memcpy(econfig_bytes, info->config, sizeof(econfig_bytes));
+ econfig_init = 1;
+ }
+
+ /* list configs */
+ if ((strncmp(argv[1], "list", 4) == 0)) {
+ cfg = econfig;
+ while (cfg->name) {
+ printf("%s: %d\n", cfg->name,
+ test_bit(cfg->bit, econfig_bytes) ? 1 : 0);
+ cfg++;
+ }
+ }
+
+ /* save */
+ else if ((strncmp(argv[1], "save", 4) == 0)) {
+ unsigned char *buf = (unsigned char *)info;
+ int chksum;
+
+ /* calculate new checksum */
+ memcpy(info->config, econfig_bytes, sizeof(econfig_bytes));
+ for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
+ chksum += buf[i];
+ debug("old chksum:0x%04x\n",
+ (info->chksum[0] << 8) | info->chksum[1]);
+ debug("new chksum:0x%04x\n", chksum);
+ info->chksum[0] = chksum >> 8;
+ info->chksum[1] = chksum & 0xff;
+
+ /* write new config data */
+ if (gsc_i2c_write(GSC_EEPROM_ADDR, info->config - (u8 *)info,
+ 1, econfig_bytes, sizeof(econfig_bytes))) {
+ printf("EEPROM: Failed updating config\n");
+ return CMD_RET_FAILURE;
+ }
+
+ /* write new config data */
+ if (gsc_i2c_write(GSC_EEPROM_ADDR, info->chksum - (u8 *)info,
+ 1, info->chksum, 2)) {
+ printf("EEPROM: Failed updating checksum\n");
+ return CMD_RET_FAILURE;
+ }
+
+ printf("Config saved to EEPROM\n");
+ }
+
+ /* get config */
+ else if (argc == 2) {
+ cfg = get_config(argv[1]);
+ if (cfg) {
+ printf("%s: %d\n", cfg->name,
+ test_bit(cfg->bit, econfig_bytes) ? 1 : 0);
+ } else {
+ printf("invalid config: %s\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+ }
+
+ /* set config */
+ else if (argc == 3) {
+ cfg = get_config(argv[1]);
+ if (cfg) {
+ if (simple_strtol(argv[2], NULL, 10)) {
+ test_and_set_bit(cfg->bit, econfig_bytes);
+ printf("Enabled %s\n", cfg->name);
+ } else {
+ test_and_clear_bit(cfg->bit, econfig_bytes);
+ printf("Disabled %s\n", cfg->name);
+ }
+ } else {
+ printf("invalid config: %s\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+ }
+
+ else
+ return CMD_RET_USAGE;
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ econfig, 3, 0, do_econfig,
+ "EEPROM configuration",
+ "list - list config\n"
+ "save - save config to EEPROM\n"
+ "<name> - get config 'name'\n"
+ "<name> [0|1] - set config 'name' to value\n"
+);
+
+#endif /* CONFIG_CMD_EECONFIG */
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
new file mode 100644
index 0000000..a34a9a8
--- /dev/null
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/errno.h>
+#include <common.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#include "gsc.h"
+
+#define MINMAX(n, percent) ((n)*(100-percent)/100), ((n)*(100+percent)/100)
+
+/*
+ * The Gateworks System Controller will fail to ACK a master transaction if
+ * it is busy, which can occur during its 1HZ timer tick while reading ADC's.
+ * When this does occur, it will never be busy long enough to fail more than
+ * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with
+ * 3 retries.
+ */
+int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ int retry = 3;
+ int n = 0;
+ int ret;
+
+ while (n++ < retry) {
+ ret = i2c_read(chip, addr, alen, buf, len);
+ if (!ret)
+ break;
+ debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
+ n, ret);
+ if (ret != -ENODEV)
+ break;
+ mdelay(10);
+ }
+ return ret;
+}
+
+int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ int retry = 3;
+ int n = 0;
+ int ret;
+
+ while (n++ < retry) {
+ ret = i2c_write(chip, addr, alen, buf, len);
+ if (!ret)
+ break;
+ debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
+ n, ret);
+ if (ret != -ENODEV)
+ break;
+ mdelay(10);
+ }
+ mdelay(100);
+ return ret;
+}
+
+#ifdef CONFIG_CMD_GSC
+static void read_hwmon(const char *name, uint reg, uint size, uint low,
+ uint high)
+{
+ unsigned char buf[3];
+ uint ui;
+
+ printf("%-8s:", name);
+ memset(buf, 0, sizeof(buf));
+ if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
+ puts("fRD\n");
+ } else {
+ ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
+ if (ui == 0xffffff)
+ printf("invalid");
+ else if (ui < low)
+ printf("%d Failed - Low", ui);
+ else if (ui > high)
+ printf("%d Failed - High", ui);
+ else
+ printf("%d", ui);
+ }
+ puts("\n");
+}
+
+int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const char *model = getenv("model");
+
+ i2c_set_bus_num(0);
+ read_hwmon("Temp", GSC_HWMON_TEMP, 2, 0, 9000);
+ read_hwmon("VIN", GSC_HWMON_VIN, 3, 8000, 60000);
+ read_hwmon("VBATT", GSC_HWMON_VBATT, 3, 1800, 3500);
+ read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3, MINMAX(3300, 10));
+ read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3, MINMAX(3000, 10));
+ read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3, MINMAX(1500, 10));
+ read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3, MINMAX(5000, 10));
+ read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3, MINMAX(2500, 10));
+ read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3, MINMAX(1800, 10));
+
+ switch (model[3]) {
+ case '1': /* GW51xx */
+ read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
+ read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
+ break;
+ case '2': /* GW52xx */
+ case '3': /* GW53xx */
+ read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
+ read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
+ read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
+ break;
+ case '4': /* GW54xx */
+ read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1375, 10));
+ read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10));
+ read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10));
+ break;
+ case '5': /* GW55xx */
+ read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10));
+ read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10));
+ break;
+ }
+ return 0;
+}
+
+U_BOOT_CMD(gsc, 1, 1, do_gsc,
+ "GSC test",
+ ""
+);
+
+#endif /* CONFIG_CMD_GSC */
diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h
new file mode 100644
index 0000000..da970c3
--- /dev/null
+++ b/board/gateworks/gw_ventana/gsc.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASSEMBLY__
+
+/* i2c slave addresses */
+#define GSC_SC_ADDR 0x20
+#define GSC_RTC_ADDR 0x68
+#define GSC_HWMON_ADDR 0x29
+#define GSC_EEPROM_ADDR 0x51
+
+/* System Controller registers */
+enum {
+ GSC_SC_CTRL0 = 0x00,
+ GSC_SC_CTRL1 = 0x01,
+ GSC_SC_STATUS = 0x0a,
+ GSC_SC_FWVER = 0x0e,
+};
+
+/* System Controller Control1 bits */
+enum {
+ GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable watchdog */
+};
+
+/* System Controller Interrupt bits */
+enum {
+ GSC_SC_IRQ_PB = 0, /* Pushbutton switch */
+ GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */
+ GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */
+ GSC_SC_IRQ_GPIO = 4, /* GPIO change */
+ GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */
+ GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */
+ GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */
+};
+
+/* Hardware Monitor registers */
+enum {
+ GSC_HWMON_TEMP = 0x00,
+ GSC_HWMON_VIN = 0x02,
+ GSC_HWMON_VDD_3P3 = 0x05,
+ GSC_HWMON_VBATT = 0x08,
+ GSC_HWMON_VDD_5P0 = 0x0b,
+ GSC_HWMON_VDD_CORE = 0x0e,
+ GSC_HWMON_VDD_HIGH = 0x14,
+ GSC_HWMON_VDD_DDR = 0x17,
+ GSC_HWMON_VDD_SOC = 0x11,
+ GSC_HWMON_VDD_1P8 = 0x1d,
+ GSC_HWMON_VDD_2P5 = 0x23,
+ GSC_HWMON_VDD_1P0 = 0x20,
+};
+
+/*
+ * I2C transactions to the GSC are done via these functions which
+ * perform retries in the case of a busy GSC NAK'ing the transaction
+ */
+int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len);
+int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len);
+#endif
+
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
new file mode 100644
index 0000000..bb08cd2
--- /dev/null
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -0,0 +1,1540 @@
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/sata.h>
+#include <asm/imx-common/spi.h>
+#include <asm/imx-common/video.h>
+#include <jffs2/load_kernel.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <mtd_node.h>
+#include <netdev.h>
+#include <pci.h>
+#include <power/pmic.h>
+#include <power/ltc3676_pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <fdt_support.h>
+#include <jffs2/load_kernel.h>
+#include <spi_flash.h>
+
+#include "gsc.h"
+#include "ventana_eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO's common to all baseboards */
+#define GP_PHY_RST IMX_GPIO_NR(1, 30)
+#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
+#define GP_SD3_CD IMX_GPIO_NR(7, 0)
+#define GP_RS232_EN IMX_GPIO_NR(2, 11)
+#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
+
+
+/*
+ * EEPROM board info struct populated by read_eeprom so that we only have to
+ * read it once.
+ */
+struct ventana_board_info ventana_info;
+
+int board_type;
+
+/* UART1: Function varies per baseboard */
+iomux_v3_cfg_t const uart1_pads[] = {
+ IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+/* UART2: Serial Console */
+iomux_v3_cfg_t const uart2_pads[] = {
+ IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C1: GSC */
+struct i2c_pads_info mx6q_i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+
+/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
+struct i2c_pads_info mx6q_i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+/* I2C3: Misc/Expansion */
+struct i2c_pads_info mx6q_i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
+ .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+
+/* MMC */
+iomux_v3_cfg_t const usdhc3_pads[] = {
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ /* CD */
+ IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+};
+
+/* ENET */
+iomux_v3_cfg_t const enet_pads[] = {
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ /* PHY nRST */
+ IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
+};
+
+/* NAND */
+iomux_v3_cfg_t const nfc_pads[] = {
+ IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+#ifdef CONFIG_CMD_NAND
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ SETUP_IOMUX_PADS(nfc_pads);
+
+ /* config gpmi and bch clock to 100 MHz */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+static void setup_iomux_enet(void)
+{
+ SETUP_IOMUX_PADS(enet_pads);
+
+ /* toggle PHY_RST# */
+ gpio_direction_output(GP_PHY_RST, 0);
+ mdelay(2);
+ gpio_set_value(GP_PHY_RST, 1);
+}
+
+static void setup_iomux_uart(void)
+{
+ SETUP_IOMUX_PADS(uart1_pads);
+ SETUP_IOMUX_PADS(uart2_pads);
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+iomux_v3_cfg_t const usb_pads[] = {
+ IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
+ IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
+ /* OTG PWR */
+ IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
+};
+
+int board_ehci_hcd_init(int port)
+{
+ struct ventana_board_info *info = &ventana_info;
+
+ SETUP_IOMUX_PADS(usb_pads);
+
+ /* Reset USB HUB (present on GW54xx/GW53xx) */
+ switch (info->model[3]) {
+ case '3': /* GW53xx */
+ case '5': /* GW552x */
+ SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
+ gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
+ mdelay(2);
+ gpio_set_value(IMX_GPIO_NR(1, 9), 1);
+ break;
+ case '4': /* GW54xx */
+ SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
+ gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
+ mdelay(2);
+ gpio_set_value(IMX_GPIO_NR(1, 16), 1);
+ break;
+ }
+
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ if (port)
+ return 0;
+ gpio_set_value(GP_USB_OTG_PWR, on);
+ return 0;
+}
+#endif /* CONFIG_USB_EHCI_MX6 */
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* Card Detect */
+ gpio_direction_input(GP_SD3_CD);
+ return !gpio_get_value(GP_SD3_CD);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ /* Only one USDHC controller on Ventana */
+ SETUP_IOMUX_PADS(usdhc3_pads);
+ usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg.max_bus_width = 4;
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+ /* SS1 */
+ IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+};
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
+}
+
+static void setup_spi(void)
+{
+ gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
+ SETUP_IOMUX_PADS(ecspi1_pads);
+}
+#endif
+
+/* configure eth0 PHY board-specific LED behavior */
+int board_phy_config(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* Marvel 88E1510 */
+ if (phydev->phy_id == 0x1410dd1) {
+ /*
+ * Page 3, Register 16: LED[2:0] Function Control Register
+ * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
+ * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
+ val &= 0xff00;
+ val |= 0x0017;
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
+ }
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+
+#ifdef CONFIG_FEC_MXC
+ if (board_type != GW552x)
+ cpu_eth_init(bis);
+#endif
+
+#ifdef CONFIG_CI_UDC
+ /* For otg ethernet*/
+ usb_eth_initialize(bis);
+#endif
+
+ return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static void enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+ return i2c_set_bus_num(dev->bus) == 0 &&
+ i2c_probe(dev->addr) == 0;
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)
+ IOMUXC_BASE_ADDR;
+
+ /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
+ u32 reg = readl(&iomux->gpr[2]);
+ reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+ writel(reg, &iomux->gpr[2]);
+
+ /* Enable Backlight */
+ SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
+ gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
+}
+
+struct display_info_t const displays[] = {{
+ /* HDMI Output */
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
+ .bus = 2,
+ .addr = 0x4,
+ .pixfmt = IPU_PIX_FMT_LVDS666,
+ .detect = detect_i2c,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "Hannstar-XGA",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+ /* Turn on LDB0,IPU,IPU DI0 clocks */
+ reg = __raw_readl(&mxc_ccm->CCGR3);
+ reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+ writel(reg, &mxc_ccm->CCGR3);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+ |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+ |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ reg = readl(&mxc_ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, &mxc_ccm->cscmr2);
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+ |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+ |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+ |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+ |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+ |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+ |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+
+ /* Backlight CABEN on LVDS connector */
+ SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
+ gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Baseboard specific GPIO
+ */
+
+/* common to add baseboards */
+static iomux_v3_cfg_t const gw_gpio_pads[] = {
+ /* MSATA_EN */
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
+ /* RS232_EN# */
+ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+};
+
+/* prototype */
+static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
+ /* PANLEDG# */
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+ /* PANLEDR# */
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+ /* LOCLED# */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+ /* RS485_EN */
+ IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
+ /* IOEXP_PWREN# */
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+ /* IOEXP_IRQ# */
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+ /* VID_EN */
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+ /* DIOI2C_DIS# */
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+ /* PCICK_SSON */
+ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
+ /* PCI_RST# */
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
+ /* PANLEDG# */
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+ /* PANLEDR# */
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+ /* IOEXP_PWREN# */
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+ /* IOEXP_IRQ# */
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+
+ /* GPS_SHDN */
+ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+ /* VID_PWR */
+ IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
+ /* PCI_RST# */
+ IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
+ /* PANLEDG# */
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+ /* PANLEDR# */
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+ /* IOEXP_PWREN# */
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+ /* IOEXP_IRQ# */
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+
+ /* MX6_LOCLED# */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+ /* GPS_SHDN */
+ IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
+ /* USBOTG_SEL */
+ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+ /* VID_PWR */
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+ /* PCI_RST# */
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
+ /* PANLEDG# */
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+ /* PANLEDR# */
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+ /* MX6_LOCLED# */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+ /* IOEXP_PWREN# */
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+ /* IOEXP_IRQ# */
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+ /* DIOI2C_DIS# */
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+ /* GPS_SHDN */
+ IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
+ /* VID_EN */
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+ /* PCI_RST# */
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
+ /* PANLEDG# */
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+ /* PANLEDR# */
+ IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
+ /* MX6_LOCLED# */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+ /* MIPI_DIO */
+ IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
+ /* RS485_EN */
+ IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
+ /* IOEXP_PWREN# */
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+ /* IOEXP_IRQ# */
+ IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+ /* DIOI2C_DIS# */
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+ /* PCICK_SSON */
+ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
+ /* PCI_RST# */
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+ /* VID_EN */
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
+ /* PANLEDG# */
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+ /* PANLEDR# */
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+ /* MX6_LOCLED# */
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+ /* PCI_RST# */
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+ /* MX6_DIO[4:9] */
+ IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
+ IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
+ IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
+ IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
+ IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
+ IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
+ /* PCIEGBE1_OFF# */
+ IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
+ /* PCIEGBE2_OFF# */
+ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+};
+
+/*
+ * each baseboard has 4 user configurable Digital IO lines which can
+ * be pinmuxed as a GPIO or in some cases a PWM
+ */
+struct dio_cfg {
+ iomux_v3_cfg_t gpio_padmux[2];
+ unsigned gpio_param;
+ iomux_v3_cfg_t pwm_padmux[2];
+ unsigned pwm_param;
+};
+
+struct ventana {
+ /* pinmux */
+ iomux_v3_cfg_t const *gpio_pads;
+ int num_pads;
+ /* DIO pinmux/val */
+ struct dio_cfg dio_cfg[4];
+ /* various gpios (0 if non-existent) */
+ int leds[3];
+ int pcie_rst;
+ int mezz_pwren;
+ int mezz_irq;
+ int rs485en;
+ int gps_shdn;
+ int vidin_en;
+ int dioi2c_en;
+ int pcie_sson;
+ int usb_sel;
+ int wdis;
+};
+
+struct ventana gpio_cfg[] = {
+ /* GW5400proto */
+ {
+ .gpio_pads = gw54xx_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
+ .dio_cfg = {
+ {
+ { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
+ IMX_GPIO_NR(1, 9),
+ { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
+ 1
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
+ IMX_GPIO_NR(2, 9),
+ { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
+ IMX_GPIO_NR(2, 10),
+ { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
+ 4
+ },
+ },
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 10),
+ IMX_GPIO_NR(4, 15),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 29),
+ .mezz_pwren = IMX_GPIO_NR(4, 7),
+ .mezz_irq = IMX_GPIO_NR(4, 9),
+ .rs485en = IMX_GPIO_NR(3, 24),
+ .dioi2c_en = IMX_GPIO_NR(4, 5),
+ .pcie_sson = IMX_GPIO_NR(1, 20),
+ },
+
+ /* GW51xx */
+ {
+ .gpio_pads = gw51xx_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
+ .dio_cfg = {
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
+ IMX_GPIO_NR(1, 18),
+ { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
+ 4
+ },
+ },
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 10),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 0),
+ .mezz_pwren = IMX_GPIO_NR(2, 19),
+ .mezz_irq = IMX_GPIO_NR(2, 18),
+ .gps_shdn = IMX_GPIO_NR(1, 2),
+ .vidin_en = IMX_GPIO_NR(5, 20),
+ .wdis = IMX_GPIO_NR(7, 12),
+ },
+
+ /* GW52xx */
+ {
+ .gpio_pads = gw52xx_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
+ .dio_cfg = {
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+ IMX_GPIO_NR(1, 20),
+ { 0, 0 },
+ 0
+ },
+ },
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 7),
+ IMX_GPIO_NR(4, 15),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 29),
+ .mezz_pwren = IMX_GPIO_NR(2, 19),
+ .mezz_irq = IMX_GPIO_NR(2, 18),
+ .gps_shdn = IMX_GPIO_NR(1, 27),
+ .vidin_en = IMX_GPIO_NR(3, 31),
+ .usb_sel = IMX_GPIO_NR(1, 2),
+ .wdis = IMX_GPIO_NR(7, 12),
+ },
+
+ /* GW53xx */
+ {
+ .gpio_pads = gw53xx_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
+ .dio_cfg = {
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+ IMX_GPIO_NR(1, 20),
+ { 0, 0 },
+ 0
+ },
+ },
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 7),
+ IMX_GPIO_NR(4, 15),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 29),
+ .mezz_pwren = IMX_GPIO_NR(2, 19),
+ .mezz_irq = IMX_GPIO_NR(2, 18),
+ .gps_shdn = IMX_GPIO_NR(1, 27),
+ .vidin_en = IMX_GPIO_NR(3, 31),
+ .wdis = IMX_GPIO_NR(7, 12),
+ },
+
+ /* GW54xx */
+ {
+ .gpio_pads = gw54xx_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
+ .dio_cfg = {
+ {
+ { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
+ IMX_GPIO_NR(1, 9),
+ { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
+ 1
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
+ IMX_GPIO_NR(2, 9),
+ { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
+ IMX_GPIO_NR(2, 10),
+ { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
+ 4
+ },
+ },
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 7),
+ IMX_GPIO_NR(4, 15),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 29),
+ .mezz_pwren = IMX_GPIO_NR(2, 19),
+ .mezz_irq = IMX_GPIO_NR(2, 18),
+ .rs485en = IMX_GPIO_NR(7, 1),
+ .vidin_en = IMX_GPIO_NR(3, 31),
+ .dioi2c_en = IMX_GPIO_NR(4, 5),
+ .pcie_sson = IMX_GPIO_NR(1, 20),
+ .wdis = IMX_GPIO_NR(5, 17),
+ },
+
+ /* GW552x */
+ {
+ .gpio_pads = gw552x_gpio_pads,
+ .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
+ .dio_cfg = {
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+ IMX_GPIO_NR(2, 10),
+ { 0, 0 },
+ 0
+ },
+ },
+ .leds = {
+ IMX_GPIO_NR(4, 6),
+ IMX_GPIO_NR(4, 7),
+ IMX_GPIO_NR(4, 15),
+ },
+ .pcie_rst = IMX_GPIO_NR(1, 29),
+ },
+};
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+ struct pmic *p;
+ u32 reg;
+
+ /* configure PFUZE100 PMIC */
+ if (board_type == GW54xx || board_type == GW54proto) {
+ power_pfuze100_init(CONFIG_I2C_PMIC);
+ p = pmic_get("PFUZE100");
+ if (p && !pmic_probe(p)) {
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ /* Set VGEN1 to 1.5V and enable */
+ pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
+ reg &= ~(LDO_VOL_MASK);
+ reg |= (LDOA_1_50V | LDO_EN);
+ pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
+
+ /* Set SWBST to 5.0V and enable */
+ pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
+ reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
+ reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
+ pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
+ }
+ }
+
+ /* configure LTC3676 PMIC */
+ else {
+ power_ltc3676_init(CONFIG_I2C_PMIC);
+ p = pmic_get("LTC3676_PMIC");
+ if (p && !pmic_probe(p)) {
+ puts("PMIC: LTC3676\n");
+ /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
+ if (is_cpu_type(MXC_CPU_MX6Q)) {
+ /* mask PGOOD during SW1 transition */
+ reg = 0x1d | LTC3676_PGOOD_MASK;
+ pmic_reg_write(p, LTC3676_DVB1B, reg);
+ /* set SW1 (VDD_SOC) to 1259mV */
+ reg = 0x1d;
+ pmic_reg_write(p, LTC3676_DVB1A, reg);
+
+ /* mask PGOOD during SW3 transition */
+ reg = 0x1d | LTC3676_PGOOD_MASK;
+ pmic_reg_write(p, LTC3676_DVB3B, reg);
+ /*set SW3 (VDD_ARM) to 1259mV */
+ reg = 0x1d;
+ pmic_reg_write(p, LTC3676_DVB3A, reg);
+ }
+ }
+ }
+
+ return 0;
+}
+
+/* setup GPIO pinmux and default configuration per baseboard */
+static void setup_board_gpio(int board)
+{
+ struct ventana_board_info *info = &ventana_info;
+ const char *s;
+ char arg[10];
+ size_t len;
+ int i;
+ int quiet = simple_strtol(getenv("quiet"), NULL, 10);
+
+ if (board >= GW_UNKNOWN)
+ return;
+
+ /* RS232_EN# */
+ gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
+
+ /* MSATA Enable */
+ if (is_cpu_type(MXC_CPU_MX6Q) &&
+ test_bit(EECONFIG_SATA, info->config)) {
+ gpio_direction_output(GP_MSATA_SEL,
+ (hwconfig("msata")) ? 1 : 0);
+ } else {
+ gpio_direction_output(GP_MSATA_SEL, 0);
+ }
+
+#if !defined(CONFIG_CMD_PCI)
+ /* assert PCI_RST# (released by OS when clock is valid) */
+ gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
+#endif
+
+ /* turn off (active-high) user LED's */
+ for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
+ if (gpio_cfg[board].leds[i])
+ gpio_direction_output(gpio_cfg[board].leds[i], 1);
+ }
+
+ /* Expansion Mezzanine IO */
+ if (gpio_cfg[board].mezz_pwren)
+ gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
+ if (gpio_cfg[board].mezz_irq)
+ gpio_direction_input(gpio_cfg[board].mezz_irq);
+
+ /* RS485 Transmit Enable */
+ if (gpio_cfg[board].rs485en)
+ gpio_direction_output(gpio_cfg[board].rs485en, 0);
+
+ /* GPS_SHDN */
+ if (gpio_cfg[board].gps_shdn)
+ gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
+
+ /* Analog video codec power enable */
+ if (gpio_cfg[board].vidin_en)
+ gpio_direction_output(gpio_cfg[board].vidin_en, 1);
+
+ /* DIOI2C_DIS# */
+ if (gpio_cfg[board].dioi2c_en)
+ gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
+
+ /* PCICK_SSON: disable spread-spectrum clock */
+ if (gpio_cfg[board].pcie_sson)
+ gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
+
+ /* USBOTG Select (PCISKT or FrontPanel) */
+ if (gpio_cfg[board].usb_sel)
+ gpio_direction_output(gpio_cfg[board].usb_sel, 0);
+
+ /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
+ if (gpio_cfg[board].wdis)
+ gpio_direction_output(gpio_cfg[board].wdis, 1);
+
+ /*
+ * Configure DIO pinmux/padctl registers
+ * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
+ */
+ for (i = 0; i < 4; i++) {
+ struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
+ iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
+ unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
+
+ sprintf(arg, "dio%d", i);
+ if (!hwconfig(arg))
+ continue;
+ s = hwconfig_subarg(arg, "padctrl", &len);
+ if (s) {
+ ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
+ & 0x1ffff) | MUX_MODE_SION;
+ }
+ if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
+ if (!quiet) {
+ printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
+ (cfg->gpio_param/32)+1,
+ cfg->gpio_param%32,
+ cfg->gpio_param);
+ }
+ imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
+ ctrl);
+ gpio_direction_input(cfg->gpio_param);
+ } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
+ cfg->pwm_padmux) {
+ if (!quiet)
+ printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
+ imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
+ MUX_PAD_CTRL(ctrl));
+ }
+ }
+
+ if (!quiet) {
+ if (is_cpu_type(MXC_CPU_MX6Q) &&
+ (test_bit(EECONFIG_SATA, info->config))) {
+ printf("MSATA: %s\n", (hwconfig("msata") ?
+ "enabled" : "disabled"));
+ }
+ printf("RS232: %s\n", (hwconfig("rs232")) ?
+ "enabled" : "disabled");
+ }
+}
+
+#if defined(CONFIG_CMD_PCI)
+int imx6_pcie_toggle_reset(void)
+{
+ if (board_type < GW_UNKNOWN) {
+ uint pin = gpio_cfg[board_type].pcie_rst;
+ gpio_direction_output(pin, 0);
+ mdelay(50);
+ gpio_direction_output(pin, 1);
+ }
+ return 0;
+}
+
+/*
+ * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
+ * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
+ * properly and assert reset for 100ms.
+ */
+void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
+ unsigned short vendor, unsigned short device,
+ unsigned short class)
+{
+ u32 dw;
+
+ debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
+ PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
+ if (vendor == PCI_VENDOR_ID_PLX &&
+ (device & 0xfff0) == 0x8600 &&
+ PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
+ debug("configuring PLX 860X downstream PERST#\n");
+ pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
+ dw |= 0xaaa8; /* GPIO1-7 outputs */
+ pci_hose_write_config_dword(hose, dev, 0x62c, dw);
+
+ pci_hose_read_config_dword(hose, dev, 0x644, &dw);
+ dw |= 0xfe; /* GPIO1-7 output high */
+ pci_hose_write_config_dword(hose, dev, 0x644, dw);
+
+ mdelay(100);
+ }
+}
+#endif /* CONFIG_CMD_PCI */
+
+#ifdef CONFIG_SERIAL_TAG
+/*
+ * called when setting up ATAGS before booting kernel
+ * populate serialnum from the following (in order of priority):
+ * serial# env var
+ * eeprom
+ */
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial = getenv("serial#");
+
+ if (serial) {
+ serialnr->high = 0;
+ serialnr->low = simple_strtoul(serial, NULL, 10);
+ } else if (ventana_info.model[0]) {
+ serialnr->high = 0;
+ serialnr->low = ventana_info.serial;
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+#endif
+
+/*
+ * Board Support
+ */
+
+/* called from SPL board_init_f() */
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
+
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
+
+int board_init(void)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ clrsetbits_le32(&iomuxc_regs->gpr[1],
+ IOMUXC_GPR1_OTG_ID_MASK,
+ IOMUXC_GPR1_OTG_ID_GPIO1);
+
+ /* address of linux boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ setup_gpmi_nand();
+#endif
+#ifdef CONFIG_MXC_SPI
+ setup_spi();
+#endif
+ if (is_cpu_type(MXC_CPU_MX6Q)) {
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
+ } else {
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
+ }
+
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+ /* read Gateworks EEPROM into global struct (used later) */
+ board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+
+ /* board-specifc GPIO iomux */
+ SETUP_IOMUX_PADS(gw_gpio_pads);
+ if (board_type < GW_UNKNOWN) {
+ iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
+ int count = gpio_cfg[board_type].num_pads;
+
+ imx_iomux_v3_setup_multiple_pads(p, count);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
+/*
+ * called during late init (after relocation and after board_init())
+ * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
+ * EEPROM read.
+ */
+int checkboard(void)
+{
+ struct ventana_board_info *info = &ventana_info;
+ unsigned char buf[4];
+ const char *p;
+ int quiet; /* Quiet or minimal output mode */
+
+ quiet = 0;
+ p = getenv("quiet");
+ if (p)
+ quiet = simple_strtol(p, NULL, 10);
+ else
+ setenv("quiet", "0");
+
+ puts("\nGateworks Corporation Copyright 2014\n");
+ if (info->model[0]) {
+ printf("Model: %s\n", info->model);
+ printf("MFGDate: %02x-%02x-%02x%02x\n",
+ info->mfgdate[0], info->mfgdate[1],
+ info->mfgdate[2], info->mfgdate[3]);
+ printf("Serial:%d\n", info->serial);
+ } else {
+ puts("Invalid EEPROM - board will not function fully\n");
+ }
+ if (quiet)
+ return 0;
+
+ /* Display GSC firmware revision/CRC/status */
+ i2c_set_bus_num(CONFIG_I2C_GSC);
+ if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
+ printf("GSC: v%d", buf[0]);
+ if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
+ printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
+ printf(" 0x%02x", buf[0]); /* irq status */
+ }
+ puts("\n");
+ }
+ /* Display RTC */
+ if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
+ printf("RTC: %d\n",
+ buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+/*
+ * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
+ * see Table 8-11 and Table 5-9
+ * BOOT_CFG1[7] = 1 (boot from NAND)
+ * BOOT_CFG1[5] = 0 - raw NAND
+ * BOOT_CFG1[4] = 0 - default pad settings
+ * BOOT_CFG1[3:2] = 00 - devices = 1
+ * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
+ * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
+ * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
+ * BOOT_CFG2[0] = 0 - Reset time 12ms
+ */
+static const struct boot_mode board_boot_modes[] = {
+ /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
+ { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
+ { NULL, 0 },
+};
+#endif
+
+/* late init */
+int misc_init_r(void)
+{
+ struct ventana_board_info *info = &ventana_info;
+ unsigned char reg;
+
+ /* set env vars based on EEPROM data */
+ if (ventana_info.model[0]) {
+ char str[16], fdt[36];
+ char *p;
+ const char *cputype = "";
+ int i;
+
+ /*
+ * FDT name will be prefixed with CPU type. Three versions
+ * will be created each increasingly generic and bootloader
+ * env scripts will try loading each from most specific to
+ * least.
+ */
+ if (is_cpu_type(MXC_CPU_MX6Q) ||
+ is_cpu_type(MXC_CPU_MX6D))
+ cputype = "imx6q";
+ else if (is_cpu_type(MXC_CPU_MX6DL) ||
+ is_cpu_type(MXC_CPU_MX6SOLO))
+ cputype = "imx6dl";
+ setenv("soctype", cputype);
+ if (8 << (ventana_info.nand_flash_size-1) >= 2048)
+ setenv("flash_layout", "large");
+ else
+ setenv("flash_layout", "normal");
+ memset(str, 0, sizeof(str));
+ for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
+ str[i] = tolower(info->model[i]);
+ if (!getenv("model"))
+ setenv("model", str);
+ if (!getenv("fdt_file")) {
+ sprintf(fdt, "%s-%s.dtb", cputype, str);
+ setenv("fdt_file", fdt);
+ }
+ p = strchr(str, '-');
+ if (p) {
+ *p++ = 0;
+
+ setenv("model_base", str);
+ if (!getenv("fdt_file1")) {
+ sprintf(fdt, "%s-%s.dtb", cputype, str);
+ setenv("fdt_file1", fdt);
+ }
+ if (board_type != GW552x)
+ str[4] = 'x';
+ str[5] = 'x';
+ str[6] = 0;
+ if (!getenv("fdt_file2")) {
+ sprintf(fdt, "%s-%s.dtb", cputype, str);
+ setenv("fdt_file2", fdt);
+ }
+ }
+
+ /* initialize env from EEPROM */
+ if (test_bit(EECONFIG_ETH0, info->config) &&
+ !getenv("ethaddr")) {
+ eth_setenv_enetaddr("ethaddr", info->mac0);
+ }
+ if (test_bit(EECONFIG_ETH1, info->config) &&
+ !getenv("eth1addr")) {
+ eth_setenv_enetaddr("eth1addr", info->mac1);
+ }
+
+ /* board serial-number */
+ sprintf(str, "%6d", info->serial);
+ setenv("serial#", str);
+ }
+
+
+ /* setup baseboard specific GPIO pinmux and config */
+ setup_board_gpio(board_type);
+
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ /*
+ * The Gateworks System Controller implements a boot
+ * watchdog (always enabled) as a workaround for IMX6 boot related
+ * errata such as:
+ * ERR005768 - no fix scheduled
+ * ERR006282 - fixed in silicon r1.2
+ * ERR007117 - fixed in silicon r1.3
+ * ERR007220 - fixed in silicon r1.3
+ * ERR007926 - no fix scheduled
+ * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
+ *
+ * Disable the boot watchdog and display/clear the timeout flag if set
+ */
+ i2c_set_bus_num(CONFIG_I2C_GSC);
+ if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) {
+ reg |= (1 << GSC_SC_CTRL1_WDDIS);
+ if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
+ puts("Error: could not disable GSC Watchdog\n");
+ } else {
+ puts("Error: could not disable GSC Watchdog\n");
+ }
+ if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) {
+ if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
+ puts("GSC boot watchdog timeout detected\n");
+ reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
+ gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1);
+ }
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+
+/*
+ * called prior to booting kernel or by 'fdt boardsetup' command
+ *
+ * unless 'fdt_noauto' env var is set we will update the following in the DTB:
+ * - mtd partitions based on mtdparts/mtdids env
+ * - system-serial (board serial num from EEPROM)
+ * - board (full model from EEPROM)
+ * - peripherals removed from DTB if not loaded on board (per EEPROM config)
+ */
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ struct ventana_board_info *info = &ventana_info;
+ struct ventana_eeprom_config *cfg;
+ struct node_info nodes[] = {
+ { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
+ { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+ };
+ const char *model = getenv("model");
+
+ if (getenv("fdt_noauto")) {
+ puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
+ return 0;
+ }
+
+ /* Update partition nodes using info from mtdparts env var */
+ puts(" Updating MTD partitions...\n");
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+ if (!model) {
+ puts("invalid board info: Leaving FDT fully enabled\n");
+ return 0;
+ }
+ printf(" Adjusting FDT per EEPROM for %s...\n", model);
+
+ /* board serial number */
+ fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
+ strlen(getenv("serial#")) + 1);
+
+ /* board (model contains model from device-tree) */
+ fdt_setprop(blob, 0, "board", info->model,
+ strlen((const char *)info->model) + 1);
+
+ /*
+ * Peripheral Config:
+ * remove nodes by alias path if EEPROM config tells us the
+ * peripheral is not loaded on the board.
+ */
+ if (getenv("fdt_noconfig")) {
+ puts(" Skiping periperhal config (fdt_noconfig defined)\n");
+ return 0;
+ }
+ cfg = econfig;
+ while (cfg->name) {
+ if (!test_bit(cfg->bit, info->config)) {
+ fdt_del_node_and_alias(blob, cfg->dtalias ?
+ cfg->dtalias : cfg->name);
+ }
+ cfg++;
+ }
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
new file mode 100644
index 0000000..9712812
--- /dev/null
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -0,0 +1,469 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <spl.h>
+
+#include "ventana_eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
+#define I2C_GSC 0
+#define GSC_EEPROM_ADDR 0x51
+#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
+#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* I2C1: GSC */
+static struct i2c_pads_info mx6q_i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+
+static void i2c_setup_iomux(void)
+{
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
+ else
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
+}
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+ /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+ .dram_sdclk_0 = 0x00020030,
+ .dram_sdclk_1 = 0x00020030,
+ .dram_cas = 0x00020030,
+ .dram_ras = 0x00020030,
+ .dram_reset = 0x00020030,
+ /* SDCKE[0:1]: 100k pull-up */
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ /* SDBA2: pull-up disabled */
+ .dram_sdba2 = 0x00000000,
+ /* SDODT[0:1]: 100k pull-up, 40 ohm */
+ .dram_sdodt0 = 0x00003030,
+ .dram_sdodt1 = 0x00003030,
+ /* SDQS[0:7]: Differential input, 40 ohm */
+ .dram_sdqs0 = 0x00000030,
+ .dram_sdqs1 = 0x00000030,
+ .dram_sdqs2 = 0x00000030,
+ .dram_sdqs3 = 0x00000030,
+ .dram_sdqs4 = 0x00000030,
+ .dram_sdqs5 = 0x00000030,
+ .dram_sdqs6 = 0x00000030,
+ .dram_sdqs7 = 0x00000030,
+
+ /* DQM[0:7]: Differential input, 40 ohm */
+ .dram_dqm0 = 0x00020030,
+ .dram_dqm1 = 0x00020030,
+ .dram_dqm2 = 0x00020030,
+ .dram_dqm3 = 0x00020030,
+ .dram_dqm4 = 0x00020030,
+ .dram_dqm5 = 0x00020030,
+ .dram_dqm6 = 0x00020030,
+ .dram_dqm7 = 0x00020030,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+ /* DDR3 */
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ /* disable DDR pullups */
+ .grp_ddrpke = 0x00000000,
+ /* ADDR[00:16], SDBA[0:1]: 40 ohm */
+ .grp_addds = 0x00000030,
+ /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+ .grp_ctlds = 0x00000030,
+ /* DATA[00:63]: Differential input, 40 ohm */
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_b2ds = 0x00000030,
+ .grp_b3ds = 0x00000030,
+ .grp_b4ds = 0x00000030,
+ .grp_b5ds = 0x00000030,
+ .grp_b6ds = 0x00000030,
+ .grp_b7ds = 0x00000030,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+ /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+ .dram_sdclk_0 = 0x00020030,
+ .dram_sdclk_1 = 0x00020030,
+ .dram_cas = 0x00020030,
+ .dram_ras = 0x00020030,
+ .dram_reset = 0x00020030,
+ /* SDCKE[0:1]: 100k pull-up */
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ /* SDBA2: pull-up disabled */
+ .dram_sdba2 = 0x00000000,
+ /* SDODT[0:1]: 100k pull-up, 40 ohm */
+ .dram_sdodt0 = 0x00003030,
+ .dram_sdodt1 = 0x00003030,
+ /* SDQS[0:7]: Differential input, 40 ohm */
+ .dram_sdqs0 = 0x00000030,
+ .dram_sdqs1 = 0x00000030,
+ .dram_sdqs2 = 0x00000030,
+ .dram_sdqs3 = 0x00000030,
+ .dram_sdqs4 = 0x00000030,
+ .dram_sdqs5 = 0x00000030,
+ .dram_sdqs6 = 0x00000030,
+ .dram_sdqs7 = 0x00000030,
+
+ /* DQM[0:7]: Differential input, 40 ohm */
+ .dram_dqm0 = 0x00020030,
+ .dram_dqm1 = 0x00020030,
+ .dram_dqm2 = 0x00020030,
+ .dram_dqm3 = 0x00020030,
+ .dram_dqm4 = 0x00020030,
+ .dram_dqm5 = 0x00020030,
+ .dram_dqm6 = 0x00020030,
+ .dram_dqm7 = 0x00020030,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ /* DDR3 */
+ .grp_ddr_type = 0x000c0000,
+ /* SDQS[0:7]: Differential input, 40 ohm */
+ .grp_ddrmode_ctl = 0x00020000,
+ /* disable DDR pullups */
+ .grp_ddrpke = 0x00000000,
+ /* ADDR[00:16], SDBA[0:1]: 40 ohm */
+ .grp_addds = 0x00000030,
+ /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+ .grp_ctlds = 0x00000030,
+ /* DATA[00:63]: Differential input, 40 ohm */
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_b2ds = 0x00000030,
+ .grp_b3ds = 0x00000030,
+ .grp_b4ds = 0x00000030,
+ .grp_b5ds = 0x00000030,
+ .grp_b6ds = 0x00000030,
+ .grp_b7ds = 0x00000030,
+};
+
+/* MT41K128M16JT-125 */
+static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+ .mem_speed = 1600,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+/* MT41K256M16HA-125 */
+static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+/*
+ * calibration - these are the various CPU/DDR3 combinations we support
+ */
+
+static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00190017,
+ .p0_mpwldectrl1 = 0x00140026,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x43380347,
+ .p0_mpdgctrl1 = 0x433C034D,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x3C313539,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x36393C39,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x003C003C,
+ .p0_mpwldectrl1 = 0x001F002A,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x42410244,
+ .p0_mpdgctrl1 = 0x4234023A,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x484A4C4B,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x33342B32,
+};
+
+static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00190017,
+ .p0_mpwldectrl1 = 0x00140026,
+ .p1_mpwldectrl0 = 0x0021001C,
+ .p1_mpwldectrl1 = 0x0011001D,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x43380347,
+ .p0_mpdgctrl1 = 0x433C034D,
+ .p1_mpdgctrl0 = 0x032C0324,
+ .p1_mpdgctrl1 = 0x03310232,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x3C313539,
+ .p1_mprddlctl = 0x37343141,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x36393C39,
+ .p1_mpwrdlctl = 0x42344438,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x003C003C,
+ .p0_mpwldectrl1 = 0x001F002A,
+ .p1_mpwldectrl0 = 0x00330038,
+ .p1_mpwldectrl1 = 0x0022003F,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x42410244,
+ .p0_mpdgctrl1 = 0x4234023A,
+ .p1_mpdgctrl0 = 0x022D022D,
+ .p1_mpdgctrl1 = 0x021C0228,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x484A4C4B,
+ .p1_mprddlctl = 0x4B4D4E4B,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x33342B32,
+ .p1_mpwrdlctl = 0x3933332B,
+};
+
+static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x001E001A,
+ .p0_mpwldectrl1 = 0x0026001F,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x43370349,
+ .p0_mpdgctrl1 = 0x032D0327,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x3D303639,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x32363934,
+};
+
+static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0X00220021,
+ .p0_mpwldectrl1 = 0X00200030,
+ .p1_mpwldectrl0 = 0X002D0027,
+ .p1_mpwldectrl1 = 0X00150026,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x43330342,
+ .p0_mpdgctrl1 = 0x0339034A,
+ .p1_mpdgctrl0 = 0x032F0325,
+ .p1_mpdgctrl1 = 0x032F022E,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0X3A2E3437,
+ .p1_mprddlctl = 0X35312F3F,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0X33363B37,
+ .p1_mpwrdlctl = 0X40304239,
+};
+
+static void spl_dram_init(int width, int size_mb, int board_model)
+{
+ struct mx6_ddr3_cfg *mem = NULL;
+ struct mx6_mmdc_calibration *calib = NULL;
+ struct mx6_ddr_sysinfo sysinfo = {
+ /* width of data bus:0=16,1=32,2=64 */
+ .dsize = width/32,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32, /* 32Gb per CS */
+ /* single chip select */
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
+#ifdef RTT_NOM_120OHM
+ .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
+#else
+ .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
+#endif
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ };
+
+ /*
+ * MMDC Calibration requires the following data:
+ * mx6_mmdc_calibration - board-specific calibration (routing delays)
+ * these calibration values depend on board routing, SoC, and DDR
+ * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
+ * mx6_ddr_cfg - chip specific timing/layout details
+ */
+ if (width == 32 && size_mb == 512) {
+ mem = &mt41k128m16jt_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_128x32_mmdc_calib;
+ else
+ calib = &mx6sdl_128x32_mmdc_calib;
+ debug("2gB density\n");
+ } else if (width == 64 && size_mb == 1024) {
+ mem = &mt41k128m16jt_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_128x64_mmdc_calib;
+ else
+ calib = &mx6sdl_128x64_mmdc_calib;
+ debug("2gB density\n");
+ } else if (width == 32 && size_mb == 1024) {
+ mem = &mt41k256m16ha_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_256x32_mmdc_calib;
+ debug("4gB density\n");
+ } else if (width == 64 && size_mb == 2048) {
+ mem = &mt41k256m16ha_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_256x64_mmdc_calib;
+ debug("4gB density\n");
+ }
+
+ if (!mem) {
+ puts("Error: Invalid Memory Configuration\n");
+ hang();
+ }
+ if (!calib) {
+ puts("Error: Invalid Board Calibration Configuration\n");
+ hang();
+ }
+
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
+ &mx6dq_grp_ioregs);
+ else
+ mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
+ &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, calib, mem);
+}
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+ struct ventana_board_info ventana_info;
+ int board_model;
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+ gpr_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+ i2c_setup_iomux();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* read/validate EEPROM info to determine board model and SDRAM cfg */
+ board_model = read_eeprom(I2C_GSC, &ventana_info);
+
+ /* provide some some default: 32bit 128MB */
+ if (GW_UNKNOWN == board_model) {
+ ventana_info.sdram_width = 2;
+ ventana_info.sdram_size = 3;
+ }
+
+ /* configure MMDC for SDRAM width/size and per-model calibration */
+ spl_dram_init(8 << ventana_info.sdram_width,
+ 16 << ventana_info.sdram_size,
+ board_model);
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h
new file mode 100644
index 0000000..af12711
--- /dev/null
+++ b/board/gateworks/gw_ventana/ventana_eeprom.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _VENTANA_EEPROM_
+#define _VENTANA_EEPROM_
+
+struct ventana_board_info {
+ u8 mac0[6]; /* 0x00: MAC1 */
+ u8 mac1[6]; /* 0x06: MAC2 */
+ u8 res0[12]; /* 0x0C: reserved */
+ u32 serial; /* 0x18: Serial Number (read only) */
+ u8 res1[4]; /* 0x1C: reserved */
+ u8 mfgdate[4]; /* 0x20: MFG date (read only) */
+ u8 res2[7]; /* 0x24 */
+ /* sdram config */
+ u8 sdram_size; /* 0x2B: (16 << n) MB */
+ u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */
+ u8 sdram_width; /* 0x2D: (8 << n) bit */
+ /* cpu config */
+ u8 cpu_speed; /* 0x2E: (33.333 * n) MHz */
+ u8 cpu_type; /* 0x2F: 7=imx6q, 8=imx6dl */
+ u8 model[16]; /* 0x30: model string */
+ /* FLASH config */
+ u8 nand_flash_size; /* 0x40: (8 << (n-1)) MB */
+ u8 spi_flash_size; /* 0x41: (4 << (n-1)) MB */
+
+ /* Config1: SoC Peripherals */
+ u8 config[8]; /* 0x42: loading options */
+
+ u8 res3[4]; /* 0x4A */
+
+ u8 chksum[2]; /* 0x4E */
+};
+
+/* config bits */
+enum {
+ EECONFIG_ETH0,
+ EECONFIG_ETH1,
+ EECONFIG_HDMI_OUT,
+ EECONFIG_SATA,
+ EECONFIG_PCIE,
+ EECONFIG_SSI0,
+ EECONFIG_SSI1,
+ EECONFIG_LCD,
+ EECONFIG_LVDS0,
+ EECONFIG_LVDS1,
+ EECONFIG_USB0,
+ EECONFIG_USB1,
+ EECONFIG_SD0,
+ EECONFIG_SD1,
+ EECONFIG_SD2,
+ EECONFIG_SD3,
+ EECONFIG_UART0,
+ EECONFIG_UART1,
+ EECONFIG_UART2,
+ EECONFIG_UART3,
+ EECONFIG_UART4,
+ EECONFIG_IPU0,
+ EECONFIG_IPU1,
+ EECONFIG_FLEXCAN,
+ EECONFIG_MIPI_DSI,
+ EECONFIG_MIPI_CSI,
+ EECONFIG_TZASC0,
+ EECONFIG_TZASC1,
+ EECONFIG_I2C0,
+ EECONFIG_I2C1,
+ EECONFIG_I2C2,
+ EECONFIG_VPU,
+ EECONFIG_CSI0,
+ EECONFIG_CSI1,
+ EECONFIG_CAAM,
+ EECONFIG_MEZZ,
+ EECONFIG_RES1,
+ EECONFIG_RES2,
+ EECONFIG_RES3,
+ EECONFIG_RES4,
+ EECONFIG_ESPCI0,
+ EECONFIG_ESPCI1,
+ EECONFIG_ESPCI2,
+ EECONFIG_ESPCI3,
+ EECONFIG_ESPCI4,
+ EECONFIG_ESPCI5,
+ EECONFIG_RES5,
+ EECONFIG_RES6,
+ EECONFIG_GPS,
+ EECONFIG_SPIFL0,
+ EECONFIG_SPIFL1,
+ EECONFIG_GSPBATT,
+ EECONFIG_HDMI_IN,
+ EECONFIG_VID_OUT,
+ EECONFIG_VID_IN,
+ EECONFIG_NAND,
+ EECONFIG_RES8,
+ EECONFIG_RES9,
+ EECONFIG_RES10,
+ EECONFIG_RES11,
+ EECONFIG_RES12,
+ EECONFIG_RES13,
+ EECONFIG_RES14,
+ EECONFIG_RES15,
+};
+
+enum {
+ GW54proto, /* original GW5400-A prototype */
+ GW51xx,
+ GW52xx,
+ GW53xx,
+ GW54xx,
+ GW552x,
+ GW_UNKNOWN,
+ GW_BADCRC,
+};
+
+/* config items */
+struct ventana_eeprom_config {
+ const char *name; /* name of item */
+ const char *dtalias; /* name of dt node to remove if not set */
+ int bit; /* bit within config */
+};
+
+extern struct ventana_eeprom_config econfig[];
+extern struct ventana_board_info ventana_info;
+
+int read_eeprom(int bus, struct ventana_board_info *);
+
+#endif
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
new file mode 100644
index 0000000..426dc05
--- /dev/null
+++ b/board/gdsys/405ep/405ep.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
+
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+#define REFLECTION_TESTREG reflection_low
+#else
+#define REFLECTION_TESTREG reflection_high
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+ return gd->arch.fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+ puts(" Waiting for FPGA-DONE timed out.\n");
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+ puts(" FPGA reflection test failed.\n");
+}
+
+int board_early_init_f(void)
+{
+ unsigned k;
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->arch.fpga_state[k] = 0;
+
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks
+ * -> ca. 15 us
+ */
+ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ unsigned k;
+ unsigned ctr;
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->arch.fpga_state[k] = 0;
+
+ /*
+ * reset FPGA
+ */
+ gd405ep_init();
+
+ gd405ep_set_fpga_reset(1);
+
+ gd405ep_setup_hw();
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ctr = 0;
+ while (!gd405ep_get_fpga_done(k)) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->arch.fpga_state[k] |=
+ FPGA_STATE_DONE_FAILED;
+ break;
+ }
+ }
+ }
+
+ udelay(10);
+
+ gd405ep_set_fpga_reset(0);
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ /*
+ * wait for fpga out of reset
+ */
+ ctr = 0;
+ while (1) {
+ u16 val;
+
+ FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
+
+ FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
+ if (val == REFLECTION_TESTPATTERN_INV)
+ break;
+
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->arch.fpga_state[k] |=
+ FPGA_STATE_REFLECTION_FAILED;
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
diff --git a/board/gdsys/405ep/405ep.h b/board/gdsys/405ep/405ep.h
new file mode 100644
index 0000000..5647dbc
--- /dev/null
+++ b/board/gdsys/405ep/405ep.h
@@ -0,0 +1,10 @@
+#ifndef __405EP_H_
+#define __405EP_H_
+
+/* functions to be provided by board implementation */
+void gd405ep_init(void);
+void gd405ep_set_fpga_reset(unsigned state);
+void gd405ep_setup_hw(void);
+int gd405ep_get_fpga_done(unsigned fpga);
+
+#endif /* __405EP_H_ */
diff --git a/board/gdsys/405ep/Kconfig b/board/gdsys/405ep/Kconfig
new file mode 100644
index 0000000..20cb80f
--- /dev/null
+++ b/board/gdsys/405ep/Kconfig
@@ -0,0 +1,51 @@
+if TARGET_DLVISION_10G
+
+config SYS_BOARD
+ default "405ep"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "dlvision-10g"
+
+endif
+
+if TARGET_IO
+
+config SYS_BOARD
+ default "405ep"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "io"
+
+endif
+
+if TARGET_IOCON
+
+config SYS_BOARD
+ default "405ep"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "iocon"
+
+endif
+
+if TARGET_NEO
+
+config SYS_BOARD
+ default "405ep"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "neo"
+
+endif
diff --git a/board/gdsys/405ep/MAINTAINERS b/board/gdsys/405ep/MAINTAINERS
new file mode 100644
index 0000000..1403880
--- /dev/null
+++ b/board/gdsys/405ep/MAINTAINERS
@@ -0,0 +1,12 @@
+405EP BOARD
+M: Dirk Eibach <eibach@gdsys.de>
+S: Maintained
+F: board/gdsys/405ep/
+F: include/configs/dlvision-10g.h
+F: configs/dlvision-10g_defconfig
+F: include/configs/io.h
+F: configs/io_defconfig
+F: include/configs/iocon.h
+F: configs/iocon_defconfig
+F: include/configs/neo.h
+F: configs/neo_defconfig
diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile
new file mode 100644
index 0000000..857ec04
--- /dev/null
+++ b/board/gdsys/405ep/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := 405ep.o
+obj-$(CONFIG_NEO) += neo.o
+obj-$(CONFIG_IO) += io.o
+obj-$(CONFIG_IOCON) += iocon.o
+obj-$(CONFIG_DLVISION_10G) += dlvision-10g.o
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
new file mode 100644
index 0000000..35dfbbc
--- /dev/null
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -0,0 +1,303 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <dtt.h>
+
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#include "../common/osd.h"
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
+
+#define LATCH2_MC2_PRESENT_N 0x0080
+
+enum {
+ UNITTYPE_VIDEO_USER = 0,
+ UNITTYPE_MAIN_USER = 1,
+ UNITTYPE_VIDEO_SERVER = 2,
+ UNITTYPE_MAIN_SERVER = 3,
+};
+
+enum {
+ HWVER_101 = 0,
+ HWVER_110 = 1,
+ HWVER_120 = 2,
+ HWVER_130 = 3,
+};
+
+enum {
+ AUDIO_NONE = 0,
+ AUDIO_TX = 1,
+ AUDIO_RX = 2,
+ AUDIO_RXTX = 3,
+};
+
+enum {
+ SYSCLK_156250 = 2,
+};
+
+enum {
+ RAM_NONE = 0,
+ RAM_DDR2_32 = 1,
+ RAM_DDR2_64 = 2,
+};
+
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int misc_init_r(void)
+{
+ /* startup fans */
+ dtt_init();
+
+ return 0;
+}
+
+static unsigned int get_hwver(void)
+{
+ u16 latch3 = in_le16((void *)LATCH3_BASE);
+
+ return latch3 & 0x0003;
+}
+
+static unsigned int get_mc2_present(void)
+{
+ u16 latch2 = in_le16((void *)LATCH2_BASE);
+
+ return !(latch2 & LATCH2_MC2_PRESENT_N);
+}
+
+static void print_fpga_info(unsigned dev)
+{
+ u16 versions;
+ u16 fpga_version;
+ u16 fpga_features;
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_rs232;
+ unsigned feature_audio;
+ unsigned feature_sysclock;
+ unsigned feature_ramconfig;
+ unsigned feature_carrier_speed;
+ unsigned feature_carriers;
+ unsigned feature_video_channels;
+ int fpga_state = get_fpga_state(dev);
+
+ printf("FPGA%d: ", dev);
+
+ FPGA_GET_REG(dev, versions, &versions);
+ FPGA_GET_REG(dev, fpga_version, &fpga_version);
+ FPGA_GET_REG(dev, fpga_features, &fpga_features);
+
+ hardware_version = versions & 0x000f;
+
+ if (fpga_state
+ && !((hardware_version == HWVER_101)
+ && (fpga_state == FPGA_STATE_DONE_FAILED))) {
+ puts("not available\n");
+ print_fpga_state(dev);
+ return;
+ }
+
+ unit_type = (versions >> 4) & 0x000f;
+ hardware_version = versions & 0x000f;
+ feature_rs232 = fpga_features & (1<<11);
+ feature_audio = (fpga_features >> 9) & 0x0003;
+ feature_sysclock = (fpga_features >> 7) & 0x0003;
+ feature_ramconfig = (fpga_features >> 5) & 0x0003;
+ feature_carrier_speed = fpga_features & (1<<4);
+ feature_carriers = (fpga_features >> 2) & 0x0003;
+ feature_video_channels = fpga_features & 0x0003;
+
+ switch (unit_type) {
+ case UNITTYPE_VIDEO_USER:
+ printf("Videochannel Userside");
+ break;
+
+ case UNITTYPE_MAIN_USER:
+ printf("Mainchannel Userside");
+ break;
+
+ case UNITTYPE_VIDEO_SERVER:
+ printf("Videochannel Serverside");
+ break;
+
+ case UNITTYPE_MAIN_SERVER:
+ printf("Mainchannel Serverside");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (hardware_version) {
+ case HWVER_101:
+ printf(" HW-Ver 1.01\n");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10-1.12\n");
+ break;
+
+ case HWVER_120:
+ printf(" HW-Ver 1.20\n");
+ break;
+
+ case HWVER_130:
+ printf(" HW-Ver 1.30\n");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+ printf(" %sRS232", feature_rs232 ? "" : "no ");
+
+ switch (feature_audio) {
+ case AUDIO_NONE:
+ printf(", no audio");
+ break;
+
+ case AUDIO_TX:
+ printf(", audio tx");
+ break;
+
+ case AUDIO_RX:
+ printf(", audio rx");
+ break;
+
+ case AUDIO_RXTX:
+ printf(", audio rx+tx");
+ break;
+
+ default:
+ printf(", audio %d(not supported)", feature_audio);
+ break;
+ }
+
+ switch (feature_sysclock) {
+ case SYSCLK_156250:
+ printf(", clock 156.25 MHz");
+ break;
+
+ default:
+ printf(", clock %d(not supported)", feature_sysclock);
+ break;
+ }
+
+ puts(",\n ");
+
+ switch (feature_ramconfig) {
+ case RAM_NONE:
+ printf("no RAM");
+ break;
+
+ case RAM_DDR2_32:
+ printf("RAM 32 bit DDR2");
+ break;
+
+ case RAM_DDR2_64:
+ printf("RAM 64 bit DDR2");
+ break;
+
+ default:
+ printf("RAM %d(not supported)", feature_ramconfig);
+ break;
+ }
+
+ printf(", %d carrier(s) %s", feature_carriers,
+ feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
+
+ printf(", %d video channel(s)\n", feature_video_channels);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ puts("Board: ");
+
+ puts("DLVision 10G");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ u16 versions;
+
+ FPGA_GET_REG(0, versions, &versions);
+
+ print_fpga_info(0);
+ if (get_mc2_present())
+ print_fpga_info(1);
+
+ if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
+ return 0;
+
+ if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
+ osd_probe(0);
+
+ if (get_mc2_present() &&
+ (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
+ osd_probe(1);
+
+ return 0;
+}
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+ if (state) {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+ } else {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+ }
+}
+
+void gd405ep_setup_hw(void)
+{
+ /*
+ * set "startup-finished"-gpios
+ */
+ gpio_write_bit(21, 0);
+ gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+ return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
new file mode 100644
index 0000000..03d796c
--- /dev/null
+++ b/board/gdsys/405ep/io.c
@@ -0,0 +1,214 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <dtt.h>
+#include <miiphy.h>
+
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+#define PHYREG_CONTROL 0
+#define PHYREG_PAGE_ADDRESS 22
+#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
+#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
+
+enum {
+ UNITTYPE_CCD_SWITCH = 1,
+};
+
+enum {
+ HWVER_100 = 0,
+ HWVER_110 = 1,
+ HWVER_121 = 2,
+ HWVER_122 = 3,
+};
+
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int misc_init_r(void)
+{
+ /* startup fans */
+ dtt_init();
+
+ return 0;
+}
+
+int configure_gbit_phy(unsigned char addr)
+{
+ unsigned short value;
+
+ /* select page 2 */
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PAGE_ADDRESS, 0x0002))
+ goto err_out;
+ /* disable SGMII autonegotiation */
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
+ goto err_out;
+ /* select page 0 */
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PAGE_ADDRESS, 0x0000))
+ goto err_out;
+ /* switch from powerdown to normal operation */
+ if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
+ goto err_out;
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
+ goto err_out;
+ /* reset phy so settings take effect */
+ if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
+ PHYREG_CONTROL, 0x9140))
+ goto err_out;
+
+ return 0;
+
+err_out:
+ printf("Error writing to the PHY addr=%02x\n", addr);
+ return -1;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ puts("Board: CATCenter Io");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+static void print_fpga_info(void)
+{
+ u16 versions;
+ u16 fpga_version;
+ u16 fpga_features;
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_channels;
+ unsigned feature_expansion;
+
+ FPGA_GET_REG(0, versions, &versions);
+ FPGA_GET_REG(0, fpga_version, &fpga_version);
+ FPGA_GET_REG(0, fpga_features, &fpga_features);
+
+ unit_type = (versions & 0xf000) >> 12;
+ hardware_version = versions & 0x000f;
+ feature_channels = fpga_features & 0x007f;
+ feature_expansion = fpga_features & (1<<15);
+
+ puts("FPGA: ");
+
+ switch (unit_type) {
+ case UNITTYPE_CCD_SWITCH:
+ printf("CCD-Switch");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (hardware_version) {
+ case HWVER_100:
+ printf(" HW-Ver 1.00\n");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10\n");
+ break;
+
+ case HWVER_121:
+ printf(" HW-Ver 1.21\n");
+ break;
+
+ case HWVER_122:
+ printf(" HW-Ver 1.22\n");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+ printf(" %d channel(s)", feature_channels);
+
+ printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
+}
+
+/*
+ * setup Gbit PHYs
+ */
+int last_stage_init(void)
+{
+ unsigned int k;
+
+ print_fpga_info();
+
+ miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
+ bb_miiphy_read, bb_miiphy_write);
+
+ for (k = 0; k < 32; ++k)
+ configure_gbit_phy(k);
+
+ /* take fpga serdes blocks out of reset */
+ FPGA_SET_REG(0, quad_serdes_reset, 0);
+
+ return 0;
+}
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+ if (state) {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+ } else {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+ }
+}
+
+void gd405ep_setup_hw(void)
+{
+ /*
+ * set "startup-finished"-gpios
+ */
+ gpio_write_bit(21, 0);
+ gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+ return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
new file mode 100644
index 0000000..3a51d86
--- /dev/null
+++ b/board/gdsys/405ep/iocon.c
@@ -0,0 +1,648 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#include "../common/osd.h"
+#include "../common/mclink.h"
+#include "../common/phy.h"
+
+#include <i2c.h>
+#include <pca953x.h>
+#include <pca9698.h>
+
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+#define MAX_MUX_CHANNELS 2
+
+enum {
+ UNITTYPE_MAIN_SERVER = 0,
+ UNITTYPE_MAIN_USER = 1,
+ UNITTYPE_VIDEO_SERVER = 2,
+ UNITTYPE_VIDEO_USER = 3,
+};
+
+enum {
+ HWVER_100 = 0,
+ HWVER_104 = 1,
+ HWVER_110 = 2,
+ HWVER_120 = 3,
+ HWVER_200 = 4,
+ HWVER_210 = 5,
+ HWVER_220 = 6,
+ HWVER_230 = 7,
+};
+
+enum {
+ FPGA_HWVER_200 = 0,
+ FPGA_HWVER_210 = 1,
+};
+
+enum {
+ COMPRESSION_NONE = 0,
+ COMPRESSION_TYPE1_DELTA = 1,
+ COMPRESSION_TYPE1_TYPE2_DELTA = 3,
+};
+
+enum {
+ AUDIO_NONE = 0,
+ AUDIO_TX = 1,
+ AUDIO_RX = 2,
+ AUDIO_RXTX = 3,
+};
+
+enum {
+ SYSCLK_147456 = 0,
+};
+
+enum {
+ RAM_DDR2_32 = 0,
+ RAM_DDR3_32 = 1,
+};
+
+enum {
+ CARRIER_SPEED_1G = 0,
+ CARRIER_SPEED_2_5G = 1,
+};
+
+enum {
+ MCFPGA_DONE = 1 << 0,
+ MCFPGA_INIT_N = 1 << 1,
+ MCFPGA_PROGRAM_N = 1 << 2,
+ MCFPGA_UPDATE_ENABLE_N = 1 << 3,
+ MCFPGA_RESET_N = 1 << 4,
+};
+
+enum {
+ GPIO_MDC = 1 << 14,
+ GPIO_MDIO = 1 << 15,
+};
+
+unsigned int mclink_fpgacount;
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+ int res;
+
+ switch (fpga) {
+ case 0:
+ out_le16(reg, data);
+ break;
+ default:
+ res = mclink_send(fpga - 1, regoff, data);
+ if (res < 0) {
+ printf("mclink_send reg %02lx data %04x returned %d\n",
+ regoff, data, res);
+ return res;
+ }
+ break;
+ }
+
+ return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+ int res;
+
+ switch (fpga) {
+ case 0:
+ *data = in_le16(reg);
+ break;
+ default:
+ if (fpga > mclink_fpgacount)
+ return -EINVAL;
+ res = mclink_receive(fpga - 1, regoff, data);
+ if (res < 0) {
+ printf("mclink_receive reg %02lx returned %d\n",
+ regoff, res);
+ return res;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ puts("Board: ");
+
+ puts("IoCon");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
+{
+ u16 versions;
+ u16 fpga_version;
+ u16 fpga_features;
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_compression;
+ unsigned feature_osd;
+ unsigned feature_audio;
+ unsigned feature_sysclock;
+ unsigned feature_ramconfig;
+ unsigned feature_carrier_speed;
+ unsigned feature_carriers;
+ unsigned feature_video_channels;
+
+ int legacy = get_fpga_state(fpga) & FPGA_STATE_PLATFORM;
+
+ FPGA_GET_REG(fpga, versions, &versions);
+ FPGA_GET_REG(fpga, fpga_version, &fpga_version);
+ FPGA_GET_REG(fpga, fpga_features, &fpga_features);
+
+ unit_type = (versions & 0xf000) >> 12;
+ feature_compression = (fpga_features & 0xe000) >> 13;
+ feature_osd = fpga_features & (1<<11);
+ feature_audio = (fpga_features & 0x0600) >> 9;
+ feature_sysclock = (fpga_features & 0x0180) >> 7;
+ feature_ramconfig = (fpga_features & 0x0060) >> 5;
+ feature_carrier_speed = fpga_features & (1<<4);
+ feature_carriers = (fpga_features & 0x000c) >> 2;
+ feature_video_channels = fpga_features & 0x0003;
+
+ if (legacy)
+ printf("legacy ");
+
+ switch (unit_type) {
+ case UNITTYPE_MAIN_USER:
+ printf("Mainchannel");
+ break;
+
+ case UNITTYPE_VIDEO_USER:
+ printf("Videochannel");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ if (unit_type == UNITTYPE_MAIN_USER) {
+ if (legacy)
+ hardware_version =
+ (in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
+ else
+ hardware_version =
+ (!!pca9698_get_value(0x20, 24) << 0)
+ | (!!pca9698_get_value(0x20, 25) << 1)
+ | (!!pca9698_get_value(0x20, 26) << 2)
+ | (!!pca9698_get_value(0x20, 27) << 3);
+ switch (hardware_version) {
+ case HWVER_100:
+ printf(" HW-Ver 1.00,");
+ break;
+
+ case HWVER_104:
+ printf(" HW-Ver 1.04,");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10,");
+ break;
+
+ case HWVER_120:
+ printf(" HW-Ver 1.20-1.21,");
+ break;
+
+ case HWVER_200:
+ printf(" HW-Ver 2.00,");
+ break;
+
+ case HWVER_210:
+ printf(" HW-Ver 2.10,");
+ break;
+
+ case HWVER_220:
+ printf(" HW-Ver 2.20,");
+ break;
+
+ case HWVER_230:
+ printf(" HW-Ver 2.30,");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported),",
+ hardware_version);
+ break;
+ }
+ if (rgmii2_present)
+ printf(" RGMII2,");
+ }
+
+ if (unit_type == UNITTYPE_VIDEO_USER) {
+ hardware_version = versions & 0x000f;
+ switch (hardware_version) {
+ case FPGA_HWVER_200:
+ printf(" HW-Ver 2.00,");
+ break;
+
+ case FPGA_HWVER_210:
+ printf(" HW-Ver 2.10,");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported),",
+ hardware_version);
+ break;
+ }
+ }
+
+ printf(" FPGA V %d.%02d\n features:",
+ fpga_version / 100, fpga_version % 100);
+
+
+ switch (feature_compression) {
+ case COMPRESSION_NONE:
+ printf(" no compression");
+ break;
+
+ case COMPRESSION_TYPE1_DELTA:
+ printf(" type1-deltacompression");
+ break;
+
+ case COMPRESSION_TYPE1_TYPE2_DELTA:
+ printf(" type1-deltacompression, type2-inlinecompression");
+ break;
+
+ default:
+ printf(" compression %d(not supported)", feature_compression);
+ break;
+ }
+
+ printf(", %sosd", feature_osd ? "" : "no ");
+
+ switch (feature_audio) {
+ case AUDIO_NONE:
+ printf(", no audio");
+ break;
+
+ case AUDIO_TX:
+ printf(", audio tx");
+ break;
+
+ case AUDIO_RX:
+ printf(", audio rx");
+ break;
+
+ case AUDIO_RXTX:
+ printf(", audio rx+tx");
+ break;
+
+ default:
+ printf(", audio %d(not supported)", feature_audio);
+ break;
+ }
+
+ puts(",\n ");
+
+ switch (feature_sysclock) {
+ case SYSCLK_147456:
+ printf("clock 147.456 MHz");
+ break;
+
+ default:
+ printf("clock %d(not supported)", feature_sysclock);
+ break;
+ }
+
+ switch (feature_ramconfig) {
+ case RAM_DDR2_32:
+ printf(", RAM 32 bit DDR2");
+ break;
+
+ case RAM_DDR3_32:
+ printf(", RAM 32 bit DDR3");
+ break;
+
+ default:
+ printf(", RAM %d(not supported)", feature_ramconfig);
+ break;
+ }
+
+ printf(", %d carrier(s) %s", feature_carriers,
+ feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
+
+ printf(", %d video channel(s)\n", feature_video_channels);
+}
+
+int last_stage_init(void)
+{
+ int slaves;
+ unsigned int k;
+ unsigned int mux_ch;
+ unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
+ int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+ u16 fpga_features;
+ int feature_carrier_speed;
+ bool ch0_rgmii2_present = false;
+
+ FPGA_GET_REG(0, fpga_features, &fpga_features);
+ feature_carrier_speed = fpga_features & (1<<4);
+
+ if (!legacy) {
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x20, 9, 1);
+
+ ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
+ }
+
+ /* wait for FPGA done */
+ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
+ unsigned int ctr = 0;
+
+ if (i2c_probe(mclink_controllers[k]))
+ continue;
+
+ while (!(pca953x_get_val(mclink_controllers[k])
+ & MCFPGA_DONE)) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ printf("no done for mclink_controller %d\n", k);
+ break;
+ }
+ }
+ }
+
+ if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
+ miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
+ bb_miiphy_write);
+ for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
+ if ((mux_ch == 1) && !ch0_rgmii2_present)
+ continue;
+
+ setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
+ }
+ }
+
+ /* give slave-PLLs and Parade DP501 some time to be up and running */
+ udelay(500000);
+
+ mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
+ slaves = mclink_probe();
+ mclink_fpgacount = 0;
+
+ print_fpga_info(0, ch0_rgmii2_present);
+ osd_probe(0);
+
+ if (slaves <= 0)
+ return 0;
+
+ mclink_fpgacount = slaves;
+
+ for (k = 1; k <= slaves; ++k) {
+ FPGA_GET_REG(k, fpga_features, &fpga_features);
+ feature_carrier_speed = fpga_features & (1<<4);
+
+ print_fpga_info(k, false);
+ osd_probe(k);
+ if (feature_carrier_speed == CARRIER_SPEED_1G) {
+ miiphy_register(bb_miiphy_buses[k].name,
+ bb_miiphy_read, bb_miiphy_write);
+ setup_88e1518(bb_miiphy_buses[k].name, 0);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * provide access to fpga gpios (for I2C bitbang)
+ * (these may look all too simple but make iocon.h much more readable)
+ */
+void fpga_gpio_set(unsigned int bus, int pin)
+{
+ FPGA_SET_REG(bus, gpio.set, pin);
+}
+
+void fpga_gpio_clear(unsigned int bus, int pin)
+{
+ FPGA_SET_REG(bus, gpio.clear, pin);
+}
+
+int fpga_gpio_get(unsigned int bus, int pin)
+{
+ u16 val;
+
+ FPGA_GET_REG(bus, gpio.read, &val);
+
+ return val & pin;
+}
+
+void gd405ep_init(void)
+{
+ unsigned int k;
+
+ if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
+ } else {
+ pca9698_direction_output(0x20, 4, 1);
+ }
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+ int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+
+ if (legacy) {
+ if (state) {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+ } else {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+ }
+ } else {
+ pca9698_set_value(0x20, 4, state ? 0 : 1);
+ }
+}
+
+void gd405ep_setup_hw(void)
+{
+ /*
+ * set "startup-finished"-gpios
+ */
+ gpio_write_bit(21, 0);
+ gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+ int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+
+ if (legacy)
+ return in_le16((void *)LATCH2_BASE)
+ & CONFIG_SYS_FPGA_DONE(fpga);
+ else
+ return pca9698_get_value(0x20, 20);
+}
+
+/*
+ * FPGA MII bitbang implementation
+ */
+
+struct fpga_mii {
+ unsigned fpga;
+ int mdio;
+} fpga_mii[] = {
+ { 0, 1},
+ { 1, 1},
+ { 2, 1},
+ { 3, 1},
+};
+
+static int mii_dummy_init(struct bb_miiphy_bus *bus)
+{
+ return 0;
+}
+
+static int mii_mdio_active(struct bb_miiphy_bus *bus)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (fpga_mii->mdio)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+ return 0;
+}
+
+static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+
+ return 0;
+}
+
+static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (v)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+ fpga_mii->mdio = v;
+
+ return 0;
+}
+
+static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+ u16 gpio;
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
+
+ *v = ((gpio & GPIO_MDIO) != 0);
+
+ return 0;
+}
+
+static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (v)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
+
+ return 0;
+}
+
+static int mii_delay(struct bb_miiphy_bus *bus)
+{
+ udelay(1);
+
+ return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+ {
+ .name = "board0",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[0],
+ },
+ {
+ .name = "board1",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[1],
+ },
+ {
+ .name = "board2",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[2],
+ },
+ {
+ .name = "board3",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[3],
+ },
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+ sizeof(bb_miiphy_buses[0]);
diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c
new file mode 100644
index 0000000..ff0edb2
--- /dev/null
+++ b/board/gdsys/405ep/neo.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <dtt.h>
+
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+enum {
+ UNITTYPE_CCX16 = 1,
+ UNITTYPE_CCIP216 = 2,
+};
+
+enum {
+ HWVER_300 = 3,
+};
+
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int misc_init_r(void)
+{
+ /* startup fans */
+ dtt_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ puts("Board: CATCenter Neo");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+static void print_fpga_info(void)
+{
+ u16 versions;
+ u16 fpga_version;
+ u16 fpga_features;
+ int fpga_state = get_fpga_state(0);
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_channels;
+
+ puts("FPGA: ");
+ if (fpga_state & FPGA_STATE_DONE_FAILED) {
+ printf(" done timed out\n");
+ return;
+ }
+
+ if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
+ printf(" refelectione test failed\n");
+ return;
+ }
+
+ FPGA_GET_REG(0, versions, &versions);
+ FPGA_GET_REG(0, fpga_version, &fpga_version);
+ FPGA_GET_REG(0, fpga_features, &fpga_features);
+
+ unit_type = (versions & 0xf000) >> 12;
+ hardware_version = versions & 0x000f;
+ feature_channels = fpga_features & 0x007f;
+
+ switch (unit_type) {
+ case UNITTYPE_CCX16:
+ printf("CCX-Switch");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (hardware_version) {
+ case HWVER_300:
+ printf(" HW-Ver 3.00-3.12\n");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+ printf(" %d channel(s)\n", feature_channels);
+}
+
+int last_stage_init(void)
+{
+ print_fpga_info();
+
+ return 0;
+}
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+ if (state) {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+ } else {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+ }
+}
+
+void gd405ep_setup_hw(void)
+{
+ /*
+ * set "startup-finished"-gpios
+ */
+ gpio_write_bit(21, 0);
+ gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+ /*
+ * Neo hardware has no FPGA-DONE GPIO
+ */
+ return 1;
+}
diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c
new file mode 100644
index 0000000..c1a583f
--- /dev/null
+++ b/board/gdsys/405ex/405ex.c
@@ -0,0 +1,252 @@
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc405.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#include <gdsys_fpga.h>
+
+#include "405ex.h"
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+#define REFLECTION_TESTREG reflection_low
+#else
+#define REFLECTION_TESTREG reflection_high
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+ return gd->arch.fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+ puts(" Waiting for FPGA-DONE timed out.\n");
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+ puts(" FPGA reflection test failed.\n");
+}
+
+int board_early_init_f(void)
+{
+ u32 val;
+
+ /*--------------------------------------------------------------------+
+ | Interrupt controller setup
+ +--------------------------------------------------------------------+
+ +---------------------------------------------------------------------+
+ |Interrupt| Source | Pol. | Sensi.| Crit. |
+ +---------+-----------------------------------+-------+-------+-------+
+ | IRQ 00 | UART0 | High | Level | Non |
+ | IRQ 01 | UART1 | High | Level | Non |
+ | IRQ 02 | IIC0 | High | Level | Non |
+ | IRQ 03 | TBD | High | Level | Non |
+ | IRQ 04 | TBD | High | Level | Non |
+ | IRQ 05 | EBM | High | Level | Non |
+ | IRQ 06 | BGI | High | Level | Non |
+ | IRQ 07 | IIC1 | Rising| Edge | Non |
+ | IRQ 08 | SPI | High | Lvl/ed| Non |
+ | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
+ | IRQ 10 | MAL TX EOB | High | Level | Non |
+ | IRQ 11 | MAL RX EOB | High | Level | Non |
+ | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
+ | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
+ | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
+ | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
+ | IRQ 16 | PCIE0 AL | high | Level | Non |
+ | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
+ | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
+ | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
+ | IRQ 20 | PCIE0 TCR | High | Level | Non |
+ | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
+ | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
+ | IRQ 23 | Security EIP-94 | High | Level | Non |
+ | IRQ 24 | EMAC0 interrupt | High | Level | Non |
+ | IRQ 25 | EMAC1 interrupt | High | Level | Non |
+ | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
+ | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
+ | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
+ | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
+ | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
+ | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
+ |----------------------------------------------------------------------
+ | IRQ 32 | MAL Serr | High | Level | Non |
+ | IRQ 33 | MAL Txde | High | Level | Non |
+ | IRQ 34 | MAL Rxde | High | Level | Non |
+ | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
+ | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
+ | IRQ 37 | EBC | High |Lvl Edg| Non |
+ | IRQ 38 | NDFC | High | Level | Non |
+ | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
+ | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
+ | IRQ 41 | PCIE1 AL | high | Level | Non |
+ | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
+ | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
+ | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
+ | IRQ 45 | PCIE1 TCR | High | Level | Non |
+ | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
+ | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
+ | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
+ | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
+ | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
+ | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
+ | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
+ | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
+ | IRQ 55 | Serial ROM | High | Level | Non |
+ | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
+ | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
+ | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
+ | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
+ |----------------------------------------------------------------------
+ | IRQ 64 | PE0 AL | High | Level | Non |
+ | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
+ | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 68 | PE0 TCR | High | Level | Non |
+ | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 70 | PE0 DCR Error | High | Level | Non |
+ | IRQ 71 | Reserved | N/A | N/A | Non |
+ | IRQ 72 | PE1 AL | High | Level | Non |
+ | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
+ | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 76 | PE1 TCR | High | Level | Non |
+ | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 78 | PE1 DCR Error | High | Level | Non |
+ | IRQ 79 | Reserved | N/A | N/A | Non |
+ | IRQ 80 | PE2 AL | High | Level | Non |
+ | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
+ | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
+ | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
+ | IRQ 84 | PE2 TCR | High | Level | Non |
+ | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
+ | IRQ 86 | PE2 DCR Error | High | Level | Non |
+ | IRQ 87 | Reserved | N/A | N/A | Non |
+ | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
+ | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
+ | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
+ | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
+ | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
+ | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
+ | IRQ 94 | Reserved | N/A | N/A | Non |
+ | IRQ 95 | Reserved | N/A | N/A | Non |
+ |---------------------------------------------------------------------
+ +---------+-----------------------------------+-------+-------+------*/
+ /*--------------------------------------------------------------------+
+ | Initialise UIC registers. Clear all interrupts. Disable all
+ | interrupts.
+ | Set critical interrupt values. Set interrupt polarities. Set
+ | interrupt trigger levels. Make bit 0 High priority. Clear all
+ | interrupts again.
+ +-------------------------------------------------------------------*/
+
+ mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
+ mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
+ mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
+ mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
+ mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */
+ /* Except cascade UIC0 and UIC1 */
+ mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
+ mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
+
+ /*
+ * Note: Some cores are still in reset when the chip starts, so
+ * take them out of reset
+ */
+ mtsdr(SDR0_SRST, 0);
+
+ /*
+ * Configure PFC (Pin Function Control) registers
+ */
+ val = SDR0_PFC1_GPT_FREQ;
+ mtsdr(SDR0_PFC1, val);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ unsigned k;
+ unsigned ctr;
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->arch.fpga_state[k] = 0;
+
+ /*
+ * reset FPGA
+ */
+ gd405ex_init();
+
+ gd405ex_set_fpga_reset(1);
+
+ gd405ex_setup_hw();
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ctr = 0;
+ while (!gd405ex_get_fpga_done(k)) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->arch.fpga_state[k] |=
+ FPGA_STATE_DONE_FAILED;
+ break;
+ }
+ }
+ }
+
+ udelay(10);
+
+ gd405ex_set_fpga_reset(0);
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ /*
+ * wait for fpga out of reset
+ */
+ ctr = 0;
+ while (1) {
+ u16 val;
+
+ FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
+
+ FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
+ if (val == REFLECTION_TESTPATTERN_INV)
+ break;
+
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->arch.fpga_state[k] |=
+ FPGA_STATE_REFLECTION_FAILED;
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
diff --git a/board/gdsys/405ex/405ex.h b/board/gdsys/405ex/405ex.h
new file mode 100644
index 0000000..b15623f
--- /dev/null
+++ b/board/gdsys/405ex/405ex.h
@@ -0,0 +1,10 @@
+#ifndef __405EX_H_
+#define __405EX_H_
+
+/* functions to be provided by board implementation */
+void gd405ex_init(void);
+void gd405ex_set_fpga_reset(unsigned state);
+void gd405ex_setup_hw(void);
+int gd405ex_get_fpga_done(unsigned fpga);
+
+#endif /* __405EX_H_ */
diff --git a/board/gdsys/405ex/Kconfig b/board/gdsys/405ex/Kconfig
new file mode 100644
index 0000000..52a8d89
--- /dev/null
+++ b/board/gdsys/405ex/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IO64
+
+config SYS_BOARD
+ default "405ex"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "io64"
+
+endif
diff --git a/board/gdsys/405ex/MAINTAINERS b/board/gdsys/405ex/MAINTAINERS
new file mode 100644
index 0000000..395b1ac
--- /dev/null
+++ b/board/gdsys/405ex/MAINTAINERS
@@ -0,0 +1,6 @@
+405EX BOARD
+M: Dirk Eibach <eibach@gdsys.de>
+S: Maintained
+F: board/gdsys/405ex/
+F: include/configs/io64.h
+F: configs/io64_defconfig
diff --git a/board/gdsys/405ex/Makefile b/board/gdsys/405ex/Makefile
new file mode 100644
index 0000000..a668460
--- /dev/null
+++ b/board/gdsys/405ex/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := 405ex.o
+obj-$(CONFIG_IO64) += io64.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
diff --git a/board/gdsys/405ex/chip_config.c b/board/gdsys/405ex/chip_config.c
new file mode 100644
index 0000000..37e76c4
--- /dev/null
+++ b/board/gdsys/405ex/chip_config.c
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "333-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83",
+ {
+ 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66",
+ {
+ 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-200-66-nor", "NOR CPU: 400 PLB: 200 OPB: 66 EBC: 66",
+ {
+ 0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
+ {
+ 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88",
+ {
+ 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
+ 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111",
+ {
+ 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
+ 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+ }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
new file mode 100644
index 0000000..3a075c4
--- /dev/null
+++ b/board/gdsys/405ex/io64.c
@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * based on kilauea.c
+ * by Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc405.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/ppc4xx-gpio.h>
+#include <flash.h>
+
+#include <pca9698.h>
+
+#include "405ex.h"
+#include <gdsys_fpga.h>
+
+#include <miiphy.h>
+#include <i2c.h>
+#include <dtt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PHYREG_CONTROL 0
+#define PHYREG_PAGE_ADDRESS 22
+#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
+#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
+#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17
+#define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
+
+enum {
+ UNITTYPE_CCD_SWITCH = 1,
+};
+
+enum {
+ HWVER_100 = 0,
+ HWVER_110 = 1,
+};
+
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+static inline void blank_string(int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++)
+ putc('\b');
+ for (i = 0; i < size; i++)
+ putc(' ');
+ for (i = 0; i < size; i++)
+ putc('\b');
+}
+
+/*
+ * Board early initialization function
+ */
+int misc_init_r(void)
+{
+ /* startup fans */
+ dtt_init();
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ /* Monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+#endif
+
+ return 0;
+}
+
+static void print_fpga_info(unsigned dev)
+{
+ u16 versions;
+ u16 fpga_version;
+ u16 fpga_features;
+ int fpga_state = get_fpga_state(dev);
+
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_channels;
+ unsigned feature_expansion;
+
+ FPGA_GET_REG(dev, versions, &versions);
+ FPGA_GET_REG(dev, fpga_version, &fpga_version);
+ FPGA_GET_REG(dev, fpga_features, &fpga_features);
+
+ printf("FPGA%d: ", dev);
+ if (fpga_state & FPGA_STATE_PLATFORM)
+ printf("(legacy) ");
+
+ if (fpga_state & FPGA_STATE_DONE_FAILED) {
+ printf(" done timed out\n");
+ return;
+ }
+
+ if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
+ printf(" refelectione test failed\n");
+ return;
+ }
+
+ unit_type = (versions & 0xf000) >> 12;
+ hardware_version = versions & 0x000f;
+ feature_channels = fpga_features & 0x007f;
+ feature_expansion = fpga_features & (1<<15);
+
+ switch (unit_type) {
+ case UNITTYPE_CCD_SWITCH:
+ printf("CCD-Switch");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (hardware_version) {
+ case HWVER_100:
+ printf(" HW-Ver 1.00\n");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10\n");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+ printf(" %d channel(s)", feature_channels);
+
+ printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: CATCenter Io64\n");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ return 0;
+}
+
+int configure_gbit_phy(char *bus, unsigned char addr)
+{
+ unsigned short value;
+
+ /* select page 0 */
+ if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
+ goto err_out;
+ /* switch to powerdown */
+ if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+ &value))
+ goto err_out;
+ if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+ value | 0x0004))
+ goto err_out;
+ /* select page 2 */
+ if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
+ goto err_out;
+ /* disable SGMII autonegotiation */
+ if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48))
+ goto err_out;
+ /* select page 0 */
+ if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
+ goto err_out;
+ /* switch from powerdown to normal operation */
+ if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+ &value))
+ goto err_out;
+ if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
+ value & ~0x0004))
+ goto err_out;
+ /* reset phy so settings take effect */
+ if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140))
+ goto err_out;
+
+ return 0;
+
+err_out:
+ printf("Error writing to the PHY addr=%02x\n", addr);
+ return -1;
+}
+
+int verify_gbit_phy(char *bus, unsigned char addr)
+{
+ unsigned short value;
+
+ /* select page 2 */
+ if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
+ goto err_out;
+ /* verify SGMII link status */
+ if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value))
+ goto err_out;
+ if (!(value & (1 << 10)))
+ return -2;
+
+ return 0;
+
+err_out:
+ printf("Error writing to the PHY addr=%02x\n", addr);
+ return -1;
+}
+
+int last_stage_init(void)
+{
+ unsigned int k;
+ unsigned int fpga;
+ int failed = 0;
+ char str_phys[] = "Setup PHYs -";
+ char str_serdes[] = "Start SERDES blocks";
+ char str_channels[] = "Start FPGA channels";
+ char str_locks[] = "Verify SERDES locks";
+ char str_hicb[] = "Verify HICB status";
+ char str_status[] = "Verify PHY status -";
+ char slash[] = "\\|/-\\|/-";
+
+ print_fpga_info(0);
+ print_fpga_info(1);
+
+ /* setup Gbit PHYs */
+ puts("TRANS: ");
+ puts(str_phys);
+ miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
+ bb_miiphy_read, bb_miiphy_write);
+
+ for (k = 0; k < 32; ++k) {
+ configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
+ putc('\b');
+ putc(slash[k % 8]);
+ }
+
+ miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME,
+ bb_miiphy_read, bb_miiphy_write);
+
+ for (k = 0; k < 32; ++k) {
+ configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
+ putc('\b');
+ putc(slash[k % 8]);
+ }
+ blank_string(strlen(str_phys));
+
+ /* take fpga serdes blocks out of reset */
+ puts(str_serdes);
+ udelay(500000);
+ FPGA_SET_REG(0, quad_serdes_reset, 0);
+ FPGA_SET_REG(1, quad_serdes_reset, 0);
+ blank_string(strlen(str_serdes));
+
+ /* take channels out of reset */
+ puts(str_channels);
+ udelay(500000);
+ for (fpga = 0; fpga < 2; ++fpga) {
+ for (k = 0; k < 32; ++k)
+ FPGA_SET_REG(fpga, ch[k].config_int, 0);
+ }
+ blank_string(strlen(str_channels));
+
+ /* verify channels serdes lock */
+ puts(str_locks);
+ udelay(500000);
+ for (fpga = 0; fpga < 2; ++fpga) {
+ for (k = 0; k < 32; ++k) {
+ u16 status;
+ FPGA_GET_REG(fpga, ch[k].status_int, &status);
+ if (!(status & (1 << 4))) {
+ failed = 1;
+ printf("fpga %d channel %d: no serdes lock\n",
+ fpga, k);
+ }
+ /* reset events */
+ FPGA_SET_REG(fpga, ch[k].status_int, 0);
+ }
+ }
+ blank_string(strlen(str_locks));
+
+ /* verify hicb_status */
+ puts(str_hicb);
+ for (fpga = 0; fpga < 2; ++fpga) {
+ for (k = 0; k < 32; ++k) {
+ u16 status;
+ FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status);
+ if (status)
+ printf("fpga %d hicb %d: hicb status %04x\n",
+ fpga, k, status);
+ /* reset events */
+ FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0);
+ }
+ }
+ blank_string(strlen(str_hicb));
+
+ /* verify phy status */
+ puts(str_status);
+ for (k = 0; k < 32; ++k) {
+ if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) {
+ printf("verify baseboard phy %d failed\n", k);
+ failed = 1;
+ }
+ putc('\b');
+ putc(slash[k % 8]);
+ }
+ for (k = 0; k < 32; ++k) {
+ if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) {
+ printf("verify extensionboard phy %d failed\n", k);
+ failed = 1;
+ }
+ putc('\b');
+ putc(slash[k % 8]);
+ }
+ blank_string(strlen(str_status));
+
+ printf("Starting 64 channels %s\n", failed ? "failed" : "ok");
+
+ return 0;
+}
+
+void gd405ex_init(void)
+{
+ unsigned int k;
+
+ if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
+ } else {
+ pca9698_direction_output(0x22, 39, 1);
+ }
+}
+
+void gd405ex_set_fpga_reset(unsigned state)
+{
+ int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+
+ if (legacy) {
+ if (state) {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+ } else {
+ out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+ out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+ }
+ } else {
+ pca9698_set_value(0x22, 39, state ? 0 : 1);
+ }
+}
+
+void gd405ex_setup_hw(void)
+{
+ gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0);
+ gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1);
+}
+
+int gd405ex_get_fpga_done(unsigned fpga)
+{
+ int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+
+ if (legacy)
+ return in_le16((void *)LATCH3_BASE)
+ & CONFIG_SYS_FPGA_DONE(fpga);
+ else
+ return pca9698_get_value(0x22, fpga ? 9 : 8);
+}
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
new file mode 100644
index 0000000..4957943
--- /dev/null
+++ b/board/gdsys/common/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
+obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
+obj-$(CONFIG_IO) += miiphybb.o
+obj-$(CONFIG_IO64) += miiphybb.o
+obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o
+obj-$(CONFIG_DLVISION_10G) += osd.o
+obj-$(CONFIG_CONTROLCENTERD) += dp501.o
+obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o
diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c
new file mode 100644
index 0000000..e0c74fe
--- /dev/null
+++ b/board/gdsys/common/cmd_ioloop.c
@@ -0,0 +1,295 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+
+#include <gdsys_fpga.h>
+
+enum {
+ STATE_TX_PACKET_BUILDING = 1<<0,
+ STATE_TX_TRANSMITTING = 1<<1,
+ STATE_TX_BUFFER_FULL = 1<<2,
+ STATE_TX_ERR = 1<<3,
+ STATE_RECEIVE_TIMEOUT = 1<<4,
+ STATE_PROC_RX_STORE_TIMEOUT = 1<<5,
+ STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6,
+ STATE_RX_DIST_ERR = 1<<7,
+ STATE_RX_LENGTH_ERR = 1<<8,
+ STATE_RX_FRAME_CTR_ERR = 1<<9,
+ STATE_RX_FCS_ERR = 1<<10,
+ STATE_RX_PACKET_DROPPED = 1<<11,
+ STATE_RX_DATA_LAST = 1<<12,
+ STATE_RX_DATA_FIRST = 1<<13,
+ STATE_RX_DATA_AVAILABLE = 1<<15,
+};
+
+enum {
+ CTRL_PROC_RECEIVE_ENABLE = 1<<12,
+ CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15,
+};
+
+enum {
+ IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5,
+ IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6,
+ IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7,
+ IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8,
+};
+
+struct io_generic_packet {
+ u16 target_address;
+ u16 source_address;
+ u8 packet_type;
+ u8 bc;
+ u16 packet_length;
+} __attribute__((__packed__));
+
+unsigned long long rx_ctr;
+unsigned long long tx_ctr;
+unsigned long long err_ctr;
+
+static void io_check_status(unsigned int fpga, u16 status, bool silent)
+{
+ u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
+ STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
+ STATE_RX_PACKET_DROPPED | STATE_TX_ERR;
+
+ if (!(status & mask)) {
+ FPGA_SET_REG(fpga, ep.rx_tx_status, status);
+ return;
+ }
+
+ err_ctr++;
+ FPGA_SET_REG(fpga, ep.rx_tx_status, status);
+
+ if (silent)
+ return;
+
+ if (status & STATE_RX_PACKET_DROPPED)
+ printf("RX_PACKET_DROPPED, status %04x\n", status);
+
+ if (status & STATE_RX_DIST_ERR)
+ printf("RX_DIST_ERR\n");
+ if (status & STATE_RX_LENGTH_ERR)
+ printf("RX_LENGTH_ERR\n");
+ if (status & STATE_RX_FRAME_CTR_ERR)
+ printf("RX_FRAME_CTR_ERR\n");
+ if (status & STATE_RX_FCS_ERR)
+ printf("RX_FCS_ERR\n");
+
+ if (status & STATE_TX_ERR)
+ printf("TX_ERR\n");
+}
+
+static void io_send(unsigned int fpga, unsigned int size)
+{
+ unsigned int k;
+ struct io_generic_packet packet = {
+ .source_address = 1,
+ .packet_type = 1,
+ .packet_length = size,
+ };
+ u16 *p = (u16 *)&packet;
+
+ for (k = 0; k < sizeof(packet) / 2; ++k)
+ FPGA_SET_REG(fpga, ep.transmit_data, *p++);
+
+ for (k = 0; k < (size + 1) / 2; ++k)
+ FPGA_SET_REG(fpga, ep.transmit_data, k);
+
+ FPGA_SET_REG(fpga, ep.rx_tx_control,
+ CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
+
+ tx_ctr++;
+}
+
+static void io_receive(unsigned int fpga)
+{
+ unsigned int k = 0;
+ u16 rx_tx_status;
+
+ FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+ while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
+ u16 rx;
+
+ if (rx_tx_status & STATE_RX_DATA_LAST)
+ rx_ctr++;
+
+ FPGA_GET_REG(fpga, ep.receive_data, &rx);
+
+ FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+ ++k;
+ }
+}
+
+static void io_reflect(unsigned int fpga)
+{
+ u16 buffer[128];
+
+ unsigned int k = 0;
+ unsigned int n;
+ u16 rx_tx_status;
+
+ FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+ while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
+ FPGA_GET_REG(fpga, ep.receive_data, &buffer[k++]);
+ if (rx_tx_status & STATE_RX_DATA_LAST)
+ break;
+
+ FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+ }
+
+ if (!k)
+ return;
+
+ for (n = 0; n < k; ++n)
+ FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]);
+
+ FPGA_SET_REG(fpga, ep.rx_tx_control,
+ CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);
+
+ tx_ctr++;
+}
+
+/*
+ * FPGA io-endpoint reflector
+ *
+ * Syntax:
+ * ioreflect {fpga} {reportrate}
+ */
+int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int fpga;
+ unsigned int rate = 0;
+ unsigned long long last_seen = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ fpga = simple_strtoul(argv[1], NULL, 10);
+
+ /*
+ * If another parameter, it is the report rate in packets.
+ */
+ if (argc > 2)
+ rate = simple_strtoul(argv[2], NULL, 10);
+
+ /* enable receive path */
+ FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
+
+ /* set device address to dummy 1*/
+ FPGA_SET_REG(fpga, ep.device_address, 1);
+
+ rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+ while (1) {
+ u16 top_int;
+ u16 rx_tx_status;
+
+ FPGA_GET_REG(fpga, top_interrupt, &top_int);
+ FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+ io_check_status(fpga, rx_tx_status, true);
+ if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
+ (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
+ io_reflect(fpga);
+
+ if (rate) {
+ if (!(tx_ctr % rate) && (tx_ctr != last_seen))
+ printf("refl %llu, err %llu\n", tx_ctr,
+ err_ctr);
+ last_seen = tx_ctr;
+ }
+
+ if (ctrlc())
+ break;
+ }
+
+ return 0;
+}
+
+/*
+ * FPGA io-endpoint looptest
+ *
+ * Syntax:
+ * ioloop {fpga} {size} {rate}
+ */
+#define DISP_LINE_LEN 16
+int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int fpga;
+ unsigned int size;
+ unsigned int rate = 0;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ /*
+ * FPGA is specified since argc > 2
+ */
+ fpga = simple_strtoul(argv[1], NULL, 10);
+
+ /*
+ * packet size is specified since argc > 2
+ */
+ size = simple_strtoul(argv[2], NULL, 10);
+
+ /*
+ * If another parameter, it is the test rate in packets per second.
+ */
+ if (argc > 3)
+ rate = simple_strtoul(argv[3], NULL, 10);
+
+ /* enable receive path */
+ FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
+
+ /* set device address to dummy 1*/
+ FPGA_SET_REG(fpga, ep.device_address, 1);
+
+ rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
+
+ while (1) {
+ u16 top_int;
+ u16 rx_tx_status;
+
+ FPGA_GET_REG(fpga, top_interrupt, &top_int);
+ FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
+
+ io_check_status(fpga, rx_tx_status, false);
+ if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
+ io_send(fpga, size);
+ if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
+ io_receive(fpga);
+
+ if (rate) {
+ if (ctrlc())
+ break;
+ udelay(1000000 / rate);
+ if (!(tx_ctr % rate))
+ printf("d %lld, tx %llu, rx %llu, err %llu\n",
+ tx_ctr - rx_ctr, tx_ctr, rx_ctr,
+ err_ctr);
+ }
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ ioloop, 4, 0, do_ioloop,
+ "fpga io-endpoint looptest",
+ "fpga packetsize [packets/sec]"
+);
+
+U_BOOT_CMD(
+ ioreflect, 3, 0, do_ioreflect,
+ "fpga io-endpoint reflector",
+ "fpga reportrate"
+);
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
new file mode 100644
index 0000000..7eb15ed
--- /dev/null
+++ b/board/gdsys/common/dp501.c
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+
+static void dp501_setbits(u8 addr, u8 reg, u8 mask)
+{
+ u8 val;
+
+ val = i2c_reg_read(addr, reg);
+ setbits_8(&val, mask);
+ i2c_reg_write(addr, reg, val);
+}
+
+static void dp501_clrbits(u8 addr, u8 reg, u8 mask)
+{
+ u8 val;
+
+ val = i2c_reg_read(addr, reg);
+ clrbits_8(&val, mask);
+ i2c_reg_write(addr, reg, val);
+}
+
+static int dp501_detect_cable_adapter(u8 addr)
+{
+ u8 val = i2c_reg_read(addr, 0x00);
+
+ return !(val & 0x04);
+}
+
+static void dp501_link_training(u8 addr)
+{
+ u8 val;
+
+ val = i2c_reg_read(addr, 0x51);
+ i2c_reg_write(addr, 0x5d, val); /* set link_bw */
+ val = i2c_reg_read(addr, 0x52);
+ i2c_reg_write(addr, 0x5e, val); /* set lane_cnt */
+ val = i2c_reg_read(addr, 0x53);
+ i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */
+
+ i2c_reg_write(addr, 0x5f, 0x0d); /* start training */
+}
+
+void dp501_powerup(u8 addr)
+{
+ dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
+ dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/
+ i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
+ dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
+ dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
+ i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
+ dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
+ dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
+ dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */
+
+#ifdef CONFIG_SYS_DP501_VCAPCTRL0
+ i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);
+#else
+ i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
+#endif
+
+#ifdef CONFIG_SYS_DP501_DIFFERENTIAL
+ i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */
+ i2c_reg_write(addr + 2, 0x25, 0x04);
+ i2c_reg_write(addr + 2, 0x26, 0x10);
+#else
+ i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
+#endif
+
+ i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
+ i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
+ i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
+ i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
+ dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
+ i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
+ i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
+ i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
+
+ if (dp501_detect_cable_adapter(addr)) {
+ printf("DVI/HDMI cable adapter detected\n");
+ i2c_reg_write(addr, 0x5e, 0x04); /* enable 4 channel */
+ dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
+ } else {
+ printf("no DVI/HDMI cable adapter detected\n");
+ dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
+
+ dp501_link_training(addr);
+ }
+}
+
+void dp501_powerdown(u8 addr)
+{
+ dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */
+}
diff --git a/board/gdsys/common/dp501.h b/board/gdsys/common/dp501.h
new file mode 100644
index 0000000..8dc3215
--- /dev/null
+++ b/board/gdsys/common/dp501.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DP501_H_
+#define _DP501_H_
+
+void dp501_powerup(u8 addr);
+void dp501_powerdown(u8 addr);
+
+#endif
diff --git a/board/gdsys/common/fpga.c b/board/gdsys/common/fpga.c
new file mode 100644
index 0000000..e10c105
--- /dev/null
+++ b/board/gdsys/common/fpga.c
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <gdsys_fpga.h>
+
+#include <asm/io.h>
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+ out_le16(reg, data);
+
+ return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+ *data = in_le16(reg);
+
+ return 0;
+}
diff --git a/board/gdsys/common/ihs_mdio.c b/board/gdsys/common/ihs_mdio.c
new file mode 100644
index 0000000..1d6eb7b
--- /dev/null
+++ b/board/gdsys/common/ihs_mdio.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <gdsys_fpga.h>
+#include <miiphy.h>
+
+#include "ihs_mdio.h"
+
+static int ihs_mdio_idle(struct mii_dev *bus)
+{
+ struct ihs_mdio_info *info = bus->priv;
+ u16 val;
+ unsigned int ctr = 0;
+
+ do {
+ FPGA_GET_REG(info->fpga, mdio.control, &val);
+ udelay(100);
+ if (ctr++ > 10)
+ return -1;
+ } while (!(val & (1 << 12)));
+
+ return 0;
+}
+
+static int ihs_mdio_reset(struct mii_dev *bus)
+{
+ ihs_mdio_idle(bus);
+
+ return 0;
+}
+
+static int ihs_mdio_read(struct mii_dev *bus, int addr, int dev_addr,
+ int regnum)
+{
+ struct ihs_mdio_info *info = bus->priv;
+ u16 val;
+
+ ihs_mdio_idle(bus);
+
+ FPGA_SET_REG(info->fpga, mdio.control,
+ ((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10));
+
+ /* wait for rx data available */
+ udelay(100);
+
+ FPGA_GET_REG(info->fpga, mdio.rx_data, &val);
+
+ return val;
+}
+
+static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr,
+ int regnum, u16 value)
+{
+ struct ihs_mdio_info *info = bus->priv;
+
+ ihs_mdio_idle(bus);
+
+ FPGA_SET_REG(info->fpga, mdio.address_data, value);
+ FPGA_SET_REG(info->fpga, mdio.control,
+ ((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10));
+
+ return 0;
+}
+
+int ihs_mdio_init(struct ihs_mdio_info *info)
+{
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate FSL MDIO bus\n");
+ return -1;
+ }
+
+ bus->read = ihs_mdio_read;
+ bus->write = ihs_mdio_write;
+ bus->reset = ihs_mdio_reset;
+ sprintf(bus->name, info->name);
+
+ bus->priv = info;
+
+ return mdio_register(bus);
+}
diff --git a/board/gdsys/common/ihs_mdio.h b/board/gdsys/common/ihs_mdio.h
new file mode 100644
index 0000000..64b4049
--- /dev/null
+++ b/board/gdsys/common/ihs_mdio.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _IHS_MDIO_H_
+#define _IHS_MDIO_H_
+
+struct ihs_mdio_info {
+ u32 fpga;
+ char *name;
+};
+
+int ihs_mdio_init(struct ihs_mdio_info *info);
+
+#endif
diff --git a/board/gdsys/common/mclink.c b/board/gdsys/common/mclink.c
new file mode 100644
index 0000000..9f230c9
--- /dev/null
+++ b/board/gdsys/common/mclink.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <errno.h>
+
+#include <gdsys_fpga.h>
+
+enum {
+ MCINT_SLAVE_LINK_CHANGED_EV = 1 << 7,
+ MCINT_TX_ERROR_EV = 1 << 9,
+ MCINT_TX_BUFFER_FREE = 1 << 10,
+ MCINT_TX_PACKET_TRANSMITTED_EV = 1 << 11,
+ MCINT_RX_ERROR_EV = 1 << 13,
+ MCINT_RX_CONTENT_AVAILABLE = 1 << 14,
+ MCINT_RX_PACKET_RECEIVED_EV = 1 << 15,
+};
+
+int mclink_probe(void)
+{
+ unsigned int k;
+ int slaves = 0;
+
+ for (k = 0; k < CONFIG_SYS_MCLINK_MAX; ++k) {
+ int timeout = 0;
+ unsigned int ctr = 0;
+ u16 mc_status;
+
+ FPGA_GET_REG(k, mc_status, &mc_status);
+
+ if (!(mc_status & (1 << 15)))
+ break;
+
+ FPGA_SET_REG(k, mc_control, 0x8000);
+
+ FPGA_GET_REG(k, mc_status, &mc_status);
+ while (!(mc_status & (1 << 14))) {
+ udelay(100);
+ if (ctr++ > 500) {
+ timeout = 1;
+ break;
+ }
+ FPGA_GET_REG(k, mc_status, &mc_status);
+ }
+ if (timeout)
+ break;
+
+ printf("waited %d us for mclink %d to come up\n", ctr * 100, k);
+
+ slaves++;
+ }
+
+ return slaves;
+}
+
+int mclink_send(u8 slave, u16 addr, u16 data)
+{
+ unsigned int ctr = 0;
+ u16 int_status;
+ u16 rx_cmd_status;
+ u16 rx_cmd;
+
+ /* reset interrupt status */
+ FPGA_GET_REG(0, mc_int, &int_status);
+ FPGA_SET_REG(0, mc_int, int_status);
+
+ /* send */
+ FPGA_SET_REG(0, mc_tx_address, addr);
+ FPGA_SET_REG(0, mc_tx_data, data);
+ FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14);
+ FPGA_SET_REG(0, mc_control, 0x8001);
+
+ /* wait for reply */
+ FPGA_GET_REG(0, mc_int, &int_status);
+ while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) {
+ udelay(100);
+ if (ctr++ > 3)
+ return -ETIMEDOUT;
+ FPGA_GET_REG(0, mc_int, &int_status);
+ }
+
+ FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
+ rx_cmd = (rx_cmd_status >> 12) & 0x03;
+ if (rx_cmd != 0)
+ printf("mclink_send: received cmd %d, expected %d\n", rx_cmd,
+ 0);
+
+ return 0;
+}
+
+int mclink_receive(u8 slave, u16 addr, u16 *data)
+{
+ u16 rx_cmd_status;
+ u16 rx_cmd;
+ u16 int_status;
+ unsigned int ctr = 0;
+
+ /* send read request */
+ FPGA_SET_REG(0, mc_tx_address, addr);
+ FPGA_SET_REG(0, mc_tx_cmd,
+ ((slave & 0x03) << 14) | (1 << 12) | (1 << 0));
+ FPGA_SET_REG(0, mc_control, 0x8001);
+
+
+ /* wait for reply */
+ FPGA_GET_REG(0, mc_int, &int_status);
+ while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) {
+ udelay(100);
+ if (ctr++ > 3)
+ return -ETIMEDOUT;
+ FPGA_GET_REG(0, mc_int, &int_status);
+ }
+
+ /* check reply */
+ FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
+ if ((rx_cmd_status >> 14) != slave) {
+ printf("mclink_receive: reply from slave %d, expected %d\n",
+ rx_cmd_status >> 14, slave);
+ return -EINVAL;
+ }
+
+ rx_cmd = (rx_cmd_status >> 12) & 0x03;
+ if (rx_cmd != 1) {
+ printf("mclink_send: received cmd %d, expected %d\n",
+ rx_cmd, 1);
+ return -EIO;
+ }
+
+ FPGA_GET_REG(0, mc_rx_data, data);
+
+ return 0;
+}
diff --git a/board/gdsys/common/mclink.h b/board/gdsys/common/mclink.h
new file mode 100644
index 0000000..febd46a
--- /dev/null
+++ b/board/gdsys/common/mclink.h
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MCLINK_H_
+#define _MCLINK_H_
+
+int mclink_probe(void);
+int mclink_send(u8 slave, u16 addr, u16 data);
+int mclink_receive(u8 slave, u16 addr, u16 *data);
+
+#endif
diff --git a/board/gdsys/common/miiphybb.c b/board/gdsys/common/miiphybb.c
new file mode 100644
index 0000000..3105629
--- /dev/null
+++ b/board/gdsys/common/miiphybb.c
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include <asm/io.h>
+
+struct io_bb_pinset {
+ int mdio;
+ int mdc;
+};
+
+static int io_bb_mii_init(struct bb_miiphy_bus *bus)
+{
+ return 0;
+}
+
+static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
+{
+ struct io_bb_pinset *pins = bus->priv;
+
+ out_be32((void *)GPIO0_TCR,
+ in_be32((void *)GPIO0_TCR) | pins->mdio);
+
+ return 0;
+}
+
+static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+ struct io_bb_pinset *pins = bus->priv;
+
+ out_be32((void *)GPIO0_TCR,
+ in_be32((void *)GPIO0_TCR) & ~pins->mdio);
+
+ return 0;
+}
+
+static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+ struct io_bb_pinset *pins = bus->priv;
+
+ if (v)
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | pins->mdio);
+ else
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~pins->mdio);
+
+ return 0;
+}
+
+static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+ struct io_bb_pinset *pins = bus->priv;
+
+ *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0);
+
+ return 0;
+}
+
+static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+ struct io_bb_pinset *pins = bus->priv;
+
+ if (v)
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | pins->mdc);
+ else
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~pins->mdc);
+
+ return 0;
+}
+
+static int io_bb_delay(struct bb_miiphy_bus *bus)
+{
+ udelay(1);
+
+ return 0;
+}
+
+struct io_bb_pinset io_bb_pinsets[] = {
+ {
+ .mdio = CONFIG_SYS_MDIO_PIN,
+ .mdc = CONFIG_SYS_MDC_PIN,
+ },
+#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
+ {
+ .mdio = CONFIG_SYS_MDIO1_PIN,
+ .mdc = CONFIG_SYS_MDC1_PIN,
+ },
+#endif
+};
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+ {
+ .name = CONFIG_SYS_GBIT_MII_BUSNAME,
+ .init = io_bb_mii_init,
+ .mdio_active = io_bb_mdio_active,
+ .mdio_tristate = io_bb_mdio_tristate,
+ .set_mdio = io_bb_set_mdio,
+ .get_mdio = io_bb_get_mdio,
+ .set_mdc = io_bb_set_mdc,
+ .delay = io_bb_delay,
+ .priv = &io_bb_pinsets[0],
+ },
+#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME
+ {
+ .name = CONFIG_SYS_GBIT_MII1_BUSNAME,
+ .init = io_bb_mii_init,
+ .mdio_active = io_bb_mdio_active,
+ .mdio_tristate = io_bb_mdio_tristate,
+ .set_mdio = io_bb_set_mdio,
+ .get_mdio = io_bb_get_mdio,
+ .set_mdc = io_bb_set_mdc,
+ .delay = io_bb_delay,
+ .priv = &io_bb_pinsets[1],
+ },
+#endif
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+ sizeof(bb_miiphy_buses[0]);
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
new file mode 100644
index 0000000..55ecdf1
--- /dev/null
+++ b/board/gdsys/common/osd.c
@@ -0,0 +1,451 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <malloc.h>
+
+#include "dp501.h"
+#include <gdsys_fpga.h>
+
+#define CH7301_I2C_ADDR 0x75
+
+#define ICS8N3QV01_I2C_ADDR 0x6E
+#define ICS8N3QV01_FREF 114285000
+#define ICS8N3QV01_FREF_LL 114285000LL
+#define ICS8N3QV01_F_DEFAULT_0 156250000LL
+#define ICS8N3QV01_F_DEFAULT_1 125000000LL
+#define ICS8N3QV01_F_DEFAULT_2 100000000LL
+#define ICS8N3QV01_F_DEFAULT_3 25175000LL
+
+#define SIL1178_MASTER_I2C_ADDRESS 0x38
+#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+
+#define DP501_I2C_ADDR 0x08
+
+#define PIXCLK_640_480_60 25180000
+
+enum {
+ CH7301_CM = 0x1c, /* Clock Mode Register */
+ CH7301_IC = 0x1d, /* Input Clock Register */
+ CH7301_GPIO = 0x1e, /* GPIO Control Register */
+ CH7301_IDF = 0x1f, /* Input Data Format Register */
+ CH7301_CD = 0x20, /* Connection Detect Register */
+ CH7301_DC = 0x21, /* DAC Control Register */
+ CH7301_HPD = 0x23, /* Hot Plug Detection Register */
+ CH7301_TCTL = 0x31, /* DVI Control Input Register */
+ CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
+ CH7301_TPD = 0x34, /* DVI PLL Divide Register */
+ CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
+ CH7301_TPF = 0x36, /* DVI PLL Filter Register */
+ CH7301_TCT = 0x37, /* DVI Clock Test Register */
+ CH7301_TSTP = 0x48, /* Test Pattern Register */
+ CH7301_PM = 0x49, /* Power Management register */
+ CH7301_VID = 0x4a, /* Version ID Register */
+ CH7301_DID = 0x4b, /* Device ID Register */
+ CH7301_DSP = 0x56, /* DVI Sync polarity Register */
+};
+
+unsigned int base_width;
+unsigned int base_height;
+size_t bufsize;
+u16 *buf;
+
+unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
+
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
+#endif
+
+#ifdef CONFIG_SYS_CH7301_I2C
+int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
+#endif
+
+#ifdef CONFIG_SYS_SIL1178_I2C
+int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
+#endif
+
+#ifdef CONFIG_SYS_DP501_I2C
+int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
+#endif
+
+
+#ifdef CONFIG_SYS_MPC92469AC
+static void mpc92469ac_calc_parameters(unsigned int fout,
+ unsigned int *post_div, unsigned int *feedback_div)
+{
+ unsigned int n = *post_div;
+ unsigned int m = *feedback_div;
+ unsigned int a;
+ unsigned int b = 14745600 / 16;
+
+ if (fout < 50169600)
+ n = 8;
+ else if (fout < 100339199)
+ n = 4;
+ else if (fout < 200678399)
+ n = 2;
+ else
+ n = 1;
+
+ a = fout * n + (b / 2); /* add b/2 for proper rounding */
+
+ m = a / b;
+
+ *post_div = n;
+ *feedback_div = m;
+}
+
+static void mpc92469ac_set(unsigned screen, unsigned int fout)
+{
+ unsigned int n;
+ unsigned int m;
+ unsigned int bitval = 0;
+ mpc92469ac_calc_parameters(fout, &n, &m);
+
+ switch (n) {
+ case 1:
+ bitval = 0x00;
+ break;
+ case 2:
+ bitval = 0x01;
+ break;
+ case 4:
+ bitval = 0x02;
+ break;
+ case 8:
+ bitval = 0x03;
+ break;
+ }
+
+ FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
+}
+#endif
+
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+
+static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
+{
+ unsigned long long n;
+ unsigned long long mint;
+ unsigned long long mfrac;
+ u8 reg_a, reg_b, reg_c, reg_d, reg_f;
+ unsigned long long fout_calc;
+
+ if (index > 3)
+ return 0;
+
+ reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index);
+ reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index);
+ reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index);
+ reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index);
+ reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index);
+
+ mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
+ mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
+ | (reg_d >> 7);
+ n = reg_d & 0x7f;
+
+ fout_calc = (mint * ICS8N3QV01_FREF_LL
+ + mfrac * ICS8N3QV01_FREF_LL / 262144LL
+ + ICS8N3QV01_FREF_LL / 524288LL
+ + n / 2)
+ / n
+ * 1000000
+ / (1000000 - 100);
+
+ return fout_calc;
+}
+
+
+static void ics8n3qv01_calc_parameters(unsigned int fout,
+ unsigned int *_mint, unsigned int *_mfrac,
+ unsigned int *_n)
+{
+ unsigned int n;
+ unsigned int foutiic;
+ unsigned int fvcoiic;
+ unsigned int mint;
+ unsigned long long mfrac;
+
+ n = (2215000000U + fout / 2) / fout;
+ if ((n & 1) && (n > 5))
+ n -= 1;
+
+ foutiic = fout - (fout / 10000);
+ fvcoiic = foutiic * n;
+
+ mint = fvcoiic / 114285000;
+ if ((mint < 17) || (mint > 63))
+ printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
+
+ mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
+ / 114285000LL;
+
+ *_mint = mint;
+ *_mfrac = mfrac;
+ *_n = n;
+}
+
+static void ics8n3qv01_set(unsigned int fout)
+{
+ unsigned int n;
+ unsigned int mint;
+ unsigned int mfrac;
+ unsigned int fout_calc;
+ unsigned long long fout_prog;
+ long long off_ppm;
+ u8 reg0, reg4, reg8, reg12, reg18, reg20;
+
+ fout_calc = ics8n3qv01_get_fout_calc(1);
+ off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
+ / ICS8N3QV01_F_DEFAULT_1;
+ printf(" PLL is off by %lld ppm\n", off_ppm);
+ fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
+ / ICS8N3QV01_F_DEFAULT_1;
+ ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
+
+ reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
+ reg0 |= (mint & 0x1f) << 1;
+ reg0 |= (mfrac >> 17) & 0x01;
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0);
+
+ reg4 = mfrac >> 9;
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4);
+
+ reg8 = mfrac >> 1;
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8);
+
+ reg12 = mfrac << 7;
+ reg12 |= n & 0x7f;
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12);
+
+ reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03;
+ reg18 |= 0x20;
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18);
+
+ reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
+ reg20 |= mint & (1 << 5);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20);
+}
+#endif
+
+static int osd_write_videomem(unsigned screen, unsigned offset,
+ u16 *data, size_t charcount)
+{
+ unsigned int k;
+
+ for (k = 0; k < charcount; ++k) {
+ if (offset + k >= bufsize)
+ return -1;
+ FPGA_SET_REG(screen, videomem[offset + k], data[k]);
+ }
+
+ return charcount;
+}
+
+static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned screen;
+
+ for (screen = 0; screen <= max_osd_screen; ++screen) {
+ unsigned x;
+ unsigned y;
+ unsigned charcount;
+ unsigned len;
+ u8 color;
+ unsigned int k;
+ char *text;
+ int res;
+
+ if (argc < 5) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ color = simple_strtoul(argv[3], NULL, 16);
+ text = argv[4];
+ charcount = strlen(text);
+ len = (charcount > bufsize) ? bufsize : charcount;
+
+ for (k = 0; k < len; ++k)
+ buf[k] = (text[k] << 8) | color;
+
+ res = osd_write_videomem(screen, y * base_width + x, buf, len);
+ if (res < 0)
+ return res;
+ }
+
+ return 0;
+}
+
+int osd_probe(unsigned screen)
+{
+ u16 version;
+ u16 features;
+ int old_bus = i2c_get_bus_num();
+ bool pixclock_present = false;
+ bool output_driver_present = false;
+
+ FPGA_GET_REG(0, osd.version, &version);
+ FPGA_GET_REG(0, osd.features, &features);
+
+ base_width = ((features & 0x3f00) >> 8) + 1;
+ base_height = (features & 0x001f) + 1;
+ bufsize = base_width * base_height;
+ buf = malloc(sizeof(u16) * bufsize);
+ if (!buf)
+ return -1;
+
+ printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+ screen, version/100, version%100, base_width, base_height);
+
+ /* setup pixclock */
+
+#ifdef CONFIG_SYS_MPC92469AC
+ pixclock_present = true;
+ mpc92469ac_set(screen, PIXCLK_640_480_60);
+#endif
+
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+ i2c_set_bus_num(ics8n3qv01_i2c[screen]);
+ if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
+ ics8n3qv01_set(PIXCLK_640_480_60);
+ pixclock_present = true;
+ }
+#endif
+
+ if (!pixclock_present)
+ printf(" no pixelclock found\n");
+
+ /* setup output driver */
+
+#ifdef CONFIG_SYS_CH7301_I2C
+ i2c_set_bus_num(ch7301_i2c[screen]);
+ if (!i2c_probe(CH7301_I2C_ADDR)) {
+ u8 value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+
+ if (value == 0x17) {
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+ output_driver_present = true;
+ }
+ }
+#endif
+
+#ifdef CONFIG_SYS_SIL1178_I2C
+ i2c_set_bus_num(sil1178_i2c[screen]);
+ if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
+ if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) {
+ /*
+ * magic initialization sequence,
+ * adapted from datasheet
+ */
+ i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+ output_driver_present = true;
+ }
+ }
+#endif
+
+#ifdef CONFIG_SYS_DP501_I2C
+ i2c_set_bus_num(dp501_i2c[screen]);
+ if (!i2c_probe(DP501_I2C_ADDR)) {
+ dp501_powerup(DP501_I2C_ADDR);
+ output_driver_present = true;
+ }
+#endif
+
+ if (!output_driver_present)
+ printf(" no output driver found\n");
+
+ FPGA_SET_REG(screen, osd.control, 0x0049);
+
+ FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
+ FPGA_SET_REG(screen, osd.x_pos, 0x007f);
+ FPGA_SET_REG(screen, osd.y_pos, 0x005f);
+
+ if (screen > max_osd_screen)
+ max_osd_screen = screen;
+
+ i2c_set_bus_num(old_bus);
+
+ return 0;
+}
+
+int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned screen;
+
+ for (screen = 0; screen <= max_osd_screen; ++screen) {
+ unsigned x;
+ unsigned y;
+ unsigned k;
+ u16 buffer[base_width];
+ char *rp;
+ u16 *wp = buffer;
+ unsigned count = (argc > 4) ?
+ simple_strtoul(argv[4], NULL, 16) : 1;
+
+ if ((argc < 4) || (strlen(argv[3]) % 4)) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ rp = argv[3];
+
+
+ while (*rp) {
+ char substr[5];
+
+ memcpy(substr, rp, 4);
+ substr[4] = 0;
+ *wp = simple_strtoul(substr, NULL, 16);
+
+ rp += 4;
+ wp++;
+ if (wp - buffer > base_width)
+ break;
+ }
+
+ for (k = 0; k < count; ++k) {
+ unsigned offset =
+ y * base_width + x + k * (wp - buffer);
+ osd_write_videomem(screen, offset, buffer,
+ wp - buffer);
+ }
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ osdw, 5, 0, osd_write,
+ "write 16-bit hex encoded buffer to osd memory",
+ "pos_x pos_y buffer count\n"
+);
+
+U_BOOT_CMD(
+ osdp, 5, 0, osd_print,
+ "write ASCII buffer to osd memory",
+ "pos_x pos_y color text\n"
+);
diff --git a/board/gdsys/common/osd.h b/board/gdsys/common/osd.h
new file mode 100644
index 0000000..440b276
--- /dev/null
+++ b/board/gdsys/common/osd.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _OSD_H_
+#define _OSD_H_
+
+int osd_probe(unsigned screen);
+
+#endif
diff --git a/board/gdsys/common/phy.c b/board/gdsys/common/phy.c
new file mode 100644
index 0000000..fb92658
--- /dev/null
+++ b/board/gdsys/common/phy.c
@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <miiphy.h>
+
+enum {
+ MIICMD_SET,
+ MIICMD_MODIFY,
+ MIICMD_VERIFY_VALUE,
+ MIICMD_WAIT_FOR_VALUE,
+};
+
+struct mii_setupcmd {
+ u8 token;
+ u8 reg;
+ u16 data;
+ u16 mask;
+ u32 timeout;
+};
+
+/*
+ * verify we are talking to a 88e1518
+ */
+struct mii_setupcmd verify_88e1518[] = {
+ { MIICMD_SET, 22, 0x0000 },
+ { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff },
+ { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 },
+};
+
+/*
+ * workaround for erratum mentioned in 88E1518 release notes
+ */
+struct mii_setupcmd fixup_88e1518[] = {
+ { MIICMD_SET, 22, 0x00ff },
+ { MIICMD_SET, 17, 0x214b },
+ { MIICMD_SET, 16, 0x2144 },
+ { MIICMD_SET, 17, 0x0c28 },
+ { MIICMD_SET, 16, 0x2146 },
+ { MIICMD_SET, 17, 0xb233 },
+ { MIICMD_SET, 16, 0x214d },
+ { MIICMD_SET, 17, 0xcc0c },
+ { MIICMD_SET, 16, 0x2159 },
+ { MIICMD_SET, 22, 0x00fb },
+ { MIICMD_SET, 7, 0xc00d },
+ { MIICMD_SET, 22, 0x0000 },
+};
+
+/*
+ * default initialization:
+ * - set RGMII receive timing to "receive clock transition when data stable"
+ * - set RGMII transmit timing to "transmit clock internally delayed"
+ * - set RGMII output impedance target to 78,8 Ohm
+ * - run output impedance calibration
+ * - set autonegotiation advertise to 1000FD only
+ */
+struct mii_setupcmd default_88e1518[] = {
+ { MIICMD_SET, 22, 0x0002 },
+ { MIICMD_MODIFY, 21, 0x0030, 0x0030 },
+ { MIICMD_MODIFY, 25, 0x0000, 0x0003 },
+ { MIICMD_MODIFY, 24, 0x8000, 0x8000 },
+ { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 },
+ { MIICMD_SET, 22, 0x0000 },
+ { MIICMD_MODIFY, 4, 0x0000, 0x01e0 },
+ { MIICMD_MODIFY, 9, 0x0200, 0x0300 },
+};
+
+/*
+ * turn off CLK125 for PHY daughterboard
+ */
+struct mii_setupcmd ch1fix_88e1518[] = {
+ { MIICMD_SET, 22, 0x0002 },
+ { MIICMD_MODIFY, 16, 0x0006, 0x0006 },
+ { MIICMD_SET, 22, 0x0000 },
+};
+
+/*
+ * perform copper software reset
+ */
+struct mii_setupcmd swreset_88e1518[] = {
+ { MIICMD_SET, 22, 0x0000 },
+ { MIICMD_MODIFY, 0, 0x8000, 0x8000 },
+ { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 },
+};
+
+/*
+ * special one for 88E1514:
+ * Force SGMII to Copper mode
+ */
+struct mii_setupcmd mii_to_copper_88e1514[] = {
+ { MIICMD_SET, 22, 0x0012 },
+ { MIICMD_MODIFY, 20, 0x0001, 0x0007 },
+ { MIICMD_MODIFY, 20, 0x8000, 0x8000 },
+ { MIICMD_SET, 22, 0x0000 },
+};
+
+/*
+ * turn off SGMII auto-negotiation
+ */
+struct mii_setupcmd sgmii_autoneg_off_88e1518[] = {
+ { MIICMD_SET, 22, 0x0001 },
+ { MIICMD_MODIFY, 0, 0x0000, 0x1000 },
+ { MIICMD_MODIFY, 0, 0x8000, 0x8000 },
+ { MIICMD_SET, 22, 0x0000 },
+};
+
+/*
+ * invert LED2 polarity
+ */
+struct mii_setupcmd invert_led2_88e1514[] = {
+ { MIICMD_SET, 22, 0x0003 },
+ { MIICMD_MODIFY, 17, 0x0030, 0x0010 },
+ { MIICMD_SET, 22, 0x0000 },
+};
+
+static int process_setupcmd(const char *bus, unsigned char addr,
+ struct mii_setupcmd *setupcmd)
+{
+ int res;
+ u8 reg = setupcmd->reg;
+ u16 data = setupcmd->data;
+ u16 mask = setupcmd->mask;
+ u32 timeout = setupcmd->timeout;
+ u16 orig_data;
+ unsigned long start;
+
+ debug("mii %s:%u reg %2u ", bus, addr, reg);
+
+ switch (setupcmd->token) {
+ case MIICMD_MODIFY:
+ res = miiphy_read(bus, addr, reg, &orig_data);
+ if (res)
+ break;
+ debug("is %04x. (value %04x mask %04x) ", orig_data, data,
+ mask);
+ data = (orig_data & ~mask) | (data & mask);
+ /* fallthrough */
+ case MIICMD_SET:
+ debug("=> %04x\n", data);
+ res = miiphy_write(bus, addr, reg, data);
+ break;
+ case MIICMD_VERIFY_VALUE:
+ res = miiphy_read(bus, addr, reg, &orig_data);
+ if (res)
+ break;
+ if ((orig_data & mask) != (data & mask))
+ res = -1;
+ debug("(value %04x mask %04x) == %04x? %s\n", data, mask,
+ orig_data, res ? "FAIL" : "PASS");
+ break;
+ case MIICMD_WAIT_FOR_VALUE:
+ res = -1;
+ start = get_timer(0);
+ while ((res != 0) && (get_timer(start) < timeout)) {
+ res = miiphy_read(bus, addr, reg, &orig_data);
+ if (res)
+ continue;
+ if ((orig_data & mask) != (data & mask))
+ res = -1;
+ }
+ debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data,
+ mask, orig_data, res ? "FAIL" : "PASS",
+ get_timer(start));
+ break;
+ default:
+ res = -1;
+ break;
+ }
+
+ return res;
+}
+
+static int process_setup(const char *bus, unsigned char addr,
+ struct mii_setupcmd *setupcmd, unsigned int count)
+{
+ int res = 0;
+ unsigned int k;
+
+ for (k = 0; k < count; ++k) {
+ res = process_setupcmd(bus, addr, &setupcmd[k]);
+ if (res) {
+ printf("mii cmd %u on bus %s addr %u failed, aborting setup\n",
+ setupcmd[k].token, bus, addr);
+ break;
+ }
+ }
+
+ return res;
+}
+
+int setup_88e1518(const char *bus, unsigned char addr)
+{
+ int res;
+
+ res = process_setup(bus, addr,
+ verify_88e1518, ARRAY_SIZE(verify_88e1518));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ default_88e1518, ARRAY_SIZE(default_88e1518));
+ if (res)
+ return res;
+
+ if (addr) {
+ res = process_setup(bus, addr,
+ ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
+ if (res)
+ return res;
+ }
+
+ res = process_setup(bus, addr,
+ swreset_88e1518, ARRAY_SIZE(swreset_88e1518));
+ if (res)
+ return res;
+
+ return 0;
+}
+
+int setup_88e1514(const char *bus, unsigned char addr)
+{
+ int res;
+
+ res = process_setup(bus, addr,
+ verify_88e1518, ARRAY_SIZE(verify_88e1518));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ fixup_88e1518, ARRAY_SIZE(fixup_88e1518));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ mii_to_copper_88e1514,
+ ARRAY_SIZE(mii_to_copper_88e1514));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ sgmii_autoneg_off_88e1518,
+ ARRAY_SIZE(sgmii_autoneg_off_88e1518));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ invert_led2_88e1514,
+ ARRAY_SIZE(invert_led2_88e1514));
+ if (res)
+ return res;
+
+ res = process_setup(bus, addr,
+ default_88e1518, ARRAY_SIZE(default_88e1518));
+ if (res)
+ return res;
+
+ if (addr) {
+ res = process_setup(bus, addr,
+ ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518));
+ if (res)
+ return res;
+ }
+
+ res = process_setup(bus, addr,
+ swreset_88e1518, ARRAY_SIZE(swreset_88e1518));
+ if (res)
+ return res;
+
+ return 0;
+}
diff --git a/board/gdsys/common/phy.h b/board/gdsys/common/phy.h
new file mode 100644
index 0000000..afbdc65
--- /dev/null
+++ b/board/gdsys/common/phy.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PHY_H_
+#define _PHY_H_
+
+int setup_88e1514(const char *bus, unsigned char addr);
+int setup_88e1518(const char *bus, unsigned char addr);
+
+#endif
diff --git a/board/gdsys/dlvision/Kconfig b/board/gdsys/dlvision/Kconfig
new file mode 100644
index 0000000..8db4fbe
--- /dev/null
+++ b/board/gdsys/dlvision/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DLVISION
+
+config SYS_BOARD
+ default "dlvision"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "dlvision"
+
+endif
diff --git a/board/gdsys/dlvision/MAINTAINERS b/board/gdsys/dlvision/MAINTAINERS
new file mode 100644
index 0000000..e4d40f8
--- /dev/null
+++ b/board/gdsys/dlvision/MAINTAINERS
@@ -0,0 +1,6 @@
+DLVISION BOARD
+M: Dirk Eibach <eibach@gdsys.de>
+S: Maintained
+F: board/gdsys/dlvision/
+F: include/configs/dlvision.h
+F: configs/dlvision_defconfig
diff --git a/board/gdsys/dlvision/Makefile b/board/gdsys/dlvision/Makefile
new file mode 100644
index 0000000..755eb4c
--- /dev/null
+++ b/board/gdsys/dlvision/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = dlvision.o
diff --git a/board/gdsys/dlvision/dlvision.c b/board/gdsys/dlvision/dlvision.c
new file mode 100644
index 0000000..32f7ba3
--- /dev/null
+++ b/board/gdsys/dlvision/dlvision.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+enum {
+ HWTYPE_DLVISION_CPU = 0,
+ HWTYPE_DLVISION_CON = 1,
+};
+
+#define HWREV_100 6
+
+int board_early_init_f(void)
+{
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks
+ * -> ca. 15 us
+ */
+ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
+
+ /*
+ * setup io-latches
+ */
+ out_le16((void *)CONFIG_SYS_LATCH_BASE, 0x00f0);
+ out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x100), 0x0002);
+ out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x200), 0x0000);
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ /*
+ * set "startup-finished"-gpios
+ */
+ gpio_write_bit(21, 0);
+ gpio_write_bit(22, 1);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+ u8 channel2_msr = in_8((void *)CONFIG_UART_BASE + 0x26);
+ u8 channel3_msr = in_8((void *)CONFIG_UART_BASE + 0x36);
+ u8 channel7_msr = in_8((void *)CONFIG_UART_BASE + 0x76);
+ u8 unit_type;
+ u8 local_con;
+ u8 audio;
+ u8 hardware_version;
+
+ printf("Board: ");
+
+ unit_type = (channel2_msr & 0x80) ? 0x01 : 0x00;
+ local_con = (channel2_msr & 0x20) ? 0x01 : 0x00;
+ audio = (channel3_msr & 0x20) ? 0x01 : 0x00;
+ hardware_version =
+ ((channel7_msr & 0x20) ? 0x01 : 0x00)
+ | ((channel7_msr & 0x80) ? 0x02 : 0x00)
+ | ((channel7_msr & 0x40) ? 0x04 : 0x00);
+
+ switch (unit_type) {
+ case HWTYPE_DLVISION_CON:
+ printf("DL-Vision-CON");
+ break;
+
+ case HWTYPE_DLVISION_CPU:
+ printf("DL-Vision-CPU");
+ break;
+
+ default:
+ printf("UnitType %d, unsupported", unit_type);
+ break;
+ }
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ puts("\n ");
+
+ switch (hardware_version) {
+ case HWREV_100:
+ printf("HW-Ver 1.00");
+ break;
+
+ default:
+ printf("HW-Ver %d, unsupported",
+ hardware_version);
+ break;
+ }
+
+ if (local_con)
+ printf(", local console");
+
+ if (audio)
+ printf(", audio support");
+
+ puts("\n");
+
+ return 0;
+}
diff --git a/board/gdsys/gdppc440etx/Kconfig b/board/gdsys/gdppc440etx/Kconfig
new file mode 100644
index 0000000..1f21c89
--- /dev/null
+++ b/board/gdsys/gdppc440etx/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GDPPC440ETX
+
+config SYS_BOARD
+ default "gdppc440etx"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "gdppc440etx"
+
+endif
diff --git a/board/gdsys/gdppc440etx/MAINTAINERS b/board/gdsys/gdppc440etx/MAINTAINERS
new file mode 100644
index 0000000..cd8d1c6
--- /dev/null
+++ b/board/gdsys/gdppc440etx/MAINTAINERS
@@ -0,0 +1,6 @@
+GDPPC440ETX BOARD
+M: Dirk Eibach <eibach@gdsys.de>
+S: Maintained
+F: board/gdsys/gdppc440etx/
+F: include/configs/gdppc440etx.h
+F: configs/gdppc440etx_defconfig
diff --git a/board/gdsys/gdppc440etx/Makefile b/board/gdsys/gdppc440etx/Makefile
new file mode 100644
index 0000000..7e3fc38
--- /dev/null
+++ b/board/gdsys/gdppc440etx/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = gdppc440etx.o
+extra-y += init.o
diff --git a/board/gdsys/gdppc440etx/config.mk b/board/gdsys/gdppc440etx/config.mk
new file mode 100644
index 0000000..73341a5
--- /dev/null
+++ b/board/gdsys/gdppc440etx/config.mk
@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#
+# G&D 440EP/GR ETX-Module
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c
new file mode 100644
index 0000000..04191df
--- /dev/null
+++ b/board/gdsys/gdppc440etx/gdppc440etx.c
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/yosemite/yosemite.c
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/4xx_pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+int board_early_init_f(void)
+{
+ register uint reg;
+
+ /*
+ * Setup the external bus controller/chip selects
+ */
+ mfebc(EBC0_CFG, reg);
+ mtebc(EBC0_CFG, reg | 0x04000000); /* Set ATC */
+
+ /*
+ * Setup the GPIO pins
+ */
+
+ /* setup Address lines for flash size 64Meg. */
+ out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000);
+
+ /* setup emac */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
+ out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
+ out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
+
+ /* UART0 and UART1*/
+ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000);
+ out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000);
+ out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000);
+ out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000);
+
+ /* disable boot-eeprom WP */
+ out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000);
+ out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000);
+ out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000);
+ out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000);
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000);
+
+ /* external interrupts IRQ0...3 */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
+ out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
+ out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
+
+
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ /*
+ * Setup other serial configuration
+ */
+ mfsdr(SDR0_PCI0, reg);
+ mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
+ mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
+ mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ uint pbcr;
+ int size_val;
+ uint sz;
+
+ /* Re-do sizing to get full correct info */
+ mfebc(PB0CR, pbcr);
+
+ if (gd->bd->bi_flashsize > 0x08000000)
+ panic("Max. flash banksize is 128 MB!\n");
+
+ for (sz = gd->bd->bi_flashsize, size_val = 7;
+ ((sz & 0x08000000) == 0) && (size_val > 0); --size_val)
+ sz <<= 1;
+
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtebc(PB0CR, pbcr);
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module");
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+/*
+ * Override weak pci_pre_init()
+ */
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller *hose)
+{
+ /* First call common code */
+ __pci_pre_init(hose);
+
+ /* enable 66 MHz ext. Clock */
+ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
+ out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000);
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S
new file mode 100644
index 0000000..2db84b5
--- /dev/null
+++ b/board/gdsys/gdppc440etx/init.S
@@ -0,0 +1,59 @@
+/*
+* (C) Copyright 2008
+* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+*
+* based on board/amcc/yosemite/init.S
+* original Copyright not specified there
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use
+ * the speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR,
+ 0, AC_RWX | SA_G/*|SA_I*/)
+
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR,
+ 0, AC_RWX | SA_G )
+
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE,
+ 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE,
+ 0, AC_RW | SA_IG )
+
+ /* PCI */
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE,
+ 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1,
+ 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2,
+ 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3,
+ 0, AC_RW | SA_IG )
+
+ tlbtab_end
diff --git a/board/gdsys/intip/Kconfig b/board/gdsys/intip/Kconfig
new file mode 100644
index 0000000..479bb12
--- /dev/null
+++ b/board/gdsys/intip/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_INTIP
+
+config SYS_BOARD
+ default "intip"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "intip"
+
+endif
diff --git a/board/gdsys/intip/MAINTAINERS b/board/gdsys/intip/MAINTAINERS
new file mode 100644
index 0000000..c99d507
--- /dev/null
+++ b/board/gdsys/intip/MAINTAINERS
@@ -0,0 +1,7 @@
+INTIP BOARD
+M: Dirk Eibach <eibach@gdsys.de>
+S: Maintained
+F: board/gdsys/intip/
+F: include/configs/intip.h
+F: configs/devconcenter_defconfig
+F: configs/intip_defconfig
diff --git a/board/gdsys/intip/Makefile b/board/gdsys/intip/Makefile
new file mode 100644
index 0000000..2fbc983
--- /dev/null
+++ b/board/gdsys/intip/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2008
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := intip.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+extra-y += init.o
diff --git a/board/gdsys/intip/chip_config.c b/board/gdsys/intip/chip_config.c
new file mode 100644
index 0000000..ea276a3
--- /dev/null
+++ b/board/gdsys/intip/chip_config.c
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "800-nor", "NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1000-nor", "NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1066-nor", "NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88",
+ {
+ 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1066-nand", "NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88",
+ {
+ 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0,
+ 0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/gdsys/intip/config.mk b/board/gdsys/intip/config.mk
new file mode 100644
index 0000000..c8c53e2
--- /dev/null
+++ b/board/gdsys/intip/config.mk
@@ -0,0 +1,19 @@
+#
+# (C) Copyright 2008-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+#
+# G&D CompactCenter
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/gdsys/intip/init.S b/board/gdsys/intip/init.S
new file mode 100644
index 0000000..1fc2a2f
--- /dev/null
+++ b/board/gdsys/intip/init.S
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/canyonlands/init.S
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+ * use the speed up boot process. It is patched after relocation to
+ * enable SA_I
+ */
+ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
+ 4, AC_RWX | SA_G) /* TLB 0 */
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
+ 0, AC_RWX | SA_G)
+#endif
+
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
+ AC_RW | SA_IG)
+
+ /* TLB-entry for NVRAM */
+ tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
+ AC_RW | SA_IG)
+
+ /* TLB-entry for UART */
+ tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
+ AC_RW | SA_IG)
+
+ /* TLB-entry for IO */
+ tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
+ AC_RW | SA_IG)
+
+ /* TLB-entry for OCM */
+ tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
+ AC_RWX | SA_I)
+
+ /* TLB-entry for Local Configuration registers => peripherals */
+ tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
+ 4, AC_RWX | SA_IG)
+
+ /* AHB: Internal USB Peripherals (USB, SATA) */
+ tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,
+ AC_RWX | SA_IG)
+
+ tlbtab_end
diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
new file mode 100644
index 0000000..8d01d8b
--- /dev/null
+++ b/board/gdsys/intip/intip.c
@@ -0,0 +1,221 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on board/amcc/canyonlands/canyonlands.c
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc440.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/4xx_pcie.h>
+#include <asm/ppc4xx-gpio.h>
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CONFIG_SYS_BCSR3_PCIE 0x10
+
+int board_early_init_f(void)
+{
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC3SR, 0xffffffff); /* clear all */
+ mtdcr(UIC3ER, 0x00000000); /* disable all */
+ mtdcr(UIC3CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC3SR, 0xffffffff); /* clear all */
+
+ /*
+ * Configure PFC (Pin Function Control) registers
+ * enable GPIO 49-63
+ * UART0: 4 pins
+ */
+ mtsdr(SDR0_PFC0, 0x00007fff);
+ mtsdr(SDR0_PFC1, 0x00040000);
+
+ /* Enable PCI host functionality in SDR0_PCI0 */
+ mtsdr(SDR0_PCI0, 0xe0000000);
+
+ mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
+
+ /* Setup PLB4-AHB bridge based on the system address map */
+ mtdcr(AHB_TOP, 0x8000004B);
+ mtdcr(AHB_BOT, 0x8000004B);
+
+ /*
+ * Configure USB-STP pins as alternate and not GPIO
+ * It seems to be neccessary to configure the STP pins as GPIO
+ * input at powerup (perhaps while USB reset is asserted). So
+ * we configure those pins to their "real" function now.
+ */
+ gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+ gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+
+ /* Trigger board component reset */
+ out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
+ out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
+ udelay(50);
+ out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf);
+ out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf);
+ udelay(50);
+ out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
+ out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
+
+ return 0;
+}
+
+int get_cpu_num(void)
+{
+ int cpu = NA_OR_UNKNOWN_CPU;
+
+ return cpu;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+#ifdef CONFIG_DEVCONCENTER
+ printf("Board: DevCon-Center");
+#else
+ printf("Board: Intip");
+#endif
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ /*
+ * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH
+ * (Spansion 29GL512), but the boot EBC mapping only supports a maximum
+ * of 16MBytes (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the FLASH has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfn00.0000 -> 4.cn00.0000
+ */
+
+ u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ?
+ EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
+
+ /* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
+ mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L
+ | bxcr_bw
+ | EBC_BXCR_BU_RW
+ | EBC_BXCR_BW_16BIT);
+
+ /* Remove TLB entry of boot EBC mapping */
+ remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
+
+ /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
+ program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
+
+ /*
+ * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
+ * 0xfc00.0000 is possible
+ */
+
+ /*
+ * Clear potential errors resulting from auto-calibration.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u32 sdr0_srst1 = 0;
+ u32 eth_cfg;
+
+ /*
+ * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+ * This is board specific, so let's do it here.
+ */
+ mfsdr(SDR0_ETH_CFG, eth_cfg);
+ /* disable SGMII mode */
+ eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
+ SDR0_ETH_CFG_SGMII1_ENABLE |
+ SDR0_ETH_CFG_SGMII0_ENABLE);
+ /* Set the for 2 RGMII mode */
+ /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
+ eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
+ eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+ mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+ /*
+ * The AHB Bridge core is held in reset after power-on or reset
+ * so enable it now
+ */
+ mfsdr(SDR0_SRST1, sdr0_srst1);
+ sdr0_srst1 &= ~SDR0_SRST1_AHB;
+ mtsdr(SDR0_SRST1, sdr0_srst1);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ __ft_board_setup(blob, bd);
+
+ fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
+ "disabled", sizeof("disabled"), 1);
+
+ fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
+ "disabled", sizeof("disabled"), 1);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig
new file mode 100644
index 0000000..43e1663
--- /dev/null
+++ b/board/gdsys/mpc8308/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_HRCON
+
+config SYS_BOARD
+ default "mpc8308"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "hrcon"
+
+endif
diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS
new file mode 100644
index 0000000..a7853a5
--- /dev/null
+++ b/board/gdsys/mpc8308/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8308 BOARD
+M: Dirk Eibach <eibach@gdsys.de>
+S: Maintained
+F: board/gdsys/mpc8308/
+F: include/configs/hrcon.h
+F: configs/hrcon_defconfig
diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile
new file mode 100644
index 0000000..b5dfdbb
--- /dev/null
+++ b/board/gdsys/mpc8308/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mpc8308.o sdram.o
+obj-$(CONFIG_HRCON) += hrcon.o
diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c
new file mode 100644
index 0000000..e4434b3
--- /dev/null
+++ b/board/gdsys/mpc8308/hrcon.c
@@ -0,0 +1,677 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <spi.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <fsl_esdhc.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+#include "mpc8308.h"
+
+#include <gdsys_fpga.h>
+
+#include "../common/osd.h"
+#include "../common/mclink.h"
+#include "../common/phy.h"
+
+#include <pca953x.h>
+#include <pca9698.h>
+
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_MUX_CHANNELS 2
+
+enum {
+ UNITTYPE_MAIN_SERVER = 0,
+ UNITTYPE_MAIN_USER = 1,
+ UNITTYPE_VIDEO_SERVER = 2,
+ UNITTYPE_VIDEO_USER = 3,
+};
+
+enum {
+ UNITTYPEPCB_DVI = 0,
+ UNITTYPEPCB_DP_165 = 1,
+ UNITTYPEPCB_DP_300 = 2,
+ UNITTYPEPCB_HDMI = 3,
+};
+
+enum {
+ HWVER_100 = 0,
+ HWVER_110 = 1,
+};
+
+enum {
+ FPGA_HWVER_200 = 0,
+ FPGA_HWVER_210 = 1,
+};
+
+enum {
+ COMPRESSION_NONE = 0,
+ COMPRESSION_TYPE1_DELTA = 1,
+ COMPRESSION_TYPE1_TYPE2_DELTA = 3,
+};
+
+enum {
+ AUDIO_NONE = 0,
+ AUDIO_TX = 1,
+ AUDIO_RX = 2,
+ AUDIO_RXTX = 3,
+};
+
+enum {
+ SYSCLK_147456 = 0,
+};
+
+enum {
+ RAM_DDR2_32 = 0,
+ RAM_DDR3_32 = 1,
+};
+
+enum {
+ CARRIER_SPEED_1G = 0,
+ CARRIER_SPEED_2_5G = 1,
+};
+
+enum {
+ MCFPGA_DONE = 1 << 0,
+ MCFPGA_INIT_N = 1 << 1,
+ MCFPGA_PROGRAM_N = 1 << 2,
+ MCFPGA_UPDATE_ENABLE_N = 1 << 3,
+ MCFPGA_RESET_N = 1 << 4,
+};
+
+enum {
+ GPIO_MDC = 1 << 14,
+ GPIO_MDIO = 1 << 15,
+};
+
+unsigned int mclink_fpgacount;
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+ int res;
+
+ switch (fpga) {
+ case 0:
+ out_le16(reg, data);
+ break;
+ default:
+ res = mclink_send(fpga - 1, regoff, data);
+ if (res < 0) {
+ printf("mclink_send reg %02lx data %04x returned %d\n",
+ regoff, data, res);
+ return res;
+ }
+ break;
+ }
+
+ return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+ int res;
+
+ switch (fpga) {
+ case 0:
+ *data = in_le16(reg);
+ break;
+ default:
+ if (fpga > mclink_fpgacount)
+ return -EINVAL;
+ res = mclink_receive(fpga - 1, regoff, data);
+ if (res < 0) {
+ printf("mclink_receive reg %02lx returned %d\n",
+ regoff, res);
+ return res;
+ }
+ }
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+ bool hw_type_cat = pca9698_get_value(0x20, 20);
+
+ puts("Board: ");
+
+ printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ return 0;
+}
+
+static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
+{
+ u16 versions;
+ u16 fpga_version;
+ u16 fpga_features;
+ unsigned unit_type;
+ unsigned unit_type_pcb_video;
+ unsigned hardware_version;
+ unsigned feature_compression;
+ unsigned feature_osd;
+ unsigned feature_audio;
+ unsigned feature_sysclock;
+ unsigned feature_ramconfig;
+ unsigned feature_carrier_speed;
+ unsigned feature_carriers;
+ unsigned feature_video_channels;
+
+ FPGA_GET_REG(fpga, versions, &versions);
+ FPGA_GET_REG(fpga, fpga_version, &fpga_version);
+ FPGA_GET_REG(fpga, fpga_features, &fpga_features);
+
+ unit_type = (versions & 0xf000) >> 12;
+ unit_type_pcb_video = (versions & 0x01c0) >> 6;
+ feature_compression = (fpga_features & 0xe000) >> 13;
+ feature_osd = fpga_features & (1<<11);
+ feature_audio = (fpga_features & 0x0600) >> 9;
+ feature_sysclock = (fpga_features & 0x0180) >> 7;
+ feature_ramconfig = (fpga_features & 0x0060) >> 5;
+ feature_carrier_speed = fpga_features & (1<<4);
+ feature_carriers = (fpga_features & 0x000c) >> 2;
+ feature_video_channels = fpga_features & 0x0003;
+
+ switch (unit_type) {
+ case UNITTYPE_MAIN_USER:
+ printf("Mainchannel");
+ break;
+
+ case UNITTYPE_VIDEO_USER:
+ printf("Videochannel");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ if (unit_type == UNITTYPE_MAIN_USER) {
+ hardware_version =
+ (!!pca9698_get_value(0x20, 24) << 0)
+ | (!!pca9698_get_value(0x20, 25) << 1)
+ | (!!pca9698_get_value(0x20, 26) << 2)
+ | (!!pca9698_get_value(0x20, 27) << 3)
+ | (!!pca9698_get_value(0x20, 28) << 4);
+ switch (hardware_version) {
+ case HWVER_100:
+ printf(" HW-Ver 1.00,");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10,");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported),",
+ hardware_version);
+ break;
+ }
+ if (rgmii2_present)
+ printf(" RGMII2,");
+ }
+
+ if (unit_type == UNITTYPE_VIDEO_USER) {
+ hardware_version = versions & 0x000f;
+ switch (hardware_version) {
+ case FPGA_HWVER_200:
+ printf(" HW-Ver 2.00,");
+ break;
+
+ case FPGA_HWVER_210:
+ printf(" HW-Ver 2.10,");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported),",
+ hardware_version);
+ break;
+ }
+ }
+
+ switch (unit_type_pcb_video) {
+ case UNITTYPEPCB_DVI:
+ printf(" DVI,");
+ break;
+
+ case UNITTYPEPCB_DP_165:
+ printf(" DP 165MPix/s,");
+ break;
+
+ case UNITTYPEPCB_DP_300:
+ printf(" DP 300MPix/s,");
+ break;
+
+ case UNITTYPEPCB_HDMI:
+ printf(" HDMI,");
+ break;
+ }
+
+ printf(" FPGA V %d.%02d\n features:",
+ fpga_version / 100, fpga_version % 100);
+
+
+ switch (feature_compression) {
+ case COMPRESSION_NONE:
+ printf(" no compression");
+ break;
+
+ case COMPRESSION_TYPE1_DELTA:
+ printf(" type1-deltacompression");
+ break;
+
+ case COMPRESSION_TYPE1_TYPE2_DELTA:
+ printf(" type1-deltacompression, type2-inlinecompression");
+ break;
+
+ default:
+ printf(" compression %d(not supported)", feature_compression);
+ break;
+ }
+
+ printf(", %sosd", feature_osd ? "" : "no ");
+
+ switch (feature_audio) {
+ case AUDIO_NONE:
+ printf(", no audio");
+ break;
+
+ case AUDIO_TX:
+ printf(", audio tx");
+ break;
+
+ case AUDIO_RX:
+ printf(", audio rx");
+ break;
+
+ case AUDIO_RXTX:
+ printf(", audio rx+tx");
+ break;
+
+ default:
+ printf(", audio %d(not supported)", feature_audio);
+ break;
+ }
+
+ puts(",\n ");
+
+ switch (feature_sysclock) {
+ case SYSCLK_147456:
+ printf("clock 147.456 MHz");
+ break;
+
+ default:
+ printf("clock %d(not supported)", feature_sysclock);
+ break;
+ }
+
+ switch (feature_ramconfig) {
+ case RAM_DDR2_32:
+ printf(", RAM 32 bit DDR2");
+ break;
+
+ case RAM_DDR3_32:
+ printf(", RAM 32 bit DDR3");
+ break;
+
+ default:
+ printf(", RAM %d(not supported)", feature_ramconfig);
+ break;
+ }
+
+ printf(", %d carrier(s) %s", feature_carriers,
+ feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
+
+ printf(", %d video channel(s)\n", feature_video_channels);
+}
+
+int last_stage_init(void)
+{
+ int slaves;
+ unsigned int k;
+ unsigned int mux_ch;
+ unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
+ u16 fpga_features;
+ bool hw_type_cat = pca9698_get_value(0x20, 20);
+ bool ch0_rgmii2_present = false;
+
+ FPGA_GET_REG(0, fpga_features, &fpga_features);
+
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x20, 10, 1);
+
+ ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
+
+ /* wait for FPGA done */
+ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
+ unsigned int ctr = 0;
+
+ if (i2c_probe(mclink_controllers[k]))
+ continue;
+
+ while (!(pca953x_get_val(mclink_controllers[k])
+ & MCFPGA_DONE)) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ printf("no done for mclink_controller %d\n", k);
+ break;
+ }
+ }
+ }
+
+ if (hw_type_cat) {
+ miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
+ bb_miiphy_write);
+ for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
+ if ((mux_ch == 1) && !ch0_rgmii2_present)
+ continue;
+
+ setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
+ }
+ }
+
+ /* give slave-PLLs and Parade DP501 some time to be up and running */
+ udelay(500000);
+
+ mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
+ slaves = mclink_probe();
+ mclink_fpgacount = 0;
+
+ print_fpga_info(0, ch0_rgmii2_present);
+ osd_probe(0);
+
+ if (slaves <= 0)
+ return 0;
+
+ mclink_fpgacount = slaves;
+
+ for (k = 1; k <= slaves; ++k) {
+ FPGA_GET_REG(k, fpga_features, &fpga_features);
+
+ print_fpga_info(k, false);
+ osd_probe(k);
+ if (hw_type_cat) {
+ miiphy_register(bb_miiphy_buses[k].name,
+ bb_miiphy_read, bb_miiphy_write);
+ setup_88e1514(bb_miiphy_buses[k].name, 0);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * provide access to fpga gpios (for I2C bitbang)
+ * (these may look all too simple but make iocon.h much more readable)
+ */
+void fpga_gpio_set(unsigned int bus, int pin)
+{
+ FPGA_SET_REG(bus, gpio.set, pin);
+}
+
+void fpga_gpio_clear(unsigned int bus, int pin)
+{
+ FPGA_SET_REG(bus, gpio.clear, pin);
+}
+
+int fpga_gpio_get(unsigned int bus, int pin)
+{
+ u16 val;
+
+ FPGA_GET_REG(bus, gpio.read, &val);
+
+ return val & pin;
+}
+
+void mpc8308_init(void)
+{
+ pca9698_direction_output(0x20, 4, 1);
+}
+
+void mpc8308_set_fpga_reset(unsigned state)
+{
+ pca9698_set_value(0x20, 4, state ? 0 : 1);
+}
+
+void mpc8308_setup_hw(void)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /*
+ * set "startup-finished"-gpios
+ */
+ setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));
+ setbits_be32(&immr->gpio[0].dat, 1 << (31-12));
+}
+
+int mpc8308_get_fpga_done(unsigned fpga)
+{
+ return pca9698_get_value(0x20, 19);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+
+ /* Enable cache snooping in eSDHC system configuration register */
+ out_be32(&sysconf->sdhccr, 0x02000000);
+
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
+static struct pci_region pcie_regions_0[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE1_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+ .size = CONFIG_SYS_PCIE1_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+void pci_init_board(void)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+ law83xx_t *pcie_law = sysconf->pcielaw;
+ struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+ /* Deassert the resets in the control register */
+ out_be32(&sysconf->pecr1, 0xE0008000);
+ udelay(2000);
+
+ /* Configure PCI Express Local Access Windows */
+ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ mpc83xx_pcie_init(1, pcie_reg);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return 1;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
+
+ return 0;
+}
+#endif
+
+/*
+ * FPGA MII bitbang implementation
+ */
+
+struct fpga_mii {
+ unsigned fpga;
+ int mdio;
+} fpga_mii[] = {
+ { 0, 1},
+ { 1, 1},
+ { 2, 1},
+ { 3, 1},
+};
+
+static int mii_dummy_init(struct bb_miiphy_bus *bus)
+{
+ return 0;
+}
+
+static int mii_mdio_active(struct bb_miiphy_bus *bus)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (fpga_mii->mdio)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+ return 0;
+}
+
+static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+
+ return 0;
+}
+
+static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (v)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
+
+ fpga_mii->mdio = v;
+
+ return 0;
+}
+
+static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+ u16 gpio;
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
+
+ *v = ((gpio & GPIO_MDIO) != 0);
+
+ return 0;
+}
+
+static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+ struct fpga_mii *fpga_mii = bus->priv;
+
+ if (v)
+ FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
+ else
+ FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
+
+ return 0;
+}
+
+static int mii_delay(struct bb_miiphy_bus *bus)
+{
+ udelay(1);
+
+ return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+ {
+ .name = "board0",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[0],
+ },
+ {
+ .name = "board1",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[1],
+ },
+ {
+ .name = "board2",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[2],
+ },
+ {
+ .name = "board3",
+ .init = mii_dummy_init,
+ .mdio_active = mii_mdio_active,
+ .mdio_tristate = mii_mdio_tristate,
+ .set_mdio = mii_set_mdio,
+ .get_mdio = mii_get_mdio,
+ .set_mdc = mii_set_mdc,
+ .delay = mii_delay,
+ .priv = &fpga_mii[3],
+ },
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+ sizeof(bb_miiphy_buses[0]);
diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c
new file mode 100644
index 0000000..4338a33
--- /dev/null
+++ b/board/gdsys/mpc8308/mpc8308.c
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
+
+#include "mpc8308.h"
+#include <gdsys_fpga.h>
+
+#define REFLECTION_TESTPATTERN 0xdede
+#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+#define REFLECTION_TESTREG reflection_low
+#else
+#define REFLECTION_TESTREG reflection_high
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+ return gd->arch.fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+ puts(" Waiting for FPGA-DONE timed out.\n");
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+ puts(" FPGA reflection test failed.\n");
+}
+
+int board_early_init_f(void)
+{
+ unsigned k;
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->arch.fpga_state[k] = 0;
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ unsigned k;
+ unsigned ctr;
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->arch.fpga_state[k] = 0;
+
+ /*
+ * reset FPGA
+ */
+ mpc8308_init();
+
+ mpc8308_set_fpga_reset(1);
+
+ mpc8308_setup_hw();
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ctr = 0;
+ while (!mpc8308_get_fpga_done(k)) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->arch.fpga_state[k] |=
+ FPGA_STATE_DONE_FAILED;
+ break;
+ }
+ }
+ }
+
+ udelay(10);
+
+ mpc8308_set_fpga_reset(0);
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ /*
+ * wait for fpga out of reset
+ */
+ ctr = 0;
+ while (1) {
+ u16 val;
+
+ FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
+
+ FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
+ if (val == REFLECTION_TESTPATTERN_INV)
+ break;
+
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->arch.fpga_state[k] |=
+ FPGA_STATE_REFLECTION_FAILED;
+ break;
+ }
+ }
+ }
+
+ return 0;
+}
diff --git a/board/gdsys/mpc8308/mpc8308.h b/board/gdsys/mpc8308/mpc8308.h
new file mode 100644
index 0000000..dc07d56
--- /dev/null
+++ b/board/gdsys/mpc8308/mpc8308.h
@@ -0,0 +1,10 @@
+#ifndef __MPC8308_H_
+#define __MPC8308_H_
+
+/* functions to be provided by board implementation */
+void mpc8308_init(void);
+void mpc8308_set_fpga_reset(unsigned state);
+void mpc8308_setup_hw(void);
+int mpc8308_get_fpga_done(unsigned fpga);
+
+#endif /* __MPC8308_H_ */
diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c
new file mode 100644
index 0000000..0fce8cf
--- /dev/null
+++ b/board/gdsys/mpc8308/sdram.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * Authors: Nick.Spence@freescale.com
+ * Wilson.Lo@freescale.com
+ * scottwood@freescale.com
+ *
+ * This files is mostly identical to the original from
+ * board\freescale\mpc8315erdb\sdram.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spd_sdram.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+ u32 msize_log2 = __ilog2(msize);
+
+ out_be32(&im->sysconf.ddrlaw[0].bar,
+ CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
+ out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+ out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+ out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+ out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+ /* Currently we use only one CS, so disable the other bank. */
+ out_be32(&im->ddr.cs_config[1], 0);
+
+ out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+ out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+ out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+ out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+ out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+ out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+ out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+ sync();
+
+ /* enable DDR controller */
+ setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+ sync();
+
+ return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+}
+
+phys_size_t initdram(int board_type)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize;
+
+ if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM */
+ msize = fixed_sdram();
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize;
+}
diff --git a/board/gdsys/p1022/Kconfig b/board/gdsys/p1022/Kconfig
new file mode 100644
index 0000000..8514d08
--- /dev/null
+++ b/board/gdsys/p1022/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CONTROLCENTERD
+
+config SYS_BOARD
+ default "p1022"
+
+config SYS_VENDOR
+ default "gdsys"
+
+config SYS_CONFIG_NAME
+ default "controlcenterd"
+
+endif
diff --git a/board/gdsys/p1022/MAINTAINERS b/board/gdsys/p1022/MAINTAINERS
new file mode 100644
index 0000000..5119fbb
--- /dev/null
+++ b/board/gdsys/p1022/MAINTAINERS
@@ -0,0 +1,9 @@
+P1022 BOARD
+M: Dirk Eibach <eibach@gdsys.de>
+S: Maintained
+F: board/gdsys/p1022/
+F: include/configs/controlcenterd.h
+F: configs/controlcenterd_36BIT_SDCARD_defconfig
+F: configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
+F: configs/controlcenterd_TRAILBLAZER_defconfig
+F: configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
diff --git a/board/gdsys/p1022/Makefile b/board/gdsys/p1022/Makefile
new file mode 100644
index 0000000..6e02447
--- /dev/null
+++ b/board/gdsys/p1022/Makefile
@@ -0,0 +1,15 @@
+#
+# Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+obj-y += law.o
+obj-y += ddr.o
+obj-y += tlb.o
+obj-y += sdhc_boot.o
+obj-$(CONFIG_CONTROLCENTERD) += controlcenterd.o controlcenterd-id.o
+obj-$(CONFIG_FSL_DIU_FB) += diu.o
diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c
new file mode 100644
index 0000000..11d075c
--- /dev/null
+++ b/board/gdsys/p1022/controlcenterd-id.c
@@ -0,0 +1,1233 @@
+/*
+ * (C) Copyright 2013
+ * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+/* TODO: some more #ifdef's to avoid unneeded code for stage 1 / stage 2 */
+
+#ifdef CCDM_ID_DEBUG
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <malloc.h>
+#include <fs.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <tpm.h>
+#include <u-boot/sha1.h>
+#include <asm/byteorder.h>
+#include <asm/unaligned.h>
+#include <pca9698.h>
+
+#undef CCDM_FIRST_STAGE
+#undef CCDM_SECOND_STAGE
+#undef CCDM_AUTO_FIRST_STAGE
+
+#ifdef CONFIG_DEVELOP
+#define CCDM_DEVELOP
+#endif
+
+#ifdef CONFIG_TRAILBLAZER
+#define CCDM_FIRST_STAGE
+#undef CCDM_SECOND_STAGE
+#else
+#undef CCDM_FIRST_STAGE
+#define CCDM_SECOND_STAGE
+#endif
+
+#if defined(CCDM_DEVELOP) && defined(CCDM_SECOND_STAGE) && \
+ !defined(CCCM_FIRST_STAGE)
+#define CCDM_AUTO_FIRST_STAGE
+#endif
+
+/* enums from TCG specs */
+enum {
+ /* capability areas */
+ TPM_CAP_NV_INDEX = 0x00000011,
+ TPM_CAP_HANDLE = 0x00000014,
+ /* resource types */
+ TPM_RT_KEY = 0x00000001,
+};
+
+/* CCDM specific contants */
+enum {
+ /* NV indices */
+ NV_COMMON_DATA_INDEX = 0x40000001,
+ /* magics for key blob chains */
+ MAGIC_KEY_PROGRAM = 0x68726500,
+ MAGIC_HMAC = 0x68616300,
+ MAGIC_END_OF_CHAIN = 0x00000000,
+ /* sizes */
+ NV_COMMON_DATA_MIN_SIZE = 3 * sizeof(uint64_t) + 2 * sizeof(uint16_t),
+};
+
+/* other constants */
+enum {
+ ESDHC_BOOT_IMAGE_SIG_OFS = 0x40,
+ ESDHC_BOOT_IMAGE_SIZE_OFS = 0x48,
+ ESDHC_BOOT_IMAGE_ADDR_OFS = 0x50,
+ ESDHC_BOOT_IMAGE_TARGET_OFS = 0x58,
+ ESDHC_BOOT_IMAGE_ENTRY_OFS = 0x60,
+};
+
+enum {
+ I2C_SOC_0 = 0,
+ I2C_SOC_1 = 1,
+};
+
+struct key_program {
+ uint32_t magic;
+ uint32_t code_crc;
+ uint32_t code_size;
+ uint8_t code[];
+};
+
+struct h_reg {
+ bool valid;
+ uint8_t digest[20];
+};
+
+
+enum access_mode {
+ HREG_NONE = 0,
+ HREG_RD = 1,
+ HREG_WR = 2,
+ HREG_RDWR = 3,
+};
+
+/* register constants */
+enum {
+ FIX_HREG_DEVICE_ID_HASH = 0,
+ FIX_HREG_SELF_HASH = 1,
+ FIX_HREG_STAGE2_HASH = 2,
+ FIX_HREG_VENDOR = 3,
+ COUNT_FIX_HREGS
+};
+
+
+/* hre opcodes */
+enum {
+ /* opcodes w/o data */
+ HRE_NOP = 0x00,
+ HRE_SYNC = HRE_NOP,
+ HRE_CHECK0 = 0x01,
+ /* opcodes w/o data, w/ sync dst */
+ /* opcodes w/ data */
+ HRE_LOAD = 0x81,
+ /* opcodes w/data, w/sync dst */
+ HRE_XOR = 0xC1,
+ HRE_AND = 0xC2,
+ HRE_OR = 0xC3,
+ HRE_EXTEND = 0xC4,
+ HRE_LOADKEY = 0xC5,
+};
+
+/* hre errors */
+enum {
+ HRE_E_OK = 0,
+ HRE_E_TPM_FAILURE,
+ HRE_E_INVALID_HREG,
+};
+
+static uint64_t device_id;
+static uint64_t device_cl;
+static uint64_t device_type;
+
+static uint32_t platform_key_handle;
+
+static void(*bl2_entry)(void);
+
+static struct h_reg pcr_hregs[24];
+static struct h_reg fix_hregs[COUNT_FIX_HREGS];
+static struct h_reg var_hregs[8];
+static uint32_t hre_tpm_err;
+static int hre_err = HRE_E_OK;
+
+#define IS_PCR_HREG(spec) ((spec) & 0x20)
+#define IS_FIX_HREG(spec) (((spec) & 0x38) == 0x08)
+#define IS_VAR_HREG(spec) (((spec) & 0x38) == 0x10)
+#define HREG_IDX(spec) ((spec) & (IS_PCR_HREG(spec) ? 0x1f : 0x7))
+
+
+static const uint8_t prg_stage1_prepare[] = {
+ 0x00, 0x20, 0x00, 0x00, /* opcode: SYNC f0 */
+ 0x00, 0x24, 0x00, 0x00, /* opcode: SYNC f1 */
+ 0x01, 0x80, 0x00, 0x00, /* opcode: CHECK0 PCR0 */
+ 0x81, 0x22, 0x00, 0x00, /* opcode: LOAD PCR0, f0 */
+ 0x01, 0x84, 0x00, 0x00, /* opcode: CHECK0 PCR1 */
+ 0x81, 0x26, 0x10, 0x00, /* opcode: LOAD PCR1, f1 */
+ 0x01, 0x88, 0x00, 0x00, /* opcode: CHECK0 PCR2 */
+ 0x81, 0x2a, 0x20, 0x00, /* opcode: LOAD PCR2, f2 */
+ 0x01, 0x8c, 0x00, 0x00, /* opcode: CHECK0 PCR3 */
+ 0x81, 0x2e, 0x30, 0x00, /* opcode: LOAD PCR3, f3 */
+};
+
+static const uint8_t prg_stage2_prepare[] = {
+ 0x00, 0x80, 0x00, 0x00, /* opcode: SYNC PCR0 */
+ 0x00, 0x84, 0x00, 0x00, /* opcode: SYNC PCR1 */
+ 0x00, 0x88, 0x00, 0x00, /* opcode: SYNC PCR2 */
+ 0x00, 0x8c, 0x00, 0x00, /* opcode: SYNC PCR3 */
+ 0x00, 0x90, 0x00, 0x00, /* opcode: SYNC PCR4 */
+};
+
+static const uint8_t prg_stage2_success[] = {
+ 0x81, 0x02, 0x40, 0x14, /* opcode: LOAD PCR4, #<20B data> */
+ 0x48, 0xfd, 0x95, 0x17, 0xe7, 0x54, 0x6b, 0x68, /* data */
+ 0x92, 0x31, 0x18, 0x05, 0xf8, 0x58, 0x58, 0x3c, /* data */
+ 0xe4, 0xd2, 0x81, 0xe0, /* data */
+};
+
+static const uint8_t prg_stage_fail[] = {
+ 0x81, 0x01, 0x00, 0x14, /* opcode: LOAD v0, #<20B data> */
+ 0xc0, 0x32, 0xad, 0xc1, 0xff, 0x62, 0x9c, 0x9b, /* data */
+ 0x66, 0xf2, 0x27, 0x49, 0xad, 0x66, 0x7e, 0x6b, /* data */
+ 0xea, 0xdf, 0x14, 0x4b, /* data */
+ 0x81, 0x42, 0x30, 0x00, /* opcode: LOAD PCR3, v0 */
+ 0x81, 0x42, 0x40, 0x00, /* opcode: LOAD PCR4, v0 */
+};
+
+static const uint8_t vendor[] = "Guntermann & Drunck";
+
+
+/**
+ * @brief read a bunch of data from MMC into memory.
+ *
+ * @param mmc pointer to the mmc structure to use.
+ * @param src offset where the data starts on MMC/SD device (in bytes).
+ * @param dst pointer to the location where the read data should be stored.
+ * @param size number of bytes to read from the MMC/SD device.
+ * @return number of bytes read or -1 on error.
+ */
+static int ccdm_mmc_read(struct mmc *mmc, u64 src, u8 *dst, int size)
+{
+ int result = 0;
+ u32 blk_len, ofs;
+ ulong block_no, n, cnt;
+ u8 *tmp_buf = NULL;
+
+ if (size <= 0)
+ goto end;
+
+ blk_len = mmc->read_bl_len;
+ tmp_buf = malloc(blk_len);
+ if (!tmp_buf)
+ goto failure;
+ block_no = src / blk_len;
+ ofs = src % blk_len;
+
+ if (ofs) {
+ n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no++, 1,
+ tmp_buf);
+ if (!n)
+ goto failure;
+ result = min(size, (int)(blk_len - ofs));
+ memcpy(dst, tmp_buf + ofs, result);
+ dst += result;
+ size -= result;
+ }
+ cnt = size / blk_len;
+ if (cnt) {
+ n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no, cnt,
+ dst);
+ if (n != cnt)
+ goto failure;
+ size -= cnt * blk_len;
+ result += cnt * blk_len;
+ dst += cnt * blk_len;
+ block_no += cnt;
+ }
+ if (size) {
+ n = mmc->block_dev.block_read(mmc->block_dev.dev, block_no++, 1,
+ tmp_buf);
+ if (!n)
+ goto failure;
+ memcpy(dst, tmp_buf, size);
+ result += size;
+ }
+ goto end;
+failure:
+ result = -1;
+end:
+ if (tmp_buf)
+ free(tmp_buf);
+ return result;
+}
+
+/**
+ * @brief returns a location where the 2nd stage bootloader can be(/ is) placed.
+ *
+ * @return pointer to the location for/of the 2nd stage bootloader
+ */
+static u8 *get_2nd_stage_bl_location(ulong target_addr)
+{
+ ulong addr;
+#ifdef CCDM_SECOND_STAGE
+ addr = getenv_ulong("loadaddr", 16, CONFIG_LOADADDR);
+#else
+ addr = target_addr;
+#endif
+ return (u8 *)(addr);
+}
+
+
+#ifdef CCDM_SECOND_STAGE
+/**
+ * @brief returns a location where the image can be(/ is) placed.
+ *
+ * @return pointer to the location for/of the image
+ */
+static u8 *get_image_location(void)
+{
+ ulong addr;
+ /* TODO use other area? */
+ addr = getenv_ulong("loadaddr", 16, CONFIG_LOADADDR);
+ return (u8 *)(addr);
+}
+#endif
+
+/**
+ * @brief get the size of a given (TPM) NV area
+ * @param index NV index of the area to get size for
+ * @param size pointer to the size
+ * @return 0 on success, != 0 on error
+ */
+static int get_tpm_nv_size(uint32_t index, uint32_t *size)
+{
+ uint32_t err;
+ uint8_t info[72];
+ uint8_t *ptr;
+ uint16_t v16;
+
+ err = tpm_get_capability(TPM_CAP_NV_INDEX, index,
+ info, sizeof(info));
+ if (err) {
+ printf("tpm_get_capability(CAP_NV_INDEX, %08x) failed: %u\n",
+ index, err);
+ return 1;
+ }
+
+ /* skip tag and nvIndex */
+ ptr = info + 6;
+ /* skip 2 pcr info fields */
+ v16 = get_unaligned_be16(ptr);
+ ptr += 2 + v16 + 1 + 20;
+ v16 = get_unaligned_be16(ptr);
+ ptr += 2 + v16 + 1 + 20;
+ /* skip permission and flags */
+ ptr += 6 + 3;
+
+ *size = get_unaligned_be32(ptr);
+ return 0;
+}
+
+/**
+ * @brief search for a key by usage auth and pub key hash.
+ * @param auth usage auth of the key to search for
+ * @param pubkey_digest (SHA1) hash of the pub key structure of the key
+ * @param[out] handle the handle of the key iff found
+ * @return 0 if key was found in TPM; != 0 if not.
+ */
+static int find_key(const uint8_t auth[20], const uint8_t pubkey_digest[20],
+ uint32_t *handle)
+{
+ uint16_t key_count;
+ uint32_t key_handles[10];
+ uint8_t buf[288];
+ uint8_t *ptr;
+ uint32_t err;
+ uint8_t digest[20];
+ size_t buf_len;
+ unsigned int i;
+
+ /* fetch list of already loaded keys in the TPM */
+ err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf));
+ if (err)
+ return -1;
+ key_count = get_unaligned_be16(buf);
+ ptr = buf + 2;
+ for (i = 0; i < key_count; ++i, ptr += 4)
+ key_handles[i] = get_unaligned_be32(ptr);
+
+ /* now search a(/ the) key which we can access with the given auth */
+ for (i = 0; i < key_count; ++i) {
+ buf_len = sizeof(buf);
+ err = tpm_get_pub_key_oiap(key_handles[i], auth, buf, &buf_len);
+ if (err && err != TPM_AUTHFAIL)
+ return -1;
+ if (err)
+ continue;
+ sha1_csum(buf, buf_len, digest);
+ if (!memcmp(digest, pubkey_digest, 20)) {
+ *handle = key_handles[i];
+ return 0;
+ }
+ }
+ return 1;
+}
+
+/**
+ * @brief read CCDM common data from TPM NV
+ * @return 0 if CCDM common data was found and read, !=0 if something failed.
+ */
+static int read_common_data(void)
+{
+ uint32_t size;
+ uint32_t err;
+ uint8_t buf[256];
+ sha1_context ctx;
+
+ if (get_tpm_nv_size(NV_COMMON_DATA_INDEX, &size) ||
+ size < NV_COMMON_DATA_MIN_SIZE)
+ return 1;
+ err = tpm_nv_read_value(NV_COMMON_DATA_INDEX,
+ buf, min(sizeof(buf), size));
+ if (err) {
+ printf("tpm_nv_read_value() failed: %u\n", err);
+ return 1;
+ }
+
+ device_id = get_unaligned_be64(buf);
+ device_cl = get_unaligned_be64(buf + 8);
+ device_type = get_unaligned_be64(buf + 16);
+
+ sha1_starts(&ctx);
+ sha1_update(&ctx, buf, 24);
+ sha1_finish(&ctx, fix_hregs[FIX_HREG_DEVICE_ID_HASH].digest);
+ fix_hregs[FIX_HREG_DEVICE_ID_HASH].valid = true;
+
+ platform_key_handle = get_unaligned_be32(buf + 24);
+
+ return 0;
+}
+
+/**
+ * @brief compute hash of bootloader itself.
+ * @param[out] dst hash register where the hash should be stored
+ * @return 0 on success, != 0 on failure.
+ *
+ * @note MUST be called at a time where the boot loader is accessible at the
+ * configured location (; so take care when code is reallocated).
+ */
+static int compute_self_hash(struct h_reg *dst)
+{
+ sha1_csum((const uint8_t *)CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_LEN, dst->digest);
+ dst->valid = true;
+ return 0;
+}
+
+int ccdm_compute_self_hash(void)
+{
+ if (!fix_hregs[FIX_HREG_SELF_HASH].valid)
+ compute_self_hash(&fix_hregs[FIX_HREG_SELF_HASH]);
+ return 0;
+}
+
+/**
+ * @brief compute the hash of the 2nd stage boot loader (on SD card)
+ * @param[out] dst hash register to store the computed hash
+ * @return 0 on success, != 0 on failure
+ *
+ * Determines the size and location of the 2nd stage boot loader on SD card,
+ * loads the 2nd stage boot loader and computes the (SHA1) hash value.
+ * Within the 1st stage boot loader, the 2nd stage boot loader is loaded at
+ * the desired memory location and the variable @a bl2_entry is set.
+ *
+ * @note This sets the variable @a bl2_entry to the entry point when the
+ * 2nd stage boot loader is loaded at its configured memory location.
+ */
+static int compute_second_stage_hash(struct h_reg *dst)
+{
+ int result = 0;
+ u32 code_len, code_offset, target_addr, exec_entry;
+ struct mmc *mmc;
+ u8 *load_addr = NULL;
+ u8 buf[128];
+
+ mmc = find_mmc_device(0);
+ if (!mmc)
+ goto failure;
+ mmc_init(mmc);
+
+ if (ccdm_mmc_read(mmc, 0, buf, sizeof(buf)) < 0)
+ goto failure;
+
+ code_offset = *(u32 *)(buf + ESDHC_BOOT_IMAGE_ADDR_OFS);
+ code_len = *(u32 *)(buf + ESDHC_BOOT_IMAGE_SIZE_OFS);
+ target_addr = *(u32 *)(buf + ESDHC_BOOT_IMAGE_TARGET_OFS);
+ exec_entry = *(u32 *)(buf + ESDHC_BOOT_IMAGE_ENTRY_OFS);
+
+ load_addr = get_2nd_stage_bl_location(target_addr);
+ if (load_addr == (u8 *)target_addr)
+ bl2_entry = (void(*)(void))exec_entry;
+
+ if (ccdm_mmc_read(mmc, code_offset, load_addr, code_len) < 0)
+ goto failure;
+
+ sha1_csum(load_addr, code_len, dst->digest);
+ dst->valid = true;
+
+ goto end;
+failure:
+ result = 1;
+ bl2_entry = NULL;
+end:
+ return result;
+}
+
+/**
+ * @brief get pointer to hash register by specification
+ * @param spec specification of a hash register
+ * @return pointer to hash register or NULL if @a spec does not qualify a
+ * valid hash register; NULL else.
+ */
+static struct h_reg *get_hreg(uint8_t spec)
+{
+ uint8_t idx;
+
+ idx = HREG_IDX(spec);
+ if (IS_FIX_HREG(spec)) {
+ if (idx < ARRAY_SIZE(fix_hregs))
+ return fix_hregs + idx;
+ hre_err = HRE_E_INVALID_HREG;
+ } else if (IS_PCR_HREG(spec)) {
+ if (idx < ARRAY_SIZE(pcr_hregs))
+ return pcr_hregs + idx;
+ hre_err = HRE_E_INVALID_HREG;
+ } else if (IS_VAR_HREG(spec)) {
+ if (idx < ARRAY_SIZE(var_hregs))
+ return var_hregs + idx;
+ hre_err = HRE_E_INVALID_HREG;
+ }
+ return NULL;
+}
+
+/**
+ * @brief get pointer of a hash register by specification and usage.
+ * @param spec specification of a hash register
+ * @param mode access mode (read or write or read/write)
+ * @return pointer to hash register if found and valid; NULL else.
+ *
+ * This func uses @a get_reg() to determine the hash register for a given spec.
+ * If a register is found it is validated according to the desired access mode.
+ * The value of automatic registers (PCR register and fixed registers) is
+ * loaded or computed on read access.
+ */
+static struct h_reg *access_hreg(uint8_t spec, enum access_mode mode)
+{
+ struct h_reg *result;
+
+ result = get_hreg(spec);
+ if (!result)
+ return NULL;
+
+ if (mode & HREG_WR) {
+ if (IS_FIX_HREG(spec)) {
+ hre_err = HRE_E_INVALID_HREG;
+ return NULL;
+ }
+ }
+ if (mode & HREG_RD) {
+ if (!result->valid) {
+ if (IS_PCR_HREG(spec)) {
+ hre_tpm_err = tpm_pcr_read(HREG_IDX(spec),
+ result->digest, 20);
+ result->valid = (hre_tpm_err == TPM_SUCCESS);
+ } else if (IS_FIX_HREG(spec)) {
+ switch (HREG_IDX(spec)) {
+ case FIX_HREG_DEVICE_ID_HASH:
+ read_common_data();
+ break;
+ case FIX_HREG_SELF_HASH:
+ ccdm_compute_self_hash();
+ break;
+ case FIX_HREG_STAGE2_HASH:
+ compute_second_stage_hash(result);
+ break;
+ case FIX_HREG_VENDOR:
+ memcpy(result->digest, vendor, 20);
+ result->valid = true;
+ break;
+ }
+ } else {
+ result->valid = true;
+ }
+ }
+ if (!result->valid) {
+ hre_err = HRE_E_INVALID_HREG;
+ return NULL;
+ }
+ }
+
+ return result;
+}
+
+static void *compute_and(void *_dst, const void *_src, size_t n)
+{
+ uint8_t *dst = _dst;
+ const uint8_t *src = _src;
+ size_t i;
+
+ for (i = n; i-- > 0; )
+ *dst++ &= *src++;
+
+ return _dst;
+}
+
+static void *compute_or(void *_dst, const void *_src, size_t n)
+{
+ uint8_t *dst = _dst;
+ const uint8_t *src = _src;
+ size_t i;
+
+ for (i = n; i-- > 0; )
+ *dst++ |= *src++;
+
+ return _dst;
+}
+
+static void *compute_xor(void *_dst, const void *_src, size_t n)
+{
+ uint8_t *dst = _dst;
+ const uint8_t *src = _src;
+ size_t i;
+
+ for (i = n; i-- > 0; )
+ *dst++ ^= *src++;
+
+ return _dst;
+}
+
+static void *compute_extend(void *_dst, const void *_src, size_t n)
+{
+ uint8_t digest[20];
+ sha1_context ctx;
+
+ sha1_starts(&ctx);
+ sha1_update(&ctx, _dst, n);
+ sha1_update(&ctx, _src, n);
+ sha1_finish(&ctx, digest);
+ memcpy(_dst, digest, min(n, sizeof(digest)));
+
+ return _dst;
+}
+
+static int hre_op_loadkey(struct h_reg *src_reg, struct h_reg *dst_reg,
+ const void *key, size_t key_size)
+{
+ uint32_t parent_handle;
+ uint32_t key_handle;
+
+ if (!src_reg || !dst_reg || !src_reg->valid || !dst_reg->valid)
+ return -1;
+ if (find_key(src_reg->digest, dst_reg->digest, &parent_handle))
+ return -1;
+ hre_tpm_err = tpm_load_key2_oiap(parent_handle, key, key_size,
+ src_reg->digest, &key_handle);
+ if (hre_tpm_err) {
+ hre_err = HRE_E_TPM_FAILURE;
+ return -1;
+ }
+ /* TODO remember key handle somehow? */
+
+ return 0;
+}
+
+/**
+ * @brief executes the next opcode on the hash register engine.
+ * @param[in,out] ip pointer to the opcode (instruction pointer)
+ * @param[in,out] code_size (remaining) size of the code
+ * @return new instruction pointer on success, NULL on error.
+ */
+static const uint8_t *hre_execute_op(const uint8_t **ip, size_t *code_size)
+{
+ bool dst_modified = false;
+ uint32_t ins;
+ uint8_t opcode;
+ uint8_t src_spec;
+ uint8_t dst_spec;
+ uint16_t data_size;
+ struct h_reg *src_reg, *dst_reg;
+ uint8_t buf[20];
+ const uint8_t *src_buf, *data;
+ uint8_t *ptr;
+ int i;
+ void * (*bin_func)(void *, const void *, size_t);
+
+ if (*code_size < 4)
+ return NULL;
+
+ ins = get_unaligned_be32(*ip);
+ opcode = **ip;
+ data = *ip + 4;
+ src_spec = (ins >> 18) & 0x3f;
+ dst_spec = (ins >> 12) & 0x3f;
+ data_size = (ins & 0x7ff);
+
+ debug("HRE: ins=%08x (op=%02x, s=%02x, d=%02x, L=%d)\n", ins,
+ opcode, src_spec, dst_spec, data_size);
+
+ if ((opcode & 0x80) && (data_size + 4) > *code_size)
+ return NULL;
+
+ src_reg = access_hreg(src_spec, HREG_RD);
+ if (hre_err || hre_tpm_err)
+ return NULL;
+ dst_reg = access_hreg(dst_spec, (opcode & 0x40) ? HREG_RDWR : HREG_WR);
+ if (hre_err || hre_tpm_err)
+ return NULL;
+
+ switch (opcode) {
+ case HRE_NOP:
+ goto end;
+ case HRE_CHECK0:
+ if (src_reg) {
+ for (i = 0; i < 20; ++i) {
+ if (src_reg->digest[i])
+ return NULL;
+ }
+ }
+ break;
+ case HRE_LOAD:
+ bin_func = memcpy;
+ goto do_bin_func;
+ case HRE_XOR:
+ bin_func = compute_xor;
+ goto do_bin_func;
+ case HRE_AND:
+ bin_func = compute_and;
+ goto do_bin_func;
+ case HRE_OR:
+ bin_func = compute_or;
+ goto do_bin_func;
+ case HRE_EXTEND:
+ bin_func = compute_extend;
+do_bin_func:
+ if (!dst_reg)
+ return NULL;
+ if (src_reg) {
+ src_buf = src_reg->digest;
+ } else {
+ if (!data_size) {
+ memset(buf, 0, 20);
+ src_buf = buf;
+ } else if (data_size == 1) {
+ memset(buf, *data, 20);
+ src_buf = buf;
+ } else if (data_size >= 20) {
+ src_buf = data;
+ } else {
+ src_buf = buf;
+ for (ptr = (uint8_t *)src_buf, i = 20; i > 0;
+ i -= data_size, ptr += data_size)
+ memcpy(ptr, data,
+ min_t(size_t, i, data_size));
+ }
+ }
+ bin_func(dst_reg->digest, src_buf, 20);
+ dst_reg->valid = true;
+ dst_modified = true;
+ break;
+ case HRE_LOADKEY:
+ if (hre_op_loadkey(src_reg, dst_reg, data, data_size))
+ return NULL;
+ break;
+ default:
+ return NULL;
+ }
+
+ if (dst_reg && dst_modified && IS_PCR_HREG(dst_spec)) {
+ hre_tpm_err = tpm_extend(HREG_IDX(dst_spec), dst_reg->digest,
+ dst_reg->digest);
+ if (hre_tpm_err) {
+ hre_err = HRE_E_TPM_FAILURE;
+ return NULL;
+ }
+ }
+end:
+ *ip += 4;
+ *code_size -= 4;
+ if (opcode & 0x80) {
+ *ip += data_size;
+ *code_size -= data_size;
+ }
+
+ return *ip;
+}
+
+/**
+ * @brief runs a program on the hash register engine.
+ * @param code pointer to the (HRE) code.
+ * @param code_size size of the code (in bytes).
+ * @return 0 on success, != 0 on failure.
+ */
+static int hre_run_program(const uint8_t *code, size_t code_size)
+{
+ size_t code_left;
+ const uint8_t *ip = code;
+
+ code_left = code_size;
+ hre_tpm_err = 0;
+ hre_err = HRE_E_OK;
+ while (code_left > 0)
+ if (!hre_execute_op(&ip, &code_left))
+ return -1;
+
+ return hre_err;
+}
+
+static int check_hmac(struct key_program *hmac,
+ const uint8_t *data, size_t data_size)
+{
+ uint8_t key[20], computed_hmac[20];
+ uint32_t type;
+
+ type = get_unaligned_be32(hmac->code);
+ if (type != 0)
+ return 1;
+ memset(key, 0, sizeof(key));
+ compute_extend(key, pcr_hregs[1].digest, 20);
+ compute_extend(key, pcr_hregs[2].digest, 20);
+ compute_extend(key, pcr_hregs[3].digest, 20);
+ compute_extend(key, pcr_hregs[4].digest, 20);
+
+ sha1_hmac(key, sizeof(key), data, data_size, computed_hmac);
+
+ return memcmp(computed_hmac, hmac->code + 4, 20);
+}
+
+static int verify_program(struct key_program *prg)
+{
+ uint32_t crc;
+ crc = crc32(0, prg->code, prg->code_size);
+
+ if (crc != prg->code_crc) {
+ printf("HRC crc mismatch: %08x != %08x\n",
+ crc, prg->code_crc);
+ return 1;
+ }
+ return 0;
+}
+
+#if defined(CCDM_FIRST_STAGE) || (defined CCDM_AUTO_FIRST_STAGE)
+static struct key_program *load_sd_key_program(void)
+{
+ u32 code_len, code_offset;
+ struct mmc *mmc;
+ u8 buf[128];
+ struct key_program *result = NULL, *hmac = NULL;
+ struct key_program header;
+
+ mmc = find_mmc_device(0);
+ if (!mmc)
+ return NULL;
+ mmc_init(mmc);
+
+ if (ccdm_mmc_read(mmc, 0, buf, sizeof(buf)) <= 0)
+ goto failure;
+
+ code_offset = *(u32 *)(buf + ESDHC_BOOT_IMAGE_ADDR_OFS);
+ code_len = *(u32 *)(buf + ESDHC_BOOT_IMAGE_SIZE_OFS);
+
+ code_offset += code_len;
+ /* TODO: the following needs to be the size of the 2nd stage env */
+ code_offset += CONFIG_ENV_SIZE;
+
+ if (ccdm_mmc_read(mmc, code_offset, buf, 4*3) < 0)
+ goto failure;
+
+ header.magic = get_unaligned_be32(buf);
+ header.code_crc = get_unaligned_be32(buf + 4);
+ header.code_size = get_unaligned_be32(buf + 8);
+
+ if (header.magic != MAGIC_KEY_PROGRAM)
+ goto failure;
+
+ result = malloc(sizeof(struct key_program) + header.code_size);
+ if (!result)
+ goto failure;
+ *result = header;
+
+ printf("load key program chunk from SD card (%u bytes) ",
+ header.code_size);
+ code_offset += 12;
+ if (ccdm_mmc_read(mmc, code_offset, result->code, header.code_size)
+ < 0)
+ goto failure;
+ code_offset += header.code_size;
+ puts("\n");
+
+ if (verify_program(result))
+ goto failure;
+
+ if (ccdm_mmc_read(mmc, code_offset, buf, 4*3) < 0)
+ goto failure;
+
+ header.magic = get_unaligned_be32(buf);
+ header.code_crc = get_unaligned_be32(buf + 4);
+ header.code_size = get_unaligned_be32(buf + 8);
+
+ if (header.magic == MAGIC_HMAC) {
+ puts("check integrity\n");
+ hmac = malloc(sizeof(struct key_program) + header.code_size);
+ if (!hmac)
+ goto failure;
+ *hmac = header;
+ code_offset += 12;
+ if (ccdm_mmc_read(mmc, code_offset, hmac->code,
+ hmac->code_size) < 0)
+ goto failure;
+ if (verify_program(hmac))
+ goto failure;
+ if (check_hmac(hmac, result->code, result->code_size)) {
+ puts("key program integrity could not be verified\n");
+ goto failure;
+ }
+ puts("key program verified\n");
+ }
+
+ goto end;
+failure:
+ if (result)
+ free(result);
+ result = NULL;
+end:
+ if (hmac)
+ free(hmac);
+
+ return result;
+}
+#endif
+
+#ifdef CCDM_SECOND_STAGE
+/**
+ * @brief load a key program from file system.
+ * @param ifname interface of the file system
+ * @param dev_part_str device part of the file system
+ * @param fs_type tyep of the file system
+ * @param path path of the file to load.
+ * @return the loaded structure or NULL on failure.
+ */
+static struct key_program *load_key_chunk(const char *ifname,
+ const char *dev_part_str, int fs_type,
+ const char *path)
+{
+ struct key_program *result = NULL;
+ struct key_program header;
+ uint32_t crc;
+ uint8_t buf[12];
+ loff_t i;
+
+ if (fs_set_blk_dev(ifname, dev_part_str, fs_type))
+ goto failure;
+ if (fs_read(path, (ulong)buf, 0, 12, &i) < 0)
+ goto failure;
+ if (i < 12)
+ goto failure;
+ header.magic = get_unaligned_be32(buf);
+ header.code_crc = get_unaligned_be32(buf + 4);
+ header.code_size = get_unaligned_be32(buf + 8);
+
+ if (header.magic != MAGIC_HMAC && header.magic != MAGIC_KEY_PROGRAM)
+ goto failure;
+
+ result = malloc(sizeof(struct key_program) + header.code_size);
+ if (!result)
+ goto failure;
+ if (fs_set_blk_dev(ifname, dev_part_str, fs_type))
+ goto failure;
+ if (fs_read(path, (ulong)result, 0,
+ sizeof(struct key_program) + header.code_size, &i) < 0)
+ goto failure;
+ if (i <= 0)
+ goto failure;
+ *result = header;
+
+ crc = crc32(0, result->code, result->code_size);
+
+ if (crc != result->code_crc) {
+ printf("%s: HRC crc mismatch: %08x != %08x\n",
+ path, crc, result->code_crc);
+ goto failure;
+ }
+ goto end;
+failure:
+ if (result) {
+ free(result);
+ result = NULL;
+ }
+end:
+ return result;
+}
+#endif
+
+#if defined(CCDM_FIRST_STAGE) || (defined CCDM_AUTO_FIRST_STAGE)
+static int first_stage_actions(void)
+{
+ int result = 0;
+ struct key_program *sd_prg = NULL;
+
+ puts("CCDM S1: start actions\n");
+#ifndef CCDM_SECOND_STAGE
+ if (tpm_continue_self_test())
+ goto failure;
+#else
+ tpm_continue_self_test();
+#endif
+ mdelay(37);
+
+ if (hre_run_program(prg_stage1_prepare, sizeof(prg_stage1_prepare)))
+ goto failure;
+
+ sd_prg = load_sd_key_program();
+ if (sd_prg) {
+ if (hre_run_program(sd_prg->code, sd_prg->code_size))
+ goto failure;
+ puts("SD code run successfully\n");
+ } else {
+ puts("no key program found on SD\n");
+ goto failure;
+ }
+ goto end;
+failure:
+ result = 1;
+end:
+ if (sd_prg)
+ free(sd_prg);
+ printf("CCDM S1: actions done (%d)\n", result);
+ return result;
+}
+#endif
+
+#ifdef CCDM_FIRST_STAGE
+static int first_stage_init(void)
+{
+ int res = 0;
+ puts("CCDM S1\n");
+ if (tpm_init() || tpm_startup(TPM_ST_CLEAR))
+ return 1;
+ res = first_stage_actions();
+#ifndef CCDM_SECOND_STAGE
+ if (!res) {
+ if (bl2_entry)
+ (*bl2_entry)();
+ res = 1;
+ }
+#endif
+ return res;
+}
+#endif
+
+#ifdef CCDM_SECOND_STAGE
+static int second_stage_init(void)
+{
+ static const char mac_suffix[] = ".mac";
+ bool did_first_stage_run = true;
+ int result = 0;
+ char *cptr, *mmcdev = NULL;
+ struct key_program *hmac_blob = NULL;
+ const char *image_path = "/ccdm.itb";
+ char *mac_path = NULL;
+ ulong image_addr;
+ loff_t image_size;
+ uint32_t err;
+
+ printf("CCDM S2\n");
+ if (tpm_init())
+ return 1;
+ err = tpm_startup(TPM_ST_CLEAR);
+ if (err != TPM_INVALID_POSTINIT)
+ did_first_stage_run = false;
+
+#ifdef CCDM_AUTO_FIRST_STAGE
+ if (!did_first_stage_run && first_stage_actions())
+ goto failure;
+#else
+ if (!did_first_stage_run)
+ goto failure;
+#endif
+
+ if (hre_run_program(prg_stage2_prepare, sizeof(prg_stage2_prepare)))
+ goto failure;
+
+ /* run "prepboot" from env to get "mmcdev" set */
+ cptr = getenv("prepboot");
+ if (cptr && !run_command(cptr, 0))
+ mmcdev = getenv("mmcdev");
+ if (!mmcdev)
+ goto failure;
+
+ cptr = getenv("ramdiskimage");
+ if (cptr)
+ image_path = cptr;
+
+ mac_path = malloc(strlen(image_path) + strlen(mac_suffix) + 1);
+ if (mac_path == NULL)
+ goto failure;
+ strcpy(mac_path, image_path);
+ strcat(mac_path, mac_suffix);
+
+ /* read image from mmcdev (ccdm.itb) */
+ image_addr = (ulong)get_image_location();
+ if (fs_set_blk_dev("mmc", mmcdev, FS_TYPE_EXT))
+ goto failure;
+ if (fs_read(image_path, image_addr, 0, 0, &image_size) < 0)
+ goto failure;
+ if (image_size <= 0)
+ goto failure;
+ printf("CCDM image found on %s, %lld bytes\n", mmcdev, image_size);
+
+ hmac_blob = load_key_chunk("mmc", mmcdev, FS_TYPE_EXT, mac_path);
+ if (!hmac_blob) {
+ puts("failed to load mac file\n");
+ goto failure;
+ }
+ if (verify_program(hmac_blob)) {
+ puts("corrupted mac file\n");
+ goto failure;
+ }
+ if (check_hmac(hmac_blob, (u8 *)image_addr, image_size)) {
+ puts("image integrity could not be verified\n");
+ goto failure;
+ }
+ puts("CCDM image OK\n");
+
+ hre_run_program(prg_stage2_success, sizeof(prg_stage2_success));
+
+ goto end;
+failure:
+ result = 1;
+ hre_run_program(prg_stage_fail, sizeof(prg_stage_fail));
+end:
+ if (hmac_blob)
+ free(hmac_blob);
+ if (mac_path)
+ free(mac_path);
+
+ return result;
+}
+#endif
+
+int show_self_hash(void)
+{
+ struct h_reg *hash_ptr;
+#ifdef CCDM_SECOND_STAGE
+ struct h_reg hash;
+
+ hash_ptr = &hash;
+ if (compute_self_hash(hash_ptr))
+ return 1;
+#else
+ hash_ptr = &fix_hregs[FIX_HREG_SELF_HASH];
+#endif
+ puts("self hash: ");
+ if (hash_ptr && hash_ptr->valid)
+ print_buffer(0, hash_ptr->digest, 1, 20, 20);
+ else
+ puts("INVALID\n");
+
+ return 0;
+}
+
+/**
+ * @brief let the system hang.
+ *
+ * Called on error.
+ * Will stop the boot process; display a message and signal the error condition
+ * by blinking the "status" and the "finder" LED of the controller board.
+ *
+ * @note the develop version runs the blink cycle 2 times and then returns.
+ * The release version never returns.
+ */
+static void ccdm_hang(void)
+{
+ static const u64 f0 = 0x0ba3bb8ba2e880; /* blink code "finder" LED */
+ static const u64 s0 = 0x00f0f0f0f0f0f0; /* blink code "status" LED */
+ u64 f, s;
+ int i;
+#ifdef CCDM_DEVELOP
+ int j;
+#endif
+
+ I2C_SET_BUS(I2C_SOC_0);
+ pca9698_direction_output(0x22, 0, 0); /* Finder */
+ pca9698_direction_output(0x22, 4, 0); /* Status */
+
+ puts("### ERROR ### Please RESET the board ###\n");
+ bootstage_error(BOOTSTAGE_ID_NEED_RESET);
+#ifdef CCDM_DEVELOP
+ puts("*** ERROR ******** THIS WOULD HANG ******** ERROR ***\n");
+ puts("** but we continue since this is a DEVELOP version **\n");
+ puts("*** ERROR ******** THIS WOULD HANG ******** ERROR ***\n");
+ for (j = 2; j-- > 0;) {
+ putc('#');
+#else
+ for (;;) {
+#endif
+ f = f0;
+ s = s0;
+ for (i = 54; i-- > 0;) {
+ pca9698_set_value(0x22, 0, !(f & 1));
+ pca9698_set_value(0x22, 4, (s & 1));
+ f >>= 1;
+ s >>= 1;
+ mdelay(120);
+ }
+ }
+ puts("\ncontinue...\n");
+}
+
+int startup_ccdm_id_module(void)
+{
+ int result = 0;
+ unsigned int orig_i2c_bus;
+
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(I2C_SOC_1);
+
+ /* goto end; */
+
+#ifdef CCDM_DEVELOP
+ show_self_hash();
+#endif
+#ifdef CCDM_FIRST_STAGE
+ result = first_stage_init();
+ if (result) {
+ puts("1st stage init failed\n");
+ goto failure;
+ }
+#endif
+#ifdef CCDM_SECOND_STAGE
+ result = second_stage_init();
+ if (result) {
+ puts("2nd stage init failed\n");
+ goto failure;
+ }
+#endif
+
+ goto end;
+failure:
+ result = 1;
+end:
+ i2c_set_bus_num(orig_i2c_bus);
+ if (result)
+ ccdm_hang();
+
+ return result;
+}
diff --git a/board/gdsys/p1022/controlcenterd-id.h b/board/gdsys/p1022/controlcenterd-id.h
new file mode 100644
index 0000000..de4770a
--- /dev/null
+++ b/board/gdsys/p1022/controlcenterd-id.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2013
+ * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __CONTROLCENTER_ID_H
+#define __CONTROLCENTER_ID_H
+
+int ccdm_compute_self_hash(void);
+int startup_ccdm_id_module(void);
+
+int show_self_hash(void);
+
+#endif /* __CONTROLCENTER_ID_H */
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
new file mode 100644
index 0000000..64d90dd
--- /dev/null
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -0,0 +1,423 @@
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <asm/fsl_law.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <pca9698.h>
+#include <watchdog.h>
+#include "../common/dp501.h"
+#include "controlcenterd-id.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ HWVER_100 = 0,
+ HWVER_110 = 1,
+ HWVER_120 = 2,
+};
+
+struct ihs_fpga {
+ u32 reflection_low; /* 0x0000 */
+ u32 versions; /* 0x0004 */
+ u32 fpga_version; /* 0x0008 */
+ u32 fpga_features; /* 0x000c */
+};
+
+#ifndef CONFIG_TRAILBLAZER
+static struct pci_device_id hydra_supported[] = {
+ { 0x6d5e, 0xcdc0 },
+ {}
+};
+
+static void hydra_initialize(void);
+#endif
+
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
+
+ /* Reset eLBC_DIU and SPI_eLBC in case we are booting from SD */
+ clrsetbits_be32(&gur->pmuxcr, 0x00600000, 0x80000000);
+
+ /* Set pmuxcr to allow both i2c1 and i2c2 */
+ setbits_be32(&gur->pmuxcr, 0x00001000);
+
+ /* Set pmuxcr to enable GPIO 3_11-3_13 */
+ setbits_be32(&gur->pmuxcr, 0x00000010);
+
+ /* Set pmuxcr to enable GPIO 2_31,3_9+10 */
+ setbits_be32(&gur->pmuxcr, 0x00000020);
+
+ /* Set pmuxcr to enable GPIO 2_28-2_30 */
+ setbits_be32(&gur->pmuxcr, 0x000000c0);
+
+ /* Set pmuxcr to enable GPIO 3_20-3_22 */
+ setbits_be32(&gur->pmuxcr2, 0x03000000);
+
+ /* Set pmuxcr to enable IRQ0-2 */
+ clrbits_be32(&gur->pmuxcr, 0x00000300);
+
+ /* Set pmuxcr to disable IRQ3-11 */
+ setbits_be32(&gur->pmuxcr, 0x000000F0);
+
+ /* Read back the register to synchronize the write. */
+ in_be32(&gur->pmuxcr);
+
+ /* Set the pin muxing to enable ETSEC2. */
+ clrbits_be32(&gur->pmuxcr2, 0x001F8000);
+
+#ifdef CONFIG_TRAILBLAZER
+ /*
+ * GPIO3_10 SPERRTRIGGER
+ */
+ setbits_be32(&pgpio->gpdir, 0x00200000);
+ clrbits_be32(&pgpio->gpdat, 0x00200000);
+ udelay(100);
+ setbits_be32(&pgpio->gpdat, 0x00200000);
+ udelay(100);
+ clrbits_be32(&pgpio->gpdat, 0x00200000);
+#endif
+
+ /*
+ * GPIO3_11 CPU-TO-FPGA-RESET#
+ */
+ setbits_be32(&pgpio->gpdir, 0x00100000);
+ clrbits_be32(&pgpio->gpdat, 0x00100000);
+
+ /*
+ * GPIO3_21 CPU-STATUS-WATCHDOG-TRIGGER#
+ */
+ setbits_be32(&pgpio->gpdir, 0x00000400);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: ControlCenter DIGITAL\n");
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+/*
+ * A list of PCI and SATA slots
+ */
+enum slot_id {
+ SLOT_PCIE1 = 1,
+ SLOT_PCIE2,
+ SLOT_PCIE3,
+ SLOT_PCIE4,
+ SLOT_PCIE5,
+ SLOT_SATA1,
+ SLOT_SATA2
+};
+
+/*
+ * This array maps the slot identifiers to their names on the P1022DS board.
+ */
+static const char * const slot_names[] = {
+ [SLOT_PCIE1] = "Slot 1",
+ [SLOT_PCIE2] = "Slot 2",
+ [SLOT_PCIE3] = "Slot 3",
+ [SLOT_PCIE4] = "Slot 4",
+ [SLOT_PCIE5] = "Mini-PCIe",
+ [SLOT_SATA1] = "SATA 1",
+ [SLOT_SATA2] = "SATA 2",
+};
+
+/*
+ * This array maps a given SERDES configuration and SERDES device to the PCI or
+ * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
+ */
+static u8 serdes_dev_slot[][SATA2 + 1] = {
+ [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
+ [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+ [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
+ [PCIE2] = SLOT_PCIE5 },
+ [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
+ [PCIE2] = SLOT_PCIE3,
+ [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+ [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
+ [PCIE2] = SLOT_PCIE3 },
+ [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
+ [PCIE2] = SLOT_PCIE3,
+ [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+ [0x1c] = { [PCIE1] = SLOT_PCIE1,
+ [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
+ [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
+ [0x1f] = { [PCIE1] = SLOT_PCIE1 },
+};
+
+
+/*
+ * Returns the name of the slot to which the PCIe or SATA controller is
+ * connected
+ */
+const char *board_serdes_name(enum srds_prtcl device)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ enum slot_id slot = serdes_dev_slot[srds_cfg][device];
+ const char *name = slot_names[slot];
+
+ if (name)
+ return name;
+ else
+ return "Nothing";
+}
+
+void hw_watchdog_reset(void)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
+
+ clrbits_be32(&pgpio->gpdat, 0x00000400);
+ setbits_be32(&pgpio->gpdat, 0x00000400);
+}
+
+#ifdef CONFIG_TRAILBLAZER
+int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ return run_command(getenv("bootcmd"), flag);
+}
+
+int board_early_init_r(void)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
+
+ /*
+ * GPIO3_12 PPC_SYSTEMREADY#
+ */
+ setbits_be32(&pgpio->gpdir, 0x00080000);
+ setbits_be32(&pgpio->gpodr, 0x00080000);
+ clrbits_be32(&pgpio->gpdat, 0x00080000);
+
+ return ccdm_compute_self_hash();
+}
+
+int last_stage_init(void)
+{
+ startup_ccdm_id_module();
+ return 0;
+}
+
+#else
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+
+ hydra_initialize();
+}
+
+int board_early_init_r(void)
+{
+ unsigned int k = 0;
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
+
+ /* wait for FPGA configuration to finish */
+ while (!pca9698_get_value(0x22, 11) && (k++ < 30))
+ udelay(100000);
+
+ if (k > 30) {
+ puts("FPGA configuration timed out.\n");
+ } else {
+ /* clear FPGA reset */
+ udelay(1000);
+ setbits_be32(&pgpio->gpdat, 0x00100000);
+ }
+
+ /* give time for PCIe link training */
+ udelay(100000);
+
+ /*
+ * GPIO3_12 PPC_SYSTEMREADY#
+ */
+ setbits_be32(&pgpio->gpdir, 0x00080000);
+ setbits_be32(&pgpio->gpodr, 0x00080000);
+ clrbits_be32(&pgpio->gpdat, 0x00080000);
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x22, 7, 1);
+ udelay(500000);
+
+ dp501_powerup(0x08);
+
+ startup_ccdm_id_module();
+
+ return 0;
+}
+
+/*
+ * Initialize on-board and/or PCI Ethernet devices
+ *
+ * Returns:
+ * <0, error
+ * 0, no ethernet devices found
+ * >0, number of ethernet devices initialized
+ */
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[2];
+ unsigned int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
+
+ return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+ FT_FSL_PCI_SETUP;
+
+ return 0;
+}
+#endif
+
+static void hydra_initialize(void)
+{
+ unsigned int i;
+ pci_dev_t devno;
+
+ /* Find and probe all the matching PCI devices */
+ for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
+ u32 val;
+ struct ihs_fpga *fpga;
+ u32 versions;
+ u32 fpga_version;
+ u32 fpga_features;
+
+ unsigned hardware_version;
+ unsigned feature_uart_channels;
+ unsigned feature_sb_channels;
+
+ /* Try to enable I/O accesses and bus-mastering */
+ val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ pci_write_config_dword(devno, PCI_COMMAND, val);
+
+ /* Make sure it worked */
+ pci_read_config_dword(devno, PCI_COMMAND, &val);
+ if (!(val & PCI_COMMAND_MEMORY)) {
+ puts("Can't enable I/O memory\n");
+ continue;
+ }
+ if (!(val & PCI_COMMAND_MASTER)) {
+ puts("Can't enable bus-mastering\n");
+ continue;
+ }
+
+ /* read FPGA details */
+ fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
+ PCI_REGION_MEM);
+
+ versions = readl(&fpga->versions);
+ fpga_version = readl(&fpga->fpga_version);
+ fpga_features = readl(&fpga->fpga_features);
+
+ hardware_version = versions & 0xf;
+ feature_uart_channels = (fpga_features >> 6) & 0x1f;
+ feature_sb_channels = fpga_features & 0x1f;
+
+ printf("FPGA%d: ", i);
+
+ switch (hardware_version) {
+ case HWVER_100:
+ printf("HW-Ver 1.00\n");
+ break;
+
+ case HWVER_110:
+ printf("HW-Ver 1.10\n");
+ break;
+
+ case HWVER_120:
+ printf("HW-Ver 1.20\n");
+ break;
+
+ default:
+ printf("HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+ printf(" %d uart channel(s)", feature_uart_channels);
+ printf(" %d sideband channel(s)\n", feature_sb_channels);
+ }
+}
+#endif
diff --git a/board/gdsys/p1022/ddr.c b/board/gdsys/p1022/ddr.c
new file mode 100644
index 0000000..7596736
--- /dev/null
+++ b/board/gdsys/p1022/ddr.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+
+ if (ctrl_num) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /* set odt_rd_cfg and odt_wr_cfg. */
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 1;
+ }
+
+ popts->clk_adjust = 5;
+ popts->cpo_override = 0x1f;
+ popts->write_data_delay = 2;
+ popts->half_strength_driver_enable = 1;
+
+ /* Per AN4039, enable ZQ calibration. */
+ popts->zq_en = 1;
+}
+
+#ifdef CONFIG_SPD_EEPROM
+/*
+ * we only have a "fake" SPD-EEPROM here, which has 16 bit addresses
+ */
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+ int ret = i2c_read(i2c_address, 0, 2, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
+
+ if (ret) {
+ if (i2c_address ==
+#ifdef SPD_EEPROM_ADDRESS
+ SPD_EEPROM_ADDRESS
+#elif defined(SPD_EEPROM_ADDRESS1)
+ SPD_EEPROM_ADDRESS1
+#endif
+ ) {
+ printf("DDR: failed to read SPD from address %u\n",
+ i2c_address);
+ } else {
+ debug("DDR: failed to read SPD from address %u\n",
+ i2c_address);
+ }
+ memset(spd, 0, sizeof(generic_spd_eeprom_t));
+ }
+}
+#endif
diff --git a/board/gdsys/p1022/diu.c b/board/gdsys/p1022/diu.c
new file mode 100644
index 0000000..52ac1e6
--- /dev/null
+++ b/board/gdsys/p1022/diu.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Authors: Timur Tabi <timur@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <video_fb.h>
+#include <fsl_diu_fb.h>
+
+#define PMUXCR_ELBCDIU_MASK 0xc0000000
+#define PMUXCR_ELBCDIU_NOR16 0x80000000
+#define PMUXCR_ELBCDIU_DIU 0x40000000
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register. So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F 0x10000000
+#define AD_ALPHA_C_SHIFT 25
+#define AD_BLUE_C_SHIFT 23
+#define AD_GREEN_C_SHIFT 21
+#define AD_RED_C_SHIFT 19
+#define AD_PIXEL_S_SHIFT 16
+#define AD_COMP_3_SHIFT 12
+#define AD_COMP_2_SHIFT 8
+#define AD_COMP_1_SHIFT 4
+#define AD_COMP_0_SHIFT 0
+
+/*
+ * Variables used by the DIU/LBC switching code. It's safe to makes these
+ * global, because the DIU requires DDR, so we'll only run this code after
+ * relocation.
+ */
+static u32 pmuxcr;
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ unsigned long speed_ccb, temp;
+ u32 pixval;
+
+ speed_ccb = get_bus_freq(0);
+ temp = 1000000000 / pixclock;
+ temp *= 1000;
+ pixval = speed_ccb / temp;
+ debug("DIU pixval = %u\n", pixval);
+
+ /* Modify PXCLK in GUTS CLKDVDR */
+ temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
+ out_be32(&gur->clkdvdr, temp); /* turn off clock */
+ out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 pixel_format;
+
+ pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+ (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+ (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+ (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+ (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+ printf("DIU: Switching to %ux%u\n", xres, yres);
+
+ /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
+ clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
+ pmuxcr = in_be32(&gur->pmuxcr);
+
+ return fsl_diu_init(xres, yres, pixel_format, 0);
+}
diff --git a/board/gdsys/p1022/law.c b/board/gdsys/p1022/law.c
new file mode 100644
index 0000000..96f38f7
--- /dev/null
+++ b/board/gdsys/p1022/law.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_ELBC_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/gdsys/p1022/sdhc_boot.c b/board/gdsys/p1022/sdhc_boot.c
new file mode 100644
index 0000000..fd0e910
--- /dev/null
+++ b/board/gdsys/p1022/sdhc_boot.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <malloc.h>
+
+/*
+ * The environment variables are written to just after the u-boot image
+ * on SDCard, so we must read the MBR to get the start address and code
+ * length of the u-boot image, then calculate the address of the env.
+ */
+#define ESDHC_BOOT_IMAGE_SIZE 0x48
+#define ESDHC_BOOT_IMAGE_ADDR 0x50
+
+int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
+{
+ u8 *tmp_buf;
+ u32 blklen, code_offset, code_len, n;
+
+ blklen = mmc->read_bl_len;
+ tmp_buf = malloc(blklen);
+ if (!tmp_buf)
+ return 1;
+
+ /* read out the first block, get the config data information */
+ n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf);
+ if (!n) {
+ free(tmp_buf);
+ return 1;
+ }
+
+ /* Get the Source Address, from offset 0x50 */
+ code_offset = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_ADDR);
+
+ /* Get the code size from offset 0x48 */
+ code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
+
+ *env_addr = code_offset + code_len;
+
+ free(tmp_buf);
+
+ return 0;
+}
diff --git a/board/gdsys/p1022/tlb.c b/board/gdsys/p1022/tlb.c
new file mode 100644
index 0000000..9cad692
--- /dev/null
+++ b/board/gdsys/p1022/tlb.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * Timur Tabi <timur@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* *I*G* - eLBC */
+ SET_TLB_ENTRY(1, CONFIG_SYS_ELBC_BASE, CONFIG_SYS_ELBC_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_TRAILBLAZER)
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_256K, 1),
+#else
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+
+#ifdef CONFIG_SYS_RAMBOOT
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_1G, 1),
+#endif
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/genesi/mx51_efikamx/Kconfig b/board/genesi/mx51_efikamx/Kconfig
new file mode 100644
index 0000000..355702a
--- /dev/null
+++ b/board/genesi/mx51_efikamx/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX51_EFIKAMX
+
+config SYS_BOARD
+ default "mx51_efikamx"
+
+config SYS_VENDOR
+ default "genesi"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "mx51_efikamx"
+
+endif
diff --git a/board/genesi/mx51_efikamx/MAINTAINERS b/board/genesi/mx51_efikamx/MAINTAINERS
new file mode 100644
index 0000000..f1398c4
--- /dev/null
+++ b/board/genesi/mx51_efikamx/MAINTAINERS
@@ -0,0 +1,7 @@
+MX51_EFIKAMX BOARD
+#M: -
+S: Maintained
+F: board/genesi/mx51_efikamx/
+F: include/configs/mx51_efikamx.h
+F: configs/mx51_efikamx_defconfig
+F: configs/mx51_efikasb_defconfig
diff --git a/board/genesi/mx51_efikamx/Makefile b/board/genesi/mx51_efikamx/Makefile
new file mode 100644
index 0000000..87f5f9e
--- /dev/null
+++ b/board/genesi/mx51_efikamx/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2010, Marek Vasut <marek.vasut@gmail.com>
+#
+# BASED ON: imx51evk
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := efikamx.o efikamx-usb.o
diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c
new file mode 100644
index 0000000..0b43101
--- /dev/null
+++ b/board/genesi/mx51_efikamx/efikamx-usb.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx51.h>
+#include <asm/gpio.h>
+#include <usb/ehci-fsl.h>
+#include <usb/ulpi.h>
+#include <errno.h>
+
+#include "../../../drivers/usb/host/ehci.h"
+
+/*
+ * Configure the USB H1 and USB H2 IOMUX
+ */
+void setup_iomux_usb(void)
+{
+ static const iomux_v3_cfg_t usb_h1_pads[] = {
+ MX51_PAD_USBH1_CLK__USBH1_CLK,
+ MX51_PAD_USBH1_DIR__USBH1_DIR,
+ MX51_PAD_USBH1_STP__USBH1_STP,
+ MX51_PAD_USBH1_NXT__USBH1_NXT,
+ MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+ MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+ MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+ MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+ MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+ MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+ MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+ MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+ };
+
+ static const iomux_v3_cfg_t usb_pads[] = {
+ MX51_PAD_EIM_D27__GPIO2_9, /* USB PHY reset */
+ MX51_PAD_GPIO1_5__GPIO1_5, /* USB HUB reset */
+ NEW_PAD_CTRL(MX51_PAD_EIM_A22__GPIO2_16, 0), /* WIFI /EN */
+ NEW_PAD_CTRL(MX51_PAD_EIM_A16__GPIO2_10, 0), /* WIFI RESET */
+ NEW_PAD_CTRL(MX51_PAD_EIM_A17__GPIO2_11, 0), /* BT /EN */
+ };
+
+ imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
+
+ if (machine_is_efikasb()) {
+ static const iomux_v3_cfg_t usb_h2_pads[] = {
+ MX51_PAD_EIM_A24__USBH2_CLK,
+ MX51_PAD_EIM_A25__USBH2_DIR,
+ MX51_PAD_EIM_A26__USBH2_STP,
+ MX51_PAD_EIM_A27__USBH2_NXT,
+ MX51_PAD_EIM_D16__USBH2_DATA0,
+ MX51_PAD_EIM_D17__USBH2_DATA1,
+ MX51_PAD_EIM_D18__USBH2_DATA2,
+ MX51_PAD_EIM_D19__USBH2_DATA3,
+ MX51_PAD_EIM_D20__USBH2_DATA4,
+ MX51_PAD_EIM_D21__USBH2_DATA5,
+ MX51_PAD_EIM_D22__USBH2_DATA6,
+ MX51_PAD_EIM_D23__USBH2_DATA7,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(usb_h2_pads,
+ ARRAY_SIZE(usb_h2_pads));
+ }
+
+ imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+}
+
+/*
+ * Enable devices connected to USB BUSes
+ */
+static void efika_usb_enable_devices(void)
+{
+ /* Enable Bluetooth */
+ gpio_direction_output(IMX_GPIO_NR(2, 11), 0);
+ udelay(10000);
+ gpio_set_value(IMX_GPIO_NR(2, 11), 1);
+
+ /* Enable WiFi */
+ gpio_direction_output(IMX_GPIO_NR(2, 16), 1);
+ udelay(10000);
+
+ /* Reset the WiFi chip */
+ gpio_direction_output(IMX_GPIO_NR(2, 10), 0);
+ udelay(10000);
+ gpio_set_value(IMX_GPIO_NR(2, 10), 1);
+}
+
+/*
+ * Reset USB HUB (or HUBs on EfikaSB)
+ */
+static void efika_usb_hub_reset(void)
+{
+ /* HUB reset */
+ gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
+ udelay(1000);
+ gpio_set_value(IMX_GPIO_NR(1, 5), 0);
+ udelay(1000);
+ gpio_set_value(IMX_GPIO_NR(1, 5), 1);
+}
+
+/*
+ * Reset USB PHY (or PHYs on EfikaSB)
+ */
+static void efika_usb_phy_reset(void)
+{
+ /* SMSC 3317 PHY reset */
+ gpio_direction_output(IMX_GPIO_NR(2, 9), 0);
+ udelay(1000);
+ gpio_set_value(IMX_GPIO_NR(2, 9), 1);
+}
+
+static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio,
+ iomux_v3_cfg_t stp_pad_gpio,
+ iomux_v3_cfg_t stp_pad_usb)
+{
+ int ret;
+ struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
+ struct ulpi_viewport ulpi_vp;
+
+ imx_iomux_v3_setup_pad(stp_pad_gpio);
+ gpio_direction_output(stp_gpio, 0);
+ udelay(1000);
+ gpio_set_value(stp_gpio, 1);
+ udelay(1000);
+
+ imx_iomux_v3_setup_pad(stp_pad_usb);
+ udelay(10000);
+
+ ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
+ ulpi_vp.port_num = 0;
+
+ ret = ulpi_init(&ulpi_vp);
+ if (ret) {
+ printf("Efika USB ULPI initialization failed\n");
+ return;
+ }
+
+ /* ULPI set flags */
+ ulpi_write(&ulpi_vp, &ulpi->otg_ctrl,
+ ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN |
+ ULPI_OTG_EXTVBUSIND);
+ ulpi_write(&ulpi_vp, &ulpi->function_ctrl,
+ ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL |
+ ULPI_FC_SUSPENDM);
+ ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0);
+
+ /* Set VBus */
+ ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set,
+ ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+
+ /*
+ * Set VBusChrg
+ *
+ * NOTE: This violates USB specification, but otherwise, USB on Efika
+ * doesn't work.
+ */
+ ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS);
+}
+
+int board_ehci_hcd_init(int port)
+{
+ /* Init iMX51 EHCI */
+ efika_usb_phy_reset();
+ efika_usb_hub_reset();
+ efika_usb_enable_devices();
+
+ return 0;
+}
+
+void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
+{
+ uint32_t port = OTG_BASE_ADDR + (0x200 * CONFIG_MXC_USB_PORT);
+ struct usb_ehci *ehci = (struct usb_ehci *)port;
+ struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
+ struct ulpi_viewport ulpi_vp;
+
+ ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
+ ulpi_vp.port_num = 0;
+
+ ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS);
+
+ mdelay(50);
+
+ /* terminate the reset */
+ *reg = ehci_readl(status_reg);
+ *reg |= EHCI_PS_PE;
+}
+
+void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
+{
+ uint32_t tmp;
+
+ if (port == 0) {
+ /* Adjust UTMI PHY frequency to 24MHz */
+ tmp = readl(OTG_BASE_ADDR + 0x80c);
+ tmp = (tmp & ~0x3) | 0x01;
+ writel(tmp, OTG_BASE_ADDR + 0x80c);
+ } else if (port == 1) {
+ efika_ehci_init(ehci, IMX_GPIO_NR(1, 27),
+ MX51_PAD_USBH1_STP__GPIO1_27,
+ MX51_PAD_USBH1_STP__USBH1_STP);
+ } else if ((port == 2) && machine_is_efikasb()) {
+ efika_ehci_init(ehci, IMX_GPIO_NR(2, 20),
+ MX51_PAD_EIM_A26__GPIO2_20,
+ MX51_PAD_EIM_A26__USBH2_STP);
+ }
+
+ if (port)
+ mdelay(10);
+}
+
+/*
+ * Ethernet on the Smarttop is on the USB bus. Rather than give an error about
+ * "CPU Net Initialization Failed", just pass this test since no other settings
+ * are required. Smartbook doesn't have built-in Ethernet but we will let it
+ * pass anyway considering someone may have plugged in a USB stick and all
+ * they need to do is run "usb start".
+ */
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c
new file mode 100644
index 0000000..6ba55cd
--- /dev/null
+++ b/board/genesi/mx51_efikamx/efikamx.c
@@ -0,0 +1,509 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx51.h>
+#include <asm/gpio.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/imx-common/spi.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Compile-time error checking
+ */
+#ifndef CONFIG_MXC_SPI
+#error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
+#endif
+
+/*
+ * Board revisions
+ *
+ * Note that we get these revisions here for convenience, but we only set
+ * up for the production model Smarttop (1.3) and Smartbook (2.0).
+ *
+ */
+#define EFIKAMX_BOARD_REV_11 0x1
+#define EFIKAMX_BOARD_REV_12 0x2
+#define EFIKAMX_BOARD_REV_13 0x3
+#define EFIKAMX_BOARD_REV_14 0x4
+
+#define EFIKASB_BOARD_REV_13 0x1
+#define EFIKASB_BOARD_REV_20 0x2
+
+/*
+ * Board identification
+ */
+static u32 get_mx_rev(void)
+{
+ u32 rev = 0;
+ /*
+ * Retrieve board ID:
+ *
+ * gpio: 16 17 11
+ * ==============
+ * r1.1: 1+ 1 1
+ * r1.2: 1 1 0
+ * r1.3: 1 0 1
+ * r1.4: 1 0 0
+ *
+ * + note: r1.1 does not strap this pin properly so it needs to
+ * be hacked or ignored.
+ */
+
+ /* set to 1 in order to get correct value on board rev 1.1 */
+ gpio_direction_output(IMX_GPIO_NR(3, 16), 1);
+ gpio_direction_input(IMX_GPIO_NR(3, 11));
+ gpio_direction_input(IMX_GPIO_NR(3, 16));
+ gpio_direction_input(IMX_GPIO_NR(3, 17));
+
+ rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 16))) << 0;
+ rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 17))) << 1;
+ rev |= (!!gpio_get_value(IMX_GPIO_NR(3, 11))) << 2;
+
+ return (~rev & 0x7) + 1;
+}
+
+static iomux_v3_cfg_t const efikasb_revision_pads[] = {
+ MX51_PAD_EIM_CS3__GPIO2_28,
+ MX51_PAD_EIM_CS4__GPIO2_29,
+};
+
+static inline u32 get_sb_rev(void)
+{
+ u32 rev = 0;
+
+ imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
+ ARRAY_SIZE(efikasb_revision_pads));
+ gpio_direction_input(IMX_GPIO_NR(2, 28));
+ gpio_direction_input(IMX_GPIO_NR(2, 29));
+
+ rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 28))) << 0;
+ rev |= (!!gpio_get_value(IMX_GPIO_NR(2, 29))) << 1;
+
+ return rev;
+}
+
+inline uint32_t get_efikamx_rev(void)
+{
+ if (machine_is_efikamx())
+ return get_mx_rev();
+ else if (machine_is_efikasb())
+ return get_sb_rev();
+}
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev() | (get_efikamx_rev() << 8);
+}
+
+/*
+ * DRAM initialization
+ */
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+/*
+ * UART configuration
+ */
+static iomux_v3_cfg_t const efikamx_uart_pads[] = {
+ MX51_PAD_UART1_RXD__UART1_RXD,
+ MX51_PAD_UART1_TXD__UART1_TXD,
+ MX51_PAD_UART1_RTS__UART1_RTS,
+ MX51_PAD_UART1_CTS__UART1_CTS,
+};
+
+/*
+ * SPI configuration
+ */
+static iomux_v3_cfg_t const efikamx_spi_pads[] = {
+ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+ MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+ MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+ MX51_PAD_CSPI1_SS0__GPIO4_24,
+ MX51_PAD_CSPI1_SS1__GPIO4_25,
+ MX51_PAD_GPIO1_6__GPIO1_6,
+};
+
+#define EFIKAMX_SPI_SS0 IMX_GPIO_NR(4, 24)
+#define EFIKAMX_SPI_SS1 IMX_GPIO_NR(4, 25)
+#define EFIKAMX_PMIC_IRQ IMX_GPIO_NR(1, 6)
+
+/*
+ * PMIC configuration
+ */
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 1) ? 121 : -1;
+}
+
+static void power_init(void)
+{
+ unsigned int val;
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ struct pmic *p;
+ int ret;
+
+ ret = pmic_init(CONFIG_FSL_PMIC_BUS);
+ if (ret)
+ return;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return;
+
+ /* Write needed to Power Gate 2 register */
+ pmic_reg_read(p, REG_POWER_MISC, &val);
+ val &= ~PWGT2SPIEN;
+ pmic_reg_write(p, REG_POWER_MISC, val);
+
+ /* Externally powered */
+ pmic_reg_read(p, REG_CHARGE, &val);
+ val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+ pmic_reg_write(p, REG_CHARGE, val);
+
+ /* power up the system first */
+ pmic_reg_write(p, REG_POWER_MISC, PWUP);
+
+ /* Set core voltage to 1.1V */
+ pmic_reg_read(p, REG_SW_0, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
+ pmic_reg_write(p, REG_SW_0, val);
+
+ /* Setup VCC (SW2) to 1.25 */
+ pmic_reg_read(p, REG_SW_1, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(p, REG_SW_1, val);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.25 */
+ pmic_reg_read(p, REG_SW_2, &val);
+ val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
+ pmic_reg_write(p, REG_SW_2, val);
+ udelay(50);
+
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, &mxc_ccm->cacrr);
+
+ /* Set switchers in Auto in NORMAL mode & STANDBY mode */
+ /* Setup the switcher mode for SW1 & SW2*/
+ pmic_reg_read(p, REG_SW_4, &val);
+ val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+ pmic_reg_write(p, REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ pmic_reg_read(p, REG_SW_5, &val);
+ val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
+ (SWMODE_MASK << SWMODE4_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
+ pmic_reg_write(p, REG_SW_5, val);
+
+ /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
+ pmic_reg_read(p, REG_SETTING_0, &val);
+ val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
+ val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
+ pmic_reg_write(p, REG_SETTING_0, val);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
+ pmic_reg_read(p, REG_SETTING_1, &val);
+ val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+ val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
+ pmic_reg_write(p, REG_SETTING_1, val);
+
+ /* Enable VGEN1, VGEN2, VDIG, VPLL */
+ pmic_reg_read(p, REG_MODE_0, &val);
+ val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
+ pmic_reg_write(p, REG_MODE_0, val);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = VGEN3CONFIG | VCAMCONFIG;
+ pmic_reg_write(p, REG_MODE_1, val);
+ udelay(200);
+
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+ VVIDEOEN | VAUDIOEN | VSDEN;
+ pmic_reg_write(p, REG_MODE_1, val);
+
+ pmic_reg_read(p, REG_POWER_CTL2, &val);
+ val |= WDIRESET;
+ pmic_reg_write(p, REG_POWER_CTL2, val);
+
+ udelay(2500);
+}
+#else
+static inline void power_init(void) { }
+#endif
+
+/*
+ * MMC configuration
+ */
+#ifdef CONFIG_FSL_ESDHC
+
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {MMC_SDHC1_BASE_ADDR},
+ {MMC_SDHC2_BASE_ADDR},
+};
+
+static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
+ MX51_PAD_SD1_CMD__SD1_CMD,
+ MX51_PAD_SD1_CLK__SD1_CLK,
+ MX51_PAD_SD1_DATA0__SD1_DATA0,
+ MX51_PAD_SD1_DATA1__SD1_DATA1,
+ MX51_PAD_SD1_DATA2__SD1_DATA2,
+ MX51_PAD_SD1_DATA3__SD1_DATA3,
+ MX51_PAD_GPIO1_1__SD1_WP,
+};
+
+#define EFIKAMX_SDHC1_WP IMX_GPIO_NR(1, 1)
+
+static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
+ MX51_PAD_GPIO1_0__SD1_CD,
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, MX51_ESDHC_PAD_CTRL),
+};
+
+#define EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0)
+#define EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27)
+
+static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
+ MX51_PAD_SD2_CMD__SD2_CMD,
+ MX51_PAD_SD2_CLK__SD2_CLK,
+ MX51_PAD_SD2_DATA0__SD2_DATA0,
+ MX51_PAD_SD2_DATA1__SD2_DATA1,
+ MX51_PAD_SD2_DATA2__SD2_DATA2,
+ MX51_PAD_SD2_DATA3__SD2_DATA3,
+ MX51_PAD_GPIO1_7__SD2_WP,
+ MX51_PAD_GPIO1_8__SD2_CD,
+};
+
+#define EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8)
+#define EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7)
+
+static inline uint32_t efikamx_mmc_getcd(u32 base)
+{
+ if (base == MMC_SDHC1_BASE_ADDR)
+ if (machine_is_efikamx())
+ return EFIKAMX_SDHC1_CD;
+ else
+ return EFIKASB_SDHC1_CD;
+ else
+ return EFIKASB_SDHC2_CD;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
+ int ret = !gpio_get_value(cd);
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /*
+ * All Efika MX boards use eSDHC1 with a common write-protect GPIO
+ */
+ imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
+ ARRAY_SIZE(efikamx_sdhc1_pads));
+ gpio_direction_input(EFIKAMX_SDHC1_WP);
+
+ /*
+ * Smartbook and Smarttop differ on the location of eSDHC1
+ * carrier-detect GPIO
+ */
+ if (machine_is_efikamx()) {
+ imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);
+ gpio_direction_input(EFIKAMX_SDHC1_CD);
+ } else if (machine_is_efikasb()) {
+ imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);
+ gpio_direction_input(EFIKASB_SDHC1_CD);
+ }
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+
+ if (machine_is_efikasb()) {
+
+ imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,
+ ARRAY_SIZE(efikasb_sdhc2_pads));
+ gpio_direction_input(EFIKASB_SDHC2_CD);
+ gpio_direction_input(EFIKASB_SDHC2_WP);
+ if (!ret)
+ ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
+ }
+
+ return ret;
+}
+#endif
+
+/*
+ * PATA
+ */
+static iomux_v3_cfg_t const efikamx_pata_pads[] = {
+ MX51_PAD_NANDF_WE_B__PATA_DIOW,
+ MX51_PAD_NANDF_RE_B__PATA_DIOR,
+ MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
+ MX51_PAD_NANDF_CLE__PATA_RESET_B,
+ MX51_PAD_NANDF_WP_B__PATA_DMACK,
+ MX51_PAD_NANDF_RB0__PATA_DMARQ,
+ MX51_PAD_NANDF_RB1__PATA_IORDY,
+ MX51_PAD_GPIO_NAND__PATA_INTRQ,
+ MX51_PAD_NANDF_CS2__PATA_CS_0,
+ MX51_PAD_NANDF_CS3__PATA_CS_1,
+ MX51_PAD_NANDF_CS4__PATA_DA_0,
+ MX51_PAD_NANDF_CS5__PATA_DA_1,
+ MX51_PAD_NANDF_CS6__PATA_DA_2,
+ MX51_PAD_NANDF_D15__PATA_DATA15,
+ MX51_PAD_NANDF_D14__PATA_DATA14,
+ MX51_PAD_NANDF_D13__PATA_DATA13,
+ MX51_PAD_NANDF_D12__PATA_DATA12,
+ MX51_PAD_NANDF_D11__PATA_DATA11,
+ MX51_PAD_NANDF_D10__PATA_DATA10,
+ MX51_PAD_NANDF_D9__PATA_DATA9,
+ MX51_PAD_NANDF_D8__PATA_DATA8,
+ MX51_PAD_NANDF_D7__PATA_DATA7,
+ MX51_PAD_NANDF_D6__PATA_DATA6,
+ MX51_PAD_NANDF_D5__PATA_DATA5,
+ MX51_PAD_NANDF_D4__PATA_DATA4,
+ MX51_PAD_NANDF_D3__PATA_DATA3,
+ MX51_PAD_NANDF_D2__PATA_DATA2,
+ MX51_PAD_NANDF_D1__PATA_DATA1,
+ MX51_PAD_NANDF_D0__PATA_DATA0,
+};
+
+/*
+ * EHCI USB
+ */
+#ifdef CONFIG_CMD_USB
+extern void setup_iomux_usb(void);
+#else
+static inline void setup_iomux_usb(void) { }
+#endif
+
+/*
+ * LED configuration
+ *
+ * Smarttop LED pad config is done in the DCD
+ *
+ */
+#define EFIKAMX_LED_BLUE IMX_GPIO_NR(3, 13)
+#define EFIKAMX_LED_GREEN IMX_GPIO_NR(3, 14)
+#define EFIKAMX_LED_RED IMX_GPIO_NR(3, 15)
+
+static iomux_v3_cfg_t const efikasb_led_pads[] = {
+ MX51_PAD_GPIO1_3__GPIO1_3,
+ MX51_PAD_EIM_CS0__GPIO2_25,
+};
+
+#define EFIKASB_CAPSLOCK_LED IMX_GPIO_NR(2, 25)
+#define EFIKASB_MESSAGE_LED IMX_GPIO_NR(1, 3) /* Note: active low */
+
+/*
+ * Board initialization
+ */
+int board_early_init_f(void)
+{
+ if (machine_is_efikasb()) {
+ imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,
+ ARRAY_SIZE(efikasb_led_pads));
+ gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);
+ gpio_direction_output(EFIKASB_MESSAGE_LED, 1);
+ } else if (machine_is_efikamx()) {
+ /*
+ * Set up GPIO directions for LEDs.
+ * IOMUX has been done in the DCD already.
+ * Turn the red LED on for pre-relocation code.
+ */
+ gpio_direction_output(EFIKAMX_LED_BLUE, 0);
+ gpio_direction_output(EFIKAMX_LED_GREEN, 0);
+ gpio_direction_output(EFIKAMX_LED_RED, 1);
+ }
+
+ /*
+ * Both these pad configurations for UART and SPI are kind of redundant
+ * since they are the Power-On Defaults for the i.MX51. But, it seems we
+ * should make absolutely sure that they are set up correctly.
+ */
+ imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
+ ARRAY_SIZE(efikamx_uart_pads));
+ imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
+ ARRAY_SIZE(efikamx_spi_pads));
+
+ /* not technically required for U-Boot operation but do it anyway. */
+ gpio_direction_input(EFIKAMX_PMIC_IRQ);
+ /* Deselect both CS for now, otherwise NOR doesn't probe properly. */
+ gpio_direction_output(EFIKAMX_SPI_SS0, 0);
+ gpio_direction_output(EFIKAMX_SPI_SS1, 1);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ if (machine_is_efikamx()) {
+ /*
+ * Set up Blue LED for "In U-Boot" status.
+ * We're all relocated and ready to U-Boot!
+ */
+ gpio_set_value(EFIKAMX_LED_RED, 0);
+ gpio_set_value(EFIKAMX_LED_GREEN, 0);
+ gpio_set_value(EFIKAMX_LED_BLUE, 1);
+ }
+
+ power_init();
+
+ imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
+ ARRAY_SIZE(efikamx_pata_pads));
+ setup_iomux_usb();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ u32 rev = get_efikamx_rev();
+
+ printf("Board: Genesi Efika MX ");
+ if (machine_is_efikamx())
+ printf("Smarttop (1.%i)\n", rev & 0xf);
+ else if (machine_is_efikasb())
+ printf("Smartbook\n");
+
+ return 0;
+}
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg
new file mode 100644
index 0000000..e2911eb
--- /dev/null
+++ b/board/genesi/mx51_efikamx/imximage_mx.cfg
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2009 Pegatron Corporation
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * BASED ON: imx51evk
+ *
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+/*
+ * Essential GPIO settings to be done as early as possible
+ * PCBIDn pad settings are all the defaults except #2 which needs HVE off
+ */
+DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16
+DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17
+DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11
+DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE
+DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13
+DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14
+DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
+
+/* DDR bus IOMUX PAD settings */
+DATA 4 0x73fa850c 0x20c5 # SDODT1
+DATA 4 0x73fa8510 0x20c5 # SDODT0
+DATA 4 0x73fa84ac 0xc5 # SDWE
+DATA 4 0x73fa84b0 0xc5 # SDCKE0
+DATA 4 0x73fa84b4 0xc5 # SDCKE1
+DATA 4 0x73fa84cc 0xc5 # DRAM_CS0
+DATA 4 0x73fa84d0 0xc5 # DRAM_CS1
+DATA 4 0x73fa882c 0x2 # DRAM_B4
+DATA 4 0x73fa88a4 0x2 # DRAM_B0
+DATA 4 0x73fa88ac 0x2 # DRAM_B1
+DATA 4 0x73fa88b8 0x2 # DRAM_B2
+DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0
+DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1
+DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2
+DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
+
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
+DATA 4 0x83fd9000 0x82a20000
+/* ESDCTL_ESDCTL1 */
+DATA 4 0x83fd9008 0x82a20000
+/* ESDCTL_ESDMISC */
+DATA 4 0x83fd9010 0xcaaaf6d0
+/* ESDCTL_ESDCFG0 */
+DATA 4 0x83fd9004 0x3f3574aa
+/* ESDCTL_ESDCFG1 */
+DATA 4 0x83fd900c 0x3f3574aa
+
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
+DATA 4 0x83fd9014 0x04008008
+DATA 4 0x83fd9014 0x0000801a
+DATA 4 0x83fd9014 0x0000801b
+DATA 4 0x83fd9014 0x00448019
+DATA 4 0x83fd9014 0x07328018
+DATA 4 0x83fd9014 0x04008008
+DATA 4 0x83fd9014 0x00008010
+DATA 4 0x83fd9014 0x00008010
+DATA 4 0x83fd9014 0x06328018
+DATA 4 0x83fd9014 0x03808019
+DATA 4 0x83fd9014 0x00408019
+DATA 4 0x83fd9014 0x00008000
+
+/* Init DRAM on CS1 */
+DATA 4 0x83fd9014 0x0400800c
+DATA 4 0x83fd9014 0x0000801e
+DATA 4 0x83fd9014 0x0000801f
+DATA 4 0x83fd9014 0x0000801d
+DATA 4 0x83fd9014 0x0732801c
+DATA 4 0x83fd9014 0x0400800c
+DATA 4 0x83fd9014 0x00008014
+DATA 4 0x83fd9014 0x00008014
+DATA 4 0x83fd9014 0x0632801c
+DATA 4 0x83fd9014 0x0380801d
+DATA 4 0x83fd9014 0x0040801d
+DATA 4 0x83fd9014 0x00008004
+
+/* Write to CTL0 */
+DATA 4 0x83fd9000 0xb2a20000
+/* Write to CTL1 */
+DATA 4 0x83fd9008 0xb2a20000
+/* ESDMISC */
+DATA 4 0x83fd9010 0x000ad6d0
+/* ESDCTL_ESDCDLYGD */
+DATA 4 0x83fd9034 0x90000000
+DATA 4 0x83fd9014 0x00000000
diff --git a/board/genesi/mx51_efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg
new file mode 100644
index 0000000..a67d41b
--- /dev/null
+++ b/board/genesi/mx51_efikamx/imximage_sb.cfg
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2009 Pegatron Corporation
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ *
+ * BASED ON: imx51evk
+ *
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+*/
+/* DDR bus IOMUX PAD settings */
+DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
+DATA 4 0x73fa850c 0x20c5 # SDODT1
+DATA 4 0x73fa8510 0x20c5 # SDODT0
+DATA 4 0x73fa8848 0x4 # DDR_A1
+DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK
+DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0
+DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1
+DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2
+DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3
+DATA 4 0x73fa8820 0x0 # DDRPKS
+DATA 4 0x73fa84ac 0xe5 # SDWE
+DATA 4 0x73fa84b0 0xe5 # SDCKE0
+DATA 4 0x73fa84b4 0xe5 # SDCKE1
+DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
+DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
+
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+/* ESDCTL_ESDCTL0 */
+DATA 4 0x83fd9000 0x82a20000
+/* ESDCTL_ESDCTL1 */
+DATA 4 0x83fd9008 0x82a20000
+/* ESDCTL_ESDMISC */
+DATA 4 0x83fd9010 0xcaaaf6d0
+/* ESDCTL_ESDCFG0 */
+DATA 4 0x83fd9004 0x333574aa
+/* ESDCTL_ESDCFG1 */
+DATA 4 0x83fd900c 0x333574aa
+
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
+DATA 4 0x83fd9014 0x04008008
+DATA 4 0x83fd9014 0x0000801a
+DATA 4 0x83fd9014 0x0000801b
+DATA 4 0x83fd9014 0x00448019
+DATA 4 0x83fd9014 0x07328018
+DATA 4 0x83fd9014 0x04008008
+DATA 4 0x83fd9014 0x00008010
+DATA 4 0x83fd9014 0x00008010
+DATA 4 0x83fd9014 0x06328018
+DATA 4 0x83fd9014 0x03808019
+DATA 4 0x83fd9014 0x00408019
+DATA 4 0x83fd9014 0x00008000
+
+/* Init DRAM on CS1 */
+DATA 4 0x83fd9014 0x0400800c
+DATA 4 0x83fd9014 0x0000801e
+DATA 4 0x83fd9014 0x0000801f
+DATA 4 0x83fd9014 0x0000801d
+DATA 4 0x83fd9014 0x0732801c
+DATA 4 0x83fd9014 0x0400800c
+DATA 4 0x83fd9014 0x00008014
+DATA 4 0x83fd9014 0x00008014
+DATA 4 0x83fd9014 0x0632801c
+DATA 4 0x83fd9014 0x0380801d
+DATA 4 0x83fd9014 0x0042801d
+DATA 4 0x83fd9014 0x00008004
+
+/* Write to CTL0 */
+DATA 4 0x83fd9000 0xb2a20000
+/* Write to CTL1 */
+DATA 4 0x83fd9008 0xb2a20000
+/* ESDMISC */
+DATA 4 0x83fd9010 0xcaaaf6d0
+/* ESDCTL_ESDCDLYGD */
+DATA 4 0x83fd9034 0x90000000
+DATA 4 0x83fd9014 0x00000000
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
new file mode 100644
index 0000000..7f79fd2
--- /dev/null
+++ b/board/google/chromebook_link/Kconfig
@@ -0,0 +1,32 @@
+if TARGET_CHROMEBOOK_LINK
+
+config SYS_BOARD
+ default "chromebook_link"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_SOC
+ default "ivybridge"
+
+config SYS_CONFIG_NAME
+ default "chromebook_link"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SOUTHBRIDGE_INTEL_C216
+ select HAVE_ACPI_RESUME
+ select MARK_GRAPHICS_MEM_WRCOMB
+ select BOARD_ROMSIZE_KB_8192
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config EARLY_POST_CROS_EC
+ bool "Enable early post to Chrome OS EC"
+ default y
+
+endif
diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS
new file mode 100644
index 0000000..bc253a2
--- /dev/null
+++ b/board/google/chromebook_link/MAINTAINERS
@@ -0,0 +1,6 @@
+CHROMEBOOK LINK BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/google/chromebook_link/
+F: include/configs/chromebook_link.h
+F: configs/chromebook_link_defconfig
diff --git a/board/google/chromebook_link/Makefile b/board/google/chromebook_link/Makefile
new file mode 100644
index 0000000..a133c2e
--- /dev/null
+++ b/board/google/chromebook_link/Makefile
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ@gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += link.o
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
new file mode 100644
index 0000000..9978e92
--- /dev/null
+++ b/board/google/chromebook_link/link.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+int arch_early_init_r(void)
+{
+ if (cros_ec_board_init())
+ return -1;
+
+ return 0;
+}
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
+ .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */
+ .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */
+ .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
+ .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */
+ .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */
+ .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
+ .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
+ .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
+ .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
+ .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
+ .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
+ .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
+ .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio1 = GPIO_LEVEL_HIGH,
+ .gpio6 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio12 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+ .gpio15 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
+ .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
+ .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
+ .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
+ .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
+ .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio36 = GPIO_DIR_OUTPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio36 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_map link_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
+
+int board_early_init_f(void)
+{
+ ich_gpio_set_gpio_map(&link_gpio_map);
+
+ return 0;
+}
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+ /* GPIO Set 1 */
+ if (gpio->set1.level)
+ outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
+ if (gpio->set1.mode)
+ outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
+ if (gpio->set1.direction)
+ outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
+ if (gpio->set1.reset)
+ outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
+ if (gpio->set1.invert)
+ outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
+ if (gpio->set1.blink)
+ outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
+
+ /* GPIO Set 2 */
+ if (gpio->set2.level)
+ outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
+ if (gpio->set2.mode)
+ outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
+ if (gpio->set2.direction)
+ outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
+ if (gpio->set2.reset)
+ outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
+
+ /* GPIO Set 3 */
+ if (gpio->set3.level)
+ outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
+ if (gpio->set3.mode)
+ outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
+ if (gpio->set3.direction)
+ outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
+ if (gpio->set3.reset)
+ outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
+}
diff --git a/board/google/common/Makefile b/board/google/common/Makefile
new file mode 100644
index 0000000..b38bc14
--- /dev/null
+++ b/board/google/common/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += early_init.o
diff --git a/board/google/common/early_init.S b/board/google/common/early_init.S
new file mode 100644
index 0000000..7017185
--- /dev/null
+++ b/board/google/common/early_init.S
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+ /* Enable post codes to EC */
+#ifdef CONFIG_EARLY_POST_CROS_EC
+ mov $0x1b, %ecx
+ rdmsr
+ and $0x100, %eax
+ test %eax, %eax
+ je 1f
+
+ mov $0x8000f8f0, %eax
+ mov $0xcf8, %dx
+ out %eax, (%dx)
+ mov $0xfed1c001, %eax
+ mov $0xcfc, %dx
+ out %eax, (%dx)
+ mov $0xfed1f410, %esp
+ mov (%esp), %eax
+ and $0xfffffffb, %eax
+ mov %eax, (%esp)
+1:
+#endif
+ jmp early_board_init_ret
diff --git a/board/gumstix/duovero/Kconfig b/board/gumstix/duovero/Kconfig
new file mode 100644
index 0000000..2f8558a
--- /dev/null
+++ b/board/gumstix/duovero/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DUOVERO
+
+config SYS_BOARD
+ default "duovero"
+
+config SYS_VENDOR
+ default "gumstix"
+
+config SYS_CONFIG_NAME
+ default "duovero"
+
+endif
diff --git a/board/gumstix/duovero/MAINTAINERS b/board/gumstix/duovero/MAINTAINERS
new file mode 100644
index 0000000..87cd4e6
--- /dev/null
+++ b/board/gumstix/duovero/MAINTAINERS
@@ -0,0 +1,6 @@
+DUOVERO BOARD
+M: Ash Charles <ash@gumstix.com>
+S: Maintained
+F: board/gumstix/duovero/
+F: include/configs/duovero.h
+F: configs/duovero_defconfig
diff --git a/board/gumstix/duovero/Makefile b/board/gumstix/duovero/Makefile
new file mode 100644
index 0000000..f738c58
--- /dev/null
+++ b/board/gumstix/duovero/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := duovero.o
diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c
new file mode 100644
index 0000000..81d6c82
--- /dev/null
+++ b/board/gumstix/duovero/duovero.c
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2013
+ * Gumstix Inc. <www.gumstix.com>
+ * Maintainer: Ash Charles <ash@gumstix.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <twl6030.h>
+#include <asm/emif.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+
+#include "duovero_mux_data.h"
+
+#define WIFI_EN 43
+
+#if defined(CONFIG_CMD_NET)
+#define SMSC_NRESET 45
+static void setup_net_chip(void);
+#endif
+
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/arch/ehci.h>
+#include <asm/ehci-omap.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: duovero\n"
+};
+
+struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gpmc_init();
+
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP4_DUOVERO;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+ int ret = 0;
+ u8 val;
+
+ /* wifi setup: first enable 32Khz clock from 6030 pmic */
+ val = 0xe1;
+ ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, &val, 1);
+ if (ret)
+ printf("Failed to enable 32Khz clock to wifi module\n");
+
+ /* then setup WIFI_EN as an output pin and send reset pulse */
+ if (!gpio_request(WIFI_EN, "")) {
+ gpio_direction_output(WIFI_EN, 0);
+ gpio_set_value(WIFI_EN, 1);
+ udelay(1);
+ gpio_set_value(WIFI_EN, 0);
+ udelay(1);
+ gpio_set_value(WIFI_EN, 1);
+ }
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif
+ return 0;
+}
+
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_essential,
+ sizeof(wkup_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_non_essential,
+ sizeof(core_padconf_array_non_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_non_essential,
+ sizeof(wkup_padconf_array_non_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+
+#if defined(CONFIG_CMD_NET)
+
+#define GPMC_SIZE_16M 0xF
+#define GPMC_BASEADDR_MASK 0x3F
+#define GPMC_CS_ENABLE 0x1
+
+static void enable_gpmc_net_config(const u32 *gpmc_config, struct gpmc_cs *cs,
+ u32 base, u32 size)
+{
+ writel(0, &cs->config7);
+ sdelay(1000);
+ /* Delay for settling */
+ writel(gpmc_config[0], &cs->config1);
+ writel(gpmc_config[1], &cs->config2);
+ writel(gpmc_config[2], &cs->config3);
+ writel(gpmc_config[3], &cs->config4);
+ writel(gpmc_config[4], &cs->config5);
+ writel(gpmc_config[5], &cs->config6);
+
+ /*
+ * Enable the config. size is the CS size and goes in
+ * bits 11:8. We set bit 6 to enable this CS and the base
+ * address goes into bits 5:0.
+ */
+ writel((size << 8) | (GPMC_CS_ENABLE << 6) |
+ ((base >> 24) & GPMC_BASEADDR_MASK),
+ &cs->config7);
+
+ sdelay(2000);
+}
+
+/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1 0x2a001203
+#define NET_LAN9221_GPMC_CONFIG2 0x000a0a02
+#define NET_LAN9221_GPMC_CONFIG3 0x00020200
+#define NET_LAN9221_GPMC_CONFIG4 0x0a030a03
+#define NET_LAN9221_GPMC_CONFIG5 0x000a0a0a
+#define NET_LAN9221_GPMC_CONFIG6 0x8a070707
+#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
+
+/* GPMC definitions for LAN9221 chips on expansion boards */
+static const u32 gpmc_lan_config[] = {
+ NET_LAN9221_GPMC_CONFIG1,
+ NET_LAN9221_GPMC_CONFIG2,
+ NET_LAN9221_GPMC_CONFIG3,
+ NET_LAN9221_GPMC_CONFIG4,
+ NET_LAN9221_GPMC_CONFIG5,
+ NET_LAN9221_GPMC_CONFIG6,
+ /*CONFIG7- computed as params */
+};
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ enable_gpmc_net_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
+ GPMC_SIZE_16M);
+
+ /* Make GPIO SMSC_NRESET as output pin and send reset pulse */
+ if (!gpio_request(SMSC_NRESET, "")) {
+ gpio_direction_output(SMSC_NRESET, 0);
+ gpio_set_value(SMSC_NRESET, 1);
+ udelay(1);
+ gpio_set_value(SMSC_NRESET, 0);
+ udelay(1);
+ gpio_set_value(SMSC_NRESET, 1);
+ }
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+#ifdef CONFIG_USB_EHCI
+
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ int ret;
+ unsigned int utmi_clk;
+ u32 auxclk, altclksrc;
+
+ /* Now we can enable our port clocks */
+ utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
+ utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
+ setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
+
+ auxclk = readl(&scrm->auxclk3);
+ /* Select sys_clk */
+ auxclk &= ~AUXCLK_SRCSELECT_MASK;
+ auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
+ /* Set the divisor to 2 */
+ auxclk &= ~AUXCLK_CLKDIV_MASK;
+ auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
+ /* Request auxilary clock #3 */
+ auxclk |= AUXCLK_ENABLE_MASK;
+ writel(auxclk, &scrm->auxclk3);
+
+ altclksrc = readl(&scrm->altclksrc);
+
+ /* Activate alternate system clock supplier */
+ altclksrc &= ~ALTCLKSRC_MODE_MASK;
+ altclksrc |= ALTCLKSRC_MODE_ACTIVE;
+
+ /* enable clocks */
+ altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
+
+ writel(altclksrc, &scrm->altclksrc);
+
+ ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+int ehci_hcd_stop(int index)
+{
+ return omap_ehci_hcd_stop();
+}
+#endif
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+ return 0x20;
+}
diff --git a/board/gumstix/duovero/duovero_mux_data.h b/board/gumstix/duovero/duovero_mux_data.h
new file mode 100644
index 0000000..1be247b
--- /dev/null
+++ b/board/gumstix/duovero/duovero_mux_data.h
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2012
+ * Gumstix Incorporated, <www.gumstix.com>
+ * Maintainer: Ash Charles <ash@gumstix.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _DUOVERO_MUX_DATA_H_
+#define _DUOVERO_MUX_DATA_H_
+
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+ {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
+ {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+ {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+ {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+ {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+ {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+ {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
+ {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
+ {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
+ {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
+ {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
+ {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
+ {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
+ {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
+ {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
+ {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
+ {UART3_RX_IRRX, (PTU | IEN | M0)}, /* uart3_rx */
+ {UART3_TX_IRTX, (M0)} /* uart3_tx */
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+ {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+ {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+ {PAD1_SYS_32K, (IEN | M0)} /* sys_32k */
+};
+
+const struct pad_conf_entry core_padconf_array_non_essential[] = {
+ {GPMC_AD0, (PTU | IEN | M0)}, /* gpmc_ad0 */
+ {GPMC_AD1, (PTU | IEN | M0)}, /* gpmc_ad1 */
+ {GPMC_AD2, (PTU | IEN | M0)}, /* gpmc_ad2 */
+ {GPMC_AD3, (PTU | IEN | M0)}, /* gpmc_ad3 */
+ {GPMC_AD4, (PTU | IEN | M0)}, /* gpmc_ad4 */
+ {GPMC_AD5, (PTU | IEN | M0)}, /* gpmc_ad5 */
+ {GPMC_AD6, (PTU | IEN | M0)}, /* gpmc_ad6 */
+ {GPMC_AD7, (PTU | IEN | M0)}, /* gpmc_ad7 */
+ {GPMC_AD8, (PTU | IEN | M0)}, /* gpmc_ad8 */
+ {GPMC_AD9, (PTU | IEN | M0)}, /* gpmc_ad9 */
+ {GPMC_AD10, (PTU | IEN | M0)}, /* gpmc_ad10 */
+ {GPMC_AD11, (PTU | IEN | M0)}, /* gpmc_ad11 */
+ {GPMC_AD12, (PTU | IEN | M0)}, /* gpmc_ad12 */
+ {GPMC_AD13, (PTU | IEN | M0)}, /* gpmc_ad13 */
+ {GPMC_AD14, (PTU | IEN | M0)}, /* gpmc_ad14 */
+ {GPMC_AD15, (PTU | IEN | M0)}, /* gpmc_ad15 */
+ {GPMC_A16, (PTU | IEN | M3)}, /* gpio_40 */
+ {GPMC_A17, (PTU | IEN | M3)}, /* gpio_41 - hdmi_ls_oe */
+ {GPMC_A18, (PTU | IEN | M3)}, /* gpio_42 */
+ {GPMC_A19, (PTU | IEN | M3)}, /* gpio_43 - wifi_en */
+ {GPMC_A20, (PTU | IEN | M3)}, /* gpio_44 - eth_irq */
+ {GPMC_A21, (PTU | IEN | M3)}, /* gpio_45 - eth_nreset */
+ {GPMC_A22, (PTU | IEN | M3)}, /* gpio_46 - eth_pme */
+ {GPMC_A23, (PTU | IEN | M3)}, /* gpio_47 */
+ {GPMC_A24, (PTU | IEN | M3)}, /* gpio_48 - eth_mdix */
+ {GPMC_A25, (PTU | IEN | M3)}, /* gpio_49 - bt_wakeup */
+ {GPMC_NCS0, (PTU | M0)}, /* gpmc_ncs0 */
+ {GPMC_NCS1, (PTU | M0)}, /* gpmc_ncs1 */
+ {GPMC_NCS2, (PTU | M0)}, /* gpmc_ncs2 */
+ {GPMC_NCS3, (PTU | IEN | M3)}, /* gpio_53 */
+ {C2C_DATA12, (PTU | M0)}, /* gpmc_ncs4 */
+ {C2C_DATA13, (PTU | M0)}, /* gpmc_ncs5 - eth_cs */
+ {GPMC_NWP, (PTU | IEN | M0)}, /* gpmc_nwp */
+ {GPMC_CLK, (PTU | IEN | M0)}, /* gpmc_clk */
+ {GPMC_NADV_ALE, (PTU | M0)}, /* gpmc_nadv_ale */
+ {GPMC_NBE0_CLE, (PTU | M0)}, /* gpmc_nbe0_cle */
+ {GPMC_NBE1, (PTU | M0)}, /* gpmc_nbe1 */
+ {GPMC_WAIT0, (PTU | IEN | M0)}, /* gpmc_wait0 */
+ {GPMC_WAIT1, (PTU | IEN | M0)}, /* gpio_62 - usbh_nreset */
+ {GPMC_NOE, (PTU | M0)}, /* gpmc_noe */
+ {GPMC_NWE, (PTU | M0)}, /* gpmc_nwe */
+ {HDMI_HPD, (PTD | IEN | M3)}, /* gpio_63 - hdmi_hpd */
+ {HDMI_CEC, (PTU | IEN | M0)}, /* hdmi_cec */
+ {HDMI_DDC_SCL, (M0)}, /* hdmi_ddc_scl */
+ {HDMI_DDC_SDA, (IEN | M0)}, /* hdmi_ddc_sda */
+ {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */
+ {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */
+ {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */
+ {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */
+ {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */
+ {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */
+ {CSI21_DX3, (IEN | M0)}, /* csi21_dx3 */
+ {CSI21_DY3, (IEN | M0)}, /* csi21_dy3 */
+ {CSI21_DX4, (IEN | M0)}, /* csi21_dx4 */
+ {CSI21_DY4, (IEN | M0)}, /* csi21_dy4 */
+ {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */
+ {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */
+ {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */
+ {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */
+ {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
+ {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
+ {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
+ {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
+ {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
+ {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
+ {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
+ {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
+ {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
+ {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
+ {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
+ {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
+ {USBB1_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_96 - usbh_cpen */
+ {USBB1_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_97 - usbh_reset */
+ {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */
+ {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */
+ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */
+ {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */
+ {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */
+ {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */
+ {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */
+ {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */
+ {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */
+ {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */
+ {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */
+ {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */
+ {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */
+ {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */
+ {UART2_RTS, (M0)}, /* uart2_rts */
+ {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */
+ {UART2_TX, (M0)}, /* uart2_tx */
+ {HDQ_SIO, (M0)}, /* hdq-sio */
+ {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */
+ {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */
+ {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */
+ {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */
+ {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs1 */
+ {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_clk */
+ {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */
+ {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */
+ {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */
+ {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */
+ {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */
+ {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */
+ {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */
+ {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */
+ {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */
+ {UART4_RX, (IEN | PTU | M0)}, /* uart4_rx */
+ {UART4_TX, (M0)}, /* uart4_tx */
+ {USBB2_ULPITLL_CLK, (PTU | IEN | M3)}, /* gpio_157 - start_adc */
+ {USBB2_ULPITLL_STP, (PTU | IEN | M3)}, /* gpio_158 - spi_nirq */
+ {USBB2_ULPITLL_DIR, (PTU | IEN | M3)}, /* gpio_159 - bt_nreset */
+ {USBB2_ULPITLL_NXT, (PTU | IEN | M3)}, /* gpio_160 - audio_pwron*/
+ {USBB2_ULPITLL_DAT0, (PTU | IEN | M3)}, /* gpio_161 - bid_0 */
+ {USBB2_ULPITLL_DAT1, (PTU | IEN | M3)}, /* gpio_162 - bid_1 */
+ {USBB2_ULPITLL_DAT2, (PTU | IEN | M3)}, /* gpio_163 - bid_2 */
+ {USBB2_ULPITLL_DAT3, (PTU | IEN | M3)}, /* gpio_164 - bid_3 */
+ {USBB2_ULPITLL_DAT4, (PTU | IEN | M3)}, /* gpio_165 - bid_4 */
+ {USBB2_ULPITLL_DAT5, (PTU | IEN | M3)}, /* gpio_166 - ts_irq*/
+ {USBB2_ULPITLL_DAT6, (PTU | IEN | M3)}, /* gpio_167 - gps_pps */
+ {USBB2_ULPITLL_DAT7, (PTU | IEN | M3)}, /* gpio_168 */
+ {USBB2_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_169 */
+ {USBB2_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_170 */
+ {UNIPRO_TX1, (PTU | IEN | M3)}, /* gpio_173 */
+ {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
+ {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
+ {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
+ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */
+ {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */
+ {SYS_BOOT0, (M0)}, /* sys_boot0 */
+ {SYS_BOOT1, (M0)}, /* sys_boot1 */
+ {SYS_BOOT2, (M0)}, /* sys_boot2 */
+ {SYS_BOOT3, (M0)}, /* sys_boot3 */
+ {SYS_BOOT4, (M0)}, /* sys_boot4 */
+ {SYS_BOOT5, (M0)}, /* sys_boot5 */
+ {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */
+ {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */
+ {DPM_EMU16, (PTU | IEN | M3)}, /* gpio_27 */
+ {DPM_EMU17, (PTU | IEN | M3)}, /* gpio_28 */
+ {DPM_EMU18, (PTU | IEN | M3)}, /* gpio_29 */
+ {DPM_EMU19, (PTU | IEN | M3)}, /* gpio_30 */
+};
+
+const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
+ {PAD1_FREF_XTAL_IN, (M0)}, /* fref_xtal_in */
+ {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */
+ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */
+ {PAD0_FREF_CLK0_OUT, (M7)}, /* safe mode */
+ {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */
+ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
+ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
+ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
+ {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */
+ {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */
+ {PAD0_SYS_BOOT6, (M0)}, /* sys_boot6 */
+ {PAD1_SYS_BOOT7, (M0)}, /* sys_boot7 */
+};
+
+
+#endif /* _DUOVERO_MUX_DATA_H_ */
diff --git a/board/gumstix/pepper/Kconfig b/board/gumstix/pepper/Kconfig
new file mode 100644
index 0000000..6f94612
--- /dev/null
+++ b/board/gumstix/pepper/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PEPPER
+
+config SYS_BOARD
+ default "pepper"
+
+config SYS_VENDOR
+ default "gumstix"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "pepper"
+
+endif
diff --git a/board/gumstix/pepper/MAINTAINERS b/board/gumstix/pepper/MAINTAINERS
new file mode 100644
index 0000000..ae860ec
--- /dev/null
+++ b/board/gumstix/pepper/MAINTAINERS
@@ -0,0 +1,6 @@
+PEPPER BOARD
+M: Ash Charles <ash@gumstix.com>
+S: Maintained
+F: board/gumstix/pepper/
+F: include/configs/pepper.h
+F: configs/pepper_defconfig
diff --git a/board/gumstix/pepper/Makefile b/board/gumstix/pepper/Makefile
new file mode 100644
index 0000000..ecb1d61
--- /dev/null
+++ b/board/gumstix/pepper/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += mux.o
+endif
+
+obj-y += board.o
diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c
new file mode 100644
index 0000000..f644f81
--- /dev/null
+++ b/board/gumstix/pepper/board.c
@@ -0,0 +1,202 @@
+/*
+ * Board functions for Gumstix Pepper and AM335x-based boards
+ *
+ * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
+ * Based on board/ti/am335x/board.c from Texas Instruments, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <environment.h>
+#include <watchdog.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+static const struct ddr_data ddr2_data = {
+ .datardsratio0 = MT47H128M16RT25E_RD_DQS,
+ .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+ .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+ .cmd0csratio = MT47H128M16RT25E_RATIO,
+
+ .cmd1csratio = MT47H128M16RT25E_RATIO,
+
+ .cmd2csratio = MT47H128M16RT25E_RATIO,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+ .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+ .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+ .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+ .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+ .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr;
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+ config_ddr(266, &ioregs, &ddr2_data,
+ &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
+}
+#endif
+
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gpmc_init();
+
+ return 0;
+}
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ .phy_if = PHY_INTERFACE_MODE_RGMII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+ const char *devname;
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+
+ /*
+ *
+ * CPSW RGMII Internal Delay Mode is not supported in all PVT
+ * operating points. So we must set the TX clock delay feature
+ * in the KSZ9021 PHY. Since we only support a single ethernet
+ * device in U-Boot, we only do this for the current instance.
+ */
+ devname = miiphy_get_current_dev();
+ /* max rx/tx clock delay, min rx/tx control delay */
+ miiphy_write(devname, 0x0, 0x0b, 0x8104);
+ miiphy_write(devname, 0x0, 0xc, 0xa0a0);
+
+ /* min rx data delay */
+ miiphy_write(devname, 0x0, 0x0b, 0x8105);
+ miiphy_write(devname, 0x0, 0x0c, 0x0000);
+
+ /* min tx data delay */
+ miiphy_write(devname, 0x0, 0x0b, 0x8106);
+ miiphy_write(devname, 0x0, 0x0c, 0x0000);
+
+ return n;
+}
+#endif
diff --git a/board/gumstix/pepper/board.h b/board/gumstix/pepper/board.h
new file mode 100644
index 0000000..0512735
--- /dev/null
+++ b/board/gumstix/pepper/board.h
@@ -0,0 +1,19 @@
+/*
+ * Gumstix Pepper and AM335x-based boards information header
+ *
+ * Copyright (C) 2014, Gumstix, Inc. - http://www.gumstix.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We must be able to enable uart0, for initial output. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/board/gumstix/pepper/mux.c b/board/gumstix/pepper/mux.c
new file mode 100644
index 0000000..50b1266
--- /dev/null
+++ b/board/gumstix/pepper/mux.c
@@ -0,0 +1,78 @@
+/*
+ * Muxing for Gumstix Pepper and AM335x-based boards
+ *
+ * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ /* I2C_DATA */
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ /* I2C_SCLK */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */
+ {OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */
+ {OFFSET(xdma_event_intr1), MODE(3)},
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+/*
+ * Do board-specific muxes.
+ */
+void enable_board_pin_mux(void)
+{
+ /* I2C0 */
+ configure_module_pin_mux(i2c0_pin_mux);
+ /* SD Card */
+ configure_module_pin_mux(mmc0_pin_mux);
+ /* Ethernet pinmux. */
+ configure_module_pin_mux(rgmii1_pin_mux);
+}
diff --git a/board/h2200/Kconfig b/board/h2200/Kconfig
new file mode 100644
index 0000000..c0e0c1e
--- /dev/null
+++ b/board/h2200/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_H2200
+
+config SYS_BOARD
+ default "h2200"
+
+config SYS_CONFIG_NAME
+ default "h2200"
+
+endif
diff --git a/board/h2200/MAINTAINERS b/board/h2200/MAINTAINERS
new file mode 100644
index 0000000..b66ff51
--- /dev/null
+++ b/board/h2200/MAINTAINERS
@@ -0,0 +1,6 @@
+H2200 BOARD
+M: Lukasz Dalek <luk0104@gmail.com>
+S: Maintained
+F: board/h2200/
+F: include/configs/h2200.h
+F: configs/h2200_defconfig
diff --git a/board/h2200/Makefile b/board/h2200/Makefile
new file mode 100644
index 0000000..e516e91
--- /dev/null
+++ b/board/h2200/Makefile
@@ -0,0 +1,14 @@
+#
+# h2200 Support
+#
+# Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := h2200.o
+
+extra-y := h2200-header.bin
+
+$(obj)/h2200-header.bin: $(obj)/h2200-header.o
+ $(OBJCOPY) -O binary $< $@
diff --git a/board/h2200/h2200-header.S b/board/h2200/h2200-header.S
new file mode 100644
index 0000000..ac2e6b4
--- /dev/null
+++ b/board/h2200/h2200-header.S
@@ -0,0 +1,15 @@
+/*
+ * iPAQ h2200 header
+ *
+ * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+ .word 0xea0003fe /* b 0x1000 */
+
+ .org 0x40
+ .ascii "ECEC"
+
+ .org 0x1000 - 1
+ .byte 0x0
diff --git a/board/h2200/h2200.c b/board/h2200/h2200.c
new file mode 100644
index 0000000..66ae4b6
--- /dev/null
+++ b/board/h2200/h2200.c
@@ -0,0 +1,61 @@
+/*
+ * iPAQ h2200 board configuration
+ *
+ * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/pxa.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_eth_init(bd_t *bis)
+{
+ usb_eth_initialize(bis);
+ return 0;
+}
+
+void reset_cpu(ulong ignore)
+{
+ /* Enable VLIO interface on Hamcop */
+ writeb(0x1, 0x4000);
+
+ /* Reset board (cold reset) */
+ writeb(0xff, 0x4002);
+}
+
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ gd->bd->bi_arch_number = MACH_TYPE_H2200;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Let host see that device is disconnected */
+ udc_disconnect();
+ mdelay(500);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /*
+ * Everything except MSC0 was already set up by
+ * 1st stage bootloader.
+ *
+ * This setting enables access to companion chip.
+ */
+ clrsetbits_le32(MSC0, 0xffffffff, CONFIG_SYS_MSC0_VAL);
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ return 0;
+}
diff --git a/board/hale/tt01/Kconfig b/board/hale/tt01/Kconfig
new file mode 100644
index 0000000..af9828a
--- /dev/null
+++ b/board/hale/tt01/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TT01
+
+config SYS_BOARD
+ default "tt01"
+
+config SYS_VENDOR
+ default "hale"
+
+config SYS_SOC
+ default "mx31"
+
+config SYS_CONFIG_NAME
+ default "tt01"
+
+endif
diff --git a/board/hale/tt01/MAINTAINERS b/board/hale/tt01/MAINTAINERS
new file mode 100644
index 0000000..2f582be
--- /dev/null
+++ b/board/hale/tt01/MAINTAINERS
@@ -0,0 +1,6 @@
+TT01 BOARD
+M: Helmut Raiger <helmut.raiger@hale.at>
+S: Maintained
+F: board/hale/tt01/
+F: include/configs/tt01.h
+F: configs/tt01_defconfig
diff --git a/board/hale/tt01/Makefile b/board/hale/tt01/Makefile
new file mode 100644
index 0000000..e06a040
--- /dev/null
+++ b/board/hale/tt01/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at>
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := tt01.o
+obj-y += lowlevel_init.o
diff --git a/board/hale/tt01/lowlevel_init.S b/board/hale/tt01/lowlevel_init.S
new file mode 100644
index 0000000..54132a1
--- /dev/null
+++ b/board/hale/tt01/lowlevel_init.S
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ * (C) Copyright 2011 Helmut Raiger <helmut.raiger@hale.at>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Also setup the Peripheral Port Remap register inside the core */
+ ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+ mov pc, lr
diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c
new file mode 100644
index 0000000..011aed0
--- /dev/null
+++ b/board/hale/tt01/tt01.c
@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <command.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc13783.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BOARD_STRING "Board: HALE TT-01"
+
+/* Clock configuration */
+#define CCM_CCMR_SETUP 0x074B0BF5
+
+static void board_setup_clocks(void)
+{
+ struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
+ volatile int wait = 0x10000;
+
+ writel(CCM_CCMR_SETUP, &ccm->ccmr);
+ while (wait--)
+ ;
+
+ writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr);
+ writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
+
+ /* Set up clock to 532MHz */
+ writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
+ PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
+ PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
+ PDR0_MCU_PODF(0), &ccm->pdr0);
+ writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12),
+ &ccm->mpctl);
+ writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1),
+ &ccm->spctl);
+}
+
+/* DRAM configuration */
+
+#define ESDMISC_MDDR_SETUP 0x00000004
+#define ESDMISC_MDDR_RESET_DL 0x0000000c
+/*
+ * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below:
+ * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
+ * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
+ * tRCD = 011, tRC = 010
+ * note: all but tWTR (1), tRC (111) are reset defaults,
+ * the same values work in the jtag configuration
+ *
+ * Bluetechnix setup has 0x75e73a (for 128MB) =
+ * 0b 0111 0101 1110 0111 0011 1010
+ * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
+ * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
+ * tRCD = 011, tRC = 010
+ */
+#define ESDCFG0_MDDR_SETUP 0x006ac73a
+#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
+#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
+ ESDCTL_DSIZ(2) | ESDCTL_BL(1))
+#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
+#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
+#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
+#define ESDCTL_RW ESDCTL_SETTINGS
+
+static void board_setup_sdram(void)
+{
+ u32 *pad;
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /*
+ * setup pad control for the controller pins
+ * no loopback, no pull, no keeper, no open drain,
+ * standard input, standard drive, slow slew rate
+ */
+ for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
+ pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
+ *pad = 0;
+
+ /* set up MX31 DDR Memory Controller */
+ writel(ESDMISC_MDDR_SETUP, &esdc->misc);
+ writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
+
+ /* perform DDR init sequence for CSD0 */
+ writel(ESDCTL_PRECHARGE, &esdc->ctl0);
+ writel(0x12344321, CSD0_BASE+0x0f00);
+ writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
+ writel(0x12344321, CSD0_BASE);
+ writel(0x12344321, CSD0_BASE);
+ writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
+ writeb(0xda, CSD0_BASE+0x33);
+ writeb(0xff, CSD0_BASE+0x1000000);
+ writel(ESDCTL_RW, &esdc->ctl0);
+ writel(0xDEADBEEF, CSD0_BASE);
+ writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);
+}
+
+static void tt01_spi3_hw_init(void)
+{
+ /* CSPI3 */
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC));
+ /* CSPI3, SS0 = Atlas */
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1));
+
+ /* start CSPI3 clock (3 = always on except if PLL off) */
+ setbits_le32(CCM_CGR0, 3 << 16);
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /* CS4: FPGA incl. network controller */
+ struct mxc_weimcs cs4 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
+ };
+
+ /* this seems essential, won't start without, but why? */
+ writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);
+
+ board_setup_clocks();
+ board_setup_sdram();
+ mxc_setup_weimcs(4, &cs4);
+
+ /* Setup UART2 and SPI3 pins */
+ mx31_uart2_hw_init();
+ tt01_spi3_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+ return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+ hw_watchdog_init();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts(BOARD_STRING "\n");
+ return 0;
+}
+
+#ifdef CONFIG_MXC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ u32 val;
+ struct pmic *p;
+ int ret;
+
+ /*
+ * this is the first driver to use the pmic, so call
+ * pmic_init() here. board_late_init() is too late for
+ * the MMC driver.
+ */
+
+ ret = pmic_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ /* configure pins for SDHC1 only */
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CLK, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CMD, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA0, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA1, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA2, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA3, MUX_CTL_FUNC));
+
+ /* turn on power V_MMC1 */
+ if (pmic_reg_read(p, REG_MODE_1, &val) < 0)
+ pmic_reg_write(p, REG_MODE_1, val | VMMC1EN);
+
+ return mxc_mmc_init(bis);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+void video_get_info_str(int line_number, char *info)
+{
+ u32 srev = get_cpu_rev();
+
+ switch (line_number) {
+ case 2:
+ sprintf(info, " CPU : Freescale i.MX31 rev %d.%d%s at %d MHz",
+ (srev & 0xF0) >> 4, (srev & 0x0F),
+ ((srev & 0x8000) ? " unknown" : ""),
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ break;
+ case 3:
+ strcpy(info, " " BOARD_STRING);
+ break;
+ default:
+ info[0] = 0;
+ }
+}
+#endif
diff --git a/board/hardkernel/odroidc2/Kconfig b/board/hardkernel/odroidc2/Kconfig
new file mode 100644
index 0000000..d8fb462
--- /dev/null
+++ b/board/hardkernel/odroidc2/Kconfig
@@ -0,0 +1,22 @@
+if TARGET_MESON_GX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "odroidc2"
+
+config SYS_VENDOR
+ string
+ default "hardkernel"
+
+config SYS_SOC
+ string
+ default "gxb"
+
+config SYS_CONFIG_NAME
+ default "odroidc2"
+
+endif
diff --git a/board/hardkernel/odroidc2/Makefile b/board/hardkernel/odroidc2/Makefile
new file mode 100644
index 0000000..baab45d
--- /dev/null
+++ b/board/hardkernel/odroidc2/Makefile
@@ -0,0 +1,3 @@
+obj-y += $(BOARD).o $(BOARD)-eth.o
+obj-$(CONFIG_USB_GADGET) += $(BOARD)-otg.o
+obj-$(CONFIG_CMD_FASTBOOT) += $(BOARD)-fastboot.o $(BOARD)-recovery.o
diff --git a/board/hardkernel/odroidc2/aml-user-key.sig b/board/hardkernel/odroidc2/aml-user-key.sig
new file mode 100644
index 0000000..6b51b19
--- /dev/null
+++ b/board/hardkernel/odroidc2/aml-user-key.sig
Binary files differ
diff --git a/board/hardkernel/odroidc2/firmware/board_init.c b/board/hardkernel/odroidc2/firmware/board_init.c
new file mode 100644
index 0000000..46838d8
--- /dev/null
+++ b/board/hardkernel/odroidc2/firmware/board_init.c
@@ -0,0 +1,28 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/board_init.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "power.c"
+
+/* bl2 customer code */
+void board_init(void)
+{
+ power_init(0);
+}
\ No newline at end of file
diff --git a/board/hardkernel/odroidc2/firmware/power.c b/board/hardkernel/odroidc2/firmware/power.c
new file mode 100644
index 0000000..f3cc7ae
--- /dev/null
+++ b/board/hardkernel/odroidc2/firmware/power.c
@@ -0,0 +1,183 @@
+
+/*
+ * board/amlogic/gxb_p200_v1/firmware/power.c
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include "config.h"
+#include <serial.h>
+//#include <stdio.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static int pwm_voltage_table[][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+void pwm_init(int id)
+{
+ unsigned int reg;
+
+ /*
+ * TODO: support more pwm controllers, right now only support
+ * PWM_B, PWM_D
+ */
+
+ switch (id) {
+ case pwm_b:
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 22);
+ reg |= (1 << 21); // enable PWM_B
+ P_PIN_MUX_REG3 = reg;
+ break;
+
+ case pwm_d:
+ reg = P_PWM_MISC_REG_CD;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_CD = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_D = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 23);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg |= (1 << 20); // enable PWM_D
+ P_PIN_MUX_REG3 = reg;
+ break;
+ default:
+ break;
+ }
+
+ _udelay_(200);
+}
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+void power_init(int mode)
+{
+ pwm_init(pwm_b);
+ pwm_init(pwm_d);
+ serial_puts("set vcck to ");
+ serial_put_dec(CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_b, CONFIG_VCCK_INIT_VOLTAGE);
+ serial_puts("set vddee to ");
+ serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
+ serial_puts(" mv\n");
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_INIT_VOLTAGE);
+}
diff --git a/board/hardkernel/odroidc2/firmware/scp_task/dvfs_board.c b/board/hardkernel/odroidc2/firmware/scp_task/dvfs_board.c
new file mode 100644
index 0000000..64e987c
--- /dev/null
+++ b/board/hardkernel/odroidc2/firmware/scp_task/dvfs_board.c
@@ -0,0 +1,157 @@
+
+int pwm_voltage_table[31][2] = {
+ { 0x1c0000, 860},
+ { 0x1b0001, 870},
+ { 0x1a0002, 880},
+ { 0x190003, 890},
+ { 0x180004, 900},
+ { 0x170005, 910},
+ { 0x160006, 920},
+ { 0x150007, 930},
+ { 0x140008, 940},
+ { 0x130009, 950},
+ { 0x12000a, 960},
+ { 0x11000b, 970},
+ { 0x10000c, 980},
+ { 0x0f000d, 990},
+ { 0x0e000e, 1000},
+ { 0x0d000f, 1010},
+ { 0x0c0010, 1020},
+ { 0x0b0011, 1030},
+ { 0x0a0012, 1040},
+ { 0x090013, 1050},
+ { 0x080014, 1060},
+ { 0x070015, 1070},
+ { 0x060016, 1080},
+ { 0x050017, 1090},
+ { 0x040018, 1100},
+ { 0x030019, 1110},
+ { 0x02001a, 1120},
+ { 0x01001b, 1130},
+ { 0x00001c, 1140}
+};
+
+struct scpi_opp_entry cpu_dvfs_tbl[] = {
+ DVFS( 100000000, 860),
+ DVFS( 250000000, 860),
+ DVFS( 500000000, 860),
+ DVFS( 667000000, 900),
+ DVFS(1000000000, 940),
+ DVFS(1200000000, 980),
+ DVFS(1296000000, 1000),
+ DVFS(1416000000, 1020),
+ DVFS(1536000000, 1050),
+ DVFS(1752000000, 1050),
+ DVFS(2016000000, 1050)
+};
+
+
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+
+void pwm_init(int id)
+{
+ /*
+ * TODO: support more pwm controllers, right now only support PWM_B
+ */
+ unsigned int reg;
+
+ reg = P_PWM_MISC_REG_AB;
+ reg &= ~(0x7f << 16);
+ reg |= ((1 << 23) | (1 << 1));
+ P_PWM_MISC_REG_AB = reg;
+ /*
+ * default set to max voltage
+ */
+ P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
+
+ reg = P_PIN_MUX_REG7;
+ reg &= ~(1 << 22);
+ P_PIN_MUX_REG7 = reg;
+
+ reg = P_PIN_MUX_REG3;
+ reg &= ~(1 << 22);
+ reg |= (1 << 21); // enable PWM_B
+ P_PIN_MUX_REG3 = reg;
+
+ _udelay(200);
+}
+
+int dvfs_get_voltage(void)
+{
+ int i = 0;
+ unsigned int reg_val;
+
+ reg_val = P_PWM_PWM_B;
+ for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
+ if (pwm_voltage_table[i][0] == reg_val) {
+ return i;
+ }
+ }
+ if (i >= ARRAY_SIZE(pwm_voltage_table)) {
+ return -1;
+ }
+ return -1;
+}
+
+void set_dvfs(unsigned int domain, unsigned int index)
+{
+ int cur, to;
+ static int init_flag = 0;
+
+ if (!init_flag) {
+ pwm_init(pwm_b);
+ init_flag = 1;
+ }
+ cur = dvfs_get_voltage();
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ _udelay(200);
+ return ;
+ }
+ while (cur != to) {
+ /*
+ * if target step is far away from current step, don't change
+ * voltage by one-step-done. You should change voltage step by
+ * step to make sure voltage output is stable
+ */
+ if (cur < to) {
+ if (cur < to - 3) {
+ cur += 3;
+ } else {
+ cur = to;
+ }
+ } else {
+ if (cur > to + 3) {
+ cur -= 3;
+ } else {
+ cur = to;
+ }
+ }
+ P_PWM_PWM_B = pwm_voltage_table[cur][0];
+ _udelay(100);
+ }
+ _udelay(200);
+}
+
diff --git a/board/hardkernel/odroidc2/firmware/scp_task/pwr_ctrl.c b/board/hardkernel/odroidc2/firmware/scp_task/pwr_ctrl.c
new file mode 100644
index 0000000..1ced3dd
--- /dev/null
+++ b/board/hardkernel/odroidc2/firmware/scp_task/pwr_ctrl.c
@@ -0,0 +1,307 @@
+/*p200/201 GPIOAO_2 powr on :0, power_off :1*/
+
+#define __SUSPEND_FIRMWARE__
+#include <config.h>
+#undef __SUSPEND_FIRMWARE__
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#ifdef CONFIG_CEC_WAKEUP
+#include <cec_tx_reg.h>
+#endif
+
+#include <gpio-gxbb.h>
+
+extern int pwm_voltage_table[31][2];
+
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2196 << 2))))
+#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2195 << 2))))
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+
+enum pwm_id {
+ pwm_a = 0,
+ pwm_b,
+ pwm_c,
+ pwm_d,
+ pwm_e,
+ pwm_f,
+};
+
+void pwm_set_voltage(unsigned int id, unsigned int voltage)
+{
+ int to;
+
+ uart_puts("set vddee to 0x");
+ uart_put_hex(voltage, 16);
+ uart_puts("mv\n");
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
+ if (pwm_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ if (to >= ARRAY_SIZE(pwm_voltage_table)) {
+ to = ARRAY_SIZE(pwm_voltage_table) - 1;
+ }
+ switch (id) {
+ case pwm_b:
+ P_PWM_PWM_B = pwm_voltage_table[to][0];
+ break;
+
+ case pwm_d:
+ P_PWM_PWM_D = pwm_voltage_table[to][0];
+ break;
+ default:
+ break;
+ }
+ _udelay(200);
+}
+
+static void power_off_3v3(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<18, 1<<18);
+}
+static void power_on_3v3(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<2, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<18, 0);
+}
+
+/*p200/201 GPIOAO_4 powr on :1, power_off :0*/
+static void power_off_vcck(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<20, 0);
+}
+static void power_on_vcck(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<4, 0);
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<20, 1<<20);
+}
+
+static void power_off_at_clk81(void)
+{
+ power_off_3v3();
+ power_off_vcck();
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_SLEEP_VOLTAGE); // reduce power
+}
+static void power_on_at_clk81(void)
+{
+ pwm_set_voltage(pwm_d, CONFIG_VDDEE_INIT_VOLTAGE);
+ power_on_vcck();
+ power_on_3v3();
+}
+
+static void power_off_at_24M(void)
+{
+ //LED gpioao_13
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<29, 0);
+}
+
+static void power_on_at_24M(void)
+{
+ aml_update_bits(AO_GPIO_O_EN_N, 1<<29, 1<<29);
+}
+
+static void power_off_at_32k(void)
+{
+}
+
+static void power_on_at_32k(void)
+{
+}
+
+void get_wakeup_source(void *response, unsigned int suspend_from)
+{
+ struct wakeup_info *p = (struct wakeup_info *)response;
+ unsigned val;
+ struct wakeup_gpio_info *gpio;
+ unsigned i = 0;
+
+ p->status = RESPONSE_OK;
+ val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC);
+#ifdef CONFIG_BT_WAKEUP
+ val |= BT_WAKEUP_SRC;
+#endif
+
+#ifdef CONFIG_CEC_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= CEC_WAKEUP_SRC;
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ if (suspend_from != SYS_POWEROFF)
+ val |= WIFI_WAKEUP_SRC;
+#endif
+
+ p->sources = val;
+
+ /* Power Key: AO_GPIO[3]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
+ gpio->gpio_in_idx = GPIOAO_3;
+ gpio->gpio_in_ao = 1;
+ gpio->gpio_out_idx = -1;
+ gpio->gpio_out_ao = -1;
+ gpio->irq = IRQ_AO_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+ /* BT Wakeup: IN: GPIOX[21], OUT: GPIOX[20]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = BT_WAKEUP;
+ gpio->gpio_in_idx = GPIOX_21;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = GPIOX_20;
+ gpio->gpio_out_ao = 0;
+ gpio->irq = IRQ_GPIO0_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+
+#ifdef CONFIG_WIFI_WAKEUP
+ if (suspend_from != SYS_POWEROFF) {
+ /*WIFI Wakeup: IN: GPIOX[7], OUT: GPIOX[6]*/
+ gpio = &(p->gpio_info[i]);
+ gpio->wakeup_id = WIFI_WAKEUP;
+ gpio->gpio_in_idx = GPIOX_7;
+ gpio->gpio_in_ao = 0;
+ gpio->gpio_out_idx = GPIOX_6;
+ gpio->gpio_out_ao = 0;
+ gpio->irq = IRQ_GPIO1_NUM;
+ gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
+ p->gpio_info_count = ++i;
+ }
+#endif
+}
+
+void wakeup_timer_setup(void)
+{
+ /* 1ms resolution*/
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value |= ((0x3<<0) | (0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+ writel(10, P_ISA_TIMERA);
+}
+void wakeup_timer_clear(void)
+{
+ unsigned value;
+ value = readl(P_ISA_TIMER_MUX);
+ value &= ~((0x1<<12) | (0x1<<16));
+ writel(value, P_ISA_TIMER_MUX);
+}
+
+static unsigned int detect_key(unsigned int suspend_from)
+{
+ int exit_reason = 0;
+ unsigned int time_out = readl(AO_DEBUG_REG2);
+ unsigned time_out_ms = time_out*100;
+ unsigned *irq = (unsigned *)SECURE_TASK_SHARE_IRQ;
+ /* unsigned *wakeup_en = (unsigned *)SECURE_TASK_RESPONSE_WAKEUP_EN; */
+
+ /* setup wakeup resources*/
+ /*auto suspend: timerA 10ms resolution*/
+ if (time_out_ms != 0)
+ wakeup_timer_setup();
+
+ init_remote();
+#ifdef CONFIG_CEC_WAKEUP
+ if (hdmi_cec_func_config & 0x1) {
+ remote_cec_hw_reset();
+ cec_node_init();
+ }
+#endif
+
+ /* *wakeup_en = 1;*/
+ do {
+ switch (*irq) {
+#ifdef CONFIG_CEC_WAKEUP
+ case IRQ_AO_CEC_NUM:
+ if (suspend_from == SYS_POWEROFF)
+ break;
+ if (cec_msg.log_addr) {
+ if (hdmi_cec_func_config & 0x1) {
+ cec_handler();
+ if (cec_msg.cec_power == 0x1) {
+ /*cec power key*/
+ exit_reason = CEC_WAKEUP;
+ break;
+ }
+ }
+ } else if (hdmi_cec_func_config & 0x1)
+ cec_node_init();
+ break;
+#endif
+ case IRQ_TIMERA_NUM:
+ if (time_out_ms != 0)
+ time_out_ms--;
+ if (time_out_ms == 0) {
+ wakeup_timer_clear();
+ exit_reason = AUTO_WAKEUP;
+ }
+ break;
+
+ case IRQ_AO_IR_DEC_NUM:
+ if (remote_detect_key())
+ exit_reason = REMOTE_WAKEUP;
+ break;
+
+ case IRQ_AO_GPIO0_NUM:
+ if ((readl(AO_GPIO_I) & (1<<3)) == 0)
+ exit_reason = POWER_KEY_WAKEUP;
+ break;
+
+#ifdef CONFIG_BT_WAKEUP
+ case IRQ_GPIO0_NUM:
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ &(0x01 << 20)) &&
+ (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 20)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 21)))
+ exit_reason = BT_WAKEUP;
+ break;
+#endif
+#ifdef CONFIG_WIFI_WAKEUP
+ case IRQ_GPIO1_NUM:
+ if (suspend_from) {
+ if (!(readl(PREG_PAD_GPIO4_EN_N)
+ & (0x01 << 6)) &&
+ (readl(PREG_PAD_GPIO4_O)
+ & (0x01 << 6)) &&
+ !(readl(PREG_PAD_GPIO4_I)
+ & (0x01 << 7)))
+ exit_reason = WIFI_WAKEUP;
+ }
+ break;
+#endif
+ default:
+ break;
+ }
+ *irq = 0xffffffff;
+ if (exit_reason)
+ break;
+ else
+ asm volatile("wfi");
+ } while (1);
+
+ return exit_reason;
+}
+
+static void pwr_op_init(struct pwr_op *pwr_op)
+{
+ pwr_op->power_off_at_clk81 = power_off_at_clk81;
+ pwr_op->power_on_at_clk81 = power_on_at_clk81;
+ pwr_op->power_off_at_24M = power_off_at_24M;
+ pwr_op->power_on_at_24M = power_on_at_24M;
+ pwr_op->power_off_at_32k = power_off_at_32k;
+ pwr_op->power_on_at_32k = power_on_at_32k;
+
+ pwr_op->detect_key = detect_key;
+ pwr_op->get_wakeup_source = get_wakeup_source;
+}
diff --git a/board/hardkernel/odroidc2/firmware/timing.c b/board/hardkernel/odroidc2/firmware/timing.c
new file mode 100644
index 0000000..46104f9
--- /dev/null
+++ b/board/hardkernel/odroidc2/firmware/timing.c
@@ -0,0 +1,383 @@
+
+/*
+ *
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+*/
+
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* DDR freq range */
+#define CONFIG_DDR_CLK_LOW 375
+#define CONFIG_DDR_CLK_HIGH 1500
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_DDR_CLK < CONFIG_DDR_CLK_LOW) || (CONFIG_DDR_CLK > CONFIG_DDR_CLK_HIGH)
+ #error "Over DDR PLL range! Please check CONFIG_DDR_CLK in board header file! \n"
+#endif
+
+/* CPU freq range */
+#define CONFIG_CPU_CLK_LOW 600
+#define CONFIG_CPU_CLK_HIGH 2000
+/* DON'T OVER THESE RANGE */
+#if (CONFIG_CPU_CLK < CONFIG_CPU_CLK_LOW) || (CONFIG_CPU_CLK > CONFIG_CPU_CLK_HIGH)
+ #error "Over CPU PLL range! Please check CONFIG_CPU_CLK in board header file! \n"
+#endif
+
+#define DDR3_DRV_40OHM 0
+#define DDR3_DRV_34OHM 1
+#define DDR3_ODT_0OHM 0
+#define DDR3_ODT_60OHM 1
+#define DDR3_ODT_120OHM 2
+#define DDR3_ODT_40OHM 3
+#define DDR3_ODT_20OHM 4
+#define DDR3_ODT_30OHM 5
+
+#define CFG_DDR3_DRV DDR3_DRV_40OHM
+#define CFG_DDR3_ODT DDR3_ODT_120OHM
+
+/*
+ * these parameters are corresponding to the pcb layout,
+ * please don't enable this function unless these signals
+ * has been measured by oscilloscope.
+ */
+#ifdef CONFIG_DDR_CMD_BDL_TUNE
+#define DDR_AC_LCDLR 0
+#define DDR_CK0_BDL 18
+#define DDR_RAS_BDL 18
+#define DDR_CAS_BDL 24
+#define DDR_WE_BDL 21
+#define DDR_BA0_BDL 16
+#define DDR_BA1_BDL 2
+#define DDR_BA2_BDL 13
+#define DDR_ACPDD_BDL 27
+#define DDR_CS0_BDL 27
+#define DDR_CS1_BDL 27
+#define DDR_ODT0_BDL 27
+#define DDR_ODT1_BDL 27
+#define DDR_CKE0_BDL 27
+#define DDR_CKE1_BDL 27
+#define DDR_A0_BDL 14
+#define DDR_A1_BDL 9
+#define DDR_A2_BDL 5
+#define DDR_A3_BDL 18
+#define DDR_A4_BDL 4
+#define DDR_A5_BDL 16
+#define DDR_A6_BDL 1
+#define DDR_A7_BDL 10
+#define DDR_A8_BDL 4
+#define DDR_A9_BDL 7
+#define DDR_A10_BDL 10
+#define DDR_A11_BDL 9
+#define DDR_A12_BDL 6
+#define DDR_A13_BDL 16
+#define DDR_A14_BDL 8
+#define DDR_A15_BDL 27
+#endif
+
+/* CAUTION!! */
+/*
+ * For DDR3:
+ * 7-7-7: CONFIG_DDR_CLK range 375~ 533
+ * 9-9-9: CONFIG_DDR_CLK range 533~ 667
+ * 11-11-11: CONFIG_DDR_CLK range 667~ 800
+ * 12-12-12: CONFIG_DDR_CLK range 800~ 933
+ * 13-13-13: CONFIG_DDR_CLK range 933~1066
+ * 14-14-14: CONFIG_DDR_CLK range 1066~1200
+ */
+ddr_timing_t __ddr_timming[] = {
+ //ddr3_7_7_7
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_7,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (7),
+ .cfg_ddr_rcd = (7),
+ .cfg_ddr_ras = (20),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (27),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (27),
+ .cfg_ddr_rfc = (160),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (4),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (7),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (5),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (4),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (512),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_9_9_9
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_9,
+ .cfg_ddr_rtp = (6),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (9),
+ .cfg_ddr_rcd = (9),
+ .cfg_ddr_ras = (27),
+ .cfg_ddr_rrd = (6),
+ .cfg_ddr_rc = (33),
+ .cfg_ddr_mrd = (4),
+ .cfg_ddr_mod = (12),
+ .cfg_ddr_faw = (30),
+ .cfg_ddr_rfc = (196),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (6),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (6),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (9),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (7),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (20),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_11_11_11
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_11,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (11),
+ .cfg_ddr_rcd = (11),
+ .cfg_ddr_ras = (35),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (45),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (5),
+ .cfg_ddr_cke = (4),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (11),
+ .cfg_ddr_wr = (12),
+ .cfg_ddr_cwl = (8),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ //ddr3_13_13_13
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_13,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (13),
+ .cfg_ddr_rcd = (13),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (13),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (9),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ },
+ {
+ .identifier = CONFIG_DDR_TIMMING_DDR3_14,
+ .cfg_ddr_rtp = (7),
+ .cfg_ddr_wtr = (7),
+ .cfg_ddr_rp = (14),
+ .cfg_ddr_rcd = (14),
+ .cfg_ddr_ras = (37),
+ .cfg_ddr_rrd = (7),
+ .cfg_ddr_rc = (52),
+ .cfg_ddr_mrd = (6),
+ .cfg_ddr_mod = (4),
+ .cfg_ddr_faw = (33),
+ .cfg_ddr_rfc = (280),
+ .cfg_ddr_wlmrd = (40),
+ .cfg_ddr_wlo = (7),
+ .cfg_ddr_xs = (512),
+ .cfg_ddr_xp = (7),
+ .cfg_ddr_cke = (5),
+ .cfg_ddr_dllk = (512),
+ .cfg_ddr_rtodt = (0),
+ .cfg_ddr_rtw = (7),
+ .cfg_ddr_refi = (78),
+ .cfg_ddr_refi_mddr3 = (4),
+ .cfg_ddr_cl = (14),
+ .cfg_ddr_wr = (16),
+ .cfg_ddr_cwl = (10),
+ .cfg_ddr_al = (0),
+ .cfg_ddr_exsr = (512),
+ .cfg_ddr_dqs = (23),
+ .cfg_ddr_cksre = (15),
+ .cfg_ddr_cksrx = (15),
+ .cfg_ddr_zqcs = (64),
+ .cfg_ddr_zqcl = (136),
+ .cfg_ddr_xpdll = (23),
+ .cfg_ddr_zqcsi = (1000),
+ }
+};
+
+ddr_set_t __ddr_setting = {
+ /* common and function defines */
+ .ddr_channel_set = CONFIG_DDR_CHANNEL_SET,
+ .ddr_type = CONFIG_DDR_TYPE,
+ .ddr_clk = CONFIG_DDR_CLK,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .ddr_timing_ind = 0,
+ .ddr_size = CONFIG_DDR_SIZE,
+ .ddr_pll_ctrl = (0),
+ .ddr_dmc_ctrl = 0,
+ .ddr0_addrmap = {0},
+ .ddr1_addrmap = {0},
+ .ddr_2t_mode = 1,
+ .ddr_full_test = CONFIG_DDR_FULL_TEST,
+ .ddr_size_detect = CONFIG_DDR_SIZE_AUTO_DETECT,
+ .ddr_drv = CFG_DDR3_DRV,
+ .ddr_odt = CFG_DDR3_ODT,
+
+ /* pub defines */
+ .t_pub_ptr = {
+ [0] = ( 6 | (320 << 6) | (80 << 21)),
+ [1] = (120 | (1000 << 16)),
+ [2] = 0,
+ [3] = (20000 | (136 << 20)),
+ [4] = (1000 | (180 << 16)),
+ }, //PUB PTR0-3
+ .t_pub_odtcr = 0x00210000,
+ .t_pub_mr = {0},
+ .t_pub_dtpr = {0},
+ .t_pub_pgcr0 = 0x07d81e3f, //PUB PGCR0
+ .t_pub_pgcr1 = 0x0380c6a0, //PUB PGCR1
+ //.t_pub_pgcr2 = 0x00f05f97, //PUB PGCR2
+ .t_pub_pgcr2 = 0x01f12480, //PUB PGCR2
+ .t_pub_pgcr3 = 0xc0aafe60, //PUB PGCR3
+ .t_pub_dxccr = 0x00181884, //PUB DXCCR
+ .t_pub_dtcr = 0x43003087, //PUB DTCR
+ .t_pub_aciocr = {0}, //PUB ACIOCRx
+ .t_pub_dx0gcr = {0}, //PUB DX0GCRx
+ .t_pub_dx1gcr = {0}, //PUB DX1GCRx
+ .t_pub_dx2gcr = {0}, //PUB DX2GCRx
+ .t_pub_dx3gcr = {0}, //PUB DX3GCRx
+ .t_pub_dcr = 0XB, //PUB DCR
+ .t_pub_dtar = (0X0 | (0X0 <<12) | (0 << 28)),
+ .t_pub_dsgcr = 0x020645a,
+ //.t_pub_zq0pr = 0x7b, //PUB ZQ0PR
+ //.t_pub_zq1pr = 0x7b, //PUB ZQ1PR
+ //.t_pub_zq2pr = 0x7b, //PUB ZQ2PR
+ //.t_pub_zq3pr = 0x7b, //PUB ZQ3PR
+ .t_pub_zq0pr = 0x69, //PUB ZQ0PR
+ .t_pub_zq1pr = 0x69, //PUB ZQ1PR
+ .t_pub_zq2pr = 0x69, //PUB ZQ2PR
+ .t_pub_zq3pr = 0x69, //PUB ZQ3PR
+
+ /* pctl0 defines */
+ /* pctl1 use same define as pctl0 */
+ .t_pctl0_1us_pck = CONFIG_DDR_CLK / 2, //PCTL TOGCNT1U
+ .t_pctl0_100ns_pck = CONFIG_DDR_CLK / 20, //PCTL TOGCNT100N
+ .t_pctl0_init_us = 2, //PCTL TINIT
+ .t_pctl0_rsth_us = 2, //PCTL TRSTH
+ .t_pctl0_mcfg = 0XA2F21, //PCTL MCFG default 1T
+ //.t_pctl0_mcfg1 = 0X80000000, //PCTL MCFG1
+ .t_pctl0_mcfg1 = (1<<31)|(0x20<<16)|(0x0<<0)//[B31]hw_exit_idle_en
+ |( 0<<8), //[B10,B9,B8] tfaw_cfg_offset:
+ //tFAW= (4 + MCFG.tfaw_cfg)*tRRD - tfaw_cfg_offset, //PCTL MCFG1
+ .t_pctl0_scfg = 0xF01, //PCTL SCFG
+ .t_pctl0_sctl = 0x1, //PCTL SCTL
+ //.t_pctl0_ppcfg = (0xF0 << 1),
+ .t_pctl0_dfistcfg0 = 0x4,
+ .t_pctl0_dfistcfg1 = 0x1,
+ .t_pctl0_dfitctrldelay = 2,
+ .t_pctl0_dfitphywrdata = 1,
+ .t_pctl0_dfitphywrlta = 2,
+ .t_pctl0_dfitrddataen = 3,
+ .t_pctl0_dfitphyrdlat = 16,
+ .t_pctl0_dfitdramclkdis = 1,
+ .t_pctl0_dfitdramclken = 1,
+ .t_pctl0_dfitphyupdtype1 = 0x200,
+ .t_pctl0_dfitctrlupdmin = 16,
+ .t_pctl0_cmdtstaten = 1,
+ //.t_pctl0_dfiodtcfg = 8,
+ //.t_pctl0_dfiodtcfg1 = ( 0x0 | (0x6 << 16) ),
+ .t_pctl0_dfiodtcfg = (1<<3)|(1<<11),
+ .t_pctl0_dfiodtcfg1 = (0x0 | (0x6 << 16)),
+ .t_pctl0_dfilpcfg0 = ( 1 | (3 << 4) | (1 << 8) | (3 << 12) | (7 <<16) | (1 <<24) | ( 3 << 28)),
+
+ .t_pub_acbdlr0 = 0x10, //2015.09.21 add for CK0 delay fine tune
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CONFIG_CPU_CLK / 24 * 24,
+ .spi_ctrl = 0,
+ .vddee = CONFIG_VDDEE_INIT_VOLTAGE,
+ .vcck = CONFIG_VCCK_INIT_VOLTAGE,
+ .lCustomerID = CONFIG_AML_CUSTOMER_ID,
+};
diff --git a/board/hardkernel/odroidc2/odroidc2-eth.c b/board/hardkernel/odroidc2/odroidc2-eth.c
new file mode 100644
index 0000000..7f69cde
--- /dev/null
+++ b/board/hardkernel/odroidc2/odroidc2-eth.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2015 Hardkernel Co,. Ltd
+ * Dongjin Kim <tobetter@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/eth_setup.h>
+#include <asm/arch/secure_apb.h>
+
+#if defined(CONFIG_AML_ETHERNET)
+extern int aml_eth_init(bd_t *bis);
+
+struct eth_board_socket* eth_board_setup(char *name)
+{
+ struct eth_board_socket* new_board;
+
+ new_board = (struct eth_board_socket*)
+ malloc(sizeof(struct eth_board_socket));
+ if (NULL == new_board)
+ return NULL;
+
+ if (name != NULL) {
+ new_board->name = (char*)malloc(strlen(name));
+ strncpy(new_board->name, name, strlen(name));
+ } else {
+ new_board->name = CONFIG_SYS_BOARD;
+ }
+
+ new_board->eth_pinmux_setup = NULL ;
+ new_board->eth_clock_configure = NULL;
+ new_board->eth_hw_reset = NULL;
+
+ return new_board;
+}
+
+static void setup_net_chip(void)
+{
+ eth_aml_reg0_t reg;
+
+ /*
+ * Set up ethernet clk need calibrate to configure
+ */
+ setbits_le32(P_PERIPHS_PIN_MUX_6, 0x3fff);
+
+ reg.d32 = 0;
+ reg.b.phy_intf_sel = 1;
+ reg.b.data_endian = 0;
+ reg.b.desc_endian = 0;
+ reg.b.rx_clk_rmii_invert = 0;
+ reg.b.rgmii_tx_clk_src = 0;
+ reg.b.rgmii_tx_clk_phase = 1;
+ reg.b.rgmii_tx_clk_ratio = 4;
+ reg.b.phy_ref_clk_enable = 1;
+ reg.b.clk_rmii_i_invert = 0;
+ reg.b.clk_en = 1;
+ reg.b.adj_enable = 0;
+ reg.b.adj_setup = 0;
+ reg.b.adj_delay = 0;
+ reg.b.adj_skew = 0;
+ reg.b.cali_start = 0;
+ reg.b.cali_rise = 0;
+ reg.b.cali_sel = 0;
+ reg.b.rgmii_rx_reuse = 0;
+ reg.b.eth_urgent = 0;
+
+ /* RGMII Mode */
+ setbits_le32(P_PREG_ETH_REG0, reg.d32);
+
+ setbits_le32(HHI_GCLK_MPEG1, 1 << 3);
+
+ /*
+ * Power on memory
+ */
+ clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+
+ /*
+ * Hardware reset ethernet phy : GPIOZ_14
+ */
+ clrbits_le32(PREG_PAD_GPIO3_EN_N, 1 << 14);
+ clrbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+ udelay(100000);
+ setbits_le32(PREG_PAD_GPIO3_O, 1 << 14);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_net_chip();
+ udelay(1000);
+ aml_eth_init(bis);
+
+ return 0;
+}
+#endif
diff --git a/board/hardkernel/odroidc2/odroidc2-fastboot.c b/board/hardkernel/odroidc2/odroidc2-fastboot.c
new file mode 100644
index 0000000..b1b9b31
--- /dev/null
+++ b/board/hardkernel/odroidc2/odroidc2-fastboot.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2015 Hardkernel Co,. Ltd
+ * Dongjin Kim <tobetter@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <linux/string.h>
+#include <usb/fastboot.h>
+
+/* FIXME: Is block size always 512? */
+#define bytes_to_lba(x) ((x) / 512)
+#define gbytes_to_lba(x) ((x) * 1024 * 1024 * 2)
+
+#define SZ_RESERVED (48 * SZ_1K + 512) /* BL1 + MBR */
+#define SZ_BOOTLOADER (720 * SZ_1K)
+#define SZ_BOOTMESSAGE (4 * SZ_1K)
+
+static struct fbt_partition {
+ const char *name;
+ lbaint_t lba;
+} partitions[] = {
+ {
+ .name = "-reserved",
+ .lba = bytes_to_lba(SZ_RESERVED)
+ }, {
+ .name = "bootloader",
+ .lba = bytes_to_lba(SZ_BOOTLOADER
+ - (SZ_RESERVED + SZ_BOOTMESSAGE))
+ }, {
+ .name = "bcb", /* Bootloader control block */
+ .lba = bytes_to_lba(SZ_BOOTMESSAGE)
+ }, {
+ .name = "env", /* "environment" */
+ .lba = bytes_to_lba(CONFIG_ENV_SIZE)
+ }, {
+ .name = "dtb", /* Device Tree */
+ .lba = bytes_to_lba(SZ_64K)
+ }, {
+ .name = "boot", /* Boot image */
+ .lba = bytes_to_lba(16 * SZ_1M)
+ }, {
+ .name = "recovery", /* Recovery Image */
+ .lba = bytes_to_lba(12 * SZ_1M)
+ }, {
+ .name = "logo", /* Logo */
+ .lba = bytes_to_lba(2 * SZ_1M)
+ }
+};
+
+static struct dos_partition {
+ const char *name;
+ int part;
+ u8 type;
+ lbaint_t lba;
+} dos_partitions[] = {
+ {
+ .name = "cache",
+ .part = 2,
+ .type = 0x83,
+ .lba = bytes_to_lba(512 * SZ_1M),
+ }, {
+ .name = "system",
+ .part = 3,
+ .type = 0x83,
+ .lba = gbytes_to_lba(1),
+ }, {
+ .name = "userdata",
+ .part = 4,
+ .type = 0x83,
+ .lba = gbytes_to_lba(3),
+ }, {
+ .name = "vfat",
+ .part = 1,
+ .type = 0x0c,
+ .lba = -1,
+ },
+};
+
+static int n = 0;
+
+static int valid_partition_number(int part)
+{
+ return (1 <= part) && (part <= ARRAY_SIZE(dos_partitions));
+}
+
+/*
+ * Initiate dos partition index and return the first sector (lba)
+ */
+lbaint_t board_dos_partition_start(void)
+{
+ int n;
+ lbaint_t next = 0;
+
+ for (n = 0 ; n < ARRAY_SIZE(partitions); n++)
+ next += partitions[n].lba;
+
+ return next;
+}
+
+/*
+ * Get the partition detail, partition number and its type, as well as
+ * return the number of sectors to allocate for the partition.
+ */
+lbaint_t board_dos_partition_next(int *part, u8 *type)
+{
+ if (!valid_partition_number(n + 1))
+ return 0;
+
+ struct dos_partition *p = &dos_partitions[n++];
+
+ *part = p->part; /* partition number */
+ *type = p->type; /* partition type */
+
+ /* Use remained sectors for this partition */
+ if (p->lba == -1)
+ return -1;
+
+ return p->lba;
+}
+
+/*
+ * Return the partition name of given partiton number. Since DOS partition
+ * does not support name on its parition table, the partition names are
+ * predefined upon each partition number.
+ */
+char *board_dos_partition_name(int part, char* name)
+{
+ int i;
+
+ if (!valid_partition_number(part))
+ return NULL;
+
+ for (i = 0; i < ARRAY_SIZE(dos_partitions); i++) {
+ /* Partition number is same with given to seek */
+ if (dos_partitions[i].part == part) {
+ strcpy(name, dos_partitions[i].name);
+ return name;
+ }
+ }
+
+ return NULL;
+}
+
+/*
+ * Initiate the fastboot partition entries with internal system partitions and
+ * DOS partition table.
+ */
+int board_partition_init(void)
+{
+ struct mmc *mmc;
+ fastboot_ptentry ptn;
+ lbaint_t next = 0;
+ lbaint_t len;
+ int n = 0;
+
+ fastboot_flash_reset_ptn();
+
+ mmc = find_mmc_device(CONFIG_FASTBOOT_FLASH_MMC_DEV);
+
+ for (n = 0 ; mmc && n < ARRAY_SIZE(partitions); n++) {
+ len = partitions[n].lba;
+
+ /* Skip to add the partition if start with '-', but move forward
+ * to next position as much as its size
+ */
+ if (partitions[n].name[0] == '-') {
+ next += len;
+ continue;
+ }
+
+ /* 'env' partition contains U-boot's environment fields, it
+ * could be damaged by fastboot if its offset is invalid with
+ * defined by CONFIG_ENV_OFFSET.
+ */
+ if (!strcmp(partitions[n].name, "env") &&
+ (bytes_to_lba(CONFIG_ENV_OFFSET) != next)) {
+ printf("WARNING!!: Invalid offset of 'env' partition,"
+ " it must be " LBAFU " but " LBAFU "\n",
+ next, (lbaint_t)bytes_to_lba(CONFIG_ENV_OFFSET));
+ }
+
+ if (len == 0)
+ len = mmc->block_dev.lba - next;
+
+ strncpy((char*)&ptn.name, partitions[n].name, sizeof(ptn.name));
+
+ ptn.start = next;
+ ptn.length = len;
+
+ /* Add the partition to fastboot partition entry table */
+ fastboot_flash_add_ptn(&ptn);
+
+ next += len;
+ }
+
+ fastboot_load_dos_partition();
+
+ return 0;
+}
+
+int board_fastboot_pre_flash(block_dev_desc_t *dev_desc, lbaint_t start,
+ void *buffer)
+{
+ if (start == 0) {
+ /* MUST be trying to modify MBR, hence at least DOS partition
+ * table have to be kept. So buffer to flashing will be
+ * overwritten with exist partition table.
+ */
+ u8 mbr[512];
+
+ if (dev_desc->block_read(dev_desc->dev, start, 1, mbr) != 1) {
+ printf("fastboot: can't read MBR from device %d\n",
+ dev_desc->dev);
+ return -EIO;
+ }
+
+ memcpy(buffer + 0x1be, &mbr[0x1be], 512 - 0x1be);
+ }
+
+ return 0;
+}
diff --git a/board/hardkernel/odroidc2/odroidc2-otg.c b/board/hardkernel/odroidc2/odroidc2-otg.c
new file mode 100644
index 0000000..d8f1f3a
--- /dev/null
+++ b/board/hardkernel/odroidc2/odroidc2-otg.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2015 Hardkernel Co,. Ltd
+ * Dongjin Kim <tobetter@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/usb.h>
+
+#include <usb.h>
+#include <usb/s3c_udc.h>
+
+#define P_RESET1_REGISTER_USB 0xc1104408
+
+#define PREI_USB_PHY_A_REG_BASE 0xC0000000
+#define PREI_USB_PHY_REG_BASE PREI_USB_PHY_A_REG_BASE
+
+#define PORT_REG_OFFSET 0x0000 /* Port - A */
+#define DWC_REG_BASE (0xC9000000 + PORT_REG_OFFSET)
+
+#define DWC_REG_GSNPSID 0x040 /* Synopsys ID Register (Read Only) */
+
+#define OTG_PHY_CONFIG 0x0000
+#define OTG_PHY_CTRL 0x0004
+#define OTG_PHY_CTRL_POR (1 << 15)
+#define OTG_PHY_CTRL_FSEL(x) ((x) << 22)
+#define OTG_PHY_CTRL_CLKDET (1 << 8)
+#define OTG_PHY_ENDP_INTR 0x0008
+#define OTG_PHY_ADP_BC 0x000c
+#define OTG_PHY_DBG_UART 0x0010
+#define OTG_PHY_TEST 0x0014
+#define OTG_PHY_TUNE 0x0018
+
+extern struct amlogic_usb_config *amlogic_usb_config(int port);
+
+static int dwc_otg_start_clk(int on)
+{
+ if (on) {
+ u32 temp;
+ u32 snpsid;
+
+ writel((1 << 2), P_RESET1_REGISTER_USB);
+ udelay(500);
+
+ /* Power On Reset & select 24MHz as reference clock */
+ temp = readl(PREI_USB_PHY_REG_BASE + OTG_PHY_CTRL);
+ temp |= OTG_PHY_CTRL_FSEL(5) | OTG_PHY_CTRL_POR;
+ writel(temp, PREI_USB_PHY_REG_BASE + OTG_PHY_CTRL);
+
+ udelay(500); // 500us
+
+ temp &= ~OTG_PHY_CTRL_POR;
+ writel(temp, PREI_USB_PHY_REG_BASE + OTG_PHY_CTRL);
+
+ udelay(50000); // 50ms
+
+ /* USB OTG PHY does work? */
+ temp = readl(PREI_USB_PHY_REG_BASE + OTG_PHY_CTRL);
+ if (0 == (temp & OTG_PHY_CTRL_CLKDET)) {
+ printf("ERROR, usb phy clock is not detected!\n");
+ }
+
+ /* Check USB OTG ID, if it can work */
+ snpsid = readl(DWC_REG_BASE + DWC_REG_GSNPSID);
+ if (0x4f543000 != (snpsid & 0xfffff000)) {
+ printf("%s, Bad value for SNPSID: 0x%08x\n",
+ __func__, snpsid);
+ return -1;
+ }
+ } else {
+ /* FIXME: Add to disable USB OTG PHY
+ */
+ }
+
+ return 0;
+}
+
+struct s3c_plat_otg_data odroid_otg_data = {
+ .phy_control = dwc_otg_start_clk,
+ .regs_otg = DWC_REG_BASE,
+};
+
+void otg_phy_init(struct s3c_udc *dev)
+{
+ dev->pdata->phy_control(1);
+
+ /* USB PHY0 Enable */
+ printf("USB PHY0 Enabled\n");
+}
+
+void otg_phy_off(struct s3c_udc *dev)
+{
+ dev->pdata->phy_control(0);
+
+ /* USB PHY0 Disable */
+ printf("USB PHY0 Disabled\n");
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ amlogic_usb_config_t *usb_config;
+
+ if (init == USB_INIT_DEVICE) {
+ usb_config = amlogic_usb_start(BOARD_USB_MODE_SLAVE, 0);
+ if (usb_config == amlogic_usb_config(0))
+ return s3c_udc_probe(&odroid_otg_data);
+ } else {
+ /* FIXME: do we need to initiate USB host here? */
+ }
+
+ return -ENODEV;
+}
diff --git a/board/hardkernel/odroidc2/odroidc2-recovery.c b/board/hardkernel/odroidc2/odroidc2-recovery.c
new file mode 100644
index 0000000..e9bbcca
--- /dev/null
+++ b/board/hardkernel/odroidc2/odroidc2-recovery.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2015 Hardkernel Co,. Ltd
+ * Dongjin Kim <tobetter@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <usb/fastboot.h>
+
+/* Bootloader Message
+ *
+ * This structure describes the content of a block in flash
+ * that is used for recovery and the bootloader to talk to
+ * each other.
+ *
+ * The command field is updated by linux when it wants to
+ * reboot into recovery or to update radio or bootloader firmware.
+ * It is also updated by the bootloader when firmware update
+ * is complete (to boot into recovery for any final cleanup)
+ *
+ * The status field is written by the bootloader after the
+ * completion of an "update-radio" or "update-hboot" command.
+ *
+ * The recovery field is only written by linux and used
+ * for the system to send a message to recovery or the
+ * other way around.
+ */
+struct bootloader_message {
+ char command[32];
+ char status[32];
+ char recovery[1024];
+};
+
+static const char *bcb_name = "bcb";
+static const char *bcb_magic = "recovery";
+static struct bootloader_message bcb;
+
+int board_get_recovery_message(void)
+{
+ block_dev_desc_t *dev_desc;
+ fastboot_ptentry *ptn;
+ unsigned int offset;
+
+ dev_desc = mmc_get_dev(0);
+ if (NULL == dev_desc)
+ return ODROID_REBOOT_CMD_UNKNOWN;
+
+ ptn = fastboot_flash_find_ptn(bcb_name);
+ if (NULL == ptn)
+ return ODROID_REBOOT_CMD_UNKNOWN;
+
+ offset = ptn->start;
+
+ dev_desc->block_read(dev_desc->dev, offset,
+ (sizeof(struct bootloader_message)
+ + (dev_desc->blksz - 1)) / dev_desc->blksz, &bcb);
+
+ bcb.recovery[strlen(bcb_magic)] = 0;
+ if (0 == strncmp(bcb.recovery, bcb_magic, strlen(bcb_magic))) {
+ do_format();
+ printf("Default Android partition is created...\n");
+ return ODROID_REBOOT_CMD_RECOVERY;
+ }
+
+ return ODROID_REBOOT_CMD_UNKNOWN;
+}
diff --git a/board/hardkernel/odroidc2/odroidc2.c b/board/hardkernel/odroidc2/odroidc2.c
new file mode 100644
index 0000000..2d29fb6
--- /dev/null
+++ b/board/hardkernel/odroidc2/odroidc2.c
@@ -0,0 +1,522 @@
+/*
+ * Copyright (C) 2015 Hardkernel Co,. Ltd
+ * Dongjin Kim <tobetter@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/eth_setup.h>
+#include <asm/arch-gxb/gpio.h>
+#include <asm-generic/gpio.h>
+//#include <usb/fastboot.h>
+#include <asm/arch/efuse.h>
+
+#ifdef CONFIG_AML_VPU
+#include <vpu.h>
+#endif
+
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/hdmi.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int board_get_recovery_message(void);
+
+#define GPIO_SW_UMS 28 /* GPIOY_5 */
+#define GPIO_BLUELED 132
+#define GPIO_USB_PWREN 123
+#define GPIO_OTG_PWREN 124
+#define GPIO_TF3V3 35 /* GPIOY_12 */
+#define GPIO_TF1V8 122 /* GPIOAO_3 */
+#define GPIO_HUB_RST 123 /* GPIOAO_4 */
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ //UART in "Always On Module"
+ //GPIOAO_0==tx,GPIOAO_1==rx
+ //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void secondary_boot_func(void)
+{
+ /*
+ * TODO: should be written in ASM if necessary
+ */
+}
+
+/*
+ * Discover the boot device within MicroSD or eMMC
+ * and return 1 for eMMC, otherwise 0.
+ */
+#define BOOT_DEVICE_RESERVED 0
+#define BOOT_DEVICE_EMMC 1
+#define BOOT_DEVICE_NAND 2
+#define BOOT_DEVICE_SPI 3
+#define BOOT_DEVICE_SD 4
+#define BOOT_DEVICE_USB 5
+
+int get_boot_device(void)
+{
+ return readl(AO_SEC_GP_CFG0) & 0xf;
+}
+
+/*
+ * Discover the boot reason:
+ * 1. check if the board is started with Android Self-Installation.
+ * 2. if rebooted by 'reboot' command in previous kernel boot.
+ * 3. Otherwise returns normal boot response by power cycle.
+ */
+int board_reboot_reason(void)
+{
+ static int __reboot_reason = ODROID_REBOOT_CMD_UNKNOWN;
+
+ if (ODROID_REBOOT_CMD_UNKNOWN == __reboot_reason) {
+ __reboot_reason = board_get_recovery_message();
+ if (ODROID_REBOOT_CMD_UNKNOWN == __reboot_reason)
+ __reboot_reason = (readl(AO_SEC_SD_CFG15) >> 12) & 0xf;
+ }
+
+ return __reboot_reason;
+}
+
+int board_print_info(void)
+{
+ int i;
+ int offset, length;
+ char buf[EFUSE_BYTES];
+
+ printf("-------------------------------------------------\n");
+ printf("* Welcome to Hardkernel's ODROID-C2\n");
+ printf("-------------------------------------------------\n");
+
+ /* CPU */
+ printf("CPU : AMLogic S905\n");
+
+ /* S/N */
+ offset = 20;
+ length = 16;
+ memset(buf, 0, EFUSE_BYTES);
+ efuse_read_usr(buf, length, (loff_t *)&offset);
+ buf[length] = '\0';
+ printf("S/N : ");
+ printf("%s\n", buf);
+
+ /* MAC */
+ offset = 52;
+ length = 6;
+ memset(buf, 0, EFUSE_BYTES);
+ efuse_read_usr(buf, length, (loff_t *)&offset);
+ buf[length] = '\0';
+ printf("MAC : ");
+ for (i=0;i<(length-1);i++)
+ printf("%02x:", buf[i]);
+ printf("%02x\n", buf[i]);
+
+ /* BID */
+ offset = 70;
+ length = 48;
+ memset(buf, 0, EFUSE_BYTES);
+ efuse_read_usr(buf, length, (loff_t *)&offset);
+ buf[0xA] = '\0';
+ printf("BID : ");
+ printf("%s\n", buf);
+
+ printf("-------------------------------------------------\n");
+
+ return 0;
+}
+
+#if CONFIG_AML_SD_EMMC
+#include <mmc.h>
+#include <asm/arch/sd_emmc.h>
+
+static int sd_emmc_init(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ //todo add card detect
+ //setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ break;
+ case SDIO_PORT_C:
+ //enable pull up
+ //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
+ break;
+ default:
+ break;
+ }
+
+ return cpu_sd_emmc_init(port);
+}
+
+extern unsigned sd_debug_board_1bit_flag;
+static int sd_emmc_detect(unsigned port)
+{
+ int ret;
+ switch (port) {
+
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ setbits_le32(P_PREG_PAD_GPIO5_EN_N,1<<29);//CARD_6
+ ret=readl(P_PREG_PAD_GPIO5_I)&(1<<29)?0:1;
+ printf("ret = %d .",ret);
+ if ((readl(P_PERIPHS_PIN_MUX_8)&(3<<9))) { //if uart pinmux set, debug board in
+ if (!(readl(P_PREG_PAD_GPIO2_I)&(1<<24))) {
+ printf("sdio debug board detected, sd card with 1bit mode\n");
+ sd_debug_board_1bit_flag = 1;
+ }
+ else{
+ printf("sdio debug board detected, no sd card in\n");
+ sd_debug_board_1bit_flag = 0;
+ return 1;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void sd_emmc_pwr_prepare(unsigned port)
+{
+ cpu_sd_emmc_pwr_prepare(port);
+}
+
+static void sd_emmc_pwr_on(unsigned port)
+{
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ // clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+ // clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ /// @todo NOT FINISH
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+static void sd_emmc_pwr_off(unsigned port)
+{
+ /// @todo NOT FINISH
+ switch (port)
+ {
+ case SDIO_PORT_A:
+ break;
+ case SDIO_PORT_B:
+ // setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
+ // clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
+ break;
+ case SDIO_PORT_C:
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+static void board_mmc_register(unsigned port)
+{
+ struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
+
+ if (aml_priv == NULL)
+ return;
+
+ aml_priv->sd_emmc_init=sd_emmc_init;
+ aml_priv->sd_emmc_detect=sd_emmc_detect;
+ aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
+ aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
+ aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
+ aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
+
+ if (NULL == aml_priv->desc_buf)
+ printf(" desc_buf Dma alloc Fail!\n");
+ else
+ printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
+
+ sd_emmc_register(aml_priv);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_VLSI_EMULATOR
+ //board_mmc_register(SDIO_PORT_A);
+#else
+ //board_mmc_register(SDIO_PORT_B);
+#endif
+ switch (get_boot_device())
+ {
+ case BOOT_DEVICE_EMMC:
+ board_mmc_register(SDIO_PORT_C); // "mmc0"
+ board_mmc_register(SDIO_PORT_B);
+ break;
+ case BOOT_DEVICE_SD:
+ board_mmc_register(SDIO_PORT_B); // "mmc0"
+ board_mmc_register(SDIO_PORT_C);
+ break;
+ default:
+ printf("No available mmc device! Check boot device!\n");
+ do_reset(NULL, 0, 0, NULL);
+ break;
+ }
+ // board_mmc_register(SDIO_PORT_B1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_I2C_AML)
+#include <aml_i2c.h>
+
+struct aml_i2c_platform g_aml_i2c_plat = {
+ .wait_count = 1000000,
+ .wait_ack_interval = 5,
+ .wait_read_interval = 5,
+ .wait_xfer_interval = 5,
+ .master_no = AML_I2C_MASTER_AO,
+ .use_pio = 0,
+ .master_i2c_speed = AML_I2C_SPPED_400K,
+ .master_ao_pinmux = {
+ .scl_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_4_REG,
+ .scl_bit = MESON_I2C_MASTER_AO_GPIOAO_4_BIT,
+ .sda_reg = (unsigned long)MESON_I2C_MASTER_AO_GPIOAO_5_REG,
+ .sda_bit = MESON_I2C_MASTER_AO_GPIOAO_5_BIT,
+ }
+};
+
+static void board_i2c_init(void)
+{
+ //disable all other pins which share with I2C_SDA_AO & I2C_SCK_AO
+ clrbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (1 << 2) | (1 << 24) | (1 << 1) | (1 << 23));
+
+ //enable I2C MASTER AO pins
+ setbits_le32(P_AO_RTI_PIN_MUX_REG,
+ (MESON_I2C_MASTER_AO_GPIOAO_4_BIT
+ | MESON_I2C_MASTER_AO_GPIOAO_5_BIT));
+
+ udelay(10);
+
+ //Amlogic I2C controller initialized
+ //note: it must be call before any I2C operation
+ aml_i2c_init();
+
+ udelay(10);
+}
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ return 0;
+}
+#endif
+#if 0
+static void board_run_fastboot(void)
+{
+ run_command("fastboot", 0);
+}
+static void board_run_recovery(void)
+{
+ run_command("movi read dtb 0 ${dtb_mem_addr}", 0);
+ run_command("movi read recovery 0 ${loadaddr}", 0);
+ run_command("bootm ${load_addr}", 0);
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+// int reboot_reason;
+
+ /*
+ * If UMS SW is 'on', the device will run as USB Mass Storage
+ */
+ if (1 == gpio_get_value(GPIO_SW_UMS))
+ run_command("ums 0 mmc 0", 0);
+
+// board_partition_init();
+
+#ifdef CONFIG_DISPLAY_LOGO
+ run_command("showlogo 720p60hz", 0);
+#endif
+
+#if 0
+ reboot_reason = board_reboot_reason();
+ if (ODROID_REBOOT_CMD_FASTBOOT == reboot_reason)
+ board_run_fastboot();
+ else if (ODROID_REBOOT_CMD_RECOVERY == reboot_reason)
+ board_run_recovery();
+#endif
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_USB_DWC_OTG_HCD)
+#include <asm/arch/usb.h>
+
+static void callback_otg_power(char power)
+{
+ gpio_direction_output(GPIO_OTG_PWREN, power);
+}
+
+static void callback_host_power(char power)
+{
+ gpio_direction_output(GPIO_USB_PWREN, power);
+}
+
+static struct amlogic_usb_config usb_config0 = {
+ .clk_selecter = USB_PHY_CLK_SEL_XTAL,
+ .pll_divider = 1,
+ .base_addr = CONFIG_M8_USBPORT_BASE_A,
+ .id_mode = USB_ID_MODE_SW_HOST,
+ .set_vbus_power = callback_otg_power,
+};
+
+static struct amlogic_usb_config usb_config1= {
+ .clk_selecter = USB_PHY_CLK_SEL_XTAL,
+ .pll_divider = 1,
+ .base_addr = CONFIG_M8_USBPORT_BASE_B,
+ .id_mode = USB_ID_MODE_SW_HOST,
+ .set_vbus_power = callback_host_power,
+};
+
+struct amlogic_usb_config *amlogic_usb_config(int port)
+{
+ if (0 == port)
+ return &usb_config0;
+ else if (1 == port)
+ return &usb_config1;
+
+ return NULL;
+}
+#endif
+
+int board_init(void)
+{
+ board_print_info();
+
+ /* T-Flash Init voltage : T-Flash I/O 3.3V, T-Flash mem 3.3V */
+ gpio_request(GPIO_TF1V8, "TF_1V8");
+ gpio_direction_output(GPIO_TF1V8, 0);
+ gpio_request(GPIO_TF3V3, "TF_3V3");
+ gpio_direction_output(GPIO_TF3V3, 1);
+
+ /* LED: SYSLED (Blue color) */
+ gpio_request(GPIO_BLUELED, "blueled");
+ gpio_direction_output(GPIO_BLUELED, 0);
+
+ /*
+ * USB Host: RST_N for GL852
+ * Off by default, On when USB HOST is activated
+ */
+ gpio_request(GPIO_USB_PWREN, "usb_pwren");
+ gpio_direction_output(GPIO_USB_PWREN, 0);
+
+ /*
+ * USB OTG: Power
+ * Off by default, On when USB OTG is activated
+ */
+ gpio_request(GPIO_OTG_PWREN, "otg_pwren");
+ gpio_direction_output(GPIO_OTG_PWREN, 0);
+
+ /*
+ * GPIO: USB MassStorage
+ * Low - Normal boot
+ * High - Act as USB Mass Storage Device
+ */
+ gpio_request(GPIO_SW_UMS, "sw_ums");
+ gpio_direction_input(GPIO_SW_UMS);
+
+ gpio_request(GPIO_HUB_RST, "hub_rst");
+ gpio_direction_output(GPIO_HUB_RST, 0);
+ mdelay(20);
+ gpio_direction_output(GPIO_HUB_RST, 1);
+ mdelay(20);
+
+#if defined(CONFIG_USB_DWC_OTG_HCD)
+ board_usb_init(&usb_config0, BOARD_USB_MODE_SLAVE);
+ board_usb_init(&usb_config1, BOARD_USB_MODE_HOST);
+#endif
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+
+#ifdef CONFIG_AML_HDMITX20
+ hdmi_tx_init();
+#endif
+
+ return 0;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ phys_size_t phys_size = (readl(AO_SEC_GP_CFG0) & 0xFFFF0000) << 4;
+
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ phys_size -= CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+
+ return phys_size;
+}
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ unsigned int ddr_size=0;
+ char loc_name[64] = {0};
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+
+ switch (ddr_size) {
+ case 0x80000000:
+ strcpy(loc_name, "odroidc2_2g\0");
+ break;
+ case 0x40000000:
+ strcpy(loc_name, "odroidc2_1g\0");
+ break;
+ case 0x2000000:
+ strcpy(loc_name, "odroidc2_512m\0");
+ break;
+ default:
+ //printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "odroidc2_unsupport");
+ break;
+ }
+
+ strcpy(name, loc_name);
+ setenv("aml_dt", loc_name);
+
+ return 0;
+}
+#endif
diff --git a/board/highbank/MAINTAINERS b/board/highbank/MAINTAINERS
new file mode 100644
index 0000000..69ddedd
--- /dev/null
+++ b/board/highbank/MAINTAINERS
@@ -0,0 +1,6 @@
+HIGHBANK BOARD
+M: Rob Herring <robh@kernel.org>
+S: Maintained
+F: board/highbank/
+F: include/configs/highbank.h
+F: configs/highbank_defconfig
diff --git a/board/highbank/Makefile b/board/highbank/Makefile
new file mode 100644
index 0000000..d3eb232
--- /dev/null
+++ b/board/highbank/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := highbank.o
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
new file mode 100644
index 0000000..fc2385c
--- /dev/null
+++ b/board/highbank/highbank.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <netdev.h>
+#include <scsi.h>
+
+#include <linux/sizes.h>
+#include <asm/io.h>
+
+#define HB_AHCI_BASE 0xffe08000
+
+#define HB_SREG_A9_PWR_REQ 0xfff3cf00
+#define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04
+#define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20
+
+#define HB_PWR_SUSPEND 0
+#define HB_PWR_SOFT_RESET 1
+#define HB_PWR_HARD_RESET 2
+#define HB_PWR_SHUTDOWN 3
+
+#define PWRDOM_STAT_SATA 0x80000000
+#define PWRDOM_STAT_PCI 0x40000000
+#define PWRDOM_STAT_EMMC 0x20000000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ icache_enable();
+
+ return 0;
+}
+
+/* We know all the init functions have been run now */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+#ifdef CONFIG_CALXEDA_XGMAC
+ rc += calxedaxgmac_initialize(0, 0xfff50000);
+ rc += calxedaxgmac_initialize(1, 0xfff51000);
+#endif
+ return rc;
+}
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+void scsi_init(void)
+{
+ u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
+
+ if (reg & PWRDOM_STAT_SATA) {
+ ahci_init(HB_AHCI_BASE);
+ scsi_scan(1);
+ }
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ char envbuffer[16];
+ u32 boot_choice;
+
+ boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
+ sprintf(envbuffer, "bootcmd%d", boot_choice);
+ if (getenv(envbuffer)) {
+ sprintf(envbuffer, "run bootcmd%d", boot_choice);
+ setenv("bootcmd", envbuffer);
+ } else
+ setenv("bootcmd", "");
+
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = SZ_512M;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+ static const char disabled[] = "disabled";
+ u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
+
+ if (!(reg & PWRDOM_STAT_SATA))
+ do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status",
+ disabled, sizeof(disabled), 1);
+
+ if (!(reg & PWRDOM_STAT_EMMC))
+ do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status",
+ disabled, sizeof(disabled), 1);
+
+ return 0;
+}
+#endif
+
+void reset_cpu(ulong addr)
+{
+ writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
+
+ wfi();
+}
diff --git a/board/htkw/mcx/Kconfig b/board/htkw/mcx/Kconfig
new file mode 100644
index 0000000..25ba548
--- /dev/null
+++ b/board/htkw/mcx/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MCX
+
+config SYS_BOARD
+ default "mcx"
+
+config SYS_VENDOR
+ default "htkw"
+
+config SYS_CONFIG_NAME
+ default "mcx"
+
+endif
diff --git a/board/htkw/mcx/MAINTAINERS b/board/htkw/mcx/MAINTAINERS
new file mode 100644
index 0000000..c5f8873
--- /dev/null
+++ b/board/htkw/mcx/MAINTAINERS
@@ -0,0 +1,6 @@
+MCX BOARD
+M: Ilya Yanok <yanok@emcraft.com>
+S: Maintained
+F: board/htkw/mcx/
+F: include/configs/mcx.h
+F: configs/mcx_defconfig
diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile
new file mode 100644
index 0000000..20149ba
--- /dev/null
+++ b/board/htkw/mcx/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+#
+# Based on ti/evm/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mcx.o
diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c
new file mode 100644
index 0000000..4330cf0
--- /dev/null
+++ b/board/htkw/mcx/mcx.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+ *
+ * Based on ti/evm/evm.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/omap_gpio.h>
+#include <asm/arch/dss.h>
+#include <asm/arch/clock.h>
+#include "errno.h"
+#include <i2c.h>
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/ehci-omap.h>
+#endif
+#include "mcx.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HOT_WATER_BUTTON 42
+#define LCD_OUTPUT 55
+
+/* Address of the framebuffer in RAM. */
+#define FB_START_ADDRESS 0x88000000
+
+#ifdef CONFIG_USB_EHCI
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(int index)
+{
+ return omap_ehci_hcd_stop();
+}
+#endif
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ gpio_direction_output(LCD_OUTPUT, 0);
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ if (gpio_request(HOT_WATER_BUTTON, "hot-water-button") < 0) {
+ puts("Failed to get hot-water-button pin\n");
+ return -ENODEV;
+ }
+ gpio_direction_input(HOT_WATER_BUTTON);
+
+ /*
+ * if hot-water-button is pressed
+ * change bootcmd
+ */
+ if (gpio_get_value(HOT_WATER_BUTTON))
+ return 0;
+
+ setenv("bootcmd", "run swupdate");
+
+ return 0;
+}
+#endif
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_MCX();
+}
+
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+
+static struct panel_config lcd_cfg = {
+ .timing_h = PANEL_TIMING_H(40, 40, 48),
+ .timing_v = PANEL_TIMING_V(29, 13, 3),
+ .pol_freq = 0x00003000, /* Pol Freq */
+ .divisor = 0x0001000E,
+ .panel_type = 0x01, /* TFT */
+ .data_lines = 0x03, /* 24 Bit RGB */
+ .load_mode = 0x02, /* Frame Mode */
+ .panel_color = 0,
+ .lcd_size = PANEL_LCD_SIZE(800, 480),
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
+};
+
+int board_video_init(void)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ void *fb;
+
+ fb = (void *)FB_START_ADDRESS;
+
+ lcd_cfg.frame_buffer = fb;
+
+ setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
+ setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
+
+ omap3_dss_panel_config(&lcd_cfg);
+ omap3_dss_enable();
+
+ return 0;
+}
+#endif
diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h
new file mode 100644
index 0000000..d6c5df2
--- /dev/null
+++ b/board/htkw/mcx/mcx.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+ *
+ * Based on ti/evm/evm.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _AM3517EVM_H_
+#define _AM3517EVM_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "HTKW mcx Board",
+ "NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_MCX() \
+ /* SDRC */\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_CKE0), (M0)) \
+ MUX_VAL(CP(SDRC_CKE1), (M0)) \
+ MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
+ /*sdrc_strben_dly0*/\
+ MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
+ /*sdrc_strben_dly1*/\
+ /* GPMC */\
+ MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_A10), (IEN | PTU | EN | M4)) \
+ /* GPIO_43 LCD buffer enable */ \
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \
+ /* GPIO_57 TS_PenIRQn */\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \
+ /* GPIO_58 ETHERNET RESET */\
+ MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \
+ /* GPIO_61 SD-CARD CD */ \
+ MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \
+ /* GPIO_62 Nand write protect, keep enabled */ \
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
+ /* GPIO_65 SD-CARD WP */\
+ /* DSS */\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
+ /* CAMERA */\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \
+ /* MMC */\
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
+ \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \
+ /* GPIO_131 LCD Enable */ \
+ MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \
+ /* GPIO_132 USB host Enable */\
+ MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \
+ /* GPIO_133 HDMI PD */\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\
+ /* McBSP */\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\
+ \
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\
+ \
+ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \
+ /* GPIO_152 USB phy2 reset */\
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \
+ /* GPIO_153 */\
+ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \
+ /* GPIO_154 USB phy1 reset */\
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \
+ /* GPIO_155 TS_BUSY */\
+ /* UART */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
+ /* I2C */\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) \
+ /* GPIO_170 Touchscreen ISR */\
+ /* McSPI */\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \
+ /* HSUSB2_dat7 */\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \
+ /* HSUSB2_dat4 */\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \
+ /* HSUSB2_dat5 */\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \
+ /* HSUSB2_dat6 */\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \
+ /* HSUSB2_dat3 */\
+ /* CCDC */\
+ MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \
+ /* CCDC_FIELD: gpio_95, uP-TXD4 */ \
+ MUX_VAL(CP(CCDC_FIELD), (IDIS | PTD | DIS | M2)) \
+ /* CCDC_HD: gpio_96, uP-RTS4# */ \
+ MUX_VAL(CP(CCDC_HD), (IDIS | PTD | DIS | M2)) \
+ /* CCDC_VD: gpio_97, uP-CTS4# */ \
+ MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M2)) \
+ /* CCDC_WEN: gpio_98, uP-RXD4 */ \
+ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M2)) \
+ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \
+ /* RMII */\
+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
+ MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
+ MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
+ /* HECC */\
+ MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M0)) \
+ /* HSUSB */\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
+ /* HDQ */\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
+ /* Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\
+ MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \
+ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\
+ /* JTAG */\
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\
+ /* ETK (ES2 onwards) */\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
+ /* hsusb1_stp */ \
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
+ /* hsusb1_clk */\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
+ /* Die to Die */\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
+
+#endif
diff --git a/board/ibf-dsp561/Kconfig b/board/ibf-dsp561/Kconfig
new file mode 100644
index 0000000..acf5d7c
--- /dev/null
+++ b/board/ibf-dsp561/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_IBF_DSP561
+
+config SYS_BOARD
+ default "ibf-dsp561"
+
+config SYS_CONFIG_NAME
+ default "ibf-dsp561"
+
+endif
diff --git a/board/ibf-dsp561/MAINTAINERS b/board/ibf-dsp561/MAINTAINERS
new file mode 100644
index 0000000..dfd0f90
--- /dev/null
+++ b/board/ibf-dsp561/MAINTAINERS
@@ -0,0 +1,6 @@
+IBF-DSP561 BOARD
+M: I-SYST Micromodule <support@i-syst.com>
+S: Maintained
+F: board/ibf-dsp561/
+F: include/configs/ibf-dsp561.h
+F: configs/ibf-dsp561_defconfig
diff --git a/board/ibf-dsp561/Makefile b/board/ibf-dsp561/Makefile
new file mode 100644
index 0000000..5b05ba8
--- /dev/null
+++ b/board/ibf-dsp561/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ibf-dsp561.o
diff --git a/board/ibf-dsp561/config.mk b/board/ibf-dsp561/config.mk
new file mode 100644
index 0000000..854d7db
--- /dev/null
+++ b/board/ibf-dsp561/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/ibf-dsp561/ibf-dsp561.c b/board/ibf-dsp561/ibf-dsp561.c
new file mode 100644
index 0000000..d2ac7a5
--- /dev/null
+++ b/board/ibf-dsp561/ibf-dsp561.c
@@ -0,0 +1,26 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2009 I-SYST.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: I-SYST IBF-DSP561 Micromodule\n");
+ printf(" Support: http://www.i-syst.com/\n");
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_AX88180
+int board_eth_init(bd_t *bis)
+{
+ return ax88180_initialize(bis);
+}
+#endif
diff --git a/board/icecube/Kconfig b/board/icecube/Kconfig
new file mode 100644
index 0000000..e5b2153
--- /dev/null
+++ b/board/icecube/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_ICECUBE
+
+config SYS_BOARD
+ default "icecube"
+
+config SYS_CONFIG_NAME
+ default "IceCube"
+
+endif
diff --git a/board/icecube/MAINTAINERS b/board/icecube/MAINTAINERS
new file mode 100644
index 0000000..8a24eb4
--- /dev/null
+++ b/board/icecube/MAINTAINERS
@@ -0,0 +1,21 @@
+ICECUBE BOARD
+M: Wolfgang Denk <wd@denx.de>
+S: Maintained
+F: board/icecube/
+F: include/configs/IceCube.h
+F: configs/icecube_5200_defconfig
+
+ICECUBE_5200_DDR BOARD
+#M: -
+S: Maintained
+F: configs/icecube_5200_DDR_defconfig
+F: configs/icecube_5200_DDR_LOWBOOT_defconfig
+F: configs/icecube_5200_DDR_LOWBOOT08_defconfig
+F: configs/icecube_5200_LOWBOOT_defconfig
+F: configs/icecube_5200_LOWBOOT08_defconfig
+F: configs/Lite5200_defconfig
+F: configs/Lite5200_LOWBOOT_defconfig
+F: configs/Lite5200_LOWBOOT08_defconfig
+F: configs/lite5200b_defconfig
+F: configs/lite5200b_LOWBOOT_defconfig
+F: configs/lite5200b_PM_defconfig
diff --git a/board/icecube/Makefile b/board/icecube/Makefile
new file mode 100644
index 0000000..c3c2cd1
--- /dev/null
+++ b/board/icecube/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := icecube.o flash.o
diff --git a/board/icecube/README b/board/icecube/README
new file mode 100644
index 0000000..5252bc9
--- /dev/null
+++ b/board/icecube/README
@@ -0,0 +1,13 @@
+---------------------------------------------------------------------------
+Build target Flash address | BDI "go" command | Reset Vector
+---------------------------------------------------------------------------
+Lite5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100
+Lite5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100
+Lite5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100
+icecube_5200 0xFFF00000 | 0xFFF00100 | 0xFFF00100
+icecube_5200_LOWBOOT 0xFF000000 | 0xFF000100 | 0x00000100
+icecube_5200_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100
+icecube_5200_DDR 0xFFF00000 | 0xFFF00100 | 0xFFF00100
+icecube_5200_DDR_LOWBOOT 0xFF800000 | 0xFF800100 | 0x00000100
+icecube_5200_DDR_LOWBOOT08 0xFF800000 | 0xFF800100 | 0x00000100
+---------------------------------------------------------------------------
diff --git a/board/icecube/README.Lite5200B_low_power b/board/icecube/README.Lite5200B_low_power
new file mode 100644
index 0000000..5b04fbb
--- /dev/null
+++ b/board/icecube/README.Lite5200B_low_power
@@ -0,0 +1,22 @@
+Lite5200B wakeup from low-power mode (CONFIG_LITE5200B_PM)
+----------------------------------------------------------
+
+Low-power mode as described in Lite5200B User's Manual, means that
+with support of MC68HLC908QT1 microcontroller (refered to as QT),
+everything but the SDRAM can be powered down. This brings
+maximum power saving, while one can still restore previous state
+quickly.
+
+Quick overview where U-Boot comes into the picture:
+- OS saves device states
+- OS saves wakeup handler address to physical 0x0, puts SDRAM into
+ self-refresh and signals to QT, it should power down the board
+- / board is sleeping here /
+- someone presses SW4 (connected to QT)
+- U-Boot checks PSC2_4 pin, if QT drives it down, then we woke up,
+ so get SDRAM out of self-refresh and transfer control to OS
+ wakeup handler
+- OS restores device states
+
+This was tested on Linux with USB and Ethernet in use. Adding
+support for other devices is an OS issue.
diff --git a/board/icecube/flash.c b/board/icecube/flash.c
new file mode 100644
index 0000000..a044e8f
--- /dev/null
+++ b/board/icecube/flash.c
@@ -0,0 +1,477 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#ifndef CONFIG_FLASH_CFI_DRIVER
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ * has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define FLASH_ID_MASK 0xFFFF
+#else
+typedef unsigned char FLASH_PORT_WIDTH;
+typedef volatile unsigned char FLASH_PORT_WIDTHV;
+#define FLASH_ID_MASK 0xFF
+#endif
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#define FLASH_CYCLE1 0x0555
+#define FLASH_CYCLE2 0x02aa
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+ unsigned long size = 0;
+ int i;
+ extern void flash_preinit(void);
+ extern void flash_afterinit(ulong);
+ ulong flashbase = CONFIG_SYS_FLASH_BASE;
+
+ flash_preinit();
+
+ /* Init: no FLASHes known */
+ for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ memset(&flash_info[i], 0, sizeof(flash_info_t));
+
+ flash_info[i].size =
+ flash_get_size((FPW *)flashbase, &flash_info[i]);
+
+ size += flash_info[i].size;
+ flashbase += 0x800000;
+ }
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+ flash_get_info(CONFIG_SYS_MONITOR_BASE));
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+ flash_get_info(CONFIG_ENV_ADDR));
+#endif
+
+
+ flash_afterinit(size);
+ return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+ FPWV *base = (FPWV *)(info->start[0]);
+
+ /* Put FLASH back in read mode */
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+ *base = (FPW)0x00FF00FF; /* Intel Read Mode */
+ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+ *base = (FPW)0x00F000F0; /* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+ int i;
+ flash_info_t * info;
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
+ info = & flash_info[i];
+ if (info->size &&
+ info->start[0] <= base && base <= info->start[0] + info->size - 1)
+ break;
+ }
+
+ return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+ uchar *boottype;
+ uchar *bootletter;
+ char *fmt;
+ uchar botbootletter[] = "B";
+ uchar topbootletter[] = "T";
+ uchar botboottype[] = "bottom boot sector";
+ uchar topboottype[] = "top boot sector";
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ case FLASH_MAN_SST: printf ("SST "); break;
+ case FLASH_MAN_STM: printf ("STM "); break;
+ case FLASH_MAN_INTEL: printf ("INTEL "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ /* check for top or bottom boot, if it applies */
+ if (info->flash_id & FLASH_BTYPE) {
+ boottype = botboottype;
+ bootletter = botbootletter;
+ }
+ else {
+ boottype = topboottype;
+ bootletter = topbootletter;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AMDLV065D:
+ fmt = "29LV065 (64 Mbit, uniform sectors)\n";
+ break;
+ default:
+ fmt = "Unknown Chip Type\n";
+ break;
+ }
+
+ printf (fmt, bootletter, boottype);
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20,
+ info->sector_count);
+
+ printf (" Sector Start Addresses:");
+
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0) {
+ printf ("\n ");
+ }
+
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+ int i;
+ FPWV* addr2;
+
+ /* Write auto select command: read Manufacturer ID */
+ /* Write auto select command sequence and test FLASH answer */
+ addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
+ addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
+ addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
+
+ /* The manufacturer codes are only 1 byte, so just use 1 byte.
+ * This works for any bus width and any FLASH device width.
+ */
+ udelay(100);
+ switch (addr[0] & 0xff) {
+
+ case (uchar)AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+
+ case (uchar)INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ break;
+ }
+
+ /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+ if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
+
+ case (FPW)AMD_ID_LV065D:
+ info->flash_id += FLASH_AMDLV065D;
+ info->sector_count = 128;
+ info->size = 0x00800000;
+ for( i = 0; i < info->sector_count; i++ )
+ info->start[i] = (ulong)addr + (i * 0x10000);
+ break; /* => 8 or 16 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* test for real flash at bank 1 */
+ addr2 = (FPW *)((ulong)addr | 0x800000);
+ if (addr2 != addr &&
+ ((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) {
+ /* Seems 2 banks are the same space (8Mb chip is installed,
+ * J24 in default position (CS0)). Disable this (first) bank.
+ */
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ }
+ /* Put FLASH back in read mode */
+ flash_reset(info);
+
+ return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ FPWV *addr;
+ int flag, prot, sect;
+ int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+ ulong start, now, last;
+ int rcode = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AMDLV065D:
+ break;
+ case FLASH_UNKNOWN:
+ default:
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ last = get_timer(0);
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+ if (info->protect[sect] != 0) /* protected, skip it */
+ continue;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr = (FPWV *)(info->start[sect]);
+ if (intel) {
+ *addr = (FPW)0x00500050; /* clear status register */
+ *addr = (FPW)0x00200020; /* erase setup */
+ *addr = (FPW)0x00D000D0; /* erase confirm */
+ }
+ else {
+ /* must be AMD style if not Intel */
+ FPWV *base; /* first address in bank */
+
+ base = (FPWV *)(info->start[0]);
+ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */
+ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
+ *addr = (FPW)0x00300030; /* erase sector */
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer(0);
+
+ /* wait at least 50us for AMD, 80us for Intel.
+ * Let's wait 1 ms.
+ */
+ udelay (1000);
+
+ while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+
+ if (intel) {
+ /* suspend erase */
+ *addr = (FPW)0x00B000B0;
+ }
+
+ flash_reset(info); /* reset to read mode */
+ rcode = 1; /* failed */
+ break;
+ }
+
+ /* show that we're waiting */
+ if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
+ putc ('.');
+ last = get_timer(0);
+ }
+ }
+
+ /* show that we're waiting */
+ if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */
+ putc ('.');
+ last = get_timer(0);
+ }
+
+ flash_reset(info); /* reset to read mode */
+ }
+
+ printf (" done\n");
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+ int bytes; /* number of bytes to program in current word */
+ int left; /* number of bytes left to program */
+ int i, res;
+
+ for (left = cnt, res = 0;
+ left > 0 && res == 0;
+ addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+ bytes = addr & (sizeof(data) - 1);
+ addr &= ~(sizeof(data) - 1);
+
+ /* combine source and destination data so can program
+ * an entire word of 16 or 32 bits
+ */
+ for (i = 0; i < sizeof(data); i++) {
+ data <<= 8;
+ if (i < bytes || i - bytes >= left )
+ data += *((uchar *)addr + i);
+ else
+ data += *src++;
+ }
+
+ /* write one word to the flash */
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ res = write_word_amd(info, (FPWV *)addr, data);
+ break;
+ default:
+ /* unknown flash type, error! */
+ printf ("missing or unknown FLASH type\n");
+ res = 1; /* not really a timeout, but gives error */
+ break;
+ }
+ }
+
+ return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+ ulong start;
+ int flag;
+ int res = 0; /* result, assume success */
+ FPWV *base; /* first address in flash bank */
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*dest & data) != data) {
+ return (2);
+ }
+
+
+ base = (FPWV *)(info->start[0]);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
+ base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
+ base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
+
+ *dest = data; /* start programming the data */
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer (0);
+
+ /* data polling for D7 */
+ while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ *dest = (FPW)0x00F000F0; /* reset bank */
+ res = 1;
+ }
+ }
+
+ return (res);
+}
+#endif /*CONFIG_FLASH_CFI_DRIVER*/
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
new file mode 100644
index 0000000..f0af24a
--- /dev/null
+++ b/board/icecube/icecube.c
@@ -0,0 +1,326 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <libfdt.h>
+#include <netdev.h>
+
+#if defined(CONFIG_LITE5200B)
+#include "mt46v32m16.h"
+#else
+# if defined(CONFIG_MPC5200_DDR)
+# include "mt46v16m16-75.h"
+# else
+#include "mt48lc16m16a2-75.h"
+# endif
+#endif
+
+#ifdef CONFIG_LITE5200B_PM
+/* u-boot part of low-power mode implementation */
+#define SAVED_ADDR (*(void **)0x00000000)
+#define PSC2_4 0x02
+
+void lite5200b_wakeup(void)
+{
+ unsigned char wakeup_pin;
+ void (*linux_wakeup)(void);
+
+ /* check PSC2_4, if it's down "QT" is signaling we have a wakeup
+ * from low power mode */
+ *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
+ __asm__ volatile ("sync");
+
+ wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
+ if (wakeup_pin & PSC2_4)
+ return;
+
+ /* acknowledge to "QT"
+ * by holding pin at 1 for 10 uS */
+ *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
+ __asm__ volatile ("sync");
+ *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
+ __asm__ volatile ("sync");
+ udelay(10);
+
+ /* put ram out of self-refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */
+ __asm__ volatile ("sync");
+ *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */
+ __asm__ volatile ("sync");
+ *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */
+ __asm__ volatile ("sync");
+ udelay(10); /* wait a bit */
+
+ /* jump back to linux kernel code */
+ linux_wakeup = SAVED_ADDR;
+ printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
+ (unsigned long)linux_wakeup);
+ linux_wakeup();
+}
+#else
+#define lite5200b_wakeup()
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+#endif
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set tap delay */
+ *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ }
+
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+ /* find RAM size using SDRAM CS1 only */
+ if (!dramsize)
+ sdram_start(0);
+ test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ if (!dramsize) {
+ sdram_start(1);
+ test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ }
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize2 = test1;
+ } else {
+ dramsize2 = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20)) {
+ dramsize2 = 0;
+ }
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+ | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13) {
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ } else {
+ dramsize = 0;
+ }
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ if (dramsize2 >= 0x13) {
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ } else {
+ dramsize2 = 0;
+ }
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+ }
+
+ lite5200b_wakeup();
+
+ return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+#if defined (CONFIG_LITE5200B)
+ puts ("Board: Freescale Lite5200B\n");
+#else
+ puts ("Board: Motorola MPC5200 (IceCube)\n");
+#endif
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+ if (size == 0x800000) { /* adjust mapping */
+ *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+ START_REG(CONFIG_SYS_BOOTCS_START | size);
+ *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+ }
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+ debug ("init_ide_reset\n");
+
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+ /* Deassert reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+ debug ("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+ /* Make a delay. MPC5200 spec says 25 usec min */
+ udelay(500000);
+ } else {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+ }
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h
new file mode 100644
index 0000000..919876f
--- /dev/null
+++ b/board/icecube/mt46v16m16-75.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x705f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/icecube/mt46v32m16.h b/board/icecube/mt46v32m16.h
new file mode 100644
index 0000000..a200bc7
--- /dev/null
+++ b/board/icecube/mt46v32m16.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x704f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..0133eaa
--- /dev/null
+++ b/board/icecube/mt48lc16m16a2-75.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 0 /* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/icpdas/lp8x4x/Kconfig b/board/icpdas/lp8x4x/Kconfig
new file mode 100644
index 0000000..3e87c40
--- /dev/null
+++ b/board/icpdas/lp8x4x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_LP8X4X
+
+config SYS_BOARD
+ default "lp8x4x"
+
+config SYS_VENDOR
+ default "icpdas"
+
+config SYS_CONFIG_NAME
+ default "lp8x4x"
+
+endif
diff --git a/board/icpdas/lp8x4x/MAINTAINERS b/board/icpdas/lp8x4x/MAINTAINERS
new file mode 100644
index 0000000..90a82e3
--- /dev/null
+++ b/board/icpdas/lp8x4x/MAINTAINERS
@@ -0,0 +1,6 @@
+LP8X4X BOARD
+M: Sergey Yanovich <ynvich@gmail.com>
+S: Maintained
+F: board/icpdas/lp8x4x/
+F: include/configs/lp8x4x.h
+F: configs/lp8x4x_defconfig
diff --git a/board/icpdas/lp8x4x/Makefile b/board/icpdas/lp8x4x/Makefile
new file mode 100644
index 0000000..88e0606
--- /dev/null
+++ b/board/icpdas/lp8x4x/Makefile
@@ -0,0 +1,9 @@
+#
+# ICPDAS LP-8x4x Support
+#
+# Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := lp8x4x.o
diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c
new file mode 100644
index 0000000..a136dc4
--- /dev/null
+++ b/board/icpdas/lp8x4x/lp8x4x.c
@@ -0,0 +1,128 @@
+/*
+ * ICP DAS LP-8x4x Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * adapted from Voipac PXA270 Support by
+ * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/regs-mmc.h>
+#include <asm/arch/pxa.h>
+#include <netdev.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ pxa2xx_dram_init();
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+int board_usb_init(int index, enum usb_init_type init)
+{
+ if (index !=0 || init != USB_INIT_HOST)
+ return -1;
+
+ writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
+
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+ udelay(11);
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ continue; /* required by checkpath.pl */
+
+ writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
+ writel(readl(UHCRHDA) & ~(0x1000), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x800, UHCRHDA);
+
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+ /* Clear any OTG Pin Hold */
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+ /* Set port power control mask bits, only 3 ports. */
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+ return 0;
+}
+
+int usb_board_stop(void)
+{
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+ udelay(11);
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
+ udelay(10);
+
+ writel(readl(UHCHR) | UHCHR_SSEP0 | UHCHR_SSE, UHCHR);
+
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ if (index !=0 || init != USB_INIT_HOST)
+ return -1;
+
+ return usb_board_stop();
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
diff --git a/board/ids/ids8313/Kconfig b/board/ids/ids8313/Kconfig
new file mode 100644
index 0000000..d165b4b
--- /dev/null
+++ b/board/ids/ids8313/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IDS8313
+
+config SYS_BOARD
+ default "ids8313"
+
+config SYS_VENDOR
+ default "ids"
+
+config SYS_CONFIG_NAME
+ default "ids8313"
+
+endif
diff --git a/board/ids/ids8313/MAINTAINERS b/board/ids/ids8313/MAINTAINERS
new file mode 100644
index 0000000..c5b2f9e
--- /dev/null
+++ b/board/ids/ids8313/MAINTAINERS
@@ -0,0 +1,6 @@
+IDS8313 BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: board/ids/ids8313/
+F: include/configs/ids8313.h
+F: configs/ids8313_defconfig
diff --git a/board/ids/ids8313/Makefile b/board/ids/ids8313/Makefile
new file mode 100644
index 0000000..56cfd40
--- /dev/null
+++ b/board/ids/ids8313/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2013
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ids8313.o
diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
new file mode 100644
index 0000000..e7838dc
--- /dev/null
+++ b/board/ids/ids8313/ids8313.c
@@ -0,0 +1,210 @@
+/*
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (c) 2011 IDS GmbH, Germany
+ * ids8313.c - ids8313 board support.
+ *
+ * Sergej Stepanov <ste@ids.de>
+ * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spi.h>
+#include <libfdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+/** CPLD contains the info about:
+ * - board type: *pCpld & 0xF0
+ * - hw-revision: *pCpld & 0x0F
+ * - cpld-revision: *pCpld+1
+ */
+int checkboard(void)
+{
+ char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
+ u8 u8Vers = readb(pcpld);
+ u8 u8Revs = readb(pcpld + 1);
+
+ printf("Board: ");
+ switch (u8Vers & 0xF0) {
+ case '\x40':
+ printf("CU73X");
+ break;
+ case '\x50':
+ printf("CC73X");
+ break;
+ default:
+ printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
+ return 0;
+ }
+ printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n",
+ u8Vers & 0x0F, u8Revs & 0xFF);
+ return 0;
+}
+
+/*
+ * fixed sdram init
+ */
+int fixed_sdram(unsigned long config)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE << 20;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ u32 msize_log2 = __ilog2(msize);
+
+ out_be32(&im->sysconf.ddrlaw[0].bar,
+ (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+ out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+ out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+ sync();
+
+ /*
+ * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+ * or the DDR2 controller may fail to initialize correctly.
+ */
+ udelay(50000);
+
+ out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+ out_be32(&im->ddr.cs_config[0], config);
+
+ /* currently we use only one CS, so disable the other banks */
+ out_be32(&im->ddr.cs_config[1], 0);
+ out_be32(&im->ddr.cs_config[2], 0);
+ out_be32(&im->ddr.cs_config[3], 0);
+
+ out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+ out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
+ out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+ out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+ out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
+
+ out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+ out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+ sync();
+ udelay(300);
+
+ /* enable DDR controller */
+ setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+ /* now check the real size */
+ disable_addr_trans();
+ msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
+ enable_addr_trans();
+#endif
+ return msize;
+}
+
+static int setup_sdram(void)
+{
+ u32 msize = CONFIG_SYS_DDR_SIZE << 20;
+ long int size_01, size_02;
+
+ size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
+ size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
+
+ if (size_01 > size_02)
+ msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
+ else
+ msize = size_02;
+
+ return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ fsl_lbc_t *lbc = &im->im_lbc;
+ u32 msize = 0;
+
+ if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ msize = setup_sdram();
+
+ out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+ out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+ sync();
+
+ return msize;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
+
+/* gpio mask for spi_cs */
+#define IDSCPLD_SPI_CS_MASK 0x00000001
+/* spi_cs multiplexed through cpld */
+#define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf)
+
+#if defined(CONFIG_MISC_INIT_R)
+/* srp umcr mask for rts */
+#define IDSUMCR_RTS_MASK 0x04
+int misc_init_r(void)
+{
+ /*srp*/
+ duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
+ duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
+
+ gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+ u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+ /* deactivate spi_cs channels */
+ out_8(spi_base, 0);
+ /* deactivate the spi_cs */
+ setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
+ /*srp - deactivate rts*/
+ out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
+ out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
+
+
+ gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MPC8XXX_SPI
+/*
+ * The following are used to control the SPI chip selects
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && ((cs >= 0) && (cs <= 2));
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+ u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+ /* select the spi_cs channel */
+ out_8(spi_base, 1 << slave->cs);
+ /* activate the spi_cs */
+ clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+ u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+ /* select the spi_cs channel */
+ out_8(spi_base, 1 << slave->cs);
+ /* deactivate the spi_cs */
+ setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
+}
+#endif /* CONFIG_HARD_SPI */
diff --git a/board/ifm/ac14xx/Kconfig b/board/ifm/ac14xx/Kconfig
new file mode 100644
index 0000000..97e80d5
--- /dev/null
+++ b/board/ifm/ac14xx/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AC14XX
+
+config SYS_BOARD
+ default "ac14xx"
+
+config SYS_VENDOR
+ default "ifm"
+
+config SYS_CONFIG_NAME
+ default "ac14xx"
+
+endif
diff --git a/board/ifm/ac14xx/MAINTAINERS b/board/ifm/ac14xx/MAINTAINERS
new file mode 100644
index 0000000..8fd74e5
--- /dev/null
+++ b/board/ifm/ac14xx/MAINTAINERS
@@ -0,0 +1,6 @@
+AC14XX BOARD
+M: Anatolij Gustschin <agust@denx.de>
+S: Maintained
+F: board/ifm/ac14xx/
+F: include/configs/ac14xx.h
+F: configs/ac14xx_defconfig
diff --git a/board/ifm/ac14xx/Makefile b/board/ifm/ac14xx/Makefile
new file mode 100644
index 0000000..55def60
--- /dev/null
+++ b/board/ifm/ac14xx/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ac14xx.o
diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c
new file mode 100644
index 0000000..5d2ab2f
--- /dev/null
+++ b/board/ifm/ac14xx/ac14xx.c
@@ -0,0 +1,617 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ * (C) Copyright 2010 ifm ecomatic GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+
+static int eeprom_diag;
+static int mac_diag;
+static int gpio_diag;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_configure(void)
+{
+ immap_t *im;
+ gpio512x_t *gpioregs;
+
+ im = (immap_t *) CONFIG_SYS_IMMR;
+ gpioregs = &im->gpio;
+ out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
+ out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
+
+ /*
+ * out_be32(&gpioregs->gpdir, 0xC2293020);
+ * workaround for a hardware effect: configure direction in pieces,
+ * setting all outputs at once drops the reset line too low and
+ * makes us lose the MII connection (breaks ethernet for us)
+ */
+ out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
+ setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
+ udelay(10);
+ setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
+ udelay(10);
+ setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
+ udelay(10);
+ setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
+
+ /* to turn from red to yellow when U-Boot runs */
+ setbits_be32(&gpioregs->gpdat, 0x00002020);
+ out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
+ out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
+ out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
+ out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
+}
+
+/* the physical location of the pins */
+#define GPIOKEY_ROW_BITMASK 0x40000000
+#define GPIOKEY_ROW_UPPER 0
+#define GPIOKEY_ROW_LOWER 1
+
+#define GPIOKEY_COL0_BITMASK 0x20000000
+#define GPIOKEY_COL1_BITMASK 0x10000000
+#define GPIOKEY_COL2_BITMASK 0x08000000
+
+/* the logical presentation of pressed keys */
+#define GPIOKEY_BIT_FNLEFT (1 << 5)
+#define GPIOKEY_BIT_FNRIGHT (1 << 4)
+#define GPIOKEY_BIT_DIRUP (1 << 3)
+#define GPIOKEY_BIT_DIRLEFT (1 << 2)
+#define GPIOKEY_BIT_DIRRIGHT (1 << 1)
+#define GPIOKEY_BIT_DIRDOWN (1 << 0)
+
+/* the hotkey combination which starts recovery */
+#define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
+ GPIOKEY_BIT_DIRDOWN)
+
+static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
+{
+
+ if (row)
+ setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
+ else
+ clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
+ udelay(10);
+}
+
+static u32 gpio_querykbd(void)
+{
+ immap_t *im;
+ gpio512x_t *gpioregs;
+ u32 keybits;
+ u32 input;
+
+ im = (immap_t *)CONFIG_SYS_IMMR;
+ gpioregs = &im->gpio;
+ keybits = 0;
+
+ /* query upper row */
+ gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
+ input = in_be32(&gpioregs->gpdat);
+ if ((input & GPIOKEY_COL0_BITMASK) == 0)
+ keybits |= GPIOKEY_BIT_FNLEFT;
+ if ((input & GPIOKEY_COL1_BITMASK) == 0)
+ keybits |= GPIOKEY_BIT_DIRUP;
+ if ((input & GPIOKEY_COL2_BITMASK) == 0)
+ keybits |= GPIOKEY_BIT_FNRIGHT;
+
+ /* query lower row */
+ gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
+ input = in_be32(&gpioregs->gpdat);
+ if ((input & GPIOKEY_COL0_BITMASK) == 0)
+ keybits |= GPIOKEY_BIT_DIRLEFT;
+ if ((input & GPIOKEY_COL1_BITMASK) == 0)
+ keybits |= GPIOKEY_BIT_DIRRIGHT;
+ if ((input & GPIOKEY_COL2_BITMASK) == 0)
+ keybits |= GPIOKEY_BIT_DIRDOWN;
+
+ /* return bit pattern for keys */
+ return keybits;
+}
+
+/* excerpt from the recovery's hw_info.h */
+
+struct __attribute__ ((__packed__)) eeprom_layout {
+ char magic[3]; /** 'ifm' */
+ u8 len[2]; /** content length without magic/len fields */
+ u8 version[3]; /** structure version */
+ u8 type; /** type of PCB */
+ u8 reserved[0x37]; /** padding up to offset 0x40 */
+ u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */
+};
+
+#define HW_COMP_MAINCPU 2
+
+static struct eeprom_layout eeprom_content;
+static int eeprom_was_read; /* has_been_read */
+static int eeprom_is_valid;
+static int eeprom_version;
+
+#define get_eeprom_field_int(name) ({ \
+ int value; \
+ int idx; \
+ value = 0; \
+ for (idx = 0; idx < sizeof(name); idx++) { \
+ value <<= 8; \
+ value |= name[idx]; \
+ } \
+ value; \
+})
+
+static int read_eeprom(void)
+{
+ int eeprom_datalen;
+ int ret;
+
+ if (eeprom_was_read)
+ return 0;
+
+ eeprom_is_valid = 0;
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+ (uchar *)&eeprom_content, sizeof(eeprom_content));
+ if (eeprom_diag) {
+ printf("DIAG: %s() read rc[%d], size[%d]\n",
+ __func__, ret, sizeof(eeprom_content));
+ }
+
+ if (ret != 0)
+ return -1;
+
+ eeprom_was_read = 1;
+
+ /*
+ * check validity of EEPROM content
+ * (check version, length, optionally checksum)
+ */
+ eeprom_is_valid = 1;
+ eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
+ eeprom_version = get_eeprom_field_int(eeprom_content.version);
+
+ if (eeprom_diag) {
+ printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
+ __func__, eeprom_content.magic[0],
+ eeprom_content.magic[1], eeprom_content.magic[2],
+ eeprom_datalen, eeprom_version, eeprom_content.type);
+ }
+ if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
+ eeprom_is_valid = 0;
+ if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
+ eeprom_is_valid = 0;
+ if ((eeprom_version != 1) && (eeprom_version != 2))
+ eeprom_is_valid = 0;
+ if (eeprom_content.type != HW_COMP_MAINCPU)
+ eeprom_is_valid = 0;
+
+ if (eeprom_diag)
+ printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);
+
+ return ret;
+}
+
+int mac_read_from_eeprom(void)
+{
+ const u8 *mac;
+ const char *mac_txt;
+
+ if (read_eeprom()) {
+ printf("I2C EEPROM read failed.\n");
+ return -1;
+ }
+
+ if (!eeprom_is_valid) {
+ printf("I2C EEPROM content not valid\n");
+ return -1;
+ }
+
+ mac = NULL;
+ switch (eeprom_version) {
+ case 1:
+ case 2:
+ mac = (const u8 *)&eeprom_content.macaddress;
+ break;
+ }
+
+ if (mac && is_valid_ether_addr(mac)) {
+ eth_setenv_enetaddr("ethaddr", mac);
+ if (mac_diag) {
+ mac_txt = getenv("ethaddr");
+ if (mac_txt)
+ printf("DIAG: MAC value [%s]\n", mac_txt);
+ else
+ printf("DIAG: failed to setup MAC env\n");
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * BEWARE!
+ * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
+ * which the ADS, Aria or PDM360NG boards are using
+ * (the steps outlined here refer to the Micron datasheet)
+ */
+u32 sdram_init_seq[] = {
+ /* item 6, at least one NOP after CKE went high */
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ /* item 7, precharge all; item 8, tRP (20ns) */
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_NOP,
+ /* item 9, extended mode register; item 10, tMRD 10ns) */
+ CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
+ CONFIG_SYS_DDRCMD_NOP,
+ /*
+ * item 11, (base) mode register _with_ reset DLL;
+ * item 12, tMRD (10ns)
+ */
+ CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
+ CONFIG_SYS_MICRON_BMODE_PARAM,
+ CONFIG_SYS_DDRCMD_NOP,
+ /* item 13, precharge all; item 14, tRP (20ns) */
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_NOP,
+ /*
+ * item 15, auto refresh (i.e. refresh with CKE held high);
+ * item 16, tRFC (70ns)
+ */
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ /*
+ * item 17, auto refresh (i.e. refresh with CKE held high);
+ * item 18, tRFC (70ns)
+ */
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
+ CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
+ CONFIG_SYS_DDRCMD_NOP,
+ /*
+ * item 21, "actually done", but make sure 200 DRAM clock cycles
+ * have passed after DLL reset before READ requests are issued
+ * (200 cycles at 160MHz -> 1.25 usec)
+ */
+ /* EMPTY, optional, we don't do it */
+};
+
+phys_size_t initdram(int board_type)
+{
+ return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
+}
+
+int misc_init_r(void)
+{
+ u32 keys;
+ char *s;
+ int want_recovery;
+
+ /* we use bus I2C-0 for the on-board eeprom */
+ i2c_set_bus_num(0);
+
+ /* setup GPIO directions and initial values */
+ gpio_configure();
+
+ /*
+ * enforce the start of the recovery system when
+ * - the appropriate keys were pressed
+ * - "some" external software told us to
+ * - a previous installation was aborted or has failed
+ */
+ want_recovery = 0;
+ keys = gpio_querykbd();
+ if (gpio_diag)
+ printf("GPIO keyboard status [0x%02X]\n", keys);
+ if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
+ printf("detected recovery request (keyboard)\n");
+ want_recovery = 1;
+ }
+ s = getenv("want_recovery");
+ if ((s != NULL) && (*s != '\0')) {
+ printf("detected recovery request (environment)\n");
+ want_recovery = 1;
+ }
+ s = getenv("install_in_progress");
+ if ((s != NULL) && (*s != '\0')) {
+ printf("previous installation has not completed\n");
+ want_recovery = 1;
+ }
+ s = getenv("install_failed");
+ if ((s != NULL) && (*s != '\0')) {
+ printf("previous installation has failed\n");
+ want_recovery = 1;
+ }
+ if (want_recovery) {
+ printf("enforced start of the recovery system\n");
+ setenv("bootcmd", "run recovery");
+ }
+
+ /*
+ * boot the recovery system without waiting; boot the
+ * production system without waiting by default, only
+ * insert a pause (to provide a chance to get a prompt)
+ * when GPIO keys were pressed during power on
+ */
+ if (want_recovery)
+ setenv("bootdelay", "0");
+ else if (!keys)
+ setenv("bootdelay", "0");
+ else
+ setenv("bootdelay", "2");
+
+ /* get the ethernet MAC from I2C EEPROM */
+ mac_read_from_eeprom();
+
+ return 0;
+}
+
+/* setup specific IO pad configuration */
+static iopin_t ioregs_init[] = {
+ { /* LPC CS3 */
+ offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ { /* LPC CS1 */
+ offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ { /* LPC CS2 */
+ offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ { /* LPC CS4, CS5 */
+ offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ { /* SDHC CLK, CMD, D0, D1, D2, D3 */
+ offsetof(struct ioctrl512x, io_control_pata_ior), 6,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ { /* GPIO keyboard */
+ offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO DN1 PF, LCD power, DN2 PF */
+ offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO reset AS-i */
+ offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO reset safety */
+ offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO reset netX */
+ offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO ma2 en */
+ offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO SD CD, SD WP */
+ offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* FEC RX DV */
+ offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(2),
+ },
+ { /* GPIO AS-i prog, AS-i done, LCD backlight */
+ offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO AS-i wdg */
+ offsetof(struct ioctrl512x, io_control_pci_req2), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO safety wdg */
+ offsetof(struct ioctrl512x, io_control_pci_req1), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO netX wdg */
+ offsetof(struct ioctrl512x, io_control_pci_req0), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO IRQ powerfail */
+ offsetof(struct ioctrl512x, io_control_pci_inta), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO AS-i PWRD */
+ offsetof(struct ioctrl512x, io_control_pci_frame), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO LED0, LED1 */
+ offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
+ offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /* DIU clk */
+ offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(2),
+ },
+ { /* FEC TX ER, CRS */
+ offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ { /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
+ offsetof(struct ioctrl512x, io_control_irq0), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ { /*
+ * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
+ * rdx 3-0, mdio, rx clk
+ */
+ offsetof(struct ioctrl512x, io_control_psc0_0), 15,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ /* optional: make sure PSC3 remains the serial console */
+ { /* LPC CS6 */
+ offsetof(struct ioctrl512x, io_control_psc3_4), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ /* make sure PSC4 remains available for SPI,
+ *BUT* PSC4_1 is a GPIO kind of SS! */
+ { /* enforce drive strength on the SPI pin */
+ offsetof(struct ioctrl512x, io_control_psc4_0), 5,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ {
+ offsetof(struct ioctrl512x, io_control_psc4_1), 1,
+ IO_PIN_OVER_FMUX,
+ IO_PIN_FMUX(3),
+ },
+ /* optional: make sure PSC5 remains available for SPI */
+ { /* enforce drive strength on the SPI pin */
+ offsetof(struct ioctrl512x, io_control_psc5_0), 5,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(1),
+ },
+ { /* LPC TSIZ1 */
+ offsetof(struct ioctrl512x, io_control_psc6_0), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(1) | IO_PIN_DS(2),
+ },
+ { /* DIU hsync */
+ offsetof(struct ioctrl512x, io_control_psc6_1), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(1),
+ },
+ { /* DIU vsync */
+ offsetof(struct ioctrl512x, io_control_psc6_4), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(1),
+ },
+ { /* PSC7, part of DIU RGB */
+ offsetof(struct ioctrl512x, io_control_psc7_0), 2,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(1),
+ },
+ { /* PSC7, safety UART */
+ offsetof(struct ioctrl512x, io_control_psc7_2), 2,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(0) | IO_PIN_DS(1),
+ },
+ { /* DIU (part of) RGB[] */
+ offsetof(struct ioctrl512x, io_control_psc8_3), 16,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(1),
+ },
+ { /* DIU data enable */
+ offsetof(struct ioctrl512x, io_control_psc11_4), 1,
+ IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+ IO_PIN_FMUX(2) | IO_PIN_DS(1),
+ },
+ /* reduce LPB drive strength for improved EMI */
+ { /* LPC OE, LPC RW */
+ offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ { /* LPC AX03 through LPC AD00 */
+ offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ { /* LPC CS5 */
+ offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ { /* SDHC CLK */
+ offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+ { /* SDHC DATA */
+ offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
+ IO_PIN_OVER_DRVSTR,
+ IO_PIN_DS(2),
+ },
+};
+
+int checkboard(void)
+{
+ puts("Board: ifm AC14xx\n");
+
+ /* initialize function mux & slew rate IO inter alia on IO Pins */
+ iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/ifm/o2dnt2/Kconfig b/board/ifm/o2dnt2/Kconfig
new file mode 100644
index 0000000..e9d32dd
--- /dev/null
+++ b/board/ifm/o2dnt2/Kconfig
@@ -0,0 +1,77 @@
+if TARGET_O2D
+
+config SYS_BOARD
+ default "o2dnt2"
+
+config SYS_VENDOR
+ default "ifm"
+
+config SYS_CONFIG_NAME
+ default "o2d"
+
+endif
+
+if TARGET_O2D300
+
+config SYS_BOARD
+ default "o2dnt2"
+
+config SYS_VENDOR
+ default "ifm"
+
+config SYS_CONFIG_NAME
+ default "o2d300"
+
+endif
+
+if TARGET_O2DNT2
+
+config SYS_BOARD
+ default "o2dnt2"
+
+config SYS_VENDOR
+ default "ifm"
+
+config SYS_CONFIG_NAME
+ default "o2dnt2"
+
+endif
+
+if TARGET_O2I
+
+config SYS_BOARD
+ default "o2dnt2"
+
+config SYS_VENDOR
+ default "ifm"
+
+config SYS_CONFIG_NAME
+ default "o2i"
+
+endif
+
+if TARGET_O2MNT
+
+config SYS_BOARD
+ default "o2dnt2"
+
+config SYS_VENDOR
+ default "ifm"
+
+config SYS_CONFIG_NAME
+ default "o2mnt"
+
+endif
+
+if TARGET_O3DNT
+
+config SYS_BOARD
+ default "o2dnt2"
+
+config SYS_VENDOR
+ default "ifm"
+
+config SYS_CONFIG_NAME
+ default "o3dnt"
+
+endif
diff --git a/board/ifm/o2dnt2/MAINTAINERS b/board/ifm/o2dnt2/MAINTAINERS
new file mode 100644
index 0000000..002f89e
--- /dev/null
+++ b/board/ifm/o2dnt2/MAINTAINERS
@@ -0,0 +1,20 @@
+O2DNT2 BOARD
+M: Anatolij Gustschin <agust@denx.de>
+S: Maintained
+F: board/ifm/o2dnt2/
+F: include/configs/o2d.h
+F: configs/O2D_defconfig
+F: include/configs/o2d300.h
+F: configs/O2D300_defconfig
+F: include/configs/o2dnt2.h
+F: configs/O2DNT2_defconfig
+F: configs/O2DNT2_RAMBOOT_defconfig
+F: include/configs/o2i.h
+F: configs/O2I_defconfig
+F: include/configs/o2mnt.h
+F: configs/O2MNT_defconfig
+F: configs/O2MNT_O2M110_defconfig
+F: configs/O2MNT_O2M112_defconfig
+F: configs/O2MNT_O2M113_defconfig
+F: include/configs/o3dnt.h
+F: configs/O3DNT_defconfig
diff --git a/board/ifm/o2dnt2/Makefile b/board/ifm/o2dnt2/Makefile
new file mode 100644
index 0000000..64d6ba8
--- /dev/null
+++ b/board/ifm/o2dnt2/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2005-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := o2dnt2.o
diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c
new file mode 100644
index 0000000..ca09767
--- /dev/null
+++ b/board/ifm/o2dnt2/o2dnt2.c
@@ -0,0 +1,386 @@
+/*
+ * Partially derived from board code for digsyMTC,
+ * (C) Copyright 2009
+ * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
+ *
+ * (C) Copyright 2012
+ * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <net.h>
+#include <pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
+
+enum ifm_sensor_type {
+ O2DNT = 0x00, /* !< O2DNT 32MB */
+ O2DNT2 = 0x01, /* !< O2DNT2 64MB */
+ O3DNT = 0x02, /* !< O3DNT 32MB */
+ O3DNT_MIN = 0x40, /* !< O3DNT Minerva 32MB */
+ UNKNOWN = 0xff, /* !< Unknow sensor */
+};
+
+static enum ifm_sensor_type gt_ifm_sensor_type;
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+ struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+ long control = SDRAM_CONTROL | hi_addr_bit;
+
+ /* unlock mode register */
+ out_be32(&sdram->ctrl, control | 0x80000000);
+
+ /* precharge all banks */
+ out_be32(&sdram->ctrl, control | 0x80000002);
+
+ /* auto refresh */
+ out_be32(&sdram->ctrl, control | 0x80000004);
+
+ /* set mode register */
+ out_be32(&sdram->mode, SDRAM_MODE);
+
+ /* normal operation */
+ out_be32(&sdram->ctrl, control);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+phys_size_t initdram(int board_type)
+{
+ struct mpc5xxx_mmap_ctl *mmap_ctl =
+ (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+ struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ uint svr, pvr;
+
+ if (gt_ifm_sensor_type == O2DNT2) {
+ /* activate SDRAM CS1 */
+ setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000);
+ }
+
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */
+ out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */
+
+ /* setup config registers */
+ out_be32(&sdram->config1, SDRAM_CONFIG1);
+ out_be32(&sdram->config2, SDRAM_CONFIG2);
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ out_be32(&mmap_ctl->sdram0,
+ (0x13 + __builtin_ffs(dramsize >> 20) - 1));
+ } else {
+ out_be32(&mmap_ctl->sdram0, 0); /* disabled */
+ }
+
+ /* let SDRAM CS1 start right after CS0 */
+ out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */
+
+ /* find RAM size using SDRAM CS1 only */
+ if (!dramsize)
+ sdram_start(0);
+
+ test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
+ 0x80000000);
+ if (!dramsize) {
+ sdram_start(1);
+ test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
+ 0x80000000);
+ }
+
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize2 = test1;
+ } else {
+ dramsize2 = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20))
+ dramsize2 = 0;
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0) {
+ out_be32(&mmap_ctl->sdram1, (dramsize |
+ (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
+ } else {
+ out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF;
+ if (dramsize >= 0x13)
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ else
+ dramsize = 0;
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF;
+ if (dramsize2 >= 0x13)
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ else
+ dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
+ out_be32(&sdram->sdelay, 0x04);
+
+ return dramsize + dramsize2;
+}
+
+
+#define GPT_GPIO_IN 0x4
+
+int checkboard(void)
+{
+ struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
+ unsigned char board_config = 0;
+ int i;
+
+ /* switch gpt0 - gpt7 to input */
+ for (i = 0; i < 7; i++)
+ out_be32(&gpt[i].emsr, GPT_GPIO_IN);
+
+ /* get configuration byte on timer-port */
+ for (i = 0; i < 7; i++)
+ board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i);
+
+ puts("Board: ");
+
+ switch (board_config) {
+ case 0:
+ puts("O2DNT\n");
+ gt_ifm_sensor_type = O2DNT;
+ break;
+ case 1:
+ puts("O3DNT\n");
+ gt_ifm_sensor_type = O3DNT;
+ break;
+ case 2:
+ puts("O2DNT2\n");
+ gt_ifm_sensor_type = O2DNT2;
+ break;
+ case 64:
+ puts("O3DNT Minerva\n");
+ gt_ifm_sensor_type = O3DNT_MIN;
+ break;
+ default:
+ puts("Unknown\n");
+ gt_ifm_sensor_type = UNKNOWN;
+ break;
+ }
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
+
+ /*
+ * Now, when we are in RAM, enable flash write access for detection
+ * process. Note that CS_BOOT cannot be cleared when executing in flash.
+ */
+ clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */
+ /* disable CS_BOOT */
+ clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
+ /* enable CS0 */
+ setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
+
+ return 0;
+}
+
+#define MIIM_LXT971_LED_CFG_REG 0x14
+#define LXT971_LED_CFG_LINK_STATUS 0x4000
+#define LXT971_LED_CFG_RX_TX_ACTIVITY 0x0700
+#define LXT971_LED_CFG_LINK_ACTIVITY 0x00D0
+#define LXT971_LED_CFG_PULSE_STRETCH 0x0002
+/*
+ * Additional PHY intialization after reset in mpc5xxx_fec_init_phy()
+ */
+void reset_phy(void)
+{
+ /*
+ * Set LED configuration bits.
+ * It can't be done in misc_init_r() since FEC is not
+ * initialized at this time. Therefore we do it here.
+ */
+ miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG,
+ LXT971_LED_CFG_LINK_STATUS |
+ LXT971_LED_CFG_RX_TX_ACTIVITY |
+ LXT971_LED_CFG_LINK_ACTIVITY |
+ LXT971_LED_CFG_PULSE_STRETCH);
+}
+
+#if defined(CONFIG_POST)
+/*
+ * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
+ * is left open, no keypress is detected.
+ */
+int post_hotkeys_pressed(void)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
+
+ /*
+ * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
+ * CODEC or UART mode. Consumer IrDA should still be possible.
+ */
+ clrbits_be32(&gpio->port_config, 0x07000000);
+ setbits_be32(&gpio->port_config, 0x03000000);
+
+ /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
+ setbits_be32(&gpio->simple_gpioe, 0x20000000);
+
+ /* Configure GPIO_IRDA_1 as input */
+ clrbits_be32(&gpio->simple_ddr, 0x20000000);
+
+ return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1;
+}
+#endif
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+static void ft_adapt_flash_base(void *blob)
+{
+ flash_info_t *dev = &flash_info[0];
+ int off;
+ struct fdt_property *prop;
+ int len;
+ u32 *reg, *reg2;
+
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
+ if (off < 0) {
+ printf("Could not find fsl,mpc5200b-lpb node.\n");
+ return;
+ }
+
+ /* found compatible property */
+ prop = fdt_get_property_w(blob, off, "ranges", &len);
+ if (prop) {
+ reg = reg2 = (u32 *)&prop->data[0];
+
+ reg[2] = dev->start[0];
+ reg[3] = dev->size;
+ fdt_setprop(blob, off, "ranges", reg2, len);
+ } else
+ printf("Could not find ranges\n");
+}
+
+extern ulong flash_get_size(phys_addr_t base, int banknum);
+
+/* Update the flash baseaddr settings */
+int update_flash_size(int flash_size)
+{
+ struct mpc5xxx_mmap_ctl *mm =
+ (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
+ flash_info_t *dev;
+ int i;
+ int size = 0;
+ unsigned long base = 0x0;
+ u32 *cs_reg = (u32 *)&mm->cs0_start;
+
+ for (i = 0; i < 2; i++) {
+ dev = &flash_info[i];
+
+ if (dev->size) {
+ /* calculate new base addr for this chipselect */
+ base -= dev->size;
+ out_be32(cs_reg, START_REG(base));
+ cs_reg++;
+ out_be32(cs_reg, STOP_REG(base, dev->size));
+ cs_reg++;
+ /* recalculate the sectoraddr in the cfi driver */
+ size += flash_get_size(base, i);
+ }
+ }
+ flash_protect_default();
+ gd->bd->bi_flashstart = base;
+ return 0;
+}
+#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int phy_addr = CONFIG_PHY_ADDR;
+ char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
+
+ ft_cpu_setup(blob, bd);
+
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+ /* Update reg property in all nor flash nodes too */
+ fdt_fixup_nor_flash_size(blob);
+#endif
+ ft_adapt_flash_base(blob);
+#endif
+ /* fix up the phy address */
+ do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig
new file mode 100644
index 0000000..4c06d0c
--- /dev/null
+++ b/board/imgtec/malta/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MALTA
+
+config SYS_BOARD
+ default "malta"
+
+config SYS_VENDOR
+ default "imgtec"
+
+config SYS_CONFIG_NAME
+ default "malta"
+
+endif
diff --git a/board/imgtec/malta/MAINTAINERS b/board/imgtec/malta/MAINTAINERS
new file mode 100644
index 0000000..a0b3284
--- /dev/null
+++ b/board/imgtec/malta/MAINTAINERS
@@ -0,0 +1,7 @@
+MALTA BOARD
+M: Paul Burton <paul.burton@imgtec.com>
+S: Maintained
+F: board/imgtec/malta/
+F: include/configs/malta.h
+F: configs/malta_defconfig
+F: configs/maltael_defconfig
diff --git a/board/imgtec/malta/Makefile b/board/imgtec/malta/Makefile
new file mode 100644
index 0000000..19dd3a3
--- /dev/null
+++ b/board/imgtec/malta/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = malta.o
+obj-y += lowlevel_init.o
+obj-y += superio.o
diff --git a/board/imgtec/malta/flash-malta-boot.tcl b/board/imgtec/malta/flash-malta-boot.tcl
new file mode 100644
index 0000000..0eedf07
--- /dev/null
+++ b/board/imgtec/malta/flash-malta-boot.tcl
@@ -0,0 +1,40 @@
+#
+# Copyright (C) 2013 Imagination Technologies
+#
+# Programs a MIPS Malta boot flash with a flat binary image.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+proc flash-boot { binfile } {
+ puts "flash monitor binary $binfile"
+ config Coherent on
+ config CoherencyDuringLoad on
+
+ if {[endian]=="big"} {
+ puts "CPU in BE mode"
+ flash device sharp_16x32_be;
+ } else {
+ puts "CPU in LE mode"
+ flash device sharp_16x32;
+ }
+
+ flash clear all;
+ flash set 0xBE000000..0xBE0FFFFF
+ flash erase sector 0xbe000000;
+ flash erase sector 0xbe020000;
+ flash erase sector 0xbe040000;
+ flash erase sector 0xbe060000;
+ flash erase sector 0xbe080000;
+ flash erase sector 0xbe0a0000;
+ flash erase sector 0xbe0c0000;
+ flash erase sector 0xbe0e0000;
+ puts "finished erasing boot flash";
+
+ puts "programming flash, please be patient"
+ load bin 0xbe000000 $binfile size4
+
+ flash clear all
+ config CoherencyDuringLoad off
+ puts "finished programming boot flash";
+}
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
new file mode 100644
index 0000000..ae09c27
--- /dev/null
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <gt64120.h>
+#include <msc01.h>
+#include <pci.h>
+
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <asm/malta.h>
+#include <asm/mipsregs.h>
+
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CPU_TO_GT32(_x) ((_x))
+#else
+#define CPU_TO_GT32(_x) ( \
+ (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \
+ (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
+#endif
+
+ .text
+ .set noreorder
+ .set mips32
+
+ .globl lowlevel_init
+lowlevel_init:
+ /* disable any L2 cache for now */
+ sync
+ mfc0 t0, CP0_CONFIG, 2
+ ori t0, t0, 0x1 << 12
+ mtc0 t0, CP0_CONFIG, 2
+
+ /* detect the core card */
+ li t0, KSEG1ADDR(MALTA_REVISION)
+ lw t0, 0(t0)
+ srl t0, t0, MALTA_REVISION_CORID_SHF
+ andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
+ MALTA_REVISION_CORID_SHF)
+
+ /* core cards using the gt64120 system controller */
+ li t1, MALTA_REVISION_CORID_CORE_LV
+ beq t0, t1, _gt64120
+
+ /* core cards using the MSC01 system controller */
+ li t1, MALTA_REVISION_CORID_CORE_FPGA6
+ beq t0, t1, _msc01
+ nop
+
+ /* unknown system controller */
+ b .
+ nop
+
+ /*
+ * Load BAR registers of GT64120 as done by YAMON
+ *
+ * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
+ * to the barebox mailing list.
+ * The subject of the original patch:
+ * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
+ * URL:
+ * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
+ *
+ * based on write_bootloader() in qemu.git/hw/mips_malta.c
+ * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
+ */
+_gt64120:
+ /* move GT64120 registers from 0x14000000 to 0x1be00000 */
+ li t1, KSEG1ADDR(GT_DEF_BASE)
+ li t0, CPU_TO_GT32(0xdf000000)
+ sw t0, GT_ISD_OFS(t1)
+
+ /* setup MEM-to-PCI0 mapping */
+ li t1, KSEG1ADDR(MALTA_GT_BASE)
+
+ /* setup PCI0 io window to 0x18000000-0x181fffff */
+ li t0, CPU_TO_GT32(0xc0000000)
+ sw t0, GT_PCI0IOLD_OFS(t1)
+ li t0, CPU_TO_GT32(0x40000000)
+ sw t0, GT_PCI0IOHD_OFS(t1)
+
+ /* setup PCI0 mem windows */
+ li t0, CPU_TO_GT32(0x80000000)
+ sw t0, GT_PCI0M0LD_OFS(t1)
+ li t0, CPU_TO_GT32(0x3f000000)
+ sw t0, GT_PCI0M0HD_OFS(t1)
+
+ li t0, CPU_TO_GT32(0xc1000000)
+ sw t0, GT_PCI0M1LD_OFS(t1)
+ li t0, CPU_TO_GT32(0x5e000000)
+ sw t0, GT_PCI0M1HD_OFS(t1)
+
+ jr ra
+ nop
+
+ /*
+ *
+ */
+_msc01:
+ /* setup peripheral bus controller clock divide */
+ li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
+ li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
+ sw t1, MSC01_PBC_CLKCFG_OFS(t0)
+
+ /* tweak peripheral bus controller timings */
+ li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
+ (0x1 << MSC01_PBC_CS0TIM_CAT_SHF)
+ sw t1, MSC01_PBC_CS0TIM_OFS(t0)
+ li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
+ (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \
+ (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \
+ (0x2 << MSC01_PBC_CS0RW_WAT_SHF)
+ sw t1, MSC01_PBC_CS0RW_OFS(t0)
+ lw t1, MSC01_PBC_CS0CFG_OFS(t0)
+ li t2, MSC01_PBC_CS0CFG_DTYP_MSK
+ and t1, t2
+ ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \
+ (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \
+ (0x10 << MSC01_PBC_CS0CFG_WS_SHF)
+ sw t1, MSC01_PBC_CS0CFG_OFS(t0)
+
+ /* setup basic address decode */
+ li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
+ li t1, 0x0
+ li t2, -CONFIG_SYS_MEM_SIZE
+ sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
+ sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
+ sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
+ sw t2, MSC01_BIU_MCMSK2L_OFS(t0)
+
+ /* initialise IP1 - unused */
+ li t1, MALTA_MSC01_IP1_BASE
+ li t2, -MALTA_MSC01_IP1_SIZE
+ sw t1, MSC01_BIU_IP1BAS1L_OFS(t0)
+ sw t2, MSC01_BIU_IP1MSK1L_OFS(t0)
+ sw t1, MSC01_BIU_IP1BAS2L_OFS(t0)
+ sw t2, MSC01_BIU_IP1MSK2L_OFS(t0)
+
+ /* initialise IP2 - PCI */
+ li t1, MALTA_MSC01_IP2_BASE1
+ li t2, -MALTA_MSC01_IP2_SIZE1
+ sw t1, MSC01_BIU_IP2BAS1L_OFS(t0)
+ sw t2, MSC01_BIU_IP2MSK1L_OFS(t0)
+ li t1, MALTA_MSC01_IP2_BASE2
+ li t2, -MALTA_MSC01_IP2_SIZE2
+ sw t1, MSC01_BIU_IP2BAS2L_OFS(t0)
+ sw t2, MSC01_BIU_IP2MSK2L_OFS(t0)
+
+ /* initialise IP3 - peripheral bus controller */
+ li t1, MALTA_MSC01_IP3_BASE
+ li t2, -MALTA_MSC01_IP3_SIZE
+ sw t1, MSC01_BIU_IP3BAS1L_OFS(t0)
+ sw t2, MSC01_BIU_IP3MSK1L_OFS(t0)
+ sw t1, MSC01_BIU_IP3BAS2L_OFS(t0)
+ sw t2, MSC01_BIU_IP3MSK2L_OFS(t0)
+
+ /* setup PCI memory */
+ li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
+ li t1, MALTA_MSC01_PCIMEM_BASE
+ li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
+ li t3, MALTA_MSC01_PCIMEM_MAP
+ sw t1, MSC01_PCI_SC2PMBASL_OFS(t0)
+ sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0)
+ sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0)
+
+ /* setup PCI I/O */
+ li t1, MALTA_MSC01_PCIIO_BASE
+ li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK
+ li t3, MALTA_MSC01_PCIIO_MAP
+ sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
+ sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0)
+ sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
+
+ /* setup PCI_BAR0 memory window */
+ li t1, -CONFIG_SYS_MEM_SIZE
+ sw t1, MSC01_PCI_BAR0_OFS(t0)
+
+ /* setup PCI to SysCon/CPU translation */
+ sw t1, MSC01_PCI_P2SCMSKL_OFS(t0)
+ sw zero, MSC01_PCI_P2SCMAPL_OFS(t0)
+
+ /* setup PCI vendor & device IDs */
+ li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
+ (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF)
+ sw t1, MSC01_PCI_HEAD0_OFS(t0)
+
+ /* setup PCI subsystem vendor & device IDs */
+ sw t1, MSC01_PCI_HEAD11_OFS(t0)
+
+ /* setup PCI class, revision */
+ li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
+ (0x1 << MSC01_PCI_HEAD2_REV_SHF)
+ sw t1, MSC01_PCI_HEAD2_OFS(t0)
+
+ /* ensure a sane setup */
+ sw zero, MSC01_PCI_HEAD3_OFS(t0)
+ sw zero, MSC01_PCI_HEAD4_OFS(t0)
+ sw zero, MSC01_PCI_HEAD5_OFS(t0)
+ sw zero, MSC01_PCI_HEAD6_OFS(t0)
+ sw zero, MSC01_PCI_HEAD7_OFS(t0)
+ sw zero, MSC01_PCI_HEAD8_OFS(t0)
+ sw zero, MSC01_PCI_HEAD9_OFS(t0)
+ sw zero, MSC01_PCI_HEAD10_OFS(t0)
+ sw zero, MSC01_PCI_HEAD12_OFS(t0)
+ sw zero, MSC01_PCI_HEAD13_OFS(t0)
+ sw zero, MSC01_PCI_HEAD14_OFS(t0)
+ sw zero, MSC01_PCI_HEAD15_OFS(t0)
+
+ /* setup PCI command register */
+ li t1, (PCI_COMMAND_FAST_BACK | \
+ PCI_COMMAND_SERR | \
+ PCI_COMMAND_PARITY | \
+ PCI_COMMAND_MASTER | \
+ PCI_COMMAND_MEMORY)
+ sw t1, MSC01_PCI_HEAD1_OFS(t0)
+
+ /* setup PCI byte swapping */
+#ifdef CONFIG_SYS_BIG_ENDIAN
+ li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
+ (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF)
+ sw t1, MSC01_PCI_SWAP_OFS(t0)
+#else
+ sw zero, MSC01_PCI_SWAP_OFS(t0)
+#endif
+
+ /* enable PCI host configuration cycles */
+ lw t1, MSC01_PCI_CFG_OFS(t0)
+ li t2, MSC01_PCI_CFG_RA_MSK | \
+ MSC01_PCI_CFG_G_MSK | \
+ MSC01_PCI_CFG_EN_MSK
+ or t1, t1, t2
+ sw t1, MSC01_PCI_CFG_OFS(t0)
+
+ jr ra
+ nop
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
new file mode 100644
index 0000000..78c4bd4
--- /dev/null
+++ b/board/imgtec/malta/malta.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <pci.h>
+#include <pci_gt64120.h>
+#include <pci_msc01.h>
+#include <rtc.h>
+#include <serial.h>
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/malta.h>
+
+#include "superio.h"
+
+enum core_card {
+ CORE_UNKNOWN,
+ CORE_LV,
+ CORE_FPGA6,
+};
+
+enum sys_con {
+ SYSCON_UNKNOWN,
+ SYSCON_GT64120,
+ SYSCON_MSC01,
+};
+
+static void malta_lcd_puts(const char *str)
+{
+ int i;
+ void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
+
+ /* print up to 8 characters of the string */
+ for (i = 0; i < min((int)strlen(str), 8); i++) {
+ __raw_writel(str[i], reg);
+ reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
+ }
+
+ /* fill the rest of the display with spaces */
+ for (; i < 8; i++) {
+ __raw_writel(' ', reg);
+ reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
+ }
+}
+
+static enum core_card malta_core_card(void)
+{
+ u32 corid, rev;
+
+ rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
+ corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
+
+ switch (corid) {
+ case MALTA_REVISION_CORID_CORE_LV:
+ return CORE_LV;
+
+ case MALTA_REVISION_CORID_CORE_FPGA6:
+ return CORE_FPGA6;
+
+ default:
+ return CORE_UNKNOWN;
+ }
+}
+
+static enum sys_con malta_sys_con(void)
+{
+ switch (malta_core_card()) {
+ case CORE_LV:
+ return SYSCON_GT64120;
+
+ case CORE_FPGA6:
+ return SYSCON_MSC01;
+
+ default:
+ return SYSCON_UNKNOWN;
+ }
+}
+
+phys_size_t initdram(int board_type)
+{
+ return CONFIG_SYS_MEM_SIZE;
+}
+
+int checkboard(void)
+{
+ enum core_card core;
+
+ malta_lcd_puts("U-boot");
+ puts("Board: MIPS Malta");
+
+ core = malta_core_card();
+ switch (core) {
+ case CORE_LV:
+ puts(" CoreLV");
+ break;
+
+ case CORE_FPGA6:
+ puts(" CoreFPGA6");
+ break;
+
+ default:
+ puts(" CoreUnknown");
+ }
+
+ putc('\n');
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+void _machine_restart(void)
+{
+ void __iomem *reset_base;
+
+ reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
+ __raw_writel(GORESET, reset_base);
+}
+
+int board_early_init_f(void)
+{
+ void *io_base;
+
+ /* choose correct PCI I/O base */
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
+ break;
+
+ case SYSCON_MSC01:
+ io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
+ break;
+
+ default:
+ return -1;
+ }
+
+ /* setup FDC37M817 super I/O controller */
+ malta_superio_init(io_base);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ rtc_reset();
+
+ return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ return &eserial1_device;
+
+ default:
+ case SYSCON_MSC01:
+ return &eserial2_device;
+ }
+}
+
+void pci_init_board(void)
+{
+ pci_dev_t bdf;
+ u32 val32;
+ u8 val8;
+
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE));
+
+ gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
+ 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+ 0x10000000, 0x10000000, 128 * 1024 * 1024,
+ 0x00000000, 0x00000000, 0x20000);
+ break;
+
+ default:
+ case SYSCON_MSC01:
+ set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE));
+
+ msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
+ 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+ MALTA_MSC01_PCIMEM_MAP,
+ CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
+ MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
+ 0x00000000, MALTA_MSC01_PCIIO_SIZE);
+ break;
+ }
+
+ bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB_0, 0);
+ if (bdf == -1)
+ panic("Failed to find PIIX4 PCI bridge\n");
+
+ /* setup PCI interrupt routing */
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
+
+ /* mux SERIRQ onto SERIRQ pin */
+ pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
+ val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
+ pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
+
+ /* enable SERIRQ - Linux currently depends upon this */
+ pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
+ val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
+}
diff --git a/board/imgtec/malta/superio.c b/board/imgtec/malta/superio.c
new file mode 100644
index 0000000..eaa14df
--- /dev/null
+++ b/board/imgtec/malta/superio.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * Setup code for the FDC37M817 super I/O controller
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define SIO_CONF_PORT 0x3f0
+#define SIO_DATA_PORT 0x3f1
+
+enum sio_conf_key {
+ SIOCONF_DEVNUM = 0x07,
+ SIOCONF_ACTIVATE = 0x30,
+ SIOCONF_ENTER_SETUP = 0x55,
+ SIOCONF_BASE_HIGH = 0x60,
+ SIOCONF_BASE_LOW = 0x61,
+ SIOCONF_PRIMARY_INT = 0x70,
+ SIOCONF_EXIT_SETUP = 0xaa,
+ SIOCONF_MODE = 0xf0,
+};
+
+static struct {
+ u8 key;
+ u8 data;
+} sio_config[] = {
+ /* tty0 */
+ { SIOCONF_DEVNUM, 0x04 },
+ { SIOCONF_BASE_HIGH, 0x03 },
+ { SIOCONF_BASE_LOW, 0xf8 },
+ { SIOCONF_MODE, 0x02 },
+ { SIOCONF_PRIMARY_INT, 0x04 },
+ { SIOCONF_ACTIVATE, 0x01 },
+
+ /* tty1 */
+ { SIOCONF_DEVNUM, 0x05 },
+ { SIOCONF_BASE_HIGH, 0x02 },
+ { SIOCONF_BASE_LOW, 0xf8 },
+ { SIOCONF_MODE, 0x02 },
+ { SIOCONF_PRIMARY_INT, 0x03 },
+ { SIOCONF_ACTIVATE, 0x01 },
+};
+
+void malta_superio_init(void *io_base)
+{
+ unsigned i;
+
+ /* enter config state */
+ writeb(SIOCONF_ENTER_SETUP, io_base + SIO_CONF_PORT);
+
+ /* configure peripherals */
+ for (i = 0; i < ARRAY_SIZE(sio_config); i++) {
+ writeb(sio_config[i].key, io_base + SIO_CONF_PORT);
+ writeb(sio_config[i].data, io_base + SIO_DATA_PORT);
+ }
+
+ /* exit config state */
+ writeb(SIOCONF_EXIT_SETUP, io_base + SIO_CONF_PORT);
+}
diff --git a/board/imgtec/malta/superio.h b/board/imgtec/malta/superio.h
new file mode 100644
index 0000000..1450da5
--- /dev/null
+++ b/board/imgtec/malta/superio.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * Setup code for the FDC37M817 super I/O controller
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BOARD_MALTA_SUPERIO_H__
+#define __BOARD_MALTA_SUPERIO_H__
+
+extern void malta_superio_init(void *io_base);
+
+#endif /* __BOARD_MALTA_SUPERIO_H__ */
diff --git a/board/imx31_phycore/Kconfig b/board/imx31_phycore/Kconfig
new file mode 100644
index 0000000..d3d2025
--- /dev/null
+++ b/board/imx31_phycore/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX31_PHYCORE
+
+config SYS_BOARD
+ default "imx31_phycore"
+
+config SYS_SOC
+ default "mx31"
+
+config SYS_CONFIG_NAME
+ default "imx31_phycore"
+
+endif
diff --git a/board/imx31_phycore/MAINTAINERS b/board/imx31_phycore/MAINTAINERS
new file mode 100644
index 0000000..41f6cae
--- /dev/null
+++ b/board/imx31_phycore/MAINTAINERS
@@ -0,0 +1,11 @@
+IMX31_PHYCORE BOARD
+#M: -
+S: Maintained
+F: board/imx31_phycore/
+F: include/configs/imx31_phycore.h
+F: configs/imx31_phycore_defconfig
+
+IMX31_PHYCORE_EET BOARD
+#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+S: Orphan (since 2013-09)
+F: configs/imx31_phycore_eet_defconfig
diff --git a/board/imx31_phycore/Makefile b/board/imx31_phycore/Makefile
new file mode 100644
index 0000000..e781c13
--- /dev/null
+++ b/board/imx31_phycore/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := imx31_phycore.o
+obj-y += lowlevel_init.o
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
new file mode 100644
index 0000000..3f45e4e
--- /dev/null
+++ b/board/imx31_phycore/imx31_phycore.c
@@ -0,0 +1,153 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <s6e63d6.h>
+#include <netdev.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+int board_init(void)
+{
+
+ gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */
+ gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /* CS0: Nor Flash */
+ static const struct mxc_weimcs cs0 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
+ };
+
+ /* CS1: Network Controller */
+ static const struct mxc_weimcs cs1 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
+ };
+
+ /* CS4: SRAM */
+ static const struct mxc_weimcs cs4 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
+ };
+
+ mxc_setup_weimcs(0, &cs0);
+ mxc_setup_weimcs(1, &cs1);
+ mxc_setup_weimcs(4, &cs4);
+
+ /* setup pins for UART1 */
+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+ mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+ /* setup pins for I2C2 (for EEPROM, RTC) */
+ mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
+ mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_S6E63D6
+ struct s6e63d6 data = {
+ /*
+ * See comment in mxc_spi.c::decode_cs() for .cs field format.
+ * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
+ * 2 of the SPI controller #1, since it is unused.
+ */
+ .cs = 2 | (57 << 8),
+ .bus = 0,
+ .id = 0,
+ };
+ int ret;
+
+ /* SPI1 */
+ mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
+ mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
+ mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
+ mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
+ mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
+ mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
+ mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
+
+ /* start SPI1 clock */
+ __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
+
+ /* GPIO 57 */
+ /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
+ mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
+
+ /* SPI1 CS2 is free */
+ ret = s6e63d6_init(&data);
+ if (ret)
+ return ret;
+
+ /*
+ * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
+ * OLED display connected to a S6E63D6 SPI display controller in the
+ * 18 bit RGB mode
+ */
+ s6e63d6_index(&data, 2);
+ s6e63d6_param(&data, 0x0182);
+ s6e63d6_index(&data, 3);
+ s6e63d6_param(&data, 0x8130);
+ s6e63d6_index(&data, 0x10);
+ s6e63d6_param(&data, 0x0000);
+ s6e63d6_index(&data, 5);
+ s6e63d6_param(&data, 0x0001);
+ s6e63d6_index(&data, 0x22);
+#endif
+ return 0;
+}
+#endif
+
+int checkboard (void)
+{
+ printf("Board: Phytec phyCore i.MX31\n");
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S
new file mode 100644
index 0000000..6ea3878
--- /dev/null
+++ b/board/imx31_phycore/lowlevel_init.S
@@ -0,0 +1,88 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/imx-regs.h>
+
+.macro REG reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ strb r3, [r2]
+.endm
+
+.macro DELAY loops
+ ldr r2, =\loops
+1:
+ subs r2, r2, #1
+ nop
+ bcs 1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+
+ REG IPU_CONF, IPU_CONF_DI_EN
+ REG CCM_CCMR, 0x074B0BF5
+
+ DELAY 0x40000
+
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+ REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
+
+ REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
+
+ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1)
+
+ REG 0x43FAC26C, 0 /* SDCLK */
+ REG 0x43FAC270, 0 /* CAS */
+ REG 0x43FAC274, 0 /* RAS */
+ REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */
+ REG 0x43FAC284, 0 /* DQM3 */
+ REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+ REG 0x43FAC28C, 0
+ REG 0x43FAC290, 0
+ REG 0x43FAC294, 0
+ REG 0x43FAC298, 0
+ REG 0x43FAC29C, 0
+ REG 0x43FAC2A0, 0
+ REG 0x43FAC2A4, 0
+ REG 0x43FAC2A8, 0
+ REG 0x43FAC2AC, 0
+ REG 0x43FAC2B0, 0
+ REG 0x43FAC2B4, 0
+ REG 0x43FAC2B8, 0
+ REG 0x43FAC2BC, 0
+ REG 0x43FAC2C0, 0
+ REG 0x43FAC2C4, 0
+ REG 0x43FAC2C8, 0
+ REG 0x43FAC2CC, 0
+ REG 0x43FAC2D0, 0
+ REG 0x43FAC2D4, 0
+ REG 0x43FAC2D8, 0
+ REG 0x43FAC2DC, 0
+ REG 0xB8001010, 0x00000004
+ REG 0xB8001004, 0x006ac73a
+ REG 0xB8001000, 0x92100000
+ REG 0x80000f00, 0x12344321
+ REG 0xB8001000, 0xa2100000
+ REG 0x80000000, 0x12344321
+ REG 0x80000000, 0x12344321
+ REG 0xB8001000, 0xb2100000
+ REG8 0x80000033, 0xda
+ REG8 0x81000000, 0xff
+ REG 0xB8001000, 0x82226080
+ REG 0x80000000, 0xDEADBEEF
+ REG 0xB8001010, 0x0000000c
+
+ mov pc, lr
diff --git a/board/in-circuit/grasshopper/Kconfig b/board/in-circuit/grasshopper/Kconfig
new file mode 100644
index 0000000..30e3855
--- /dev/null
+++ b/board/in-circuit/grasshopper/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_GRASSHOPPER
+
+config SYS_BOARD
+ default "grasshopper"
+
+config SYS_VENDOR
+ default "in-circuit"
+
+config SYS_SOC
+ default "at32ap700x"
+
+config SYS_CONFIG_NAME
+ default "grasshopper"
+
+endif
diff --git a/board/in-circuit/grasshopper/MAINTAINERS b/board/in-circuit/grasshopper/MAINTAINERS
new file mode 100644
index 0000000..db8bd0a
--- /dev/null
+++ b/board/in-circuit/grasshopper/MAINTAINERS
@@ -0,0 +1,6 @@
+GRASSHOPPER BOARD
+M: Andreas Bießmann <andreas.devel@googlemail.com>
+S: Maintained
+F: board/in-circuit/grasshopper/
+F: include/configs/grasshopper.h
+F: configs/grasshopper_defconfig
diff --git a/board/in-circuit/grasshopper/Makefile b/board/in-circuit/grasshopper/Makefile
new file mode 100644
index 0000000..0457635
--- /dev/null
+++ b/board/in-circuit/grasshopper/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2011
+# Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += grasshopper.o
diff --git a/board/in-circuit/grasshopper/grasshopper.c b/board/in-circuit/grasshopper/grasshopper.c
new file mode 100644
index 0000000..340b713
--- /dev/null
+++ b/board/in-circuit/grasshopper/grasshopper.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2011
+ * Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
+static const struct sdram_config sdram_config = {
+ /* Dual MT48LC16M16A2-7E (or equal) */
+ .data_bits = SDRAM_DATA_32BIT,
+ .row_bits = 13,
+ .col_bits = 9,
+ .bank_bits = 2,
+ .cas = 2,
+ .twr = 2,
+ .trc = 7,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 4,
+ .txsr = 7,
+ /* 7.81 us */
+ .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+int board_early_init_f(void)
+{
+ /* Enable SDRAM in the EBI mux */
+ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+ portmux_enable_ebi(SDRAM_DATA_32BIT, 23, 0, PORTMUX_DRIVE_HIGH);
+ portmux_enable_usart0(PORTMUX_DRIVE_MIN);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+#if defined(CONFIG_MACB)
+ /* set PHY reset and pwrdown to low */
+ portmux_select_gpio(PORTMUX_PORT_B, (1 << 29) | (1 << 30),
+ PORTMUX_DIR_OUTPUT | PORTMUX_INIT_LOW);
+ udelay(100);
+ /* release PHYs reset */
+ gpio_set_value(GPIO_PIN_PB(29), 1);
+
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
+#endif
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ unsigned long expected_size;
+ unsigned long actual_size;
+ void *sdram_base;
+
+ sdram_base = uncached(EBI_SDRAM_BASE);
+
+ expected_size = sdram_init(sdram_base, &sdram_config);
+ actual_size = get_ram_size(sdram_base, expected_size);
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return actual_size;
+}
+
+int board_early_init_r(void)
+{
+ gd->bd->bi_phy_id[0] = 0x00;
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+ macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+ return 0;
+}
+#endif
+/* vim: set noet ts=8: */
diff --git a/board/inka4x0/Kconfig b/board/inka4x0/Kconfig
new file mode 100644
index 0000000..94a41f0
--- /dev/null
+++ b/board/inka4x0/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_INKA4X0
+
+config SYS_BOARD
+ default "inka4x0"
+
+config SYS_CONFIG_NAME
+ default "inka4x0"
+
+endif
diff --git a/board/inka4x0/MAINTAINERS b/board/inka4x0/MAINTAINERS
new file mode 100644
index 0000000..246b2d4
--- /dev/null
+++ b/board/inka4x0/MAINTAINERS
@@ -0,0 +1,6 @@
+INKA4X0 BOARD
+M: Detlev Zundel <dzu@denx.de>
+S: Maintained
+F: board/inka4x0/
+F: include/configs/inka4x0.h
+F: configs/inka4x0_defconfig
diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile
new file mode 100644
index 0000000..c9a3540
--- /dev/null
+++ b/board/inka4x0/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2009
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := inka4x0.o inkadiag.o
diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c
new file mode 100644
index 0000000..0a32f0e
--- /dev/null
+++ b/board/inka4x0/inka4x0.c
@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2008-2009
+ * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
+ *
+ * (C) Copyright 2009
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#if defined(CONFIG_DDR_MT46V16M16)
+#include "mt46v16m16-75.h"
+#elif defined(CONFIG_SDR_MT48LC16M16A2)
+#include "mt48lc16m16a2-75.h"
+#elif defined(CONFIG_DDR_MT46V32M16)
+#include "mt46v32m16.h"
+#elif defined(CONFIG_DDR_HYB25D512160BF)
+#include "hyb25d512160bf.h"
+#elif defined(CONFIG_DDR_K4H511638C)
+#include "k4h511638c.h"
+#else
+#error "INKA4x0 SDRAM: invalid chip type specified!"
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+ volatile struct mpc5xxx_sdram *sdram =
+ (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
+
+ /* precharge all banks */
+ out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ out_be32(&sdram->mode, SDRAM_EMODE);
+
+ /* set mode register: reset DLL */
+ out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
+#endif
+
+ /* precharge all banks */
+ out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+ /* auto refresh */
+ out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
+
+ /* set mode register */
+ out_be32(&sdram->mode, SDRAM_MODE);
+
+ /* normal operation */
+ out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+ volatile struct mpc5xxx_mmap_ctl *mm =
+ (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
+ volatile struct mpc5xxx_cdm *cdm =
+ (struct mpc5xxx_cdm *) MPC5XXX_CDM;
+ volatile struct mpc5xxx_sdram *sdram =
+ (struct mpc5xxx_sdram *) MPC5XXX_SDRAM;
+ ulong dramsize = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+ long test1, test2;
+
+ /* setup SDRAM chip selects */
+ out_be32(&mm->sdram0, 0x0000001c); /* 512MB at 0x0 */
+ out_be32(&mm->sdram1, 0x40000000); /* disabled */
+
+ /* setup config registers */
+ out_be32(&sdram->config1, SDRAM_CONFIG1);
+ out_be32(&sdram->config2, SDRAM_CONFIG2);
+
+#if SDRAM_DDR
+ /* set tap delay */
+ out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ out_be32(&mm->sdram0, 0x13 +
+ __builtin_ffs(dramsize >> 20) - 1);
+ } else {
+ out_be32(&mm->sdram0, 0); /* disabled */
+ }
+
+ out_be32(&mm->sdram1, dramsize); /* disabled */
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = in_be32(&mm->sdram0) & 0xFF;
+ if (dramsize >= 0x13) {
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ } else {
+ dramsize = 0;
+ }
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ return dramsize;
+}
+
+int checkboard (void)
+{
+ puts ("Board: INKA 4X0\n");
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
+
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT (CS0) cannot be cleared when
+ * executing in flash.
+ */
+ clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
+}
+
+int misc_init_f (void)
+{
+ volatile struct mpc5xxx_gpio *gpio =
+ (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
+ volatile struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+ volatile struct mpc5xxx_gpt *gpt;
+ char tmp[10];
+ int i, br;
+
+ i = getenv_f("brightness", tmp, sizeof(tmp));
+ br = (i > 0)
+ ? (int) simple_strtoul (tmp, NULL, 10)
+ : CONFIG_SYS_BRIGHTNESS;
+ if (br > 255)
+ br = 255;
+
+ /* Initialize GPIO output pins.
+ */
+ /* Configure GPT as GPIO output (and set them as they control low-active LEDs */
+ for (i = 0; i <= 5; i++) {
+ gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
+ out_be32(&gpt->emsr, 0x34);
+ }
+
+ /* Configure GPT7 as PWM timer, 1kHz, no ints. */
+ gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
+ out_be32(&gpt->emsr, 0); /* Disable */
+ out_be32(&gpt->cir, 0x020000fe);
+ out_be32(&gpt->pwmcr, (br << 16));
+ out_be32(&gpt->emsr, 0x3); /* Enable PWM mode and start */
+
+ /* Configure PSC3_6,7 as GPIO output */
+ setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
+ MPC5XXX_GPIO_SIMPLE_PSC3_7);
+ setbits_be32(&gpio->simple_ddr, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
+ MPC5XXX_GPIO_SIMPLE_PSC3_7);
+
+ /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
+ setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_6 |
+ MPC5XXX_GPIO_WKUP_7 |
+ MPC5XXX_GPIO_WKUP_PSC3_9);
+ setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_6 |
+ MPC5XXX_GPIO_WKUP_7 |
+ MPC5XXX_GPIO_WKUP_PSC3_9);
+
+ /* Set LR mirror bit because it is low-active */
+ setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_7);
+
+ /* Reset Coral-P graphics controller */
+ setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC3_9);
+
+ /* Enable display backlight */
+ clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
+ setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
+ setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_8);
+ setbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_8);
+
+ /*
+ * Configure three wire serial interface to RTC (PSC1_4,
+ * PSC2_4, PSC3_4, PSC3_5)
+ */
+ setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_PSC1_4 |
+ MPC5XXX_GPIO_WKUP_PSC2_4);
+ setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_PSC1_4 |
+ MPC5XXX_GPIO_WKUP_PSC2_4);
+ clrbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4);
+ clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
+ MPC5XXX_GPIO_SINT_PSC3_5);
+ setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
+ MPC5XXX_GPIO_SINT_PSC3_5);
+ setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_5);
+ clrbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_5);
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
diff --git a/board/inka4x0/inkadiag.c b/board/inka4x0/inkadiag.c
new file mode 100644
index 0000000..0bd12ec
--- /dev/null
+++ b/board/inka4x0/inkadiag.c
@@ -0,0 +1,464 @@
+/*
+ * (C) Copyright 2008, 2009 Andreas Pfefferle,
+ * DENX Software Engineering, ap@denx.de.
+ * (C) Copyright 2009 Detlev Zundel,
+ * DENX Software Engineering, dzu@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <config.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#include <command.h>
+
+/* This is needed for the includes in ns16550.h */
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#include <ns16550.h>
+
+#define GPIO_BASE ((u_char *)CONFIG_SYS_CS3_START)
+
+#define DIGIN_TOUCHSCR_MASK 0x00003000 /* Inputs 12-13 */
+#define DIGIN_KEYB_MASK 0x00010000 /* Input 16 */
+
+#define DIGIN_DRAWER_SW1 0x00400000 /* Input 22 */
+#define DIGIN_DRAWER_SW2 0x00800000 /* Input 23 */
+
+#define DIGIO_LED0 0x00000001 /* Output 0 */
+#define DIGIO_LED1 0x00000002 /* Output 1 */
+#define DIGIO_LED2 0x00000004 /* Output 2 */
+#define DIGIO_LED3 0x00000008 /* Output 3 */
+#define DIGIO_LED4 0x00000010 /* Output 4 */
+#define DIGIO_LED5 0x00000020 /* Output 5 */
+
+#define DIGIO_DRAWER1 0x00000100 /* Output 8 */
+#define DIGIO_DRAWER2 0x00000200 /* Output 9 */
+
+#define SERIAL_PORT_BASE ((u_char *)CONFIG_SYS_CS2_START)
+
+#define PSC_OP1_RTS 0x01
+#define PSC_OP0_RTS 0x01
+
+/*
+ * Table with supported baudrates (defined in inka4x0.h)
+ */
+static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
+#define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0]))
+
+static unsigned int inka_digin_get_input(void)
+{
+ return in_8(GPIO_BASE + 0) << 0 | in_8(GPIO_BASE + 1) << 8 |
+ in_8(GPIO_BASE + 2) << 16 | in_8(GPIO_BASE + 3) << 24;
+}
+
+#define LED_HIGH(NUM) \
+ do { \
+ setbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
+ } while (0)
+
+#define LED_LOW(NUM) \
+ do { \
+ clrbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
+ } while (0)
+
+#define CHECK_LED(NUM) \
+ do { \
+ if (state & (1 << NUM)) { \
+ LED_HIGH(NUM); \
+ } else { \
+ LED_LOW(NUM); \
+ } \
+ } while (0)
+
+static void inka_digio_set_output(unsigned int state, int which)
+{
+ volatile struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ if (which == 0) {
+ /* other */
+ CHECK_LED(0);
+ CHECK_LED(1);
+ CHECK_LED(2);
+ CHECK_LED(3);
+ CHECK_LED(4);
+ CHECK_LED(5);
+ } else {
+ if (which == 1) {
+ /* drawer1 */
+ if (state) {
+ clrbits_be32(&gpio->simple_dvo, 0x1000);
+ udelay(1);
+ setbits_be32(&gpio->simple_dvo, 0x1000);
+ } else {
+ setbits_be32(&gpio->simple_dvo, 0x1000);
+ udelay(1);
+ clrbits_be32(&gpio->simple_dvo, 0x1000);
+ }
+ }
+ if (which == 2) {
+ /* drawer 2 */
+ if (state) {
+ clrbits_be32(&gpio->simple_dvo, 0x2000);
+ udelay(1);
+ setbits_be32(&gpio->simple_dvo, 0x2000);
+ } else {
+ setbits_be32(&gpio->simple_dvo, 0x2000);
+ udelay(1);
+ clrbits_be32(&gpio->simple_dvo, 0x2000);
+ }
+ }
+ }
+ udelay(1);
+}
+
+static int do_inkadiag_io(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]) {
+ unsigned int state, val;
+
+ switch (argc) {
+ case 3:
+ /* Write a value */
+ val = simple_strtol(argv[2], NULL, 16);
+
+ if (strcmp(argv[1], "drawer1") == 0) {
+ inka_digio_set_output(val, 1);
+ } else if (strcmp(argv[1], "drawer2") == 0) {
+ inka_digio_set_output(val, 2);
+ } else if (strcmp(argv[1], "other") == 0)
+ inka_digio_set_output(val, 0);
+ else {
+ printf("Invalid argument: %s\n", argv[1]);
+ return -1;
+ }
+ /* fall through */
+ case 2:
+ /* Read a value */
+ state = inka_digin_get_input();
+
+ if (strcmp(argv[1], "drawer1") == 0) {
+ val = (state & DIGIN_DRAWER_SW1) >> (ffs(DIGIN_DRAWER_SW1) - 1);
+ } else if (strcmp(argv[1], "drawer2") == 0) {
+ val = (state & DIGIN_DRAWER_SW2) >> (ffs(DIGIN_DRAWER_SW2) - 1);
+ } else if (strcmp(argv[1], "other") == 0) {
+ val = ((state & DIGIN_KEYB_MASK) >> (ffs(DIGIN_KEYB_MASK) - 1))
+ | (state & DIGIN_TOUCHSCR_MASK) >> (ffs(DIGIN_TOUCHSCR_MASK) - 2);
+ } else {
+ printf("Invalid argument: %s\n", argv[1]);
+ return -1;
+ }
+ printf("exit code: 0x%X\n", val);
+ return 0;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return -1;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int ser_init(volatile struct mpc5xxx_psc *psc, int baudrate)
+{
+ unsigned long baseclk;
+ int div;
+
+ /* reset PSC */
+ out_8(&psc->command, PSC_SEL_MODE_REG_1);
+
+ /* select clock sources */
+
+ out_be16(&psc->psc_clock_select, 0);
+ baseclk = (gd->arch.ipb_clk + 16) / 32;
+
+ /* switch to UART mode */
+ out_be32(&psc->sicr, 0);
+
+ /* configure parity, bit length and so on */
+
+ out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
+ out_8(&psc->mode, PSC_MODE_ONE_STOP);
+
+ /* set up UART divisor */
+ div = (baseclk + (baudrate / 2)) / baudrate;
+ out_8(&psc->ctur, (div >> 8) & 0xff);
+ out_8(&psc->ctlr, div & 0xff);
+
+ /* disable all interrupts */
+ out_be16(&psc->psc_imr, 0);
+
+ /* reset and enable Rx/Tx */
+ out_8(&psc->command, PSC_RST_RX);
+ out_8(&psc->command, PSC_RST_TX);
+ out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+ return 0;
+}
+
+static void ser_putc(volatile struct mpc5xxx_psc *psc, const char c)
+{
+ /* Wait 1 second for last character to go. */
+ int i = 0;
+
+ while (!(psc->psc_status & PSC_SR_TXEMP) && (i++ < 1000000/10))
+ udelay(10);
+ psc->psc_buffer_8 = c;
+
+}
+
+static int ser_getc(volatile struct mpc5xxx_psc *psc)
+{
+ /* Wait for a character to arrive. */
+ int i = 0;
+
+ while (!(in_be16(&psc->psc_status) & PSC_SR_RXRDY) && (i++ < 1000000/10))
+ udelay(10);
+
+ return in_8(&psc->psc_buffer_8);
+}
+
+static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]) {
+ volatile struct NS16550 *uart;
+ volatile struct mpc5xxx_psc *psc;
+ unsigned int num, mode;
+ int combrd, baudrate, i, j, len;
+ int address;
+
+ if (argc < 5)
+ return cmd_usage(cmdtp);
+
+ argc--;
+ argv++;
+
+ num = simple_strtol(argv[0], NULL, 0);
+ if (num < 0 || num > 11) {
+ printf("invalid argument for num: %d\n", num);
+ return -1;
+ }
+
+ mode = simple_strtol(argv[1], NULL, 0);
+
+ combrd = 0;
+ baudrate = simple_strtoul(argv[2], NULL, 10);
+ for (i=0; i<N_BAUDRATES; ++i) {
+ if (baudrate == baudrate_table[i])
+ break;
+ }
+ if (i == N_BAUDRATES) {
+ printf("## Baudrate %d bps not supported\n",
+ baudrate);
+ return 1;
+ }
+ combrd = 115200 / baudrate;
+
+ uart = (struct NS16550 *)(SERIAL_PORT_BASE + (num << 3));
+
+ printf("Testing uart %d.\n\n", num);
+
+ if ((num >= 0) && (num <= 7)) {
+ if (mode & 1) {
+ /* turn on 'loopback' mode */
+ out_8(&uart->mcr, UART_MCR_LOOP);
+ } else {
+ /*
+ * establish the UART's operational parameters
+ * set DLAB=1, so rbr accesses DLL
+ */
+ out_8(&uart->lcr, UART_LCR_DLAB);
+ /* set baudrate */
+ out_8(&uart->rbr, combrd);
+ /* set data-format: 8-N-1 */
+ out_8(&uart->lcr, UART_LCR_WLS_8);
+ }
+
+ if (mode & 2) {
+ /* set request to send */
+ out_8(&uart->mcr, UART_MCR_RTS);
+ udelay(10);
+ /* check clear to send */
+ if ((in_8(&uart->msr) & UART_MSR_CTS) == 0x00)
+ return -1;
+ }
+ if (mode & 4) {
+ /* set data terminal ready */
+ out_8(&uart->mcr, UART_MCR_DTR);
+ udelay(10);
+ /* check data set ready and carrier detect */
+ if ((in_8(&uart->msr) & (UART_MSR_DSR | UART_MSR_DCD))
+ != (UART_MSR_DSR | UART_MSR_DCD))
+ return -1;
+ }
+
+ /* write each message-character, read it back, and display it */
+ for (i = 0, len = strlen(argv[3]); i < len; ++i) {
+ j = 0;
+ while ((in_8(&uart->lsr) & UART_LSR_THRE) == 0x00) {
+ if (j++ > CONFIG_SYS_HZ)
+ break;
+ udelay(10);
+ }
+ out_8(&uart->rbr, argv[3][i]);
+ j = 0;
+ while ((in_8(&uart->lsr) & UART_LSR_DR) == 0x00) {
+ if (j++ > CONFIG_SYS_HZ)
+ break;
+ udelay(10);
+ }
+ printf("%c", in_8(&uart->rbr));
+ }
+ printf("\n\n");
+ out_8(&uart->mcr, 0x00);
+ } else {
+ address = 0;
+
+ switch (num) {
+ case 8:
+ address = MPC5XXX_PSC6;
+ break;
+ case 9:
+ address = MPC5XXX_PSC3;
+ break;
+ case 10:
+ address = MPC5XXX_PSC2;
+ break;
+ case 11:
+ address = MPC5XXX_PSC1;
+ break;
+ }
+ psc = (struct mpc5xxx_psc *)address;
+ ser_init(psc, simple_strtol(argv[2], NULL, 0));
+ if (mode & 2) {
+ /* set request to send */
+ out_8(&psc->op0, PSC_OP0_RTS);
+ udelay(10);
+ /* check clear to send */
+ if ((in_8(&psc->ip) & PSC_IPCR_CTS) == 0)
+ return -1;
+ }
+ len = strlen(argv[3]);
+ for (i = 0; i < len; ++i) {
+ ser_putc(psc, argv[3][i]);
+ printf("%c", ser_getc(psc));
+ }
+ printf("\n\n");
+ }
+ return 0;
+}
+
+#define BUZZER_GPT (MPC5XXX_GPT + 0x60) /* GPT6 */
+static void buzzer_turn_on(unsigned int freq)
+{
+ volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
+
+ const u32 prescale = gd->arch.ipb_clk / freq / 128;
+ const u32 count = 128;
+ const u32 width = 64;
+
+ gpt->cir = (prescale << 16) | count;
+ gpt->pwmcr = width << 16;
+ gpt->emsr = 3; /* Timer enabled for PWM */
+}
+
+static void buzzer_turn_off(void)
+{
+ volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
+
+ gpt->emsr = 0;
+}
+
+static int do_inkadiag_buzzer(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]) {
+
+ unsigned int period, freq;
+ int prev, i;
+
+ if (argc != 3)
+ return cmd_usage(cmdtp);
+
+ argc--;
+ argv++;
+
+ period = simple_strtol(argv[0], NULL, 0);
+ if (!period)
+ printf("Zero period is senseless\n");
+ argc--;
+ argv++;
+
+ freq = simple_strtol(argv[0], NULL, 0);
+ /* avoid zero prescale in buzzer_turn_on() */
+ if (freq > gd->arch.ipb_clk / 128) {
+ printf("%dHz exceeds maximum (%ldHz)\n", freq,
+ gd->arch.ipb_clk / 128);
+ } else if (!freq)
+ printf("Zero frequency is senseless\n");
+ else
+ buzzer_turn_on(freq);
+
+ clear_ctrlc();
+ prev = disable_ctrlc(0);
+
+ printf("Buzzing for %d ms. Type ^C to abort!\n\n", period);
+
+ i = 0;
+ while (!ctrlc() && (i++ < CONFIG_SYS_HZ))
+ udelay(period);
+
+ clear_ctrlc();
+ disable_ctrlc(prev);
+
+ buzzer_turn_off();
+
+ return 0;
+}
+
+static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+cmd_tbl_t cmd_inkadiag_sub[] = {
+ U_BOOT_CMD_MKENT(io, 1, 1, do_inkadiag_io, "read digital input",
+ "<drawer1|drawer2|other> [value] - get or set specified signal"),
+ U_BOOT_CMD_MKENT(serial, 4, 1, do_inkadiag_serial, "test serial port",
+ "<num> <mode> <baudrate> <msg> - test uart num [0..11] in mode\n"
+ "and baudrate with msg"),
+ U_BOOT_CMD_MKENT(buzzer, 2, 1, do_inkadiag_buzzer, "activate buzzer",
+ "<period> <freq> - turn buzzer on for period ms with freq hz"),
+ U_BOOT_CMD_MKENT(help, 4, 1, do_inkadiag_help, "get help",
+ "[command] - get help for command"),
+};
+
+static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[]) {
+ extern int _do_help (cmd_tbl_t *cmd_start, int cmd_items,
+ cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[]);
+ /* do_help prints command name - we prepend inkadiag to our subcommands! */
+#ifdef CONFIG_SYS_LONGHELP
+ puts ("inkadiag ");
+#endif
+ return _do_help(&cmd_inkadiag_sub[0],
+ ARRAY_SIZE(cmd_inkadiag_sub), cmdtp, flag, argc, argv);
+}
+
+static int do_inkadiag(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]) {
+ cmd_tbl_t *c;
+
+ c = find_cmd_tbl(argv[1], &cmd_inkadiag_sub[0], ARRAY_SIZE(cmd_inkadiag_sub));
+
+ if (c) {
+ argc--;
+ argv++;
+ return c->cmd(c, flag, argc, argv);
+ } else {
+ /* Unrecognized command */
+ return cmd_usage(cmdtp);
+ }
+}
+
+U_BOOT_CMD(inkadiag, 6, 1, do_inkadiag,
+ "inkadiag - inka diagnosis\n",
+ "[inkadiag what ...]\n"
+ " - perform a diagnosis on inka hardware\n"
+ "'inkadiag' performs hardware tests.");
diff --git a/board/inka4x0/k4h511638c.h b/board/inka4x0/k4h511638c.h
new file mode 100644
index 0000000..054ddaf
--- /dev/null
+++ b/board/inka4x0/k4h511638c.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x714F0F00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x46770000
+#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h
new file mode 100644
index 0000000..23fc6f0
--- /dev/null
+++ b/board/inka4x0/mt46v16m16-75.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x714F0F00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/inka4x0/mt46v32m16-75.h b/board/inka4x0/mt46v32m16-75.h
new file mode 100644
index 0000000..f16f450
--- /dev/null
+++ b/board/inka4x0/mt46v32m16-75.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x714F0F00
+#define SDRAM_CONFIG1 0x73711930
+#define SDRAM_CONFIG2 0x46770000
+#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..0133eaa
--- /dev/null
+++ b/board/inka4x0/mt48lc16m16a2-75.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 0 /* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig
new file mode 100644
index 0000000..4709f9b
--- /dev/null
+++ b/board/intel/crownbay/Kconfig
@@ -0,0 +1,20 @@
+if TARGET_CROWNBAY
+
+config SYS_BOARD
+ default "crownbay"
+
+config SYS_VENDOR
+ default "intel"
+
+config SYS_SOC
+ default "queensbay"
+
+config SYS_CONFIG_NAME
+ default "crownbay"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select INTEL_QUEENSBAY
+ select BOARD_ROMSIZE_KB_1024
+
+endif
diff --git a/board/intel/crownbay/MAINTAINERS b/board/intel/crownbay/MAINTAINERS
new file mode 100644
index 0000000..1eb6869
--- /dev/null
+++ b/board/intel/crownbay/MAINTAINERS
@@ -0,0 +1,6 @@
+INTEL CROWNBAY BOARD
+M: Bin Meng <bmeng.cn@gmail.com>
+S: Maintained
+F: board/intel/crownbay/
+F: include/configs/crownbay.h
+F: configs/crownbay_defconfig
diff --git a/board/intel/crownbay/Makefile b/board/intel/crownbay/Makefile
new file mode 100644
index 0000000..aeb219b
--- /dev/null
+++ b/board/intel/crownbay/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += crownbay.o start.o
diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
new file mode 100644
index 0000000..2a254ef
--- /dev/null
+++ b/board/intel/crownbay/crownbay.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ibmpc.h>
+#include <asm/pnp_def.h>
+#include <netdev.h>
+#include <smsc_lpc47m.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, 4)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
+
+ return 0;
+}
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
diff --git a/board/intel/crownbay/start.S b/board/intel/crownbay/start.S
new file mode 100644
index 0000000..cf92b4c
--- /dev/null
+++ b/board/intel/crownbay/start.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+ jmp early_board_init_ret
diff --git a/board/intercontrol/digsy_mtc/Kconfig b/board/intercontrol/digsy_mtc/Kconfig
new file mode 100644
index 0000000..1cf2275
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DIGSY_MTC
+
+config SYS_BOARD
+ default "digsy_mtc"
+
+config SYS_VENDOR
+ default "intercontrol"
+
+config SYS_CONFIG_NAME
+ default "digsy_mtc"
+
+endif
diff --git a/board/intercontrol/digsy_mtc/MAINTAINERS b/board/intercontrol/digsy_mtc/MAINTAINERS
new file mode 100644
index 0000000..c83ebcd
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/MAINTAINERS
@@ -0,0 +1,9 @@
+DIGSY_MTC BOARD
+M: Werner Pfister <Pfister_Werner@intercontrol.de>
+S: Maintained
+F: board/intercontrol/digsy_mtc/
+F: include/configs/digsy_mtc.h
+F: configs/digsy_mtc_defconfig
+F: configs/digsy_mtc_RAMBOOT_defconfig
+F: configs/digsy_mtc_rev5_defconfig
+F: configs/digsy_mtc_rev5_RAMBOOT_defconfig
diff --git a/board/intercontrol/digsy_mtc/Makefile b/board/intercontrol/digsy_mtc/Makefile
new file mode 100644
index 0000000..44b7c0a
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/Makefile
@@ -0,0 +1,6 @@
+#
+# Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com
+#
+
+obj-y := digsy_mtc.o cmd_mtc.o
+obj-$(CONFIG_VIDEO) += cmd_disp.o
diff --git a/board/intercontrol/digsy_mtc/cmd_disp.c b/board/intercontrol/digsy_mtc/cmd_disp.c
new file mode 100644
index 0000000..2ffa8bf
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/cmd_disp.c
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2011 DENX Software Engineering,
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc5xxx.h>
+#include <asm/io.h>
+
+#define GPIO_USB1_0 0x00010000
+
+static int cmd_disp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ if (argc < 2) {
+ printf("%s\n",
+ in_be32(&gpio->simple_dvo) & GPIO_USB1_0 ? "on" : "off");
+ return 0;
+ }
+
+ if (!strncmp(argv[1], "on", 2)) {
+ setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
+ } else if (!strncmp(argv[1], "off", 3)) {
+ clrbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
+ } else {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+ return 0;
+}
+
+U_BOOT_CMD(disp, 2, 1, cmd_disp,
+ "disp [on/off] - switch display on/off",
+ "\n - print display on/off status\n"
+ "on\n - turn on\n"
+ "off\n - turn off\n"
+);
diff --git a/board/intercontrol/digsy_mtc/cmd_mtc.c b/board/intercontrol/digsy_mtc/cmd_mtc.c
new file mode 100644
index 0000000..f17ec55
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/cmd_mtc.c
@@ -0,0 +1,369 @@
+/*
+ * (C) Copyright 2009
+ * Werner Pfister <Pfister_Werner@intercontrol.de>
+ *
+ * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc5xxx.h>
+#include "spi.h"
+#include "cmd_mtc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uchar user_out;
+
+static const char *led_names[] = {
+ "diag",
+ "can1",
+ "can2",
+ "can3",
+ "can4",
+ "usbpwr",
+ "usbbusy",
+ "user1",
+ "user2",
+ ""
+};
+
+static int msp430_xfer(const void *dout, void *din)
+{
+ int err;
+
+ err = spi_xfer(NULL, MTC_TRANSFER_SIZE, dout, din,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+
+ /* The MSP chip needs time to ready itself for the next command */
+ udelay(1000);
+
+ return err;
+}
+
+static void mtc_calculate_checksum(tx_msp_cmd *packet)
+{
+ int i;
+ uchar *buff;
+
+ buff = (uchar *) packet;
+
+ for (i = 0; i < 6; i++)
+ packet->cks += buff[i];
+}
+
+static int do_mtc_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err;
+ int i;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_SET_LED;
+
+ pcmd.cmd_val0 = 0xff;
+ for (i = 0; strlen(led_names[i]) != 0; i++) {
+ if (strncmp(argv[1], led_names[i], strlen(led_names[i])) == 0) {
+ pcmd.cmd_val0 = i;
+ break;
+ }
+ }
+
+ if (pcmd.cmd_val0 == 0xff) {
+ printf("Usage:\n%s\n", cmdtp->help);
+ return -1;
+ }
+
+ if (argc >= 3) {
+ if (strncmp(argv[2], "red", 3) == 0)
+ pcmd.cmd_val1 = 1;
+ else if (strncmp(argv[2], "green", 5) == 0)
+ pcmd.cmd_val1 = 2;
+ else if (strncmp(argv[2], "orange", 6) == 0)
+ pcmd.cmd_val1 = 3;
+ else
+ pcmd.cmd_val1 = 0;
+ }
+
+ if (argc >= 4)
+ pcmd.cmd_val2 = simple_strtol(argv[3], NULL, 10);
+ else
+ pcmd.cmd_val2 = 0;
+
+ pcmd.user_out = user_out;
+
+ mtc_calculate_checksum(&pcmd);
+ err = msp430_xfer(&pcmd, &prx);
+
+ return err;
+}
+
+static int do_mtc_key(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err;
+
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_GET_VIM;
+ pcmd.user_out = user_out;
+
+ mtc_calculate_checksum(&pcmd);
+ err = msp430_xfer(&pcmd, &prx);
+
+ if (!err) {
+ /* function returns '0' if key is pressed */
+ err = (prx.input & 0x80) ? 0 : 1;
+ }
+
+ return err;
+}
+
+static int do_mtc_digout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err;
+ uchar channel_mask = 0;
+
+ if (argc < 3)
+ return cmd_usage(cmdtp);
+
+ if (strncmp(argv[1], "on", 2) == 0)
+ channel_mask |= 1;
+ if (strncmp(argv[2], "on", 2) == 0)
+ channel_mask |= 2;
+
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_GET_VIM;
+ pcmd.user_out = channel_mask;
+ user_out = channel_mask;
+
+ mtc_calculate_checksum(&pcmd);
+ err = msp430_xfer(&pcmd, &prx);
+
+ return err;
+}
+
+static int do_mtc_digin(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err;
+ uchar channel_num = 0;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ channel_num = simple_strtol(argv[1], NULL, 10);
+ if ((channel_num != 1) && (channel_num != 2)) {
+ printf("mtc digin: invalid parameter - must be '1' or '2'\n");
+ return -1;
+ }
+
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_GET_VIM;
+ pcmd.user_out = user_out;
+
+ mtc_calculate_checksum(&pcmd);
+ err = msp430_xfer(&pcmd, &prx);
+
+ if (!err) {
+ /* function returns '0' when digin is on */
+ err = (prx.input & channel_num) ? 0 : 1;
+ }
+
+ return err;
+}
+
+static int do_mtc_appreg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err;
+ char buf[5];
+ uchar appreg;
+
+ /* read appreg */
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_WD_PARA;
+ pcmd.cmd_val0 = 5; /* max. Count */
+ pcmd.cmd_val1 = 5; /* max. Time */
+ pcmd.cmd_val2 = 0; /* =0 means read appreg */
+ pcmd.user_out = user_out;
+
+ mtc_calculate_checksum(&pcmd);
+ err = msp430_xfer(&pcmd, &prx);
+
+ /* on success decide between read or write */
+ if (!err) {
+ if (argc == 2) {
+ appreg = simple_strtol(argv[1], NULL, 10);
+ if (appreg == 0) {
+ printf("mtc appreg: invalid parameter - "
+ "must be between 1 and 255\n");
+ return -1;
+ }
+ memset(&pcmd, 0, sizeof(pcmd));
+ pcmd.cmd = CMD_WD_PARA;
+ pcmd.cmd_val0 = prx.ack3; /* max. Count */
+ pcmd.cmd_val1 = prx.ack0; /* max. Time */
+ pcmd.cmd_val2 = appreg; /* !=0 means write appreg */
+ pcmd.user_out = user_out;
+ memset(&prx, 0, sizeof(prx));
+
+ mtc_calculate_checksum(&pcmd);
+ err = msp430_xfer(&pcmd, &prx);
+ } else {
+ sprintf(buf, "%d", prx.ack2);
+ setenv("appreg", buf);
+ }
+ }
+
+ return err;
+}
+
+static int do_mtc_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err;
+
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_FW_VERSION;
+ pcmd.user_out = user_out;
+
+ mtc_calculate_checksum(&pcmd);
+ err = msp430_xfer(&pcmd, &prx);
+
+ if (!err) {
+ printf("FW V%d.%d.%d / HW %d\n",
+ prx.ack0, prx.ack1, prx.ack3, prx.ack2);
+ }
+
+ return err;
+}
+
+static int do_mtc_state(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ tx_msp_cmd pcmd;
+ rx_msp_cmd prx;
+ int err;
+
+ memset(&pcmd, 0, sizeof(pcmd));
+ memset(&prx, 0, sizeof(prx));
+
+ pcmd.cmd = CMD_WD_WDSTATE;
+ pcmd.cmd_val2 = 1;
+ pcmd.user_out = user_out;
+
+ mtc_calculate_checksum(&pcmd);
+ err = msp430_xfer(&pcmd, &prx);
+
+ if (!err) {
+ printf("State %02Xh\n", prx.state);
+ printf("Input %02Xh\n", prx.input);
+ printf("UserWD %02Xh\n", prx.ack2);
+ printf("Sys WD %02Xh\n", prx.ack3);
+ printf("WD Timout %02Xh\n", prx.ack0);
+ printf("eSysState %02Xh\n", prx.ack1);
+ }
+
+ return err;
+}
+
+static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+cmd_tbl_t cmd_mtc_sub[] = {
+ U_BOOT_CMD_MKENT(led, 3, 1, do_mtc_led,
+ "set state of leds",
+ "[ledname] [state] [blink]\n"
+ " - lednames: diag can1 can2 can3 can4 usbpwr usbbusy user1 user2\n"
+ " - state: off red green orange\n"
+ " - blink: blink interval in 100ms steps (1 - 10; 0 = static)\n"),
+ U_BOOT_CMD_MKENT(key, 0, 1, do_mtc_key,
+ "returns state of user key", ""),
+ U_BOOT_CMD_MKENT(version, 0, 1, do_mtc_version,
+ "returns firmware version of supervisor uC", ""),
+ U_BOOT_CMD_MKENT(appreg, 1, 1, do_mtc_appreg,
+ "reads or writes appreg value and stores in environment "
+ "variable 'appreg'",
+ "[value] - value (1 - 255) to write to appreg"),
+ U_BOOT_CMD_MKENT(digin, 1, 1, do_mtc_digin,
+ "returns state of digital input",
+ "<channel_num> - get state of digital input (1 or 2)\n"),
+ U_BOOT_CMD_MKENT(digout, 2, 1, do_mtc_digout,
+ "sets digital outputs",
+ "<on|off> <on|off>- set state of digital output 1 and 2\n"),
+ U_BOOT_CMD_MKENT(state, 0, 1, do_mtc_state,
+ "displays state", ""),
+ U_BOOT_CMD_MKENT(help, 4, 1, do_mtc_help, "get help",
+ "[command] - get help for command\n"),
+};
+
+static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ extern int _do_help(cmd_tbl_t *cmd_start, int cmd_items,
+ cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[]);
+#ifdef CONFIG_SYS_LONGHELP
+ puts("mtc ");
+#endif
+ return _do_help(&cmd_mtc_sub[0],
+ ARRAY_SIZE(cmd_mtc_sub), cmdtp, flag, argc, argv);
+}
+
+int cmd_mtc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ cmd_tbl_t *c;
+ int err = 0;
+
+ c = find_cmd_tbl(argv[1], &cmd_mtc_sub[0], ARRAY_SIZE(cmd_mtc_sub));
+ if (c) {
+ argc--;
+ argv++;
+ return c->cmd(c, flag, argc, argv);
+ } else {
+ /* Unrecognized command */
+ return cmd_usage(cmdtp);
+ }
+
+ return err;
+}
+
+U_BOOT_CMD(mtc, 5, 1, cmd_mtc,
+ "special commands for digsyMTC",
+ "[subcommand] [args...]\n"
+ "Subcommands list:\n"
+ "led [ledname] [state] [blink] - set state of leds\n"
+ " [ledname]: diag can1 can2 can3 can4 usbpwr usbbusy user1 user2\n"
+ " [state]: off red green orange\n"
+ " [blink]: blink interval in 100ms steps (1 - 10; 0 = static)\n"
+ "key - returns state of user key\n"
+ "version - returns firmware version of supervisor uC\n"
+ "appreg [value] - reads (in environment variable 'appreg') or writes"
+ " appreg value\n"
+ " [value]: value (1 - 255) to write to appreg\n"
+ "digin [channel] - returns state of digital input (1 or 2)\n"
+ "digout <on|off> <on|off> - sets state of two digital outputs\n"
+ "state - displays state\n"
+ "help [subcommand] - get help for subcommand\n"
+);
diff --git a/board/intercontrol/digsy_mtc/cmd_mtc.h b/board/intercontrol/digsy_mtc/cmd_mtc.h
new file mode 100644
index 0000000..4493433
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/cmd_mtc.h
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2009
+ * Werner Pfister <Pfister_Werner@intercontrol.de>
+ *
+ * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef CMD_MTC_H
+#define CMD_MTC_H
+
+#define CMD_WD_PARA 0x02
+#define CMD_WD_WDSTATE 0x04
+#define CMD_FW_VERSION 0x10
+#define CMD_GET_VIM 0x30
+#define CMD_SET_LED 0x40
+
+typedef struct {
+ u8 cmd;
+ u8 sys_in;
+ u8 cmd_val0;
+ u8 cmd_val1;
+ u8 cmd_val2;
+ u8 user_out;
+ u8 cks;
+ u8 dummy1;
+ u8 dummy2;
+} tx_msp_cmd;
+
+typedef struct {
+ u8 input;
+ u8 state;
+ u8 ack2;
+ u8 ack3;
+ u8 ack0;
+ u8 ack1;
+ u8 ack;
+ u8 dummy;
+ u8 cks;
+} rx_msp_cmd;
+
+#define MTC_TRANSFER_SIZE (sizeof(tx_msp_cmd) * 8)
+
+#endif
diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c
new file mode 100644
index 0000000..4ab7160
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/digsy_mtc.c
@@ -0,0 +1,484 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2005-2009
+ * Modified for InterControl digsyMTC MPC5200 board by
+ * Frank Bodammer, GCD Hard- & Software GmbH,
+ * frank.bodammer@gcd-solutions.de
+ *
+ * (C) Copyright 2009
+ * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <net.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "eeprom.h"
+#if defined(CONFIG_DIGSY_REV5)
+#include "is45s16800a2.h"
+#include <mtd/cfi_flash.h>
+#include <flash.h>
+#else
+#include "is42s16800a-7t.h"
+#endif
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <mb862xx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int usb_cpu_init(void);
+
+#if defined(CONFIG_DIGSY_REV5)
+/*
+ * The M29W128GH needs a specail reset command function,
+ * details see the doc/README.cfi file
+ */
+void flash_cmd_reset(flash_info_t *info)
+{
+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+}
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+ long control = SDRAM_CONTROL | hi_addr_bit;
+
+ /* unlock mode register */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
+
+ /* precharge all banks */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+
+ /* auto refresh */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
+
+ /* set mode register */
+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+ /* normal operation */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ uint svr, pvr;
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
+ out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
+
+ /* setup config registers */
+ out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+ out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
+ (0x13 + __builtin_ffs(dramsize >> 20) - 1));
+ } else {
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
+ }
+
+ /* let SDRAM CS1 start right after CS0 */
+ out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
+
+ /* find RAM size using SDRAM CS1 only */
+ test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
+ 0x08000000);
+ dramsize2 = test1;
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20))
+ dramsize2 = 0;
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0) {
+ out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
+ (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
+ } else {
+ out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
+ if (dramsize >= 0x13)
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ else
+ dramsize = 0;
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
+ if (dramsize2 >= 0x13)
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ else
+ dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
+ out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
+
+ return dramsize + dramsize2;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ puts ("Board: InterControl digsyMTC");
+#if defined(CONFIG_DIGSY_REV5)
+ puts (" rev5");
+#endif
+ if (i > 0) {
+ puts(", ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+#if defined(CONFIG_VIDEO)
+
+#define GPIO_USB1_0 0x00010000 /* Power-On pin */
+#define GPIO_USB1_9 0x08 /* PX_~EN pin */
+
+#define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */
+#define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */
+#define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */
+#define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */
+
+#define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */
+
+static void exbo_hw_init(void)
+{
+ struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+ /* configure IrDA pins (PSC6 port) as gpios */
+ gpio->port_config &= 0xFF8FFFFF;
+
+ /* Init for USB1_0, EE_CLK and EE_DI - Low */
+ setbits_be32(&gpio->simple_ddr,
+ GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
+ clrbits_be32(&gpio->simple_ode,
+ GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
+ clrbits_be32(&gpio->simple_dvo,
+ GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
+ setbits_be32(&gpio->simple_gpioe,
+ GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
+
+ /* Init for EE_DO, EE_CTS - Input */
+ clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS);
+ setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS);
+
+ /* Init for PX_~EN (USB1_9) - High */
+ clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
+ setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
+ clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
+ setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
+ setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
+
+ /* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
+ out_be32(&gpt[0].emsr, GPT_GPIO_ON);
+ /* Init for S Switch (GPIO4) - Timer_1 GPIO High */
+ out_be32(&gpt[1].emsr, GPT_GPIO_ON);
+
+ /* Power-On camera supply */
+ setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
+}
+#else
+static inline void exbo_hw_init(void) {}
+#endif /* CONFIG_VIDEO */
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_MPC52XX_SPI
+ struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
+#endif
+ /*
+ * Now, when we are in RAM, enable flash write access for detection
+ * process. Note that CS_BOOT cannot be cleared when executing in
+ * flash.
+ */
+ /* disable CS_BOOT */
+ clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
+ /* enable CS1 */
+ setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
+ /* enable CS0 */
+ setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
+ /* Low level USB init, required for proper kernel operation */
+ usb_cpu_init();
+#endif
+#ifdef CONFIG_MPC52XX_SPI
+ /* GPT 6 Output Enable */
+ out_be32(&gpt[6].emsr, 0x00000034);
+ /* GPT 7 Output Enable */
+ out_be32(&gpt[7].emsr, 0x00000034);
+#endif
+
+ return (0);
+}
+
+void board_get_enetaddr (uchar * enet)
+{
+ ushort read = 0;
+ ushort addr_of_eth_addr = 0;
+ ushort len_sys = 0;
+ ushort len_sys_cfg = 0;
+
+ /* check identification word */
+ eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
+ if (read != EEPROM_IDENT)
+ return;
+
+ /* calculate offset of config area */
+ eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
+ eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
+ (uchar *)&len_sys_cfg, 2);
+ addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
+ if (addr_of_eth_addr >= EEPROM_LEN)
+ return;
+
+ eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
+}
+
+int misc_init_r(void)
+{
+ pci_dev_t devbusfn;
+ uchar enetaddr[6];
+
+ /* check if graphic extension board is present */
+ devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU,
+ PCI_DEVICE_ID_CORAL_PA, 0);
+ if (devbusfn != -1)
+ exbo_hw_init();
+
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ board_get_enetaddr(enetaddr);
+ eth_setenv_enetaddr("ethaddr", enetaddr);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#ifdef CONFIG_CMD_IDE
+
+#ifdef CONFIG_IDE_RESET
+
+void init_ide_reset(void)
+{
+ debug ("init_ide_reset\n");
+
+ /* set gpio output value to 1 */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
+ /* open drain output */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
+ /* direction output */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
+ /* enable gpio */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
+
+}
+
+void ide_set_reset(int idereset)
+{
+ debug ("ide_reset(%d)\n", idereset);
+
+ /* set gpio output value to 0 */
+ clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
+ /* open drain output */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
+ /* direction output */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
+ /* enable gpio */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
+
+ udelay(10000);
+
+ /* set gpio output value to 1 */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
+ /* open drain output */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
+ /* direction output */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
+ /* enable gpio */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
+}
+#endif /* CONFIG_IDE_RESET */
+#endif /* CONFIG_CMD_IDE */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+static void ft_delete_node(void *fdt, const char *compat)
+{
+ int off = -1;
+ int ret;
+
+ off = fdt_node_offset_by_compatible(fdt, -1, compat);
+ if (off < 0) {
+ printf("Could not find %s node.\n", compat);
+ return;
+ }
+
+ ret = fdt_del_node(fdt, off);
+ if (ret < 0)
+ printf("Could not delete %s node.\n", compat);
+}
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+static void ft_adapt_flash_base(void *blob)
+{
+ flash_info_t *dev = &flash_info[0];
+ int off;
+ struct fdt_property *prop;
+ int len;
+ u32 *reg, *reg2;
+
+ off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
+ if (off < 0) {
+ printf("Could not find fsl,mpc5200b-lpb node.\n");
+ return;
+ }
+
+ /* found compatible property */
+ prop = fdt_get_property_w(blob, off, "ranges", &len);
+ if (prop) {
+ reg = reg2 = (u32 *)&prop->data[0];
+
+ reg[2] = dev->start[0];
+ reg[3] = dev->size;
+ fdt_setprop(blob, off, "ranges", reg2, len);
+ } else
+ printf("Could not find ranges\n");
+}
+
+extern ulong flash_get_size (phys_addr_t base, int banknum);
+
+/* Update the Flash Baseaddr settings */
+int update_flash_size (int flash_size)
+{
+ volatile struct mpc5xxx_mmap_ctl *mm =
+ (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
+ flash_info_t *dev;
+ int i;
+ int size = 0;
+ unsigned long base = 0x0;
+ u32 *cs_reg = (u32 *)&mm->cs0_start;
+
+ for (i = 0; i < 2; i++) {
+ dev = &flash_info[i];
+
+ if (dev->size) {
+ /* calculate new base addr for this chipselect */
+ base -= dev->size;
+ out_be32(cs_reg, START_REG(base));
+ cs_reg++;
+ out_be32(cs_reg, STOP_REG(base, dev->size));
+ cs_reg++;
+ /* recalculate the sectoraddr in the cfi driver */
+ size += flash_get_size(base, i);
+ }
+ }
+ flash_protect_default();
+ gd->bd->bi_flashstart = base;
+ return 0;
+}
+#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int phy_addr = CONFIG_PHY_ADDR;
+ char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
+
+ ft_cpu_setup(blob, bd);
+ /*
+ * There are 2 RTC nodes in the DTS, so remove
+ * the unneeded node here.
+ */
+#if defined(CONFIG_DIGSY_REV5)
+ ft_delete_node(blob, "dallas,ds1339");
+#else
+ ft_delete_node(blob, "mc,rv3029c2");
+#endif
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+ /* Update reg property in all nor flash nodes too */
+ fdt_fixup_nor_flash_size(blob);
+#endif
+ ft_adapt_flash_base(blob);
+#endif
+ /* fix up the phy address */
+ do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/intercontrol/digsy_mtc/eeprom.h b/board/intercontrol/digsy_mtc/eeprom.h
new file mode 100644
index 0000000..17bd034
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/eeprom.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2009 Semihalf.
+ * Written by: Grzegorz Bernacki <gjb@semihalf.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef CMD_EEPROM_H
+#define CMD_EEPROM_H
+
+#define EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR
+#define EEPROM_LEN 1024 /* eeprom length */
+#define EEPROM_IDENT 2408 /* identification word */
+#define EEPROM_ADDR_IDENT 0 /* identification word offset */
+#define EEPROM_ADDR_LEN_SYS 2 /* system area lenght offset */
+#define EEPROM_ADDR_LEN_SYSCFG 4 /* system config area length offset */
+#define EEPROM_ADDR_ETHADDR 23 /* ethernet address offset */
+
+#endif
diff --git a/board/intercontrol/digsy_mtc/is42s16800a-7t.h b/board/intercontrol/digsy_mtc/is42s16800a-7t.h
new file mode 100644
index 0000000..c555d2d
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/is42s16800a-7t.h
@@ -0,0 +1,11 @@
+/*
+ * (C) Copyright 2004-2009
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x505F0000
+#define SDRAM_CONFIG1 0xD2322900
+#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/intercontrol/digsy_mtc/is45s16800a2.h b/board/intercontrol/digsy_mtc/is45s16800a2.h
new file mode 100644
index 0000000..c42ba38
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/is45s16800a2.h
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * based on:
+ * (C) Copyright 2004-2009
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x50470000
+#define SDRAM_CONFIG1 0xD2322900
+#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/iomega/iconnect/Kconfig b/board/iomega/iconnect/Kconfig
new file mode 100644
index 0000000..e56b029
--- /dev/null
+++ b/board/iomega/iconnect/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ICONNECT
+
+config SYS_BOARD
+ default "iconnect"
+
+config SYS_VENDOR
+ default "iomega"
+
+config SYS_CONFIG_NAME
+ default "iconnect"
+
+endif
diff --git a/board/iomega/iconnect/MAINTAINERS b/board/iomega/iconnect/MAINTAINERS
new file mode 100644
index 0000000..167cf07
--- /dev/null
+++ b/board/iomega/iconnect/MAINTAINERS
@@ -0,0 +1,6 @@
+ICONNECT BOARD
+M: Luka Perkov <luka@openwrt.org>
+S: Maintained
+F: board/iomega/iconnect/
+F: include/configs/iconnect.h
+F: configs/iconnect_defconfig
diff --git a/board/iomega/iconnect/Makefile b/board/iomega/iconnect/Makefile
new file mode 100644
index 0000000..65e357a
--- /dev/null
+++ b/board/iomega/iconnect/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := iconnect.o
diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c
new file mode 100644
index 0000000..086a473
--- /dev/null
+++ b/board/iomega/iconnect/iconnect.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "iconnect.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(ICONNECT_OE_VAL_LOW,
+ ICONNECT_OE_VAL_HIGH,
+ ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn, /* Reset signal */
+ MPP7_GPO,
+ MPP8_TW_SDA, /* I2C */
+ MPP9_TW_SCK, /* I2C */
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO, /* Reset button */
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GE1_14,
+ MPP35_GPIO, /* OTB button */
+ MPP36_AUDIO_SPDIFI,
+ MPP37_AUDIO_SPDIFO,
+ MPP38_GPIO,
+ MPP39_TDM_SPI_CS0,
+ MPP40_TDM_SPI_SCK,
+ MPP41_GPIO, /* LED brightness */
+ MPP42_GPIO, /* LED power (blue) */
+ MPP43_GPIO, /* LED power (red) */
+ MPP44_GPIO, /* LED USB 1 */
+ MPP45_GPIO, /* LED USB 2 */
+ MPP46_GPIO, /* LED USB 3 */
+ MPP47_GPIO, /* LED USB 4 */
+ MPP48_GPIO, /* LED OTB */
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
diff --git a/board/iomega/iconnect/iconnect.h b/board/iomega/iconnect/iconnect.h
new file mode 100644
index 0000000..6107a99
--- /dev/null
+++ b/board/iomega/iconnect/iconnect.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ICONNECT_H
+#define __ICONNECT_H
+
+#define ICONNECT_OE_LOW (~(1 << 7))
+#define ICONNECT_OE_HIGH (~(1 << 10))
+#define ICONNECT_OE_VAL_LOW (0)
+#define ICONNECT_OE_VAL_HIGH (1 << 10)
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __ICONNECT_H */
diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg
new file mode 100644
index 0000000..3c63a03
--- /dev/null
+++ b/board/iomega/iconnect/kwbimage.cfg
@@ -0,0 +1,151 @@
+#
+# (C) Copyright 2009-2012
+# Wojciech Dubowik <wojciech.dubowik@neratec.com>
+# Luka Perkov <luka@openwrt.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xffd100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xffd01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
+# bit23-14: 0x0,
+# bit24: 0x1, enable exit self refresh mode on DDR access
+# bit25: 0x1, required
+# bit29-26: 0x0,
+# bit31-30: 0x1,
+
+DATA 0xffd01404 0x37543000 # DDR Controller Control Low
+# bit4: 0x0, addr/cmd in smame cycle
+# bit5: 0x0, clk is driven during self refresh, we don't care for APX
+# bit6: 0x0, use recommended falling edge of clk for addr/cmd
+# bit14: 0x0, input buffer always powered up
+# bit18: 0x1, cpu lock transaction enabled
+# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 0x3, required
+# bit31: 0x0, no additional STARTBURST delay
+
+DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11-8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: 0x0, required
+
+DATA 0xffd01410 0x000000cc # DDR Address Control
+# bit1-0: 00, Cs0width (x8)
+# bit3-2: 11, Cs0size (1Gb)
+# bit5-4: 00, Cs1width (x8)
+# bit7-6: 11, Cs1size (1Gb)
+# bit9-8: 00, Cs2width (nonexistent)
+# bit11-10: 00, Cs2size (nonexistent)
+# bit13-12: 00, Cs3width (nonexistent)
+# bit15-14: 00, Cs3size (nonexistent)
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0x0, required
+
+DATA 0xffd01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0x0, required
+
+DATA 0xffd01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0x0, required
+
+DATA 0xffd0141c 0x00000c52 # DDR Mode
+# bit2-0: 0x2, BurstLen=2 required
+# bit3: 0x0, BurstType=0 required
+# bit6-4: 0x4, CL=5
+# bit7: 0x0, TestMode=0 normal
+# bit8: 0x0, DLL reset=0 normal
+# bit11-9: 0x6, auto-precharge write recovery ????????????
+# bit12: 0x0, PD must be zero
+# bit31-13: 0x0, required
+
+DATA 0xffd01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 0x0, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 0x0, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0x0, required
+
+DATA 0xffd01424 0x0000f17f # DDR Controller Control High
+# bit2-0: 0x7, required
+# bit3: 0x1, MBUS Burst Chop disabled
+# bit6-4: 0x7, required
+# bit7: 0x0,
+# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9: 0x0, no half clock cycle addition to dataout
+# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf, required
+# bit31-16: 0x0, required
+
+DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
+# bit0: 0x1, Window enabled
+# bit1: 0x0, Write Protect disabled
+# bit3-2: 0x0, CS0 hit selected
+# bit23-4: 0xfffff, required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+DATA 0xffd01508 0x00000000 # CS[1]n Base address to 256Mb
+DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled
+
+DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
+# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 0x1, ODT1 active NEVER!
+# bit31-4: 0x0, required
+
+DATA 0xffd0149c 0x0000e803 # CPU ODT Control
+DATA 0xffd01480 0x00000001 # DDR Initialization Control
+# bit0: 0x1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/ip04/Kconfig b/board/ip04/Kconfig
new file mode 100644
index 0000000..670bf89
--- /dev/null
+++ b/board/ip04/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_IP04
+
+config SYS_BOARD
+ default "ip04"
+
+config SYS_CONFIG_NAME
+ default "ip04"
+
+endif
diff --git a/board/ip04/MAINTAINERS b/board/ip04/MAINTAINERS
new file mode 100644
index 0000000..c37b011
--- /dev/null
+++ b/board/ip04/MAINTAINERS
@@ -0,0 +1,6 @@
+IP04 BOARD
+#M: Brent Kandetzki <brentk@teleco.com>
+S: Orphan (since 2014-06)
+F: board/ip04/
+F: include/configs/ip04.h
+F: configs/ip04_defconfig
diff --git a/board/ip04/Makefile b/board/ip04/Makefile
new file mode 100644
index 0000000..caba16f
--- /dev/null
+++ b/board/ip04/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2010 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ip04.o
diff --git a/board/ip04/config.mk b/board/ip04/config.mk
new file mode 100644
index 0000000..ab0fbec
--- /dev/null
+++ b/board/ip04/config.mk
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/ip04/ip04.c b/board/ip04/ip04.c
new file mode 100644
index 0000000..ae52633
--- /dev/null
+++ b/board/ip04/ip04.c
@@ -0,0 +1,41 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2007 David Rowe,
+ * (c) 2006 Ivan Danov
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+
+int checkboard(void)
+{
+ printf("Board: IP04 IP-PBX\n");
+ printf(" http://www.rowetel.com/ucasterisk/ip04.html\n");
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+
+int misc_init_r(void)
+{
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ puts("Warning: Generating 'random' MAC address\n");
+ eth_random_addr(enetaddr);
+ eth_setenv_enetaddr("ethaddr", enetaddr);
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/ipek01/Kconfig b/board/ipek01/Kconfig
new file mode 100644
index 0000000..34e094d
--- /dev/null
+++ b/board/ipek01/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_IPEK01
+
+config SYS_BOARD
+ default "ipek01"
+
+config SYS_CONFIG_NAME
+ default "ipek01"
+
+endif
diff --git a/board/ipek01/MAINTAINERS b/board/ipek01/MAINTAINERS
new file mode 100644
index 0000000..060f8a5
--- /dev/null
+++ b/board/ipek01/MAINTAINERS
@@ -0,0 +1,6 @@
+IPEK01 BOARD
+M: Wolfgang Grandegger <wg@denx.de>
+S: Maintained
+F: board/ipek01/
+F: include/configs/ipek01.h
+F: configs/ipek01_defconfig
diff --git a/board/ipek01/Makefile b/board/ipek01/Makefile
new file mode 100644
index 0000000..a786ab2
--- /dev/null
+++ b/board/ipek01/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ipek01.o
diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c
new file mode 100644
index 0000000..2078f53
--- /dev/null
+++ b/board/ipek01/ipek01.c
@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2006
+ * MicroSys GmbH
+ *
+ * (C) Copyright 2009
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <mb862xx.h>
+#include <video_fb.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_OF_LIBFDT
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
+/* mt46v16m16-75 */
+#ifdef CONFIG_MPC5200_DDR
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x714f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+#else
+#error SDRAM is not supported on this board
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start (int hi_addr)
+{
+ struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
+
+ /* precharge all banks */
+ out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+ /* set mode register: extended mode */
+ out_be32 (&sdram->mode, SDRAM_EMODE);
+
+ /* set mode register: reset DLL */
+ out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000);
+
+ /* precharge all banks */
+ out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+ /* auto refresh */
+ out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
+
+ /* set mode register */
+ out_be32 (&sdram->mode, SDRAM_MODE);
+
+ /* normal operation */
+ out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+ struct mpc5xxx_mmap_ctl *mmap_ctl =
+ (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+ struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+ struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM;
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ out_be32 (&mmap_ctl->sdram0, 0x0000001e); /* 2G at 0x0 */
+ out_be32 (&mmap_ctl->sdram1, 0x00000000); /* disabled */
+
+ /* setup config registers */
+ out_be32 (&sdram->config1, SDRAM_CONFIG1);
+ out_be32 (&sdram->config2, SDRAM_CONFIG2);
+
+ /* set tap delay */
+ out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start (0);
+ test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start (1);
+ test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start (0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0)
+ out_be32 (&mmap_ctl->sdram0,
+ 0x13 + __builtin_ffs (dramsize >> 20) - 1);
+ else
+ out_be32 (&mmap_ctl->sdram1, 0); /* disabled */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ out_be32 (&sdram->sdelay, 0x04);
+
+ return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+ puts ("Board: IPEK01 \n");
+ return 0;
+}
+
+void flash_preinit (void)
+{
+ struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
+
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ clrbits_be32 (&lpb->cs0_cfg, 0x1); /* clear RO */
+}
+
+void flash_afterinit (ulong start, ulong size)
+{
+ struct mpc5xxx_mmap_ctl *mmap_ctl =
+ (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+
+#if defined(CONFIG_BOOT_ROM)
+ /* adjust mapping */
+ out_be32 (&mmap_ctl->cs1_start, START_REG (start));
+ out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size));
+#else
+ /* adjust mapping */
+ out_be32 (&mmap_ctl->boot_start, START_REG (start));
+ out_be32 (&mmap_ctl->cs0_start, START_REG (start));
+ out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size));
+ out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size));
+#endif
+}
+
+extern flash_info_t flash_info[]; /* info for FLASH chips */
+
+int misc_init_r (void)
+{
+ /* adjust flash start */
+ gd->bd->bi_flashstart = flash_info[0].start[0];
+ return (0);
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init (struct pci_controller *);
+
+void pci_init_board (void)
+{
+ pci_mpc5xxx_init (&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup (blob, bd);
+ fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_VIDEO
+extern GraphicDevice mb862xx;
+
+static const gdc_regs init_regs[] = {
+ {0x0100, 0x00000900},
+ {0x0020, 0x80190257},
+ {0x0024, 0x00000000},
+ {0x0028, 0x00000000},
+ {0x002c, 0x00000000},
+ {0x0110, 0x00000000},
+ {0x0114, 0x00000000},
+ {0x0118, 0x02570320},
+ {0x0004, 0x041f0000},
+ {0x0008, 0x031f031f},
+ {0x000c, 0x067f0347},
+ {0x0010, 0x02780000},
+ {0x0014, 0x0257025c},
+ {0x0018, 0x00000000},
+ {0x001c, 0x02570320},
+ {0x0100, 0x80010900},
+ {0x0, 0x0}
+};
+
+const gdc_regs *board_get_regs (void)
+{
+ return init_regs;
+}
+
+/* Returns Lime base address */
+unsigned int board_video_init (void)
+{
+ if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME)
+ return 0;
+
+ mb862xx.winSizeX = 800;
+ mb862xx.winSizeY = 600;
+ mb862xx.gdfIndex = GDF_15BIT_555RGB;
+ mb862xx.gdfBytesPP = 2;
+
+ return CONFIG_SYS_LIME_BASE;
+}
+
+#if defined(CONFIG_CONSOLE_EXTRA_INFO)
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+ if (line_number == 1)
+ strcpy (info, " Board: IPEK01");
+ else
+ info[0] = '\0';
+}
+#endif
+#endif /* CONFIG_VIDEO */
diff --git a/board/isee/igep0033/Kconfig b/board/isee/igep0033/Kconfig
new file mode 100644
index 0000000..e989e4b
--- /dev/null
+++ b/board/isee/igep0033/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AM335X_IGEP0033
+
+config SYS_BOARD
+ default "igep0033"
+
+config SYS_VENDOR
+ default "isee"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "am335x_igep0033"
+
+endif
diff --git a/board/isee/igep0033/MAINTAINERS b/board/isee/igep0033/MAINTAINERS
new file mode 100644
index 0000000..d162d77
--- /dev/null
+++ b/board/isee/igep0033/MAINTAINERS
@@ -0,0 +1,6 @@
+IGEP0033 BOARD
+M: Enric Balletbo i Serra <eballetbo@iseebcn.com>
+S: Maintained
+F: board/isee/igep0033/
+F: include/configs/am335x_igep0033.h
+F: configs/am335x_igep0033_defconfig
diff --git a/board/isee/igep0033/Makefile b/board/isee/igep0033/Makefile
new file mode 100644
index 0000000..fc985b4
--- /dev/null
+++ b/board/isee/igep0033/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += mux.o
+endif
+
+obj-y += board.o
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
new file mode 100644
index 0000000..9f8fcf2
--- /dev/null
+++ b/board/isee/igep0033/board.c
@@ -0,0 +1,174 @@
+/*
+ * Board functions for IGEP COM AQUILA based boards
+ *
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#ifdef CONFIG_SPL_BUILD
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
+ .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
+ .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
+ .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = K4B2G1646EBIH9_RATIO,
+ .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+
+ .cmd1csratio = K4B2G1646EBIH9_RATIO,
+ .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+
+ .cmd2csratio = K4B2G1646EBIH9_RATIO,
+ .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
+ .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
+ .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
+ .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
+ .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
+ .zq_config = K4B2G1646EBIH9_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
+};
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+ 400, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr;
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+ .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+ .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+ .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+ .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+ config_ddr(400, &ioregs, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ gpmc_init();
+
+ return 0;
+}
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ .phy_if = PHY_INTERFACE_MODE_RMII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, ret = 0;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
+ &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ ret += rv;
+
+ return ret;
+}
+#endif
diff --git a/board/isee/igep0033/board.h b/board/isee/igep0033/board.h
new file mode 100644
index 0000000..a11d7ab
--- /dev/null
+++ b/board/isee/igep0033/board.h
@@ -0,0 +1,19 @@
+/*
+ * IGEP COM AQUILA boards information header
+ *
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We must be able to enable uart0, for initial output. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/board/isee/igep0033/mux.c b/board/isee/igep0033/mux.c
new file mode 100644
index 0000000..e862776
--- /dev/null
+++ b/board/isee/igep0033/mux.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)}, /* MMC0_CD */
+ {-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
+ {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
+ {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REF_CLK */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+/*
+ * Do board-specific muxes.
+ */
+void enable_board_pin_mux(void)
+{
+ /* NAND Flash */
+ configure_module_pin_mux(nand_pin_mux);
+ /* SD Card */
+ configure_module_pin_mux(mmc0_pin_mux);
+ /* Ethernet pinmux. */
+ configure_module_pin_mux(rmii1_pin_mux);
+}
diff --git a/board/isee/igep00x0/Kconfig b/board/isee/igep00x0/Kconfig
new file mode 100644
index 0000000..aa46882
--- /dev/null
+++ b/board/isee/igep00x0/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP3_IGEP00X0
+
+config SYS_BOARD
+ default "igep00x0"
+
+config SYS_VENDOR
+ default "isee"
+
+config SYS_CONFIG_NAME
+ default "omap3_igep00x0"
+
+endif
diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS
new file mode 100644
index 0000000..3fc2c6c
--- /dev/null
+++ b/board/isee/igep00x0/MAINTAINERS
@@ -0,0 +1,14 @@
+IGEP00X0 BOARD
+M: Enric Balletbo i Serra <eballetbo@iseebcn.com>
+S: Maintained
+F: board/isee/igep00x0/
+F: include/configs/omap3_igep00x0.h
+F: configs/igep0020_defconfig
+F: configs/igep0030_defconfig
+F: configs/igep0032_defconfig
+
+IGEP0020_NAND BOARD
+#M: -
+S: Maintained
+F: configs/igep0020_nand_defconfig
+F: configs/igep0030_nand_defconfig
diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile
new file mode 100644
index 0000000..68b151c
--- /dev/null
+++ b/board/isee/igep00x0/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := igep00x0.o
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
new file mode 100644
index 0000000..47522f8
--- /dev/null
+++ b/board/isee/igep00x0/igep00x0.c
@@ -0,0 +1,217 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <twl4030.h>
+#include <netdev.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "igep00x0.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+/* GPMC definitions for LAN9221 chips */
+static const u32 gpmc_lan_config[] = {
+ NET_LAN9221_GPMC_CONFIG1,
+ NET_LAN9221_GPMC_CONFIG2,
+ NET_LAN9221_GPMC_CONFIG3,
+ NET_LAN9221_GPMC_CONFIG4,
+ NET_LAN9221_GPMC_CONFIG5,
+ NET_LAN9221_GPMC_CONFIG6,
+};
+#endif
+
+static const struct ns16550_platdata igep_serial = {
+ OMAP34XX_UART3,
+ 2,
+ V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(igep_uart) = {
+ "serial_omap",
+ &igep_serial
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD)
+void show_boot_progress(int val)
+{
+ if (val < 0) {
+ /* something went wrong */
+ return;
+ }
+
+ if (!gpio_request(IGEP00X0_GPIO_LED, ""))
+ gpio_direction_output(IGEP00X0_GPIO_LED, 1);
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: omap_rev_string
+ * Description: For SPL builds output board rev
+ */
+void omap_rev_string(void)
+{
+}
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings->mr = MICRON_V_MR_165;
+#ifdef CONFIG_BOOT_NAND
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+#else
+ if (get_cpu_family() == CPU_OMAP34XX) {
+ timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_165;
+ timings->ctrlb = NUMONYX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+
+ } else {
+ timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_200;
+ timings->ctrlb = NUMONYX_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ }
+#endif
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
+ GPMC_SIZE_16M);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 64 as output pin and send a magic pulse through it */
+ if (!gpio_request(64, "")) {
+ gpio_direction_output(64, 0);
+ gpio_set_value(64, 1);
+ udelay(1);
+ gpio_set_value(64, 0);
+ udelay(1);
+ gpio_set_value(64, 1);
+ }
+}
+#else
+static inline void setup_net_chip(void) {}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
+void set_fdt(void)
+{
+ switch (gd->bd->bi_arch_number) {
+ case MACH_TYPE_IGEP0020:
+ setenv("dtbfile", "omap3-igep0020.dtb");
+ break;
+ case MACH_TYPE_IGEP0030:
+ setenv("dtbfile", "omap3-igep0030.dtb");
+ break;
+ }
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ twl4030_power_init();
+
+ setup_net_chip();
+
+ dieid_num_r();
+
+ set_fdt();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_DEFAULT();
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+ MUX_IGEP0020();
+#endif
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+ MUX_IGEP0030();
+#endif
+}
+
+#if defined(CONFIG_CMD_NET)
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h
new file mode 100644
index 0000000..181f81f
--- /dev/null
+++ b/board/isee/igep00x0/igep00x0.h
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _IGEP00X0_H_
+#define _IGEP00X0_H_
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+#define IGEP00X0_GPIO_LED 27
+#endif
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+#define IGEP00X0_GPIO_LED 16
+#endif
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+ "IGEPv2",
+#endif
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+ "IGEP COM MODULE/ELECTRON",
+#endif
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
+ "IGEP COM PROTON",
+#endif
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+ "ONENAND",
+#else
+ "NAND",
+#endif
+};
+
+static void setup_net_chip(void);
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DEFAULT()\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
+#endif
+
+#define MUX_IGEP0020() \
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
+
+#define MUX_IGEP0030() \
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */
diff --git a/board/jornada/Kconfig b/board/jornada/Kconfig
new file mode 100644
index 0000000..195bc26
--- /dev/null
+++ b/board/jornada/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_JORNADA
+
+config SYS_BOARD
+ default "jornada"
+
+config SYS_CONFIG_NAME
+ default "jornada"
+
+endif
diff --git a/board/jornada/MAINTAINERS b/board/jornada/MAINTAINERS
new file mode 100644
index 0000000..c77d745
--- /dev/null
+++ b/board/jornada/MAINTAINERS
@@ -0,0 +1,6 @@
+JORNADA BOARD
+M: Kristoffer Ericson <kristoffer.ericson@gmail.com>
+S: Maintained
+F: board/jornada/
+F: include/configs/jornada.h
+F: configs/jornada_defconfig
diff --git a/board/jornada/Makefile b/board/jornada/Makefile
new file mode 100644
index 0000000..6a6fbf3
--- /dev/null
+++ b/board/jornada/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# 2004 (c) MontaVista Software, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := jornada.o
+obj-y += setup.o
diff --git a/board/jornada/jornada.c b/board/jornada/jornada.c
new file mode 100644
index 0000000..ff6dbf0
--- /dev/null
+++ b/board/jornada/jornada.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <SA-1100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_JORNADA720;
+ gd->bd->bi_boot_params = 0xc0000100;
+
+
+ /*
+ * Turn on flashing.
+ * Would be nice to have some protection but
+ * that would have to be implemented in the
+ * flash init function, which isnt possible yet.
+ */
+ PPSR |= (1 << 7);
+ PPDR |= (1 << 7);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+ return (0);
+}
diff --git a/board/jornada/setup.S b/board/jornada/setup.S
new file mode 100644
index 0000000..da9f006
--- /dev/null
+++ b/board/jornada/setup.S
@@ -0,0 +1,194 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+/*-----------------------------------------------------------------------
+ * Board defines:
+ */
+
+#define MDCNFG 0x00
+#define MDCAS00 0x04
+#define MDCAS01 0x08
+#define MDCAS02 0x0C
+#define MSC0 0x10
+#define MSC1 0x14
+#define MECR 0x18
+#define MDREFR 0x1C
+#define MDCAS20 0x20
+#define MDCAS21 0x24
+#define MDCAS22 0x28
+#define MSC2 0x2C
+#define SMCNFG 0x30
+
+#define GPDR 0x04
+#define GPSR 0x08
+#define GPCR 0x0C
+#define GAFR 0x1C
+
+#define PPDR 0x00
+#define PPSR 0x04
+#define PPAR 0x08
+
+#define MDREFR_TRASR(n_) (n_ & (0x0000000f))
+#define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4)
+#define MDREFR_K0DB2 (1 << 18)
+#define MDREFR_K1DB2 (1 << 22)
+#define MDREFR_K2DB2 (1 << 26)
+
+#define MDREFR_K0RUN (1 << 17)
+#define MDREFR_K1RUN (1 << 21)
+#define MDREFR_K2RUN (1 << 25)
+
+#define MDREFR_SLFRSH (1 << 31)
+#define MDREFR_E1PIN (1 << 20)
+
+#define PSSR 0x04
+#define PSSR_DH 0x00000008
+#define POSR 0x08
+#define RCSR 0x04
+
+/*-----------------------------------------------------------------------
+ * Setup parameters for the board:
+ */
+MEM_BASE: .long 0xa0000000
+MEM_START: .long 0xc0000000
+PWR_BASE: .word 0x90020000
+RST_BASE: .long 0x90030000
+PPC_BASE: .long 0x90060000
+GPIO_BASE: .long 0x90040000
+IC_BASE: .word 0x90050000
+
+cpuspeed: .word 0xa0
+/* calculated from old blob bootloader */
+mdcnfg: .long 0x00037267 /* mdcnfg 0x00037267 */
+mdcas00: .long 0x5555557f /* mdcas00 0x5555557f */
+mdcas01: .long 0x55555555 /* mdcas01 0x55555555 */
+mdcas02: .long 0x55555555 /* mdcas02 0x55555555 */
+msc0: .long 0xfff04f78 /* msc0 0xfff04f78 */
+msc1: .long 0xfff8fff0 /* msc1 0xfff8fff0 */
+mecr: .long 0x98c698c6 /* mecr 0x98c698c6 */
+mdrefr: .long 0x067600c7 /* mdrefr 0x04340327 */
+mdcas20: .long 0xd1284142 /* mdcas20 0xd1284142 */
+mdcas21: .long 0x72249529 /* mdcas21 0x72249529 */
+mdcas22: .long 0x78414351 /* mdcas22 0x78414351 */
+msc2: .long 0x201d2959 /* msc2 0x201d2959 */
+smcnfg: .long 0x00000000 /* smcnfg 0x00000000 */
+
+pin_set_out: .long 0x37ff70
+pin_set_dir: .long 0x11480
+
+gpdr_set: .long 0x0B3A0900
+gpsr_set: .long 0x02100800
+gpcr_set: .long 0x092A0100
+gafr_set: .long 0x08600000
+
+.globl lowlevel_init
+lowlevel_init:
+
+
+ /* this is required for flashing */
+ ldr r0, PPC_BASE
+ ldr r1, pin_set_out
+ str r1, [r0, #PPSR]
+ ldr r1, pin_set_dir
+ str r1, [r0, #PPDR]
+
+ /* Setting up the memory and stuff */
+ /***********************************/
+
+ ldr r0, MEM_BASE
+
+ ldr r1, mdcnfg
+ str r1, [r0, #MDCNFG]
+ ldr r1, mdcas00
+ str r1, [r0, #MDCAS00]
+ ldr r1, mdcas01
+ str r1, [r0, #MDCAS01]
+ ldr r1, mdcas02
+ str r1, [r0, #MDCAS02]
+ ldr r1, mdcas20
+ str r1, [r0, #MDCAS20]
+ ldr r1, mdcas21
+ str r1, [r0, #MDCAS21]
+ ldr r1, mdcas22
+ str r1, [r0, #MDCAS22]
+
+ /* clear kxDB2 */
+ ldr r2, [r0, #MDREFR]
+ bic r2, r2, #MDREFR_K0DB2
+ bic r2, r2, #MDREFR_K1DB2
+ bic r2, r2, #MDREFR_K2DB2
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_TRASR(7)
+
+ mov r4, #0x2000
+ spin: subs r4, r4, #1
+ bne spin
+
+ ldr r1, PWR_BASE
+ mov r2, #PSSR_DH
+ str r2, [r1, #PSSR]
+
+ ldr r2, [r0, #MDREFR]
+ bic r2, r2, #MDREFR_K0DB2
+ bic r2, r2, #MDREFR_K1DB2
+ bic r2, r2, #MDREFR_K2DB2
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_TRASR(7)
+ orr r2, r2, #MDREFR_DRI(12)
+ orr r2, r2, #MDREFR_K0DB2
+ orr r2, r2, #MDREFR_K1DB2
+ orr r2, r2, #MDREFR_K2DB2
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_K0RUN
+ orr r2, r2, #MDREFR_K1RUN
+ orr r2, r2, #MDREFR_K2RUN
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ bic r2, r2, #MDREFR_SLFRSH
+ str r2, [r0, #MDREFR]
+
+ ldr r2, [r0, #MDREFR]
+ orr r2, r2, #MDREFR_E1PIN
+ str r2, [r0, #MDREFR]
+
+ ldr r2, MEM_START
+.rept 8
+ ldr r3, [r2]
+.endr
+
+ ldr r2, [r0, #MDCNFG]
+ orr r2, r2, #0x00000003
+ orr r2, r2, #0x00030000
+ str r2, [r0, #MDCNFG]
+
+ ldr r1, msc0
+ str r1, [r0, #MSC0]
+ ldr r1, msc1
+ str r1, [r0, #MSC1]
+ ldr r1, msc2
+ str r1, [r0, #MSC2]
+ ldr r1, smcnfg
+ str r1, [r0, #SMCNFG]
+ ldr r1, mecr
+ str r1, [r0, #MECR]
+
+ mov pc, lr
diff --git a/board/jse/Kconfig b/board/jse/Kconfig
new file mode 100644
index 0000000..48905fa
--- /dev/null
+++ b/board/jse/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_JSE
+
+config SYS_BOARD
+ default "jse"
+
+config SYS_CONFIG_NAME
+ default "JSE"
+
+endif
diff --git a/board/jse/MAINTAINERS b/board/jse/MAINTAINERS
new file mode 100644
index 0000000..818a5a0
--- /dev/null
+++ b/board/jse/MAINTAINERS
@@ -0,0 +1,6 @@
+JSE BOARD
+M: Stephen Williams <steve@icarus.com>
+S: Maintained
+F: board/jse/
+F: include/configs/JSE.h
+F: configs/JSE_defconfig
diff --git a/board/jse/Makefile b/board/jse/Makefile
new file mode 100644
index 0000000..feac3a8
--- /dev/null
+++ b/board/jse/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright 2004 Picture Elements, Inc.
+# Stephen Williams <steve@icarus.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = jse.o sdram.o flash.o host_bridge.o
+obj-y += init.o
diff --git a/board/jse/README.txt b/board/jse/README.txt
new file mode 100644
index 0000000..84497db
--- /dev/null
+++ b/board/jse/README.txt
@@ -0,0 +1,48 @@
+JSE Configuration Details
+
+Memory Bank 0 -- Flash chip
+---------------------------
+
+0xfff00000 - 0xffffffff
+
+The flash chip is really only 512Kbytes, but the high address bit of
+the 1Meg region is ignored, so the flash is replicated through the
+region. Thus, this is consistent with a flash base address 0xfff80000.
+
+The placement at the end is to be consistent with reset behavior,
+where the processor itself initially uses this bus to load the branch
+vector and start running.
+
+On-Chip Memory
+--------------
+
+0xf4000000 - 0xf4000fff
+
+The 405GPr includes a 4K on-chip memory that can be placed however
+software chooses. I choose to place the memory at this address, to
+keep it out of the cachable areas.
+
+
+Memory Bank 1 -- SystemACE Controller
+-------------------------------------
+
+0xf0000000 - 0xf00fffff
+
+The SystemACE chip is along on peripheral bank CS#1. We don't need
+much space, but 1Meg is the smallest we can configure the chip to
+allocate. We need it far away from the flash region, because this
+region is set to be non-cached.
+
+
+Internal Peripherals
+--------------------
+
+0xef600300 - 0xef6008ff
+
+These are scattered various peripherals internal to the PPC405GPr
+chip.
+
+SDRAM
+-----
+
+0x00000000 - 0x07ffffff (128 MBytes)
diff --git a/board/jse/flash.c b/board/jse/flash.c
new file mode 100644
index 0000000..a550f7d
--- /dev/null
+++ b/board/jse/flash.c
@@ -0,0 +1,491 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+#if CONFIG_SYS_MAX_FLASH_BANKS != 1
+#error "CONFIG_SYS_MAX_FLASH_BANKS must be 1"
+#endif
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+#define ADDR0 0x5555
+#define ADDR1 0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size_b0;
+
+ /* Init: no FLASHes known */
+ flash_info[0].flash_id = FLASH_UNKNOWN;
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ /* Only one bank */
+ /* Setup offsets */
+ flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ /* Monitor protection ON by default */
+ (void) flash_protect (FLAG_PROTECT_SET,
+ FLASH_BASE0_PRELIM,
+ FLASH_BASE0_PRELIM + monitor_flash_len - 1,
+ &flash_info[0]);
+ flash_info[0].size = size_b0;
+
+ return size_b0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+/*
+ * This implementation assumes that the flash chips are uniform sector
+ * devices. This is true for all likely JSE devices.
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+ unsigned idx;
+ unsigned long sector_size = info->size / info->sector_count;
+
+ for (idx = 0; idx < info->sector_count; idx += 1) {
+ info->start[idx] = base + (idx * sector_size);
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf ("AMD ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf ("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf ("SST ");
+ break;
+ case FLASH_MAN_STM:
+ printf ("ST Micro ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ /* (Reduced table of only parts expected in JSE boards.) */
+ switch (info->flash_id) {
+ case FLASH_MAN_AMD | FLASH_AM040:
+ printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_MAN_STM | FLASH_AM040:
+ printf ("MM29W040W (512 Kbit, uniform sector size)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *) info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ", info->protect[i] ? "RO " : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+ short i;
+ FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
+
+ value = addr2[0];
+
+ switch (value) {
+ case (FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (FLASH_WORD_SIZE) SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (FLASH_WORD_SIZE)STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ printf("Unknown flash manufacturer code: 0x%x\n", value);
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+
+ switch (value) {
+ case (FLASH_WORD_SIZE) AMD_ID_F040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+ case (FLASH_WORD_SIZE) AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+ case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele JSE chip */
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 512 ko */
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* Calculate the sector offsets (Use JSE Optimized code). */
+ flash_get_offsets(base, info);
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr2 = (FLASH_WORD_SIZE *) info->start[0];
+ *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+int wait_for_DQ7 (flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile FLASH_WORD_SIZE *addr =
+ (FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer (0);
+ last = start;
+ while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+ (FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+ volatile FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect;
+ int i;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+ } else {
+ printf ("\n");
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+ printf ("Erasing sector %p\n", addr2); /* CLH */
+
+ if ((info->flash_id & FLASH_VENDMASK) ==
+ FLASH_MAN_SST) {
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
+ for (i = 0; i < 50; i++)
+ udelay (1000); /* wait 1 ms */
+ } else {
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+ addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+ }
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7 (info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /* reset to read mode */
+ addr = (FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_word (info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word (info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+ volatile FLASH_WORD_SIZE *addr2 =
+ (FLASH_WORD_SIZE *) (info->start[0]);
+ volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+ volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((volatile FLASH_WORD_SIZE *) dest) &
+ (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+ addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
diff --git a/board/jse/host_bridge.c b/board/jse/host_bridge.c
new file mode 100644
index 0000000..76c07b0
--- /dev/null
+++ b/board/jse/host_bridge.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ * Stephen Williams (steve@icarus.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ident "$Id:$"
+
+# include <common.h>
+# include <pci.h>
+# include "jse_priv.h"
+
+/*
+ * The JSE board has an Intel 21555 non-transparent bridge for
+ * communication with the host. We need to render it harmless on the
+ * JSE side, but leave it alone on the host (primary) side. Normally,
+ * this will all be done before the host BIOS can gain access to the
+ * board, due to the Primary Access Lockout bit.
+ *
+ * The host_bridge_init function is called as a late initialization
+ * function, after most of the board is set up, including a PCI scan.
+ */
+
+void host_bridge_init (void)
+{
+ /* The bridge chip is at a fixed location. */
+ pci_dev_t dev = PCI_BDF (0, 10, 0);
+
+ /* Set PCI Class code --
+ The primary side sees this class code at 0x08 in the
+ primary config space. This must be something other then a
+ bridge, or MS Windows starts doing weird stuff to me. */
+ pci_write_config_dword (dev, 0x48, 0x04800000);
+
+ /* Set subsystem ID --
+ The primary side sees this value at 0x2c. We set it here so
+ that the host can tell what sort of device this is:
+ We are a Picture Elements [0x12c5] JSE [0x008a]. */
+ pci_write_config_dword (dev, 0x6c, 0x008a12c5);
+
+ /* Downstream (Primary-to-Secondary) BARs are set up mostly
+ off. We need only the Memory-0 Bar so that the host can get
+ at the CSR region to set up tables and the lot. */
+
+ /* Downstream Memory 0 setup (4K for CSR) */
+ pci_write_config_dword (dev, 0xac, 0xfffff000);
+ /* Downstream Memory 1 setup (off) */
+ pci_write_config_dword (dev, 0xb0, 0x00000000);
+ /* Downstream Memory 2 setup (off) */
+ pci_write_config_dword (dev, 0xb4, 0x00000000);
+ /* Downstream Memory 3 setup (off) */
+ pci_write_config_dword (dev, 0xb8, 0x00000000);
+
+ /* Upstream (Secondary-to-Primary) BARs are used to get at
+ host memory from the JSE card. Create two regions: a small
+ one to manage individual word reads/writes, and a larger
+ one for doing bulk frame moves. */
+
+ /* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */
+ pci_write_config_dword (dev, 0xc4, 0xfffff000);
+ /* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */
+ pci_write_config_dword (dev, 0xc8, 0xfffff000);
+
+ /* Upstream Memory 2 (BAR4) uses page translation, and is set
+ up in CCR1. Configure for 4K pages. */
+
+ /* Set CCR1,0 reigsters. This clears the Primary PCI Lockout
+ bit as well, so we are done configuring after this
+ point. Therefore, this must be the last step.
+
+ CC1[15:12]= 0 (disable I2O message unit)
+ CC1[11:8] = 0x5 (4K page size)
+ CC0[11] = 1 (Secondary Clock Disable: disable clock)
+ CC0[10] = 0 (Primary Access Lockout: allow primary access)
+ */
+ pci_write_config_dword (dev, 0xcc, 0x05000800);
+}
diff --git a/board/jse/init.S b/board/jse/init.S
new file mode 100644
index 0000000..4e449fe
--- /dev/null
+++ b/board/jse/init.S
@@ -0,0 +1,75 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0 IBM-pibs
+ */
+/*------------------------------------------------------------------------- */
+/* Function: ext_bus_cntlr_init */
+/* Description: Initializes the External Bus Controller for the external */
+/* peripherals. IMPORTANT: For pass1 this code must run from */
+/* cache since you can not reliably change a peripheral banks */
+/* timing register (pbxap) while running code from that bank. */
+/* For ex., since we are running from ROM on bank 0, we can NOT */
+/* execute the code that modifies bank 0 timings from ROM, so */
+/* we run it from cache. */
+/* */
+/* */
+/* The layout for the PEI JSE board: */
+/* Bank 0 - Flash and SRAM */
+/* Bank 1 - SystemACE */
+/* Bank 2 - not used */
+/* Bank 3 - not used */
+/* Bank 4 - not used */
+/* Bank 5 - not used */
+/* Bank 6 - not used */
+/* Bank 7 - not used */
+/*------------------------------------------------------------------------- */
+#include <asm/ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+ .globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+ mflr r4 /* save link register */
+ bl ..getAddr
+..getAddr:
+ mflr r3 /* get address of ..getAddr */
+ mtlr r4 /* restore link register */
+ addi r4,0,14 /* set ctr to 10; used to prefetch */
+ mtctr r4 /* 10 cache lines to fit this function */
+ /* in cache (gives us 8x10=80 instrctns) */
+..ebcloop:
+ icbt r0,r3 /* prefetch cache line for addr in r3 */
+ addi r3,r3,32 /* move to next cache line */
+ bdnz ..ebcloop /* continue for 10 cache lines */
+
+ /*----------------------------------------------------------------- */
+ /* Delay to ensure all accesses to ROM are complete before changing */
+ /* bank 0 timings. 200usec should be enough. */
+ /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+ /*----------------------------------------------------------------- */
+ addis r3,0,0x0
+ ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
+ mtctr r3
+..spinlp:
+ bdnz ..spinlp /* spin loop */
+
+ /*----------------------------------------------------------------- */
+ /* Memory Bank 0 (Flash) initialization */
+ /*----------------------------------------------------------------- */
+
+ addi r4,0,PB1AP
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x9B01
+ ori r4,r4,0x5480
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
+ ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
+ mtdcr EBC0_CFGDATA,r4
+
+ blr
diff --git a/board/jse/jse.c b/board/jse/jse.c
new file mode 100644
index 0000000..a0913c3
--- /dev/null
+++ b/board/jse/jse.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ * Stephen Williams (steve@icarus.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+# include <common.h>
+# include <asm/ppc4xx.h>
+# include <asm/processor.h>
+# include <asm/io.h>
+# include "jse_priv.h"
+
+/*
+ * This function is run very early, out of flash, and before devices are
+ * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
+ * of being in the init_sequence array.
+ *
+ * The SDRAM has been initialized already -- start.S:start called
+ * init.S:init_sdram early on -- but it is not yet being used for
+ * anything, not even stack. So be careful.
+ */
+int board_early_init_f (void)
+{
+ /*-------------------------------------------------------------------------+
+ | Interrupt controller setup for the JSE board.
+ | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
+ | IRQ 16 405GP internally generated; active low; level sensitive
+ | IRQ 17-24 RESERVED/UNUSED
+ | IRQ 25 (EXT IRQ 0) PCI SLOT 0; active low; level sensitive
+ | IRQ 26 (EXT IRQ 1) PCI SLOT 1; active low; level sensitive
+ | IRQ 27 (EXT IRQ 2) JP2C CHIP ; active low; level sensitive
+ | IRQ 28 (EXT IRQ 3) PCI bridge; active low; level sensitive
+ | IRQ 29 (EXT IRQ 4) SystemACE IRQ; active high
+ | IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
+ | IRQ 31 (EXT IRQ 6) (unused)
+ +-------------------------------------------------------------------------*/
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr (UIC0PR, 0xFFFFFF87); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /* Configure the interface to the SystemACE MCU port.
+ The SystemACE is fast, but there is no reason to have
+ excessivly tight timings. So the settings are slightly
+ generous. */
+
+ /* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1,
+ WBN=0, WBF=1, TH=0, RE=0, SOR=0, BEM=0, PEN=0 */
+ mtdcr (EBC0_CFGADDR, PB1AP);
+ mtdcr (EBC0_CFGDATA, 0x01011000);
+
+ /* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ mtdcr (EBC0_CFGDATA, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000);
+
+ /* Enable the /PerWE output as /PerWE, instead of /PCIINT. */
+ /* CPC0_CR1 |= PCIPW */
+ mtdcr (0xb2, mfdcr (0xb2) | 0x00004000);
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_PRE_INIT
+int board_pre_init (void)
+{
+ return board_early_init_f ();
+}
+
+#endif
+
+/*
+ * This function is also called by arch/powerpc/lib/board.c:board_init_f (it is
+ * also in the init_sequence array) but later. Many more things are
+ * configured, but we are still running from flash.
+ */
+int checkboard (void)
+{
+ unsigned vers, status;
+
+ /* check that the SystemACE chip is alive. */
+ printf ("ACE: ");
+ vers = readw (CONFIG_SYS_SYSTEMACE_BASE + 0x16);
+ printf ("SystemACE %u.%u (build %u)",
+ (vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff);
+
+ status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
+#ifdef DEBUG
+ printf (" STATUS=0x%08x", status);
+#endif
+ /* If the flash card is present and there is an initial error,
+ then force a restart of the program. */
+ if (status & 0x00000010) {
+ printf (" CFDETECT");
+
+ if (status & 0x04) {
+ /* CONTROLREG = CFGPROG */
+ writew (0x1000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
+ udelay (500);
+ /* CONTROLREG = CFGRESET */
+ writew (0x0080, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
+ udelay (500);
+ writew (0x0000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
+ /* CONTROLREG = CFGSTART */
+ writew (0x0020, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
+
+ status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
+ }
+ }
+
+ /* Wait for the SystemACE to program its chain of devices. */
+ while ((status & 0x84) == 0x00) {
+ udelay (500);
+ status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
+ }
+
+ if (status & 0x04)
+ printf (" CFG-ERROR");
+ if (status & 0x80)
+ printf (" CFGDONE");
+
+ printf ("\n");
+
+ /* Force /RTS to active. The board it not wired quite
+ correctly to use cts/rtc flow control, so just force the
+ /RST active and forget about it. */
+ writeb (readb (0xef600404) | 0x03, 0xef600404);
+
+ printf ("JSE: ready\n");
+
+ return 0;
+}
+
+/* **** No more functions called by board_init_f. **** */
+
+/*
+ * This function is called by arch/powerpc/lib/board.c:board_init_r. At this
+ * point, basic setup is done, U-Boot has been moved into SDRAM and
+ * PCI has been set up. From here we done late setup.
+ */
+int misc_init_r (void)
+{
+ host_bridge_init ();
+ return 0;
+}
diff --git a/board/jse/jse_priv.h b/board/jse/jse_priv.h
new file mode 100644
index 0000000..f61204b
--- /dev/null
+++ b/board/jse/jse_priv.h
@@ -0,0 +1,12 @@
+#ifndef __jse_priv_H
+#define __jse_prov_H
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ * Stephen Williams (steve@icarus.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+extern void host_bridge_init(void);
+
+#endif
diff --git a/board/jse/sdram.c b/board/jse/sdram.c
new file mode 100644
index 0000000..5639bed
--- /dev/null
+++ b/board/jse/sdram.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ * Stephen Williams (steve@icarus.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+# define SDRAM_LEN 0x08000000
+
+/*
+ * this is even after checkboard. It returns the size of the SDRAM
+ * that we have installed. This function is called by board_init_f
+ * in arch/powerpc/lib/board.c to initialize the memory and return what I
+ * found.
+ */
+phys_size_t initdram (int board_type)
+{
+ /* Configure the SDRAMS */
+
+ /* disable memory controller */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ mtdcr (SDRAM0_CFGDATA, 0x00000000);
+
+ udelay (500);
+
+ /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0);
+ mtdcr (SDRAM0_CFGDATA, 0xffffffff);
+
+ /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1);
+ mtdcr (SDRAM0_CFGDATA, 0xffffffff);
+
+ /* Clear SDRAM0_ECCCFG (disable ECC) */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+ mtdcr (SDRAM0_CFGDATA, 0x00000000);
+
+ /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR);
+ mtdcr (SDRAM0_CFGDATA, 0xffffffff);
+
+ /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+ mtdcr (SDRAM0_CFGDATA, 0x010a4016);
+
+ /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ mtdcr (SDRAM0_CFGDATA, 0x00084001);
+
+ /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+ mtdcr (SDRAM0_CFGDATA, 0x04084001);
+
+ /* Memory Bank 2 Config == BE=0 */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+ mtdcr (SDRAM0_CFGDATA, 0x00000000);
+
+ /* Memory Bank 3 Config == BE=0 */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+ mtdcr (SDRAM0_CFGDATA, 0x00000000);
+
+ /* refresh timer = 0x400 */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+ mtdcr (SDRAM0_CFGDATA, 0x04000000);
+
+ /* Power management idle timer set to the default. */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT);
+ mtdcr (SDRAM0_CFGDATA, 0x07c00000);
+
+ udelay (500);
+
+ /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ mtdcr (SDRAM0_CFGDATA, 0x80e00000);
+
+ return SDRAM_LEN;
+}
+
+/*
+ * The U-Boot core, as part of the initialization to prepare for
+ * loading the monitor into SDRAM, requests of this function that the
+ * memory be tested. Return 0 if the memory tests OK.
+ */
+int testdram (void)
+{
+ unsigned long idx;
+ unsigned val;
+ unsigned errors;
+ volatile unsigned long *sdram;
+
+#ifdef DEBUG
+ printf ("SDRAM Controller Registers --\n");
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ val = mfdcr (SDRAM0_CFGDATA);
+ printf (" SDRAM0_CFG : 0x%08x\n", val);
+
+ mtdcr (SDRAM0_CFGADDR, 0x24);
+ val = mfdcr (SDRAM0_CFGDATA);
+ printf (" SDRAM0_STATUS: 0x%08x\n", val);
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ val = mfdcr (SDRAM0_CFGDATA);
+ printf (" SDRAM0_B0CR : 0x%08x\n", val);
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+ val = mfdcr (SDRAM0_CFGDATA);
+ printf (" SDRAM0_B1CR : 0x%08x\n", val);
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+ val = mfdcr (SDRAM0_CFGDATA);
+ printf (" SDRAM0_TR : 0x%08x\n", val);
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+ val = mfdcr (SDRAM0_CFGDATA);
+ printf (" SDRAM0_RTR : 0x%08x\n", val);
+#endif
+
+ /* Wait for memory to be ready by testing MRSCMPbit
+ bit. Really, there should already have been plenty of time,
+ given it was started long ago. But, best to check. */
+ for (idx = 0; idx < 1000000; idx += 1) {
+ mtdcr (SDRAM0_CFGADDR, 0x24);
+ val = mfdcr (SDRAM0_CFGDATA);
+ if (val & 0x80000000)
+ break;
+ }
+
+ if (!(val & 0x80000000)) {
+ printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n");
+ return 1;
+ }
+
+ /* Start memory test. */
+ printf ("test: %u MB - ", SDRAM_LEN / 1048576);
+
+ sdram = (unsigned long *) CONFIG_SYS_SDRAM_BASE;
+
+ printf ("write - ");
+ for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
+ sdram[idx + 0] = idx;
+ sdram[idx + 1] = ~idx;
+ }
+
+ printf ("read - ");
+ errors = 0;
+ for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
+ if (sdram[idx + 0] != idx)
+ errors += 1;
+ if (sdram[idx + 1] != ~idx)
+ errors += 1;
+ if (errors > 0)
+ break;
+ }
+
+ if (errors > 0) {
+ printf ("NOT OK\n");
+ printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n",
+ sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx);
+ return 1;
+ }
+
+ printf ("ok\n");
+ return 0;
+}
diff --git a/board/jupiter/Kconfig b/board/jupiter/Kconfig
new file mode 100644
index 0000000..d71acbb
--- /dev/null
+++ b/board/jupiter/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_JUPITER
+
+config SYS_BOARD
+ default "jupiter"
+
+config SYS_CONFIG_NAME
+ default "jupiter"
+
+endif
diff --git a/board/jupiter/MAINTAINERS b/board/jupiter/MAINTAINERS
new file mode 100644
index 0000000..5a79a61
--- /dev/null
+++ b/board/jupiter/MAINTAINERS
@@ -0,0 +1,6 @@
+JUPITER BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: board/jupiter/
+F: include/configs/jupiter.h
+F: configs/jupiter_defconfig
diff --git a/board/jupiter/Makefile b/board/jupiter/Makefile
new file mode 100644
index 0000000..4d3ef9e
--- /dev/null
+++ b/board/jupiter/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := jupiter.o
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
new file mode 100644
index 0000000..8856393
--- /dev/null
+++ b/board/jupiter/jupiter.c
@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <libfdt.h>
+
+#define SDRAM_DDR 0
+#if 1
+/* Settings Icecube */
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
+#else
+/*Settings Jupiter UB 1.0.0 */
+#define SDRAM_MODE 0x008D0000
+#define SDRAM_CONTROL 0xD04F0000
+#define SDRAM_CONFIG1 0xf7277f00
+#define SDRAM_CONFIG2 0x88b70004
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+#endif
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set tap delay */
+ *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ }
+
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+ /* find RAM size using SDRAM CS1 only */
+ if (!dramsize)
+ sdram_start(0);
+ test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ if (!dramsize) {
+ sdram_start(1);
+ test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ }
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize2 = test1;
+ } else {
+ dramsize2 = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20)) {
+ dramsize2 = 0;
+ }
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+ | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13) {
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ } else {
+ dramsize = 0;
+ }
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ if (dramsize2 >= 0x13) {
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ } else {
+ dramsize2 = 0;
+ }
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+ }
+
+ return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+ puts ("Board: Sauter (Jupiter)\n");
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+int board_early_init_r (void)
+{
+ flash_preinit ();
+ return 0;
+}
+
+void flash_afterinit(ulong size)
+{
+ if (size == 0x1000000) { /* adjust mapping */
+ *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+ START_REG(CONFIG_SYS_BOOTCS_START | size);
+ *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+ }
+ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+ *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+}
+
+int update_flash_size (int flash_size)
+{
+ flash_afterinit (flash_size);
+ return 0;
+}
+
+int board_early_init_f (void)
+{
+ *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+ debug ("init_ide_reset\n");
+
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+ /* Deassert reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+ debug ("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+ /* Make a delay. MPC5200 spec says 25 usec min */
+ udelay(500000);
+ } else {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+ }
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/karo/tk71/Kconfig b/board/karo/tk71/Kconfig
new file mode 100644
index 0000000..7b3d548
--- /dev/null
+++ b/board/karo/tk71/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TK71
+
+config SYS_BOARD
+ default "tk71"
+
+config SYS_VENDOR
+ default "karo"
+
+config SYS_CONFIG_NAME
+ default "tk71"
+
+endif
diff --git a/board/karo/tk71/MAINTAINERS b/board/karo/tk71/MAINTAINERS
new file mode 100644
index 0000000..ac85d6b
--- /dev/null
+++ b/board/karo/tk71/MAINTAINERS
@@ -0,0 +1,6 @@
+TK71 BOARD
+#M: -
+S: Maintained
+F: board/karo/tk71/
+F: include/configs/tk71.h
+F: configs/tk71_defconfig
diff --git a/board/karo/tk71/Makefile b/board/karo/tk71/Makefile
new file mode 100644
index 0000000..0e0df77
--- /dev/null
+++ b/board/karo/tk71/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2012 Marek Vasut <marex@denx.de>
+# on behalf of DENX Software Engineering GmbH
+#
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := tk71.o
diff --git a/board/karo/tk71/kwbimage.cfg b/board/karo/tk71/kwbimage.cfg
new file mode 100644
index 0000000..a32e27c
--- /dev/null
+++ b/board/karo/tk71/kwbimage.cfg
@@ -0,0 +1,158 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# adopted to TK71 by
+# Nils Faerber <nils.faerber@kernelconcepts.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000034 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000000 # DDR Address Control
+# bit1-0: 01, Cs0width=x16
+# bit3-2: 10, Cs0size=512Mb
+# bit5-4: 01, Cs1width=x16
+# bit7-6: 10, Cs1size=512Mb
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000652 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000042 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00110000 # DDR ODT Control (Low)
+# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
+# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
+# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
+# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
+# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
+# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
+# bit14: 1, M_STARTBURST_IN ODT: Enabled
+# bit15: 1, DDR IO ODT Unit: Use ODT block
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c
new file mode 100644
index 0000000..35546d2
--- /dev/null
+++ b/board/karo/tk71/tk71.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TK71_OE_LOW (~0)
+#define TK71_OE_HIGH (~0)
+#define TK71_OE_VAL_LOW (0)
+#define TK71_OE_VAL_HIGH (0)
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(TK71_OE_VAL_LOW,
+ TK71_OE_VAL_HIGH,
+ TK71_OE_LOW, TK71_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+
+#define MV88E1116_MAC_CTRL2_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+static void mv_phy_88e1118_init(char *name)
+{
+ u16 reg;
+ u16 devadr;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __func__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1118 Initialized on %s\n", name);
+}
+
+/* Configure and enable Switch and PHY */
+void reset_phy(void)
+{
+ /* configure and initialize PHY */
+ mv_phy_88e1118_init("egiga0");
+
+}
+#endif
diff --git a/board/karo/tx25/Kconfig b/board/karo/tx25/Kconfig
new file mode 100644
index 0000000..42746c1
--- /dev/null
+++ b/board/karo/tx25/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TX25
+
+config SYS_BOARD
+ default "tx25"
+
+config SYS_VENDOR
+ default "karo"
+
+config SYS_SOC
+ default "mx25"
+
+config SYS_CONFIG_NAME
+ default "tx25"
+
+endif
diff --git a/board/karo/tx25/MAINTAINERS b/board/karo/tx25/MAINTAINERS
new file mode 100644
index 0000000..2defe34
--- /dev/null
+++ b/board/karo/tx25/MAINTAINERS
@@ -0,0 +1,6 @@
+TX25 BOARD
+M: John Rigby <jcrigby@gmail.com>
+S: Maintained
+F: board/karo/tx25/
+F: include/configs/tx25.h
+F: configs/tx25_defconfig
diff --git a/board/karo/tx25/Makefile b/board/karo/tx25/Makefile
new file mode 100644
index 0000000..add5dd3
--- /dev/null
+++ b/board/karo/tx25/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2009 DENX Software Engineering
+# Author: John Rigby <jcrigby@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += lowlevel_init.o
+endif
+obj-y += tx25.o
diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S
new file mode 100644
index 0000000..11b80b4
--- /dev/null
+++ b/board/karo/tx25/lowlevel_init.S
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on U-Boot and RedBoot sources for several different i.mx
+ * platforms.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/macro.h>
+#include <asm/arch/macro.h>
+
+.macro init_clocks
+ /*
+ * clocks
+ *
+ * first enable CLKO debug output
+ * 0x40000000 enables the debug CLKO signal
+ * 0x05000000 sets CLKO divider to 6
+ * 0x00600000 makes CLKO parent clk the USB clk
+ */
+ write32 0x53f80064, 0x45600000
+
+ /* CCTL: ARM = 399 MHz, AHB = 133 MHz */
+ write32 0x53f80008, 0x20034000
+
+ /*
+ * PCDR2: NFC = 33.25 MHz
+ * This is required for the NAND Flash of this board, which is a Samsung
+ * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
+ * the NFC driver in symmetric (i.e. one-cycle) mode.
+ */
+ write32 0x53f80020, 0x01010103
+
+ /*
+ * enable all implemented clocks in all three
+ * clock control registers
+ */
+ write32 0x53f8000c, 0x1fffffff
+ write32 0x53f80010, 0xffffffff
+ write32 0x53f80014, 0xfdfff
+.endm
+
+.macro init_ddrtype
+ /*
+ * ddr_type is 3.3v SDRAM
+ */
+ write32 0x43fac454, 0x800
+.endm
+
+/*
+ * sdram controller init
+ */
+.macro init_sdram_bank bankaddr, ctl, cfg
+ ldr r0, =0xb8001000
+ ldr r2, =\bankaddr
+ /*
+ * reset SDRAM controller
+ * then wait for initialization to complete
+ */
+ ldr r1, =(1 << 1)
+ str r1, [r0, #0x10]
+1: ldr r3, [r0, #0x10]
+ tst r3, #(1 << 31)
+ beq 1b
+
+ ldr r1, =0x95728
+ str r1, [r0, #\cfg] /* config */
+
+ ldr r1, =0x92116480 /* control | precharge */
+ str r1, [r0, #\ctl] /* write command to controller */
+ str r1, [r2, #0x400] /* command encoded in address */
+
+ ldr r1, =0xa2116480 /* auto refresh */
+ str r1, [r0, #\ctl]
+ ldrb r3, [r2] /* read dram twice to auto refresh */
+ ldrb r3, [r2]
+
+ ldr r1, =0xb2116480 /* control | load mode */
+ str r1, [r0, #\ctl] /* write command to controller */
+ strb r1, [r2, #0x33] /* command encoded in address */
+
+ ldr r1, =0x82116480 /* control | normal (0)*/
+ str r1, [r0, #\ctl] /* write command to controller */
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+ init_aips
+ init_max
+ init_m3if
+ init_clocks
+
+ init_sdram_bank 0x80000000, 0x0, 0x4
+
+ init_sdram_bank 0x90000000, 0x8, 0xc
+ mov pc, lr
diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c
new file mode 100644
index 0000000..4d1a0ec
--- /dev/null
+++ b/board/karo/tx25/tx25.c
@@ -0,0 +1,210 @@
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on imx27lite.c:
+ * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ * And:
+ * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx25.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong bootflag)
+{
+ /*
+ * copy ourselves from where we are running to where we were
+ * linked at. Use ulong pointers as all addresses involved
+ * are 4-byte-aligned.
+ */
+ ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
+ asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
+ asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
+ asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
+ asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
+ for (dst = start_ptr; dst < end_ptr; dst++)
+ *dst = *(dst+(run_ptr-link_ptr));
+ /*
+ * branch to nand_boot's link-time address.
+ */
+ asm volatile("ldr pc, =nand_boot");
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ * 0 for no pull
+ * or:
+ * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define FEC_OUT_PAD_CTRL 0
+
+#define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7)
+#define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9)
+
+void tx25_fec_init(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+ NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
+ MX25_PAD_FEC_MDIO__FEC_MDIO,
+ MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+ NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
+
+ NEW_PAD_CTRL(MX25_PAD_D13__GPIO_4_7, 0), /* FEC_RESET_B */
+ NEW_PAD_CTRL(MX25_PAD_D11__GPIO_4_9, 0), /* FEC_ENABLE_B */
+ };
+
+ static const iomux_v3_cfg_t fec_cfg_pads[] = {
+ MX25_PAD_FEC_RDATA0__GPIO_3_10,
+ MX25_PAD_FEC_RDATA1__GPIO_3_11,
+ MX25_PAD_FEC_RX_DV__GPIO_3_12,
+ };
+
+ debug("tx25_fec_init\n");
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+
+ /* drop PHY power and assert reset (low) */
+ gpio_direction_output(GPIO_FEC_RESET_B, 0);
+ gpio_direction_output(GPIO_FEC_ENABLE_B, 0);
+
+ mdelay(5);
+
+ debug("resetting phy\n");
+
+ /* turn on PHY power leaving reset asserted */
+ gpio_set_value(GPIO_FEC_ENABLE_B, 1);
+
+ mdelay(10);
+
+ /*
+ * Setup some strapping pins that are latched by the PHY
+ * as reset goes high.
+ *
+ * Set PHY mode to 111
+ * mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5
+ * mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5
+ * mode2 is tied high so nothing to do
+ *
+ * Turn on RMII mode
+ * RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode
+ */
+ /*
+ * set each mux mode to gpio mode
+ */
+ imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
+ ARRAY_SIZE(fec_cfg_pads));
+
+ /*
+ * set each to 1 and make each an output
+ */
+ gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
+ gpio_direction_output(IMX_GPIO_NR(3, 11), 1);
+ gpio_direction_output(IMX_GPIO_NR(3, 12), 1);
+
+ mdelay(22); /* this value came from RedBoot */
+
+ /*
+ * deassert PHY reset
+ */
+ gpio_set_value(GPIO_FEC_RESET_B, 1);
+
+ mdelay(5);
+
+ /*
+ * set FEC pins back
+ */
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+#else
+#define tx25_fec_init()
+#endif
+
+#ifdef CONFIG_MXC_UART
+/*
+ * Set up input pins with hysteresis and 100-k pull-ups
+ */
+#define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ * 0 for no pull
+ * or:
+ * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define UART1_OUT_PAD_CTRL 0
+
+static void tx25_uart1_init(void)
+{
+ static const iomux_v3_cfg_t uart1_pads[] = {
+ NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+#else
+#define tx25_uart1_init()
+#endif
+
+int board_init()
+{
+ tx25_uart1_init();
+
+ /* board id for linux */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+ return 0;
+}
+
+int board_late_init(void)
+{
+ tx25_fec_init();
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+#if CONFIG_NR_DRAM_BANKS > 1
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+#else
+
+#endif
+}
+
+int checkboard(void)
+{
+ printf("KARO TX25\n");
+ return 0;
+}
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
new file mode 100644
index 0000000..b9aff1a
--- /dev/null
+++ b/board/keymile/common/common.c
@@ -0,0 +1,374 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2011
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <command.h>
+#include <malloc.h>
+#include <cli_hush.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <linux/ctype.h>
+
+#if defined(CONFIG_POST)
+#include "post.h"
+#endif
+#include "common.h"
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Set Keymile specific environment variables
+ * Currently only some memory layout variables are calculated here
+ * ... ------------------------------------------------
+ * ... |@rootfsaddr |@pnvramaddr |@varaddr |@reserved |@END_OF_RAM
+ * ... |<------------------- pram ------------------->|
+ * ... ------------------------------------------------
+ * @END_OF_RAM: denotes the RAM size
+ * @pnvramaddr: Startadress of pseudo non volatile RAM in hex
+ * @pram : preserved ram size in k
+ * @varaddr : startadress for /var mounted into RAM
+ */
+int set_km_env(void)
+{
+ uchar buf[32];
+ unsigned int pnvramaddr;
+ unsigned int pram;
+ unsigned int varaddr;
+ unsigned int kernelmem;
+ char *p;
+ unsigned long rootfssize = 0;
+
+ pnvramaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM
+ - CONFIG_KM_PNVRAM;
+ sprintf((char *)buf, "0x%x", pnvramaddr);
+ setenv("pnvramaddr", (char *)buf);
+
+ /* try to read rootfssize (ram image) from envrionment */
+ p = getenv("rootfssize");
+ if (p != NULL)
+ strict_strtoul(p, 16, &rootfssize);
+ pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM +
+ CONFIG_KM_PNVRAM) / 0x400;
+ sprintf((char *)buf, "0x%x", pram);
+ setenv("pram", (char *)buf);
+
+ varaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
+ sprintf((char *)buf, "0x%x", varaddr);
+ setenv("varaddr", (char *)buf);
+
+ kernelmem = gd->ram_size - 0x400 * pram;
+ sprintf((char *)buf, "0x%x", kernelmem);
+ setenv("kernelmem", (char *)buf);
+
+ return 0;
+}
+
+#if defined(CONFIG_SYS_I2C_INIT_BOARD)
+static void i2c_write_start_seq(void)
+{
+ set_sda(1);
+ udelay(DELAY_HALF_PERIOD);
+ set_scl(1);
+ udelay(DELAY_HALF_PERIOD);
+ set_sda(0);
+ udelay(DELAY_HALF_PERIOD);
+ set_scl(0);
+ udelay(DELAY_HALF_PERIOD);
+}
+
+/*
+ * I2C is a synchronous protocol and resets of the processor in the middle
+ * of an access can block the I2C Bus until a powerdown of the full unit is
+ * done. This function toggles the SCL until the SCL and SCA line are
+ * released, but max. 16 times, after this a I2C start-sequence is sent.
+ * This I2C Deblocking mechanism was developed by Keymile in association
+ * with Anatech and Atmel in 1998.
+ */
+int i2c_make_abort(void)
+{
+ int scl_state = 0;
+ int sda_state = 0;
+ int i = 0;
+ int ret = 0;
+
+ if (!get_sda()) {
+ ret = -1;
+ while (i < 16) {
+ i++;
+ set_scl(0);
+ udelay(DELAY_ABORT_SEQ);
+ set_scl(1);
+ udelay(DELAY_ABORT_SEQ);
+ scl_state = get_scl();
+ sda_state = get_sda();
+ if (scl_state && sda_state) {
+ ret = 0;
+ break;
+ }
+ }
+ }
+ if (ret == 0)
+ for (i = 0; i < 5; i++)
+ i2c_write_start_seq();
+
+ /* respect stop setup time */
+ udelay(DELAY_ABORT_SEQ);
+ set_scl(1);
+ udelay(DELAY_ABORT_SEQ);
+ set_sda(1);
+ get_sda();
+
+ return ret;
+}
+
+/**
+ * i2c_init_board - reset i2c bus. When the board is powercycled during a
+ * bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
+ */
+void i2c_init_board(void)
+{
+ /* Now run the AbortSequence() */
+ i2c_make_abort();
+}
+#endif
+
+#if defined(CONFIG_KM_COMMON_ETH_INIT)
+int board_eth_init(bd_t *bis)
+{
+ if (ethernet_present())
+ return cpu_eth_init(bis);
+
+ return -1;
+}
+#endif
+
+/*
+ * do_setboardid command
+ * read out the board id and the hw key from the intventory EEPROM and set
+ * this values as environment variables.
+ */
+static int do_setboardid(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ unsigned char buf[32];
+ char *p;
+
+ p = get_local_var("IVM_BoardId");
+ if (p == NULL) {
+ printf("can't get the IVM_Boardid\n");
+ return 1;
+ }
+ sprintf((char *)buf, "%s", p);
+ setenv("boardid", (char *)buf);
+ printf("set boardid=%s\n", buf);
+
+ p = get_local_var("IVM_HWKey");
+ if (p == NULL) {
+ printf("can't get the IVM_HWKey\n");
+ return 1;
+ }
+ sprintf((char *)buf, "%s", p);
+ setenv("hwkey", (char *)buf);
+ printf("set hwkey=%s\n", buf);
+ printf("Execute manually saveenv for persistent storage.\n");
+
+ return 0;
+}
+
+U_BOOT_CMD(km_setboardid, 1, 0, do_setboardid, "setboardid", "read out bid and "
+ "hwkey from IVM and set in environment");
+
+/*
+ * command km_checkbidhwk
+ * if "boardid" and "hwkey" are not already set in the environment, do:
+ * if a "boardIdListHex" exists in the environment:
+ * - read ivm data for boardid and hwkey
+ * - compare each entry of the boardIdListHex with the
+ * IVM data:
+ * if match:
+ * set environment variables boardid, boardId,
+ * hwkey, hwKey to the found values
+ * both (boardid and boardId) are set because
+ * they might be used differently in the
+ * application and in the init scripts (?)
+ * return 0 in case of match, 1 if not match or error
+ */
+static int do_checkboardidhwk(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ unsigned long ivmbid = 0, ivmhwkey = 0;
+ unsigned long envbid = 0, envhwkey = 0;
+ char *p;
+ int verbose = argc > 1 && *argv[1] == 'v';
+ int rc = 0;
+
+ /*
+ * first read out the real inventory values, these values are
+ * already stored in the local hush variables
+ */
+ p = get_local_var("IVM_BoardId");
+ if (p == NULL) {
+ printf("can't get the IVM_Boardid\n");
+ return 1;
+ }
+ rc = strict_strtoul(p, 16, &ivmbid);
+
+ p = get_local_var("IVM_HWKey");
+ if (p == NULL) {
+ printf("can't get the IVM_HWKey\n");
+ return 1;
+ }
+ rc = strict_strtoul(p, 16, &ivmhwkey);
+
+ if (!ivmbid || !ivmhwkey) {
+ printf("Error: IVM_BoardId and/or IVM_HWKey not set!\n");
+ return rc;
+ }
+
+ /* now try to read values from environment if available */
+ p = getenv("boardid");
+ if (p != NULL)
+ rc = strict_strtoul(p, 16, &envbid);
+ p = getenv("hwkey");
+ if (p != NULL)
+ rc = strict_strtoul(p, 16, &envhwkey);
+
+ if (rc != 0) {
+ printf("strict_strtoul returns error: %d", rc);
+ return rc;
+ }
+
+ if (!envbid || !envhwkey) {
+ /*
+ * BoardId/HWkey not available in the environment, so try the
+ * environment variable for BoardId/HWkey list
+ */
+ char *bidhwklist = getenv("boardIdListHex");
+
+ if (bidhwklist) {
+ int found = 0;
+ char *rest = bidhwklist;
+ char *endp;
+
+ if (verbose) {
+ printf("IVM_BoardId: %ld, IVM_HWKey=%ld\n",
+ ivmbid, ivmhwkey);
+ printf("boardIdHwKeyList: %s\n",
+ bidhwklist);
+ }
+ while (!found) {
+ /* loop over each bid/hwkey pair in the list */
+ unsigned long bid = 0;
+ unsigned long hwkey = 0;
+
+ while (*rest && !isxdigit(*rest))
+ rest++;
+ /*
+ * use simple_strtoul because we need &end and
+ * we know we got non numeric char at the end
+ */
+ bid = simple_strtoul(rest, &endp, 16);
+ /* BoardId and HWkey are separated with a "_" */
+ if (*endp == '_') {
+ rest = endp + 1;
+ /*
+ * use simple_strtoul because we need
+ * &end
+ */
+ hwkey = simple_strtoul(rest, &endp, 16);
+ rest = endp;
+ while (*rest && !isxdigit(*rest))
+ rest++;
+ }
+ if ((!bid) || (!hwkey)) {
+ /* end of list */
+ break;
+ }
+ if (verbose) {
+ printf("trying bid=0x%lX, hwkey=%ld\n",
+ bid, hwkey);
+ }
+ /*
+ * Compare the values of the found entry in the
+ * list with the valid values which are stored
+ * in the inventory eeprom. If they are equal
+ * set the values in environment variables.
+ */
+ if ((bid == ivmbid) && (hwkey == ivmhwkey)) {
+ char buf[10];
+
+ found = 1;
+ envbid = bid;
+ envhwkey = hwkey;
+ sprintf(buf, "%lx", bid);
+ setenv("boardid", buf);
+ sprintf(buf, "%lx", hwkey);
+ setenv("hwkey", buf);
+ }
+ } /* end while( ! found ) */
+ }
+ }
+
+ /* compare now the values */
+ if ((ivmbid == envbid) && (ivmhwkey == envhwkey)) {
+ printf("boardid=0x%3lX, hwkey=%ld\n", envbid, envhwkey);
+ rc = 0; /* match */
+ } else {
+ printf("Error: env boardid=0x%3lX, hwkey=%ld\n", envbid,
+ envhwkey);
+ printf(" IVM bId=0x%3lX, hwKey=%ld\n", ivmbid, ivmhwkey);
+ rc = 1; /* don't match */
+ }
+ return rc;
+}
+
+U_BOOT_CMD(km_checkbidhwk, 2, 0, do_checkboardidhwk,
+ "check boardid and hwkey",
+ "[v]\n - check environment parameter "\
+ "\"boardIdListHex\" against stored boardid and hwkey "\
+ "from the IVM\n v: verbose output"
+);
+
+/*
+ * command km_checktestboot
+ * if the testpin of the board is asserted, return 1
+ * * else return 0
+ */
+static int do_checktestboot(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int testpin = 0;
+ char *s = NULL;
+ int testboot = 0;
+ int verbose = argc > 1 && *argv[1] == 'v';
+
+#if defined(CONFIG_POST)
+ testpin = post_hotkeys_pressed();
+ s = getenv("test_bank");
+#endif
+ /* when test_bank is not set, act as if testpin is not asserted */
+ testboot = (testpin != 0) && (s);
+ if (verbose) {
+ printf("testpin = %d\n", testpin);
+ /* cppcheck-suppress nullPointer */
+ printf("test_bank = %s\n", s ? s : "not set");
+ printf("boot test app : %s\n", (testboot) ? "yes" : "no");
+ }
+ /* return 0 means: testboot, therefore we need the inversion */
+ return !testboot;
+}
+
+U_BOOT_CMD(km_checktestboot, 2, 0, do_checktestboot,
+ "check if testpin is asserted",
+ "[v]\n v - verbose output"
+);
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
new file mode 100644
index 0000000..e075f46
--- /dev/null
+++ b/board/keymile/common/common.h
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __KEYMILE_COMMON_H
+#define __KEYMILE_COMMON_H
+
+#define WRG_RESET 0x80
+#define H_OPORTS_14 0x40
+#define WRG_LED 0x02
+#define WRL_BOOT 0x01
+
+#define OPRTL_XBUFENA 0x20
+
+#define H_OPORTS_SCC4_ENA 0x10
+#define H_OPORTS_SCC4_FD_ENA 0x04
+#define H_OPORTS_FCC1_PW_DWN 0x01
+
+#define PIGGY_PRESENT 0x80
+
+struct km_bec_fpga {
+ unsigned char id;
+ unsigned char rev;
+ unsigned char oprth;
+ unsigned char oprtl;
+ unsigned char res1[3];
+ unsigned char bprth;
+ unsigned char bprtl;
+ unsigned char gprt3;
+ unsigned char gprt2;
+ unsigned char gprt1;
+ unsigned char gprt0;
+ unsigned char res2[2];
+ unsigned char prst;
+ unsigned char res3[0xfff0];
+ unsigned char pgy_id;
+ unsigned char pgy_rev;
+ unsigned char pgy_outputs;
+ unsigned char pgy_eth;
+};
+
+#define BFTICU_DIPSWITCH_MASK 0x0f
+
+/*
+ * BFTICU FPGA iomap
+ * BFTICU is used on mgcoge and mgocge3ne
+ */
+struct bfticu_iomap {
+ u8 xi_ena; /* General defect enable */
+ u8 pack1[3];
+ u8 en_csn;
+ u8 pack2;
+ u8 safe_mem;
+ u8 pack3;
+ u8 id;
+ u8 pack4;
+ u8 rev;
+ u8 build;
+ u8 p_frc;
+ u8 p_msk;
+ u8 pack5[2];
+ u8 xg_int;
+ u8 pack6[15];
+ u8 s_conf;
+ u8 pack7;
+ u8 dmx_conf12;
+ u8 pack8;
+ u8 s_clkslv;
+ u8 pack9[11];
+ u8 d_conf;
+ u8 d_mask_ca;
+ u8 d_pll_del;
+ u8 pack10[16];
+ u8 t_conf_ca;
+ u8 t_mask_ca;
+ u8 pack11[13];
+ u8 m_def0;
+ u8 m_def1;
+ u8 m_def2;
+ u8 m_def3;
+ u8 m_def4;
+ u8 m_def5;
+ u8 m_def_trap0;
+ u8 m_def_trap1;
+ u8 m_def_trap2;
+ u8 m_def_trap3;
+ u8 m_def_trap4;
+ u8 m_def_trap5;
+ u8 m_mask_def0;
+ u8 m_mask_def1;
+ u8 m_mask_def2;
+ u8 m_mask_def3;
+ u8 m_mask_def4;
+ u8 m_mask_def5;
+ u8 m_def_mask0;
+ u8 m_def_mask1;
+ u8 m_def_mask2;
+ u8 m_def_mask3;
+ u8 m_def_mask4;
+ u8 m_def_mask5;
+ u8 m_def_pri;
+ u8 pack12[11];
+ u8 hw_status;
+ u8 pack13;
+ u8 hw_control1;
+ u8 hw_control2;
+ u8 hw_control3;
+ u8 pack14[7];
+ u8 led_on; /* Leds */
+ u8 pack15;
+ u8 sfp_control; /* SFP modules */
+ u8 pack16;
+ u8 alarm_control; /* Alarm output */
+ u8 pack17;
+ u8 icps; /* ICN clock pulse shaping */
+ u8 mswitch; /* Read mode switch */
+ u8 pack18[6];
+ u8 pb_dbug;
+};
+
+#if !defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET)
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 0
+#endif
+
+int ethernet_present(void);
+int ivm_read_eeprom(void);
+
+int trigger_fpga_config(void);
+int wait_for_fpga_config(void);
+int fpga_reset(void);
+int toggle_eeprom_spi_bus(void);
+
+int set_km_env(void);
+int fdt_set_node_and_value(void *blob,
+ char *nodename,
+ char *regname,
+ void *var,
+ int size);
+int fdt_get_node_and_value(void *blob,
+ char *nodename,
+ char *propname,
+ void **var);
+
+#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */
+#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000))
+
+int i2c_soft_read_pin(void);
+int i2c_make_abort(void);
+#endif /* __KEYMILE_COMMON_H */
diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c
new file mode 100644
index 0000000..b6b19cc
--- /dev/null
+++ b/board/keymile/common/ivm.c
@@ -0,0 +1,316 @@
+/*
+ * (C) Copyright 2011
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cli_hush.h>
+#include <i2c.h>
+#include "common.h"
+
+static int ivm_calc_crc(unsigned char *buf, int len)
+{
+ const unsigned short crc_tab[16] = {
+ 0x0000, 0xCC01, 0xD801, 0x1400,
+ 0xF001, 0x3C00, 0x2800, 0xE401,
+ 0xA001, 0x6C00, 0x7800, 0xB401,
+ 0x5000, 0x9C01, 0x8801, 0x4400};
+
+ unsigned short crc = 0; /* final result */
+ unsigned short r1 = 0; /* temp */
+ unsigned char byte = 0; /* input buffer */
+ int i;
+
+ /* calculate CRC from array data */
+ for (i = 0; i < len; i++) {
+ byte = buf[i];
+
+ /* lower 4 bits */
+ r1 = crc_tab[crc & 0xF];
+ crc = ((crc) >> 4) & 0x0FFF;
+ crc = crc ^ r1 ^ crc_tab[byte & 0xF];
+
+ /* upper 4 bits */
+ r1 = crc_tab[crc & 0xF];
+ crc = (crc >> 4) & 0x0FFF;
+ crc = crc ^ r1 ^ crc_tab[(byte >> 4) & 0xF];
+ }
+ return crc;
+}
+
+static int ivm_set_value(char *name, char *value)
+{
+ char tempbuf[256];
+
+ if (value != NULL) {
+ sprintf(tempbuf, "%s=%s", name, value);
+ return set_local_var(tempbuf, 0);
+ } else {
+ unset_local_var(name);
+ }
+ return 0;
+}
+
+static int ivm_get_value(unsigned char *buf, int len, char *name, int off,
+ int check)
+{
+ unsigned short val;
+ unsigned char valbuf[30];
+
+ if ((buf[off + 0] != buf[off + 2]) &&
+ (buf[off + 2] != buf[off + 4])) {
+ printf("%s Error corrupted %s\n", __func__, name);
+ val = -1;
+ } else {
+ val = buf[off + 0] + (buf[off + 1] << 8);
+ if ((val == 0) && (check == 1))
+ val = -1;
+ }
+ sprintf((char *)valbuf, "%x", val);
+ ivm_set_value(name, (char *)valbuf);
+ return val;
+}
+
+#define INV_BLOCKSIZE 0x100
+#define INV_DATAADDRESS 0x21
+#define INVENTORYDATASIZE (INV_BLOCKSIZE - INV_DATAADDRESS - 3)
+
+#define IVM_POS_SHORT_TEXT 0
+#define IVM_POS_MANU_ID 1
+#define IVM_POS_MANU_SERIAL 2
+#define IVM_POS_PART_NUMBER 3
+#define IVM_POS_BUILD_STATE 4
+#define IVM_POS_SUPPLIER_PART_NUMBER 5
+#define IVM_POS_DELIVERY_DATE 6
+#define IVM_POS_SUPPLIER_BUILD_STATE 7
+#define IVM_POS_CUSTOMER_ID 8
+#define IVM_POS_CUSTOMER_PROD_ID 9
+#define IVM_POS_HISTORY 10
+#define IVM_POS_SYMBOL_ONLY 11
+
+static char convert_char(char c)
+{
+ return (c < ' ' || c > '~') ? '.' : c;
+}
+
+static int ivm_findinventorystring(int type,
+ unsigned char *const string,
+ unsigned long maxlen,
+ unsigned char *buf)
+{
+ int xcode = 0;
+ unsigned long cr = 0;
+ unsigned long addr = INV_DATAADDRESS;
+ unsigned long size = 0;
+ unsigned long nr = type;
+ int stop = 0; /* stop on semicolon */
+
+ memset(string, '\0', maxlen);
+ switch (type) {
+ case IVM_POS_SYMBOL_ONLY:
+ nr = 0;
+ stop = 1;
+ break;
+ default:
+ nr = type;
+ stop = 0;
+ }
+
+ /* Look for the requested number of CR. */
+ while ((cr != nr) && (addr < INVENTORYDATASIZE)) {
+ if (buf[addr] == '\r')
+ cr++;
+ addr++;
+ }
+
+ /*
+ * the expected number of CR was found until the end of the IVM
+ * content --> fill string
+ */
+ if (addr < INVENTORYDATASIZE) {
+ /* Copy the IVM string in the corresponding string */
+ for (; (buf[addr] != '\r') &&
+ ((buf[addr] != ';') || (!stop)) &&
+ (size < (maxlen - 1) &&
+ (addr < INVENTORYDATASIZE)); addr++) {
+ size += sprintf((char *)string + size, "%c",
+ convert_char (buf[addr]));
+ }
+
+ /*
+ * copy phase is done: check if everything is ok. If not,
+ * the inventory data is most probably corrupted: tell
+ * the world there is a problem!
+ */
+ if (addr == INVENTORYDATASIZE) {
+ xcode = -1;
+ printf("Error end of string not found\n");
+ } else if ((size > (maxlen - 1)) &&
+ (buf[addr] != '\r')) {
+ xcode = -1;
+ printf("string too long till next CR\n");
+ }
+ } else {
+ /*
+ * some CR are missing...
+ * the inventory data is most probably corrupted
+ */
+ xcode = -1;
+ printf("not enough cr found\n");
+ }
+ return xcode;
+}
+
+#define GET_STRING(name, which, len) \
+ if (ivm_findinventorystring(which, valbuf, len, buf) == 0) { \
+ ivm_set_value(name, (char *)valbuf); \
+ }
+
+static int ivm_check_crc(unsigned char *buf, int block)
+{
+ unsigned long crc;
+ unsigned long crceeprom;
+
+ crc = ivm_calc_crc(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2);
+ crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \
+ buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256);
+ if (crc != crceeprom) {
+ if (block == 0)
+ printf("Error CRC Block: %d EEprom: calculated: \
+ %lx EEprom: %lx\n", block, crc, crceeprom);
+ return -1;
+ }
+ return 0;
+}
+
+static int calculate_mac_offset(unsigned char *valbuf, unsigned char *buf,
+ int offset)
+{
+ unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6];
+
+ if (offset == 0)
+ return 0;
+
+ val += offset;
+ buf[4] = (val >> 16) & 0xff;
+ buf[5] = (val >> 8) & 0xff;
+ buf[6] = val & 0xff;
+ sprintf((char *)valbuf, "%pM", buf + 1);
+ return 0;
+}
+
+static int ivm_analyze_block2(unsigned char *buf, int len)
+{
+ unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
+ unsigned long count;
+
+ /* IVM_MAC Adress begins at offset 1 */
+ sprintf((char *)valbuf, "%pM", buf + 1);
+ ivm_set_value("IVM_MacAddress", (char *)valbuf);
+ /* if an offset is defined, add it */
+ calculate_mac_offset(buf, valbuf, CONFIG_PIGGY_MAC_ADRESS_OFFSET);
+#ifdef MACH_TYPE_KM_KIRKWOOD
+ setenv((char *)"ethaddr", (char *)valbuf);
+#else
+ if (getenv("ethaddr") == NULL)
+ setenv((char *)"ethaddr", (char *)valbuf);
+#endif
+#ifdef CONFIG_KMVECT1
+/* KMVECT1 has two ethernet interfaces */
+ if (getenv("eth1addr") == NULL) {
+ calculate_mac_offset(buf, valbuf, 1);
+ setenv((char *)"eth1addr", (char *)valbuf);
+ }
+#endif
+ /* IVM_MacCount */
+ count = (buf[10] << 24) +
+ (buf[11] << 16) +
+ (buf[12] << 8) +
+ buf[13];
+ if (count == 0xffffffff)
+ count = 1;
+ sprintf((char *)valbuf, "%lx", count);
+ ivm_set_value("IVM_MacCount", (char *)valbuf);
+ return 0;
+}
+
+static int ivm_analyze_eeprom(unsigned char *buf, int len)
+{
+ unsigned short val;
+ unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
+ unsigned char *tmp;
+
+ if (ivm_check_crc(buf, 0) != 0)
+ return -1;
+
+ ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
+ "IVM_BoardId", 0, 1);
+ val = ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
+ "IVM_HWKey", 6, 1);
+ if (val != 0xffff) {
+ sprintf((char *)valbuf, "%x", ((val / 100) % 10));
+ ivm_set_value("IVM_HWVariant", (char *)valbuf);
+ sprintf((char *)valbuf, "%x", (val % 100));
+ ivm_set_value("IVM_HWVersion", (char *)valbuf);
+ }
+ ivm_get_value(buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN,
+ "IVM_Functions", 12, 0);
+
+ GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8)
+ GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64)
+ tmp = (unsigned char *) getenv("IVM_DeviceName");
+ if (tmp) {
+ int len = strlen((char *)tmp);
+ int i = 0;
+
+ while (i < len) {
+ if (tmp[i] == ';') {
+ ivm_set_value("IVM_ShortText",
+ (char *)&tmp[i + 1]);
+ break;
+ }
+ i++;
+ }
+ if (i >= len)
+ ivm_set_value("IVM_ShortText", NULL);
+ } else {
+ ivm_set_value("IVM_ShortText", NULL);
+ }
+ GET_STRING("IVM_ManufacturerID", IVM_POS_MANU_ID, 32)
+ GET_STRING("IVM_ManufacturerSerialNumber", IVM_POS_MANU_SERIAL, 20)
+ GET_STRING("IVM_ManufacturerPartNumber", IVM_POS_PART_NUMBER, 32)
+ GET_STRING("IVM_ManufacturerBuildState", IVM_POS_BUILD_STATE, 32)
+ GET_STRING("IVM_SupplierPartNumber", IVM_POS_SUPPLIER_PART_NUMBER, 32)
+ GET_STRING("IVM_DelieveryDate", IVM_POS_DELIVERY_DATE, 32)
+ GET_STRING("IVM_SupplierBuildState", IVM_POS_SUPPLIER_BUILD_STATE, 32)
+ GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32)
+ GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32)
+
+ if (ivm_check_crc(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0)
+ return 0;
+ ivm_analyze_block2(&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2],
+ CONFIG_SYS_IVM_EEPROM_PAGE_LEN);
+
+ return 0;
+}
+
+int ivm_read_eeprom(void)
+{
+ uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+ int ret;
+
+ i2c_set_bus_num(CONFIG_KM_IVM_BUS);
+ /* add deblocking here */
+ i2c_make_abort();
+
+ ret = i2c_read(CONFIG_SYS_IVM_EEPROM_ADR, 0, 1, i2c_buffer,
+ CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+ if (ret != 0) {
+ printf("Error reading EEprom\n");
+ return -2;
+ }
+
+ return ivm_analyze_eeprom(i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+}
diff --git a/board/keymile/km82xx/Kconfig b/board/keymile/km82xx/Kconfig
new file mode 100644
index 0000000..c9a093c
--- /dev/null
+++ b/board/keymile/km82xx/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_KM82XX
+
+config SYS_BOARD
+ default "km82xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "km82xx"
+
+endif
diff --git a/board/keymile/km82xx/MAINTAINERS b/board/keymile/km82xx/MAINTAINERS
new file mode 100644
index 0000000..50e06b2
--- /dev/null
+++ b/board/keymile/km82xx/MAINTAINERS
@@ -0,0 +1,7 @@
+KM82XX BOARD
+M: Holger Brunck <holger.brunck@keymile.com>
+S: Maintained
+F: board/keymile/km82xx/
+F: include/configs/km82xx.h
+F: configs/mgcoge_defconfig
+F: configs/mgcoge3ne_defconfig
diff --git a/board/keymile/km82xx/Makefile b/board/keymile/km82xx/Makefile
new file mode 100644
index 0000000..20f193a
--- /dev/null
+++ b/board/keymile/km82xx/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2001-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := km82xx.o ../common/common.o ../common/ivm.o
diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c
new file mode 100644
index 0000000..bf84676
--- /dev/null
+++ b/board/keymile/km82xx/km82xx.c
@@ -0,0 +1,467 @@
+/*
+ * (C) Copyright 2007 - 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+#include <malloc.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+#include <i2c.h>
+#include "../common/common.h"
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A */
+ { /* conf ppar psor pdir podr pdat */
+ { 0, 0, 0, 0, 0, 0 }, /* PA31 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA30 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA29 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA28 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA27 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA26 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA21 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA20 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA19 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA18 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA17 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA16 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA15 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA14 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
+ { 1, 1, 0, 1, 0, 0 }, /* PA9 SMC2 TxD */
+ { 1, 1, 0, 0, 0, 0 }, /* PA8 SMC2 RxD */
+ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
+ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
+ { 0, 0, 0, 0, 0, 0 } /* PA0 */
+ },
+
+ /* Port B */
+ { /* conf ppar psor pdir podr pdat */
+ { 0, 0, 0, 0, 0, 0 }, /* PB31 */
+ { 0, 0, 0, 0, 0, 0 }, /* PB30 */
+ { 0, 0, 0, 0, 0, 0 }, /* PB29 */
+ { 0, 0, 0, 0, 0, 0 }, /* PB28 */
+ { 0, 0, 0, 0, 0, 0 }, /* PB27 */
+ { 0, 0, 0, 0, 0, 0 }, /* PB26 */
+ { 0, 0, 0, 0, 0, 0 }, /* PB25 */
+ { 0, 0, 0, 0, 0, 0 }, /* PB24 */
+ { 0, 0, 0, 0, 0, 0 }, /* PB23 */
+ { 0, 0, 0, 0, 0, 0 }, /* PB22 */
+ { 0, 0, 0, 0, 0, 0 }, /* PB21 */
+ { 0, 0, 0, 0, 0, 0 }, /* PB20 */
+ { 0, 0, 0, 0, 0, 0 }, /* PB19 */
+ { 0, 0, 0, 0, 0, 0 }, /* PB18 */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 } /* non-existent */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
+ { 1, 1, 0, 0, 0, 0 }, /* PC25 RxClk */
+ { 1, 1, 0, 0, 0, 0 }, /* PC24 TxClk */
+ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC18 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
+ { 1, 1, 0, 0, 0, 0 }, /* PC9 SCC4: CTS */
+ { 1, 1, 0, 0, 0, 0 }, /* PC8 SCC4: CD */
+ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
+ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
+ { 1, 1, 0, 0, 0, 0 }, /* PD22 SCC4: RXD */
+ { 1, 1, 0, 1, 0, 0 }, /* PD21 SCC4: TXD */
+ { 1, 1, 0, 1, 0, 0 }, /* PD20 SCC4: RTS */
+ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
+#if defined(CONFIG_HARD_I2C)
+ { 1, 1, 1, 0, 1, 0 }, /* PD15 I2C SDA */
+ { 1, 1, 1, 0, 1, 0 }, /* PD14 I2C SCL */
+#else
+ { 1, 0, 0, 0, 1, 1 }, /* PD15 */
+ { 1, 0, 0, 1, 1, 1 }, /* PD14 */
+#endif
+ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
+ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ { 0, 0, 0, 0, 0, 0 } /* non-existent */
+ }
+};
+
+/*
+ * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init(memctl8260_t *memctl, ulong sdmr,
+ ulong orx, uchar *base)
+{
+ uchar c = 0xff;
+ ulong maxsize, size;
+ int i;
+
+ /*
+ * We must be able to test a location outsize the maximum legal size
+ * to find out THAT we are outside; but this address still has to be
+ * mapped by the controller. That means, that the initial mapping has
+ * to be (at least) twice as large as the maximum expected size.
+ */
+ maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
+
+ out_be32(&memctl->memc_or1, orx);
+
+ /*
+ * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+ *
+ * "At system reset, initialization software must set up the
+ * programmable parameters in the memory controller banks registers
+ * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+ * system software should execute the following initialization sequence
+ * for each SDRAM device.
+ *
+ * 1. Issue a PRECHARGE-ALL-BANKS command
+ * 2. Issue eight CBR REFRESH commands
+ * 3. Issue a MODE-SET command to initialize the mode register
+ *
+ * The initial commands are executed by setting P/LSDMR[OP] and
+ * accessing the SDRAM with a single-byte transaction."
+ *
+ * The appropriate BRx/ORx registers have already been set when we
+ * get here. The SDRAM can be accessed at the address
+ * CONFIG_SYS_SDRAM_BASE.
+ */
+
+ out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
+ out_8(base, c);
+
+ out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR);
+ for (i = 0; i < 8; i++)
+ out_8(base, c);
+
+ out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW);
+ /* setting MR on address lines */
+ out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);
+
+ out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN);
+ out_8(base, c);
+
+ size = get_ram_size((long *)base, maxsize);
+ out_be32(&memctl->memc_or1, orx | ~(size - 1));
+
+ return size;
+}
+
+#ifdef CONFIG_SYS_SDRAM_LIST
+
+/*
+ * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM
+ * configurations therein (should be from high to lower) to find the
+ * one actually matching the current configuration.
+ * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are
+ * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST
+ * (defined as the initialization value for the array of struct sdram_conf_s)
+ * will then be ORed with such base values.
+ */
+
+struct sdram_conf_s {
+ ulong size;
+ int or1;
+ int psdmr;
+};
+
+static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST;
+
+static long probe_sdram(memctl8260_t *memctl)
+{
+ int n = 0;
+ long psize = 0;
+
+ for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) {
+ psize = try_init(memctl,
+ CONFIG_SYS_PSDMR | sdram_conf[n].psdmr,
+ CONFIG_SYS_OR1 | sdram_conf[n].or1,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
+ debug("Probing %ld bytes returned %ld\n",
+ sdram_conf[n].size, psize);
+ if (psize == sdram_conf[n].size)
+ break;
+ }
+ return psize;
+}
+
+#else /* CONFIG_SYS_SDRAM_LIST */
+
+static long probe_sdram(memctl8260_t *memctl)
+{
+ return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
+}
+#endif /* CONFIG_SYS_SDRAM_LIST */
+
+
+phys_size_t initdram(int board_type)
+{
+ immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ memctl8260_t *memctl = &immap->im_memctl;
+
+ long psize;
+
+ out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
+ out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
+
+ /* 60x SDRAM setup:
+ */
+ psize = probe_sdram(memctl);
+
+ icache_enable();
+
+ return psize;
+}
+
+int checkboard(void)
+{
+#if defined(CONFIG_MGCOGE)
+ puts("Board: Keymile mgcoge");
+#else
+ puts("Board: Keymile mgcoge3ne");
+#endif
+ if (ethernet_present())
+ puts(" with PIGGY.");
+ puts("\n");
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ struct bfticu_iomap *base =
+ (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE;
+ u8 dip_switch;
+
+ dip_switch = in_8(&base->mswitch);
+ dip_switch &= BFTICU_DIPSWITCH_MASK;
+ /* dip switch 'full reset' or 'db erase' */
+ if (dip_switch & 0x1 || dip_switch & 0x2) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
+ set_km_env();
+ return 0;
+}
+
+#ifdef CONFIG_MGCOGE3NE
+static void set_pin(int state, unsigned long mask);
+
+/*
+ * For mgcoge3ne boards, the mgcoge3un control is controlled from
+ * a GPIO line on the PPC CPU. If bobcatreset is set the line
+ * will toggle once what forces the mgocge3un part to restart
+ * immediately.
+ */
+static void handle_mgcoge3un_reset(void)
+{
+ char *bobcatreset = getenv("bobcatreset");
+ if (bobcatreset) {
+ if (strcmp(bobcatreset, "true") == 0) {
+ puts("Forcing bobcat reset\n");
+ set_pin(0, 0x00000004); /* clear PD29 to reset arm */
+ udelay(1000);
+ set_pin(1, 0x00000004);
+ } else
+ set_pin(1, 0x00000004); /* set PD29 to not reset arm */
+ }
+}
+#endif
+
+int ethernet_present(void)
+{
+ struct km_bec_fpga *base =
+ (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+
+ return in_8(&base->bprth) & PIGGY_PRESENT;
+}
+
+/*
+ * Early board initalization.
+ */
+int board_early_init_r(void)
+{
+ struct km_bec_fpga *base =
+ (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+
+ /* setup the UPIOx */
+ /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
+ out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED));
+ /* SCC4 enable, halfduplex, FCC1 powerdown */
+ out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
+ H_OPORTS_FCC1_PW_DWN));
+
+#ifdef CONFIG_MGCOGE3NE
+ handle_mgcoge3un_reset();
+#endif
+ return 0;
+}
+
+int hush_init_var(void)
+{
+ ivm_read_eeprom();
+ return 0;
+}
+
+#define SDA_MASK 0x00010000
+#define SCL_MASK 0x00020000
+
+static void set_pin(int state, unsigned long mask)
+{
+ ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
+
+ if (state)
+ setbits_be32(&iop->pdat, mask);
+ else
+ clrbits_be32(&iop->pdat, mask);
+
+ setbits_be32(&iop->pdir, mask);
+}
+
+static int get_pin(unsigned long mask)
+{
+ ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
+
+ clrbits_be32(&iop->pdir, mask);
+ return 0 != (in_be32(&iop->pdat) & mask);
+}
+
+void set_sda(int state)
+{
+ set_pin(state, SDA_MASK);
+}
+
+void set_scl(int state)
+{
+ set_pin(state, SCL_MASK);
+}
+
+int get_sda(void)
+{
+ return get_pin(SDA_MASK);
+}
+
+int get_scl(void)
+{
+ return get_pin(SCL_MASK);
+}
+
+#if defined(CONFIG_HARD_I2C)
+static void setports(int gpio)
+{
+ ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
+
+ if (gpio) {
+ clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
+ clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
+ } else {
+ setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
+ clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
+ setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
+ }
+}
+#endif
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig
new file mode 100644
index 0000000..d6c594c
--- /dev/null
+++ b/board/keymile/km83xx/Kconfig
@@ -0,0 +1,38 @@
+if TARGET_KM8360
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "km8360"
+
+endif
+
+if TARGET_SUVD3
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "suvd3"
+
+endif
+
+if TARGET_TUXX1
+
+config SYS_BOARD
+ default "km83xx"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "tuxx1"
+
+endif
diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS
new file mode 100644
index 0000000..cee7e08
--- /dev/null
+++ b/board/keymile/km83xx/MAINTAINERS
@@ -0,0 +1,19 @@
+KM83XX BOARD
+M: Holger Brunck <holger.brunck@keymile.com>
+S: Maintained
+F: board/keymile/km83xx/
+F: include/configs/km8360.h
+F: configs/kmcoge5ne_defconfig
+F: configs/kmeter1_defconfig
+F: include/configs/tuxx1.h
+F: configs/kmopti2_defconfig
+F: include/configs/suvd3.h
+F: configs/kmvect1_defconfig
+F: configs/suvd3_defconfig
+F: configs/tuge1_defconfig
+F: configs/tuxx1_defconfig
+
+KMSUPX5 BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: configs/kmsupx5_defconfig
diff --git a/board/keymile/km83xx/Makefile b/board/keymile/km83xx/Makefile
new file mode 100644
index 0000000..6c32688
--- /dev/null
+++ b/board/keymile/km83xx/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += km83xx.o ../common/common.o ../common/ivm.o km83xx_i2c.o
diff --git a/board/keymile/km83xx/README.kmeter1 b/board/keymile/km83xx/README.kmeter1
new file mode 100644
index 0000000..7f4fc99
--- /dev/null
+++ b/board/keymile/km83xx/README.kmeter1
@@ -0,0 +1,91 @@
+Keymile kmeter1 Board
+-----------------------------------------
+1. Alternative Boot EEPROM
+
+ Upon the kmeter1 startup the I2C_1 controller is used to fetch the boot
+ configuration from a serial EEPROM. During the development and debugging
+ phase it might be helpful to apply an alternative boot configuration in
+ a simple way. Therefore it is an alternative boot eeprom on the PIGGY,
+ which can be activated by setting the "ST" jumper on the PIGGY board.
+
+2. Memory Map
+
+ BaseAddr PortSz Size Device
+ ----------- ------ ----- ------
+ 0x0000_0000 64 bit 256MB DDR
+ 0x8000_0000 8 bit 256KB GPIO/PIGGY on CS1
+ 0xa000_0000 8 bit 256MB PAXE on CS3
+ 0xe000_0000 2MB Int Mem Reg Space
+ 0xf000_0000 16 bit 256MB FLASH on CS0
+
+
+ DDR-SDRAM:
+ The current realization is made with four 16-bits memory devices.
+ Mounting options have been foreseen for device architectures from
+ 4Mx16 to 512Mx16. The kmeter1 is equipped with four 32Mx16 devices
+ thus resulting in a total capacity of 256MBytes.
+
+3. Compilation
+
+ Assuming you're using BASH shell:
+
+ export CROSS_COMPILE=your-cross-compile-prefix
+ cd u-boot
+ make distclean
+ make kmeter1_config
+ make
+
+4. Downloading and Flashing Images
+
+4.0 Download over serial line using Kermit:
+
+ loadb
+ [Drop to kermit:
+ ^\c
+ send <u-boot-bin-image>
+ c
+ ]
+
+
+ Or via tftp:
+
+ tftp 10000 u-boot.bin
+ => run load
+ Using UEC0 device
+ TFTP from server 192.168.1.1; our IP address is 192.168.205.4
+ Filename '/tftpboot/kmeter1/u-boot.bin'.
+ Load address: 0x200000
+ Loading: ##############
+ done
+ Bytes transferred = 204204 (31dac hex)
+ =>
+
+4.1 Reflash U-boot Image using U-boot
+
+ => run update
+ ..... done
+ Un-Protected 5 sectors
+
+ ..... done
+ Erased 5 sectors
+ Copy to Flash... done
+ ..... done
+ Protected 5 sectors
+ Total of 204204 bytes were the same
+ Saving Environment to Flash...
+ . done
+ Un-Protected 1 sectors
+ . done
+ Un-Protected 1 sectors
+ Erasing Flash...
+ . done
+ Erased 1 sectors
+ Writing to Flash... done
+ . done
+ Protected 1 sectors
+ . done
+ Protected 1 sectors
+ =>
+
+5. Notes
+ 1) The console baudrate for kmeter1 is 115200bps.
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
new file mode 100644
index 0000000..1da0dcb
--- /dev/null
+++ b/board/keymile/km83xx/km83xx.c
@@ -0,0 +1,412 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ * Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008 - 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <pci.h>
+#include <libfdt.h>
+#include <post.h>
+
+#include "../common/common.h"
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* port pin dir open_drain assign */
+#if defined(CONFIG_MPC8360)
+ /* MDIO */
+ {0, 1, 3, 0, 2}, /* MDIO */
+ {0, 2, 1, 0, 1}, /* MDC */
+
+ /* UCC4 - UEC */
+ {1, 14, 1, 0, 1}, /* TxD0 */
+ {1, 15, 1, 0, 1}, /* TxD1 */
+ {1, 20, 2, 0, 1}, /* RxD0 */
+ {1, 21, 2, 0, 1}, /* RxD1 */
+ {1, 18, 1, 0, 1}, /* TX_EN */
+ {1, 26, 2, 0, 1}, /* RX_DV */
+ {1, 27, 2, 0, 1}, /* RX_ER */
+ {1, 24, 2, 0, 1}, /* COL */
+ {1, 25, 2, 0, 1}, /* CRS */
+ {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
+ {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
+
+ /* DUART - UART2 */
+ {5, 0, 1, 0, 2}, /* UART2_SOUT */
+ {5, 2, 1, 0, 1}, /* UART2_RTS */
+ {5, 3, 2, 0, 2}, /* UART2_SIN */
+ {5, 1, 2, 0, 3}, /* UART2_CTS */
+#elif !defined(CONFIG_MPC8309)
+ /* Local Bus */
+ {0, 16, 1, 0, 3}, /* LA00 */
+ {0, 17, 1, 0, 3}, /* LA01 */
+ {0, 18, 1, 0, 3}, /* LA02 */
+ {0, 19, 1, 0, 3}, /* LA03 */
+ {0, 20, 1, 0, 3}, /* LA04 */
+ {0, 21, 1, 0, 3}, /* LA05 */
+ {0, 22, 1, 0, 3}, /* LA06 */
+ {0, 23, 1, 0, 3}, /* LA07 */
+ {0, 24, 1, 0, 3}, /* LA08 */
+ {0, 25, 1, 0, 3}, /* LA09 */
+ {0, 26, 1, 0, 3}, /* LA10 */
+ {0, 27, 1, 0, 3}, /* LA11 */
+ {0, 28, 1, 0, 3}, /* LA12 */
+ {0, 29, 1, 0, 3}, /* LA13 */
+ {0, 30, 1, 0, 3}, /* LA14 */
+ {0, 31, 1, 0, 3}, /* LA15 */
+
+ /* MDIO */
+ {3, 4, 3, 0, 2}, /* MDIO */
+ {3, 5, 1, 0, 2}, /* MDC */
+
+ /* UCC4 - UEC */
+ {1, 18, 1, 0, 1}, /* TxD0 */
+ {1, 19, 1, 0, 1}, /* TxD1 */
+ {1, 22, 2, 0, 1}, /* RxD0 */
+ {1, 23, 2, 0, 1}, /* RxD1 */
+ {1, 26, 2, 0, 1}, /* RxER */
+ {1, 28, 2, 0, 1}, /* Rx_DV */
+ {1, 30, 1, 0, 1}, /* TxEN */
+ {1, 31, 2, 0, 1}, /* CRS */
+ {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
+#endif
+
+ /* END of table */
+ {0, 0, 0, 0, QE_IOP_TAB_END},
+};
+
+#if defined(CONFIG_SUVD3)
+const uint upma_table[] = {
+ 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
+ 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
+ 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
+ 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
+ 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
+};
+#endif
+
+static int piggy_present(void)
+{
+ struct km_bec_fpga __iomem *base =
+ (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
+
+ return in_8(&base->bprth) & PIGGY_PRESENT;
+}
+
+#if defined(CONFIG_KMVECT1)
+int ethernet_present(void)
+{
+ /* ethernet port connected to simple switch without piggy */
+ return 1;
+}
+#else
+int ethernet_present(void)
+{
+ return piggy_present();
+}
+#endif
+
+
+int board_early_init_r(void)
+{
+ struct km_bec_fpga *base =
+ (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+#if defined(CONFIG_SUVD3)
+ immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ fsl_lbc_t *lbc = &immap->im_lbc;
+ u32 *mxmr = &lbc->mamr;
+#endif
+
+#if defined(CONFIG_MPC8360)
+ unsigned short svid;
+ /*
+ * Because of errata in the UCCs, we have to write to the reserved
+ * registers to slow the clocks down.
+ */
+ svid = SVR_REV(mfspr(SVR));
+ switch (svid) {
+ case 0x0020:
+ /*
+ * MPC8360ECE.pdf QE_ENET10 table 4:
+ * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
+ * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
+ */
+ setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
+ break;
+ case 0x0021:
+ /*
+ * MPC8360ECE.pdf QE_ENET10 table 4:
+ * IMMR + 0x14AC[24:27] = 1010
+ */
+ clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
+ 0x00000050, 0x000000a0);
+ break;
+ }
+#endif
+
+ /* enable the PHY on the PIGGY */
+ setbits_8(&base->pgy_eth, 0x01);
+ /* enable the Unit LED (green) */
+ setbits_8(&base->oprth, WRL_BOOT);
+ /* enable Application Buffer */
+ setbits_8(&base->oprtl, OPRTL_XBUFENA);
+
+#if defined(CONFIG_SUVD3)
+ /* configure UPMA for APP1 */
+ upmconfig(UPMA, (uint *) upma_table,
+ sizeof(upma_table) / sizeof(uint));
+ out_be32(mxmr, CONFIG_SYS_MAMR);
+#endif
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+#if defined(CONFIG_KMVECT1)
+#include <mv88e6352.h>
+/* Marvell MV88E6122 switch configuration */
+static struct mv88e_sw_reg extsw_conf[] = {
+ /* port 1, FRONT_MDI, autoneg */
+ { PORT(1), PORT_PHY, NO_SPEED_FOR },
+ { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ { PHY(1), PHY_1000_CTRL, NO_ADV },
+ { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN },
+ { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
+ FULL_DUPLEX },
+ /* port 2, unused */
+ { PORT(2), PORT_CTRL, PORT_DIS },
+ { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 3, BP_MII (CPU), PHY mode, 100BASE */
+ { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */
+ { PORT(4), PORT_STATUS, NO_PHY_DETECT },
+ { PORT(4), PORT_PHY, SPEED_1000_FOR },
+ { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */
+ { PORT(5), PORT_STATUS, NO_PHY_DETECT },
+ { PORT(5), PORT_PHY, SPEED_1000_FOR },
+ { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ /*
+ * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
+ * acc . MV-S300889-00D.pdf , clause 4.5
+ */
+ { PORT(5), 0x1A, 0xADB1 },
+ /* port 6, unused, this port has no phy */
+ { PORT(6), PORT_CTRL, PORT_DIS },
+ /*
+ * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
+ * acc . MV-S300889-00D.pdf , clause 4.5
+ */
+ { PORT(5), 0x1A, 0xADB1 },
+};
+#endif
+
+int last_stage_init(void)
+{
+#if defined(CONFIG_KMVECT1)
+ struct km_bec_fpga __iomem *base =
+ (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
+ u8 tmp_reg;
+
+ /* Release mv88e6122 from reset */
+ tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */
+ out_8(&base->res1[0], tmp_reg); /* GP28 as output */
+ tmp_reg = in_8(&base->gprt3) | 0x10; /* GP28 to high */
+ out_8(&base->gprt3, tmp_reg);
+
+ /* configure MV88E6122 switch */
+ char *name = "UEC2";
+
+ if (miiphy_set_current_dev(name))
+ return 0;
+
+ mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
+ ARRAY_SIZE(extsw_conf));
+
+ mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
+
+ if (piggy_present()) {
+ setenv("ethact", "UEC2");
+ setenv("netdev", "eth1");
+ puts("using PIGGY for network boot\n");
+ } else {
+ setenv("netdev", "eth0");
+ puts("using frontport for network boot\n");
+ }
+#endif
+
+#if defined(CONFIG_KMCOGE5NE)
+ struct bfticu_iomap *base =
+ (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
+ u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
+
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
+#endif
+ set_km_env();
+ return 0;
+}
+
+static int fixed_sdram(void)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = 0;
+ u32 ddr_size;
+ u32 ddr_size_log2;
+
+ out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
+ out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
+ out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+ out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+ out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+ out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+ out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+ out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+ out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+ out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+ udelay(200);
+ setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+
+ msize = CONFIG_SYS_DDR_SIZE << 20;
+ disable_addr_trans();
+ msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
+ enable_addr_trans();
+ msize /= (1024 * 1024);
+ if (CONFIG_SYS_DDR_SIZE != msize) {
+ for (ddr_size = msize << 20, ddr_size_log2 = 0;
+ (ddr_size > 1);
+ ddr_size = ddr_size >> 1, ddr_size_log2++)
+ if (ddr_size & 1)
+ return -1;
+ out_be32(&im->sysconf.ddrlaw[0].ar,
+ (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
+ out_be32(&im->ddr.csbnds[0].csbnds,
+ (((msize / 16) - 1) & 0xff));
+ }
+
+ return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = 0;
+
+ if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ out_be32(&im->sysconf.ddrlaw[0].bar,
+ CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
+ msize = fixed_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize DDR ECC byte
+ */
+ ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+ puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
+
+ if (piggy_present())
+ puts(" with PIGGY.");
+ puts("\n");
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var(void)
+{
+ ivm_read_eeprom();
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_POST)
+int post_hotkeys_pressed(void)
+{
+ int testpin = 0;
+ struct km_bec_fpga *base =
+ (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+ int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
+ testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
+ debug("post_hotkeys_pressed: %d\n", !testpin);
+ return testpin;
+}
+
+ulong post_word_load(void)
+{
+ void* addr = (ulong *) (CPM_POST_WORD_ADDR);
+ debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
+ return in_le32(addr);
+
+}
+void post_word_store(ulong value)
+{
+ void* addr = (ulong *) (CPM_POST_WORD_ADDR);
+ debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
+ out_le32(addr, value);
+}
+
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ *vstart = CONFIG_SYS_MEMTEST_START;
+ *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
+ debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
+
+ return 0;
+}
+#endif
diff --git a/board/keymile/km83xx/km83xx_i2c.c b/board/keymile/km83xx/km83xx_i2c.c
new file mode 100644
index 0000000..c961937
--- /dev/null
+++ b/board/keymile/km83xx/km83xx_i2c.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2011
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <linux/ctype.h>
+#include "../common/common.h"
+
+static void i2c_write_start_seq(void)
+{
+ struct fsl_i2c *dev;
+ dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+ udelay(DELAY_ABORT_SEQ);
+ out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+ udelay(DELAY_ABORT_SEQ);
+ out_8(&dev->cr, (I2C_CR_MEN));
+}
+
+int i2c_make_abort(void)
+{
+ struct fsl_i2c *dev;
+ dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
+ uchar last;
+ int nbr_read = 0;
+ int i = 0;
+ int ret = 0;
+
+ /* wait after each operation to finsh with a delay */
+ out_8(&dev->cr, (I2C_CR_MSTA));
+ udelay(DELAY_ABORT_SEQ);
+ out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA));
+ udelay(DELAY_ABORT_SEQ);
+ in_8(&dev->dr);
+ udelay(DELAY_ABORT_SEQ);
+ last = in_8(&dev->dr);
+ nbr_read++;
+
+ /*
+ * do read until the last bit is 1, but stop if the full eeprom is
+ * read.
+ */
+ while (((last & 0x01) != 0x01) &&
+ (nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) {
+ udelay(DELAY_ABORT_SEQ);
+ last = in_8(&dev->dr);
+ nbr_read++;
+ }
+ if ((last & 0x01) != 0x01)
+ ret = -2;
+ if ((last != 0xff) || (nbr_read > 1))
+ printf("[INFO] i2c abort after %d bytes (0x%02x)\n",
+ nbr_read, last);
+ udelay(DELAY_ABORT_SEQ);
+ out_8(&dev->cr, (I2C_CR_MEN));
+ udelay(DELAY_ABORT_SEQ);
+ /* clear status reg */
+ out_8(&dev->sr, 0);
+
+ for (i = 0; i < 5; i++)
+ i2c_write_start_seq();
+ if (ret != 0)
+ printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n",
+ nbr_read, last);
+
+ return ret;
+}
diff --git a/board/keymile/km_arm/Kconfig b/board/keymile/km_arm/Kconfig
new file mode 100644
index 0000000..3476780
--- /dev/null
+++ b/board/keymile/km_arm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_KM_KIRKWOOD
+
+config SYS_BOARD
+ default "km_arm"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "km_kirkwood"
+
+endif
diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS
new file mode 100644
index 0000000..079c803
--- /dev/null
+++ b/board/keymile/km_arm/MAINTAINERS
@@ -0,0 +1,14 @@
+KM_ARM BOARD
+M: Valentin Longchamp <valentin.longchamp@keymile.com>
+S: Maintained
+F: board/keymile/km_arm/
+F: include/configs/km_kirkwood.h
+F: configs/km_kirkwood_defconfig
+F: configs/km_kirkwood_128m16_defconfig
+F: configs/km_kirkwood_pci_defconfig
+F: configs/kmcoge5un_defconfig
+F: configs/kmnusa_defconfig
+F: configs/kmsugp1_defconfig
+F: configs/kmsuv31_defconfig
+F: configs/mgcoge3un_defconfig
+F: configs/portl2_defconfig
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
new file mode 100644
index 0000000..a17d8d9
--- /dev/null
+++ b/board/keymile/km_arm/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := km_arm.o ../common/common.o ../common/ivm.o
+
+ifdef CONFIG_KM_FPGA_CONFIG
+obj-y += fpga_config.o
+endif
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
new file mode 100644
index 0000000..51a3cfe
--- /dev/null
+++ b/board/keymile/km_arm/fpga_config.c
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/errno.h>
+
+/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
+#define KM_XLX_PROGRAM_B_PIN 39
+
+#define BOCO_ADDR 0x10
+
+#define ID_REG 0x00
+#define BOCO2_ID 0x5b
+
+static int check_boco2(void)
+{
+ int ret;
+ u8 id;
+
+ ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO id !!\n", __func__);
+ return ret;
+ }
+
+ return (id == BOCO2_ID);
+}
+
+static int boco_clear_bits(u8 reg, u8 flags)
+{
+ int ret;
+ u8 regval;
+
+ /* give access to the EEPROM from FPGA */
+ ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO @%#x !!\n",
+ __func__, reg);
+ return ret;
+ }
+ regval &= ~flags;
+ ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
+ if (ret) {
+ printf("%s: error writing the BOCO @%#x !!\n",
+ __func__, reg);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int boco_set_bits(u8 reg, u8 flags)
+{
+ int ret;
+ u8 regval;
+
+ /* give access to the EEPROM from FPGA */
+ ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO @%#x !!\n",
+ __func__, reg);
+ return ret;
+ }
+ regval |= flags;
+ ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
+ if (ret) {
+ printf("%s: error writing the BOCO @%#x !!\n",
+ __func__, reg);
+ return ret;
+ }
+
+ return 0;
+}
+
+#define SPI_REG 0x06
+#define CFG_EEPROM 0x02
+#define FPGA_PROG 0x04
+#define FPGA_INIT_B 0x10
+#define FPGA_DONE 0x20
+
+static int fpga_done(void)
+{
+ int ret = 0;
+ u8 regval;
+
+ /* this is only supported with the boco2 design */
+ if (!check_boco2())
+ return 0;
+
+ ret = i2c_read(BOCO_ADDR, SPI_REG, 1, ®val, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO @%#x !!\n",
+ __func__, SPI_REG);
+ return 0;
+ }
+
+ return regval & FPGA_DONE ? 1 : 0;
+}
+
+int skip;
+
+int trigger_fpga_config(void)
+{
+ int ret = 0;
+
+ /* if the FPGA is already configured, we do not want to
+ * reconfigure it */
+ skip = 0;
+ if (fpga_done()) {
+ printf("PCIe FPGA config: skipped\n");
+ skip = 1;
+ return 0;
+ }
+
+ if (check_boco2()) {
+ /* we have a BOCO2, this has to be triggered here */
+
+ /* make sure the FPGA_can access the EEPROM */
+ ret = boco_clear_bits(SPI_REG, CFG_EEPROM);
+ if (ret)
+ return ret;
+
+ /* trigger the config start */
+ ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B);
+ if (ret)
+ return ret;
+
+ /* small delay for the pulse */
+ udelay(10);
+
+ /* up signal for pulse end */
+ ret = boco_set_bits(SPI_REG, FPGA_PROG);
+ if (ret)
+ return ret;
+
+ /* finally, raise INIT_B to remove the config delay */
+ ret = boco_set_bits(SPI_REG, FPGA_INIT_B);
+ if (ret)
+ return ret;
+
+ } else {
+ /* we do it the old way, with the gpio pin */
+ kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
+ kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
+ /* small delay for the pulse */
+ udelay(10);
+ kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
+ }
+
+ return 0;
+}
+
+int wait_for_fpga_config(void)
+{
+ int ret = 0;
+ u8 spictrl;
+ u32 timeout = 20000;
+
+ if (skip)
+ return 0;
+
+ if (!check_boco2()) {
+ /* we do not have BOCO2, this is not really used */
+ return 0;
+ }
+
+ printf("PCIe FPGA config:");
+ do {
+ ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1);
+ if (ret) {
+ printf("%s: error reading the BOCO spictrl !!\n",
+ __func__);
+ return ret;
+ }
+ if (timeout-- == 0) {
+ printf(" FPGA_DONE timeout\n");
+ return -EFAULT;
+ }
+ udelay(10);
+ } while (!(spictrl & FPGA_DONE));
+
+ printf(" done\n");
+
+ return 0;
+}
+
+#if defined(KM_PCIE_RESET_MPP7)
+
+#define KM_PEX_RST_GPIO_PIN 7
+int fpga_reset(void)
+{
+ if (!check_boco2()) {
+ /* we do not have BOCO2, this is not really used */
+ return 0;
+ }
+
+ printf("PCIe reset through GPIO7: ");
+ /* apply PCIe reset via GPIO */
+ kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1);
+ kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1);
+ kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0);
+ udelay(1000*10);
+ kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1);
+
+ printf(" done\n");
+
+ return 0;
+}
+
+#else
+
+#define PRST1 0x4
+#define PCIE_RST 0x10
+#define TRAFFIC_RST 0x04
+
+int fpga_reset(void)
+{
+ int ret = 0;
+ u8 resets;
+
+ if (!check_boco2()) {
+ /* we do not have BOCO2, this is not really used */
+ return 0;
+ }
+
+ /* if we have skipped, we only want to reset the PCIe part */
+ resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
+
+ ret = boco_clear_bits(PRST1, resets);
+ if (ret)
+ return ret;
+
+ /* small delay for the pulse */
+ udelay(10);
+
+ ret = boco_set_bits(PRST1, resets);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#endif
+
+/* the FPGA was configured, we configure the BOCO2 so that the EEPROM
+ * is available from the Bobcat SPI bus */
+int toggle_eeprom_spi_bus(void)
+{
+ int ret = 0;
+
+ if (!check_boco2()) {
+ /* we do not have BOCO2, this is not really used */
+ return 0;
+ }
+
+ ret = boco_set_bits(SPI_REG, CFG_EEPROM);
+ if (ret)
+ return ret;
+
+ return 0;
+}
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
new file mode 100644
index 0000000..1c7c108
--- /dev/null
+++ b/board/keymile/km_arm/km_arm.c
@@ -0,0 +1,495 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <nand.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+
+#include "../common/common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * BOCO FPGA definitions
+ */
+#define BOCO 0x10
+#define REG_CTRL_H 0x02
+#define MASK_WRL_UNITRUN 0x01
+#define MASK_RBX_PGY_PRESENT 0x40
+#define REG_IRQ_CIRQ2 0x2d
+#define MASK_RBI_DEFECT_16 0x01
+
+/* Multi-Purpose Pins Functionality configuration */
+static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+#if defined(KM_PCIE_RESET_MPP7)
+ MPP7_GPO,
+#else
+ MPP7_PEX_RST_OUTn,
+#endif
+#if defined(CONFIG_SYS_I2C_SOFT)
+ MPP8_GPIO, /* SDA */
+ MPP9_GPIO, /* SCL */
+#endif
+#if defined(CONFIG_HARD_I2C)
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+#endif
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO, /* Reserved */
+ MPP13_UART1_TXD,
+ MPP14_UART1_RXD,
+ MPP15_GPIO, /* Not used */
+ MPP16_GPIO, /* Not used */
+ MPP17_GPIO, /* Reserved */
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO, /* CDL1 (input) */
+ MPP35_GPIO, /* CDL2 (input) */
+ MPP36_GPIO, /* MAIN_IRQ (input) */
+ MPP37_GPIO, /* BOARD_LED */
+ MPP38_GPIO, /* Piggy3 LED[1] */
+ MPP39_GPIO, /* Piggy3 LED[2] */
+ MPP40_GPIO, /* Piggy3 LED[3] */
+ MPP41_GPIO, /* Piggy3 LED[4] */
+ MPP42_GPIO, /* Piggy3 LED[5] */
+ MPP43_GPIO, /* Piggy3 LED[6] */
+ MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
+ MPP45_GPIO, /* Piggy3 LED[8] */
+ MPP46_GPIO, /* Reserved */
+ MPP47_GPIO, /* Reserved */
+ MPP48_GPIO, /* Reserved */
+ MPP49_GPIO, /* SW_INTOUTn */
+ 0
+};
+
+#if defined(CONFIG_KM_MGCOGE3UN)
+/*
+ * Wait for startup OK from mgcoge3ne
+ */
+static int startup_allowed(void)
+{
+ unsigned char buf;
+
+ /*
+ * Read CIRQ16 bit (bit 0)
+ */
+ if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
+ printf("%s: Error reading Boco\n", __func__);
+ else
+ if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
+ return 1;
+ return 0;
+}
+#endif
+
+#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
+/*
+ * All boards with PIGGY4 connected via a simple switch have ethernet always
+ * present.
+ */
+int ethernet_present(void)
+{
+ return 1;
+}
+#else
+int ethernet_present(void)
+{
+ uchar buf;
+ int ret = 0;
+
+ if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
+ printf("%s: Error reading Boco\n", __func__);
+ return -1;
+ }
+ if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
+ ret = 1;
+
+ return ret;
+}
+#endif
+
+static int initialize_unit_leds(void)
+{
+ /*
+ * Init the unit LEDs per default they all are
+ * ok apart from bootstat
+ */
+ uchar buf;
+
+ if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
+ printf("%s: Error reading Boco\n", __func__);
+ return -1;
+ }
+ buf |= MASK_WRL_UNITRUN;
+ if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
+ printf("%s: Error writing Boco\n", __func__);
+ return -1;
+ }
+ return 0;
+}
+
+static void set_bootcount_addr(void)
+{
+ uchar buf[32];
+ unsigned int bootcountaddr;
+ bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
+ sprintf((char *)buf, "0x%x", bootcountaddr);
+ setenv("bootcountaddr", (char *)buf);
+}
+
+int misc_init_r(void)
+{
+#if defined(CONFIG_KM_MGCOGE3UN)
+ char *wait_for_ne;
+ wait_for_ne = getenv("waitforne");
+ if (wait_for_ne != NULL) {
+ if (strcmp(wait_for_ne, "true") == 0) {
+ int cnt = 0;
+ int abort = 0;
+ puts("NE go: ");
+ while (startup_allowed() == 0) {
+ if (tstc()) {
+ (void) getc(); /* consume input */
+ abort = 1;
+ break;
+ }
+ udelay(200000);
+ cnt++;
+ if (cnt == 5)
+ puts("wait\b\b\b\b");
+ if (cnt == 10) {
+ cnt = 0;
+ puts(" \b\b\b\b");
+ }
+ }
+ if (abort == 1)
+ printf("\nAbort waiting for ne\n");
+ else
+ puts("OK\n");
+ }
+ }
+#endif
+
+ initialize_unit_leds();
+ set_km_env();
+ set_bootcount_addr();
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_SYS_I2C_SOFT)
+ u32 tmp;
+
+ /* set the 2 bitbang i2c pins as output gpios */
+ tmp = readl(MVEBU_GPIO0_BASE + 4);
+ writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
+#endif
+ /* adjust SDRAM size for bank 0 */
+ mvebu_sdram_size_adjust(0);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ /*
+ * The KM_FLASH_GPIO_PIN switches between using a
+ * NAND or a SPI FLASH. Set this pin on start
+ * to NAND mode.
+ */
+ kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
+ kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
+
+#if defined(CONFIG_SYS_I2C_SOFT)
+ /*
+ * Reinit the GPIO for I2C Bitbang driver so that the now
+ * available gpio framework is consistent. The calls to
+ * direction output in are not necessary, they are already done in
+ * board_early_init_f
+ */
+ kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
+ kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+ kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
+ kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
+#endif
+
+#if defined(CONFIG_KM_FPGA_CONFIG)
+ trigger_fpga_config();
+#endif
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_KMCOGE5UN)
+/* I/O pin to erase flash RGPP09 = MPP43 */
+#define KM_FLASH_ERASE_ENABLE 43
+ u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
+
+ /* if pin 1 do full erase */
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
+#endif
+
+#if defined(CONFIG_KM_FPGA_CONFIG)
+ wait_for_fpga_config();
+ fpga_reset();
+ toggle_eeprom_spi_bus();
+#endif
+ return 0;
+}
+
+int board_spi_claim_bus(struct spi_slave *slave)
+{
+ kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
+
+ return 0;
+}
+
+void board_spi_release_bus(struct spi_slave *slave)
+{
+ kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
+}
+
+#if (defined(CONFIG_KM_PIGGY4_88E6061))
+
+#define PHY_LED_SEL_REG 0x18
+#define PHY_LED0_LINK (0x5)
+#define PHY_LED1_ACT (0x8<<4)
+#define PHY_LED2_INT (0xe<<8)
+#define PHY_SPEC_CTRL_REG 0x1c
+#define PHY_RGMII_CLK_STABLE (0x1<<10)
+#define PHY_CLSA (0x1<<1)
+
+/* Configure and enable MV88E3018 PHY */
+void reset_phy(void)
+{
+ char *name = "egiga0";
+ unsigned short reg;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* RGMII clk transition on data stable */
+ if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
+ printf("Error reading PHY spec ctrl reg\n");
+ if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
+ reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
+ printf("Error writing PHY spec ctrl reg\n");
+
+ /* leds setup */
+ if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
+ PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
+ printf("Error writing PHY LED reg\n");
+
+ /* reset the phy */
+ miiphy_reset(name, CONFIG_PHY_BASE_ADR);
+}
+#elif defined(CONFIG_KM_PIGGY4_88E6352)
+
+#include <mv88e6352.h>
+
+#if defined(CONFIG_KM_NUSA)
+struct mv88e_sw_reg extsw_conf[] = {
+ /*
+ * port 0, PIGGY4, autoneg
+ * first the fix for the 1000Mbits Autoneg, this is from
+ * a Marvell errata, the regs are undocumented
+ */
+ { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
+ { PHY(0), PHY_STATUS, AN1000FIX },
+ { PHY(0), PHY_PAGE, 0 },
+ /* now the real port and phy configuration */
+ { PORT(0), PORT_PHY, NO_SPEED_FOR },
+ { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ { PHY(0), PHY_1000_CTRL, NO_ADV },
+ { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
+ { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
+ FULL_DUPLEX },
+ /* port 1, unused */
+ { PORT(1), PORT_CTRL, PORT_DIS },
+ { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 2, unused */
+ { PORT(2), PORT_CTRL, PORT_DIS },
+ { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 3, unused */
+ { PORT(3), PORT_CTRL, PORT_DIS },
+ { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 4, ICNEV, SerDes, SGMII */
+ { PORT(4), PORT_STATUS, NO_PHY_DETECT },
+ { PORT(4), PORT_PHY, SPEED_1000_FOR },
+ { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 5, CPU_RGMII */
+ { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
+ FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
+ FULL_DPX_FOR | SPEED_1000_FOR },
+ { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ /* port 6, unused, this port has no phy */
+ { PORT(6), PORT_CTRL, PORT_DIS },
+};
+#else
+struct mv88e_sw_reg extsw_conf[] = {};
+#endif
+
+void reset_phy(void)
+{
+#if defined(CONFIG_KM_MVEXTSW_ADDR)
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
+ ARRAY_SIZE(extsw_conf));
+ mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
+#endif
+}
+
+#else
+/* Configure and enable MV88E1118 PHY on the piggy*/
+void reset_phy(void)
+{
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* reset the phy */
+ miiphy_reset(name, CONFIG_PHY_BASE_ADR);
+}
+#endif
+
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var(void)
+{
+ ivm_read_eeprom();
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_I2C_SOFT)
+void set_sda(int state)
+{
+ I2C_ACTIVE;
+ I2C_SDA(state);
+}
+
+void set_scl(int state)
+{
+ I2C_SCL(state);
+}
+
+int get_sda(void)
+{
+ I2C_TRISTATE;
+ return I2C_READ;
+}
+
+int get_scl(void)
+{
+ return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
+}
+#endif
+
+#if defined(CONFIG_POST)
+
+#define KM_POST_EN_L 44
+#define POST_WORD_OFF 8
+
+int post_hotkeys_pressed(void)
+{
+#if defined(CONFIG_KM_COGE5UN)
+ return kw_gpio_get_value(KM_POST_EN_L);
+#else
+ return !kw_gpio_get_value(KM_POST_EN_L);
+#endif
+}
+
+ulong post_word_load(void)
+{
+ void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
+ return in_le32(addr);
+
+}
+void post_word_store(ulong value)
+{
+ void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
+ out_le32(addr, value);
+}
+
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ *vstart = CONFIG_SYS_SDRAM_BASE;
+
+ /* we go up to relocation plus a 1 MB margin */
+ *size = CONFIG_SYS_TEXT_BASE - (1<<20);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_EEPROM_WREN)
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+ kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
+
+ return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
+}
+#endif
diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg
new file mode 100644
index 0000000..e910f42
--- /dev/null
+++ b/board/keymile/km_arm/kwbimage-memphis.cfg
@@ -0,0 +1,181 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# (C) Copyright 2011
+# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
+# bit 3-0: MPPSel0 2, NF_IO[2]
+# bit 7-4: MPPSel1 2, NF_IO[3]
+# bit 12-8: MPPSel2 2, NF_IO[4]
+# bit 15-12: MPPSel3 2, NF_IO[5]
+# bit 19-16: MPPSel4 1, NF_IO[6]
+# bit 23-20: MPPSel5 1, NF_IO[7]
+# bit 27-24: MPPSel6 1, SYSRST_O
+# bit 31-28: MPPSel7 0, GPO[7]
+
+DATA 0xFFD10004 0x03303300
+
+DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
+# bit 3-0: MPPSel16 0, GPIO[16]
+# bit 7-4: MPPSel17 0, GPIO[17]
+# bit 12-8: MPPSel18 1, NF_IO[0]
+# bit 15-12: MPPSel19 1, NF_IO[1]
+# bit 19-16: MPPSel20 0, GPIO[20]
+# bit 23-20: MPPSel21 0, GPIO[21]
+# bit 27-24: MPPSel22 0, GPIO[22]
+# bit 31-28: MPPSel23 0, GPIO[23]
+
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
+
+#Dram initalization
+DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
+# bit13-0: 0x4E0 (DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
+# bit 3-0: 0 reserved
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A3E # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x00000001 # DDR Address Control
+# bit1-0: 01, Cs0width=x16
+# bit3-2: 00, Cs0size=2Gb
+# bit5-4: 00, Cs2width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000652 # DDR Mode
+DATA 0xFFD01420 0x00000006 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 1, DDR drive strenght reduced
+# bit2: 1, DDR ODT control lsd disabled
+# bit5-3: 000, required
+# bit6: 0, DDR ODT control msb disabled
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add a sample stage
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
+# bit3-0 : 0000, required
+# bit7-4 : 0010, M_ODT assertion 2 cycles after read
+# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
+# bit15-12: 0100, internal ODT assertion 4 cycles after read
+# bit19-16: 1000, internal ODT de-assertion 8 cycles after read
+# bit31-20: 0 , required
+
+DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High
+# bit3-0 : 0001, M_ODT assertion same cycle as write
+# bit7-4 : 0101, M_ODT de-assertion x cycles after write
+# bit11-8 : 0100, internal ODT assertion x cycles after write
+# bit15-12: 1000, internal ODT de-assertion x cycles after write
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+# bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 00, ODT1 controlled by register
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000F801 # CPU ODT Control
+# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
+# bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
+# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm
+# bit14 :1, STARTBURST ODT enabled
+# bit15 :1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+# bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg
new file mode 100644
index 0000000..ce2c3e2
--- /dev/null
+++ b/board/keymile/km_arm/kwbimage.cfg
@@ -0,0 +1,163 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
+# bit 3-0: MPPSel0 2, NF_IO[2]
+# bit 7-4: MPPSel1 2, NF_IO[3]
+# bit 12-8: MPPSel2 2, NF_IO[4]
+# bit 15-12: MPPSel3 2, NF_IO[5]
+# bit 19-16: MPPSel4 1, NF_IO[6]
+# bit 23-20: MPPSel5 1, NF_IO[7]
+# bit 27-24: MPPSel6 1, SYSRST_O
+# bit 31-28: MPPSel7 0, GPO[7]
+
+DATA 0xFFD10004 0x03303300
+
+DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
+# bit 3-0: MPPSel16 0, GPIO[16]
+# bit 7-4: MPPSel17 0, GPIO[17]
+# bit 12-8: MPPSel18 1, NF_IO[0]
+# bit 15-12: MPPSel19 1, NF_IO[1]
+# bit 19-16: MPPSel20 0, GPIO[20]
+# bit 23-20: MPPSel21 0, GPIO[21]
+# bit 27-24: MPPSel22 0, GPIO[22]
+# bit 31-28: MPPSel23 0, GPIO[23]
+
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
+
+#Dram initalization
+DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
+# bit13-0: 0x400 (DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
+# bit 3-0: 0 reserved
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000033 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000D # DDR Address Control
+# bit1-0: 01, Cs0width=x16
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs2width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000652 # DDR Mode
+DATA 0xFFD01420 0x00000044 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 1, DDR ODT control lsd disabled
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, enabled
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 0 , no sample stage
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+DATA 0xFFD01428 0x00074510
+DATA 0xFFD0147c 0x00007451
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
+# bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 00, ODT1 controlled by register
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control
+# bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit9-8: 1, ODTEn, never active
+# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+# bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg
new file mode 100644
index 0000000..71e3609
--- /dev/null
+++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg
@@ -0,0 +1,257 @@
+#
+# (C) Copyright 2010
+# Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# (C) Copyright 2012
+# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
+# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
+#
+# (C) Copyright 2012
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
+# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
+# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
+# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4 NF_IO[6]
+# bit 23-20: 1, MPPSel5 NF_IO[7]
+# bit 27-24: 1, MPPSel6 SYSRST_O
+# bit 31-28: 0, MPPSel7 GPO[7]
+
+DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
+# bit 3-0: 0, MPPSel8 GPIO[8]
+# bit 7-4: 0, MPPSel9 GPIO[9]
+# bit 12-8: 3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 UA1_TXD
+# bit 27-24: 3, MPPSel14 UA1_RXD
+# bit 31-28: 0, MPPSel15 GPIO[15]
+
+DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
+# bit 3-0: 0, MPPSel16 GPIO[16]
+# bit 7-4: 0, MPPSel17 not connected
+# bit 12-8: 1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
+# bit 2-0: 3, Reserved
+# bit 5-3: 3, Reserved
+# bit 6: 0, Reserved
+# bit 7: 0, RGMII-pads voltage = 3.3V
+# bit 10-8: 3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14: 0, Reserved
+# bit 15: 0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16 0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
+# bit 0-1: 2, Tag RAM RTC RAM0
+# bit 3-2: 1, Tag RAM WTC RAM0
+# bit 7-4: 6, Reserve
+# bit 9-8: 2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
+# bit 15-0: ???, Reserve
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ???,Reserve
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
+# bit 13-0: 0x4E0, DDR2 clks refresh rate
+# bit 14: 0, reserved
+# bit 15: 0, reserved
+# bit 16: 0, CPU to Dram Write buffer policy
+# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24: 1, enable exit self refresh mode on DDR access
+# bit 25: 1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
+# bit 3-0: 0, reserved
+# bit 4: 0, 2T mode =addr/cmd in same cycle
+# bit 5: 0, clk is driven during self refresh, we don't care for APX
+# bit 6: 0, use recommended falling edge of clk for addr/cmd
+# bit 7-11: 0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14: 0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18: 1, cpu lock transaction enabled
+# bit 19: 0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM
+# bit 30-28: 3, required
+# bit 31: 0,no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1)
+# bit 3-0: 0xE, TRAS, 15 clk (45 ns)
+# bit 7-4: 0x4, TRCD, 5 clk (15 ns)
+# bit 11-8: 0x4, TRP, 5 clk (15 ns)
+# bit 15-12: 0x4, TWR, 5 clk (15 ns)
+# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns)
+# bit 20: 0, extended TRAS msb
+# bit 23-21: 0, reserved
+# bit 27-24: 0x3, TRRD, 4 clk (10 ns)
+# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
+
+DATA 0xFFD0140C 0x0000003e # DDR Timing (High)
+# bit 6-0: 0x3E, TRFC, 63 clk (195 ns)
+# bit 8-7: 0, TR2R
+# bit 10-9: 0, TR2W
+# bit 12-11: 0, TW2W
+# bit 31-13: 0, reserved
+
+DATA 0xFFD01410 0x00000001 # DDR Address Control
+# bit 1-0: 1, Cs0width=x16
+# bit 3-2: 0, Cs0size=2Gb
+# bit 5-4: 0, Cs1width=nonexistent
+# bit 7-6: 0, Cs1size =nonexistent
+# bit 9-8: 0, Cs2width=nonexistent
+# bit 11-10: 0, Cs2size =nonexistent
+# bit 13-12: 0, Cs3width=nonexistent
+# bit 15-14: 0, Cs3size =nonexistent
+# bit 16: 0, Cs0AddrSel
+# bit 17: 0, Cs1AddrSel
+# bit 18: 0, Cs2AddrSel
+# bit 19: 0, Cs3AddrSel
+# bit 31-20: 0, required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit 0: 0, OpenPage enabled
+# bit 31-1: 0, required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit 3-0: 0, DDR cmd
+# bit 31-4: 0, required
+
+DATA 0xFFD0141C 0x00000652 # DDR Mode
+# bit 2-0: 2, Burst Length = 4
+# bit 3: 0, Burst Type
+# bit 6-4: 5, CAS Latency = 5
+# bit 7: 0, Test mode
+# bit 8: 0, DLL Reset
+# bit 11-9: 3, Write recovery for auto-precharge must be 3
+# bit 12: 0, Active power down exit time, fast exit
+# bit 14-13: 0, reserved
+# bit 31-15: 0, reserved
+
+DATA 0xFFD01420 0x00000006 # DDR Extended Mode
+# bit 0: 0, DDR DLL enabled
+# bit 1: 1, DDR drive strength reduced
+# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0]
+# bit 5-3: 0, required
+# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1]
+# bit 9-7: 0, required
+# bit 10: 0, differential DQS enabled
+# bit 11: 0, required
+# bit 12: 0, DDR output buffer enabled
+# bit 31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit 2-0: 7, required
+# bit 3: 1, MBUS Burst Chop disabled
+# bit 6-4: 7, required
+# bit 7: 0, reserved
+# bit 8: 1, add sample stage required for f > 266 MHz
+# bit 9: 0, no half clock cycle addition to dataout
+# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11: 0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16: 0, required
+
+DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
+# bit 3-0: 0, required
+# bit 7-4: 2, M_ODT assertion 2 cycles after read start command
+# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
+# (ODT turn off delay 2,5 clk cycles)
+# bit 15-12: 4, internal ODT time based on bit 7-4
+# with the considered SDRAM internal delay
+# bit 19-16: 8, internal ODT de-assertion based on bit 11-8
+# with the considered SDRAM internal delay
+# bit 31-20: 0, required
+
+DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
+# bit 3-0: 2, M_ODT assertion same as bit 11-8
+# bit 7-4: 5, M_ODT de-assertion same as bit 15-12
+# bit 11-8: 4, internal ODT assertion 2 cycles after write start command
+# with the considered SDRAM internal delay
+# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
+# with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+# bit 23-0: 0, reserved
+# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
+# bit 0: 1, Window enabled
+# bit 1: 0, Write Protect disabled
+# bit 3-2: 0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4: 0, ODT0Rd, MODT[1] not asserted
+# bit 11-8: 0, required
+# big 15-11: 0, required
+# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20: 0, ODT0Wr, MODT[1] not asserted
+# bit 27-24: 0, required
+# bit 31-28: 0, required
+
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2: 0, ODT1 controlled by register
+# bit 31-4: 0, required
+
+DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
+# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM
+# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr
+# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14: 1, STARTBURST ODT enabled
+# bit 15: 1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+# bit 0: 1, enable DDR init upon this register write
+# bit 31-1: 0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg
new file mode 100644
index 0000000..3934138
--- /dev/null
+++ b/board/keymile/km_arm/kwbimage_256M8_1.cfg
@@ -0,0 +1,259 @@
+#
+# (C) Copyright 2012
+# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com
+# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com
+# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+# This configuration applies to COGE5 design (ARM-part)
+# Two 8-Bit devices are connected on the 16-Bit bus on the same
+# chip-select. The supported devices are
+# MT47H256M8EB-3IT:C
+# MT47H256M8EB-25EIT:C
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
+# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
+# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
+# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
+# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5])
+# bit 19-16: 1, MPPSel4 NF_IO[6]
+# bit 23-20: 1, MPPSel5 NF_IO[7]
+# bit 27-24: 1, MPPSel6 SYSRST_O
+# bit 31-28: 0, MPPSel7 GPO[7]
+
+DATA 0xFFD10004 0x03303300 # MPP Control 1 Register
+# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged
+# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged
+# bit 12-8: 3, MPPSel10 UA0_TXD
+# bit 15-12: 3, MPPSel11 UA0_RXD
+# bit 19-16: 0, MPPSel12 not connected
+# bit 23-20: 3, MPPSel13 GPIO[14]
+# bit 27-24: 3, MPPSel14 GPIO[15]
+# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
+
+DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
+# bit 3-0: 0, MPPSel16 GPIO[16]
+# bit 7-4: 0, MPPSel17 not connected
+# bit 11-8: 1, MPPSel18 NF_IO[0]
+# bit 15-12: 1, MPPSel19 NF_IO[1]
+# bit 19-16: 0, MPPSel20 GPIO[20]
+# bit 23-20: 0, MPPSel21 GPIO[21]
+# bit 27-24: 0, MPPSel22 GPIO[22]
+# bit 31-28: 0, MPPSel23 GPIO[23]
+
+# MPP Control 3-6 Register untouched (MPP24-49)
+
+DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
+# bit 2-0: 3, Reserved
+# bit 5-3: 3, Reserved
+# bit 6: 0, Reserved
+# bit 7: 0, RGMII-pads voltage = 3.3V
+# bit 10-8: 3, Reserved
+# bit 13-11: 3, Reserved
+# bit 14: 0, Reserved
+# bit 15: 0, MPP RGMII-pads voltage = 3.3V
+# bit 31-16 0x1B1B, Reserved
+
+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
+# bit 0-1: 2, Tag RAM RTC RAM0
+# bit 3-2: 1, Tag RAM WTC RAM0
+# bit 7-4: 6, Reserved
+# bit 9-8: 2, Valid RAM RTC RAM
+# bit 11-10: 1, Valid RAM WTC RAM
+# bit 13-12: 2, Dirty RAM RTC RAM
+# bit 15-14: 1, Dirty RAM WTC RAM
+# bit 17-16: 2, Data RAM RTC RAM0
+# bit 19-18: 1, Data RAM WTC RAM0
+# bit 21-20: 2, Data RAM RTC RAM1
+# bit 23-22: 1, Data RAM WTC RAM1
+# bit 25-24: 2, Data RAM RTC RAM2
+# bit 27-26: 1, Data RAM WTC RAM2
+# bit 29-28: 2, Data RAM RTC RAM3
+# bit 31-30: 1, Data RAM WTC RAM4
+
+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
+# bit 15-0: ?, Reserved
+# bit 17-16: 2, ECC RAM RTC RAM0
+# bit 19-18: 1, ECC RAM WTC RAM0
+# bit 31-20: ?,Reserved
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
+
+# SDRAM initalization
+DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
+# bit 13-0: 0x4E0, DDR2 clks refresh rate
+# bit 14: 0, reserved
+# bit 15: 0, reserved
+# bit 16: 0, CPU to Dram Write buffer policy
+# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic
+# bit 19-18: 0, reserved
+# bit 23-20: 0, reserved
+# bit 24: 1, enable exit self refresh mode on DDR access
+# bit 25: 1, required
+# bit 29-26: 0, reserved
+# bit 31-30: 1, reserved
+
+DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
+# bit 3-0: 0, reserved
+# bit 4: 0, 2T mode =addr/cmd in same cycle
+# bit 5: 0, clk is driven during self refresh, we don't care for APX
+# bit 6: 0, use recommended falling edge of clk for addr/cmd
+# bit 7-11: 0, reserved
+# bit 12-13: 1, reserved, required 1
+# bit 14: 0, input buffer always powered up
+# bit 17-15: 0, reserved
+# bit 18: 1, cpu lock transaction enabled
+# bit 19: 0, reserved
+# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
+# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM
+# bit 30-28: 3, required
+# bit 31: 0, no additional STARTBURST delay
+
+DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1)
+# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles
+# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles
+# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles
+# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
+# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
+# bit 20: 0, extended TRAS msb
+# bit 23-21: 0, reserved
+# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
+# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
+
+DATA 0xFFD0140C 0x0000003E # DDR Timing (High)
+# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles
+# bit 8-7: 0, TR2R
+# bit 10-9: 0, TR2W
+# bit 12-11: 0, TW2W
+# bit 31-13: 0, reserved
+
+DATA 0xFFD01410 0x00000000 # DDR Address Control
+# bit 1-0: 0, Cs0width=x8 (2 devices)
+# bit 3-2: 0, Cs0size=2Gb
+# bit 5-4: 0, Cs1width=nonexistent
+# bit 7-6: 0, Cs1size =nonexistent
+# bit 9-8: 0, Cs2width=nonexistent
+# bit 11-10: 0, Cs2size =nonexistent
+# bit 13-12: 0, Cs3width=nonexistent
+# bit 15-14: 0, Cs3size =nonexistent
+# bit 16: 0, Cs0AddrSel
+# bit 17: 0, Cs1AddrSel
+# bit 18: 0, Cs2AddrSel
+# bit 19: 0, Cs3AddrSel
+# bit 31-20: 0, required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit 0: 0, OpenPage enabled
+# bit 31-1: 0, required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit 3-0: 0, DDR cmd
+# bit 31-4: 0, required
+
+DATA 0xFFD0141C 0x00000652 # DDR Mode
+# bit 2-0: 2, Burst Length = 4
+# bit 3: 0, Burst Type
+# bit 6-4: 5, CAS Latency = 5
+# bit 7: 0, Test mode
+# bit 8: 0, DLL Reset
+# bit 11-9: 3, Write recovery for auto-precharge must be 3
+# bit 12: 0, Active power down exit time, fast exit
+# bit 14-13: 0, reserved
+# bit 31-15: 0, reserved
+
+DATA 0xFFD01420 0x00000006 # DDR Extended Mode
+# bit 0: 0, DDR DLL enabled
+# bit 1: 1, DDR drive strenght reduced
+# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0]
+# bit 5-3: 0, required
+# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1]
+# bit 9-7: 0, required
+# bit 10: 0, differential DQS enabled
+# bit 11: 0, required
+# bit 12: 0, DDR output buffer enabled
+# bit 31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit 2-0: 7, required
+# bit 3: 1, MBUS Burst Chop disabled
+# bit 6-4: 7, required
+# bit 7: 0, reserved
+# bit 8: 1, add sample stage required for > 266Mhz
+# bit 9: 0, no half clock cycle addition to dataout
+# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit 11: 0, 1/4 clock cycle skew disabled for write mesh
+# bit 15-12:0xf, required
+# bit 31-16: 0, required
+
+DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
+# bit 3-0: 0, required
+# bit 7-4: 2, M_ODT assertion 2 cycles after read start command
+# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
+# (ODT turn off delay 2,5 clk cycles)
+# bit 15-12: 4, internal ODT time based on bit 7-4
+# with the considered SDRAM internal delay
+# bit 19-16: 8, internal ODT de-assertion based on bit 11-8
+# with the considered SDRAM internal delay
+# bit 31-20: 0, required
+
+DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
+# bit 3-0: 2, M_ODT assertion same as bit 11-8
+# bit 7-4: 5, M_ODT de-assertion same as bit 15-12
+# bit 11-8: 4, internal ODT assertion 2 cycles after write start command
+# with the considered SDRAM internal delay
+# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
+# with the considered SDRAM internal delay
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+# bit 23-0: 0, reserved
+# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
+
+DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
+# bit 0: 1, Window enabled
+# bit 1: 0, Write Protect disabled
+# bit 3-2: 0, CS0 hit selected
+# bit 23-4:ones, required
+# bit 31-24:0x1F, Size (i.e. 512MB)
+
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
+# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
+# bit 7-4: 0, ODT0Rd, MODT[1] not asserted
+# bit 11-8: 0, required
+# big 15-11: 0, required
+# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+# bit 23-20: 0, ODT0Wr, MODT[1] not asserted
+# bit 27-24: 0, required
+# bit 31-28: 0, required
+
+DATA 0xFFD01498 0x00000004 # DDR ODT Control (High)
+# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
+# bit 3-2: 1, ODT1 never active
+# bit 31-4: 0, required
+
+DATA 0xFFD0149C 0x0000E801 # CPU ODT Control
+# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
+# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
+# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
+# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
+# bit 14: 1, STARTBURST ODT enabled
+# bit 15: 1, Use ODT Block
+
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+# bit 0: 1, enable DDR init upon this register write
+# bit 31-1: 0, reserved
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/keymile/kmp204x/Kconfig b/board/keymile/kmp204x/Kconfig
new file mode 100644
index 0000000..7b45a13
--- /dev/null
+++ b/board/keymile/kmp204x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_KMP204X
+
+config SYS_BOARD
+ default "kmp204x"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmp204x"
+
+endif
diff --git a/board/keymile/kmp204x/MAINTAINERS b/board/keymile/kmp204x/MAINTAINERS
new file mode 100644
index 0000000..93b6bad
--- /dev/null
+++ b/board/keymile/kmp204x/MAINTAINERS
@@ -0,0 +1,7 @@
+KMP204X BOARD
+M: Valentin Longchamp <valentin.longchamp@keymile.com>
+S: Maintained
+F: board/keymile/kmp204x/
+F: include/configs/kmp204x.h
+F: configs/kmcoge4_defconfig
+F: configs/kmlion1_defconfig
diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile
new file mode 100644
index 0000000..c57ca08
--- /dev/null
+++ b/board/keymile/kmp204x/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2001-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o qrio.o \
+ ../common/common.o ../common/ivm.o
diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c
new file mode 100644
index 0000000..34ac697
--- /dev/null
+++ b/board/keymile/kmp204x/ddr.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ if (ctrl_num) {
+ printf("Wrong parameter for controller number %d", ctrl_num);
+ return;
+ }
+
+ /* automatic calibration for nb of cycles between read and DQS pre */
+ popts->cpo_override = 0xFF;
+
+ /* 1/2 clk delay between wr command and data strobe */
+ popts->write_data_delay = 4;
+ /* clk lauched 1/2 applied cylcle after address command */
+ popts->clk_adjust = 4;
+ /* 1T timing: command/address held for only 1 cycle */
+ popts->twot_en = 0;
+
+ /* we have only one module, half str should be OK */
+ popts->half_strength_driver_enable = 1;
+
+ /* wrlvl values overriden as recommended by ddr init func */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x6;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size = 0;
+
+ puts("Initializing with SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ debug(" DDR: ");
+ return dram_size;
+}
diff --git a/board/keymile/kmp204x/eth.c b/board/keymile/kmp204x/eth.c
new file mode 100644
index 0000000..a073105
--- /dev/null
+++ b/board/keymile/kmp204x/eth.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <phy.h>
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+#ifdef CONFIG_FMAN_ENET
+ struct fsl_pq_mdio_info dtsec_mdio_info;
+
+ printf("Initializing Fman\n");
+
+ dtsec_mdio_info.regs =
+ (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the real 1G MDIO bus */
+ fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+ /* DTESC1/2 don't have a PHY, they are temporarily disabled
+ * so that u-boot doesn't try to unsuccessfuly enable them */
+ fm_disable_port(FM1_DTSEC1);
+ fm_disable_port(FM1_DTSEC2);
+
+ /*
+ * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf
+ * This is the debug interface, the only one used in u-boot
+ */
+ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ fm_info_set_mdio(FM1_DTSEC5,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+
+ ret = cpu_eth_init(bis);
+
+ /* reenable DTSEC1/2 for later (kernel) */
+ fm_enable_port(FM1_DTSEC1);
+ fm_enable_port(FM1_DTSEC2);
+#endif
+
+ return ret;
+}
+
+#if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL)
+
+#define mv88E1118_PAGE_REG 22
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) {
+ /* driver config is good */
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ /* but we still need to fix the LEDs */
+ phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840);
+ phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000);
+ }
+
+ return 0;
+}
+#endif
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
new file mode 100644
index 0000000..a74f75b
--- /dev/null
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -0,0 +1,304 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2011,2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/common.h"
+#include "kmp204x.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);
+
+ return 0;
+}
+
+/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
+ * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
+ * For I2C only the low state is activly driven and high state is pulled-up
+ * by a resistor. Therefore the deblock GPIOs are used
+ * -> as an active output to drive a low state
+ * -> as an open-drain input to have a pulled-up high state
+ */
+
+/* QRIO GPIOs used for deblocking */
+#define DEBLOCK_PORT1 GPIO_A
+#define DEBLOCK_SCL1 20
+#define DEBLOCK_SDA1 21
+
+/* By default deblock GPIOs are floating */
+static void i2c_deblock_gpio_cfg(void)
+{
+ /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
+ qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
+ qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
+
+ qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
+ qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
+}
+
+void set_sda(int state)
+{
+ qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
+}
+
+void set_scl(int state)
+{
+ qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
+}
+
+int get_sda(void)
+{
+ return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
+}
+
+int get_scl(void)
+{
+ return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
+}
+
+
+#define ZL30158_RST 8
+#define BFTIC4_RST 0
+#define RSTRQSR1_WDT_RR 0x00200000
+#define RSTRQSR1_SW_RR 0x00100000
+
+int board_early_init_f(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ bool cpuwd_flag = false;
+
+ /* configure mode for uP reset request */
+ qrio_uprstreq(UPREQ_CORE_RST);
+
+ /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
+ setbits_be32(&gur->ddrclkdr, 0x001f000f);
+
+ /* set reset reason according CPU register */
+ if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
+ RSTRQSR1_WDT_RR)
+ cpuwd_flag = true;
+
+ qrio_cpuwd_flag(cpuwd_flag);
+ /* clear CPU bits by writing 1 */
+ setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
+
+ /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable WD on it */
+ qrio_wdmask(BFTIC4_RST, true);
+
+ /* set the ZL30138's prstcfg to reset at power-up only */
+ qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
+ /* and take it out of reset as soon as possible (needed for Hooper) */
+ qrio_prst(ZL30158_RST, false, false);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ int ret = 0;
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ set_liodns();
+ setup_portals();
+
+ ret = trigger_fpga_config();
+ if (ret)
+ printf("error triggering PCIe FPGA config\n");
+
+ /* enable the Unit LED (red) & Boot LED (on) */
+ qrio_set_leds();
+
+ /* enable Application Buffer */
+ qrio_enable_app_buffer();
+
+ return ret;
+}
+
+unsigned long get_board_sys_clk(unsigned long dummy)
+{
+ return 66666666;
+}
+
+#define ETH_FRONT_PHY_RST 15
+#define QSFP2_RST 11
+#define QSFP1_RST 10
+#define ZL30343_RST 9
+
+int misc_init_f(void)
+{
+ /* configure QRIO pis for i2c deblocking */
+ i2c_deblock_gpio_cfg();
+
+ /* configure the front phy's prstcfg and take it out of reset */
+ qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prst(ETH_FRONT_PHY_RST, false, false);
+
+ /* set the ZL30343 prstcfg to reset at power-up only */
+ qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
+ /* and enable the WD on it */
+ qrio_wdmask(ZL30343_RST, true);
+
+ /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
+ qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
+
+ /* and enable the WD on them */
+ qrio_wdmask(QSFP1_RST, true);
+ qrio_wdmask(QSFP2_RST, true);
+
+ return 0;
+}
+
+#define NUM_SRDS_BANKS 2
+
+int misc_init_r(void)
+{
+ serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
+ SRDS_PLLCR0_RFCK_SEL_125};
+ unsigned int i;
+
+ /* check SERDES reference clocks */
+ for (i = 0; i < NUM_SRDS_BANKS; i++) {
+ u32 actual = in_be32(®s->bank[i].pllcr0);
+ actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
+ if (actual != expected[i]) {
+ printf("Warning: SERDES bank %u expects reference \
+ clock %sMHz, but actual is %sMHz\n", i + 1,
+ serdes_clock_to_string(expected[i]),
+ serdes_clock_to_string(actual));
+ }
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var(void)
+{
+ ivm_read_eeprom();
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_LAST_STAGE_INIT)
+
+int last_stage_init(void)
+{
+#if defined(CONFIG_KMCOGE4)
+ /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
+ struct bfticu_iomap *bftic4 =
+ (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
+ u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
+
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
+#endif
+ set_km_env();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+void fdt_fixup_fman_mac_addresses(void *blob)
+{
+ int node, i, ret;
+ char *tmp, *end;
+ unsigned char mac_addr[6];
+
+ /* get the mac addr from env */
+ tmp = getenv("ethaddr");
+ if (!tmp) {
+ printf("ethaddr env variable not defined\n");
+ return;
+ }
+ for (i = 0; i < 6; i++) {
+ mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
+ if (tmp)
+ tmp = (*end) ? end+1 : end;
+ }
+
+ /* find the correct fdt ethernet path and correct it */
+ node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
+ if (node < 0) {
+ printf("no /soc/fman/ethernet path offset\n");
+ return;
+ }
+ ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
+ if (ret) {
+ printf("error setting local-mac-address property\n");
+ return;
+ }
+}
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_fman_mac_addresses(blob);
+#endif
+
+ return 0;
+}
+
+#if defined(CONFIG_POST)
+
+/* DIC26_SELFTEST GPIO used to start factory test sw */
+#define SELFTEST_PORT GPIO_A
+#define SELFTEST_PIN 31
+
+int post_hotkeys_pressed(void)
+{
+ qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
+ return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
+}
+#endif
diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h
new file mode 100644
index 0000000..e90e8ab
--- /dev/null
+++ b/board/keymile/kmp204x/kmp204x.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* QRIO GPIO ports */
+#define GPIO_A 0x40
+#define GPIO_B 0x60
+
+int qrio_get_gpio(u8 port_off, u8 gpio_nr);
+void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val);
+void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value);
+void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value);
+void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr);
+
+#define PRSTCFG_POWUP_UNIT_CORE_RST 0x0
+#define PRSTCFG_POWUP_UNIT_RST 0x1
+#define PRSTCFG_POWUP_RST 0x3
+
+void qrio_prst(u8 bit, bool en, bool wden);
+void qrio_wdmask(u8 bit, bool wden);
+void qrio_prstcfg(u8 bit, u8 mode);
+void qrio_set_leds(void);
+void qrio_enable_app_buffer(void);
+void qrio_cpuwd_flag(bool flag);
+int qrio_reset_reason(void);
+
+#define UPREQ_UNIT_RST 0x0
+#define UPREQ_CORE_RST 0x1
+
+void qrio_uprstreq(u8 mode);
+
+void pci_of_setup(void *blob, bd_t *bd);
diff --git a/board/keymile/kmp204x/law.c b/board/keymile/kmp204x/law.c
new file mode 100644
index 0000000..75d69e8
--- /dev/null
+++ b/board/keymile/kmp204x/law.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
+#endif
+ SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
+ SET_LAW(CONFIG_SYS_LBAPP1_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#endif
+#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
+ SET_LAW(CONFIG_SYS_LBAPP2_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/keymile/kmp204x/pbi.cfg b/board/keymile/kmp204x/pbi.cfg
new file mode 100644
index 0000000..1e0a171
--- /dev/null
+++ b/board/keymile/kmp204x/pbi.cfg
@@ -0,0 +1,76 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer docs/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Configure ALTCBAR for DCSR -> DCSR@89000000
+091380c0 000009C4
+09000010 00000000
+091380c0 000009C4
+09000014 00000000
+091380c0 000009C4
+09000018 81d00000
+#Workaround for A-004849
+091380c0 000009C4
+890B0050 00000002
+091380c0 000009C4
+890B0054 00000002
+091380c0 000009C4
+890B0058 00000002
+091380c0 000009C4
+890B005C 00000002
+091380c0 000009C4
+890B0090 00000002
+091380c0 000009C4
+890B0094 00000002
+091380c0 000009C4
+890B0098 00000002
+091380c0 000009C4
+890B009C 00000002
+091380c0 000009C4
+890B0108 00000012
+091380c0 000009C4
+#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
+89021008 0000f000
+091380c0 000009C4
+89021028 0000f000
+091380c0 000009C4
+89021048 0000f000
+091380c0 000009C4
+89021068 0000f000
+091380c0 000009C4
+#Flush PBL data
+09138000 00000000
+#Disable ALTCBAR
+09000018 00000000
+091380c0 000009C4
+#Initialize CPC1 as 1MB SRAM
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+09010100 00000000
+09010104 fff0000b
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff00000
+09000d08 81000013
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 27170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c
new file mode 100644
index 0000000..2b0b054
--- /dev/null
+++ b/board/keymile/kmp204x/pci.c
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+#include <asm/errno.h>
+
+#include "kmp204x.h"
+
+#define PROM_SEL_L 11
+/* control the PROM_SEL_L signal*/
+static void toggle_fpga_eeprom_bus(bool cpu_own)
+{
+ qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own);
+}
+
+#define CONF_SEL_L 10
+#define FPGA_PROG_L 19
+#define FPGA_DONE 18
+#define FPGA_INIT_L 17
+
+int trigger_fpga_config(void)
+{
+ int ret = 0, init_l;
+ /* approx 10ms */
+ u32 timeout = 10000;
+
+ /* make sure the FPGA_can access the EEPROM */
+ toggle_fpga_eeprom_bus(false);
+
+ /* assert CONF_SEL_L to be able to drive FPGA_PROG_L */
+ qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0);
+
+ /* trigger the config start */
+ qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0);
+
+ /* small delay for INIT_L line */
+ udelay(10);
+
+ /* wait for FPGA_INIT to be asserted */
+ do {
+ init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L);
+ if (timeout-- == 0) {
+ printf("FPGA_INIT timeout\n");
+ ret = -EFAULT;
+ break;
+ }
+ udelay(10);
+ } while (init_l);
+
+ /* deassert FPGA_PROG, config should start */
+ qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1);
+
+ return ret;
+}
+
+/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */
+static int wait_for_fpga_config(void)
+{
+ int ret = 0, done;
+ /* approx 5 s */
+ u32 timeout = 500000;
+
+ printf("PCIe FPGA config:");
+ do {
+ done = qrio_get_gpio(GPIO_A, FPGA_DONE);
+ if (timeout-- == 0) {
+ printf(" FPGA_DONE timeout\n");
+ ret = -EFAULT;
+ goto err_out;
+ }
+ udelay(10);
+ } while (!done);
+
+ printf(" done\n");
+
+err_out:
+ /* deactive CONF_SEL and give the CPU conf EEPROM access */
+ qrio_set_gpio(GPIO_A, CONF_SEL_L, 1);
+ toggle_fpga_eeprom_bus(true);
+
+ return ret;
+}
+
+#define PCIE_SW_RST 14
+#define PEXHC_RST 13
+#define HOOPER_RST 12
+
+void pci_init_board(void)
+{
+ qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+
+ /* wait for the PCIe FPGA to be configured
+ * it has been triggered earlier in board_early_init_r */
+ if (wait_for_fpga_config())
+ printf("error finishing PCIe FPGA config\n");
+
+ qrio_prst(PCIE_SW_RST, false, false);
+ qrio_prst(PEXHC_RST, false, false);
+ qrio_prst(HOOPER_RST, false, false);
+ /* Hooper is not direcly PCIe capable */
+ mdelay(50);
+
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/keymile/kmp204x/qrio.c b/board/keymile/kmp204x/qrio.c
new file mode 100644
index 0000000..edf3bf1
--- /dev/null
+++ b/board/keymile/kmp204x/qrio.c
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include "../common/common.h"
+#include "kmp204x.h"
+
+/* QRIO GPIO register offsets */
+#define DIRECT_OFF 0x18
+#define GPRT_OFF 0x1c
+
+int qrio_get_gpio(u8 port_off, u8 gpio_nr)
+{
+ u32 gprt;
+
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ gprt = in_be32(qrio_base + port_off + GPRT_OFF);
+
+ return (gprt >> gpio_nr) & 1U;
+}
+
+void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value)
+{
+ u32 gprt, mask;
+
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ mask = 1U << gpio_nr;
+
+ gprt = in_be32(qrio_base + port_off + GPRT_OFF);
+ if (value)
+ gprt |= mask;
+ else
+ gprt &= ~mask;
+
+ out_be32(qrio_base + port_off + GPRT_OFF, gprt);
+}
+
+void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value)
+{
+ u32 direct, mask;
+
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ mask = 1U << gpio_nr;
+
+ direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+ direct |= mask;
+ out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+
+ qrio_set_gpio(port_off, gpio_nr, value);
+}
+
+void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr)
+{
+ u32 direct, mask;
+
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ mask = 1U << gpio_nr;
+
+ direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+ direct &= ~mask;
+ out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+}
+
+void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val)
+{
+ u32 direct, mask;
+
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ mask = 1U << gpio_nr;
+
+ direct = in_be32(qrio_base + port_off + DIRECT_OFF);
+ if (val == 0)
+ /* set to output -> GPIO drives low */
+ direct |= mask;
+ else
+ /* set to input -> GPIO floating */
+ direct &= ~mask;
+
+ out_be32(qrio_base + port_off + DIRECT_OFF, direct);
+}
+
+#define WDMASK_OFF 0x16
+
+void qrio_wdmask(u8 bit, bool wden)
+{
+ u16 wdmask;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ wdmask = in_be16(qrio_base + WDMASK_OFF);
+
+ if (wden)
+ wdmask |= (1 << bit);
+ else
+ wdmask &= ~(1 << bit);
+
+ out_be16(qrio_base + WDMASK_OFF, wdmask);
+}
+
+#define PRST_OFF 0x1a
+
+void qrio_prst(u8 bit, bool en, bool wden)
+{
+ u16 prst;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ qrio_wdmask(bit, wden);
+
+ prst = in_be16(qrio_base + PRST_OFF);
+
+ if (en)
+ prst &= ~(1 << bit);
+ else
+ prst |= (1 << bit);
+
+ out_be16(qrio_base + PRST_OFF, prst);
+}
+
+#define PRSTCFG_OFF 0x1c
+
+void qrio_prstcfg(u8 bit, u8 mode)
+{
+ u32 prstcfg;
+ u8 i;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
+
+ for (i = 0; i < 2; i++) {
+ if (mode & (1<<i))
+ set_bit(2*bit+i, &prstcfg);
+ else
+ clear_bit(2*bit+i, &prstcfg);
+ }
+
+ out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
+}
+
+#define CTRLH_OFF 0x02
+#define CTRLH_WRL_BOOT 0x01
+#define CTRLH_WRL_UNITRUN 0x02
+
+void qrio_set_leds(void)
+{
+ u8 ctrlh;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ /* set UNIT LED to RED and BOOT LED to ON */
+ ctrlh = in_8(qrio_base + CTRLH_OFF);
+ ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN);
+ out_8(qrio_base + CTRLH_OFF, ctrlh);
+}
+
+#define CTRLL_OFF 0x03
+#define CTRLL_WRB_BUFENA 0x20
+
+void qrio_enable_app_buffer(void)
+{
+ u8 ctrll;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ /* enable application buffer */
+ ctrll = in_8(qrio_base + CTRLL_OFF);
+ ctrll |= (CTRLL_WRB_BUFENA);
+ out_8(qrio_base + CTRLL_OFF, ctrll);
+}
+
+#define REASON1_OFF 0x12
+#define REASON1_CPUWD 0x01
+
+void qrio_cpuwd_flag(bool flag)
+{
+ u8 reason1;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+ reason1 = in_8(qrio_base + REASON1_OFF);
+ if (flag)
+ reason1 |= REASON1_CPUWD;
+ else
+ reason1 &= ~REASON1_CPUWD;
+ out_8(qrio_base + REASON1_OFF, reason1);
+}
+
+#define RSTCFG_OFF 0x11
+
+void qrio_uprstreq(u8 mode)
+{
+ u32 rstcfg;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ rstcfg = in_8(qrio_base + RSTCFG_OFF);
+
+ if (mode & UPREQ_CORE_RST)
+ rstcfg |= UPREQ_CORE_RST;
+ else
+ rstcfg &= ~UPREQ_CORE_RST;
+
+ out_8(qrio_base + RSTCFG_OFF, rstcfg);
+}
diff --git a/board/keymile/kmp204x/rcw_kmp204x.cfg b/board/keymile/kmp204x/rcw_kmp204x.cfg
new file mode 100644
index 0000000..236d513
--- /dev/null
+++ b/board/keymile/kmp204x/rcw_kmp204x.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for kmp204x boards
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+14600000 00000000 28200000 00000000
+148E70CF CFC02000 58000000 41000000
+00000000 00000000 00000000 F0428816
+00000000 00000000 00000000 00000000
diff --git a/board/keymile/kmp204x/tlb.c b/board/keymile/kmp204x/tlb.c
new file mode 100644
index 0000000..d03ca80
--- /dev/null
+++ b/board/keymile/kmp204x/tlb.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ /* TLB 1 */
+ /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+ /* QRIO */
+ SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_64K, 1),
+ /* *I*G* - PCI1 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_512M, 1),
+ /* *I*G* - PCI3 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_512M, 1),
+ /* *I*G* - PCI1&3 I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_128K, 1),
+#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
+ /* LBAPP1 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256M, 1),
+#endif
+#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
+ /* LBAPP2 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_256M, 1),
+#endif
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_32K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/keymile/scripts/README b/board/keymile/scripts/README
new file mode 100644
index 0000000..dd935b2
--- /dev/null
+++ b/board/keymile/scripts/README
@@ -0,0 +1,31 @@
+These scripts are needed for our development usecases. Copy this directory
+into your tftp root directory to be able to use this scripts.
+cp -r <u-boot-repo>/board/keymile/scripts <your_tftp_root>/
+
+To load and configure these usecase, two environment variables in the u-boot
+default environment must be parsed:
+run develop : setup environment to configure for rootfs via nfs
+run ramfs : setup environment to configure for rootfs in ram
+
+Last change: 24.11.2011
+
+develop-common.txt
+============================
+This file defines variables for working with rootfs via nfs for powerpc and
+arm.
+
+develop-<arch>.txt
+============================
+This file defines architecture specific variables for working with rootfs via
+nfs arm.
+
+
+ramfs-common.txt
+============================
+This file defines variables for working with rootfs inside the ram for powerpc
+and arm.
+
+ramfs-<arch>.txt
+============================
+This file defines architecture specific variables for working with rootfs inside
+ram.
diff --git a/board/keymile/scripts/develop-arm.txt b/board/keymile/scripts/develop-arm.txt
new file mode 100644
index 0000000..d3c974f
--- /dev/null
+++ b/board/keymile/scripts/develop-arm.txt
@@ -0,0 +1 @@
+setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt
new file mode 100644
index 0000000..a80812a
--- /dev/null
+++ b/board/keymile/scripts/develop-common.txt
@@ -0,0 +1,10 @@
+altbootcmd=run ${subbootcmds}
+bootcmd=run ${subbootcmds}
+configure=run set_uimage; km_setboardid && saveenv && reset
+subbootcmds=tftpfdt tftpkernel nfsargs add_default boot
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch}
+tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi
+tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage}
+toolchain=/opt/eldk
+rootfssize=0
+set_uimage=printenv uimage || setenv uimage uImage
diff --git a/board/keymile/scripts/develop-ppc_82xx.txt b/board/keymile/scripts/develop-ppc_82xx.txt
new file mode 100644
index 0000000..d3c974f
--- /dev/null
+++ b/board/keymile/scripts/develop-ppc_82xx.txt
@@ -0,0 +1 @@
+setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
diff --git a/board/keymile/scripts/develop-ppc_8xx.txt b/board/keymile/scripts/develop-ppc_8xx.txt
new file mode 100644
index 0000000..d3c974f
--- /dev/null
+++ b/board/keymile/scripts/develop-ppc_8xx.txt
@@ -0,0 +1 @@
+setup_debug_env=tftpboot 0x200000 scripts/develop-common.txt && env import -t 0x200000 ${filesize} && run configure
diff --git a/board/keymile/scripts/ramfs-arm.txt b/board/keymile/scripts/ramfs-arm.txt
new file mode 100644
index 0000000..87e984e
--- /dev/null
+++ b/board/keymile/scripts/ramfs-arm.txt
@@ -0,0 +1 @@
+setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
diff --git a/board/keymile/scripts/ramfs-common.txt b/board/keymile/scripts/ramfs-common.txt
new file mode 100644
index 0000000..d79ad2e
--- /dev/null
+++ b/board/keymile/scripts/ramfs-common.txt
@@ -0,0 +1,13 @@
+addramfs=setenv bootargs "${bootargs} phram.phram=rootfs${boot_bank},${rootfsaddr},${rootfssize}"
+boot_bank=-1
+altbootcmd=run ${subbootcmds}
+bootcmd=run ${subbootcmds}
+subbootcmds=tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}
+configure=run set_uimage; km_setboardid && saveenv && reset
+rootfsfile=${hostname}/rootfsImage
+setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value}
+tftpfdt=if run set_fdthigh || test ${arch} != arm; then tftpboot ${fdt_addr_r} ${hostname}/${hostname}.dtb; else true; fi
+tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage}
+tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage
+set_uimage=printenv uimage || setenv uimage uImage
diff --git a/board/keymile/scripts/ramfs-ppc_82xx.txt b/board/keymile/scripts/ramfs-ppc_82xx.txt
new file mode 100644
index 0000000..87e984e
--- /dev/null
+++ b/board/keymile/scripts/ramfs-ppc_82xx.txt
@@ -0,0 +1 @@
+setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
diff --git a/board/keymile/scripts/ramfs-ppc_8xx.txt b/board/keymile/scripts/ramfs-ppc_8xx.txt
new file mode 100644
index 0000000..87e984e
--- /dev/null
+++ b/board/keymile/scripts/ramfs-ppc_8xx.txt
@@ -0,0 +1 @@
+setup_debug_env=tftpboot 0x200000 scripts/ramfs-common.txt && env import -t 0x200000 ${filesize} && run configure
diff --git a/board/kmc/kzm9g/Kconfig b/board/kmc/kzm9g/Kconfig
new file mode 100644
index 0000000..f163efd
--- /dev/null
+++ b/board/kmc/kzm9g/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_KZM9G
+
+config SYS_BOARD
+ default "kzm9g"
+
+config SYS_VENDOR
+ default "kmc"
+
+config SYS_CONFIG_NAME
+ default "kzm9g"
+
+endif
diff --git a/board/kmc/kzm9g/MAINTAINERS b/board/kmc/kzm9g/MAINTAINERS
new file mode 100644
index 0000000..411efd1
--- /dev/null
+++ b/board/kmc/kzm9g/MAINTAINERS
@@ -0,0 +1,7 @@
+KZM9G BOARD
+M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+M: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
+S: Maintained
+F: board/kmc/kzm9g/
+F: include/configs/kzm9g.h
+F: configs/kzm9g_defconfig
diff --git a/board/kmc/kzm9g/Makefile b/board/kmc/kzm9g/Makefile
new file mode 100644
index 0000000..7989884
--- /dev/null
+++ b/board/kmc/kzm9g/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+# (C) Copyright 2012 Renesas Solutions Corp.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := kzm9g.o
diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c
new file mode 100644
index 0000000..ea36fa4
--- /dev/null
+++ b/board/kmc/kzm9g/kzm9g.c
@@ -0,0 +1,374 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <netdev.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CS0BCR_D (0x06C00400)
+#define CS4BCR_D (0x16c90400)
+#define CS0WCR_D (0x55062C42)
+#define CS4WCR_D (0x1e071dc3)
+
+#define CMNCR_BROMMD0 (1 << 21)
+#define CMNCR_BROMMD1 (1 << 22)
+#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1)
+#define VCLKCR1_D (0x27)
+
+#define SMSTPCR1_CMT0 (1 << 24)
+#define SMSTPCR1_I2C0 (1 << 16)
+#define SMSTPCR3_USB (1 << 22)
+#define SMSTPCR3_I2C1 (1 << 23)
+
+#define PORT32CR (0xE6051020)
+#define PORT33CR (0xE6051021)
+#define PORT34CR (0xE6051022)
+#define PORT35CR (0xE6051023)
+
+static int cmp_loop(u32 *addr, u32 data, u32 cmp)
+{
+ int err = -1;
+ int timeout = 100;
+ u32 value;
+
+ while (timeout > 0) {
+ value = readl(addr);
+ if ((value & data) == cmp) {
+ err = 0;
+ break;
+ }
+ timeout--;
+ }
+
+ return err;
+}
+
+/* SBSC Init function */
+static void sbsc_init(struct sh73a0_sbsc *sbsc)
+{
+ writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0);
+ writel(0x5, &sbsc->sdgencnt);
+ cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+ writel(0xacc90159, &sbsc->sdcr0);
+ writel(0x00010059, &sbsc->sdcr1);
+ writel(0x50874114, &sbsc->sdwcrc0);
+ writel(0x33199b37, &sbsc->sdwcrc1);
+ writel(0x008f2313, &sbsc->sdwcrc2);
+ writel(0x31020707, &sbsc->sdwcr00);
+ writel(0x0017040a, &sbsc->sdwcr01);
+ writel(0x31020707, &sbsc->sdwcr10);
+ writel(0x0017040a, &sbsc->sdwcr11);
+ writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */
+ writel(0x30000000, &sbsc->sdwcr2);
+
+ writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
+ cmp_loop(&sbsc->sdpcr, 0x80, 0x80);
+
+ writel(0x00002710, &sbsc->sdgencnt);
+ cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+ writel(0x0000003f, &sbsc->sdmracr0);
+ writel(0x0, SDMRA1A);
+ writel(0x000001f4, &sbsc->sdgencnt);
+ cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+ writel(0x0000ff0a, &sbsc->sdmracr0);
+ if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE)
+ writel(0x0, SDMRA3A);
+ else
+ writel(0x0, SDMRA3B);
+
+ writel(0x00000032, &sbsc->sdgencnt);
+ cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+ if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) {
+ writel(0x00002201, &sbsc->sdmracr0);
+ writel(0x0, SDMRA1A);
+ writel(0x00000402, &sbsc->sdmracr0);
+ writel(0x0, SDMRA1A);
+ writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
+ writel(0x0, SDMRA1A);
+ writel(0x0, SDMRA2A);
+ } else {
+ writel(0x00002201, &sbsc->sdmracr0);
+ writel(0x0, SDMRA1B);
+ writel(0x00000402, &sbsc->sdmracr0);
+ writel(0x0, SDMRA1B);
+ writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
+ writel(0x0, SDMRA1B);
+ writel(0x0, SDMRA2B);
+ }
+
+ writel(0x88800004, &sbsc->sdmrtmpcr);
+ writel(0x00000004, &sbsc->sdmrtmpmsk);
+ writel(0xa55a0032, &sbsc->rtcor);
+ writel(0xa55a000c, &sbsc->rtcorh);
+ writel(0xa55a2048, &sbsc->rtcsr);
+ writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0);
+ writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1);
+ writel(0xfff20000, &sbsc->zqccr);
+
+ /* SCBS2 only */
+ if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) {
+ writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0);
+ writel(0xa5390000, &sbsc->dphycnt1);
+ writel(0x00001200, &sbsc->dphycnt0);
+ writel(0x07ce0000, &sbsc->dphycnt1);
+ writel(0x00001247, &sbsc->dphycnt0);
+ cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000);
+ writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0);
+ }
+}
+
+void s_init(void)
+{
+ struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE;
+ struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
+ struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
+ (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
+ struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE;
+ struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE;
+ struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+ struct sh73a0_hpb_bscr *hpb_bscr =
+ (struct sh73a0_hpb_bscr *)HPBSCR_BASE;
+
+ /* Watchdog init */
+ writew(0xA507, &rwdt->rwtcsra0);
+
+ /* Secure control register Init */
+ #define LIFEC_SEC_SRC_BIT (1 << 15)
+ writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC);
+
+ clrbits_le32(&cpg->smstpcr3, (1 << 15));
+ clrbits_le32(&cpg_srcr->srcr3, (1 << 15));
+ clrbits_le32(&cpg->smstpcr2, (1 << 18));
+ clrbits_le32(&cpg_srcr->srcr2, (1 << 18));
+ writel(0x0, &cpg->pllecr);
+
+ cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
+ cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+
+ writel(0x2D000000, &cpg->pll0cr);
+ writel(0x17100000, &cpg->pll1cr);
+ writel(0x96235880, &cpg->frqcrb);
+ cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+
+ writel(0xB, &cpg->flckcr);
+ clrbits_le32(&cpg->smstpcr0, (1 << 1));
+
+ clrbits_le32(&cpg_srcr->srcr0, (1 << 1));
+ writel(0x0514, &hpb_bscr->smgpiotime);
+ writel(0x0514, &hpb_bscr->smcmt2time);
+ writel(0x0514, &hpb_bscr->smcpgtime);
+ writel(0x0514, &hpb_bscr->smsysctime);
+
+ writel(0x00092000, &cpg->dvfscr4);
+ writel(0x000000DC, &cpg->dvfscr5);
+ writel(0x0, &cpg->pllecr);
+ cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
+
+ /* FRQCR Init */
+ writel(0x0012453C, &cpg->frqcra);
+ writel(0x80431350, &cpg->frqcrb); /* ETM TRCLK 78MHz */
+ cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+ writel(0x00000B0B, &cpg->frqcrd);
+ cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+
+ /* Clock Init */
+ writel(0x00000003, PCLKCR);
+ writel(0x0000012F, &cpg->vclkcr1);
+ writel(0x00000119, &cpg->vclkcr2);
+ writel(0x00000119, &cpg->vclkcr3);
+ writel(0x00000002, &cpg->zbckcr);
+ writel(0x00000005, &cpg->flckcr);
+ writel(0x00000080, &cpg->sd0ckcr);
+ writel(0x00000080, &cpg->sd1ckcr);
+ writel(0x00000080, &cpg->sd2ckcr);
+ writel(0x0000003F, &cpg->fsiackcr);
+ writel(0x0000003F, &cpg->fsibckcr);
+ writel(0x00000080, &cpg->subckcr);
+ writel(0x0000000B, &cpg->spuackcr);
+ writel(0x0000000B, &cpg->spuvckcr);
+ writel(0x0000013F, &cpg->msuckcr);
+ writel(0x00000080, &cpg->hsickcr);
+ writel(0x0000003F, &cpg->mfck1cr);
+ writel(0x0000003F, &cpg->mfck2cr);
+ writel(0x00000107, &cpg->dsitckcr);
+ writel(0x00000313, &cpg->dsi0pckcr);
+ writel(0x0000130D, &cpg->dsi1pckcr);
+ writel(0x2A800E0E, &cpg->dsi0phycr);
+ writel(0x1E000000, &cpg->pll0cr);
+ writel(0x2D000000, &cpg->pll0cr);
+ writel(0x17100000, &cpg->pll1cr);
+ writel(0x27000080, &cpg->pll2cr);
+ writel(0x1D000000, &cpg->pll3cr);
+ writel(0x00080000, &cpg->pll0stpcr);
+ writel(0x000120C0, &cpg->pll1stpcr);
+ writel(0x00012000, &cpg->pll2stpcr);
+ writel(0x00000030, &cpg->pll3stpcr);
+
+ writel(0x0000000B, &cpg->pllecr);
+ cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00);
+
+ writel(0x000120F0, &cpg->dvfscr3);
+ writel(0x00000020, &cpg->mpmode);
+ writel(0x0000028A, &cpg->vrefcr);
+ writel(0xE4628087, &cpg->rmstpcr0);
+ writel(0xFFFFFFFF, &cpg->rmstpcr1);
+ writel(0x53FFFFFF, &cpg->rmstpcr2);
+ writel(0xFFFFFFFF, &cpg->rmstpcr3);
+ writel(0x00800D3D, &cpg->rmstpcr4);
+ writel(0xFFFFF3FF, &cpg->rmstpcr5);
+ writel(0x00000000, &cpg->smstpcr2);
+ writel(0x00040000, &cpg_srcr->srcr2);
+
+ clrbits_le32(&cpg->pllecr, (1 << 3));
+ cmp_loop(&cpg->pllecr, 0x00000800, 0x0);
+
+ writel(0x00000001, &hpb->hpbctrl6);
+ cmp_loop(&hpb->hpbctrl6, 0x1, 0x1);
+
+ writel(0x00001414, &cpg->frqcrd);
+ cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+
+ writel(0x1d000000, &cpg->pll3cr);
+ setbits_le32(&cpg->pllecr, (1 << 3));
+ cmp_loop(&cpg->pllecr, 0x800, 0x800);
+
+ /* SBSC1 Init*/
+ sbsc_init(sbsc1);
+
+ /* SBSC2 Init*/
+ sbsc_init(sbsc2);
+
+ writel(0x00000b0b, &cpg->frqcrd);
+ cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+ writel(0xfffffffc, &cpg->cpgxxcs4);
+}
+
+int board_early_init_f(void)
+{
+ struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
+ struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE;
+ struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
+ (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
+
+ writel(CS0BCR_D, &bsc->cs0bcr);
+ writel(CS4BCR_D, &bsc->cs4bcr);
+ writel(CS0WCR_D, &bsc->cs0wcr);
+ writel(CS4WCR_D, &bsc->cs4wcr);
+
+ clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD);
+
+ clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
+ clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
+ clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
+ clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
+ writel(VCLKCR1_D, &cpg->vclkcr1);
+
+ /* Setup SCIF4 / workaround */
+ writeb(0x12, PORT32CR);
+ writeb(0x22, PORT33CR);
+ writeb(0x12, PORT34CR);
+ writeb(0x22, PORT35CR);
+
+ return 0;
+}
+
+void adjust_core_voltage(void)
+{
+ u8 data;
+
+ data = 0x35;
+ i2c_set_bus_num(0);
+ i2c_write(0x40, 3, 1, &data, 1);
+}
+
+int board_init(void)
+{
+ adjust_core_voltage();
+ sh73a0_pinmux_init();
+
+ /* SCIFA 4 */
+ gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
+ gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
+ gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
+ gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
+
+ /* Ethernet/SMSC */
+ gpio_request(GPIO_PORT224, NULL);
+ gpio_direction_input(GPIO_PORT224);
+
+ /* SMSC/USB */
+ gpio_request(GPIO_FN_CS4_, NULL);
+
+ /* MMCIF */
+ gpio_request(GPIO_FN_MMCCLK0, NULL);
+ gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
+ gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
+
+ /* SDHI */
+ gpio_request(GPIO_FN_SDHIWP0, NULL);
+ gpio_request(GPIO_FN_SDHICD0, NULL);
+ gpio_request(GPIO_FN_SDHICMD0, NULL);
+ gpio_request(GPIO_FN_SDHICLK0, NULL);
+ gpio_request(GPIO_FN_SDHID0_3, NULL);
+ gpio_request(GPIO_FN_SDHID0_2, NULL);
+ gpio_request(GPIO_FN_SDHID0_1, NULL);
+ gpio_request(GPIO_FN_SDHID0_0, NULL);
+ gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
+ gpio_request(GPIO_PORT15, NULL);
+ gpio_direction_output(GPIO_PORT15, 1);
+
+ /* I2C */
+ gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
+ gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
+ gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
+ gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
+
+ gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+
+ return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_RMOBILE_BOARD_STRING
+};
+
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+#ifdef CONFIG_SMC911X
+ ret = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return ret;
+}
+
+void reset_cpu(ulong addr)
+{
+ /* Soft Power On Reset */
+ writel((1 << 31), RESCNT2);
+}
diff --git a/board/korat/Kconfig b/board/korat/Kconfig
new file mode 100644
index 0000000..f434dea
--- /dev/null
+++ b/board/korat/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_KORAT
+
+config SYS_BOARD
+ default "korat"
+
+config SYS_CONFIG_NAME
+ default "korat"
+
+endif
diff --git a/board/korat/MAINTAINERS b/board/korat/MAINTAINERS
new file mode 100644
index 0000000..8b96846
--- /dev/null
+++ b/board/korat/MAINTAINERS
@@ -0,0 +1,7 @@
+KORAT BOARD
+M: Larry Johnson <lrj@acm.org>
+S: Maintained
+F: board/korat/
+F: include/configs/korat.h
+F: configs/korat_defconfig
+F: configs/korat_perm_defconfig
diff --git a/board/korat/Makefile b/board/korat/Makefile
new file mode 100644
index 0000000..63914bc
--- /dev/null
+++ b/board/korat/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = korat.o
+extra-y += init.o
diff --git a/board/korat/README b/board/korat/README
new file mode 100644
index 0000000..e059f78
--- /dev/null
+++ b/board/korat/README
@@ -0,0 +1,64 @@
+The Korat board has two NOR flashes, FLASH0 and FLASH1, which are connected to
+chip select 0 and 1, respectively. FLASH0 contains 16 MiB, and is mapped to
+addresses 0xFF000000 - 0xFFFFFFFF as U-Boot Flash Bank #2. FLASH1 contains
+from 16 to 128 MiB, and is mapped to 0xF?000000 - 0xF7FFFFFF as U-Boot Flash
+Bank #1 (with the starting address depending on the flash size detected at
+runtime). The write-enable pin on FLASH0 is disabled, so the contents of FLASH0
+cannot be modified in the field. This also prevents FLASH0 from executing
+commands to return chip information, so its configuration is hard-coded in
+U-Boot.
+
+There are two versions of U-Boot for Korat: "permanent" and "upgradable". The
+permanent U-Boot is pre-programmed at the top of FLASH0, e.g., at addresses
+0xFFFA0000 - 0xFFFFFFFF for the current 384 KiB size. The upgradable U-Boot is
+located 256 KiB from the top of FLASH1, e.g. at addresses 0xF7F6000 - 0xF7FC0000
+for the current 384 KiB size. FLASH1 addresses 0xF7FE0000 - 0xF7FF0000 are
+used for the U-Boot environmental parameters, and addresses 0xF7FC0000 -
+0xF7FDFFFF are used for the redundant copy of the parameters. These locations
+are used by both versions of U-Boot.
+
+On booting, the permanent U-Boot in FLASH0 begins executing. After performing
+minimal setup, it monitors the state of the board's Reset switch (GPIO47). If
+the switch is sensed as open before a timeout period, then U-Boot branches to
+address 0xF7FBFFFC. This causes the upgradable U-Boot to execute from the
+beginning. If the switch remains closed thoughout the timeout period, the
+permanent U-Boot activates the on-board buzzer until the switch is sensed as
+opened. It then continues to execute without branching to FLASH1. The effect
+of this is that normally the Korat board boots its upgradable U-Boot, but, if
+this has been corrupted, the user can boot the permanent U-Boot, which can then
+be used to erase and reload FLASH1 as needed.
+
+Note that it is not necessary for the permanent U-Boot to have all the latest
+features, but only that it have sufficient functionality (working "tftp",
+"erase", "cp.b", etc.) to repair FLASH1. Also, the permanent U-Boot makes no
+assumptions about the size of FLASH1 or the size of the upgradable U-Boot: it is
+sufficient that the upgradable U-Boot can be started by a branch to 0xF7FBFFFC.
+
+The build sequence:
+
+ make korat_perm_config
+ make all
+
+builds the permanent U-Boot by selecting loader file "u-boot.lds" and defining
+preprocessor symbol "CONFIG_KORAT_PERMANENT". The default build:
+
+ make korat_config
+ make all
+
+creates the upgradable U-Boot by selecting loader file "u-boot-F7FC.lds" and
+leaving preprocessor symbol "CONFIG_KORAT_PERMANENT" undefined.
+
+2008-02-22, Larry Johnson <lrj@acm.org>
+
+
+The CompactFlash(R) controller on the Korat board provides a hi-speed USB
+interface. This may be connected to either a dedicated port on the on-board
+USB controller, or to a USB port on the PowerPC 440EPx processor. The U-Boot
+environment variable "korat_usbcf" can be used to specify which of these two
+USB host ports is used for CompactFlash. The valid setting for the variable are
+the strings "pci" and "ppc". If the variable defined and set to "ppc", then the
+PowerPC USB port is used. In all other cases the on-board USB controller is
+used, but if "korat_usbcf" is defined but is set to a string other than the two
+valid options, a warning is also issued.
+
+2009-01-28, Larry Johnson <lrj@acm.org>
diff --git a/board/korat/config.mk b/board/korat/config.mk
new file mode 100644
index 0000000..42e0060
--- /dev/null
+++ b/board/korat/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+#
+# Korat (PPC440EPx) board
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(emul),1)
+PLATFORM_CPPFLAGS += -fno-schedule-insns -fno-schedule-insns2
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000
+endif
+
+ifndef CONFIG_KORAT_PERMANENT
+LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-F7FC.lds
+endif
diff --git a/board/korat/init.S b/board/korat/init.S
new file mode 100644
index 0000000..20c5bdd
--- /dev/null
+++ b/board/korat/init.S
@@ -0,0 +1,80 @@
+/*
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G )
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform. They are
+ * generated dynamically in the SPD DDR2 detection routine.
+ */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
+ AC_RWX | SA_G )
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
+ CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG )
+
+ tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
+ CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG )
+
+ tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
+ CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG )
+
+ tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
+ CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG )
+
+ /* TLB-entry for EBC */
+ tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG )
+
+ /* TLB-entry for Internal Registers & OCM */
+ /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
+ tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I )
+
+ /*TLB-entry PCI registers*/
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG )
+
+ /* TLB-entry for peripherals */
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG)
+
+ /* TLB-entry PCI IO Space - from sr@denx.de */
+ tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG)
+
+ tlbtab_end
+
+#if defined(CONFIG_KORAT_PERMANENT)
+ .globl korat_branch_absolute
+korat_branch_absolute:
+ mtlr r3
+ blr
+#endif
diff --git a/board/korat/korat.c b/board/korat/korat.c
new file mode 100644
index 0000000..d9ab2fd
--- /dev/null
+++ b/board/korat/korat.c
@@ -0,0 +1,633 @@
+/*
+ * (C) Copyright 2007-2010
+ * Larry Johnson, lrj@acm.org
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <asm/ppc440.h>
+#include <asm/bitops.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-uic.h>
+#include <asm/processor.h>
+#include <asm/4xx_pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+ulong flash_get_size(ulong base, int banknum);
+
+#if defined(CONFIG_KORAT_PERMANENT)
+void korat_buzzer(int const on)
+{
+ if (on) {
+ out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
+ in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80);
+ } else {
+ out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
+ in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80);
+ }
+}
+#endif
+
+int board_early_init_f(void)
+{
+ uint32_t sdr0_pfc1, sdr0_pfc2;
+ uint32_t reg;
+ int eth;
+
+#if defined(CONFIG_KORAT_PERMANENT)
+ unsigned mscount;
+
+ extern void korat_branch_absolute(uint32_t addr);
+
+ for (mscount = 0; mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) {
+ udelay(1000);
+ if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) {
+ /* This call does not return. */
+ korat_branch_absolute(
+ CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4);
+ }
+ }
+ korat_buzzer(1);
+ while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_))
+ udelay(1000);
+
+ korat_buzzer(0);
+#endif
+
+ mtdcr(EBC0_CFGADDR, EBC0_CFG);
+ mtdcr(EBC0_CFGDATA, 0xb8400000);
+
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ /*
+ * Take sim card reader and CF controller out of reset. Also enable PHY
+ * auto-detect until board-specific PHY resets are available.
+ */
+ out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0);
+
+ /* Configure the two Ethernet PHYs. For each PHY, configure for fiber
+ * if the SFP module is present, and for copper if it is not present.
+ */
+ for (eth = 0; eth < 2; ++eth) {
+ if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) {
+ /* SFP module not present: configure PHY for copper. */
+ /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
+ out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
+ in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) |
+ 0x06 << (4 * eth));
+ } else {
+ /* SFP module present: configure PHY for fiber and
+ enable output */
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1);
+ gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0);
+ }
+ }
+ /* enable Ethernet: set GPIO45 and GPIO46 to 1 */
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1);
+
+ /* Wait 1 ms, then enable Fiber signal detect to PHYs. */
+ udelay(1000);
+ out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
+ in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88);
+
+ /* select Ethernet (and optionally IIC1) pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_4;
+#ifdef CONFIG_I2C_MULTI_BUS
+ sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
+#endif
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_4;
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /* PCI arbiter enabled */
+ mfsdr(SDR0_PCI0, reg);
+ mtsdr(SDR0_PCI0, 0x80000000 | reg);
+
+ return 0;
+}
+
+/*
+ * The boot flash on CS0 normally has its write-enable pin disabled, and so will
+ * not respond to CFI commands. This routine therefore fills in the flash
+ * information for the boot flash. (The flash at CS1 operates normally.)
+ */
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+ uint32_t addr;
+ int i;
+
+ if (1 != banknum)
+ return 0;
+
+ info->size = CONFIG_SYS_FLASH0_SIZE;
+ info->sector_count = CONFIG_SYS_FLASH0_SIZE / 0x20000;
+ info->flash_id = 0x01000000;
+ info->portwidth = 2;
+ info->chipwidth = 2;
+ info->buffer_size = 32;
+ info->erase_blk_tout = 16384;
+ info->write_tout = 2;
+ info->buffer_write_tout = 5;
+ info->vendor = 2;
+ info->cmd_reset = 0x00F0;
+ info->interface = 2;
+ info->legacy_unlock = 0;
+ info->manufacturer_id = 1;
+ info->device_id = 0x007E;
+
+#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
+ info->device_id2 = 0x2101;
+#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
+ info->device_id2 = 0x2301;
+#else
+#error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE
+#endif
+
+ info->ext_addr = 0x0040;
+ info->cfi_version = 0x3133;
+ info->cfi_offset = 0x0055;
+ info->addr_unlock1 = 0x00000555;
+ info->addr_unlock2 = 0x000002AA;
+ info->name = "CFI conformant";
+ for (i = 0, addr = -info->size;
+ i < info->sector_count;
+ ++i, addr += 0x20000) {
+ info->start[i] = addr;
+ info->protect[i] = 0x00;
+ }
+ return 1;
+}
+
+static int man_data_read(unsigned int addr)
+{
+ /*
+ * Read an octet of data from address "addr" in the manufacturer's
+ * information serial EEPROM, or -1 on error.
+ */
+ u8 data[2];
+
+ if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) ||
+ 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) {
+ debug("man_data_read(0x%02X) failed\n", addr);
+ return -1;
+ }
+ debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]);
+ return data[0];
+}
+
+static unsigned int man_data_field_addr(unsigned int const field)
+{
+ /*
+ * The manufacturer's information serial EEPROM contains a sequence of
+ * zero-delimited fields. Return the starting address of field "field",
+ * or 0 on error.
+ */
+ unsigned addr, i;
+
+ if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1))
+ /* Only format "A" is currently supported */
+ return 0;
+
+ for (addr = 2, i = 1; i < field && addr < 256; ++addr) {
+ if ('\0' == man_data_read(addr))
+ ++i;
+ }
+ return (addr < 256) ? addr : 0;
+}
+
+static char *man_data_read_field(char s[], unsigned const field,
+ unsigned const length)
+{
+ /*
+ * Place the null-terminated contents of field "field" of length
+ * "length" from the manufacturer's information serial EEPROM into
+ * string "s[length + 1]" and return a pointer to s, or return 0 on
+ * error. In either case the original contents of s[] is not preserved.
+ */
+ unsigned addr, i;
+
+ addr = man_data_field_addr(field);
+ if (0 == addr || addr + length >= 255)
+ return 0;
+
+ for (i = 0; i < length; ++i) {
+ int const c = man_data_read(addr++);
+
+ if (c <= 0)
+ return 0;
+
+ s[i] = (char)c;
+ }
+ if (0 != man_data_read(addr))
+ return 0;
+
+ s[i] = '\0';
+ return s;
+}
+
+static void set_serial_number(void)
+{
+ /*
+ * If the environmental variable "serial#" is not set, try to set it
+ * from the manufacturer's information serial EEPROM.
+ */
+ char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2];
+
+ if (getenv("serial#"))
+ return;
+
+ if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH))
+ return;
+
+ s[MAN_INFO_LENGTH] = '-';
+ if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD,
+ MAN_MAC_ADDR_LENGTH))
+ return;
+
+ setenv("serial#", s);
+}
+
+static void set_mac_addresses(void)
+{
+ /*
+ * If the environmental variables "ethaddr" and/or "eth1addr" are not
+ * set, try to set them from the manufacturer's information serial
+ * EEPROM.
+ */
+
+#if MAN_MAC_ADDR_LENGTH % 2 != 0
+#error MAN_MAC_ADDR_LENGTH must be an even number
+#endif
+
+ char s[(3 * MAN_MAC_ADDR_LENGTH) / 2];
+ char *src;
+ char *dst;
+
+ if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
+ return;
+
+ if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1,
+ MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH))
+ return;
+
+ for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) {
+ *dst++ = *src++;
+ *dst++ = *src++;
+ *dst++ = ':';
+ }
+ if (0 == getenv("ethaddr"))
+ setenv("ethaddr", s);
+
+ if (0 == getenv("eth1addr")) {
+ ++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2];
+ setenv("eth1addr", s);
+ }
+}
+
+int misc_init_r(void)
+{
+ uint32_t pbcr;
+ int size_val;
+ uint32_t reg;
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1;
+ uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
+ char const *const act = getenv("usbact");
+ char const *const usbcf = getenv("korat_usbcf");
+
+ /*
+ * Re-do FLASH1 sizing and adjust flash start and offset.
+ */
+ gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size;
+ gd->bd->bi_flashoffset = 0;
+
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ size_val = ffs(flash1_size) - 21;
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+ /*
+ * Re-do FLASH1 sizing and adjust flash offset to reserve space for
+ * environment
+ */
+ gd->bd->bi_flashoffset =
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR;
+
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21;
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* Monitor protection ON by default */
+#if defined(CONFIG_KORAT_PERMANENT)
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+ flash_info + 1);
+#else
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+ flash_info);
+#endif
+ /* Env protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ flash_info);
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ flash_info);
+
+ /*
+ * USB suff...
+ */
+ /*
+ * Select the USB controller on the 440EPx ("ppc") or on the PCI bus
+ * ("pci") for the CompactFlash.
+ */
+ if (usbcf != NULL && (strcmp(usbcf, "ppc") == 0)) {
+ /*
+ * If environment variable "usbcf" is defined and set to "ppc",
+ * then connect the CompactFlash controller to the PowerPC USB
+ * port.
+ */
+ printf("Attaching CompactFlash controller to PPC USB\n");
+ out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02,
+ in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10);
+ } else {
+ if (usbcf != NULL && (strcmp(usbcf, "pci") != 0))
+ printf("Warning: \"korat_usbcf\" is not set to a legal "
+ "value (\"ppc\" or \"pci\")\n");
+
+ printf("Attaching CompactFlash controller to PCI USB\n");
+ }
+ if (act == NULL || strcmp(act, "hostdev") == 0) {
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+
+ /*
+ * An 8-bit/60MHz interface is the only possible alternative
+ * when connecting the Device to the PHY
+ */
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
+
+ /*
+ * To enable the USB 2.0 Device function
+ * through the UTMI interface
+ */
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /* clear resets */
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay(1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Host(int phy) Device(ext phy)\n");
+
+ } else if (strcmp(act, "dev") == 0) {
+ /*-------------------PATCH-------------------------------*/
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x672c6000);
+
+ udelay(1000);
+ mtsdr(SDR0_SRST0, 0x00000080);
+
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x60206000);
+
+ *(unsigned int *)(0xe0000350) = 0x00000001;
+
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x60306000);
+ /*-------------------PATCH-------------------------------*/
+
+ /* SDR Setting */
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
+ usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
+
+ usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
+
+ usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
+ usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
+
+ sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
+ sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
+
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ /* clear resets */
+ udelay(1000);
+ mtsdr(SDR0_SRST1, 0x00000000);
+ udelay(1000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ printf("USB: Device(int phy)\n");
+ }
+
+ mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
+ reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
+ mtsdr(SDR0_SRST1, reg);
+
+ /*
+ * Clear PLB4A0_ACR[WRP]
+ * This fix will make the MAL burst disabling patch for the Linux
+ * EMAC driver obsolete.
+ */
+ reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+ mtdcr(PLB4A0_ACR, reg);
+
+ set_serial_number();
+ set_mac_addresses();
+ gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char const *const s = getenv("serial#");
+ u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0);
+
+ printf("Board: Korat, Rev. %X", rev);
+ if (s)
+ printf(", serial# %s", s);
+
+ printf(".\n Ethernet PHY 0: ");
+ if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL))
+ printf("fiber");
+ else
+ printf("copper");
+
+ printf(", PHY 1: ");
+ if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL))
+ printf("fiber");
+ else
+ printf("copper");
+
+ printf(".\n");
+#if defined(CONFIG_KORAT_PERMANENT)
+ printf(" Executing permanent copy of U-Boot.\n");
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
+/*
+ * Assign interrupts to PCI devices.
+ */
+void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
+}
+#endif
+
+/*
+ * pci_target_init
+ *
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+ /* First do 440EP(x) common setup */
+ __pci_target_init(hose);
+
+ /*
+ * Set up Configuration registers for on-board NEC uPD720101 USB
+ * controller.
+ */
+ pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
+}
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[4];
+ int rc;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR mapping */
+ val[0] = 1; /* chip select number */
+ val[1] = 0; /* always 0 */
+ val[2] = gd->bd->bi_flashstart;
+ val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
+ rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+ val, sizeof(val), 1);
+ if (rc)
+ printf("Unable to update property NOR mapping, err=%s\n",
+ fdt_strerror(rc));
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds
new file mode 100644
index 0000000..bee4d9a
--- /dev/null
+++ b/board/korat/u-boot-F7FC.lds
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xF7FBFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xF7FBF000 :
+ {
+ arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/kosagi/novena/Kconfig b/board/kosagi/novena/Kconfig
new file mode 100644
index 0000000..94f1754
--- /dev/null
+++ b/board/kosagi/novena/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_KOSAGI_NOVENA
+
+config SYS_BOARD
+ default "novena"
+
+config SYS_VENDOR
+ default "kosagi"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "novena"
+
+endif
diff --git a/board/kosagi/novena/MAINTAINERS b/board/kosagi/novena/MAINTAINERS
new file mode 100644
index 0000000..d3471c2
--- /dev/null
+++ b/board/kosagi/novena/MAINTAINERS
@@ -0,0 +1,6 @@
+NOVENA BOARD
+M: Marek Vasut <marex@denx.de>
+S: Maintained
+F: board/kosagi/novena/
+F: include/configs/novena.h
+F: configs/novena_defconfig
diff --git a/board/kosagi/novena/Makefile b/board/kosagi/novena/Makefile
new file mode 100644
index 0000000..6893b63
--- /dev/null
+++ b/board/kosagi/novena/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := novena_spl.o
+else
+obj-y := novena.o
+obj-$(CONFIG_VIDEO_IPUV3) += video.o
+endif
diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c
new file mode 100644
index 0000000..69f5be3
--- /dev/null
+++ b/board/kosagi/novena/novena.c
@@ -0,0 +1,269 @@
+/*
+ * Novena board support
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/sata.h>
+#include <asm/imx-common/video.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <input.h>
+#include <ipu_pixfmt.h>
+#include <linux/fb.h>
+#include <linux/input.h>
+#include <malloc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <stdio_dev.h>
+
+#include "novena.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * GPIO button
+ */
+#ifdef CONFIG_KEYBOARD
+static struct input_config button_input;
+
+static int novena_gpio_button_read_keys(struct input_config *input)
+{
+ int key = KEY_ENTER;
+ if (gpio_get_value(NOVENA_BUTTON_GPIO))
+ return 0;
+ input_send_keycodes(&button_input, &key, 1);
+ return 1;
+}
+
+static int novena_gpio_button_getc(struct stdio_dev *dev)
+{
+ return input_getc(&button_input);
+}
+
+static int novena_gpio_button_tstc(struct stdio_dev *dev)
+{
+ return input_tstc(&button_input);
+}
+
+static int novena_gpio_button_init(struct stdio_dev *dev)
+{
+ gpio_direction_input(NOVENA_BUTTON_GPIO);
+ input_set_delays(&button_input, 250, 250);
+ return 0;
+}
+
+int drv_keyboard_init(void)
+{
+ int error;
+ struct stdio_dev dev = {
+ .name = "button",
+ .flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM,
+ .start = novena_gpio_button_init,
+ .getc = novena_gpio_button_getc,
+ .tstc = novena_gpio_button_tstc,
+ };
+
+ error = input_init(&button_input, 0);
+ if (error) {
+ debug("%s: Cannot set up input\n", __func__);
+ return -1;
+ }
+ button_input.read_keys = novena_gpio_button_read_keys;
+
+ error = input_stdio_register(&dev);
+ if (error)
+ return error;
+
+ return 0;
+}
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+ { USDHC3_BASE_ADDR, 0, 4 }, /* Micro SD */
+ { USDHC2_BASE_ADDR, 0, 4 }, /* Big SD */
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ /* There is no CD for a microSD card, assume always present. */
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+ return 1;
+ else
+ return !gpio_get_value(NOVENA_SD_CD);
+}
+
+int board_mmc_getwp(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ /* There is no WP for a microSD card, assume always read-write. */
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+ return 0;
+ else
+ return gpio_get_value(NOVENA_SD_WP);
+}
+
+
+int board_mmc_init(bd_t *bis)
+{
+ s32 status = 0;
+ int index;
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ /* Big SD write-protect and card-detect */
+ gpio_direction_input(NOVENA_SD_WP);
+ gpio_direction_input(NOVENA_SD_CD);
+
+ for (index = 0; index < ARRAY_SIZE(usdhc_cfg); index++) {
+ status = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (status)
+ return status;
+ }
+
+ return status;
+}
+#endif
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display_clock();
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display_lvds();
+#endif
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Novena 4x\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+ struct pmic *p;
+ u32 reg;
+ int ret;
+
+ power_pfuze100_init(1);
+ p = pmic_get("PFUZE100");
+ if (!p)
+ return -EINVAL;
+
+ ret = pmic_probe(p);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ /* Set SWBST to 5.0V and enable (for USB) */
+ pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
+ reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
+ reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
+ pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
+
+ return 0;
+}
+
+/* EEPROM configuration data */
+struct novena_eeprom_data {
+ uint8_t signature[6];
+ uint8_t version;
+ uint8_t reserved;
+ uint32_t serial;
+ uint8_t mac[6];
+ uint16_t features;
+};
+
+int misc_init_r(void)
+{
+ struct novena_eeprom_data data;
+ uchar *datap = (uchar *)&data;
+ const char *signature = "Novena";
+ int ret;
+
+ /* If 'ethaddr' is already set, do nothing. */
+ if (getenv("ethaddr"))
+ return 0;
+
+ /* EEPROM is at bus 2. */
+ ret = i2c_set_bus_num(2);
+ if (ret) {
+ puts("Cannot select EEPROM I2C bus.\n");
+ return 0;
+ }
+
+ /* EEPROM is at address 0x56. */
+ ret = eeprom_read(0x56, 0, datap, sizeof(data));
+ if (ret) {
+ puts("Cannot read I2C EEPROM.\n");
+ return 0;
+ }
+
+ /* Check EEPROM signature. */
+ if (memcmp(data.signature, signature, 6)) {
+ puts("Invalid I2C EEPROM signature.\n");
+ return 0;
+ }
+
+ /* Set ethernet address from EEPROM. */
+ eth_setenv_enetaddr("ethaddr", data.mac);
+
+ return ret;
+}
diff --git a/board/kosagi/novena/novena.h b/board/kosagi/novena/novena.h
new file mode 100644
index 0000000..8f11583
--- /dev/null
+++ b/board/kosagi/novena/novena.h
@@ -0,0 +1,33 @@
+/*
+ * Novena board support
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BOARD_KOSAGI_NOVENA_NOVENA_H__
+#define __BOARD_KOSAGI_NOVENA_NOVENA_H__
+
+#define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17)
+#define NOVENA_BACKLIGHT_PWM_GPIO IMX_GPIO_NR(4, 29)
+#define NOVENA_BACKLIGHT_PWR_GPIO IMX_GPIO_NR(4, 15)
+#define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14)
+#define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7)
+#define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4)
+#define NOVENA_ITE6251_PWR_GPIO IMX_GPIO_NR(5, 28)
+#define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16)
+#define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12)
+#define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29)
+#define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22)
+#define NOVENA_SD_CD IMX_GPIO_NR(1, 4)
+#define NOVENA_SD_WP IMX_GPIO_NR(1, 2)
+
+#define NOVENA_IT6251_I2C_BUS 2
+#define NOVENA_IT6251_CHIPADDR 0x5c
+#define NOVENA_IT6251_LVDSADDR 0x5e
+
+void setup_display_clock(void);
+void setup_display_lvds(void);
+
+#endif /* __BOARD_KOSAGI_NOVENA_NOVENA_H__ */
diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c
new file mode 100644
index 0000000..b1688e0
--- /dev/null
+++ b/board/kosagi/novena/novena_spl.c
@@ -0,0 +1,613 @@
+/*
+ * Novena SPL
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/arch/crm_regs.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spl.h>
+
+#include <asm/arch/mx6-ddr.h>
+
+#include "novena.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PHY_CFG_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_HYS)
+
+#define RGMII_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL \
+ (PAD_CTL_HYS | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+#define BUTTON_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/*
+ * Audio
+ */
+static iomux_v3_cfg_t audio_pads[] = {
+ /* AUD_PWRON */
+ MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_audio(void)
+{
+ imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads));
+ gpio_direction_output(NOVENA_AUDIO_PWRON, 1);
+}
+
+/*
+ * ENET
+ */
+static iomux_v3_cfg_t enet_pads1[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+ /* pin 35, PHY_AD2 */
+ MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 32, MODE0 */
+ MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 31, MODE1 */
+ MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 28, MODE2 */
+ MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 27, MODE3 */
+ MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 33, CLK125_EN */
+ MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+
+ /* pin 42 PHY nRST */
+ MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t enet_pads2[] = {
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+
+ /* Assert Ethernet PHY nRST */
+ gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+
+ /*
+ * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset
+ * de-assertion. The intention is to use weak signal drivers (pull-ups)
+ * to prevent the conflict between PHY pins becoming outputs after
+ * reset and imx6 still driving the pins. The issue is described in PHY
+ * datasheet, p.14
+ */
+ gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */
+
+ /* Following reset timing (p.53, fig.8 from the PHY datasheet) */
+ mdelay(10);
+
+ /* De-assert Ethernet PHY nRST */
+ gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+
+ /* PHY is now configured, connect FEC to the pads */
+ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+
+ /*
+ * PHY datasheet recommends on p.53 to wait at least 100us after reset
+ * before using MII, so we enforce the delay here
+ */
+ udelay(100);
+}
+
+/*
+ * FPGA
+ */
+static iomux_v3_cfg_t fpga_pads[] = {
+ /* FPGA_RESET_N */
+ MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_fpga(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads));
+ gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0);
+}
+
+/*
+ * GPIO Button
+ */
+static iomux_v3_cfg_t button_pads[] = {
+ /* Debug */
+ MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_buttons(void)
+{
+ imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads));
+}
+
+/*
+ * I2C
+ */
+/*
+ * I2C1:
+ * 0x1d ... MMA7455L
+ * 0x30 ... SO-DIMM temp sensor
+ * 0x44 ... STMPE610
+ * 0x50 ... SO-DIMM ID
+ */
+struct i2c_pads_info i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+
+/*
+ * I2C2:
+ * 0x08 ... PMIC
+ * 0x3a ... HDMI DCC
+ * 0x50 ... HDMI DCC
+ */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+ .gp = IMX_GPIO_NR(3, 16)
+ }
+};
+
+/*
+ * I2C3:
+ * 0x11 ... ES8283
+ * 0x50 ... LCD EDID
+ * 0x56 ... EEPROM
+ */
+static struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+ .gp = IMX_GPIO_NR(3, 17)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+static void novena_spl_setup_iomux_i2c(void)
+{
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+}
+
+/*
+ * PCI express
+ */
+#ifdef CONFIG_CMD_PCI
+static iomux_v3_cfg_t pcie_pads[] = {
+ /* "Reset" pin */
+ MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* "Power on" pin */
+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* "Wake up" pin (input) */
+ MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* "Disable endpoint" (rfkill) pin */
+ MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_pcie(void)
+{
+ imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+
+ /* Ensure PCIe is powered down */
+ gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0);
+
+ /* Put the card into reset */
+ gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0);
+
+ /* Input signal to wake system from mPCIe card */
+ gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO);
+
+ /* Drive RFKILL high, to ensure the radio is turned on */
+ gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1);
+}
+#else
+static inline void novena_spl_setup_iomux_pcie(void) {}
+#endif
+
+/*
+ * SDHC
+ */
+static iomux_v3_cfg_t usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_sdhc(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+
+ /* Big SD write-protect and card-detect */
+ gpio_direction_input(IMX_GPIO_NR(1, 2));
+ gpio_direction_input(IMX_GPIO_NR(1, 4));
+}
+
+/*
+ * SPI
+ */
+#ifdef CONFIG_MXC_SPI
+static iomux_v3_cfg_t ecspi3_pads[] = {
+ /* SS1 */
+ MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
+ /* De-assert the nCS */
+ gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1);
+ gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1);
+ gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1);
+}
+#else
+static void novena_spl_setup_iomux_spi(void) {}
+#endif
+
+/*
+ * UART
+ */
+static iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+ MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+
+};
+
+static void novena_spl_setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+/*
+ * Video
+ */
+#ifdef CONFIG_VIDEO
+static iomux_v3_cfg_t hdmi_pads[] = {
+ /* "Ghost HPD" pin */
+ MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* LCD_PWR_CTL */
+ MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LCD_BL_ON */
+ MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* GPIO_PWM1 */
+ MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_video(void)
+{
+ imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads));
+ gpio_direction_input(NOVENA_HDMI_GHOST_HPD);
+}
+#else
+static inline void novena_spl_setup_iomux_video(void) {}
+#endif
+
+/*
+ * SPL boots from uSDHC card
+ */
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg = {
+ USDHC3_BASE_ADDR, 0, 4
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* There is no CD for a microSD card, assume always present. */
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif
+
+/* Configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = {
+ /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+ .dram_sdclk_0 = 0x00020038,
+ .dram_sdclk_1 = 0x00020038,
+ .dram_cas = 0x00000038,
+ .dram_ras = 0x00000038,
+ .dram_reset = 0x00000038,
+ /* SDCKE[0:1]: 100k pull-up */
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ /* SDBA2: pull-up disabled */
+ .dram_sdba2 = 0x00000000,
+ /* SDODT[0:1]: 100k pull-up, 40 ohm */
+ .dram_sdodt0 = 0x00000038,
+ .dram_sdodt1 = 0x00000038,
+ /* SDQS[0:7]: Differential input, 40 ohm */
+ .dram_sdqs0 = 0x00000038,
+ .dram_sdqs1 = 0x00000038,
+ .dram_sdqs2 = 0x00000038,
+ .dram_sdqs3 = 0x00000038,
+ .dram_sdqs4 = 0x00000038,
+ .dram_sdqs5 = 0x00000038,
+ .dram_sdqs6 = 0x00000038,
+ .dram_sdqs7 = 0x00000038,
+
+ /* DQM[0:7]: Differential input, 40 ohm */
+ .dram_dqm0 = 0x00000038,
+ .dram_dqm1 = 0x00000038,
+ .dram_dqm2 = 0x00000038,
+ .dram_dqm3 = 0x00000038,
+ .dram_dqm4 = 0x00000038,
+ .dram_dqm5 = 0x00000038,
+ .dram_dqm6 = 0x00000038,
+ .dram_dqm7 = 0x00000038,
+};
+
+/* Configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs novena_grp_ioregs = {
+ /* DDR3 */
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ /* Disable DDR pullups */
+ .grp_ddrpke = 0x00000000,
+ /* ADDR[00:16], SDBA[0:1]: 40 ohm */
+ .grp_addds = 0x00000038,
+ /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+ .grp_ctlds = 0x00000038,
+ /* DATA[00:63]: Differential input, 40 ohm */
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000038,
+ .grp_b1ds = 0x00000038,
+ .grp_b2ds = 0x00000038,
+ .grp_b3ds = 0x00000038,
+ .grp_b4ds = 0x00000038,
+ .grp_b5ds = 0x00000038,
+ .grp_b6ds = 0x00000038,
+ .grp_b7ds = 0x00000038,
+};
+
+static struct mx6_mmdc_calibration novena_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00420048,
+ .p0_mpwldectrl1 = 0x006f0059,
+ .p1_mpwldectrl0 = 0x005a0104,
+ .p1_mpwldectrl1 = 0x01070113,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x437c040b,
+ .p0_mpdgctrl1 = 0x0413040e,
+ .p1_mpdgctrl0 = 0x444f0446,
+ .p1_mpdgctrl1 = 0x044d0422,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x4c424249,
+ .p1_mprddlctl = 0x4e48414f,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x42414641,
+ .p1_mpwrdlctl = 0x46374b43,
+};
+
+static struct mx6_ddr_sysinfo novena_ddr_info = {
+ /* Width of data bus: 0=16, 1=32, 2=64 */
+ .dsize = 2,
+ /* Config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32, /* 32Gb per CS */
+ /* Single chip select */
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 1, /* RTT_Wr = RZQ/4 */
+ .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
+ .walat = 3, /* Write additional latency */
+ .ralat = 7, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+};
+
+static struct mx6_ddr3_cfg elpida_4gib_1600 = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 64,
+ .banks = 8,
+ .rowaddr = 16,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1300,
+ .trcmin = 4900,
+ .trasmin = 3590,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0xFFFFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ ccgr_init();
+ gpr_init();
+
+ /* setup GP timer */
+ timer_init();
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+ board_postclk_init();
+#endif
+#ifdef CONFIG_FSL_ESDHC
+ get_clocks();
+#endif
+
+ /* Setup IOMUX and configure basics. */
+ novena_spl_setup_iomux_audio();
+ novena_spl_setup_iomux_buttons();
+ novena_spl_setup_iomux_enet();
+ novena_spl_setup_iomux_fpga();
+ novena_spl_setup_iomux_i2c();
+ novena_spl_setup_iomux_pcie();
+ novena_spl_setup_iomux_sdhc();
+ novena_spl_setup_iomux_spi();
+ novena_spl_setup_iomux_uart();
+ novena_spl_setup_iomux_video();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* Start the DDR DRAM */
+ mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
+ mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c
new file mode 100644
index 0000000..3bb1b71
--- /dev/null
+++ b/board/kosagi/novena/video.c
@@ -0,0 +1,456 @@
+/*
+ * Novena video output support
+ *
+ * IT6251 code based on code Copyright (C) 2014 Sean Cross
+ * from https://github.com/xobs/novena-linux.git commit
+ * 3d85836ee1377d445531928361809612aa0a18db
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/video.h>
+#include <i2c.h>
+#include <input.h>
+#include <ipu_pixfmt.h>
+#include <linux/fb.h>
+#include <linux/input.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+
+#include "novena.h"
+
+#define IT6251_VENDOR_ID_LOW 0x00
+#define IT6251_VENDOR_ID_HIGH 0x01
+#define IT6251_DEVICE_ID_LOW 0x02
+#define IT6251_DEVICE_ID_HIGH 0x03
+#define IT6251_SYSTEM_STATUS 0x0d
+#define IT6251_SYSTEM_STATUS_RINTSTATUS (1 << 0)
+#define IT6251_SYSTEM_STATUS_RHPDSTATUS (1 << 1)
+#define IT6251_SYSTEM_STATUS_RVIDEOSTABLE (1 << 2)
+#define IT6251_SYSTEM_STATUS_RPLL_IOLOCK (1 << 3)
+#define IT6251_SYSTEM_STATUS_RPLL_XPLOCK (1 << 4)
+#define IT6251_SYSTEM_STATUS_RPLL_SPLOCK (1 << 5)
+#define IT6251_SYSTEM_STATUS_RAUXFREQ_LOCK (1 << 6)
+#define IT6251_REF_STATE 0x0e
+#define IT6251_REF_STATE_MAIN_LINK_DISABLED (1 << 0)
+#define IT6251_REF_STATE_AUX_CHANNEL_READ (1 << 1)
+#define IT6251_REF_STATE_CR_PATTERN (1 << 2)
+#define IT6251_REF_STATE_EQ_PATTERN (1 << 3)
+#define IT6251_REF_STATE_NORMAL_OPERATION (1 << 4)
+#define IT6251_REF_STATE_MUTED (1 << 5)
+
+#define IT6251_REG_PCLK_CNT_LOW 0x57
+#define IT6251_REG_PCLK_CNT_HIGH 0x58
+
+#define IT6521_RETRY_MAX 20
+
+static int it6251_is_stable(void)
+{
+ const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+ const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
+ int status;
+ int clkcnt;
+ int rpclkcnt;
+ int refstate;
+
+ rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) |
+ ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00);
+ debug("RPCLKCnt: %d\n", rpclkcnt);
+
+ status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS);
+ debug("System status: 0x%02x\n", status);
+
+ clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) |
+ ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) &
+ 0x0f00);
+ debug("Clock: 0x%02x\n", clkcnt);
+
+ refstate = i2c_reg_read(laddr, IT6251_REF_STATE);
+ debug("Ref Link State: 0x%02x\n", refstate);
+
+ if ((refstate & 0x1f) != 0)
+ return 0;
+
+ /* If video is muted, that's a failure */
+ if (refstate & IT6251_REF_STATE_MUTED)
+ return 0;
+
+ if (!(status & IT6251_SYSTEM_STATUS_RVIDEOSTABLE))
+ return 0;
+
+ return 1;
+}
+
+static int it6251_ready(void)
+{
+ const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+
+ /* Test if the IT6251 came out of reset by reading ID regs. */
+ if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15)
+ return 0;
+ if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca)
+ return 0;
+ if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51)
+ return 0;
+ if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62)
+ return 0;
+
+ return 1;
+}
+
+static void it6251_program_regs(void)
+{
+ const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+ const unsigned int laddr = NOVENA_IT6251_LVDSADDR;
+
+ i2c_reg_write(caddr, 0x05, 0x00);
+ mdelay(1);
+
+ /* set LVDSRX address, and enable */
+ i2c_reg_write(caddr, 0xfd, 0xbc);
+ i2c_reg_write(caddr, 0xfe, 0x01);
+
+ /*
+ * LVDSRX
+ */
+ /* This write always fails, because the chip goes into reset */
+ /* reset LVDSRX */
+ i2c_reg_write(laddr, 0x05, 0xff);
+ i2c_reg_write(laddr, 0x05, 0x00);
+
+ /* reset LVDSRX PLL */
+ i2c_reg_write(laddr, 0x3b, 0x42);
+ i2c_reg_write(laddr, 0x3b, 0x43);
+
+ /* something with SSC PLL */
+ i2c_reg_write(laddr, 0x3c, 0x08);
+ /* don't swap links, but writing reserved registers */
+ i2c_reg_write(laddr, 0x0b, 0x88);
+
+ /* JEIDA, 8-bit depth 0x11, orig 0x42 */
+ i2c_reg_write(laddr, 0x2c, 0x01);
+ /* "reserved" */
+ i2c_reg_write(laddr, 0x32, 0x04);
+ /* "reserved" */
+ i2c_reg_write(laddr, 0x35, 0xe0);
+ /* "reserved" + clock delay */
+ i2c_reg_write(laddr, 0x2b, 0x24);
+
+ /* reset LVDSRX pix clock */
+ i2c_reg_write(laddr, 0x05, 0x02);
+ i2c_reg_write(laddr, 0x05, 0x00);
+
+ /*
+ * DPTX
+ */
+ /* set for two lane mode, normal op, no swapping, no downspread */
+ i2c_reg_write(caddr, 0x16, 0x02);
+
+ /* some AUX channel EDID magic */
+ i2c_reg_write(caddr, 0x23, 0x40);
+
+ /* power down lanes 3-0 */
+ i2c_reg_write(caddr, 0x5c, 0xf3);
+
+ /* enable DP scrambling, change EQ CR phase */
+ i2c_reg_write(caddr, 0x5f, 0x06);
+
+ /* color mode RGB, pclk/2 */
+ i2c_reg_write(caddr, 0x60, 0x02);
+ /* dual pixel input mode, no EO swap, no RGB swap */
+ i2c_reg_write(caddr, 0x61, 0x04);
+ /* M444B24 video format */
+ i2c_reg_write(caddr, 0x62, 0x01);
+
+ /* vesa range / not interlace / vsync high / hsync high */
+ i2c_reg_write(caddr, 0xa0, 0x0F);
+
+ /* hpd event timer set to 1.6-ish ms */
+ i2c_reg_write(caddr, 0xc9, 0xf5);
+
+ /* more reserved magic */
+ i2c_reg_write(caddr, 0xca, 0x4d);
+ i2c_reg_write(caddr, 0xcb, 0x37);
+
+ /* enhanced framing mode, auto video fifo reset, video mute disable */
+ i2c_reg_write(caddr, 0xd3, 0x03);
+
+ /* "vidstmp" and some reserved stuff */
+ i2c_reg_write(caddr, 0xd4, 0x45);
+
+ /* queue number -- reserved */
+ i2c_reg_write(caddr, 0xe7, 0xa0);
+ /* info frame packets and reserved */
+ i2c_reg_write(caddr, 0xe8, 0x33);
+ /* more AVI stuff */
+ i2c_reg_write(caddr, 0xec, 0x00);
+
+ /* select PC master reg for aux channel? */
+ i2c_reg_write(caddr, 0x23, 0x42);
+
+ /* send PC request commands */
+ i2c_reg_write(caddr, 0x24, 0x00);
+ i2c_reg_write(caddr, 0x25, 0x00);
+ i2c_reg_write(caddr, 0x26, 0x00);
+
+ /* native aux read */
+ i2c_reg_write(caddr, 0x2b, 0x00);
+ /* back to internal */
+ i2c_reg_write(caddr, 0x23, 0x40);
+
+ /* voltage swing level 3 */
+ i2c_reg_write(caddr, 0x19, 0xff);
+ /* pre-emphasis level 3 */
+ i2c_reg_write(caddr, 0x1a, 0xff);
+
+ /* start link training */
+ i2c_reg_write(caddr, 0x17, 0x01);
+}
+
+static int it6251_init(void)
+{
+ const unsigned int caddr = NOVENA_IT6251_CHIPADDR;
+ int reg;
+ int tries, retries = 0;
+
+ for (retries = 0; retries < IT6521_RETRY_MAX; retries++) {
+ /* Program the chip. */
+ it6251_program_regs();
+
+ /* Wait for video stable. */
+ for (tries = 0; tries < 100; tries++) {
+ reg = i2c_reg_read(caddr, 0x17);
+ /* Test Link CFG, STS, LCS read done. */
+ if ((reg & 0xe0) != 0xe0) {
+ /* Not yet, wait a bit more. */
+ mdelay(2);
+ continue;
+ }
+
+ /* Test if the video input is stable. */
+ if (it6251_is_stable())
+ return 0;
+ }
+ /*
+ * If we couldn't stabilize, requeue and try again,
+ * because it means that the LVDS channel isn't
+ * stable yet.
+ */
+ printf("Display didn't stabilize.\n");
+ printf("This may be because the LVDS port is still in powersave mode.\n");
+ mdelay(50);
+ }
+
+ return -EINVAL;
+}
+
+static void enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+static int lvds_enabled;
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ if (lvds_enabled)
+ return;
+
+ /* ITE IT6251 power enable. */
+ gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 0);
+ mdelay(10);
+ gpio_direction_output(NOVENA_ITE6251_PWR_GPIO, 1);
+ mdelay(20);
+ lvds_enabled = 1;
+}
+
+static int detect_lvds(struct display_info_t const *dev)
+{
+ int ret, loops = 250;
+
+ enable_lvds(dev);
+
+ ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
+ if (ret) {
+ puts("Cannot select IT6251 I2C bus.\n");
+ return 0;
+ }
+
+ /* Wait up-to ~250 mS for the LVDS to come up. */
+ while (--loops) {
+ ret = it6251_ready();
+ if (ret)
+ return ret;
+
+ mdelay(1);
+ }
+
+ return 0;
+}
+
+struct display_info_t const displays[] = {
+ {
+ /* HDMI Output */
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15384,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+ },
+ }, {
+ /* LVDS Output: N133HSE-EA1 Rev. C1 */
+ .bus = -1,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_lvds,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "Chimei-FHD",
+ .refresh = 60,
+ .xres = 1920,
+ .yres = 1080,
+ .pixclock = 15384,
+ .left_margin = 148,
+ .right_margin = 88,
+ .upper_margin = 36,
+ .lower_margin = 4,
+ .hsync_len = 44,
+ .vsync_len = 5,
+ .sync = FB_SYNC_HOR_HIGH_ACT |
+ FB_SYNC_VERT_HIGH_ACT |
+ FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ },
+ },
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+static void enable_vpll(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int timeout = 100000;
+
+ setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+ clrsetbits_le32(&ccm->analog_pll_video,
+ BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+ BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+ BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
+ BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
+
+ writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+ writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+ clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+ while (timeout--)
+ if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+ break;
+ if (timeout < 0)
+ printf("Warning: video pll lock timeout!\n");
+
+ clrsetbits_le32(&ccm->analog_pll_video,
+ BM_ANADIG_PLL_VIDEO_BYPASS,
+ BM_ANADIG_PLL_VIDEO_ENABLE);
+}
+
+void setup_display_clock(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ enable_ipu_clock();
+ enable_vpll();
+ imx_setup_hdmi();
+
+ /* Turn on IPU LDB DI0 clocks */
+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+ /* Switch LDB DI0 to PLL5 (Video PLL) */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
+ (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+
+ /* LDB clock div by 3.5 */
+ clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+ /* DI0 clock derived from ldb_di0_clk */
+ clrsetbits_le32(&mxc_ccm->chsccdr,
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+ (CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
+ );
+
+ /* Enable both LVDS channels, both connected to DI0. */
+ writel(IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH |
+ IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+ IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
+ IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+ &iomux->gpr[2]);
+
+ clrsetbits_le32(&iomux->gpr[3],
+ IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+ IOMUXC_GPR3_LVDS1_MUX_CTL_MASK,
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+ );
+}
+
+void setup_display_lvds(void)
+{
+ int ret;
+
+ ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS);
+ if (ret) {
+ puts("Cannot select LVDS-to-eDP I2C bus.\n");
+ return;
+ }
+
+ /* The IT6251 should be ready now, if it's not, it's not connected. */
+ ret = it6251_ready();
+ if (!ret)
+ return;
+
+ /* Init the LVDS-to-eDP chip and if it succeeded, enable backlight. */
+ ret = it6251_init();
+ if (!ret) {
+ /* Backlight power enable. */
+ gpio_direction_output(NOVENA_BACKLIGHT_PWR_GPIO, 1);
+ /* PWM backlight pin, always on for full brightness. */
+ gpio_direction_output(NOVENA_BACKLIGHT_PWM_GPIO, 1);
+ }
+}
diff --git a/board/logicpd/am3517evm/Kconfig b/board/logicpd/am3517evm/Kconfig
new file mode 100644
index 0000000..901f609
--- /dev/null
+++ b/board/logicpd/am3517evm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AM3517_EVM
+
+config SYS_BOARD
+ default "am3517evm"
+
+config SYS_VENDOR
+ default "logicpd"
+
+config SYS_CONFIG_NAME
+ default "am3517_evm"
+
+endif
diff --git a/board/logicpd/am3517evm/MAINTAINERS b/board/logicpd/am3517evm/MAINTAINERS
new file mode 100644
index 0000000..7f03ac1
--- /dev/null
+++ b/board/logicpd/am3517evm/MAINTAINERS
@@ -0,0 +1,6 @@
+AM3517EVM BOARD
+M: Vaibhav Hiremath <hvaibhav@ti.com>
+S: Maintained
+F: board/logicpd/am3517evm/
+F: include/configs/am3517_evm.h
+F: configs/am3517_evm_defconfig
diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile
new file mode 100644
index 0000000..73b11df
--- /dev/null
+++ b/board/logicpd/am3517evm/Makefile
@@ -0,0 +1,11 @@
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Based on ti/evm/Makefile
+#
+# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := am3517evm.o
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
new file mode 100644
index 0000000..24be6ea
--- /dev/null
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -0,0 +1,177 @@
+/*
+ * am3517evm.c - board file for TI's AM3517 family of devices.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/omap_musb.h>
+#include <asm/arch/am35x_def.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/musb.h>
+#include <asm/mach-types.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include <i2c.h>
+#include <netdev.h>
+#include "am3517evm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AM3517_IP_SW_RESET 0x48002598
+#define CPGMACSS_SW_RST (1 << 1)
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_MUSB_AM35X
+static struct musb_hdrc_config musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12,
+};
+
+static struct omap_musb_board_data musb_board_data = {
+ .set_phy_power = am35x_musb_phy_power,
+ .clear_irq = am35x_musb_clear_irq,
+ .reset = am35x_musb_reset,
+};
+
+static struct musb_hdrc_platform_data musb_plat = {
+#if defined(CONFIG_MUSB_HOST)
+ .mode = MUSB_HOST,
+#elif defined(CONFIG_MUSB_GADGET)
+ .mode = MUSB_PERIPHERAL,
+#else
+#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET"
+#endif
+ .config = &musb_config,
+ .power = 250,
+ .platform_ops = &am35x_ops,
+ .board_data = &musb_board_data,
+};
+
+static void am3517_evm_musb_init(void)
+{
+ /*
+ * Set up USB clock/mode in the DEVCONF2 register.
+ * USB2.0 PHY reference clock is 13 MHz
+ */
+ clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+ CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
+ CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
+ CONF2_VBDTCTEN | CONF2_DATPOL);
+
+ musb_register(&musb_plat, &musb_board_data,
+ (void *)AM35XX_IPSS_USBOTGSS_BASE);
+}
+#else
+#define am3517_evm_musb_init() do {} while (0)
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Init i2c, ethernet, etc... (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+ volatile unsigned int ctr;
+ u32 reset;
+
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+#endif
+
+ dieid_num_r();
+
+ am3517_evm_musb_init();
+
+ /* activate PHY reset */
+ gpio_direction_output(30, 0);
+ gpio_set_value(30, 0);
+
+ ctr = 0;
+ do {
+ udelay(1000);
+ ctr++;
+ } while (ctr < 300);
+
+ /* deactivate PHY reset */
+ gpio_set_value(30, 1);
+
+ /* allow the PHY to stabilize and settle down */
+ ctr = 0;
+ do {
+ udelay(1000);
+ ctr++;
+ } while (ctr < 300);
+
+ /* ensure that the module is out of reset */
+ reset = readl(AM3517_IP_SW_RESET);
+ reset &= (~CPGMACSS_SW_RST);
+ writel(reset,AM3517_IP_SW_RESET);
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_AM3517EVM();
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+
+ rv = cpu_eth_init(bis);
+ if (rv > 0)
+ n += rv;
+
+ rv = usb_eth_initialize(bis);
+ if (rv > 0)
+ n += rv;
+
+ return n;
+}
+#endif
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h
new file mode 100644
index 0000000..a6a55ee
--- /dev/null
+++ b/board/logicpd/am3517evm/am3517evm.h
@@ -0,0 +1,393 @@
+/*
+ * am3517evm.h - Header file for the AM3517 EVM.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.h
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _AM3517EVM_H_
+#define _AM3517EVM_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "AM3517EVM Board",
+ "NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_AM3517EVM() \
+ /* SDRC */\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_CKE0), (M0)) \
+ MUX_VAL(CP(SDRC_CKE1), (M0)) \
+ /*sdrc_strben_dly0*/\
+ MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
+ /*sdrc_strben_dly1*/\
+ MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
+ /* GPMC */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
+ /* - ETH_nRESET*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
+ /* DSS */\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
+ /* CAMERA */\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ /* - CAM_RESET*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
+ /* MMC */\
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
+ /* WriteProtect */\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*CardDetect*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
+ \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \
+ /* McBSP */\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+ /* - LCD_INI*/\
+ MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+ /* - LCD_ENVDD */\
+ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+ /* - LCD_QVGA/nVGA */\
+ MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+ /* - LCD_RESB */\
+ /* UART */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
+ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
+ /* I2C */\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
+ /* McSPI */\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
+ /* - LAN_INTR*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \
+ \
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \
+ /* CCDC */\
+ MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
+ /* RMII */\
+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
+ MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
+ MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
+ /* HECC */\
+ MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
+ /* HSUSB */\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
+ /* HDQ */\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \
+ /* Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
+ /*SYS_nRESWARM */\
+ MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \
+ /* - GPIO30 */\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ /* - PEN_IRQ */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+ /* - VIO_1V8*/\
+ MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
+ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
+ /* JTAG */\
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
+ /* ETK (ES2 onwards) */\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \
+ /* Die to Die */\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
+
+#endif
diff --git a/board/logicpd/imx27lite/Kconfig b/board/logicpd/imx27lite/Kconfig
new file mode 100644
index 0000000..c7de2e3
--- /dev/null
+++ b/board/logicpd/imx27lite/Kconfig
@@ -0,0 +1,31 @@
+if TARGET_IMX27LITE
+
+config SYS_BOARD
+ default "imx27lite"
+
+config SYS_VENDOR
+ default "logicpd"
+
+config SYS_SOC
+ default "mx27"
+
+config SYS_CONFIG_NAME
+ default "imx27lite"
+
+endif
+
+if TARGET_MAGNESIUM
+
+config SYS_BOARD
+ default "imx27lite"
+
+config SYS_VENDOR
+ default "logicpd"
+
+config SYS_SOC
+ default "mx27"
+
+config SYS_CONFIG_NAME
+ default "magnesium"
+
+endif
diff --git a/board/logicpd/imx27lite/MAINTAINERS b/board/logicpd/imx27lite/MAINTAINERS
new file mode 100644
index 0000000..a7b22ac
--- /dev/null
+++ b/board/logicpd/imx27lite/MAINTAINERS
@@ -0,0 +1,12 @@
+IMX27LITE BOARD
+M: Wolfgang Denk <wd@denx.de>
+S: Maintained
+F: board/logicpd/imx27lite/
+F: include/configs/imx27lite.h
+F: configs/imx27lite_defconfig
+
+MAGNESIUM BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: include/configs/magnesium.h
+F: configs/magnesium_defconfig
diff --git a/board/logicpd/imx27lite/Makefile b/board/logicpd/imx27lite/Makefile
new file mode 100644
index 0000000..50a3da6
--- /dev/null
+++ b/board/logicpd/imx27lite/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := imx27lite.o
+obj-y += lowlevel_init.o
diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c
new file mode 100644
index 0000000..07b07a0
--- /dev/null
+++ b/board/logicpd/imx27lite/imx27lite.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+#if defined(CONFIG_SYS_NAND_LARGEPAGE)
+ struct system_control_regs *sc_regs =
+ (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+#endif
+
+ gd->bd->bi_arch_number = MACH_TYPE_IMX27LITE;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+#ifdef CONFIG_MXC_UART
+ mx27_uart1_init_pins();
+#endif
+#ifdef CONFIG_FEC_MXC
+ mx27_fec_init_pins();
+ imx_gpio_mode((GPIO_PORTC | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 31));
+ gpio_set_value(GPIO_PORTC | 31, 1);
+#endif
+#ifdef CONFIG_MXC_MMC
+#if defined(CONFIG_MAGNESIUM)
+ mx27_sd1_init_pins();
+#else
+ mx27_sd2_init_pins();
+#endif
+#endif
+
+#if defined(CONFIG_SYS_NAND_LARGEPAGE)
+ /*
+ * set in FMCR NF_FMS Bit(5) to 1
+ * (NAND Flash with 2 Kbyte page size)
+ */
+ writel(readl(&sc_regs->fmcr) | (1 << 5), &sc_regs->fmcr);
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ PHYS_SDRAM_1_SIZE);
+#if CONFIG_NR_DRAM_BANKS > 1
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+#endif
+}
+
+int checkboard(void)
+{
+ puts("Board: ");
+ puts(CONFIG_BOARDNAME);
+ return 0;
+}
diff --git a/board/logicpd/imx27lite/lowlevel_init.S b/board/logicpd/imx27lite/lowlevel_init.S
new file mode 100644
index 0000000..c286d0d
--- /dev/null
+++ b/board/logicpd/imx27lite/lowlevel_init.S
@@ -0,0 +1,157 @@
+/*
+ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
+ * Applications Processor Reference Manual, Rev. 0.2".
+ *
+ * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
+ * (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+SOC_ESDCTL_BASE_W: .word IMX_ESD_BASE
+SOC_SI_ID_REG_W: .word IMX_SYSTEM_CTL_BASE
+SDRAM_ESDCFG_T1_W: .word SDRAM_ESDCFG_REGISTER_VAL(0)
+SDRAM_ESDCFG_T2_W: .word SDRAM_ESDCFG_REGISTER_VAL(3)
+SDRAM_PRECHARGE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
+ ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_AUTOREF_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
+ ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_LOADMODE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
+ ESDCTL_ROW13 | ESDCTL_COL10)
+SDRAM_NORMAL_CMD_W: .word SDRAM_ESDCTL_REGISTER_VAL
+
+.macro init_aipi
+ /*
+ * setup AIPI1 and AIPI2
+ */
+ write32 AIPI1_PSR0, AIPI1_PSR0_VAL
+ write32 AIPI1_PSR1, AIPI1_PSR1_VAL
+ write32 AIPI2_PSR0, AIPI2_PSR0_VAL
+ write32 AIPI2_PSR1, AIPI2_PSR1_VAL
+
+.endm /* init_aipi */
+
+.macro init_clock
+ ldr r0, =CSCR
+ /* disable MPLL/SPLL first */
+ ldr r1, [r0]
+ bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
+ str r1, [r0]
+
+ write32 MPCTL0, MPCTL0_VAL
+ write32 SPCTL0, SPCTL0_VAL
+
+ write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
+
+ /*
+ * add some delay here
+ */
+ wait_timer 0x1000
+
+ /* peripheral clock divider */
+ write32 PCDR0, PCDR0_VAL
+ write32 PCDR1, PCDR1_VAL
+
+ /* Configure PCCR0 and PCCR1 */
+ write32 PCCR0, PCCR0_VAL
+ write32 PCCR1, PCCR1_VAL
+
+.endm /* init_clock */
+
+.macro sdram_init
+ ldr r0, SOC_ESDCTL_BASE_W
+ mov r2, #PHYS_SDRAM_1
+
+ /* Do initial reset */
+ mov r1, #ESDMISC_MDDR_DL_RST
+ str r1, [r0, #ESDMISC_ROF]
+
+ /* Hold for more than 200ns */
+ wait_timer 0x10000
+
+ /* Activate LPDDR iface */
+ mov r1, #ESDMISC_MDDREN
+ str r1, [r0, #ESDMISC_ROF]
+
+ /* Check The chip version TO1 or TO2 */
+ ldr r1, SOC_SI_ID_REG_W
+ ldr r1, [r1]
+ ands r1, r1, #0xF0000000
+ /* add Latency on CAS only for TO2 */
+ ldreq r1, SDRAM_ESDCFG_T2_W
+ ldrne r1, SDRAM_ESDCFG_T1_W
+ str r1, [r0, #ESDCFG0_ROF]
+
+ /* Run initialization sequence */
+ ldr r1, SDRAM_PRECHARGE_CMD_W
+ str r1, [r0, #ESDCTL0_ROF]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+
+ ldr r1, SDRAM_AUTOREF_CMD_W
+ str r1, [r0, #ESDCTL0_ROF]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+
+ ldr r1, SDRAM_LOADMODE_CMD_W
+ str r1, [r0, #ESDCTL0_ROF]
+ ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
+ add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
+ ldrb r1, [r3]
+
+ ldr r1, SDRAM_NORMAL_CMD_W
+ str r1, [r0, #ESDCTL0_ROF]
+
+#if (CONFIG_NR_DRAM_BANKS > 1)
+ /* 2nd sdram */
+ mov r2, #PHYS_SDRAM_2
+
+ /* Check The chip version TO1 or TO2 */
+ ldr r1, SOC_SI_ID_REG_W
+ ldr r1, [r1]
+ ands r1, r1, #0xF0000000
+ /* add Latency on CAS only for TO2 */
+ ldreq r1, SDRAM_ESDCFG_T2_W
+ ldrne r1, SDRAM_ESDCFG_T1_W
+ str r1, [r0, #ESDCFG1_ROF]
+
+ /* Run initialization sequence */
+ ldr r1, SDRAM_PRECHARGE_CMD_W
+ str r1, [r0, #ESDCTL1_ROF]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+
+ ldr r1, SDRAM_AUTOREF_CMD_W
+ str r1, [r0, #ESDCTL1_ROF]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+ ldr r1, [r2, #SDRAM_ALL_VAL]
+
+ ldr r1, SDRAM_LOADMODE_CMD_W
+ str r1, [r0, #ESDCTL1_ROF]
+ ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
+ add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
+ ldrb r1, [r3]
+
+ ldr r1, SDRAM_NORMAL_CMD_W
+ str r1, [r0, #ESDCTL1_ROF]
+#endif /* CONFIG_NR_DRAM_BANKS > 1 */
+
+.endm /* sdram_init */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+ init_aipi
+
+ init_clock
+
+ sdram_init
+
+ mov pc,r10
diff --git a/board/logicpd/imx31_litekit/Kconfig b/board/logicpd/imx31_litekit/Kconfig
new file mode 100644
index 0000000..d90f854
--- /dev/null
+++ b/board/logicpd/imx31_litekit/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX31_LITEKIT
+
+config SYS_BOARD
+ default "imx31_litekit"
+
+config SYS_VENDOR
+ default "logicpd"
+
+config SYS_SOC
+ default "mx31"
+
+config SYS_CONFIG_NAME
+ default "imx31_litekit"
+
+endif
diff --git a/board/logicpd/imx31_litekit/MAINTAINERS b/board/logicpd/imx31_litekit/MAINTAINERS
new file mode 100644
index 0000000..8e3608e
--- /dev/null
+++ b/board/logicpd/imx31_litekit/MAINTAINERS
@@ -0,0 +1,6 @@
+IMX31_LITEKIT BOARD
+#M: -
+S: Maintained
+F: board/logicpd/imx31_litekit/
+F: include/configs/imx31_litekit.h
+F: configs/imx31_litekit_defconfig
diff --git a/board/logicpd/imx31_litekit/Makefile b/board/logicpd/imx31_litekit/Makefile
new file mode 100644
index 0000000..3fd71c8
--- /dev/null
+++ b/board/logicpd/imx31_litekit/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := imx31_litekit.o
+obj-y += lowlevel_init.o
diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c
new file mode 100644
index 0000000..386e106
--- /dev/null
+++ b/board/logicpd/imx31_litekit/imx31_litekit.c
@@ -0,0 +1,91 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ /* CS0: Nor Flash */
+ static const struct mxc_weimcs cs0 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(10, 0, 3, 3, 0, 1, 5, 0, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
+ };
+
+ /* CS4: Network Controller */
+ static const struct mxc_weimcs cs4 = {
+ /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
+ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
+ /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
+ CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
+ /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
+ CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
+ };
+
+ mxc_setup_weimcs(0, &cs0);
+ mxc_setup_weimcs(4, &cs4);
+
+ /* setup pins for UART1 */
+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+ mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+ /* SPI2 */
+ mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+ mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+ mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+ mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+ mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+ mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+ mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
+
+ /* start SPI2 clock */
+ __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: i.MX31 Litekit\n");
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/logicpd/imx31_litekit/lowlevel_init.S b/board/logicpd/imx31_litekit/lowlevel_init.S
new file mode 100644
index 0000000..7c456bc
--- /dev/null
+++ b/board/logicpd/imx31_litekit/lowlevel_init.S
@@ -0,0 +1,87 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/imx-regs.h>
+
+.macro REG reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ strb r3, [r2]
+.endm
+
+.macro DELAY loops
+ ldr r2, =\loops
+1:
+ subs r2, r2, #1
+ nop
+ bcs 1b
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+
+ REG IPU_CONF, IPU_CONF_DI_EN
+ REG CCM_CCMR, 0x074B0BF5
+
+ DELAY 0x40000
+
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+ REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
+
+ REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
+ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+ REG 0x43FAC26C, 0 /* SDCLK */
+ REG 0x43FAC270, 0 /* CAS */
+ REG 0x43FAC274, 0 /* RAS */
+ REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */
+ REG 0x43FAC284, 0 /* DQM3 */
+ REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+ REG 0x43FAC28C, 0
+ REG 0x43FAC290, 0
+ REG 0x43FAC294, 0
+ REG 0x43FAC298, 0
+ REG 0x43FAC29C, 0
+ REG 0x43FAC2A0, 0
+ REG 0x43FAC2A4, 0
+ REG 0x43FAC2A8, 0
+ REG 0x43FAC2AC, 0
+ REG 0x43FAC2B0, 0
+ REG 0x43FAC2B4, 0
+ REG 0x43FAC2B8, 0
+ REG 0x43FAC2BC, 0
+ REG 0x43FAC2C0, 0
+ REG 0x43FAC2C4, 0
+ REG 0x43FAC2C8, 0
+ REG 0x43FAC2CC, 0
+ REG 0x43FAC2D0, 0
+ REG 0x43FAC2D4, 0
+ REG 0x43FAC2D8, 0
+ REG 0x43FAC2DC, 0
+ REG 0xB8001010, 0x00000004
+ REG 0xB8001004, 0x006ac73a
+ REG 0xB8001000, 0x92100000
+ REG 0x80000f00, 0x12344321
+ REG 0xB8001000, 0xa2100000
+ REG 0x80000000, 0x12344321
+ REG 0x80000000, 0x12344321
+ REG 0xB8001000, 0xb2100000
+ REG8 0x80000033, 0xda
+ REG8 0x81000000, 0xff
+ REG 0xB8001000, 0x82226080
+ REG 0x80000000, 0xDEADBEEF
+ REG 0xB8001010, 0x0000000c
+
+ mov pc, lr
diff --git a/board/logicpd/omap3som/Kconfig b/board/logicpd/omap3som/Kconfig
new file mode 100644
index 0000000..03d272a
--- /dev/null
+++ b/board/logicpd/omap3som/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP3_LOGIC
+
+config SYS_BOARD
+ default "omap3som"
+
+config SYS_VENDOR
+ default "logicpd"
+
+config SYS_CONFIG_NAME
+ default "omap3_logic"
+
+endif
diff --git a/board/logicpd/omap3som/MAINTAINERS b/board/logicpd/omap3som/MAINTAINERS
new file mode 100644
index 0000000..ffe2201
--- /dev/null
+++ b/board/logicpd/omap3som/MAINTAINERS
@@ -0,0 +1,6 @@
+OMAP3SOM BOARD
+M: Peter Barada <peter.barada@logicpd.com>
+S: Maintained
+F: board/logicpd/omap3som/
+F: include/configs/omap3_logic.h
+F: configs/omap3_logic_defconfig
diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile
new file mode 100644
index 0000000..87b86ad
--- /dev/null
+++ b/board/logicpd/omap3som/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := omap3logic.o
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
new file mode 100644
index 0000000..609edf1
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -0,0 +1,242 @@
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author :
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+#include <flash.h>
+#include <nand.h>
+#include <i2c.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include "omap3logic.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * two dimensional array of strucures containining board name and Linux
+ * machine IDs; row it selected based on CPU column is slected based
+ * on hsusb0_data5 pin having a pulldown resistor
+ */
+static struct board_id {
+ char *name;
+ int machine_id;
+} boards[2][2] = {
+ {
+ {
+ .name = "OMAP35xx SOM LV",
+ .machine_id = MACH_TYPE_OMAP3530_LV_SOM,
+ },
+ {
+ .name = "OMAP35xx Torpedo",
+ .machine_id = MACH_TYPE_OMAP3_TORPEDO,
+ },
+ },
+ {
+ {
+ .name = "DM37xx SOM LV",
+ .machine_id = MACH_TYPE_DM3730_SOM_LV,
+ },
+ {
+ .name = "DM37xx Torpedo",
+ .machine_id = MACH_TYPE_DM3730_TORPEDO,
+ },
+ },
+};
+
+/*
+ * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
+ */
+#define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ struct board_id *board;
+ unsigned int val;
+
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ /*
+ * To identify between a SOM LV and Torpedo module,
+ * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
+ * Drive the pin (and let it soak), then read it back.
+ * If the pin is still high its a Torpedo. If low its a SOM LV
+ */
+
+ /* Mux hsusb0_data5 as a GPIO */
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
+
+ if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
+
+ /*
+ * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
+ * will drain the voltage.
+ */
+ gpio_direction_output(BOARD_ID_GPIO, 0);
+ gpio_set_value(BOARD_ID_GPIO, 1);
+
+ /* Let it soak for a bit */
+ sdelay(0x100);
+
+ /*
+ * Read state of BOARD_ID_GPIO as an input and if its set.
+ * If so the board is a Torpedo
+ */
+ gpio_direction_input(BOARD_ID_GPIO);
+ val = gpio_get_value(BOARD_ID_GPIO);
+ gpio_free(BOARD_ID_GPIO);
+
+ board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
+ printf("Board: %s\n", board->name);
+
+ /* Set the machine_id passed to Linux */
+ gd->bd->bi_arch_number = board->machine_id;
+ }
+
+ /* restore hsusb0_data5 pin as hsusb0_data5 */
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
+
+ return 0;
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
+#ifdef CONFIG_SMC911X
+/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
+static const u32 gpmc_lan92xx_config[] = {
+ NET_LAN92XX_GPMC_CONFIG1,
+ NET_LAN92XX_GPMC_CONFIG2,
+ NET_LAN92XX_GPMC_CONFIG3,
+ NET_LAN92XX_GPMC_CONFIG4,
+ NET_LAN92XX_GPMC_CONFIG5,
+ NET_LAN92XX_GPMC_CONFIG6,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
+ CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+
+ return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ /*GPMC*/
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4));
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
+
+ /*Expansion card */
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
+
+ /* Serial Console */
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
+
+ /* I2C */
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
+
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0));
+
+ /*Control and debug */
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
+}
diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h
new file mode 100644
index 0000000..3a3ef6e
--- /dev/null
+++ b/board/logicpd/omap3som/omap3logic.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2011
+ * Logic Product Development <www.logicpd.com>
+ *
+ * Author:
+ * Peter Barada <peter.barada@logicpd.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _OMAP3LOGIC_H_
+#define _OMAP3LOGIC_H_
+
+/*
+ * OMAP3 GPMC register settings for CS1 LAN922x
+ */
+#define NET_LAN92XX_GPMC_CONFIG1 0x00001000
+#define NET_LAN92XX_GPMC_CONFIG2 0x00080801
+#define NET_LAN92XX_GPMC_CONFIG3 0x00000000
+#define NET_LAN92XX_GPMC_CONFIG4 0x08010801
+#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a
+#define NET_LAN92XX_GPMC_CONFIG6 0x03000280
+
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "Logic DM37x/OMAP35x reference board",
+ "NAND",
+};
+
+
+#endif
diff --git a/board/logicpd/zoom1/Kconfig b/board/logicpd/zoom1/Kconfig
new file mode 100644
index 0000000..d76cb66
--- /dev/null
+++ b/board/logicpd/zoom1/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP3_ZOOM1
+
+config SYS_BOARD
+ default "zoom1"
+
+config SYS_VENDOR
+ default "logicpd"
+
+config SYS_CONFIG_NAME
+ default "omap3_zoom1"
+
+endif
diff --git a/board/logicpd/zoom1/MAINTAINERS b/board/logicpd/zoom1/MAINTAINERS
new file mode 100644
index 0000000..338b965
--- /dev/null
+++ b/board/logicpd/zoom1/MAINTAINERS
@@ -0,0 +1,6 @@
+ZOOM1 BOARD
+M: Nishanth Menon <nm@ti.com>
+S: Maintained
+F: board/logicpd/zoom1/
+F: include/configs/omap3_zoom1.h
+F: configs/omap3_zoom1_defconfig
diff --git a/board/logicpd/zoom1/Makefile b/board/logicpd/zoom1/Makefile
new file mode 100644
index 0000000..7da0da0
--- /dev/null
+++ b/board/logicpd/zoom1/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := zoom1.o
diff --git a/board/logicpd/zoom1/config.mk b/board/logicpd/zoom1/config.mk
new file mode 100644
index 0000000..c7ebfd9
--- /dev/null
+++ b/board/logicpd/zoom1/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2006-2008
+# Texas Instruments, <www.ti.com>
+#
+# Zoom MDK uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
new file mode 100644
index 0000000..d39203a
--- /dev/null
+++ b/board/logicpd/zoom1/zoom1.c
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Nishanth Menon <nm@ti.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "zoom1.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* gpmc_cfg is initialized by gpmc_init and we use it here */
+extern struct gpmc *gpmc_cfg;
+
+/* GPMC definitions for Ethenet Controller LAN9211 */
+static const u32 gpmc_lab_enet[] = {
+ ZOOM1_ENET_GPMC_CONF1,
+ ZOOM1_ENET_GPMC_CONF2,
+ ZOOM1_ENET_GPMC_CONF3,
+ ZOOM1_ENET_GPMC_CONF4,
+ ZOOM1_ENET_GPMC_CONF5,
+ ZOOM1_ENET_GPMC_CONF6,
+ /*CONF7- computed as params */
+};
+
+static const struct ns16550_platdata zoom1_serial = {
+ OMAP34XX_UART3,
+ 2,
+ V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(zoom1_uart) = {
+ "serial_omap",
+ &zoom1_serial
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* CS1 is Ethernet LAN9211 */
+ enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1],
+ DEBUG_BASE, GPMC_SIZE_16M);
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure zoom board specific configurations
+ */
+int misc_init_r(void)
+{
+ twl4030_power_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+ dieid_num_r();
+
+ /*
+ * Board Reset
+ * The board is reset by holding the red button on the
+ * top right front face for eight seconds.
+ */
+ twl4030_power_reset_init();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ /* platform specific muxes */
+ MUX_ZOOM1_MDK();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+#ifdef CONFIG_SMC911X
+#define STR_ENV_ETHADDR "ethaddr"
+
+ struct eth_device *dev;
+ uchar eth_addr[6];
+
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
+ dev = eth_get_dev_by_index(0);
+ if (dev) {
+ eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
+ } else {
+ printf("zoom1: Couldn't get eth device\n");
+ rc = -1;
+ }
+ }
+#endif
+
+ return rc;
+}
+#endif
diff --git a/board/logicpd/zoom1/zoom1.h b/board/logicpd/zoom1/zoom1.h
new file mode 100644
index 0000000..3a943df
--- /dev/null
+++ b/board/logicpd/zoom1/zoom1.h
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments
+ * Nishanth Menon <nm@ti.com>
+ *
+ * Derived from: board/omap3/beagle/beagle.h
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _BOARD_ZOOM1_H_
+#define _BOARD_ZOOM1_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "OMAP3 Zoom MDK Rev 1",
+ "NAND",
+};
+
+#define ZOOM1_ENET_GPMC_CONF1 0x00611000
+#define ZOOM1_ENET_GPMC_CONF2 0x001F1F01
+#define ZOOM1_ENET_GPMC_CONF3 0x00080803
+#define ZOOM1_ENET_GPMC_CONF4 0x1D091D09
+#define ZOOM1_ENET_GPMC_CONF5 0x041D1F1F
+#define ZOOM1_ENET_GPMC_CONF6 0x1D0904C4
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_ZOOM1_MDK() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | DIS | M4)) /*GPMC_nCS3 -> GPIO54*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M4)) /*GPMC_nCS4 -> GPIO 55*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)) /*GPMC_nCS5 -> GPIO 56*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7 -> GPMC_IO_DIR*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/
+
+#endif /* _BOARD_ZOOM_H_ */
diff --git a/board/lwmon5/Kconfig b/board/lwmon5/Kconfig
new file mode 100644
index 0000000..90566d8
--- /dev/null
+++ b/board/lwmon5/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_LWMON5
+
+config SYS_BOARD
+ default "lwmon5"
+
+config SYS_CONFIG_NAME
+ default "lwmon5"
+
+endif
diff --git a/board/lwmon5/MAINTAINERS b/board/lwmon5/MAINTAINERS
new file mode 100644
index 0000000..7402ab6
--- /dev/null
+++ b/board/lwmon5/MAINTAINERS
@@ -0,0 +1,7 @@
+LWMON5 BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/lwmon5/
+F: include/configs/lwmon5.h
+F: configs/lcd4_lwmon5_defconfig
+F: configs/lwmon5_defconfig
diff --git a/board/lwmon5/Makefile b/board/lwmon5/Makefile
new file mode 100644
index 0000000..02478ca
--- /dev/null
+++ b/board/lwmon5/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = lwmon5.o kbd.o sdram.o
+extra-y += init.o
diff --git a/board/lwmon5/config.mk b/board/lwmon5/config.mk
new file mode 100644
index 0000000..d0348e8
--- /dev/null
+++ b/board/lwmon5/config.mk
@@ -0,0 +1,18 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# lwmon5 (440EPx)
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S
new file mode 100644
index 0000000..e5207c2
--- /dev/null
+++ b/board/lwmon5/init.S
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
+#endif
+
+ /* TLB-entry for PCI Memory */
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
+
+ /* TLB-entry for the FPGA Chip select 2 */
+ tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
+
+ /* TLB-entry for the FPGA Chip select 3 */
+ tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
+
+ /* TLB-entry for the LIME Controller */
+ tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
+ tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
+ tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
+ tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
+
+ /* TLB-entry for Internal Registers & OCM */
+ tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I)
+
+ /*TLB-entry PCI registers*/
+ tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG)
+
+ /* TLB-entry for peripherals */
+ tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
+
+ tlbtab_end
diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c
new file mode 100644
index 0000000..97962da
--- /dev/null
+++ b/board/lwmon5/kbd.c
@@ -0,0 +1,490 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2001, 2002
+ * DENX Software Engineering
+ * Wolfgang Denk, wd@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <i2c.h>
+#include <command.h>
+#include <post.h>
+#include <serial.h>
+#include <malloc.h>
+
+#include <linux/types.h>
+#include <linux/string.h> /* for strdup */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void kbd_init (void);
+static int compare_magic (uchar *kbd_data, uchar *str);
+
+/*--------------------- Local macros and constants --------------------*/
+#define _NOT_USED_ 0xFFFFFFFF
+
+/*------------------------- dspic io expander -----------------------*/
+#define DSPIC_PON_STATUS_REG 0x80A
+#define DSPIC_PON_INV_STATUS_REG 0x80C
+#define DSPIC_PON_KEY_REG 0x810
+/*------------------------- Keyboard controller -----------------------*/
+/* command codes */
+#define KEYBD_CMD_READ_KEYS 0x01
+#define KEYBD_CMD_READ_VERSION 0x02
+#define KEYBD_CMD_READ_STATUS 0x03
+#define KEYBD_CMD_RESET_ERRORS 0x10
+
+/* status codes */
+#define KEYBD_STATUS_MASK 0x3F
+#define KEYBD_STATUS_H_RESET 0x20
+#define KEYBD_STATUS_BROWNOUT 0x10
+#define KEYBD_STATUS_WD_RESET 0x08
+#define KEYBD_STATUS_OVERLOAD 0x04
+#define KEYBD_STATUS_ILLEGAL_WR 0x02
+#define KEYBD_STATUS_ILLEGAL_RD 0x01
+
+/* Number of bytes returned from Keyboard Controller */
+#define KEYBD_VERSIONLEN 2 /* version information */
+
+/*
+ * This is different from the "old" lwmon dsPIC kbd controller
+ * implementation. Now the controller still answers with 9 bytes,
+ * but the last 3 bytes are always "0x06 0x07 0x08". So we just
+ * set the length to compare to 6 instead of 9.
+ */
+#define KEYBD_DATALEN 6 /* normal key scan data */
+
+/* maximum number of "magic" key codes that can be assigned */
+
+static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
+static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
+
+static uchar *key_match (uchar *);
+
+#define KEYBD_SET_DEBUGMODE '#' /* Magic key to enable debug output */
+
+/***********************************************************************
+F* Function: int board_postclk_init (void) P*A*Z*
+ *
+P* Parameters: none
+P*
+P* Returnvalue: int
+P* - 0 is always returned.
+ *
+Z* Intention: This function is the board_postclk_init() method implementation
+Z* for the lwmon board.
+ *
+ ***********************************************************************/
+int board_postclk_init (void)
+{
+ kbd_init();
+
+ return (0);
+}
+
+static void kbd_init (void)
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ uchar tmp_data[KEYBD_DATALEN];
+ uchar val, errcd;
+ int i;
+
+ i2c_set_bus_num(0);
+
+ gd->arch.kbd_status = 0;
+
+ /* Forced by PIC. Delays <= 175us loose */
+ udelay(1000);
+
+ /* Read initial keyboard error code */
+ val = KEYBD_CMD_READ_STATUS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, &errcd, 1);
+ /* clear unused bits */
+ errcd &= KEYBD_STATUS_MASK;
+ /* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
+ errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
+ if (errcd) {
+ gd->arch.kbd_status |= errcd << 8;
+ }
+ /* Reset error code and verify */
+ val = KEYBD_CMD_RESET_ERRORS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ udelay(1000); /* delay NEEDED by keyboard PIC !!! */
+
+ val = KEYBD_CMD_READ_STATUS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, &val, 1);
+
+ val &= KEYBD_STATUS_MASK; /* clear unused bits */
+ if (val) { /* permanent error, report it */
+ gd->arch.kbd_status |= val;
+ return;
+ }
+
+ /*
+ * Read current keyboard state.
+ *
+ * After the error reset it may take some time before the
+ * keyboard PIC picks up a valid keyboard scan - the total
+ * scan time is approx. 1.6 ms (information by Martin Rajek,
+ * 28 Sep 2002). We read a couple of times for the keyboard
+ * to stabilize, using a big enough delay.
+ * 10 times should be enough. If the data is still changing,
+ * we use what we get :-(
+ */
+
+ memset (tmp_data, 0xFF, KEYBD_DATALEN); /* impossible value */
+ for (i=0; i<10; ++i) {
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
+ /* consistent state, done */
+ break;
+ }
+ /* remeber last state, delay, and retry */
+ memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
+ udelay (5000);
+ }
+}
+
+
+/* Read a register from the dsPIC. */
+int _dspic_read(ushort reg, ushort *data)
+{
+ uchar buf[sizeof(*data)];
+ int rval;
+
+ if (i2c_read(dspic_addr, reg, 2, buf, 2))
+ return -1;
+
+ rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
+ *data = (buf[0] << 8) | buf[1];
+
+ return rval;
+}
+
+
+/***********************************************************************
+F* Function: int misc_init_r (void) P*A*Z*
+ *
+P* Parameters: none
+P*
+P* Returnvalue: int
+P* - 0 is always returned, even in the case of a keyboard
+P* error.
+ *
+Z* Intention: This function is the misc_init_r() method implementation
+Z* for the lwmon board.
+Z* The keyboard controller is initialized and the result
+Z* of a read copied to the environment variable "keybd".
+Z* If KEYBD_SET_DEBUGMODE is defined, a check is made for
+Z* this key, and if found display to the LCD will be enabled.
+Z* The keys in "keybd" are checked against the magic
+Z* keycommands defined in the environment.
+Z* See also key_match().
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int misc_init_r_kbd (void)
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
+ uchar kbd_init_status = gd->arch.kbd_status >> 8;
+ uchar kbd_status = gd->arch.kbd_status;
+ uchar val;
+ ushort data, inv_data;
+ char *str;
+ int i;
+
+ if (kbd_init_status) {
+ printf ("KEYBD: Error %02X\n", kbd_init_status);
+ }
+ if (kbd_status) { /* permanent error, report it */
+ printf ("*** Keyboard error code %02X ***\n", kbd_status);
+ sprintf (keybd_env, "%02X", kbd_status);
+ setenv ("keybd", keybd_env);
+ return 0;
+ }
+
+ /*
+ * Now we know that we have a working keyboard, so disable
+ * all output to the LCD except when a key press is detected.
+ */
+
+ if ((console_assign (stdout, "serial") < 0) ||
+ (console_assign (stderr, "serial") < 0)) {
+ printf ("Can't assign serial port as output device\n");
+ }
+
+ /* Read Version */
+ val = KEYBD_CMD_READ_VERSION;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
+ printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
+
+ /* Read current keyboard state */
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ /* read out start key from bse01 received via can */
+ _dspic_read(DSPIC_PON_STATUS_REG, &data);
+ /* check highbyte from status register */
+ if (data > 0xFF) {
+ _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
+
+ /* check inverse data */
+ if ((data+inv_data) == 0xFFFF) {
+ /* don't overwrite local key */
+ if (kbd_data[1] == 0) {
+ /* read key value */
+ _dspic_read(DSPIC_PON_KEY_REG, &data);
+ str = (char *)&data;
+ /* swap bytes */
+ kbd_data[1] = str[1];
+ kbd_data[2] = str[0];
+ printf("CAN received startkey: 0x%X\n", data);
+ }
+ }
+ }
+
+ for (i = 0; i < KEYBD_DATALEN; ++i) {
+ sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+ }
+
+ setenv ("keybd", keybd_env);
+
+ str = strdup ((char *)key_match (kbd_data)); /* decode keys */
+#ifdef KEYBD_SET_DEBUGMODE
+ if (kbd_data[0] == KEYBD_SET_DEBUGMODE) { /* set debug mode */
+ if ((console_assign (stdout, "lcd") < 0) ||
+ (console_assign (stderr, "lcd") < 0)) {
+ printf ("Can't assign LCD display as output device\n");
+ }
+ }
+#endif /* KEYBD_SET_DEBUGMODE */
+#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
+ setenv ("preboot", str); /* set or delete definition */
+#endif /* CONFIG_PREBOOT */
+ if (str != NULL) {
+ free (str);
+ }
+ return (0);
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+static int compare_magic (uchar *kbd_data, uchar *str)
+{
+ uchar compare[KEYBD_DATALEN-1];
+ char *nxt;
+ int i;
+
+ /* Don't include modifier byte */
+ memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
+
+ for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
+ uchar c;
+ int k;
+
+ c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
+
+ if (str == (uchar *)nxt) { /* invalid character */
+ break;
+ }
+
+ /*
+ * Check if this key matches the input.
+ * Set matches to zero, so they match only once
+ * and we can find duplicates or extra keys
+ */
+ for (k = 0; k < sizeof(compare); ++k) {
+ if (compare[k] == '\0') /* only non-zero entries */
+ continue;
+ if (c == compare[k]) { /* found matching key */
+ compare[k] = '\0';
+ break;
+ }
+ }
+ if (k == sizeof(compare)) {
+ return -1; /* unmatched key */
+ }
+ }
+
+ /*
+ * A full match leaves no keys in the `compare' array,
+ */
+ for (i = 0; i < sizeof(compare); ++i) {
+ if (compare[i])
+ {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/***********************************************************************
+F* Function: static uchar *key_match (uchar *kbd_data) P*A*Z*
+ *
+P* Parameters: uchar *kbd_data
+P* - The keys to match against our magic definitions
+P*
+P* Returnvalue: uchar *
+P* - != NULL: Pointer to the corresponding command(s)
+P* NULL: No magic is about to happen
+ *
+Z* Intention: Check if pressed key(s) match magic sequence,
+Z* and return the command string associated with that key(s).
+Z*
+Z* If no key press was decoded, NULL is returned.
+Z*
+Z* Note: the first character of the argument will be
+Z* overwritten with the "magic charcter code" of the
+Z* decoded key(s), or '\0'.
+Z*
+Z* Note: the string points to static environment data
+Z* and must be saved before you call any function that
+Z* modifies the environment.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+static uchar *key_match (uchar *kbd_data)
+{
+ char magic[sizeof (kbd_magic_prefix) + 1];
+ uchar *suffix;
+ char *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can pe appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+ kbd_magic_keys = "";
+
+ /* loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
+ sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+ debug ("### Check magic \"%s\"\n", magic);
+ if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
+ char cmd_name[sizeof (kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+
+ cmd = getenv (cmd_name);
+ debug ("### Set PREBOOT to $(%s): \"%s\"\n",
+ cmd_name, cmd ? cmd : "<<NULL>>");
+ *kbd_data = *suffix;
+ return ((uchar *)cmd);
+ }
+ }
+ debug ("### Delete PREBOOT\n");
+ *kbd_data = '\0';
+ return (NULL);
+}
+#endif /* CONFIG_PREBOOT */
+
+/***********************************************************************
+F* Function: int do_kbd (cmd_tbl_t *cmdtp, int flag,
+F* int argc, char * const argv[]) P*A*Z*
+ *
+P* Parameters: cmd_tbl_t *cmdtp
+P* - Pointer to our command table entry
+P* int flag
+P* - If the CMD_FLAG_REPEAT bit is set, then this call is
+P* a repetition
+P* int argc
+P* - Argument count
+P* char * const argv[]
+P* - Array of the actual arguments
+P*
+P* Returnvalue: int
+P* - 0 is always returned.
+ *
+Z* Intention: Implement the "kbd" command.
+Z* The keyboard status is read. The result is printed on
+Z* the console and written into the "keybd" environment
+Z* variable.
+ *
+D* Design: wd@denx.de
+C* Coding: wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
+ uchar val;
+ int i;
+
+#if 0 /* Done in kbd_init */
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+ /* Read keys */
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ puts ("Keys:");
+ for (i = 0; i < KEYBD_DATALEN; ++i) {
+ sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+ printf (" %02x", kbd_data[i]);
+ }
+ putc ('\n');
+ setenv ("keybd", keybd_env);
+ return 0;
+}
+
+U_BOOT_CMD(
+ kbd, 1, 1, do_kbd,
+ "read keyboard status",
+ ""
+);
+
+/*----------------------------- Utilities -----------------------------*/
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ uchar val;
+
+ /* Read keys */
+ val = KEYBD_CMD_READ_KEYS;
+ i2c_write (kbd_addr, 0, 0, &val, 1);
+ i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+ return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
+}
+#endif
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
new file mode 100644
index 0000000..e9aa0b7
--- /dev/null
+++ b/board/lwmon5/lwmon5.c
@@ -0,0 +1,558 @@
+/*
+ * (C) Copyright 2007-2013
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/ppc440.h>
+#include <asm/processor.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/io.h>
+#include <post.h>
+#include <flash.h>
+#include <mtd/cfi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
+
+ulong flash_get_size(ulong base, int banknum);
+int misc_init_r_kbd(void);
+
+int board_early_init_f(void)
+{
+ u32 sdr0_pfc1, sdr0_pfc2;
+ u32 reg;
+
+ /* PLB Write pipelining disabled. Denali Core workaround */
+ mtdcr(PLB4A0_ACR, 0xDE000000);
+ mtdcr(PLB4A1_ACR, 0xDE000000);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
+ mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
+ mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
+ mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
+ mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ /* Trace Pins are disabled. SDR0_PFC0 Register */
+ mtsdr(SDR0_PFC0, 0x0);
+
+ /* select Ethernet pins */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ /* SMII via ZMII */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
+ SDR0_PFC1_SELECT_CONFIG_6;
+ mfsdr(SDR0_PFC2, sdr0_pfc2);
+ sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
+ SDR0_PFC2_SELECT_CONFIG_6;
+
+ /* enable SPI (SCP) */
+ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
+
+ mtsdr(SDR0_PFC2, sdr0_pfc2);
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+
+ mtsdr(SDR0_PFC4, 0x80000000);
+
+ /* PCI arbiter disabled */
+ /* PCI Host Configuration disbaled */
+ mfsdr(SDR0_PCI0, reg);
+ reg = 0;
+ mtsdr(SDR0_PCI0, 0x00000000 | reg);
+
+ gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
+
+#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
+ /* enable the LSB transmitter */
+ gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
+ /* enable the CAN transmitter */
+ gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
+
+ reg = 0; /* reuse as counter */
+ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
+ in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
+ & ~CONFIG_SYS_DSPIC_TEST_MASK);
+ while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
+ udelay(1000);
+ }
+ if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
+ /* set "boot error" flag */
+ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
+ in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
+ CONFIG_SYS_DSPIC_TEST_MASK);
+ }
+#endif
+
+ /*
+ * Reset PHY's:
+ * The PHY's need a 2nd reset pulse, since the MDIO address is latched
+ * upon reset, and with the first reset upon powerup, the addresses are
+ * not latched reliable, since the IRQ line is multiplexed with an
+ * MDIO address. A 2nd reset at this time will make sure, that the
+ * correct address is latched.
+ */
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
+ udelay(1000);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
+ udelay(1000);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
+ gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
+
+ return 0;
+}
+
+/*
+ * Override weak default with board specific version
+ */
+phys_addr_t cfi_flash_bank_addr(int bank)
+{
+ return lwmon5_cfi_flash_bank_addr[bank];
+}
+
+/*
+ * Override the weak default mapping function with a board specific one
+ */
+u32 flash_get_bank_size(int cs, int idx)
+{
+ return flash_info[idx].size;
+}
+
+int board_early_init_r(void)
+{
+ u32 val0, val1;
+
+ /*
+ * lwmon5 is manufactured in 2 different board versions:
+ * The lwmon5a board has 64MiB NOR flash instead of the
+ * 128MiB of the original lwmon5. Unfortunately the CFI driver
+ * will report 2 banks of 64MiB even for the smaller flash
+ * chip, since the bank is mirrored. To fix this, we bring
+ * one bank into CFI query mode and read its response. This
+ * enables us to detect the real number of flash devices/
+ * banks which will be used later on by the common CFI driver.
+ */
+
+ /* Put bank 0 into CFI command mode and read */
+ out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
+ val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
+ val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
+
+ /* Reset flash again out of query mode */
+ out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
+
+ /* When not identical, we have 2 different flash devices/banks */
+ if (val0 != val1)
+ return 0;
+
+ /*
+ * Now we're sure that we're running on a LWMON5a board with
+ * only 64MiB NOR flash in one bank:
+ *
+ * Set flash base address and bank count for CFI driver probing.
+ */
+ cfi_flash_num_flash_banks = 1;
+ lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u32 pbcr;
+ int size_val = 0;
+ u32 reg;
+#ifndef CONFIG_LCD4_LWMON5
+ unsigned long usb2d0cr = 0;
+ unsigned long usb2phy0cr, usb2h0cr = 0;
+ unsigned long sdr0_pfc1, sdr0_srst;
+#endif
+
+ /*
+ * FLASH stuff...
+ */
+
+ /* Re-do sizing to get full correct info */
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ mfebc(PB0CR, pbcr);
+ size_val = ffs(gd->bd->bi_flashsize) - 21;
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtebc(PB0CR, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+ /* Monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
+ &flash_info[cfi_flash_num_flash_banks - 1]);
+
+ /* Env protection ON by default */
+ flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[cfi_flash_num_flash_banks - 1]);
+
+#ifndef CONFIG_LCD4_LWMON5
+ /*
+ * USB suff...
+ */
+
+ /* Reset USB */
+ /* Reset of USB2PHY0 must be active at least 10 us */
+ mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
+ udelay(2000);
+
+ mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
+ SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
+ SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
+ udelay(2000);
+
+ /* Errata CHIP_6 */
+
+ /* 1. Set internal PHY configuration */
+ /* SDR Setting */
+ mfsdr(SDR0_PFC1, sdr0_pfc1);
+ mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mfsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
+ usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
+ usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
+
+ /*
+ * An 8-bit/60MHz interface is the only possible alternative
+ * when connecting the Device to the PHY
+ */
+ usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
+ usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
+
+ mtsdr(SDR0_PFC1, sdr0_pfc1);
+ mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
+ mtsdr(SDR0_USB2H0CR, usb2h0cr);
+
+ /* 2. De-assert internal PHY reset */
+ mfsdr(SDR0_SRST1, sdr0_srst);
+ sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
+ mtsdr(SDR0_SRST1, sdr0_srst);
+
+ /* 3. Wait for more than 1 ms */
+ udelay(2000);
+
+ /* 4. De-assert USB 2.0 Host main reset */
+ mfsdr(SDR0_SRST0, sdr0_srst);
+ sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
+ mtsdr(SDR0_SRST0, sdr0_srst);
+ udelay(1000);
+
+ /* 5. De-assert reset of OPB2 cores */
+ mfsdr(SDR0_SRST1, sdr0_srst);
+ sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
+ sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
+ sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
+ mtsdr(SDR0_SRST1, sdr0_srst);
+ udelay(1000);
+
+ /* 6. Set EHCI Configure FLAG */
+
+ /* 7. Reassert internal PHY reset: */
+ mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
+ udelay(1000);
+#endif
+
+ /*
+ * Clear resets
+ */
+ mtsdr(SDR0_SRST1, 0x00000000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+#ifndef CONFIG_LCD4_LWMON5
+ printf("USB: Host(int phy) Device(ext phy)\n");
+#endif
+
+ /*
+ * Clear PLB4A0_ACR[WRP]
+ * This fix will make the MAL burst disabling patch for the Linux
+ * EMAC driver obsolete.
+ */
+ reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
+ mtdcr(PLB4A0_ACR, reg);
+
+#ifndef CONFIG_LCD4_LWMON5
+ /*
+ * Init matrix keyboard
+ */
+ misc_init_r_kbd();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: %s", __stringify(CONFIG_HOSTNAME));
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+void hw_watchdog_reset(void)
+{
+ int val;
+#if defined(CONFIG_WD_MAX_RATE)
+ unsigned long long ct = get_ticks();
+
+ /*
+ * Don't allow watch-dog triggering more frequently than
+ * the predefined value CONFIG_WD_MAX_RATE [ticks].
+ */
+ if (ct >= gd->arch.wdt_last) {
+ if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
+ return;
+ } else {
+ /* Time base counter had been reset */
+ if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
+ CONFIG_WD_MAX_RATE)
+ return;
+ }
+ gd->arch.wdt_last = get_ticks();
+#endif
+
+ /*
+ * Toggle watchdog output
+ */
+ val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
+ gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
+}
+
+int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ if ((strcmp(argv[1], "on") == 0))
+ gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
+ else if ((strcmp(argv[1], "off") == 0))
+ gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
+ else
+ return cmd_usage(cmdtp);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ eepromwp, 2, 0, do_eeprom_wp,
+ "eeprom write protect off/on",
+ "<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
+);
+
+#if defined(CONFIG_VIDEO)
+#include <video_fb.h>
+#include <mb862xx.h>
+
+extern GraphicDevice mb862xx;
+
+static const gdc_regs init_regs [] = {
+ { 0x0100, 0x00000f00 },
+ { 0x0020, 0x801401df },
+ { 0x0024, 0x00000000 },
+ { 0x0028, 0x00000000 },
+ { 0x002c, 0x00000000 },
+ { 0x0110, 0x00000000 },
+ { 0x0114, 0x00000000 },
+ { 0x0118, 0x01df0280 },
+ { 0x0004, 0x031f0000 },
+ { 0x0008, 0x027f027f },
+ { 0x000c, 0x015f028f },
+ { 0x0010, 0x020c0000 },
+ { 0x0014, 0x01df01ea },
+ { 0x0018, 0x00000000 },
+ { 0x001c, 0x01e00280 },
+ { 0x0100, 0x80010f00 },
+ { 0x0, 0x0 }
+};
+
+const gdc_regs *board_get_regs(void)
+{
+ return init_regs;
+}
+
+/* Returns Lime base address */
+unsigned int board_video_init(void)
+{
+ /*
+ * Reset Lime controller
+ */
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
+ udelay(500);
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
+
+ mb862xx.winSizeX = 640;
+ mb862xx.winSizeY = 480;
+ mb862xx.gdfBytesPP = 2;
+ mb862xx.gdfIndex = GDF_15BIT_555RGB;
+
+ return CONFIG_SYS_LIME_BASE_0;
+}
+
+#define DEFAULT_BRIGHTNESS 0x64
+
+static void board_backlight_brightness(int brightness)
+{
+ if (brightness > 0) {
+ /* pwm duty, lamp on */
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
+ } else {
+ /* lamp off */
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
+ }
+}
+
+void board_backlight_switch(int flag)
+{
+ char * param;
+ int rc;
+
+ if (flag) {
+ param = getenv("brightness");
+ rc = param ? simple_strtol(param, NULL, 10) : -1;
+ if (rc < 0)
+ rc = DEFAULT_BRIGHTNESS;
+ } else {
+ rc = 0;
+ }
+ board_backlight_brightness(rc);
+}
+
+#if defined(CONFIG_CONSOLE_EXTRA_INFO)
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str(int line_number, char *info)
+{
+ if (line_number == 1)
+ strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
+ else
+ info [0] = '\0';
+}
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
+#endif /* CONFIG_VIDEO */
+
+void board_reset(void)
+{
+ gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * lwmon5 specific implementation of spl_start_uboot()
+ *
+ * RETURN
+ * 0 if booting into OS is selected (default)
+ * 1 if booting into U-Boot is selected
+ */
+int spl_start_uboot(void)
+{
+ char s[8];
+
+ env_init();
+ getenv_f("boot_os", s, sizeof(s));
+ if ((s != NULL) && (strcmp(s, "yes") == 0))
+ return 0;
+
+ return 1;
+}
+
+/*
+ * This function is called from the SPL U-Boot version for
+ * early init stuff, that needs to be done for OS (e.g. Linux)
+ * booting. Doing it later in the real U-Boot would not work
+ * in case that the SPL U-Boot boots Linux directly.
+ */
+void spl_board_init(void)
+{
+ const gdc_regs *regs = board_get_regs();
+
+ /*
+ * Setup PFC registers, mainly for ethernet support
+ * later on in Linux
+ */
+ board_early_init_f();
+
+ /* enable the LSB transmitter */
+ gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
+
+ /*
+ * Clear resets
+ */
+ mtsdr(SDR0_SRST1, 0x00000000);
+ mtsdr(SDR0_SRST0, 0x00000000);
+
+ /*
+ * Reset Lime controller
+ */
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
+ udelay(500);
+ gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
+
+ out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
+ udelay(300);
+ out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
+
+ while (regs->index) {
+ out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
+ regs->index, regs->value);
+ regs++;
+ }
+
+ board_backlight_brightness(DEFAULT_BRIGHTNESS);
+}
+#endif
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
new file mode 100644
index 0000000..5dfbb0b
--- /dev/null
+++ b/board/lwmon5/sdram.c
@@ -0,0 +1,247 @@
+/*
+ * (C) Copyright 2006
+ * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
+ *
+ * (C) Copyright 2007-2013
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/ppc440.h>
+#include <watchdog.h>
+
+/*
+ * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
+ * region. Right now the cache should still be disabled in U-Boot because of the
+ * EMAC driver, that need it's buffer descriptor to be located in non cached
+ * memory.
+ *
+ * If at some time this restriction doesn't apply anymore, just define
+ * CONFIG_4xx_DCACHE in the board config file and this code should setup
+ * everything correctly.
+ */
+#ifdef CONFIG_4xx_DCACHE
+#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
+#else
+#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
+#endif
+
+/*-----------------------------------------------------------------------------+
+ * Prototypes
+ *-----------------------------------------------------------------------------*/
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
+extern void dcbz_area(u32 start_address, u32 num_bytes);
+
+static u32 is_ecc_enabled(void)
+{
+ u32 val;
+
+ mfsdram(DDR0_22, val);
+ val &= DDR0_22_CTRL_RAW_MASK;
+ if (val)
+ return 1;
+ else
+ return 0;
+}
+
+void board_add_ram_info(int use_default)
+{
+ PPC4xx_SYS_INFO board_cfg;
+ u32 val;
+
+ if (is_ecc_enabled())
+ puts(" (ECC");
+ else
+ puts(" (ECC not");
+
+ get_sys_info(&board_cfg);
+ printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
+
+ mfsdram(DDR0_03, val);
+ val = DDR0_03_CASLAT_DECODE(val);
+ printf(", CL%d)", val);
+}
+
+#ifdef CONFIG_DDR_ECC
+static void wait_ddr_idle(void)
+{
+ /*
+ * Controller idle status cannot be determined for Denali
+ * DDR2 code. Just return here.
+ */
+}
+
+static void program_ecc(u32 start_address,
+ u32 num_bytes,
+ u32 tlb_word2_i_value)
+{
+ u32 val;
+ u32 current_addr = start_address;
+ u32 size;
+ int bytes_remaining;
+
+ sync();
+ wait_ddr_idle();
+
+ /*
+ * Because of 440EPx errata CHIP 11, we don't touch the last 256
+ * bytes of SDRAM.
+ */
+ bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
+
+ /*
+ * We have to write the ECC bytes by zeroing and flushing in smaller
+ * steps, since the whole 256MByte takes too long for the external
+ * watchdog.
+ */
+ while (bytes_remaining > 0) {
+ size = min((64 << 20), bytes_remaining);
+
+ /* Write zero's to SDRAM */
+ dcbz_area(current_addr, size);
+
+ /* Write modified dcache lines back to memory */
+ clean_dcache_range(current_addr, current_addr + size);
+
+ current_addr += 64 << 20;
+ bytes_remaining -= 64 << 20;
+ WATCHDOG_RESET();
+ }
+
+ sync();
+ wait_ddr_idle();
+
+ /* Clear error status */
+ mfsdram(DDR0_00, val);
+ mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
+
+ /* Set 'int_mask' parameter to functionnal value */
+ mfsdram(DDR0_01, val);
+ mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
+
+ sync();
+ wait_ddr_idle();
+}
+#endif
+
+/*************************************************************************
+ *
+ * initdram -- 440EPx's DDR controller is a DENALI Core
+ *
+ ************************************************************************/
+phys_size_t initdram (int board_type)
+{
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_LCD4_LWMON5)
+ /* CL=4 */
+ mtsdram(DDR0_02, 0x00000000);
+
+ mtsdram(DDR0_00, 0x0000190A);
+ mtsdram(DDR0_01, 0x01000000);
+ mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
+
+ mtsdram(DDR0_04, 0x0B030300);
+ mtsdram(DDR0_05, 0x02020308);
+ mtsdram(DDR0_06, 0x0003C812);
+ mtsdram(DDR0_07, 0x00090100);
+ mtsdram(DDR0_08, 0x03c80001);
+ mtsdram(DDR0_09, 0x00011D5F);
+ mtsdram(DDR0_10, 0x00000100);
+ mtsdram(DDR0_11, 0x000CC800);
+ mtsdram(DDR0_12, 0x00000003);
+ mtsdram(DDR0_14, 0x00000000);
+ mtsdram(DDR0_17, 0x1e000000);
+ mtsdram(DDR0_18, 0x1e1e1e1e);
+ mtsdram(DDR0_19, 0x1e1e1e1e);
+ mtsdram(DDR0_20, 0x0B0B0B0B);
+ mtsdram(DDR0_21, 0x0B0B0B0B);
+#ifdef CONFIG_DDR_ECC
+ mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
+#else
+ mtsdram(DDR0_22, 0x00267F0B);
+#endif
+
+ mtsdram(DDR0_23, 0x01000000);
+ mtsdram(DDR0_24, 0x01010001);
+
+ mtsdram(DDR0_26, 0x2D93028A);
+ mtsdram(DDR0_27, 0x0784682B);
+
+ mtsdram(DDR0_28, 0x00000080);
+ mtsdram(DDR0_31, 0x00000000);
+ mtsdram(DDR0_42, 0x01000008);
+
+ mtsdram(DDR0_43, 0x050A0200);
+ mtsdram(DDR0_44, 0x00000005);
+ mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
+
+ denali_wait_for_dlllock();
+
+#if defined(CONFIG_DDR_DATA_EYE)
+ /* -----------------------------------------------------------+
+ * Perform data eye search if requested.
+ * ----------------------------------------------------------*/
+ program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
+ TLB_WORD2_I_ENABLE);
+ denali_core_search_data_eye();
+ remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
+#endif
+
+ /*
+ * Program tlb entries for this size (dynamic)
+ */
+ program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
+ MY_TLB_WORD2_I_ENABLE);
+
+#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_4xx_DCACHE)
+ /*
+ * If ECC is enabled, initialize the parity bits.
+ */
+ program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+#else /* CONFIG_4xx_DCACHE */
+ /*
+ * Setup 2nd TLB with same physical address but different virtual address
+ * with cache enabled. This is done for fast ECC generation.
+ */
+ program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+
+ /*
+ * If ECC is enabled, initialize the parity bits.
+ */
+ program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
+
+ /*
+ * Now after initialization (auto-calibration and ECC generation)
+ * remove the TLB entries with caches enabled and program again with
+ * desired cache functionality
+ */
+ remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
+#endif /* CONFIG_4xx_DCACHE */
+#endif /* CONFIG_DDR_ECC */
+
+ /*
+ * Clear possible errors resulting from data-eye-search.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+#endif /* CONFIG_SPL_BUILD */
+
+ return (CONFIG_SYS_MBYTES_SDRAM << 20);
+}
diff --git a/board/matrix_vision/mvblx/Kconfig b/board/matrix_vision/mvblx/Kconfig
new file mode 100644
index 0000000..adbc20a
--- /dev/null
+++ b/board/matrix_vision/mvblx/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP3_MVBLX
+
+config SYS_BOARD
+ default "mvblx"
+
+config SYS_VENDOR
+ default "matrix_vision"
+
+config SYS_CONFIG_NAME
+ default "omap3_mvblx"
+
+endif
diff --git a/board/matrix_vision/mvblx/MAINTAINERS b/board/matrix_vision/mvblx/MAINTAINERS
new file mode 100644
index 0000000..2f9a153
--- /dev/null
+++ b/board/matrix_vision/mvblx/MAINTAINERS
@@ -0,0 +1,6 @@
+MVBLX BOARD
+M: Michael Jones <michael.jones@matrix-vision.de>
+S: Maintained
+F: board/matrix_vision/mvblx/
+F: include/configs/omap3_mvblx.h
+F: configs/omap3_mvblx_defconfig
diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile
new file mode 100644
index 0000000..c056eba
--- /dev/null
+++ b/board/matrix_vision/mvblx/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += mvblx.o fpga.o
+obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
+
+ccflags-y += -Werror
diff --git a/board/matrix_vision/mvblx/config.mk b/board/matrix_vision/mvblx/config.mk
new file mode 100644
index 0000000..de13072
--- /dev/null
+++ b/board/matrix_vision/mvblx/config.mk
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c
new file mode 100644
index 0000000..7f9b245
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.c
@@ -0,0 +1,214 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * (C) Copyright 2011
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
+ * Michael Jones, Matrix Vision GmbH, michael.jones@matrix-vision.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include <asm/gpio.h>
+#include <linux/byteorder/generic.h>
+#include "fpga.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+ fpga_null_fn, /* Altera_pre_fn */
+ fpga_config_fn,
+ fpga_status_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_null_fn,
+ fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+ Altera_CYC2,
+ fast_passive_parallel,
+ Altera_EP3C5_SIZE,
+ (void *) &altera_fns,
+ NULL,
+ 0
+};
+
+#define GPIO_RESET 43
+#define GPIO_DCLK 65
+#define GPIO_nSTATUS 157
+#define GPIO_CONF_DONE 158
+#define GPIO_nCONFIG 159
+#define GPIO_DATA0 54
+#define GPIO_DATA1 55
+#define GPIO_DATA2 56
+#define GPIO_DATA3 57
+#define GPIO_DATA4 58
+#define GPIO_DATA5 60
+#define GPIO_DATA6 61
+#define GPIO_DATA7 62
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* return FPGA_SUCCESS on success, else FPGA_FAIL
+ */
+int mvblx_init_fpga(void)
+{
+ fpga_debug("Initializing FPGA interface\n");
+ fpga_init();
+ fpga_add(fpga_altera, &cyclone2);
+
+ if (gpio_request(GPIO_DCLK, "dclk") ||
+ gpio_request(GPIO_nSTATUS, "nStatus") ||
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ gpio_request(GPIO_CONF_DONE, "conf_done") ||
+#endif
+ gpio_request(GPIO_nCONFIG, "nConfig") ||
+ gpio_request(GPIO_DATA0, "data0") ||
+ gpio_request(GPIO_DATA1, "data1") ||
+ gpio_request(GPIO_DATA2, "data2") ||
+ gpio_request(GPIO_DATA3, "data3") ||
+ gpio_request(GPIO_DATA4, "data4") ||
+ gpio_request(GPIO_DATA5, "data5") ||
+ gpio_request(GPIO_DATA6, "data6") ||
+ gpio_request(GPIO_DATA7, "data7")) {
+ printf("%s: error requesting GPIOs.", __func__);
+ return FPGA_FAIL;
+ }
+
+ /* set up outputs */
+ gpio_direction_output(GPIO_DCLK, 0);
+ gpio_direction_output(GPIO_nCONFIG, 0);
+ gpio_direction_output(GPIO_DATA0, 0);
+ gpio_direction_output(GPIO_DATA1, 0);
+ gpio_direction_output(GPIO_DATA2, 0);
+ gpio_direction_output(GPIO_DATA3, 0);
+ gpio_direction_output(GPIO_DATA4, 0);
+ gpio_direction_output(GPIO_DATA5, 0);
+ gpio_direction_output(GPIO_DATA6, 0);
+ gpio_direction_output(GPIO_DATA7, 0);
+
+ /* NB omap_free_gpio() resets to an input, so we can't
+ * free ie. nCONFIG, or else the FPGA would reset
+ * Q: presumably gpio_free() has the same effect?
+ */
+
+ /* set up inputs */
+ gpio_direction_input(GPIO_nSTATUS);
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ gpio_direction_input(GPIO_CONF_DONE);
+#endif
+
+ fpga_config_fn(0, 1, 0);
+ udelay(60);
+
+ return FPGA_SUCCESS;
+}
+
+int fpga_null_fn(int cookie)
+{
+ return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+ fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
+ if (flush) {
+ gpio_set_value(GPIO_nCONFIG, !assert);
+ udelay(1);
+ gpio_set_value(GPIO_nCONFIG, assert);
+ }
+
+ return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+ int result = 0;
+
+ /* since revA of BLX, we will not get this signal. */
+ udelay(10);
+#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ fpga_debug("not waiting for CONF_DONE.");
+ result = 1;
+#else
+ fpga_debug("CONF_DONE check ... ");
+ if (gpio_get_value(GPIO_CONF_DONE)) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+ gpio_free(GPIO_CONF_DONE);
+#endif
+
+ return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+ int result = 0;
+ fpga_debug("STATUS check ... ");
+
+ result = gpio_get_value(GPIO_nSTATUS);
+
+ if (result < 0)
+ fpga_debug("error\n");
+ else if (result > 0)
+ fpga_debug("high\n");
+ else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+static inline int _write_fpga(u8 byte)
+{
+ gpio_set_value(GPIO_DATA0, byte & 0x01);
+ gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01);
+ gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01);
+ gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01);
+ gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01);
+ gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01);
+ gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01);
+ gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01);
+
+ /* clock */
+ gpio_set_value(GPIO_DCLK, 1);
+ udelay(1);
+ gpio_set_value(GPIO_DCLK, 0);
+ udelay(1);
+
+ return 0;
+}
+
+int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
+{
+ unsigned char *data = (unsigned char *) buf;
+ int i;
+ int headerlen = len - cyclone2.size;
+
+ if (headerlen < 0)
+ return FPGA_FAIL;
+ else if (headerlen == sizeof(uint32_t)) {
+ const unsigned int fpgavers_len = 11; /* '0x' + 8 hex digits + \0 */
+ char fpgavers_str[fpgavers_len];
+ snprintf(fpgavers_str, fpgavers_len, "0x%08x",
+ be32_to_cpup((uint32_t*)data));
+ setenv("fpgavers", fpgavers_str);
+ }
+
+ fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+ for (i = headerlen; i < len; i++)
+ _write_fpga(data[i]);
+ fpga_debug("-%s\n", __func__);
+
+ return FPGA_SUCCESS;
+}
diff --git a/board/matrix_vision/mvblx/fpga.h b/board/matrix_vision/mvblx/fpga.h
new file mode 100644
index 0000000..411b039
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.h
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+extern int mvblx_init_fpga(void);
+
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c
new file mode 100644
index 0000000..c9d615b
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.c
@@ -0,0 +1,159 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from Beagle and Overo
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "mvblx.h"
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ printf("mvBlueLYNX-X\n");
+ if (get_cpu_family() == CPU_OMAP36XX)
+ setenv("mpurate", "1000");
+ else
+ setenv("mpurate", "600");
+
+ twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif /* CONFIG_CMD_NET */
+
+ mvblx_init_fpga();
+
+ mac_read_from_eeprom();
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_MVBLX();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
+ return 0;
+}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+ twl4030_power_mmc_init(1);
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Configure GPMC registers */
+ writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
+ writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
+ writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
+ writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
+ writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
+ writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
+ writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 139 as output pin */
+ writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
+
+ /* Now send a pulse on the GPIO pin */
+ writel(GPIO11, &gpio5_base->setdataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->cleardataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->setdataout);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+int overwrite_console(void)
+{
+ /* return true if console should be overwritten */
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET */
diff --git a/board/matrix_vision/mvblx/mvblx.h b/board/matrix_vision/mvblx/mvblx.h
new file mode 100644
index 0000000..6c1c752
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.h
@@ -0,0 +1,346 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _MVBLX_H_
+#define _MVBLX_H_
+
+#include <asm/arch/sys_proto.h>
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 mvBlueLYNX-X camera",
+ "no NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_MVBLX() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M4)) /*GPIO_41*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO_42*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO_43*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO54*/\
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)) /*GPIO55*/\
+ MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) /*GPIO56*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) /*GPIO57*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) /*GPIO58*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IEN | PTU | EN | M4)) /*GPIO60*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M4)) /*GPIO61*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTU | EN | M4)) /*GPIO62*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)) /*GPIO65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card 1*/\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M7)) /*GPIO_129 disabled*/\
+ /*Expansion card 2 */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M1)) /*UART2_RX*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IDIS | PTU | DIS | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTU | DIS | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IDIS | PTU | DIS | M4)) /*GPIO_173*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M4)) /*GPIO_174*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /*GPIO_177*/\
+ /* USB EHCI (port 2) not used */\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+ MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+ MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) /*GPIO_10*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT2*/\
+ /* USB EHCI (port 1) */\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M4)) /*GPIO_29*/\
+ /*Die to Die */\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+#endif
diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c
new file mode 100644
index 0000000..db42987
--- /dev/null
+++ b/board/matrix_vision/mvblx/sys_eeprom.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun@freescale.com)
+ * Haiying Wang (haiying.wang@freescale.com)
+ * Timur Tabi (timur@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+/* #define DEBUG */
+
+/*
+ * static eeprom: EEPROM layout
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+ u8 id[16]; /* 0x01 - 0x0F Type e.g. 100wG-5111 */
+ u8 sn[10]; /* 0x10 - 0x19 Serial Number */
+ u8 date[6]; /* 0x1A - 0x1F Build Date */
+ u8 mac[6]; /* 0x20 - 0x25 MAC address */
+ u8 reserved[10];/* 0x26 - 0x2f reserved */
+ u32 crc; /* x+1 CRC32 checksum */
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+ unsigned int crc;
+ char safe_string[16];
+
+#ifdef DEBUG
+ int i;
+#endif
+ u8 *p;
+
+ /* ID */
+ strncpy(safe_string, (char *)e.id, sizeof(e.id));
+ safe_string[sizeof(e.id)-1] = 0;
+ printf("ID: mvBlueLYNX-X%s\n", safe_string);
+
+ /* Serial number */
+ strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
+ safe_string[sizeof(e.sn)-1] = 0;
+ printf("SN: %s\n", safe_string);
+
+ /* Build date, BCD date values, as YYMMDDhhmmss */
+ printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+ e.date[0], e.date[1], e.date[2],
+ e.date[3] & 0x7F, e.date[4], e.date[5],
+ e.date[3] & 0x80 ? "PM" : "");
+
+ /* Show MAC address */
+ p = e.mac;
+ printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ p[0], p[1], p[2], p[3], p[4], p[5]);
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+ if (crc == be32_to_cpu(e.crc))
+ printf("CRC: %08x\n", be32_to_cpu(e.crc));
+ else
+ printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+ printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+ for (i = 0; i < sizeof(e); i++) {
+ if ((i % 16) == 0)
+ printf("%02X: ", i);
+ printf("%02X ", ((u8 *)&e)[i]);
+ if (((i % 16) == 15) || (i == sizeof(e) - 1))
+ printf("\n");
+ }
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
+{
+ int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ if (has_been_read)
+ return 0;
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+#ifdef DEBUG
+ show_eeprom();
+#endif
+
+ has_been_read = (ret == 0) ? 1 : 0;
+
+ return ret;
+}
+
+/**
+ * update_crc - update the CRC
+ *
+ * This function should be called after each update to the EEPROM structure,
+ * to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+ u32 crc;
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+ e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+ int ret = 0;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ update_crc();
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct eeprom e2;
+#ifdef DEBUG
+ printf("%s verifying...\n", __func__);
+#endif
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e2, sizeof(e2));
+
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+ if (ret) {
+ printf("Programming failed.\n");
+ has_been_read = 0;
+ return -1;
+ }
+
+ printf("Programming passed.\n");
+ return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+ if ((p >= '0') && (p <= '9'))
+ return p - '0';
+
+ if ((p >= 'A') && (p <= 'F'))
+ return (p - 'A') + 10;
+
+ if ((p >= 'a') && (p <= 'f'))
+ return (p - 'a') + 10;
+
+ return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+ unsigned int i;
+
+ if (strlen(string) != 12) {
+ printf("Usage: mac date YYMMDDhhmmss\n");
+ return;
+ }
+
+ for (i = 0; i < 6; i++)
+ e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+ update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in the MAC address field in the EEPROM local copy.
+ */
+static void set_mac_address(const char *string)
+{
+ char *p = (char *) string;
+ unsigned int i;
+
+ for (i = 0; *p && (i < 6); i++) {
+ e.mac[i] = simple_strtoul(p, &p, 16);
+ if (*p == ':')
+ p++;
+ }
+
+ update_crc();
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char cmd;
+
+ if (argc == 1) {
+ show_eeprom();
+ return 0;
+ }
+
+ cmd = argv[1][0];
+
+ if (cmd == 'r') {
+#ifdef DEBUG
+ printf("%s read\n", __func__);
+#endif
+ read_eeprom();
+ return 0;
+ }
+
+ if (argc == 2) {
+ switch (cmd) {
+ case 's': /* save */
+#ifdef DEBUG
+ printf("%s save\n", __func__);
+#endif
+ prog_eeprom();
+ break;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+ }
+
+ /* We know we have at least one parameter */
+
+ switch (cmd) {
+ case 'n': /* serial number */
+#ifdef DEBUG
+ printf("%s serial number\n", __func__);
+#endif
+ memset(e.sn, 0, sizeof(e.sn));
+ strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+ update_crc();
+ break;
+ case 'd': /* date BCD format YYMMDDhhmmss */
+ set_date(argv[2]);
+ break;
+ case 'e': /* errata */
+ printf("mac errata not implemented\n");
+ break;
+ case 'i': /* id */
+ memset(e.id, 0, sizeof(e.id));
+ strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
+ update_crc();
+ break;
+ case 'p': /* ports */
+ printf("mac ports not implemented (always 1 port)\n");
+ break;
+ case '0' ... '9':
+ /* we only have "mac 0" but any digit can be used here */
+ set_mac_address(argv[2]);
+ break;
+ case 'h': /* help */
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+static inline int is_portrait(void)
+{
+ int i;
+ unsigned int orient_index = 0; /* idx of char which determines orientation */
+
+ for (i = sizeof(e.id)/sizeof(*e.id) - 1; i>=0; i--) {
+ if (e.id[i] == '-') {
+ orient_index = i+1;
+ break;
+ }
+ }
+
+ return (orient_index &&
+ (e.id[orient_index] >= '5') && (e.id[orient_index] <= '8'));
+}
+
+int mac_read_from_eeprom(void)
+{
+ u32 crc, crc_offset = offsetof(struct eeprom, crc);
+ u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+#define FILENAME_LANDSCAPE "mvBlueLynx_X.rbf"
+#define FILENAME_PORTRAIT "mvBlueLynx_X_sensor_cd.rbf"
+
+ if (read_eeprom()) {
+ printf("EEPROM Read failed.\n");
+ return -1;
+ }
+
+ crc = crc32(0, (void *)&e, crc_offset);
+ crcp = (void *)&e + crc_offset;
+ if (crc != be32_to_cpu(*crcp)) {
+ printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
+ be32_to_cpu(e.crc));
+ return -1;
+ }
+
+ if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) &&
+ memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+ char ethaddr[18];
+
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ e.mac[0],
+ e.mac[1],
+ e.mac[2],
+ e.mac[3],
+ e.mac[4],
+ e.mac[5]);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("ethaddr"))
+ setenv("ethaddr", ethaddr);
+ }
+
+ if (memcmp(&e.sn, "\0\0\0\0\0\0\0\0\0\0", 10) &&
+ memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
+ char serial_num[12];
+
+ strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("serial#"))
+ setenv("serial#", serial_num);
+ }
+
+ /* decide which fpga file to load depending on orientation */
+ if (is_portrait())
+ setenv("fpgafilename", FILENAME_PORTRAIT);
+ else
+ setenv("fpgafilename", FILENAME_LANDSCAPE);
+
+ /* TODO should I calculate CRC here? */
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial = getenv("serial#");
+
+ if (serial && (strlen(serial) > 3)) {
+ /* use the numerical part of the serial number LXnnnnnn */
+ serialnr->high = 0;
+ serialnr->low = simple_strtoul(serial + 2, NULL, 10);
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+#endif
diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig
new file mode 100644
index 0000000..d833ca0
--- /dev/null
+++ b/board/maxbcm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MAXBCM
+
+config SYS_BOARD
+ default "maxbcm"
+
+config SYS_SOC
+ default "armada-xp"
+
+config SYS_CONFIG_NAME
+ default "maxbcm"
+
+endif
diff --git a/board/maxbcm/MAINTAINERS b/board/maxbcm/MAINTAINERS
new file mode 100644
index 0000000..3c8af21
--- /dev/null
+++ b/board/maxbcm/MAINTAINERS
@@ -0,0 +1,6 @@
+MAXBCM BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/maxbcm/
+F: include/configs/maxbcm.h
+F: configs/maxbcm_defconfig
diff --git a/board/maxbcm/Makefile b/board/maxbcm/Makefile
new file mode 100644
index 0000000..37c17d6
--- /dev/null
+++ b/board/maxbcm/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := maxbcm.o
diff --git a/board/maxbcm/binary.0 b/board/maxbcm/binary.0
new file mode 100644
index 0000000..17bfad9
--- /dev/null
+++ b/board/maxbcm/binary.0
@@ -0,0 +1,17 @@
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
+
+In a few weeks, mainline U-Boot will get support to generate the
+bin_hdr with the DDR training code itself. By implementing this code
+as SPL U-Boot. Then this file will not be needed any more and will
+get removed.
+
diff --git a/board/maxbcm/kwbimage.cfg b/board/maxbcm/kwbimage.cfg
new file mode 100644
index 0000000..5a3bc67
--- /dev/null
+++ b/board/maxbcm/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/maxbcm/binary.0 0000005b 00000068
diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c
new file mode 100644
index 0000000..7fc83ee
--- /dev/null
+++ b/board/maxbcm/maxbcm.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/mbus.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Base addresses for the external device chip selects */
+#define DEV_CS0_BASE 0xe0000000
+#define DEV_CS1_BASE 0xe1000000
+#define DEV_CS2_BASE 0xe2000000
+#define DEV_CS3_BASE 0xe3000000
+
+/* Needed for dynamic (board-specific) mbus configuration */
+extern struct mvebu_mbus_state mbus_state;
+
+int board_early_init_f(void)
+{
+ /*
+ * Don't configure MPP (pin multiplexing) and GPIO here,
+ * its already done in bin_hdr
+ */
+
+ /*
+ * Setup some board specific mbus address windows
+ */
+ mbus_dt_setup_win(&mbus_state, DEV_CS0_BASE, 16 << 20,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0);
+ mbus_dt_setup_win(&mbus_state, DEV_CS1_BASE, 16 << 20,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
+ mbus_dt_setup_win(&mbus_state, DEV_CS2_BASE, 16 << 20,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2);
+ mbus_dt_setup_win(&mbus_state, DEV_CS3_BASE, 16 << 20,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: maxBCM\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E6185 switch */
+void reset_phy(void)
+{
+ u16 devadr = CONFIG_PHY_BASE_ADDR;
+ char *name = "neta0";
+ u16 reg;
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* todo: fill this with the real setup / config code */
+
+ printf("88E6185 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
new file mode 100644
index 0000000..288a1ae
--- /dev/null
+++ b/board/micronas/vct/Kconfig
@@ -0,0 +1,36 @@
+if TARGET_VCT
+
+config SYS_BOARD
+ default "vct"
+
+config SYS_VENDOR
+ default "micronas"
+
+config SYS_CONFIG_NAME
+ default "vct"
+
+menu "vct board options"
+
+choice
+ prompt "Board variant"
+
+config VCT_PLATINUM
+ bool "Enable VCT_PLATINUM"
+
+config VCT_PLATINUMAVC
+ bool "Enable VCT_PLATINUMAVC"
+
+config VCT_PREMIUM
+ bool "Enable VCT_PLATINUMAVC"
+
+endchoice
+
+config VCT_ONENAND
+ bool "Enable VCT_ONENAND"
+
+config VCT_SMALL_IMAGE
+ bool "Enable VCT_SMALL_IMAGE"
+
+endmenu
+
+endif
diff --git a/board/micronas/vct/MAINTAINERS b/board/micronas/vct/MAINTAINERS
new file mode 100644
index 0000000..cbaa585
--- /dev/null
+++ b/board/micronas/vct/MAINTAINERS
@@ -0,0 +1,17 @@
+VCT BOARD
+#M: -
+S: Maintained
+F: board/micronas/vct/
+F: include/configs/vct.h
+F: configs/vct_platinum_defconfig
+F: configs/vct_platinum_onenand_defconfig
+F: configs/vct_platinum_onenand_small_defconfig
+F: configs/vct_platinum_small_defconfig
+F: configs/vct_platinumavc_defconfig
+F: configs/vct_platinumavc_onenand_defconfig
+F: configs/vct_platinumavc_onenand_small_defconfig
+F: configs/vct_platinumavc_small_defconfig
+F: configs/vct_premium_defconfig
+F: configs/vct_premium_onenand_defconfig
+F: configs/vct_premium_onenand_small_defconfig
+F: configs/vct_premium_small_defconfig
diff --git a/board/micronas/vct/Makefile b/board/micronas/vct/Makefile
new file mode 100644
index 0000000..ed28cb8
--- /dev/null
+++ b/board/micronas/vct/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := vct.o
+obj-y += ebi.o
+obj-$(CONFIG_VCT_NOR) += ebi_nor_flash.o
+obj-$(CONFIG_VCT_ONENAND) += ebi_onenand.o
+obj-$(CONFIG_DRIVER_SMC911X) += ebi_smc911x.o smc_eeprom.o
+obj-y += gpio.o
+obj-y += top.o
+obj-$(CONFIG_USB_EHCI_VCT) += dcgu.o ehci.o scc.o
diff --git a/board/micronas/vct/bcu.h b/board/micronas/vct/bcu.h
new file mode 100644
index 0000000..19ff978
--- /dev/null
+++ b/board/micronas/vct/bcu.h
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BCU_H
+#define _BCU_H
+
+enum bcu_tags {
+ BCU_VBV1 = 0,
+ BCU_VBV2 = 1,
+ BCU_BSS1 = 2,
+ BCU_BSS2 = 3,
+ BCU_TSD_TXT = 4,
+ BCU_TSD_SUBTITLES = 5,
+ BCU_TSD_PES_0 = 6,
+ BCU_TSD_PES_1 = 7,
+ BCU_TSD_PES_2 = 8,
+ BCU_TSD_PES_3 = 9,
+ BCU_TSIO_RECORD_0 = 10,
+ BCU_TSIO_RECORD_1 = 11,
+ BCU_TSIO_PLAYBACK_0 = 12,
+ BCU_TSIO_PLAYBACK_1 = 13,
+ BCU_SECURE_BUFFER = 14,
+ BCU_PCM1 = 15,
+ BCU_PCM2 = 16,
+ BCU_BSS_COPY = 17,
+ BCU_BSS_EXT1 = 18,
+ BCU_BSS_EXT2 = 19,
+ BCU_PCM_JINGLE = 20,
+ BCU_EBI_CPU_BUFFER = 21,
+ BCU_PCM_DELAY = 22,
+ BCU_FH_BUFFER_0 = 23,
+ BCU_FH_BUFFER_1 = 24,
+ BCU_TSD_SECTION_0 = 25,
+ BCU_TSD_SECTION_1 = 26,
+ BCU_TSD_SECTION_2 = 27,
+ BCU_TSD_SECTION_3 = 28,
+ BCU_TSD_SECTION_4 = 29,
+ BCU_TSD_SECTION_5 = 30,
+ BCU_TSD_SECTION_6 = 31,
+ BCU_TSD_SECTION_7 = 32,
+ BCU_TSD_SECTION_8 = 33,
+ BCU_TSD_SECTION_9 = 34,
+ BCU_TSD_SECTION_10 = 35,
+ BCU_TSD_SECTION_11 = 36,
+ BCU_TSD_SECTION_12 = 37,
+ BCU_TSD_SECTION_13 = 38,
+ BCU_TSD_SECTION_14 = 39,
+ BCU_TSD_SECTION_15 = 40,
+ BCU_TSD_SECTION_16 = 41,
+ BCU_TSD_SECTION_17 = 42,
+ BCU_TSD_SECTION_18 = 43,
+ BCU_TSD_SECTION_19 = 44,
+ BCU_TSD_SECTION_20 = 45,
+ BCU_TSD_SECTION_21 = 46,
+ BCU_TSD_SECTION_22 = 47,
+ BCU_TSD_SECTION_23 = 48,
+ BCU_TSD_SECTION_24 = 49,
+ BCU_TSD_SECTION_25 = 50,
+ BCU_TSD_SECTION_26 = 51,
+ BCU_TSD_SECTION_27 = 52,
+ BCU_TSD_SECTION_28 = 53,
+ BCU_TSD_SECTION_29 = 54,
+ BCU_TSD_SECTION_30 = 55,
+ BCU_TSD_SECTION_31 = 56,
+ BCU_TSD_SECTION_32 = 57,
+ BCU_TSD_SECTION_33 = 58,
+ BCU_TSD_SECTION_34 = 59,
+ BCU_TSD_SECTION_35 = 60,
+ BCU_TSD_SECTION_36 = 61,
+ BCU_TSD_SECTION_37 = 62,
+ BCU_TSD_SECTION_38 = 63,
+ BCU_TSD_SECTION_39 = 64,
+ BCU_TSD_SECTION_40 = 65,
+ BCU_TSD_SECTION_41 = 66,
+ BCU_TSD_SECTION_42 = 67,
+ BCU_TSD_SECTION_43 = 68,
+ BCU_TSD_SECTION_44 = 69,
+ BCU_TSD_SECTION_45 = 70,
+ BCU_TSD_SECTION_46 = 71,
+ BCU_TSD_SECTION_47 = 72,
+ BCU_TSD_SECTION_48 = 73,
+ BCU_TSD_SECTION_49 = 74,
+ BCU_TSD_SECTION_50 = 75,
+ BCU_TSD_SECTION_51 = 76,
+ BCU_TSD_SECTION_52 = 77,
+ BCU_TSD_SECTION_53 = 78,
+ BCU_TSIO_RECORD_2 = 79,
+ BCU_TSIO_RECORD_3 = 80,
+ BCU_TSIO_RECORD_4 = 81,
+ BCU_TSIO_RECORD_5 = 82,
+ BCU_TSIO_RECORD_6 = 83,
+ BCU_TSIO_RECORD_7 = 84,
+ BCU_TSIO_RECORD_8 = 85,
+ BCU_TSIO_RECORD_9 = 86,
+ BCU_PCM_DELAY_LINEAR = 87,
+ BCU_VD_MASTER_USER_DATA = 88,
+ BCU_VD_SLAVE_USER_DATA = 89,
+ BCU_VD_MASTER_REF0 = 90,
+ BCU_VD_MASTER_REF1 = 91,
+ BCU_VD_SLAVE_REF0 = 92,
+ BCU_VD_SLAVE_REF1 = 93,
+ BCU_VD_MASTER_DISP0_Y = 94,
+ BCU_VD_MASTER_DISP1_Y = 95,
+ BCU_VD_MASTER_DISP2_Y = 96,
+ BCU_VD_MASTER_DISP0_C = 97,
+ BCU_VD_MASTER_DISP1_C = 98,
+ BCU_VD_MASTER_DISP2_C = 99,
+ BCU_VD_SLAVE_DISP0_Y = 100,
+ BCU_VD_SLAVE_DISP1_Y = 101,
+ BCU_VD_SLAVE_DISP2_Y = 102,
+ BCU_VD_SLAVE_DISP0_C = 103,
+ BCU_VD_SLAVE_DISP1_C = 104,
+ BCU_VD_SLAVE_DISP2_C = 105,
+ BCU_CLUT_BUFFER_0 = 106,
+ BCU_CLUT_BUFFER_1 = 107,
+ BCU_OSD_FRAME_BUFFER_0 = 108,
+ BCU_OSD_FRAME_BUFFER_1 = 109,
+ BCU_GRAPHIC_FRAME_BUFFER0 = 110,
+ BCU_GRAPHIC_FRAME_BUFFER1 = 111,
+ BCU_DVP_VBI_REINSERTION = 112,
+ BCU_DVP_OSD_FRAME_BUFFER0 = 113,
+ BCU_DVP_OSD_FRAME_BUFFER1 = 114,
+ BCU_GAI_BUFFER = 115,
+ BCU_GA_SRC_BUFFER_0 = 116,
+ BCU_GA_SRC_BUFFER_1 = 117,
+ BCU_USB_BUFFER_0 = 118,
+ BCU_USB_BUFFER_1 = 119,
+ BCU_FE_3DCOMB_0 = 120,
+ BCU_FE_3DCOMB_1 = 121,
+ BCU_FE_3DCOMB_2 = 122,
+ BCU_FE_3DCOMB_3 = 123,
+ BCU_TNR_BUFFER_0 = 124,
+ BCU_TNR_BUFFER_1 = 125,
+ BCU_TNR_BUFFER_2 = 126,
+ BCU_MVAL_BUFFER = 127,
+ BCU_RC_BUFFER_0 = 128,
+ BCU_RC_BUFFER_1 = 129,
+ BCU_RC_BUFFER_2 = 130,
+ BCU_RC_BUFFER_3 = 131,
+ BCU_PIP_BUFFER_0 = 132,
+ BCU_PIP_BUFFER_1 = 133,
+ BCU_PIP_BUFFER_2 = 134,
+ BCU_PIP_BUFFER_3 = 135,
+ BCU_EWARP_BUFFER = 136,
+ BCU_OSD_BUFFER_0 = 137,
+ BCU_OSD_BUFFER_1 = 138,
+ BCU_GLOBAL_BUFFER_0 = 139,
+ BCU_GLOBAL_BUFFER_1 = 140,
+ BCU_MAX = 141
+};
+
+#endif /* _BCU_H */
diff --git a/board/micronas/vct/config.mk b/board/micronas/vct/config.mk
new file mode 100644
index 0000000..354d918
--- /dev/null
+++ b/board/micronas/vct/config.mk
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#
+# vct_xxx boards with MIPS 4Kc CPU core
+#
+
+ifndef CONFIG_SYS_TEXT_BASE
+CONFIG_SYS_TEXT_BASE = 0x87000000
+endif
diff --git a/board/micronas/vct/dcgu.c b/board/micronas/vct/dcgu.c
new file mode 100644
index 0000000..20ee3ac
--- /dev/null
+++ b/board/micronas/vct/dcgu.c
@@ -0,0 +1,245 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Original Author Guenter Gebhardt
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+
+#include "vct.h"
+
+int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
+{
+ u32 enable;
+ union dcgu_clk_en1 en1;
+ union dcgu_clk_en2 en2;
+
+ switch (setup) {
+ case DCGU_SWITCH_ON:
+ enable = 1;
+ break;
+ case DCGU_SWITCH_OFF:
+ enable = 0;
+ break;
+ default:
+ printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__,
+ setup);
+ return -EINVAL;
+ }
+
+ if (module == DCGU_HW_MODULE_CPU)
+ en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
+ else
+ en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
+
+ switch (module) {
+ case DCGU_HW_MODULE_MSMC:
+ en1.bits.en_clkmsmc = enable;
+ break;
+ case DCGU_HW_MODULE_SSI_S:
+ en1.bits.en_clkssi_s = enable;
+ break;
+ case DCGU_HW_MODULE_SSI_M:
+ en1.bits.en_clkssi_m = enable;
+ break;
+ case DCGU_HW_MODULE_SMC:
+ en1.bits.en_clksmc = enable;
+ break;
+ case DCGU_HW_MODULE_EBI:
+ en1.bits.en_clkebi = enable;
+ break;
+ case DCGU_HW_MODULE_USB_PLL:
+ en1.bits.en_usbpll = enable;
+ break;
+ case DCGU_HW_MODULE_USB_60:
+ en1.bits.en_clkusb60 = enable;
+ break;
+ case DCGU_HW_MODULE_USB_24:
+ en1.bits.en_clkusb24 = enable;
+ break;
+ case DCGU_HW_MODULE_UART_2:
+ en1.bits.en_clkuart2 = enable;
+ break;
+ case DCGU_HW_MODULE_UART_1:
+ en1.bits.en_clkuart1 = enable;
+ break;
+ case DCGU_HW_MODULE_PERI:
+ en1.bits.en_clkperi20 = enable;
+ break;
+ case DCGU_HW_MODULE_CPU:
+ en2.bits.en_clkcpu = enable;
+ break;
+ case DCGU_HW_MODULE_I2S:
+ en1.bits.en_clk_i2s_dly = enable;
+ break;
+ case DCGU_HW_MODULE_ABP_SCC:
+ en1.bits.en_clk_scc_abp = enable;
+ break;
+ case DCGU_HW_MODULE_SPDIF:
+ en1.bits.en_clk_dtv_spdo = enable;
+ break;
+ case DCGU_HW_MODULE_AD:
+ en1.bits.en_clkad = enable;
+ break;
+ case DCGU_HW_MODULE_MVD:
+ en1.bits.en_clkmvd = enable;
+ break;
+ case DCGU_HW_MODULE_TSD:
+ en1.bits.en_clktsd = enable;
+ break;
+ case DCGU_HW_MODULE_GA:
+ en1.bits.en_clkga = enable;
+ break;
+ case DCGU_HW_MODULE_DVP:
+ en1.bits.en_clkdvp = enable;
+ break;
+ case DCGU_HW_MODULE_MR2:
+ en1.bits.en_clkmr2 = enable;
+ break;
+ case DCGU_HW_MODULE_MR1:
+ en1.bits.en_clkmr1 = enable;
+ break;
+ default:
+ printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
+ __LINE__, module);
+ return -EINVAL;
+ }
+
+ /*
+ * The reg_read() following the reg_write() below forces the write to
+ * be really done on the bus.
+ * Otherwise the clock may not be switched on when this API function
+ * returns, which may cause an bus error if a registers of the hardware
+ * module connected to the clock is accessed.
+ */
+ if (module == DCGU_HW_MODULE_CPU) {
+ reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg);
+ en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
+ } else {
+ reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg);
+ en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
+ }
+
+ return 0;
+}
+
+int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
+{
+ union dcgu_reset_unit1 val;
+ u32 enable;
+
+ switch (setup) {
+ case DCGU_SWITCH_ON:
+ enable = 1;
+ break;
+ case DCGU_SWITCH_OFF:
+ enable = 0;
+ break;
+ default:
+ printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__,
+ setup);
+ return -EINVAL;
+ }
+
+ val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE));
+ switch (module) {
+ case DCGU_HW_MODULE_MSMC:
+ val.bits.swreset_clkmsmc = enable;
+ break;
+ case DCGU_HW_MODULE_SSI_S:
+ val.bits.swreset_clkssi_s = enable;
+ break;
+ case DCGU_HW_MODULE_SSI_M:
+ val.bits.swreset_clkssi_m = enable;
+ break;
+ case DCGU_HW_MODULE_SMC:
+ val.bits.swreset_clksmc = enable;
+ break;
+ case DCGU_HW_MODULE_EBI:
+ val.bits.swreset_clkebi = enable;
+ break;
+ case DCGU_HW_MODULE_USB_60:
+ val.bits.swreset_clkusb60 = enable;
+ break;
+ case DCGU_HW_MODULE_USB_24:
+ val.bits.swreset_clkusb24 = enable;
+ break;
+ case DCGU_HW_MODULE_UART_2:
+ val.bits.swreset_clkuart2 = enable;
+ break;
+ case DCGU_HW_MODULE_UART_1:
+ val.bits.swreset_clkuart1 = enable;
+ break;
+ case DCGU_HW_MODULE_PWM:
+ val.bits.swreset_pwm = enable;
+ break;
+ case DCGU_HW_MODULE_GPT:
+ val.bits.swreset_gpt = enable;
+ break;
+ case DCGU_HW_MODULE_I2C2:
+ val.bits.swreset_i2c2 = enable;
+ break;
+ case DCGU_HW_MODULE_I2C1:
+ val.bits.swreset_i2c1 = enable;
+ break;
+ case DCGU_HW_MODULE_GPIO2:
+ val.bits.swreset_gpio2 = enable;
+ break;
+ case DCGU_HW_MODULE_GPIO1:
+ val.bits.swreset_gpio1 = enable;
+ break;
+ case DCGU_HW_MODULE_CPU:
+ val.bits.swreset_clkcpu = enable;
+ break;
+ case DCGU_HW_MODULE_I2S:
+ val.bits.swreset_clk_i2s_dly = enable;
+ break;
+ case DCGU_HW_MODULE_ABP_SCC:
+ val.bits.swreset_clk_scc_abp = enable;
+ break;
+ case DCGU_HW_MODULE_SPDIF:
+ val.bits.swreset_clk_dtv_spdo = enable;
+ break;
+ case DCGU_HW_MODULE_AD:
+ val.bits.swreset_clkad = enable;
+ break;
+ case DCGU_HW_MODULE_MVD:
+ val.bits.swreset_clkmvd = enable;
+ break;
+ case DCGU_HW_MODULE_TSD:
+ val.bits.swreset_clktsd = enable;
+ break;
+ case DCGU_HW_MODULE_TSIO:
+ val.bits.swreset_clktsio = enable;
+ break;
+ case DCGU_HW_MODULE_GA:
+ val.bits.swreset_clkga = enable;
+ break;
+ case DCGU_HW_MODULE_MPC:
+ val.bits.swreset_clkmpc = enable;
+ break;
+ case DCGU_HW_MODULE_CVE:
+ val.bits.swreset_clkcve = enable;
+ break;
+ case DCGU_HW_MODULE_DVP:
+ val.bits.swreset_clkdvp = enable;
+ break;
+ case DCGU_HW_MODULE_MR2:
+ val.bits.swreset_clkmr2 = enable;
+ break;
+ case DCGU_HW_MODULE_MR1:
+ val.bits.swreset_clkmr1 = enable;
+ break;
+ default:
+ printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
+ __LINE__, module);
+ return -EINVAL;
+ }
+ reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg);
+
+ return 0;
+}
diff --git a/board/micronas/vct/dcgu.h b/board/micronas/vct/dcgu.h
new file mode 100644
index 0000000..36fba33
--- /dev/null
+++ b/board/micronas/vct/dcgu.h
@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DCGU_H
+#define _DCGU_H
+
+enum dcgu_switch {
+ DCGU_SWITCH_OFF, /* Switch off */
+ DCGU_SWITCH_ON /* Switch on */
+};
+
+enum dcgu_hw_module {
+ DCGU_HW_MODULE_DCGU, /* Selects digital clock gen. unit */
+
+ DCGU_HW_MODULE_MIC32_SCI, /* Selects MIC32 SoC interface */
+ DCGU_HW_MODULE_SCI, /* Selects SCI target agent port modules*/
+
+ DCGU_HW_MODULE_MR1, /* Selects first MPEG reader module */
+ DCGU_HW_MODULE_MR2, /* Selects second MPEG reader module */
+ DCGU_HW_MODULE_MVD, /* Selects MPEG video decoder module */
+ DCGU_HW_MODULE_DVP, /* Selects dig video processing module */
+ DCGU_HW_MODULE_CVE, /* Selects color video encoder module */
+ DCGU_HW_MODULE_VID_ENC, /* Selects video encoder module */
+
+ DCGU_HW_MODULE_SSI_S, /* Selects slave sync serial interface */
+ DCGU_HW_MODULE_SSI_M, /* Selects master sync serial interface */
+
+ DCGU_HW_MODULE_GA, /* Selects graphics accelerator module */
+ DCGU_HW_MODULE_DGPU, /* Selects digital graphics processing */
+
+ DCGU_HW_MODULE_UART_1, /* Selects first UART module */
+ DCGU_HW_MODULE_UART_2, /* Selects second UART module */
+
+ DCGU_HW_MODULE_AD, /* Selects audio decoder module */
+ DCGU_HW_MODULE_ABP_DTV, /* Selects audio baseband processing */
+ DCGU_HW_MODULE_ABP_SCC, /* Selects audio base band processor SCC*/
+ DCGU_HW_MODULE_SPDIF, /* Selects sony philips digital interf. */
+
+ DCGU_HW_MODULE_TSIO, /* Selects trasnport stream input/output*/
+ DCGU_HW_MODULE_TSD, /* Selects trasnport stream decoder */
+ DCGU_HW_MODULE_TSD_KEY, /* Selects trasnport stream decoder key */
+
+ DCGU_HW_MODULE_USBH, /* Selects USB hub module */
+ DCGU_HW_MODULE_USB_PLL, /* Selects USB phase locked loop module */
+ DCGU_HW_MODULE_USB_60, /* Selects USB 60 module */
+ DCGU_HW_MODULE_USB_24, /* Selects USB 24 module */
+
+ DCGU_HW_MODULE_PERI, /* Selects all mod connected to clkperi20*/
+ DCGU_HW_MODULE_WDT, /* Selects wtg timer mod con to clkperi20*/
+ DCGU_HW_MODULE_I2C1, /* Selects first I2C mod con to clkperi20*/
+ DCGU_HW_MODULE_I2C2, /* Selects 2nd I2C mod con to clkperi20 */
+ DCGU_HW_MODULE_GPIO1, /* Selects gpio module 1 */
+ DCGU_HW_MODULE_GPIO2, /* Selects gpio module 2 */
+
+ DCGU_HW_MODULE_GPT, /* Selects gpt mod connected to clkperi20*/
+ DCGU_HW_MODULE_PWM, /* Selects pwm mod connected to clkperi20*/
+
+ DCGU_HW_MODULE_MPC, /* Selects multi purpose cipher module */
+ DCGU_HW_MODULE_MPC_KEY, /* Selects multi purpose cipher key */
+
+ DCGU_HW_MODULE_COM, /* Selects COM unit module */
+ DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module */
+ DCGU_HW_MODULE_FWSRAM, /* Selects firmware SRAM module */
+
+ DCGU_HW_MODULE_EBI, /* Selects external bus interface module*/
+ DCGU_HW_MODULE_I2S, /* Selects integrated interchip sound */
+ DCGU_HW_MODULE_MSMC, /* Selects memory stick and mmc module */
+ DCGU_HW_MODULE_SMC, /* Selects smartcard interface module */
+
+ DCGU_HW_MODULE_IRQC, /* Selects interrupt C module */
+ DCGU_HW_MODULE_TOP, /* Selects top level pinmux module */
+ DCGU_HW_MODULE_SRAM, /* Selects SRAM module */
+ DCGU_HW_MODULE_EIC, /* Selects External Interrupt controller*/
+ DCGU_HW_MODULE_CPU, /* Selects CPU subsystem module */
+ DCGU_HW_MODULE_SCC, /* Selects SCC module */
+ DCGU_HW_MODULE_MM, /* Selects Memory Manager module */
+ DCGU_HW_MODULE_BCU, /* Selects Buffer Configuration Unit */
+ DCGU_HW_MODULE_FH, /* Selects FIFO Handler module */
+ DCGU_HW_MODULE_IMU, /* Selects Interrupt Management Unit */
+ DCGU_HW_MODULE_MDU, /* Selects MCI Debug Unit module */
+ DCGU_HW_MODULE_SI2OCP /* Selects Standard Interface to OCP bridge*/
+};
+
+union dcgu_clk_en1 {
+ u32 reg;
+ struct {
+ u32 res1:8; /* reserved */
+ u32 en_clkmsmc:1; /* Enable bit for clkmsmc (#) */
+ u32 en_clkssi_s:1; /* Enable bit for clkssi_s (#) */
+ u32 en_clkssi_m:1; /* Enable bit for clkssi_m (#) */
+ u32 en_clksmc:1; /* Enable bit for clksmc (#) */
+ u32 en_clkebi:1; /* Enable bit for clkebi (#) */
+ u32 en_usbpll:1; /* Enable bit for the USB PLL */
+ u32 en_clkusb60:1; /* Enable bit for clkusb60 (#) */
+ u32 en_clkusb24:1; /* Enable bit for clkusb24 (#) */
+ u32 en_clkuart2:1; /* Enable bit for clkuart2 (#) */
+ u32 en_clkuart1:1; /* Enable bit for clkuart1 (#) */
+ u32 en_clkperi20:1; /* Enable bit for clkperi20 (#) */
+ u32 res2:3; /* reserved */
+ u32 en_clk_i2s_dly:1; /* Enable bit for clk_scc_abp */
+ u32 en_clk_scc_abp:1; /* Enable bit for clk_scc_abp */
+ u32 en_clk_dtv_spdo:1; /* Enable bit for clk_dtv_spdo */
+ u32 en_clkad:1; /* Enable bit for clkad (#) */
+ u32 en_clkmvd:1; /* Enable bit for clkmvd (#) */
+ u32 en_clktsd:1; /* Enable bit for clktsd (#) */
+ u32 en_clkga:1; /* Enable bit for clkga (#) */
+ u32 en_clkdvp:1; /* Enable bit for clkdvp (#) */
+ u32 en_clkmr2:1; /* Enable bit for clkmr2 (#) */
+ u32 en_clkmr1:1; /* Enable bit for clkmr1 (#) */
+ } bits;
+};
+
+union dcgu_clk_en2 {
+ u32 reg;
+ struct {
+ u32 res1:31; /* reserved */
+ u32 en_clkcpu:1; /* Enable bit for clkcpu */
+ } bits;
+};
+
+union dcgu_reset_unit1 {
+ u32 reg;
+ struct {
+ u32 res1:1;
+ u32 swreset_clkmsmc:1;
+ u32 swreset_clkssi_s:1;
+ u32 swreset_clkssi_m:1;
+ u32 swreset_clksmc:1;
+ u32 swreset_clkebi:1;
+ u32 swreset_clkusb60:1;
+ u32 swreset_clkusb24:1;
+ u32 swreset_clkuart2:1;
+ u32 swreset_clkuart1:1;
+ u32 swreset_pwm:1;
+ u32 swreset_gpt:1;
+ u32 swreset_i2c2:1;
+ u32 swreset_i2c1:1;
+ u32 swreset_gpio2:1;
+ u32 swreset_gpio1:1;
+ u32 swreset_clkcpu:1;
+ u32 res2:2;
+ u32 swreset_clk_i2s_dly:1;
+ u32 swreset_clk_scc_abp:1;
+ u32 swreset_clk_dtv_spdo:1;
+ u32 swreset_clkad:1;
+ u32 swreset_clkmvd:1;
+ u32 swreset_clktsd:1;
+ u32 swreset_clktsio:1;
+ u32 swreset_clkga:1;
+ u32 swreset_clkmpc:1;
+ u32 swreset_clkcve:1;
+ u32 swreset_clkdvp:1;
+ u32 swreset_clkmr2:1;
+ u32 swreset_clkmr1:1;
+ } bits;
+};
+
+int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
+int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup);
+
+#endif /* _DCGU_H */
diff --git a/board/micronas/vct/ebi.c b/board/micronas/vct/ebi.c
new file mode 100644
index 0000000..8a2c2dc
--- /dev/null
+++ b/board/micronas/vct/ebi.c
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+int ebi_initialize(void)
+{
+#if defined(CONFIG_VCT_NOR)
+ if (ebi_init_nor_flash())
+ return -1;
+#endif
+
+#if defined(CONFIG_VCT_ONENAND)
+ if (ebi_init_onenand())
+ return -1;
+#endif
+
+#if defined(CONFIG_DRIVER_SMC911X)
+ if (ebi_init_smc911x())
+ return -1;
+#endif
+
+ reg_write(EBI_CTRL_SIG_ACTLV(EBI_BASE), 0x00004100);
+
+ ebi_wait();
+
+ return 0;
+}
diff --git a/board/micronas/vct/ebi.h b/board/micronas/vct/ebi.h
new file mode 100644
index 0000000..efa36cf
--- /dev/null
+++ b/board/micronas/vct/ebi.h
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EBI__
+#define __EBI__
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+#define EXT_DEVICE_CHANNEL_3 (0x30000000)
+#define EXT_DEVICE_CHANNEL_2 (0x20000000)
+#define EXT_DEVICE_CHANNEL_1 (0x10000000)
+#define EXT_CPU_ACCESS_ACTIVE (0x00000001)
+#define EXT_DMA_ACCESS_ACTIVE (1 << 14)
+#define EXT_CPU_IORDY_SL (0x00000001)
+
+#define EBI_CPU_WRITE (1 << 31)
+#define EBI_CPU_ID_SHIFT (28)
+#define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT)
+
+/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */
+#define ADDR_LATCH_ENABLE 0
+#define ADDR_ACTIVATION 4
+#define CHIP_SELECT_START 8
+#define OUTPUT_ENABLE_START 12
+#define WAIT_TIME 28
+#define READ_DURATION 20
+
+/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */
+#define OUTPUT_ENABLE_END 0
+#define CHIP_SELECT_END 4
+#define ADDR_DEACTIVATION 8
+#define RECOVER_TIME 12
+#define ACK_TIME 20
+
+/* various bits in configuration register EBI_DEV[01]_CONFIG1 */
+#define EBI_EXTERNAL_DATA_8 (1 << 8)
+#define EBI_EXT_ADDR_SHIFT (1 << 22)
+#define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT
+#define EBI_CHIP_SELECT_1 0x2
+#define EBI_CHIP_SELECT_2 0x4
+#define EBI_BUSY_EN_RD (1 << 12)
+#define DIR_ACCESS_WRITE (1 << 20)
+#define DIR_ACCESS_MASK (1 << 20)
+
+/* various bits in configuration register EBI_DEV[01]_CONFIG2 */
+#define ADDRESS_INCREMENT_ON 0x0
+#define ADDRESS_INCREMENT_OFF 0x100
+#define QUEUE_LENGTH_1 0x40
+#define QUEUE_LENGTH_2 0x80
+#define QUEUE_LENGTH_3 0xC0
+#define QUEUE_LENGTH_4 0
+#define CPU_TRANSFER_SIZE_32 0
+#define CPU_TRANSFER_SIZE_16 0x10
+#define CPU_TRANSFER_SIZE_8 0x20
+#define READ_ENDIANNESS_ABCD 0
+#define READ_ENDIANNESS_DCBA 0x4
+#define READ_ENDIANNESS_BADC 0x8
+#define READ_ENDIANNESS_CDAB 0xC
+#define WRITE_ENDIANNESS_ABCD 0
+#define WRITE_ENDIANNESS_DCBA 0x1
+#define WRITE_ENDIANNESS_BADC 0x2
+#define WRITE_ENDIANNESS_CDAB 0x3
+
+/* various bits in configuration register EBI_CTRL_SIG_ACTLV */
+#define IORDY_ACTIVELEVEL_HIGH (1 << 14)
+#define ALE_ACTIVELEVEL_HIGH (1 << 8)
+
+/* bits in register EBI_SIG_LEVEL */
+#define IORDY_LEVEL_MASK 1
+
+static inline void ebi_wait(void)
+{
+ while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE)
+ ; /* wait */
+}
+
+#endif
diff --git a/board/micronas/vct/ebi_nor_flash.c b/board/micronas/vct/ebi_nor_flash.c
new file mode 100644
index 0000000..80fbc84
--- /dev/null
+++ b/board/micronas/vct/ebi_nor_flash.c
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+static u32 ebi_read(u32 addr)
+{
+ addr &= ~0xFC000000;
+
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE), EXT_DEVICE_CHANNEL_2 | addr);
+ ebi_wait();
+
+ return reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
+}
+
+static int ebi_write_u16(u32 addr, u32 data, int fetchIO)
+{
+ u32 val = (data << 16);
+
+ addr &= ~0xFC000000;
+
+ ebi_wait();
+
+ reg_write(EBI_IO_ACCS_DATA(EBI_BASE), val);
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+ EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | addr);
+ ebi_wait();
+
+ if (fetchIO) {
+ u32 counter = 0;
+ while (!(reg_read(EBI_SIG_LEVEL(EBI_BASE)) & EXT_CPU_IORDY_SL)) {
+ if (counter++ > 0xFFFFFF)
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+static u16 ebi_read_u16(u32 addr)
+{
+ return ((ebi_read(addr) >> 16) & 0xFFFF);
+}
+
+static u8 ebi_read_u8(u32 addr)
+{
+ u32 val = ebi_read(addr) >> 16;
+
+ if (addr & 0x1)
+ return val & 0xff;
+ else
+ return (val >> 8) & 0xff;
+}
+
+/*
+ * EBI initialization for NOR FLASH access
+ */
+int ebi_init_nor_flash(void)
+{
+ reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000);
+
+ reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x400002);
+ reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50);
+
+ reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x409113);
+ reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0xFF01000);
+ reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x04003113);
+ reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC12011);
+ reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000);
+
+ return 0;
+}
+
+/*
+ * Accessor functions replacing the "weak" functions in
+ * drivers/mtd/cfi_flash.c
+ */
+void flash_write8(u8 value, void *addr)
+{
+ ebi_write_u16((u32)addr, value, 0);
+}
+
+void flash_write16(u16 value, void *addr)
+{
+ ebi_write_u16((u32)addr, value, 0);
+}
+
+u8 flash_read8(void *addr)
+{
+ return ebi_read_u8((u32)addr);
+}
+
+u16 flash_read16(void *addr)
+{
+ return ebi_read_u16((u32)addr);
+}
+
+u32 flash_read32(void *addr)
+{
+ return ((u32)ebi_read_u16((u32)addr) << 16) |
+ ebi_read_u16((u32)addr + 2);
+}
+
+void *board_flash_read_memcpy(void *dest, const void *src, size_t count)
+{
+ u16 *tmp = (u16 *)dest, *s = (u16 *)src;
+ int i;
+
+ for (i = 0; i < count; i += 2)
+ *tmp++ = flash_read16(s++);
+
+ return dest;
+}
diff --git a/board/micronas/vct/ebi_onenand.c b/board/micronas/vct/ebi_onenand.c
new file mode 100644
index 0000000..62eb648
--- /dev/null
+++ b/board/micronas/vct/ebi_onenand.c
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include "vct.h"
+
+#define BURST_SIZE_WORDS 4
+
+static u16 ebi_nand_read_word(void __iomem *addr)
+{
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr));
+ ebi_wait();
+
+ return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)) >> 16;
+}
+
+static void ebi_nand_write_word(u16 data, void __iomem * addr)
+{
+ ebi_wait();
+ reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16));
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+ EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | (u32)addr);
+ ebi_wait();
+}
+
+/*
+ * EBI initialization for OneNAND FLASH access
+ */
+int ebi_init_onenand(void)
+{
+ reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000);
+
+ reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002);
+ reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50);
+
+ reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002);
+ reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */
+
+ reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000);
+ reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000);
+ reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x12002223);
+ reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC02220);
+ reg_write(EBI_DEV3_TIM1_RD1(EBI_BASE), 0x00504000);
+ reg_write(EBI_DEV3_TIM1_RD2(EBI_BASE), 0x00001000);
+ reg_write(EBI_DEV3_TIM1_WR1(EBI_BASE), 0x05001000);
+ reg_write(EBI_DEV3_TIM1_WR2(EBI_BASE), 0x00010200);
+
+ reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000);
+ reg_write(EBI_DEV2_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
+
+ reg_write(EBI_DEV3_TIM_EXT(EBI_BASE), 0xFFF00000);
+ reg_write(EBI_DEV3_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
+
+ /* prepare DMA configuration for EBI */
+ reg_write(EBI_DEV3_FIFO_CONFIG(EBI_BASE), 0x0101ff00);
+
+ /* READ only no byte order change, TAG 1 used */
+ reg_write(EBI_DEV3_DMA_CONFIG2(EBI_BASE), 0x00000004);
+
+ reg_write(EBI_TAG1_SYS_ID(EBI_BASE), 0x0); /* SCC DMA channel 0 */
+ reg_write(EBI_TAG2_SYS_ID(EBI_BASE), 0x1);
+ reg_write(EBI_TAG3_SYS_ID(EBI_BASE), 0x2);
+ reg_write(EBI_TAG4_SYS_ID(EBI_BASE), 0x3);
+
+ return 0;
+}
+
+static void *memcpy_16_from_onenand(void *dst, const void *src, unsigned int len)
+{
+ void *ret = dst;
+ u16 *d = dst;
+ u16 *s = (u16 *)src;
+
+ len >>= 1;
+ while (len-- > 0)
+ *d++ = ebi_nand_read_word(s++);
+
+ return ret;
+}
+
+static void *memcpy_32_from_onenand(void *dst, const void *src, unsigned int len)
+{
+ void *ret = dst;
+ u32 *d = (u32 *)dst;
+ u32 s = (u32)src;
+ u32 bytes_per_block = BURST_SIZE_WORDS * sizeof(int);
+ u32 n_blocks = len / bytes_per_block;
+ u32 block = 0;
+ u32 burst_word;
+
+ for (block = 0; block < n_blocks; block++) {
+ /* Trigger read channel 3 */
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+ (EXT_DEVICE_CHANNEL_3 | (s + (block * bytes_per_block))));
+ /* Poll status to see whether read has finished */
+ ebi_wait();
+
+ /* Squirrel the data away in a safe place */
+ for (burst_word = 0; burst_word < BURST_SIZE_WORDS; burst_word++)
+ *d++ = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
+ }
+
+ return ret;
+}
+
+static void *memcpy_16_to_onenand(void *dst, const void *src, unsigned int len)
+{
+ void *ret = dst;
+ u16 *d = dst;
+ u16 *s = (u16 *)src;
+
+ len >>= 1;
+ while (len-- > 0)
+ ebi_nand_write_word(*s++, d++);
+
+ return ret;
+}
+
+static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
+{
+ struct onenand_chip *this = mtd->priv;
+
+ if (ONENAND_CURRENT_BUFFERRAM(this)) {
+ if (area == ONENAND_DATARAM)
+ return mtd->writesize;
+ if (area == ONENAND_SPARERAM)
+ return mtd->oobsize;
+ }
+
+ return 0;
+}
+
+static int ebi_read_bufferram(struct mtd_info *mtd, loff_t addr, int area,
+ unsigned char *buffer, int offset,
+ size_t count)
+{
+ struct onenand_chip *this = mtd->priv;
+ void __iomem *bufferram;
+
+ bufferram = this->base + area;
+ bufferram += onenand_bufferram_offset(mtd, area);
+
+ if (count < 4)
+ memcpy_16_from_onenand(buffer, bufferram + offset, count);
+ else
+ memcpy_32_from_onenand(buffer, bufferram + offset, count);
+
+ return 0;
+}
+
+static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area,
+ const unsigned char *buffer, int offset,
+ size_t count)
+{
+ struct onenand_chip *this = mtd->priv;
+ void __iomem *bufferram;
+
+ bufferram = this->base + area;
+ bufferram += onenand_bufferram_offset(mtd, area);
+
+ memcpy_16_to_onenand(bufferram + offset, buffer, count);
+
+ return 0;
+}
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+ struct onenand_chip *chip = mtd->priv;
+
+ /*
+ * Insert board specific OneNAND access functions
+ */
+ chip->read_word = ebi_nand_read_word;
+ chip->write_word = ebi_nand_write_word;
+
+ chip->read_bufferram = ebi_read_bufferram;
+ chip->write_bufferram = ebi_write_bufferram;
+}
diff --git a/board/micronas/vct/ebi_smc911x.c b/board/micronas/vct/ebi_smc911x.c
new file mode 100644
index 0000000..2628f99
--- /dev/null
+++ b/board/micronas/vct/ebi_smc911x.c
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include "vct.h"
+
+/*
+ * EBI initialization for SMC911x access
+ */
+int ebi_init_smc911x(void)
+{
+ reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x00003020);
+ reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
+
+ reg_write(EBI_DEV1_TIM1_RD1(EBI_BASE), 0x00501100);
+ reg_write(EBI_DEV1_TIM1_RD2(EBI_BASE), 0x0FF02111);
+
+ reg_write(EBI_DEV1_TIM_EXT(EBI_BASE), 0xFFF00000);
+ reg_write(EBI_DEV1_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
+
+ reg_write(EBI_DEV1_TIM1_WR1(EBI_BASE), 0x05001100);
+ reg_write(EBI_DEV1_TIM1_WR2(EBI_BASE), 0x3FC21110);
+
+ return 0;
+}
+
+/*
+ * Accessor functions replacing the "weak" functions in
+ * drivers/net/smc911x.c
+ */
+u32 smc911x_reg_read(struct eth_device *dev, u32 addr)
+{
+ volatile u32 data;
+
+ addr += dev->iobase;
+ reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
+ ebi_wait();
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr));
+ ebi_wait();
+ data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
+
+ return (data);
+}
+
+void smc911x_reg_write(struct eth_device *dev, u32 addr, u32 data)
+{
+ addr += dev->iobase;
+ reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F);
+ ebi_wait();
+ reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data);
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+ EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr);
+ ebi_wait();
+}
+
+void pkt_data_push(struct eth_device *dev, u32 addr, u32 data)
+{
+ addr += dev->iobase;
+ reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A);
+ ebi_wait();
+ reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data);
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
+ EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr);
+ ebi_wait();
+
+ return;
+}
+
+u32 pkt_data_pull(struct eth_device *dev, u32 addr)
+{
+ volatile u32 data;
+
+ addr += dev->iobase;
+ reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A);
+ ebi_wait();
+ reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr));
+ ebi_wait();
+ data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
+
+ return data;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_DRIVER_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/micronas/vct/ehci.c b/board/micronas/vct/ehci.c
new file mode 100644
index 0000000..2362669
--- /dev/null
+++ b/board/micronas/vct/ehci.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Original Author Guenter Gebhardt
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include "vct.h"
+
+int vct_ehci_hcd_init(u32 *hccr, u32 *hcor)
+{
+ int retval;
+ u32 val;
+ u32 addr;
+
+ dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
+ dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
+ dcgu_set_clk_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON);
+ dcgu_set_clk_switch(DCGU_HW_MODULE_USB_PLL, DCGU_SWITCH_ON);
+ dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_OFF);
+
+ /* Wait until (DCGU_USBPHY_STAT == 7) */
+ addr = DCGU_USBPHY_STAT(DCGU_BASE);
+ val = reg_read(addr);
+ while (val != 7)
+ val = reg_read(addr);
+
+ dcgu_set_clk_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON);
+ dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_OFF);
+
+ retval = scc_reset(SCC_USB_RW, 0);
+ if (retval) {
+ printf("scc_reset(SCC_USB_RW, 0) returned: 0x%x\n", retval);
+ return retval;
+ } else {
+ retval = scc_reset(SCC_CPU1_SPDMA_RW, 0);
+ if (retval) {
+ printf("scc_reset(SCC_CPU1_SPDMA_RW, 0) returned: 0x%x\n",
+ retval);
+ return retval;
+ }
+ }
+
+ if (!retval) {
+ /*
+ * For the AGU bypass, where the SCC client provides full
+ * physical address
+ */
+ scc_set_usb_address_generation_mode(1);
+ scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
+ USE_NO_FH, DMA_READ, 0);
+ scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_1, DMA_LINEAR,
+ USE_NO_FH, DMA_WRITE, 0);
+ scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
+ USE_NO_FH, DMA_WRITE, 0);
+ scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_0, DMA_LINEAR,
+ USE_NO_FH, DMA_READ, 0);
+
+ /* Enable memory interface */
+ scc_enable(SCC_USB_RW, 1);
+
+ /* Start (start_cmd=0) DMAs */
+ scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_READ);
+ scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_WRITE);
+ } else {
+ printf("Cannot configure USB memory channel.\n");
+ printf("USB can not access RAM. SCC configuration failed.\n");
+ return retval;
+ }
+
+ /* Wait a short while */
+ udelay(300000);
+
+ reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
+
+ /* Set EHCI structures and DATA in RAM */
+ reg_write(USBH_USBHMISC(USBH_BASE), 0x00840003);
+ /* Set USBMODE to bigendian and set host mode */
+ reg_write(USBH_USBMODE(USBH_BASE), 0x00000007);
+
+ /*
+ * USBH_BURSTSIZE MUST EQUAL 0x00001c1c in order for
+ * 512 byte USB transfers on the bulk pipe to work properly.
+ * Set USBH_BURSTSIZE to 0x00001c1c
+ */
+ reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c);
+
+ /* Insert access register addresses */
+ *hccr = REG_GLOBAL_START_ADDR + USBH_CAPLENGTH(USBH_BASE);
+ *hcor = REG_GLOBAL_START_ADDR + USBH_USBCMD(USBH_BASE);
+
+ return 0;
+}
diff --git a/board/micronas/vct/gpio.c b/board/micronas/vct/gpio.c
new file mode 100644
index 0000000..1eaa89f
--- /dev/null
+++ b/board/micronas/vct/gpio.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+/*
+ * Find out to which of the 2 gpio modules the pin specified in the
+ * argument belongs:
+ * GPIO_MODULE yields 0 for pins 0 to 31,
+ * 1 for pins 32 to 63
+ */
+#define GPIO_MODULE(pin) ((pin) >> 5)
+
+/*
+ * Bit position within a 32-bit peripheral register (where every
+ * bit is one bitslice)
+ */
+#define MASK(pin) (1 << ((pin) & 0x1F))
+#define BASE_ADDR(mod) module_base[mod]
+
+/*
+ * Lookup table for transforming gpio module number 0 to 2 to
+ * address offsets
+ */
+static u32 module_base[] = {
+ GPIO1_BASE,
+ GPIO2_BASE
+};
+
+static void clrsetbits(u32 addr, u32 and_mask, u32 or_mask)
+{
+ reg_write(addr, (reg_read(addr) & ~and_mask) | or_mask);
+}
+
+int vct_gpio_dir(int pin, int dir)
+{
+ u32 gpio_base;
+
+ gpio_base = BASE_ADDR(GPIO_MODULE(pin));
+
+ if (dir == 0)
+ clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0);
+ else
+ clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin));
+
+ return 0;
+}
+
+void vct_gpio_set(int pin, int val)
+{
+ u32 gpio_base;
+
+ gpio_base = BASE_ADDR(GPIO_MODULE(pin));
+
+ if (val == 0)
+ clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0);
+ else
+ clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin));
+}
+
+int vct_gpio_get(int pin)
+{
+ u32 gpio_base;
+ u32 value;
+
+ gpio_base = BASE_ADDR(GPIO_MODULE(pin));
+ value = reg_read(GPIO_EXT_PORTA(gpio_base));
+
+ return ((value & MASK(pin)) ? 1 : 0);
+}
diff --git a/board/micronas/vct/scc.c b/board/micronas/vct/scc.c
new file mode 100644
index 0000000..40f8ecd
--- /dev/null
+++ b/board/micronas/vct/scc.c
@@ -0,0 +1,656 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+
+#include "vct.h"
+
+/*
+ * List of statically defined buffers per SCC.
+ * The first entry in the table is the number of fixed buffers
+ * followed by the list of buffer IDs
+ */
+static u32 buffer_list_0[] = { 6, 120, 121, 122, 123, 139, 140 };
+static u32 buffer_list_1[] = { 6, 120, 121, 122, 123, 139, 140 };
+static u32 buffer_list_2[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_3[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_4[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_5[] = { 3, 127, 139, 140 };
+static u32 buffer_list_6[] = { 3, 127, 139, 140 };
+static u32 buffer_list_7[] = { 6, 128, 129, 130, 131, 139, 140 };
+static u32 buffer_list_8[] = { 6, 128, 129, 130, 131, 139, 140 };
+static u32 buffer_list_9[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_10[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_11[] = { 5, 124, 125, 126, 139, 140 };
+static u32 buffer_list_12[] = { 6, 132, 133, 134, 135, 139, 140 };
+static u32 buffer_list_13[] = { 6, 132, 133, 134, 135, 139, 140 };
+static u32 buffer_list_14[] = { 4, 137, 138, 139, 140 };
+static u32 buffer_list_15[] = { 6, 136, 136, 137, 138, 139, 140 };
+
+/** Issue#7674 (new) - DP/DVP buffer assignment */
+static u32 buffer_list_16[] = { 6, 106, 108, 109, 107, 139, 140 };
+static u32 buffer_list_17[] = { 6, 106, 110, 107, 111, 139, 140 };
+static u32 buffer_list_18[] = { 6, 106, 113, 107, 114, 139, 140 };
+static u32 buffer_list_19[] = { 3, 112, 139, 140 };
+static u32 buffer_list_20[] = { 35, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 79, 80, 81, 82, 83, 84, 85, 86, 139, 140 };
+static u32 buffer_list_21[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 139, 140 };
+static u32 buffer_list_22[] = { 81, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
+ 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60,
+ 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72,
+ 73, 74, 75, 76, 77, 78, 139, 140 };
+static u32 buffer_list_23[] = { 29, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 88, 89, 139, 140 };
+static u32 buffer_list_24[] = { 6, 90, 91, 92, 93, 139, 140 };
+static u32 buffer_list_25[] = { 18, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,
+ 100, 101, 102, 103, 104, 105, 139, 140 };
+static u32 buffer_list_26[] = { 5, 94, 95, 96, 139, 140 };
+static u32 buffer_list_27[] = { 5, 97, 98, 99, 139, 140 };
+static u32 buffer_list_28[] = { 5, 100, 101, 102, 139, 140 };
+static u32 buffer_list_29[] = { 5, 103, 104, 105, 139, 140 };
+static u32 buffer_list_30[] = { 10, 108, 109, 110, 111, 113, 114, 116, 117,
+ 139, 140 };
+static u32 buffer_list_31[] = { 13, 106, 107, 108, 109, 110, 111, 113, 114,
+ 115, 116, 117, 139, 140 };
+static u32 buffer_list_32[] = { 13, 106, 107, 108, 109, 110, 111, 113, 114,
+ 115, 116, 117, 139, 140 };
+static u32 buffer_list_33[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 139, 140 };
+static u32 buffer_list_34[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 139, 140 };
+static u32 buffer_list_35[] = { 28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 87, 139, 140 };
+static u32 buffer_list_36[] = { 28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 87, 139, 140 };
+static u32 buffer_list_37[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 139, 140 };
+static u32 buffer_list_38[] = { 29, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 118, 119, 139, 140 };
+static u32 buffer_list_39[] = { 91, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
+ 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
+ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60,
+ 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72,
+ 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84,
+ 85, 86, 118, 119, 139, 140 };
+static u32 buffer_list_40[] = { 0 };
+
+/*
+ * List of statically defined vcid.csize values.
+ * The first entry in the table is the number of possible csize values
+ * followed by the list of data path values in bits.
+ */
+static u32 csize_list_0[] = { 2, 0, 1 };
+static u32 csize_list_1[] = { 2, 0, 1 };
+static u32 csize_list_2[] = { 1, 1 };
+static u32 csize_list_3[] = { 1, 1 };
+static u32 csize_list_4[] = { 1, 1 };
+static u32 csize_list_5[] = { 1, 0 };
+static u32 csize_list_6[] = { 1, 0 };
+static u32 csize_list_7[] = { 1, 1 };
+static u32 csize_list_8[] = { 1, 1 };
+static u32 csize_list_9[] = { 1, 1 };
+static u32 csize_list_10[] = { 1, 1 };
+static u32 csize_list_11[] = { 1, 1 };
+static u32 csize_list_12[] = { 1, 1 };
+static u32 csize_list_13[] = { 1, 1 };
+static u32 csize_list_14[] = { 1, 2 };
+static u32 csize_list_15[] = { 1, 4 };
+static u32 csize_list_16[] = { 3, 0, 1, 2 };
+static u32 csize_list_17[] = { 3, 0, 1, 2 };
+static u32 csize_list_18[] = { 3, 0, 1, 2 };
+static u32 csize_list_19[] = { 1, 2 };
+static u32 csize_list_20[] = { 1, 0 };
+static u32 csize_list_21[] = { 1, 0 };
+static u32 csize_list_22[] = { 1, 2 };
+static u32 csize_list_23[] = { 1, 3 };
+static u32 csize_list_24[] = { 1, 3 };
+static u32 csize_list_25[] = { 1, 3 };
+static u32 csize_list_26[] = { 1, 0 };
+static u32 csize_list_27[] = { 1, 0 };
+static u32 csize_list_28[] = { 1, 0 };
+static u32 csize_list_29[] = { 1, 0 };
+static u32 csize_list_30[] = { 1, 2 };
+static u32 csize_list_31[] = { 1, 2 };
+static u32 csize_list_32[] = { 1, 2 };
+static u32 csize_list_33[] = { 1, 2 };
+static u32 csize_list_34[] = { 1, 2 };
+static u32 csize_list_35[] = { 1, 2 };
+static u32 csize_list_36[] = { 1, 2 };
+static u32 csize_list_37[] = { 2, 0, 1 };
+static u32 csize_list_38[] = { 1, 2 };
+static u32 csize_list_39[] = { 1, 3 };
+static u32 csize_list_40[] = { 1, 3 };
+
+/*
+ * SCC_Configuration table
+ */
+static const struct scc_descriptor scc_descriptor_table[] = {
+/* scn scc_name profile SCC scc_id mci_id rd wr m p fh si cfg sta */
+ {"fe_", "fe_3dcomb_wr", STRM_P, SCC0_BASE, 0, 0, 0, 4, 1, 1, 0, 0, 0, 1,
+ buffer_list_0, csize_list_0},
+ {"fe_", "fe_3dcomb_rd", STRM_P, SCC1_BASE, 1, 18, 4, 0, 1, 1, 0, 1, 0,
+ 1, buffer_list_1, csize_list_1},
+ {"di_", "di_tnr_wr", STRM_P, SCC2_BASE, 2, 1, 0, 3, 1, 1, 0, 2, 0, 1,
+ buffer_list_2, csize_list_2},
+ {"di_", "di_tnr_field_rd", STRM_P, SCC3_BASE, 3, 19, 3, 0, 1, 1, 0, 3,
+ 0, 1, buffer_list_3, csize_list_3},
+ {"di_", "di_tnr_frame_rd", STRM_P, SCC4_BASE, 4, 20, 3, 0, 1, 1, 0, 4,
+ 0, 1, buffer_list_4, csize_list_4},
+ {"di_", "di_mval_wr", STRM_P, SCC5_BASE, 5, 2, 0, 1, 1, 1, 0, 5, 0, 1,
+ buffer_list_5, csize_list_5},
+ {"di_", "di_mval_rd", STRM_P, SCC6_BASE, 6, 21, 1, 0, 1, 1, 0, 6, 0, 1,
+ buffer_list_6, csize_list_6},
+ {"rc_", "rc_frame_wr", STRM_P, SCC7_BASE, 7, 3, 0, 4, 1, 1, 0, 7, 0, 1,
+ buffer_list_7, csize_list_7},
+ {"rc_", "rc_frame0_rd", STRM_P, SCC8_BASE, 8, 22, 4, 0, 1, 1, 0, 8, 0,
+ 1, buffer_list_8, csize_list_8},
+ {"opt", "opt_field0_rd", STRM_P, SCC9_BASE, 9, 23, 3, 0, 1, 1, 0, 9, 0,
+ 1, buffer_list_9, csize_list_9},
+ {"opt", "opt_field1_rd", STRM_P, SCC10_BASE, 10, 24, 3, 0, 1, 1, 0, 10,
+ 0, 1, buffer_list_10, csize_list_10},
+ {"opt", "opt_field2_rd", STRM_P, SCC11_BASE, 11, 25, 3, 0, 1, 1, 0, 11,
+ 0, 1, buffer_list_11, csize_list_11},
+ {"pip", "pip_frame_wr", STRM_P, SCC12_BASE, 12, 4, 0, 4, 1, 1, 0, 12, 0,
+ 1, buffer_list_12, csize_list_12},
+ {"pip", "pip_frame_rd", STRM_P, SCC13_BASE, 13, 26, 4, 0, 1, 1, 0, 13,
+ 0, 1, buffer_list_13, csize_list_13},
+ {"dp_", "dp_agpu_rd", STRM_P, SCC14_BASE, 14, 27, 2, 0, 2, 1, 0, 14, 0,
+ 1, buffer_list_14, csize_list_14},
+ {"ewa", "ewarp_rw", SRMD, SCC15_BASE, 15, 11, 1, 1, 0, 0, 0, -1, 0, 0,
+ buffer_list_15, csize_list_15},
+ {"dp_", "dp_osd_rd", STRM_P, SCC16_BASE, 16, 28, 3, 0, 2, 1, 0, 15, 0,
+ 1, buffer_list_16, csize_list_16},
+ {"dp_", "dp_graphic_rd", STRM_P, SCC17_BASE, 17, 29, 3, 0, 2, 1, 0, 16,
+ 0, 1, buffer_list_17, csize_list_17},
+ {"dvp", "dvp_osd_rd", STRM_P, SCC18_BASE, 18, 30, 2, 0, 2, 1, 0, 17, 0,
+ 1, buffer_list_18, csize_list_18},
+ {"dvp", "dvp_vbi_rd", STRM_D, SCC19_BASE, 19, 31, 1, 0, 0, 1, 0, -1, 0,
+ 0, buffer_list_19, csize_list_19},
+ {"tsi", "tsio_wr", STRM_P, SCC20_BASE, 20, 5, 0, 8, 2, 1, 1, -1, 0, 0,
+ buffer_list_20, csize_list_20},
+ {"tsi", "tsio_rd", STRM_P, SCC21_BASE, 21, 32, 4, 0, 2, 1, 1, -1, 0, 0,
+ buffer_list_21, csize_list_21},
+ {"tsd", "tsd_wr", SRMD, SCC22_BASE, 22, 6, 0, 64, 0, 0, 1, -1, 0, 0,
+ buffer_list_22, csize_list_22},
+ {"vd_", "vd_ud_st_rw", SRMD, SCC23_BASE, 23, 12, 2, 2, 0, 0, 1, -1, 0,
+ 0, buffer_list_23, csize_list_23},
+ {"vd_", "vd_frr_rd", SRMD, SCC24_BASE, 24, 33, 4, 0, 0, 0, 0, -1, 0, 0,
+ buffer_list_24, csize_list_24},
+ {"vd_", "vd_frw_disp_wr", SRMD, SCC25_BASE, 25, 7, 0, 16, 0, 0, 0, -1,
+ 0, 0, buffer_list_25, csize_list_25},
+ {"mr_", "mr_vd_m_y_rd", STRM_P, SCC26_BASE, 26, 34, 3, 0, 2, 1, 0, 18,
+ 0, 1, buffer_list_26, csize_list_26},
+ {"mr_", "mr_vd_m_c_rd", STRM_P, SCC27_BASE, 27, 35, 3, 0, 2, 1, 0, 19,
+ 0, 1, buffer_list_27, csize_list_27},
+ {"mr_", "mr_vd_s_y_rd", STRM_P, SCC28_BASE, 28, 36, 3, 0, 2, 1, 0, 20,
+ 0, 1, buffer_list_28, csize_list_28},
+ {"mr_", "mr_vd_s_c_rd", STRM_P, SCC29_BASE, 29, 37, 3, 0, 2, 1, 0, 21,
+ 0, 1, buffer_list_29, csize_list_29},
+ {"ga_", "ga_wr", STRM_P, SCC30_BASE, 30, 8, 0, 1, 1, 1, 0, -1, 1, 1,
+ buffer_list_30, csize_list_30},
+ {"ga_", "ga_src1_rd", STRM_P, SCC31_BASE, 31, 38, 1, 0, 1, 1, 0, -1, 1,
+ 1, buffer_list_31, csize_list_31},
+ {"ga_", "ga_src2_rd", STRM_P, SCC32_BASE, 32, 39, 1, 0, 1, 1, 0, -1, 1,
+ 1, buffer_list_32, csize_list_32},
+ {"ad_", "ad_rd", STRM_D, SCC33_BASE, 33, 40, 2, 0, 0, 1, 1, -1, 0, 0,
+ buffer_list_33, csize_list_33},
+ {"ad_", "ad_wr", STRM_D, SCC34_BASE, 34, 9, 0, 3, 0, 1, 1, -1, 0, 0,
+ buffer_list_34, csize_list_34},
+ {"abp", "abp_rd", STRM_D, SCC35_BASE, 35, 41, 5, 0, 0, 1, 1, -1, 0, 0,
+ buffer_list_35, csize_list_35},
+ {"abp", "abp_wr", STRM_D, SCC36_BASE, 36, 10, 0, 3, 0, 1, 1, -1, 0, 0,
+ buffer_list_36, csize_list_36},
+ {"ebi", "ebi_rw", STRM_P, SCC37_BASE, 37, 13, 4, 4, 2, 1, 1, -1, 0, 0,
+ buffer_list_37, csize_list_37},
+ {"usb", "usb_rw", SRMD, SCC38_BASE, 38, 14, 1, 1, 0, 0, 1, -1, 0, 0,
+ buffer_list_38, csize_list_38},
+ {"cpu", "cpu1_spdma_rw", SRMD, SCC39_BASE, 39, 15, 1, 1, 0, 0, 1, -1, 0,
+ 0, buffer_list_39, csize_list_39},
+ {"cpu", "cpu1_bridge_rw", SRMD, SCC40_BASE, 40, 16, 0, 0, 0, 0, 0, -1,
+ 0, 0, buffer_list_40, csize_list_40},
+};
+
+/* DMA state structures for read and write channels for each SCC */
+
+static struct scc_dma_state scc_state_rd_0[] = { {-1} };
+static struct scc_dma_state scc_state_wr_0[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_1[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_1[] = { {-1} };
+static struct scc_dma_state scc_state_rd_2[] = { {-1} };
+static struct scc_dma_state scc_state_wr_2[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_3[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_3[] = { {-1} };
+static struct scc_dma_state scc_state_rd_4[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_4[] = { {-1} };
+static struct scc_dma_state scc_state_rd_5[] = { {-1} };
+static struct scc_dma_state scc_state_wr_5[] = { {0} };
+static struct scc_dma_state scc_state_rd_6[] = { {0} };
+static struct scc_dma_state scc_state_wr_6[] = { {-1} };
+static struct scc_dma_state scc_state_rd_7[] = { {-1} };
+static struct scc_dma_state scc_state_wr_7[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_8[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_8[] = { {-1} };
+static struct scc_dma_state scc_state_rd_9[] = { {0}, {0}, {0}, };
+static struct scc_dma_state scc_state_wr_9[] = { {-1} };
+static struct scc_dma_state scc_state_rd_10[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_10[] = { {-1} };
+static struct scc_dma_state scc_state_rd_11[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_11[] = { {-1} };
+static struct scc_dma_state scc_state_rd_12[] = { {-1} };
+static struct scc_dma_state scc_state_wr_12[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_13[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_13[] = { {-1} };
+static struct scc_dma_state scc_state_rd_14[] = { {0}, {0} };
+static struct scc_dma_state scc_state_wr_14[] = { {-1} };
+static struct scc_dma_state scc_state_rd_15[] = { {0} };
+static struct scc_dma_state scc_state_wr_15[] = { {0} };
+static struct scc_dma_state scc_state_rd_16[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_16[] = { {-1} };
+static struct scc_dma_state scc_state_rd_17[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_17[] = { {-1} };
+static struct scc_dma_state scc_state_rd_18[] = { {0}, {0} };
+static struct scc_dma_state scc_state_wr_18[] = { {-1} };
+static struct scc_dma_state scc_state_rd_19[] = { {0} };
+static struct scc_dma_state scc_state_wr_19[] = { {-1} };
+static struct scc_dma_state scc_state_rd_20[] = { {-1} };
+static struct scc_dma_state scc_state_wr_20[] = {
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_21[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_21[] = { {-1} };
+static struct scc_dma_state scc_state_rd_22[] = { {-1} };
+static struct scc_dma_state scc_state_wr_22[] = {
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_23[] = { {0}, {0} };
+static struct scc_dma_state scc_state_wr_23[] = { {0}, {0} };
+static struct scc_dma_state scc_state_rd_24[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_24[] = { {-1} };
+static struct scc_dma_state scc_state_rd_25[] = { {-1} };
+static struct scc_dma_state scc_state_wr_25[] = {
+ {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0},
+ {0}, {0} };
+static struct scc_dma_state scc_state_rd_26[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_26[] = { {-1} };
+static struct scc_dma_state scc_state_rd_27[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_27[] = { {-1} };
+static struct scc_dma_state scc_state_rd_28[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_28[] = { {-1} };
+static struct scc_dma_state scc_state_rd_29[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_29[] = { {-1} };
+static struct scc_dma_state scc_state_rd_30[] = { {-1} };
+static struct scc_dma_state scc_state_wr_30[] = { {0} };
+static struct scc_dma_state scc_state_rd_31[] = { {0} };
+static struct scc_dma_state scc_state_wr_31[] = { {-1} };
+static struct scc_dma_state scc_state_rd_32[] = { {0} };
+static struct scc_dma_state scc_state_wr_32[] = { {-1} };
+static struct scc_dma_state scc_state_rd_33[] = { {0}, {0} };
+static struct scc_dma_state scc_state_wr_33[] = { {-1} };
+static struct scc_dma_state scc_state_rd_34[] = { {-1} };
+static struct scc_dma_state scc_state_wr_34[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_35[] = { {0}, {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_35[] = { {-1} };
+static struct scc_dma_state scc_state_rd_36[] = { {-1} };
+static struct scc_dma_state scc_state_wr_36[] = { {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_37[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_wr_37[] = { {0}, {0}, {0}, {0} };
+static struct scc_dma_state scc_state_rd_38[] = { {0} };
+static struct scc_dma_state scc_state_wr_38[] = { {0} };
+static struct scc_dma_state scc_state_rd_39[] = { {0} };
+static struct scc_dma_state scc_state_wr_39[] = { {0} };
+static struct scc_dma_state scc_state_rd_40[] = { {-1} };
+static struct scc_dma_state scc_state_wr_40[] = { {-1} };
+
+/* DMA state references to access from the driver */
+static struct scc_dma_state *scc_state_rd[] = {
+ scc_state_rd_0,
+ scc_state_rd_1,
+ scc_state_rd_2,
+ scc_state_rd_3,
+ scc_state_rd_4,
+ scc_state_rd_5,
+ scc_state_rd_6,
+ scc_state_rd_7,
+ scc_state_rd_8,
+ scc_state_rd_9,
+ scc_state_rd_10,
+ scc_state_rd_11,
+ scc_state_rd_12,
+ scc_state_rd_13,
+ scc_state_rd_14,
+ scc_state_rd_15,
+ scc_state_rd_16,
+ scc_state_rd_17,
+ scc_state_rd_18,
+ scc_state_rd_19,
+ scc_state_rd_20,
+ scc_state_rd_21,
+ scc_state_rd_22,
+ scc_state_rd_23,
+ scc_state_rd_24,
+ scc_state_rd_25,
+ scc_state_rd_26,
+ scc_state_rd_27,
+ scc_state_rd_28,
+ scc_state_rd_29,
+ scc_state_rd_30,
+ scc_state_rd_31,
+ scc_state_rd_32,
+ scc_state_rd_33,
+ scc_state_rd_34,
+ scc_state_rd_35,
+ scc_state_rd_36,
+ scc_state_rd_37,
+ scc_state_rd_38,
+ scc_state_rd_39,
+ scc_state_rd_40,
+};
+
+static struct scc_dma_state *scc_state_wr[] = {
+ scc_state_wr_0,
+ scc_state_wr_1,
+ scc_state_wr_2,
+ scc_state_wr_3,
+ scc_state_wr_4,
+ scc_state_wr_5,
+ scc_state_wr_6,
+ scc_state_wr_7,
+ scc_state_wr_8,
+ scc_state_wr_9,
+ scc_state_wr_10,
+ scc_state_wr_11,
+ scc_state_wr_12,
+ scc_state_wr_13,
+ scc_state_wr_14,
+ scc_state_wr_15,
+ scc_state_wr_16,
+ scc_state_wr_17,
+ scc_state_wr_18,
+ scc_state_wr_19,
+ scc_state_wr_20,
+ scc_state_wr_21,
+ scc_state_wr_22,
+ scc_state_wr_23,
+ scc_state_wr_24,
+ scc_state_wr_25,
+ scc_state_wr_26,
+ scc_state_wr_27,
+ scc_state_wr_28,
+ scc_state_wr_29,
+ scc_state_wr_30,
+ scc_state_wr_31,
+ scc_state_wr_32,
+ scc_state_wr_33,
+ scc_state_wr_34,
+ scc_state_wr_35,
+ scc_state_wr_36,
+ scc_state_wr_37,
+ scc_state_wr_38,
+ scc_state_wr_39,
+ scc_state_wr_40,
+};
+
+static u32 scc_takeover_mode = SCC_TO_IMMEDIATE;
+
+/* Change mode of the SPDMA for given direction */
+static u32 scc_agu_mode_sp = AGU_BYPASS;
+
+/* Change mode of the USB for given direction */
+static u32 scc_agu_mode_usb = AGU_BYPASS;
+
+static union scc_softwareconfiguration scc_software_configuration[SCC_MAX];
+
+static u32 dma_fsm[4][4] = {
+ /* DMA_CMD_RESET DMA_CMD_SETUP DMA_CMD_START DMA_CMD_STOP */
+ /* DMA_STATE_RESET */
+ {DMA_STATE_RESET, DMA_STATE_SETUP, DMA_STATE_ERROR, DMA_STATE_ERROR},
+ /* DMA_STATE_SETUP */
+ {DMA_STATE_RESET, DMA_STATE_SETUP, DMA_STATE_START, DMA_STATE_SETUP},
+ /* DMA_STATE_START */
+ {DMA_STATE_RESET, DMA_STATE_ERROR, DMA_STATE_START, DMA_STATE_SETUP},
+ /* DMA_STATE_ERROR */
+ {DMA_STATE_RESET, DMA_STATE_ERROR, DMA_STATE_ERROR, DMA_STATE_ERROR},
+};
+
+static void dma_state_process(struct scc_dma_state *dma_state, u32 cmd)
+{
+ dma_state->dma_status = dma_fsm[dma_state->dma_status][cmd];
+ dma_state->dma_cmd = cmd;
+}
+
+static void dma_state_process_dma_command(struct scc_dma_state *dma_state,
+ u32 dma_cmd)
+{
+ dma_state->dma_cmd = dma_cmd;
+ switch (dma_cmd) {
+ case DMA_START:
+ case DMA_START_FH_RESET:
+ dma_state_process(dma_state, DMA_CMD_START);
+ break;
+ case DMA_STOP:
+ dma_state_process(dma_state, DMA_CMD_STOP);
+ break;
+ default:
+ break;
+ }
+}
+
+static void scc_takeover_dma(enum scc_id id, u32 dma_id, u32 drs)
+{
+ union scc_cmd dma_cmd;
+
+ dma_cmd.reg = 0;
+
+ /* Prepare the takeover for the DMA channel */
+ dma_cmd.bits.action = DMA_TAKEOVER;
+ dma_cmd.bits.id = dma_id;
+ dma_cmd.bits.rid = TO_DMA_CFG; /* this is DMA_CFG register takeover */
+ if (drs == DMA_WRITE)
+ dma_cmd.bits.drs = DMA_WRITE;
+
+ reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg);
+}
+
+int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs)
+{
+ union scc_cmd dma_cmd;
+ struct scc_dma_state *dma_state;
+
+ if ((id >= SCC_MAX) || (id < 0))
+ return -EINVAL;
+
+ dma_cmd.reg = 0;
+
+ /* Prepare the takeover for the DMA channel */
+ dma_cmd.bits.action = cmd;
+ dma_cmd.bits.id = dma_id;
+ if (drs == DMA_WRITE) {
+ dma_cmd.bits.drs = DMA_WRITE;
+ dma_state = &scc_state_wr[id][dma_id];
+ } else {
+ dma_state = &scc_state_rd[id][dma_id];
+ }
+
+ dma_state->scc_id = id;
+ dma_state->dma_id = dma_id;
+ dma_state_process_dma_command(dma_state, cmd);
+
+ reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg);
+
+ return 0;
+}
+
+int scc_set_usb_address_generation_mode(u32 agu_mode)
+{
+ if (AGU_ACTIVE == agu_mode) {
+ /* Ensure both DMAs are stopped */
+ scc_dma_cmd(SCC_USB_RW, DMA_STOP, 0, DMA_WRITE);
+ scc_dma_cmd(SCC_USB_RW, DMA_STOP, 0, DMA_READ);
+ } else {
+ agu_mode = AGU_BYPASS;
+ }
+
+ scc_agu_mode_usb = agu_mode;
+
+ return 0;
+}
+
+int scc_setup_dma(enum scc_id id, u32 buffer_tag,
+ u32 type, u32 fh_mode, u32 drs, u32 dma_id)
+{
+ struct scc_dma_state *dma_state;
+ int return_value = 0;
+ union scc_dma_cfg dma_cfg;
+ u32 *buffer_tag_list = scc_descriptor_table[id].buffer_tag_list;
+ u32 tag_count, t, t_valid;
+
+ if ((id >= SCC_MAX) || (id < 0))
+ return -EINVAL;
+
+ /* if the register is only configured by hw, cannot write! */
+ if (1 == scc_descriptor_table[id].hw_dma_cfg)
+ return -EACCES;
+
+ if (DMA_WRITE == drs) {
+ if (dma_id >= scc_descriptor_table[id].p_dma_channels_wr)
+ return -EINVAL;
+ dma_state = &scc_state_wr[id][dma_id];
+ } else {
+ if (dma_id >= scc_descriptor_table[id].p_dma_channels_rd)
+ return -EINVAL;
+ dma_state = &scc_state_rd[id][dma_id];
+ }
+
+ /* Compose the DMA configuration register */
+ tag_count = buffer_tag_list[0];
+ t_valid = 0;
+ for (t = 1; t <= tag_count; t++) {
+ if (buffer_tag == buffer_tag_list[t]) {
+ /* Tag found - validate */
+ t_valid = 1;
+ break;
+ }
+ }
+
+ if (!t_valid)
+ return -EACCES;
+
+ /*
+ * Read the register first -- two functions write into the register
+ * it does not make sense to read the DMA config back, because there
+ * are two register configuration sets (drs)
+ */
+ dma_cfg.reg = 0;
+ dma_cfg.bits.buffer_id = buffer_tag;
+ dma_state_process(dma_state, DMA_CMD_SETUP);
+
+ /*
+ * This is Packet CFG set select - usable for TSIO, EBI and those SCCs
+ * which habe 2 packet configs
+ */
+ dma_cfg.bits.packet_cfg_id =
+ scc_software_configuration[id].bits.packet_select;
+
+ if (type == DMA_CYCLIC)
+ dma_cfg.bits.buffer_type = 1;
+ else
+ dma_cfg.bits.buffer_type = 0;
+
+ if (fh_mode == USE_FH)
+ dma_cfg.bits.fh_mode = 1;
+ else
+ dma_cfg.bits.fh_mode = 0;
+
+ if (id == SCC_CPU1_SPDMA_RW)
+ dma_cfg.bits.agu_mode = scc_agu_mode_sp;
+
+ if (id == SCC_USB_RW)
+ dma_cfg.bits.agu_mode = scc_agu_mode_usb;
+
+ reg_write(SCC_DMA_CFG(scc_descriptor_table[id].base_address),
+ dma_cfg.reg);
+
+ /* The DMA_CFG needs a takeover! */
+ if (SCC_TO_IMMEDIATE == scc_takeover_mode)
+ scc_takeover_dma(id, dma_id, drs);
+
+ /* if (buffer_tag is not used) */
+ dma_state->buffer_tag = buffer_tag;
+
+ dma_state->scc_id = id;
+ dma_state->dma_id = dma_id;
+
+ return return_value;
+}
+
+int scc_enable(enum scc_id id, u32 value)
+{
+ if ((id >= SCC_MAX) || (id < 0))
+ return -EINVAL;
+
+ if (value == 0) {
+ scc_software_configuration[id].bits.enable_status = 0;
+ } else {
+ value = 1;
+ scc_software_configuration[id].bits.enable_status = 1;
+ }
+ reg_write(SCC_ENABLE(scc_descriptor_table[id].base_address), value);
+
+ return 0;
+}
+
+static inline void ehb(void)
+{
+ __asm__ __volatile__(
+ " .set mips32r2 \n"
+ " ehb \n"
+ " .set mips0 \n");
+}
+
+int scc_reset(enum scc_id id, u32 value)
+{
+ if ((id >= SCC_MAX) || (id < 0))
+ return -EINVAL;
+
+ /* Invert value to the strait logic from the negative hardware logic */
+ if (value == 0)
+ value = 1;
+ else
+ value = 0;
+
+ /* Write the value to the register */
+ reg_write(SCC_RESET(scc_descriptor_table[id].base_address), value);
+
+ /* sync flush */
+ asm("sync"); /* request bus write queue flush */
+ ehb(); /* wait until previous bus commit instr has finished */
+ asm("nop"); /* wait for flush to occur */
+ asm("nop"); /* wait for flush to occur */
+
+ udelay(100);
+
+ return 0;
+}
diff --git a/board/micronas/vct/scc.h b/board/micronas/vct/scc.h
new file mode 100644
index 0000000..7cadc92
--- /dev/null
+++ b/board/micronas/vct/scc.h
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SCC_H
+#define _SCC_H
+
+#define DMA_READ 0 /* SCC read DMA */
+#define DMA_WRITE 1 /* SCC write DMA */
+
+#define DMA_LINEAR 0 /* DMA linear buffer access method */
+#define DMA_CYCLIC 1 /* DMA cyclic buffer access method */
+
+#define DMA_START 0 /* DMA command - start DMA */
+#define DMA_STOP 1 /* DMA command - stop DMA */
+#define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */
+#define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */
+
+#define AGU_ACTIVE 0 /* enable AGU address calculation */
+#define AGU_BYPASS 1 /* set AGU to bypass mode */
+
+#define USE_NO_FH 0 /* order the DMA to not use FH */
+#define USE_FH 1 /* order the DMA to work with FH*/
+
+#define SCC_DBG_IDLE 0 /* DEBUG status (idle interfaces) */
+#define SCC_DBG_SYNC_RES 0x0001 /* synchronuous reset */
+
+#define SCC_TO_IMMEDIATE 1 /* takeover command issued immediately*/
+#define TO_DMA_CFG 2 /* takeover command for the DMA config*/
+
+#define DMA_CMD_RESET 0
+#define DMA_CMD_SETUP 1
+#define DMA_CMD_START 2
+#define DMA_CMD_STOP 3
+
+#define DMA_STATE_RESET 0
+#define DMA_STATE_SETUP 1
+#define DMA_STATE_START 2
+#define DMA_STATE_ERROR 3
+
+#define SRMD 0
+#define STRM_D 1
+#define STRM_P 2
+
+/*
+ * Slowest Monterey domain is DVP 27 MHz (324/27 = 12; 12*16 = 192 CPU clocks)
+ */
+#define RESET_TIME 2 /* cycle calc see in SCC_Reset */
+
+struct scc_descriptor {
+ char *pu_name; /* PU identifier */
+ char *scc_instance; /* SCC Name */
+ u32 profile; /* SCC VCI_D profile */
+
+ u32 base_address; /* base address of the SCC unit reg shell*/
+
+ /* SCS Interconnect configuration */
+ u32 p_scc_id; /* instance number of SCC unit */
+ u32 p_mci_id; /* memory channel ID */
+
+ /* DMA Registers configuration */
+ u32 p_dma_channels_rd; /* Number of Read DMA channels */
+ u32 p_dma_channels_wr; /* Number of Write DMA channels */
+
+ u32 p_dma_packet_desc; /* Number of packet descriptors */
+ u32 p_dma_mci_desc; /* Number of MCI_CFG Descriptors */
+
+ int use_fh; /* the flag tells if SCC uses an FH */
+
+ int p_si2ocp_id; /* instance number of SI2OCP unit */
+ int hw_dma_cfg; /* HW or SW DMA config flag */
+ int hw_dma_start; /* HW or SW DMA start/stop flag */
+
+ u32 *buffer_tag_list; /* list of the buffer tags available */
+ u32 *csize_list; /* list of the valid CSIZE values */
+};
+
+struct scc_dma_state {
+ u32 scc_id:8; /* SCC id */
+ u32 dma_id:8; /* DMA id, used for match with array idx*/
+ u32 buffer_tag:8; /* mem buf tag, assigned to this DMA */
+ u32 dma_status:2; /* state of DMA, of the DMA_STATE_ const*/
+ u32 dma_drs:2; /* DMA dir, either DMA_READ or DMA_WRITE*/
+ u32 dma_cmd:4; /* last executed command on this DMA */
+};
+
+union scc_cmd {
+ u32 reg;
+ struct {
+ u32 res1:19; /* reserved */
+ u32 drs:1; /* DMA Register Set */
+ u32 rid:2; /* Register Identifier */
+ u32 id:6; /* DMA Identifier */
+ u32 action:4; /* DMA Command encoding */
+ } bits;
+};
+
+union scc_dma_cfg {
+ u32 reg;
+ struct {
+ u32 res1:17; /* reserved */
+ u32 agu_mode:1; /* AGU Mode */
+ u32 res2:1; /* reserved */
+ u32 fh_mode:1; /* Fifo Handler */
+ u32 buffer_type:1; /* Defines type of mem buffers */
+ u32 mci_cfg_id:1; /* MCI_CFG register selector */
+ u32 packet_cfg_id:1; /* PACKET_CFG register selector */
+ u32 buffer_id:8; /* DMA Buffer Identifier */
+ } bits;
+};
+
+union scc_debug {
+ u32 reg;
+ struct {
+ u32 res1:20; /* reserved */
+ u32 arg:8; /* SCC Debug Command Argument (#) */
+ u32 cmd:4; /* SCC Debug Command Register */
+ } bits;
+};
+
+union scc_softwareconfiguration {
+ u32 reg;
+ struct {
+ u32 res1:28; /* reserved */
+ u32 clock_status:1; /* clock on/off */
+ u32 packet_select:1; /* active SCC packet id */
+ u32 enable_status:1; /* enabled [1/0] */
+ u32 active_status:1; /* 1=active 0=reset */
+ } bits;
+};
+
+/*
+ * System on Chip Channel ID
+ */
+enum scc_id {
+ SCC_NULL = -1, /* illegal SCC identifier */
+ SCC_FE_3DCOMB_WR, /* SCC_FE_3DCOMB Write channel */
+ SCC_FE_3DCOMB_RD, /* SCC_FE_3DCOMB Read channel */
+ SCC_DI_TNR_WR, /* SCC_DI_TNR Write channel */
+ SCC_DI_TNR_FIELD_RD, /* SCC_DI_TNR_FIELD Read channel */
+ SCC_DI_TNR_FRAME_RD, /* SCC_DI_TNR_FRAME Read channel */
+ SCC_DI_MVAL_WR, /* SCC_DI_MVAL Write channel */
+ SCC_DI_MVAL_RD, /* SCC_DI_MVAL Read channel */
+ SCC_RC_FRAME_WR, /* SCC_RC_FRAME Write channel */
+ SCC_RC_FRAME0_RD, /* SCC_RC_FRAME0 Read channel */
+ SCC_OPT_FIELD0_RD, /* SCC_OPT_FIELD0 Read channel */
+ SCC_OPT_FIELD1_RD, /* SCC_OPT_FIELD1 Read channel */
+ SCC_OPT_FIELD2_RD, /* SCC_OPT_FIELD2 Read channel */
+ SCC_PIP_FRAME_WR, /* SCC_PIP_FRAME Write channel */
+ SCC_PIP_FRAME_RD, /* SCC_PIP_FRAME Read channel */
+ SCC_DP_AGPU_RD, /* SCC_DP_AGPU Read channel */
+ SCC_EWARP_RW, /* SCC_EWARP Read/Write channel */
+ SCC_DP_OSD_RD, /* SCC_DP_OSD Read channel */
+ SCC_DP_GRAPHIC_RD, /* SCC_DP_GRAPHIC Read channel */
+ SCC_DVP_OSD_RD, /* SCC_DVP_OSD Read channel */
+ SCC_DVP_VBI_RD, /* SCC_DVP_VBI Read channel */
+ SCC_TSIO_WR, /* SCC_TSIO Write channel */
+ SCC_TSIO_RD, /* SCC_TSIO Read channel */
+ SCC_TSD_WR, /* SCC_TSD Write channel */
+ SCC_VD_UD_ST_RW, /* SCC_VD_UD_ST Read/Write channel */
+ SCC_VD_FRR_RD, /* SCC_VD_FRR Read channel */
+ SCC_VD_FRW_DISP_WR, /* SCC_VD_FRW_DISP Write channel */
+ SCC_MR_VD_M_Y_RD, /* SCC_MR_VD_M_Y Read channel */
+ SCC_MR_VD_M_C_RD, /* SCC_MR_VD_M_C Read channel */
+ SCC_MR_VD_S_Y_RD, /* SCC_MR_VD_S_Y Read channel */
+ SCC_MR_VD_S_C_RD, /* SCC_MR_VD_S_C Read channel */
+ SCC_GA_WR, /* SCC_GA Write channel */
+ SCC_GA_SRC1_RD, /* SCC_GA_SRC1 Read channel */
+ SCC_GA_SRC2_RD, /* SCC_GA_SRC2 Read channel */
+ SCC_AD_RD, /* SCC_AD Read channel */
+ SCC_AD_WR, /* SCC_AD Write channel */
+ SCC_ABP_RD, /* SCC_ABP Read channel */
+ SCC_ABP_WR, /* SCC_ABP Write channel */
+ SCC_EBI_RW, /* SCC_EBI Read/Write channel */
+ SCC_USB_RW, /* SCC_USB Read/Write channel */
+ SCC_CPU1_SPDMA_RW, /* SCC_CPU1_SPDMA Read/Write channel */
+ SCC_CPU1_BRIDGE_RW, /* SCC_CPU1_BRIDGE Read/Write channel */
+ SCC_MAX /* maximum limit on the SCC id */
+};
+
+int scc_set_usb_address_generation_mode(u32 agu_mode);
+int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs);
+int scc_setup_dma(enum scc_id id, u32 buffer_tag,
+ u32 type, u32 fh_mode, u32 drs, u32 dma_id);
+int scc_enable(enum scc_id id, u32 value);
+int scc_reset(enum scc_id id, u32 value);
+
+#endif /* _SCC_H */
diff --git a/board/micronas/vct/smc_eeprom.c b/board/micronas/vct/smc_eeprom.c
new file mode 100644
index 0000000..b5a5521
--- /dev/null
+++ b/board/micronas/vct/smc_eeprom.c
@@ -0,0 +1,394 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright 2005, Seagate Technology LLC
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#undef DEBUG
+
+#include <common.h>
+#include <command.h>
+#include <config.h>
+#include <net.h>
+
+#include "vct.h"
+
+#define SMSC9118_BASE CONFIG_DRIVER_SMC911X_BASE
+#define BYTE_TEST (SMSC9118_BASE + 0x64)
+#define GPIO_CFG (SMSC9118_BASE + 0x88)
+#define MAC_CSR_CMD (SMSC9118_BASE + 0xA4)
+#define MAC_CSR_CMD_CSR_BUSY (0x80000000)
+#define MAC_CSR_CMD_RNW (0x40000000)
+#define MAC_RD_CMD(reg) ((reg & 0x000000FF) | \
+ (MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_RNW))
+#define MAC_WR_CMD(reg) ((reg & 0x000000FF) | \
+ (MAC_CSR_CMD_CSR_BUSY))
+#define MAC_CSR_DATA (SMSC9118_BASE + 0xA8)
+#define E2P_CMD (SMSC9118_BASE + 0xB0)
+#define E2P_CMD_EPC_BUSY_ (0x80000000UL) /* Self Clearing */
+#define E2P_CMD_EPC_CMD_ (0x70000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_READ_ (0x00000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000UL) /* R/W */
+#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000UL) /* R/W */
+#define E2P_CMD_EPC_TIMEOUT_ (0x00000200UL) /* R */
+#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100UL) /* RO */
+#define E2P_CMD_EPC_ADDR_ (0x000000FFUL) /* R/W */
+#define E2P_DATA (SMSC9118_BASE + 0xB4)
+
+#define MAC_ADDRH (0x2)
+#define MAC_ADDRL (0x3)
+
+#define MAC_TIMEOUT 200
+
+#define HIBYTE(word) ((u8)(((u16)(word)) >> 8))
+#define LOBYTE(word) ((u8)(((u16)(word)) & 0x00FFU))
+#define HIWORD(dword) ((u16)(((u32)(dword)) >> 16))
+#define LOWORD(dword) ((u16)(((u32)(dword)) & 0x0000FFFFUL))
+
+static int mac_busy(int req_to)
+{
+ int timeout = req_to;
+
+ while (timeout--) {
+ if (!(smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY))
+ goto done;
+ }
+ return 1; /* Timeout */
+
+done:
+ return 0; /* No timeout */
+}
+
+static ulong get_mac_reg(int reg)
+{
+ ulong reg_val = 0xffffffff;
+
+ if (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) {
+ printf("get_mac_reg: previous command not complete\n");
+ goto done;
+ }
+
+ smc911x_reg_write(MAC_CSR_CMD, MAC_RD_CMD(reg));
+ udelay(10000);
+
+ if (mac_busy(MAC_TIMEOUT) == 1) {
+ printf("get_mac_reg: timeout waiting for response from MAC\n");
+ goto done;
+ }
+
+ reg_val = smc911x_reg_read(MAC_CSR_DATA);
+
+done:
+ return (reg_val);
+}
+
+static ulong eeprom_enable_access(void)
+{
+ ulong gpio;
+
+ gpio = smc911x_reg_read(GPIO_CFG);
+ debug("%s: gpio= 0x%08lx ---> 0x%08lx\n", __func__, gpio,
+ (gpio & 0xFF0FFFFFUL));
+
+ smc911x_reg_write(GPIO_CFG, (gpio & 0xFF0FFFFFUL));
+ return gpio;
+}
+
+static void eeprom_disable_access(ulong gpio)
+{
+ debug("%s: gpio= 0x%08lx\n", __func__, gpio);
+ smc911x_reg_write(GPIO_CFG, gpio);
+}
+
+static int eeprom_is_mac_address_loaded(void)
+{
+ int ret;
+
+ ret = smc911x_reg_read(MAC_CSR_CMD) & E2P_CMD_MAC_ADDR_LOADED_;
+ debug("%s: ret = %x\n", __func__, ret);
+
+ return ret;
+}
+
+static int eeprom_read_location(unchar address, u8 *data)
+{
+ ulong timeout = 100000;
+ ulong temp = 0;
+
+ if ((temp = smc911x_reg_read(E2P_CMD)) & E2P_CMD_EPC_BUSY_) {
+ printf("%s: Busy at start, E2P_CMD=0x%08lX\n", __func__, temp);
+ return 0;
+ }
+
+ smc911x_reg_write(E2P_CMD,
+ (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_ |
+ ((ulong) address)));
+
+ while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0) {
+ printf("Timeout\n");
+ return 0;
+ }
+ (*data) = (unchar) (smc911x_reg_read(E2P_DATA));
+ debug("%s: ret = %x\n", __func__, (*data));
+
+ return 1;
+}
+
+static int eeprom_enable_erase_and_write(void)
+{
+ ulong timeout = 100000;
+
+ if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+ printf("%s: Busy at start\n", __func__);
+ return 0;
+ }
+ smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_));
+
+ while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0) {
+ printf("Timeout[1]\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+static int eeprom_disable_erase_and_write(void)
+{
+ ulong timeout = 100000;
+
+ if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+ printf("%s: Busy at start\n", __func__);
+ return 0;
+ }
+ smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWDS_));
+
+ while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0) {
+ printf("Timeout[2]\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+static int eeprom_write_location(unchar address, unchar data)
+{
+ ulong timeout = 100000;
+
+ debug("%s: address: %x data = %x\n", __func__, address, data);
+
+ if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+ printf("%s: Busy at start\n", __func__);
+ return 0;
+ }
+
+ smc911x_reg_write(E2P_DATA, ((ulong) data));
+ smc911x_reg_write(E2P_CMD,
+ (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_ |
+ ((ulong) address)));
+
+ while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0) {
+ printf("Timeout[3]\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+static int eeprom_erase_all(void)
+{
+ ulong timeout = 100000;
+
+ if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+ printf("%s: Busy at start\n", __func__);
+ return 0;
+ }
+
+ smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_ERAL_));
+
+ while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0) {
+ printf("Timeout[4]\n");
+ return 0;
+ }
+
+ return 1;
+}
+
+static int eeprom_reload(void)
+{
+ ulong timeout = 100000;
+
+ if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) {
+ printf("%s: Busy at start\n", __func__);
+ return -1;
+ }
+ smc911x_reg_write(E2P_CMD,
+ (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
+
+ while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) {
+ udelay(10);
+ timeout--;
+ }
+
+ if (timeout == 0)
+ return 0;
+
+ return 1;
+}
+
+static int eeprom_save_mac_address(ulong dwHi16, ulong dwLo32)
+{
+ int result = 0;
+
+ debug("%s: dwHI: 0x%08lx dwLO: %08lx, \n", __func__, dwHi16, dwLo32);
+
+ if (!eeprom_enable_erase_and_write())
+ goto DONE;
+ if (!eeprom_erase_all())
+ goto DONE;
+ if (!eeprom_write_location(0, 0xA5))
+ goto DONE;
+ if (!eeprom_write_location(1, LOBYTE(LOWORD(dwLo32))))
+ goto DONE;
+ if (!eeprom_write_location(2, HIBYTE(LOWORD(dwLo32))))
+ goto DONE;
+ if (!eeprom_write_location(3, LOBYTE(HIWORD(dwLo32))))
+ goto DONE;
+ if (!eeprom_write_location(4, HIBYTE(HIWORD(dwLo32))))
+ goto DONE;
+ if (!eeprom_write_location(5, LOBYTE(LOWORD(dwHi16))))
+ goto DONE;
+ if (!eeprom_write_location(6, HIBYTE(LOWORD(dwHi16))))
+ goto DONE;
+ if (!eeprom_disable_erase_and_write())
+ goto DONE;
+
+ result = 1;
+
+DONE:
+ return result;
+}
+
+static int do_eeprom_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unchar data = 0, index = 0;
+ ulong gpio_old_val;
+
+ gpio_old_val = eeprom_enable_access();
+
+ printf("EEPROM content: \n");
+ for (index = 0; index < 8; index++) {
+ if (eeprom_read_location(index, &data))
+ printf("%02x ", data);
+ else
+ printf("FAILED");
+ }
+
+ eeprom_disable_access(gpio_old_val);
+ printf("\n");
+
+ return 0;
+}
+
+static int do_eeprom_erase_all(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ eeprom_erase_all();
+
+ return 0;
+}
+
+static int do_eeprom_save_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong hi16, lo32;
+ unchar ethaddr[6], i;
+ ulong gpio;
+ char *tmp, *end;
+
+ tmp = argv[1];
+ for (i = 0; i < 6; i++) {
+ ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
+ if (tmp)
+ tmp = (*end) ? end + 1 : end;
+ }
+
+ hi16 = (ethaddr[5] << 8) | (ethaddr[4]);
+ lo32 = (ethaddr[3] << 24) | (ethaddr[2] << 16) |
+ (ethaddr[1] << 8) | (ethaddr[0]);
+
+ gpio = eeprom_enable_access();
+
+ eeprom_save_mac_address(hi16, lo32);
+
+ eeprom_reload();
+
+ /* Check new values */
+ if (eeprom_is_mac_address_loaded()) {
+ ulong mac_hi16, mac_lo32;
+
+ mac_hi16 = get_mac_reg(MAC_ADDRH);
+ mac_lo32 = get_mac_reg(MAC_ADDRL);
+ printf("New MAC address: %lx, %lx\n", mac_hi16, mac_lo32);
+ } else {
+ printf("Address is not reloaded \n");
+ }
+ eeprom_disable_access(gpio);
+
+ return 0;
+}
+
+U_BOOT_CMD(smcee, 1, 0, do_eeprom_erase_all,
+ "smcee - Erase content of SMC EEPROM",);
+
+U_BOOT_CMD(smced, 1, 0, do_eeprom_dump,
+ "smced - Dump content of SMC EEPROM",);
+
+U_BOOT_CMD(smcew, 2, 0, do_eeprom_save_mac,
+ "smcew - Write MAC address to SMC EEPROM\n",
+ "aa:bb:cc:dd:ee:ff new mac address");
diff --git a/board/micronas/vct/top.c b/board/micronas/vct/top.c
new file mode 100644
index 0000000..4e8e410
--- /dev/null
+++ b/board/micronas/vct/top.c
@@ -0,0 +1,276 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "vct.h"
+
+typedef union _TOP_PINMUX_t
+{
+ u32 reg;
+ struct {
+ u32 res : 24; /* reserved */
+ u32 drive : 2; /* Driver strength */
+ u32 slew : 1; /* Slew rate */
+ u32 strig : 1; /* Schmitt trigger input*/
+ u32 pu_pd : 2; /* Pull up/ pull down */
+ u32 funsel : 2; /* Pin function */
+ } Bits;
+} TOP_PINMUX_t;
+
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+
+static TOP_PINMUX_t top_read_pin(int pin)
+{
+ TOP_PINMUX_t reg;
+
+ switch (pin) {
+ case 2:
+ case 3:
+ case 6:
+ case 9:
+ reg.reg = 0xdeadbeef;
+ break;
+ case 4:
+ reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE));
+ break;
+ case 5:
+ reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE));
+ break;
+ case 7:
+ reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE));
+ break;
+ case 8:
+ reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE));
+ break;
+ case 10:
+ case 11:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
+ ((pin - 10) * 4));
+ break;
+ default:
+ reg.reg = reg_read(TOP_BASE + (pin * 4));
+ break;
+ }
+
+ return reg;
+}
+
+static void top_write_pin(int pin, TOP_PINMUX_t reg)
+{
+
+ switch (pin) {
+ case 4:
+ reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg);
+ break;
+ case 5:
+ reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg);
+ break;
+ case 7:
+ reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg);
+ break;
+ case 8:
+ reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg);
+ break;
+ case 10:
+ case 11:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
+ ((pin - 10) * 4), reg.reg);
+ break;
+ default:
+ reg_write(TOP_BASE + (pin * 4), reg.reg);
+ break;
+ }
+}
+
+int top_set_pin(int pin, int func)
+{
+ TOP_PINMUX_t reg;
+
+ /* check global range */
+ if ((pin < 0) || (pin > 170) || (func < 0) || (func > 3))
+ return -1; /* pin number or function out of valid range */
+
+ /* check undefined values; */
+ if ((pin == 2) || (pin == 3) || (pin == 6) || (pin == 9))
+ return -1; /* pin number out of valid range */
+
+ reg = top_read_pin(pin);
+ reg.Bits.funsel = func;
+ top_write_pin(pin, reg);
+
+ return 0;
+}
+
+#endif
+
+#if defined(CONFIG_VCT_PLATINUMAVC)
+
+int top_set_pin(int pin, int func)
+{
+ TOP_PINMUX_t reg;
+
+ /* check global range */
+ if ((pin < 0) || (pin > 158))
+ return -1; /* pin number or function out of valid range */
+
+ reg.reg = reg_read(TOP_BASE + (pin * 4));
+ reg.Bits.funsel = func;
+ reg_write(TOP_BASE + (pin * 4), reg.reg);
+
+ return 0;
+}
+
+#endif
+
+void vct_pin_mux_initialize(void)
+{
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+ top_set_pin(34, 01); /* EBI_CS0 */
+ top_set_pin(33, 01); /* EBI_CS1 */
+ top_set_pin(32, 01); /* EBI_CS2 */
+ top_set_pin(100, 02); /* EBI_CS3 */
+ top_set_pin(101, 02); /* EBI_CS4 */
+ top_set_pin(102, 02); /* EBI_CS5 */
+ top_set_pin(103, 02); /* EBI_CS6 */
+ top_set_pin(104, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */
+ top_set_pin(35, 01); /* EBI_ALE */
+ top_set_pin(36, 01); /* EBI_ADDR15 */
+ top_set_pin(37, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */
+ top_set_pin(38, 01); /* EBI_ADDR13 */
+ top_set_pin(39, 01); /* EBI_ADDR12 */
+ top_set_pin(40, 01); /* EBI_ADDR11 */
+ top_set_pin(41, 01); /* EBI_ADDR10 */
+ top_set_pin(42, 01); /* EBI_ADDR9 */
+ top_set_pin(43, 01); /* EBI_ADDR8 */
+ top_set_pin(44, 01); /* EBI_ADDR7 */
+ top_set_pin(45, 01); /* EBI_ADDR6 */
+ top_set_pin(46, 01); /* EBI_ADDR5 */
+ top_set_pin(47, 01); /* EBI_ADDR4 */
+ top_set_pin(48, 01); /* EBI_ADDR3 */
+ top_set_pin(49, 01); /* EBI_ADDR2 */
+ top_set_pin(50, 01); /* EBI_ADDR1 */
+ top_set_pin(51, 01); /* EBI_ADDR0 */
+ top_set_pin(52, 01); /* EBI_DIR */
+ top_set_pin(53, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */
+ top_set_pin(54, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */
+ top_set_pin(55, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */
+ top_set_pin(56, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */
+ top_set_pin(57, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */
+ top_set_pin(58, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */
+ top_set_pin(59, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */
+ top_set_pin(60, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */
+ top_set_pin(61, 01); /* EBI_DAT7 */
+ top_set_pin(62, 01); /* EBI_DAT6 */
+ top_set_pin(63, 01); /* EBI_DAT5 */
+ top_set_pin(64, 01); /* EBI_DAT4 */
+ top_set_pin(65, 01); /* EBI_DAT3 */
+ top_set_pin(66, 01); /* EBI_DAT2 */
+ top_set_pin(67, 01); /* EBI_DAT1 */
+ top_set_pin(68, 01); /* EBI_DAT0 */
+ top_set_pin(69, 01); /* EBI_IORD */
+ top_set_pin(70, 01); /* EBI_IOWR */
+ top_set_pin(71, 01); /* EBI_WE */
+ top_set_pin(72, 01); /* EBI_OE */
+ top_set_pin(73, 01); /* EBI_IORDY */
+ top_set_pin(95, 02); /* EBI_EBI_DMACK*/
+ top_set_pin(112, 02); /* EBI_IRQ0 */
+ top_set_pin(111, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */
+ top_set_pin(107, 02); /* EBI_IRQ2 */
+ top_set_pin(108, 02); /* EBI_IRQ3 */
+ top_set_pin(30, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */
+ top_set_pin(31, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */
+ top_set_pin(105, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */
+ top_set_pin(106, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */
+ top_set_pin(109, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */
+ top_set_pin(110, 02); /* EBI_BURST_CLK */
+#endif
+
+#if defined(CONFIG_VCT_PLATINUMAVC)
+ top_set_pin(19, 01); /* EBI_CS0 */
+ top_set_pin(18, 01); /* EBI_CS1 */
+ top_set_pin(17, 01); /* EBI_CS2 */
+ top_set_pin(92, 02); /* EBI_CS3 */
+ top_set_pin(93, 02); /* EBI_CS4 */
+ top_set_pin(95, 02); /* EBI_CS6 */
+ top_set_pin(96, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */
+ top_set_pin(20, 01); /* EBI_ALE */
+ top_set_pin(21, 01); /* EBI_ADDR15 */
+ top_set_pin(22, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */
+ top_set_pin(23, 01); /* EBI_ADDR13 */
+ top_set_pin(24, 01); /* EBI_ADDR12 */
+ top_set_pin(25, 01); /* EBI_ADDR11 */
+ top_set_pin(26, 01); /* EBI_ADDR10 */
+ top_set_pin(27, 01); /* EBI_ADDR9 */
+ top_set_pin(28, 01); /* EBI_ADDR8 */
+ top_set_pin(29, 01); /* EBI_ADDR7 */
+ top_set_pin(30, 01); /* EBI_ADDR6 */
+ top_set_pin(31, 01); /* EBI_ADDR5 */
+ top_set_pin(32, 01); /* EBI_ADDR4 */
+ top_set_pin(33, 01); /* EBI_ADDR3 */
+ top_set_pin(34, 01); /* EBI_ADDR2 */
+ top_set_pin(35, 01); /* EBI_ADDR1 */
+ top_set_pin(36, 01); /* EBI_ADDR0 */
+ top_set_pin(37, 01); /* EBI_DIR */
+ top_set_pin(38, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */
+ top_set_pin(39, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */
+ top_set_pin(40, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */
+ top_set_pin(41, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */
+ top_set_pin(42, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */
+ top_set_pin(43, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */
+ top_set_pin(44, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */
+ top_set_pin(45, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */
+ top_set_pin(46, 01); /* EBI_DAT7 */
+ top_set_pin(47, 01); /* EBI_DAT6 */
+ top_set_pin(48, 01); /* EBI_DAT5 */
+ top_set_pin(49, 01); /* EBI_DAT4 */
+ top_set_pin(50, 01); /* EBI_DAT3 */
+ top_set_pin(51, 01); /* EBI_DAT2 */
+ top_set_pin(52, 01); /* EBI_DAT1 */
+ top_set_pin(53, 01); /* EBI_DAT0 */
+ top_set_pin(54, 01); /* EBI_IORD */
+ top_set_pin(55, 01); /* EBI_IOWR */
+ top_set_pin(56, 01); /* EBI_WE */
+ top_set_pin(57, 01); /* EBI_OE */
+ top_set_pin(58, 01); /* EBI_IORDY */
+ top_set_pin(87, 02); /* EBI_EBI_DMACK*/
+ top_set_pin(106, 02); /* EBI_IRQ0 */
+ top_set_pin(105, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */
+ top_set_pin(101, 02); /* EBI_IRQ2 */
+ top_set_pin(102, 02); /* EBI_IRQ3 */
+ top_set_pin(15, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */
+ top_set_pin(16, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */
+ top_set_pin(99, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */
+ top_set_pin(100, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */
+ top_set_pin(103, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */
+ top_set_pin(104, 02); /* EBI_BURST_CLK */
+#endif
+
+ /* I2C: Configure I2C-2 as GPIO to enable soft-i2c */
+ top_set_pin(0, 2); /* SCL2 on GPIO 11 */
+ top_set_pin(1, 2); /* SDA2 on GPIO 10 */
+
+ /* UART pins */
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+ top_set_pin(141, 1);
+ top_set_pin(143, 1);
+#endif
+#if defined(CONFIG_VCT_PLATINUMAVC)
+ top_set_pin(107, 1);
+ top_set_pin(109, 1);
+#endif
+}
diff --git a/board/micronas/vct/vct.c b/board/micronas/vct/vct.c
new file mode 100644
index 0000000..0745cee
--- /dev/null
+++ b/board/micronas/vct/vct.c
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mipsregs.h>
+#include "vct.h"
+
+#if defined(CONFIG_VCT_PREMIUM)
+#define BOARD_NAME "PremiumD"
+#elif defined(CONFIG_VCT_PLATINUM)
+#define BOARD_NAME "PlatinumD"
+#elif defined(CONFIG_VCT_PLATINUMAVC)
+#define BOARD_NAME "PlatinumAVC"
+#else
+#error "vct: No board variant defined!"
+#endif
+
+#if defined(CONFIG_VCT_ONENAND)
+#define BOARD_NAME_ADD " OneNAND"
+#else
+#define BOARD_NAME_ADD " NOR"
+#endif
+
+int board_early_init_f(void)
+{
+ /*
+ * First initialize the PIN mulitplexing
+ */
+ vct_pin_mux_initialize();
+
+ /*
+ * Init the EBI very early so that FLASH can be accessed
+ */
+ ebi_initialize();
+
+ return 0;
+}
+
+void _machine_restart(void)
+{
+ reg_write(DCGU_EN_WDT_RESET(DCGU_BASE), DCGU_MAGIC_WDT);
+ reg_write(WDT_TORR(WDT_BASE), 0x00);
+ reg_write(WDT_CR(WDT_BASE), 0x1D);
+
+ /*
+ * Now wait for the watchdog to trigger the reset
+ */
+ udelay(1000000);
+}
+
+/*
+ * SDRAM is already configured by the bootstrap code, only return the
+ * auto-detected size here
+ */
+phys_size_t initdram(int board_type)
+{
+ return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_MBYTES_SDRAM << 20);
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+ u32 config0 = read_c0_prid();
+
+ if ((config0 & 0xff0000) == PRID_COMP_LEGACY
+ && (config0 & 0xff00) == PRID_IMP_LX4280) {
+ puts("Board: MDED \n");
+ printf("CPU: LX4280 id: 0x%02x, rev: 0x%02x\n",
+ (config0 >> 8) & 0xFF, config0 & 0xFF);
+ } else if ((config0 & 0xff0000) == PRID_COMP_MIPS
+ && (config0 & 0xff00) == PRID_IMP_VGC) {
+ u32 jedec_id = *((u32 *) 0xBEBC71A0);
+ if ((((jedec_id) >> 12) & 0xFF) == 0x40) {
+ puts("Board: VGCA \n");
+ } else if ((((jedec_id) >> 12) & 0xFF) == 0x48
+ || (((jedec_id) >> 12) & 0xFF) == 0x49) {
+ puts("Board: VGCB \n");
+ }
+ printf("CPU: MIPS 4K id: 0x%02x, rev: 0x%02x\n",
+ (config0 >> 8) & 0xFF, config0 & 0xFF);
+ } else if (config0 == 0x19378) {
+ printf("CPU: MIPS 24K id: 0x%02x, rev: 0x%02x\n",
+ (config0 >> 8) & 0xFF, config0 & 0xFF);
+ } else {
+ printf("Unsupported cpu %d, proc_id=0x%x\n", config0 >> 24,
+ config0);
+ }
+
+ printf("Board: Micronas VCT " BOARD_NAME BOARD_NAME_ADD);
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/micronas/vct/vct.h b/board/micronas/vct/vct.h
new file mode 100644
index 0000000..0a1c5fc
--- /dev/null
+++ b/board/micronas/vct/vct.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+
+#include "bcu.h"
+#include "dcgu.h"
+#include "ebi.h"
+#include "scc.h"
+
+#ifdef CONFIG_VCT_PREMIUM
+/* Global start address of all memory mapped registers */
+#define REG_GLOBAL_START_ADDR 0xbf800000
+#define TOP_BASE 0x000c8000
+
+#include "vcth/reg_ebi.h"
+#include "vcth/reg_dcgu.h"
+#include "vcth/reg_wdt.h"
+#include "vcth/reg_gpio.h"
+#include "vcth/reg_fwsram.h"
+#include "vcth/reg_scc.h"
+#include "vcth/reg_usbh.h"
+#endif
+
+#ifdef CONFIG_VCT_PLATINUM
+/* Global start address of all memory mapped registers */
+#define REG_GLOBAL_START_ADDR 0xbf800000
+#define TOP_BASE 0x000c8000
+
+#include "vcth2/reg_ebi.h"
+#include "vcth/reg_dcgu.h"
+#include "vcth/reg_wdt.h"
+#include "vcth/reg_gpio.h"
+#include "vcth/reg_fwsram.h"
+#include "vcth/reg_scc.h"
+#include "vcth/reg_usbh.h"
+#endif
+
+#ifdef CONFIG_VCT_PLATINUMAVC
+/* Global start address of all memory mapped registers */
+#define REG_GLOBAL_START_ADDR 0xbdc00000
+#define TOP_BASE 0x00050000
+
+#include "vctv/reg_ebi.h"
+#include "vctv/reg_dcgu.h"
+#include "vctv/reg_wdt.h"
+#include "vctv/reg_gpio.h"
+#endif
+
+#ifndef _VCT_H
+#define _VCT_H
+
+/*
+ * Defines
+ */
+#define PRID_COMP_LEGACY 0x000000
+#define PRID_COMP_MIPS 0x010000
+#define PRID_IMP_LX4280 0xc200
+#define PRID_IMP_VGC 0x9000
+
+/*
+ * Prototypes
+ */
+int ebi_initialize(void);
+int ebi_init_nor_flash(void);
+int ebi_init_onenand(void);
+int ebi_init_smc911x(void);
+u32 smc911x_reg_read(u32 addr);
+void smc911x_reg_write(u32 addr, u32 data);
+int top_set_pin(int pin, int func);
+void vct_pin_mux_initialize(void);
+
+/*
+ * static inlines
+ */
+static inline void reg_write(u32 addr, u32 data)
+{
+ __raw_writel(data, addr + REG_GLOBAL_START_ADDR);
+}
+
+static inline u32 reg_read(u32 addr)
+{
+ return __raw_readl(addr + REG_GLOBAL_START_ADDR);
+}
+
+#endif /* _VCT_H */
diff --git a/board/micronas/vct/vcth/reg_dcgu.h b/board/micronas/vct/vcth/reg_dcgu.h
new file mode 100644
index 0000000..2c7f52a
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_dcgu.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2008-2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define DCGU_BASE 0x00084000
+
+/* Relative offsets of the register adresses */
+
+#define DCGU_CLK_EN1_OFFS 0x00000010
+#define DCGU_CLK_EN1(base) ((base) + DCGU_CLK_EN1_OFFS)
+#define DCGU_CLK_EN2_OFFS 0x00000014
+#define DCGU_CLK_EN2(base) ((base) + DCGU_CLK_EN2_OFFS)
+#define DCGU_RESET_UNIT1_OFFS 0x00000018
+#define DCGU_RESET_UNIT1(base) ((base) + DCGU_RESET_UNIT1_OFFS)
+#define DCGU_USBPHY_STAT_OFFS 0x00000054
+#define DCGU_USBPHY_STAT(base) ((base) + DCGU_USBPHY_STAT_OFFS)
+#define DCGU_EN_WDT_RESET_OFFS 0x00000064
+#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS)
+
+/* The magic value to write in order to activate the WDT */
+#define DCGU_MAGIC_WDT 0x1909
diff --git a/board/micronas/vct/vcth/reg_ebi.h b/board/micronas/vct/vcth/reg_ebi.h
new file mode 100644
index 0000000..43728d1
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_ebi.h
@@ -0,0 +1,229 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _REG_EBI_PREMIUM_H_
+#define _REG_EBI_PREMIUM_H_
+
+#define EBI_BASE 0x00000000
+
+/* Relative offsets of the register adresses */
+
+#define EBI_CPU_IO_ACCS_OFFS 0x00000000
+#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
+#define EBI_IO_ACCS_DATA_OFFS 0x00000004
+#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
+#define EBI_CTRL_OFFS 0x00000008
+#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
+#define EBI_IRQ_MASK_OFFS 0x00000010
+#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
+#define EBI_TAG1_SYS_ID_OFFS 0x00000030
+#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
+#define EBI_TAG2_SYS_ID_OFFS 0x00000040
+#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
+#define EBI_TAG3_SYS_ID_OFFS 0x00000050
+#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
+#define EBI_TAG4_SYS_ID_OFFS 0x00000060
+#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
+#define EBI_GEN_DMA_CTRL_OFFS 0x00000070
+#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
+#define EBI_STATUS_OFFS 0x00000080
+#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
+#define EBI_STATUS_DMA_CNT_OFFS 0x00000084
+#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
+#define EBI_SIG_LEVEL_OFFS 0x00000088
+#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
+#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
+#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
+#define EBI_EXT_ADDR_OFFS 0x000000A0
+#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
+#define EBI_IRQ_STATUS_OFFS 0x000000B0
+#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
+#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
+#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV1_EXT_ACC_OFFS 0x00000104
+#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
+#define EBI_DEV1_CONFIG1_OFFS 0x00000108
+#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
+#define EBI_DEV1_CONFIG2_OFFS 0x0000010C
+#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
+#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
+#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
+#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
+#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
+#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
+#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
+#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
+#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
+#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
+#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
+#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
+#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
+#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
+#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
+#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
+#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
+#define EBI_DEV1_TIM_EXT_OFFS 0x00000134
+#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
+#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
+#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
+#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
+#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
+#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
+#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
+#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
+#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
+#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV2_EXT_ACC_OFFS 0x00000204
+#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
+#define EBI_DEV2_CONFIG1_OFFS 0x00000208
+#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
+#define EBI_DEV2_CONFIG2_OFFS 0x0000020C
+#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
+#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
+#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
+#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
+#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
+#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
+#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
+#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
+#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
+#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
+#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
+#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
+#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
+#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
+#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
+#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
+#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
+#define EBI_DEV2_TIM_EXT_OFFS 0x00000234
+#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
+#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
+#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
+#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
+#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
+#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
+#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
+#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
+#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
+#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV3_EXT_ACC_OFFS 0x00000304
+#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
+#define EBI_DEV3_CONFIG1_OFFS 0x00000308
+#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
+#define EBI_DEV3_CONFIG2_OFFS 0x0000030C
+#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
+#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
+#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
+#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
+#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
+#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
+#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
+#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
+#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
+#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
+#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
+#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
+#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
+#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
+#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
+#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
+#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
+#define EBI_DEV3_TIM_EXT_OFFS 0x00000334
+#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
+#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
+#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
+#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
+#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
+#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
+#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
+#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
+#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
+#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV4_EXT_ACC_OFFS 0x00000404
+#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
+#define EBI_DEV4_CONFIG1_OFFS 0x00000408
+#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
+#define EBI_DEV4_CONFIG2_OFFS 0x0000040C
+#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
+#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
+#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
+#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
+#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
+#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
+#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
+#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
+#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
+#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
+#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
+#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
+#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
+#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
+#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
+#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
+#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
+#define EBI_DEV4_TIM_EXT_OFFS 0x00000434
+#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
+#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
+#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
+#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
+#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
+#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
+#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
+#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
+#define EBI_CNT_FL_PROGR_OFFS 0x00000904
+#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
+#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
+#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
+#define EBI_CNT_WAIT_RDY_OFFS 0x00000914
+#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
+#define EBI_CNT_ACK_OFFS 0x00000918
+#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
+#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
+#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
+#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
+#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
+#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
+#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
+#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
+#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
+#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
+#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
+#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
+#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
+#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
+#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
+#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
+#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
+#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
+#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
+#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
+#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
+#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
+#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
+#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
+#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
+#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
+#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
+#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
+#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
+#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
+#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vcth/reg_fwsram.h b/board/micronas/vct/vcth/reg_fwsram.h
new file mode 100644
index 0000000..271baa4
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_fwsram.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Premium & Platinum register addresses/definitions seem to be
+ * identical, so we only need to use one file for both platforms.
+ */
+
+#ifndef _REG_FWSRAM_H_
+#define _REG_FWSRAM_H_
+
+#define FWSRAM_BASE 0x00030000
+
+/* Relative offsets of the register adresses */
+
+#define FWSRAM_SR_ADDR_OFFSET_OFFS 0x00002000
+#define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS)
+#define FWSRAM_TOP_BOOT_LOG_OFFS 0x00002004
+#define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS)
+#define FWSRAM_TOP_ROM_KBIST_OFFS 0x00002008
+#define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS)
+#define FWSRAM_TOP_CID1_H_OFFS 0x0000200C
+#define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS)
+#define FWSRAM_TOP_CID1_L_OFFS 0x00002010
+#define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS)
+#define FWSRAM_TOP_CID2_H_OFFS 0x00002014
+#define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS)
+#define FWSRAM_TOP_CID2_L_OFFS 0x00002018
+#define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS)
+#define FWSRAM_TOP_TDO_CFG_OFFS 0x0000203C
+#define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_0_CFG_OFFS 0x00002040
+#define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_1_CFG_OFFS 0x00002044
+#define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_2_CFG_OFFS 0x00002048
+#define FWSRAM_TOP_GPIO2_2_CFG(base) ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_3_CFG_OFFS 0x0000204C
+#define FWSRAM_TOP_GPIO2_3_CFG(base) ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_4_CFG_OFFS 0x00002050
+#define FWSRAM_TOP_GPIO2_4_CFG(base) ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_5_CFG_OFFS 0x00002054
+#define FWSRAM_TOP_GPIO2_5_CFG(base) ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_6_CFG_OFFS 0x00002058
+#define FWSRAM_TOP_GPIO2_6_CFG(base) ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_7_CFG_OFFS 0x0000205C
+#define FWSRAM_TOP_GPIO2_7_CFG(base) ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS)
+#define FWSRAM_TOP_SCL_CFG_OFFS 0x00002060
+#define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS)
+#define FWSRAM_TOP_SDA_CFG_OFFS 0x00002064
+#define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS)
+#define FWSRAM_NO_MCM_FLASH_OFFS 0x00002068
+#define FWSRAM_NO_MCM_FLASH(base) ((base) + FWSRAM_NO_MCM_FLASH_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vcth/reg_gpio.h b/board/micronas/vct/vcth/reg_gpio.h
new file mode 100644
index 0000000..43752c3
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_gpio.h
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define GPIO1_BASE 0x00088000
+#define GPIO2_BASE 0x0008c000
+
+/* Instances */
+#define GPIO_INSTANCES 2
+
+/* Relative offsets of the register adresses */
+#define GPIO_SWPORTA_DR_OFFS 0x00000000
+#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS)
+#define GPIO_SWPORTA_DDR_OFFS 0x00000004
+#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS)
+#define GPIO_EXT_PORTA_OFFS 0x00000050
+#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS)
diff --git a/board/micronas/vct/vcth/reg_scc.h b/board/micronas/vct/vcth/reg_scc.h
new file mode 100644
index 0000000..726e438
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_scc.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _REG_SCC_PREMIUM_H_
+#define _REG_SCC_PREMIUM_H_
+
+#define SCC0_BASE 0x00110000
+#define SCC1_BASE 0x00110080
+#define SCC2_BASE 0x00110100
+#define SCC3_BASE 0x00110180
+#define SCC4_BASE 0x00110200
+#define SCC5_BASE 0x00110280
+#define SCC6_BASE 0x00110300
+#define SCC7_BASE 0x00110380
+#define SCC8_BASE 0x00110400
+#define SCC9_BASE 0x00110480
+#define SCC10_BASE 0x00110500
+#define SCC11_BASE 0x00110580
+#define SCC12_BASE 0x00110600
+#define SCC13_BASE 0x00110680
+#define SCC14_BASE 0x00110700
+#define SCC15_BASE 0x00110780
+#define SCC16_BASE 0x00110800
+#define SCC17_BASE 0x00110880
+#define SCC18_BASE 0x00110900
+#define SCC19_BASE 0x00110980
+#define SCC20_BASE 0x00110a00
+#define SCC21_BASE 0x00110a80
+#define SCC22_BASE 0x00110b00
+#define SCC23_BASE 0x00110b80
+#define SCC24_BASE 0x00110c00
+#define SCC25_BASE 0x00110c80
+#define SCC26_BASE 0x00110d00
+#define SCC27_BASE 0x00110d80
+#define SCC28_BASE 0x00110e00
+#define SCC29_BASE 0x00110e80
+#define SCC30_BASE 0x00110f00
+#define SCC31_BASE 0x00110f80
+#define SCC32_BASE 0x00111000
+#define SCC33_BASE 0x00111080
+#define SCC34_BASE 0x00111100
+#define SCC35_BASE 0x00111180
+#define SCC36_BASE 0x00111200
+#define SCC37_BASE 0x00111280
+#define SCC38_BASE 0x00111300
+#define SCC39_BASE 0x00111380
+#define SCC40_BASE 0x00111400
+
+/* Relative offsets of the register adresses */
+
+#define SCC_ENABLE_OFFS 0x00000000
+#define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS)
+#define SCC_RESET_OFFS 0x00000004
+#define SCC_RESET(base) ((base) + SCC_RESET_OFFS)
+#define SCC_VCID_OFFS 0x00000008
+#define SCC_VCID(base) ((base) + SCC_VCID_OFFS)
+#define SCC_MCI_CFG_OFFS 0x0000000C
+#define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS)
+#define SCC_PACKET_CFG1_OFFS 0x00000010
+#define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS)
+#define SCC_PACKET_CFG2_OFFS 0x00000014
+#define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS)
+#define SCC_PACKET_CFG3_OFFS 0x00000018
+#define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS)
+#define SCC_DMA_CFG_OFFS 0x0000001C
+#define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS)
+#define SCC_CMD_OFFS 0x00000020
+#define SCC_CMD(base) ((base) + SCC_CMD_OFFS)
+#define SCC_PRIO_OFFS 0x00000024
+#define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS)
+#define SCC_DEBUG_OFFS 0x00000028
+#define SCC_DEBUG(base) ((base) + SCC_DEBUG_OFFS)
+#define SCC_STATUS_OFFS 0x0000002C
+#define SCC_STATUS(base) ((base) + SCC_STATUS_OFFS)
+#define SCC_IMR_OFFS 0x00000030
+#define SCC_IMR(base) ((base) + SCC_IMR_OFFS)
+#define SCC_ISR_OFFS 0x00000034
+#define SCC_ISR(base) ((base) + SCC_ISR_OFFS)
+#define SCC_DMA_OFFSET_OFFS 0x00000038
+#define SCC_DMA_OFFSET(base) ((base) + SCC_DMA_OFFSET_OFFS)
+#define SCC_RS_CTLSTS_OFFS 0x0000003C
+#define SCC_RS_CTLSTS(base) ((base) + SCC_RS_CTLSTS_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vcth/reg_usbh.h b/board/micronas/vct/vcth/reg_usbh.h
new file mode 100644
index 0000000..44b7c4a
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_usbh.h
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define USBH_BASE 0x00080000
+
+/* Relative offsets of the register adresses */
+
+#define USBH_CAPLENGTH_OFFS 0x00000100
+#define USBH_CAPLENGTH(base) ((base) + USBH_CAPLENGTH_OFFS)
+#define USBH_USBCMD_OFFS 0x00000140
+#define USBH_USBCMD(base) ((base) + USBH_USBCMD_OFFS)
+#define USBH_BURSTSIZE_OFFS 0x00000160
+#define USBH_BURSTSIZE(base) ((base) + USBH_BURSTSIZE_OFFS)
+#define USBH_USBMODE_OFFS 0x000001A8
+#define USBH_USBMODE(base) ((base) + USBH_USBMODE_OFFS)
+#define USBH_USBHMISC_OFFS 0x00000200
+#define USBH_USBHMISC(base) ((base) + USBH_USBHMISC_OFFS)
diff --git a/board/micronas/vct/vcth/reg_wdt.h b/board/micronas/vct/vcth/reg_wdt.h
new file mode 100644
index 0000000..f1a5073
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_wdt.h
@@ -0,0 +1,11 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define WDT_BASE 0x000b0000
+#define WDT_CR_OFFS 0x00000000
+#define WDT_CR(base) ((base) + WDT_CR_OFFS)
+#define WDT_TORR_OFFS 0x00000004
+#define WDT_TORR(base) ((base) + WDT_TORR_OFFS)
diff --git a/board/micronas/vct/vcth2/reg_ebi.h b/board/micronas/vct/vcth2/reg_ebi.h
new file mode 100644
index 0000000..0c21cd9
--- /dev/null
+++ b/board/micronas/vct/vcth2/reg_ebi.h
@@ -0,0 +1,277 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _REG_EBI_PREMIUM_H_
+#define _REG_EBI_PREMIUM_H_
+
+#define EBI_BASE 0x00000000
+
+/* Relative offsets of the register adresses */
+
+#define EBI_CPU_IO_ACCS_OFFS 0x00000000
+#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
+#define EBI_IO_ACCS_DATA_OFFS 0x00000004
+#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
+#define EBI_CPU_IO_ACCS2_OFFS 0x00000008
+#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS)
+#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C
+#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS)
+#define EBI_CTRL_OFFS 0x00000010
+#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
+#define EBI_IRQ_MASK_OFFS 0x00000018
+#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
+#define EBI_IRQ_MASK2_OFFS 0x0000001C
+#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS)
+#define EBI_TAG1_SYS_ID_OFFS 0x00000030
+#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
+#define EBI_TAG2_SYS_ID_OFFS 0x00000040
+#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
+#define EBI_TAG3_SYS_ID_OFFS 0x00000050
+#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
+#define EBI_TAG4_SYS_ID_OFFS 0x00000060
+#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
+#define EBI_GEN_DMA_CTRL_OFFS 0x00000070
+#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
+#define EBI_STATUS_OFFS 0x00000080
+#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
+#define EBI_STATUS_DMA_CNT_OFFS 0x00000084
+#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
+#define EBI_SIG_LEVEL_OFFS 0x00000088
+#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
+#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
+#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
+#define EBI_CRC_GEN_OFFS 0x00000090
+#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS)
+#define EBI_EXT_ADDR_OFFS 0x000000A0
+#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
+#define EBI_IRQ_STATUS_OFFS 0x000000B0
+#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
+#define EBI_IRQ_STATUS2_OFFS 0x000000B4
+#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS)
+#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0
+#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS)
+#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4
+#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS)
+#define EBI_ECC0_OFFS 0x000000D0
+#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS)
+#define EBI_ECC1_OFFS 0x000000D4
+#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS)
+#define EBI_ECC2_OFFS 0x000000D8
+#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS)
+#define EBI_ECC3_OFFS 0x000000DC
+#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS)
+#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
+#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV1_EXT_ACC_OFFS 0x00000104
+#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
+#define EBI_DEV1_CONFIG1_OFFS 0x00000108
+#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
+#define EBI_DEV1_CONFIG2_OFFS 0x0000010C
+#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
+#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
+#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
+#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
+#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
+#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
+#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
+#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
+#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
+#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120
+#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
+#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
+#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
+#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
+#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
+#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
+#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
+#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
+#define EBI_DEV1_TIM_EXT_OFFS 0x00000134
+#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
+#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
+#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
+#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
+#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
+#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
+#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148
+#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS)
+#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C
+#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS)
+#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
+#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
+#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
+#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV2_EXT_ACC_OFFS 0x00000204
+#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
+#define EBI_DEV2_CONFIG1_OFFS 0x00000208
+#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
+#define EBI_DEV2_CONFIG2_OFFS 0x0000020C
+#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
+#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
+#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
+#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
+#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
+#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
+#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
+#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
+#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
+#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220
+#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
+#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
+#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
+#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
+#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
+#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
+#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
+#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
+#define EBI_DEV2_TIM_EXT_OFFS 0x00000234
+#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
+#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
+#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
+#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
+#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
+#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
+#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248
+#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS)
+#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C
+#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS)
+#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
+#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
+#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
+#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV3_EXT_ACC_OFFS 0x00000304
+#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
+#define EBI_DEV3_CONFIG1_OFFS 0x00000308
+#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
+#define EBI_DEV3_CONFIG2_OFFS 0x0000030C
+#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
+#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
+#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
+#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
+#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
+#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
+#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
+#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
+#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
+#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320
+#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
+#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
+#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
+#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
+#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
+#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
+#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
+#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
+#define EBI_DEV3_TIM_EXT_OFFS 0x00000334
+#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
+#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
+#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
+#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
+#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
+#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
+#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348
+#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS)
+#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C
+#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS)
+#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
+#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
+#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
+#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV4_EXT_ACC_OFFS 0x00000404
+#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
+#define EBI_DEV4_CONFIG1_OFFS 0x00000408
+#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
+#define EBI_DEV4_CONFIG2_OFFS 0x0000040C
+#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
+#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
+#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
+#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
+#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
+#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
+#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
+#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
+#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
+#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420
+#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
+#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
+#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
+#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
+#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
+#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
+#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
+#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
+#define EBI_DEV4_TIM_EXT_OFFS 0x00000434
+#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
+#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
+#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
+#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
+#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
+#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
+#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448
+#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS)
+#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C
+#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS)
+#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
+#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
+#define EBI_INTERLEAVE_CNT_OFFS 0x00000900
+#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS)
+#define EBI_CNT_FL_PROGR_OFFS 0x00000904
+#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
+#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
+#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
+#define EBI_CNT_WAIT_RDY_OFFS 0x00000914
+#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
+#define EBI_CNT_ACK_OFFS 0x00000918
+#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
+#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
+#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
+#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
+#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
+#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
+#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
+#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
+#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
+#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
+#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
+#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
+#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
+#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
+#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
+#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
+#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
+#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
+#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
+#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
+#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
+#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
+#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
+#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
+#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
+#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
+#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
+#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
+#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
+#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
+#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vctv/reg_dcgu.h b/board/micronas/vct/vctv/reg_dcgu.h
new file mode 100644
index 0000000..c4c7e8b
--- /dev/null
+++ b/board/micronas/vct/vctv/reg_dcgu.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define DCGU_BASE 0x0004c000
+#define DCGU_EN_WDT_RESET_OFFS 0x000000FC
+#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS)
+
+/* The magic value to write in order to activate the WDT */
+#define DCGU_MAGIC_WDT 0x1909
diff --git a/board/micronas/vct/vctv/reg_ebi.h b/board/micronas/vct/vctv/reg_ebi.h
new file mode 100644
index 0000000..edccea0
--- /dev/null
+++ b/board/micronas/vct/vctv/reg_ebi.h
@@ -0,0 +1,277 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _REG_EBI_PLATINUMAVC_H_
+#define _REG_EBI_PLATINUMAVC_H_
+
+#define EBI_BASE 0x00014000
+
+/* Relative offsets of the register adresses */
+
+#define EBI_CPU_IO_ACCS_OFFS 0x00000000
+#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
+#define EBI_IO_ACCS_DATA_OFFS 0x00000004
+#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
+#define EBI_CPU_IO_ACCS2_OFFS 0x00000008
+#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS)
+#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C
+#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS)
+#define EBI_CTRL_OFFS 0x00000010
+#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
+#define EBI_IRQ_MASK_OFFS 0x00000018
+#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
+#define EBI_IRQ_MASK2_OFFS 0x0000001C
+#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS)
+#define EBI_TAG1_SYS_ID_OFFS 0x00000030
+#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
+#define EBI_TAG2_SYS_ID_OFFS 0x00000040
+#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
+#define EBI_TAG3_SYS_ID_OFFS 0x00000050
+#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
+#define EBI_TAG4_SYS_ID_OFFS 0x00000060
+#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
+#define EBI_GEN_DMA_CTRL_OFFS 0x00000070
+#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
+#define EBI_STATUS_OFFS 0x00000080
+#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
+#define EBI_STATUS_DMA_CNT_OFFS 0x00000084
+#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
+#define EBI_SIG_LEVEL_OFFS 0x00000088
+#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
+#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
+#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
+#define EBI_CRC_GEN_OFFS 0x00000090
+#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS)
+#define EBI_EXT_ADDR_OFFS 0x000000A0
+#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
+#define EBI_IRQ_STATUS_OFFS 0x000000B0
+#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
+#define EBI_IRQ_STATUS2_OFFS 0x000000B4
+#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS)
+#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0
+#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS)
+#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4
+#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS)
+#define EBI_ECC0_OFFS 0x000000D0
+#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS)
+#define EBI_ECC1_OFFS 0x000000D4
+#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS)
+#define EBI_ECC2_OFFS 0x000000D8
+#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS)
+#define EBI_ECC3_OFFS 0x000000DC
+#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS)
+#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
+#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV1_EXT_ACC_OFFS 0x00000104
+#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
+#define EBI_DEV1_CONFIG1_OFFS 0x00000108
+#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
+#define EBI_DEV1_CONFIG2_OFFS 0x0000010C
+#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
+#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
+#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
+#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
+#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
+#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
+#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
+#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
+#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
+#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120
+#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
+#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
+#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
+#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
+#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
+#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
+#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
+#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
+#define EBI_DEV1_TIM_EXT_OFFS 0x00000134
+#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
+#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
+#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
+#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
+#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
+#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
+#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148
+#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS)
+#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C
+#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS)
+#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
+#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
+#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
+#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV2_EXT_ACC_OFFS 0x00000204
+#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
+#define EBI_DEV2_CONFIG1_OFFS 0x00000208
+#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
+#define EBI_DEV2_CONFIG2_OFFS 0x0000020C
+#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
+#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
+#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
+#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
+#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
+#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
+#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
+#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
+#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
+#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220
+#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
+#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
+#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
+#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
+#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
+#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
+#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
+#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
+#define EBI_DEV2_TIM_EXT_OFFS 0x00000234
+#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
+#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
+#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
+#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
+#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
+#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
+#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248
+#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS)
+#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C
+#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS)
+#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
+#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
+#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
+#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV3_EXT_ACC_OFFS 0x00000304
+#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
+#define EBI_DEV3_CONFIG1_OFFS 0x00000308
+#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
+#define EBI_DEV3_CONFIG2_OFFS 0x0000030C
+#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
+#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
+#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
+#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
+#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
+#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
+#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
+#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
+#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
+#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320
+#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
+#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
+#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
+#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
+#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
+#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
+#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
+#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
+#define EBI_DEV3_TIM_EXT_OFFS 0x00000334
+#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
+#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
+#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
+#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
+#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
+#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
+#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348
+#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS)
+#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C
+#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS)
+#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
+#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
+#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
+#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV4_EXT_ACC_OFFS 0x00000404
+#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
+#define EBI_DEV4_CONFIG1_OFFS 0x00000408
+#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
+#define EBI_DEV4_CONFIG2_OFFS 0x0000040C
+#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
+#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
+#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
+#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
+#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
+#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
+#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
+#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
+#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
+#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420
+#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
+#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
+#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
+#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
+#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
+#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
+#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
+#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
+#define EBI_DEV4_TIM_EXT_OFFS 0x00000434
+#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
+#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
+#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
+#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
+#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
+#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
+#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448
+#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS)
+#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C
+#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS)
+#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
+#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
+#define EBI_INTERLEAVE_CNT_OFFS 0x00000900
+#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS)
+#define EBI_CNT_FL_PROGR_OFFS 0x00000904
+#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
+#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
+#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
+#define EBI_CNT_WAIT_RDY_OFFS 0x00000914
+#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
+#define EBI_CNT_ACK_OFFS 0x00000918
+#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
+#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
+#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
+#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
+#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
+#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
+#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
+#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
+#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
+#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
+#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
+#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
+#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
+#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
+#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
+#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
+#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
+#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
+#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
+#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
+#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
+#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
+#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
+#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
+#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
+#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
+#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
+#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
+#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
+#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
+#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vctv/reg_gpio.h b/board/micronas/vct/vctv/reg_gpio.h
new file mode 100644
index 0000000..6ff0ce4
--- /dev/null
+++ b/board/micronas/vct/vctv/reg_gpio.h
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define GPIO1_BASE 0x00044000
+#define GPIO2_BASE 0x00048000
+
+/* Instances */
+#define GPIO_INSTANCES 2
+
+/* Relative offsets of the register adresses */
+#define GPIO_SWPORTA_DR_OFFS 0x00000000
+#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS)
+#define GPIO_SWPORTA_DDR_OFFS 0x00000004
+#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS)
+#define GPIO_EXT_PORTA_OFFS 0x00000050
+#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS)
diff --git a/board/micronas/vct/vctv/reg_wdt.h b/board/micronas/vct/vctv/reg_wdt.h
new file mode 100644
index 0000000..48e8aeb
--- /dev/null
+++ b/board/micronas/vct/vctv/reg_wdt.h
@@ -0,0 +1,11 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define WDT_BASE 0x00040000
+#define WDT_CR_OFFS 0x00000000
+#define WDT_CR(base) ((base) + WDT_CR_OFFS)
+#define WDT_TORR_OFFS 0x00000004
+#define WDT_TORR(base) ((base) + WDT_TORR_OFFS)
diff --git a/board/mimc/mimc200/Kconfig b/board/mimc/mimc200/Kconfig
new file mode 100644
index 0000000..18736d7
--- /dev/null
+++ b/board/mimc/mimc200/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MIMC200
+
+config SYS_BOARD
+ default "mimc200"
+
+config SYS_VENDOR
+ default "mimc"
+
+config SYS_SOC
+ default "at32ap700x"
+
+config SYS_CONFIG_NAME
+ default "mimc200"
+
+endif
diff --git a/board/mimc/mimc200/MAINTAINERS b/board/mimc/mimc200/MAINTAINERS
new file mode 100644
index 0000000..6cb51dd
--- /dev/null
+++ b/board/mimc/mimc200/MAINTAINERS
@@ -0,0 +1,6 @@
+MIMC200 BOARD
+M: Mark Jackson <mpfj@mimc.co.uk>
+S: Maintained
+F: board/mimc/mimc200/
+F: include/configs/mimc200.h
+F: configs/mimc200_defconfig
diff --git a/board/mimc/mimc200/Makefile b/board/mimc/mimc200/Makefile
new file mode 100644
index 0000000..5c30c0d
--- /dev/null
+++ b/board/mimc/mimc200/Makefile
@@ -0,0 +1,6 @@
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := mimc200.o
diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c
new file mode 100644
index 0000000..2ad53ec
--- /dev/null
+++ b/board/mimc/mimc200/mimc200.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+#include <atmel_lcdc.h>
+#include <lcd.h>
+
+#include "../../../arch/avr32/cpu/hsmc3.h"
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = EBI_SRAM_CS2_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SRAM_CS2_SIZE >> PAGE_SHIFT,
+ .phys = (EBI_SRAM_CS2_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
+#if defined(CONFIG_LCD)
+/* 480x272x16 @ 72 Hz */
+vidinfo_t panel_info = {
+ .vl_col = 480, /* Number of columns */
+ .vl_row = 272, /* Number of rows */
+ .vl_clk = 5000000, /* pixel clock in ps */
+ .vl_sync = ATMEL_LCDC_INVCLK_INVERTED |
+ ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = LCD_COLOR16, /* Bits per pixel, BPP = 2^n */
+ .vl_tft = 1, /* 0 = passive, 1 = TFT */
+ .vl_hsync_len = 42, /* Length of horizontal sync */
+ .vl_left_margin = 1, /* Time from sync to picture */
+ .vl_right_margin = 1, /* Time from picture to sync */
+ .vl_vsync_len = 1, /* Length of vertical sync */
+ .vl_upper_margin = 12, /* Time from sync to picture */
+ .vl_lower_margin = 1, /* Time from picture to sync */
+ .mmio = LCDC_BASE, /* Memory mapped registers */
+};
+
+void lcd_enable(void)
+{
+}
+
+void lcd_disable(void)
+{
+}
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct sdram_config sdram_config = {
+ .data_bits = SDRAM_DATA_16BIT,
+ .row_bits = 13,
+ .col_bits = 9,
+ .bank_bits = 2,
+ .cas = 3,
+ .twr = 2,
+ .trc = 6,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 6,
+ .txsr = 6,
+ /* 15.6 us */
+ .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
+};
+
+int board_early_init_f(void)
+{
+ /* Enable SDRAM in the EBI mux */
+ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+ /* Enable 26 address bits and NCS2 */
+ portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+ /* de-assert "force sys reset" pin */
+ portmux_select_gpio(PORTMUX_PORT_D, 1 << 15,
+ PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
+
+ /* init custom i/o */
+ /* cpu type inputs */
+ portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23),
+ PORTMUX_DIR_INPUT);
+ /* main board type inputs */
+ portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29),
+ PORTMUX_DIR_INPUT);
+ /* DEBUG input (use weak pullup) */
+ portmux_select_gpio(PORTMUX_PORT_E, 1 << 21,
+ PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
+
+ /* are we suppressing the console ? */
+ if (gpio_get_value(GPIO_PIN_PE(21)) == 1)
+ gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE);
+
+ /* reset phys */
+ portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT);
+ portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
+ PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
+
+ udelay(5000);
+
+ /* release phys reset */
+ gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */
+
+ /* setup Data Flash chip select (NCS2) */
+ hsmc3_writel(MODE2, 0x20121003);
+ hsmc3_writel(CYCLE2, 0x000a0009);
+ hsmc3_writel(PULSE2, 0x0a060806);
+ hsmc3_writel(SETUP2, 0x00030102);
+
+ /* setup FRAM chip select (NCS3) */
+ hsmc3_writel(MODE3, 0x10120001);
+ hsmc3_writel(CYCLE3, 0x001e001d);
+ hsmc3_writel(PULSE3, 0x08040704);
+ hsmc3_writel(SETUP3, 0x02050204);
+
+#if defined(CONFIG_MACB)
+ /* init macb0 pins */
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+ portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+
+#if defined(CONFIG_MMC)
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+
+#if defined(CONFIG_LCD)
+ portmux_enable_lcdc(1);
+#endif
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ unsigned long expected_size;
+ unsigned long actual_size;
+ void *sdram_base;
+
+ sdram_base = uncached(EBI_SDRAM_BASE);
+
+ expected_size = sdram_init(sdram_base, &sdram_config);
+ actual_size = get_ram_size(sdram_base, expected_size);
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return actual_size;
+}
+
+int board_early_init_r(void)
+{
+ gd->bd->bi_phy_id[0] = 0x01;
+ gd->bd->bi_phy_id[1] = 0x03;
+ return 0;
+}
+
+int board_postclk_init(void)
+{
+ /* Use GCLK0 as 10MHz output */
+ gclk_enable_output(0, PORTMUX_DRIVE_LOW);
+ gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
+ return 0;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return (bus == 0) && (cs == 0);
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+ macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+ macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
+
+ return 0;
+}
+#endif
diff --git a/board/miromico/hammerhead/Kconfig b/board/miromico/hammerhead/Kconfig
new file mode 100644
index 0000000..1f09ef7
--- /dev/null
+++ b/board/miromico/hammerhead/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HAMMERHEAD
+
+config SYS_BOARD
+ default "hammerhead"
+
+config SYS_VENDOR
+ default "miromico"
+
+config SYS_SOC
+ default "at32ap700x"
+
+config SYS_CONFIG_NAME
+ default "hammerhead"
+
+endif
diff --git a/board/miromico/hammerhead/MAINTAINERS b/board/miromico/hammerhead/MAINTAINERS
new file mode 100644
index 0000000..a87ceee
--- /dev/null
+++ b/board/miromico/hammerhead/MAINTAINERS
@@ -0,0 +1,6 @@
+HAMMERHEAD BOARD
+M: Alex Raimondi <alex.raimondi@miromico.ch>
+S: Maintained
+F: board/miromico/hammerhead/
+F: include/configs/hammerhead.h
+F: configs/hammerhead_defconfig
diff --git a/board/miromico/hammerhead/Makefile b/board/miromico/hammerhead/Makefile
new file mode 100644
index 0000000..638a9df
--- /dev/null
+++ b/board/miromico/hammerhead/Makefile
@@ -0,0 +1,6 @@
+#
+# Copyright (C) 2008 Miromico AG
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := hammerhead.o
diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c
new file mode 100644
index 0000000..d82fee7
--- /dev/null
+++ b/board/miromico/hammerhead/hammerhead.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2008 Miromico AG
+ *
+ * Mostly copied form atmel ATNGW100 sources
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
+static const struct sdram_config sdram_config = {
+ .data_bits = SDRAM_DATA_32BIT,
+ .row_bits = 13,
+ .col_bits = 9,
+ .bank_bits = 2,
+ .cas = 3,
+ .twr = 2,
+ .trc = 7,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 5,
+ .txsr = 5,
+ /* 7.81 us */
+ .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
+ bis->bi_phy_id[0]);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ /* Enable SDRAM in the EBI mux */
+ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+ portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+#if defined(CONFIG_MACB)
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+#if defined(CONFIG_MMC)
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ unsigned long expected_size;
+ unsigned long actual_size;
+ void *sdram_base;
+
+ sdram_base = uncached(EBI_SDRAM_BASE);
+
+ expected_size = sdram_init(sdram_base, &sdram_config);
+ actual_size = get_ram_size(sdram_base, expected_size);
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return actual_size;
+}
+
+int board_early_init_r(void)
+{
+ gd->bd->bi_phy_id[0] = 0x01;
+ return 0;
+}
+
+int board_postclk_init(void)
+{
+ /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
+ gclk_enable_output(3, PORTMUX_DRIVE_LOW);
+ gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
+ return 0;
+}
diff --git a/board/mosaixtech/icon/Kconfig b/board/mosaixtech/icon/Kconfig
new file mode 100644
index 0000000..3145a06
--- /dev/null
+++ b/board/mosaixtech/icon/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ICON
+
+config SYS_BOARD
+ default "icon"
+
+config SYS_VENDOR
+ default "mosaixtech"
+
+config SYS_CONFIG_NAME
+ default "icon"
+
+endif
diff --git a/board/mosaixtech/icon/MAINTAINERS b/board/mosaixtech/icon/MAINTAINERS
new file mode 100644
index 0000000..f3af072
--- /dev/null
+++ b/board/mosaixtech/icon/MAINTAINERS
@@ -0,0 +1,6 @@
+ICON BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/mosaixtech/icon/
+F: include/configs/icon.h
+F: configs/icon_defconfig
diff --git a/board/mosaixtech/icon/Makefile b/board/mosaixtech/icon/Makefile
new file mode 100644
index 0000000..d554a8b
--- /dev/null
+++ b/board/mosaixtech/icon/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2009-2010
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := icon.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+extra-y += init.o
diff --git a/board/mosaixtech/icon/chip_config.c b/board/mosaixtech/icon/chip_config.c
new file mode 100644
index 0000000..3c5706f
--- /dev/null
+++ b/board/mosaixtech/icon/chip_config.c
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2009-2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "400-133", "CPU: 400 PLB: 133 OPB: 66 EBC: 66",
+ { 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "500-166", "CPU: 500 PLB: 166 OPB: 83 EBC: 83",
+ { 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "533-133", "CPU: 533 PLB: 133 OPB: 66 EBC: 66",
+ { 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "667-133", "CPU: 667 PLB: 133 OPB: 66 EBC: 66",
+ { 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "667-166", "CPU: 667 PLB: 166 OPB: 83 EBC: 83",
+ { 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 }
+ },
+ {
+ "800-160", "CPU: 800 PLB: 160 OPB: 53 EBC: 17",
+ { 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/mosaixtech/icon/config.mk b/board/mosaixtech/icon/config.mk
new file mode 100644
index 0000000..b689fd0
--- /dev/null
+++ b/board/mosaixtech/icon/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2009-2010
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/mosaixtech/icon/icon.c b/board/mosaixtech/icon/icon.c
new file mode 100644
index 0000000..e3fb1e6
--- /dev/null
+++ b/board/mosaixtech/icon/icon.c
@@ -0,0 +1,372 @@
+/*
+ * (C) Copyright 2009-2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/4xx_pcie.h>
+#include <asm/errno.h>
+#include <asm/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ unsigned long mfr;
+
+ /*
+ * Interrupt controller setup for the ICON 440SPe board.
+ *
+ *--------------------------------------------------------------------
+ * IRQ | Source | Pol. | Sensi.| Crit.
+ *--------+-----------------------------------+-------+-------+-------
+ * IRQ 00 | UART0 | High | Level | Non
+ * IRQ 01 | UART1 | High | Level | Non
+ * IRQ 02 | IIC0 | High | Level | Non
+ * IRQ 03 | IIC1 | High | Level | Non
+ * IRQ 04 | PCI0X0 MSG IN | High | Level | Non
+ * IRQ 05 | PCI0X0 CMD Write | High | Level | Non
+ * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non
+ * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non
+ * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non
+ * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non
+ * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non
+ * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit
+ * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non
+ * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non
+ * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non
+ * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non
+ * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non
+ * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit
+ * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non
+ * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non
+ * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non
+ * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non
+ * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non
+ * IRQ 23 | I2O Inbound Doorbell | High | Level | Non
+ * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non
+ * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non
+ * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non
+ * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non
+ * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non
+ * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non
+ * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non
+ * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit.
+ *--------------------------------------------------------------------
+ * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non
+ * IRQ 33 | MAL Serr | High | Level | Non
+ * IRQ 34 | MAL Txde | High | Level | Non
+ * IRQ 35 | MAL Rxde | High | Level | Non
+ * IRQ 36 | DMC CE or DMC UE | High | Level | Non
+ * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non
+ * IRQ 38 | MAL TX EOB | High | Level | Non
+ * IRQ 39 | MAL RX EOB | High | Level | Non
+ * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non
+ * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non
+ * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non
+ * IRQ 43 | L2 Cache | Risin | Edge | Non
+ * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non
+ * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non
+ * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non
+ * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non
+ * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non
+ * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non
+ * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non
+ * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non
+ * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non
+ * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non
+ * IRQ 54 | DMA Error | High | Level | Non
+ * IRQ 55 | DMA I2O Error | High | Level | Non
+ * IRQ 56 | Serial ROM | High | Level | Non
+ * IRQ 57 | PCIX0 Error | High | Edge | Non
+ * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non
+ * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non
+ * IRQ 60 | EMAC0 Interrupt | High | Level | Non
+ * IRQ 61 | EMAC0 Wake-up | High | Level | Non
+ * IRQ 62 | Reserved | High | Level | Non
+ * IRQ 63 | XOR | High | Level | Non
+ *--------------------------------------------------------------------
+ * IRQ 64 | PE0 AL | High | Level | Non
+ * IRQ 65 | PE0 VPD Access | Risin | Edge | Non
+ * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non
+ * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non
+ * IRQ 68 | PE0 TCR | High | Level | Non
+ * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non
+ * IRQ 70 | PE0 DCR Error | High | Level | Non
+ * IRQ 71 | Reserved | N/A | N/A | Non
+ * IRQ 72 | PE1 AL | High | Level | Non
+ * IRQ 73 | PE1 VPD Access | Risin | Edge | Non
+ * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non
+ * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non
+ * IRQ 76 | PE1 TCR | High | Level | Non
+ * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non
+ * IRQ 78 | PE1 DCR Error | High | Level | Non
+ * IRQ 79 | Reserved | N/A | N/A | Non
+ * IRQ 80 | PE2 AL | High | Level | Non
+ * IRQ 81 | PE2 VPD Access | Risin | Edge | Non
+ * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non
+ * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non
+ * IRQ 84 | PE2 TCR | High | Level | Non
+ * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non
+ * IRQ 86 | PE2 DCR Error | High | Level | Non
+ * IRQ 87 | Reserved | N/A | N/A | Non
+ * IRQ 88 | External IRQ(5) | Progr | Progr | Non
+ * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non
+ * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non
+ * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non
+ * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non
+ * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non
+ * IRQ 94 | Reserved | N/A | N/A | Non
+ * IRQ 95 | Reserved | N/A | N/A | Non
+ *--------------------------------------------------------------------
+ * IRQ 96 | PE0 INTA | High | Level | Non
+ * IRQ 97 | PE0 INTB | High | Level | Non
+ * IRQ 98 | PE0 INTC | High | Level | Non
+ * IRQ 99 | PE0 INTD | High | Level | Non
+ * IRQ 100| PE1 INTA | High | Level | Non
+ * IRQ 101| PE1 INTB | High | Level | Non
+ * IRQ 102| PE1 INTC | High | Level | Non
+ * IRQ 103| PE1 INTD | High | Level | Non
+ * IRQ 104| PE2 INTA | High | Level | Non
+ * IRQ 105| PE2 INTB | High | Level | Non
+ * IRQ 106| PE2 INTC | High | Level | Non
+ * IRQ 107| PE2 INTD | Risin | Edge | Non
+ * IRQ 108| PCI Express MSI Level 4 | Risin | Edge | Non
+ * IRQ 109| PCI Express MSI Level 5 | Risin | Edge | Non
+ * IRQ 110| PCI Express MSI Level 6 | Risin | Edge | Non
+ * IRQ 111| PCI Express MSI Level 7 | Risin | Edge | Non
+ * IRQ 116| PCI Express MSI Level 12 | Risin | Edge | Non
+ * IRQ 112| PCI Express MSI Level 8 | Risin | Edge | Non
+ * IRQ 113| PCI Express MSI Level 9 | Risin | Edge | Non
+ * IRQ 114| PCI Express MSI Level 10 | Risin | Edge | Non
+ * IRQ 115| PCI Express MSI Level 11 | Risin | Edge | Non
+ * IRQ 117| PCI Express MSI Level 13 | Risin | Edge | Non
+ * IRQ 118| PCI Express MSI Level 14 | Risin | Edge | Non
+ * IRQ 119| PCI Express MSI Level 15 | Risin | Edge | Non
+ * IRQ 120| PCI Express MSI Level 16 | Risin | Edge | Non
+ * IRQ 121| PCI Express MSI Level 17 | Risin | Edge | Non
+ * IRQ 122| PCI Express MSI Level 18 | Risin | Edge | Non
+ * IRQ 123| PCI Express MSI Level 19 | Risin | Edge | Non
+ * IRQ 124| PCI Express MSI Level 20 | Risin | Edge | Non
+ * IRQ 125| PCI Express MSI Level 21 | Risin | Edge | Non
+ * IRQ 126| PCI Express MSI Level 22 | Risin | Edge | Non
+ * IRQ 127| PCI Express MSI Level 23 | Risin | Edge | Non
+ */
+
+ /*
+ * Put UICs in PowerPC 440SPe mode.
+ * Initialise UIC registers. Clear all interrupts. Disable all
+ * interrupts. Set critical interrupt values. Set interrupt polarities.
+ * Set interrupt trigger levels. Make bit 0 High priority. Clear all
+ * interrupts again.
+ */
+ mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */
+ mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical IRQs */
+ mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/
+ mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
+ mtdcr(UIC3SR, 0x00000000); /* clear all interrupts*/
+ mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts*/
+
+ mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC2ER, 0x00000000); /* disable all interrupts*/
+ mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical IRQs */
+ mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/
+ mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
+ mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts*/
+ mtdcr(UIC1ER, 0x00000000); /* disable all interrupts*/
+ mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical IRQs */
+ mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */
+ mtdcr(UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/
+ mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
+ mtdcr(UIC1SR, 0x00000000); /* clear all interrupts*/
+ mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts*/
+
+ mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr(UIC0ER, 0x00000000); /* disable all int. excepted cascade */
+ mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical IRQs */
+ mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/
+ mtdcr(UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */
+ mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest prio */
+ mtdcr(UIC0SR, 0x00000000); /* clear all interrupts*/
+ mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts*/
+
+ mfsdr(SDR0_MFR, mfr);
+ mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
+ mtsdr(SDR0_MFR, mfr);
+
+ mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
+
+ out_be32((void *)GPIO0_OR, CONFIG_SYS_GPIO_OR);
+ out_be32((void *)GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
+ out_be32((void *)GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ /*
+ * ICON has 64MBytes of NOR FLASH (Spansion 29GL512), but the
+ * boot EBC mapping only supports a maximum of 16MBytes
+ * (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the FLASH has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfc00.0000 -> 4.ec00.0000
+ */
+
+ /* Remap the NOR FLASH to 0xec00.0000 ... 0xefff.ffff */
+ mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
+
+ /* Remove TLB entry of boot EBC mapping */
+ remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
+
+ /* Add TLB entry for 0xfc00.0000 -> 0x4.ec00.0000 */
+ program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
+
+ /*
+ * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
+ * 0xfc00.0000 is possible
+ */
+
+ /*
+ * Clear potential errors resulting from auto-calibration.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: ICON");
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ *
+ * Tested successfully with the following SODIMM:
+ * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
+ *
+ * Tests with Micron MT4HTF6464HZ-667H1 showed problems in "cold" state,
+ * directly after power-up. Only after running for more than 10 minutes
+ * real stable auto-calibration windows could be found.
+ */
+u32 ddr_wrdtr(u32 default_val)
+{
+ return SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV;
+}
+
+u32 ddr_clktr(u32 default_val)
+{
+ return SDRAM_CLKTR_CLKP_180_DEG_ADV;
+}
+
+/*
+ * Override the weak default implementation and return the
+ * last PCIe slot number (max number - 1).
+ */
+int board_pcie_last(void)
+{
+ /* Only 2 PCIe ports used on ICON, so the last one is 1 */
+ return 1;
+}
+
+/*
+ * Video
+ */
+#ifdef CONFIG_VIDEO_SM501
+#include <sm501.h>
+
+#define DISPLAY_WIDTH 640
+#define DISPLAY_HEIGHT 480
+
+static const SMI_REGS sm502_init_regs[] = {
+ {0x00004, 0x0},
+ {0x00040, 0x00021847},
+ {0x00044, 0x091a0a01}, /* 24 MHz pixclk */
+ {0x00054, 0x0},
+ {0x00048, 0x00021847},
+ {0x0004C, 0x091a0a01},
+ {0x00054, 0x1},
+ {0x80004, 0xc428bb17},
+ {0x8000C, 0x00000000},
+ {0x80010, 0x0a000a00},
+ {0x80014, 0x02800000},
+ {0x80018, 0x01e00000},
+ {0x8001C, 0x00000000},
+ {0x80020, 0x01e00280},
+ {0x80024, 0x02fa027f},
+ {0x80028, 0x004a0280},
+ {0x8002C, 0x020c01df},
+ {0x80030, 0x000201e7},
+ {0x80200, 0x00010000},
+ {0x00008, 0x20000000}, /* gpio29 is pwm0, LED_PWM */
+ {0x0000C, 0x3f000000}, /* gpio56 - gpio61 as flat panel data pins */
+ {0x10020, 0x25725728}, /* 20 kHz pwm0, 50 % duty cycle, disabled */
+ {0x80000, 0x0f010106}, /* vsync & hsync pos, disp on */
+ {0, 0}
+};
+
+/*
+ * Return a pointer to the register initialization table.
+ */
+const SMI_REGS *board_get_regs(void)
+{
+ return sm502_init_regs;
+}
+
+int board_get_width(void)
+{
+ return DISPLAY_WIDTH;
+}
+
+int board_get_height(void)
+{
+ return DISPLAY_HEIGHT;
+}
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str(int line_number, char *info)
+{
+ if (line_number == 1)
+ strcpy(info, " Board: ICON");
+ else
+ info[0] = '\0';
+}
+#endif
+
+#endif /* CONFIG_VIDEO_SM501 */
diff --git a/board/mosaixtech/icon/init.S b/board/mosaixtech/icon/init.S
new file mode 100644
index 0000000..c28a3a3
--- /dev/null
+++ b/board/mosaixtech/icon/init.S
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2009-2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ */
+
+ .section .bootpg,"ax"
+
+ .globl tlbtab
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+ * use the speed up boot process. It is patched after relocation to
+ * enable SA_I.
+ */
+ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
+ 4, AC_RWX | SA_G) /* TLB 0 */
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4,
+ AC_RWX | SA_I)
+
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4,
+ AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K,
+ CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H,
+ AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD,
+ AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD,
+ AC_RW | SA_IG)
+ tlbtab_end
diff --git a/board/motionpro/Kconfig b/board/motionpro/Kconfig
new file mode 100644
index 0000000..f624f6c
--- /dev/null
+++ b/board/motionpro/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_MOTIONPRO
+
+config SYS_BOARD
+ default "motionpro"
+
+config SYS_CONFIG_NAME
+ default "motionpro"
+
+endif
diff --git a/board/motionpro/MAINTAINERS b/board/motionpro/MAINTAINERS
new file mode 100644
index 0000000..2f8b5cb
--- /dev/null
+++ b/board/motionpro/MAINTAINERS
@@ -0,0 +1,6 @@
+MOTIONPRO BOARD
+#M: -
+S: Maintained
+F: board/motionpro/
+F: include/configs/motionpro.h
+F: configs/motionpro_defconfig
diff --git a/board/motionpro/Makefile b/board/motionpro/Makefile
new file mode 100644
index 0000000..898a384
--- /dev/null
+++ b/board/motionpro/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := motionpro.o
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
new file mode 100644
index 0000000..4d0ebaa
--- /dev/null
+++ b/board/motionpro/motionpro.c
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * modified for Promess PRO - by Andy Joseph, andy@promessdev.com
+ * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
+ * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
+ * Also changed the refresh for 100MHz operation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <miiphy.h>
+#include <libfdt.h>
+
+#if defined(CONFIG_STATUS_LED)
+#include <status_led.h>
+#endif /* CONFIG_STATUS_LED */
+
+/* Kollmorgen DPR initialization data */
+struct init_elem {
+ unsigned long addr;
+ unsigned len;
+ char *data;
+ } init_seq[] = {
+ {0x500003F2, 2, "\x86\x00"}, /* HW parameter */
+ {0x500003F0, 2, "\x00\x00"},
+ {0x500003EC, 4, "\x00\x80\xc1\x52"}, /* Magic word */
+ };
+
+/*
+ * Initialize Kollmorgen DPR
+ */
+static void kollmorgen_init(void)
+{
+ unsigned i, j;
+ vu_char *p;
+
+ for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) {
+ p = (vu_char *)init_seq[i].addr;
+ for (j = 0; j < init_seq[i].len; ++j)
+ *(p + j) = *(init_seq[i].data + j);
+ }
+
+ printf("DPR: Kollmorgen DPR initialized\n");
+}
+
+
+/*
+ * Early board initalization.
+ */
+int board_early_init_r(void)
+{
+ /* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */
+ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);
+ *(vu_long *)MPC5XXX_ADDECR |= (1 << 16);
+
+ /* Initialize Kollmorgen DPR */
+ kollmorgen_init();
+
+ return 0;
+}
+
+
+/*
+ * Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(),
+ * PHY goes into FX mode. To take it out of the FX mode and switch into
+ * desired TX operation, one needs to clear the FX_SEL bit of Mode Control
+ * Register.
+ */
+void reset_phy(void)
+{
+ unsigned short mode_control;
+
+ miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control);
+ miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15,
+ mode_control & 0xfffe);
+ return;
+}
+
+#ifndef CONFIG_SYS_RAMBOOT
+/*
+ * Helper function to initialize SDRAM controller.
+ */
+static void sdram_start(int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
+ hi_addr_bit;
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+ hi_addr_bit;
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+ hi_addr_bit;
+
+ /* auto refresh, second time */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+ hi_addr_bit;
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+}
+#endif /* !CONFIG_SYS_RAMBOOT */
+
+
+/*
+ * Initalize SDRAM - configure SDRAM controller, detect memory size.
+ */
+phys_size_t initdram(int board_type)
+{
+ ulong dramsize = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* According to AN3221 (MPC5200B SDRAM Initialization and
+ * Configuration), the SDelay register must be written a value of
+ * 0x00000004 as the first step of the SDRAM contorller configuration.
+ */
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+
+ /* configure SDRAM start/end for detection */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+ __builtin_ffs(dramsize >> 20) - 1;
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ }
+
+ /* let SDRAM CS1 start right after CS0 and disable it */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;
+
+#else /* !CONFIG_SYS_RAMBOOT */
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13)
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ else
+ dramsize = 0;
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ /* return total ram size */
+ return dramsize;
+}
+
+
+int checkboard(void)
+{
+ uchar rev = *(vu_char *)CPLD_REV_REGISTER;
+ printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
+ return 0;
+}
+
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+
+#if defined(CONFIG_STATUS_LED)
+void __led_init(led_id_t regaddr, int state)
+{
+ *((vu_long *) regaddr) |= ENABLE_GPIO_OUT;
+
+ if (state == STATUS_LED_ON)
+ *((vu_long *) regaddr) |= LED_ON;
+ else
+ *((vu_long *) regaddr) &= ~LED_ON;
+}
+
+void __led_set(led_id_t regaddr, int state)
+{
+ if (state == STATUS_LED_ON)
+ *((vu_long *) regaddr) |= LED_ON;
+ else
+ *((vu_long *) regaddr) &= ~LED_ON;
+}
+
+void __led_toggle(led_id_t regaddr)
+{
+ *((vu_long *) regaddr) ^= LED_ON;
+}
+#endif /* CONFIG_STATUS_LED */
diff --git a/board/mpc8308_p1m/Kconfig b/board/mpc8308_p1m/Kconfig
new file mode 100644
index 0000000..b7e39da
--- /dev/null
+++ b/board/mpc8308_p1m/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_MPC8308_P1M
+
+config SYS_BOARD
+ default "mpc8308_p1m"
+
+config SYS_CONFIG_NAME
+ default "mpc8308_p1m"
+
+endif
diff --git a/board/mpc8308_p1m/MAINTAINERS b/board/mpc8308_p1m/MAINTAINERS
new file mode 100644
index 0000000..80d8de7
--- /dev/null
+++ b/board/mpc8308_p1m/MAINTAINERS
@@ -0,0 +1,6 @@
+MPC8308_P1M BOARD
+M: Ilya Yanok <yanok@emcraft.com>
+S: Maintained
+F: board/mpc8308_p1m/
+F: include/configs/mpc8308_p1m.h
+F: configs/mpc8308_p1m_defconfig
diff --git a/board/mpc8308_p1m/Makefile b/board/mpc8308_p1m/Makefile
new file mode 100644
index 0000000..fb8ca3a
--- /dev/null
+++ b/board/mpc8308_p1m/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010
+# Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mpc8308_p1m.o sdram.o
diff --git a/board/mpc8308_p1m/mpc8308_p1m.c b/board/mpc8308_p1m/mpc8308_p1m.c
new file mode 100644
index 0000000..688cc12
--- /dev/null
+++ b/board/mpc8308_p1m/mpc8308_p1m.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: MPC8308 P1M\n");
+
+ return 0;
+}
+
+static struct pci_region pcie_regions_0[] = {
+ {
+ .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+ .size = CONFIG_SYS_PCIE1_MEM_SIZE,
+ .flags = PCI_REGION_MEM,
+ },
+ {
+ .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+ .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+ .size = CONFIG_SYS_PCIE1_IO_SIZE,
+ .flags = PCI_REGION_IO,
+ },
+};
+
+void pci_init_board(void)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+ law83xx_t *pcie_law = sysconf->pcielaw;
+ struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+ /* Deassert the resets in the control register */
+ out_be32(&sysconf->pecr1, 0xE0008000);
+ udelay(2000);
+
+ /* Configure PCI Express Local Access Windows */
+ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+ out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ mpc83xx_pcie_init(1, pcie_reg);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_dr_usb(blob, bd);
+
+ return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, num_if = 0;
+
+ /* Initialize TSECs first */
+ rv = cpu_eth_init(bis);
+ if (rv >= 0)
+ num_if += rv;
+ else
+ printf("ERROR: failed to initialize TSECs.\n");
+
+ rv = pci_eth_init(bis);
+ if (rv >= 0)
+ num_if += rv;
+ else
+ printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+ return num_if;
+}
diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c
new file mode 100644
index 0000000..da36f63
--- /dev/null
+++ b/board/mpc8308_p1m/sdram.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * This files is mostly identical to the original from
+ * board/freescale/mpc8308rdb/sdram.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+ u32 msize_log2 = __ilog2(msize);
+
+ out_be32(&im->sysconf.ddrlaw[0].bar,
+ CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000);
+ out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+ out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+ out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+ out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+ /* Currently we use only one CS, so disable the other bank. */
+ out_be32(&im->ddr.cs_config[1], 0);
+
+ out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+ out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+ out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+ out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+ out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+ out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+ out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+ sync();
+
+ /* enable DDR controller */
+ setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+ sync();
+
+ return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+}
+
+phys_size_t initdram(int board_type)
+{
+ immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize;
+
+ if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM */
+ msize = fixed_sdram();
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize;
+}
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
new file mode 100644
index 0000000..6b96bd5
--- /dev/null
+++ b/board/mpl/common/common_util.c
@@ -0,0 +1,757 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <video_fb.h>
+#include "common_util.h"
+#include <asm/processor.h>
+#include <asm/byteorder.h>
+#include <i2c.h>
+#include <pci.h>
+#include <malloc.h>
+#include <bzlib.h>
+
+#ifdef CONFIG_PIP405
+#include "../pip405/pip405.h"
+#include <asm/4xx_pci.h>
+#endif
+#ifdef CONFIG_MIP405
+#include "../mip405/mip405.h"
+#include <asm/4xx_pci.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_PATI)
+#define FIRM_START 0xFFF00000
+#endif
+
+extern int mem_test(ulong start, ulong ramsize, int quiet);
+
+#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */
+#define IMAGE_SIZE CONFIG_SYS_MONITOR_LEN /* ugly, but it works for now */
+
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
+/*-----------------------------------------------------------------------
+ * On PIP/MIP405 we have 3 (4) possible boot mode
+ *
+ * - Boot from Flash (Flash CS = CS0, MPS CS = CS1)
+ * - Boot from MPS (Flash CS = CS1, MPS CS = CS0)
+ * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1)
+ * - Boot from PCI with MPS map (Flash CS = CS1, MPS CS = CS0)
+ * The flash init is the first board specific routine which is called
+ * after code relocation (running from SDRAM)
+ * The first thing we do is to map the Flash CS to the Flash area and
+ * the MPS CS to the MPS area. Since the flash size is unknown at this
+ * point, we use the max flash size and the lowest flash address as base.
+ *
+ * After flash detection we adjust the size of the CS area accordingly.
+ * update_flash_size() will fix in wrong values in the flash_info structure,
+ * misc_init_r() will fix the values in the board info structure
+ */
+int get_boot_mode(void)
+{
+ unsigned long pbcr;
+ int res = 0;
+ pbcr = mfdcr(CPC0_PSR);
+ if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
+ /* boot via MPS or MPS mapping */
+ res = BOOT_MPS;
+ if (pbcr & PSR_ROM_LOC)
+ /* boot via PCI.. */
+ res |= BOOT_PCI;
+ return res;
+}
+
+/* Map the flash high (in boot area)
+ This code can only be executed from SDRAM (after relocation).
+*/
+void setup_cs_reloc(void)
+{
+ int mode;
+ /*
+ * since we are relocated, we can set-up the CS finaly
+ * but first of all, switch off PCI mapping (in case it
+ * was a PCI boot)
+ */
+ out32r(PMM0MA, 0L);
+ /* get boot mode */
+ mode = get_boot_mode();
+ /*
+ * we map the flash high in every case
+ * first find out to which CS the flash is attached to
+ */
+ if (mode & BOOT_MPS) {
+ /* map flash high on CS1 and MPS on CS0 */
+ mtdcr(EBC0_CFGADDR, PB0AP);
+ mtdcr(EBC0_CFGDATA, MPS_AP);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ mtdcr(EBC0_CFGDATA, MPS_CR);
+ /*
+ * we use the default values (max values) for the flash
+ * because its real size is not yet known
+ */
+ mtdcr(EBC0_CFGADDR, PB1AP);
+ mtdcr(EBC0_CFGDATA, FLASH_AP);
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ mtdcr(EBC0_CFGDATA, FLASH_CR_B);
+ } else {
+ /* map flash high on CS0 and MPS on CS1 */
+ mtdcr(EBC0_CFGADDR, PB1AP);
+ mtdcr(EBC0_CFGDATA, MPS_AP);
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ mtdcr(EBC0_CFGDATA, MPS_CR);
+ /*
+ * we use the default values (max values) for the flash
+ * because its real size is not yet known
+ */
+ mtdcr(EBC0_CFGADDR, PB0AP);
+ mtdcr(EBC0_CFGDATA, FLASH_AP);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ mtdcr(EBC0_CFGDATA, FLASH_CR_B);
+ }
+}
+#endif /* #if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) */
+
+#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
+/* adjust flash start and protection info */
+int update_flash_size(int flash_size)
+{
+ int i = 0, mode;
+ flash_info_t *info = &flash_info[0];
+ unsigned long flashcr;
+ unsigned long flash_base = (0 - flash_size) & 0xFFF00000;
+
+ if (flash_size > 128*1024*1024) {
+ printf("\n ### ERROR, wrong flash size: %X, reset board ###\n",
+ flash_size);
+ hang();
+ }
+
+ if ((flash_size >> 20) != 0)
+ i = __ilog2(flash_size >> 20);
+
+ /* set up flash CS according to the size */
+ mode = get_boot_mode();
+ if (mode & BOOT_MPS) {
+ /* flash is on CS1 */
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ flashcr = mfdcr(EBC0_CFGDATA);
+ /* we map the flash high in every case */
+ flashcr &= 0x0001FFFF; /* mask out address bits */
+ flashcr |= flash_base; /* start addr */
+ flashcr |= (i << 17); /* size addr */
+ mtdcr(EBC0_CFGADDR, PB1CR);
+ mtdcr(EBC0_CFGDATA, flashcr);
+ } else {
+ /* flash is on CS0 */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ flashcr = mfdcr(EBC0_CFGDATA);
+ /* we map the flash high in every case */
+ flashcr &= 0x0001FFFF; /* mask out address bits */
+ flashcr |= flash_base; /* start addr */
+ flashcr |= (i << 17); /* size addr */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ mtdcr(EBC0_CFGDATA, flashcr);
+ }
+
+ for (i = 0; i < info->sector_count; i++)
+ /* adjust sector start address */
+ info->start[i] = flash_base +
+ (info->start[i] - CONFIG_SYS_FLASH_BASE);
+
+ /* unprotect all sectors */
+ flash_protect(FLAG_PROTECT_CLEAR,
+ info->start[0],
+ 0xFFFFFFFF,
+ info);
+ flash_protect_default();
+ /* protect reset vector too*/
+ flash_protect(FLAG_PROTECT_SET,
+ info->start[info->sector_count-1],
+ 0xFFFFFFFF,
+ info);
+
+ return 0;
+}
+#endif
+
+static int
+mpl_prg(uchar *src, ulong size)
+{
+ ulong start;
+ flash_info_t *info = &flash_info[0];
+ int i, rc;
+#if defined(CONFIG_PATI)
+ int start_sect;
+#endif
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI)
+ char *copystr = (char *)src;
+ ulong *magic = (ulong *)src;
+#endif
+
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI)
+ if (uimage_to_cpu (magic[0]) != IH_MAGIC) {
+ puts("Bad Magic number\n");
+ return -1;
+ }
+ /* some more checks before we delete the Flash... */
+ /* Checking the ISO_STRING prevents to program a
+ * wrong Firmware Image into the flash.
+ */
+ i = 4; /* skip Magic number */
+ while (1) {
+ if (strncmp(©str[i], "MEV-", 4) == 0)
+ break;
+ if (i++ >= 0x100) {
+ puts("Firmware Image for unknown Target\n");
+ return -1;
+ }
+ }
+ /* we have the ISO STRING, check */
+ if (strncmp(©str[i], CONFIG_ISO_STRING, sizeof(CONFIG_ISO_STRING)-1) != 0) {
+ printf("Wrong Firmware Image: %s\n", ©str[i]);
+ return -1;
+ }
+#if !defined(CONFIG_PATI)
+ start = 0 - size;
+
+ /* unprotect sectors used by u-boot */
+ flash_protect(FLAG_PROTECT_CLEAR,
+ start,
+ 0xFFFFFFFF,
+ info);
+
+ /* search start sector */
+ for (i = info->sector_count-1; i > 0; i--)
+ if (start >= info->start[i])
+ break;
+
+ /* now erase flash */
+ printf("Erasing at %lx (sector %d) (start %lx)\n",
+ start,i,info->start[i]);
+ if ((rc = flash_erase (info, i, info->sector_count-1)) != 0) {
+ puts("ERROR ");
+ flash_perror(rc);
+ return (1);
+ }
+
+#else /* #if !defined(CONFIG_PATI */
+ start = FIRM_START;
+ start_sect = -1;
+
+ /* search start sector */
+ for (i = info->sector_count-1; i > 0; i--)
+ if (start >= info->start[i])
+ break;
+
+ start_sect = i;
+
+ for (i = info->sector_count-1; i > 0; i--)
+ if ((start + size) >= info->start[i])
+ break;
+
+ /* unprotect sectors used by u-boot */
+ flash_protect(FLAG_PROTECT_CLEAR,
+ start,
+ start + size,
+ info);
+
+ /* now erase flash */
+ printf ("Erasing at %lx to %lx (sector %d to %d) (%lx to %lx)\n",
+ start, start + size, start_sect, i,
+ info->start[start_sect], info->start[i]);
+ if ((rc = flash_erase (info, start_sect, i)) != 0) {
+ puts ("ERROR ");
+ flash_perror (rc);
+ return (1);
+ }
+#endif /* defined(CONFIG_PATI) */
+
+#elif defined(CONFIG_VCMA9)
+ start = 0;
+
+ /* search end sector */
+ for (i = 0; i < info->sector_count; i++)
+ if (size < info->start[i])
+ break;
+
+ flash_protect(FLAG_PROTECT_CLEAR,
+ start,
+ size,
+ info);
+
+ /* now erase flash */
+ printf("Erasing at %lx (sector %d) (start %lx)\n",
+ start,0,info->start[0]);
+ if ((rc = flash_erase (info, 0, i)) != 0) {
+ puts("ERROR ");
+ flash_perror(rc);
+ return (1);
+ }
+
+#endif
+ printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",
+ (ulong)src, size);
+ if ((rc = flash_write ((char *)src, start, size)) != 0) {
+ puts("ERROR ");
+ flash_perror(rc);
+ return (1);
+ }
+ puts("OK programming done\n");
+ return 0;
+}
+
+
+static int
+mpl_prg_image(uchar *ld_addr)
+{
+ unsigned long len;
+ uchar *data;
+ image_header_t *hdr = (image_header_t *)ld_addr;
+ int rc;
+
+#if defined(CONFIG_FIT)
+ if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
+ puts ("Non legacy image format not supported\n");
+ return -1;
+ }
+#endif
+
+ if (!image_check_magic (hdr)) {
+ puts("Bad Magic Number\n");
+ return 1;
+ }
+ image_print_contents (hdr);
+ if (!image_check_os (hdr, IH_OS_U_BOOT)) {
+ puts("No U-Boot Image\n");
+ return 1;
+ }
+ if (!image_check_type (hdr, IH_TYPE_FIRMWARE)) {
+ puts("No Firmware Image\n");
+ return 1;
+ }
+ if (!image_check_hcrc (hdr)) {
+ puts("Bad Header Checksum\n");
+ return 1;
+ }
+ puts("Verifying Checksum ... ");
+ if (!image_check_dcrc (hdr)) {
+ puts("Bad Data CRC\n");
+ return 1;
+ }
+ puts("OK\n");
+
+ data = (uchar *)image_get_data (hdr);
+ len = image_get_data_size (hdr);
+
+ if (image_get_comp (hdr) != IH_COMP_NONE) {
+ uchar *buf;
+ /* reserve space for uncompressed image */
+ if ((buf = malloc(IMAGE_SIZE)) == NULL) {
+ puts("Insufficient space for decompression\n");
+ return 1;
+ }
+
+ switch (image_get_comp (hdr)) {
+ case IH_COMP_GZIP:
+ puts("Uncompressing (GZIP) ... ");
+ rc = gunzip ((void *)(buf), IMAGE_SIZE, data, &len);
+ if (rc != 0) {
+ puts("GUNZIP ERROR\n");
+ free(buf);
+ return 1;
+ }
+ puts("OK\n");
+ break;
+#ifdef CONFIG_BZIP2
+ case IH_COMP_BZIP2:
+ puts("Uncompressing (BZIP2) ... ");
+ {
+ uint retlen = IMAGE_SIZE;
+ rc = BZ2_bzBuffToBuffDecompress ((char *)(buf), &retlen,
+ (char *)data, len, 0, 0);
+ len = retlen;
+ }
+ if (rc != BZ_OK) {
+ printf ("BUNZIP2 ERROR: %d\n", rc);
+ free(buf);
+ return 1;
+ }
+ puts("OK\n");
+ break;
+#endif
+ default:
+ printf ("Unimplemented compression type %d\n",
+ image_get_comp (hdr));
+ free(buf);
+ return 1;
+ }
+
+ rc = mpl_prg(buf, len);
+ free(buf);
+ } else {
+ rc = mpl_prg(data, len);
+ }
+
+ return(rc);
+}
+
+#if !defined(CONFIG_PATI)
+void get_backup_values(backup_t *buf)
+{
+ i2c_read(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t));
+}
+
+void set_backup_values(int overwrite)
+{
+ backup_t back;
+ int i;
+
+ get_backup_values(&back);
+ if(!overwrite) {
+ if(strncmp(back.signature,"MPL\0",4)==0) {
+ puts("Not possible to write Backup\n");
+ return;
+ }
+ }
+ memcpy(back.signature,"MPL\0",4);
+ i = getenv_f("serial#",back.serial_name,16);
+ if(i < 0) {
+ puts("Not possible to write Backup\n");
+ return;
+ }
+ back.serial_name[16]=0;
+ i = getenv_f("ethaddr",back.eth_addr,20);
+ if(i < 0) {
+ puts("Not possible to write Backup\n");
+ return;
+ }
+ back.eth_addr[20]=0;
+ i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
+}
+
+void clear_env_values(void)
+{
+ backup_t back;
+ unsigned char env_crc[4];
+
+ memset(&back,0xff,sizeof(backup_t));
+ memset(env_crc,0x00,4);
+ i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
+ i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,CONFIG_ENV_OFFSET,2,(void *)env_crc,4);
+}
+
+/*
+ * check crc of "older" environment
+ */
+int check_env_old_size(ulong oldsize)
+{
+ ulong crc, len, new;
+ unsigned off;
+ uchar buf[64];
+
+ /* read old CRC */
+ eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR,
+ CONFIG_ENV_OFFSET,
+ (uchar *)&crc, sizeof(ulong));
+
+ new = 0;
+ len = oldsize;
+ off = sizeof(long);
+ len = oldsize-off;
+ while (len > 0) {
+ int n = (len > sizeof(buf)) ? sizeof(buf) : len;
+
+ eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, buf, n);
+ new = crc32 (new, buf, n);
+ len -= n;
+ off += n;
+ }
+
+ return (crc == new);
+}
+
+static ulong oldsizes[] = {
+ 0x200,
+ 0x800,
+ 0
+};
+
+void copy_old_env(ulong size)
+{
+ uchar name_buf[64];
+ uchar value_buf[0x800];
+ uchar c;
+ ulong len;
+ unsigned off;
+ uchar *name, *value;
+
+ name = &name_buf[0];
+ value = &value_buf[0];
+ len=size;
+ off = sizeof(long);
+ while (len > off) {
+ eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
+ if(c != '=') {
+ *name++=c;
+ off++;
+ }
+ else {
+ *name++='\0';
+ off++;
+ do {
+ eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
+ *value++=c;
+ off++;
+ if(c == '\0')
+ break;
+ } while(len > off);
+ name = &name_buf[0];
+ value = &value_buf[0];
+ if(strncmp((char *)name,"baudrate",8)!=0) {
+ setenv((char *)name,(char *)value);
+ }
+
+ }
+ }
+}
+
+
+void check_env(void)
+{
+ char *s;
+ int i=0;
+ char buf[32];
+ backup_t back;
+
+ s=getenv("serial#");
+ if(!s) {
+ while(oldsizes[i]) {
+ if(check_env_old_size(oldsizes[i]))
+ break;
+ i++;
+ }
+ if(!oldsizes[i]) {
+ /* no old environment has been found */
+ get_backup_values (&back);
+ if (strncmp (back.signature, "MPL\0", 4) == 0) {
+ sprintf (buf, "%s", back.serial_name);
+ setenv ("serial#", buf);
+ sprintf (buf, "%s", back.eth_addr);
+ setenv ("ethaddr", buf);
+ printf ("INFO: serial# and ethaddr recovered, use saveenv\n");
+ return;
+ }
+ }
+ else {
+ copy_old_env(oldsizes[i]);
+ puts("INFO: old environment ajusted, use saveenv\n");
+ }
+ }
+ else {
+ /* check if back up is set */
+ get_backup_values(&back);
+ if(strncmp(back.signature,"MPL\0",4)!=0) {
+ set_backup_values(0);
+ }
+ }
+}
+
+#endif /* #if !defined(CONFIG_PATI) */
+
+int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong ld_addr;
+ int result;
+#if !defined(CONFIG_PATI)
+ ulong size = IMAGE_SIZE;
+ ulong src = MULTI_PURPOSE_SOCKET_ADDR;
+ backup_t back;
+#endif
+
+ if (strcmp(argv[1], "flash") == 0)
+ {
+#if defined(CONFIG_CMD_FDC)
+ if (strcmp(argv[2], "floppy") == 0) {
+ char *local_args[3];
+ extern int do_fdcboot (cmd_tbl_t *, int, int, char *[]);
+ puts("\nupdating bootloader image from floppy\n");
+ local_args[0] = argv[0];
+ if(argc==4) {
+ local_args[1] = argv[3];
+ local_args[2] = NULL;
+ ld_addr=simple_strtoul(argv[3], NULL, 16);
+ result=do_fdcboot(cmdtp, 0, 2, local_args);
+ }
+ else {
+ local_args[1] = NULL;
+ ld_addr=CONFIG_SYS_LOAD_ADDR;
+ result=do_fdcboot(cmdtp, 0, 1, local_args);
+ }
+ result=mpl_prg_image((uchar *)ld_addr);
+ return result;
+ }
+#endif
+ if (strcmp(argv[2], "mem") == 0) {
+ if(argc==4) {
+ ld_addr=simple_strtoul(argv[3], NULL, 16);
+ }
+ else {
+ ld_addr=load_addr;
+ }
+ printf ("\nupdating bootloader image from memory at %lX\n",ld_addr);
+ result=mpl_prg_image((uchar *)ld_addr);
+ return result;
+ }
+#if !defined(CONFIG_PATI)
+ if (strcmp(argv[2], "mps") == 0) {
+ puts("\nupdating bootloader image from MPS\n");
+ result=mpl_prg((uchar *)src,size);
+ return result;
+ }
+#endif /* #if !defined(CONFIG_PATI) */
+ }
+#if !defined(CONFIG_PATI)
+ if (strcmp(argv[1], "clearenvvalues") == 0)
+ {
+ if (strcmp(argv[2], "yes") == 0)
+ {
+ clear_env_values();
+ return 0;
+ }
+ }
+ if (strcmp(argv[1], "getback") == 0) {
+ get_backup_values(&back);
+ back.signature[3]=0;
+ back.serial_name[16]=0;
+ back.eth_addr[20]=0;
+ printf("GetBackUp: signature: %s\n",back.signature);
+ printf(" serial#: %s\n",back.serial_name);
+ printf(" ethaddr: %s\n",back.eth_addr);
+ return 0;
+ }
+ if (strcmp(argv[1], "setback") == 0) {
+ set_backup_values(1);
+ return 0;
+ }
+#endif
+ return cmd_usage(cmdtp);
+}
+
+
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void)
+{
+ doc_probe(MULTI_PURPOSE_SOCKET_ADDR);
+}
+#endif
+
+
+#ifdef CONFIG_VIDEO
+/******************************************************
+ * Routines to display the Board information
+ * to the screen (since the VGA will be initialized as last,
+ * we must resend the infos)
+ */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+extern GraphicDevice ctfb;
+extern int get_boot_mode(void);
+
+void video_get_info_str (int line_number, char *info)
+{
+ /* init video info strings for graphic console */
+ PPC4xx_SYS_INFO sys_info;
+ char rev;
+ int i,boot;
+ unsigned long pvr;
+ char buf[64];
+ char buf1[32], buf2[32], buf3[32], buf4[32];
+ char cpustr[16];
+ char *s, *e, bc;
+ switch (line_number)
+ {
+ case 2:
+ /* CPU and board infos */
+ pvr=get_pvr();
+ get_sys_info (&sys_info);
+ switch (pvr) {
+ case PVR_405GP_RB: rev='B'; break;
+ case PVR_405GP_RC: rev='C'; break;
+ case PVR_405GP_RD: rev='D'; break;
+ case PVR_405GP_RE: rev='E'; break;
+ case PVR_405GPR_RB: rev='B'; break;
+ default: rev='?'; break;
+ }
+ if(pvr==PVR_405GPR_RB)
+ sprintf(cpustr,"PPC405GPr %c",rev);
+ else
+ sprintf(cpustr,"PPC405GP %c",rev);
+ /* Board info */
+ i=0;
+ s=getenv ("serial#");
+#ifdef CONFIG_PIP405
+ if (!s || strncmp (s, "PIP405", 6)) {
+ sprintf(buf,"### No HW ID - assuming PIP405");
+ }
+#endif
+#ifdef CONFIG_MIP405
+ if (!s || strncmp (s, "MIP405", 6)) {
+ sprintf(buf,"### No HW ID - assuming MIP405");
+ }
+#endif
+ else {
+ for (e = s; *e; ++e) {
+ if (*e == ' ')
+ break;
+ }
+ for (; s < e; ++s) {
+ if (*s == '_') {
+ ++s;
+ break;
+ }
+ buf[i++] = *s;
+ }
+ sprintf(&buf[i]," SN ");
+ i+=4;
+ for (; s < e; ++s) {
+ buf[i++] = *s;
+ }
+ buf[i++]=0;
+ }
+ sprintf (info," %s %s %s MHz (%s/%s/%s MHz)",
+ buf, cpustr,
+ strmhz (buf1, gd->cpu_clk),
+ strmhz (buf2, sys_info.freqPLB),
+ strmhz (buf3, sys_info.freqPLB / sys_info.pllOpbDiv),
+ strmhz (buf4, sys_info.freqPLB / sys_info.pllExtBusDiv));
+ return;
+ case 3:
+ /* Memory Info */
+ boot = get_boot_mode();
+ bc = in8 (CONFIG_PORT_ADDR);
+ sprintf(info, " %luMB RAM, %luMB Flash Cfg 0x%02X %s %s",
+ gd->bd->bi_memsize / 0x100000,
+ gd->bd->bi_flashsize / 0x100000,
+ bc,
+ (boot & BOOT_MPS) ? "MPS boot" : "Flash boot",
+ ctfb.modeIdent);
+ return;
+ case 1:
+ sprintf (buf, "%s",CONFIG_IDENT_STRING);
+ sprintf (info, " %s", &buf[1]);
+ return;
+ }
+ /* no more info lines */
+ *info = 0;
+ return;
+}
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
+
+#endif /* CONFIG_VIDEO */
diff --git a/board/mpl/common/common_util.h b/board/mpl/common/common_util.h
new file mode 100644
index 0000000..e81ee35
--- /dev/null
+++ b/board/mpl/common/common_util.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _COMMON_UTIL_H_
+#define _COMMON_UTIL_H_
+
+typedef struct {
+ char signature[4];
+ char serial_name[17]; /* "MIP405_1000xxxxx" */
+ char eth_addr[21]; /* "00:60:C2:0a:00:00" */
+} backup_t;
+
+extern flash_info_t flash_info[]; /* info for FLASH chips */
+
+void get_backup_values(backup_t *buf);
+
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
+#define BOOT_MPS 0x01
+#define BOOT_PCI 0x02
+int get_boot_mode(void);
+void setup_cs_reloc(void);
+#endif
+
+void check_env(void);
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void);
+#endif
+
+#endif /* _COMMON_UTIL_H_ */
diff --git a/board/mpl/common/isa.c b/board/mpl/common/isa.c
new file mode 100644
index 0000000..54ec66b
--- /dev/null
+++ b/board/mpl/common/isa.c
@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * TODO: clean-up
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <stdio_dev.h>
+#include "isa.h"
+#include "piix4_pci.h"
+#include "kbd.h"
+#include "video.h"
+
+
+#undef ISA_DEBUG
+
+#ifdef ISA_DEBUG
+#define PRINTF(fmt,args...) printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+#if defined(CONFIG_PIP405)
+
+extern int drv_isa_kbd_init (void);
+
+/* fdc (logical device 0) */
+const SIO_LOGDEV_TABLE sio_fdc[] = {
+ {0x60, 3}, /* set IO to FDPort (3F0) */
+ {0x61, 0xF0}, /* set IO to FDPort (3F0) */
+ {0x70, 06}, /* set IRQ 6 for FDPort */
+ {0x74, 02}, /* set DMA 2 for FDPort */
+ {0xF0, 0x05}, /* set to PS2 type */
+ {0xF1, 0x00}, /* default value */
+ {0x30, 1}, /* and activate the device */
+ {0xFF, 0} /* end of device table */
+};
+/* paralell port (logical device 3) */
+const SIO_LOGDEV_TABLE sio_pport[] = {
+ {0x60, 3}, /* set IO to PPort (378) */
+ {0x61, 0x78}, /* set IO to PPort (378) */
+ {0x70, 07}, /* set IRQ 7 for PPort */
+ {0xF1, 00}, /* set PPort to normal */
+ {0x30, 1}, /* and activate the device */
+ {0xFF, 0} /* end of device table */
+};
+/* paralell port (logical device 3) Floppy assigned to lpt */
+const SIO_LOGDEV_TABLE sio_pport_fdc[] = {
+ {0x60, 3}, /* set IO to PPort (378) */
+ {0x61, 0x78}, /* set IO to PPort (378) */
+ {0x70, 07}, /* set IRQ 7 for PPort */
+ {0xF1, 02}, /* set PPort to Floppy */
+ {0x30, 1}, /* and activate the device */
+ {0xFF, 0} /* end of device table */
+};
+/* uart 1 (logical device 4) */
+const SIO_LOGDEV_TABLE sio_com1[] = {
+ {0x60, 3}, /* set IO to COM1 (3F8) */
+ {0x61, 0xF8}, /* set IO to COM1 (3F8) */
+ {0x70, 04}, /* set IRQ 4 for COM1 */
+ {0x30, 1}, /* and activate the device */
+ {0xFF, 0} /* end of device table */
+};
+/* uart 2 (logical device 5) */
+const SIO_LOGDEV_TABLE sio_com2[] = {
+ {0x60, 2}, /* set IO to COM2 (2F8) */
+ {0x61, 0xF8}, /* set IO to COM2 (2F8) */
+ {0x70, 03}, /* set IRQ 3 for COM2 */
+ {0x30, 1}, /* and activate the device */
+ {0xFF, 0} /* end of device table */
+};
+
+/* keyboard controller (logical device 7) */
+const SIO_LOGDEV_TABLE sio_keyboard[] = {
+ {0x70, 1}, /* set IRQ 1 for keyboard */
+ {0x72, 12}, /* set IRQ 12 for mouse */
+ {0xF0, 0}, /* disable Port92 (this is a PowerPC!!) */
+ {0x30, 1}, /* and activate the device */
+ {0xFF, 0} /* end of device table */
+};
+
+
+/*******************************************************************************
+* Config SuperIO FDC37C672
+********************************************************************************/
+unsigned char open_cfg_super_IO(int address)
+{
+ out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */
+ out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */
+ if(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */
+ return true;
+ else
+ return false;
+}
+
+void close_cfg_super_IO(int address)
+{
+ out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0xAA); /* close config */
+}
+
+
+unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr)
+{
+ /* assuming config reg is open */
+ out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
+ out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
+ out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
+ return in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1);
+}
+
+void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data)
+{
+ /* assuming config reg is open */
+ out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
+ out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
+ out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
+ out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,data); /* writes the data */
+}
+
+void isa_write_table(SIO_LOGDEV_TABLE *ldt,unsigned char ldev)
+{
+ while (ldt->index != 0xFF) {
+ write_cfg_super_IO(SIO_CFG_PORT, ldev, ldt->index, ldt->val);
+ ldt++;
+ } /* endwhile */
+}
+
+void isa_sio_loadtable(void)
+{
+ char *s = getenv("floppy");
+ /* setup Floppy device 0*/
+ isa_write_table((SIO_LOGDEV_TABLE *)&sio_fdc,0);
+ /* setup parallel port device 3 */
+ if(s && !strncmp(s, "lpt", 3)) {
+ printf("SIO: Floppy assigned to LPT\n");
+ /* floppy is assigned to the LPT */
+ isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport_fdc,3);
+ }
+ else {
+ /*printf("Floppy assigned to internal port\n");*/
+ isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport,3);
+ }
+ /* setup Com1 port device 4 */
+ isa_write_table((SIO_LOGDEV_TABLE *)&sio_com1,4);
+ /* setup Com2 port device 5 */
+ isa_write_table((SIO_LOGDEV_TABLE *)&sio_com2,5);
+ /* setup keyboards device 7 */
+ isa_write_table((SIO_LOGDEV_TABLE *)&sio_keyboard,7);
+}
+
+
+void isa_sio_setup(void)
+{
+ if (open_cfg_super_IO(SIO_CFG_PORT) == true)
+ {
+ isa_sio_loadtable();
+ close_cfg_super_IO(0x3F0);
+ }
+}
+#endif
+
+/******************************************************************************
+ * IRQ Controller
+ * we use the Vector mode
+ */
+
+struct isa_irq_action {
+ interrupt_handler_t *handler;
+ void *arg;
+ int count;
+};
+
+static struct isa_irq_action isa_irqs[16];
+
+
+/*
+ * This contains the irq mask for both 8259A irq controllers,
+ */
+static unsigned int cached_irq_mask = 0xfff9;
+
+#define cached_imr1 (unsigned char)cached_irq_mask
+#define cached_imr2 (unsigned char)(cached_irq_mask>>8)
+#define IMR_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_OCW1
+#define IMR_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_OCW1
+#define ICW1_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW1
+#define ICW1_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW1
+#define ICW2_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW2
+#define ICW2_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW2
+#define ICW3_1 ICW2_1
+#define ICW3_2 ICW2_2
+#define ICW4_1 ICW2_1
+#define ICW4_2 ICW2_2
+#define ISR_1 ICW1_1
+#define ISR_2 ICW1_2
+
+
+void disable_8259A_irq(unsigned int irq)
+{
+ unsigned int mask = 1 << irq;
+
+ cached_irq_mask |= mask;
+ if (irq & 8)
+ out8(IMR_2,cached_imr2);
+ else
+ out8(IMR_1,cached_imr1);
+}
+
+void enable_8259A_irq(unsigned int irq)
+{
+ unsigned int mask = ~(1 << irq);
+
+ cached_irq_mask &= mask;
+ if (irq & 8)
+ out8(IMR_2,cached_imr2);
+ else
+ out8(IMR_1,cached_imr1);
+}
+/*
+int i8259A_irq_pending(unsigned int irq)
+{
+ unsigned int mask = 1<<irq;
+ int ret;
+
+ if (irq < 8)
+ ret = inb(0x20) & mask;
+ else
+ ret = inb(0xA0) & (mask >> 8);
+ spin_unlock_irqrestore(&i8259A_lock, flags);
+
+ return ret;
+}
+*/
+
+/*
+ * This function assumes to be called rarely. Switching between
+ * 8259A registers is slow.
+ */
+int i8259A_irq_real(unsigned int irq)
+{
+ int value;
+ int irqmask = 1<<irq;
+
+ if (irq < 8) {
+ out8(ISR_1,0x0B); /* ISR register */
+ value = in8(ISR_1) & irqmask;
+ out8(ISR_1,0x0A); /* back to the IRR register */
+ return value;
+ }
+ out8(ISR_2,0x0B); /* ISR register */
+ value = in8(ISR_2) & (irqmask >> 8);
+ out8(ISR_2,0x0A); /* back to the IRR register */
+ return value;
+}
+
+/*
+ * Careful! The 8259A is a fragile beast, it pretty
+ * much _has_ to be done exactly like this (mask it
+ * first, _then_ send the EOI, and the order of EOI
+ * to the two 8259s is important!
+ */
+void mask_and_ack_8259A(unsigned int irq)
+{
+ unsigned int irqmask = 1 << irq;
+ unsigned int temp_irqmask = cached_irq_mask;
+ /*
+ * Lightweight spurious IRQ detection. We do not want
+ * to overdo spurious IRQ handling - it's usually a sign
+ * of hardware problems, so we only do the checks we can
+ * do without slowing down good hardware unnecesserily.
+ *
+ * Note that IRQ7 and IRQ15 (the two spurious IRQs
+ * usually resulting from the 8259A-1|2 PICs) occur
+ * even if the IRQ is masked in the 8259A. Thus we
+ * can check spurious 8259A IRQs without doing the
+ * quite slow i8259A_irq_real() call for every IRQ.
+ * This does not cover 100% of spurious interrupts,
+ * but should be enough to warn the user that there
+ * is something bad going on ...
+ */
+ if (temp_irqmask & irqmask)
+ goto spurious_8259A_irq;
+ temp_irqmask |= irqmask;
+
+handle_real_irq:
+ if (irq & 8) {
+ in8(IMR_2); /* DUMMY - (do we need this?) */
+ out8(IMR_2,(unsigned char)(temp_irqmask>>8));
+ out8(ISR_2,0x60+(irq&7));/* 'Specific EOI' to slave */
+ out8(ISR_1,0x62); /* 'Specific EOI' to master-IRQ2 */
+ out8(IMR_2,cached_imr2); /* turn it on again */
+ } else {
+ in8(IMR_1); /* DUMMY - (do we need this?) */
+ out8(IMR_1,(unsigned char)temp_irqmask);
+ out8(ISR_1,0x60+irq); /* 'Specific EOI' to master */
+ out8(IMR_1,cached_imr1); /* turn it on again */
+ }
+
+ return;
+
+spurious_8259A_irq:
+ /*
+ * this is the slow path - should happen rarely.
+ */
+ if (i8259A_irq_real(irq))
+ /*
+ * oops, the IRQ _is_ in service according to the
+ * 8259A - not spurious, go handle it.
+ */
+ goto handle_real_irq;
+
+ {
+ static int spurious_irq_mask;
+ /*
+ * At this point we can be sure the IRQ is spurious,
+ * lets ACK and report it. [once per IRQ]
+ */
+ if (!(spurious_irq_mask & irqmask)) {
+ PRINTF("spurious 8259A interrupt: IRQ%d.\n", irq);
+ spurious_irq_mask |= irqmask;
+ }
+ /* irq_err_count++; */
+ /*
+ * Theoretically we do not have to handle this IRQ,
+ * but in Linux this does not cause problems and is
+ * simpler for us.
+ */
+ goto handle_real_irq;
+ }
+}
+
+void init_8259A(void)
+{
+ out8(IMR_1,0xff); /* mask all of 8259A-1 */
+ out8(IMR_2,0xff); /* mask all of 8259A-2 */
+
+ out8(ICW1_1,0x11); /* ICW1: select 8259A-1 init */
+ out8(ICW2_1,0x20 + 0); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
+ out8(ICW3_1,0x04); /* 8259A-1 (the master) has a slave on IR2 */
+ out8(ICW4_1,0x01); /* master expects normal EOI */
+ out8(ICW1_2,0x11); /* ICW2: select 8259A-2 init */
+ out8(ICW2_2,0x20 + 8); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
+ out8(ICW3_2,0x02); /* 8259A-2 is a slave on master's IR2 */
+ out8(ICW4_2,0x01); /* (slave's support for AEOI in flat mode
+ is to be investigated) */
+ udelay(10000); /* wait for 8259A to initialize */
+ out8(IMR_1,cached_imr1); /* restore master IRQ mask */
+ udelay(10000); /* wait for 8259A to initialize */
+ out8(IMR_2,cached_imr2); /* restore slave IRQ mask */
+}
+
+
+#define PCI_INT_ACK_ADDR 0xEED00000
+
+int handle_isa_int(void)
+{
+ unsigned long irqack;
+ unsigned char irq;
+ /* first we acknokledge the int via the PCI bus */
+ irqack=in32(PCI_INT_ACK_ADDR);
+ /* now we get the ISRs */
+ in8(ISR_2);
+ in8(ISR_1);
+ irq=(unsigned char)irqack;
+ irq-=32;
+/* if((irq==7)&&((isr1&0x80)==0)) {
+ PRINTF("IRQ7 detected but not in ISR\n");
+ }
+ else {
+*/ /* we should handle cascaded interrupts here also */
+ {
+/* printf("ISA Irq %d\n",irq); */
+ isa_irqs[irq].count++;
+ if(irq!=2) { /* just swallow the cascade irq 2 */
+ if (isa_irqs[irq].handler != NULL)
+ (*isa_irqs[irq].handler)(isa_irqs[irq].arg); /* call isr */
+ else {
+ PRINTF ("bogus interrupt vector 0x%x\n", irq);
+ }
+ }
+ }
+ /* issue EOI instruction to clear the IRQ */
+ mask_and_ack_8259A(irq);
+ return 0;
+}
+
+
+/******************************************************************
+ * Install and free an ISA interrupt handler.
+ */
+
+void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+{
+ if (isa_irqs[vec].handler != NULL) {
+ printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
+ vec, (uint)handler, (uint)isa_irqs[vec].handler);
+ }
+ isa_irqs[vec].handler = handler;
+ isa_irqs[vec].arg = arg;
+ enable_8259A_irq(vec);
+ PRINTF ("Install ISA IRQ %d ==> %p, @ %p mask=%04x\n", vec, handler, &isa_irqs[vec].handler,cached_irq_mask);
+
+}
+
+void isa_irq_free_handler(int vec)
+{
+ disable_8259A_irq(vec);
+ isa_irqs[vec].handler = NULL;
+ isa_irqs[vec].arg = NULL;
+ PRINTF ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
+
+}
+
+/****************************************************************************/
+void isa_init_irq_contr(void)
+{
+ int i;
+ /* disable all Interrupts */
+ /* first write icws controller 1 */
+ for(i=0;i<16;i++)
+ {
+ isa_irqs[i].handler=NULL;
+ isa_irqs[i].arg=NULL;
+ isa_irqs[i].count=0;
+ }
+ init_8259A();
+ out8(IMR_2,0xFF);
+}
+/*************************************************************************/
+
+void isa_show_irq(void)
+{
+ int vec;
+
+ printf ("\nISA Interrupt-Information:\n");
+ printf ("Nr Routine Arg Count\n");
+
+ for (vec=0; vec<16; vec++) {
+ if (isa_irqs[vec].handler != NULL) {
+ printf ("%02d %08lx %08lx %d\n",
+ vec,
+ (ulong)isa_irqs[vec].handler,
+ (ulong)isa_irqs[vec].arg,
+ isa_irqs[vec].count);
+ }
+ }
+}
+
+int isa_irq_get_count(int vec)
+{
+ return(isa_irqs[vec].count);
+}
+
+/******************************************************************
+ * Init the ISA bus and devices.
+ */
+
+#if defined(CONFIG_PIP405)
+
+int isa_init(void)
+{
+ isa_sio_setup();
+ isa_init_irq_contr();
+ drv_isa_kbd_init();
+ return 0;
+}
+#endif
diff --git a/board/mpl/common/isa.h b/board/mpl/common/isa.h
new file mode 100644
index 0000000..c706d67
--- /dev/null
+++ b/board/mpl/common/isa.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ISA_H_
+#define _ISA_H_
+/* Super IO */
+#define SIO_CFG_PORT 0x3F0 /* Config Port Address */
+
+#if defined(CONFIG_PIP405)
+/* table fore SIO initialization */
+typedef struct {
+ const uchar index;
+ const uchar val;
+} SIO_LOGDEV_TABLE;
+
+typedef struct {
+ const uchar ldev;
+ const SIO_LOGDEV_TABLE *ldev_table;
+} SIO_TABLE;
+
+
+unsigned char open_cfg_super_IO(int address);
+unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr);
+void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data);
+void close_cfg_super_IO(int address);
+void isa_sio_setup(void);
+#endif
+
+void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg);
+void isa_irq_free_handler(int vec);
+int handle_isa_int(void);
+void isa_init_irq_contr(void);
+void isa_show_irq(void);
+int isa_irq_get_count(int vec);
+
+
+#endif
diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c
new file mode 100644
index 0000000..99de2ca
--- /dev/null
+++ b/board/mpl/common/kbd.c
@@ -0,0 +1,624 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Source partly derived from:
+ * linux/drivers/char/pc_keyb.c
+ */
+#include <common.h>
+#include <asm/processor.h>
+#include <stdio_dev.h>
+#include "isa.h"
+#include "kbd.h"
+
+
+unsigned char kbd_read_status(void);
+unsigned char kbd_read_input(void);
+void kbd_send_data(unsigned char data);
+void disable_8259A_irq(unsigned int irq);
+void enable_8259A_irq(unsigned int irq);
+
+/* used only by send_data - set by keyboard_interrupt */
+
+
+#undef KBG_DEBUG
+
+#ifdef KBG_DEBUG
+#define PRINTF(fmt,args...) printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+#define KBD_STAT_KOBF 0x01
+#define KBD_STAT_IBF 0x02
+#define KBD_STAT_SYS 0x04
+#define KBD_STAT_CD 0x08
+#define KBD_STAT_LOCK 0x10
+#define KBD_STAT_MOBF 0x20
+#define KBD_STAT_TI_OUT 0x40
+#define KBD_STAT_PARERR 0x80
+
+#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */
+#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */
+#define KBD_TIMEOUT 2000 /* Timeout in ms for keyboard command acknowledge */
+/*
+ * Keyboard Controller Commands
+ */
+
+#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
+#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
+#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
+#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
+#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
+#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
+#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
+#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
+#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
+#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
+#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
+ initiated by the auxiliary device */
+#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
+
+/*
+ * Keyboard Commands
+ */
+
+#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
+#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
+#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
+#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */
+#define KBD_CMD_RESET 0xFF /* Reset */
+
+/*
+ * Keyboard Replies
+ */
+
+#define KBD_REPLY_POR 0xAA /* Power on reset */
+#define KBD_REPLY_ACK 0xFA /* Command ACK */
+#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
+
+/*
+ * Status Register Bits
+ */
+
+#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
+#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
+#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
+#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
+#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
+#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
+#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
+#define KBD_STAT_PERR 0x80 /* Parity error */
+
+#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
+
+/*
+ * Controller Mode Register Bits
+ */
+
+#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
+#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
+#define KBD_MODE_SYS 0x04 /* The system flag (?) */
+#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
+#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
+#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
+#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
+#define KBD_MODE_RFU 0x80
+
+
+#define KDB_DATA_PORT 0x60
+#define KDB_COMMAND_PORT 0x64
+
+#define LED_SCR 0x01 /* scroll lock led */
+#define LED_CAP 0x04 /* caps lock led */
+#define LED_NUM 0x02 /* num lock led */
+
+#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
+
+
+static volatile char kbd_buffer[KBD_BUFFER_LEN];
+static volatile int in_pointer = 0;
+static volatile int out_pointer = 0;
+
+
+static unsigned char num_lock = 0;
+static unsigned char caps_lock = 0;
+static unsigned char scroll_lock = 0;
+static unsigned char shift = 0;
+static unsigned char ctrl = 0;
+static unsigned char alt = 0;
+static unsigned char e0 = 0;
+static unsigned char leds = 0;
+
+#define DEVNAME "kbd"
+
+/* Simple translation table for the keys */
+
+static unsigned char kbd_plain_xlate[] = {
+ 0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t', /* 0x00 - 0x0f */
+ 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's', /* 0x10 - 0x1f */
+ 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */
+ 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
+ '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
+ '\r',0xff,0xff
+ };
+
+static unsigned char kbd_shift_xlate[] = {
+ 0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t', /* 0x00 - 0x0f */
+ 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S', /* 0x10 - 0x1f */
+ 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V', /* 0x20 - 0x2f */
+ 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
+ '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
+ '\r',0xff,0xff
+ };
+
+static unsigned char kbd_ctrl_xlate[] = {
+ 0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t', /* 0x00 - 0x0f */
+ 0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13, /* 0x10 - 0x1f */
+ 0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16, /* 0x20 - 0x2f */
+ 0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
+ '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
+ '\r',0xff,0xff
+ };
+
+/******************************************************************
+ * Init
+ ******************************************************************/
+int isa_kbd_init(void)
+{
+ char* result;
+ result=kbd_initialize();
+ if(result==NULL) {
+ PRINTF("AT Keyboard initialized\n");
+ irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL);
+ isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
+ return (1);
+ } else {
+ printf("%s\n",result);
+ return (-1);
+ }
+}
+
+#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+extern int overwrite_console (void);
+#else
+int overwrite_console (void)
+{
+ return (0);
+}
+#endif
+
+int drv_isa_kbd_init (void)
+{
+ int error;
+ struct stdio_dev kbddev ;
+ char *stdinname = getenv ("stdin");
+
+ if(isa_kbd_init()==-1)
+ return -1;
+ memset (&kbddev, 0, sizeof(kbddev));
+ strcpy(kbddev.name, DEVNAME);
+ kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+ kbddev.getc = kbd_getc ;
+ kbddev.tstc = kbd_testc ;
+
+ error = stdio_register (&kbddev);
+ if(error==0) {
+ /* check if this is the standard input device */
+ if(strcmp(stdinname,DEVNAME)==0) {
+ /* reassign the console */
+ if(overwrite_console()) {
+ return 1;
+ }
+ error=console_assign(stdin,DEVNAME);
+ if(error==0)
+ return 1;
+ else
+ return error;
+ }
+ return 1;
+ }
+ return error;
+}
+
+/******************************************************************
+ * Queue handling
+ ******************************************************************/
+/* puts character in the queue and sets up the in and out pointer */
+void kbd_put_queue(char data)
+{
+ if((in_pointer+1)==KBD_BUFFER_LEN) {
+ if(out_pointer==0) {
+ return; /* buffer full */
+ } else{
+ in_pointer=0;
+ }
+ } else {
+ if((in_pointer+1)==out_pointer)
+ return; /* buffer full */
+ in_pointer++;
+ }
+ kbd_buffer[in_pointer]=data;
+ return;
+}
+
+/* test if a character is in the queue */
+int kbd_testc(struct stdio_dev *dev)
+{
+ if(in_pointer==out_pointer)
+ return(0); /* no data */
+ else
+ return(1);
+}
+/* gets the character from the queue */
+int kbd_getc(struct stdio_dev *dev)
+{
+ char c;
+ while(in_pointer==out_pointer);
+ if((out_pointer+1)==KBD_BUFFER_LEN)
+ out_pointer=0;
+ else
+ out_pointer++;
+ c=kbd_buffer[out_pointer];
+ return (int)c;
+
+}
+
+
+/* set LEDs */
+
+void kbd_set_leds(void)
+{
+ if(caps_lock==0)
+ leds&=~LED_CAP; /* switch caps_lock off */
+ else
+ leds|=LED_CAP; /* switch on LED */
+ if(num_lock==0)
+ leds&=~LED_NUM; /* switch LED off */
+ else
+ leds|=LED_NUM; /* switch on LED */
+ if(scroll_lock==0)
+ leds&=~LED_SCR; /* switch LED off */
+ else
+ leds|=LED_SCR; /* switch on LED */
+ kbd_send_data(KBD_CMD_SET_LEDS);
+ kbd_send_data(leds);
+}
+
+
+void handle_keyboard_event (unsigned char scancode)
+{
+ unsigned char keycode;
+
+ /* Convert scancode to keycode */
+ PRINTF ("scancode %x\n", scancode);
+ if (scancode == 0xe0) {
+ e0 = 1; /* special charakters */
+ return;
+ }
+ if (e0 == 1) {
+ e0 = 0; /* delete flag */
+ if (!(((scancode & 0x7F) == 0x38) || /* the right ctrl key */
+ ((scancode & 0x7F) == 0x1D) || /* the right alt key */
+ ((scancode & 0x7F) == 0x35) || /* the right '/' key */
+ ((scancode & 0x7F) == 0x1C)))
+ /* the right enter key */
+ /* we swallow unknown e0 codes */
+ return;
+ }
+ /* special cntrl keys */
+ switch (scancode) {
+ case 0x2A:
+ case 0x36: /* shift pressed */
+ shift = 1;
+ return; /* do nothing else */
+ case 0xAA:
+ case 0xB6: /* shift released */
+ shift = 0;
+ return; /* do nothing else */
+ case 0x38: /* alt pressed */
+ alt = 1;
+ return; /* do nothing else */
+ case 0xB8: /* alt released */
+ alt = 0;
+ return; /* do nothing else */
+ case 0x1d: /* ctrl pressed */
+ ctrl = 1;
+ return; /* do nothing else */
+ case 0x9d: /* ctrl released */
+ ctrl = 0;
+ return; /* do nothing else */
+ case 0x46: /* scrollock pressed */
+ scroll_lock = ~scroll_lock;
+ kbd_set_leds ();
+ return; /* do nothing else */
+ case 0x3A: /* capslock pressed */
+ caps_lock = ~caps_lock;
+ kbd_set_leds ();
+ return;
+ case 0x45: /* numlock pressed */
+ num_lock = ~num_lock;
+ kbd_set_leds ();
+ return;
+ case 0xC6: /* scroll lock released */
+ case 0xC5: /* num lock released */
+ case 0xBA: /* caps lock released */
+ return; /* just swallow */
+ }
+ if ((scancode & 0x80) == 0x80) /* key released */
+ return;
+ /* now, decide which table we need */
+ if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) { /* scancode not in list */
+ PRINTF ("unkown scancode %X\n", scancode);
+ return; /* swallow it */
+ }
+ /* setup plain code first */
+ keycode = kbd_plain_xlate[scancode];
+ if (caps_lock == 1) { /* caps_lock is pressed, overwrite plain code */
+ if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
+ PRINTF ("unkown caps-locked scancode %X\n", scancode);
+ return; /* swallow it */
+ }
+ keycode = kbd_shift_xlate[scancode];
+ if (keycode < 'A') { /* we only want the alphas capital */
+ keycode = kbd_plain_xlate[scancode];
+ }
+ }
+ if (shift == 1) { /* shift overwrites caps_lock */
+ if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
+ PRINTF ("unkown shifted scancode %X\n", scancode);
+ return; /* swallow it */
+ }
+ keycode = kbd_shift_xlate[scancode];
+ }
+ if (ctrl == 1) { /* ctrl overwrites caps_lock and shift */
+ if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) { /* scancode not in list */
+ PRINTF ("unkown ctrl scancode %X\n", scancode);
+ return; /* swallow it */
+ }
+ keycode = kbd_ctrl_xlate[scancode];
+ }
+ /* check if valid keycode */
+ if (keycode == 0xff) {
+ PRINTF ("unkown scancode %X\n", scancode);
+ return; /* swallow unknown codes */
+ }
+
+ kbd_put_queue (keycode);
+ PRINTF ("%x\n", keycode);
+}
+
+/*
+ * This reads the keyboard status port, and does the
+ * appropriate action.
+ *
+ */
+unsigned char handle_kbd_event(void)
+{
+ unsigned char status = kbd_read_status();
+ unsigned int work = 10000;
+
+ while ((--work > 0) && (status & KBD_STAT_OBF)) {
+ unsigned char scancode;
+
+ scancode = kbd_read_input();
+
+ /* Error bytes must be ignored to make the
+ Synaptics touchpads compaq use work */
+ /* Ignore error bytes */
+ if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR)))
+ {
+ if (status & KBD_STAT_MOUSE_OBF)
+ ; /* not supported: handle_mouse_event(scancode); */
+ else
+ handle_keyboard_event(scancode);
+ }
+ status = kbd_read_status();
+ }
+ if (!work)
+ PRINTF("pc_keyb: controller jammed (0x%02X).\n", status);
+ return status;
+}
+
+
+/******************************************************************************
+ * Lowlevel Part of keyboard section
+ */
+unsigned char kbd_read_status(void)
+{
+ return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
+}
+
+unsigned char kbd_read_input(void)
+{
+ return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
+}
+
+void kbd_write_command(unsigned char cmd)
+{
+ out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
+}
+
+void kbd_write_output(unsigned char data)
+{
+ out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
+}
+
+int kbd_read_data(void)
+{
+ int val;
+ unsigned char status;
+
+ val = -1;
+ status = kbd_read_status();
+ if (status & KBD_STAT_OBF) {
+ val = kbd_read_input();
+ if (status & (KBD_STAT_GTO | KBD_STAT_PERR))
+ val = -2;
+ }
+ return val;
+}
+
+int kbd_wait_for_input(void)
+{
+ unsigned long timeout;
+ int val;
+
+ timeout = KBD_TIMEOUT;
+ val=kbd_read_data();
+ while(val < 0)
+ {
+ if(timeout--==0)
+ return -1;
+ udelay(1000);
+ val=kbd_read_data();
+ }
+ return val;
+}
+
+
+int kb_wait(void)
+{
+ unsigned long timeout = KBC_TIMEOUT * 10;
+
+ do {
+ unsigned char status = handle_kbd_event();
+ if (!(status & KBD_STAT_IBF))
+ return 0; /* ok */
+ udelay(1000);
+ timeout--;
+ } while (timeout);
+ return 1;
+}
+
+void kbd_write_command_w(int data)
+{
+ if(kb_wait())
+ PRINTF("timeout in kbd_write_command_w\n");
+ kbd_write_command(data);
+}
+
+void kbd_write_output_w(int data)
+{
+ if(kb_wait())
+ PRINTF("timeout in kbd_write_output_w\n");
+ kbd_write_output(data);
+}
+
+void kbd_send_data(unsigned char data)
+{
+ unsigned char status;
+ disable_8259A_irq(1); /* disable interrupt */
+ kbd_write_output_w(data);
+ status = kbd_wait_for_input();
+ if (status == KBD_REPLY_ACK)
+ enable_8259A_irq(1); /* enable interrupt */
+}
+
+
+char * kbd_initialize(void)
+{
+ int status;
+
+ in_pointer = 0; /* delete in Buffer */
+ out_pointer = 0;
+ /*
+ * Test the keyboard interface.
+ * This seems to be the only way to get it going.
+ * If the test is successful a x55 is placed in the input buffer.
+ */
+ kbd_write_command_w(KBD_CCMD_SELF_TEST);
+ if (kbd_wait_for_input() != 0x55)
+ return "Kbd: failed self test";
+ /*
+ * Perform a keyboard interface test. This causes the controller
+ * to test the keyboard clock and data lines. The results of the
+ * test are placed in the input buffer.
+ */
+ kbd_write_command_w(KBD_CCMD_KBD_TEST);
+ if (kbd_wait_for_input() != 0x00)
+ return "Kbd: interface failed self test";
+ /*
+ * Enable the keyboard by allowing the keyboard clock to run.
+ */
+ kbd_write_command_w(KBD_CCMD_KBD_ENABLE);
+ status = kbd_wait_for_input();
+ /*
+ * Reset keyboard. If the read times out
+ * then the assumption is that no keyboard is
+ * plugged into the machine.
+ * This defaults the keyboard to scan-code set 2.
+ *
+ * Set up to try again if the keyboard asks for RESEND.
+ */
+ do {
+ kbd_write_output_w(KBD_CMD_RESET);
+ status = kbd_wait_for_input();
+ if (status == KBD_REPLY_ACK)
+ break;
+ if (status != KBD_REPLY_RESEND) {
+ PRINTF("status: %X\n",status);
+ return "Kbd: reset failed, no ACK";
+ }
+ } while (1);
+ if (kbd_wait_for_input() != KBD_REPLY_POR)
+ return "Kbd: reset failed, no POR";
+
+ /*
+ * Set keyboard controller mode. During this, the keyboard should be
+ * in the disabled state.
+ *
+ * Set up to try again if the keyboard asks for RESEND.
+ */
+ do {
+ kbd_write_output_w(KBD_CMD_DISABLE);
+ status = kbd_wait_for_input();
+ if (status == KBD_REPLY_ACK)
+ break;
+ if (status != KBD_REPLY_RESEND)
+ return "Kbd: disable keyboard: no ACK";
+ } while (1);
+
+ kbd_write_command_w(KBD_CCMD_WRITE_MODE);
+ kbd_write_output_w(KBD_MODE_KBD_INT
+ | KBD_MODE_SYS
+ | KBD_MODE_DISABLE_MOUSE
+ | KBD_MODE_KCC);
+
+ /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
+ kbd_write_command_w(KBD_CCMD_READ_MODE);
+ if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
+ /*
+ * If the controller does not support conversion,
+ * Set the keyboard to scan-code set 1.
+ */
+ kbd_write_output_w(0xF0);
+ kbd_wait_for_input();
+ kbd_write_output_w(0x01);
+ kbd_wait_for_input();
+ }
+ kbd_write_output_w(KBD_CMD_ENABLE);
+ if (kbd_wait_for_input() != KBD_REPLY_ACK)
+ return "Kbd: enable keyboard: no ACK";
+
+ /*
+ * Finally, set the typematic rate to maximum.
+ */
+ kbd_write_output_w(KBD_CMD_SET_RATE);
+ if (kbd_wait_for_input() != KBD_REPLY_ACK)
+ return "Kbd: Set rate: no ACK";
+ kbd_write_output_w(0x00);
+ if (kbd_wait_for_input() != KBD_REPLY_ACK)
+ return "Kbd: Set rate: no ACK";
+ return NULL;
+}
+
+void kbd_interrupt(void)
+{
+ handle_kbd_event();
+}
diff --git a/board/mpl/common/kbd.h b/board/mpl/common/kbd.h
new file mode 100644
index 0000000..b549e20
--- /dev/null
+++ b/board/mpl/common/kbd.h
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _KBD_H_
+#define _KBD_H_
+
+struct stdio_dev;
+
+int kbd_testc(struct stdio_dev *sdev);
+int kbd_getc(struct stdio_dev *sdev);
+extern void kbd_interrupt(void);
+extern char *kbd_initialize(void);
+
+unsigned char kbd_is_init(void);
+#define KBD_INTERRUPT 1
+#endif
diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c
new file mode 100644
index 0000000..cd969cb
--- /dev/null
+++ b/board/mpl/common/pci.c
@@ -0,0 +1,90 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0 IBM-pibs
+ */
+/*
+ * Adapted for PIP405 03.07.01
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * TODO: Clean-up
+ */
+
+#include <common.h>
+#include <pci.h>
+#include "isa.h"
+
+#ifdef CONFIG_405GP
+#ifdef CONFIG_PCI
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#include "piix4_pci.h"
+#include "pci_parts.h"
+
+void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
+ struct pci_config_table *entry)
+{
+ struct pci_pip405_config_entry *table;
+ int i;
+
+ table = (struct pci_pip405_config_entry*) entry->priv[0];
+
+ for (i=0; table[i].width; i++)
+ {
+#ifdef DEBUG
+ printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
+ table[i].index, table[i].val, table[i].width);
+#endif
+
+ switch(table[i].width)
+ {
+ case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break;
+ case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break;
+ case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break;
+ }
+ }
+}
+
+
+static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+ unsigned char int_line = 0xff;
+ unsigned char pin;
+ /*
+ * Write pci interrupt line register
+ */
+ if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */
+ return;
+ pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
+ if ((pin == 0) || (pin > 4))
+ return;
+
+ int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+#ifdef DEBUG
+ printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
+ PCI_DEV(dev),dev,int_line,int_line);
+#endif
+}
+
+extern void pci_405gp_init(struct pci_controller *hose);
+
+
+static struct pci_controller hose = {
+ config_table: pci_pip405_config_table,
+ fixup_irq: pci_pip405_fixup_irq,
+};
+
+
+void pci_init_board(void)
+{
+ /*we want the ptrs to RAM not flash (ie don't use init list)*/
+ hose.fixup_irq = pci_pip405_fixup_irq;
+ hose.config_table = pci_pip405_config_table;
+#ifdef DEBUG
+ printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose);
+#endif
+ pci_405gp_init(&hose);
+}
+
+#endif /* CONFIG_PCI */
+#endif /* CONFIG_405GP */
diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h
new file mode 100644
index 0000000..4193e92
--- /dev/null
+++ b/board/mpl/common/pci_parts.h
@@ -0,0 +1,176 @@
+ /*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _PCI_PARTS_H_
+#define _PCI_PARTS_H_
+
+
+/* Board specific file containing:
+ * - PCI Memory Mapping
+ * - PCI IO Mapping
+ * - PCI Interrupt Mapping
+ */
+
+/* PIP405 PCI INT Routing:
+ * IRQ0 VECTOR
+ * PIXX4 IDSEL = AD16 INTA# 28 (Function 2 USB is INTD# = 31)
+ * VGA IDSEL = AD17 INTB# 29
+ * SCSI IDSEL = AD18 INTC# 30
+ * PC104 IDSEL0 = AD20 INTA# 28
+ * PC104 IDSEL1 = AD21 INTB# 29
+ * PC104 IDSEL2 = AD22 INTC# 30
+ * PC104 IDSEL3 = AD23 INTD# 31
+ *
+ * busdevfunc = EXXX XXXX BBBB BBBB DDDD DFFF RRRR RR00
+ * ^ ^ ^ ^ ^
+ * 31 23 15 10 7
+ * E = Enabled
+ * B = Bussnumber
+ * D = Devicenumber (Device0 = AD10)
+ * F = Functionnumber
+ * R = Registernumber
+ *
+ * Device = (busdevfunc>>11) + 10
+ * Vector = devicenumber % 4 + 28
+ *
+ */
+#define PCI_HIGHEST_ON_BOARD_ID 19
+/*#define PCI_DEV_NUMBER(x) (((x>>11) & 0x1f) + 10) */
+#define PCI_IRQ_VECTOR(x) ((PCI_DEV(x) + 10) % 4) + 28
+
+
+/* PCI Device List for PIP405 */
+
+/* Mapping:
+ * +-------------+------------+------------+--------------------------------+
+ * | PCI MemAddr | PCI IOAddr | Local Addr | Device / Function |
+ * +-------------+------------+------------+--------------------------------+
+ * | 0x00000000 | | 0xA0000000 | ISA Memory (hard wired) |
+ * | 0x00FFFFFF | | 0xA0FFFFFF | |
+ * +-------------+------------+------------+--------------------------------+
+ * | | 0x00000000 | 0xE8000000 | ISA IO (hard wired) |
+ * | | 0x0000FFFF | 0xE800FFFF | |
+ * +-------------+------------+------------+--------------------------------+
+ * | 0x80000000 | | 0x80000000 | VGA Controller Memory |
+ * | 0x80FFFFFF | | 0x80FFFFFF | |
+ * +-------------+------------+------------+--------------------------------+
+ * | 0x81000000 | | 0x81000000 | SCSI Controller Memory |
+ * | 0x81FFFFFF | | 0x81FFFFFF | |
+ * +-------------+------------+------------+--------------------------------+
+ */
+
+struct pci_pip405_config_entry {
+ int index; /* address */
+ unsigned long val; /* value */
+ int width; /* data size */
+};
+
+extern void pci_pip405_write_regs(struct pci_controller *,
+ pci_dev_t,
+ struct pci_config_table *);
+
+/* PIIX4 ISA Bridge Function 0 */
+static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
+ {PCI_CFG_PIIX4_SERIRQ, 0xD0, 1}, /* enable Continous SERIRQ Pin */
+ {PCI_CFG_PIIX4_GENCFG, 0x00018041, 4}, /* enable SERIRQs, ISA, PNP, GPI11 */
+ {PCI_CFG_PIIX4_TOM, 0xFE, 1}, /* Top of Memory */
+ {PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */
+ {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */
+#if defined(CONFIG_PIP405)
+ {PCI_CFG_PIIX4_MBDMA, 0x82, 1}, /* set MBDMA0 to DMA 2 */
+ {PCI_CFG_PIIX4_MBDMA+1, 0x83, 1}, /* set MBDMA1 to DMA 3 */
+#endif
+ {PCI_CFG_PIIX4_DLC, 0x0, 1}, /* disable passive release feature */
+ { } /* end of device table */
+};
+
+/* PIIX4 IDE Controller Function 1 */
+static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
+ {PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */
+ {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
+#if !defined(CONFIG_MIP405T)
+ {PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */
+#else
+ {PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */
+#endif
+ { } /* end of device table */
+};
+
+/* PIIX4 USB Controller Function 2 */
+static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
+#if !defined(CONFIG_MIP405T)
+ {PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */
+ {PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */
+ {PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */
+ {0xC0, 0x2000, 2}, /* Legacy support */
+ {PCI_COMMAND, 0x0005, 2}, /* enable IO access and Master */
+#endif
+ { } /* end of device table */
+};
+
+/* PIIX4 Power Management Function 3 */
+static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
+ {PCI_CFG_PIIX4_PMBA, 0x00004000, 4}, /* set PMBA to "valid" value */
+ {PCI_CFG_PIIX4_SMBBA, 0x00005000, 4}, /* set SMBBA to "valid" value */
+ {PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */
+ {PCI_COMMAND, 0x0001, 2}, /* enable IO access */
+ { } /* end of device table */
+};
+/* PPC405 Dummy only used to prevent autosetup on this host bridge */
+static struct pci_pip405_config_entry ppc405_dummy[] = {
+ { } /* end of device table */
+};
+
+void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
+ struct pci_config_table *entry);
+
+
+static struct pci_config_table pci_pip405_config_table[]={
+ {PCI_VENDOR_ID_IBM, /* 405 dummy */
+ PCI_DEVICE_ID_IBM_405GP,
+ PCI_ANY_ID,
+ PCI_ANY_ID, PCI_ANY_ID, 0,
+ pci_pip405_write_regs, {(unsigned long) ppc405_dummy}},
+
+ {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */
+ PCI_DEVICE_ID_INTEL_82371AB_0,
+ PCI_ANY_ID,
+ PCI_ANY_ID, PCI_ANY_ID, 0,
+ pci_pip405_write_regs, {(unsigned long) piix4_isa_bridge_f0}},
+
+ {PCI_VENDOR_ID_INTEL, /* PIIX4 IDE Controller Function 1 */
+ PCI_DEVICE_ID_INTEL_82371AB,
+ PCI_ANY_ID,
+ PCI_ANY_ID, PCI_ANY_ID, 1,
+ pci_pip405_write_regs, {(unsigned long) piix4_ide_cntrl_f1}},
+
+ {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 2 */
+ PCI_DEVICE_ID_INTEL_82371AB_2,
+ PCI_ANY_ID,
+ PCI_ANY_ID, PCI_ANY_ID, 2,
+ pci_pip405_write_regs, {(unsigned long) piix4_usb_cntrl_f2}},
+
+ {PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 3 */
+ PCI_DEVICE_ID_INTEL_82371AB_3,
+ PCI_ANY_ID,
+ PCI_ANY_ID, PCI_ANY_ID, 3,
+ pci_pip405_write_regs, {(unsigned long) piix4_pmm_cntrl_f3}},
+
+ {PCI_ANY_ID,
+ PCI_ANY_ID,
+ PCI_CLASS_DISPLAY_VGA,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ pci_405gp_setup_vga},
+
+ {PCI_ANY_ID,
+ PCI_ANY_ID,
+ PCI_CLASS_NOT_DEFINED_VGA,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ pci_405gp_setup_vga},
+
+ { }
+};
+#endif /* _PCI_PARTS_H_ */
diff --git a/board/mpl/common/piix4_pci.h b/board/mpl/common/piix4_pci.h
new file mode 100644
index 0000000..c19b64e
--- /dev/null
+++ b/board/mpl/common/piix4_pci.h
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#ifndef _PIIX4_PCI_H
+#define _PIIX4_PCI_H
+
+/***************************************************************************
+* Defines PIIX4 Config Registers
+****************************************************************************/
+
+/* Function 0 ISA Bridge */
+#define PCI_CFG_PIIX4_IORT 0x4C /* 8 bit ISA Recovery Timer Reg (default 0x4D) */
+#define PCI_CFG_PIIX4_XBCS 0x4E /* 16 bit XBus Chip select reg (default 0x0003) */
+#define PCI_CFG_PIIX4_PIRQC 0x60 /* PCI IRQ Route Register 4 x 8bit (default )*/
+#define PCI_CFG_PIIX4_SERIRQ 0x64
+#define PCI_CFG_PIIX4_TOM 0x69
+#define PCI_CFG_PIIX4_MSTAT 0x6A
+#define PCI_CFG_PIIX4_MBDMA 0x76
+#define PCI_CFG_PIIX4_APICBS 0x80
+#define PCI_CFG_PIIX4_DLC 0x82
+#define PCI_CFG_PIIX4_PDMACFG 0x90
+#define PCI_CFG_PIIX4_DDMABS 0x92
+#define PCI_CFG_PIIX4_GENCFG 0xB0
+#define PCI_CFG_PIIX4_RTCCFG 0xCB
+
+/* IO Addresses */
+#define PIIX4_ISA_DMA1_CH0BA 0x00
+#define PIIX4_ISA_DMA1_CH0CA 0x01
+#define PIIX4_ISA_DMA1_CH1BA 0x02
+#define PIIX4_ISA_DMA1_CH1CA 0x03
+#define PIIX4_ISA_DMA1_CH2BA 0x04
+#define PIIX4_ISA_DMA1_CH2CA 0x05
+#define PIIX4_ISA_DMA1_CH3BA 0x06
+#define PIIX4_ISA_DMA1_CH3CA 0x07
+#define PIIX4_ISA_DMA1_CMDST 0x08
+#define PIIX4_ISA_DMA1_REQ 0x09
+#define PIIX4_ISA_DMA1_WSBM 0x0A
+#define PIIX4_ISA_DMA1_CH_MOD 0x0B
+#define PIIX4_ISA_DMA1_CLR_PT 0x0C
+#define PIIX4_ISA_DMA1_M_CLR 0x0D
+#define PIIX4_ISA_DMA1_CLR_M 0x0E
+#define PIIX4_ISA_DMA1_RWAMB 0x0F
+
+#define PIIX4_ISA_DMA2_CH0BA 0xC0
+#define PIIX4_ISA_DMA2_CH0CA 0xC1
+#define PIIX4_ISA_DMA2_CH1BA 0xC2
+#define PIIX4_ISA_DMA2_CH1CA 0xC3
+#define PIIX4_ISA_DMA2_CH2BA 0xC4
+#define PIIX4_ISA_DMA2_CH2CA 0xC5
+#define PIIX4_ISA_DMA2_CH3BA 0xC6
+#define PIIX4_ISA_DMA2_CH3CA 0xC7
+#define PIIX4_ISA_DMA2_CMDST 0xD0
+#define PIIX4_ISA_DMA2_REQ 0xD2
+#define PIIX4_ISA_DMA2_WSBM 0xD4
+#define PIIX4_ISA_DMA2_CH_MOD 0xD6
+#define PIIX4_ISA_DMA2_CLR_PT 0xD8
+#define PIIX4_ISA_DMA2_M_CLR 0xDA
+#define PIIX4_ISA_DMA2_CLR_M 0xDC
+#define PIIX4_ISA_DMA2_RWAMB 0xDE
+
+#define PIIX4_ISA_INT1_ICW1 0x20
+#define PIIX4_ISA_INT1_OCW2 0x20
+#define PIIX4_ISA_INT1_OCW3 0x20
+#define PIIX4_ISA_INT1_ICW2 0x21
+#define PIIX4_ISA_INT1_ICW3 0x21
+#define PIIX4_ISA_INT1_ICW4 0x21
+#define PIIX4_ISA_INT1_OCW1 0x21
+
+#define PIIX4_ISA_INT1_ELCR 0x4D0
+
+#define PIIX4_ISA_INT2_ICW1 0xA0
+#define PIIX4_ISA_INT2_OCW2 0xA0
+#define PIIX4_ISA_INT2_OCW3 0xA0
+#define PIIX4_ISA_INT2_ICW2 0xA1
+#define PIIX4_ISA_INT2_ICW3 0xA1
+#define PIIX4_ISA_INT2_ICW4 0xA1
+#define PIIX4_ISA_INT2_OCW1 0xA1
+#define PIIX4_ISA_INT2_IMR 0xA1 /* read only */
+
+#define PIIX4_ISA_INT2_ELCR 0x4D1
+
+#define PIIX4_ISA_TMR0_CNT_ST 0x40
+#define PIIX4_ISA_TMR1_CNT_ST 0x41
+#define PIIX4_ISA_TMR2_CNT_ST 0x42
+#define PIIX4_ISA_TMR_TCW 0x43
+
+#define PIIX4_ISA_RST_XBUS 0x60
+
+#define PIIX4_ISA_NMI_CNT_ST 0x61
+#define PIIX4_ISA_NMI_ENABLE 0x70
+
+#define PIIX4_ISA_RTC_INDEX 0x70
+#define PIIX4_ISA_RTC_DATA 0x71
+#define PIIX4_ISA_RTCEXT_IND 0x70
+#define PIIX4_ISA_RTCEXT_DATA 0x71
+
+#define PIIX4_ISA_DMA1_CH2LPG 0x81
+#define PIIX4_ISA_DMA1_CH3LPG 0x82
+#define PIIX4_ISA_DMA1_CH1LPG 0x83
+#define PIIX4_ISA_DMA1_CH0LPG 0x87
+#define PIIX4_ISA_DMA2_CH2LPG 0x89
+#define PIIX4_ISA_DMA2_CH3LPG 0x8A
+#define PIIX4_ISA_DMA2_CH1LPG 0x8B
+#define PIIX4_ISA_DMA2_LPGRFR 0x8F
+
+#define PIIX4_ISA_PORT_92 0x92
+
+#define PIIX4_ISA_APM_CONTRL 0xB2
+#define PIIX4_ISA_APM_STATUS 0xB3
+
+#define PIIX4_ISA_COCPU_ERROR 0xF0
+
+/* Function 1 IDE Controller */
+#define PCI_CFG_PIIX4_BMIBA 0x20
+#define PCI_CFG_PIIX4_IDETIM 0x40
+#define PCI_CFG_PIIX4_SIDETIM 0x44
+#define PCI_CFG_PIIX4_UDMACTL 0x48
+#define PCI_CFG_PIIX4_UDMATIM 0x4A
+
+/* Function 2 USB Controller */
+#define PCI_CFG_PIIX4_SBRNUM 0x60
+#define PCI_CFG_PIIX4_LEGSUP 0xC0
+
+/* Function 3 Power Management */
+#define PCI_CFG_PIIX4_PMBA 0x40
+#define PCI_CFG_PIIX4_CNTA 0x44
+#define PCI_CFG_PIIX4_CNTB 0x48
+#define PCI_CFG_PIIX4_GPICTL 0x4C
+#define PCI_CFG_PIIX4_DEVRESD 0x50
+#define PCI_CFG_PIIX4_DEVACTA 0x54
+#define PCI_CFG_PIIX4_DEVACTB 0x58
+#define PCI_CFG_PIIX4_DEVRESA 0x5C
+#define PCI_CFG_PIIX4_DEVRESB 0x60
+#define PCI_CFG_PIIX4_DEVRESC 0x64
+#define PCI_CFG_PIIX4_DEVRESE 0x68
+#define PCI_CFG_PIIX4_DEVRESF 0x6C
+#define PCI_CFG_PIIX4_DEVRESG 0x70
+#define PCI_CFG_PIIX4_DEVRESH 0x74
+#define PCI_CFG_PIIX4_DEVRESI 0x78
+#define PCI_CFG_PIIX4_PMMISC 0x80
+#define PCI_CFG_PIIX4_SMBBA 0x90
+
+
+#endif
diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c
new file mode 100644
index 0000000..5590be1
--- /dev/null
+++ b/board/mpl/common/usb_uhci.c
@@ -0,0 +1,1042 @@
+/*
+ * Part of this code has been derived from linux:
+ * Universal Host Controller Interface driver for USB (take II).
+ *
+ * (c) 1999-2001 Georg Acher, acher@in.tum.de (executive slave) (base guitar)
+ * Deti Fliegl, deti@fliegl.de (executive slave) (lead voice)
+ * Thomas Sailer, sailer@ife.ee.ethz.ch (chief consultant) (cheer leader)
+ * Roman Weissgaerber, weissg@vienna.at (virt root hub) (studio porter)
+ * (c) 2000 Yggdrasil Computing, Inc. (port of new PCI interface support
+ * from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
+ * (C) 2000 David Brownell, david-b@pacbell.net (usb-ohci.c)
+ *
+ * HW-initalization based on material of
+ *
+ * (C) Copyright 1999 Linus Torvalds
+ * (C) Copyright 1999 Johannes Erdfelt
+ * (C) Copyright 1999 Randy Dunlap
+ * (C) Copyright 1999 Gregory P. Smith
+ *
+ *
+ * Adapted for U-Boot:
+ * (C) Copyright 2001 Denis Peter, MPL AG Switzerland
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/**********************************************************************
+ * How it works:
+ * -------------
+ * The framelist / Transfer descriptor / Queue Heads are similar like
+ * in the linux usb_uhci.c.
+ *
+ * During initialization, the following skeleton is allocated in init_skel:
+ *
+ * framespecific | common chain
+ *
+ * framelist[]
+ * [ 0 ]-----> TD ---------\
+ * [ 1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL
+ * ... TD ---------/
+ * [1023]-----> TD --------/
+ *
+ * ^^ ^^ ^^ ^^ ^^
+ * 7 TDs for 1 TD for Start of Start of End Chain
+ * INT (2-128ms) 1ms-INT CTRL Chain BULK Chain
+ *
+ *
+ * Since this is a bootloader, the isochronous transfer descriptor have been removed.
+ *
+ * Interrupt Transfers.
+ * --------------------
+ * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * will be inserted after the appropriate (depending the interval setting) skeleton TD.
+ * If an interrupt has been detected the dev->irqhandler is called. The status and number
+ * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
+ * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned,
+ * the interrupt TD will be reactivated.
+ *
+ * Control Transfers
+ * -----------------
+ * Control Transfers are issued by filling the tmp_td with the appropriate data and connect
+ * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued,
+ * the programm has to wait for completion. This does not allows asynchronous data transfer.
+ *
+ * Bulk Transfers
+ * --------------
+ * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect
+ * them to the qh_bulk queue header. Before other control/bulk transfers can be issued,
+ * the programm has to wait for completion. This does not allows asynchronous data transfer.
+ *
+ *
+ */
+
+#include <common.h>
+#include <pci.h>
+
+#ifdef CONFIG_USB_UHCI
+
+#include <usb.h>
+#include "usb_uhci.h"
+
+#define USB_MAX_TEMP_TD 128 /* number of temporary TDs for bulk and control transfers */
+#define USB_MAX_TEMP_INT_TD 32 /* number of temporary TDs for Interrupt transfers */
+
+
+#undef USB_UHCI_DEBUG
+
+#ifdef USB_UHCI_DEBUG
+#define USB_UHCI_PRINTF(fmt,args...) printf (fmt ,##args)
+#else
+#define USB_UHCI_PRINTF(fmt,args...)
+#endif
+
+
+static int irqvec = -1; /* irq vector, if -1 uhci is stopped / reseted */
+unsigned int usb_base_addr; /* base address */
+
+static uhci_td_t td_int[8]; /* Interrupt Transfer descriptors */
+static uhci_qh_t qh_cntrl; /* control Queue Head */
+static uhci_qh_t qh_bulk; /* bulk Queue Head */
+static uhci_qh_t qh_end; /* end Queue Head */
+static uhci_td_t td_last; /* last TD (linked with end chain) */
+
+/* temporary tds */
+static uhci_td_t tmp_td[USB_MAX_TEMP_TD]; /* temporary bulk/control td's */
+static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD]; /* temporary interrupt td's */
+
+static unsigned long framelist[1024] __attribute__ ((aligned (0x1000))); /* frame list */
+
+static struct virt_root_hub rh; /* struct for root hub */
+
+/**********************************************************************
+ * some forward decleration
+ */
+int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len,struct devrequest *setup);
+
+/* fill a td with the approproiate data. Link, status, info and buffer
+ * are used by the USB controller itselfes, dev is used to identify the
+ * "connected" device
+ */
+void usb_fill_td(uhci_td_t* td,unsigned long link,unsigned long status,
+ unsigned long info, unsigned long buffer, unsigned long dev)
+{
+ td->link=swap_32(link);
+ td->status=swap_32(status);
+ td->info=swap_32(info);
+ td->buffer=swap_32(buffer);
+ td->dev_ptr=dev;
+}
+
+/* fill a qh with the approproiate data. Head and element are used by the USB controller
+ * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh.
+ * Please note, that after completion of the td chain, the entry element is removed /
+ * marked invalid by the USB controller.
+ */
+void usb_fill_qh(uhci_qh_t* qh,unsigned long head,unsigned long element)
+{
+ qh->head=swap_32(head);
+ qh->element=swap_32(element);
+ qh->dev_ptr=0L;
+}
+
+/* get the status of a td->status
+ */
+unsigned long usb_uhci_td_stat(unsigned long status)
+{
+ unsigned long result=0;
+ result |= (status & TD_CTRL_NAK) ? USB_ST_NAK_REC : 0;
+ result |= (status & TD_CTRL_STALLED) ? USB_ST_STALLED : 0;
+ result |= (status & TD_CTRL_DBUFERR) ? USB_ST_BUF_ERR : 0;
+ result |= (status & TD_CTRL_BABBLE) ? USB_ST_BABBLE_DET : 0;
+ result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0;
+ result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0;
+ result |= (status & TD_CTRL_ACTIVE) ? USB_ST_NOT_PROC : 0;
+ return result;
+}
+
+/* get the status and the transfered len of a td chain.
+ * called from the completion handler
+ */
+int usb_get_td_status(uhci_td_t *td,struct usb_device *dev)
+{
+ unsigned long temp,info;
+ unsigned long stat;
+ uhci_td_t *mytd=td;
+
+ if(dev->devnum==rh.devnum)
+ return 0;
+ dev->act_len=0;
+ stat=0;
+ do {
+ temp=swap_32((unsigned long)mytd->status);
+ stat=usb_uhci_td_stat(temp);
+ info=swap_32((unsigned long)mytd->info);
+ if(((info & 0xff)!= USB_PID_SETUP) &&
+ (((info >> 21) & 0x7ff)!= 0x7ff) &&
+ (temp & 0x7FF)!=0x7ff)
+ { /* if not setup and not null data pack */
+ dev->act_len+=(temp & 0x7FF) + 1; /* the transfered len is act_len + 1 */
+ }
+ if(stat) { /* status no ok */
+ dev->status=stat;
+ return -1;
+ }
+ temp=swap_32((unsigned long)mytd->link);
+ mytd=(uhci_td_t *)(temp & 0xfffffff0);
+ }while((temp & 0x1)==0); /* process all TDs */
+ dev->status=stat;
+ return 0; /* Ok */
+}
+
+
+/*-------------------------------------------------------------------
+ * LOW LEVEL STUFF
+ * assembles QHs und TDs for control, bulk and iso
+ *-------------------------------------------------------------------*/
+
+/* Submits a control message. That is a Setup, Data and Status transfer.
+ * Routine does not wait for completion.
+ */
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len,struct devrequest *setup)
+{
+ unsigned long destination, status;
+ int maxsze = usb_maxpacket(dev, pipe);
+ unsigned long dataptr;
+ int len;
+ int pktsze;
+ int i=0;
+
+ if (!maxsze) {
+ USB_UHCI_PRINTF("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", pipe);
+ return -1;
+ }
+ if(((pipe>>8)&0x7f)==rh.devnum) {
+ /* this is the root hub -> redirect it */
+ return uhci_submit_rh_msg(dev,pipe,buffer,transfer_len,setup);
+ }
+ USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",transfer_len,maxsze);
+ /* The "pipe" thing contains the destination in bits 8--18 */
+ destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */
+ /* 3 errors */
+ status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
+ /* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */
+ /* Build the TD for the control request, try forever, 8 bytes of data */
+ usb_fill_td(&tmp_td[i],UHCI_PTR_TERM ,status, destination | (7 << 21),(unsigned long)setup,(unsigned long)dev);
+#if 0
+ {
+ char *sp=(char *)setup;
+ printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe,
+ sp[0],sp[1],sp[2],sp[3],sp[4],sp[5],sp[6],sp[7]);
+ }
+#endif
+ dataptr = (unsigned long)buffer;
+ len=transfer_len;
+
+ /* If direction is "send", change the frame from SETUP (0x2D)
+ to OUT (0xE1). Else change it from SETUP to IN (0x69). */
+ destination = (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN)==0 ? USB_PID_OUT : USB_PID_IN);
+ while (len > 0) {
+ /* data stage */
+ pktsze = len;
+ i++;
+ if (pktsze > maxsze)
+ pktsze = maxsze;
+ destination ^= 1 << TD_TOKEN_TOGGLE; /* toggle DATA0/1 */
+ usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21),dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */
+ tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
+
+ dataptr += pktsze;
+ len -= pktsze;
+ }
+
+ /* Build the final TD for control status */
+ /* It's only IN if the pipe is out AND we aren't expecting data */
+
+ destination &= ~UHCI_PID;
+ if (((pipe & USB_DIR_IN)==0) || (transfer_len == 0))
+ destination |= USB_PID_IN;
+ else
+ destination |= USB_PID_OUT;
+ destination |= 1 << TD_TOKEN_TOGGLE; /* End in Data1 */
+ i++;
+ status &=~TD_CTRL_SPD;
+ /* no limit on errors on final packet , 0 bytes of data */
+ usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status | TD_CTRL_IOC, destination | (UHCI_NULL_DATA_SIZE << 21),0,(unsigned long)dev);
+ tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]); /* queue status td */
+ /* usb_show_td(i+1);*/
+ USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n",i);
+ /* first mark the control QH element terminated */
+ qh_cntrl.element=0xffffffffL;
+ /* set qh active */
+ qh_cntrl.dev_ptr=(unsigned long)dev;
+ /* fill in tmp_td_chain */
+ qh_cntrl.element=swap_32((unsigned long)&tmp_td[0]);
+ return 0;
+}
+
+/*-------------------------------------------------------------------
+ * Prepare TDs for bulk transfers.
+ */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len)
+{
+ unsigned long destination, status,info;
+ unsigned long dataptr;
+ int maxsze = usb_maxpacket(dev, pipe);
+ int len;
+ int i=0;
+
+ if(transfer_len < 0) {
+ printf("Negative transfer length in submit_bulk\n");
+ return -1;
+ }
+ if (!maxsze)
+ return -1;
+ /* The "pipe" thing contains the destination in bits 8--18. */
+ destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe);
+ /* 3 errors */
+ status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
+ /* ((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */
+ /* Build the TDs for the bulk request */
+ len = transfer_len;
+ dataptr = (unsigned long)buffer;
+ do {
+ int pktsze = len;
+ if (pktsze > maxsze)
+ pktsze = maxsze;
+ /* pktsze bytes of data */
+ info = destination | (((pktsze - 1)&UHCI_NULL_DATA_SIZE) << 21) |
+ (usb_gettoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)) << TD_TOKEN_TOGGLE);
+
+ if((len-pktsze)==0)
+ status |= TD_CTRL_IOC; /* last one generates INT */
+
+ usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, info,dataptr,(unsigned long)dev); /* Status, pktsze bytes of data */
+ if(i>0)
+ tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
+ i++;
+ dataptr += pktsze;
+ len -= pktsze;
+ usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
+ } while (len > 0);
+ /* first mark the bulk QH element terminated */
+ qh_bulk.element=0xffffffffL;
+ /* set qh active */
+ qh_bulk.dev_ptr=(unsigned long)dev;
+ /* fill in tmp_td_chain */
+ qh_bulk.element=swap_32((unsigned long)&tmp_td[0]);
+ return 0;
+}
+
+
+/* search a free interrupt td
+ */
+uhci_td_t *uhci_alloc_int_td(void)
+{
+ int i;
+ for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
+ if(tmp_int_td[i].dev_ptr==0) /* no device assigned -> free TD */
+ return &tmp_int_td[i];
+ }
+ return NULL;
+}
+
+#if 0
+void uhci_show_temp_int_td(void)
+{
+ int i;
+ for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
+ if((tmp_int_td[i].dev_ptr&0x01)!=0x1L) /* no device assigned -> free TD */
+ printf("temp_td %d is assigned to dev %lx\n",i,tmp_int_td[i].dev_ptr);
+ }
+ printf("all others temp_tds are free\n");
+}
+#endif
+/*-------------------------------------------------------------------
+ * submits USB interrupt (ie. polling ;-)
+ */
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len, int interval)
+{
+ int nint, n;
+ unsigned long status, destination;
+ unsigned long info,tmp;
+ uhci_td_t *mytd;
+ if (interval < 0 || interval >= 256)
+ return -1;
+
+ if (interval == 0)
+ nint = 0;
+ else {
+ for (nint = 0, n = 1; nint <= 8; nint++, n += n) /* round interval down to 2^n */
+ {
+ if(interval < n) {
+ interval = n / 2;
+ break;
+ }
+ }
+ nint--;
+ }
+
+ USB_UHCI_PRINTF("Rounded interval to %i, chain %i\n", interval, nint);
+ mytd=uhci_alloc_int_td();
+ if(mytd==NULL) {
+ printf("No free INT TDs found\n");
+ return -1;
+ }
+ status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27);
+/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27);
+*/
+
+ destination =(pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe) | (((transfer_len - 1) & 0x7ff) << 21);
+
+ info = destination | (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << TD_TOKEN_TOGGLE);
+ tmp = swap_32(td_int[nint].link);
+ usb_fill_td(mytd,tmp,status, info,(unsigned long)buffer,(unsigned long)dev);
+ /* Link it */
+ tmp = swap_32((unsigned long)mytd);
+ td_int[nint].link=tmp;
+
+ usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
+
+ return 0;
+}
+
+/**********************************************************************
+ * Low Level functions
+ */
+
+
+void reset_hc(void)
+{
+
+ /* Global reset for 100ms */
+ out16r( usb_base_addr + USBPORTSC1,0x0204);
+ out16r( usb_base_addr + USBPORTSC2,0x0204);
+ out16r( usb_base_addr + USBCMD,USBCMD_GRESET | USBCMD_RS);
+ /* Turn off all interrupts */
+ out16r(usb_base_addr + USBINTR,0);
+ mdelay(50);
+ out16r( usb_base_addr + USBCMD,0);
+ mdelay(10);
+}
+
+void start_hc(void)
+{
+ int timeout = 1000;
+
+ while(in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) {
+ if (!--timeout) {
+ printf("USBCMD_HCRESET timed out!\n");
+ break;
+ }
+ }
+ /* Turn on all interrupts */
+ out16r(usb_base_addr + USBINTR,USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP);
+ /* Start at frame 0 */
+ out16r(usb_base_addr + USBFRNUM,0);
+ /* set Framebuffer base address */
+ out32r(usb_base_addr+USBFLBASEADD,(unsigned long)&framelist);
+ /* Run and mark it configured with a 64-byte max packet */
+ out16r(usb_base_addr + USBCMD,USBCMD_RS | USBCMD_CF | USBCMD_MAXP);
+}
+
+/* Initialize the skeleton
+ */
+void usb_init_skel(void)
+{
+ unsigned long temp;
+ int n;
+
+ for(n=0;n<USB_MAX_TEMP_INT_TD;n++)
+ tmp_int_td[n].dev_ptr=0L; /* no devices connected */
+ /* last td */
+ usb_fill_td(&td_last,UHCI_PTR_TERM,TD_CTRL_IOC ,0,0,0L);
+ /* usb_fill_td(&td_last,UHCI_PTR_TERM,0,0,0); */
+ /* End Queue Header */
+ usb_fill_qh(&qh_end,UHCI_PTR_TERM,(unsigned long)&td_last);
+ /* Bulk Queue Header */
+ temp=(unsigned long)&qh_end;
+ usb_fill_qh(&qh_bulk,temp | UHCI_PTR_QH,UHCI_PTR_TERM);
+ /* Control Queue Header */
+ temp=(unsigned long)&qh_bulk;
+ usb_fill_qh(&qh_cntrl, temp | UHCI_PTR_QH,UHCI_PTR_TERM);
+ /* 1ms Interrupt td */
+ temp=(unsigned long)&qh_cntrl;
+ usb_fill_td(&td_int[0],temp | UHCI_PTR_QH,0,0,0,0L);
+ temp=(unsigned long)&td_int[0];
+ for(n=1; n<8; n++)
+ usb_fill_td(&td_int[n],temp,0,0,0,0L);
+ for (n = 0; n < 1024; n++) {
+ /* link all framelist pointers to one of the interrupts */
+ int m, o;
+ if ((n&127)==127)
+ framelist[n]= swap_32((unsigned long)&td_int[0]);
+ else
+ for (o = 1, m = 2; m <= 128; o++, m += m)
+ if ((n & (m - 1)) == ((m - 1) / 2))
+ framelist[n]= swap_32((unsigned long)&td_int[o]);
+ }
+}
+
+/* check the common skeleton for completed transfers, and update the status
+ * of the "connected" device. Called from the IRQ routine.
+ */
+void usb_check_skel(void)
+{
+ struct usb_device *dev;
+ /* start with the control qh */
+ if(qh_cntrl.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
+ {
+ dev=(struct usb_device *)qh_cntrl.dev_ptr;
+ usb_get_td_status(&tmp_td[0],dev); /* update status */
+ if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
+ qh_cntrl.dev_ptr=0;
+ }
+ }
+ /* now process the bulk */
+ if(qh_bulk.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
+ {
+ dev=(struct usb_device *)qh_bulk.dev_ptr;
+ usb_get_td_status(&tmp_td[0],dev); /* update status */
+ if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
+ qh_bulk.dev_ptr=0;
+ }
+ }
+}
+
+/* check the interrupt chain, ubdate the status of the appropriate device,
+ * call the appropriate irqhandler and reactivate the TD if the irqhandler
+ * returns with 1
+ */
+void usb_check_int_chain(void)
+{
+ int i,res;
+ unsigned long link,status;
+ struct usb_device *dev;
+ uhci_td_t *td,*prevtd;
+
+ for(i=0;i<8;i++) {
+ prevtd = &td_int[i]; /* the first previous td is the skeleton td */
+ link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */
+ td=(uhci_td_t *)link; /* assign it */
+ /* all interrupt TDs are finally linked to the td_int[0].
+ * so we process all until we find the td_int[0].
+ * if int0 chain points to a QH, we're also done
+ */
+ while(((i>0) && (link != (unsigned long)&td_int[0])) ||
+ ((i==0) && !(swap_32(td->link) & UHCI_PTR_QH)))
+ {
+ /* check if a device is assigned with this td */
+ status=swap_32(td->status);
+ if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) {
+ /* td is not active and a device is assigned -> call irqhandler */
+ dev=(struct usb_device *)td->dev_ptr;
+ dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transfered length */
+ dev->irq_status=usb_uhci_td_stat(status); /* get status */
+ res=dev->irq_handle(dev); /* call irqhandler */
+ if(res==1) {
+ /* reactivate */
+ status|=TD_CTRL_ACTIVE;
+ td->status=swap_32(status);
+ prevtd=td; /* previous td = this td */
+ }
+ else {
+ prevtd->link=td->link; /* link previous td directly to the nex td -> unlinked */
+ /* remove device pointer */
+ td->dev_ptr=0L;
+ }
+ } /* if we call the irq handler */
+ link=swap_32(td->link) & 0xfffffff0; /* next in chain */
+ td=(uhci_td_t *)link; /* assign it */
+ } /* process all td in this int chain */
+ } /* next interrupt chain */
+}
+
+
+/* usb interrupt service routine.
+ */
+void handle_usb_interrupt(void)
+{
+ unsigned short status;
+
+ /*
+ * Read the interrupt status, and write it back to clear the
+ * interrupt cause
+ */
+
+ status = in16r(usb_base_addr + USBSTS);
+
+ if (!status) /* shared interrupt, not mine */
+ return;
+ if (status != 1) {
+ /* remove host controller halted state */
+ if ((status&0x20) && ((in16r(usb_base_addr+USBCMD) && USBCMD_RS)==0)) {
+ out16r(usb_base_addr + USBCMD, USBCMD_RS | in16r(usb_base_addr + USBCMD));
+ }
+ }
+ usb_check_int_chain(); /* call interrupt handlers for int tds */
+ usb_check_skel(); /* call completion handler for common transfer routines */
+ out16r(usb_base_addr+USBSTS,status);
+}
+
+
+/* init uhci
+ */
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
+{
+ unsigned char temp;
+ int busdevfunc;
+
+ busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */
+ if(busdevfunc==-1) {
+ printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID);
+ return -1;
+ }
+ pci_read_config_byte(busdevfunc,PCI_INTERRUPT_LINE,&temp);
+ irqvec = temp;
+ irq_free_handler(irqvec);
+ USB_UHCI_PRINTF("Interrupt Line = %d, is %d\n",irqvec);
+ pci_read_config_byte(busdevfunc,PCI_INTERRUPT_PIN,&temp);
+ USB_UHCI_PRINTF("Interrupt Pin = %ld\n",temp);
+ pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr);
+ USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr);
+ usb_base_addr&=0xFFFFFFF0;
+ usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS;
+ rh.devnum = 0;
+ usb_init_skel();
+ reset_hc();
+ start_hc();
+ irq_install_handler(irqvec, (interrupt_handler_t *)handle_usb_interrupt, NULL);
+ return 0;
+}
+
+/* stop uhci
+ */
+int usb_lowlevel_stop(int index)
+{
+ if(irqvec==-1)
+ return 1;
+ irq_free_handler(irqvec);
+ reset_hc();
+ irqvec = -1;
+ return 0;
+}
+
+/*******************************************************************************************
+ * Virtual Root Hub
+ * Since the uhci does not have a real HUB, we simulate one ;-)
+ */
+#undef USB_RH_DEBUG
+
+#ifdef USB_RH_DEBUG
+#define USB_RH_PRINTF(fmt,args...) printf (fmt ,##args)
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex);
+static void usb_display_Req(unsigned short req);
+#else
+#define USB_RH_PRINTF(fmt,args...)
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {}
+static void usb_display_Req(unsigned short req) {}
+#endif
+
+#define WANT_USB_ROOT_HUB_HUB_DES
+#include <usbroothubdes.h>
+#undef WANT_USB_ROOT_HUB_HUB_DES
+
+/*
+ * Root Hub Control Pipe (interrupt Pipes are not supported)
+ */
+
+
+int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len,struct devrequest *cmd)
+{
+ void *data = buffer;
+ int leni = transfer_len;
+ int len = 0;
+ int status = 0;
+ int stat = 0;
+ int i;
+
+ unsigned short cstatus;
+
+ unsigned short bmRType_bReq;
+ unsigned short wValue;
+ unsigned short wIndex;
+ unsigned short wLength;
+
+ if (usb_pipeint(pipe)) {
+ printf("Root-Hub submit IRQ: NOT implemented\n");
+#if 0
+ uhci->rh.urb = urb;
+ uhci->rh.send = 1;
+ uhci->rh.interval = urb->interval;
+ rh_init_int_timer (urb);
+#endif
+ return 0;
+ }
+ bmRType_bReq = cmd->requesttype | cmd->request << 8;
+ wValue = swap_16(cmd->value);
+ wIndex = swap_16(cmd->index);
+ wLength = swap_16(cmd->length);
+ usb_display_Req(bmRType_bReq);
+ for (i = 0; i < 8; i++)
+ rh.c_p_r[i] = 0;
+ USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n",
+ dev->devnum, 8, cmd->requesttype,cmd->request, wValue, wIndex, wLength);
+
+ switch (bmRType_bReq) {
+ /* Request Destination:
+ without flags: Device,
+ RH_INTERFACE: interface,
+ RH_ENDPOINT: endpoint,
+ RH_CLASS means HUB here,
+ RH_OTHER | RH_CLASS almost ever means HUB_PORT here
+ */
+
+ case RH_GET_STATUS:
+ *(unsigned short *) data = swap_16(1);
+ len=2;
+ break;
+ case RH_GET_STATUS | RH_INTERFACE:
+ *(unsigned short *) data = swap_16(0);
+ len=2;
+ break;
+ case RH_GET_STATUS | RH_ENDPOINT:
+ *(unsigned short *) data = swap_16(0);
+ len=2;
+ break;
+ case RH_GET_STATUS | RH_CLASS:
+ *(unsigned long *) data = swap_32(0);
+ len=4;
+ break; /* hub power ** */
+ case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+
+ status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1));
+ cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) |
+ ((status & USBPORTSC_PEC) >> (3 - 1)) |
+ (rh.c_p_r[wIndex - 1] << (0 + 4));
+ status = (status & USBPORTSC_CCS) |
+ ((status & USBPORTSC_PE) >> (2 - 1)) |
+ ((status & USBPORTSC_SUSP) >> (12 - 2)) |
+ ((status & USBPORTSC_PR) >> (9 - 4)) |
+ (1 << 8) | /* power on ** */
+ ((status & USBPORTSC_LSDA) << (-8 + 9));
+
+ *(unsigned short *) data = swap_16(status);
+ *(unsigned short *) (data + 2) = swap_16(cstatus);
+ len=4;
+ break;
+ case RH_CLEAR_FEATURE | RH_ENDPOINT:
+ switch (wValue) {
+ case (RH_ENDPOINT_STALL):
+ len=0;
+ break;
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_CLASS:
+ switch (wValue) {
+ case (RH_C_HUB_OVER_CURRENT):
+ len=0; /* hub power over current ** */
+ break;
+ }
+ break;
+
+ case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+ usb_display_wValue(wValue,wIndex);
+ switch (wValue) {
+ case (RH_PORT_ENABLE):
+ status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+ status = (status & 0xfff5) & ~USBPORTSC_PE;
+ out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+ len=0;
+ break;
+ case (RH_PORT_SUSPEND):
+ status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+ status = (status & 0xfff5) & ~USBPORTSC_SUSP;
+ out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+ len=0;
+ break;
+ case (RH_PORT_POWER):
+ len=0; /* port power ** */
+ break;
+ case (RH_C_PORT_CONNECTION):
+ status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+ status = (status & 0xfff5) | USBPORTSC_CSC;
+ out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+ len=0;
+ break;
+ case (RH_C_PORT_ENABLE):
+ status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+ status = (status & 0xfff5) | USBPORTSC_PEC;
+ out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+ len=0;
+ break;
+ case (RH_C_PORT_SUSPEND):
+/*** WR_RH_PORTSTAT(RH_PS_PSSC); */
+ len=0;
+ break;
+ case (RH_C_PORT_OVER_CURRENT):
+ len=0;
+ break;
+ case (RH_C_PORT_RESET):
+ rh.c_p_r[wIndex - 1] = 0;
+ len=0;
+ break;
+ }
+ break;
+ case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+ usb_display_wValue(wValue,wIndex);
+ switch (wValue) {
+ case (RH_PORT_SUSPEND):
+ status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+ status = (status & 0xfff5) | USBPORTSC_SUSP;
+ out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+ len=0;
+ break;
+ case (RH_PORT_RESET):
+ status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+ status = (status & 0xfff5) | USBPORTSC_PR;
+ out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+ mdelay(10);
+ status = (status & 0xfff5) & ~USBPORTSC_PR;
+ out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+ udelay(10);
+ status = (status & 0xfff5) | USBPORTSC_PE;
+ out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+ mdelay(10);
+ status = (status & 0xfff5) | 0xa;
+ out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+ len=0;
+ break;
+ case (RH_PORT_POWER):
+ len=0; /* port power ** */
+ break;
+ case (RH_PORT_ENABLE):
+ status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+ status = (status & 0xfff5) | USBPORTSC_PE;
+ out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+ len=0;
+ break;
+ }
+ break;
+
+ case RH_SET_ADDRESS:
+ rh.devnum = wValue;
+ len=0;
+ break;
+ case RH_GET_DESCRIPTOR:
+ switch ((wValue & 0xff00) >> 8) {
+ case (0x01): /* device descriptor */
+ i=sizeof(root_hub_config_des);
+ status=i > wLength ? wLength : i;
+ len = leni > status ? status : leni;
+ memcpy (data, root_hub_dev_des, len);
+ break;
+ case (0x02): /* configuration descriptor */
+ i=sizeof(root_hub_config_des);
+ status=i > wLength ? wLength : i;
+ len = leni > status ? status : leni;
+ memcpy (data, root_hub_config_des, len);
+ break;
+ case (0x03): /*string descriptors */
+ if(wValue==0x0300) {
+ i=sizeof(root_hub_str_index0);
+ status = i > wLength ? wLength : i;
+ len = leni > status ? status : leni;
+ memcpy (data, root_hub_str_index0, len);
+ break;
+ }
+ if(wValue==0x0301) {
+ i=sizeof(root_hub_str_index1);
+ status = i > wLength ? wLength : i;
+ len = leni > status ? status : leni;
+ memcpy (data, root_hub_str_index1, len);
+ break;
+ }
+ stat = USB_ST_STALLED;
+ }
+ break;
+
+ case RH_GET_DESCRIPTOR | RH_CLASS:
+ root_hub_hub_des[2] = 2;
+ i=sizeof(root_hub_hub_des);
+ status= i > wLength ? wLength : i;
+ len = leni > status ? status : leni;
+ memcpy (data, root_hub_hub_des, len);
+ break;
+ case RH_GET_CONFIGURATION:
+ *(unsigned char *) data = 0x01;
+ len = 1;
+ break;
+ case RH_SET_CONFIGURATION:
+ len=0;
+ break;
+ default:
+ stat = USB_ST_STALLED;
+ }
+ USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n",stat,
+ in16r(usb_base_addr + USBPORTSC1), in16r(usb_base_addr + USBPORTSC2));
+ dev->act_len=len;
+ dev->status=stat;
+ return stat;
+
+}
+
+/********************************************************************************
+ * Some Debug Routines
+ */
+
+#ifdef USB_RH_DEBUG
+
+static void usb_display_Req(unsigned short req)
+{
+ USB_RH_PRINTF("- Root-Hub Request: ");
+ switch (req) {
+ case RH_GET_STATUS:
+ USB_RH_PRINTF("Get Status ");
+ break;
+ case RH_GET_STATUS | RH_INTERFACE:
+ USB_RH_PRINTF("Get Status Interface ");
+ break;
+ case RH_GET_STATUS | RH_ENDPOINT:
+ USB_RH_PRINTF("Get Status Endpoint ");
+ break;
+ case RH_GET_STATUS | RH_CLASS:
+ USB_RH_PRINTF("Get Status Class");
+ break; /* hub power ** */
+ case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+ USB_RH_PRINTF("Get Status Class Others");
+ break;
+ case RH_CLEAR_FEATURE | RH_ENDPOINT:
+ USB_RH_PRINTF("Clear Feature Endpoint ");
+ break;
+ case RH_CLEAR_FEATURE | RH_CLASS:
+ USB_RH_PRINTF("Clear Feature Class ");
+ break;
+ case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+ USB_RH_PRINTF("Clear Feature Other Class ");
+ break;
+ case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+ USB_RH_PRINTF("Set Feature Other Class ");
+ break;
+ case RH_SET_ADDRESS:
+ USB_RH_PRINTF("Set Address ");
+ break;
+ case RH_GET_DESCRIPTOR:
+ USB_RH_PRINTF("Get Descriptor ");
+ break;
+ case RH_GET_DESCRIPTOR | RH_CLASS:
+ USB_RH_PRINTF("Get Descriptor Class ");
+ break;
+ case RH_GET_CONFIGURATION:
+ USB_RH_PRINTF("Get Configuration ");
+ break;
+ case RH_SET_CONFIGURATION:
+ USB_RH_PRINTF("Get Configuration ");
+ break;
+ default:
+ USB_RH_PRINTF("****UNKNOWN**** 0x%04X ",req);
+ }
+ USB_RH_PRINTF("\n");
+
+}
+
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex)
+{
+ switch (wValue) {
+ case (RH_PORT_ENABLE):
+ USB_RH_PRINTF("Root-Hub: Enable Port %d\n",wIndex);
+ break;
+ case (RH_PORT_SUSPEND):
+ USB_RH_PRINTF("Root-Hub: Suspend Port %d\n",wIndex);
+ break;
+ case (RH_PORT_POWER):
+ USB_RH_PRINTF("Root-Hub: Port Power %d\n",wIndex);
+ break;
+ case (RH_C_PORT_CONNECTION):
+ USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n",wIndex);
+ break;
+ case (RH_C_PORT_ENABLE):
+ USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n",wIndex);
+ break;
+ case (RH_C_PORT_SUSPEND):
+ USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n",wIndex);
+ break;
+ case (RH_C_PORT_OVER_CURRENT):
+ USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",wIndex);
+ break;
+ case (RH_C_PORT_RESET):
+ USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n",wIndex);
+ break;
+ default:
+ USB_RH_PRINTF("Root-Hub: unknown %x %x\n",wValue,wIndex);
+ break;
+ }
+}
+
+#endif
+
+
+#ifdef USB_UHCI_DEBUG
+
+static int usb_display_td(uhci_td_t *td)
+{
+ unsigned long tmp;
+ int valid;
+
+ printf("TD at %p:\n",td);
+
+ tmp=swap_32(td->link);
+ printf("Link points to 0x%08lX, %s first, %s, %s\n",tmp&0xfffffff0,
+ ((tmp & 0x4)==0x4) ? "Depth" : "Breath",
+ ((tmp & 0x2)==0x2) ? "QH" : "TD",
+ ((tmp & 0x1)==0x1) ? "invalid" : "valid");
+ valid=((tmp & 0x1)==0x0);
+ tmp=swap_32(td->status);
+ printf(" %s %ld Errors %s %s %s \n %s %s %s %s %s %s\n Len 0x%lX\n",
+ (((tmp>>29)&0x1)==0x1) ? "SPD Enable" : "SPD Disable",
+ ((tmp>>28)&0x3),
+ (((tmp>>26)&0x1)==0x1) ? "Low Speed" : "Full Speed",
+ (((tmp>>25)&0x1)==0x1) ? "ISO " : "",
+ (((tmp>>24)&0x1)==0x1) ? "IOC " : "",
+ (((tmp>>23)&0x1)==0x1) ? "Active " : "Inactive ",
+ (((tmp>>22)&0x1)==0x1) ? "Stalled" : "",
+ (((tmp>>21)&0x1)==0x1) ? "Data Buffer Error" : "",
+ (((tmp>>20)&0x1)==0x1) ? "Babble" : "",
+ (((tmp>>19)&0x1)==0x1) ? "NAK" : "",
+ (((tmp>>18)&0x1)==0x1) ? "Bitstuff Error" : "",
+ (tmp&0x7ff));
+ tmp=swap_32(td->info);
+ printf(" MaxLen 0x%lX\n",((tmp>>21)&0x7FF));
+ printf(" %s Endpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",((tmp>>19)&0x1)==0x1 ? "TOGGLE" : "",
+ ((tmp>>15)&0xF),((tmp>>8)&0x7F),tmp&0xFF);
+ tmp=swap_32(td->buffer);
+ printf(" Buffer 0x%08lX\n",tmp);
+ printf(" DEV %08lX\n",td->dev_ptr);
+ return valid;
+}
+
+
+void usb_show_td(int max)
+{
+ int i;
+ if(max>0) {
+ for(i=0;i<max;i++) {
+ usb_display_td(&tmp_td[i]);
+ }
+ }
+ else {
+ i=0;
+ do {
+ printf("tmp_td[%d]\n",i);
+ }while(usb_display_td(&tmp_td[i++]));
+ }
+}
+
+
+#endif
+#endif /* CONFIG_USB_UHCI */
+
+/* EOF */
diff --git a/board/mpl/common/usb_uhci.h b/board/mpl/common/usb_uhci.h
new file mode 100644
index 0000000..582015f
--- /dev/null
+++ b/board/mpl/common/usb_uhci.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Note: Part of this code has been derived from linux
+ */
+#ifndef _USB_UHCI_H_
+#define _USB_UHCI_H_
+
+
+/* Command register */
+#define USBCMD 0
+#define USBCMD_RS 0x0001 /* Run/Stop */
+#define USBCMD_HCRESET 0x0002 /* Host reset */
+#define USBCMD_GRESET 0x0004 /* Global reset */
+#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
+#define USBCMD_FGR 0x0010 /* Force Global Resume */
+#define USBCMD_SWDBG 0x0020 /* SW Debug mode */
+#define USBCMD_CF 0x0040 /* Config Flag (sw only) */
+#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
+
+/* Status register */
+#define USBSTS 2
+#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
+#define USBSTS_ERROR 0x0002 /* Interrupt due to error */
+#define USBSTS_RD 0x0004 /* Resume Detect */
+#define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */
+#define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */
+#define USBSTS_HCH 0x0020 /* HC Halted */
+
+/* Interrupt enable register */
+#define USBINTR 4
+#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
+#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
+#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
+#define USBINTR_SP 0x0008 /* Short packet interrupt enable */
+
+#define USBFRNUM 6
+#define USBFLBASEADD 8
+#define USBSOF 12
+
+/* USB port status and control registers */
+#define USBPORTSC1 16
+#define USBPORTSC2 18
+#define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */
+#define USBPORTSC_CSC 0x0002 /* Connect Status Change */
+#define USBPORTSC_PE 0x0004 /* Port Enable */
+#define USBPORTSC_PEC 0x0008 /* Port Enable Change */
+#define USBPORTSC_LS 0x0030 /* Line Status */
+#define USBPORTSC_RD 0x0040 /* Resume Detect */
+#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
+#define USBPORTSC_PR 0x0200 /* Port Reset */
+#define USBPORTSC_SUSP 0x1000 /* Suspend */
+
+/* Legacy support register */
+#define USBLEGSUP 0xc0
+#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
+
+#define UHCI_NULL_DATA_SIZE 0x7ff /* for UHCI controller TD */
+#define UHCI_PID 0xff /* PID MASK */
+
+#define UHCI_PTR_BITS 0x000F
+#define UHCI_PTR_TERM 0x0001
+#define UHCI_PTR_QH 0x0002
+#define UHCI_PTR_DEPTH 0x0004
+
+/* for TD <status>: */
+#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
+#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
+#define TD_CTRL_LS (1 << 26) /* Low Speed Device */
+#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
+#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
+#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
+#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
+#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
+#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
+#define TD_CTRL_NAK (1 << 19) /* NAK Received */
+#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
+#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
+#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */
+
+#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
+ TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
+
+#define TD_TOKEN_TOGGLE 19
+
+/* ------------------------------------------------------------------------------------
+ Virtual Root HUB
+ ------------------------------------------------------------------------------------ */
+/* destination of request */
+#define RH_INTERFACE 0x01
+#define RH_ENDPOINT 0x02
+#define RH_OTHER 0x03
+
+#define RH_CLASS 0x20
+#define RH_VENDOR 0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS 0x0080
+#define RH_CLEAR_FEATURE 0x0100
+#define RH_SET_FEATURE 0x0300
+#define RH_SET_ADDRESS 0x0500
+#define RH_GET_DESCRIPTOR 0x0680
+#define RH_SET_DESCRIPTOR 0x0700
+#define RH_GET_CONFIGURATION 0x0880
+#define RH_SET_CONFIGURATION 0x0900
+#define RH_GET_STATE 0x0280
+#define RH_GET_INTERFACE 0x0A80
+#define RH_SET_INTERFACE 0x0B00
+#define RH_SYNC_FRAME 0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP 0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION 0x00
+#define RH_PORT_ENABLE 0x01
+#define RH_PORT_SUSPEND 0x02
+#define RH_PORT_OVER_CURRENT 0x03
+#define RH_PORT_RESET 0x04
+#define RH_PORT_POWER 0x08
+#define RH_PORT_LOW_SPEED 0x09
+#define RH_C_PORT_CONNECTION 0x10
+#define RH_C_PORT_ENABLE 0x11
+#define RH_C_PORT_SUSPEND 0x12
+#define RH_C_PORT_OVER_CURRENT 0x13
+#define RH_C_PORT_RESET 0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER 0x00
+#define RH_C_HUB_OVER_CURRENT 0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP 0x00
+#define RH_ENDPOINT_STALL 0x01
+
+/* Our Vendor Specific feature */
+#define RH_REMOVE_EP 0x00
+
+
+#define RH_ACK 0x01
+#define RH_REQ_ERR -1
+#define RH_NACK 0x00
+
+
+/* Transfer descriptor structure */
+typedef struct {
+ unsigned long link; /* next td/qh (LE)*/
+ unsigned long status; /* status of the td */
+ unsigned long info; /* Max Lenght / Endpoint / device address and PID */
+ unsigned long buffer; /* pointer to data buffer (LE) */
+ unsigned long dev_ptr; /* pointer to the assigned device (BE) */
+ unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */
+} uhci_td_t, *puhci_td_t;
+
+/* Queue Header structure */
+typedef struct {
+ unsigned long head; /* Next QH (LE)*/
+ unsigned long element; /* Queue element pointer (LE) */
+ unsigned long res[5]; /* reserved */
+ unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */
+} uhci_qh_t, *puhci_qh_t;
+
+struct virt_root_hub {
+ int devnum; /* Address of Root Hub endpoint */
+ int numports; /* number of ports */
+ int c_p_r[8]; /* C_PORT_RESET */
+};
+
+
+#endif /* _USB_UHCI_H_ */
diff --git a/board/mpl/mip405/Kconfig b/board/mpl/mip405/Kconfig
new file mode 100644
index 0000000..48ba91a
--- /dev/null
+++ b/board/mpl/mip405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MIP405
+
+config SYS_BOARD
+ default "mip405"
+
+config SYS_VENDOR
+ default "mpl"
+
+config SYS_CONFIG_NAME
+ default "MIP405"
+
+endif
diff --git a/board/mpl/mip405/MAINTAINERS b/board/mpl/mip405/MAINTAINERS
new file mode 100644
index 0000000..b323e5a
--- /dev/null
+++ b/board/mpl/mip405/MAINTAINERS
@@ -0,0 +1,7 @@
+MIP405 BOARD
+M: Denis Peter <d.peter@mpl.ch>
+S: Maintained
+F: board/mpl/mip405/
+F: include/configs/MIP405.h
+F: configs/MIP405_defconfig
+F: configs/MIP405T_defconfig
diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile
new file mode 100644
index 0000000..5bcf130
--- /dev/null
+++ b/board/mpl/mip405/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = mip405.o cmd_mip405.o \
+ ../common/pci.o \
+ ../common/usb_uhci.o \
+ ../common/common_util.o
+obj-y += init.o
diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c
new file mode 100644
index 0000000..ca6f0af
--- /dev/null
+++ b/board/mpl/mip405/cmd_mip405.c
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * hacked for MIP405
+ */
+
+#include <common.h>
+#include <command.h>
+#include "mip405.h"
+#include "../common/common_util.h"
+
+
+extern void print_mip405_info(void);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+
+/* ------------------------------------------------------------------------- */
+
+int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+
+ ulong led_on;
+
+ if (strcmp(argv[1], "info") == 0)
+ {
+ print_mip405_info();
+ return 0;
+ }
+ if (strcmp(argv[1], "led") == 0)
+ {
+ led_on = (ulong)simple_strtoul(argv[2], NULL, 10);
+ user_led0(led_on);
+ return 0;
+ }
+ return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+U_BOOT_CMD(
+ mip405, 8, 1, do_mip405,
+ "MIP405 specific Cmds",
+ "flash mem [SrcAddr] - updates U-Boot with image in memory\n"
+ "mip405 flash mps - updates U-Boot with image from MPS\n"
+ "mip405 info - displays board information\n"
+ "mip405 led <on> - switches LED on (on=1) or off (on=0)"
+);
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S
new file mode 100644
index 0000000..2ea2e29
--- /dev/null
+++ b/board/mpl/mip405/init.S
@@ -0,0 +1,200 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0 IBM-pibs
+ */
+/*-----------------------------------------------------------------------------
+ * Function: ext_bus_cntlr_init
+ * Description: Initializes the External Bus Controller for the external
+ * peripherals. IMPORTANT: For pass1 this code must run from
+ * cache since you can not reliably change a peripheral banks
+ * timing register (pbxap) while running code from that bank.
+ * For ex., since we are running from ROM on bank 0, we can NOT
+ * execute the code that modifies bank 0 timings from ROM, so
+ * we run it from cache.
+ * Bank 0 - Flash or Multi Purpose Socket
+ * Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
+ * Bank 2 - UART 1 (set in C-Code)
+ * Bank 3 - UART 2 (set in C-Code)
+ * Bank 4 - not used
+ * Bank 5 - not used
+ * Bank 6 - not used
+ * Bank 7 - PLD Register
+ *-----------------------------------------------------------------------------*/
+
+#include <configs/MIP405.h>
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+#include "mip405.h"
+
+
+ .globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+ mflr r4 /* save link register */
+ mfdcr r3,CPC0_PSR /* get strapping reg */
+ andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
+ bnelr /* jump back if PCI boot */
+
+ bl ..getAddr
+..getAddr:
+ mflr r3 /* get address of ..getAddr */
+ mtlr r4 /* restore link register */
+ addi r4,0,14 /* set ctr to 14; used to prefetch */
+ mtctr r4 /* 14 cache lines to fit this function */
+ /* in cache (gives us 8x14=112 instrctns) */
+..ebcloop:
+ icbt r0,r3 /* prefetch cache line for addr in r3 */
+ addi r3,r3,32 /* move to next cache line */
+ bdnz ..ebcloop /* continue for 14 cache lines */
+
+ /*-------------------------------------------------------------------
+ * Delay to ensure all accesses to ROM are complete before changing
+ * bank 0 timings.
+ *------------------------------------------------------------------- */
+ addis r3,0,0x0
+ ori r3,r3,0xA000
+ mtctr r3
+..spinlp:
+ bdnz ..spinlp /* spin loop */
+
+ /*-----------------------------------------------------------------------
+ * decide boot up mode
+ *----------------------------------------------------------------------- */
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
+ mfdcr r4,EBC0_CFGDATA
+
+ andi. r0, r4, 0x2000 /* mask out irrelevant bits */
+ beq 0f /* jump if 8 bit bus width */
+
+ /* setup 16 bit things
+ *-----------------------------------------------------------------------
+ * Memory Bank 0 (16 Bit Flash) initialization
+ *---------------------------------------------------------------------- */
+
+ addi r4,0,PB1AP
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,(FLASH_AP_B)@h
+ ori r4,r4,(FLASH_AP_B)@l
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
+ /* BS=0x010(4MB),BU=0x3(R/W), */
+ addis r4,0,(FLASH_CR_B)@h
+ ori r4,r4,(FLASH_CR_B)@l
+ mtdcr EBC0_CFGDATA,r4
+ b 1f
+
+0:
+
+ /* 8Bit boot mode: */
+ /*-----------------------------------------------------------------------
+ * Memory Bank 0 Multi Purpose Socket initialization
+ *----------------------------------------------------------------------- */
+ /* 0x7F8FFE80 slowest boot */
+ addi r4,0,PB1AP
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,(MPS_AP_B)@h
+ ori r4,r4,(MPS_AP_B)@l
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
+ /* BS=0x010(4MB),BU=0x3(R/W), */
+ addis r4,0,(MPS_CR_B)@h
+ ori r4,r4,(MPS_CR_B)@l
+
+ mtdcr EBC0_CFGDATA,r4
+
+
+1:
+ /*-----------------------------------------------------------------------
+ * Memory Bank 2-3-4-5-6 (not used) initialization
+ *-----------------------------------------------------------------------*/
+ addi r4,0,PB1CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB2CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB3CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB4CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB5CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB6CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB7CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+ nop /* pass2 DCR errata #8 */
+ blr
+
+#if defined(CONFIG_BOOT_PCI)
+ .section .bootpg,"ax"
+ .globl _start_pci
+/*******************************************
+ */
+
+_start_pci:
+ /* first handle errata #68 / PCI_18 */
+ iccci r0, r0 /* invalidate I-cache */
+ lis r31, 0
+ mticcr r31 /* ICCR = 0 (all uncachable) */
+ isync
+
+ mfccr0 r28 /* set CCR0[24] = 1 */
+ ori r28, r28, 0x0080
+ mtccr0 r28
+
+ /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
+ lis r28, 0xEF40
+ addi r28, r28, 0x0004
+ stw r31, 0x0C(r28) /* clear PMM0PCIHA */
+ lis r29, 0xFFF8 /* open 512 kByte */
+ addi r29, r29, 0x0001/* and enable this region */
+ stwbrx r29, r0, r28 /* write PMM0MA */
+
+ lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
+ addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
+
+ lis r31, 0x8000 /* set en bit bus 0 */
+ ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
+ stwbrx r31, r0, r28 /* write it */
+
+ lwbrx r31, r0, r29 /* load XBCS register */
+ oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
+ stwbrx r31, r0, r29 /* write back XBCS register */
+
+ nop
+ nop
+ b _start /* normal start */
+#endif
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
new file mode 100644
index 0000000..4a0d696
--- /dev/null
+++ b/board/mpl/mip405/mip405.c
@@ -0,0 +1,803 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * TODO: clean-up
+ */
+
+/*
+ * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
+ *
+ * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
+ * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
+ * parameters from the datasheet are:
+ * Tclk = 7.5ns (CL = 2)
+ * Trp = 15ns
+ * Trc = 60ns
+ * Trcd = 15ns
+ * Trfc = 66ns
+ *
+ * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
+ * period is 10ns and the parameters needed for the Timing Register are:
+ * CASL = CL = 2 clock cycles
+ * PTA = Trp = 15ns / 10ns = 2 clock cycles
+ * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
+ * LDF = 2 clock cycles (but can be extended to meet board-level timing)
+ * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
+ * RCD = Trcd = 15ns / 10ns= 2 clock cycles
+ *
+ * The actual bit settings in the register would be:
+ *
+ * CASL = 0b01
+ * PTA = 0b01
+ * CTP = 0b10
+ * LDF = 0b01
+ * RFTA = 0b011
+ * RCD = 0b01
+ *
+ * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
+ * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
+ * defined as Trc rather than Trfc.
+ * When using DIMM modules, most but not all of the required timing parameters can be read
+ * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
+ * are not available from the EEPROM
+ */
+
+#include <common.h>
+#include "mip405.h"
+#include <asm/processor.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc4xx-i2c.h>
+#include <miiphy.h>
+#include "../common/common_util.h"
+#include <stdio_dev.h>
+#include <i2c.h>
+#include <rtc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef SDRAM_DEBUG
+#define ENABLE_ECC /* for ecc boards */
+
+/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
+#ifndef __ldiv_t_defined
+typedef struct {
+ long int quot; /* Quotient */
+ long int rem; /* Remainder */
+} ldiv_t;
+extern ldiv_t ldiv (long int __numer, long int __denom);
+# define __ldiv_t_defined 1
+#endif
+
+
+#define PLD_PART_REG PER_PLD_ADDR + 0
+#define PLD_VERS_REG PER_PLD_ADDR + 1
+#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
+#define PLD_IRQ_REG PER_PLD_ADDR + 3
+#define PLD_COM_MODE_REG PER_PLD_ADDR + 4
+#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
+
+#define MEGA_BYTE (1024*1024)
+
+typedef struct {
+ unsigned char boardtype; /* Board revision and Population Options */
+ unsigned char cal; /* cas Latency (will be programmend as cal-1) */
+ unsigned char trp; /* datain27 in clocks */
+ unsigned char trcd; /* datain29 in clocks */
+ unsigned char tras; /* datain30 in clocks */
+ unsigned char tctp; /* tras - trcd in clocks */
+ unsigned char am; /* Address Mod (will be programmed as am-1) */
+ unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
+ unsigned char ecc; /* if true, ecc is enabled */
+} sdram_t;
+#if defined(CONFIG_MIP405T)
+const sdram_t sdram_table[] = {
+ { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
+ 3, /* Case Latenty = 3 */
+ 3, /* trp 20ns / 7.5 ns datain[27] */
+ 3, /* trcd 20ns /7.5 ns (datain[29]) */
+ 6, /* tras 44ns /7.5 ns (datain[30]) */
+ 4, /* tcpt 44 - 20ns = 24ns */
+ 2, /* Address Mode = 2 (12x9x4) */
+ 3, /* size value (32MByte) */
+ 0}, /* ECC disabled */
+ { 0xff, /* terminator */
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff }
+};
+#else
+const sdram_t sdram_table[] = {
+ { 0x0f, /* Rev A, 128MByte -1 Board */
+ 3, /* Case Latenty = 3 */
+ 3, /* trp 20ns / 7.5 ns datain[27] */
+ 3, /* trcd 20ns /7.5 ns (datain[29]) */
+ 6, /* tras 44ns /7.5 ns (datain[30]) */
+ 4, /* tcpt 44 - 20ns = 24ns */
+ 3, /* Address Mode = 3 */
+ 5, /* size value */
+ 1}, /* ECC enabled */
+ { 0x07, /* Rev A, 64MByte -2 Board */
+ 3, /* Case Latenty = 3 */
+ 3, /* trp 20ns / 7.5 ns datain[27] */
+ 3, /* trcd 20ns /7.5 ns (datain[29]) */
+ 6, /* tras 44ns /7.5 ns (datain[30]) */
+ 4, /* tcpt 44 - 20ns = 24ns */
+ 2, /* Address Mode = 2 */
+ 4, /* size value */
+ 1}, /* ECC enabled */
+ { 0x03, /* Rev A, 128MByte -4 Board */
+ 3, /* Case Latenty = 3 */
+ 3, /* trp 20ns / 7.5 ns datain[27] */
+ 3, /* trcd 20ns /7.5 ns (datain[29]) */
+ 6, /* tras 44ns /7.5 ns (datain[30]) */
+ 4, /* tcpt 44 - 20ns = 24ns */
+ 3, /* Address Mode = 3 */
+ 5, /* size value */
+ 1}, /* ECC enabled */
+ { 0x1f, /* Rev B, 128MByte -3 Board */
+ 3, /* Case Latenty = 3 */
+ 3, /* trp 20ns / 7.5 ns datain[27] */
+ 3, /* trcd 20ns /7.5 ns (datain[29]) */
+ 6, /* tras 44ns /7.5 ns (datain[30]) */
+ 4, /* tcpt 44 - 20ns = 24ns */
+ 3, /* Address Mode = 3 */
+ 5, /* size value */
+ 1}, /* ECC enabled */
+ { 0x2f, /* Rev C, 128MByte -3 Board */
+ 3, /* Case Latenty = 3 */
+ 3, /* trp 20ns / 7.5 ns datain[27] */
+ 3, /* trcd 20ns /7.5 ns (datain[29]) */
+ 6, /* tras 44ns /7.5 ns (datain[30]) */
+ 4, /* tcpt 44 - 20ns = 24ns */
+ 3, /* Address Mode = 3 */
+ 5, /* size value */
+ 1}, /* ECC enabled */
+ { 0xff, /* terminator */
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff }
+};
+#endif /*CONFIG_MIP405T */
+void SDRAM_err (const char *s)
+{
+#ifndef SDRAM_DEBUG
+ (void) get_clocks ();
+ gd->baudrate = 9600;
+ serial_init ();
+#endif
+ serial_puts ("\n");
+ serial_puts (s);
+ serial_puts ("\n enable SDRAM_DEBUG for more info\n");
+ for (;;);
+}
+
+
+unsigned char get_board_revcfg (void)
+{
+ out8 (PER_BOARD_ADDR, 0);
+ return (in8 (PER_BOARD_ADDR));
+}
+
+
+#ifdef SDRAM_DEBUG
+
+void write_hex (unsigned char i)
+{
+ char cc;
+
+ cc = i >> 4;
+ cc &= 0xf;
+ if (cc > 9)
+ serial_putc (cc + 55);
+ else
+ serial_putc (cc + 48);
+ cc = i & 0xf;
+ if (cc > 9)
+ serial_putc (cc + 55);
+ else
+ serial_putc (cc + 48);
+}
+
+void write_4hex (unsigned long val)
+{
+ write_hex ((unsigned char) (val >> 24));
+ write_hex ((unsigned char) (val >> 16));
+ write_hex ((unsigned char) (val >> 8));
+ write_hex ((unsigned char) val);
+}
+
+#endif
+
+
+int init_sdram (void)
+{
+ unsigned long tmp, baseaddr;
+ unsigned short i;
+ unsigned char trp_clocks,
+ trcd_clocks,
+ tras_clocks,
+ trc_clocks;
+ unsigned char cal_val;
+ unsigned char bc;
+ unsigned long sdram_tim, sdram_bank;
+
+ /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/
+ (void) get_clocks ();
+ gd->baudrate = 9600;
+ serial_init ();
+ /* set up the pld */
+ mtdcr (EBC0_CFGADDR, PB7AP);
+ mtdcr (EBC0_CFGDATA, PLD_AP);
+ mtdcr (EBC0_CFGADDR, PB7CR);
+ mtdcr (EBC0_CFGDATA, PLD_CR);
+ /* THIS IS OBSOLETE */
+ /* set up the board rev reg*/
+ mtdcr (EBC0_CFGADDR, PB5AP);
+ mtdcr (EBC0_CFGDATA, BOARD_AP);
+ mtdcr (EBC0_CFGADDR, PB5CR);
+ mtdcr (EBC0_CFGDATA, BOARD_CR);
+#ifdef SDRAM_DEBUG
+ /* get all informations from PLD */
+ serial_puts ("\nPLD Part 0x");
+ bc = in8 (PLD_PART_REG);
+ write_hex (bc);
+ serial_puts ("\nPLD Vers 0x");
+ bc = in8 (PLD_VERS_REG);
+ write_hex (bc);
+ serial_puts ("\nBoard Rev 0x");
+ bc = in8 (PLD_BOARD_CFG_REG);
+ write_hex (bc);
+ serial_puts ("\n");
+#endif
+ /* check board */
+ bc = in8 (PLD_PART_REG);
+#if defined(CONFIG_MIP405T)
+ if((bc & 0x80)==0)
+ SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
+#else
+ if((bc & 0x80)==0x80)
+ SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
+#endif
+ /* set-up the chipselect machine */
+ mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */
+ tmp = mfdcr (EBC0_CFGDATA);
+ if ((tmp & 0x00002000) == 0) {
+ /* MPS Boot, set up the flash */
+ mtdcr (EBC0_CFGADDR, PB1AP);
+ mtdcr (EBC0_CFGDATA, FLASH_AP);
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ mtdcr (EBC0_CFGDATA, FLASH_CR);
+ } else {
+ /* Flash boot, set up the MPS */
+ mtdcr (EBC0_CFGADDR, PB1AP);
+ mtdcr (EBC0_CFGDATA, MPS_AP);
+ mtdcr (EBC0_CFGADDR, PB1CR);
+ mtdcr (EBC0_CFGDATA, MPS_CR);
+ }
+ /* set up UART0 (CS2) and UART1 (CS3) */
+ mtdcr (EBC0_CFGADDR, PB2AP);
+ mtdcr (EBC0_CFGDATA, UART0_AP);
+ mtdcr (EBC0_CFGADDR, PB2CR);
+ mtdcr (EBC0_CFGDATA, UART0_CR);
+ mtdcr (EBC0_CFGADDR, PB3AP);
+ mtdcr (EBC0_CFGDATA, UART1_AP);
+ mtdcr (EBC0_CFGADDR, PB3CR);
+ mtdcr (EBC0_CFGDATA, UART1_CR);
+ bc = in8 (PLD_BOARD_CFG_REG);
+#ifdef SDRAM_DEBUG
+ serial_puts ("\nstart SDRAM Setup\n");
+ serial_puts ("\nBoard Rev: ");
+ write_hex (bc);
+ serial_puts ("\n");
+#endif
+ i = 0;
+ baseaddr = CONFIG_SYS_SDRAM_BASE;
+ while (sdram_table[i].sz != 0xff) {
+ if (sdram_table[i].boardtype == bc)
+ break;
+ i++;
+ }
+ if (sdram_table[i].boardtype != bc)
+ SDRAM_err ("No SDRAM table found for this board!!!\n");
+#ifdef SDRAM_DEBUG
+ serial_puts (" found table ");
+ write_hex (i);
+ serial_puts (" \n");
+#endif
+ /* since the ECC initialisation needs some time,
+ * we show that we're alive
+ */
+ if (sdram_table[i].ecc)
+ serial_puts ("\nInitializing SDRAM, Please stand by");
+ cal_val = sdram_table[i].cal - 1; /* Cas Latency */
+ trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
+ trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
+ tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
+ /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
+ /* trc_clocks is sum of trp_clocks + tras_clocks */
+ trc_clocks = trp_clocks + tras_clocks;
+ /* get SDRAM timing register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+ sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
+ /* insert CASL value */
+ sdram_tim |= ((unsigned long) (cal_val)) << 23;
+ /* insert PTA value */
+ sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
+ /* insert CTP value */
+ sdram_tim |=
+ ((unsigned long) (trc_clocks - trp_clocks -
+ trcd_clocks)) << 16;
+ /* insert LDF (always 01) */
+ sdram_tim |= ((unsigned long) 0x01) << 14;
+ /* insert RFTA value */
+ sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
+ /* insert RCD value */
+ sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
+
+ tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
+ /* insert SZ value; */
+ tmp |= ((unsigned long) sdram_table[i].sz << 17);
+ /* get SDRAM bank 0 register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
+ sdram_bank |= (baseaddr | tmp | 0x01);
+
+#ifdef SDRAM_DEBUG
+ serial_puts ("sdtr: ");
+ write_4hex (sdram_tim);
+ serial_puts ("\n");
+#endif
+
+ /* write SDRAM timing register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+ mtdcr (SDRAM0_CFGDATA, sdram_tim);
+
+#ifdef SDRAM_DEBUG
+ serial_puts ("mb0cf: ");
+ write_4hex (sdram_bank);
+ serial_puts ("\n");
+#endif
+
+ /* write SDRAM bank 0 register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ mtdcr (SDRAM0_CFGDATA, sdram_bank);
+
+ if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
+ /* get SDRAM refresh interval register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+ tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
+ tmp |= 0x07F00000;
+ } else {
+ /* get SDRAM refresh interval register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+ tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
+ tmp |= 0x05F00000;
+ }
+ /* write SDRAM refresh interval register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+ mtdcr (SDRAM0_CFGDATA, tmp);
+ /* enable ECC if used */
+#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
+ if (sdram_table[i].ecc) {
+ /* disable checking for all banks */
+ unsigned long *p;
+#ifdef SDRAM_DEBUG
+ serial_puts ("disable ECC.. ");
+#endif
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+ tmp = mfdcr (SDRAM0_CFGDATA);
+ tmp &= 0xff0fffff; /* disable all banks */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+ /* set up SDRAM Controller with ECC enabled */
+#ifdef SDRAM_DEBUG
+ serial_puts ("setup SDRAM Controller.. ");
+#endif
+ mtdcr (SDRAM0_CFGDATA, tmp);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ mtdcr (SDRAM0_CFGDATA, tmp);
+ udelay (600);
+#ifdef SDRAM_DEBUG
+ serial_puts ("fill the memory..\n");
+#endif
+ serial_puts (".");
+ /* now, fill all the memory */
+ tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
+ p = (unsigned long) 0;
+ while ((unsigned long) p < tmp) {
+ *p++ = 0L;
+ if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
+ serial_puts (".");
+ }
+ /* enable bank 0 */
+ serial_puts (".");
+#ifdef SDRAM_DEBUG
+ serial_puts ("enable ECC\n");
+#endif
+ udelay (400);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+ tmp = mfdcr (SDRAM0_CFGDATA);
+ tmp |= 0x00800000; /* enable bank 0 */
+ mtdcr (SDRAM0_CFGDATA, tmp);
+ udelay (400);
+ } else
+#endif
+ {
+ /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ mtdcr (SDRAM0_CFGDATA, tmp);
+ udelay (400);
+ }
+ serial_puts ("\n");
+ return (0);
+}
+
+int board_early_init_f (void)
+{
+ init_sdram ();
+
+ /*-------------------------------------------------------------------------+
+ | Interrupt controller setup for the PIP405 board.
+ | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
+ | IRQ 16 405GP internally generated; active low; level sensitive
+ | IRQ 17-24 RESERVED
+ | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
+ | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
+ | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
+ | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+ | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+ | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+ | Note for MIP405 board:
+ | An interrupt taken for the SouthBridge (IRQ 25) indicates that
+ | the Interrupt Controller in the South Bridge has caused the
+ | interrupt. The IC must be read to determine which device
+ | caused the interrupt.
+ |
+ +-------------------------------------------------------------------------*/
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
+ mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ int mode;
+
+ /*
+ * since we are relocated, we can finally enable i-cache
+ * and set up the flash CS correctly
+ */
+ icache_enable();
+ setup_cs_reloc();
+ /* get and display boot mode */
+ mode = get_boot_mode();
+ if (mode & BOOT_PCI)
+ printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ?
+ "MPS" : "Flash");
+ else
+ printf("%s Boot\n", (mode & BOOT_MPS) ?
+ "MPS" : "Flash");
+
+ return 0;
+}
+
+/*
+ * Get some PLD Registers
+ */
+
+unsigned short get_pld_parvers (void)
+{
+ unsigned short result;
+ unsigned char rc;
+
+ rc = in8 (PLD_PART_REG);
+ result = (unsigned short) rc << 8;
+ rc = in8 (PLD_VERS_REG);
+ result |= rc;
+ return result;
+}
+
+
+void user_led0 (unsigned char on)
+{
+ if (on)
+ out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
+ else
+ out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
+}
+
+
+void ide_set_reset (int idereset)
+{
+ /* if reset = 1 IDE reset will be asserted */
+ if (idereset)
+ out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
+ else {
+ udelay (10000);
+ out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
+ }
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
+{
+#if !defined(CONFIG_MIP405T)
+ unsigned char bc,rc,tmp;
+ int i;
+
+ bc = in8 (PLD_BOARD_CFG_REG);
+ tmp = ~bc;
+ tmp &= 0xf;
+ rc = 0;
+ for (i = 0; i < 4; i++) {
+ rc <<= 1;
+ rc += (tmp & 0x1);
+ tmp >>= 1;
+ }
+ rc++;
+ if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */
+ || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */
+ && (rc==0x1)) /* Population Option 1 is a -3 */
+ rc=3;
+ *pcbrev=(bc >> 4) & 0xf;
+ *var=rc;
+#else
+ unsigned char bc;
+ bc = in8 (PLD_BOARD_CFG_REG);
+ *pcbrev=(bc >> 4) & 0xf;
+ *var=16-(bc & 0xf);
+#endif
+}
+
+/*
+ * Check Board Identity:
+ */
+/* serial String: "MIP405_1000" OR "MIP405T_1000" */
+#if !defined(CONFIG_MIP405T)
+#define BOARD_NAME "MIP405"
+#else
+#define BOARD_NAME "MIP405T"
+#endif
+
+int checkboard (void)
+{
+ char s[50];
+ unsigned char bc, var;
+ int i;
+ backup_t *b = (backup_t *) s;
+
+ puts ("Board: ");
+ get_pcbrev_var(&bc,&var);
+ i = getenv_f("serial#", (char *)s, 32);
+ if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
+ get_backup_values (b);
+ if (strncmp (b->signature, "MPL\0", 4) != 0) {
+ puts ("### No HW ID - assuming " BOARD_NAME);
+ printf ("-%d Rev %c", var, 'A' + bc);
+ } else {
+ b->serial_name[sizeof(BOARD_NAME)-1] = 0;
+ printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
+ 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
+ }
+ } else {
+ s[sizeof(BOARD_NAME)-1] = 0;
+ printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
+ &s[sizeof(BOARD_NAME)]);
+ }
+ bc = in8 (PLD_EXT_CONF_REG);
+ printf (" Boot Config: 0x%x\n", bc);
+ return (0);
+}
+
+
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+/*
+ initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ the necessary info for SDRAM controller configuration
+*/
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+static int test_dram (unsigned long ramsize);
+
+phys_size_t initdram (int board_type)
+{
+
+ unsigned long bank_reg[4], tmp, bank_size;
+ int i;
+ unsigned long TotalSize;
+
+ /* since the DRAM controller is allready set up, calculate the size with the
+ bank registers */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+ bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+ bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+ bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
+ TotalSize = 0;
+ for (i = 0; i < 4; i++) {
+ if ((bank_reg[i] & 0x1) == 0x1) {
+ tmp = (bank_reg[i] >> 17) & 0x7;
+ bank_size = 4 << tmp;
+ TotalSize += bank_size;
+ }
+ }
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
+ tmp = mfdcr (SDRAM0_CFGDATA);
+
+ if (!tmp)
+ printf ("No ");
+ printf ("ECC ");
+
+ test_dram (TotalSize * MEGA_BYTE);
+ return (TotalSize * MEGA_BYTE);
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+static int test_dram (unsigned long ramsize)
+{
+#ifdef SDRAM_DEBUG
+ mem_test (0L, ramsize, 1);
+#endif
+ /* not yet implemented */
+ return (1);
+}
+
+/* used to check if the time in RTC is valid */
+static unsigned long start;
+static struct rtc_time tm;
+
+int misc_init_r (void)
+{
+ /* adjust flash start and size as well as the offset */
+ gd->bd->bi_flashstart=0-flash_info[0].size;
+ gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
+ gd->bd->bi_flashoffset=0;
+
+ /* check, if RTC is running */
+ rtc_get (&tm);
+ start=get_timer(0);
+ /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
+ if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
+ mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
+
+ return (0);
+}
+
+
+void print_mip405_rev (void)
+{
+ unsigned char part, vers, pcbrev, var;
+
+ get_pcbrev_var(&pcbrev,&var);
+ part = in8 (PLD_PART_REG);
+ vers = in8 (PLD_VERS_REG);
+ printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
+ var, pcbrev + 'A', part & 0x7F, vers);
+}
+
+
+extern int mk_date (char *, struct rtc_time *);
+
+int last_stage_init (void)
+{
+ unsigned long stop;
+ struct rtc_time newtm;
+ char *s;
+
+ /* write correct LED configuration */
+ if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
+ printf ("Error writing to the PHY\n");
+ }
+ /* since LED/CFG2 is not connected on the -2,
+ * write to correct capability information */
+ if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
+ printf ("Error writing to the PHY\n");
+ }
+ print_mip405_rev ();
+ stdio_print_current_devices ();
+ check_env ();
+ /* check if RTC time is valid */
+ stop=get_timer(start);
+ while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */
+ udelay(1000);
+ stop=get_timer(start);
+ }
+ rtc_get (&newtm);
+ if(tm.tm_sec==newtm.tm_sec) {
+ s=getenv("defaultdate");
+ if(!s)
+ mk_date ("010112001970", &newtm);
+ else
+ if(mk_date (s, &newtm)!=0) {
+ printf("RTC: Bad date format in defaultdate\n");
+ return 0;
+ }
+ rtc_reset ();
+ rtc_set(&newtm);
+ }
+ return 0;
+}
+
+/***************************************************************************
+ * some helping routines
+ */
+
+int overwrite_console (void)
+{
+ /* return true if console should be overwritten */
+ return ((in8(PLD_EXT_CONF_REG) & 0x1) == 0);
+}
+
+
+/************************************************************************
+* Print MIP405 Info
+************************************************************************/
+void print_mip405_info (void)
+{
+ unsigned char part, vers, cfg, irq_reg, com_mode, ext;
+
+ part = in8 (PLD_PART_REG);
+ vers = in8 (PLD_VERS_REG);
+ cfg = in8 (PLD_BOARD_CFG_REG);
+ irq_reg = in8 (PLD_IRQ_REG);
+ com_mode = in8 (PLD_COM_MODE_REG);
+ ext = in8 (PLD_EXT_CONF_REG);
+
+ printf ("PLD Part %d version %d\n", part & 0x7F, vers);
+ printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
+ printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
+ (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
+ printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
+ printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
+#if !defined(CONFIG_MIP405T)
+ printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
+ (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
+ (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
+ (ext >> 6) & 0x1, (ext >> 7) & 0x1);
+ printf ("SER1 uses handshakes %s\n",
+ (ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
+#else
+ printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
+ (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
+ (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
+ (ext >> 6) & 0x1,(ext >> 7) & 0x1);
+#endif
+ printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
+ printf ("IRQs:\n");
+ printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
+#if !defined(CONFIG_MIP405T)
+ printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
+ printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
+#endif
+ printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
+ printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
+ printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");
+}
diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h
new file mode 100644
index 0000000..b1f69aa
--- /dev/null
+++ b/board/mpl/mip405/mip405.h
@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+ /****************************************************************************
+ * Global routines used for MIP405
+ *****************************************************************************/
+#ifndef __ASSEMBLY__
+/*int switch_cs(unsigned char boot);*/
+
+extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
+
+void user_led0(unsigned char on);
+
+
+#endif
+/* timings */
+/* PLD (CS7) */
+#define PLD_BME 0 /* Burst disable */
+#define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
+#define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define PLD_OEN 1 /* Cycles from CS low to OE low */
+#define PLD_WBN 1 /* Cycles from CS low to WE low */
+#define PLD_WBF 1 /* Cycles from WE high to CS high */
+#define PLD_TH 2 /* Number of hold cycles after transfer */
+#define PLD_RE 0 /* Ready disabled */
+#define PLD_SOR 1 /* Sample on Ready disabled */
+#define PLD_BEM 0 /* Byte Write only active on Write cycles */
+#define PLD_PEN 0 /* Parity disable */
+#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
+ (PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define PLD_BS 0 /* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define PLD_BU 3 /* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define PLD_BW 0 /* 16Bit */
+#define PLD_CR ((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13))
+
+
+/* timings */
+
+#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
+/* Dummy CS to get the board revision */
+#define BOARD_BME 0 /* Burst disable */
+#define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
+#define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define BOARD_OEN 1 /* Cycles from CS low to OE low */
+#define BOARD_WBN 1 /* Cycles from CS low to WE low */
+#define BOARD_WBF 1 /* Cycles from WE high to CS high */
+#define BOARD_TH 2 /* Number of hold cycles after transfer */
+#define BOARD_RE 0 /* Ready disabled */
+#define BOARD_SOR 1 /* Sample on Ready disabled */
+#define BOARD_BEM 0 /* Byte Write only active on Write cycles */
+#define BOARD_PEN 0 /* Parity disable */
+#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
+ (BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define BOARD_BS 0 /* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define BOARD_BU 3 /* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define BOARD_BW 0 /* 16Bit */
+#define BOARD_CR ((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13))
+
+
+/* UART0 CS2 */
+#define UART0_BME 0 /* Burst disable */
+#define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
+#define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define UART0_OEN 1 /* Cycles from CS low to OE low */
+#define UART0_WBN 1 /* Cycles from CS low to WE low */
+#define UART0_WBF 1 /* Cycles from WE high to CS high */
+#define UART0_TH 2 /* Number of hold cycles after transfer */
+#define UART0_RE 0 /* Ready disabled */
+#define UART0_SOR 1 /* Sample on Ready disabled */
+#define UART0_BEM 0 /* Byte Write only active on Write cycles */
+#define UART0_PEN 0 /* Parity disable */
+#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
+ (UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define UART0_BS 0 /* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define UART0_BU 3 /* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define UART0_BW 0 /* 8Bit */
+#define UART0_CR ((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
+
+/* UART1 CS3 */
+#define UART1_AP UART0_AP /* same timing as UART0 */
+#define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
+
+
+/* Flash CS0 or CS 1 */
+/* 0x7F8FFE80 slowest timing at all... */
+#define FLASH_BME_B 1 /* Burst enable */
+#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */
+#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
+#define FLASH_BME 0 /* Burst disable */
+#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
+#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define FLASH_OEN 1 /* Cycles from CS low to OE low */
+#define FLASH_WBN 1 /* Cycles from CS low to WE low */
+#define FLASH_WBF 1 /* Cycles from WE high to CS high */
+#define FLASH_TH 2 /* Number of hold cycles after transfer */
+#define FLASH_RE 0 /* Ready disabled */
+#define FLASH_SOR 1 /* Sample on Ready disabled */
+#define FLASH_BEM 0 /* Byte Write only active on Write cycles */
+#define FLASH_PEN 0 /* Parity disable */
+/* Access Parameter Register for non Boot */
+#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+ (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+/* Access Parameter Register for Boot */
+#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+ (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define FLASH_BU 3 /* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define FLASH_BW 1 /* 16Bit */
+/* CR register for Boot */
+#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+/* CR register for non Boot */
+#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+
+/* MPS CS1 or CS0 */
+/* Boot CS: */
+#define MPS_BME_B 1 /* Burst enable */
+#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */
+#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
+#define MPS_BME 0 /* Burst disable */
+#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
+#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define MPS_OEN 1 /* Cycles from CS low to OE low */
+#define MPS_WBN 1 /* Cycles from CS low to WE low */
+#define MPS_WBF 1 /* Cycles from WE high to CS high */
+#define MPS_TH 2 /* Number of hold cycles after transfer */
+#define MPS_RE 0 /* Ready disabled */
+#define MPS_SOR 1 /* Sample on Ready disabled */
+#define MPS_BEM 0 /* Byte Write only active on Write cycles */
+#define MPS_PEN 0 /* Parity disable */
+/* Access Parameter Register for non Boot */
+#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+ (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+/* Access Parameter Register for Boot */
+#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+ (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define MPS_BS 2 /* 4 MByte */
+#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define MPS_BU 3 /* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define MPS_BW 0 /* 8Bit */
+/* CR register for Boot */
+#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13))
+/* CR register for non Boot */
+#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
diff --git a/board/mpl/pati/Kconfig b/board/mpl/pati/Kconfig
new file mode 100644
index 0000000..b141da3
--- /dev/null
+++ b/board/mpl/pati/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PATI
+
+config SYS_BOARD
+ default "pati"
+
+config SYS_VENDOR
+ default "mpl"
+
+config SYS_CONFIG_NAME
+ default "PATI"
+
+endif
diff --git a/board/mpl/pati/MAINTAINERS b/board/mpl/pati/MAINTAINERS
new file mode 100644
index 0000000..19ad05d
--- /dev/null
+++ b/board/mpl/pati/MAINTAINERS
@@ -0,0 +1,6 @@
+PATI BOARD
+#M: -
+S: Maintained
+F: board/mpl/pati/
+F: include/configs/PATI.h
+F: configs/PATI_defconfig
diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile
new file mode 100644
index 0000000..9822082
--- /dev/null
+++ b/board/mpl/pati/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := pati.o cmd_pati.o \
+ ../common/common_util.o
diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c
new file mode 100644
index 0000000..fcae5e0
--- /dev/null
+++ b/board/mpl/pati/cmd_pati.c
@@ -0,0 +1,433 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Adapted for PATI
+ */
+
+#include <common.h>
+#include <command.h>
+#define PLX9056_LOC
+#include "plx9056.h"
+#include "pati.h"
+#include "pci_eeprom.h"
+
+extern void show_pld_regs(void);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+extern void user_led0(int led_on);
+extern void user_led1(int led_on);
+
+/* ------------------------------------------------------------------------- */
+#if defined(CONFIG_SYS_PCI_CON_DEVICE)
+extern void pci_con_disc(void);
+extern void pci_con_connect(void);
+#endif
+
+/******************************************************************************
+ * Eeprom Support
+ ******************************************************************************/
+unsigned long get32(unsigned long addr)
+{
+ unsigned long *p=(unsigned long *)addr;
+ return *p;
+}
+
+void set32(unsigned long addr,unsigned long data)
+{
+ unsigned long *p=(unsigned long *)addr;
+ *p=data;
+}
+
+#define PCICFG_GET_REG(x) (get32((x) + PCI_CONFIG_BASE))
+#define PCICFG_SET_REG(x,y) (set32((x) + PCI_CONFIG_BASE,(y)))
+
+
+/******************************************************************************
+ * reload_pci_eeprom
+ ******************************************************************************/
+
+static void reload_pci_eeprom(void)
+{
+ unsigned long reg;
+ /* Set Bit 29 and clear it again */
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ udelay(1);
+ /* set it*/
+ reg|=(1<<29);
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ /* EECLK @ 33MHz = 125kHz
+ * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec
+ * use 20msec
+ */
+ udelay(20000); /* wait 20ms */
+ reg &= ~(1<<29); /* set it low */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ udelay(1); /* wait some time */
+}
+
+/******************************************************************************
+ * clock_pci_eeprom
+ ******************************************************************************/
+
+static void clock_pci_eeprom(void)
+{
+ unsigned long reg;
+ /* clock is low, data is valid */
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ udelay(1);
+ /* set clck high */
+ reg|=(1<<24);
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ udelay(1); /* wait some time */
+ reg &= ~(1<<24); /* set clock low */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ udelay(1); /* wait some time */
+}
+
+/******************************************************************************
+ * send_pci_eeprom_cmd
+ ******************************************************************************/
+static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len)
+{
+ unsigned long reg;
+ int i;
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ /* Clear all EEPROM bits */
+ reg &= ~(0xF << 24);
+ /* Toggle EEPROM's Chip select to get it out of Shift Register Mode */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ udelay(1); /* wait some time */
+ /* Enable EEPROM Chip Select */
+ reg |= (1 << 25);
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ /* Send EEPROM command - one bit at a time */
+ for (i = (int)(len-1); i >= 0; i--) {
+ /* Check if current bit is 0 or 1 */
+ if (cmd & (1 << i))
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
+ else
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+ clock_pci_eeprom();
+ }
+}
+
+/******************************************************************************
+ * write_pci_eeprom_offs
+ ******************************************************************************/
+static void write_pci_eeprom_offs(unsigned short offset, unsigned short value)
+{
+ unsigned long reg;
+ int bitpos, cmdshft, cmdlen, timeout;
+ /* we're using the Eeprom 93CS66 */
+ cmdshft = 2;
+ cmdlen = EE66_CMD_LEN;
+ /* Send Write_Enable command to EEPROM */
+ send_pci_eeprom_cmd((EE_WREN << cmdshft),cmdlen);
+ /* Send EEPROM Write command and offset to EEPROM */
+ send_pci_eeprom_cmd((EE_WRITE << cmdshft) | (offset / 2),cmdlen);
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ /* Clear all EEPROM bits */
+ reg &= ~(0xF << 24);
+ /* Make sure EEDO Input is disabled for some PLX chips */
+ reg &= ~(1 << 31);
+ /* Enable EEPROM Chip Select */
+ reg |= (1 << 25);
+ /* Write 16-bit value to EEPROM - one bit at a time */
+ for (bitpos = 15; bitpos >= 0; bitpos--) {
+ /* Get bit value and shift into result */
+ if (value & (1 << bitpos))
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
+ else
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg );
+ clock_pci_eeprom();
+ } /* for */
+ /* Deselect Chip */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25));
+ /* Re-select Chip */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25));
+ /* A small delay is needed to let EEPROM complete */
+ timeout = 0;
+ do {
+ udelay(10);
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ timeout++;
+ } while (((reg & (1 << 27)) == 0) && timeout < 20000);
+ /* Send Write_Disable command to EEPROM */
+ send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen);
+ /* Clear Chip Select and all other EEPROM bits */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
+}
+
+
+/******************************************************************************
+ * read_pci_eeprom_offs
+ ******************************************************************************/
+static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue)
+{
+ unsigned long reg;
+ int bitpos, cmdshft, cmdlen;
+ /* we're using the Eeprom 93CS66 */
+ cmdshft = 2;
+ cmdlen = EE66_CMD_LEN;
+ /* Send EEPROM read command and offset to EEPROM */
+ send_pci_eeprom_cmd((EE_READ << cmdshft) | (offset / 2),cmdlen);
+ /* Set EEPROM write output bit */
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ /* Set EEDO Input enable */
+ reg |= (1 << 31);
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26));
+ /* Get 16-bit value from EEPROM - one bit at a time */
+ for (bitpos = 0; bitpos < 16; bitpos++) {
+ clock_pci_eeprom();
+ udelay(10);
+ reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+ /* Get bit value and shift into result */
+ if (reg & (1 << 27))
+ *pvalue = (unsigned short)((*pvalue << 1) | 1);
+ else
+ *pvalue = (unsigned short)(*pvalue << 1);
+ }
+ /* Clear EEDO Input enable */
+ reg &= ~(1 << 31);
+ /* Clear Chip Select and all other EEPROM bits */
+ PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
+}
+
+
+/******************************************************************************
+ * EEPROM read/writes
+******************************************************************************/
+
+#undef EEPROM_DBG
+static int pati_pci_eeprom_erase(void)
+{
+ int i;
+ printf("Erasing EEPROM ");
+ for( i=0; i < PATI_EEPROM_LAST_OFFSET; i+=2) {
+ write_pci_eeprom_offs(i,0xffff);
+ if((i%0x10))
+ printf(".");
+ }
+ printf("\nDone\n");
+ return 0;
+}
+
+static int pati_pci_eeprom_prg(void)
+{
+ int i;
+ i=0;
+ printf("Programming EEPROM ");
+ while(pati_eeprom[i].offset<0xffff) {
+ write_pci_eeprom_offs(pati_eeprom[i].offset,pati_eeprom[i].value);
+ #ifdef EEPROM_DBG
+ printf("0x%04X: 0x%04X\n",pati_eeprom[i].offset, pati_eeprom[i].value);
+ #else
+ if((i%0x10))
+ printf(".");
+ #endif
+ i++;
+ }
+ printf("\nDone\n");
+ return 0;
+}
+
+static int pati_pci_eeprom_write(unsigned short offset, unsigned long addr, unsigned short size)
+{
+ int i;
+ unsigned short value;
+ unsigned short *buffer =(unsigned short *)addr;
+ if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
+ size = PATI_EEPROM_LAST_OFFSET - offset;
+ }
+ printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr, offset, size/2);
+ for( i = offset; i< (offset + size); i+=2) {
+ value = *buffer++;
+ write_pci_eeprom_offs(i,value);
+ #ifdef EEPROM_DBG
+ printf("0x%04X: 0x%04X\n",i, value);
+ #else
+ if((i%0x10))
+ printf(".");
+ #endif
+ }
+ printf("\nDone\n");
+ return 0;
+}
+
+static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size)
+{
+ int i;
+ unsigned short value = 0;
+ unsigned short *buffer =(unsigned short *)addr;
+ if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
+ size = PATI_EEPROM_LAST_OFFSET - offset;
+ }
+ printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset, addr, size/2);
+ for( i = offset; i< (offset + size); i+=2) {
+ read_pci_eeprom_offs(i,&value);
+ *buffer++=value;
+ #ifdef EEPROM_DBG
+ printf("0x%04X: 0x%04X\n",i, value);
+ #else
+ if((i%0x10))
+ printf(".");
+ #endif
+ }
+ printf("\nDone\n");
+ return 0;
+}
+
+/******************************************************************************
+ * PCI Bridge Registers Dump
+*******************************************************************************/
+static void display_pci_regs(void)
+{
+ printf(" PCI9056_SPACE0_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE));
+ printf(" PCI9056_SPACE0_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP));
+ printf(" PCI9056_LOCAL_DMA_ARBIT %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT));
+ printf(" PCI9056_ENDIAN_DESC %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC));
+ printf(" PCI9056_EXP_ROM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE));
+ printf(" PCI9056_EXP_ROM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP));
+ printf(" PCI9056_SPACE0_ROM_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC));
+ printf(" PCI9056_DM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE));
+ printf(" PCI9056_DM_MEM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE));
+ printf(" PCI9056_DM_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE));
+ printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP));
+ printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG));
+ printf(" PCI9056_SPACE1_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE));
+ printf(" PCI9056_SPACE1_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP));
+ printf(" PCI9056_SPACE1_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC));
+ printf(" PCI9056_DM_DAC %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC));
+ printf(" PCI9056_MAILBOX0 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0));
+ printf(" PCI9056_MAILBOX1 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1));
+ printf(" PCI9056_MAILBOX2 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2));
+ printf(" PCI9056_MAILBOX3 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3));
+ printf(" PCI9056_MAILBOX4 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4));
+ printf(" PCI9056_MAILBOX5 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5));
+ printf(" PCI9056_MAILBOX6 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6));
+ printf(" PCI9056_MAILBOX7 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7));
+ printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL));
+ printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL));
+ printf(" PCI9056_INT_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT));
+ printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT));
+ printf(" PCI9056_PERM_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID));
+ printf(" PCI9056_REVISION_ID %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID));
+ printf(" \n");
+ printf(" PCI9056_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID));
+ printf(" PCI9056_COMMAND %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND));
+ printf(" PCI9056_REVISION %08lX\n",PCICFG_GET_REG(PCI9056_REVISION));
+ printf(" PCI9056_CACHE_SIZE %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE));
+ printf(" PCI9056_RTR_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE));
+ printf(" PCI9056_RTR_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE));
+ printf(" PCI9056_LOCAL_BASE0 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0));
+ printf(" PCI9056_LOCAL_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1));
+ printf(" PCI9056_UNUSED_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1));
+ printf(" PCI9056_UNUSED_BASE2 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2));
+ printf(" PCI9056_CIS_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR));
+ printf(" PCI9056_SUB_ID %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID));
+ printf(" PCI9056_EXP_ROM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE));
+ printf(" PCI9056_CAP_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR));
+ printf(" PCI9056_INT_LINE %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE));
+ printf(" PCI9056_PM_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID));
+ printf(" PCI9056_PM_CSR %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR));
+ printf(" PCI9056_HS_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID));
+ printf(" PCI9056_VPD_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID));
+ printf(" PCI9056_VPD_DATA %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA));
+}
+
+
+int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (strcmp(argv[1], "info") == 0)
+ {
+ show_pld_regs();
+ return 0;
+ }
+ if (strcmp(argv[1], "pci") == 0)
+ {
+ display_pci_regs();
+ return 0;
+ }
+ if (strcmp(argv[1], "led") == 0)
+ {
+ int led_nr,led_on;
+ led_nr = (int)simple_strtoul(argv[2], NULL, 10);
+ led_on = (int)simple_strtoul(argv[3], NULL, 10);
+ if(!led_nr)
+ user_led0(led_on);
+ else
+ user_led1(led_on);
+ return 0;
+ }
+#if defined(CONFIG_SYS_PCI_CON_DEVICE)
+ if (strcmp(argv[1], "con") == 0) {
+ pci_con_connect();
+ return 0;
+ }
+ if (strcmp(argv[1], "disc") == 0) {
+ pci_con_disc();
+ return 0;
+ }
+#endif
+ if (strcmp(argv[1], "eeprom") == 0) {
+ unsigned long addr;
+ int size, offset;
+ offset = 0;
+ size = PATI_EEPROM_LAST_OFFSET;
+ if(argc>2) {
+ if(argc>3) {
+ addr = simple_strtoul(argv[3], NULL, 16);
+ if(argc>4)
+ offset = (int) simple_strtoul(argv[4], NULL, 16);
+ if(argc>5)
+ size = (int) simple_strtoul(argv[5], NULL, 16);
+ if (strcmp(argv[2], "read") == 0) {
+ return (pati_pci_eeprom_read(offset, addr, size));
+ }
+ if (strcmp(argv[2], "write") == 0) {
+ return (pati_pci_eeprom_write(offset, addr, size));
+ }
+ }
+ if (strcmp(argv[2], "prg") == 0) {
+ return (pati_pci_eeprom_prg());
+ }
+ if (strcmp(argv[2], "era") == 0) {
+ return (pati_pci_eeprom_erase());
+ }
+ if (strcmp(argv[2], "reload") == 0) {
+ reload_pci_eeprom();
+ return 0;
+ }
+
+
+ }
+ }
+
+ return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+
+U_BOOT_CMD(
+ pati, 8, 1, do_pati,
+ "PATI specific Cmds",
+ "info - displays board information\n"
+ "pati pci - displays PCI registers\n"
+ "pati led <nr> <on> \n"
+ " - switch LED <nr> <on>\n"
+ "pati flash mem [SrcAddr]\n"
+ " - updates U-Boot with image in memory\n"
+ "pati eeprom <cmd> - PCI EEPROM sub-system\n"
+ " read <addr> <offset> <size>\n"
+ " - read PCI EEPROM to <addr> from <offset> <size> words\n"
+ " write <addr> <offset> <size>\n"
+ " - write PCI EEPROM from <addr> to <offset> <size> words\n"
+ " prg - programm PCI EEPROM with default values\n"
+ " era - erase PCI EEPROM (write all word to 0xffff)\n"
+ " reload- Reload PCI Bridge with EEPROM Values\n"
+ " NOTE: <addr> must start on word boundary\n"
+ " <offset> and <size> must be even byte values"
+);
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c
new file mode 100644
index 0000000..b9d88ee
--- /dev/null
+++ b/board/mpl/pati/pati.c
@@ -0,0 +1,605 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ * Atapted for PATI
+ * Denis Peter, d.peter@mpl.ch
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/***********************************************************************************
+ * Bits for the SDRAM controller
+ * -----------------------------
+ *
+ * CAL: CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on
+ * the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM
+ * controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3).
+ * RCD: RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default)
+ * tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns.
+ * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns.
+ * If set to 1 tWR must be equal or less 50ns.
+ * RP: Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less
+ * 25ns. If set to 1 tRP must be equal or less 50ns.
+ * RC: Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal
+ * or less 75ns. If set to 1 tRC must be equal or less 100ns.
+ * LMR: Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM
+ * is the Load Mode Register Command.
+ * IIP: Init in progress. Set to 1 for starting the init sequence
+ * (Precharge All). As long this bit is set, the Precharge All is still in progress.
+ * After command has completed, wait at least for 8 refresh (200usec) before proceed.
+ **********************************************************************************/
+
+#include <common.h>
+#include <mpc5xx.h>
+#include <stdio_dev.h>
+#include <pci_ids.h>
+#define PLX9056_LOC
+#include "plx9056.h"
+#include "pati.h"
+
+#if defined(__APPLE__)
+/* Leading underscore on symbols */
+# define SYM_CHAR "_"
+#else /* No leading character on symbols */
+# define SYM_CHAR
+#endif
+
+#undef SDRAM_DEBUG
+/*
+ * Macros to generate global absolutes.
+ */
+#define GEN_SYMNAME(str) SYM_CHAR #str
+#define GEN_VALUE(str) #str
+#define GEN_ABS(name, value) \
+ asm (".globl " GEN_SYMNAME(name)); \
+ asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
+
+
+/************************************************************************
+ * Early debug routines
+ */
+void write_hex (unsigned char i)
+{
+ char cc;
+
+ cc = i >> 4;
+ cc &= 0xf;
+ if (cc > 9)
+ serial_putc (cc + 55);
+ else
+ serial_putc (cc + 48);
+ cc = i & 0xf;
+ if (cc > 9)
+ serial_putc (cc + 55);
+ else
+ serial_putc (cc + 48);
+}
+
+#if defined(SDRAM_DEBUG)
+
+void write_4hex (unsigned long val)
+{
+ write_hex ((unsigned char) (val >> 24));
+ write_hex ((unsigned char) (val >> 16));
+ write_hex ((unsigned char) (val >> 8));
+ write_hex ((unsigned char) val);
+}
+
+#endif
+
+unsigned long in32(unsigned long addr)
+{
+ unsigned long *p=(unsigned long *)addr;
+ return *p;
+}
+
+void out32(unsigned long addr,unsigned long data)
+{
+ unsigned long *p=(unsigned long *)addr;
+ *p=data;
+}
+
+typedef struct {
+ unsigned short boardtype; /* Board revision and Population Options */
+ unsigned char cal; /* cas Latency 0:CAL=2 1:CAL=3 */
+ unsigned char rcd; /* ras to cas delay 0:<25ns 1:<50ns*/
+ unsigned char wrec; /* write recovery 0:<25ns 1:<50ns */
+ unsigned char pr; /* Precharge Command Time 0:<25ns 1:<50ns */
+ unsigned char rc; /* Auto Refresh to Active Time 0:<75ns 1:<100ns */
+ unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
+} sdram_t;
+
+const sdram_t sdram_table[] = {
+ { 0x0000, /* PATI Rev A, 16MByte -1 Board */
+ 1, /* Case Latenty = 3 */
+ 0, /* ras to cas delay 0 (20ns) */
+ 0, /* write recovery 0:<25ns 1:<50ns*/
+ 0, /* Precharge Command Time 0 (20ns) */
+ 0, /* Auto Refresh to Active Time 0 (68) */
+ 2 /* log binary => Size 2 = 16MByte, 1=8 */
+ },
+ { 0xffff, /* terminator */
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff,
+ 0xff }
+};
+
+
+extern int mem_test (unsigned long start, unsigned long ramsize, int quiet);
+
+/*
+ * Get RAM size.
+ */
+phys_size_t initdram(int board_type)
+{
+ unsigned char board_rev;
+ unsigned long reg;
+ unsigned long lmr;
+ int i,timeout;
+
+#if defined(SDRAM_DEBUG)
+ reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
+ puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg));
+ puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg));
+ puts("\nSDRAM part 0x"); write_4hex(SDRAM_PART(reg));
+ puts(" Vers 0x"); write_4hex(SDRAM_ID(reg));
+ reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+ puts("\nBoard rev. 0x"); write_4hex(SYSCNTR_BREV(reg));
+ putc('\n');
+#endif
+ reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+ board_rev=(unsigned char)(SYSCNTR_BREV(reg));
+ i=0;
+ while(1) {
+ if(sdram_table[i].boardtype==0xffff) {
+ puts("ERROR, found no table for Board 0x");
+ write_hex(board_rev);
+ while(1);
+ }
+ if(sdram_table[i].boardtype==(unsigned char)board_rev)
+ break;
+ i++;
+ }
+ /* Set CAL, RCD, WREQ, PR and RC Bits */
+#if defined(SDRAM_DEBUG)
+ puts("Set CAL, RCD, WREQ, PR and RC Bits\n");
+#endif
+ /* mask bits */
+ reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) |
+ SET_REG_BIT(1,SDRAM_PR) | SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR) |
+ SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0));
+ /* set bits */
+ reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) |
+ SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) |
+ SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) |
+ SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) |
+ SET_REG_BIT(sdram_table[i].rc,SDRAM_RC));
+
+ out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
+ /* step 2 set IIP */
+#if defined(SDRAM_DEBUG)
+ puts("step 2 set IIP\n");
+#endif
+ /* step 2 set IIP */
+ reg |= SET_REG_BIT(1,SDRAM_IIP);
+ timeout=0;
+ while (timeout!=0xffff) {
+ __asm__ volatile("eieio");
+ reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+ if((reg & SET_REG_BIT(1,SDRAM_IIP))==0)
+ break;
+ timeout++;
+ udelay(1);
+ }
+ /* wait for at least 8 refresh */
+ udelay(1000);
+ /* set LMR */
+ reg |= SET_REG_BIT(1,SDRAM_LMR);
+ out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
+ __asm__ volatile("eieio");
+ lmr=0x00000002; /* sequential burst 4 data */
+ if(sdram_table[i].cal==1)
+ lmr|=0x00000030; /* cal = 3 */
+ else
+ lmr|=0000000020; /* cal = 2 */
+ /* rest standard operation programmed write burst length */
+ /* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */
+ lmr<<=2;
+ in32(CONFIG_SYS_SDRAM_BASE + lmr);
+ /* ok, we're done, return SDRAM size */
+ return ((0x400000 << sdram_table[i].sz)); /* log2 value of 4MByte */
+}
+
+
+void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp)
+{
+ unsigned long reg;
+ reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE);
+ reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) |
+ SET_REG_BIT(1,SYSCNTR_FL_VPP) |
+ SET_REG_BIT(1,SYSCNTR_FL_WP));
+
+ reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) |
+ SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) |
+ SET_REG_BIT(ext_wp,SYSCNTR_FL_WP));
+ out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg);
+ udelay(100);
+}
+
+
+void show_pld_regs(void)
+{
+ unsigned long reg,reg1;
+ reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
+ printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg));
+ printf("SDRAM part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg));
+ reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+ printf("Board rev. %c\n",(char) (SYSCNTR_BREV(reg)+'A'));
+ printf("Waitstates %ld\n",GET_SYSCNTR_FLWAIT(reg));
+ printf("SDRAM: CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n RC=%ld LMR=%ld IIP=%ld\n",
+ GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD),
+ GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR),
+ GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR),
+ GET_REG_BIT(reg,SDRAM_IIP));
+ reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1);
+ reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2);
+ printf("HW Config: FLAG=%ld IP=%ld index=%ld PRPM=%ld\n ICW=%ld ISB=%ld BDIS=%ld PCIM=%ld\n",
+ GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP),
+ GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM),
+ GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg),
+ GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM));
+ printf("Switches: MUX=%ld PCI_DIS=%ld Boot_EN=%ld Config=%ld\n",GET_SDRAM_MUX(reg),
+ GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN),
+ GET_SYSCNTR_CFG(reg1));
+ printf("Misc: RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n",
+ GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP),
+ GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP));
+}
+
+
+/****************************************************************
+ * Setting IOs
+ * -----------
+ * GPIO6 is User LED1
+ * GPIO7 is Interrupt PLX (Output)
+ * GPIO5 is User LED0
+ * GPIO2 is PLX USERi (Output)
+ * GPIO1 is PLX Interrupt (Input)
+ ****************************************************************/
+ void init_ios(void)
+ {
+ volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
+ volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
+ unsigned long reg;
+ reg=sysconf->sc_sgpiocr; /* Data direction register */
+ reg &= ~0x67000000;
+ reg |= 0x27000000; /* set outpupts */
+ sysconf->sc_sgpiocr=reg; /* Data direction register */
+ reg=sysconf->sc_sgpiodt2; /* Data register */
+ /* set output to 0 */
+ reg &= ~0x27000000;
+ /* set IRQ and USERi to 1 */
+ reg |= 0x28000000;
+ sysconf->sc_sgpiodt2=reg; /* Data register */
+}
+
+void user_led0(int led_on)
+{
+ volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
+ volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
+ unsigned long reg;
+ reg=sysconf->sc_sgpiodt2; /* Data register */
+ if(led_on) /* set output to 1 */
+ reg |= 0x04000000;
+ else
+ reg &= ~0x04000000;
+ sysconf->sc_sgpiodt2=reg; /* Data register */
+}
+
+void user_led1(int led_on)
+{
+ volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
+ volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
+ unsigned long reg;
+ reg=sysconf->sc_sgpiodt2; /* Data register */
+ if(led_on) /* set output to 1 */
+ reg |= 0x02000000;
+ else
+ reg &= ~0x02000000;
+ sysconf->sc_sgpiodt2=reg; /* Data register */
+}
+
+int board_early_init_f(void)
+{
+ spi_init_f();
+ return 0;
+}
+
+/****************************************************************
+ * Last Stage Init
+ ****************************************************************/
+int last_stage_init (void)
+{
+ init_ios();
+ return 0;
+}
+
+/****************************************************************
+ * Check the board
+ ****************************************************************/
+
+#define BOARD_NAME "PATI"
+
+int checkboard (void)
+{
+ char s[50];
+ ulong reg;
+ char rev;
+ int i;
+
+ puts ("\nBoard: ");
+ reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+ rev=(char)(SYSCNTR_BREV(reg)+'A');
+ i = getenv_f("serial#", s, 32);
+ if ((i == -1)) {
+ puts ("### No HW ID - assuming " BOARD_NAME);
+ printf(" Rev. %c\n",rev);
+ }
+ else {
+ s[sizeof(BOARD_NAME)-1] = 0;
+ printf ("%s-1 Rev %c SN: %s\n", s,rev,
+ &s[sizeof(BOARD_NAME)]);
+ }
+ set_flash_vpp(1,0,0); /* set Flash VPP */
+ return 0;
+}
+
+
+#ifdef CONFIG_SYS_PCI_CON_DEVICE
+/************************************************************************
+ * PCI Communication
+ *
+ * Alive (Pinging):
+ * ----------------
+ * PCI Host sends message ALIVE, Local acknowledges with ALIVE
+ *
+ * PCI_CON console over PCI:
+ * -------------------------
+ * Local side:
+ * - uses PCI9056_LOC_TO_PCI_DBELL register to signal that
+ * data is avaible (PCIMSG_CONN)
+ * - uses PCI9056_MAILBOX1 to send data
+ * - uses PCI9056_MAILBOX0 to receive data
+ * PCI side:
+ * - uses PCI9056_PCI_TO_LOC_DBELL register to signal that
+ * data is avaible (PCIMSG_CONN)
+ * - uses PCI9056_MAILBOX0 to send data
+ * - uses PCI9056_MAILBOX1 to receive data
+ *
+ * How it works:
+ * Send:
+ * - check if PCICON_TRANSMIT_REG is empty
+ * - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG
+ * - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data
+ * is waiting
+ * Receive:
+ * - get an interrupt via the PCICON_ACK_REG register message
+ * PCIMSG_CONN
+ * - write the data from the PCICON_RECEIVE_REG into the receive
+ * buffer and if the receive buffer is not full, clear the
+ * PCICON_RECEIVE_REG (this allows the counterpart to write more data)
+ * - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG
+ *
+ * The PCICON_RECEIVE_REG must be cleared by the routine which reads
+ * the receive buffer if the buffer is not full any more
+ *
+ */
+
+#undef PCI_CON_DEBUG
+
+#ifdef PCI_CON_DEBUG
+#define PCI_CON_PRINTF(fmt,args...) serial_printf (fmt ,##args)
+#else
+#define PCI_CON_PRINTF(fmt,args...)
+#endif
+
+
+/*********************************************************
+ * we work only with a receive buffer on eiter side.
+ * Transmit buffer is free, if mailbox is cleared.
+ * Transmit character is or'ed with 0x80000000
+ * PATI receive register MAILBOX0
+ * PATI transmit register MAILBOX1
+ *********************************************************/
+#define PCICON_RECEIVE_REG PCI9056_MAILBOX0
+#define PCICON_TRANSMIT_REG PCI9056_MAILBOX1
+#define PCICON_DBELL_REG PCI9056_LOC_TO_PCI_DBELL
+#define PCICON_ACK_REG PCI9056_PCI_TO_LOC_DBELL
+
+
+#define PCIMSG_ALIVE 0x1
+#define PCIMSG_CONN 0x2
+#define PCIMSG_DISC 0x3
+#define PCIMSG_CON_DATA 0x5
+
+
+#define PCICON_GET_REG(x) (in32(x + PCI_CONFIG_BASE))
+#define PCICON_SET_REG(x,y) (out32(x + PCI_CONFIG_BASE,y))
+#define PCICON_TX_FLAG 0x80000000
+
+
+#define REC_BUFFER_SIZE 0x100
+int recbuf[REC_BUFFER_SIZE];
+static int r_ptr = 0;
+int w_ptr;
+struct stdio_dev pci_con_dev;
+int conn=0;
+int buff_full=0;
+
+void pci_con_put_it(const char c)
+{
+ /* Test for completition */
+ unsigned long reg;
+ do {
+ reg=PCICON_GET_REG(PCICON_TRANSMIT_REG);
+ }while(reg);
+ reg=PCICON_TX_FLAG + c;
+ PCICON_SET_REG(PCICON_TRANSMIT_REG,reg);
+ PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA);
+}
+
+void pci_con_putc(struct stdio_dev *dev, const char c)
+{
+ pci_con_put_it(c);
+ if(c == '\n')
+ pci_con_put_it('\r');
+}
+
+
+int pci_con_getc(struct stdio_dev *dev)
+{
+ int res;
+ int diff;
+ while(r_ptr==(volatile int)w_ptr);
+ res=recbuf[r_ptr++];
+ if(r_ptr==REC_BUFFER_SIZE)
+ r_ptr=0;
+ if(w_ptr<r_ptr)
+ diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
+ else
+ diff=r_ptr-w_ptr;
+ if((diff<(REC_BUFFER_SIZE-4)) && buff_full) {
+ /* clear Mail box */
+ buff_full=0;
+ PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+ }
+ return res;
+}
+
+int pci_con_tstc(struct stdio_dev *dev)
+{
+ if(r_ptr==(volatile int)w_ptr)
+ return 0;
+ return 1;
+}
+
+void pci_con_puts(struct stdio_dev *dev, const char *s)
+{
+ while (*s) {
+ pci_con_putc(*s);
+ ++s;
+ }
+}
+
+void pci_con_init (void)
+{
+ w_ptr = 0;
+ r_ptr = 0;
+ PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+ conn=1;
+}
+
+/*******************************************
+ * IRQ routine
+ ******************************************/
+int pci_dorbell_irq(void)
+{
+ unsigned long reg,data;
+ int diff;
+ reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
+ PCI_CON_PRINTF(" PCI9056_INT_CTRL_STAT = %08lX\n",reg);
+ if(reg & (1<<20) ) {
+ /* read doorbell */
+ reg=PCICON_GET_REG(PCICON_ACK_REG);
+ switch(reg) {
+ case PCIMSG_ALIVE:
+ PCI_CON_PRINTF(" Alive\n");
+ PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_ALIVE);
+ break;
+ case PCIMSG_CONN:
+ PCI_CON_PRINTF(" Conn %d",conn);
+ w_ptr = 0;
+ r_ptr = 0;
+ buff_full=0;
+ PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+ conn=1;
+ PCI_CON_PRINTF(" ... %d\n",conn);
+ break;
+ case PCIMSG_CON_DATA:
+ data=PCICON_GET_REG(PCICON_RECEIVE_REG);
+ recbuf[w_ptr++]=(int)(data&0xff);
+ PCI_CON_PRINTF(" Data Console %lX, %X %d %d %X\n",data,((int)(data&0xFF)),
+ r_ptr,w_ptr,recbuf[w_ptr-1]);
+ if(w_ptr==REC_BUFFER_SIZE)
+ w_ptr=0;
+ if(w_ptr<r_ptr)
+ diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
+ else
+ diff=r_ptr-w_ptr;
+ if(diff>(REC_BUFFER_SIZE-4))
+ buff_full=1;
+ else
+ /* clear Mail box */
+ PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+ break;
+ default:
+ serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg);
+ }
+ /* clear IRQ */
+ PCICON_SET_REG(PCICON_ACK_REG,~0L);
+ }
+ return 0;
+}
+
+void pci_con_connect(void)
+{
+ unsigned long reg;
+ conn=0;
+ reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
+ /* default 0x0f010180 */
+ reg &= 0xff000000;
+ reg |= 0x00030000; /* enable local dorbell */
+ reg |= 0x00000300; /* enable PCI dorbell */
+ PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg);
+ irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL);
+ memset (&pci_con_dev, 0, sizeof (pci_con_dev));
+ strcpy (pci_con_dev.name, "pci_con");
+ pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+ pci_con_dev.putc = pci_con_putc;
+ pci_con_dev.puts = pci_con_puts;
+ pci_con_dev.getc = pci_con_getc;
+ pci_con_dev.tstc = pci_con_tstc;
+ stdio_register (&pci_con_dev);
+ printf("PATI ready for PCI connection, type ctrl-c for exit\n");
+ do {
+ udelay(10);
+ if((volatile int)conn)
+ break;
+ if(ctrlc()) {
+ irq_free_handler(0x2);
+ return;
+ }
+ }while(1);
+ console_assign(stdin,"pci_con");
+ console_assign(stderr,"pci_con");
+ console_assign(stdout,"pci_con");
+}
+
+void pci_con_disc(void)
+{
+ console_assign(stdin,"serial");
+ console_assign(stderr,"serial");
+ console_assign(stdout,"serial");
+ PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC);
+ /* reconnection */
+ irq_free_handler(0x02);
+ pci_con_connect();
+}
+#endif /* #ifdef CONFIG_SYS_PCI_CON_DEVICE */
+
+/*
+ * Absolute environment address for linker file.
+ */
+GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE);
diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h
new file mode 100644
index 0000000..2600bba
--- /dev/null
+++ b/board/mpl/pati/pati.h
@@ -0,0 +1,424 @@
+/*
+ * (C) Copyright 2003
+ * Denis Peter, d.peter@mpl.ch
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/************************************************************************
+ * MACROS and register definitions for PATI Registers
+ ************************************************************************/
+#ifndef __PATI_H_
+#define __PATI_H_ 1
+
+#define PLD_PART_ID 0x0
+#define PLD_BOARD_TIMING 0x4
+#define PLD_CONF_REG1 0x8
+#define PLD_CONF_REG2 0xC
+#define PLD_CONF_RES 0x10
+
+#define SET_REG_BIT(y,x) (y<<(31-x))
+#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L)
+
+/* SDRAM Controller PLD_PART_ID */
+/* 9 10 11 12 13 14 19 31 */
+#define SDRAM_PART3 9
+#define SDRAM_PART2 10
+#define SDRAM_PART1 11
+#define SDRAM_PART0 12
+#define SDRAM_ID3 13
+#define SDRAM_ID2 14
+#define SDRAM_ID1 19
+#define SDRAM_ID0 31
+
+#define SDRAM_PART(x) ( \
+ (GET_REG_BIT(x,SDRAM_PART3)<<3) |\
+ (GET_REG_BIT(x,SDRAM_PART2)<<2) |\
+ (GET_REG_BIT(x,SDRAM_PART1)<<1) |\
+ (GET_REG_BIT(x,SDRAM_PART0)))
+
+#define SDRAM_ID(x) ( \
+ (GET_REG_BIT(x,SDRAM_ID3)<<3) |\
+ (GET_REG_BIT(x,SDRAM_ID2)<<2) |\
+ (GET_REG_BIT(x,SDRAM_ID1)<<1) |\
+ (GET_REG_BIT(x,SDRAM_ID0)))
+
+/* System Controller */
+/* 0 1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_PART4 0
+#define SYSCNTR_PART3 1
+#define SYSCNTR_PART2 3
+#define SYSCNTR_PART1 4
+#define SYSCNTR_PART0 5
+#define SYSCNTR_ID4 16
+#define SYSCNTR_ID3 20
+#define SYSCNTR_ID2 28
+#define SYSCNTR_ID1 29
+#define SYSCNTR_ID0 30
+
+#define SYSCNTR_PART(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\
+ (GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\
+ (GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\
+ (GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\
+ (GET_REG_BIT(x,SYSCNTR_PART0)))
+
+#define SYSCNTR_ID(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\
+ (GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\
+ (GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\
+ (GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\
+ (GET_REG_BIT(x,SYSCNTR_ID0)))
+
+/* SDRAM Controller PLD_BOARD_TIMING */
+/* 9 10 11 12 13 14 19 31 */
+#define SDRAM_CAL 9
+#define SDRAM_RCD 10
+#define SDRAM_WREQ 11
+#define SDRAM_PR 12
+#define SDRAM_RC 13
+#define SDRAM_LMR 14
+#define SDRAM_IIP 19
+#define SDRAM_RES0 31
+/* System Controller */
+/* 0 1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_BREV0 0
+#define SYSCNTR_BREV1 1
+#define SYSCNTR_BREV2 3
+#define SYSCNTR_BREV3 4
+#define SYSCNTR_RES0 5
+#define SYSCNTR_RES1 16
+#define SYSCNTR_RES2 20
+#define SYSCNTR_FLWAIT2 28
+#define SYSCNTR_FLWAIT1 29
+#define SYSCNTR_FLWAIT0 30
+
+#define SYSCNTR_BREV(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\
+ (GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\
+ (GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\
+ (GET_REG_BIT(x,SYSCNTR_BREV0)))
+
+#define GET_SYSCNTR_FLWAIT(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\
+ (GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\
+ (GET_REG_BIT(x,SYSCNTR_FLWAIT0)))
+
+#define SET_SYSCNTR_FLWAIT(x) ( \
+ (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\
+ (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\
+ (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0)))
+
+/* SDRAM Controller REG 2*/
+/* 9 10 11 12 13 14 19 31 */
+#define SDRAM_MUX0 9
+#define SDRAM_MUX1 10
+#define SDRAM_PDIS 11
+#define SDRAM_RES1 12
+#define SDRAM_RES2 13
+#define SDRAM_RES3 14
+#define SDRAM_RES4 19
+#define SDRAM_RIP 31
+
+#define GET_SDRAM_MUX(x) ( \
+ (GET_REG_BIT(x,SDRAM_MUX1)<<1)| \
+ (GET_REG_BIT(x,SDRAM_MUX0)))
+
+
+/* System Controller */
+/* 0 1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_FLAG 0
+#define SYSCNTR_IP 1
+#define SYSCNTR_BIND2 3
+#define SYSCNTR_BIND1 4
+#define SYSCNTR_BIND0 5
+#define SYSCNTR_PRM 16
+#define SYSCNTR_ICW 20
+#define SYSCNTR_ISB2 28
+#define SYSCNTR_ISB1 29
+#define SYSCNTR_ISB0 30
+
+#define GET_SYSCNTR_BOOTIND(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\
+ (GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\
+ (GET_REG_BIT(x,SYSCNTR_BIND0)))
+
+#define SET_SYSCNTR_BOOTIND(x) ( \
+ (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\
+ (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \
+ (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0)))
+
+#define GET_SYSCNTR_ISB(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \
+ (GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \
+ (GET_REG_BIT(x,SYSCNTR_ISB0)))
+
+#define SET_SYSCNTR_ISB(x) ( \
+ (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \
+ (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \
+ (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0)))
+
+/* SDRAM Controller REG 3*/
+/* 9 10 11 12 13 14 19 31 */
+#define SDRAM_RES5 9
+#define SDRAM_CFG1 10
+#define SDRAM_CFG2 11
+#define SDRAM_CFG3 12
+#define SDRAM_RES6 13
+#define SDRAM_CFG5 14
+#define SDRAM_CFG6 19
+#define SDRAM_RES7 31
+
+#define GET_SDRAM_CFG(x) ( \
+ (GET_REG_BIT(x,SDRAM_CFG6)<<4) |\
+ (GET_REG_BIT(x,SDRAM_CFG5)<<3) |\
+ (GET_REG_BIT(x,SDRAM_CFG3)<<2) |\
+ (GET_REG_BIT(x,SDRAM_CFG2)<<1) |\
+ (GET_REG_BIT(x,SDRAM_CFG1)))
+
+/* System Controller */
+/* 0 1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_BDIS 0
+#define SYSCNTR_PCIM 1
+#define SYSCNTR_CFG0 3
+#define SYSCNTR_CFG1 4
+#define SYSCNTR_CFG2 5
+#define SYSCNTR_CFG3 16
+#define SYSCNTR_BOOTEN 20
+#define SYSCNTR_CPU_VPP 28
+#define SYSCNTR_FL_VPP 29
+#define SYSCNTR_FL_WP 30
+
+#define GET_SYSCNTR_CFG(x) ( \
+ (GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \
+ (GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \
+ (GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \
+ (GET_REG_BIT(x,SYSCNTR_CFG0)))
+
+
+/***************************************************************
+ * MISC Defines
+ ***************************************************************/
+
+#define PCI_VENDOR_ID_MPL 0x18E6
+#define PCI_DEVICE_ID_PATI 0x00DA
+
+#if defined(CONFIG_MIP405)
+#define PATI_FIRMWARE_START_OFFSET 0x00300000
+#define PATI_ISO_STRING "MEV-10084-001"
+#endif
+
+#define PATI_ENDIAN_MODE 0x3E
+
+/*******************************************
+ * PATI Mapping:
+ * -------------
+ * PCI Map:
+ * -------
+ * All addreses are mapped into the memory area
+ * (IO Area on some areas may also be possible)
+ * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
+ * - pci_space0_addr: configurable
+ * - pci_space1_addr configurable
+ *
+ * Local Map:
+ * ----------
+ * Local addresses (Remap)
+ * - SDRAM 0x06000000 Size 16MByte mask 0xff000000
+ * - EPLD CFG 0x07000000 Size 512Bytes
+ * - FLASH 0x03000000 Size up to 8MByte
+ * - CPU 0x01000000 Size 4MByte (only accessable if special configured)
+ *
+ * Implemention:
+ * -------------
+ * To prevent using large resources reservation on the host following
+ * PCI mapping is choosed:
+ * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
+ * - pci_space0_addr: configured to the EPLD Config Area size 256Bytes
+ * - pci_space1_addr: configured to the SDRAM Area size 1MBytes, this
+ * space is used to switch between SDRAM, Flash and CPU
+ *
+ */
+
+/* Attribute definitions */
+#define PATI_BUS_SIZE_8 0
+#define PATI_BUS_SIZE_16 1
+#define PATI_BUS_SIZE_32 3
+
+#define PATI_SPACE0_MASK (0xFEFFFE00) /* Mask Attributes */
+#define PATI_SPACE1_MASK (0x00000000) /* Mask Attributes */
+
+#define PATI_EXTRA_LONG_EEPROM 1
+
+#define SPACE0_TA_ENABLE (1<<6)
+#define SPACE1_TA_ENABLE (1<<6)
+
+/* Config Area */
+#define PATI_LOC_CFG_ADDR 0x07000000 /* Local Address */
+#define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */
+/* Attributes */
+#define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
+#define PATI_LOC_CFG_BURST 0 /* No Burst */
+#define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */
+#define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */
+
+#define PATI_LOC_CFG_SPACE0_ATTR ( \
+ PATI_LOC_CFG_BUS_SIZE | \
+ (PATI_LOC_CFG_TA_ENABLE << 6) | \
+ (PATI_LOC_CFG_NO_PREFETCH << 8) | \
+ (PATI_LOC_CFG_BURST << 24) | \
+ (PATI_EXTRA_LONG_EEPROM << 25))
+
+/* should never be used */
+#define PATI_LOC_CFG_SPACE1_ATTR ( \
+ PATI_LOC_CFG_BUS_SIZE | \
+ (PATI_LOC_CFG_TA_ENABLE << 6) | \
+ (PATI_LOC_CFG_NO_PREFETCH << 9) | \
+ (PATI_LOC_CFG_BURST << 8))
+
+
+/* SDRAM Area */
+#define PATI_LOC_SDRAM_ADDR 0x06000000 /* Local Address */
+#define PATI_LOC_SDRAM_MASK 0xFFF00000 /* 1MByte */
+/* Attributes */
+#define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
+#define PATI_LOC_SDRAM_BURST 0 /* No Burst */
+#define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */
+#define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */
+
+/* should never be used */
+#define PATI_LOC_SDRAM_SPACE0_ATTR ( \
+ PATI_LOC_SDRAM_BUS_SIZE | \
+ (PATI_LOC_SDRAM_TA_ENABLE << 6) | \
+ (PATI_LOC_SDRAM_NO_PREFETCH << 8) | \
+ (PATI_LOC_SDRAM_BURST << 24) | \
+ (PATI_EXTRA_LONG_EEPROM << 25))
+
+#define PATI_LOC_SDRAM_SPACE1_ATTR ( \
+ PATI_LOC_SDRAM_BUS_SIZE | \
+ (PATI_LOC_SDRAM_TA_ENABLE << 6) | \
+ (PATI_LOC_SDRAM_NO_PREFETCH << 9) | \
+ (PATI_LOC_SDRAM_BURST << 8))
+
+
+/* Flash Area */
+#define PATI_LOC_FLASH_ADDR 0x03000000 /* Local Address */
+#define PATI_LOC_FLASH_MASK 0xFFF00000 /* 1MByte */
+/* Attributes */
+#define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */
+#define PATI_LOC_FLASH_BURST 0 /* No Burst */
+#define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */
+#define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */
+
+/* should never be used */
+#define PATI_LOC_FLASH_SPACE0_ATTR ( \
+ PATI_LOC_FLASH_BUS_SIZE | \
+ (PATI_LOC_FLASH_TA_ENABLE << 6) | \
+ (PATI_LOC_FLASH_NO_PREFETCH << 8) | \
+ (PATI_LOC_FLASH_BURST << 24) | \
+ (PATI_EXTRA_LONG_EEPROM << 25))
+
+#define PATI_LOC_FLASH_SPACE1_ATTR ( \
+ PATI_LOC_FLASH_BUS_SIZE | \
+ (PATI_LOC_FLASH_TA_ENABLE << 6) | \
+ (PATI_LOC_FLASH_NO_PREFETCH << 9) | \
+ (PATI_LOC_FLASH_BURST << 8))
+
+
+/* CPU Area */
+#define PATI_LOC_CPU_ADDR 0x01000000 /* Local Address */
+#define PATI_LOC_CPU_MASK 0xFFF00000 /* 1Mbyte */
+/* Attributes */
+#define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
+#define PATI_LOC_CPU_BURST 0 /* No Burst */
+#define PATI_LOC_CPU_NO_PREFETCH 1 /* No Prefetch */
+#define PATI_LOC_CPU_TA_ENABLE 1 /* Enable TA */
+
+/* should never be used */
+#define PATI_LOC_CPU_SPACE0_ATTR ( \
+ PATI_LOC_CPU_BUS_SIZE | \
+ (PATI_LOC_CPU_TA_ENABLE << 6) | \
+ (PATI_LOC_CPU_NO_PREFETCH << 8) | \
+ (PATI_LOC_CPU_BURST << 24) | \
+ (PATI_EXTRA_CPU_EEPROM << 25))
+
+#define PATI_LOC_CPU_SPACE1_ATTR ( \
+ PATI_LOC_CPU_BUS_SIZE | \
+ (PATI_LOC_CPU_TA_ENABLE << 6) | \
+ (PATI_LOC_CPU_NO_PREFETCH << 9) | \
+ (PATI_LOC_CPU_BURST << 8))
+
+/***************************************************
+ * Hardware Config word definition
+ ***************************************************/
+#define BOOT_EXT_FLASH 0x00000000
+#define BOOT_INT_FLASH 0x00000004
+#define BOOT_FROM_PCI 0x00000006
+#define BOOT_FROM_SDRAM 0x00000005
+
+#define ENABLE_INT_ARB 0x00000008
+
+#define INITIAL_IRQ_PREF 0x00000010
+
+#define INITIAL_MEM_0M 0x00000000
+#define INITIAL_MEM_4M 0x00000080
+#define INITIAL_MEM_8M 0x00000040
+#define INITIAL_MEM_12M 0x000000C0
+#define INITIAL_MEM_16M 0x00000020
+#define INITIAL_MEM_20M 0x000000A0
+#define INITIAL_MEM_24M 0x00000060
+#define INITIAL_MEM_28M 0x000000E0
+/* CONF */
+#define INTERNAL_HWCONF 0x00000100
+/* PRPM */
+#define LOCAL_CPU_SLAVE 0x00000200
+/* BDIS */
+#define DISABLE_MEM_CNTR 0x00000400
+/* PCIM */
+#define PCI_MASTER_ONLY 0x00000800
+
+
+#define PATI_HW_START ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF))
+#define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
+#define PATI_HW_CPU_ACC ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
+#define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
+
+/***************************************************
+ * Direct Master Config
+ ***************************************************/
+#define PATI_DMASTER_PCI_ADDR 0x01000000
+#define PATI_BUS_MASTER 1
+
+
+#define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */
+#define PATI_DMASTER_ADDR 0x01000000 /* Local Address */
+
+#define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */
+#define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */
+#define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */
+#define PATI_DMASTER_PRE_SIZE_CNTRL_0 0x00000000
+#define PATI_DMASTER_PRE_SIZE_CNTRL_4 0x00000008
+#define PATI_DMASTER_PRE_SIZE_CNTRL_8 0x00001000
+#define PATI_DMASTER_PRE_SIZE_CNTRL_16 0x00001008
+#define PATI_DMASTER_REL_PCI 0x00000000
+#define PATI_DMASTER_NOT_REL_PCI 0x00000010
+#define PATI_DMASTER_WR_INVAL 0x00000200
+#define PATI_DMASTER_NOT_WR_INVAL 0x00000000
+#define PATI_DMASTER_PRE_LIMIT 0x00000800
+#define PATI_DMASTER_PRE_CONT 0x00000000
+#define PATI_DMASTER_DELAY_WR_0 0x00000000
+#define PATI_DMASTER_DELAY_WR_4 0x00004000
+#define PATI_DMASTER_DELAY_WR_8 0x00008000
+#define PATI_DMASTER_DELAY_WR_16 0x0000C000
+
+#define PATI_DMASTER_PCI_ADDR_MASK 0xFFFF0000
+
+#define PATI_DMASTER_ATTR \
+ PATI_DMASTER_MEMORY_EN | \
+ PATI_DMASTER_READ_AHEAD | \
+ PATI_DMASTER_PRE_SIZE_CNTRL_4 | \
+ PATI_DMASTER_REL_PCI | \
+ PATI_DMASTER_NOT_WR_INVAL | \
+ PATI_DMASTER_PRE_LIMIT | \
+ PATI_DMASTER_DELAY_WR_0
+
+
+#endif /* #ifndef __PATI_H_ */
diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h
new file mode 100644
index 0000000..459c143
--- /dev/null
+++ b/board/mpl/pati/pci_eeprom.h
@@ -0,0 +1,90 @@
+#ifndef __PCI_EEPROM_H_
+#define __PCI_EEPROM_H_ 1
+
+#include "pati.h"
+/******************************************************************************
+ * Eeprom Support
+ ******************************************************************************/
+/**********************************************
+* Definitions
+**********************************************/
+#define EE46_CMD_LEN 9 /* Bits in instructions */
+#define EE56_CMD_LEN 11 /* Bits in instructions */
+#define EE66_CMD_LEN 11 /* Bits in instructions */
+#define EE_READ 0x0180 /* 01 1000 0000 read instruction */
+#define EE_WRITE 0x0140 /* 01 0100 0000 write instruction */
+#define EE_WREN 0x0130 /* 01 0011 0000 write enable instruction */
+#define EE_WRALL 0x0110 /* 01 0001 0000 write all registers */
+#define EE_PRREAD 0x0180 /* 01 1000 0000 read address stored in Protect Register */
+#define EE_PRWRITE 0x0140 /* 01 0100 0000 write the address into PR */
+#define EE_WDS 0x0100 /* 01 0000 0000 write disable instruction */
+#define EE_PREN 0x0130 /* 01 0011 0000 protect enable instruction */
+#define EE_PRCLEAR 0x01FF /* 01 1111 1111 clear protect register instr */
+#define EE_PRDS 0x0100 /* 01 0000 0000 ONE TIME ONLY, permenant */
+
+/***************************************************
+ * EEPROM
+ ***************************************************/
+#define LOW_WORD(x) (((x) & 0xFFFF))
+#define HIGH_WORD(x) (((x) >> 16) & 0xFFFF)
+
+typedef struct pci_eeprom_t {
+ unsigned short offset;
+ unsigned short value;
+} pci_eeprom;
+
+static pci_eeprom pati_eeprom[] = {
+ { 0x00,PCI_DEVICE_ID_PATI }, /* PCI Device ID PCIIDR[31:16] */
+ { 0x02,PCI_VENDOR_ID_MPL }, /* PCI Vendor ID PCIIDR[15:0] */
+ { 0x04,PCI_CLASS_PROCESSOR_POWERPC }, /* PCI Class Code PCICCR[23:8] */
+ { 0x06,0x00BA }, /* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */
+ { 0x08,0x0007 }, /* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */
+ { 0x0A,0x0100 }, /* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */
+ { 0x0C,0x0000 }, /* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */
+ { 0x0E,0x0000 }, /* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */
+ { 0x10,0x0000 }, /* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */
+ { 0x12,0x0000 }, /* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */
+ { 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, /* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */
+ { 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, /* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */
+ { 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, /* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */
+ { 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, /* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */
+ { 0x1C,0x0000 }, /* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */
+ { 0x1E,0x0000 }, /* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */
+ { 0x20,0x0030 }, /* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */
+ { 0x22,0x0510 }, /* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */
+ { 0x24,0x0000 }, /* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */
+ { 0x26,0x0000 }, /* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1] */
+ { 0x28,0x0000 }, /* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */
+ { 0x2A,0x0000 }, /* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */
+ { 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, /* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */
+ { 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, /* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */
+ { 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, /* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */
+ { 0x32,LOW_WORD(PATI_DMASTER_MASK) }, /* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */
+ { 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, /* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */
+ { 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, /* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */
+ { 0x38,0x0000 }, /* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */
+ { 0x3A,0x0000 }, /* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */
+ { 0x3C,0x0000 }, /* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */
+ { 0x3E,0x0000 }, /* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */
+ { 0x40,0x0000 }, /* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/
+ { 0x42,0x0000 }, /* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */
+ { 0x44,0x0000 }, /* PCI Subsystem ID PCISID[15:0] */
+ { 0x46,0x0000 }, /* PCI Subsystem Vendor ID PCISVID[15:0] */
+ { 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, /* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */
+ { 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, /* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */
+ { 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, /* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */
+ { 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, /* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */
+ { 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */
+ { 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */
+ { 0x54,0x0000 }, /* Hot Swap Control/Status (Reserved) Reserved */
+ { 0x56,0x0000 }, /* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */
+ { 0x58,0x0000 }, /* Reserved Reserved */
+ { 0x5A,0x0000 }, /* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */
+ { 0x5C,0x0000 }, /* Power Management Capabilities PMC[15:9, 2:0] */
+ { 0x5E,0x0000 }, /* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/
+ { 0x60,0x0000 }, /* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */
+ { 0x62,0x0000 }, /* Power Management Control/Status PMCSR[14:8] */
+ { 0xFFFF,0xFFFF} /* terminaror */
+};
+#define PATI_EEPROM_LAST_OFFSET 0x64
+#endif /* #ifndef __PCI_EEPROM_H_ */
diff --git a/board/mpl/pati/plx9056.h b/board/mpl/pati/plx9056.h
new file mode 100644
index 0000000..754e720
--- /dev/null
+++ b/board/mpl/pati/plx9056.h
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2003
+ * Denis Peter, d.peter@mpl.ch
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/* PLX9096 register definitions
+*/
+#ifndef __PLX9056_H_
+#define __PLX9056_H_ 1
+
+#include <pci.h>
+
+#ifdef PLX9056_LOC
+#define LOCAL_OFFSET 0x080
+/* PCI Config regs */
+#else
+#define LOCAL_OFFSET 0x000
+#endif
+
+#define PCI9056_VENDOR_ID PCI_VENDOR_ID
+/*#define PCI9656_DEVICE_ID PCI_DEVICE_ID */
+#define PCI9056_COMMAND PCI_COMMAND
+/*#define PCI9656_STATUS PCI_STATUS */
+#define PCI9056_REVISION PCI_REVISION_ID
+
+#define PCI9056_CACHE_SIZE PCI_CACHE_LINE_SIZE
+#define PCI9056_RTR_BASE PCI_BASE_ADDRESS_0
+#define PCI9056_RTR_IO_BASE PCI_BASE_ADDRESS_1
+#define PCI9056_LOCAL_BASE0 PCI_BASE_ADDRESS_2
+#define PCI9056_LOCAL_BASE1 PCI_BASE_ADDRESS_3
+#define PCI9056_UNUSED_BASE1 PCI_BASE_ADDRESS_4
+#define PCI9056_UNUSED_BASE2 PCI_BASE_ADDRESS_5
+#define PCI9056_CIS_PTR PCI_CARDBUS_CIS
+#define PCI9056_SUB_ID PCI_SUBSYSTEM_VENDOR_ID
+#define PCI9056_EXP_ROM_BASE PCI_ROM_ADDRESS
+#define PCI9056_CAP_PTR PCI_CAPABILITY_LIST
+#define PCI9056_INT_LINE PCI_INTERRUPT_LINE
+
+#if defined(PLX9056_LOC)
+ #define PCI9056_PM_CAP_ID 0x180
+ #define PCI9056_PM_CSR 0x184
+ #define PCI9056_HS_CAP_ID 0x188
+ #define PCI9056_VPD_CAP_ID 0x18C
+ #define PCI9056_VPD_DATA 0x190
+#endif
+
+
+#define PCI_DEVICE_ID_PLX9056 0x9056
+
+/* Local Configuration Registers Accessible via the PCI Base address + Variable */
+#define PCI9056_SPACE0_RANGE (0x000 + LOCAL_OFFSET)
+#define PCI9056_SPACE0_REMAP (0x004 + LOCAL_OFFSET)
+#define PCI9056_LOCAL_DMA_ARBIT (0x008 + LOCAL_OFFSET)
+#define PCI9056_ENDIAN_DESC (0x00c + LOCAL_OFFSET)
+#define PCI9056_EXP_ROM_RANGE (0x010 + LOCAL_OFFSET)
+#define PCI9056_EXP_ROM_REMAP (0x014 + LOCAL_OFFSET)
+#define PCI9056_SPACE0_ROM_DESC (0x018 + LOCAL_OFFSET)
+#define PCI9056_DM_RANGE (0x01c + LOCAL_OFFSET)
+#define PCI9056_DM_MEM_BASE (0x020 + LOCAL_OFFSET)
+#define PCI9056_DM_IO_BASE (0x024 + LOCAL_OFFSET)
+#define PCI9056_DM_PCI_MEM_REMAP (0x028 + LOCAL_OFFSET)
+#define PCI9056_DM_PCI_IO_CONFIG (0x02c + LOCAL_OFFSET)
+#define PCI9056_SPACE1_RANGE (0x0f0 + LOCAL_OFFSET)
+#define PCI9056_SPACE1_REMAP (0x0f4 + LOCAL_OFFSET)
+#define PCI9056_SPACE1_DESC (0x0f8 + LOCAL_OFFSET)
+#define PCI9056_DM_DAC (0x0fc + LOCAL_OFFSET)
+
+#ifdef PLX9056_LOC
+#define PCI9056_ARBITER_CTRL 0x1A0
+#define PCI9056_ABORT_ADDRESS 0x1A4
+#endif
+
+/* Runtime registers PCI Address + LOCAL_OFFSET */
+#ifdef PLX9056_LOC
+#define PCI9056_MAILBOX0 0x0C0
+#define PCI9056_MAILBOX1 0x0C4
+#else
+#define PCI9056_MAILBOX0 0x078
+#define PCI9056_MAILBOX1 0x07c
+#endif
+
+#define PCI9056_MAILBOX2 (0x048 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX3 (0x04c + LOCAL_OFFSET)
+#define PCI9056_MAILBOX4 (0x050 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX5 (0x054 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX6 (0x058 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX7 (0x05c + LOCAL_OFFSET)
+#define PCI9056_PCI_TO_LOC_DBELL (0x060 + LOCAL_OFFSET)
+#define PCI9056_LOC_TO_PCI_DBELL (0x064 + LOCAL_OFFSET)
+#define PCI9056_INT_CTRL_STAT (0x068 + LOCAL_OFFSET)
+#define PCI9056_EEPROM_CTRL_STAT (0x06c + LOCAL_OFFSET)
+#define PCI9056_PERM_VENDOR_ID (0x070 + LOCAL_OFFSET)
+#define PCI9056_REVISION_ID (0x074 + LOCAL_OFFSET)
+
+#endif /* #ifndef __PLX9056_H_ */
diff --git a/board/mpl/pip405/Kconfig b/board/mpl/pip405/Kconfig
new file mode 100644
index 0000000..f485367
--- /dev/null
+++ b/board/mpl/pip405/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PIP405
+
+config SYS_BOARD
+ default "pip405"
+
+config SYS_VENDOR
+ default "mpl"
+
+config SYS_CONFIG_NAME
+ default "PIP405"
+
+endif
diff --git a/board/mpl/pip405/MAINTAINERS b/board/mpl/pip405/MAINTAINERS
new file mode 100644
index 0000000..9b3b974
--- /dev/null
+++ b/board/mpl/pip405/MAINTAINERS
@@ -0,0 +1,6 @@
+PIP405 BOARD
+M: Denis Peter <d.peter@mpl.ch>
+S: Maintained
+F: board/mpl/pip405/
+F: include/configs/PIP405.h
+F: configs/PIP405_defconfig
diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile
new file mode 100644
index 0000000..0a3d059
--- /dev/null
+++ b/board/mpl/pip405/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = pip405.o cmd_pip405.o \
+ ../common/pci.o \
+ ../common/isa.o \
+ ../common/kbd.o \
+ ../common/usb_uhci.o \
+ ../common/common_util.o
+obj-y += init.o
diff --git a/board/mpl/pip405/README b/board/mpl/pip405/README
new file mode 100644
index 0000000..012db1c
--- /dev/null
+++ b/board/mpl/pip405/README
@@ -0,0 +1,375 @@
+U-Boot Changes due to PIP405 Port:
+===================================
+
+Changed files:
+==============
+- MAKEALL added PIP405
+- makefile added PIP405
+- common/Makefile added Floppy disk and SCSI support
+- common/board.c added PIP405, SCSI support, get_PCI_freq()
+- common/bootm.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
+- common/cmd_i2c.c added "defined(CONFIG_PIP405)"
+- common/cmd_ide.c changed div. functions to work with block device
+ description
+ added ATAPI support
+- common/command.c added SCSI and Floppy support
+- common/console.c replaced // with /* comments
+ added console settings from environment
+- common/devices.c added ISA keyboard init
+- common/main.c corrected the read of bootdelay
+- arch/powerpc/cpu/ppc4xx/405gp_pci.c excluded file from PIP405
+- arch/powerpc/cpu/ppc4xx/i2c.c added 16bit read write I2C support
+ added page write
+- arch/powerpc/cpu/ppc4xx/speed.c added get_PCI_freq
+- arch/powerpc/cpu/ppc4xx/start.S added CONFIG_IDENT_STRING
+- disk/Makefile added part_iso for CD support
+- disk/part.c changed to work with block device description
+ added ISO CD support
+ added dev_print (was ide_print in cmd_ide.c)
+- disk/part_dos.c changed to work with block device description
+- disk/part_mac.c changed to work with block device description
+- include/ata.h added ATAPI commands
+- include/cmd_bsp.h added PIP405 commands definitions
+- include/cmd_condefs.h added Floppy and SCSI support
+- include/cmd_disk.h changed to work with block device description
+- include/config_LANTEC.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI
+- include/config_hymod.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI
+- include/flash.h added INTEL_ID_28F320C3T 0x88C488C4
+- include/i2c.h added "defined(CONFIG_PIP405)"
+- include/image.h added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
+- include/u-boot.h moved partitions functions definitions to part.h
+ added "defined(CONFIG_PIP405)"
+ added get_PCI_freq() definition
+- rtc/Makefile added MC146818 RTC support
+- tools/mkimage.c added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
+
+Added files:
+============
+- board/pip405 directory for PIP405
+- board/pip405/cmd_pip405.c board specific commands
+- board/pip405/config.mk config make
+- board/pip405/flash.c flash support
+- board/pip405/init.s start-up
+- board/pip405/kbd.c keyboard support
+- board/pip405/kbd.h keyboard support
+- board/pip405/Makefile Makefile
+- board/pip405/pci_piix4.h southbridge definitions
+- board/pip405/pci_pip405.c PCI support for PIP405
+- board/pip405/pci_pip405.h PCI support for PIP405
+- board/pip405/pip405.c PIP405 board init
+- board/pip405/pip405.h PIP405 board init
+- board/pip405/pip405_isa.c ISA support
+- board/pip405/pip405_isa.h ISA support
+- board/pip405/u-boot.lds Linker description
+- board/pip405/u-boot.lds.debugLinker description debug
+- board/pip405/sym53c8xx.c SYM53C810A support
+- board/pip405/sym53c8xx_defs.h SYM53C810A definitions
+- board/pip405/vga_table.h definitions of tables for VGA
+- board/pip405/video.c CT69000 support
+- board/pip405/video.h CT69000 support
+- common/cmd_fdc.c Floppy disk support
+- common/cmd_scsi.c SCSI support
+- disk/part_iso.c ISO CD ROM support
+- disk/part_iso.h ISO CD ROM support
+- include/cmd_fdc.h command forFloppy disk support
+- include/cmd_scsi.h command for SCSI support
+- include/part.h partitions functions definitions
+ (was part of u-boot.h)
+- include/scsi.h SCSI support
+- rtc/mc146818.c MC146818 RTC support
+
+
+New Config Switches:
+====================
+For detailed description, refer to the corresponding paragraph in the
+section "Changes".
+
+New Commands:
+-------------
+CONFIG_CMD_SCSI SCSI Support
+CONFIG_CMF_FDC Floppy disk support
+
+IDE additions:
+--------------
+CONFIG_IDE_RESET_ROUTINE defines that instead of a reset Pin,
+ the routine ide_set_reset(int idereset) is used.
+ATAPI support (experimental)
+----------------------------
+CONFIG_ATAPI enables ATAPI Support
+
+SCSI support (experimental) only SYM53C8xx supported
+----------------------------------------------------
+CONFIG_SCSI_SYM53C8XX type of SCSI controller
+CONFIG_SYS_SCSI_MAX_LUN 8 number of supported LUNs
+CONFIG_SYS_SCSI_MAX_SCSI_ID 7 maximum SCSI ID (0..6)
+CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN
+ maximum of Target devices (multiple LUN support
+ for boot)
+
+ISO (CD-Boot) partition support (Experimental)
+----------------------------------------------
+CONFIG_ISO_PARTITION CD-boot support
+
+RTC
+----
+CONFIG_RTC_MC146818 MC146818 RTC support
+
+Keyboard:
+---------
+CONFIG_ISA_KEYBOARD Standard (PC-Style) Keyboard support
+
+Video:
+------
+CONFIG_VIDEO_CT69000 Enable Chips & Technologies 69000 Video chip
+ CONFIG_VIDEO must be defined also
+
+External peripheral base address:
+---------------------------------
+CONFIG_SYS_ISA_IO_BASE_ADDRESS address of all ISA-bus related parts
+ _must_ be defined for ISA-bus parts
+
+Identify:
+---------
+CONFIG_IDENT_STRING added to the U_BOOT_VERSION String
+
+Environment / Console:
+----------------------
+
+CONFIG_SYS_CONSOLE_IS_IN_ENV if defined, stdin, stdout and stderr used from
+ the values stored in the evironment.
+
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE if defined, console_overwrite() decides if the
+ values stored in the environment or the standard
+ serial in/out put should be assigned to the console.
+
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE if defined, the start-up console switching
+ are stored in the environment.
+
+PIP405 specific:
+----------------
+CONFIG_PORT_ADDR address used to read boot configuration
+MULTI_PURPOSE_SOCKET_ADDR address of the multi purpose socked
+SDRAM_EEPROM_WRITE_ADDRESS addresses of the serial presence detect
+SDRAM_EEPROM_READ_ADDRESS EEPROM on the SDRAM module.
+
+
+Changes:
+========
+
+Added Devices:
+==============
+
+Floppy support:
+---------------
+Support of a standard floppy disk controller at address CONFIG_SYS_ISA_IO_BASE_ADDRESS
++ 0x3F0. Enabled with define CONFIG_CMD_FDC. Reads a unformated floppy disk
+with a image header (see: mkimage). No interrupts and no DMA are used for this.
+Added files:
+- common/cmd_fdc.c
+- include/cmd_fdc.h
+
+SCSI support:
+-------------
+Support for Symbios SYM53C810A chip. Implemented as follows:
+- without disconnect
+- only asynchrounous
+- multiple LUN support (caution, needs a lot of RAM. define CONFIG_SYS_SCSI_MAX_LUN 1 to
+ save RAM)
+- multiple SCSI ID support
+- no write support
+- analyses the MAC, DOS and ISO pratition similar to the IDE support
+- allows booting from SCSI devices similar to the IDE support.
+The device numbers are not assigned like they are within the IDE support. The first
+device found will get the number 0, the next 1 etc. If all SCSI IDs (0..6) and all
+LUNs (8) are enabled, 56 boot devices are possible. This uses a lot of RAM since the
+device descriptors are not yet dynamically allocated. 56 boot devices are overkill
+anyway. Please refer to the section "Todo" chapter "block device support enhancement".
+The SYM53C810A uses 1 Interrupt and must be able of mastering the PCI bus.
+Added files:
+- common/cmd_scsi.c
+- common/board.c
+- include/cmd_scsi.h
+- include/scsi.h
+- board/pip405/sym53c8xx.c
+- board/pip405/sym53c8xx_defs.h
+
+ATAPI support (IDE changes):
+----------------------------
+Added ATAPI support (with CONFIG_ATAPI) in the file cmd_ide.c.
+To support a hardreset, when the IDE reset pin is not connected to the
+CONFIG_SYS_PC_IDE_RESET pin, the switch CONFIG_IDE_RESET_ROUTINE has been added. When
+this switch is enabled the routine void ide_set_reset(int idereset) must be
+within the board specific files.
+Only read from ATAPI devices are supported.
+Found out that the function trim_trail cuts off the last character if the whole
+string is filled. Added function cpy_ident instead, which trims also leading
+spaces and copies the string in the buffer.
+Changed files:
+- common/cmd_ide.c
+- include/ata.h
+
+ISO partition support:
+----------------------
+Added CD boot support for El-Torito bootable ISO CDs. The bootfile image must contain
+the U-Boot image header. Since CDs do not have "partitions", the boot partition is 0.
+The bootcatalog feature has not been tested so far. CD Boot is supported for ATAPI
+("diskboot") and SCSI ("scsiboot") devices.
+Added files:
+- disk/iso_part.c
+- disk/iso_part.h
+
+Block device changes:
+---------------------
+To allow the use of dos_part.c, mac_part.c and iso_part.c, the parameter
+block_dev_desc will be used when accessing the functions in these files. The block
+device descriptor (block_dev_desc) contains a pointer to the read routine of the
+device, which will be used to read blocks from the device.
+Renamed function ide_print to dev_print and moved it to the file disk/part.c to use
+it for IDE ATAPI and SCSI devices.
+Please refer to the section "Todo" chapter "block device support enhancement".
+Added files:
+- include/part.h
+changed files:
+- disk/dos_part.c
+- disk/dos_part.h
+- disk/mac_part.c
+- disk/mac_part.h
+- disk/part.c
+- common/cmd_ide.c
+- include/u-boot.h
+
+
+MC146818 RTC support:
+---------------------
+Added support for MC146818 RTC with defining CONFIG_RTC_MC146818. The ISA bus IO
+base address must be defined with CONFIG_SYS_ISA_IO_BASE_ADDRESS.
+Added files:
+- rtc/mc146818.c
+
+Standard ISA bus Keyboard support:
+----------------------------------
+Added support for the standard PC kyeboard controller. For the PIP405 the superIO
+controller must be set up previously. The keyboard uses the standard ISA IRQ, so
+the ISA PIC must also be set up.
+Added files:
+- board/pip405/kbd.c
+- board/pip405/kbd.h
+- board/pip405/pip405_isa.c
+- board/pip405/pip405_isa.h
+
+Chips and Technologie 69000 VGA controller support:
+---------------------------------------------------
+Added support for the CT69000 VGA controller.
+Added files:
+- board/pip405/video.c
+- board/pip405/video.h
+- board/pip405/vga_table.h
+
+
+Changed Items:
+==============
+
+Identify:
+---------
+Added the config variable CONFIG_IDENT_STRING which will be added to the
+"U_BOOT_VERSION __TIME__ DATE___ " String, to allows to identify intermidiate
+and custom versions.
+Changed files:
+- arch/powerpc/cpu/ppc4xx/start.s
+
+Firmware Image:
+---------------
+Added IH_OS_U_BOOT and IH_TYPE_FIRMWARE to the image definitions to allows the
+U-Boot update with prior CRC check.
+Changed files:
+- include/image.h
+- tools/mkimage.c
+- common/cmd_bootm.c
+
+Correct PCI Frequency for PPC405:
+---------------------------------
+Added function (in arch/powerpc/cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU.
+The PCI Frequency will now be set correct in the board description in common/board.c.
+(was set to the busfreq before).
+Changed files:
+- arch/powerpc/cpu/ppc4xx/speed.c
+- common/board.c
+
+I2C Stuff:
+----------
+Added defined(CONFIG_PIP405) at several points in common/cmd_i2c.c.
+Added 16bit read/write support for I2C (PPC405), and page write to
+I2C EEPROM if defined CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE.
+Changed files:
+- arch/powerpc/cpu/ppc4xx/i2c.c
+- common/cmd_i2c.c
+
+Environment / Console:
+----------------------
+Although in README.console described, the U-Boot has not assinged the values
+found in the environment to the console. Corrected this behavior, but only if
+CONFIG_SYS_CONSOLE_IS_IN_ENV is defined.
+If CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is defined, console_overwrite() decides if the
+values stored in the environment or the standard serial in/output should be
+assigned to the console. This is useful if the environment values are not correct.
+If CONFIG_SYS_CONSOLE_ENV_OVERWRITE is defined the devices assigned to the console at
+start-up time will be written to the environment. This means that if the
+environment values are overwritten by the overwrite_console() routine, they will be
+stored in the environment.
+Changed files:
+- common/console.c
+
+Correct bootdelay intepretation:
+--------------------------------
+Changed bootdelay read from the environment from simple_strtoul (unsigned) to
+simple_strtol (signed), to be able to get a bootdelay of -1.
+Changed files:
+- common/main.c
+
+Todo:
+=====
+
+Block device support enhancement:
+---------------------------------
+Consider to unify the block device handling. Instead of using diskboot for IDE,
+scsiboot for SCSI and fdcboot for floppy disks, it would make sense to use only
+one command ("devboot" ???) with a parameter of the desired device ("hda1", "sda1",
+"fd0" ???) to boot from. The other ide commands can be handled in the same way
+("dev hda read.." instead of "ide read.." or "dev sda read.." instead of
+"scsi read..."). Todo this, a common way of assign a block device to its name
+(first found ide device = hda, second found hdb etc., or hda is device 0 on bus 0,
+hdb is device 1 on bus 0 etc.) as well as the names (hdx for ide, sdx for scsi, fx for
+floppy ???) must be defined.
+Maybe there are better ideas to do this.
+
+Console assingment:
+-------------------
+Consider to initialize and assign the console stdin, stdout and stderr as soon as
+possible to see the boot messages also on an other console than serial.
+
+
+Todo for PIP405:
+================
+
+LCD support for VGA:
+--------------------
+Add LCD support for the CT69000
+
+Default environment:
+--------------------
+Consider to write a default environment to the OTP part of the EEPROM and use it
+if the normal environment is not valid. Useful for serial# and ethaddr values.
+
+Watchdog:
+---------
+Implement Watchdog.
+
+Files clean-up:
+---------------
+Following files needs to be cleaned up:
+- cmd_pip405.c
+- flash.c
+- pci_pip405.c
+- pip405.c
+- pip405_isa.c
+Consider to split up the files in their functions.
diff --git a/board/mpl/pip405/cmd_pip405.c b/board/mpl/pip405/cmd_pip405.c
new file mode 100644
index 0000000..43b182e
--- /dev/null
+++ b/board/mpl/pip405/cmd_pip405.c
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * hacked for PIP405
+ */
+
+#include <common.h>
+#include <command.h>
+#include "pip405.h"
+#include "../common/common_util.h"
+
+
+extern void print_pip405_info(void);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+
+/* ------------------------------------------------------------------------- */
+
+int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+
+ ulong led_on,led_nr;
+
+ if (strcmp(argv[1], "info") == 0)
+ {
+ print_pip405_info();
+ return 0;
+ }
+ if (strcmp(argv[1], "led") == 0)
+ {
+ led_nr = (ulong)simple_strtoul(argv[2], NULL, 10);
+ led_on = (ulong)simple_strtoul(argv[3], NULL, 10);
+ if(!led_nr)
+ user_led0(led_on);
+ else
+ user_led1(led_on);
+ return 0;
+ }
+
+ return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+U_BOOT_CMD(
+ pip405, 6, 1, do_pip405,
+ "PIP405 specific Cmds",
+ "flash mem [SrcAddr] - updates U-Boot with image in memory\n"
+ "pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n"
+ "pip405 flash mps - updates U-Boot with image from MPS"
+);
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S
new file mode 100644
index 0000000..292393e
--- /dev/null
+++ b/board/mpl/pip405/init.S
@@ -0,0 +1,197 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0 IBM-pibs
+ */
+/*-----------------------------------------------------------------------------
+ * Function: ext_bus_cntlr_init
+ * Description: Initializes the External Bus Controller for the external
+ * peripherals. IMPORTANT: For pass1 this code must run from
+ * cache since you can not reliably change a peripheral banks
+ * timing register (pbxap) while running code from that bank.
+ * For ex., since we are running from ROM on bank 0, we can NOT
+ * execute the code that modifies bank 0 timings from ROM, so
+ * we run it from cache.
+ * Bank 0 - Flash or Multi Purpose Socket
+ * Bank 1 - Multi Purpose Socket or Flash
+ * Bank 2 - not used
+ * Bank 3 - not used
+ * Bank 4 - not used
+ * Bank 5 - not used
+ * Bank 6 - used to switch on the 12V for the Multipurpose socket
+ * Bank 7 - Config Register
+ *-----------------------------------------------------------------------------*/
+
+#include <configs/PIP405.h>
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+#include "pip405.h"
+
+ .globl ext_bus_cntlr_init
+ ext_bus_cntlr_init:
+ mflr r4 /* save link register */
+ mfdcr r3,CPC0_PSR /* get strapping reg */
+ andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
+ bnelr /* jump back if PCI boot */
+
+ bl ..getAddr
+..getAddr:
+ mflr r3 /* get address of ..getAddr */
+ mtlr r4 /* restore link register */
+ addi r4,0,14 /* set ctr to 14; used to prefetch */
+ mtctr r4 /* 14 cache lines to fit this function */
+ /* in cache (gives us 8x14=112 instrctns) */
+..ebcloop:
+ icbt r0,r3 /* prefetch cache line for addr in r3 */
+ addi r3,r3,32 /* move to next cache line */
+ bdnz ..ebcloop /* continue for 14 cache lines */
+
+ /*-------------------------------------------------------------------
+ * Delay to ensure all accesses to ROM are complete before changing
+ * bank 0 timings.
+ *------------------------------------------------------------------- */
+ addis r3,0,0x0
+ ori r3,r3,0xA000
+ mtctr r3
+..spinlp:
+ bdnz ..spinlp /* spin loop */
+
+ /*-----------------------------------------------------------------------
+ * decide boot up mode
+ *----------------------------------------------------------------------- */
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
+ mfdcr r4,EBC0_CFGDATA
+
+ andi. r0, r4, 0x2000 /* mask out irrelevant bits */
+ beq 0f /* jump if 8 bit bus width */
+
+ /* setup 16 bit things
+ *-----------------------------------------------------------------------
+ * Memory Bank 0 (16 Bit Flash) initialization
+ *---------------------------------------------------------------------- */
+
+ addi r4,0,PB1AP
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,(FLASH_AP_B)@h
+ ori r4,r4,(FLASH_AP_B)@l
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
+ /* BS=0x010(4MB),BU=0x3(R/W), */
+ addis r4,0,(FLASH_CR_B)@h
+ ori r4,r4,(FLASH_CR_B)@l
+ mtdcr EBC0_CFGDATA,r4
+ b 1f
+
+0:
+ /* 8Bit boot mode: */
+ /*-----------------------------------------------------------------------
+ * Memory Bank 0 Multi Purpose Socket initialization
+ *----------------------------------------------------------------------- */
+ /* 0x7F8FFE80 slowest boot */
+ addi r4,0,PB1AP
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,(MPS_AP_B)@h
+ ori r4,r4,(MPS_AP_B)@l
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB0CR
+ mtdcr EBC0_CFGADDR,r4
+ /* BS=0x010(4MB),BU=0x3(R/W), */
+ addis r4,0,(MPS_CR_B)@h
+ ori r4,r4,(MPS_CR_B)@l
+ mtdcr EBC0_CFGDATA,r4
+
+
+1:
+ /*-----------------------------------------------------------------------
+ * Memory Bank 2-3-4-5-6 (not used) initialization
+ *-----------------------------------------------------------------------*/
+ addi r4,0,PB1CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB2CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB3CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB4CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB5CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB6CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+
+ addi r4,0,PB7CR
+ mtdcr EBC0_CFGADDR,r4
+ addis r4,0,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+ nop /* pass2 DCR errata #8 */
+ blr
+
+#if defined(CONFIG_BOOT_PCI)
+ .section .bootpg,"ax"
+ .globl _start_pci
+/*******************************************
+ */
+
+_start_pci:
+ /* first handle errata #68 / PCI_18 */
+ iccci r0, r0 /* invalidate I-cache */
+ lis r31, 0
+ mticcr r31 /* ICCR = 0 (all uncachable) */
+ isync
+
+ mfccr0 r28 /* set CCR0[24] = 1 */
+ ori r28, r28, 0x0080
+ mtccr0 r28
+
+ /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
+ lis r28, 0xEF40
+ addi r28, r28, 0x0004
+ stw r31, 0x0C(r28) /* clear PMM0PCIHA */
+ lis r29, 0xFFF8 /* open 512 kByte */
+ addi r29, r29, 0x0001/* and enable this region */
+ stwbrx r29, r0, r28 /* write PMM0MA */
+
+ lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
+ addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
+
+ lis r31, 0x8000 /* set en bit bus 0 */
+ ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
+ stwbrx r31, r0, r28 /* write it */
+
+ lwbrx r31, r0, r29 /* load XBCS register */
+ oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
+ stwbrx r31, r0, r29 /* write back XBCS register */
+
+ nop
+ nop
+ b _start /* normal start */
+#endif
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
new file mode 100644
index 0000000..7c7690f
--- /dev/null
+++ b/board/mpl/pip405/pip405.c
@@ -0,0 +1,956 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * TODO: clean-up
+ */
+
+#include <common.h>
+#include "pip405.h"
+#include <asm/processor.h>
+#include <i2c.h>
+#include <stdio_dev.h>
+#include "../common/isa.h"
+#include "../common/common_util.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef SDRAM_DEBUG
+
+/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
+#ifndef __ldiv_t_defined
+typedef struct {
+ long int quot; /* Quotient */
+ long int rem; /* Remainder */
+} ldiv_t;
+extern ldiv_t ldiv (long int __numer, long int __denom);
+
+# define __ldiv_t_defined 1
+#endif
+
+
+typedef enum {
+ SDRAM_NO_ERR,
+ SDRAM_SPD_COMM_ERR,
+ SDRAM_SPD_CHKSUM_ERR,
+ SDRAM_UNSUPPORTED_ERR,
+ SDRAM_UNKNOWN_ERR
+} SDRAM_ERR;
+
+typedef struct {
+ const unsigned char mode;
+ const unsigned char row;
+ const unsigned char col;
+ const unsigned char bank;
+} SDRAM_SETUP;
+
+static const SDRAM_SETUP sdram_setup_table[] = {
+ {1, 11, 9, 2},
+ {1, 11, 10, 2},
+ {2, 12, 9, 4},
+ {2, 12, 10, 4},
+ {3, 13, 9, 4},
+ {3, 13, 10, 4},
+ {3, 13, 11, 4},
+ {4, 12, 8, 2},
+ {4, 12, 8, 4},
+ {5, 11, 8, 2},
+ {5, 11, 8, 4},
+ {6, 13, 8, 2},
+ {6, 13, 8, 4},
+ {7, 13, 9, 2},
+ {7, 13, 10, 2},
+ {0, 0, 0, 0}
+};
+
+static const unsigned char cal_indextable[] = {
+ 9, 23, 25
+};
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+
+unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
+{
+ unsigned short ns, ns10;
+
+ /* isolate upper nibble */
+ ns = (spd_byte >> 4) & 0x0F;
+ /* isolate lower nibble */
+ ns10 = (spd_byte & 0x0F);
+
+ return (ns * 100 + ns10 * 10);
+}
+
+/*
+ * translate ns.ns/4 coding of SPD timing values
+ * into 10 ps unit values
+ */
+
+unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
+{
+ unsigned short ns, ns4;
+
+ /* isolate upper 6 bits */
+ ns = (spd_byte >> 2) & 0x3F;
+ /* isloate lower 2 bits */
+ ns4 = (spd_byte & 0x03);
+
+ return (ns * 100 + ns4 * 25);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+
+unsigned short NSto10PS (unsigned char spd_byte)
+{
+ return (spd_byte * 100);
+}
+
+void SDRAM_err (const char *s)
+{
+#ifndef SDRAM_DEBUG
+ (void) get_clocks ();
+ gd->baudrate = 9600;
+ serial_init ();
+#endif
+ serial_puts ("\n");
+ serial_puts (s);
+ serial_puts ("\n enable SDRAM_DEBUG for more info\n");
+ for (;;);
+}
+
+
+#ifdef SDRAM_DEBUG
+
+void write_hex (unsigned char i)
+{
+ char cc;
+
+ cc = i >> 4;
+ cc &= 0xf;
+ if (cc > 9)
+ serial_putc (cc + 55);
+ else
+ serial_putc (cc + 48);
+ cc = i & 0xf;
+ if (cc > 9)
+ serial_putc (cc + 55);
+ else
+ serial_putc (cc + 48);
+}
+
+void write_4hex (unsigned long val)
+{
+ write_hex ((unsigned char) (val >> 24));
+ write_hex ((unsigned char) (val >> 16));
+ write_hex ((unsigned char) (val >> 8));
+ write_hex ((unsigned char) val);
+}
+
+#endif
+
+int board_early_init_f (void)
+{
+ unsigned char datain[128];
+ unsigned long sdram_size = 0;
+ SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
+ unsigned long memclk;
+ unsigned long tmemclk = 0;
+ unsigned long tmp, bank, baseaddr, bank_size;
+ unsigned short i;
+ unsigned char rows, cols, banks, sdram_banks, density;
+ unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
+ trc_clocks;
+ unsigned char cal_index, cal_val, spd_version, spd_chksum;
+ unsigned char buf[8];
+#ifdef SDRAM_DEBUG
+ unsigned char tctp_clocks;
+#endif
+
+ /* set up the config port */
+ mtdcr (EBC0_CFGADDR, PB7AP);
+ mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP);
+ mtdcr (EBC0_CFGADDR, PB7CR);
+ mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR);
+
+ memclk = get_bus_freq (tmemclk);
+ tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
+
+#ifdef SDRAM_DEBUG
+ (void) get_clocks ();
+ gd->baudrate = 9600;
+ serial_init ();
+ serial_puts ("\nstart SDRAM Setup\n");
+#endif
+
+ /* Read Serial Presence Detect Information */
+ i2c_set_bus_num(0);
+ for (i = 0; i < 128; i++)
+ datain[i] = 127;
+ i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
+#ifdef SDRAM_DEBUG
+ serial_puts ("\ni2c_read returns ");
+ write_hex (i);
+ serial_puts ("\n");
+#endif
+
+#ifdef SDRAM_DEBUG
+ for (i = 0; i < 128; i++) {
+ write_hex (datain[i]);
+ serial_puts (" ");
+ if (((i + 1) % 16) == 0)
+ serial_puts ("\n");
+ }
+ serial_puts ("\n");
+#endif
+ spd_chksum = 0;
+ for (i = 0; i < 63; i++) {
+ spd_chksum += datain[i];
+ } /* endfor */
+ if (datain[63] != spd_chksum) {
+#ifdef SDRAM_DEBUG
+ serial_puts ("SPD chksum: 0x");
+ write_hex (datain[63]);
+ serial_puts (" != calc. chksum: 0x");
+ write_hex (spd_chksum);
+ serial_puts ("\n");
+#endif
+ SDRAM_err ("SPD checksum Error");
+ }
+ /* SPD seems to be ok, use it */
+
+ /* get SPD version */
+ spd_version = datain[62];
+
+ /* do some sanity checks on the kind of RAM */
+ if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */
+ (datain[2] != 0x04) || /* if not SDRAM */
+ (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */
+ (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */
+ (datain[126] == 0x66)) /* or a 66MHz modules */
+ SDRAM_err ("unsupported SDRAM");
+#ifdef SDRAM_DEBUG
+ serial_puts ("SDRAM sanity ok\n");
+#endif
+
+ /* get number of rows/cols/banks out of byte 3+4+5 */
+ rows = datain[3];
+ cols = datain[4];
+ banks = datain[5];
+
+ /* get number of SDRAM banks out of byte 17 and
+ supported CAS latencies out of byte 18 */
+ sdram_banks = datain[17];
+ supported_cal = datain[18] & ~0x81;
+
+ while (t->mode != 0) {
+ if ((t->row == rows) && (t->col == cols)
+ && (t->bank == sdram_banks))
+ break;
+ t++;
+ } /* endwhile */
+
+#ifdef SDRAM_DEBUG
+ serial_puts ("rows: ");
+ write_hex (rows);
+ serial_puts (" cols: ");
+ write_hex (cols);
+ serial_puts (" banks: ");
+ write_hex (banks);
+ serial_puts (" mode: ");
+ write_hex (t->mode);
+ serial_puts ("\n");
+#endif
+ if (t->mode == 0)
+ SDRAM_err ("unsupported SDRAM");
+ /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
+#ifdef SDRAM_DEBUG
+ serial_puts ("tRP: ");
+ write_hex (datain[27]);
+ serial_puts ("\ntRCD: ");
+ write_hex (datain[29]);
+ serial_puts ("\ntRAS: ");
+ write_hex (datain[30]);
+ serial_puts ("\n");
+#endif
+
+ trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
+ trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
+ tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
+ density = datain[31];
+
+ /* trc_clocks is sum of trp_clocks + tras_clocks */
+ trc_clocks = trp_clocks + tras_clocks;
+
+#ifdef SDRAM_DEBUG
+ /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
+ tctp_clocks =
+ ((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
+ (tmemclk - 1)) / tmemclk;
+
+ serial_puts ("c_RP: ");
+ write_hex (trp_clocks);
+ serial_puts ("\nc_RCD: ");
+ write_hex (trcd_clocks);
+ serial_puts ("\nc_RAS: ");
+ write_hex (tras_clocks);
+ serial_puts ("\nc_RC: (RP+RAS): ");
+ write_hex (trc_clocks);
+ serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
+ write_hex (tctp_clocks);
+ serial_puts ("\nt_CTP: RAS - RCD: ");
+ write_hex ((unsigned
+ char) ((NSto10PS (datain[30]) -
+ NSto10PS (datain[29])) >> 8));
+ write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
+ serial_puts ("\ntmemclk: ");
+ write_hex ((unsigned char) (tmemclk >> 8));
+ write_hex ((unsigned char) (tmemclk));
+ serial_puts ("\n");
+#endif
+
+
+ cal_val = 255;
+ for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
+ /* is this CAS latency supported ? */
+ if ((supported_cal >> i) & 0x01) {
+ buf[0] = datain[cal_indextable[cal_index]];
+ if (cal_index < 2) {
+ if (NS10to10PS (buf[0], spd_version) <= tmemclk)
+ cal_val = i;
+ } else {
+ /* SPD bytes 25+26 have another format */
+ if (NS4to10PS (buf[0], spd_version) <= tmemclk)
+ cal_val = i;
+ } /* endif */
+ cal_index++;
+ } /* endif */
+ } /* endfor */
+#ifdef SDRAM_DEBUG
+ serial_puts ("CAL: ");
+ write_hex (cal_val + 1);
+ serial_puts ("\n");
+#endif
+
+ if (cal_val == 255)
+ SDRAM_err ("unsupported SDRAM");
+
+ /* get SDRAM timing register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+ tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
+ /* insert CASL value */
+/* tmp |= ((unsigned long)cal_val) << 23; */
+ tmp |= ((unsigned long) cal_val) << 23;
+ /* insert PTA value */
+ tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
+ /* insert CTP value */
+/* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
+ tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
+ /* insert LDF (always 01) */
+ tmp |= ((unsigned long) 0x01) << 14;
+ /* insert RFTA value */
+ tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
+ /* insert RCD value */
+ tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
+
+#ifdef SDRAM_DEBUG
+ serial_puts ("sdtr: ");
+ write_4hex (tmp);
+ serial_puts ("\n");
+#endif
+
+ /* write SDRAM timing register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+ mtdcr (SDRAM0_CFGDATA, tmp);
+ baseaddr = CONFIG_SYS_SDRAM_BASE;
+ bank_size = (((unsigned long) density) << 22) / 2;
+ /* insert AM value */
+ tmp = ((unsigned long) t->mode - 1) << 13;
+ /* insert SZ value; */
+ switch (bank_size) {
+ case 0x00400000:
+ tmp |= ((unsigned long) 0x00) << 17;
+ break;
+ case 0x00800000:
+ tmp |= ((unsigned long) 0x01) << 17;
+ break;
+ case 0x01000000:
+ tmp |= ((unsigned long) 0x02) << 17;
+ break;
+ case 0x02000000:
+ tmp |= ((unsigned long) 0x03) << 17;
+ break;
+ case 0x04000000:
+ tmp |= ((unsigned long) 0x04) << 17;
+ break;
+ case 0x08000000:
+ tmp |= ((unsigned long) 0x05) << 17;
+ break;
+ case 0x10000000:
+ tmp |= ((unsigned long) 0x06) << 17;
+ break;
+ default:
+ SDRAM_err ("unsupported SDRAM");
+ } /* endswitch */
+ /* get SDRAM bank 0 register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
+ bank |= (baseaddr | tmp | 0x01);
+#ifdef SDRAM_DEBUG
+ serial_puts ("bank0: baseaddr: ");
+ write_4hex (baseaddr);
+ serial_puts (" banksize: ");
+ write_4hex (bank_size);
+ serial_puts (" mb0cf: ");
+ write_4hex (bank);
+ serial_puts ("\n");
+#endif
+ baseaddr += bank_size;
+ sdram_size += bank_size;
+
+ /* write SDRAM bank 0 register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ mtdcr (SDRAM0_CFGDATA, bank);
+
+ /* get SDRAM bank 1 register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+ bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
+ sdram_size = 0;
+
+#ifdef SDRAM_DEBUG
+ serial_puts ("bank1: baseaddr: ");
+ write_4hex (baseaddr);
+ serial_puts (" banksize: ");
+ write_4hex (bank_size);
+#endif
+ if (banks == 2) {
+ bank |= (baseaddr | tmp | 0x01);
+ baseaddr += bank_size;
+ sdram_size += bank_size;
+ } /* endif */
+#ifdef SDRAM_DEBUG
+ serial_puts (" mb1cf: ");
+ write_4hex (bank);
+ serial_puts ("\n");
+#endif
+ /* write SDRAM bank 1 register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+ mtdcr (SDRAM0_CFGDATA, bank);
+
+ /* get SDRAM bank 2 register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+ bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
+
+ bank |= (baseaddr | tmp | 0x01);
+
+#ifdef SDRAM_DEBUG
+ serial_puts ("bank2: baseaddr: ");
+ write_4hex (baseaddr);
+ serial_puts (" banksize: ");
+ write_4hex (bank_size);
+ serial_puts (" mb2cf: ");
+ write_4hex (bank);
+ serial_puts ("\n");
+#endif
+
+ baseaddr += bank_size;
+ sdram_size += bank_size;
+
+ /* write SDRAM bank 2 register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+ mtdcr (SDRAM0_CFGDATA, bank);
+
+ /* get SDRAM bank 3 register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+ bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
+
+#ifdef SDRAM_DEBUG
+ serial_puts ("bank3: baseaddr: ");
+ write_4hex (baseaddr);
+ serial_puts (" banksize: ");
+ write_4hex (bank_size);
+#endif
+
+ if (banks == 2) {
+ bank |= (baseaddr | tmp | 0x01);
+ baseaddr += bank_size;
+ sdram_size += bank_size;
+ }
+ /* endif */
+#ifdef SDRAM_DEBUG
+ serial_puts (" mb3cf: ");
+ write_4hex (bank);
+ serial_puts ("\n");
+#endif
+
+ /* write SDRAM bank 3 register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+ mtdcr (SDRAM0_CFGDATA, bank);
+
+
+ /* get SDRAM refresh interval register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+ tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
+
+ if (tmemclk < NSto10PS (16))
+ tmp |= 0x05F00000;
+ else
+ tmp |= 0x03F80000;
+
+ /* write SDRAM refresh interval register */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+ mtdcr (SDRAM0_CFGDATA, tmp);
+
+ /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000;
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ mtdcr (SDRAM0_CFGDATA, tmp);
+
+
+ /*-------------------------------------------------------------------------+
+ | Interrupt controller setup for the PIP405 board.
+ | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
+ | IRQ 16 405GP internally generated; active low; level sensitive
+ | IRQ 17-24 RESERVED
+ | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
+ | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
+ | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
+ | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+ | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+ | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+ | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+ | Note for PIP405 board:
+ | An interrupt taken for the SouthBridge (IRQ 25) indicates that
+ | the Interrupt Controller in the South Bridge has caused the
+ | interrupt. The IC must be read to determine which device
+ | caused the interrupt.
+ |
+ +-------------------------------------------------------------------------*/
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
+ mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ int mode;
+
+ /*
+ * since we are relocated, we can finally enable i-cache
+ * and set up the flash CS correctly
+ */
+ icache_enable();
+ setup_cs_reloc();
+ /* get and display boot mode */
+ mode = get_boot_mode();
+ if (mode & BOOT_PCI)
+ printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ?
+ "MPS" : "Flash");
+ else
+ printf("%s Boot\n", (mode & BOOT_MPS) ?
+ "MPS" : "Flash");
+
+ return 0;
+}
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+ char s[50];
+ unsigned char bc;
+ int i;
+ backup_t *b = (backup_t *) s;
+
+ puts ("Board: ");
+
+ i = getenv_f("serial#", (char *)s, 32);
+ if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) {
+ get_backup_values (b);
+ if (strncmp (b->signature, "MPL\0", 4) != 0) {
+ puts ("### No HW ID - assuming PIP405");
+ } else {
+ b->serial_name[6] = 0;
+ printf ("%s SN: %s", b->serial_name,
+ &b->serial_name[7]);
+ }
+ } else {
+ s[6] = 0;
+ printf ("%s SN: %s", s, &s[7]);
+ }
+ bc = in8 (CONFIG_PORT_ADDR);
+ printf (" Boot Config: 0x%x\n", bc);
+ return (0);
+}
+
+
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+/*
+ initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ the necessary info for SDRAM controller configuration
+*/
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+static int test_dram (unsigned long ramsize);
+
+phys_size_t initdram (int board_type)
+{
+ unsigned long bank_reg[4], tmp, bank_size;
+ int i, ds;
+ unsigned long TotalSize;
+
+ ds = 0;
+ /* since the DRAM controller is allready set up,
+ * calculate the size with the bank registers
+ */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+ bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+ bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+ bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
+ TotalSize = 0;
+ for (i = 0; i < 4; i++) {
+ if ((bank_reg[i] & 0x1) == 0x1) {
+ tmp = (bank_reg[i] >> 17) & 0x7;
+ bank_size = 4 << tmp;
+ TotalSize += bank_size;
+ } else
+ ds = 1;
+ }
+ if (ds == 1)
+ printf ("single-sided DIMM ");
+ else
+ printf ("double-sided DIMM ");
+ test_dram (TotalSize * 1024 * 1024);
+ /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
+ (void) get_clocks();
+ if (gd->cpu_clk > 220000000)
+ TotalSize /= 2;
+ return (TotalSize * 1024 * 1024);
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+static int test_dram (unsigned long ramsize)
+{
+ /* not yet implemented */
+ return (1);
+}
+
+int misc_init_r (void)
+{
+ /* adjust flash start and size as well as the offset */
+ gd->bd->bi_flashstart=0-flash_info[0].size;
+ gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
+ gd->bd->bi_flashoffset=0;
+
+ /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
+ if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
+ mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
+
+ return (0);
+}
+
+/***************************************************************************
+ * some helping routines
+ */
+
+int overwrite_console (void)
+{
+ /* return true if console should be overwritten */
+ return in8(CONFIG_PORT_ADDR) & 0x1;
+}
+
+
+extern int isa_init (void);
+
+
+void print_pip405_rev (void)
+{
+ unsigned char part, vers, cfg;
+
+ part = in8 (PLD_PART_REG);
+ vers = in8 (PLD_VERS_REG);
+ cfg = in8 (PLD_BOARD_CFG_REG);
+ printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
+ 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
+ vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
+}
+
+extern void check_env(void);
+
+
+int last_stage_init (void)
+{
+ print_pip405_rev ();
+ isa_init ();
+ stdio_print_current_devices ();
+ check_env();
+ return 0;
+}
+
+/************************************************************************
+* Print PIP405 Info
+************************************************************************/
+void print_pip405_info (void)
+{
+ unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
+ compwr, nicvga, scsirst;
+
+ part = in8 (PLD_PART_REG);
+ vers = in8 (PLD_VERS_REG);
+ cfg = in8 (PLD_BOARD_CFG_REG);
+ ledu = in8 (PLD_LED_USER_REG);
+ sysman = in8 (PLD_SYS_MAN_REG);
+ flashcom = in8 (PLD_FLASH_COM_REG);
+ can = in8 (PLD_CAN_REG);
+ serpwr = in8 (PLD_SER_PWR_REG);
+ compwr = in8 (PLD_COM_PWR_REG);
+ nicvga = in8 (PLD_NIC_VGA_REG);
+ scsirst = in8 (PLD_SCSI_RST_REG);
+ printf ("PLD Part %d version %d\n",
+ part & 0xf, vers & 0xf);
+ printf ("PLD Part %d version %d\n",
+ (part >> 4) & 0xf, (vers >> 4) & 0xf);
+ printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
+ printf ("Population Options %d %d %d %d\n",
+ (cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
+ (cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
+ printf ("User LED0 %s User LED1 %s\n",
+ ((ledu & 0x1) == 0x1) ? "on" : "off",
+ ((ledu & 0x2) == 0x2) ? "on" : "off");
+ printf ("Additionally Options %d %d\n",
+ (ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
+ printf ("User Config Switch %d %d %d %d\n",
+ (ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
+ (ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
+ switch (sysman & 0x3) {
+ case 0:
+ printf ("PCI Clocks are running\n");
+ break;
+ case 1:
+ printf ("PCI Clocks are stopped in POS State\n");
+ break;
+ case 2:
+ printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
+ break;
+ case 3:
+ printf ("PCI Clocks are stopped\n");
+ break;
+ }
+ switch ((sysman >> 2) & 0x3) {
+ case 0:
+ printf ("Main Clocks are running\n");
+ break;
+ case 1:
+ printf ("Main Clocks are stopped in POS State\n");
+ break;
+ case 2:
+ case 3:
+ printf ("PCI Clocks are stopped\n");
+ break;
+ }
+ printf ("INIT asserts %sINT2# (SMI)\n",
+ ((sysman & 0x10) == 0x10) ? "" : "not ");
+ printf ("INIT asserts %sINT1# (NMI)\n",
+ ((sysman & 0x20) == 0x20) ? "" : "not ");
+ printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
+ printf ("SER1 is routed to %s\n",
+ ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
+ printf ("COM2 is routed to %s\n",
+ ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
+ printf ("RS485 is configured as %s duplex\n",
+ ((flashcom & 0x4) == 0x4) ? "full" : "half");
+ printf ("RS485 is connected to %s\n",
+ ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
+ printf ("SER1 uses handshakes %s\n",
+ ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
+ printf ("Bootflash is %swriteprotected\n",
+ ((flashcom & 0x20) == 0x20) ? "not " : "");
+ printf ("Bootflash VPP is %s\n",
+ ((flashcom & 0x40) == 0x40) ? "on" : "off");
+ printf ("Bootsector is %swriteprotected\n",
+ ((flashcom & 0x80) == 0x80) ? "not " : "");
+ switch ((can) & 0x3) {
+ case 0:
+ printf ("CAN Controller is on address 0x1000..0x10FF\n");
+ break;
+ case 1:
+ printf ("CAN Controller is on address 0x8000..0x80FF\n");
+ break;
+ case 2:
+ printf ("CAN Controller is on address 0xE000..0xE0FF\n");
+ break;
+ case 3:
+ printf ("CAN Controller is disabled\n");
+ break;
+ }
+ switch ((can >> 2) & 0x3) {
+ case 0:
+ printf ("CAN Controller Reset is ISA Reset\n");
+ break;
+ case 1:
+ printf ("CAN Controller Reset is ISA Reset and POS State\n");
+ break;
+ case 2:
+ case 3:
+ printf ("CAN Controller is in reset\n");
+ break;
+ }
+ if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
+ printf ("CAN Interrupt is disabled\n");
+ else
+ printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
+ switch (serpwr & 0x3) {
+ case 0:
+ printf ("SER0 Drivers are enabled\n");
+ break;
+ case 1:
+ printf ("SER0 Drivers are disabled in the POS state\n");
+ break;
+ case 2:
+ case 3:
+ printf ("SER0 Drivers are disabled\n");
+ break;
+ }
+ switch ((serpwr >> 2) & 0x3) {
+ case 0:
+ printf ("SER1 Drivers are enabled\n");
+ break;
+ case 1:
+ printf ("SER1 Drivers are disabled in the POS state\n");
+ break;
+ case 2:
+ case 3:
+ printf ("SER1 Drivers are disabled\n");
+ break;
+ }
+ switch (compwr & 0x3) {
+ case 0:
+ printf ("COM1 Drivers are enabled\n");
+ break;
+ case 1:
+ printf ("COM1 Drivers are disabled in the POS state\n");
+ break;
+ case 2:
+ case 3:
+ printf ("COM1 Drivers are disabled\n");
+ break;
+ }
+ switch ((compwr >> 2) & 0x3) {
+ case 0:
+ printf ("COM2 Drivers are enabled\n");
+ break;
+ case 1:
+ printf ("COM2 Drivers are disabled in the POS state\n");
+ break;
+ case 2:
+ case 3:
+ printf ("COM2 Drivers are disabled\n");
+ break;
+ }
+ switch ((nicvga) & 0x3) {
+ case 0:
+ printf ("PHY is running\n");
+ break;
+ case 1:
+ printf ("PHY is in Power save mode in POS state\n");
+ break;
+ case 2:
+ case 3:
+ printf ("PHY is in Power save mode\n");
+ break;
+ }
+ switch ((nicvga >> 2) & 0x3) {
+ case 0:
+ printf ("VGA is running\n");
+ break;
+ case 1:
+ printf ("VGA is in Power save mode in POS state\n");
+ break;
+ case 2:
+ case 3:
+ printf ("VGA is in Power save mode\n");
+ break;
+ }
+ printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
+ printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
+ printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
+ (nicvga >> 7) & 0x1);
+ switch ((scsirst) & 0x3) {
+ case 0:
+ printf ("SCSI Controller is running\n");
+ break;
+ case 1:
+ printf ("SCSI Controller is in Power save mode in POS state\n");
+ break;
+ case 2:
+ case 3:
+ printf ("SCSI Controller is in Power save mode\n");
+ break;
+ }
+ printf ("SCSI termination is %s\n",
+ ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
+ printf ("SCSI Controller is %sreseted\n",
+ ((scsirst & 0x10) == 0x10) ? "" : "not ");
+ printf ("IDE disks are %sreseted\n",
+ ((scsirst & 0x20) == 0x20) ? "" : "not ");
+ printf ("ISA Bus is %sreseted\n",
+ ((scsirst & 0x40) == 0x40) ? "" : "not ");
+ printf ("Super IO is %sreseted\n",
+ ((scsirst & 0x80) == 0x80) ? "" : "not ");
+}
+
+void user_led0 (unsigned char on)
+{
+ if (on == true)
+ out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
+ else
+ out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
+}
+
+void user_led1 (unsigned char on)
+{
+ if (on == true)
+ out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
+ else
+ out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
+}
+
+void ide_set_reset (int idereset)
+{
+ /* if reset = 1 IDE reset will be asserted */
+ unsigned char resreg;
+
+ resreg = in8 (PLD_SCSI_RST_REG);
+ if (idereset == 1)
+ resreg |= 0x20;
+ else {
+ udelay(10000);
+ resreg &= 0xdf;
+ }
+ out8 (PLD_SCSI_RST_REG, resreg);
+}
diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h
new file mode 100644
index 0000000..1f07d79
--- /dev/null
+++ b/board/mpl/pip405/pip405.h
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+ /****************************************************************************
+ * Global routines used for PIP405
+ *****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
+
+void print_pip405_info(void);
+
+void user_led0(unsigned char on);
+void user_led1(unsigned char on);
+
+
+#define PLD_BASE_ADDRESS CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x800
+#define PLD_PART_REG PLD_BASE_ADDRESS + 0
+#define PLD_VERS_REG PLD_BASE_ADDRESS + 1
+#define PLD_BOARD_CFG_REG PLD_BASE_ADDRESS + 2
+#define PLD_LED_USER_REG PLD_BASE_ADDRESS + 3
+#define PLD_SYS_MAN_REG PLD_BASE_ADDRESS + 4
+#define PLD_FLASH_COM_REG PLD_BASE_ADDRESS + 5
+#define PLD_CAN_REG PLD_BASE_ADDRESS + 6
+#define PLD_SER_PWR_REG PLD_BASE_ADDRESS + 7
+#define PLD_COM_PWR_REG PLD_BASE_ADDRESS + 8
+#define PLD_NIC_VGA_REG PLD_BASE_ADDRESS + 9
+#define PLD_SCSI_RST_REG PLD_BASE_ADDRESS + 0xA
+
+#define PIIX4_VENDOR_ID 0x8086
+#define PIIX4_IDE_DEV_ID 0x7111
+
+#endif
+
+/* timings */
+
+/* CS Config register (CS7) */
+#define CONFIG_PORT_BME 0 /* Burst disable */
+#define CONFIG_PORT_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
+#define CONFIG_PORT_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define CONFIG_PORT_OEN 1 /* Cycles from CS low to OE low */
+#define CONFIG_PORT_WBN 1 /* Cycles from CS low to WE low */
+#define CONFIG_PORT_WBF 1 /* Cycles from WE high to CS high */
+#define CONFIG_PORT_TH 2 /* Number of hold cycles after transfer */
+#define CONFIG_PORT_RE 0 /* Ready disabled */
+#define CONFIG_PORT_SOR 1 /* Sample on Ready disabled */
+#define CONFIG_PORT_BEM 0 /* Byte Write only active on Write cycles */
+#define CONFIG_PORT_PEN 0 /* Parity disable */
+#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
+ (CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define CONFIG_PORT_BS 0 /* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define CONFIG_PORT_BU 3 /* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define CONFIG_PORT_BW 0 /* 16Bit */
+#define CONFIG_PORT_CR ((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13))
+
+/* Flash CS0 or CS 1 */
+/* 0x7F8FFE80 slowest timing at all... */
+#define FLASH_BME_B 1 /* Burst enable */
+#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */
+#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
+#define FLASH_BME 0 /* Burst disable */
+#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
+#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define FLASH_OEN 1 /* Cycles from CS low to OE low */
+#define FLASH_WBN 1 /* Cycles from CS low to WE low */
+#define FLASH_WBF 1 /* Cycles from WE high to CS high */
+#define FLASH_TH 2 /* Number of hold cycles after transfer */
+#define FLASH_RE 0 /* Ready disabled */
+#define FLASH_SOR 1 /* Sample on Ready disabled */
+#define FLASH_BEM 0 /* Byte Write only active on Write cycles */
+#define FLASH_PEN 0 /* Parity disable */
+/* Access Parameter Register for non Boot */
+#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+ (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+/* Access Parameter Register for Boot */
+#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+ (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define FLASH_BU 3 /* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define FLASH_BW 1 /* 16Bit */
+/* CR register for Boot */
+#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+/* CR register for non Boot */
+#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+
+/* MPS CS1 or CS0 */
+/* Boot CS: */
+#define MPS_BME_B 1 /* Burst enable */
+#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */
+#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
+#define MPS_BME 0 /* Burst disable */
+#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
+#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define MPS_OEN 1 /* Cycles from CS low to OE low */
+#define MPS_WBN 1 /* Cycles from CS low to WE low */
+#define MPS_WBF 1 /* Cycles from WE high to CS high */
+#define MPS_TH 2 /* Number of hold cycles after transfer */
+#define MPS_RE 0 /* Ready disabled */
+#define MPS_SOR 1 /* Sample on Ready disabled */
+#define MPS_BEM 0 /* Byte Write only active on Write cycles */
+#define MPS_PEN 0 /* Parity disable */
+/* Access Parameter Register for non Boot */
+#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+ (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+/* Access Parameter Register for Boot */
+#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+ (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define MPS_BS 2 /* 4 MByte */
+#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define MPS_BU 3 /* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define MPS_BW 0 /* 8Bit */
+/* CR register for Boot */
+#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
+/* CR register for non Boot */
+#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug
new file mode 100644
index 0000000..890f592
--- /dev/null
+++ b/board/mpl/pip405/u-boot.lds.debug
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/powerpc/lib/extable.o (.text)
+
+ common/env_embedded.o(.text)
+
+ *(.text)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/mpl/vcma9/Kconfig b/board/mpl/vcma9/Kconfig
new file mode 100644
index 0000000..a156452
--- /dev/null
+++ b/board/mpl/vcma9/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_VCMA9
+
+config SYS_BOARD
+ default "vcma9"
+
+config SYS_VENDOR
+ default "mpl"
+
+config SYS_SOC
+ default "s3c24x0"
+
+config SYS_CONFIG_NAME
+ default "VCMA9"
+
+endif
diff --git a/board/mpl/vcma9/MAINTAINERS b/board/mpl/vcma9/MAINTAINERS
new file mode 100644
index 0000000..3817436
--- /dev/null
+++ b/board/mpl/vcma9/MAINTAINERS
@@ -0,0 +1,6 @@
+VCMA9 BOARD
+M: David Müller <d.mueller@elsoft.ch>
+S: Maintained
+F: board/mpl/vcma9/
+F: include/configs/VCMA9.h
+F: configs/VCMA9_defconfig
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile
new file mode 100644
index 0000000..175a19f
--- /dev/null
+++ b/board/mpl/vcma9/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ../common/common_util.o
+obj-y += vcma9.o cmd_vcma9.o
+
+obj-y += lowlevel_init.o
diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c
new file mode 100644
index 0000000..c2d62e4
--- /dev/null
+++ b/board/mpl/vcma9/cmd_vcma9.c
@@ -0,0 +1,119 @@
+/*
+ * (C) Copyright 2002
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * adapted for VCMA9
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include "vcma9.h"
+#include "../common/common_util.h"
+
+#if defined(CONFIG_CS8900)
+#include <../drivers/net/cs8900.h>
+
+static uchar cs8900_chksum(ushort data)
+{
+ return((data >> 8) & 0x00FF) + (data & 0x00FF);
+}
+
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct eth_device *dev;
+ char cs8900_name[10];
+ if (strcmp(argv[1], "info") == 0)
+ {
+ vcma9_print_info();
+ return 0;
+ }
+#if defined(CONFIG_CS8900)
+ if (strcmp(argv[1], "cs8900") == 0) {
+ sprintf(cs8900_name, "%s-0", CS8900_DRIVERNAME);
+ dev = eth_get_dev_by_name(cs8900_name);
+ if (!dev) {
+ printf("Couldn't find CS8900 driver");
+ return 0;
+ }
+ if (strcmp(argv[2], "read") == 0) {
+ uchar addr; ushort data;
+
+ addr = simple_strtoul(argv[3], NULL, 16);
+ cs8900_e2prom_read(dev, addr, &data);
+ printf("0x%2.2X: 0x%4.4X\n", addr, data);
+ } else if (strcmp(argv[2], "write") == 0) {
+ uchar addr; ushort data;
+
+ addr = simple_strtoul(argv[3], NULL, 16);
+ data = simple_strtoul(argv[4], NULL, 16);
+ cs8900_e2prom_write(dev, addr, data);
+ } else if (strcmp(argv[2], "setaddr") == 0) {
+ uchar addr, i, csum; ushort data;
+ uchar ethaddr[6];
+
+ /* check for valid ethaddr */
+ if (eth_getenv_enetaddr("ethaddr", ethaddr)) {
+ addr = 1;
+ data = 0x2158;
+ cs8900_e2prom_write(dev, addr, data);
+ csum = cs8900_chksum(data);
+ addr++;
+ for (i = 0; i < 6; i+=2) {
+ data = ethaddr[i+1] << 8 |
+ ethaddr[i];
+ cs8900_e2prom_write(dev, addr, data);
+ csum += cs8900_chksum(data);
+ addr++;
+ }
+ /* calculate header link byte */
+ data = 0xA100 | (addr * 2);
+ cs8900_e2prom_write(dev, 0, data);
+ csum += cs8900_chksum(data);
+ /* write checksum word */
+ cs8900_e2prom_write(dev, addr, (0 - csum) << 8);
+ } else {
+ puts("\nplease defined 'ethaddr'\n");
+ }
+ } else if (strcmp(argv[2], "dump") == 0) {
+ uchar addr = 0, endaddr, csum; ushort data;
+
+ puts("Dump of CS8900 config device: ");
+ cs8900_e2prom_read(dev, addr, &data);
+ if ((data & 0xE000) == 0xA000) {
+ endaddr = (data & 0x00FF) / 2;
+ csum = cs8900_chksum(data);
+ for (addr = 1; addr <= endaddr; addr++) {
+ cs8900_e2prom_read(dev, addr, &data);
+ printf("\n0x%2.2X: 0x%4.4X", addr, data);
+ csum += cs8900_chksum(data);
+ }
+ printf("\nChecksum: %s", (csum == 0) ? "ok" : "wrong");
+ } else {
+ puts("no valid config found");
+ }
+ puts("\n");
+ }
+
+ return 0;
+ }
+#endif
+
+ return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+
+U_BOOT_CMD(
+ vcma9, 6, 1, do_vcma9,
+ "VCMA9 specific commands",
+ "flash mem [SrcAddr] - updates U-Boot with image in memory\n"
+ "vcma9 info - displays board information"
+);
diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S
new file mode 100644
index 0000000..ee9b7a9
--- /dev/null
+++ b/board/mpl/vcma9/lowlevel_init.S
@@ -0,0 +1,502 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for MPL VCMA9 by
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ * (C) Copyright 2002, 2003, 2004, 2005
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* register definitions */
+
+#define PLD_BASE 0x28000000
+#define MISC_REG 0x103
+#define SDRAM_REG 0x106
+#define BWSCON 0x48000000
+#define CLKBASE 0x4C000000
+#define LOCKTIME 0x0
+#define MPLLCON 0x4
+#define UPLLCON 0x8
+#define GPIOBASE 0x56000000
+#define GSTATUS1 0xB0
+#define FASTCPU 0x02
+
+/* some parameters for the board */
+/* BWSCON */
+#define DW8 (0x0)
+#define DW16 (0x1)
+#define DW32 (0x2)
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+/* BANKSIZE */
+#define BURST_EN (0x1<<7)
+
+/* BANK0CON 200 */
+#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
+#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
+#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
+#define B0_Tcoh_200 0x0 /* 0clk */
+#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */
+#define B0_Tacp_200 0x0 /* page mode is not used */
+#define B0_PMC_200 0x0 /* page mode disabled */
+
+/* BANK0CON 250 */
+#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
+#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
+#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
+#define B0_Tcoh_250 0x0 /* 0clk */
+#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
+#define B0_Tacp_250 0x0 /* page mode is not used */
+#define B0_PMC_250 0x0 /* page mode disabled */
+
+/* BANK0CON 266 */
+#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
+#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
+#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
+#define B0_Tcoh_266 0x0 /* 0clk */
+#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
+#define B0_Tacp_266 0x0 /* page mode is not used */
+#define B0_PMC_266 0x0 /* page mode disabled */
+
+/* BANK1CON 200 */
+#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
+#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
+#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
+#define B1_Tcoh_200 0x0 /* 0clk */
+#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */
+#define B1_Tacp_200 0x0 /* page mode is not used */
+#define B1_PMC_200 0x0 /* page mode disabled */
+
+/* BANK1CON 250 */
+#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
+#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
+#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
+#define B1_Tcoh_250 0x0 /* 0clk */
+#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
+#define B1_Tacp_250 0x0 /* page mode is not used */
+#define B1_PMC_250 0x0 /* page mode disabled */
+
+/* BANK1CON 266 */
+#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
+#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
+#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
+#define B1_Tcoh_266 0x0 /* 0clk */
+#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
+#define B1_Tacp_266 0x0 /* page mode is not used */
+#define B1_PMC_266 0x0 /* page mode disabled */
+
+/* BANK2CON 200 + 250 + 266 */
+#define B2_Tacs 0x3 /* 4clk */
+#define B2_Tcos 0x3 /* 4clk */
+#define B2_Tacc 0x7 /* 14clk */
+#define B2_Tcoh 0x3 /* 4clk */
+#define B2_Tcah 0x3 /* 4clk */
+#define B2_Tacp 0x0 /* page mode is not used */
+#define B2_PMC 0x0 /* page mode disabled */
+
+/* BANK3CON 200 + 250 + 266 */
+#define B3_Tacs 0x3 /* 4clk */
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7 /* 14clk */
+#define B3_Tcoh 0x3 /* 4clk */
+#define B3_Tcah 0x3 /* 4clk */
+#define B3_Tacp 0x0 /* page mode is not used */
+#define B3_PMC 0x0 /* page mode disabled */
+
+/* BANK4CON 200 */
+#define B4_Tacs_200 0x1 /* 1clk */
+#define B4_Tcos_200 0x3 /* 4clk */
+#define B4_Tacc_200 0x7 /* 14clk */
+#define B4_Tcoh_200 0x3 /* 4clk */
+#define B4_Tcah_200 0x2 /* 2clk */
+#define B4_Tacp_200 0x0 /* page mode is not used */
+#define B4_PMC_200 0x0 /* page mode disabled */
+
+/* BANK4CON 250 */
+#define B4_Tacs_250 0x1 /* 1clk */
+#define B4_Tcos_250 0x3 /* 4clk */
+#define B4_Tacc_250 0x7 /* 14clk */
+#define B4_Tcoh_250 0x3 /* 4clk */
+#define B4_Tcah_250 0x2 /* 2clk */
+#define B4_Tacp_250 0x0 /* page mode is not used */
+#define B4_PMC_250 0x0 /* page mode disabled */
+
+/* BANK4CON 266 */
+#define B4_Tacs_266 0x1 /* 1clk */
+#define B4_Tcos_266 0x3 /* 4clk */
+#define B4_Tacc_266 0x7 /* 14clk */
+#define B4_Tcoh_266 0x3 /* 4clk */
+#define B4_Tcah_266 0x2 /* 2clk */
+#define B4_Tacp_266 0x0 /* page mode is not used */
+#define B4_PMC_266 0x0 /* page mode disabled */
+
+/* BANK5CON 200 */
+#define B5_Tacs_200 0x0 /* 0clk */
+#define B5_Tcos_200 0x3 /* 4clk */
+#define B5_Tacc_200 0x4 /* 6clk */
+#define B5_Tcoh_200 0x3 /* 4clk */
+#define B5_Tcah_200 0x1 /* 1clk */
+#define B5_Tacp_200 0x0 /* page mode is not used */
+#define B5_PMC_200 0x0 /* page mode disabled */
+
+/* BANK5CON 250 */
+#define B5_Tacs_250 0x0 /* 0clk */
+#define B5_Tcos_250 0x3 /* 4clk */
+#define B5_Tacc_250 0x5 /* 8clk */
+#define B5_Tcoh_250 0x3 /* 4clk */
+#define B5_Tcah_250 0x1 /* 1clk */
+#define B5_Tacp_250 0x0 /* page mode is not used */
+#define B5_PMC_250 0x0 /* page mode disabled */
+
+/* BANK5CON 266 */
+#define B5_Tacs_266 0x0 /* 0clk */
+#define B5_Tcos_266 0x3 /* 4clk */
+#define B5_Tacc_266 0x5 /* 8clk */
+#define B5_Tcoh_266 0x3 /* 4clk */
+#define B5_Tcah_266 0x1 /* 1clk */
+#define B5_Tacp_266 0x0 /* page mode is not used */
+#define B5_PMC_266 0x0 /* page mode disabled */
+
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd_200 0x0 /* 2clk */
+#define B6_Trcd_250 0x1 /* 3clk */
+#define B6_Trcd_266 0x1 /* 3clk */
+#define B6_SCAN 0x2 /* 10bit */
+
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd_200 0x0 /* 2clk */
+#define B7_Trcd_250 0x1 /* 3clk */
+#define B7_Trcd_266 0x1 /* 3clk */
+#define B7_SCAN 0x2 /* 10bit */
+
+/* REFRESH parameter */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp_200 0x0 /* 2clk */
+#define Trp_250 0x1 /* 3clk */
+#define Trp_266 0x1 /* 3clk */
+#define Tsrc_200 0x1 /* 5clk */
+#define Tsrc_250 0x2 /* 6clk */
+#define Tsrc_266 0x3 /* 7clk */
+
+/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */
+#define REFCNT_200 489
+/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */
+#define REFCNT_250 99
+/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */
+#define REFCNT_266 0
+/**************************************/
+
+.globl lowlevel_init
+lowlevel_init:
+ /* use r0 to relocate DATA read/write to flash rather than memory ! */
+ ldr r0, =CONFIG_SYS_TEXT_BASE
+ ldr r13, =BWSCON
+
+ /* enable minimal access to PLD */
+ ldr r1, [r13] /* load default BWSCON */
+ orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */
+ str r1, [r13] /* set BWSCON */
+ ldr r1, =0x7FF0 /* select slowest timing */
+ str r1, [r13, #0x18] /* set BANKCON5 */
+
+ ldr r1, =PLD_BASE
+ ldr r2, =SETUPDATA
+ ldrb r1, [r1, #MISC_REG]
+ sub r2, r2, r0
+ tst r1, #FASTCPU /* FASTCPU available ? */
+ addeq r2, r2, #SETUPENTRY_SIZE
+
+ /* memory control configuration */
+ /* r2 = pointer into timing table */
+ /* r13 = pointer to MEM controller regs (starting with BWSCON) */
+ add r3, r2, #CSDATA_OFFSET
+ add r4, r3, #CSDATAENTRY_SIZE
+0:
+ ldr r1, [r3], #4
+ str r1, [r13], #4
+ cmp r3, r4
+ bne 0b
+
+ /* PLD access is now possible */
+ /* r3 = SDRAMDATA */
+ /* r13 = pointer to MEM controller regs */
+ ldr r1, =PLD_BASE
+ mov r4, #SDRAMENTRY_SIZE
+ ldrb r1, [r1, #SDRAM_REG]
+ /* calculate start and end point */
+ mla r3, r4, r1, r3
+ add r4, r3, r4
+0:
+ ldr r1, [r3], #4
+ str r1, [r13], #4
+ cmp r3, r4
+ bne 0b
+
+ /* setup MPLL registers */
+ ldr r1, =CLKBASE
+ ldr r4, =0xFFFFFF
+ add r3, r2, #4 /* r3 points to PLL values */
+ str r4, [r1, #LOCKTIME]
+ ldmia r3, {r4,r5}
+ str r5, [r1, #UPLLCON] /* writing PLL register */
+ /* !! order seems to be important !! */
+ /* a little delay */
+ ldr r3, =0x4000
+0:
+ subs r3, r3, #1
+ bne 0b
+
+ str r4, [r1, #MPLLCON] /* writing PLL register */
+ /* !! order seems to be important !! */
+ /* a little delay */
+ ldr r3, =0x4000
+0:
+ subs r3, r3, #1
+ bne 0b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \
+ ((bws1) << 4) + \
+ ((bws2) << 8) + \
+ ((bws3) << 12) + \
+ ((bws4) << 16) + \
+ ((bws5) << 20) + \
+ ((bws6) << 24) + \
+ ((bws7) << 28)
+
+#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \
+ ((tacs) << 13) + \
+ ((tcos) << 11) + \
+ ((tacc) << 8) + \
+ ((tcoh) << 6) + \
+ ((tcah) << 4) + \
+ ((tacp) << 2) + \
+ (pmc)
+
+#define MK_BANKCON_SDRAM(trcd, scan) \
+ ((0x03) << 15) + \
+ ((trcd) << 2) + \
+ (scan)
+
+#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \
+ ((enable) << 23) + \
+ ((trefmd) << 22) + \
+ ((trp) << 20) + \
+ ((tsrc) << 18) + \
+ (cnt)
+
+SETUPDATA:
+ .word 0x32410002
+ /* PLL values (MDIV, PDIV, SDIV) for 250 MHz */
+ .word (0x75 << 12) + (0x01 << 4) + (0x01 << 0)
+ /* PLL values for USB clock */
+ .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
+
+ /* timing for 250 MHz*/
+0:
+ .equiv CSDATA_OFFSET, (. - SETUPDATA)
+ .word MK_BWSCON(DW16, \
+ DW32, \
+ DW32, \
+ DW16 + WAIT + UBLB, \
+ DW8 + UBLB, \
+ DW32, \
+ DW32)
+
+ .word MK_BANKCON(B0_Tacs_250, \
+ B0_Tcos_250, \
+ B0_Tacc_250, \
+ B0_Tcoh_250, \
+ B0_Tcah_250, \
+ B0_Tacp_250, \
+ B0_PMC_250)
+
+ .word MK_BANKCON(B1_Tacs_250, \
+ B1_Tcos_250, \
+ B1_Tacc_250, \
+ B1_Tcoh_250, \
+ B1_Tcah_250, \
+ B1_Tacp_250, \
+ B1_PMC_250)
+
+ .word MK_BANKCON(B2_Tacs, \
+ B2_Tcos, \
+ B2_Tacc, \
+ B2_Tcoh, \
+ B2_Tcah, \
+ B2_Tacp, \
+ B2_PMC)
+
+ .word MK_BANKCON(B3_Tacs, \
+ B3_Tcos, \
+ B3_Tacc, \
+ B3_Tcoh, \
+ B3_Tcah, \
+ B3_Tacp, \
+ B3_PMC)
+
+ .word MK_BANKCON(B4_Tacs_250, \
+ B4_Tcos_250, \
+ B4_Tacc_250, \
+ B4_Tcoh_250, \
+ B4_Tcah_250, \
+ B4_Tacp_250, \
+ B4_PMC_250)
+
+ .word MK_BANKCON(B5_Tacs_250, \
+ B5_Tcos_250, \
+ B5_Tacc_250, \
+ B5_Tcoh_250, \
+ B5_Tcah_250, \
+ B5_Tacp_250, \
+ B5_PMC_250)
+
+ .equiv CSDATAENTRY_SIZE, (. - 0b)
+ /* 4Mx8x4 */
+0:
+ .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
+ .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
+ .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
+ .word 0x32 + BURST_EN
+ .word 0x30
+ .word 0x30
+ .equiv SDRAMENTRY_SIZE, (. - 0b)
+
+ /* 8Mx8x4 */
+ .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
+ .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
+ .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
+ .word 0x32 + BURST_EN
+ .word 0x30
+ .word 0x30
+
+ /* 2Mx8x4 */
+ .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
+ .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
+ .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
+ .word 0x32 + BURST_EN
+ .word 0x30
+ .word 0x30
+
+ /* 4Mx8x2 */
+ .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
+ .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
+ .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
+ .word 0x32 + BURST_EN
+ .word 0x30
+ .word 0x30
+
+ .equiv SETUPENTRY_SIZE, (. - SETUPDATA)
+
+ .word 0x32410000
+ /* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */
+ .word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0)
+ /* PLL values for USB clock */
+ .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
+
+ /* timing for 200 MHz and default*/
+ .word MK_BWSCON(DW16, \
+ DW32, \
+ DW32, \
+ DW16 + WAIT + UBLB, \
+ DW8 + UBLB, \
+ DW32, \
+ DW32)
+
+ .word MK_BANKCON(B0_Tacs_200, \
+ B0_Tcos_200, \
+ B0_Tacc_200, \
+ B0_Tcoh_200, \
+ B0_Tcah_200, \
+ B0_Tacp_200, \
+ B0_PMC_200)
+
+ .word MK_BANKCON(B1_Tacs_200, \
+ B1_Tcos_200, \
+ B1_Tacc_200, \
+ B1_Tcoh_200, \
+ B1_Tcah_200, \
+ B1_Tacp_200, \
+ B1_PMC_200)
+
+ .word MK_BANKCON(B2_Tacs, \
+ B2_Tcos, \
+ B2_Tacc, \
+ B2_Tcoh, \
+ B2_Tcah, \
+ B2_Tacp, \
+ B2_PMC)
+
+ .word MK_BANKCON(B3_Tacs, \
+ B3_Tcos, \
+ B3_Tacc, \
+ B3_Tcoh, \
+ B3_Tcah, \
+ B3_Tacp, \
+ B3_PMC)
+
+ .word MK_BANKCON(B4_Tacs_200, \
+ B4_Tcos_200, \
+ B4_Tacc_200, \
+ B4_Tcoh_200, \
+ B4_Tcah_200, \
+ B4_Tacp_200, \
+ B4_PMC_200)
+
+ .word MK_BANKCON(B5_Tacs_200, \
+ B5_Tcos_200, \
+ B5_Tacc_200, \
+ B5_Tcoh_200, \
+ B5_Tcah_200, \
+ B5_Tacp_200, \
+ B5_PMC_200)
+
+ /* 4Mx8x4 */
+ .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
+ .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
+ .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
+ .word 0x32 + BURST_EN
+ .word 0x30
+ .word 0x30
+
+ /* 8Mx8x4 */
+ .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
+ .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
+ .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
+ .word 0x32 + BURST_EN
+ .word 0x30
+ .word 0x30
+
+ /* 2Mx8x4 */
+ .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
+ .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
+ .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
+ .word 0x32 + BURST_EN
+ .word 0x30
+ .word 0x30
+
+ /* 4Mx8x2 */
+ .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
+ .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
+ .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
+ .word 0x32 + BURST_EN
+ .word 0x30
+ .word 0x30
+
+ .equiv SETUPDATA_SIZE, (. - SETUPDATA)
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
new file mode 100644
index 0000000..43a3d47
--- /dev/null
+++ b/board/mpl/vcma9/vcma9.c
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002, 2010
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+#include "vcma9.h"
+#include "../common/common_util.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_early_init_f(void)
+{
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+ /* set up the I/O ports */
+ writel(0x007FFFFF, &gpio->gpacon);
+ writel(0x002AAAAA, &gpio->gpbcon);
+ writel(0x000002BF, &gpio->gpbup);
+ writel(0xAAAAAAAA, &gpio->gpccon);
+ writel(0x0000FFFF, &gpio->gpcup);
+ writel(0xAAAAAAAA, &gpio->gpdcon);
+ writel(0x0000FFFF, &gpio->gpdup);
+ writel(0xAAAAAAAA, &gpio->gpecon);
+ writel(0x000037F7, &gpio->gpeup);
+ writel(0x00000000, &gpio->gpfcon);
+ writel(0x00000000, &gpio->gpfup);
+ writel(0xFFEAFF5A, &gpio->gpgcon);
+ writel(0x0000F0DC, &gpio->gpgup);
+ writel(0x0028AAAA, &gpio->gphcon);
+ writel(0x00000656, &gpio->gphup);
+
+ /* setup correct IRQ modes for NIC (rising edge mode) */
+ writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2);
+
+ /* select USB port 2 to be host or device (setup as host for now) */
+ writel(readl(&gpio->misccr) | 0x08, &gpio->misccr);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x30000100;
+
+ icache_enable();
+ dcache_enable();
+
+ return 0;
+}
+
+/*
+ * Get some Board/PLD Info
+ */
+
+static u8 get_pld_reg(enum vcma9_pld_regs reg)
+{
+ return readb(VCMA9_PLD_BASE + reg);
+}
+
+static u8 get_pld_version(void)
+{
+ return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F;
+}
+
+static u8 get_pld_revision(void)
+{
+ return get_pld_reg(VCMA9_PLD_ID) & 0x0F;
+}
+
+static uchar get_board_pcb(void)
+{
+ return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A';
+}
+
+static u8 get_nr_chips(void)
+{
+ switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) {
+ case 0: return 4;
+ case 1: return 1;
+ case 2: return 2;
+ default: return 0;
+ }
+}
+
+static ulong get_chip_size(void)
+{
+ switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
+ case 0: return 16 * (1024*1024);
+ case 1: return 32 * (1024*1024);
+ case 2: return 8 * (1024*1024);
+ case 3: return 8 * (1024*1024);
+ default: return 0;
+ }
+}
+
+static const char *get_chip_geom(void)
+{
+ switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
+ case 0: return "4Mx8x4";
+ case 1: return "8Mx8x4";
+ case 2: return "2Mx8x4";
+ case 3: return "4Mx8x2";
+ default: return "unknown";
+ }
+}
+
+static void vcma9_show_info(char *board_name, char *serial)
+{
+ printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n",
+ board_name, serial,
+ get_board_pcb(), get_pld_version(), get_pld_revision());
+ printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom());
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_chip_size() * get_nr_chips();
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+ char s[50];
+ int i;
+ backup_t *b = (backup_t *) s;
+
+ i = getenv_f("serial#", s, 32);
+ if ((i < 0) || strncmp (s, "VCMA9", 5)) {
+ get_backup_values (b);
+ if (strncmp (b->signature, "MPL\0", 4) != 0) {
+ puts ("### No HW ID - assuming VCMA9");
+ } else {
+ b->serial_name[5] = 0;
+ vcma9_show_info(b->serial_name, &b->serial_name[6]);
+ }
+ } else {
+ s[5] = 0;
+ vcma9_show_info(s, &s[6]);
+ }
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ /*
+ * check if environment is healthy, otherwise restore values
+ * from shadow copy
+ */
+ check_env();
+ return 0;
+}
+
+void vcma9_print_info(void)
+{
+ char *s = getenv("serial#");
+
+ if (!s) {
+ puts ("### No HW ID - assuming VCMA9");
+ } else {
+ s[5] = 0;
+ vcma9_show_info(s, &s[6]);
+ }
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_CS8900
+ rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+ return rc;
+}
+#endif
+
+/*
+ * Hardcoded flash setup:
+ * Flash 0 is a non-CFI AMD AM29F400BB flash.
+ */
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return 1;
+}
diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h
new file mode 100644
index 0000000..c585c8e
--- /dev/null
+++ b/board/mpl/vcma9/vcma9.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2002, 2003
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+ /****************************************************************************
+ * Global routines used for VCMA9
+ *****************************************************************************/
+
+#include <asm/arch/s3c24x0_cpu.h>
+
+extern void vcma9_print_info(void);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag,
+ int argc, char *const argv[]);
+
+/* VCMA9 PLD registers */
+enum vcma9_pld_regs {
+ VCMA9_PLD_ID,
+ VCMA9_PLD_NIC,
+ VCMA9_PLD_CAN,
+ VCMA9_PLD_MISC,
+ VCMA9_PLD_GPCD,
+ VCMA9_PLD_BOARD,
+ VCMA9_PLD_SDRAM
+};
+
+#define VCMA9_PLD_BASE (0x2C000100)
diff --git a/board/mpr2/Kconfig b/board/mpr2/Kconfig
new file mode 100644
index 0000000..54176e8
--- /dev/null
+++ b/board/mpr2/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_MPR2
+
+config SYS_BOARD
+ default "mpr2"
+
+config SYS_CONFIG_NAME
+ default "mpr2"
+
+endif
diff --git a/board/mpr2/MAINTAINERS b/board/mpr2/MAINTAINERS
new file mode 100644
index 0000000..beedf8d
--- /dev/null
+++ b/board/mpr2/MAINTAINERS
@@ -0,0 +1,6 @@
+MPR2 BOARD
+M: Mark Jonas <mark.jonas@de.bosch.com>
+S: Maintained
+F: board/mpr2/
+F: include/configs/mpr2.h
+F: configs/mpr2_defconfig
diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile
new file mode 100644
index 0000000..b6cdeb4
--- /dev/null
+++ b/board/mpr2/Makefile
@@ -0,0 +1,19 @@
+#
+# Copyright (C) 2007
+# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# (C) Copyright 2008
+# Mark Jonas <mark.jonas@de.bosch.com>
+#
+# board/mpr2/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := mpr2.o
+obj-y += lowlevel_init.o
diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S
new file mode 100644
index 0000000..5246b63
--- /dev/null
+++ b/board/mpr2/lowlevel_init.S
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * (C) Copyright 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * board/mpr2/lowlevel_init.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <asm/macro.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+/*
+ * Set frequency multipliers and dividers in FRQCR.
+ */
+ write16 WTCSR_A, WTCSR_D
+
+ write16 WTCNT_A, WTCNT_D
+
+ write16 FRQCR_A, FRQCR_D
+
+/*
+ * Setup CS0 (Flash).
+ */
+ write32 CS0BCR_A, CS0BCR_D
+
+ write32 CS0WCR_A, CS0WCR_D
+
+/*
+ * Setup CS3 (SDRAM).
+ */
+ write32 CS3BCR_A, CS3BCR_D
+
+ write32 CS3WCR_A, CS3WCR_D
+
+ write32 SDCR_A, SDCR_D1
+
+ write32 RTCSR_A, RTCSR_D
+
+ write32 RTCNT_A, RTCNT_D
+
+ write32 RTCOR_A, RTCOR_D
+
+ write32 SDCR_A, SDCR_D2
+
+ mov.l SDMR3_A, r1
+ mov.l SDMR3_D, r0
+ add r0, r1
+ mov #0, r0
+ mov.w r0, @r1
+
+ rts
+ nop
+
+ .align 4
+
+/*
+ * Configuration for MPR2 A.3 through A.7
+ */
+
+/*
+ * PLL Settings
+ */
+FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */
+WTCNT_D: .word 0x5A00 /* start counting at zero */
+WTCSR_D: .word 0xA507 /* divide by 4096 */
+.align 2
+/*
+ * Spansion S29GL256N11 @ 48 MHz
+ */
+/* 1 idle cycle inserted, normal space, 16 bit */
+CS0BCR_D: .long 0x12490400
+/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
+CS0WCR_D: .long 0x00000340
+
+/*
+ * Samsung K4S511632B-UL75 @ 48 MHz
+ * Micron MT48LC32M16A2-75 @ 48 MHz
+ */
+/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
+CS3BCR_D: .long 0x10004400
+/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
+CS3WCR_D: .long 0x00000091
+/* no refresh, 13 rows, 10 cols, NO bank active mode */
+SDCR_D1: .long 0x00000012
+SDCR_D2: .long 0x00000812 /* refresh */
+RTCSR_D: .long 0xA55A0008 /* 1/4, once */
+RTCNT_D: .long 0xA55A005D /* count 93 */
+RTCOR_D: .long 0xa55a005d /* count 93 */
+/* mode register CL2, burst read and SINGLE WRITE */
+SDMR3_D: .long 0x440
+
+/*
+ * Registers
+ */
+
+FRQCR_A: .long 0xA415FF80
+WTCNT_A: .long 0xA415FF84
+WTCSR_A: .long 0xA415FF86
+
+#define BSC_BASE 0xA4FD0000
+CS0BCR_A: .long BSC_BASE + 0x04
+CS3BCR_A: .long BSC_BASE + 0x0C
+CS0WCR_A: .long BSC_BASE + 0x24
+CS3WCR_A: .long BSC_BASE + 0x2C
+SDCR_A: .long BSC_BASE + 0x44
+RTCSR_A: .long BSC_BASE + 0x48
+RTCNT_A: .long BSC_BASE + 0x4C
+RTCOR_A: .long BSC_BASE + 0x50
+SDMR3_A: .long BSC_BASE + 0x5000
diff --git a/board/mpr2/mpr2.c b/board/mpr2/mpr2.c
new file mode 100644
index 0000000..7449e03
--- /dev/null
+++ b/board/mpr2/mpr2.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * board/mpr2/mpr2.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("BOARD: MPR2\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * For MPR2 A.3 through A.7
+ */
+
+ /* CS2: Ethernet (0xA8000000 - 0xABFFFFFF) */
+ __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */
+ __raw_writel(0x000003c0, CS2WCR); /* (WR:8), no ext. wait */
+
+ /* CS4: CAN1 (0xB0000000 - 0xB3FFFFFF) */
+ __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x00100981, CS4WCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+ /* CS5a: CAN2 (0xB4000000 - 0xB5FFFFFF) */
+ __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x00100981, CS5AWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+ /* CS5b: CAN3 (0xB6000000 - 0xB7FFFFFF) */
+ __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x00100981, CS5BWCR); /* (SW:1.5 WR:3 HW:1.5), ext. wait */
+
+ /* CS6a: Rotary (0xB8000000 - 0xB9FFFFFF) */
+ __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */
+ __raw_writel(0x001009C1, CS6AWCR); /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
+
+ /* set Pin Select Register A: /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND */
+ __raw_writew(0xAABC, PSELA); /* 10 10 10 10 10 11 11 00 */
+
+ /* set Pin Select Register B: /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved */
+ __raw_writew(0x3C00, PSELB); /* 0 0 11 11 0 0 00000000 */
+
+ /* set Pin Select Register C: SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved */
+ __raw_writew(0x0000, PSELC); /* 00 00 00 00 00000000 */
+
+ /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */
+ __raw_writew(0x0000, PSELD); /* 0 00 00 00 00 00 00 00 0 */
+
+ /* OTH: (00) Other fuction
+ * GPO: (01) General Purpose Output
+ * GPI: (11) General Purpose Input
+ * GPI+: (10) General Purpose Input with internal pull-up
+ *-------------------------------------------------------
+ * A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
+ * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); */
+ __raw_writew(0x5555, PACR); /* 01 01 01 01 01 01 01 01 */
+
+ /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
+ * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); */
+ __raw_writew(0x5555, PBCR); /* 01 01 01 01 01 01 01 01 */
+
+ /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
+ * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; */
+ __raw_writew(0x5500, PCCR); /* 01 01 01 01 00 00 00 00 */
+
+ /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
+ * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); */
+ __raw_writew(0x5555, PDCR); /* 01 01 01 01 01 01 01 01 */
+
+ /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
+ * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; */
+ __raw_writew(0x2800, PECR); /* 00 10 10 00 00 00 00 00 */
+
+ /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
+ * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); */
+ __raw_writew(0x0002, PFCR); /* 00 00 00 00 00 00 00 10 */
+
+ /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ);G4 GPI(KEY2);
+ * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); */
+ __raw_writew(0x03D5, PGCR); /* 00 00 00 11 11 01 01 01 */
+
+ /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
+ * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; */
+ __raw_writew(0x0050, PHCR); /* 00 00 00 00 01 01 00 00 */
+
+ /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
+ * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; */
+ __raw_writew(0x0000, PJCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* K7 (x); K6 (x); K5 (x); K4 (x)
+ * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nc); K0 PINT4(FLASH_READY); */
+ __raw_writew(0x00FB, PKCR); /* 00 00 00 00 11 11 10 11 */
+
+ /* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
+ * L3 TCK; L2 (x); L1 (x); L0 (x); */
+ __raw_writew(0x0000, PLCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* M7 GPO(CURRENT_SINK);M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); M4 GPO(LAN_RESET);
+ * M3 GPO(BUZZER); M2 GPO(LCD_BL); M1 CS5B(CAN3_CS); M0 GPI+(nc); */
+ __raw_writew(0x5552, PMCR); /* 01 01 01 01 01 01 00 10 */
+ __raw_writeb(0xF0, PMDR); /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, LAN_RESET=off, BUZZER=off, LCD_BL=off */
+
+ /* P7 (x); P6 (x); P5 (x); P4 GPO(on pullup);
+ * P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ); */
+ __raw_writew(0x0100, PPCR); /* 00 00 00 01 00 00 00 00 */
+ __raw_writeb(0x10, PPDR); /* no current flow through pullup */
+
+ /* R7 A25; R6 A24; R5 A23; R4 A22;
+ * R3 A21; R2 A20; R1 A19; R0 A0; */
+ __raw_writew(0x0000, PRCR); /* 00 00 00 00 00 00 00 00 */
+
+ /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
+ * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; */
+ __raw_writew(0x0140, PSCR); /* 00 00 00 01 01 00 00 00 */
+
+ /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
+ * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG); */
+ __raw_writew(0x0001, PTCR); /* 00 00 00 00 00 00 00 01 */
+
+ /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
+ * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; */
+ __raw_writew(0x0240, PUCR); /* 00 00 00 10 01 00 00 00 */
+
+ /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
+ * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); */
+ __raw_writew(0x0142, PVCR); /* 00 00 00 01 01 00 00 10 */
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("SDRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
diff --git a/board/ms7720se/Kconfig b/board/ms7720se/Kconfig
new file mode 100644
index 0000000..8331327
--- /dev/null
+++ b/board/ms7720se/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_MS7720SE
+
+config SYS_BOARD
+ default "ms7720se"
+
+config SYS_CONFIG_NAME
+ default "ms7720se"
+
+endif
diff --git a/board/ms7720se/MAINTAINERS b/board/ms7720se/MAINTAINERS
new file mode 100644
index 0000000..96a80f4
--- /dev/null
+++ b/board/ms7720se/MAINTAINERS
@@ -0,0 +1,6 @@
+MS7720SE BOARD
+M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+S: Maintained
+F: board/ms7720se/
+F: include/configs/ms7720se.h
+F: configs/ms7720se_defconfig
diff --git a/board/ms7720se/Makefile b/board/ms7720se/Makefile
new file mode 100644
index 0000000..1819c4c
--- /dev/null
+++ b/board/ms7720se/Makefile
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2007
+# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/ms7720se/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := ms7720se.o
+obj-y += lowlevel_init.o
diff --git a/board/ms7720se/lowlevel_init.S b/board/ms7720se/lowlevel_init.S
new file mode 100644
index 0000000..3f3d21e
--- /dev/null
+++ b/board/ms7720se/lowlevel_init.S
@@ -0,0 +1,185 @@
+/*
+ * (C) Copyright 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/macro.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ write16 WTCSR_A, WTCSR_D
+
+ write16 WTCNT_A, WTCNT_D
+
+ write16 FRQCR_A, FRQCR_D
+
+ write16 UCLKCR_A, UCLKCR_D
+
+ write32 CMNCR_A, CMNCR_D
+
+ write32 CMNCR_A, CMNCR_D
+
+ write32 CS0BCR_A, CS0BCR_D
+
+ write32 CS2BCR_A, CS2BCR_D
+
+ write32 CS3BCR_A, CS3BCR_D
+
+ write32 CS4BCR_A, CS4BCR_D
+
+ write32 CS5ABCR_A, CS5ABCR_D
+
+ write32 CS5BBCR_A, CS5BBCR_D
+
+ write32 CS6ABCR_A, CS6ABCR_D
+
+ write32 CS6BBCR_A, CS6BBCR_D
+
+ write32 CS0WCR_A, CS0WCR_D
+
+ write32 CS2WCR_A, CS2WCR_D
+
+ write32 CS3WCR_A, CS3WCR_D
+
+ write32 CS4WCR_A, CS4WCR_D
+
+ write32 CS5AWCR_A, CS5AWCR_D
+
+ write32 CS5BWCR_A, CS5BWCR_D
+
+ write32 CS6AWCR_A, CS6AWCR_D
+
+ write32 CS6BWCR_A, CS6BWCR_D
+
+ write32 SDCR_A, SDCR_D1
+
+ write32 RTCSR_A, RTCSR_D
+
+ write32 RTCNT_A RTCNT_D
+
+ write32 RTCOR_A, RTCOR_D
+
+ write32 SDCR_A, SDCR_D2
+
+ write16 SDMR3_A, SDMR3_D
+
+ write16 PCCR_A, PCCR_D
+
+ write16 PDCR_A, PDCR_D
+
+ write16 PECR_A, PECR_D
+
+ write16 PGCR_A, PGCR_D
+
+ write16 PHCR_A, PHCR_D
+
+ write16 PPCR_A, PPCR_D
+
+ write16 PTCR_A, PTCR_D
+
+ write16 PVCR_A, PVCR_D
+
+ write16 PSELA_A, PSELA_D
+
+ write32 CCR_A, CCR_D
+
+ write8 LED_A, LED_D
+
+ rts
+ nop
+
+ .align 4
+
+FRQCR_A: .long 0xA415FF80 /* FRQCR Address */
+WTCNT_A: .long 0xA415FF84
+WTCSR_A: .long 0xA415FF86
+UCLKCR_A: .long 0xA40A0008
+FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */
+WTCNT_D: .word 0x5A00
+WTCSR_D: .word 0xA506
+UCLKCR_D: .word 0xA5C0
+
+#define BSC_BASE 0xA4FD0000
+CMNCR_A: .long BSC_BASE
+CS0BCR_A: .long BSC_BASE + 0x04
+CS2BCR_A: .long BSC_BASE + 0x08
+CS3BCR_A: .long BSC_BASE + 0x0C
+CS4BCR_A: .long BSC_BASE + 0x10
+CS5ABCR_A: .long BSC_BASE + 0x14
+CS5BBCR_A: .long BSC_BASE + 0x18
+CS6ABCR_A: .long BSC_BASE + 0x1C
+CS6BBCR_A: .long BSC_BASE + 0x20
+CS0WCR_A: .long BSC_BASE + 0x24
+CS2WCR_A: .long BSC_BASE + 0x28
+CS3WCR_A: .long BSC_BASE + 0x2C
+CS4WCR_A: .long BSC_BASE + 0x30
+CS5AWCR_A: .long BSC_BASE + 0x34
+CS5BWCR_A: .long BSC_BASE + 0x38
+CS6AWCR_A: .long BSC_BASE + 0x3C
+CS6BWCR_A: .long BSC_BASE + 0x40
+SDCR_A: .long BSC_BASE + 0x44
+RTCSR_A: .long BSC_BASE + 0x48
+RTCNT_A: .long BSC_BASE + 0x4C
+RTCOR_A: .long BSC_BASE + 0x50
+SDMR3_A: .long BSC_BASE + 0x58C0
+
+CMNCR_D: .long 0x00000010
+CS0BCR_D: .long 0x36DB0400
+CS2BCR_D: .long 0x36DB0400
+CS3BCR_D: .long 0x36DB4600
+CS4BCR_D: .long 0x36DB0400
+CS5ABCR_D: .long 0x36DB0400
+CS5BBCR_D: .long 0x36DB0200
+CS6ABCR_D: .long 0x36DB0400
+CS6BBCR_D: .long 0x36DB0400
+CS0WCR_D: .long 0x00000B01
+CS2WCR_D: .long 0x00000500
+CS3WCR_D: .long 0x00006D1B
+CS4WCR_D: .long 0x00000500
+CS5AWCR_D: .long 0x00000500
+CS5BWCR_D: .long 0x00000500
+CS6AWCR_D: .long 0x00000500
+CS6BWCR_D: .long 0x00000500
+SDCR_D1: .long 0x00000011
+RTCSR_D: .long 0xA55A0010
+RTCNT_D: .long 0xA55A001F
+RTCOR_D: .long 0xA55A001F
+SDMR3_D: .word 0x0000
+.align 2
+SDCR_D2: .long 0x00000811
+
+#define PFC_BASE 0xA4050100
+PCCR_A: .long PFC_BASE + 0x04
+PDCR_A: .long PFC_BASE + 0x06
+PECR_A: .long PFC_BASE + 0x08
+PGCR_A: .long PFC_BASE + 0x0C
+PHCR_A: .long PFC_BASE + 0x0E
+PPCR_A: .long PFC_BASE + 0x18
+PTCR_A: .long PFC_BASE + 0x1E
+PVCR_A: .long PFC_BASE + 0x22
+PSELA_A: .long PFC_BASE + 0x24
+
+PCCR_D: .word 0x0000
+PDCR_D: .word 0x0000
+PECR_D: .word 0x0000
+PGCR_D: .word 0x0000
+PHCR_D: .word 0x0000
+PPCR_D: .word 0x00AA
+PTCR_D: .word 0x0280
+PVCR_D: .word 0x0000
+PSELA_D: .word 0x0000
+.align 2
+
+CCR_A: .long 0xFFFFFFEC
+!CCR_D: .long 0x0000000D
+CCR_D: .long 0x0000000B
+
+LED_A: .long 0xB6800000
+LED_D: .long 0xFF
diff --git a/board/ms7720se/ms7720se.c b/board/ms7720se/ms7720se.c
new file mode 100644
index 0000000..534a422
--- /dev/null
+++ b/board/ms7720se/ms7720se.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2007
+ * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/ms7720se/ms7720se.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LED_BASE 0xB0800000
+
+int checkboard(void)
+{
+ puts("BOARD: Hitachi UL MS7720SE\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+ outw(value & 0xFF, LED_BASE);
+}
diff --git a/board/ms7722se/Kconfig b/board/ms7722se/Kconfig
new file mode 100644
index 0000000..39027c9
--- /dev/null
+++ b/board/ms7722se/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_MS7722SE
+
+config SYS_BOARD
+ default "ms7722se"
+
+config SYS_CONFIG_NAME
+ default "ms7722se"
+
+endif
diff --git a/board/ms7722se/MAINTAINERS b/board/ms7722se/MAINTAINERS
new file mode 100644
index 0000000..61614ba
--- /dev/null
+++ b/board/ms7722se/MAINTAINERS
@@ -0,0 +1,7 @@
+MS7722SE BOARD
+M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S: Maintained
+F: board/ms7722se/
+F: include/configs/ms7722se.h
+F: configs/ms7722se_defconfig
diff --git a/board/ms7722se/Makefile b/board/ms7722se/Makefile
new file mode 100644
index 0000000..9f7af78
--- /dev/null
+++ b/board/ms7722se/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/ms7722se/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := ms7722se.o
+obj-y += lowlevel_init.o
diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S
new file mode 100644
index 0000000..db859f4
--- /dev/null
+++ b/board/ms7722se/lowlevel_init.S
@@ -0,0 +1,226 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/ms7722se/lowlevel_init.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ /*
+ * Cache Control Register
+ * Instruction Cache Invalidate
+ */
+ write32 CCR_A, CCR_D
+
+ /*
+ * Address of MMU Control Register
+ * TI == TLB Invalidate bit
+ */
+ write32 MMUCR_A, MMUCR_D
+
+ /* Address of Power Control Register 0 */
+ write32 MSTPCR0_A, MSTPCR0_D
+
+ /* Address of Power Control Register 2 */
+ write32 MSTPCR2_A, MSTPCR2_D
+
+ write16 SBSCR_A, SBSCR_D
+
+ write16 PSCR_A, PSCR_D
+
+ /* 0xA4520004 (Watchdog Control / Status Register) */
+! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */
+
+ /* 0xA4520000 (Watchdog Count Register) */
+ write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */
+
+ /* 0xA4520004 (Watchdog Control / Status Register) */
+ write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */
+
+ /* 0xA4150000 Frequency control register */
+ write32 FRQCR_A, FRQCR_D
+
+ write32 CCR_A, CCR_D_2
+
+bsc_init:
+
+ write16 PSELA_A, PSELA_D
+
+ write16 DRVCR_A, DRVCR_D
+
+ write16 PCCR_A, PCCR_D
+
+ write16 PECR_A, PECR_D
+
+ write16 PJCR_A, PJCR_D
+
+ write16 PXCR_A, PXCR_D
+
+ write32 CMNCR_A, CMNCR_D
+
+ write32 CS0BCR_A, CS0BCR_D
+
+ write32 CS2BCR_A, CS2BCR_D
+
+ write32 CS4BCR_A, CS4BCR_D
+
+ write32 CS5ABCR_A, CS5ABCR_D
+
+ write32 CS5BBCR_A, CS5BBCR_D
+
+ write32 CS6ABCR_A, CS6ABCR_D
+
+ write32 CS0WCR_A, CS0WCR_D
+
+ write32 CS2WCR_A, CS2WCR_D
+
+ write32 CS4WCR_A, CS4WCR_D
+
+ write32 CS5AWCR_A, CS5AWCR_D
+
+ write32 CS5BWCR_A, CS5BWCR_D
+
+ write32 CS6AWCR_A, CS6AWCR_D
+
+ ! SDRAM initialization
+ write32 SDCR_A, SDCR_D
+
+ write32 SDWCR_A, SDWCR_D
+
+ write32 SDPCR_A, SDPCR_D
+
+ write32 RTCOR_A, RTCOR_D
+
+ write32 RTCSR_A, RTCSR_D
+
+ write8 SDMR3_A, SDMR3_D
+
+ ! BL bit off (init = ON) (?!?)
+
+ stc sr, r0 ! BL bit off(init=ON)
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+ mov #0, r0
+
+ .align 2
+
+CCR_A: .long CCR
+MMUCR_A: .long MMUCR
+MSTPCR0_A: .long MSTPCR0
+MSTPCR2_A: .long MSTPCR2
+SBSCR_A: .long SBSCR
+PSCR_A: .long PSCR
+RWTCSR_A: .long RWTCSR
+RWTCNT_A: .long RWTCNT
+FRQCR_A: .long FRQCR
+
+CCR_D: .long 0x00000800
+CCR_D_2: .long 0x00000103
+MMUCR_D: .long 0x00000004
+MSTPCR0_D: .long 0x00001001
+MSTPCR2_D: .long 0xffffffff
+FRQCR_D: .long 0x07022538
+
+PSELA_A: .long 0xa405014E
+PSELA_D: .word 0x0A10
+ .align 2
+
+DRVCR_A: .long 0xa405018A
+DRVCR_D: .word 0x0554
+ .align 2
+
+PCCR_A: .long 0xa4050104
+PCCR_D: .word 0x8800
+ .align 2
+
+PECR_A: .long 0xa4050108
+PECR_D: .word 0x0000
+ .align 2
+
+PJCR_A: .long 0xa4050110
+PJCR_D: .word 0x1000
+ .align 2
+
+PXCR_A: .long 0xa4050148
+PXCR_D: .word 0x0AAA
+ .align 2
+
+CMNCR_A: .long CMNCR
+CMNCR_D: .long 0x00000013
+CS0BCR_A: .long CS0BCR ! Flash bank 1
+CS0BCR_D: .long 0x24920400
+CS2BCR_A: .long CS2BCR ! SRAM
+CS2BCR_D: .long 0x24920400
+CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
+CS4BCR_D: .long 0x24920400
+CS5ABCR_A: .long CS5ABCR ! Ext slot
+CS5ABCR_D: .long 0x24920400
+CS5BBCR_A: .long CS5BBCR ! USB controller
+CS5BBCR_D: .long 0x24920400
+CS6ABCR_A: .long CS6ABCR ! Ethernet
+CS6ABCR_D: .long 0x24920400
+
+CS0WCR_A: .long CS0WCR
+CS0WCR_D: .long 0x00000300
+CS2WCR_A: .long CS2WCR
+CS2WCR_D: .long 0x00000300
+CS4WCR_A: .long CS4WCR
+CS4WCR_D: .long 0x00000300
+CS5AWCR_A: .long CS5AWCR
+CS5AWCR_D: .long 0x00000300
+CS5BWCR_A: .long CS5BWCR
+CS5BWCR_D: .long 0x00000300
+CS6AWCR_A: .long CS6AWCR
+CS6AWCR_D: .long 0x00000300
+
+SDCR_A: .long SBSC_SDCR
+SDCR_D: .long 0x00020809
+SDWCR_A: .long SBSC_SDWCR
+SDWCR_D: .long 0x00164d0d
+SDPCR_A: .long SBSC_SDPCR
+SDPCR_D: .long 0x00000087
+RTCOR_A: .long SBSC_RTCOR
+RTCOR_D: .long 0xA55A0034
+RTCSR_A: .long SBSC_RTCSR
+RTCSR_D: .long 0xA55A0010
+SDMR3_A: .long 0xFE500180
+SDMR3_D: .long 0x0
+
+ .align 1
+
+SBSCR_D: .word 0x0040
+PSCR_D: .word 0x0000
+RWTCSR_D_1: .word 0xA507
+RWTCSR_D_2: .word 0xA507
+RWTCNT_D: .word 0x5A00
+ .align 2
+
+SR_MASK_D: .long 0xEFFFFF0F
diff --git a/board/ms7722se/ms7722se.c b/board/ms7722se/ms7722se.c
new file mode 100644
index 0000000..ee1e99c
--- /dev/null
+++ b/board/ms7722se/ms7722se.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/ms7722se/ms7722se.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define LED_BASE 0xB0800000
+
+int checkboard(void)
+{
+ puts("BOARD: Hitachi UL MS7722SE\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Setup PTXMD[1:0] for /CS6A */
+ outw(inw(PXCR) & ~0xf000, PXCR);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+ writew(value & 0xFF, LED_BASE);
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/ms7750se/Kconfig b/board/ms7750se/Kconfig
new file mode 100644
index 0000000..2c0b88c
--- /dev/null
+++ b/board/ms7750se/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_MS7750SE
+
+config SYS_BOARD
+ default "ms7750se"
+
+config SYS_CONFIG_NAME
+ default "ms7750se"
+
+endif
diff --git a/board/ms7750se/MAINTAINERS b/board/ms7750se/MAINTAINERS
new file mode 100644
index 0000000..e23a532
--- /dev/null
+++ b/board/ms7750se/MAINTAINERS
@@ -0,0 +1,7 @@
+MS7750SE BOARD
+M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S: Maintained
+F: board/ms7750se/
+F: include/configs/ms7750se.h
+F: configs/ms7750se_defconfig
diff --git a/board/ms7750se/Makefile b/board/ms7750se/Makefile
new file mode 100644
index 0000000..a8e3ca0
--- /dev/null
+++ b/board/ms7750se/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ms7750se.o
+obj-y += lowlevel_init.o
diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S
new file mode 100644
index 0000000..c02306f
--- /dev/null
+++ b/board/ms7750se/lowlevel_init.S
@@ -0,0 +1,143 @@
+/*
+ modified from SH-IPL+g
+ Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
+
+ Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
+
+ Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
+
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+#ifdef CONFIG_CPU_SH7751
+#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
+#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
+#ifdef CONFIG_MARUBUN_PCCARD
+#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+ A3:2 A2:15 A1:15 A0:6 A0B:7 */
+#else /* CONFIG_MARUBUN_PCCARD */
+#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
+ A3:2 A2:15 A1:15 A0:6 A0B:7 */
+#endif /* CONFIG_MARUBUN_PCCARD */
+#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
+ A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
+#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
+#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
+#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
+#else /* CONFIG_CPU_SH7751 */
+#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
+#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
+#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+ A3:2 A2:15 A1:15 A0:15 A0B:7 */
+#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
+ A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
+#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
+#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
+#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
+#endif /* CONFIG_CPU_SH7751 */
+
+ .global lowlevel_init
+ .text
+ .align 2
+
+lowlevel_init:
+
+ write32 CCR_A, CCR_D_DISABLE
+
+init_bsc:
+ write16 FRQCR_A, FRQCR_D
+
+ write32 BCR1_A, BCR1_D
+
+ write16 BCR2_A, BCR2_D
+
+ write32 WCR1_A, WCR1_D
+
+ write32 WCR2_A, WCR2_D
+
+ write32 WCR3_A, WCR3_D
+
+ write32 MCR_A, MCR_D1
+
+ /* Set SDRAM mode */
+ write8 SDMR3_A, SDMR3_D
+
+ ! Do you need PCMCIA setting?
+ ! If so, please add the lines here...
+
+ write16 RTCNT_A, RTCNT_D
+
+ write16 RTCOR_A, RTCOR_D
+
+ write16 RTCSR_A, RTCSR_D
+
+ write16 RFCR_A, RFCR_D
+
+ /* Wait DRAM refresh 30 times */
+ mov #30, r3
+1:
+ mov.w @r1, r0
+ extu.w r0, r2
+ cmp/hi r3, r2
+ bf 1b
+
+ write32 MCR_A, MCR_D2
+
+ /* Set SDRAM mode */
+ write8 SDMR3_A, SDMR3_D
+
+ rts
+ nop
+
+ .align 2
+
+CCR_A: .long CCR
+CCR_D_DISABLE: .long 0x0808
+FRQCR_A: .long FRQCR
+FRQCR_D:
+#ifdef CONFIG_CPU_TYPE_R
+ .word 0x0e1a /* 12:3:3 */
+#else /* CONFIG_CPU_TYPE_R */
+#ifdef CONFIG_GOOD_SESH4
+ .word 0x00e13 /* 6:2:1 */
+#else
+ .word 0x00e23 /* 6:1:1 */
+#endif
+.align 2
+#endif /* CONFIG_CPU_TYPE_R */
+
+BCR1_A: .long BCR1
+BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
+BCR2_A: .long BCR2
+BCR2_D: .long BCR2_D_VALUE /* Bus width settings */
+WCR1_A: .long WCR1
+WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
+WCR2_A: .long WCR2
+WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
+WCR3_A: .long WCR3
+WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
+RTCSR_A: .long RTCSR
+RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */
+.align 2
+RTCNT_A: .long RTCNT
+RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
+.align 2
+RTCOR_A: .long RTCOR
+RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */
+.align 2
+SDMR3_A: .long SDMR3_ADDRESS
+SDMR3_D: .long 0x00
+MCR_A: .long MCR
+MCR_D1: .long MCR_D1_VALUE
+MCR_D2: .long MCR_D2_VALUE
+RFCR_A: .long RFCR
+RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */
+.align 2
diff --git a/board/ms7750se/ms7750se.c b/board/ms7750se/ms7750se.c
new file mode 100644
index 0000000..a7f9346
--- /dev/null
+++ b/board/ms7750se/ms7750se.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
diff --git a/board/munices/Kconfig b/board/munices/Kconfig
new file mode 100644
index 0000000..019aaae
--- /dev/null
+++ b/board/munices/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_MUNICES
+
+config SYS_BOARD
+ default "munices"
+
+config SYS_CONFIG_NAME
+ default "munices"
+
+endif
diff --git a/board/munices/MAINTAINERS b/board/munices/MAINTAINERS
new file mode 100644
index 0000000..50d3e7e
--- /dev/null
+++ b/board/munices/MAINTAINERS
@@ -0,0 +1,6 @@
+MUNICES BOARD
+#M: -
+S: Maintained
+F: board/munices/
+F: include/configs/munices.h
+F: configs/munices_defconfig
diff --git a/board/munices/Makefile b/board/munices/Makefile
new file mode 100644
index 0000000..d16e2a1
--- /dev/null
+++ b/board/munices/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := munices.o
diff --git a/board/munices/mt48lc16m16a2-75.h b/board/munices/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..0133eaa
--- /dev/null
+++ b/board/munices/mt48lc16m16a2-75.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 0 /* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/munices/munices.c b/board/munices/munices.c
new file mode 100644
index 0000000..23d0f56
--- /dev/null
+++ b/board/munices/munices.c
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#include "mt48lc16m16a2-75.h"
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+#endif
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR && SDRAM_TAPDELAY
+ /* set tap delay */
+ *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
+ sdram_start(1);
+ test2 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13) {
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ } else {
+ dramsize = 0;
+ }
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ if (dramsize2 >= 0x13) {
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ } else {
+ dramsize2 = 0;
+ }
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+ puts ("Board: MUNICes\n");
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/nokia/rx51/Kconfig b/board/nokia/rx51/Kconfig
new file mode 100644
index 0000000..ec6a571
--- /dev/null
+++ b/board/nokia/rx51/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NOKIA_RX51
+
+config SYS_BOARD
+ default "rx51"
+
+config SYS_VENDOR
+ default "nokia"
+
+config SYS_CONFIG_NAME
+ default "nokia_rx51"
+
+endif
diff --git a/board/nokia/rx51/MAINTAINERS b/board/nokia/rx51/MAINTAINERS
new file mode 100644
index 0000000..8bdddc1
--- /dev/null
+++ b/board/nokia/rx51/MAINTAINERS
@@ -0,0 +1,6 @@
+RX51 BOARD
+M: Pali Rohár <pali.rohar@gmail.com>
+S: Maintained
+F: board/nokia/rx51/
+F: include/configs/nokia_rx51.h
+F: configs/nokia_rx51_defconfig
diff --git a/board/nokia/rx51/Makefile b/board/nokia/rx51/Makefile
new file mode 100644
index 0000000..8d4d97b
--- /dev/null
+++ b/board/nokia/rx51/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := rx51.o
+obj-y += lowlevel_init.o
diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S
new file mode 100644
index 0000000..e252909
--- /dev/null
+++ b/board/nokia/rx51/lowlevel_init.S
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+relocaddr: /* address of this relocaddr section after coping */
+ .word . /* address of section (calculated at compile time) */
+
+startaddr: /* address of u-boot after copying */
+ .word CONFIG_SYS_TEXT_BASE
+
+kernaddr: /* address of kernel after copying */
+ .word KERNEL_ADDRESS
+
+kernsize: /* maximal size of kernel image */
+ .word KERNEL_MAXSIZE
+
+kernoffs: /* offset of kernel image in loaded u-boot */
+ .word KERNEL_OFFSET
+
+imagesize: /* maximal size of image */
+ .word IMAGE_MAXSIZE
+
+ih_magic: /* IH_MAGIC in big endian from include/image.h */
+ .word 0x56190527
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ * Description: Copy attached kernel to address KERNEL_ADDRESS
+ * Copy u-boot to address CONFIG_SYS_TEXT_BASE
+ * Return to copied u-boot address
+ */
+
+.global save_boot_params
+save_boot_params:
+
+
+/* Copy valid attached kernel to address KERNEL_ADDRESS */
+
+copy_kernel_start:
+ adr r0, relocaddr /* r0 - address of section relocaddr */
+ ldr r1, relocaddr /* r1 - address of relocaddr after relocation */
+ cmp r0, r1
+
+ /* r4 - calculated offset */
+ subhi r4, r0, r1
+ sublo r4, r1, r0
+
+ /* r0 - start of kernel before */
+ ldr r0, startaddr
+ addhi r0, r0, r4
+ sublo r0, r0, r4
+ ldr r1, kernoffs
+ add r0, r0, r1
+
+ /* r3 - start of kernel after */
+ ldr r3, kernaddr
+
+ /* r2 - end of kernel after */
+ ldr r1, kernsize
+ add r2, r3, r1
+
+ /* r1 - end of kernel before */
+ add r1, r0, r1
+
+ /* remove header in target kernel */
+ mov r5, #0
+ str r5, [r3]
+
+ /* check for valid kernel uImage */
+ ldr r4, [r0] /* r4 - 4 bytes header of kernel */
+ ldr r5, ih_magic /* r5 - IH_MAGIC */
+ cmp r4, r5
+ bne copy_kernel_end /* skip if invalid image */
+
+copy_kernel_loop:
+ ldmdb r1!, {r3 - r10}
+ stmdb r2!, {r3 - r10}
+ cmp r1, r0
+ bhi copy_kernel_loop
+
+copy_kernel_end:
+ mov r5, #0
+ str r5, [r0] /* remove 4 bytes header of kernel */
+
+
+/* Fix u-boot code */
+
+fix_start:
+ adr r0, relocaddr /* r0 - address of section relocaddr */
+ ldr r1, relocaddr /* r1 - address of relocaddr after relocation */
+ cmp r0, r1
+
+ beq copy_uboot_end /* skip if u-boot is on correct address */
+
+ /* r5 - calculated offset */
+ subhi r5, r0, r1
+ sublo r5, r1, r0
+
+ /* r6 - maximal u-boot size */
+ ldr r6, imagesize
+
+ /* fix return address */
+ subhi lr, lr, r5
+ addlo lr, lr, r5
+
+ /* r1 - start of u-boot after */
+ ldr r1, startaddr
+
+ /* r0 - start of u-boot before */
+ addhi r0, r1, r5
+ sublo r0, r1, r5
+
+ /* check if we need to move uboot copy code before calling it */
+ cmp r5, r6
+ bhi copy_uboot_start /* now coping u-boot code directly is safe */
+
+
+copy_code_start:
+ /* r0 - start of u-boot before */
+ /* r1 - start of u-boot after */
+ /* r6 - maximal u-boot size */
+
+ /* r7 - maximal kernel size */
+ ldr r7, kernsize
+
+ /* r4 - end of kernel before */
+ add r4, r0, r6
+ add r4, r4, r7
+
+ /* r5 - end of u-boot after */
+ ldr r5, startaddr
+ add r5, r5, r6
+
+ /* r2 - start of loop code after */
+ cmp r4, r5 /* higher address (r4 or r5) */
+ movhs r2, r4
+ movlo r2, r5
+
+ /* r3 - end of loop code before */
+ adr r3, end
+
+ /* r4 - end of loop code after */
+ adr r4, copy_uboot_start
+ sub r4, r3, r4
+ add r4, r2, r4
+
+copy_code_loop:
+ ldmdb r3!, {r7 - r10}
+ stmdb r4!, {r7 - r10}
+ cmp r4, r2
+ bhi copy_code_loop
+
+copy_code_end:
+ mov pc, r2
+
+
+/* Copy u-boot to address CONFIG_SYS_TEXT_BASE */
+
+copy_uboot_start:
+ /* r0 - start of u-boot before */
+ /* r1 - start of u-boot after */
+ /* r6 - maximal u-boot size */
+
+ /* r2 - end of u-boot after */
+ add r2, r1, r6
+
+ /* condition for copying from left to right */
+ cmp r0, r1
+ addlo r1, r0, r6 /* r1 - end of u-boot before */
+ blo copy_uboot_loop_right
+
+copy_uboot_loop_left:
+ ldmia r0!, {r3 - r10}
+ stmia r1!, {r3 - r10}
+ cmp r1, r2
+ blo copy_uboot_loop_left
+ b copy_uboot_end
+
+copy_uboot_loop_right:
+ ldmdb r1!, {r3 - r10}
+ stmdb r2!, {r3 - r10}
+ cmp r1, r0
+ bhi copy_uboot_loop_right
+
+copy_uboot_end:
+ bx lr
+
+end:
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
new file mode 100644
index 0000000..08fcaf2
--- /dev/null
+++ b/board/nokia/rx51/rx51.c
@@ -0,0 +1,671 @@
+/*
+ * (C) Copyright 2012
+ * Ивайло Димитров <freemangordon@abv.bg>
+ *
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * (C) Copyright 2010
+ * Alistair Buxton <a.j.buxton@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code:
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <malloc.h>
+#include <twl4030.h>
+#include <i2c.h>
+#include <video_fb.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/bitops.h>
+#include <asm/mach-types.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+
+#include "rx51.h"
+#include "tag_omap.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+GraphicDevice gdev;
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "Nokia RX-51",
+ "OneNAND"
+};
+
+/* This structure contains default omap tags needed for booting Maemo 5 */
+static struct tag_omap omap[] = {
+ OMAP_TAG_UART_CONFIG(0x04),
+ OMAP_TAG_SERIAL_CONSOLE_CONFIG(0x03, 0x01C200),
+ OMAP_TAG_LCD_CONFIG("acx565akm", "internal", 90, 0x18),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cam_focus", 0x44, 0x1, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cam_launch", 0x45, 0x1, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cam_shutter", 0x6e, 0x1, 0x0, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_apeslpx", 0x46, 0x2, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_bsi", 0x9d, 0x2, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_en", 0x4a, 0x2, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst", 0x4b, 0x6, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_rst_rq", 0x49, 0x6, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("cmt_wddis", 0x0d, 0x2, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("headphone", 0xb1, 0x1, 0x1, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("kb_lock", 0x71, 0x1, 0x0, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("proximity", 0x59, 0x0, 0x0, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("sleep_ind", 0xa2, 0x2, 0x2, 0x0),
+ OMAP_TAG_GPIO_SWITCH_CONFIG("slide", GPIO_SLIDE, 0x0, 0x0, 0x0),
+ OMAP_TAG_WLAN_CX3110X_CONFIG(0x25, 0xff, 87, 42, -1),
+ OMAP_TAG_PARTITION_CONFIG(PART1_NAME, PART1_SIZE * PART1_MULL,
+ PART1_OFFS, PART1_MASK),
+ OMAP_TAG_PARTITION_CONFIG(PART2_NAME, PART2_SIZE * PART2_MULL,
+ PART2_OFFS, PART2_MASK),
+ OMAP_TAG_PARTITION_CONFIG(PART3_NAME, PART3_SIZE * PART3_MULL,
+ PART3_OFFS, PART3_MASK),
+ OMAP_TAG_PARTITION_CONFIG(PART4_NAME, PART4_SIZE * PART4_MULL,
+ PART4_OFFS, PART4_MASK),
+ OMAP_TAG_PARTITION_CONFIG(PART5_NAME, PART5_SIZE * PART5_MULL,
+ PART5_OFFS, PART5_MASK),
+ OMAP_TAG_PARTITION_CONFIG(PART6_NAME, PART6_SIZE * PART6_MULL,
+ PART6_OFFS, PART6_MASK),
+ OMAP_TAG_BOOT_REASON_CONFIG("pwr_key"),
+ OMAP_TAG_VERSION_STR_CONFIG("product", "RX-51"),
+ OMAP_TAG_VERSION_STR_CONFIG("hw-build", "2101"),
+ OMAP_TAG_VERSION_STR_CONFIG("nolo", "1.4.14"),
+ OMAP_TAG_VERSION_STR_CONFIG("boot-mode", "normal"),
+ { }
+};
+
+static char *boot_reason_ptr;
+static char *hw_build_ptr;
+static char *nolo_version_ptr;
+static char *boot_mode_ptr;
+
+/*
+ * Routine: init_omap_tags
+ * Description: Initialize pointers to values in tag_omap
+ */
+static void init_omap_tags(void)
+{
+ char *component;
+ char *version;
+ int i = 0;
+ while (omap[i].hdr.tag) {
+ switch (omap[i].hdr.tag) {
+ case OMAP_TAG_BOOT_REASON:
+ boot_reason_ptr = omap[i].u.boot_reason.reason_str;
+ break;
+ case OMAP_TAG_VERSION_STR:
+ component = omap[i].u.version.component;
+ version = omap[i].u.version.version;
+ if (strcmp(component, "hw-build") == 0)
+ hw_build_ptr = version;
+ else if (strcmp(component, "nolo") == 0)
+ nolo_version_ptr = version;
+ else if (strcmp(component, "boot-mode") == 0)
+ boot_mode_ptr = version;
+ break;
+ default:
+ break;
+ }
+ i++;
+ }
+}
+
+static void reuse_omap_atags(struct tag_omap *t)
+{
+ char *component;
+ char *version;
+ while (t->hdr.tag) {
+ switch (t->hdr.tag) {
+ case OMAP_TAG_BOOT_REASON:
+ memset(boot_reason_ptr, 0, 12);
+ strcpy(boot_reason_ptr, t->u.boot_reason.reason_str);
+ break;
+ case OMAP_TAG_VERSION_STR:
+ component = t->u.version.component;
+ version = t->u.version.version;
+ if (strcmp(component, "hw-build") == 0) {
+ memset(hw_build_ptr, 0, 12);
+ strcpy(hw_build_ptr, version);
+ } else if (strcmp(component, "nolo") == 0) {
+ memset(nolo_version_ptr, 0, 12);
+ strcpy(nolo_version_ptr, version);
+ } else if (strcmp(component, "boot-mode") == 0) {
+ memset(boot_mode_ptr, 0, 12);
+ strcpy(boot_mode_ptr, version);
+ }
+ break;
+ default:
+ break;
+ }
+ t = tag_omap_next(t);
+ }
+}
+
+/*
+ * Routine: reuse_atags
+ * Description: Reuse atags from previous bootloader.
+ * Reuse only only HW build, boot reason, boot mode and nolo
+ */
+static void reuse_atags(void)
+{
+ struct tag *t = (struct tag *)gd->bd->bi_boot_params;
+
+ /* First tag must be ATAG_CORE */
+ if (t->hdr.tag != ATAG_CORE)
+ return;
+
+ if (!boot_reason_ptr || !hw_build_ptr)
+ return;
+
+ /* Last tag must be ATAG_NONE */
+ while (t->hdr.tag != ATAG_NONE) {
+ switch (t->hdr.tag) {
+ case ATAG_REVISION:
+ memset(hw_build_ptr, 0, 12);
+ sprintf(hw_build_ptr, "%x", t->u.revision.rev);
+ break;
+ case ATAG_BOARD:
+ reuse_omap_atags((struct tag_omap *)&t->u);
+ break;
+ default:
+ break;
+ }
+ t = tag_next(t);
+ }
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ /* in SRAM or SDRAM, finish GPMC */
+ gpmc_init();
+ /* boot param addr */
+ gd->bd->bi_boot_params = OMAP34XX_SDRC_CS0 + 0x100;
+ return 0;
+}
+
+/*
+ * Routine: get_board_revision
+ * Description: Return board revision.
+ */
+u32 get_board_rev(void)
+{
+ return simple_strtol(hw_build_ptr, NULL, 16);
+}
+
+/*
+ * Routine: setup_board_tags
+ * Description: Append board specific boot tags.
+ */
+void setup_board_tags(struct tag **in_params)
+{
+ int setup_console_atag;
+ char *setup_boot_reason_atag;
+ char *setup_boot_mode_atag;
+ char *str;
+ int i;
+ int size;
+ int total_size;
+ struct tag *params;
+ struct tag_omap *t;
+
+ params = (struct tag *)gd->bd->bi_boot_params;
+
+ params->u.core.flags = 0x0;
+ params->u.core.pagesize = 0x1000;
+ params->u.core.rootdev = 0x0;
+
+ /* append omap atag only if env setup_omap_atag is set to 1 */
+ str = getenv("setup_omap_atag");
+ if (!str || str[0] != '1')
+ return;
+
+ str = getenv("setup_console_atag");
+ if (str && str[0] == '1')
+ setup_console_atag = 1;
+ else
+ setup_console_atag = 0;
+
+ setup_boot_reason_atag = getenv("setup_boot_reason_atag");
+ setup_boot_mode_atag = getenv("setup_boot_mode_atag");
+
+ params = *in_params;
+ t = (struct tag_omap *)¶ms->u;
+ total_size = sizeof(struct tag_header);
+
+ for (i = 0; omap[i].hdr.tag; i++) {
+
+ /* skip serial console tag */
+ if (!setup_console_atag &&
+ omap[i].hdr.tag == OMAP_TAG_SERIAL_CONSOLE)
+ continue;
+
+ size = omap[i].hdr.size + sizeof(struct tag_omap_header);
+ memcpy(t, &omap[i], size);
+
+ /* set uart tag to 0 - disable serial console */
+ if (!setup_console_atag && omap[i].hdr.tag == OMAP_TAG_UART)
+ t->u.uart.enabled_uarts = 0;
+
+ /* change boot reason */
+ if (setup_boot_reason_atag &&
+ omap[i].hdr.tag == OMAP_TAG_BOOT_REASON) {
+ memset(t->u.boot_reason.reason_str, 0, 12);
+ strcpy(t->u.boot_reason.reason_str,
+ setup_boot_reason_atag);
+ }
+
+ /* change boot mode */
+ if (setup_boot_mode_atag &&
+ omap[i].hdr.tag == OMAP_TAG_VERSION_STR &&
+ strcmp(omap[i].u.version.component, "boot-mode") == 0) {
+ memset(t->u.version.version, 0, 12);
+ strcpy(t->u.version.version, setup_boot_mode_atag);
+ }
+
+ total_size += size;
+ t = tag_omap_next(t);
+
+ }
+
+ params->hdr.tag = ATAG_BOARD;
+ params->hdr.size = total_size >> 2;
+ params = tag_next(params);
+
+ *in_params = params;
+}
+
+/*
+ * Routine: video_hw_init
+ * Description: Set up the GraphicDevice depending on sys_boot.
+ */
+void *video_hw_init(void)
+{
+ /* fill in Graphic Device */
+ gdev.frameAdrs = 0x8f9c0000;
+ gdev.winSizeX = 800;
+ gdev.winSizeY = 480;
+ gdev.gdfBytesPP = 2;
+ gdev.gdfIndex = GDF_16BIT_565RGB;
+ memset((void *)gdev.frameAdrs, 0, 0xbb800);
+ return (void *) &gdev;
+}
+
+/*
+ * Routine: twl4030_regulator_set_mode
+ * Description: Set twl4030 regulator mode over i2c powerbus.
+ */
+static void twl4030_regulator_set_mode(u8 id, u8 mode)
+{
+ u16 msg = MSG_SINGULAR(DEV_GRP_P1, id, mode);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_PB_WORD_MSB, msg >> 8);
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER,
+ TWL4030_PM_MASTER_PB_WORD_LSB, msg & 0xff);
+}
+
+static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
+{
+ u32 i, num_params = *parameters;
+ u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
+
+ /*
+ * copy the parameters to an un-cached area to avoid coherency
+ * issues
+ */
+ for (i = 0; i < num_params; i++) {
+ __raw_writel(*parameters, sram_scratch_space);
+ parameters++;
+ sram_scratch_space++;
+ }
+
+ /* Now make the PPA call */
+ do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
+}
+
+/*
+ * Routine: omap3_update_aux_cr_secure_rx51
+ * Description: Modify the contents Auxiliary Control Register.
+ * Parameters:
+ * set_bits - bits to set in ACR
+ * clr_bits - bits to clear in ACR
+ */
+static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
+{
+ struct emu_hal_params_rx51 emu_romcode_params = { 0, };
+ u32 acr;
+
+ /* Read ACR */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+ acr &= ~clear_bits;
+ acr |= set_bits;
+
+ emu_romcode_params.num_params = 2;
+ emu_romcode_params.param1 = acr;
+
+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+ (u32 *)&emu_romcode_params);
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts.
+ */
+int misc_init_r(void)
+{
+ char buf[12];
+ u8 state;
+
+ /* reset lp5523 led */
+ i2c_set_bus_num(1);
+ state = 0xff;
+ i2c_write(0x32, 0x3d, 1, &state, 1);
+ i2c_set_bus_num(0);
+
+ /* initialize twl4030 power managment */
+ twl4030_power_init();
+
+ /* set VSIM to 1.8V */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
+ TWL4030_PM_RECEIVER_VSIM_VSEL_18,
+ TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+ /* store I2C access state */
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+ &state);
+
+ /* enable I2C access to powerbus (needed for twl4030 regulator) */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+ 0x02);
+
+ /* set VAUX3, VSIM and VMMC1 state to active - enable eMMC memory */
+ twl4030_regulator_set_mode(RES_VAUX3, RES_STATE_ACTIVE);
+ twl4030_regulator_set_mode(RES_VSIM, RES_STATE_ACTIVE);
+ twl4030_regulator_set_mode(RES_VMMC1, RES_STATE_ACTIVE);
+
+ /* restore I2C access state */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, TWL4030_PM_MASTER_PB_CFG,
+ state);
+
+ /* set env variable attkernaddr for relocated kernel */
+ sprintf(buf, "%#x", KERNEL_ADDRESS);
+ setenv("attkernaddr", buf);
+
+ /* initialize omap tags */
+ init_omap_tags();
+
+ /* reuse atags from previous bootloader */
+ reuse_atags();
+
+ dieid_num_r();
+ print_cpuinfo();
+
+ /*
+ * Cortex-A8(r1p0..r1p2) errata 430973 workaround
+ * Set IBE bit in Auxiliary Control Register
+ *
+ * Call this routine only on real secure device
+ * Qemu does not implement secure PPA and crash
+ */
+ if (get_device_type() == HS_DEVICE)
+ omap3_update_aux_cr_secure_rx51(1 << 6, 0);
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_RX51();
+}
+
+static unsigned long int twl_wd_time; /* last time of watchdog reset */
+static unsigned long int twl_i2c_lock;
+
+/*
+ * Routine: hw_watchdog_reset
+ * Description: Reset timeout of twl4030 watchdog.
+ */
+void hw_watchdog_reset(void)
+{
+ u8 timeout = 0;
+
+ /* do not reset watchdog too often - max every 4s */
+ if (get_timer(twl_wd_time) < 4 * CONFIG_SYS_HZ)
+ return;
+
+ /* localy lock twl4030 i2c bus */
+ if (test_and_set_bit(0, &twl_i2c_lock))
+ return;
+
+ /* read actual watchdog timeout */
+ twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_WATCHDOG_CFG, &timeout);
+
+ /* timeout 0 means watchdog is disabled */
+ /* reset watchdog timeout to 31s (maximum) */
+ if (timeout != 0)
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_WATCHDOG_CFG, 31);
+
+ /* store last watchdog reset time */
+ twl_wd_time = get_timer(0);
+
+ /* localy unlock twl4030 i2c bus */
+ test_and_clear_bit(0, &twl_i2c_lock);
+}
+
+/*
+ * TWL4030 keypad handler for cfb_console
+ */
+
+static const char keymap[] = {
+ /* normal */
+ 'q', 'o', 'p', ',', '\b', 0, 'a', 's',
+ 'w', 'd', 'f', 'g', 'h', 'j', 'k', 'l',
+ 'e', '.', 0, '\r', 0, 'z', 'x', 'c',
+ 'r', 'v', 'b', 'n', 'm', ' ', ' ', 0,
+ 't', 0, 0, 0, 0, 0, 0, 0,
+ 'y', 0, 0, 0, 0, 0, 0, 0,
+ 'u', 0, 0, 0, 0, 0, 0, 0,
+ 'i', 5, 6, 0, 0, 0, 0, 0,
+ /* fn */
+ '1', '9', '0', '=', '\b', 0, '*', '+',
+ '2', '#', '-', '_', '(', ')', '&', '!',
+ '3', '?', '^', '\r', 0, 156, '$', 238,
+ '4', '/', '\\', '"', '\'', '@', 0, '<',
+ '5', '|', '>', 0, 0, 0, 0, 0,
+ '6', 0, 0, 0, 0, 0, 0, 0,
+ '7', 0, 0, 0, 0, 0, 0, 0,
+ '8', 16, 17, 0, 0, 0, 0, 0,
+};
+
+static u8 keys[8];
+static u8 old_keys[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+#define KEYBUF_SIZE 32
+static u8 keybuf[KEYBUF_SIZE];
+static u8 keybuf_head;
+static u8 keybuf_tail;
+
+/*
+ * Routine: rx51_kp_init
+ * Description: Initialize HW keyboard.
+ */
+int rx51_kp_init(void)
+{
+ int ret = 0;
+ u8 ctrl;
+ ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_CTRL_REG, &ctrl);
+
+ if (ret)
+ return ret;
+
+ /* turn on keyboard and use hardware scanning */
+ ctrl |= TWL4030_KEYPAD_CTRL_KBD_ON;
+ ctrl |= TWL4030_KEYPAD_CTRL_SOFT_NRST;
+ ctrl |= TWL4030_KEYPAD_CTRL_SOFTMODEN;
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_CTRL_REG, ctrl);
+ /* enable key event status */
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_IMR1, 0xfe);
+ /* enable interrupt generation on rising and falling */
+ /* this is a workaround for qemu twl4030 emulation */
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_EDR, 0x57);
+ /* enable ISR clear on read */
+ ret |= twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_SIH_CTRL, 0x05);
+ return 0;
+}
+
+static void rx51_kp_fill(u8 k, u8 mods)
+{
+ /* check if some cursor key without meta fn key was pressed */
+ if (!(mods & 2) && (k == 18 || k == 31 || k == 33 || k == 34)) {
+ keybuf[keybuf_tail++] = '\e';
+ keybuf_tail %= KEYBUF_SIZE;
+ keybuf[keybuf_tail++] = '[';
+ keybuf_tail %= KEYBUF_SIZE;
+ if (k == 18) /* up */
+ keybuf[keybuf_tail++] = 'A';
+ else if (k == 31) /* left */
+ keybuf[keybuf_tail++] = 'D';
+ else if (k == 33) /* down */
+ keybuf[keybuf_tail++] = 'B';
+ else if (k == 34) /* right */
+ keybuf[keybuf_tail++] = 'C';
+ keybuf_tail %= KEYBUF_SIZE;
+ return;
+ }
+
+ if (mods & 2) { /* fn meta key was pressed */
+ k = keymap[k+64];
+ } else {
+ k = keymap[k];
+ if (mods & 1) { /* ctrl key was pressed */
+ if (k >= 'a' && k <= 'z')
+ k -= 'a' - 1;
+ }
+ if (mods & 4) { /* shift key was pressed */
+ if (k >= 'a' && k <= 'z')
+ k += 'A' - 'a';
+ else if (k == '.')
+ k = ':';
+ else if (k == ',')
+ k = ';';
+ }
+ }
+ keybuf[keybuf_tail++] = k;
+ keybuf_tail %= KEYBUF_SIZE;
+}
+
+/*
+ * Routine: rx51_kp_tstc
+ * Description: Test if key was pressed (from buffer).
+ */
+int rx51_kp_tstc(struct stdio_dev *sdev)
+{
+ u8 c, r, dk, i;
+ u8 intr;
+ u8 mods;
+
+ /* localy lock twl4030 i2c bus */
+ if (test_and_set_bit(0, &twl_i2c_lock))
+ return 0;
+
+ /* twl4030 remembers up to 2 events */
+ for (i = 0; i < 2; i++) {
+
+ /* check interrupt register for events */
+ twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_KEYP_ISR1 + (2 * i), &intr);
+
+ /* no event */
+ if (!(intr&1))
+ continue;
+
+ /* read the key state */
+ i2c_read(TWL4030_CHIP_KEYPAD,
+ TWL4030_KEYPAD_FULL_CODE_7_0, 1, keys, 8);
+
+ /* cut out modifier keys from the keystate */
+ mods = keys[4] >> 4;
+ keys[4] &= 0x0f;
+
+ for (c = 0; c < 8; c++) {
+
+ /* get newly pressed keys only */
+ dk = ((keys[c] ^ old_keys[c])&keys[c]);
+ old_keys[c] = keys[c];
+
+ /* fill the keybuf */
+ for (r = 0; r < 8; r++) {
+ if (dk&1)
+ rx51_kp_fill((c*8)+r, mods);
+ dk = dk >> 1;
+ }
+
+ }
+
+ }
+
+ /* localy unlock twl4030 i2c bus */
+ test_and_clear_bit(0, &twl_i2c_lock);
+
+ return (KEYBUF_SIZE + keybuf_tail - keybuf_head)%KEYBUF_SIZE;
+}
+
+/*
+ * Routine: rx51_kp_getc
+ * Description: Get last pressed key (from buffer).
+ */
+int rx51_kp_getc(struct stdio_dev *sdev)
+{
+ keybuf_head %= KEYBUF_SIZE;
+ while (!rx51_kp_tstc(sdev))
+ WATCHDOG_RESET();
+ return keybuf[keybuf_head++];
+}
+
+/*
+ * Routine: board_mmc_init
+ * Description: Initialize mmc devices.
+ */
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
+ return 0;
+}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+ twl4030_power_mmc_init(1);
+}
diff --git a/board/nokia/rx51/rx51.h b/board/nokia/rx51/rx51.h
new file mode 100644
index 0000000..0d2f0a5
--- /dev/null
+++ b/board/nokia/rx51/rx51.h
@@ -0,0 +1,371 @@
+/*
+ * (C) Copyright 2012
+ * Ивайло Димитров <freemangordon@abv.bg>
+ *
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _RX51_H_
+#define _RX51_H_
+
+/* Needed for ROM SMC call */
+struct emu_hal_params_rx51 {
+ u32 num_params;
+ u32 param1;
+ u32 param2;
+ u32 param3;
+ u32 param4;
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_RX51() \
+/* SDRC */\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+/* GPMC */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*nDMA_REQ2*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*nDMA_REQ3*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+/* DSS */\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+/* CAMERA */\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS*/\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS*/\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+/* Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLK*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+/* Expansion card */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
+/* Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+/* Bluetooth */\
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
+/* Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT*/\
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG*/\
+ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY*/\
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+/* Serial Interface */\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOM*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+/* USB EHCI (port 2) */\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DA2*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DA7*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DA4*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DA5*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DA6*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DA3*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DA0*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DA1*/\
+/* Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*MMC1_WP*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MD*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26m*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespw*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswa*/\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9ni*/\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmare0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmare1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmare2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmare3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrs*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtc*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeu*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlere*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleac*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusfl*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusfl*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+#define MUX_RX51_C() \
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/
+
+#endif
diff --git a/board/nokia/rx51/tag_omap.h b/board/nokia/rx51/tag_omap.h
new file mode 100644
index 0000000..fab7670
--- /dev/null
+++ b/board/nokia/rx51/tag_omap.h
@@ -0,0 +1,295 @@
+/*
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * (C) Copyright 2011
+ * marcel@mesa.nl, Mesa Consulting B.V.
+ *
+ * (C) Copyright 2004-2005
+ * Nokia Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+/*
+ * Code copied from maemo kernel 2.6.28 file
+ * arch/arm/plat-omap/include/mach/board.h
+ *
+ * Information structures for board-specific data
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+
+/* Different peripheral ids */
+#define OMAP_TAG_CLOCK 0x4f01
+#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
+#define OMAP_TAG_USB 0x4f04
+#define OMAP_TAG_LCD 0x4f05
+#define OMAP_TAG_GPIO_SWITCH 0x4f06
+#define OMAP_TAG_UART 0x4f07
+#define OMAP_TAG_FBMEM 0x4f08
+#define OMAP_TAG_STI_CONSOLE 0x4f09
+#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
+#define OMAP_TAG_PARTITION 0x4f0b
+#define OMAP_TAG_TEA5761 0x4f10
+#define OMAP_TAG_TMP105 0x4f11
+
+#define OMAP_TAG_BOOT_REASON 0x4f80
+#define OMAP_TAG_FLASH_PART_STR 0x4f81
+#define OMAP_TAG_VERSION_STR 0x4f82
+
+#define OMAP_TAG_NOKIA_BT 0x4e01
+#define OMAP_TAG_WLAN_CX3110X 0x4e02
+#define OMAP_TAG_CBUS 0x4e03
+#define OMAP_TAG_EM_ASIC_BB5 0x4e04
+
+
+struct omap_clock_config {
+ /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
+ u8 system_clock_type;
+};
+
+struct omap_serial_console_config {
+ u8 console_uart;
+ u32 console_speed;
+};
+
+struct omap_sti_console_config {
+ unsigned enable:1;
+ u8 channel;
+};
+
+struct omap_usb_config {
+ /* Configure drivers according to the connectors on your board:
+ * - "A" connector (rectagular)
+ * ... for host/OHCI use, set "register_host".
+ * - "B" connector (squarish) or "Mini-B"
+ * ... for device/gadget use, set "register_dev".
+ * - "Mini-AB" connector (very similar to Mini-B)
+ * ... for OTG use as device OR host, initialize "otg"
+ */
+ unsigned register_host:1;
+ unsigned register_dev:1;
+ u8 otg; /* port number, 1-based: usb1 == 2 */
+
+ u8 hmc_mode;
+
+ /* implicitly true if otg: host supports remote wakeup? */
+ u8 rwc;
+
+ /* signaling pins used to talk to transceiver on usbN:
+ * 0 == usbN unused
+ * 2 == usb0-only, using internal transceiver
+ * 3 == 3 wire bidirectional
+ * 4 == 4 wire bidirectional
+ * 6 == 6 wire unidirectional (or TLL)
+ */
+ u8 pins[3];
+};
+
+struct omap_lcd_config {
+ char panel_name[16];
+ char ctrl_name[16];
+ s16 nreset_gpio;
+ u8 data_lines;
+};
+
+struct omap_fbmem_config {
+ u32 start;
+ u32 size;
+};
+
+struct omap_gpio_switch_config {
+ char name[12];
+ u16 gpio;
+ u8 flags:4;
+ u8 type:4;
+ unsigned int key_code:24; /* Linux key code */
+};
+
+struct omap_uart_config {
+ /* Bit field of UARTs present; bit 0 --> UART1 */
+ unsigned int enabled_uarts;
+};
+
+struct omap_tea5761_config {
+ u16 enable_gpio;
+};
+
+struct omap_partition_config {
+ char name[16];
+ unsigned int size;
+ unsigned int offset;
+ /* same as in include/linux/mtd/partitions.h */
+ unsigned int mask_flags;
+};
+
+struct omap_flash_part_str_config {
+ char part_table[0];
+};
+
+struct omap_boot_reason_config {
+ char reason_str[12];
+};
+
+struct omap_version_config {
+ char component[12];
+ char version[12];
+};
+
+/*
+ * Code copied from maemo kernel 2.6.28 file
+ * arch/arm/plat-omap/include/mach/board-nokia.h
+ *
+ * Information structures for Nokia-specific board config data
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ */
+
+struct omap_bluetooth_config {
+ u8 chip_type;
+ u8 bt_wakeup_gpio;
+ u8 host_wakeup_gpio;
+ u8 reset_gpio;
+ u8 bt_uart;
+ u8 bd_addr[6];
+ u8 bt_sysclk;
+};
+
+struct omap_wlan_cx3110x_config {
+ u8 chip_type;
+ u8 reserverd;
+ s16 power_gpio;
+ s16 irq_gpio;
+ s16 spi_cs_gpio;
+};
+
+struct omap_cbus_config {
+ s16 clk_gpio;
+ s16 dat_gpio;
+ s16 sel_gpio;
+};
+
+struct omap_em_asic_bb5_config {
+ s16 retu_irq_gpio;
+ s16 tahvo_irq_gpio;
+};
+
+/*
+ * omap_tag handling
+ *
+ * processing omap tag structures
+ *
+ * Copyright (C) 2011 marcel@mesa.nl, Mesa Consulting B.V.
+ * Copyright (C) 2012 Pali Rohár <pali.rohar@gmail.com>
+ */
+
+/* TI OMAP specific information */
+#define ATAG_BOARD 0x414f4d50
+
+struct tag_omap_header {
+ u16 tag;
+ u16 size;
+};
+
+struct tag_omap {
+ struct tag_omap_header hdr;
+ union {
+ struct omap_clock_config clock;
+ struct omap_serial_console_config serial_console;
+ struct omap_sti_console_config sti_console;
+ struct omap_usb_config usb;
+ struct omap_lcd_config lcd;
+ struct omap_fbmem_config fbmem;
+ struct omap_gpio_switch_config gpio_switch;
+ struct omap_uart_config uart;
+ struct omap_tea5761_config tea5761;
+ struct omap_partition_config partition;
+ struct omap_flash_part_str_config flash_part_str;
+ struct omap_boot_reason_config boot_reason;
+ struct omap_version_config version;
+ struct omap_bluetooth_config bluetooth;
+ struct omap_wlan_cx3110x_config wlan_cx3110x;
+ struct omap_cbus_config cbus;
+ struct omap_em_asic_bb5_config em_asic_bb5;
+ } u;
+};
+
+#define tag_omap_next(t) ((struct tag_omap *)((u8 *)(t) + \
+ (t)->hdr.size + sizeof(struct tag_omap_header)))
+
+#define OMAP_TAG_HEADER_CONFIG(config, type) \
+ .hdr.tag = config, \
+ .hdr.size = sizeof(struct type)
+
+#define OMAP_TAG_UART_CONFIG(p1) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_UART, omap_uart_config), \
+ .u.uart.enabled_uarts = p1, \
+ }
+
+#define OMAP_TAG_SERIAL_CONSOLE_CONFIG(p1, p2) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_SERIAL_CONSOLE, \
+ omap_serial_console_config), \
+ .u.serial_console.console_uart = p1, \
+ .u.serial_console.console_speed = p2, \
+ }
+
+#define OMAP_TAG_LCD_CONFIG(p1, p2, p3, p4) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_LCD, omap_lcd_config), \
+ .u.lcd.panel_name = p1, \
+ .u.lcd.ctrl_name = p2, \
+ .u.lcd.nreset_gpio = p3, \
+ .u.lcd.data_lines = p4, \
+ }
+
+#define OMAP_TAG_GPIO_SWITCH_CONFIG(p1, p2, p3, p4, p5) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_GPIO_SWITCH, \
+ omap_gpio_switch_config), \
+ .u.gpio_switch.name = p1, \
+ .u.gpio_switch.gpio = p2, \
+ .u.gpio_switch.flags = p3, \
+ .u.gpio_switch.type = p4, \
+ .u.gpio_switch.key_code = p5, \
+ }
+
+#define OMAP_TAG_WLAN_CX3110X_CONFIG(p1, p2, p3, p4, p5) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_WLAN_CX3110X, \
+ omap_wlan_cx3110x_config), \
+ .u.wlan_cx3110x.chip_type = p1, \
+ .u.wlan_cx3110x.reserverd = p2, \
+ .u.wlan_cx3110x.power_gpio = p3, \
+ .u.wlan_cx3110x.irq_gpio = p4, \
+ .u.wlan_cx3110x.spi_cs_gpio = p5, \
+ }
+
+#define OMAP_TAG_PARTITION_CONFIG(p1, p2, p3, p4) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_PARTITION, \
+ omap_partition_config), \
+ .u.partition.name = p1, \
+ .u.partition.size = p2, \
+ .u.partition.offset = p3, \
+ .u.partition.mask_flags = p4, \
+ }
+
+#define OMAP_TAG_BOOT_REASON_CONFIG(p1) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_BOOT_REASON, \
+ omap_boot_reason_config), \
+ .u.boot_reason.reason_str = p1, \
+ }
+
+#define OMAP_TAG_VERSION_STR_CONFIG(p1, p2) \
+ { \
+ OMAP_TAG_HEADER_CONFIG(OMAP_TAG_VERSION_STR, \
+ omap_version_config), \
+ .u.version.component = p1, \
+ .u.version.version = p2, \
+ }
diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/beaver/Kconfig
new file mode 100644
index 0000000..23f7c94
--- /dev/null
+++ b/board/nvidia/beaver/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BEAVER
+
+config SYS_BOARD
+ default "beaver"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "beaver"
+
+endif
diff --git a/board/nvidia/beaver/MAINTAINERS b/board/nvidia/beaver/MAINTAINERS
new file mode 100644
index 0000000..26bcacc
--- /dev/null
+++ b/board/nvidia/beaver/MAINTAINERS
@@ -0,0 +1,7 @@
+BEAVER BOARD
+M: Tom Warren <twarren@nvidia.com>
+M: Stephen Warren <swarren@nvidia.com>
+S: Maintained
+F: board/nvidia/beaver/
+F: include/configs/beaver.h
+F: configs/beaver_defconfig
diff --git a/board/nvidia/beaver/Makefile b/board/nvidia/beaver/Makefile
new file mode 100644
index 0000000..1f7c31d
--- /dev/null
+++ b/board/nvidia/beaver/Makefile
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+obj-y = ../cardhu/cardhu.o
diff --git a/board/nvidia/cardhu/Kconfig b/board/nvidia/cardhu/Kconfig
new file mode 100644
index 0000000..63ace66
--- /dev/null
+++ b/board/nvidia/cardhu/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CARDHU
+
+config SYS_BOARD
+ default "cardhu"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "cardhu"
+
+endif
diff --git a/board/nvidia/cardhu/MAINTAINERS b/board/nvidia/cardhu/MAINTAINERS
new file mode 100644
index 0000000..d3c3e36
--- /dev/null
+++ b/board/nvidia/cardhu/MAINTAINERS
@@ -0,0 +1,6 @@
+CARDHU BOARD
+M: Tom Warren <twarren@nvidia.com>
+S: Maintained
+F: board/nvidia/cardhu/
+F: include/configs/cardhu.h
+F: configs/cardhu_defconfig
diff --git a/board/nvidia/cardhu/Makefile b/board/nvidia/cardhu/Makefile
new file mode 100644
index 0000000..3f9b55f
--- /dev/null
+++ b/board/nvidia/cardhu/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := cardhu.o
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
new file mode 100644
index 0000000..95c4ff2
--- /dev/null
+++ b/board/nvidia/cardhu/cardhu.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include "pinmux-config-cardhu.h"
+#include <i2c.h>
+#include <netdev.h>
+
+#define PMU_I2C_ADDRESS 0x2D
+#define MAX_I2C_RETRY 3
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_config_pingrp_table(tegra3_pinmux_common,
+ ARRAY_SIZE(tegra3_pinmux_common));
+
+ pinmux_config_pingrp_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
+
+ /* Initialize any non-default pad configs (APB_MISC_GP regs) */
+ pinmux_config_drvgrp_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
+}
+
+#if defined(CONFIG_TEGRA_MMC)
+/*
+ * Do I2C/PMU writes to bring up SD card bus power
+ *
+ */
+void board_sdmmc_voltage_init(void)
+{
+ struct udevice *dev;
+ uchar reg, data_buffer[1];
+ int ret;
+ int i;
+
+ ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
+ if (ret) {
+ debug("%s: Cannot find PMIC I2C chip\n", __func__);
+ return;
+ }
+
+ /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */
+ data_buffer[0] = 0x65;
+ reg = 0x32;
+
+ for (i = 0; i < MAX_I2C_RETRY; ++i) {
+ if (i2c_write(dev, reg, data_buffer, 1))
+ udelay(100);
+ }
+
+ /* TPS659110: GPIO7_REG = PDEN, output a 1 to EN_3V3_SYS */
+ data_buffer[0] = 0x09;
+ reg = 0x67;
+
+ for (i = 0; i < MAX_I2C_RETRY; ++i) {
+ if (i2c_write(dev, reg, data_buffer, 1))
+ udelay(100);
+ }
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+ /*
+ * NOTE: We don't do mmc-specific pin muxes here.
+ * They were done globally in pinmux_init().
+ */
+
+ /* Bring up the SDIO1 power rail */
+ board_sdmmc_voltage_init();
+}
+#endif /* MMC */
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+ struct udevice *dev;
+ u8 addr, data[1];
+ int err;
+
+ err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
+ if (err) {
+ debug("failed to find PMU bus\n");
+ return err;
+ }
+
+ /* TPS659110: LDO1_REG = 1.05V, ACTIVE */
+ data[0] = 0x15;
+ addr = 0x30;
+
+ err = i2c_write(dev, addr, data, 1);
+ if (err) {
+ debug("failed to set VDD supply\n");
+ return err;
+ }
+
+ /* GPIO: PEX = 3.3V */
+ err = gpio_request(GPIO_PL7, "PEX");
+ if (err < 0)
+ return err;
+
+ gpio_direction_output(GPIO_PL7, 1);
+
+ /* TPS659110: LDO2_REG = 1.05V, ACTIVE */
+ data[0] = 0x15;
+ addr = 0x31;
+
+ err = i2c_write(dev, addr, data, 1);
+ if (err) {
+ debug("failed to set AVDD supply\n");
+ return err;
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+#endif /* PCI */
diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h
new file mode 100644
index 0000000..255e4cd
--- /dev/null
+++ b/board/nvidia/cardhu/pinmux-config-cardhu.h
@@ -0,0 +1,346 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PINMUX_CONFIG_CARDHU_H_
+#define _PINMUX_CONFIG_CARDHU_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static struct pmux_pingrp_config tegra3_pinmux_common[] = {
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux */
+ LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* I2C1 pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C2 pinmux */
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C3 pinmux */
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C4 pinmux */
+ I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* Power I2C pinmux */
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
+ LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
+ DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
+ DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
+ DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
+
+ /* KBC keys */
+ DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
+
+ /* GPIOs */
+ /* SDMMC1 CD gpio */
+ DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
+ /* SDMMC1 WP gpio */
+ LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* Touch panel GPIO */
+ /* Touch IRQ */
+ DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
+
+ /* Touch RESET */
+ DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
+
+ /* Power rails GPIO */
+ DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
+
+ LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+};
+
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+ DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+static struct pmux_drvgrp_config cardhu_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+ DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+ SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif /* _PINMUX_CONFIG_CARDHU_H_ */
diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile
new file mode 100644
index 0000000..e3b2651
--- /dev/null
+++ b/board/nvidia/common/Makefile
@@ -0,0 +1,4 @@
+# Copyright (c) 2011 The Chromium OS Authors.
+# SPDX-License-Identifier: GPL-2.0+
+
+include $(src)/common.mk
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
new file mode 100644
index 0000000..80ef8fd
--- /dev/null
+++ b/board/nvidia/common/board.c
@@ -0,0 +1,232 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#ifdef CONFIG_LCD
+#include <asm/arch/display.h>
+#endif
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/pmu.h>
+#ifdef CONFIG_PWM_TEGRA
+#include <asm/arch/pwm.h>
+#endif
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch-tegra/uart.h>
+#include <asm/arch-tegra/warmboot.h>
+#ifdef CONFIG_TEGRA_CLOCK_SCALING
+#include <asm/arch/emc.h>
+#endif
+#ifdef CONFIG_USB_EHCI_TEGRA
+#include <asm/arch-tegra/usb.h>
+#include <usb.h>
+#endif
+#ifdef CONFIG_TEGRA_MMC
+#include <asm/arch-tegra/tegra_mmc.h>
+#include <asm/arch-tegra/mmc.h>
+#endif
+#include <asm/arch-tegra/xusb-padctl.h>
+#include <i2c.h>
+#include <spi.h>
+#include "emc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
+U_BOOT_DEVICE(tegra_gpios) = {
+ "gpio_tegra"
+};
+#endif
+
+const struct tegra_sysinfo sysinfo = {
+ CONFIG_TEGRA_BOARD_STRING
+};
+
+__weak void pinmux_init(void) {}
+__weak void pin_mux_usb(void) {}
+__weak void pin_mux_spi(void) {}
+__weak void gpio_early_init_uart(void) {}
+__weak void pin_mux_display(void) {}
+
+#if defined(CONFIG_TEGRA_NAND)
+__weak void pin_mux_nand(void)
+{
+ funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
+}
+#endif
+
+/*
+ * Routine: power_det_init
+ * Description: turn off power detects
+ */
+static void power_det_init(void)
+{
+#if defined(CONFIG_TEGRA20)
+ struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ /* turn off power detects */
+ writel(0, &pmc->pmc_pwr_det_latch);
+ writel(0, &pmc->pmc_pwr_det);
+#endif
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ __maybe_unused int err;
+
+ /* Do clocks and UART first so that printf() works */
+ clock_init();
+ clock_verify();
+
+#ifdef CONFIG_TEGRA_SPI
+ pin_mux_spi();
+#endif
+
+#ifdef CONFIG_PWM_TEGRA
+ if (pwm_init(gd->fdt_blob))
+ debug("%s: Failed to init pwm\n", __func__);
+#endif
+#ifdef CONFIG_LCD
+ pin_mux_display();
+ tegra_lcd_check_next_stage(gd->fdt_blob, 0);
+#endif
+ /* boot param addr */
+ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
+
+ power_det_init();
+
+#ifdef CONFIG_SYS_I2C_TEGRA
+# ifdef CONFIG_TEGRA_PMU
+ if (pmu_set_nominal())
+ debug("Failed to select nominal voltages\n");
+# ifdef CONFIG_TEGRA_CLOCK_SCALING
+ err = board_emc_init();
+ if (err)
+ debug("Memory controller init failed: %d\n", err);
+# endif
+# endif /* CONFIG_TEGRA_PMU */
+#endif /* CONFIG_SYS_I2C_TEGRA */
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+ pin_mux_usb();
+ usb_process_devicetree(gd->fdt_blob);
+#endif
+
+#ifdef CONFIG_LCD
+ tegra_lcd_check_next_stage(gd->fdt_blob, 0);
+#endif
+
+#ifdef CONFIG_TEGRA_NAND
+ pin_mux_nand();
+#endif
+
+ tegra_xusb_padctl_init(gd->fdt_blob);
+
+#ifdef CONFIG_TEGRA_LP0
+ /* save Sdram params to PMC 2, 4, and 24 for WB0 */
+ warmboot_save_sdram_params();
+
+ /* prepare the WB code to LP0 location */
+ warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+static void __gpio_early_init(void)
+{
+}
+
+void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
+
+int board_early_init_f(void)
+{
+ pinmux_init();
+ board_init_uart_f();
+
+ /* Initialize periph GPIOs */
+ gpio_early_init();
+ gpio_early_init_uart();
+#ifdef CONFIG_LCD
+ tegra_lcd_early_init(gd->fdt_blob);
+#endif
+
+ return 0;
+}
+#endif /* EARLY_INIT */
+
+int board_late_init(void)
+{
+#ifdef CONFIG_LCD
+ /* Make sure we finish initing the LCD */
+ tegra_lcd_check_next_stage(gd->fdt_blob, 1);
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_TEGRA_MMC)
+__weak void pin_mux_mmc(void)
+{
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+ debug("%s called\n", __func__);
+
+ /* Enable muxes, etc. for SDMMC controllers */
+ pin_mux_mmc();
+
+ debug("%s: init MMC\n", __func__);
+ tegra_mmc_init();
+
+ return 0;
+}
+
+void pad_init_mmc(struct mmc_host *host)
+{
+#if defined(CONFIG_TEGRA30)
+ enum periph_id id = host->mmc_id;
+ u32 val;
+
+ debug("%s: sdmmc address = %08x, id = %d\n", __func__,
+ (unsigned int)host->reg, id);
+
+ /* Set the pad drive strength for SDMMC1 or 3 only */
+ if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
+ debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
+ __func__);
+ return;
+ }
+
+ val = readl(&host->reg->sdmemcmppadctl);
+ val &= 0xFFFFFFF0;
+ val |= MEMCOMP_PADCTRL_VREF;
+ writel(val, &host->reg->sdmemcmppadctl);
+
+ val = readl(&host->reg->autocalcfg);
+ val &= 0xFFFF0000;
+ val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
+ writel(val, &host->reg->autocalcfg);
+#endif /* T30 */
+}
+#endif /* MMC */
diff --git a/board/nvidia/common/common.mk b/board/nvidia/common/common.mk
new file mode 100644
index 0000000..9a9b529
--- /dev/null
+++ b/board/nvidia/common/common.mk
@@ -0,0 +1,3 @@
+# common options for all tegra boards
+obj-y += ../../nvidia/common/board.o
+obj-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o
diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c
new file mode 100644
index 0000000..8c62f36
--- /dev/null
+++ b/board/nvidia/common/emc.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "emc.h"
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/emc.h>
+#include <asm/arch/pmu.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* These rates are hard-coded for now, until fdt provides them */
+#define EMC_SDRAM_RATE_T20 (333000 * 2 * 1000)
+#define EMC_SDRAM_RATE_T25 (380000 * 2 * 1000)
+
+int board_emc_init(void)
+{
+ unsigned rate;
+
+ switch (tegra_get_chip_sku()) {
+ default:
+ case TEGRA_SOC_T20:
+ rate = EMC_SDRAM_RATE_T20;
+ break;
+ case TEGRA_SOC_T25:
+ rate = EMC_SDRAM_RATE_T25;
+ break;
+ }
+ return tegra_set_emc(gd->fdt_blob, rate);
+}
diff --git a/board/nvidia/common/emc.h b/board/nvidia/common/emc.h
new file mode 100644
index 0000000..4095235
--- /dev/null
+++ b/board/nvidia/common/emc.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _NVIDIA_EMC_H_
+#define _NVIDIA_EMC_H_
+
+int board_emc_init(void);
+
+#endif
diff --git a/board/nvidia/dalmore/Kconfig b/board/nvidia/dalmore/Kconfig
new file mode 100644
index 0000000..96eaa01
--- /dev/null
+++ b/board/nvidia/dalmore/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DALMORE
+
+config SYS_BOARD
+ default "dalmore"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "dalmore"
+
+endif
diff --git a/board/nvidia/dalmore/MAINTAINERS b/board/nvidia/dalmore/MAINTAINERS
new file mode 100644
index 0000000..fe86375
--- /dev/null
+++ b/board/nvidia/dalmore/MAINTAINERS
@@ -0,0 +1,6 @@
+DALMORE BOARD
+M: Tom Warren <twarren@nvidia.com>
+S: Maintained
+F: board/nvidia/dalmore/
+F: include/configs/dalmore.h
+F: configs/dalmore_defconfig
diff --git a/board/nvidia/dalmore/Makefile b/board/nvidia/dalmore/Makefile
new file mode 100644
index 0000000..7cdff9c
--- /dev/null
+++ b/board/nvidia/dalmore/Makefile
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+obj-y := dalmore.o
diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c
new file mode 100644
index 0000000..2a73746
--- /dev/null
+++ b/board/nvidia/dalmore/dalmore.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include "pinmux-config-dalmore.h"
+#include <i2c.h>
+
+#define BAT_I2C_ADDRESS 0x48 /* TPS65090 charger */
+#define PMU_I2C_ADDRESS 0x58 /* TPS65913 PMU */
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_config_pingrp_table(tegra114_pinmux_set_nontristate,
+ ARRAY_SIZE(tegra114_pinmux_set_nontristate));
+
+ pinmux_config_pingrp_table(tegra114_pinmux_common,
+ ARRAY_SIZE(tegra114_pinmux_common));
+
+ pinmux_config_pingrp_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
+
+ /* Initialize any non-default pad configs (APB_MISC_GP regs) */
+ pinmux_config_drvgrp_table(dalmore_padctrl,
+ ARRAY_SIZE(dalmore_padctrl));
+}
+
+#if defined(CONFIG_TEGRA_MMC)
+/*
+ * Do I2C/PMU writes to bring up SD card bus power
+ *
+ */
+void board_sdmmc_voltage_init(void)
+{
+ struct udevice *dev;
+ uchar reg, data_buffer[1];
+ int ret;
+
+ ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
+ if (ret) {
+ debug("%s: Cannot find PMIC I2C chip\n", __func__);
+ return;
+ }
+
+ /* TPS65913: LDO9_VOLTAGE = 3.3V */
+ data_buffer[0] = 0x31;
+ reg = 0x61;
+
+ ret = i2c_write(dev, reg, data_buffer, 1);
+ if (ret)
+ printf("%s: PMU i2c_write %02X<-%02X returned %d\n",
+ __func__, reg, data_buffer[0], ret);
+
+ /* TPS65913: LDO9_CTRL = Active */
+ data_buffer[0] = 0x01;
+ reg = 0x60;
+
+ ret = i2c_write(dev, reg, data_buffer, 1);
+ if (ret)
+ printf("%s: PMU i2c_write %02X<-%02X returned %d\n",
+ __func__, reg, data_buffer[0], ret);
+
+ /* TPS65090: FET6_CTRL = enable output auto discharge, enable FET6 */
+ data_buffer[0] = 0x03;
+ reg = 0x14;
+
+ ret = i2c_get_chip_for_busnum(0, BAT_I2C_ADDRESS, &dev);
+ if (ret) {
+ debug("%s: Cannot find charger I2C chip\n", __func__);
+ return;
+ }
+ ret = i2c_write(dev, reg, data_buffer, 1);
+ if (ret)
+ printf("%s: BAT i2c_write %02X<-%02X returned %d\n",
+ __func__, reg, data_buffer[0], ret);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+ /*
+ * NOTE: We don't do mmc-specific pin muxes here.
+ * They were done globally in pinmux_init().
+ */
+
+ /* Bring up the SDIO3 power rail */
+ board_sdmmc_voltage_init();
+}
+#endif /* MMC */
diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h
new file mode 100644
index 0000000..891ac07
--- /dev/null
+++ b/board/nvidia/dalmore/pinmux-config-dalmore.h
@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PINMUX_CONFIG_DALMORE_H_
+#define _PINMUX_CONFIG_DALMORE_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define USB_PINMUX CEC_PINMUX
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static struct pmux_pingrp_config tegra114_pinmux_common[] = {
+ /* EXTPERIPH1 pinmux */
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
+
+ /* I2S0 pinmux */
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
+
+ /* I2S1 pinmux */
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
+
+ /* I2S3 pinmux */
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
+
+ /* CLDVFS pinmux */
+ DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT),
+
+ /* ULPI pinmux */
+ DEFAULT_PINMUX(ULPI_CLK_PY0, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, ULPI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, ULPI, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, ULPI, NORMAL, NORMAL, OUTPUT),
+
+ /* I2C3 pinmux */
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+ /* VI pinmux */
+ VI_PINMUX(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+ /* VI_ALT1 pinmux */
+ VI_PINMUX(PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+ /* VGP4 pinmux */
+ VI_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+ /* I2C2 pinmux */
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+ /* UARTD pinmux */
+ DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
+
+ /* SPI4 pinmux */
+ DEFAULT_PINMUX(GMI_AD5_PG5, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, SPI4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, SPI4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS6_N_PI3, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, SPI4, NORMAL, NORMAL, INPUT),
+
+ /* PWM1 pinmux */
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+
+ /* SOC pinmux */
+ DEFAULT_PINMUX(GMI_CS1_N_PJ2, SOC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, SOC, NORMAL, TRISTATE, INPUT),
+
+ /* EXTPERIPH2 pinmux */
+ DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT),
+
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux */
+ DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT),
+
+ /* BLINK pinmux */
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
+
+ /* KBC pinmux */
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
+
+ /*Audio Codec*/
+ DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT),
+
+ /* UARTA pinmux */
+ DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, NORMAL, NORMAL, OUTPUT),
+
+ /* I2CPWR pinmux (I2C5) */
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+ /* SYSCLK pinmux */
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
+
+ /* RTCK pinmux */
+ DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
+
+ /* CLK pinmux */
+ DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT),
+
+ /* PWRON pinmux */
+ DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT),
+
+ /* CPU pinmux */
+ DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT),
+
+ /* PMI pinmux */
+ DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT),
+
+ /* RESET_OUT_N pinmux */
+ DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT),
+
+ /* EXTPERIPH3 pinmux */
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+
+ /* I2C1 pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+ /* UARTB pinmux */
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
+
+ /* IRDA pinmux */
+ DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT),
+
+ /* UARTC pinmux */
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+
+ /* OWR pinmux */
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+
+ /* CEC pinmux */
+ CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+ /* I2C4 pinmux */
+ DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+ DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+
+ /* USB pinmux */
+ USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+ /* nct */
+ DEFAULT_PINMUX(GPIO_X6_AUD_PX6, SPI6, UP, TRISTATE, INPUT),
+};
+
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(USB_VBUS_EN1_PN5, RSVD3, DOWN, TRISTATE, OUTPUT),
+};
+
+/* Initially setting all used GPIO's to non-TRISTATE */
+static struct pmux_pingrp_config tegra114_pinmux_set_nontristate[] = {
+ DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X6_AUD_PX6, RSVD3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X1_AUD_PX1, RSVD3, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(PBB3, RSVD3, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB5, RSVD3, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB6, RSVD3, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB7, RSVD3, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PCC1, RSVD3, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC2, RSVD3, DOWN, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(GMI_AD0_PG0, GMI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, GMI, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD10_PH2, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD12_PH4, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD8_PH0, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, GMI, DOWN, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS0_N_PJ0, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, GMI, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS4_N_PK2, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_DQS_P_PJ3, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_IORDY_PI5, GMI, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SDMMC1_WP_N_PV3, SPI4, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, DOWN, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SPDIF_IN_PK6, USB, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT),
+};
+
+static struct pmux_drvgrp_config dalmore_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+ DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+ SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
+};
+#endif /* PINMUX_CONFIG_COMMON_H */
diff --git a/board/nvidia/harmony/Kconfig b/board/nvidia/harmony/Kconfig
new file mode 100644
index 0000000..328c946
--- /dev/null
+++ b/board/nvidia/harmony/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_HARMONY
+
+config SYS_BOARD
+ default "harmony"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "harmony"
+
+endif
diff --git a/board/nvidia/harmony/MAINTAINERS b/board/nvidia/harmony/MAINTAINERS
new file mode 100644
index 0000000..f3508ed
--- /dev/null
+++ b/board/nvidia/harmony/MAINTAINERS
@@ -0,0 +1,6 @@
+HARMONY BOARD
+M: Tom Warren <twarren@nvidia.com>
+S: Maintained
+F: board/nvidia/harmony/
+F: include/configs/harmony.h
+F: configs/harmony_defconfig
diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile
new file mode 100644
index 0000000..222b025
--- /dev/null
+++ b/board/nvidia/harmony/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := harmony.o
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
new file mode 100644
index 0000000..c892a25
--- /dev/null
+++ b/board/nvidia/harmony/harmony.c
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/gpio.h>
+
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
+ funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT);
+
+ /* For power GPIO PI6 */
+ pinmux_tristate_disable(PMUX_PINGRP_ATA);
+ /* For CD GPIO PH2 */
+ pinmux_tristate_disable(PMUX_PINGRP_ATD);
+
+ /* For power GPIO PT3 */
+ pinmux_tristate_disable(PMUX_PINGRP_DTB);
+ /* For CD GPIO PI5 */
+ pinmux_tristate_disable(PMUX_PINGRP_ATC);
+}
+#endif
+
+void pin_mux_usb(void)
+{
+ funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+ pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+ pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+ /* USB2 PHY reset GPIO */
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
+}
+
+void pin_mux_display(void)
+{
+ pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
+ pinmux_tristate_disable(PMUX_PINGRP_SDC);
+}
diff --git a/board/nvidia/jetson-tk1/Kconfig b/board/nvidia/jetson-tk1/Kconfig
new file mode 100644
index 0000000..d90a74e
--- /dev/null
+++ b/board/nvidia/jetson-tk1/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_JETSON_TK1
+
+config SYS_BOARD
+ default "jetson-tk1"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "jetson-tk1"
+
+endif
diff --git a/board/nvidia/jetson-tk1/MAINTAINERS b/board/nvidia/jetson-tk1/MAINTAINERS
new file mode 100644
index 0000000..a5c687d
--- /dev/null
+++ b/board/nvidia/jetson-tk1/MAINTAINERS
@@ -0,0 +1,6 @@
+JETSON-TK1 BOARD
+M: Stephen Warren <swarren@nvidia.com>
+S: Maintained
+F: board/nvidia/jetson-tk1/
+F: include/configs/jetson-tk1.h
+F: configs/jetson-tk1_defconfig
diff --git a/board/nvidia/jetson-tk1/Makefile b/board/nvidia/jetson-tk1/Makefile
new file mode 100644
index 0000000..0f05411
--- /dev/null
+++ b/board/nvidia/jetson-tk1/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ../venice2/as3722_init.o
+obj-y += jetson-tk1.o
diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c
new file mode 100644
index 0000000..daa74a4
--- /dev/null
+++ b/board/nvidia/jetson-tk1/jetson-tk1.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <power/as3722.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+
+#include "pinmux-config-jetson-tk1.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_set_tristate_input_clamping();
+
+ gpio_config_table(jetson_tk1_gpio_inits,
+ ARRAY_SIZE(jetson_tk1_gpio_inits));
+
+ pinmux_config_pingrp_table(jetson_tk1_pingrps,
+ ARRAY_SIZE(jetson_tk1_pingrps));
+
+ pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
+ ARRAY_SIZE(jetson_tk1_drvgrps));
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+ struct udevice *pmic;
+ int err;
+
+ err = as3722_init(&pmic);
+ if (err) {
+ error("failed to initialize AS3722 PMIC: %d\n", err);
+ return err;
+ }
+
+ err = as3722_sd_enable(pmic, 4);
+ if (err < 0) {
+ error("failed to enable SD4: %d\n", err);
+ return err;
+ }
+
+ err = as3722_sd_set_voltage(pmic, 4, 0x24);
+ if (err < 0) {
+ error("failed to set SD4 voltage: %d\n", err);
+ return err;
+ }
+
+ err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH |
+ AS3722_GPIO_INVERT);
+ if (err < 0) {
+ error("failed to configure GPIO#1 as output: %d\n", err);
+ return err;
+ }
+
+ err = as3722_gpio_direction_output(pmic, 2, 1);
+ if (err < 0) {
+ error("failed to set GPIO#2 high: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+#endif /* PCI */
diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
new file mode 100644
index 0000000..de4eb35
--- /dev/null
+++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
@@ -0,0 +1,324 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_JETSON_TK1_H_
+#define _PINMUX_CONFIG_JETSON_TK1_H_
+
+#define GPIO_INIT(_gpio, _init) \
+ { \
+ .gpio = GPIO_P##_gpio, \
+ .init = TEGRA_GPIO_INIT_##_init, \
+ }
+
+static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
+ /* gpio, init_val */
+ GPIO_INIT(C7, IN),
+ GPIO_INIT(G0, OUT0),
+ GPIO_INIT(G1, OUT0),
+ GPIO_INIT(G2, IN),
+ GPIO_INIT(G3, IN),
+ GPIO_INIT(H2, OUT0),
+ GPIO_INIT(H3, OUT0),
+ GPIO_INIT(H4, IN),
+ GPIO_INIT(H5, OUT0),
+ GPIO_INIT(H6, IN),
+ GPIO_INIT(H7, OUT0),
+ GPIO_INIT(I0, OUT0),
+ GPIO_INIT(I2, OUT0),
+ GPIO_INIT(I4, OUT0),
+ GPIO_INIT(I5, IN),
+ GPIO_INIT(I6, IN),
+ GPIO_INIT(J0, IN),
+ GPIO_INIT(J2, IN),
+ GPIO_INIT(K1, OUT0),
+ GPIO_INIT(K2, IN),
+ GPIO_INIT(K3, IN),
+ GPIO_INIT(K4, OUT0),
+ GPIO_INIT(K5, OUT0),
+ GPIO_INIT(K6, OUT0),
+ GPIO_INIT(N7, IN),
+ GPIO_INIT(O0, IN),
+ GPIO_INIT(O1, IN),
+ GPIO_INIT(O2, IN),
+ GPIO_INIT(O3, IN),
+ GPIO_INIT(O4, IN),
+ GPIO_INIT(O5, IN),
+ GPIO_INIT(O6, OUT0),
+ GPIO_INIT(O7, IN),
+ GPIO_INIT(P0, OUT0),
+ GPIO_INIT(P1, OUT0),
+ GPIO_INIT(P2, OUT0),
+ GPIO_INIT(Q0, IN),
+ GPIO_INIT(Q1, IN),
+ GPIO_INIT(Q2, IN),
+ GPIO_INIT(Q5, IN),
+ GPIO_INIT(Q6, IN),
+ GPIO_INIT(Q7, IN),
+ GPIO_INIT(R0, OUT0),
+ GPIO_INIT(R1, OUT0),
+ GPIO_INIT(R2, OUT0),
+ GPIO_INIT(R4, IN),
+ GPIO_INIT(R5, OUT0),
+ GPIO_INIT(R7, IN),
+ GPIO_INIT(S0, IN),
+ GPIO_INIT(S3, OUT0),
+ GPIO_INIT(S4, OUT0),
+ GPIO_INIT(S5, IN),
+ GPIO_INIT(S6, OUT0),
+ GPIO_INIT(T0, OUT0),
+ GPIO_INIT(T1, OUT0),
+ GPIO_INIT(U0, OUT0),
+ GPIO_INIT(U1, IN),
+ GPIO_INIT(U2, IN),
+ GPIO_INIT(U3, OUT0),
+ GPIO_INIT(U4, OUT0),
+ GPIO_INIT(U5, IN),
+ GPIO_INIT(U6, IN),
+ GPIO_INIT(V0, IN),
+ GPIO_INIT(V1, IN),
+ GPIO_INIT(W2, IN),
+ GPIO_INIT(W3, IN),
+ GPIO_INIT(X1, OUT0),
+ GPIO_INIT(X3, IN),
+ GPIO_INIT(X4, OUT0),
+ GPIO_INIT(X5, IN),
+ GPIO_INIT(X6, IN),
+ GPIO_INIT(X7, OUT0),
+ GPIO_INIT(BB3, OUT0),
+ GPIO_INIT(BB5, OUT0),
+ GPIO_INIT(BB6, OUT0),
+ GPIO_INIT(BB7, OUT0),
+ GPIO_INIT(CC1, IN),
+ GPIO_INIT(CC2, IN),
+ GPIO_INIT(CC5, OUT0),
+ GPIO_INIT(EE1, OUT0),
+ GPIO_INIT(FF1, OUT0),
+ GPIO_INIT(FF2, IN),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .od = PMUX_PIN_OD_##_od, \
+ .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
+ /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
+ PINCFG(CLK_32K_OUT_PA0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_CTS_N_PA1, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PB0, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PB1, UARTD, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PC7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG3, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_OUT_PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(ULPI_DATA7_PO0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA0_PO1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA1_PO2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA2_PO3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA3_PO4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA6_PO7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_FS_PP0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DIN_PP1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL0_PQ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL1_PQ1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL5_PQ5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW4_PR4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW5_PR5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW7_PR7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW8_PS0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW13_PS5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW14_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(GPIO_W2_AUD_PW2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_W3_AUD_PW3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X3_AUD_PX3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X5_AUD_PX5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X6_AUD_PX6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_RST_N_PDD1, PE0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_CLKREQ_N_PDD2, PE0, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_WAKE_N_PDD3, PE, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_RST_N_PDD5, PE1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_CLKREQ_N_PDD6, PE1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN2_PFF1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PFF2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
+ PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
+ PINCFG(CLK_32K_IN, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_JETSON_TK1_H */
diff --git a/board/nvidia/nyan-big/Kconfig b/board/nvidia/nyan-big/Kconfig
new file mode 100644
index 0000000..341c8d7
--- /dev/null
+++ b/board/nvidia/nyan-big/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NYAN_BIG
+
+config SYS_BOARD
+ default "nyan-big"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "nyan-big"
+
+endif
diff --git a/board/nvidia/nyan-big/MAINTAINERS b/board/nvidia/nyan-big/MAINTAINERS
new file mode 100644
index 0000000..ff74627
--- /dev/null
+++ b/board/nvidia/nyan-big/MAINTAINERS
@@ -0,0 +1,6 @@
+NORRIN BOARD
+M: Allen Martin <amartin@nvidia.com>
+S: Maintained
+F: board/nvidia/nyan-big/
+F: include/configs/nyan-big.h
+F: configs/nyan-big_defconfig
diff --git a/board/nvidia/nyan-big/Makefile b/board/nvidia/nyan-big/Makefile
new file mode 100644
index 0000000..cd2f61d
--- /dev/null
+++ b/board/nvidia/nyan-big/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ../venice2/as3722_init.o
+obj-y += nyan-big.o
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c
new file mode 100644
index 0000000..d4d2496
--- /dev/null
+++ b/board/nvidia/nyan-big/nyan-big.c
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-nyan-big.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ gpio_config_table(nyan_big_gpio_inits,
+ ARRAY_SIZE(nyan_big_gpio_inits));
+
+ pinmux_config_pingrp_table(nyan_big_pingrps,
+ ARRAY_SIZE(nyan_big_pingrps));
+
+ pinmux_config_drvgrp_table(nyan_big_drvgrps,
+ ARRAY_SIZE(nyan_big_drvgrps));
+}
diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h
new file mode 100644
index 0000000..9c5fbaa
--- /dev/null
+++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_NYAN_BIG_H_
+#define _PINMUX_CONFIG_NYAN_BIG_H_
+
+#define GPIO_INIT(_gpio, _init) \
+ { \
+ .gpio = GPIO_P##_gpio, \
+ .init = TEGRA_GPIO_INIT_##_init, \
+ }
+
+static const struct tegra_gpio_config nyan_big_gpio_inits[] = {
+ /* gpio, init_val */
+ GPIO_INIT(A0, IN),
+ GPIO_INIT(C7, IN),
+ GPIO_INIT(G0, IN),
+ GPIO_INIT(G1, IN),
+ GPIO_INIT(G2, IN),
+ GPIO_INIT(G3, IN),
+ GPIO_INIT(H2, IN),
+ GPIO_INIT(H4, IN),
+ GPIO_INIT(H6, IN),
+ GPIO_INIT(H7, OUT1),
+ GPIO_INIT(I0, IN),
+ GPIO_INIT(I1, IN),
+ GPIO_INIT(I5, OUT1),
+ GPIO_INIT(I6, IN),
+ GPIO_INIT(I7, IN),
+ GPIO_INIT(J0, IN),
+ GPIO_INIT(J7, IN),
+ GPIO_INIT(K1, OUT0),
+ GPIO_INIT(K2, IN),
+ GPIO_INIT(K4, OUT0),
+ GPIO_INIT(K6, OUT0),
+ GPIO_INIT(K7, IN),
+ GPIO_INIT(N7, IN),
+ GPIO_INIT(P2, OUT0),
+ GPIO_INIT(Q0, IN),
+ GPIO_INIT(Q2, IN),
+ GPIO_INIT(Q3, IN),
+ GPIO_INIT(Q6, IN),
+ GPIO_INIT(Q7, IN),
+ GPIO_INIT(R0, OUT0),
+ GPIO_INIT(R1, IN),
+ GPIO_INIT(R4, IN),
+ GPIO_INIT(R7, IN),
+ GPIO_INIT(S3, OUT0),
+ GPIO_INIT(S4, OUT0),
+ GPIO_INIT(S7, IN),
+ GPIO_INIT(T1, IN),
+ GPIO_INIT(U4, IN),
+ GPIO_INIT(U5, IN),
+ GPIO_INIT(U6, IN),
+ GPIO_INIT(V0, IN),
+ GPIO_INIT(W3, IN),
+ GPIO_INIT(X1, IN),
+ GPIO_INIT(X4, IN),
+ GPIO_INIT(X7, OUT0),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .od = PMUX_PIN_OD_##_od, \
+ .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+static const struct pmux_pingrp_config nyan_big_pingrps[] = {
+ /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
+ PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_TXD_PC2, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_RXD_PC3, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI5, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_CTS_N_PJ5, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_RTS_N_PJ6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_DOUT_PN2, I2S0, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL2_PQ2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL6_PQ6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL7_PQ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CAM_I2C_SCL_PBB1, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CAM_I2C_SDA_PBB2, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK3_OUT_PEE0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
+ PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static const struct pmux_drvgrp_config nyan_big_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_NYAN_BIG_H */
diff --git a/board/nvidia/seaboard/Kconfig b/board/nvidia/seaboard/Kconfig
new file mode 100644
index 0000000..0924bde
--- /dev/null
+++ b/board/nvidia/seaboard/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SEABOARD
+
+config SYS_BOARD
+ default "seaboard"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "seaboard"
+
+endif
diff --git a/board/nvidia/seaboard/MAINTAINERS b/board/nvidia/seaboard/MAINTAINERS
new file mode 100644
index 0000000..7926ca1
--- /dev/null
+++ b/board/nvidia/seaboard/MAINTAINERS
@@ -0,0 +1,6 @@
+SEABOARD BOARD
+M: Tom Warren <twarren@nvidia.com>
+S: Maintained
+F: board/nvidia/seaboard/
+F: include/configs/seaboard.h
+F: configs/seaboard_defconfig
diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile
new file mode 100644
index 0000000..9171418
--- /dev/null
+++ b/board/nvidia/seaboard/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := seaboard.o
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
new file mode 100644
index 0000000..11472eb
--- /dev/null
+++ b/board/nvidia/seaboard/seaboard.c
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/gpio.h>
+
+/* TODO: Remove this code when the SPI switch is working */
+#if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
+void gpio_early_init_uart(void)
+{
+ /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
+#ifndef CONFIG_SPL_BUILD
+ gpio_request(GPIO_PI3, NULL);
+#endif
+ tegra_spl_gpio_direction_output(GPIO_PI3, 0);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
+ funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
+
+ /* For power GPIO PI6 */
+ pinmux_tristate_disable(PMUX_PINGRP_ATA);
+ /* For CD GPIO PI5 */
+ pinmux_tristate_disable(PMUX_PINGRP_ATC);
+}
+#endif
+
+void pin_mux_usb(void)
+{
+ /* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
+ pinmux_tristate_disable(PMUX_PINGRP_SLXK);
+}
diff --git a/board/nvidia/venice2/Kconfig b/board/nvidia/venice2/Kconfig
new file mode 100644
index 0000000..6905f00
--- /dev/null
+++ b/board/nvidia/venice2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VENICE2
+
+config SYS_BOARD
+ default "venice2"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "venice2"
+
+endif
diff --git a/board/nvidia/venice2/MAINTAINERS b/board/nvidia/venice2/MAINTAINERS
new file mode 100644
index 0000000..221df65
--- /dev/null
+++ b/board/nvidia/venice2/MAINTAINERS
@@ -0,0 +1,6 @@
+VENICE2 BOARD
+M: Tom Warren <twarren@nvidia.com>
+S: Maintained
+F: board/nvidia/venice2/
+F: include/configs/venice2.h
+F: configs/venice2_defconfig
diff --git a/board/nvidia/venice2/Makefile b/board/nvidia/venice2/Makefile
new file mode 100644
index 0000000..5fac5ab
--- /dev/null
+++ b/board/nvidia/venice2/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += as3722_init.o
+obj-y += venice2.o
diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c
new file mode 100644
index 0000000..960fea7
--- /dev/null
+++ b/board/nvidia/venice2/as3722_init.c
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "as3722_init.h"
+
+/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(addr, ®->cmd_addr0);
+ writel(config, ®->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(data, ®->cmd_data1);
+ writel(config, ®->cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+ debug("%s entry\n", __func__);
+
+ /* Don't need to set up VDD_CORE - already done - by OTP */
+
+ debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
+ /*
+ * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
+ * First set VDD to 1.0V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ /*
+ * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+ * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
+ */
+ udelay(10 * 1000);
+
+ debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
+ /*
+ * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
+ * First set VDD to 1.0V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ /*
+ * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+ * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
+ */
+ udelay(10 * 1000);
+
+ debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
+ /*
+ * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
+ * First set VDD to 1.2V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ /*
+ * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+ * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
+ */
+ udelay(10 * 1000);
+
+ debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
+ /*
+ * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
+ * First set it to bypass 3.3V straight thru, then enable the regulator
+ *
+ * NOTE: We do this early because doing it later seems to hose the CPU
+ * power rail/partition startup. Need to debug.
+ */
+ tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+ /*
+ * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+ * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
+ */
+ udelay(10 * 1000);
+}
diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h
new file mode 100644
index 0000000..992b11f
--- /dev/null
+++ b/board/nvidia/venice2/as3722_init.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* AS3722-PMIC-specific early init regs */
+
+#define AS3722_I2C_ADDR 0x80
+
+#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
+#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
+#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
+#define AS3722_SDCONTROL_REG 0x4D
+
+#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
+#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
+#define AS3722_LDCONTROL_REG 0x4E
+
+#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_NYAN_BIG)
+#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
+#else
+#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
+#endif
+#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
+#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
+#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
+
+#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
+
+#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
+
+#define I2C_SEND_2_BYTES 0x0A02
+
+void pmic_enable_cpu_vdd(void);
diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h
new file mode 100644
index 0000000..bf8e3fd
--- /dev/null
+++ b/board/nvidia/venice2/pinmux-config-venice2.h
@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_VENICE2_H_
+#define _PINMUX_CONFIG_VENICE2_H_
+
+#define GPIO_INIT(_gpio, _init) \
+ { \
+ .gpio = GPIO_P##_gpio, \
+ .init = TEGRA_GPIO_INIT_##_init, \
+ }
+
+static const struct tegra_gpio_config venice2_gpio_inits[] = {
+ /* gpio, init_val */
+ GPIO_INIT(A0, IN),
+ GPIO_INIT(C7, IN),
+ GPIO_INIT(G0, IN),
+ GPIO_INIT(G1, IN),
+ GPIO_INIT(G2, IN),
+ GPIO_INIT(G3, IN),
+ GPIO_INIT(H2, IN),
+ GPIO_INIT(H4, IN),
+ GPIO_INIT(H5, OUT0),
+ GPIO_INIT(H6, IN),
+ GPIO_INIT(H7, OUT1),
+ GPIO_INIT(I0, IN),
+ GPIO_INIT(I1, IN),
+ GPIO_INIT(I2, OUT0),
+ GPIO_INIT(I4, OUT0),
+ GPIO_INIT(I5, OUT1),
+ GPIO_INIT(I6, IN),
+ GPIO_INIT(J0, IN),
+ GPIO_INIT(J7, IN),
+ GPIO_INIT(K0, IN),
+ GPIO_INIT(K1, OUT0),
+ GPIO_INIT(K2, IN),
+ GPIO_INIT(K3, IN),
+ GPIO_INIT(K4, OUT0),
+ GPIO_INIT(K6, OUT0),
+ GPIO_INIT(K7, IN),
+ GPIO_INIT(N7, IN),
+ GPIO_INIT(O2, IN),
+ GPIO_INIT(O5, IN),
+ GPIO_INIT(O6, OUT0),
+ GPIO_INIT(O7, IN),
+ GPIO_INIT(P2, OUT0),
+ GPIO_INIT(Q0, IN),
+ GPIO_INIT(Q2, IN),
+ GPIO_INIT(Q3, IN),
+ GPIO_INIT(Q6, IN),
+ GPIO_INIT(Q7, IN),
+ GPIO_INIT(R0, OUT0),
+ GPIO_INIT(R1, IN),
+ GPIO_INIT(R4, IN),
+ GPIO_INIT(S0, IN),
+ GPIO_INIT(S3, OUT0),
+ GPIO_INIT(S4, OUT0),
+ GPIO_INIT(S7, IN),
+ GPIO_INIT(T1, IN),
+ GPIO_INIT(U4, IN),
+ GPIO_INIT(U5, IN),
+ GPIO_INIT(U6, IN),
+ GPIO_INIT(V0, IN),
+ GPIO_INIT(V1, IN),
+ GPIO_INIT(W3, IN),
+ GPIO_INIT(X1, IN),
+ GPIO_INIT(X3, IN),
+ GPIO_INIT(X4, IN),
+ GPIO_INIT(X7, OUT0),
+ GPIO_INIT(CC5, OUT0),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .od = PMUX_PIN_OD_##_od, \
+ .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+static const struct pmux_pingrp_config venice2_pingrps[] = {
+ /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
+ PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_RXD_PC3, IRDA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH0, PWM0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA1_PO2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DATA6_PO7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW7_PR7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW8_PS0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU0, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU1, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU3, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PV1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
+ PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X3_AUD_PX3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
+ PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+ PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
+ PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
+ PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static const struct pmux_drvgrp_config venice2_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_VENICE2_H */
diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c
new file mode 100644
index 0000000..c56ef12
--- /dev/null
+++ b/board/nvidia/venice2/venice2.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-venice2.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_set_tristate_input_clamping();
+
+ gpio_config_table(venice2_gpio_inits,
+ ARRAY_SIZE(venice2_gpio_inits));
+
+ pinmux_config_pingrp_table(venice2_pingrps,
+ ARRAY_SIZE(venice2_pingrps));
+
+ pinmux_config_drvgrp_table(venice2_drvgrps,
+ ARRAY_SIZE(venice2_drvgrps));
+}
diff --git a/board/nvidia/ventana/Kconfig b/board/nvidia/ventana/Kconfig
new file mode 100644
index 0000000..c1ad7b7
--- /dev/null
+++ b/board/nvidia/ventana/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VENTANA
+
+config SYS_BOARD
+ default "ventana"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "ventana"
+
+endif
diff --git a/board/nvidia/ventana/MAINTAINERS b/board/nvidia/ventana/MAINTAINERS
new file mode 100644
index 0000000..285b84d
--- /dev/null
+++ b/board/nvidia/ventana/MAINTAINERS
@@ -0,0 +1,7 @@
+VENTANA BOARD
+M: Tom Warren <twarren@nvidia.com>
+M: Stephen Warren <swarren@nvidia.com>
+S: Maintained
+F: board/nvidia/ventana/
+F: include/configs/ventana.h
+F: configs/ventana_defconfig
diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile
new file mode 100644
index 0000000..f67044f
--- /dev/null
+++ b/board/nvidia/ventana/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = ../seaboard/seaboard.o
diff --git a/board/nvidia/whistler/Kconfig b/board/nvidia/whistler/Kconfig
new file mode 100644
index 0000000..5febc07
--- /dev/null
+++ b/board/nvidia/whistler/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_WHISTLER
+
+config SYS_BOARD
+ default "whistler"
+
+config SYS_VENDOR
+ default "nvidia"
+
+config SYS_CONFIG_NAME
+ default "whistler"
+
+endif
diff --git a/board/nvidia/whistler/MAINTAINERS b/board/nvidia/whistler/MAINTAINERS
new file mode 100644
index 0000000..66e2c8d
--- /dev/null
+++ b/board/nvidia/whistler/MAINTAINERS
@@ -0,0 +1,7 @@
+WHISTLER BOARD
+M: Tom Warren <twarren@nvidia.com>
+M: Stephen Warren <swarren@nvidia.com>
+S: Maintained
+F: board/nvidia/whistler/
+F: include/configs/whistler.h
+F: configs/whistler_defconfig
diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile
new file mode 100644
index 0000000..b54c5fd
--- /dev/null
+++ b/board/nvidia/whistler/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := whistler.o
diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c
new file mode 100644
index 0000000..3114b20
--- /dev/null
+++ b/board/nvidia/whistler/whistler.c
@@ -0,0 +1,80 @@
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+ struct udevice *dev;
+ uchar val;
+ int ret;
+
+ /* Turn on MAX8907B LDO12 to 2.8V for J40 power */
+ ret = i2c_get_chip_for_busnum(0, 0x3c, &dev);
+ if (ret) {
+ printf("%s: Cannot find MAX8907B I2C chip\n", __func__);
+ return;
+ }
+ val = 0x29;
+ ret = i2c_write(dev, 0x46, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret);
+ val = 0x00;
+ ret = i2c_write(dev, 0x45, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret);
+ val = 0x1f;
+ ret = i2c_write(dev, 0x44, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret);
+
+ funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT);
+ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT);
+}
+#endif
+
+/* this is a weak define that we are overriding */
+void pin_mux_usb(void)
+{
+ struct udevice *dev;
+ uchar val;
+ int ret;
+
+ /*
+ * This is a hack. This should be represented in DT using the
+ * vbus-gpio property. However, U-Boot's DT support doesn't
+ * support any GPIO controller other than the Tegra's yet.
+ */
+
+ /* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */
+ ret = i2c_get_chip_for_busnum(0, 0x20, &dev);
+ if (ret) {
+ printf("%s: Cannot find TAC6416 I2C chip\n", __func__);
+ return;
+ }
+ val = 0x03;
+ ret = i2c_write(dev, 2, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x20 2 failed: %d\n", ret);
+ val = 0xfc;
+ ret = i2c_write(dev, 6, &val, 1);
+ if (ret)
+ printf("i2c_write 0 0x20 6 failed: %d\n", ret);
+}
diff --git a/board/olimex/mx23_olinuxino/Kconfig b/board/olimex/mx23_olinuxino/Kconfig
new file mode 100644
index 0000000..0b151c9
--- /dev/null
+++ b/board/olimex/mx23_olinuxino/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MX23_OLINUXINO
+
+config SYS_BOARD
+ default "mx23_olinuxino"
+
+config SYS_VENDOR
+ default "olimex"
+
+config SYS_SOC
+ default "mxs"
+
+config SYS_CONFIG_NAME
+ default "mx23_olinuxino"
+
+endif
diff --git a/board/olimex/mx23_olinuxino/MAINTAINERS b/board/olimex/mx23_olinuxino/MAINTAINERS
new file mode 100644
index 0000000..25f4a10
--- /dev/null
+++ b/board/olimex/mx23_olinuxino/MAINTAINERS
@@ -0,0 +1,6 @@
+MX23_OLINUXINO BOARD
+M: Marek Vasut <marek.vasut@gmail.com>
+S: Maintained
+F: board/olimex/mx23_olinuxino/
+F: include/configs/mx23_olinuxino.h
+F: configs/mx23_olinuxino_defconfig
diff --git a/board/olimex/mx23_olinuxino/Makefile b/board/olimex/mx23_olinuxino/Makefile
new file mode 100644
index 0000000..133114c
--- /dev/null
+++ b/board/olimex/mx23_olinuxino/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := mx23_olinuxino.o
+else
+obj-y := spl_boot.o
+endif
diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
new file mode 100644
index 0000000..65cbbf1
--- /dev/null
+++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
@@ -0,0 +1,80 @@
+/*
+ * Olimex MX23 Olinuxino board
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_USB
+int board_ehci_hcd_init(int port)
+{
+ /* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
+ gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1);
+ udelay(100);
+ return 0;
+}
+
+int board_ehci_hcd_exit(int port)
+{
+ /* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
+ gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 0);
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+#ifdef CONFIG_CMD_MMC
+static int mx23_olx_mmc_cd(int id)
+{
+ return 1; /* Card always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ return mxsmmc_initialize(bis, 0, NULL, mx23_olx_mmc_cd);
+}
+#endif
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_STATE);
+#endif
+
+ return 0;
+}
diff --git a/board/olimex/mx23_olinuxino/spl_boot.c b/board/olimex/mx23_olinuxino/spl_boot.c
new file mode 100644
index 0000000..de3b0e4
--- /dev/null
+++ b/board/olimex/mx23_olinuxino/spl_boot.c
@@ -0,0 +1,121 @@
+/*
+ * Olimex MX23 Olinuxino Boot setup
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP (MXS_PAD_8MA | MXS_PAD_PULLUP)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* DUART */
+ MX23_PAD_PWM0__DUART_RX,
+ MX23_PAD_PWM1__DUART_TX,
+
+ /* EMI */
+ MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
+
+ MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+
+ MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+
+ /* Green LED */
+ MX23_PAD_SSP1_DETECT__GPIO_2_1 |
+ (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL),
+
+ /* MMC 0 */
+ MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
+
+ /* Ethernet */
+ MX23_PAD_GPMI_ALE__GPIO_0_17 |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+};
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
+
+/* Fine-tune the DRAM configuration. */
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ /* Enable Auto Precharge. */
+ dram_vals[3] |= 1 << 8;
+ /* Enable Fast Writes. */
+ dram_vals[5] |= 1 << 8;
+ /* tEMRS = 3*tCK */
+ dram_vals[10] &= ~(0x3 << 8);
+ dram_vals[10] |= (0x3 << 8);
+ /* CASLAT = 3*tCK */
+ dram_vals[11] &= ~(0x3 << 0);
+ dram_vals[11] |= (0x3 << 0);
+ /* tCKE = 1*tCK */
+ dram_vals[12] &= ~(0x7 << 0);
+ dram_vals[12] |= (0x1 << 0);
+ /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
+ dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
+ dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
+ /* tDAL = 6*tCK */
+ dram_vals[15] &= ~(0xf << 16);
+ dram_vals[15] |= (0x6 << 16);
+ /* tREF = 1040*tCK */
+ dram_vals[26] &= ~0xffff;
+ dram_vals[26] |= 0x0410;
+ /* tRAS_MAX = 9334*tCK */
+ dram_vals[32] &= ~0xffff;
+ dram_vals[32] |= 0x2475;
+}
diff --git a/board/omicron/calimain/Kconfig b/board/omicron/calimain/Kconfig
new file mode 100644
index 0000000..1ec48e6
--- /dev/null
+++ b/board/omicron/calimain/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CALIMAIN
+
+config SYS_BOARD
+ default "calimain"
+
+config SYS_VENDOR
+ default "omicron"
+
+config SYS_CONFIG_NAME
+ default "calimain"
+
+endif
diff --git a/board/omicron/calimain/MAINTAINERS b/board/omicron/calimain/MAINTAINERS
new file mode 100644
index 0000000..f6e37a2
--- /dev/null
+++ b/board/omicron/calimain/MAINTAINERS
@@ -0,0 +1,7 @@
+CALIMAIN BOARD
+M: Manfred Rudigier <manfred.rudigier@omicron.at>
+M: Christian Riesch <christian.riesch@omicron.at>
+S: Maintained
+F: board/omicron/calimain/
+F: include/configs/calimain.h
+F: configs/calimain_defconfig
diff --git a/board/omicron/calimain/Makefile b/board/omicron/calimain/Makefile
new file mode 100644
index 0000000..59c118d
--- /dev/null
+++ b/board/omicron/calimain/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := calimain.o
diff --git a/board/omicron/calimain/calimain.c b/board/omicron/calimain/calimain.c
new file mode 100644
index 0000000..32f2b20
--- /dev/null
+++ b/board/omicron/calimain/calimain.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2011 OMICRON electronics GmbH
+ *
+ * Based on da850evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <net.h>
+#include <netdev.h>
+#include <watchdog.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/arch/pinmux_defs.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/timer_defs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CALIMAIN_HWVERSION_MASK 0x7f000000
+#define CALIMAIN_HWVERSION_SHIFT 24
+
+/* Hardware version pinmux settings */
+const struct pinmux_config hwversion_pins[] = {
+ { pinmux(16), 8, 2 }, /* GP7[15] */
+ { pinmux(16), 8, 3 }, /* GP7[14] */
+ { pinmux(16), 8, 4 }, /* GP7[13] */
+ { pinmux(16), 8, 5 }, /* GP7[12] */
+ { pinmux(16), 8, 6 }, /* GP7[11] */
+ { pinmux(16), 8, 7 }, /* GP7[10] */
+ { pinmux(17), 8, 0 }, /* GP7[9] */
+ { pinmux(17), 8, 1 } /* GP7[8] */
+};
+
+const struct pinmux_resource pinmuxes[] = {
+ PINMUX_ITEM(uart2_pins_txrx),
+ PINMUX_ITEM(emac_pins_mii),
+ PINMUX_ITEM(emac_pins_mdio),
+ PINMUX_ITEM(emifa_pins_nor),
+ PINMUX_ITEM(emifa_pins_cs2),
+ PINMUX_ITEM(emifa_pins_cs3),
+};
+
+const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
+
+const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
+ { DAVINCI_LPSC_EMAC }, /* image download */
+ { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_GPIO },
+};
+
+const int lpsc_size = ARRAY_SIZE(lpsc);
+
+/* read board revision from GPIO7[8..14] */
+u32 get_board_rev(void)
+{
+ lpsc_on(DAVINCI_LPSC_GPIO);
+ if (davinci_configure_pin_mux(hwversion_pins,
+ ARRAY_SIZE(hwversion_pins)) != 0)
+ return 0xffffffff;
+
+ return (davinci_gpio_bank67->in_data & CALIMAIN_HWVERSION_MASK)
+ >> CALIMAIN_HWVERSION_SHIFT;
+}
+
+/*
+ * determine the oscillator frequency depending on the board revision
+ *
+ * rev 0x00 ... 25 MHz oscillator
+ * rev 0x01 ... 24 MHz oscillator
+ */
+int calimain_get_osc_freq(void)
+{
+ u32 rev;
+ int freq;
+
+ rev = get_board_rev();
+ switch (rev) {
+ case 0x00:
+ freq = 25000000;
+ break;
+ default:
+ freq = 24000000;
+ break;
+ }
+ return freq;
+}
+
+int board_init(void)
+{
+ int val;
+
+#ifndef CONFIG_USE_IRQ
+ irq_init();
+#endif
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+ /* select emac MII mode */
+ val = readl(&davinci_syscfg_regs->cfgchip3);
+ val &= ~(1 << 8);
+ writel(val, &davinci_syscfg_regs->cfgchip3);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+#ifdef CONFIG_HW_WATCHDOG
+ davinci_hw_watchdog_enable();
+#endif
+
+ printf("Input clock frequency: %d Hz\n", calimain_get_osc_freq());
+ printf("Board revision: %d\n", get_board_rev());
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ davinci_hw_watchdog_reset();
+}
+#endif
diff --git a/board/openrisc/openrisc-generic/Kconfig b/board/openrisc/openrisc-generic/Kconfig
new file mode 100644
index 0000000..cd2a94f
--- /dev/null
+++ b/board/openrisc/openrisc-generic/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OPENRISC_GENERIC
+
+config SYS_BOARD
+ default "openrisc-generic"
+
+config SYS_VENDOR
+ default "openrisc"
+
+config SYS_CONFIG_NAME
+ default "openrisc-generic"
+
+endif
diff --git a/board/openrisc/openrisc-generic/MAINTAINERS b/board/openrisc/openrisc-generic/MAINTAINERS
new file mode 100644
index 0000000..c8dbc74
--- /dev/null
+++ b/board/openrisc/openrisc-generic/MAINTAINERS
@@ -0,0 +1,6 @@
+OPENRISC-GENERIC BOARD
+M: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+S: Maintained
+F: board/openrisc/openrisc-generic/
+F: include/configs/openrisc-generic.h
+F: configs/openrisc-generic_defconfig
diff --git a/board/openrisc/openrisc-generic/Makefile b/board/openrisc/openrisc-generic/Makefile
new file mode 100644
index 0000000..342bc80
--- /dev/null
+++ b/board/openrisc/openrisc-generic/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := openrisc-generic.o
diff --git a/board/openrisc/openrisc-generic/config.mk b/board/openrisc/openrisc-generic/config.mk
new file mode 100644
index 0000000..dd6595f
--- /dev/null
+++ b/board/openrisc/openrisc-generic/config.mk
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2011, Julius Baxter <julius@opencores.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mhard-mul -mhard-div
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/openrisc/openrisc-generic/openrisc-generic.c b/board/openrisc/openrisc-generic/openrisc-generic.c
new file mode 100644
index 0000000..4f82600
--- /dev/null
+++ b/board/openrisc/openrisc-generic/openrisc-generic.c
@@ -0,0 +1,39 @@
+/*
+ * Based on nios2-generic.c:
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("BOARD: %s\n", CONFIG_BOARD_NAME);
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+#ifdef CONFIG_ETHOC
+ rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/openrisc/openrisc-generic/or1ksim.cfg b/board/openrisc/openrisc-generic/or1ksim.cfg
new file mode 100644
index 0000000..2bd8642
--- /dev/null
+++ b/board/openrisc/openrisc-generic/or1ksim.cfg
@@ -0,0 +1,871 @@
+/* sim.cfg -- Simulator configuration script file
+ Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
+
+This file is part of OpenRISC 1000 Architectural Simulator.
+It contains the default configuration and help about configuring
+the simulator.
+
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+/* INTRODUCTION
+
+ The ork1sim has various parameters, that are set in configuration files
+ like this one. The user can switch between configurations at startup by
+ specifying the required configuration file with the -f <filename.cfg> option.
+ If no configuration file is specified or1ksim searches for the default
+ configuration file sim.cfg. First it searches for './sim.cfg'. If this
+ file is not found, it searches for '~/or1k/sim.cfg'. If this file is
+ not found too, it reverts to the built-in default configuration.
+
+ NOTE: Users should not rely on the built-in configuration, since the
+ default configuration may differ between version.
+ Rather create a configuration file that sets all critical values.
+
+ This file may contain (standard C) comments only - no // support.
+
+ Configure files may be be included, using:
+ include "file_name_to_include"
+
+ Like normal configuration files, the included file is divided into
+ sections. Each section is described in detail also.
+
+ Some section have subsections. One example of such a subsection is:
+
+ device <index>
+ instance specific parameters...
+ enddevice
+
+ which creates a device instance.
+*/
+
+
+/* MEMORY SECTION
+
+ This section specifies how the memory is generated and the blocks
+ it consists of.
+
+ type = random/unknown/pattern
+ Specifies the initial memory values.
+ 'random' generates random memory using seed 'random_seed'.
+ 'pattern' fills memory with 'pattern'.
+ 'unknown' does not specify how memory should be generated,
+ leaving the memory in a undefined state. This is the fastest
+ option.
+
+ random_seed = <value>
+ random seed for randomizer, used if type = 'random'.
+
+ pattern = <value>
+ pattern to fill memory, used if type = 'pattern'.
+
+ nmemories = <value>
+ number of memory instances connected
+
+ baseaddr = <hex_value>
+ memory start address
+
+ size = <hex_value>
+ memory size
+
+ name = "<string>"
+ memory block name
+
+ ce = <value>
+ chip enable index of the memory instance
+
+ mc = <value>
+ memory controller this memory is connected to
+
+ delayr = <value>
+ cycles, required for read access, -1 if instance does not support reading
+
+ delayw = <value>
+ cycles, required for write access, -1 if instance does not support writing
+
+ log = "<filename>"
+ filename, where to log memory accesses to, no log, if log command is not specified
+*/
+
+
+section memory
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "FLASH"
+ ce = 0
+ mc = 0
+ baseaddr = 0xf0000000
+ size = 0x01000000
+ delayr = 1
+ delayw = -1
+end
+
+section memory
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "RAM"
+ ce = 1
+ mc = 0
+ baseaddr = 0x00000000
+ size = 0x02000000
+ delayr = 1
+ delayw = 1
+end
+
+section memory
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ name = "SRAM"
+ mc = 0
+ ce = 2
+ baseaddr = 0xa4000000
+ size = 0x00100000
+ delayr = 1
+ delayw = 2
+end
+
+
+/* IMMU SECTION
+
+ This section configures the Instruction Memory Manangement Unit
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets = <value>
+ number of ITLB sets; must be power of two
+
+ nways = <value>
+ number of ITLB ways
+
+ pagesize = <value>
+ instruction page size; must be power of two
+
+ entrysize = <value>
+ instruction entry size in bytes
+
+ ustates = <value>
+ number of ITLB usage states (2, 3, 4 etc., max is 4)
+
+ hitdelay = <value>
+ number of cycles immu hit costs
+
+ missdelay = <value>
+ number of cycles immu miss costs
+*/
+
+section immu
+ enabled = 1
+ nsets = 64
+ nways = 1
+ pagesize = 8192
+ hitdelay = 0
+ missdelay = 0
+end
+
+
+/* DMMU SECTION
+
+ This section configures the Data Memory Manangement Unit
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets = <value>
+ number of DTLB sets; must be power of two
+
+ nways = <value>
+ number of DTLB ways
+
+ pagesize = <value>
+ data page size; must be power of two
+
+ entrysize = <value>
+ data entry size in bytes
+
+ ustates = <value>
+ number of DTLB usage states (2, 3, 4 etc., max is 4)
+
+ hitdelay = <value>
+ number of cycles dmmu hit costs
+
+ missdelay = <value>
+ number of cycles dmmu miss costs
+*/
+
+section dmmu
+ enabled = 1
+ nsets = 64
+ nways = 1
+ pagesize = 8192
+ hitdelay = 0
+ missdelay = 0
+end
+
+
+/* IC SECTION
+
+ This section configures the Instruction Cache
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets = <value>
+ number of IC sets; must be power of two
+
+ nways = <value>
+ number of IC ways
+
+ blocksize = <value>
+ IC block size in bytes; must be power of two
+
+ ustates = <value>
+ number of IC usage states (2, 3, 4 etc., max is 4)
+
+ hitdelay = <value>
+ number of cycles ic hit costs
+
+ missdelay = <value>
+ number of cycles ic miss costs
+*/
+
+section ic
+ enabled = 1
+ nsets = 512
+ nways = 1
+ blocksize = 16
+ hitdelay = 1
+ missdelay = 1
+end
+
+
+/* DC SECTION
+
+ This section configures the Data Cache
+
+ enabled = 0/1
+ '0': disabled
+ '1': enabled
+ (NOTE: UPR bit is set)
+
+ nsets = <value>
+ number of DC sets; must be power of two
+
+ nways = <value>
+ number of DC ways
+
+ blocksize = <value>
+ DC block size in bytes; must be power of two
+
+ ustates = <value>
+ number of DC usage states (2, 3, 4 etc., max is 4)
+
+ load_hitdelay = <value>
+ number of cycles dc load hit costs
+
+ load_missdelay = <value>
+ number of cycles dc load miss costs
+
+ store_hitdelay = <value>
+ number of cycles dc load hit costs
+
+ store_missdelay = <value>
+ number of cycles dc load miss costs
+*/
+
+section dc
+ enabled = 1
+ nsets = 512
+ nways = 1
+ blocksize = 16
+ load_hitdelay = 1
+ load_missdelay = 1
+ store_hitdelay = 1
+ store_missdelay = 1
+end
+
+
+/* SIM SECTION
+
+ This section specifies how or1ksim should behave.
+
+ verbose = 0/1
+ '0': don't print extra messages
+ '1': print extra messages
+
+ debug = 0-9
+ 0 : no debug messages
+ 1-9: debug message level.
+ higher numbers produce more messages
+
+ profile = 0/1
+ '0': don't generate profiling file 'sim.profile'
+ '1': don't generate profiling file 'sim.profile'
+
+ prof_fn = "<filename>"
+ optional filename for the profiling file.
+ valid only if 'profile' is set
+
+ mprofile = 0/1
+ '0': don't generate memory profiling file 'sim.mprofile'
+ '1': generate memory profiling file 'sim.mprofile'
+
+ mprof_fn = "<filename>"
+ optional filename for the memory profiling file.
+ valid only if 'mprofile' is set
+
+ history = 0/1
+ '0': don't track execution flow
+ '1': track execution flow
+ Execution flow can be tracked for the simulator's
+ 'hist' command. Useful for back-trace debugging.
+
+ iprompt = 0/1
+ '0': start in <not interactive prompt> (so what do we start in ???)
+ '1': start in interactive prompt.
+
+ exe_log = 0/1
+ '0': don't generate execution log.
+ '1': generate execution log.
+
+ exe_log = default/hardware/simple/software
+ type of execution log, default is used when not specified
+
+ exe_log_start = <value>
+ index of first instruction to start logging, default = 0
+
+ exe_log_end = <value>
+ index of last instruction to end logging; not limited, if omitted
+
+ exe_log_marker = <value>
+ <value> specifies number of instructions before horizontal marker is
+ printed; if zero, markers are disabled (default)
+
+ exe_log_fn = "<filename>"
+ filename for the exection log file.
+ valid only if 'exe_log' is set
+
+ clkcycle = <value>[ps|ns|us|ms]
+ specifies time measurement for one cycle
+*/
+
+section sim
+ verbose = 1
+ debug = 0
+ profile = 0
+ history = 0
+
+ clkcycle = 10ns
+end
+
+
+/* SECTION VAPI
+
+ This section configures the Verification API, used for Advanced
+ Core Verification.
+
+ enabled = 0/1
+ '0': disbable VAPI server
+ '1': enable/start VAPI server
+
+ server_port = <value>
+ TCP/IP port to start VAPI server on
+
+ log_enabled = 0/1
+ '0': disable VAPI requests logging
+ '1': enable VAPI requests logging
+
+ hide_device_id = 0/1
+ '0': don't log device id (for compatability with old version)
+ '1': log device id
+
+
+ vapi_fn = <filename>
+ filename for the log file.
+ valid only if log_enabled is set
+*/
+
+section VAPI
+ enabled = 0
+ server_port = 9998
+ log_enabled = 0
+ vapi_log_fn = "vapi.log"
+end
+
+
+/* CPU SECTION
+
+ This section specifies various CPU parameters.
+
+ ver = <value>
+ rev = <value>
+ specifies version and revision of the CPU used
+
+ upr = <value>
+ changes the upr register
+
+ sr = <value>
+ sets the initial Supervision Register value
+ supervisor mode (SM) and fixed one (FO) set = 0x8001
+ exception prefix high (EPH, vectors@0xf0000000) = 0x4000
+ together, (SM | FO | EPH) = 0xc001
+ superscalar = 0/1
+ '0': CPU is scalar
+ '1': CPU is superscalar
+ (modify cpu/or32/execute.c to tune superscalar model)
+
+ hazards = 0/1
+ '0': don't track data hazards in superscalar CPU
+ '1': track data hazards in superscalar CPU
+ If tracked, data hazards can be displayed using the
+ simulator's 'r' command.
+
+ dependstats = 0/1
+ '0': don't calculate inter-instruction dependencies.
+ '1': calculate inter-instruction dependencies.
+ If calculated, inter-instruction dependencies can be
+ displayed using the simulator's 'stat' command.
+
+ sbuf_len = <value>
+ length of store buffer (<= 256), 0 = disabled
+*/
+
+section cpu
+ ver = 0x12
+ cfg = 0x00
+ rev = 0x01
+ sr = 0x8001 /*SPR_SR_FO | SPR_SR_SM | SPR_SR_EPH */
+ /* upr = */
+ superscalar = 0
+ hazards = 0
+ dependstats = 0
+ sbuf_len = 0
+end
+
+
+/* PM SECTION
+
+ This section specifies Power Management parameters
+
+ enabled = 0/1
+ '0': disable power management
+ '1': enable power management
+*/
+
+section pm
+ enabled = 0
+end
+
+
+/* BPB SECTION
+
+ This section specifies how branch prediction should behave.
+
+ enabled = 0/1
+ '0': disable branch prediction
+ '1': enable branch prediction
+
+ btic = 0/1
+ '0': disable branch target instruction cache model
+ '1': enable branch target instruction cache model
+
+ sbp_bf_fwd = 0/1
+ Static branch prediction for 'l.bf'
+ '0': don't use forward prediction
+ '1': use forward prediction
+
+ sbp_bnf_fwd = 0/1
+ Static branch prediction for 'l.bnf'
+ '0': don't use forward prediction
+ '1': use forward prediction
+
+ hitdelay = <value>
+ number of cycles bpb hit costs
+
+ missdelay = <value>
+ number of cycles bpb miss costs
+*/
+
+section bpb
+ enabled = 0
+ btic = 0
+ sbp_bf_fwd = 0
+ sbp_bnf_fwd = 0
+ hitdelay = 0
+ missdelay = 0
+end
+
+
+/* DEBUG SECTION
+
+ This sections specifies how the debug unit should behave.
+
+ enabled = 0/1
+ '0': disable debug unit
+ '1': enable debug unit
+
+ gdb_enabled = 0/1
+ '0': don't start gdb server
+ '1': start gdb server at port 'server_port'
+
+ server_port = <value>
+ TCP/IP port to start gdb server on
+ valid only if gdb_enabled is set
+
+ vapi_id = <hex_value>
+ Used to create "fake" vapi log file containing the JTAG proxy messages.
+*/
+section debug
+ enabled = 0
+/* gdb_enabled = 0 */
+/* server_port = 9999*/
+ rsp_enabled = 1
+ rsp_port = 50001
+end
+
+
+/* MC SECTION
+
+ This section configures the memory controller
+
+ enabled = 0/1
+ '0': disable memory controller
+ '1': enable memory controller
+
+ baseaddr = <hex_value>
+ address of first MC register
+
+ POC = <hex_value>
+ Power On Configuration register
+
+ index = <value>
+ Index of this memory controller amongst all the memory controllers
+*/
+
+section mc
+ enabled = 0
+ baseaddr = 0x93000000
+ POC = 0x00000008 /* Power on configuration register */
+ index = 0
+end
+
+
+/* UART SECTION
+
+ This section configures the UARTs
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr = <hex_value>
+ address of first UART register for this device
+
+
+ channel = <channeltype>:<args>
+
+ The channel parameter indicates the source of received UART characters
+ and the sink for transmitted UART characters.
+
+ The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty"
+ (without quotes).
+
+ A) To send/receive characters from a pair of files, use a file
+ channel:
+
+ channel=file:<rxfile>,<txfile>
+
+ B) To create an interactive terminal window, use an xterm channel:
+
+ channel=xterm:[<xterm_arg>]*
+
+ C) To create a bidirectional tcp socket which one could, for example,
+ access via telnet, use a tcp channel:
+
+ channel=tcp:<port number>
+
+ D) To cause the UART to read/write from existing numeric file
+ descriptors, use an fd channel:
+
+ channel=fd:<rx file descriptor num>,<tx file descriptor num>
+
+ E) To connect the UART to a physical serial port, create a tty
+ channel:
+
+ channel=tty:device=/dev/ttyS0,baud=9600
+
+ irq = <value>
+ irq number for this device
+
+ 16550 = 0/1
+ '0': this device is a UART16450
+ '1': this device is a UART16550
+
+ jitter = <value>
+ in msecs... time to block, -1 to disable it
+
+ vapi_id = <hex_value>
+ VAPI id of this instance
+*/
+
+section uart
+ enabled = 1
+ baseaddr = 0x90000000
+ irq = 2
+ /* channel = "file:uart0.rx,uart0.tx" */
+ /* channel = "tcp:10084" */
+ channel = "xterm:"
+ jitter = -1 /* async behaviour */
+ 16550 = 1
+end
+
+
+/* DMA SECTION
+
+ This section configures the DMAs
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr = <hex_value>
+ address of first DMA register for this device
+
+ irq = <value>
+ irq number for this device
+
+ vapi_id = <hex_value>
+ VAPI id of this instance
+*/
+
+section dma
+ enabled = 1
+ baseaddr = 0x9a000000
+ irq = 11
+end
+
+
+/* ETHERNET SECTION
+
+ This section configures the ETHERNETs
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr = <hex_value>
+ address of first ethernet register for this device
+
+ dma = <value>
+ which controller is this ethernet "connected" to
+
+ irq = <value>
+ ethernet mac IRQ level
+
+ rtx_type = <value>
+ use 0 - file interface, 1 - socket interface
+
+ rx_channel = <value>
+ DMA channel used for RX
+
+ tx_channel = <value>
+ DMA channel used for TX
+
+ rxfile = "<filename>"
+ filename, where to read data from
+
+ txfile = "<filename>"
+ filename, where to write data to
+
+ sockif = "<ifacename>"
+ interface name of ethernet socket
+
+ vapi_id = <hex_value>
+ VAPI id of this instance
+*/
+
+section ethernet
+ enabled = 1
+ baseaddr = 0x92000000
+ /* dma = 0 */
+ irq = 4
+ rtx_type = "tap"
+ tap_dev = "tap0"
+ /* tx_channel = 0 */
+ /* rx_channel = 1 */
+ rxfile = "eth0.rx"
+ txfile = "eth0.tx"
+ sockif = "eth0"
+end
+
+
+/* GPIO SECTION
+
+ This section configures the GPIOs
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr = <hex_value>
+ address of first GPIO register for this device
+
+ irq = <value>
+ irq number for this device
+
+ base_vapi_id = <hex_value>
+ first VAPI id of this instance
+ GPIO uses 8 consecutive VAPI IDs
+*/
+
+section gpio
+ enabled = 0
+ baseaddr = 0x91000000
+ irq = 3
+ base_vapi_id = 0x0200
+end
+
+/* VGA SECTION
+
+ This section configures the VGA/LCD controller
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr = <hex_value>
+ address of first VGA register
+
+ irq = <value>
+ irq number for this device
+
+ refresh_rate = <value>
+ number of cycles between screen dumps
+
+ filename = "<filename>"
+ template name for generated names (e.g. "primary" produces "primary0023.bmp")
+*/
+
+section vga
+ enabled = 0
+ baseaddr = 0x97100000
+ irq = 8
+ refresh_rate = 100000
+ filename = "primary"
+end
+
+
+/* TICK TIMER SECTION
+
+ This section configures tick timer
+
+ enabled = 0/1
+ whether tick timer is enabled
+*/
+
+section pic
+ enabled = 1
+ edge_trigger = 1
+end
+
+/* FB SECTION
+
+ This section configures the frame buffer
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ baseaddr = <hex_value>
+ base address of frame buffer
+
+ paladdr = <hex_value>
+ base address of first palette entry
+
+ refresh_rate = <value>
+ number of cycles between screen dumps
+
+ filename = "<filename>"
+ template name for generated names (e.g. "primary" produces "primary0023.bmp")
+*/
+
+section fb
+ enabled = 0
+ baseaddr = 0x97000000
+ refresh_rate = 1000000
+ filename = "primary"
+end
+
+
+/* KBD SECTION
+
+ This section configures the PS/2 compatible keyboard
+
+ baseaddr = <hex_value>
+ base address of the keyboard device
+
+ rxfile = "<filename>"
+ filename, where to read data from
+*/
+
+section kbd
+ enabled = 0
+ irq = 5
+ baseaddr = 0x94000000
+ rxfile = "kbd.rx"
+end
+
+
+/* ATA SECTION
+
+ This section configures the ATA/ATAPI host controller
+
+ baseaddr = <hex_value>
+ address of first ATA register
+
+ enabled = <0|1>
+ Enable/disable the peripheral. By default if it is enabled.
+
+ irq = <value>
+ irq number for this device
+
+ debug = <value>
+ debug level for ata models.
+ 0: no debug messages
+ 1: verbose messages
+ 3: normal messages (more messages than verbose)
+ 5: debug messages (normal debug messages)
+ 7: flow control messages (debug statemachine flows)
+ 9: low priority message (display everything the code does)
+
+ dev_type0/1 = <value>
+ ata device 0 type
+ 0: NO_CONNeCT: none (not connected)
+ 1: FILE : simulated harddisk
+ 2: LOCAL : local system harddisk
+
+ dev_file0/1 = "<filename>"
+ filename for simulated ATA device
+ valid only if dev_type0 == 1
+
+ dev_size0/1 = <value>
+ size of simulated hard-disk (in MBytes)
+ valid only if dev_type0 == 1
+
+ dev_packet0/1 = <value>
+ 0: simulated ATA device does NOT implement PACKET command feature set
+ 1: simulated ATA device does implement PACKET command feature set
+
+ FIXME: irq number
+*/
+
+section ata
+ enabled = 0
+ baseaddr = 0x9e000000
+ irq = 15
+
+end
diff --git a/board/overo/Kconfig b/board/overo/Kconfig
new file mode 100644
index 0000000..74572a6
--- /dev/null
+++ b/board/overo/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_OMAP3_OVERO
+
+config SYS_BOARD
+ default "overo"
+
+config SYS_CONFIG_NAME
+ default "omap3_overo"
+
+endif
diff --git a/board/overo/MAINTAINERS b/board/overo/MAINTAINERS
new file mode 100644
index 0000000..8f089e8
--- /dev/null
+++ b/board/overo/MAINTAINERS
@@ -0,0 +1,6 @@
+OVERO BOARD
+M: Steve Sakoman <sakoman@gmail.com>
+S: Maintained
+F: board/overo/
+F: include/configs/omap3_overo.h
+F: configs/omap3_overo_defconfig
diff --git a/board/overo/Makefile b/board/overo/Makefile
new file mode 100644
index 0000000..9109484
--- /dev/null
+++ b/board/overo/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := overo.o
diff --git a/board/overo/overo.c b/board/overo/overo.c
new file mode 100644
index 0000000..b7f85e7
--- /dev/null
+++ b/board/overo/overo.c
@@ -0,0 +1,530 @@
+/*
+ * Maintainer : Steve Sakoman <steve@sakoman.com>
+ *
+ * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <linux/mtd/nand.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include "overo.h"
+
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/ehci-omap.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TWL4030_I2C_BUS 0
+#define EXPANSION_EEPROM_I2C_BUS 2
+#define EXPANSION_EEPROM_I2C_ADDRESS 0x51
+
+#define GUMSTIX_EMPTY_EEPROM 0x0
+
+#define GUMSTIX_SUMMIT 0x01000200
+#define GUMSTIX_TOBI 0x02000200
+#define GUMSTIX_TOBI_DUO 0x03000200
+#define GUMSTIX_PALO35 0x04000200
+#define GUMSTIX_PALO43 0x05000200
+#define GUMSTIX_CHESTNUT43 0x06000200
+#define GUMSTIX_PINTO 0x07000200
+#define GUMSTIX_GALLOP43 0x08000200
+#define GUMSTIX_ALTO35 0x09000200
+#define GUMSTIX_STAGECOACH 0x0A000200
+#define GUMSTIX_THUMBO 0x0B000200
+#define GUMSTIX_TURTLECORE 0x0C000200
+#define GUMSTIX_ARBOR43C 0x0D000200
+
+#define ETTUS_USRP_E 0x01000300
+
+#define GUMSTIX_NO_EEPROM 0xffffffff
+
+static struct {
+ unsigned int device_vendor;
+ unsigned char revision;
+ unsigned char content;
+ char fab_revision[8];
+ char env_var[16];
+ char env_setting[64];
+} expansion_config = {0x0};
+
+static const struct ns16550_platdata overo_serial = {
+ OMAP34XX_UART3,
+ 2,
+ V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(overo_uart) = {
+ "serial_omap",
+ &overo_serial
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OVERO;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: get_board_revision
+ * Description: Returns the board revision
+ */
+int get_board_revision(void)
+{
+ int revision;
+
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+ unsigned char data;
+
+ /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
+ /* these boards should return a revision number of 0 */
+ /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
+ i2c_set_bus_num(TWL4030_I2C_BUS);
+ data = 0x01;
+ i2c_write(0x4B, 0x29, 1, &data, 1);
+ data = 0x0c;
+ i2c_write(0x4B, 0x2b, 1, &data, 1);
+ i2c_read(0x4B, 0x2a, 1, &data, 1);
+#endif
+
+ if (!gpio_request(112, "") &&
+ !gpio_request(113, "") &&
+ !gpio_request(115, "")) {
+
+ gpio_direction_input(112);
+ gpio_direction_input(113);
+ gpio_direction_input(115);
+
+ revision = gpio_get_value(115) << 2 |
+ gpio_get_value(113) << 1 |
+ gpio_get_value(112);
+ } else {
+ puts("Error: unable to acquire board revision GPIOs\n");
+ revision = -1;
+ }
+
+ return revision;
+}
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings->mr = MICRON_V_MR_165;
+ switch (get_board_revision()) {
+ case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ break;
+ case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
+ case REVISION_4:
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ break;
+ case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
+ timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+ timings->ctrla = HYNIX_V_ACTIMA_200;
+ timings->ctrlb = HYNIX_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ break;
+ case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */
+ timings->mcfg = MCFG(512 << 20, 15);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ break;
+ default:
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ }
+}
+#endif
+
+/*
+ * Routine: get_sdio2_config
+ * Description: Return information about the wifi module connection
+ * Returns 0 if the module connects though a level translator
+ * Returns 1 if the module connects directly
+ */
+int get_sdio2_config(void)
+{
+ int sdio_direct;
+
+ if (!gpio_request(130, "") && !gpio_request(139, "")) {
+
+ gpio_direction_output(130, 0);
+ gpio_direction_input(139);
+
+ sdio_direct = 1;
+ gpio_set_value(130, 0);
+ if (gpio_get_value(139) == 0) {
+ gpio_set_value(130, 1);
+ if (gpio_get_value(139) == 1)
+ sdio_direct = 0;
+ }
+
+ gpio_direction_input(130);
+ } else {
+ puts("Error: unable to acquire sdio2 clk GPIOs\n");
+ sdio_direct = -1;
+ }
+
+ return sdio_direct;
+}
+
+/*
+ * Routine: get_expansion_id
+ * Description: This function checks for expansion board by checking I2C
+ * bus 2 for the availability of an AT24C01B serial EEPROM.
+ * returns the device_vendor field from the EEPROM
+ */
+unsigned int get_expansion_id(void)
+{
+ if (expansion_config.device_vendor != 0x0)
+ return expansion_config.device_vendor;
+
+ i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
+
+ /* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */
+ if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
+ i2c_set_bus_num(TWL4030_I2C_BUS);
+ return GUMSTIX_NO_EEPROM;
+ }
+
+ /* read configuration data */
+ i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
+ sizeof(expansion_config));
+
+ i2c_set_bus_num(TWL4030_I2C_BUS);
+
+ return expansion_config.device_vendor;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ unsigned int expansion_id;
+
+ twl4030_power_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+
+ printf("Board revision: %d\n", get_board_revision());
+
+ switch (get_sdio2_config()) {
+ case 0:
+ puts("Tranceiver detected on mmc2\n");
+ MUX_OVERO_SDIO2_TRANSCEIVER();
+ break;
+ case 1:
+ puts("Direct connection on mmc2\n");
+ MUX_OVERO_SDIO2_DIRECT();
+ break;
+ default:
+ puts("Unable to detect mmc2 connection type\n");
+ }
+
+ expansion_id = get_expansion_id();
+ switch (expansion_id) {
+ case GUMSTIX_SUMMIT:
+ printf("Recognized Summit expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ setenv("defaultdisplay", "dvi");
+ setenv("expansionname", "summit");
+ break;
+ case GUMSTIX_TOBI:
+ printf("Recognized Tobi expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ setenv("defaultdisplay", "dvi");
+ setenv("expansionname", "tobi");
+ break;
+ case GUMSTIX_TOBI_DUO:
+ printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ break;
+ case GUMSTIX_PALO35:
+ printf("Recognized Palo35 expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ setenv("defaultdisplay", "lcd35");
+ break;
+ case GUMSTIX_PALO43:
+ printf("Recognized Palo43 expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ setenv("defaultdisplay", "lcd43");
+ setenv("expansionname", "palo43");
+ break;
+ case GUMSTIX_CHESTNUT43:
+ printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ setenv("defaultdisplay", "lcd43");
+ setenv("expansionname", "chestnut43");
+ break;
+ case GUMSTIX_PINTO:
+ printf("Recognized Pinto expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ break;
+ case GUMSTIX_GALLOP43:
+ printf("Recognized Gallop43 expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ setenv("defaultdisplay", "lcd43");
+ setenv("expansionname", "gallop43");
+ break;
+ case GUMSTIX_ALTO35:
+ printf("Recognized Alto35 expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ MUX_ALTO35();
+ setenv("defaultdisplay", "lcd35");
+ setenv("expansionname", "alto35");
+ break;
+ case GUMSTIX_STAGECOACH:
+ printf("Recognized Stagecoach expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ break;
+ case GUMSTIX_THUMBO:
+ printf("Recognized Thumbo expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ break;
+ case GUMSTIX_TURTLECORE:
+ printf("Recognized Turtlecore expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ break;
+ case GUMSTIX_ARBOR43C:
+ printf("Recognized Arbor43C expansion board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ MUX_ARBOR43C();
+ setenv("defaultdisplay", "lcd43");
+ break;
+ case ETTUS_USRP_E:
+ printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_GUMSTIX();
+ MUX_USRP_E();
+ setenv("defaultdisplay", "dvi");
+ break;
+ case GUMSTIX_NO_EEPROM:
+ case GUMSTIX_EMPTY_EEPROM:
+ puts("No or empty EEPROM on expansion board\n");
+ MUX_GUMSTIX();
+ setenv("expansionname", "tobi");
+ break;
+ default:
+ printf("Unrecognized expansion board 0x%08x\n", expansion_id);
+ break;
+ }
+
+ if (expansion_config.content == 1)
+ setenv(expansion_config.env_var, expansion_config.env_setting);
+
+ dieid_num_r();
+
+ if (get_cpu_family() == CPU_OMAP34XX)
+ setenv("boardname", "overo");
+ else
+ setenv("boardname", "overo-storm");
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_OVERO();
+}
+
+#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SPL_BUILD)
+/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
+static const u32 gpmc_lan_config[] = {
+ NET_LAN9221_GPMC_CONFIG1,
+ NET_LAN9221_GPMC_CONFIG2,
+ NET_LAN9221_GPMC_CONFIG3,
+ NET_LAN9221_GPMC_CONFIG4,
+ NET_LAN9221_GPMC_CONFIG5,
+ NET_LAN9221_GPMC_CONFIG6,
+ /*CONFIG7- computed as params */
+};
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+}
+
+/*
+ * Routine: reset_net_chip
+ * Description: Reset the Ethernet hardware.
+ */
+static void reset_net_chip(void)
+{
+ /* Make GPIO 64 as output pin and send a magic pulse through it */
+ if (!gpio_request(64, "")) {
+ gpio_direction_output(64, 0);
+ gpio_set_value(64, 1);
+ udelay(1);
+ gpio_set_value(64, 0);
+ udelay(1);
+ gpio_set_value(64, 1);
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+ unsigned int expansion_id;
+ int rc = 0;
+
+#ifdef CONFIG_SMC911X
+ expansion_id = get_expansion_id();
+ switch (expansion_id) {
+ case GUMSTIX_TOBI_DUO:
+ /* second lan chip */
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
+ 0x2B000000, GPMC_SIZE_16M);
+ /* no break */
+ case GUMSTIX_TOBI:
+ case GUMSTIX_CHESTNUT43:
+ case GUMSTIX_STAGECOACH:
+ case GUMSTIX_NO_EEPROM:
+ case GUMSTIX_EMPTY_EEPROM:
+ /* first lan chip */
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
+ 0x2C000000, GPMC_SIZE_16M);
+
+ setup_net_chip();
+ reset_net_chip();
+
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ break;
+ default:
+ break;
+ }
+#endif
+
+ return rc;
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
+#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
+};
+
+#define GUMSTIX_GPIO_USBH_CPEN 168
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ /* Enable USB power */
+ if (!gpio_request(GUMSTIX_GPIO_USBH_CPEN, "usbh_cpen"))
+ gpio_direction_output(GUMSTIX_GPIO_USBH_CPEN, 1);
+
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(void)
+{
+ /* Disable USB power */
+ gpio_set_value(GUMSTIX_GPIO_USBH_CPEN, 0);
+ gpio_free(GUMSTIX_GPIO_USBH_CPEN);
+
+ return omap_ehci_hcd_stop();
+}
+
+#endif /* CONFIG_USB_EHCI */
diff --git a/board/overo/overo.h b/board/overo/overo.h
new file mode 100644
index 0000000..d0edf86
--- /dev/null
+++ b/board/overo/overo.h
@@ -0,0 +1,432 @@
+/*
+ * (C) Copyright 2008
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _OVERO_H_
+#define _OVERO_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "Gumstix Overo board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+ "OneNAND",
+#else
+ "NAND",
+#endif
+};
+
+/* overo revisions */
+#define REVISION_0 0x0
+#define REVISION_1 0x1
+#define REVISION_2 0x2
+#define REVISION_3 0x3
+#define REVISION_4 0x4
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_OVERO() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\
+ /* - MMC1_WP*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card */\
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
+ MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\
+ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /*McBSP1_FSR*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M0)) /*McBSP1_DX*/\
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\
+ /* BT_NRESET*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
+ /* - USBH_CPEN*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
+ /* - USBH_RESET*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\
+ /* - W2W_NRESET*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/\
+ /* die to die */\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+#define MUX_GUMSTIX() \
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) /*GPIO_63*/\
+ /* - CAM_IRQ*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
+ /* - SMSC911X_NRES*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
+ /* - PEN_DOWN*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\
+ /* - LAN_INTR */\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\
+
+#define MUX_OVERO_SDIO2_DIRECT() \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M0)) /*MMC2_DAT4*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M0)) /*MMC2_DAT5*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M0)) /*MMC2_DAT6*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
+
+#define MUX_OVERO_SDIO2_TRANSCEIVER() \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) /*GPIO_126*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
+
+#define MUX_USRP_E() \
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M4)) /*GPIO_173 */\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175 */\
+
+#define MUX_ALTO35() \
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-BTN*/\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M4)) /*GPIO_148-RED LED*/\
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\
+ MUX_VAL(CP(UART1_RX), (IDIS | PTD | DIS | M4)) /*GPIO_151-BLUE LED*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTD | DIS | M4)) /*GPIO_170-GREEN LED*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175*/\
+
+#define MUX_ARBOR43C() \
+ MUX_VAL(CP(CSI2_DX1), (IDIS | PTD | DIS | M4)) /*GPIO_114-RED LED*/\
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) /*GPIO_170-BUTTON */\
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)) /*GPIO_186-BLUE LED*/\
+ MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M4)) /*GPIO_31-CAP WAKE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-CAP IRQ*/\
+
+#endif
diff --git a/board/palmld/Kconfig b/board/palmld/Kconfig
new file mode 100644
index 0000000..3111295
--- /dev/null
+++ b/board/palmld/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_PALMLD
+
+config SYS_BOARD
+ default "palmld"
+
+config SYS_CONFIG_NAME
+ default "palmld"
+
+endif
diff --git a/board/palmld/MAINTAINERS b/board/palmld/MAINTAINERS
new file mode 100644
index 0000000..7d21b7b
--- /dev/null
+++ b/board/palmld/MAINTAINERS
@@ -0,0 +1,6 @@
+PALMLD BOARD
+M: Marek Vasut <marek.vasut@gmail.com>
+S: Maintained
+F: board/palmld/
+F: include/configs/palmld.h
+F: configs/palmld_defconfig
diff --git a/board/palmld/Makefile b/board/palmld/Makefile
new file mode 100644
index 0000000..ea93ca8
--- /dev/null
+++ b/board/palmld/Makefile
@@ -0,0 +1,9 @@
+#
+# Palm LifeDrive Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := palmld.o
diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c
new file mode 100644
index 0000000..fee4dcd
--- /dev/null
+++ b/board/palmld/palmld.c
@@ -0,0 +1,61 @@
+/*
+ * Palm LifeDrive Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* arch number of PalmLD */
+ gd->bd->bi_arch_number = MACH_TYPE_PALMLD;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Set PWM for LCD */
+ writel(0x7, PWM_CTRL0);
+ writel(0x16c, PWM_PERVAL0);
+ writel(0x11a, PWM_PWDUTY0);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ pxa2xx_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return 1;
+}
diff --git a/board/palmtc/Kconfig b/board/palmtc/Kconfig
new file mode 100644
index 0000000..3eb7198
--- /dev/null
+++ b/board/palmtc/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_PALMTC
+
+config SYS_BOARD
+ default "palmtc"
+
+config SYS_CONFIG_NAME
+ default "palmtc"
+
+endif
diff --git a/board/palmtc/MAINTAINERS b/board/palmtc/MAINTAINERS
new file mode 100644
index 0000000..57b6a22
--- /dev/null
+++ b/board/palmtc/MAINTAINERS
@@ -0,0 +1,6 @@
+PALMTC BOARD
+M: Marek Vasut <marek.vasut@gmail.com>
+S: Maintained
+F: board/palmtc/
+F: include/configs/palmtc.h
+F: configs/palmtc_defconfig
diff --git a/board/palmtc/Makefile b/board/palmtc/Makefile
new file mode 100644
index 0000000..b4a682d
--- /dev/null
+++ b/board/palmtc/Makefile
@@ -0,0 +1,9 @@
+#
+# Palm Tungsten|C Support
+#
+# Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := palmtc.o
diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c
new file mode 100644
index 0000000..a6207b4
--- /dev/null
+++ b/board/palmtc/palmtc.c
@@ -0,0 +1,61 @@
+/*
+ * Palm Tungsten|C Support
+ *
+ * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/arch/pxa.h>
+#include <asm/arch/regs-mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* Arch number of Palm Tungsten|C */
+ gd->bd->bi_arch_number = MACH_TYPE_PALMTC;
+
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Set PWM for LCD */
+ writel(0x5f, PWM_CTRL1);
+ writel(0x3ff, PWM_PERVAL1);
+ writel(892, PWM_PWDUTY1);
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ pxa2xx_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
diff --git a/board/palmtreo680/Kconfig b/board/palmtreo680/Kconfig
new file mode 100644
index 0000000..b5fdb9a
--- /dev/null
+++ b/board/palmtreo680/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_PALMTREO680
+
+config SYS_BOARD
+ default "palmtreo680"
+
+config SYS_CONFIG_NAME
+ default "palmtreo680"
+
+endif
diff --git a/board/palmtreo680/MAINTAINERS b/board/palmtreo680/MAINTAINERS
new file mode 100644
index 0000000..b0ff9d0
--- /dev/null
+++ b/board/palmtreo680/MAINTAINERS
@@ -0,0 +1,6 @@
+PALMTREO680 BOARD
+#M: Mike Dunn <mikedunn@newsguy.com>
+S: Orphan (since 2014-06)
+F: board/palmtreo680/
+F: include/configs/palmtreo680.h
+F: configs/palmtreo680_defconfig
diff --git a/board/palmtreo680/Makefile b/board/palmtreo680/Makefile
new file mode 100644
index 0000000..4f79e4b
--- /dev/null
+++ b/board/palmtreo680/Makefile
@@ -0,0 +1,9 @@
+#
+# Palm Treo680 Support
+#
+# Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for details.
+
+obj-y := palmtreo680.o
diff --git a/board/palmtreo680/README b/board/palmtreo680/README
new file mode 100644
index 0000000..c8799c6
--- /dev/null
+++ b/board/palmtreo680/README
@@ -0,0 +1,563 @@
+
+README for the Palm Treo 680.
+
+Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+
+You may reproduce the contents of this file entirely or in part, but please
+credit me by name if you do. Thanks.
+
+
+Intro
+=====
+
+Yes, you can program u-boot onto the flash of your Palm Treo 680 so that u-boot
+(then Linux, Android, ...) runs at power-up. This document describes how, and
+gives some implementation details on this port of u-boot and describes how the
+Treo 680 boots from reset.
+
+But first, I probably don't need to tell you that after doing this, your phone
+will no longer run PalmOS. You *may* be able to later restore your phone to its
+original state by creating a backup image of the flash before writing u-boot
+(details below), but this is not heavily tested and should not be relied upon.
+There is also the possibility that something may go wrong during the process of
+programming u-boot, leaving you with a bricked phone. If you follow these
+instructions carefully this chance will be minimized, but I do not recommend
+that you program u-boot onto a phone that you can not afford to lose, and
+certainly not one that contains important data that is not backed up elsewhere.
+I AM NOT RESPONSIBLE FOR THE LOSS OF YOUR PHONE. DO THIS AT YOUR OWN RISK.
+Having said that, feel free to send me a note cursing me out if something does
+go wrong, but please tell me what happened exactly. For that matter, I'd love
+to hear from you if you succeed.
+
+
+Details on the SPL
+==================
+
+The docg4 features a 2k region at the start of its address space that interfaces
+to the system bus like a NOR flash. This allows the docg4 to function as a boot
+ROM. The Treo 680 uses this feature. The contents of this 2k region are
+write-protected and can not be reprogrammed. Fortunately, the code it contains
+does what we need to do, at least partially. After some essential hardware
+initialization (like the SDRAM controller), it runs an IPL (initial program
+loader) that copies 128K (no more, no less) from flash to a fixed address in
+SDRAM (0xa1700000) and jumps to it. 128K is too small for u-boot, so we use it
+to load a u-boot secondary program loader (SPL). But since our SPL only
+occupies a little over 1k, we can economize on flash usage by having the IPL
+load a portion of u-boot proper as well. We let the IPL load the first 128k of
+a concatenated spl + u-boot image, and because the SPL is placed before u-boot
+proper, the IPL jumps to the SPL, which copies the portion of u-boot that the
+IPL has already loaded to its correct SDRAM address, and then loads the
+remainder of u-boot and jumps to it.
+
+
+The docg4's "reliable mode"
+===========================
+
+This is a special mode of operation of the docg4's integrated controller whereby
+consecutive pairs of 2k regions are used in parallel (in some fashion) to store
+2k of data. In other words, the normal capacity is halved, but the data
+integrity is improved. In this mode, the data is read or written from pages in
+even-numbered 2k regions (regions starting at 0x000, 0x1000, 0x2000, ...). The
+odd-numbered 2k regions (regions starting at 0x800, 0x1800, 0x2800, ...) are
+transparently used in parallel. In reliable mode, the odd-numbered 2k regions
+are not meant to be read or written directly.
+
+Reliable mode is used by the IPL because there is not enough space in its 2k
+footprint to implement the BCH ecc algorithm. Data that is read while reliable
+mode is enabled must have been written in reliable mode, or the read fails.
+However, data written in reliable mode can also be read in normal mode (just not
+as reliably), but only from the even-numbered 2k regions; the odd-numbered 2k
+regions appear to contain junk, and will generate ecc errors. When the IPL and
+SPL read from flash, the odd-numbered 2k regions are explicitly skipped. The
+same is true for the flash_u-boot utility when it writes the u-boot image in
+reliable mode.
+
+The docg4 Linux driver supports writing in reliable mode (it is enabled by the
+module parameter), but not reading. However, the u-boot docg4_spl driver does
+read in reliable mode, in the same fashion as the IPL.
+
+
+Details on the IPL and its data format
+======================================
+
+Starting from block 5 and counting upward, the IPL will search for and load the
+first two blocks it finds that contain a magic number in the oob of the first
+page of the block. The contents are loaded to SDRAM starting at address
+0xa1700000. After two blocks have been loaded, it jumps to 0xa1700000. The
+number of blocks loaded and the load address in SDRAM are hard-coded; only the
+flash offset of the blocks can vary at run-time (based on the presence of the
+magic number).
+
+In addition to using the docg4's reliable mode, the IPL expects each 512 byte
+page to be written redundantly in the subsequent page. The hardware is capable
+of detecting bit errors (but not correcting them), and if a bit error is
+detected when a page is read, the page contents are discarded and the subsequent
+page is read.
+
+Reliable mode reduces the capacity of a block by half, and the redundant pages
+reduce it by half again. As a result, the normal 256k capacity of a block is
+reduced to 64k for the purposes of the IPL/SPL.
+
+For the sake of simplicity and uniformity, the u-boot SPL mimics the operation
+of the IPL, and expects the image to be stored in the same format.
+
+
+Instructions on Programming u-boot to flash
+===========================================
+
+To program u-boot to your flash, you will need to boot the Linux kernel on your
+phone using a PalmOS bootloader such as cocoboot. The details of building and
+running Linux on your Treo (cross-compiling, creating a root filesystem,
+configuring the kernel, etc) are beyond the scope of this document. The
+remainder of this document describes in detail how to program u-boot to the
+flash using Linux running on the Treo.
+
+
+Hardware Prerequisites
+======================
+
+A Palm Treo 680:
+ (dugh)
+
+A Palm usb cable:
+ You'll need this to establish a usbtty console connection to u-boot from a
+ desktop PC. Currently there is no support in u-boot for the pxa27x keypad
+ (coming soon), so a serial link must be used for the console.
+ These cables are still widely available if you don't already have one.
+
+A Linux desktop PC.
+ You may be able to use Windows for the u-boot console if you have a usb driver
+ that is compatible with the Linux usbserial driver, but for programming u-boot
+ to flash, you'll really want to use a Linux PC.
+
+
+Treo-side Software Prerequisites
+================================
+
+Linux bootloader for PalmOS:
+
+ Cocoboot is the only one I'm aware of. If you don't already have this, you
+ can download it from
+ https://download.enlightenment.org/misc/Illume/Treo-650/2008-11-13/sdcard-base.tar.gz
+ which is a compressed tar archive of the contents of an sd card containing
+ cocoboot. Use mkdosfs to create a fat16 filesystem on the first primary
+ partition of the card, mount the partition, and extract the tar file to it.
+ You will probably need to edit the cocoboot.conf file to customize the
+ parameters passed to the kernel.
+
+
+Linux kernel:
+
+ The kernel on the Treo 680 is still a little rough around the edges, and the
+ official kernel frequently breaks on the Treo :( A development kernel
+ specifically for the Treo 680 can be found on github:
+ http://github.com/mike-dunn/linux-treo680
+ The master branch of this tree has been tested on the Treo, and I recommend
+ using this kernel for programming u-boot. As of this writing, there may be a
+ bug in the docg4 nand flash driver that sometimes causes block erasures to
+ fail. This has been fixed in the above tree.
+
+ If you choose to use the official kernel, it must contain the docg4 driver that
+ includes the reliable_mode module parameter. This was a later enhancement to
+ the driver, and was merged to the kernel as of v3.8. Do not try to use an
+ earlier kernel that contains the docg4 driver without support for writing in
+ reliable mode. If you try to program u-boot to flash with the docg4 driver
+ loaded without the reliable_mode parameter enabled, you *will* brick your
+ phone!
+
+ For the purpose of programming u-boot to flash, the following options must be
+ enabled in the Treo kernel's .config:
+
+ CONFIG_MTD=y
+ CONFIG_MTD_CMDLINE_PARTS=y
+ CONFIG_MTD_CHAR=y
+ CONFIG_MTD_NAND_DOCG4=m
+
+ Note that the docg4 nand driver is configured as a module, because we will
+ want to load and unload it with reliable_mode enabled or disabled as needed.
+
+ You will also need to specify mtd partitions on the kernel command line. In
+ the instructions that follow, we will assume that the flash blocks to which
+ u-boot will be programmed are defined by the second partition on the device.
+ The u-boot config file (include/configs/palmtreo680.h) places the u-boot image
+ at the start of block 6 (offset 0x180000), which is the first writable
+ (non-protected) block on the flash (this is also where the PalmOS SPL starts).
+ The u-boot image occupies four blocks, so to create the u-boot partition, pass
+ this command line to the kernel:
+ mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part)
+ This will create three partitions:
+ protected_part: the first six blocks, which are read-only
+ bootloader_part: the next four blocks, for the u-boot image
+ filesys_part: the remainder of the device
+ The mtdchar kernel device driver will use device nodes /dev/mtd0, /dev/mtd1,
+ and /dev/mtd2 for these partitions, respectively. Ensure that your root file
+ system at least has /dev/mtd1 if you are not running udev or mdev.
+
+Userspace Utilities:
+
+ In addition to everything necessary to provide a useful userspace environment
+ (busybox is indispensable, of course), you will need the mtd-utils package on
+ your root filesystem. I use version 1.5.0 of mtd-utils, and I suggest you use
+ this version as well, or at leat a version very close to this one, as
+ mtd-utils has tended to be fluid.
+
+ Note that busybox includes a version of mtd-utils. These are deficient and
+ should not be used. When you run one of these utilities (nanddump, etc),
+ ensure you are invoking the separate executable from mtd-utils, and not the
+ one built into busybox. I recommend that you configure busybox with its
+ mtd-utils disabled to avoid any possibility of confusion.
+
+ You will also need to cross-compile the userspace Linux utility in
+ tools/palmtreo680/flash_u-boot.c, which we will run on the Treo to perform the
+ actual write of the u-boot image to flash. This utility links against libmtd
+ from the mtd-utils package.
+
+
+Desktop PC-side Software Prerequisites
+======================================
+
+Terminal emulator application:
+ minicom, kermit, etc.
+
+Linux kernel:
+ Compiled with CONFIG_USB_SERIAL enabled. Build this as a module.
+
+
+Recommended (Not directly related to u-boot)
+============================================
+
+Working directly on the Treo's tiny screen and keypad is difficult and
+error-prone. I recommend that you log into the Linux kernel running on your
+Treo from your desktop PC using ethernet over usb. The desktop's kernel must be
+configured with CONFIG_USB_USBNET, CONFIG_USB_NET_CDCETHER, and
+CONFIG_USB_NET_CDC_SUBSET. The Treo's kernel will need CONFIG_USB_ETH, and its
+init script will need to start an ssh daemon like dropbear. Note that the usb0
+network interface will not appear on the desktop PC until the Treo kernel's usb
+ethernet gadget driver has initialized. You must wait for this to occur (watch
+the PC's kernel log) before you can assign usb0 an ip address and log in to the
+Treo. If you also build the Treo's kernel with CONFIG_IP_PNP enabled, you can
+pass its ip address on the kernel command line, and obviate the need to
+initialize the network interface in your init script.
+
+Having the Palm usb cable connected to the host has the added benefit of keeping
+power supplied to your Treo, reducing the drain on the battery. If something
+goes wrong while you're programming u-boot to the flash, you will have lots of
+time to correct it before the battery dies.
+
+I have encountered a situation where the kernel is sometimes unable to mount a
+root filesystem on the mmc card due to the mmc controller not initializing in
+time, (and CONFIG_MMC_UNSAFE_RESUME doesn't seem to help) so I recommend that
+you build a minimal root filesystem into the kernel using the kernel's initramfs
+feature (CONFIG_BLK_DEV_INITRD). If you want your root filesystem on the mmc
+card, your init script can mount and switch_root to the mmc card after a short
+sleep. But keep in mind that in this case you won't be able to use an mmc card
+to transfer files between your desktop and the Treo once Linux is running.
+Another option for transfering files is to mount an nfs filesystem exported by
+the desktop PC. For greatest convenience, you can export the root filesystem
+itself from your desktop PC and switch_root to it in your init script. This
+will work if your initramfs init script contains a loop that waits for you to
+initialize the usb0 network interface on the desktop PC; e.g., loop while a ping
+to the desktop PC returns an error. After the loop exits, do the nfs mount and
+call switch_root. (You can not use the kernel nfsroot feature because the
+network will not be up when the kernel expects it to be; i.e., not until you
+configure the usb0 interface on the desktop.) Use the nfs 'nolock' option when
+mounting to avoid the need to run a portmapper like rpcbind.
+
+
+Preliminaries
+=============
+
+Once Linux is running on your Treo, you may want to perform a few sanity checks
+before programming u-boot. These checks will verify my assumptions regarding
+all the Treo 680s out there, and also ensure that the flash and mtd-utils are
+working correctly. If you are impatient and reckless, you may skip this
+section, but see disclaimer at the top of this file!
+
+Load the docg4 driver:
+
+ $ modprobe docg4 ignore_badblocks=1 reliable_mode=1
+
+We tell the driver to use the docg4's "reliable mode" when writing because this
+is the format required by the IPL, which runs from power-up and loads the first
+portion of u-boot. We must ignore bad blocks because linux mtd uses out-of-band
+(oob) bytes to mark bad blocks, which will cause the blocks written by PalmOS to
+be misidentified as "bad" by libmtd.
+
+Check the kernel log to ensure that all's well:
+
+ $ dmesg | tail
+ <... snip ...>
+ docg4 docg4: NAND device: 128MiB Diskonchip G4 detected
+ 3 cmdlinepart partitions found on MTD device Msys_Diskonchip_G4
+ Creating 3 MTD partitions on "Msys_Diskonchip_G4":
+ 0x000000000000-0x000000180000 : "protected_part"
+ 0x000000180000-0x000000280000 : "bootloader_part"
+ 0x000000280000-0x000008000000 : "filesys_part"
+
+Ensure that the partition boundaries are as shown. (If no partitions are shown,
+did you remember to pass them to the kernel on the command line?) We will write
+u-boot to bootloader_part, which starts at offset 0x180000 (block 6) and spans 4
+256k blocks. This partition is accessed through the device node /dev/mtd1.
+
+The docg4 contains a read-only table that identifies blocks that were marked as
+bad at the factory. This table is in the page at offset 0x2000, which is within
+the partition protected_part (/dev/mtd0). There is a slight chance that one or
+more of the four blocks that we will use for u-boot is listed in the table, so
+use nanddump to inspect the table to see if this is the case:
+
+ $ nanddump -p -l 512 -s 0x2000 -o /dev/mtd0
+ ECC failed: 0
+ ECC corrected: 0
+ Number of bad blocks: 0
+ Number of bbt blocks: 0
+ Block size 262144, page size 512, OOB size 16
+ Dumping data starting at 0x00002000 and ending at 0x00002200...
+ 0x00002000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+ <... snip ...>
+
+The format of the table is simple: one bit per block, with block numbers
+increasing from left to right, starting with block 0 as the most significant bit
+of the first byte. A bit will be clear if the corresponding block is bad. We
+want to use blocks 6 throgh 9, so both of the two least significant bits of the
+first byte must be set, as must the two most significant bits of the second
+byte. If this is not true in your case (you are very unlucky), you should use
+the first contiguous set of four good blocks after block 6, and adjust the
+partition boundaries accordingly. You will also have to change the value of
+CONFIG_SYS_NAND_U_BOOT_OFFS in include/configs/palmtreo680.h and recompile
+u-boot. Because the two blocks loaded by the IPL do not have to be contiguous,
+but our SPL expects them to be, you will need to erase any good blocks that are
+at an offset prior to CONFIG_SYS_NAND_U_BOOT_OFFS, so that the IPL does not find
+the magic number in oob and load it. Once you have done all this, the
+instructions in this file still apply, except that the instructions below for
+restoring the original PalmOS block contents may need to be modified.
+
+Next, use nanddump to verify that the PalmOS SPL is where we expect it to be.
+The SPL can be identified by a magic number in the oob bytes of the first page
+of each of the two blocks containing the SPL image. Pages are 512 bytes in
+size, so to dump the first page, plus the oob:
+
+ $ nanddump -p -l 512 -s 0 -o /dev/mtd1
+ ECC failed: 0
+ ECC corrected: 0
+ Number of bad blocks: 0
+ Number of bbt blocks: 0
+ Block size 262144, page size 512, OOB size 16
+ Dumping data starting at 0x00000000 and ending at 0x00000200...
+ 0x00000000: 0a 00 00 ea 00 00 00 00 00 00 00 00 00 00 00 00
+ <... snip ...>
+ 0x000001f0: 13 4c 21 60 13 4d 2a 69 13 4b 29 69 89 1a 99 42
+ OOB Data: 42 49 50 4f 30 30 30 10 3a e2 00 92 be a0 11 ff
+
+Verify that the first seven bytes of oob data match those in the above line.
+(This is ASCII "BIPO000".)
+
+Do the same for the next block:
+ $ nanddump -p -l 512 -s 0x40000 -o /dev/mtd1
+
+The first seven oob bytes in last line should read:
+
+ OOB Data: 42 49 50 4f 30 30 31 81 db 8e 8f 46 07 9b 59 ff
+
+(This is ASCII "BIPO001".)
+
+For additional assurance, verify that the next block does *not* contain SPL
+data.
+
+ $ nanddump -p -l 512 -s 0x80000 -o /dev/mtd1
+
+It doesn't matter what the oob contains, as long as the first four bytes are
+*not* ASCII "BIPO". PalmOS should only be using two blocks for the SPL
+(although we will need four for u-boot).
+
+If you want, you can back up the contents of bootloader_part to a file. You may
+be able to restore it later, if desired (see "Restoring PalmOS" below).
+
+ $ nanddump -l 0x100000 -s 0 -o -f bootloader_part.orig /dev/mtd1
+
+nanddump will spew voluminous warnings about uncorrectable ecc errors. This is
+a consequence of reading pages that were written in reliable mode, and is
+expected (these should all occur on pages in odd-numbered 2k regions; i.e.,
+0x800, 0xa00, 0xc00, 0xe00, 0x1800, 0x1a00, ...). The size of the file
+bootloader_part.orig should be 1081344, which is 2048 pages, each of size 512
+plus 16 oob bytes. If you are using initramfs for the root filesystem, don't
+forget to copy the file to permanent storage, such as an mmc card.
+
+If all of the above went well, you can now program u-boot.
+
+
+Programming u-boot
+==================
+
+Our u-boot includes a small SPL that must be prepended to u-boot proper. From
+the base u-boot source directory on your desktop PC:
+
+ $ cat spl/u-boot-spl.bin u-boot.bin > u-boot-concat.bin
+
+cd to the tools/palmtreo680/ directory, and cross-compile flash_u-boot.c for the
+Treo:
+
+ $(CC) -o flash_u-boot $(CFLAGS) $(INCLUDEPATH) $(LIBPATH) flash_u-boot.c -lmtd
+
+Substitute variable values from your cross-compilation environment as
+appropriate. Note that it links to libmtd from mtd-utils, and this must be
+included in $(LIBPATH) and $(INCLUDEPATH).
+
+Transfer u-boot-concat.bin and the compiled flash_u-boot utility to the Treo's
+root filesystem. On the Treo, cd to the directory where these files were
+placed.
+
+Load the docg4 driver if you have not already done so.
+
+ $ modprobe docg4 ignore_badblocks=1 reliable_mode=1
+
+Erase the blocks to which we will write u-boot:
+
+ $ flash_erase /dev/mtd1 0x00 4
+
+If no errors are reported, write u-boot to the flash:
+
+ $ ./flash_u-boot u-boot-concat.bin /dev/mtd1
+
+You can use nanddump (see above) to verify that the data was written. This
+time, "BIPO" should be seen in the first four oob bytes of the first page of all
+four blocks in /dev/mtd1; i.e., at offsets 0x00000, 0x40000, 0x80000, 0xc0000.
+
+Shutdown linux, remove and re-insert the battery, hold your breath...
+
+
+Enjoying u-boot
+===============
+
+After you insert the battery, the u-boot splash screen should appear on the lcd
+after a few seconds. With the usb cable connecting the Treo to your PC, in the
+kernel log of your PC you should see
+
+ <6>usb 3-1: New USB device found, idVendor=0525, idProduct=a4a6
+ <6>usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
+ <6>usb 3-1: Product: U-Boot 2013.01-00167-gd62ef56-dirty
+ <6>usb 3-1: Manufacturer: Das U-Boot
+
+Load the usbserial module on your desktop PC:
+
+ $ modprobe usbserial vendor=0x0525 product=0xa4a6
+
+and run your favorite terminal emulation utility (minicom, kermit, etc) with the
+serial device set to /dev/ttyUSB0 (assuming this is your only usb serial
+device). You should be at the u-boot console (type 'help').
+
+There is not much that is unique about using u-boot on the palm treo 680.
+Kernels can be loaded from mmc, flash, and from the desktop PC via kermit. You
+can expand the size of the second partition on the flash to contain a kernel, or
+else put the kernel(s) in their own partition.
+
+Nand commands work as expected, with the excepton that blocks not written by the
+linux mtd subsystem may be misidentified by the u-boot docg4 driver as "bad" if
+they contain data in the oob bytes. This will be the case for the blocks
+containing the u-boot image, for example. To work around this, use 'nand scrub'
+instead of 'nand erase' to erase these blocks, and 'nand read.raw' to read them
+to memory. (It would be useful if u-boot's nand commands provided a way to
+explicitly ignore "bad" blocks, because read.raw does not perform ecc.) The
+'nand dump' command will read these "bad" blocks, however.
+
+Currently u-boot itself can only be programmed to flash from Linux; there is no
+support for reliable mode in u-boot's docg4 flash driver. This should be
+corrected soon.
+
+
+Customizing
+===========
+
+If you change u-boot's configuration significantly (adding or removing
+features), you may have to adjust the value of CONFIG_SYS_NAND_U_BOOT_SIZE.
+This is the size of the concatenated spl + u-boot image, and tells the SPL how
+many flash blocks it needs to load. It will be rounded up to the next 64k
+boundary (the spl flash block capacity), so it does not have to be exact, but
+you must ensure that it is not less than the actual image size. If it is larger
+than the image, blocks may be needlessly loaded, but if too small, u-boot may
+only be partially loaded, resulting in a boot failure (bricked phone), so better
+to be too large. The flash_u-boot utility will work with any size image and
+write the required number of blocks, provided that the partition is large
+enough.
+
+As the first writable block on the device, block 6 seems to make the most sense
+as the flash offset for writing u-boot (and this is where PalmOS places its
+SPL). But you can place it elsewhere if you like. If you do, you need to
+adjust CONFIG_SYS_NAND_U_BOOT_OFFS accordingly, and you must ensure that blocks
+preceeding the ones containing u-boot do *not* have the magic number in oob (the
+IPL looks for this). In other words, make sure that any blocks that previously
+contained the u-boot image or PalmOS SPL are erased (and optionally written with
+something else) so that the IPL does not load it. Also make sure that the new
+u-boot starting offset is at the start of a flash partition (check the kernel
+log after loading the docg4 driver), and pass the corresponding mtd device file
+to the flash_u-boot utility.
+
+The u-boot built-in default environment is used because a writable environment
+in flash did not seem worth the cost of a 256k flash block. But adding this
+should be straightforward.
+
+
+Restoring PalmOS
+================
+
+If you backed up the contents of bootloader_part flash partition earlier, you
+should be able to restore it with the shell script shown below. The first two
+blocks of data contain the PalmOS SPL and were written in reliable mode, whereas
+the next two blocks were written in normal mode, so the script has to load and
+unload the docg4 driver. Make sure that the mtd-utils nandwrite and flash_erase
+are in your path (and are not those from busybox). Also double-check that the
+backup image file bootloader_part.orig is exactly 1081344 bytes in length. If
+not, it was not backed up correctly. Run the script as:
+
+ ./restore_bootpart bootloader_part.orig /dev/mtd1
+
+The script will take a minute or so to run. When it finishes, you may want to
+verify with nanddump that the data looks correct before you cycle power, because
+if the backup or restore failed, your phone will be bricked. Note that as a
+consequence of reliable mode, the odd-numbered 2k regions in the first two
+blocks will not exactly match the contents of the backup file, (so unfortunately
+we can't simply dump the flash contents to a file and do a binary diff with the
+original back-up image to verify that it was restored correctly). Also,
+nanddump will report uncorrectable ecc errors when it reads those regions.
+
+#!/bin/sh
+
+if [ $# -ne 2 ]; then
+ echo "usage: $0: <image file> <mtd device node>"
+ exit 1
+fi
+
+# reliable mode used for the first two blocks
+modprobe -r docg4
+modprobe docg4 ignore_badblocks=1 reliable_mode=1 || exit 1
+
+# erase all four blocks
+flash_erase $2 0 4
+
+# Program the first two blocks in reliable mode.
+# 2k (4 pages) is written at a time, skipping alternate 2k regions
+# Note that "2k" is 2112 bytes, including 64 oob bytes
+file_ofs=0
+flash_ofs=0
+page=0
+while [ $page -ne 1024 ]; do
+ dd if=$1 bs=2112 skip=$file_ofs count=1 | nandwrite -o -n -s $flash_ofs $2 - || exit 1
+ file_ofs=$((file_ofs+2))
+ flash_ofs=$((flash_ofs+0x1000))
+ page=$((page+8))
+done;
+
+# normal mode used for the next two blocks
+modprobe -r docg4
+modprobe docg4 ignore_badblocks=1 || exit 1
+dd if=$1 bs=1 skip=$file_ofs count=540672 | nandwrite -o -n -s 0x80000 $2 - || exit 1
+modprobe -r docg4
+
+TODO
+====
+
+ - Keypad support.
+ - Interactive boot menu using keypad and lcd.
+ - Add reliable mode support to the u-boot docg4 driver.
+ - U-boot command that will write a new image to the bootloader partition in
+ flash.
+ - Linux FTD support.
diff --git a/board/palmtreo680/palmtreo680.c b/board/palmtreo680/palmtreo680.c
new file mode 100644
index 0000000..f4f6e1f
--- /dev/null
+++ b/board/palmtreo680/palmtreo680.c
@@ -0,0 +1,148 @@
+/*
+ * Palm Treo 680 Support
+ *
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <nand.h>
+#include <malloc.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch-pxa/pxa.h>
+#include <asm/arch-pxa/regs-mmc.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+#include <u-boot/crc.h>
+#include <linux/mtd/docg4.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct nand_chip docg4_nand_chip;
+
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+ gd->bd->bi_boot_params = CONFIG_SYS_DRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* IPL initializes SDRAM (we're already running from it) */
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_LCD
+void lcd_enable(void)
+{
+ /*
+ * Undo the L_BIAS / gpio77 pin configuration performed by the pxa lcd
+ * driver code. We need it as an output gpio.
+ */
+ writel((readl(GAFR2_L) & ~(0xc << 24)), GAFR2_L);
+
+ /* power-up and enable the lcd */
+ writel(0x00400000, GPSR(86)); /* enable; drive high */
+ writel(0x00002000, GPSR(77)); /* power; drive high */
+ writel(0x02000000, GPCR(25)); /* enable_n; drive low */
+
+ /* turn on LCD backlight and configure PWM for reasonable brightness */
+ writel(0x00, PWM_CTRL0);
+ writel(0x1b1, PWM_PERVAL0);
+ writel(0xfd, PWM_PWDUTY0);
+ writel(0x00000040, GPSR(38)); /* backlight power on */
+}
+#endif
+
+#ifdef CONFIG_MMC
+int board_mmc_init(bd_t *bis)
+{
+ writel(1 << 10, GPSR(42)); /* power on */
+ return pxa_mmc_register(0);
+}
+#endif
+
+void board_nand_init(void)
+{
+ /* we have one 128M diskonchip G4 */
+
+ struct mtd_info *mtd = &nand_info[0];
+ struct nand_chip *nand = &docg4_nand_chip;
+ if (docg4_nand_init(mtd, nand, 0))
+ hang();
+}
+
+#ifdef CONFIG_SPL_BUILD
+void nand_boot(void)
+{
+ __attribute__((noreturn)) void (*uboot)(void);
+
+ extern const void *_start, *_end; /* boundaries of spl in memory */
+
+ /* size of spl; ipl loads this, and then a portion of u-boot */
+ const size_t spl_image_size = ((size_t)&_end - (size_t)&_start);
+
+ /* the flash offset of the blocks that are loaded by the spl */
+ const uint32_t spl_load_offset = CONFIG_SYS_NAND_U_BOOT_OFFS +
+ DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_SIZE;
+
+ /* total number of bytes loaded by IPL */
+ const size_t ipl_load_size =
+ DOCG4_IPL_LOAD_BLOCK_COUNT * DOCG4_BLOCK_CAPACITY_SPL;
+
+ /* number of bytes of u-boot proper that was loaded by the IPL */
+ const size_t ipl_uboot_load_size = ipl_load_size - spl_image_size;
+
+ /* number of remaining bytes of u-boot that the SPL must load */
+ const size_t spl_load_size =
+ CONFIG_SYS_NAND_U_BOOT_SIZE - ipl_load_size;
+
+ /* memory address where we resume loading u-boot */
+ void *const load_addr =
+ (void *)(CONFIG_SYS_NAND_U_BOOT_DST + ipl_uboot_load_size);
+
+ /*
+ * Copy the portion of u-boot already read from flash by the IPL to its
+ * correct load address.
+ */
+ memcpy((void *)CONFIG_SYS_NAND_U_BOOT_DST, &_end, ipl_uboot_load_size);
+
+ /*
+ * Resume loading u-boot where the IPL left off.
+ */
+ nand_spl_load_image(spl_load_offset, spl_load_size, load_addr);
+
+#ifdef CONFIG_NAND_ENV_DST
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST);
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+ nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+#endif
+#endif
+ /*
+ * Jump to U-Boot image
+ */
+ uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ (*uboot)();
+}
+
+void board_init_f(ulong bootflag)
+{
+ nand_boot();
+}
+
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/pandora/Kconfig b/board/pandora/Kconfig
new file mode 100644
index 0000000..0b33818
--- /dev/null
+++ b/board/pandora/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_OMAP3_PANDORA
+
+config SYS_BOARD
+ default "pandora"
+
+config SYS_CONFIG_NAME
+ default "omap3_pandora"
+
+endif
diff --git a/board/pandora/MAINTAINERS b/board/pandora/MAINTAINERS
new file mode 100644
index 0000000..e123517
--- /dev/null
+++ b/board/pandora/MAINTAINERS
@@ -0,0 +1,6 @@
+PANDORA BOARD
+M: Grazvydas Ignotas <notasas@gmail.com>
+S: Maintained
+F: board/pandora/
+F: include/configs/omap3_pandora.h
+F: configs/omap3_pandora_defconfig
diff --git a/board/pandora/Makefile b/board/pandora/Makefile
new file mode 100644
index 0000000..918b656
--- /dev/null
+++ b/board/pandora/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := pandora.o
diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c
new file mode 100644
index 0000000..59b5a7e
--- /dev/null
+++ b/board/pandora/pandora.c
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2008
+ * Grazvydas Ignotas <notasas@gmail.com>
+ *
+ * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "pandora.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TWL4030_BB_CFG_BBCHEN (1 << 4)
+#define TWL4030_BB_CFG_BBSEL_3200MV (3 << 2)
+#define TWL4030_BB_CFG_BBISEL_500UA 2
+
+#define CONTROL_WKUP_CTRL 0x48002a5c
+#define GPIO_IO_PWRDNZ (1 << 6)
+#define PBIASLITEVMODE1 (1 << 8)
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+static void set_output_gpio(unsigned int gpio, int value)
+{
+ int ret;
+
+ ret = gpio_request(gpio, "");
+ if (ret != 0) {
+ printf("could not request GPIO %u\n", gpio);
+ return;
+ }
+ ret = gpio_direction_output(gpio, value);
+ if (ret != 0)
+ printf("could not set GPIO %u to %d\n", gpio, value);
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ t2_t *t2_base = (t2_t *)T2_BASE;
+ u32 pbias_lite;
+
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
+
+ /* set up dual-voltage GPIOs to 1.8V */
+ pbias_lite = readl(&t2_base->pbias_lite);
+ pbias_lite &= ~PBIASLITEVMODE1;
+ pbias_lite |= PBIASLITEPWRDNZ1;
+ writel(pbias_lite, &t2_base->pbias_lite);
+ if (get_cpu_family() == CPU_OMAP36XX)
+ writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
+ CONTROL_WKUP_CTRL);
+
+ /* make sure audio and BT chips are in powerdown state */
+ set_output_gpio(14, 0);
+ set_output_gpio(15, 0);
+ set_output_gpio(118, 0);
+
+ /* enable USB supply */
+ set_output_gpio(164, 1);
+
+ /* wifi needs a short pulse to enter powersave state */
+ set_output_gpio(23, 1);
+ udelay(5000);
+ gpio_direction_output(23, 0);
+
+ /* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
+ TWL4030_PM_RECEIVER_BB_CFG,
+ TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
+ TWL4030_BB_CFG_BBISEL_500UA);
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_PANDORA();
+ if (get_cpu_family() == CPU_OMAP36XX) {
+ MUX_PANDORA_3730();
+ }
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
diff --git a/board/pandora/pandora.h b/board/pandora/pandora.h
new file mode 100644
index 0000000..268b929
--- /dev/null
+++ b/board/pandora/pandora.h
@@ -0,0 +1,392 @@
+/*
+ * (C) Copyright 2008
+ * Grazvydas Ignotas <notasas@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _PANDORA_H_
+#define _PANDORA_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "OMAP3 Pandora",
+ "NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_PANDORA() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*GPIO based game buttons*/\
+ MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | DIS | M4)) /*GPIO_96 - LEFT*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M4)) /*GPIO_97 - L2*/\
+ MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 - RIGHT*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M4)) /*GPIO_99 - MENU*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M4)) /*GPIO_100 - START*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M4)) /*GPIO_101 - Y*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M4)) /*GPIO_102 - L1*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M4)) /*GPIO_103 - DOWN*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M4)) /*GPIO_104 - SELECT*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M4)) /*GPIO_105 - R1*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M4)) /*GPIO_106 - B*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M4)) /*GPIO_107 - R2*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M4)) /*GPIO_109 - X*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M4)) /*GPIO_110 - UP*/\
+ MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M4)) /*GPIO_111 - A*/\
+ /*Audio Interface To External DAC (Headphone, Speakers)*/\
+ MUX_VAL(CP(MCBSP2_FSX), (IDIS | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IDIS | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP2_DR), (IDIS | PTD | DIS | M4)) /*GPIO_118*/\
+ /* - nPOWERDOWN_DAC*/\
+ /*Expansion card 1*/\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\
+ /*Expansion card 2*/\
+ MUX_VAL(CP(MMC2_CLK), (IDIS | PTD | DIS | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_CMD */\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\
+ /*SDIO Interface to WIFI Module*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /*MMC3_CLK*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
+ /*Audio Interface To Bluetooth chip*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\
+ /*Digital Interface to Bluetooth (UART)*/\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M0)) /*UART1_CTS*/\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ /*Audio Interface to Triton2 chip (TPS65950)*/\
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\
+ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M0)) /*McBSP4_DX*/\
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\
+ /*GPIO definitions for muxed pins on AV connector*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M4)) /*GPIO_144,*/\
+ /*UART2_CTS*/\
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)) /*GPIO_145,*/\
+ /*UART2_RTS*/\
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)) /*GPIO_146,*/\
+ /*UART2_TX*/\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)) /*GPIO_147,*/\
+ /*UART2_RX*/\
+ /*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\
+ /*RX pulled up to avoid noise when nothing is connected to serial port*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\
+ /*LEDs (Controlled by OMAP)*/\
+ MUX_VAL(CP(MMC1_DAT6), (IDIS | PTD | DIS | M4)) /*GPIO_128*/\
+ /* - LED_MMC1*/\
+ MUX_VAL(CP(MMC1_DAT7), (IDIS | PTD | DIS | M4)) /*GPIO_129*/\
+ /* - LED_MMC2*/\
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+ /* - LED_BT*/\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ /* - LED_WIFI*/\
+ /*Switches*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /*GPIO_176*/\
+ /* - nHOLD_SWITCH*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M4)) /*GPIO_108*/\
+ /* - nLID_SWITCH*/\
+ /*External IRQs*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTD | DIS | M4)) /*GPIO_94*/\
+ /* - nTOUCH_IRQ*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M4)) /*GPIO_21*/\
+ /* - WIFI_IRQ*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\
+ /* - nIRQ_NUB1*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
+ /* - nIRQ_NUB2*/\
+ /*Various other stuff*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | DIS | M4)) /*GPIO_163*/\
+ /* - nOC_USB5*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M4)) /*GPIO_22*/\
+ /* - MSECURE*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M4)) /*GPIO_115*/\
+ /* - POP_OVERHEAT*/\
+ /*External Resets and Enables*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_14*/\
+ /* - nHDPHN_SHUTDOWN*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_15*/\
+ /* - nBT_SHUTDOWN*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_23*/\
+ /* - nWIFI_RESET*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)) /*GPIO_157*/\
+ /* - nLCD_RESET*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ /* - RESET_NUBS*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M4)) /*GPIO_164*/\
+ /* - EN_USB_5V*/\
+ /*Spare GPIOs*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | EN | M4)) /*GPIO_58*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M4)) /*GPIO_64*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | EN | M4)) /*GPIO_65*/\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) /*GPIO_95*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /*GPIO_170*/\
+ /*HS USB OTG Port (connects to HSUSB0)*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ /*I2C Ports*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL - T2_CTRL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA - T2_CTRL*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL - NUBS*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA - NUBS*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL - T2_SR*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA - T2_SR*/\
+ /*Serial Interface (Touch, LCD control)*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTU | EN | M0)) /*McSPI1_CS0 - TOUCH*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTU | EN | M0)) /*McSPI1_CS1 - LCD*/\
+ /*HS USB HOST Port (connects to HSUSB2)*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*USB_HOST_CLK*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | EN | M3)) /*USB_HOST_STP*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_DIR*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_NXT*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_D0*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_D1*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*USB_HOST_D2*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*USB_HOST_D3*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*USB_HOST_D4*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*USB_HOST_D5*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*USB_HOST_D6*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*USB_HOST_D7*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_16*/\
+ /* - nRESET_USB_HOST*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8*/\
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ /*JTAG*/\
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
+ /*Die to Die stuff*/\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm*/\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq*/\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+#define MUX_PANDORA_3730() \
+ MUX_VAL(CP(GPIO126), (IEN | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\
+ MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\
+ MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /*GPIO_128 - LED_MMC1*/\
+ MUX_VAL(CP(GPIO129), (IDIS | PTD | DIS | M4)) /*GPIO_129 - LED_MMC2*/
+
+#endif
diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
new file mode 100644
index 0000000..251db6a
--- /dev/null
+++ b/board/pb1x00/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PB1X00
+
+config SYS_BOARD
+ default "pb1x00"
+
+config SYS_SOC
+ default "au1x00"
+
+config SYS_CONFIG_NAME
+ default "pb1x00"
+
+endif
diff --git a/board/pb1x00/MAINTAINERS b/board/pb1x00/MAINTAINERS
new file mode 100644
index 0000000..8326cc7
--- /dev/null
+++ b/board/pb1x00/MAINTAINERS
@@ -0,0 +1,6 @@
+PB1X00 BOARD
+#M: -
+S: Maintained
+F: board/pb1x00/
+F: include/configs/pb1x00.h
+F: configs/pb1000_defconfig
diff --git a/board/pb1x00/Makefile b/board/pb1x00/Makefile
new file mode 100644
index 0000000..647eb85
--- /dev/null
+++ b/board/pb1x00/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = pb1x00.o flash.o
+obj-y += lowlevel_init.o
diff --git a/board/pb1x00/README b/board/pb1x00/README
new file mode 100644
index 0000000..b1e9494
--- /dev/null
+++ b/board/pb1x00/README
@@ -0,0 +1,63 @@
+By Thomas.Lange@corelatus.se 2004-Oct-05
+----------------------------------------
+DbAu1xx0 are development boards from AMD containing
+an Alchemy AU1xx0 series cpu with mips32 core.
+Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
+
+Limitations & comments
+----------------------
+Support was originally big endian only.
+I have not tested, but several u-boot users report working
+configurations in little endian mode.
+
+I named the board dbau1x00, to allow
+support for all three development boards
+( dbau1000, dbau1100 and dbau1500 ).
+Now there is a new board called dbau1550 also, which
+should be supported RSN.
+
+I only have a dbau1000, so my testing is limited
+to this board.
+
+The board has two different flash banks, that can
+be selected via dip switch. This makes it possible
+to test new bootloaders without thrashing the YAMON
+boot loader delivered with board.
+
+NOTE! When you switch between the two boot flashes, the
+base addresses will be swapped.
+Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has
+to match the address where u-boot is located when you
+actually launch.
+
+Ethernet only supported for mac0.
+
+PCMCIA only supported for slot 0, only 3.3V.
+
+PCMCIA IDE tested with Sandisk Compact Flash and
+IBM microdrive.
+
+###################################
+######## NOTE!!!!!! #########
+###################################
+If you partition a disk on another system (e.g. laptop),
+all bytes will be swapped on 16bit level when using
+PCMCIA and running cpu in big endian mode!!!!
+
+This is probably due to an error in Au1000 chip.
+
+Solution:
+
+a) Boot via network and partition disk directly from
+dbau1x00. The endian will then be correct.
+
+b) Partition disk on "laptop" and fill it with all files
+you need. Then write a simple program that endian swaps
+whole disk,
+
+Example:
+Original "laptop" byte order:
+B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
+
+Dbau1000 byte order will then be:
+B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
diff --git a/board/pb1x00/config.mk b/board/pb1x00/config.mk
new file mode 100644
index 0000000..8f13301
--- /dev/null
+++ b/board/pb1x00/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#
+# AMD development board AMD Alchemy Pb1x00, MIPS32 core
+#
+
+# ROM version
+#CONFIG_SYS_TEXT_BASE = 0xbfc00000
+
+# SDRAM version
+CONFIG_SYS_TEXT_BASE = 0x83800000
diff --git a/board/pb1x00/flash.c b/board/pb1x00/flash.c
new file mode 100644
index 0000000..8935365
--- /dev/null
+++ b/board/pb1x00/flash.c
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+ printf ("Skipping flash_init\n");
+ return (0);
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ printf ("write_buff not implemented\n");
+ return (-1);
+}
diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S
new file mode 100644
index 0000000..b145e43
--- /dev/null
+++ b/board/pb1x00/lowlevel_init.S
@@ -0,0 +1,391 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#define AU1500_SYS_ADDR 0xB1900000
+#define sys_endian 0x0038
+#define CP0_Config0 $16
+#define MEM_1MS ((396000000/1000000) * 1000)
+
+ .text
+ .set noreorder
+ .set mips32
+
+ .globl lowlevel_init
+lowlevel_init:
+ /*
+ * Step 1) Establish CPU endian mode.
+ * NOTE: A fair amount of code is necessary on the Pb1000 to
+ * obtain the value of Switch S8.1 which is used to determine
+ * endian at run-time.
+ */
+
+ /* RCE1 */
+ li t0, MEM_STCFG1
+ li t1, 0x00000083
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME1
+ li t1, 0x33030A10
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR1
+ li t1, 0x11803E40
+ sw t1, 0(t0)
+
+ /* Set DSTRB bits so switch will read correctly */
+ li t1, 0xBE00000C
+ lw t2, 0(t1)
+ or t2, t2, 0x00000300
+ sw t2, 0(t1)
+
+ /* Check switch setting */
+ li t1, 0xBE000014
+ lw t2, 0(t1)
+ and t2, t2, 0x00000100
+ bne t2, zero, big_endian
+ nop
+
+little_endian:
+
+ /* Change Au1 core to little endian */
+ li t0, AU1500_SYS_ADDR
+ li t1, 1
+ sw t1, sys_endian(t0)
+ mfc0 t2, CP0_CONFIG
+ mtc0 t2, CP0_CONFIG
+ nop
+ nop
+
+ /* Big Endian is default so nothing to do but fall through */
+
+big_endian:
+
+ /*
+ * Step 2) Establish Status Register
+ * (set BEV, clear ERL, clear EXL, clear IE)
+ */
+ li t1, 0x00400000
+ mtc0 t1, CP0_STATUS
+
+ /*
+ * Step 3) Establish CP0 Config0
+ * (set OD, set K0=3)
+ */
+ li t1, 0x00080003
+ mtc0 t1, CP0_CONFIG
+
+ /*
+ * Step 4) Disable Watchpoint facilities
+ */
+ li t1, 0x00000000
+ mtc0 t1, CP0_WATCHLO
+ mtc0 t1, CP0_IWATCHLO
+ /*
+ * Step 5) Disable the performance counters
+ */
+ mtc0 zero, CP0_PERFORMANCE
+ nop
+
+ /*
+ * Step 6) Establish EJTAG Debug register
+ */
+ mtc0 zero, CP0_DEBUG
+ nop
+
+ /*
+ * Step 7) Establish Cause
+ * (set IV bit)
+ */
+ li t1, 0x00800000
+ mtc0 t1, CP0_CAUSE
+
+ /* Establish Wired (and Random) */
+ mtc0 zero, CP0_WIRED
+ nop
+
+ /* First setup pll:s to make serial work ok */
+ /* We have a 12 MHz crystal */
+ li t0, SYS_CPUPLL
+ li t1, 0x21 /* 396 MHz */
+ sw t1, 0(t0)
+ sync
+ nop
+ nop
+
+ /* wait 1mS for clocks to settle */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+ /* Setup AUX PLL */
+ li t0, SYS_AUXPLL
+ li t1, 8 /* 96 MHz */
+ sw t1, 0(t0) /* aux pll */
+ sync
+
+ /* Static memory controller */
+
+ /* RCE0 8MB AMD29D323 Flash */
+ li t0, MEM_STCFG0
+ li t1, 0x00001403
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME0
+ li t1, 0xFFFFFFDD
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR0
+ li t1, 0x11F83FE0
+ sw t1, 0(t0)
+
+ /* RCE1 CPLD Board Logic */
+ li t0, MEM_STCFG1
+ li t1, 0x00000083
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME1
+ li t1, 0x33030A10
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR1
+ li t1, 0x11803E40
+ sw t1, 0(t0)
+
+ /* RCE2 CPLD Board Logic */
+ li t0, MEM_STCFG2
+ li t1, 0x00000004
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME2
+ li t1, 0x08061908
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR2
+ li t1, 0x12A03FC0
+ sw t1, 0(t0)
+
+ /* RCE3 PCMCIA 250ns */
+ li t0, MEM_STCFG3
+ li t1, 0x00000002
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME3
+ li t1, 0x280E3E07
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR3
+ li t1, 0x10000000
+ sw t1, 0(t0)
+
+ sync
+
+ /* Set peripherals to a known state */
+ li t0, IC0_CFG0CLR
+ li t1, 0xFFFFFFFF
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG0CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG1CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG2CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_SRCSET
+ sw t1, 0(t0)
+
+ li t0, IC0_ASSIGNSET
+ sw t1, 0(t0)
+
+ li t0, IC0_WAKECLR
+ sw t1, 0(t0)
+
+ li t0, IC0_RISINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC0_FALLINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC0_TESTBIT
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, IC1_CFG0CLR
+ li t1, 0xFFFFFFFF
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG0CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG1CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG2CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_SRCSET
+ sw t1, 0(t0)
+
+ li t0, IC1_ASSIGNSET
+ sw t1, 0(t0)
+
+ li t0, IC1_WAKECLR
+ sw t1, 0(t0)
+
+ li t0, IC1_RISINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC1_FALLINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC1_TESTBIT
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, SYS_FREQCTRL0
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_FREQCTRL1
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_CLKSRC
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_PININPUTEN
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, 0xB1100100
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, 0xB1400100
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+
+ li t0, SYS_WAKEMSK
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_WAKESRC
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ /* wait 1mS before setup */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+
+ /*
+ * Skip memory setup if we are running from memory
+ */
+ li t0, 0x90000000
+ sub t0, ra, t0
+ bltz t0, skip_memsetup
+ nop
+
+ /*
+ * SDCS0 - Not used, for SMROM
+ * SDCS1 - 32MB Micron 48LCBM16A2
+ * SDCS2 - 32MB Micron 48LCBM16A2
+ */
+ li t0, MEM_SDMODE0
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE1
+ li t1, 0x00552229
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE2
+ li t1, 0x00552229
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR0
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR1
+ li t1, 0x001003F8
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR2
+ li t1, 0x001023F8
+ sw t1, 0(t0)
+
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x74000c30 /* Disable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDPRECMD
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDAUTOREF
+ sw zero, 0(t0)
+ sync
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x76000c30 /* Enable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD0
+ li t1, 0x00000023
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD1
+ li t1, 0x00000023
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD2
+ li t1, 0x00000023
+ sw t1, 0(t0)
+ sync
+
+ /* wait 1mS after setup */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+
+skip_memsetup:
+
+ li t0, SYS_PINFUNC
+ li t1, 0/*0x00008080*/
+ sw t1, 0(t0)
+
+ /*
+ li t0, SYS_TRIOUTCLR
+ li t1, 0x00001FFF
+ sw t1, 0(t0)
+
+ li t0, SYS_OUTPUTCLR
+ li t1, 0x00008000
+ sw t1, 0(t0)
+ */
+ sync
+
+ jr ra
+ nop
diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c
new file mode 100644
index 0000000..34814c4
--- /dev/null
+++ b/board/pb1x00/pb1x00.c
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+#include <asm/io.h>
+
+phys_size_t initdram(int board_type)
+{
+ /* Sdram is setup by assembler code */
+ /* If memory could be changed, we should return the true value here */
+ return 64*1024*1024;
+}
+
+#define BCSR_PCMCIA_PC0DRVEN 0x0010
+#define BCSR_PCMCIA_PC0RST 0x0080
+
+/* In arch/mips/cpu/cpu.c */
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
+
+int checkboard (void)
+{
+#if defined(CONFIG_IDE_PCMCIA) && 0
+ u16 status;
+#endif
+ /* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */
+ volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
+ u32 proc_id;
+
+ *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
+
+ proc_id = read_c0_prid();
+
+ switch (proc_id >> 24) {
+ case 0:
+ puts ("Board: Pb1000\n");
+ printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
+ (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+ break;
+ case 1:
+ puts ("Board: Pb1500\n");
+ printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
+ (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+ break;
+ case 2:
+ puts ("Board: Pb1100\n");
+ printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
+ (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+ break;
+ default:
+ printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
+ }
+
+ set_io_port_base(0);
+
+#if defined(CONFIG_IDE_PCMCIA) && 0
+ /* Enable 3.3 V on slot 0 ( VCC )
+ No 5V */
+ status = 4;
+ *pcmcia_bcsr = status;
+
+ status |= BCSR_PCMCIA_PC0DRVEN;
+ *pcmcia_bcsr = status;
+ au_sync();
+
+ udelay(300*1000);
+
+ status |= BCSR_PCMCIA_PC0RST;
+ *pcmcia_bcsr = status;
+ au_sync();
+
+ udelay(100*1000);
+
+ /* PCMCIA is on a 36 bit physical address.
+ We need to map it into a 32 bit addresses */
+
+#if 0
+ /* We dont need theese unless we run whole pcmcia package */
+ write_one_tlb(20, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
+ 0x3C000017, /* Lo0 */
+ 0x3C200017); /* Lo1 */
+
+ write_one_tlb(21, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
+ 0x3D000017, /* Lo0 */
+ 0x3D200017); /* Lo1 */
+#endif /* 0 */
+ write_one_tlb(22, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
+ 0x3E000017, /* Lo0 */
+ 0x3E200017); /* Lo1 */
+#endif /* CONFIG_IDE_PCMCIA */
+
+ return 0;
+}
diff --git a/board/pcs440ep/Kconfig b/board/pcs440ep/Kconfig
new file mode 100644
index 0000000..5b280f6
--- /dev/null
+++ b/board/pcs440ep/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_PCS440EP
+
+config SYS_BOARD
+ default "pcs440ep"
+
+config SYS_CONFIG_NAME
+ default "pcs440ep"
+
+endif
diff --git a/board/pcs440ep/MAINTAINERS b/board/pcs440ep/MAINTAINERS
new file mode 100644
index 0000000..6eccc85
--- /dev/null
+++ b/board/pcs440ep/MAINTAINERS
@@ -0,0 +1,6 @@
+PCS440EP BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/pcs440ep/
+F: include/configs/pcs440ep.h
+F: configs/pcs440ep_defconfig
diff --git a/board/pcs440ep/Makefile b/board/pcs440ep/Makefile
new file mode 100644
index 0000000..4fc24d6
--- /dev/null
+++ b/board/pcs440ep/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = pcs440ep.o flash.o
+extra-y += init.o
diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk
new file mode 100644
index 0000000..b90d5d0
--- /dev/null
+++ b/board/pcs440ep/config.mk
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#
+# PCS440EP board
+#
+
+# Check the U-Boot Image with a SHA1 checksum
+ALL-y += u-boot.sha1
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/pcs440ep/flash.c b/board/pcs440ep/flash.c
new file mode 100644
index 0000000..8c5e94f
--- /dev/null
+++ b/board/pcs440ep/flash.c
@@ -0,0 +1,607 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#ifndef CONFIG_SYS_FLASH_READ0
+#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
+#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
+#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
+#endif
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * Functions
+ */
+static int write_word(flash_info_t *info, ulong dest, ulong data);
+static ulong flash_get_size(vu_long *addr, flash_info_t *info);
+
+unsigned long flash_init(void)
+{
+ unsigned long size_b0, size_b1;
+ int i;
+ unsigned long base_b0, base_b1;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ base_b0 = FLASH_BASE0_PRELIM;
+ size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ }
+
+ base_b1 = FLASH_BASE1_PRELIM;
+ size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+ return (size_b0 + size_b1);
+}
+
+void flash_print_info(flash_info_t *info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ case FLASH_MAN_SST: printf ("SST "); break;
+ case FLASH_MAN_STM: printf ("ST Micro"); break;
+ case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break;
+ case FLASH_MAN_MX: printf ("MXIC "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM040: printf ("AM29LV040B (4 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n");
+ break;
+ case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n");
+ break;
+ case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n");
+ break;
+ case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n");
+ break;
+ case FLASH_SST020: printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
+ break;
+ case STM_ID_M29W040B: printf ("ST Micro M29W040B (4 Mbit, uniform sector size)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count-1))
+ size = info->start[i+1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k=0; k<size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf ("\n ");
+ /* print empty and read-only info */
+ printf (" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " ");
+#else
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+#endif
+
+ }
+ printf ("\n");
+ return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size(vu_long *addr, flash_info_t *info)
+{
+ short i;
+ short n;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE value;
+ ulong base = (ulong)addr;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
+
+ value = addr2[CONFIG_SYS_FLASH_READ0];
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
+ info->flash_id = FLASH_MAN_SST;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+ info->flash_id = FLASH_MAN_EXCEL;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE)MX_MANUFACT:
+ info->flash_id = FLASH_MAN_MX;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 0.5 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 0.5 MB */
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_M29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x0080000; /* => 0,5 MB */
+ break;
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
+ info->flash_id += FLASH_AMDL322T;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
+ info->flash_id += FLASH_AMDL322B;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
+ info->flash_id += FLASH_AMDL323T;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
+ info->flash_id += FLASH_AMDL323B;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020:
+ info->flash_id += FLASH_SST020;
+ info->sector_count = 64;
+ info->size = 0x00040000;
+ break; /* => 256 kB */
+
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040:
+ info->flash_id += FLASH_SST040;
+ info->sector_count = 128;
+ info->size = 0x00080000;
+ break; /* => 512 kB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00001000);
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+ /* set sector offsets for bottom boot block type */
+ for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
+ info->start[i] = base;
+ base += 8 << 10;
+ }
+ while (i < info->sector_count) { /* 64k regular sectors */
+ info->start[i] = base;
+ base += 64 << 10;
+ ++i;
+ }
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+ ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+ /* set sector offsets for top boot block type */
+ base += info->size;
+ i = info->sector_count;
+ for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
+ base -= 8 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ while (i > 0) { /* 64k regular sectors */
+ base -= 64 << 10;
+ --i;
+ info->start[i] = base;
+ }
+ } else {
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+ if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+ *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf ("- missing\n");
+ else
+ printf ("- no sectors to erase\n");
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect)
+ if (info->protect[sect])
+ prot++;
+
+ if (prot)
+ printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+ else
+ printf ("\n");
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
+
+ /* re-enable interrupts if necessary */
+ if (flag) {
+ enable_interrupts();
+ flag = 0;
+ }
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+ (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+ return (1);
+ }
+ } else {
+ if (sect == s_first) {
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ }
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ }
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+ while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+DONE:
+ /* reset to read mode */
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+ addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+
+ printf (" done\n");
+ return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i)
+ data = (data << 8) | *src++;
+ if ((rc = write_word(info, wp, data)) != 0)
+ return (rc);
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0)
+ return (0);
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp)
+ data = (data << 8) | (*(uchar *)cp);
+
+ return (write_word(info, wp, data));
+}
+
+/*
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word(flash_info_t *info, ulong dest, ulong data)
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data;
+ ulong start;
+ int flag;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data)
+ return (2);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+ (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+ return (1);
+ }
+ }
+
+ return (0);
+}
diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S
new file mode 100644
index 0000000..c0e83de
--- /dev/null
+++ b/board/pcs440ep/init.S
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
+
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR detection
+ * routine.
+ */
+
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
+
+ /* PCI */
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
+
+ /* USB 2.0 Device */
+ tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
+
+ tlbtab_end
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
new file mode 100644
index 0000000..267c001
--- /dev/null
+++ b/board/pcs440ep/pcs440ep.c
@@ -0,0 +1,755 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <malloc.h>
+#include <command.h>
+#include <crc.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <status_led.h>
+#include <u-boot/sha1.h>
+#include <asm/io.h>
+#include <net.h>
+#include <ata.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+unsigned char sha1_checksum[SHA1_SUM_LEN];
+
+/* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */
+unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
+ 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
+
+static void set_leds (int val)
+{
+ out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27));
+}
+
+#define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27)
+
+void __led_init (led_id_t mask, int state)
+{
+ int val = GET_LEDS;
+
+ if (state == STATUS_LED_ON)
+ val |= mask;
+ else
+ val &= ~mask;
+ set_leds (val);
+}
+
+void __led_set (led_id_t mask, int state)
+{
+ int val = GET_LEDS;
+
+ if (state == STATUS_LED_ON)
+ val |= mask;
+ else if (state == STATUS_LED_OFF)
+ val &= ~mask;
+ set_leds (val);
+}
+
+void __led_toggle (led_id_t mask)
+{
+ int val = GET_LEDS;
+
+ val ^= mask;
+ set_leds (val);
+}
+
+static void status_led_blink (void)
+{
+ int i;
+ int val = GET_LEDS;
+
+ /* set all LED which are on, to state BLINKING */
+ for (i = 0; i < 4; i++) {
+ if (val & 0x01) status_led_set (3 - i, STATUS_LED_BLINKING);
+ else status_led_set (3 - i, STATUS_LED_OFF);
+ val = val >> 1;
+ }
+}
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress (int val)
+{
+ /* find all valid Codes for val in README */
+ if (val == -BOOTSTAGE_ID_NEED_RESET)
+ return;
+ if (val < 0) {
+ /* smthing goes wrong */
+ status_led_blink ();
+ return;
+ }
+ switch (val) {
+ case BOOTSTAGE_ID_CHECK_MAGIC:
+ /* validating Image */
+ status_led_set(0, STATUS_LED_OFF);
+ status_led_set(1, STATUS_LED_ON);
+ status_led_set(2, STATUS_LED_ON);
+ break;
+ case BOOTSTAGE_ID_RUN_OS:
+ status_led_set(0, STATUS_LED_ON);
+ status_led_set(1, STATUS_LED_ON);
+ status_led_set(2, STATUS_LED_ON);
+ break;
+#if 0
+ case BOOTSTAGE_ID_NET_ETH_START:
+ /* starting Ethernet configuration */
+ status_led_set(0, STATUS_LED_OFF);
+ status_led_set(1, STATUS_LED_OFF);
+ status_led_set(2, STATUS_LED_ON);
+ break;
+#endif
+ case BOOTSTAGE_ID_NET_START:
+ /* loading Image */
+ status_led_set(0, STATUS_LED_ON);
+ status_led_set(1, STATUS_LED_OFF);
+ status_led_set(2, STATUS_LED_ON);
+ break;
+ }
+}
+#endif
+
+int board_early_init_f(void)
+{
+ register uint reg;
+
+ set_leds(0); /* display boot info counter */
+
+ /*--------------------------------------------------------------------
+ * Setup the external bus controller/chip selects
+ *-------------------------------------------------------------------*/
+ mtdcr(EBC0_CFGADDR, EBC0_CFG);
+ reg = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
+
+ /*--------------------------------------------------------------------
+ * GPIO's are alreay setup in arch/powerpc/cpu/ppc4xx/cpu_init.c
+ * via define from board config file.
+ *-------------------------------------------------------------------*/
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */
+ mtdcr(UIC0PR, 0xfffffe1f); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x01c00000); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ /*--------------------------------------------------------------------
+ * Setup other serial configuration
+ *-------------------------------------------------------------------*/
+ mfsdr(SDR0_PCI0, reg);
+ mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
+ mtsdr(SDR0_PFC0, 0x00000000); /* Pin function: enable GPIO49-63 */
+ mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */
+
+ return 0;
+}
+
+#define EEPROM_LEN 256
+static void load_ethaddr(void)
+{
+ int ok_ethaddr, ok_eth1addr;
+ int ret;
+ uchar buf[EEPROM_LEN];
+ char *use_eeprom;
+ u16 checksumcrc16 = 0;
+
+ /* If the env is sane, then nothing for us to do */
+ ok_ethaddr = eth_getenv_enetaddr("ethaddr", buf);
+ ok_eth1addr = eth_getenv_enetaddr("eth1addr", buf);
+ if (ok_ethaddr && ok_eth1addr)
+ return;
+
+ /* read the MACs from EEprom */
+ status_led_set (0, STATUS_LED_ON);
+ status_led_set (1, STATUS_LED_ON);
+ ret = eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 0, buf, EEPROM_LEN);
+ if (ret == 0) {
+ checksumcrc16 = cyg_crc16 (buf, EEPROM_LEN - 2);
+ /* check, if the EEprom is programmed:
+ * - The Prefix(Byte 0,1,2) is equal to "ATR"
+ * - The checksum, stored in the last 2 Bytes, is correct
+ */
+ if ((strncmp ((char *)buf,"ATR",3) != 0) ||
+ ((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) ||
+ ((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) {
+ /* EEprom is not programmed */
+ printf("%s: EEPROM Checksum not OK\n", __FUNCTION__);
+ } else {
+ /* get the MACs */
+ if (!ok_ethaddr)
+ eth_setenv_enetaddr("ethaddr", &buf[3]);
+ if (!ok_eth1addr)
+ eth_setenv_enetaddr("eth1addr", &buf[9]);
+ return;
+ }
+ }
+
+ /* some error reading the EEprom */
+ if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) {
+ /* dont use bootcmd */
+ setenv("bootdelay", "-1");
+ return;
+ }
+ /* == default ? use standard */
+ if (strncmp (use_eeprom, "default", 7) == 0) {
+ return;
+ }
+ /* Env doesnt exist -> hang */
+ status_led_blink ();
+ /* here we do this "handy" because we have no interrupts
+ at this time */
+ puts ("### EEPROM ERROR ### Please RESET the board ###\n");
+ for (;;) {
+ __led_toggle (12);
+ udelay (100000);
+ }
+ return;
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+struct kbd_data_t {
+ char s1;
+ char s2;
+};
+
+struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
+{
+ char *val;
+ unsigned long tmp;
+
+ /* use the DIPs for some bootoptions */
+ val = getenv (ENV_NAME_DIP);
+ tmp = simple_strtoul (val, NULL, 16);
+
+ kbd_data->s2 = (tmp & 0x0f);
+ kbd_data->s1 = (tmp & 0xf0) >> 4;
+ return kbd_data;
+}
+
+static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
+{
+ char s1 = str[0];
+
+ if (s1 >= '0' && s1 <= '9')
+ s1 -= '0';
+ else if (s1 >= 'a' && s1 <= 'f')
+ s1 = s1 - 'a' + 10;
+ else if (s1 >= 'A' && s1 <= 'F')
+ s1 = s1 - 'A' + 10;
+ else
+ return -1;
+
+ if (s1 != kbd_data->s1) return -1;
+
+ s1 = str[1];
+ if (s1 >= '0' && s1 <= '9')
+ s1 -= '0';
+ else if (s1 >= 'a' && s1 <= 'f')
+ s1 = s1 - 'a' + 10;
+ else if (s1 >= 'A' && s1 <= 'F')
+ s1 = s1 - 'A' + 10;
+ else
+ return -1;
+
+ if (s1 != kbd_data->s2) return -1;
+ return 0;
+}
+
+static char *key_match (const struct kbd_data_t *kbd_data)
+{
+ char magic[sizeof (kbd_magic_prefix) + 1];
+ char *suffix;
+ char *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can be appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+ kbd_magic_keys = "";
+
+ /* loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix = kbd_magic_keys; *suffix ||
+ suffix == kbd_magic_keys; ++suffix) {
+ sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+ if (compare_magic (kbd_data, getenv (magic)) == 0) {
+ char cmd_name[sizeof (kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+ cmd = getenv (cmd_name);
+
+ return (cmd);
+ }
+ }
+ return (NULL);
+}
+
+#endif /* CONFIG_PREBOOT */
+
+static int pcs440ep_readinputs (void)
+{
+ int i;
+ char value[20];
+
+ /* read the inputs and set the Envvars */
+ /* Revision Level Bit 26 - 29 */
+ i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2);
+ i = swapbits[i];
+ sprintf (value, "%02x", i);
+ setenv (ENV_NAME_REVLEV, value);
+ /* Solder Switch Bit 30 - 33 */
+ i = (in32 (GPIO0_IR) & 0x00000003) << 2;
+ i += (in32 (GPIO1_IR) & 0xc0000000) >> 30;
+ i = swapbits[i];
+ sprintf (value, "%02x", i);
+ setenv (ENV_NAME_SOLDER, value);
+ /* DIP Switch Bit 49 - 56 */
+ i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7);
+ i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4];
+ sprintf (value, "%02x", i);
+ setenv (ENV_NAME_DIP, value);
+ return 0;
+}
+
+
+#if defined(CONFIG_SHA1_CHECK_UB_IMG)
+/*************************************************************************
+ * calculate a SHA1 sum for the U-Boot image in Flash.
+ *
+ ************************************************************************/
+static int pcs440ep_sha1 (int docheck)
+{
+ unsigned char *data;
+ unsigned char *ptroff;
+ unsigned char output[20];
+ unsigned char org[20];
+ int i, len = CONFIG_SHA1_LEN;
+
+ memcpy ((char *)CONFIG_SYS_LOAD_ADDR, (char *)CONFIG_SHA1_START, len);
+ data = (unsigned char *)CONFIG_SYS_LOAD_ADDR;
+ ptroff = &data[len + SHA1_SUM_POS];
+
+ for (i = 0; i < SHA1_SUM_LEN; i++) {
+ org[i] = ptroff[i];
+ ptroff[i] = 0;
+ }
+
+ sha1_csum ((unsigned char *) data, len, (unsigned char *)output);
+
+ if (docheck == 2) {
+ for (i = 0; i < 20 ; i++) {
+ printf("%02X ", output[i]);
+ }
+ printf("\n");
+ }
+ if (docheck == 1) {
+ for (i = 0; i < 20 ; i++) {
+ if (org[i] != output[i]) return 1;
+ }
+ }
+ return 0;
+}
+
+/*************************************************************************
+ * do some checks after the SHA1 checksum from the U-Boot Image was
+ * calculated.
+ *
+ ************************************************************************/
+static void pcs440ep_checksha1 (void)
+{
+ int ret;
+ char *cs_test;
+
+ status_led_set (0, STATUS_LED_OFF);
+ status_led_set (1, STATUS_LED_OFF);
+ status_led_set (2, STATUS_LED_ON);
+ ret = pcs440ep_sha1 (1);
+ if (ret == 0) return;
+
+ if ((cs_test = getenv ("cs_test")) == NULL) {
+ /* Env doesnt exist -> hang */
+ status_led_blink ();
+ /* here we do this "handy" because we have no interrupts
+ at this time */
+ puts ("### SHA1 ERROR ### Please RESET the board ###\n");
+ for (;;) {
+ __led_toggle (2);
+ udelay (100000);
+ }
+ }
+
+ if (strncmp (cs_test, "off", 3) == 0) {
+ printf ("SHA1 U-Boot sum NOT ok!\n");
+ setenv ("bootdelay", "-1");
+ }
+}
+#else
+static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);}
+#endif
+
+int misc_init_r (void)
+{
+ uint pbcr;
+ int size_val = 0;
+
+ load_ethaddr();
+
+ /* Re-do sizing to get full correct info */
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ switch (gd->bd->bi_flashsize) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ case 32 << 20:
+ size_val = 5;
+ break;
+ case 64 << 20:
+ size_val = 6;
+ break;
+ case 128 << 20:
+ size_val = 7;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ mtdcr(EBC0_CFGDATA, pbcr);
+
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[1]);
+
+ /* Env protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[1]);
+
+ pcs440ep_readinputs ();
+ pcs440ep_checksha1 ();
+#ifdef CONFIG_PREBOOT
+ {
+ struct kbd_data_t kbd_data;
+ /* Decode keys */
+ char *str = strdup (key_match (get_keys (&kbd_data)));
+ /* Set or delete definition */
+ setenv ("preboot", str);
+ free (str);
+ }
+#endif /* CONFIG_PREBOOT */
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: PCS440EP");
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return (0);
+}
+
+void spd_ddr_init_hang (void)
+{
+ status_led_set (0, STATUS_LED_OFF);
+ status_led_set (1, STATUS_LED_ON);
+ /* we cannot use hang() because we are still running from
+ Flash, and so the status_led driver is not initialized */
+ puts ("### SDRAM ERROR ### Please RESET the board ###\n");
+ for (;;) {
+ __led_toggle (4);
+ udelay (100000);
+ }
+}
+
+phys_size_t initdram (int board_type)
+{
+ long dram_size = 0;
+
+ status_led_set (0, STATUS_LED_ON);
+ status_led_set (1, STATUS_LED_OFF);
+ dram_size = spd_sdram();
+ status_led_set (0, STATUS_LED_OFF);
+ status_led_set (1, STATUS_LED_ON);
+ if (dram_size == 0) {
+ hang();
+ }
+
+ return dram_size;
+}
+
+/*************************************************************************
+ * hw_watchdog_reset
+ *
+ * This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+
+}
+#endif
+
+/*************************************************************************
+ * "led" Commando for the U-Boot shell
+ *
+ ************************************************************************/
+int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rcode = 0, i;
+ ulong pattern = 0;
+
+ pattern = simple_strtoul (argv[1], NULL, 16);
+ if (pattern > 0x400) {
+ int val = GET_LEDS;
+ printf ("led: %x\n", val);
+ return rcode;
+ }
+ if (pattern > 0x200) {
+ status_led_blink ();
+ hang ();
+ return rcode;
+ }
+ if (pattern > 0x100) {
+ status_led_blink ();
+ return rcode;
+ }
+ pattern &= 0x0f;
+ for (i = 0; i < 4; i++) {
+ if (pattern & 0x01) status_led_set (i, STATUS_LED_ON);
+ else status_led_set (i, STATUS_LED_OFF);
+ pattern = pattern >> 1;
+ }
+ return rcode;
+}
+
+U_BOOT_CMD(
+ led, 2, 1, do_led,
+ "set the DIAG-LED",
+ "[bitmask] 0x01 = DIAG 1 on\n"
+ " 0x02 = DIAG 2 on\n"
+ " 0x04 = DIAG 3 on\n"
+ " 0x08 = DIAG 4 on\n"
+ " > 0x100 set the LED, who are on, to state blinking"
+);
+
+#if defined(CONFIG_SHA1_CHECK_UB_IMG)
+/*************************************************************************
+ * "sha1" Commando for the U-Boot shell
+ *
+ ************************************************************************/
+int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rcode = -1;
+
+ if (argc < 2) {
+usage:
+ return cmd_usage(cmdtp);
+ }
+
+ if (argc >= 3) {
+ unsigned char *data;
+ unsigned char output[20];
+ int len;
+ int i;
+
+ data = (unsigned char *)simple_strtoul (argv[1], NULL, 16);
+ len = simple_strtoul (argv[2], NULL, 16);
+ sha1_csum (data, len, (unsigned char *)output);
+ printf ("U-Boot sum:\n");
+ for (i = 0; i < 20 ; i++) {
+ printf ("%02X ", output[i]);
+ }
+ printf ("\n");
+ if (argc == 4) {
+ data = (unsigned char *)simple_strtoul (argv[3], NULL, 16);
+ memcpy (data, output, 20);
+ }
+ return 0;
+ }
+ if (argc == 2) {
+ char *ptr = argv[1];
+ if (*ptr != '-') goto usage;
+ ptr++;
+ if ((*ptr == 'c') || (*ptr == 'C')) {
+ rcode = pcs440ep_sha1 (1);
+ printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : "");
+ } else if ((*ptr == 'p') || (*ptr == 'P')) {
+ rcode = pcs440ep_sha1 (2);
+ } else {
+ rcode = pcs440ep_sha1 (0);
+ }
+ return rcode;
+ }
+ return rcode;
+}
+
+U_BOOT_CMD(
+ sha1, 4, 1, do_sha1,
+ "calculate the SHA1 Sum",
+ "address len [addr] calculate the SHA1 sum [save at addr]\n"
+ " -p calculate the SHA1 sum from the U-Boot image in flash and print\n"
+ " -c check the U-Boot image in flash"
+);
+#endif
+
+#if defined (CONFIG_CMD_IDE)
+/* These addresses need to be shifted one place to the left
+ * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
+ * These values are shifted
+ */
+void inline ide_outb(int dev, int port, unsigned char val)
+{
+ debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
+ dev, port, val, (ATA_CURR_BASE(dev)+port));
+
+ out_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)), val);
+}
+unsigned char inline ide_inb(int dev, int port)
+{
+ uchar val;
+ val = in_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)));
+ debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
+ dev, port, (ATA_CURR_BASE(dev)+port), val);
+ return (val);
+}
+#endif
+
+#ifdef CONFIG_IDE_PREINIT
+int ide_preinit (void)
+{
+ /* Set True IDE Mode */
+ out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000));
+ out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
+ out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040));
+ udelay (100000);
+ return 0;
+}
+#endif
+
+#if defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+void ide_set_reset (int idereset)
+{
+ debug ("ide_reset(%d)\n", idereset);
+ if (idereset == 0) {
+ out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
+ } else {
+ out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000));
+ }
+ udelay (10000);
+}
+#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+
+/* this is motly the same as it should, causing a little code duplication */
+#if defined(CONFIG_CMD_IDE)
+#define EIEIO __asm__ volatile ("eieio")
+
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+ volatile ushort *pbuf =
+ (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ ushort *dbuf = (ushort *) sect_buf;
+
+ debug("in input swap data base for read is %lx\n",
+ (unsigned long) pbuf);
+
+ while (words--) {
+ *dbuf++ = *pbuf;
+ *dbuf++ = *pbuf;
+ }
+}
+
+void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *) sect_buf;
+ while (words--) {
+ EIEIO;
+ *pbuf = ld_le16(dbuf++);
+ EIEIO;
+ *pbuf = ld_le16(dbuf++);
+ }
+}
+
+void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *) sect_buf;
+
+ debug("in input data base for read is %lx\n", (unsigned long) pbuf);
+
+ while (words--) {
+ EIEIO;
+ *dbuf++ = ld_le16(pbuf);
+ EIEIO;
+ *dbuf++ = ld_le16(pbuf);
+ }
+}
+
+#endif
diff --git a/board/pdm360ng/Kconfig b/board/pdm360ng/Kconfig
new file mode 100644
index 0000000..33173a0
--- /dev/null
+++ b/board/pdm360ng/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_PDM360NG
+
+config SYS_BOARD
+ default "pdm360ng"
+
+config SYS_CONFIG_NAME
+ default "pdm360ng"
+
+endif
diff --git a/board/pdm360ng/MAINTAINERS b/board/pdm360ng/MAINTAINERS
new file mode 100644
index 0000000..5c99f59
--- /dev/null
+++ b/board/pdm360ng/MAINTAINERS
@@ -0,0 +1,6 @@
+PDM360NG BOARD
+M: Michael Weiss <michael.weiss@ifm.com>
+S: Maintained
+F: board/pdm360ng/
+F: include/configs/pdm360ng.h
+F: configs/pdm360ng_defconfig
diff --git a/board/pdm360ng/Makefile b/board/pdm360ng/Makefile
new file mode 100644
index 0000000..99201a4
--- /dev/null
+++ b/board/pdm360ng/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := pdm360ng.o
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
new file mode 100644
index 0000000..81f3024
--- /dev/null
+++ b/board/pdm360ng/pdm360ng.c
@@ -0,0 +1,609 @@
+/*
+ * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
+ *
+ * (C) Copyright 2009-2010
+ * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#include <flash.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+#include <serial.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[];
+ulong flash_get_size (phys_addr_t base, int banknum);
+
+sdram_conf_t mddrc_config[] = {
+ {
+ (512 << 20), /* 512 MB RAM configuration */
+ {
+ CONFIG_SYS_MDDRC_SYS_CFG,
+ CONFIG_SYS_MDDRC_TIME_CFG0,
+ CONFIG_SYS_MDDRC_TIME_CFG1,
+ CONFIG_SYS_MDDRC_TIME_CFG2
+ }
+ },
+ {
+ (128 << 20), /* 128 MB RAM configuration */
+ {
+ CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
+ CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
+ CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
+ CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
+ }
+ },
+};
+
+phys_size_t initdram (int board_type)
+{
+ int i;
+ u32 msize = 0;
+ u32 pdm360ng_init_seq[] = {
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_MICRON_INIT_DEV_OP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_EM2,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_EM2,
+ CONFIG_SYS_DDRCMD_EM3,
+ CONFIG_SYS_DDRCMD_EN_DLL,
+ CONFIG_SYS_DDRCMD_RES_DLL,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_MICRON_INIT_DEV_OP,
+ CONFIG_SYS_DDRCMD_OCD_DEFAULT,
+ CONFIG_SYS_DDRCMD_OCD_EXIT,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_NOP
+ };
+
+ for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
+ msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
+ ARRAY_SIZE(pdm360ng_init_seq));
+ if (msize == mddrc_config[i].size)
+ break;
+ }
+
+ return msize;
+}
+
+static int set_lcd_brightness(char *);
+
+int misc_init_r(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ /*
+ * Re-configure flash setup using auto-detected info
+ */
+ if (flash_info[1].size > 0) {
+ out_be32(&im->sysconf.lpcs1aw,
+ CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
+ CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
+ flash_info[1].size));
+ sync_law(&im->sysconf.lpcs1aw);
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
+ } else {
+ /* Disable Bank 1 */
+ out_be32(&im->sysconf.lpcs1aw, 0x01000100);
+ sync_law(&im->sysconf.lpcs1aw);
+ }
+
+ out_be32(&im->sysconf.lpcs0aw,
+ CSAW_START(gd->bd->bi_flashstart) |
+ CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
+ sync_law(&im->sysconf.lpcs0aw);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size (gd->bd->bi_flashstart, 0);
+
+ /*
+ * Re-do flash protection upon new addresses
+ */
+ flash_protect (FLAG_PROTECT_CLEAR,
+ gd->bd->bi_flashstart, 0xffffffff,
+ &flash_info[0]);
+
+ /* Monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+ &flash_info[0]);
+
+ /* Environment protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+ /* Redundant environment protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+#ifdef CONFIG_FSL_DIU_FB
+ set_lcd_brightness(0);
+ /* Switch LCD-Backlight and LVDS-Interface on */
+ setbits_be32(&im->gpio.gpdir, 0x01040000);
+ clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
+#endif
+
+#if defined(CONFIG_HARD_I2C)
+ if (!getenv("ethaddr")) {
+ uchar buf[6];
+ uchar ifm_oui[3] = { 0, 2, 1, };
+ int ret;
+
+ /* I2C-0 for on-board eeprom */
+ i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
+
+ /* Read ethaddr from EEPROM */
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
+ if (ret != 0) {
+ printf("Error: Unable to read MAC from I2C"
+ " EEPROM at address %02X:%02X\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
+ return 1;
+ }
+
+ /* Owned by IFM ? */
+ if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
+ printf("Illegal MAC address in EEPROM: %pM\n", buf);
+ return 1;
+ }
+
+ eth_setenv_enetaddr("ethaddr", buf);
+ }
+#endif /* defined(CONFIG_HARD_I2C) */
+
+ return 0;
+}
+
+static iopin_t ioregs_init[] = {
+ /* FUNC1=LPC_CS4 */
+ {
+ offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
+ IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=GPIO10 */
+ {
+ offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC1=CAN3_TX */
+ {
+ offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO14 */
+ {
+ offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
+ /* DIU_LD22-DIU_LD23 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
+ /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
+ /* VIU_DATA0-VIU_DATA2 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=FEC_TXD_0 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
+ /* VIU_DATA3, VIU_DATA4 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
+ /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
+ /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
+ /* DIU_LD00-DIU_LD21 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
+ /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
+ {
+ offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC2=CAN3_RX */
+ {
+ offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* Sets lowest slew on 2 CAN_TX Pins*/
+ {
+ offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
+ /* CAN4_TX, CAN4_RX */
+ {
+ offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
+ /* GPIO8, GPIO9 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
+ /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
+ /* FEC_RXD_3, FEC_RXD_2 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=GPIO17 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
+ /* GPIO2, GPIO20, GPIO21 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC2=VIU_PIX_CLK */
+ {
+ offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
+ /* GPIO24, GPIO25 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC1=NFC_CE2 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
+ IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
+ /* VIU_DATA5-VIU_DATA9 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
+ /* LPC_TSIZ1-LPC_TSIZ2 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=LPC_TS */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=GPIO16 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
+ /* GPIO18-GPIO19, GPT7/GPIO7 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO0/GPT0 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
+ /* GPIO11, GPIO2, GPIO12, GPIO13 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC2=DIU_DE */
+ {
+ offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ }
+};
+
+int checkboard (void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ puts("Board: PDM360NG\n");
+
+ /* initialize function mux & slew rate IO inter alia on IO Pins */
+
+ iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+ /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
+ setbits_be32(&im->io_ctrl.io_control_gp,
+ (1 << 0) | /* GP_MUX7->GPIO7 */
+ (1 << 5)); /* GP_MUX2->GPIO2 */
+
+ /* configure GPIO24 (VIU_CE), output/high */
+ setbits_be32(&im->gpio.gpdir, 0x80);
+ setbits_be32(&im->gpio.gpdat, 0x80);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+struct node_info nodes[] = {
+ { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
+ { "cfi-flash", MTD_DEV_TYPE_NOR, },
+};
+#endif
+
+#if defined(CONFIG_VIDEO)
+/*
+ * EDID block has been generated using Phoenix EDID Designer 1.3.
+ * This tool creates a text file containing:
+ *
+ * EDID BYTES:
+ * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
+ * ------------------------------------------------
+ * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
+ * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
+ * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
+ * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
+ * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
+ * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
+ * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
+ * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
+ *
+ * Then this data has been manually converted to the char
+ * array below.
+ */
+static unsigned char edid_buf[128] = {
+ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
+ 0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
+ 0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
+ 0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
+ 0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
+ 0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
+ 0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
+ 0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
+ 0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
+ 0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
+ 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
+ 0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+ 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
+};
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[8];
+ int rc, i = 0;
+
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+#if defined(CONFIG_VIDEO)
+ fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
+#endif
+
+ /* Fixup NOR FLASH mapping */
+ val[i++] = 0; /* chip select number */
+ val[i++] = 0; /* always 0 */
+ val[i++] = gd->bd->bi_flashstart;
+ val[i++] = gd->bd->bi_flashsize;
+
+ /* Fixup MRAM mapping */
+ val[i++] = 2; /* chip select number */
+ val[i++] = 0; /* always 0 */
+ val[i++] = CONFIG_SYS_MRAM_BASE;
+ val[i++] = CONFIG_SYS_MRAM_SIZE;
+
+ rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
+ val, i * sizeof(u32), 1);
+ if (rc)
+ printf("Unable to update localbus ranges, err=%s\n",
+ fdt_strerror(rc));
+
+ /* Fixup reg property in NOR Flash node */
+ i = 0;
+ val[i++] = 0; /* always 0 */
+ val[i++] = 0; /* start at offset 0 */
+ val[i++] = flash_info[0].size; /* size of Bank 0 */
+
+ /* Second Bank available? */
+ if (flash_info[1].size > 0) {
+ val[i++] = 0; /* always 0 */
+ val[i++] = flash_info[0].size; /* offset of Bank 1 */
+ val[i++] = flash_info[1].size; /* size of Bank 1 */
+ }
+
+ rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
+ val, i * sizeof(u32), 1);
+ if (rc)
+ printf("Unable to update flash reg property, err=%s\n",
+ fdt_strerror(rc));
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+/*
+ * If argument is NULL, set the LCD brightness to the
+ * value from "brightness" environment variable. Set
+ * the LCD brightness to the value specified by the
+ * argument otherwise. Default brightness is zero.
+ */
+#define MAX_BRIGHTNESS 99
+static int set_lcd_brightness(char *brightness)
+{
+ struct stdio_dev *cop_port;
+ char *env;
+ char cmd_buf[20];
+ int val = 0;
+ int cs = 0;
+ int len, i;
+
+ if (brightness) {
+ val = simple_strtol(brightness, NULL, 10);
+ } else {
+ env = getenv("brightness");
+ if (env)
+ val = simple_strtol(env, NULL, 10);
+ }
+
+ if (val < 0)
+ val = 0;
+
+ if (val > MAX_BRIGHTNESS)
+ val = MAX_BRIGHTNESS;
+
+ sprintf(cmd_buf, "$SB;%04d;", val);
+
+ len = strlen(cmd_buf);
+ for (i = 1; i <= len; i++)
+ cs += cmd_buf[i];
+
+ cs = (~cs + 1) & 0xff;
+ sprintf(cmd_buf + len, "%02X\n", cs);
+
+ /* IO Coprocessor communication */
+ cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
+ if (!cop_port) {
+ printf("Error: Can't open IO Coprocessor port.\n");
+ return -1;
+ }
+
+ debug("%s: cmd: %s", __func__, cmd_buf);
+ write_port(cop_port, cmd_buf);
+ /*
+ * Wait for transmission and maybe response data
+ * before closing the port.
+ */
+ udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
+ memset(cmd_buf, 0, sizeof(cmd_buf));
+ len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
+ if (len)
+ printf("Error: %s\n", cmd_buf);
+
+ close_port(4);
+
+ return 0;
+}
+
+static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ return set_lcd_brightness(argv[1]);
+}
+
+U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
+ "set LCD brightness",
+ "<brightness> - set LCD backlight level to <brightness>.\n"
+);
diff --git a/board/phytec/pcm030/Kconfig b/board/phytec/pcm030/Kconfig
new file mode 100644
index 0000000..3a3eab8
--- /dev/null
+++ b/board/phytec/pcm030/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PCM030
+
+config SYS_BOARD
+ default "pcm030"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_CONFIG_NAME
+ default "pcm030"
+
+endif
diff --git a/board/phytec/pcm030/MAINTAINERS b/board/phytec/pcm030/MAINTAINERS
new file mode 100644
index 0000000..4e2ab0d
--- /dev/null
+++ b/board/phytec/pcm030/MAINTAINERS
@@ -0,0 +1,7 @@
+PCM030 BOARD
+M: Jon Smirl <jonsmirl@gmail.com>
+S: Maintained
+F: board/phytec/pcm030/
+F: include/configs/pcm030.h
+F: configs/pcm030_defconfig
+F: configs/pcm030_LOWBOOT_defconfig
diff --git a/board/phytec/pcm030/Makefile b/board/phytec/pcm030/Makefile
new file mode 100644
index 0000000..2bb49dc
--- /dev/null
+++ b/board/phytec/pcm030/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := pcm030.o
diff --git a/board/phytec/pcm030/README b/board/phytec/pcm030/README
new file mode 100644
index 0000000..05faab6
--- /dev/null
+++ b/board/phytec/pcm030/README
@@ -0,0 +1,42 @@
+To build RAMBOOT, replace this section the main Makefile
+
+pcm030_config \
+pcm030_RAMBOOT_config \
+pcm030_LOWBOOT_config: unconfig
+ @ >include/config.h
+ @[ -z "$(findstring LOWBOOT_,$@)" ] || \
+ { echo "CONFIG_SYS_TEXT_BASE = 0xFF000000" >board/phytec/pcm030/config.tmp ; \
+ echo "... with LOWBOOT configuration" ; \
+ }
+ @[ -z "$(findstring RAMBOOT_,$@)" ] || \
+ { echo "CONFIG_SYS_TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\
+ config.tmp ; \
+ echo "... with RAMBOOT configuration" ; \
+ echo "... remember to make sure that MBAR is already \
+ switched to 0xF0000000 !!!" ; \
+ }
+ @$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec
+ @ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1"
+
+Alternative SDRAM settings:
+
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x715f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+
+/* Settings for XLB = 99 MHz */
+#define SDRAM_MODE 0x008D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x714b0f00
+#define SDRAM_CONFIG1 0x63611730
+#define SDRAM_CONFIG2 0x47670000
+
+The board ships default with the environment in EEPROM
+Moving the environment to flash can be more reliable
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xfe0000)
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_SECT_SIZE 0x20000
diff --git a/board/phytec/pcm030/mt46v32m16-75.h b/board/phytec/pcm030/mt46v32m16-75.h
new file mode 100644
index 0000000..47fc7c0
--- /dev/null
+++ b/board/phytec/pcm030/mt46v32m16-75.h
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * Eric Schumann, Phytec Messtechnik
+ * adapted for mt46v32m16-75 DDR-RAM
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x71500F00
+#define SDRAM_CONFIG1 0x73711930
+#define SDRAM_CONFIG2 0x47770000
+
+#define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */
diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c
new file mode 100644
index 0000000..ed41de1
--- /dev/null
+++ b/board/phytec/pcm030/pcm030.c
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2006
+ * Eric Schumann, Phytec Messtechnik GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/io.h>
+
+#include "mt46v32m16-75.h"
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+ volatile struct mpc5xxx_cdm *cdm =
+ (struct mpc5xxx_cdm *)MPC5XXX_CDM;
+ volatile struct mpc5xxx_sdram *sdram =
+ (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ out_be32 (&sdram->ctrl,
+ (SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
+
+ /* precharge all banks */
+ out_be32 (&sdram->ctrl,
+ (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
+
+#ifdef SDRAM_DDR
+ /* set mode register: extended mode */
+ out_be32 (&sdram->mode, (SDRAM_EMODE));
+
+ /* set mode register: reset DLL */
+ out_be32 (&sdram->mode,
+ (SDRAM_MODE | 0x04000000));
+#endif
+
+ /* precharge all banks */
+ out_be32 (&sdram->ctrl,
+ (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
+
+ /* auto refresh */
+ out_be32 (&sdram->ctrl,
+ (SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
+
+ /* set mode register */
+ out_be32 (&sdram->mode, (SDRAM_MODE));
+
+ /* normal operation */
+ out_be32 (&sdram->ctrl,
+ (SDRAM_CONTROL | hi_addr_bit));
+
+ /* set CDM clock enable register, set MPC5200B SDRAM bus */
+ /* to reduced driver strength */
+ out_be32 (&cdm->clock_enable, (0x00CFFFFF));
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make
+ * real use of CONFIG_SYS_SDRAM_BASE. The code does not
+ * work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+ volatile struct mpc5xxx_mmap_ctl *mm =
+ (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+ volatile struct mpc5xxx_cdm *cdm =
+ (struct mpc5xxx_cdm *)MPC5XXX_CDM;
+ volatile struct mpc5xxx_sdram *sdram =
+ (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ /* 256MB at 0x0 */
+ out_be32 (&mm->sdram0, 0x0000001b);
+ /* disabled */
+ out_be32 (&mm->sdram1, 0x10000000);
+
+ /* setup config registers */
+ out_be32 (&sdram->config1, SDRAM_CONFIG1);
+ out_be32 (&sdram->config2, SDRAM_CONFIG2);
+
+#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY)
+ /* set tap delay */
+ out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else
+ dramsize = test2;
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ out_be32 (&mm->sdram0,
+ (0x13 + __builtin_ffs(dramsize >> 20) - 1));
+ } else {
+ /* disabled */
+ out_be32 (&mm->sdram0, 0);
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = in_be32(&mm->sdram0) & 0xFF;
+ if (dramsize >= 0x13)
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ else
+ dramsize = 0;
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = in_be32(&mm->sdram1) & 0xFF;
+ if (dramsize2 >= 0x13)
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ else
+ dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ return dramsize + dramsize2;
+}
+
+int checkboard(void)
+{
+ puts("Board: phyCORE-MPC5200B-tiny\n");
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+#define GPIO_PSC2_4 0x02000000UL
+
+void init_ide_reset(void)
+{
+ volatile struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+ debug("init_ide_reset\n");
+
+ /* Configure PSC2_4 as GPIO output for ATA reset */
+ setbits_be32(&wu_gpio->enable, GPIO_PSC2_4);
+ setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4);
+ /* Deassert reset */
+ setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
+}
+
+void ide_set_reset(int idereset)
+{
+ volatile struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+ debug("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
+ /* Make a delay. MPC5200 spec says 25 usec min */
+ udelay(500000);
+ } else
+ setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
+}
+#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
diff --git a/board/phytec/pcm051/Kconfig b/board/phytec/pcm051/Kconfig
new file mode 100644
index 0000000..2cc0d88
--- /dev/null
+++ b/board/phytec/pcm051/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PCM051
+
+config SYS_BOARD
+ default "pcm051"
+
+config SYS_VENDOR
+ default "phytec"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "pcm051"
+
+endif
diff --git a/board/phytec/pcm051/MAINTAINERS b/board/phytec/pcm051/MAINTAINERS
new file mode 100644
index 0000000..18ea636
--- /dev/null
+++ b/board/phytec/pcm051/MAINTAINERS
@@ -0,0 +1,7 @@
+PCM051 BOARD
+M: Lars Poeschel <poeschel@lemonage.de>
+S: Maintained
+F: board/phytec/pcm051/
+F: include/configs/pcm051.h
+F: configs/pcm051_rev1_defconfig
+F: configs/pcm051_rev3_defconfig
diff --git a/board/phytec/pcm051/Makefile b/board/phytec/pcm051/Makefile
new file mode 100644
index 0000000..ecb1d61
--- /dev/null
+++ b/board/phytec/pcm051/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += mux.o
+endif
+
+obj-y += board.o
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
new file mode 100644
index 0000000..1071662
--- /dev/null
+++ b/board/phytec/pcm051/board.c
@@ -0,0 +1,256 @@
+/*
+ * board.c
+ *
+ * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
+ *
+ * Copyright (C) 2013 Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* MII mode defines */
+#define RMII_RGMII2_MODE_ENABLE 0x49
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#ifdef CONFIG_SPL_BUILD
+
+/* DDR RAM defines */
+#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+ DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr;
+}
+
+#ifdef CONFIG_REV1
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+ .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+ .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+ .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+ .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
+};
+
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41J256M8HX15E_RD_DQS,
+ .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
+ .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41J256M8HX15E_RATIO,
+ .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41J256M8HX15E_RATIO,
+ .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41J256M8HX15E_RATIO,
+ .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
+ .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
+ .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
+ .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
+ .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
+ .zq_config = MT41J256M8HX15E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
+};
+
+void sdram_init(void)
+{
+ config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#else
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
+};
+
+void sdram_init(void)
+{
+ config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ /* Initalize the board header */
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ enable_board_pin_mux();
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ .phy_if = PHY_INTERFACE_MODE_RGMII,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ .phy_if = PHY_INTERFACE_MODE_RGMII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+ (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+#ifdef CONFIG_DRIVER_TI_CPSW
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ printf("<ethaddr> not set. Reading from E-fuse\n");
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ else
+ goto try_usbether;
+ }
+
+ writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+try_usbether:
+#endif
+
+#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
+ rv = usb_eth_initialize(bis);
+ if (rv < 0)
+ printf("Error %d registering USB_ETHER\n", rv);
+ else
+ n += rv;
+#endif
+ return n;
+}
+#endif
diff --git a/board/phytec/pcm051/board.h b/board/phytec/pcm051/board.h
new file mode 100644
index 0000000..e0b39e0
--- /dev/null
+++ b/board/phytec/pcm051/board.h
@@ -0,0 +1,25 @@
+/*
+ * board.h
+ *
+ * Phytec phyCORE-AM335x (pcm051) boards information header
+ *
+ * Copyright (C) 2013, Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have three pin mux functions that must exist. We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+void enable_cbmux_pin_mux(void);
+#endif
diff --git a/board/phytec/pcm051/mux.c b/board/phytec/pcm051/mux.c
new file mode 100644
index 0000000..6e9c3d2
--- /dev/null
+++ b/board/phytec/pcm051/mux.c
@@ -0,0 +1,127 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+#endif
+
+#ifdef CONFIG_I2C
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+#endif
+
+#ifdef CONFIG_SPI
+static struct module_pin_mux spi0_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
+ {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
+ PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
+ {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
+ {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
+ PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
+ {-1},
+};
+#endif
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
+ {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
+ {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+ {-1},
+};
+
+static struct module_pin_mux cbmux_pin_mux[] = {
+ {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
+ {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN}, /* JP4 */
+ {-1},
+};
+
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+#endif
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux()
+{
+ configure_module_pin_mux(rmii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(cbmux_pin_mux);
+#ifdef CONFIG_NAND
+ configure_module_pin_mux(nand_pin_mux);
+#endif
+#ifdef CONFIG_SPI
+ configure_module_pin_mux(spi0_pin_mux);
+#endif
+}
diff --git a/board/pm520/Kconfig b/board/pm520/Kconfig
new file mode 100644
index 0000000..3f0a258
--- /dev/null
+++ b/board/pm520/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_PM520
+
+config SYS_BOARD
+ default "pm520"
+
+config SYS_CONFIG_NAME
+ default "PM520"
+
+endif
diff --git a/board/pm520/MAINTAINERS b/board/pm520/MAINTAINERS
new file mode 100644
index 0000000..7b255bc
--- /dev/null
+++ b/board/pm520/MAINTAINERS
@@ -0,0 +1,9 @@
+PM520 BOARD
+M: Josef Wagner <Wagner@Microsys.de>
+S: Maintained
+F: board/pm520/
+F: include/configs/PM520.h
+F: configs/PM520_defconfig
+F: configs/PM520_DDR_defconfig
+F: configs/PM520_ROMBOOT_defconfig
+F: configs/PM520_ROMBOOT_DDR_defconfig
diff --git a/board/pm520/Makefile b/board/pm520/Makefile
new file mode 100644
index 0000000..8b5a7eb
--- /dev/null
+++ b/board/pm520/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := pm520.o flash.o
diff --git a/board/pm520/flash.c b/board/pm520/flash.c
new file mode 100644
index 0000000..89c9f02
--- /dev/null
+++ b/board/pm520/flash.c
@@ -0,0 +1,659 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH ushort
+#define FLASH_PORT_WIDTHV vu_short
+#define SWAP(x) (x)
+#else
+#define FLASH_PORT_WIDTH ulong
+#define FLASH_PORT_WIDTHV vu_long
+#define SWAP(x) (x)
+#endif
+
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT 0x00890089
+#define INTEL_ALT 0x00B000B0
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM 0x00100010
+#define INTEL_ERASE 0x00200020
+#define INTEL_CLEAR 0x00500050
+#define INTEL_LOCKBIT 0x00600060
+#define INTEL_PROTECT 0x00010001
+#define INTEL_STATUS 0x00700070
+#define INTEL_READID 0x00900090
+#define INTEL_CONFIRM 0x00D000D0
+#define INTEL_RESET 0xFFFFFFFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x00800080
+#define INTEL_OK 0x00800080
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+static void flash_sync_real_protect (flash_info_t * info);
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ int i;
+ ulong size = 0;
+ extern void flash_preinit(void);
+ extern void flash_afterinit(ulong, ulong);
+ ulong flashbase = CONFIG_SYS_FLASH_BASE;
+
+ flash_preinit();
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+ switch (i) {
+ case 0:
+ memset(&flash_info[i], 0, sizeof(flash_info_t));
+ flash_get_size ((FPW *) flashbase, &flash_info[i]);
+ flash_get_offsets (flash_info[i].start[0], &flash_info[i]);
+ break;
+ default:
+ panic ("configured to many flash banks!\n");
+ break;
+ }
+ size += flash_info[i].size;
+
+ /* get the h/w and s/w protection status in sync */
+ flash_sync_real_protect(&flash_info[i]);
+ }
+
+ /* Protect monitor and environment sectors
+ */
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#ifndef CONFIG_BOOT_ROM
+ flash_protect ( FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ &flash_info[0] );
+#endif
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ flash_protect ( FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
+#endif
+
+ flash_afterinit(flash_info[0].start[0], flash_info[0].size);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ printf ("INTEL ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F256J3A:
+ printf ("28F256J3A\n");
+ break;
+
+ case FLASH_28F128J3A:
+ printf ("28F128J3A\n");
+ break;
+
+ case FLASH_28F640J3A:
+ printf ("28F640J3A\n");
+ break;
+
+ case FLASH_28F320J3A:
+ printf ("28F320J3A\n");
+ break;
+
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+ return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+ volatile FPW value;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x5555] = (FPW) 0x00AA00AA;
+ addr[0x2AAA] = (FPW) 0x00550055;
+ addr[0x5555] = (FPW) 0x00900090;
+
+ mb ();
+ udelay(100);
+
+ value = addr[0];
+
+ switch (value) {
+
+ case (FPW) INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ mb ();
+ value = addr[1]; /* device ID */
+
+ switch (value) {
+
+ case (FPW) INTEL_ID_28F256J3A:
+ info->flash_id += FLASH_28F256J3A;
+ /* In U-Boot we support only 32 MB (no bank-switching) */
+ info->sector_count = 256 / 2;
+ info->size = 0x04000000 / 2;
+ info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000;
+ break; /* => 32 MB */
+
+ case (FPW) INTEL_ID_28F128J3A:
+ info->flash_id += FLASH_28F128J3A;
+ info->sector_count = 128;
+ info->size = 0x02000000;
+ info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000;
+ break; /* => 32 MB */
+
+ case (FPW) INTEL_ID_28F640J3A:
+ info->flash_id += FLASH_28F640J3A;
+ info->sector_count = 64;
+ info->size = 0x01000000;
+ info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03000000;
+ break; /* => 16 MB */
+
+ case (FPW) INTEL_ID_28F320J3A:
+ info->flash_id += FLASH_28F320J3A;
+ info->sector_count = 32;
+ info->size = 0x800000;
+ info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03800000;
+ break; /* => 8 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ break;
+ }
+
+ if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ }
+
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+
+ return (info->size);
+}
+
+
+/*
+ * This function gets the u-boot flash sector protection status
+ * (flash_info_t.protect[]) in sync with the sector protection
+ * status stored in hardware.
+ */
+static void flash_sync_real_protect (flash_info_t * info)
+{
+ int i;
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+
+ case FLASH_28F256J3A:
+ case FLASH_28F128J3A:
+ case FLASH_28F640J3A:
+ case FLASH_28F320J3A:
+ for (i = 0; i < info->sector_count; ++i) {
+ info->protect[i] = intel_sector_protected(info, i);
+ }
+ break;
+ default:
+ /* no h/w protect support */
+ break;
+ }
+}
+
+
+/*
+ * checks if "sector" in bank "info" is protected. Should work on intel
+ * strata flash chips 28FxxxJ3x in 8-bit mode.
+ * Returns 1 if sector is protected (or timed-out while trying to read
+ * protection status), 0 if it is not.
+ */
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
+{
+ FPWV *addr;
+ FPWV *lock_conf_addr;
+ ulong start;
+ unsigned char ret;
+
+ /*
+ * first, wait for the WSM to be finished. The rationale for
+ * waiting for the WSM to become idle for at most
+ * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+ * because of: (1) erase, (2) program or (3) lock bit
+ * configuration. So we just wait for the longest timeout of
+ * the (1)-(3), i.e. the erase timeout.
+ */
+
+ /* wait at least 35ns (W12) before issuing Read Status Register */
+ udelay(1);
+ addr = (FPWV *) info->start[sector];
+ *addr = (FPW) INTEL_STATUS;
+
+ start = get_timer (0);
+ while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+ if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ *addr = (FPW) INTEL_RESET; /* restore read mode */
+ printf("WSM busy too long, can't get prot status\n");
+ return 1;
+ }
+ }
+
+ /* issue the Read Identifier Codes command */
+ *addr = (FPW) INTEL_READID;
+
+ /* wait at least 35ns (W12) before reading */
+ udelay(1);
+
+ /* Intel example code uses offset of 2 for 16 bit flash */
+ lock_conf_addr = (FPWV *) info->start[sector] + 2;
+ ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
+
+ /* put flash back in read mode */
+ *addr = (FPW) INTEL_RESET;
+
+ return ret;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong type, start;
+ int rcode = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ type = (info->flash_id & FLASH_VENDMASK);
+ if ((type != FLASH_MAN_INTEL)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ start = get_timer (0);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ FPWV *addr = (FPWV *) (info->start[sect]);
+ FPW status;
+
+ printf ("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ *addr = (FPW) 0x00500050; /* clear status register */
+ *addr = (FPW) 0x00200020; /* erase setup */
+ *addr = (FPW) 0x00D000D0; /* erase confirm */
+
+ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = (FPW) 0x00B000B0; /* suspend erase */
+ *addr = (FPW) 0x00FF00FF; /* reset to read mode */
+ rcode = 1;
+ break;
+ }
+ }
+
+ *addr = 0x00500050; /* clear status register cmd. */
+ *addr = 0x00FF00FF; /* resest to read mode */
+
+ printf (" done\n");
+ }
+ }
+
+ if (flag)
+ enable_interrupts();
+
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ FPW data;
+ int count, i, l, rc, port_width;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return 4;
+ }
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+ wp = (addr & ~1);
+ port_width = 2;
+#else
+ wp = (addr & ~3);
+ port_width = 4;
+#endif
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < port_width && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ count = 0;
+ while (cnt >= port_width) {
+ data = 0;
+ for (i = 0; i < port_width; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ cnt -= port_width;
+ if (count++ > 0x800) {
+ spin_wheel ();
+ count = 0;
+ }
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+ FPWV *addr = (FPWV *) dest;
+ ulong status;
+ ulong start;
+ int flag;
+ int rcode = 0;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ *addr = (FPW) 0x00400040; /* write setup */
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ /* wait while polling the status register */
+ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ rcode = 1;
+ break;
+ }
+ }
+
+ *addr = (FPW) 0x00FF00FF; /* restore read mode */
+
+ if (flag)
+ enable_interrupts();
+
+ return rcode;
+}
+
+void inline spin_wheel (void)
+{
+ static int p = 0;
+ static char w[] = "\\/-";
+
+ printf ("\010%c", w[p]);
+ (++p == 3) ? (p = 0) : 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect (flash_info_t *info, long sector, int prot)
+{
+ ulong start;
+ int i;
+ int rc = 0;
+ vu_long *addr = (vu_long *)(info->start[sector]);
+ int flag = disable_interrupts();
+
+ *addr = INTEL_CLEAR; /* Clear status register */
+ if (prot) { /* Set sector lock bit */
+ *addr = INTEL_LOCKBIT; /* Sector lock bit */
+ *addr = INTEL_PROTECT; /* set */
+ }
+ else { /* Clear sector lock bit */
+ *addr = INTEL_LOCKBIT; /* All sectors lock bits */
+ *addr = INTEL_CONFIRM; /* clear */
+ }
+
+ start = get_timer(0);
+
+ while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
+ printf("Flash lock bit operation timed out\n");
+ rc = 1;
+ break;
+ }
+ }
+
+ if (*addr != INTEL_OK) {
+ printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+ (uint)addr, (uint)*addr);
+ rc = 1;
+ }
+
+ if (!rc)
+ info->protect[sector] = prot;
+
+ /*
+ * Clear lock bit command clears all sectors lock bits, so
+ * we have to restore lock bits of protected sectors.
+ * WARNING: code below re-locks sectors only for one bank (info).
+ * This causes problems on boards where several banks share
+ * the same chip, as sectors in othere banks will be unlocked
+ * but not re-locked. It works fine on pm520 though, as there
+ * is only one chip and one bank.
+ */
+ if (!prot)
+ {
+ for (i = 0; i < info->sector_count; i++)
+ {
+ if (info->protect[i])
+ {
+ start = get_timer(0);
+ addr = (vu_long *)(info->start[i]);
+ *addr = INTEL_LOCKBIT; /* Sector lock bit */
+ *addr = INTEL_PROTECT; /* set */
+ while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
+ {
+ if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT)
+ {
+ printf("Flash lock bit operation timed out\n");
+ rc = 1;
+ break;
+ }
+ }
+ }
+ }
+ /*
+ * get the s/w sector protection status in sync with the h/w,
+ * in case something went wrong during the re-locking.
+ */
+ flash_sync_real_protect(info); /* resets flash to read mode */
+ }
+
+ if (flag)
+ enable_interrupts();
+
+ *addr = INTEL_RESET; /* Reset to read array mode */
+
+ return rc;
+}
diff --git a/board/pm520/mt46v16m16-75.h b/board/pm520/mt46v16m16-75.h
new file mode 100644
index 0000000..9068fbf
--- /dev/null
+++ b/board/pm520/mt46v16m16-75.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 1 /* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x714f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..0133eaa
--- /dev/null
+++ b/board/pm520/mt48lc16m16a2-75.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 0 /* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c
new file mode 100644
index 0000000..4ec4505
--- /dev/null
+++ b/board/pm520/pm520.c
@@ -0,0 +1,253 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <netdev.h>
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+#endif
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set tap delay */
+ *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ }
+
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+ /* find RAM size using SDRAM CS1 only */
+ if (!dramsize)
+ sdram_start(0);
+ test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ if (!dramsize) {
+ sdram_start(1);
+ test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ }
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize2 = test1;
+ } else {
+ dramsize2 = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20)) {
+ dramsize2 = 0;
+ }
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+ | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13) {
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ } else {
+ dramsize = 0;
+ }
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ if (dramsize2 >= 0x13) {
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ } else {
+ dramsize2 = 0;
+ }
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+ puts ("Board: MicroSys PM520 \n");
+ return 0;
+}
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong start, ulong size)
+{
+#if defined(CONFIG_BOOT_ROM)
+ /* adjust mapping */
+ *(vu_long *)MPC5XXX_CS1_START =
+ START_REG(start);
+ *(vu_long *)MPC5XXX_CS1_STOP =
+ STOP_REG(start, size);
+#else
+ /* adjust mapping */
+ *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+ START_REG(start);
+ *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+ STOP_REG(start, size);
+#endif
+}
+
+
+extern flash_info_t flash_info[]; /* info for FLASH chips */
+
+int misc_init_r (void)
+{
+ /* adjust flash start */
+ gd->bd->bi_flashstart = flash_info[0].start[0];
+ return (0);
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+ debug ("init_ide_reset\n");
+
+}
+
+void ide_set_reset (int idereset)
+{
+ debug ("ide_reset(%d)\n", idereset);
+
+}
+#endif
+
+#if defined(CONFIG_CMD_DOC)
+void doc_init (void)
+{
+ doc_probe (CONFIG_SYS_DOC_BASE);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
diff --git a/board/ppcag/bg0900/Kconfig b/board/ppcag/bg0900/Kconfig
new file mode 100644
index 0000000..d7f2368
--- /dev/null
+++ b/board/ppcag/bg0900/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BG0900
+
+config SYS_BOARD
+ default "bg0900"
+
+config SYS_VENDOR
+ default "ppcag"
+
+config SYS_SOC
+ default "mxs"
+
+config SYS_CONFIG_NAME
+ default "bg0900"
+
+endif
diff --git a/board/ppcag/bg0900/MAINTAINERS b/board/ppcag/bg0900/MAINTAINERS
new file mode 100644
index 0000000..853c0d5
--- /dev/null
+++ b/board/ppcag/bg0900/MAINTAINERS
@@ -0,0 +1,6 @@
+BG0900 BOARD
+M: Marek Vasut <marex@denx.de>
+S: Maintained
+F: board/ppcag/bg0900/
+F: include/configs/bg0900.h
+F: configs/bg0900_defconfig
diff --git a/board/ppcag/bg0900/Makefile b/board/ppcag/bg0900/Makefile
new file mode 100644
index 0000000..74c6db5
--- /dev/null
+++ b/board/ppcag/bg0900/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := bg0900.o
+else
+obj-y := spl_boot.o
+endif
diff --git a/board/ppcag/bg0900/bg0900.c b/board/ppcag/bg0900/bg0900.c
new file mode 100644
index 0000000..06612fa
--- /dev/null
+++ b/board/ppcag/bg0900/bg0900.c
@@ -0,0 +1,86 @@
+/*
+ * PPC-AG BG0900 board
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP2 clock at 160MHz */
+ mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct eth_device *dev;
+ int ret;
+
+ ret = cpu_eth_init(bis);
+
+ /* BG0900 uses ENET_CLK PAD to drive FEC clock */
+ writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
+ &clkctrl_regs->hw_clkctrl_enet);
+
+ /* Reset FEC PHYs */
+ gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
+ udelay(200);
+ gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
+
+ ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+ if (ret) {
+ puts("FEC MXS: Unable to init FEC0\n");
+ return ret;
+ }
+
+ dev = eth_get_dev_by_name("FEC0");
+ if (!dev) {
+ puts("FEC MXS: Unable to get FEC0 device entry\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+#endif
diff --git a/board/ppcag/bg0900/spl_boot.c b/board/ppcag/bg0900/spl_boot.c
new file mode 100644
index 0000000..a04c955
--- /dev/null
+++ b/board/ppcag/bg0900/spl_boot.c
@@ -0,0 +1,153 @@
+/*
+ * PPC-AG BG0900 Boot setup
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* DUART */
+ MX28_PAD_PWM0__DUART_RX,
+ MX28_PAD_PWM1__DUART_TX,
+
+ /* GPMI NAND */
+ MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+ MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+
+ /* FEC0 */
+ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+ /* FEC0 Reset */
+ MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+ /* EMI */
+ MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+ /* SPI2 (for SPI flash) */
+ MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_SS0__SSP2_D3 |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+};
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ /*
+ * DDR Controller Registers
+ * Manufacturer: Winbond
+ * Device Part Number: W972GG6JB-25I
+ * Clock Freq.: 200MHz
+ * Density: 2Gb
+ * Chip Selects: 1
+ * Number of Banks: 8
+ * Row address: 14
+ * Column address: 10
+ */
+
+ dram_vals[0x74 / 4] = 0x0102010A;
+ dram_vals[0x98 / 4] = 0x04005003;
+ dram_vals[0x9c / 4] = 0x090000c8;
+
+ dram_vals[0xa8 / 4] = 0x0036b009;
+ dram_vals[0xac / 4] = 0x03270612;
+
+ dram_vals[0xb0 / 4] = 0x02020202;
+ dram_vals[0xb4 / 4] = 0x00c80029;
+
+ dram_vals[0xc0 / 4] = 0x00011900;
+
+ dram_vals[0x12c / 4] = 0x07400300;
+ dram_vals[0x130 / 4] = 0x07400300;
+ dram_vals[0x2c4 / 4] = 0x02030303;
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/ppmc7xx/Kconfig b/board/ppmc7xx/Kconfig
new file mode 100644
index 0000000..f101940
--- /dev/null
+++ b/board/ppmc7xx/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_PPMC7XX
+
+config SYS_BOARD
+ default "ppmc7xx"
+
+config SYS_CONFIG_NAME
+ default "ppmc7xx"
+
+endif
diff --git a/board/ppmc7xx/MAINTAINERS b/board/ppmc7xx/MAINTAINERS
new file mode 100644
index 0000000..a0c1f44
--- /dev/null
+++ b/board/ppmc7xx/MAINTAINERS
@@ -0,0 +1,6 @@
+PPMC7XX BOARD
+#M: -
+S: Maintained
+F: board/ppmc7xx/
+F: include/configs/ppmc7xx.h
+F: configs/ppmc7xx_defconfig
diff --git a/board/ppmc7xx/Makefile b/board/ppmc7xx/Makefile
new file mode 100644
index 0000000..f8957f3
--- /dev/null
+++ b/board/ppmc7xx/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := init.o
+obj-y += ppmc7xx.o pci.o flash.o
diff --git a/board/ppmc7xx/flash.c b/board/ppmc7xx/flash.c
new file mode 100644
index 0000000..e724227
--- /dev/null
+++ b/board/ppmc7xx/flash.c
@@ -0,0 +1,494 @@
+/*
+ * flash.c
+ * -------
+ *
+ * Flash programming routines for the Wind River PPMC 74xx/7xx
+ * based on flash.c from the TQM8260 board.
+ *
+ * By Richard Danter (richard.danter@windriver.com)
+ * Copyright (C) 2005 Wind River Systems
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <74xx_7xx.h>
+
+#define DWORD unsigned long long
+
+/* Local function prototypes */
+static int write_dword (flash_info_t* info, ulong dest, unsigned char *pdata);
+static void write_via_fpu (volatile DWORD* addr, DWORD* data);
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+void flash_reset (void)
+{
+ unsigned long msr;
+ DWORD cmd_reset = 0x00F000F000F000F0LL;
+
+ if (flash_info[0].flash_id != FLASH_UNKNOWN) {
+ msr = get_msr ();
+ set_msr (msr | MSR_FP);
+
+ write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
+
+ set_msr (msr);
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (ulong baseaddr, flash_info_t * info)
+{
+ int i;
+ unsigned long msr;
+ DWORD flashtest;
+ DWORD cmd_select[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
+ 0x0090009000900090LL };
+
+ /* Enable FPU */
+ msr = get_msr ();
+ set_msr (msr | MSR_FP);
+
+ /* Write auto-select command sequence */
+ write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
+ write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
+ write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
+
+ /* Restore FPU */
+ set_msr (msr);
+
+ /* Read manufacturer ID */
+ flashtest = *(volatile DWORD*)baseaddr;
+ switch ((int)flashtest) {
+ case AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ default:
+ /* No, faulty or unknown flash */
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0);
+ }
+
+ /* Read device ID */
+ flashtest = *(volatile DWORD*)(baseaddr + 8);
+ switch ((long)flashtest) {
+ case AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00400000;
+ break;
+ case AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00400000;
+ break;
+ case AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00800000;
+ break;
+ case AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00800000;
+ break;
+ case AMD_ID_DL322T:
+ info->flash_id += FLASH_AMDL322T;
+ info->sector_count = 71;
+ info->size = 0x01000000;
+ break;
+ case AMD_ID_DL322B:
+ info->flash_id += FLASH_AMDL322B;
+ info->sector_count = 71;
+ info->size = 0x01000000;
+ break;
+ case AMD_ID_DL323T:
+ info->flash_id += FLASH_AMDL323T;
+ info->sector_count = 71;
+ info->size = 0x01000000;
+ break;
+ case AMD_ID_DL323B:
+ info->flash_id += FLASH_AMDL323B;
+ info->sector_count = 71;
+ info->size = 0x01000000;
+ break;
+ case AMD_ID_LV640U:
+ info->flash_id += FLASH_AM640U;
+ info->sector_count = 128;
+ info->size = 0x02000000;
+ break;
+ default:
+ /* Unknown flash type */
+ info->flash_id = FLASH_UNKNOWN;
+ return (0);
+ }
+
+ if ((long)flashtest == AMD_ID_LV640U) {
+ /* set up sector start adress table (uniform sector type) */
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = baseaddr + (i * 0x00040000);
+ } else if (info->flash_id & FLASH_BTYPE) {
+ /* set up sector start adress table (bottom sector type) */
+ info->start[0] = baseaddr + 0x00000000;
+ info->start[1] = baseaddr + 0x00010000;
+ info->start[2] = baseaddr + 0x00018000;
+ info->start[3] = baseaddr + 0x00020000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
+ }
+ } else {
+ /* set up sector start adress table (top sector type) */
+ i = info->sector_count - 1;
+ info->start[i--] = baseaddr + info->size - 0x00010000;
+ info->start[i--] = baseaddr + info->size - 0x00018000;
+ info->start[i--] = baseaddr + info->size - 0x00020000;
+ for (; i >= 0; i--) {
+ info->start[i] = baseaddr + i * 0x00040000;
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ if (*(volatile DWORD*)(info->start[i] + 16) & 0x0001000100010001LL) {
+ info->protect[i] = 1; /* D0 = 1 if protected */
+ } else {
+ info->protect[i] = 0;
+ }
+ }
+
+ flash_reset ();
+ return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+ unsigned long size_b0 = 0;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here (only one bank) */
+ size_b0 = flash_get_size (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+ if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 >> 20);
+ }
+
+ /*
+ * protect monitor and environment sectors
+ */
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
+# ifndef CONFIG_ENV_SIZE
+# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+# endif
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+ return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf ("AMD ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf ("FUJITSU ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM800T:
+ printf ("29LV800T (8 M, top sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf ("29LV800T (8 M, bottom sector)\n");
+ break;
+ case FLASH_AM160T:
+ printf ("29LV160T (16 M, top sector)\n");
+ break;
+ case FLASH_AM160B:
+ printf ("29LV160B (16 M, bottom sector)\n");
+ break;
+ case FLASH_AMDL322T:
+ printf ("29DL322T (32 M, top sector)\n");
+ break;
+ case FLASH_AMDL322B:
+ printf ("29DL322B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AMDL323T:
+ printf ("29DL323T (32 M, top sector)\n");
+ break;
+ case FLASH_AMDL323B:
+ printf ("29DL323B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AM640U:
+ printf ("29LV640D (64 M, uniform sector)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+ unsigned long msr;
+ DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
+ 0x0080008000800080LL, 0x00AA00AA00AA00AALL,
+ 0x0055005500550055LL, 0x0030003000300030LL };
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Enable FPU */
+ msr = get_msr();
+ set_msr ( msr | MSR_FP );
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[0] );
+ write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[1] );
+ write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[2] );
+ write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[3] );
+ write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[4] );
+ udelay (1000);
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ write_via_fpu ((DWORD*)info->start[sect], &cmd_erase[5] );
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* Restore FPU */
+ set_msr (msr);
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL )
+ != 0x0080008000800080LL )
+ {
+ if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ serial_putc ('.');
+ last = now;
+ }
+ }
+
+ DONE:
+ /* reset to read mode */
+ flash_reset ();
+
+ printf (" done\n");
+ return 0;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong dp;
+ static unsigned char bb[8];
+ int i, l, rc, cc = cnt;
+
+ dp = (addr & ~7); /* get lower dword aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - dp) != 0) {
+ for (i = 0; i < 8; i++)
+ bb[i] = (i < l || (i - l) >= cc) ? *(char*)(dp + i) : *src++;
+ if ((rc = write_dword (info, dp, bb)) != 0) {
+ return (rc);
+ }
+ dp += 8;
+ cc -= 8 - l;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cc >= 8) {
+ if ((rc = write_dword (info, dp, src)) != 0) {
+ return (rc);
+ }
+ dp += 8;
+ src += 8;
+ cc -= 8;
+ }
+
+ if (cc <= 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ for (i = 0; i < 8; i++) {
+ bb[i] = (i < cc) ? *src++ : *(char*)(dp + i);
+ }
+ return (write_dword (info, dp, bb));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a dword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
+{
+ ulong start;
+ unsigned long msr;
+ int flag, i;
+ DWORD data;
+ DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
+ 0x00A000A000A000A0LL };
+
+ for (data = 0, i = 0; i < 8; i++)
+ data = (data << 8) + *pdata++;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*(DWORD*)dest & data) != data) {
+ return (2);
+ }
+
+ /* Enable FPU */
+ msr = get_msr();
+ set_msr( msr | MSR_FP );
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[0] );
+ write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_write[1] );
+ write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[2] );
+ write_via_fpu ((DWORD*)dest, &data );
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* Restore FPU */
+ set_msr(msr);
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while (*(volatile DWORD*)dest != data ) {
+ if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void write_via_fpu (volatile DWORD* addr, DWORD* data)
+{
+ __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
+ __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
+ __asm__ __volatile__ ("eieio");
+}
diff --git a/board/ppmc7xx/init.S b/board/ppmc7xx/init.S
new file mode 100644
index 0000000..99a818a
--- /dev/null
+++ b/board/ppmc7xx/init.S
@@ -0,0 +1,336 @@
+/*
+ * init.S
+ * ------
+ *
+ * Wind River PPMC 7xx/74xx init code.
+ *
+ * By Richard Danter (richard.danter@windriver.com)
+ * Copyright (C) 2005 Wind River Systems
+ *
+ * NOTE: The following code was generated automatically by Workbench
+ * from the ppmc7400_107.reg register file.
+ */
+
+#include <ppc_asm.tmpl>
+
+
+.globl board_asm_init
+board_asm_init:
+
+ lis r4,0xFEC0
+ ori r4,r4,0x0000
+ lis r5,0xFEE0
+ ori r5,r5,0x0000
+ lis r3,0x8000 # ADDR_00
+ ori r3,r3,0x0000
+ stwbrx r3,0,r4
+ li r3,0x1057 # VENDOR
+ li r8, 0x0
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_02
+ ori r3,r3,0x0002
+ stwbrx r3,0,r4
+ li r3,0x0004 # ID
+ li r8, 0x2
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_04
+ ori r3,r3,0x0004
+ stwbrx r3,0,r4
+ li r3,0x0006 # PCICMD
+ li r8, 0x0
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_06
+ ori r3,r3,0x0006
+ stwbrx r3,0,r4
+ li r3,0x00A0 # PCISTAT
+ li r8, 0x2
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_08
+ ori r3,r3,0x0008
+ stwbrx r3,0,r4
+ li r3,0x10 # REVID
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_09
+ ori r3,r3,0x0009
+ stwbrx r3,0,r4
+ li r3,0x00 # PROGIR
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_0A
+ ori r3,r3,0x000A
+ stwbrx r3,0,r4
+ li r3,0x00 # SUBCCODE
+ stb r3,0x2(r5)
+ lis r3,0x8000 # ADDR_0B
+ ori r3,r3,0x000B
+ stwbrx r3,0,r4
+ li r3,0x06 # PBCCR
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_0C
+ ori r3,r3,0x000C
+ stwbrx r3,0,r4
+ li r3,0x08 # PCLSR
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_0D
+ ori r3,r3,0x000D
+ stwbrx r3,0,r4
+ li r3,0x00 # PLTR
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_0E
+ ori r3,r3,0x000E
+ stwbrx r3,0,r4
+ li r3,0x00 # HEADTYPE
+ stb r3,0x2(r5)
+ lis r3,0x8000 # ADDR_0F
+ ori r3,r3,0x000F
+ stwbrx r3,0,r4
+ li r3,0x00 # BISTCTRL
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_10
+ ori r3,r3,0x0010
+ stwbrx r3,0,r4
+ lis r3,0x0000 # LMBAR
+ ori r3,r3,0x0008
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_14
+ ori r3,r3,0x0014
+ stwbrx r3,0,r4
+ lis r3,0xF000 # PCSRBAR
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_3C
+ ori r3,r3,0x003C
+ stwbrx r3,0,r4
+ li r3,0x00 # ILR
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_3D
+ ori r3,r3,0x003D
+ stwbrx r3,0,r4
+ li r3,0x01 # INTPIN
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_3E
+ ori r3,r3,0x003E
+ stwbrx r3,0,r4
+ li r3,0x00 # MIN_GNT
+ stb r3,0x2(r5)
+ lis r3,0x8000 # ADDR_3F
+ ori r3,r3,0x003F
+ stwbrx r3,0,r4
+ li r3,0x00 # MAX_LAT
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_40
+ ori r3,r3,0x0040
+ stwbrx r3,0,r4
+ li r3,0x00 # BUSNB
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_41
+ ori r3,r3,0x0041
+ stwbrx r3,0,r4
+ li r3,0x00 # SBUSNB
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_46
+ ori r3,r3,0x0046
+ stwbrx r3,0,r4
+# li r3,0xE080 # PCIARB
+ li r3,-0x1F80 # PCIARB
+ li r8, 0x2
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_70
+ ori r3,r3,0x0070
+ stwbrx r3,0,r4
+ li r3,0x0000 # PMCR1
+ li r8, 0x0
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_72
+ ori r3,r3,0x0072
+ stwbrx r3,0,r4
+ li r3,0xC0 # PMCR2
+ stb r3,0x2(r5)
+ lis r3,0x8000 # ADDR_73
+ ori r3,r3,0x0073
+ stwbrx r3,0,r4
+ li r3,0xEF # ODCR
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_74
+ ori r3,r3,0x0074
+ stwbrx r3,0,r4
+ li r3,0x7D00 # CLKDCR
+ li r8, 0x0
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_76
+ ori r3,r3,0x0076
+ stwbrx r3,0,r4
+ li r3,0x00 # MDCR
+ stb r3,0x2(r5)
+ lis r6,0xFCE0
+ ori r6,r6,0x0000 # r6 is the EUMBAR Base Address
+ lis r3,0x8000 # ADDR_78
+ ori r3,r3,0x0078
+ stwbrx r3,0,r4
+ lis r3,0xFCE0 # EUMBBAR
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_80
+ ori r3,r3,0x0080
+ stwbrx r3,0,r4
+ lis r3,0xFFFF # MSADDR1
+ ori r3,r3,0x4000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_84
+ ori r3,r3,0x0084
+ stwbrx r3,0,r4
+ lis r3,0xFFFF # MSADDR2
+ ori r3,r3,0xFFFF
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_88
+ ori r3,r3,0x0088
+ stwbrx r3,0,r4
+ lis r3,0x0303 # EMSADDR1
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_8C
+ ori r3,r3,0x008C
+ stwbrx r3,0,r4
+ lis r3,0x0303 # EMSADDR2
+ ori r3,r3,0x0303
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_90
+ ori r3,r3,0x0090
+ stwbrx r3,0,r4
+ lis r3,0xFFFF # EMEADDR1
+ ori r3,r3,0x7F3F
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_94
+ ori r3,r3,0x0094
+ stwbrx r3,0,r4
+ lis r3,0xFFFF # EMEADDR2
+ ori r3,r3,0xFFFF
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_98
+ ori r3,r3,0x0098
+ stwbrx r3,0,r4
+ lis r3,0x0303 # EXTEMEM1
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_9C
+ ori r3,r3,0x009C
+ stwbrx r3,0,r4
+ lis r3,0x0303 # EXTEMEM2
+ ori r3,r3,0x0303
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_A0
+ ori r3,r3,0x00A0
+ stwbrx r3,0,r4
+ li r3,0x03 # MEMBNKEN
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_A3
+ ori r3,r3,0x00A3
+ stwbrx r3,0,r4
+ li r3,0x00 # MEMPMODE
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_B8
+ ori r3,r3,0x00B8
+ stwbrx r3,0,r4
+ li r3,0x00 # ECCCNT
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_B9
+ ori r3,r3,0x00B9
+ stwbrx r3,0,r4
+ li r3,0x00 # ECCTRG
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_C0
+ ori r3,r3,0x00C0
+ stwbrx r3,0,r4
+ li r3,0xFF # ERRENR1
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_C1
+ ori r3,r3,0x00C1
+ stwbrx r3,0,r4
+ li r3,0x00 # ERRDR1
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_C3
+ ori r3,r3,0x00C3
+ stwbrx r3,0,r4
+ li r3,0x50 # IPBESR
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_C4
+ ori r3,r3,0x00C4
+ stwbrx r3,0,r4
+ li r3,0xBF # ERRENR2
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_C5
+ ori r3,r3,0x00C5
+ stwbrx r3,0,r4
+ li r3,0x00 # ERRDR2
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_C7
+ ori r3,r3,0x00C7
+ stwbrx r3,0,r4
+ li r3,0x00 # PCIBESR
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_C8
+ ori r3,r3,0x00C8
+ stwbrx r3,0,r4
+ lis r3,0x0000 # BERRADDR
+ ori r3,r3,0xE0FE
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_E0
+ ori r3,r3,0x00E0
+ stwbrx r3,0,r4
+ li r3,0xC0 # AMBOR
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_F4
+ ori r3,r3,0x00F4
+ stwbrx r3,0,r4
+ lis r3,0x0000 # MCCR2
+ ori r3,r3,0x020C
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_F8
+ ori r3,r3,0x00F8
+ stwbrx r3,0,r4
+ lis r3,0x0230 # MCCR3
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_FC
+ ori r3,r3,0x00FC
+ stwbrx r3,0,r4
+ lis r3,0x2532 # MCCR4
+ ori r3,r3,0x2220
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_F0
+ ori r3,r3,0x00F0
+ stwbrx r3,0,r4
+ lis r3,0xFFC8 # MCCR1
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_A8
+ ori r3,r3,0x00A8
+ stwbrx r3,0,r4
+ lis r3,0xFF14 # PICR1
+ ori r3,r3,0x1CC8
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_AC
+ ori r3,r3,0x00AC
+ stwbrx r3,0,r4
+ lis r3,0x0000 # PICR2
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+
+ blr
diff --git a/board/ppmc7xx/pci.c b/board/ppmc7xx/pci.c
new file mode 100644
index 0000000..d81a41a
--- /dev/null
+++ b/board/ppmc7xx/pci.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * PCI initialisation for the MPC10x.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <mpc106.h>
+
+#ifdef CONFIG_PCI
+
+struct pci_controller local_hose;
+
+void pci_init_board(void)
+{
+ struct pci_controller* hose = (struct pci_controller *)&local_hose;
+ u16 reg16;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ pci_set_region(hose->regions + 0,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_SYS_PCI_MEM_BUS,
+ CONFIG_SYS_PCI_MEM_PHYS,
+ CONFIG_SYS_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* ISA/PCI memory space */
+ pci_set_region(hose->regions + 2,
+ CONFIG_SYS_ISA_MEM_BUS,
+ CONFIG_SYS_ISA_MEM_PHYS,
+ CONFIG_SYS_ISA_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI I/O space */
+ pci_set_region(hose->regions + 3,
+ CONFIG_SYS_PCI_IO_BUS,
+ CONFIG_SYS_PCI_IO_PHYS,
+ CONFIG_SYS_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ /* ISA/PCI I/O space */
+ pci_set_region(hose->regions + 4,
+ CONFIG_SYS_ISA_IO_BUS,
+ CONFIG_SYS_ISA_IO_PHYS,
+ CONFIG_SYS_ISA_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 5;
+
+ pci_setup_indirect(hose,
+ MPC106_REG_ADDR,
+ MPC106_REG_DATA);
+
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+
+ /* Initialises the MPC10x PCI Configuration regs. */
+ pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+ /* Clear non-reserved bits in status register */
+ pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+}
+
+#endif /* CONFIG_PCI */
diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c
new file mode 100644
index 0000000..432d366
--- /dev/null
+++ b/board/ppmc7xx/ppmc7xx.c
@@ -0,0 +1,112 @@
+/*
+ * ppmc7xx.c
+ * ---------
+ *
+ * Main board-specific routines for Wind River PPMC 7xx/74xx board.
+ *
+ * By Richard Danter (richard.danter@windriver.com)
+ * Copyright (C) 2005 Wind River Systems
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+
+
+/* Define some MPC107 (memory controller) registers */
+#define MPC107_EUMB_GCR 0xfce41020
+#define MPC107_EUMB_IACKR 0xfce600a0
+
+
+/* Function prototypes */
+extern void _start(void);
+
+
+/*
+ * initdram()
+ *
+ * This function normally initialises the (S)DRAM of the system. For this board
+ * the SDRAM was already initialised by board_asm_init (see init.S) so we just
+ * return the size of RAM.
+ */
+phys_size_t initdram( int board_type )
+{
+ return CONFIG_SYS_SDRAM_SIZE;
+}
+
+
+/*
+ * after_reloc()
+ *
+ * This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
+ * us an opportunity to do some additional setup before the rest of the system
+ * is initialised. We don't need to do anything, so we just call board_init_r()
+ * which should never return.
+ */
+void after_reloc( ulong dest_addr, gd_t* gd )
+{
+ /* Jump to the main U-Boot board init code */
+ board_init_r( gd, dest_addr );
+}
+
+
+/*
+ * checkboard()
+ *
+ * We could do some board level checks here, such as working out what version
+ * it is, but for this board we simply display it's name (on the console).
+ */
+int checkboard( void )
+{
+ puts( "Board: Wind River PPMC 7xx/74xx\n" );
+ return 0;
+}
+
+
+/*
+ * misc_init_r
+ *
+ * Used for other setup which needs to be done late in the bring-up phase.
+ */
+int misc_init_r( void )
+{
+ /* Reset the EPIC and clear pending interrupts */
+ out32r(MPC107_EUMB_GCR, 0xa0000000);
+ while( in32r( MPC107_EUMB_GCR ) & 0x80000000 );
+ out32r( MPC107_EUMB_GCR, 0x20000000 );
+ while( in32r( MPC107_EUMB_IACKR ) != 0xff );
+
+ /* Enable the I-Cache */
+ icache_enable();
+
+ return 0;
+}
+
+
+/*
+ * do_reset()
+ *
+ * Shell command to reset the board.
+ */
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ printf( "Resetting...\n" );
+
+ /* Disabe and invalidate cache */
+ icache_disable();
+ dcache_disable();
+
+ /* Jump to cold reset point (in RAM) */
+ _start();
+
+ /* Should never get here */
+ while(1)
+ ;
+
+ return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
diff --git a/board/pr1/Kconfig b/board/pr1/Kconfig
new file mode 100644
index 0000000..fb04648
--- /dev/null
+++ b/board/pr1/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_PR1
+
+config SYS_BOARD
+ default "pr1"
+
+config SYS_CONFIG_NAME
+ default "pr1"
+
+endif
diff --git a/board/pr1/MAINTAINERS b/board/pr1/MAINTAINERS
new file mode 100644
index 0000000..23fdbc7
--- /dev/null
+++ b/board/pr1/MAINTAINERS
@@ -0,0 +1,6 @@
+PR1 BOARD
+M: Dimitar Penev <dpn@switchfin.org>
+S: Maintained
+F: board/pr1/
+F: include/configs/pr1.h
+F: configs/pr1_defconfig
diff --git a/board/pr1/Makefile b/board/pr1/Makefile
new file mode 100644
index 0000000..4f375a8
--- /dev/null
+++ b/board/pr1/Makefile
@@ -0,0 +1,14 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) Switchfin Org. <dpn@switchfin.org>
+#
+# Copyright (c) 2005-2007 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := pr1.o
diff --git a/board/pr1/pr1.c b/board/pr1/pr1.c
new file mode 100644
index 0000000..bb907f3
--- /dev/null
+++ b/board/pr1/pr1.c
@@ -0,0 +1,30 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) Switchfin Org. <dpn@switchfin.org>
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+
+int checkboard(void)
+{
+ printf("Board: Switchvoice PR1 Appliance\n");
+ printf(" Support: http://www.switchvoice.com/\n");
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_MAC
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
diff --git a/board/prodrive/alpr/Kconfig b/board/prodrive/alpr/Kconfig
new file mode 100644
index 0000000..543b455
--- /dev/null
+++ b/board/prodrive/alpr/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ALPR
+
+config SYS_BOARD
+ default "alpr"
+
+config SYS_VENDOR
+ default "prodrive"
+
+config SYS_CONFIG_NAME
+ default "alpr"
+
+endif
diff --git a/board/prodrive/alpr/MAINTAINERS b/board/prodrive/alpr/MAINTAINERS
new file mode 100644
index 0000000..31baabb
--- /dev/null
+++ b/board/prodrive/alpr/MAINTAINERS
@@ -0,0 +1,6 @@
+ALPR BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/prodrive/alpr/
+F: include/configs/alpr.h
+F: configs/alpr_defconfig
diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile
new file mode 100644
index 0000000..812d041
--- /dev/null
+++ b/board/prodrive/alpr/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = alpr.o fpga.o nand.o
+extra-y += init.o
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
new file mode 100644
index 0000000..31c1ab5
--- /dev/null
+++ b/board/prodrive/alpr/alpr.c
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <spd_sdram.h>
+#include <asm/ppc4xx-emac.h>
+#include <miiphy.h>
+#include <asm/processor.h>
+#include <asm/4xx_pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int alpr_fpga_init(void);
+
+int board_early_init_f (void)
+{
+ /*-------------------------------------------------------------------------
+ * Initialize EBC CONFIG
+ *-------------------------------------------------------------------------*/
+ mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
+ EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
+ EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
+ EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
+ EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ /*
+ * Because of the interrupt handling rework to handle 440GX interrupts
+ * with the common code, we needed to change names of the UIC registers.
+ * Here the new relationship:
+ *
+ * U-Boot name 440GX name
+ * -----------------------
+ * UIC0 UICB0
+ * UIC1 UIC0
+ * UIC2 UIC1
+ * UIC3 UIC2
+ */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+ mtdcr (UIC1ER, 0x00000000); /* disable all */
+ mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
+ mtdcr (UIC1PR, 0xfffffe03); /* per manual */
+ mtdcr (UIC1TR, 0x01c00000); /* per manual */
+ mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+ mtdcr (UIC2ER, 0x00000000); /* disable all */
+ mtdcr (UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+ mtdcr (UIC3ER, 0x00000000); /* disable all */
+ mtdcr (UIC3CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
+ mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC0SR, 0xfc000000); /* clear all */
+ mtdcr (UIC0ER, 0x00000000); /* disable all */
+ mtdcr (UIC0CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC0PR, 0xfc000000); /* */
+ mtdcr (UIC0TR, 0x00000000); /* */
+ mtdcr (UIC0VR, 0x00000001); /* */
+
+ /* Setup shutdown/SSD empty interrupt as inputs */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
+ out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
+
+ /* Setup GPIO/IRQ multiplexing */
+ mtsdr(SDR0_PFC0, 0x01a33e00);
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ unsigned short reg;
+
+ /*
+ * Configure LED's of both Marvell 88E1111 PHY's
+ *
+ * This has to be done after the 4xx ethernet driver is loaded,
+ * so "last_stage_init()" is the right place.
+ */
+ miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®);
+ reg |= 0x0001;
+ miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
+ miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®);
+ reg |= 0x0001;
+ miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
+
+ return 0;
+}
+
+static int board_rev(void)
+{
+ /* Setup as input */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
+ out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
+
+ return (in32(GPIO0_IR) >> 16) & 0x3;
+}
+
+int checkboard (void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf ("Board: ALPR");
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ printf(" (Rev. %d)\n", board_rev());
+
+ return (0);
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Override weak pci_pre_init()
+ */
+int pci_pre_init(struct pci_controller *hose)
+{
+ if (__pci_pre_init(hose) == 0)
+ return 0;
+
+ /* FPGA Init */
+ alpr_fpga_init();
+
+ return 1;
+}
+
+/*************************************************************************
+ * Override weak is_pci_host()
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+static void wait_for_pci_ready(void)
+{
+ /*
+ * Configure EREADY as input
+ */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY);
+ udelay(1000);
+
+ for (;;) {
+ if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY)
+ return;
+ }
+
+}
+
+int is_pci_host(struct pci_controller *hose)
+{
+ wait_for_pci_ready();
+ return 1; /* return 1 for host controller */
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ * pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+ /*--------------------------------------------------------------------------+
+ | PowerPC440 PCI Master configuration.
+ | Map PLB/processor addresses to PCI memory space.
+ | PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
+ | Use byte reversed out routines to handle endianess.
+ | Make this region non-prefetchable.
+ +--------------------------------------------------------------------------*/
+ out32r( PCIL0_POM0SA, 0 ); /* disable */
+ out32r( PCIL0_POM1SA, 0 ); /* disable */
+ out32r( PCIL0_POM2SA, 0 ); /* disable */
+
+ out32r(PCIL0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_POM0LAH, 0x00000003); /* PMM0 Local Address */
+ out32r(PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIL0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
+
+ out32r(PCIL0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIL0_POM1LAH, 0x00000003); /* PMM0 Local Address */
+ out32r(PCIL0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIL0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
+}
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
diff --git a/board/prodrive/alpr/config.mk b/board/prodrive/alpr/config.mk
new file mode 100644
index 0000000..0ccb2e6
--- /dev/null
+++ b/board/prodrive/alpr/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c
new file mode 100644
index 0000000..3133f94
--- /dev/null
+++ b/board/prodrive/alpr/fpga.c
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2006
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Altera FPGA configuration support for the ALPR computer from prodrive
+ */
+
+#include <common.h>
+#include <altera.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/ppc440.h>
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+#ifdef FPGA_DEBUG
+#define PRINTF(fmt, args...) printf(fmt , ##args)
+#else
+#define PRINTF(fmt, args...)
+#endif
+
+static unsigned long regval;
+
+#define SET_GPIO_REG_0(reg, bit) do { \
+ regval = in32(reg); \
+ regval &= ~(0x80000000 >> bit); \
+ out32(reg, regval); \
+ } while (0)
+
+#define SET_GPIO_REG_1(reg, bit) do { \
+ regval = in32(reg); \
+ regval |= (0x80000000 >> bit); \
+ out32(reg, regval); \
+ } while (0)
+
+#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
+#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
+
+#define FPGA_PRG (0x80000000 >> CONFIG_SYS_GPIO_PROG_EN)
+#define FPGA_CONFIG (0x80000000 >> CONFIG_SYS_GPIO_CONFIG)
+#define FPGA_DATA (0x80000000 >> CONFIG_SYS_GPIO_DATA)
+#define FPGA_CLK (0x80000000 >> CONFIG_SYS_GPIO_CLK)
+#define OLD_VAL (FPGA_PRG | FPGA_CONFIG)
+
+#define SET_FPGA(data) out32(GPIO0_OR, data)
+
+#define FPGA_WRITE_1 do { \
+ SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \
+ SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA); /* set data to 1 */ \
+} while (0)
+
+#define FPGA_WRITE_0 do { \
+ SET_FPGA(OLD_VAL | 0 | 0); /* set data to 0 */ \
+ SET_FPGA(OLD_VAL | FPGA_CLK | 0); /* set data to 1 */ \
+} while (0)
+
+/* Plattforminitializations */
+/* Here we have to set the FPGA Chain */
+/* PROGRAM_PROG_EN = HIGH */
+/* PROGRAM_SEL_DPR = LOW */
+int fpga_pre_fn(int cookie)
+{
+ /* Enable the FPGA Chain */
+ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN);
+ SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN);
+ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR);
+ SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR));
+
+ /* initialize the GPIO Pins */
+ /* output */
+ SET_GPIO_0(CONFIG_SYS_GPIO_CLK);
+ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK);
+
+ /* output */
+ SET_GPIO_0(CONFIG_SYS_GPIO_DATA);
+ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA);
+
+ /* First we set STATUS to 0 then as an input */
+ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
+ SET_GPIO_0(CONFIG_SYS_GPIO_STATUS);
+ SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
+
+ /* output */
+ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG);
+ SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
+
+ /* input */
+ SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON);
+ SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON);
+
+ /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
+ SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
+ return FPGA_SUCCESS;
+}
+
+/* Set the state of CONFIG Pin */
+int fpga_config_fn(int assert_config, int flush, int cookie)
+{
+ if (assert_config)
+ SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG);
+ else
+ SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
+
+ return FPGA_SUCCESS;
+}
+
+/* Returns the state of STATUS Pin */
+int fpga_status_fn(int cookie)
+{
+ unsigned long reg;
+
+ reg = in32(GPIO0_IR);
+ if (reg & (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) {
+ PRINTF("STATUS = HIGH\n");
+ return FPGA_FAIL;
+ }
+ PRINTF("STATUS = LOW\n");
+ return FPGA_SUCCESS;
+}
+
+/* Returns the state of CONF_DONE Pin */
+int fpga_done_fn(int cookie)
+{
+ unsigned long reg;
+ reg = in32(GPIO0_IR);
+ if (reg & (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) {
+ PRINTF("CONF_DON = HIGH\n");
+ return FPGA_FAIL;
+ }
+ PRINTF("CONF_DON = LOW\n");
+ return FPGA_SUCCESS;
+}
+
+/* writes the complete buffer to the FPGA
+ writing the complete buffer in one function is much faster,
+ then calling it for every bit */
+int fpga_write_fn(const void *buf, size_t len, int flush, int cookie)
+{
+ size_t bytecount = 0;
+ unsigned char *data = (unsigned char *) buf;
+ unsigned char val = 0;
+ int i;
+ int len_40 = len / 40;
+
+ while (bytecount < len) {
+ val = data[bytecount++];
+ i = 8;
+ do {
+ if (val & 0x01)
+ FPGA_WRITE_1;
+ else
+ FPGA_WRITE_0;
+
+ val >>= 1;
+ i--;
+ } while (i > 0);
+
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+ if (bytecount % len_40 == 0) {
+ putc('.'); /* let them know we are alive */
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
+ if (ctrlc())
+ return FPGA_FAIL;
+#endif
+ }
+#endif
+ }
+ return FPGA_SUCCESS;
+}
+
+/* called, when programming is aborted */
+int fpga_abort_fn(int cookie)
+{
+ SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR));
+ return FPGA_SUCCESS;
+}
+
+/* called, when programming was succesful */
+int fpga_post_fn(int cookie)
+{
+ return fpga_abort_fn(cookie);
+}
+
+/* Note that these are pointers to code that is in Flash. They will be
+ * relocated at runtime.
+ */
+Altera_CYC2_Passive_Serial_fns fpga_fns = {
+ fpga_pre_fn,
+ fpga_config_fn,
+ fpga_status_fn,
+ fpga_done_fn,
+ fpga_write_fn,
+ fpga_abort_fn,
+ fpga_post_fn
+};
+
+Altera_desc fpga[CONFIG_FPGA_COUNT] = {
+ {Altera_CYC2,
+ passive_serial,
+ Altera_EP2C35_SIZE,
+ (void *) &fpga_fns,
+ NULL,
+ 0}
+};
+
+/*
+ * Initialize the fpga. Return 1 on success, 0 on failure.
+ */
+int alpr_fpga_init(void)
+{
+ int i;
+
+ PRINTF("%s:%d: Initialize FPGA interface\n", __func__, __LINE__);
+ fpga_init();
+
+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+ PRINTF("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
+ fpga_add(fpga_altera, &fpga[i]);
+ }
+ return 1;
+}
+
+#endif
diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S
new file mode 100644
index 0000000..7ff7a59
--- /dev/null
+++ b/board/prodrive/alpr/init.S
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG )
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
+ tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
+#ifdef CONFIG_4xx_DCACHE
+ tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G)
+#else
+ tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG)
+#endif
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
+#endif
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
+
+ /* PCI */
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG)
+
+ /* NAND */
+ tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG)
+ tlbtab_end
diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c
new file mode 100644
index 0000000..5427de5
--- /dev/null
+++ b/board/prodrive/alpr/nand.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2006
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <asm/processor.h>
+#include <nand.h>
+
+struct alpr_ndfc_regs {
+ u8 cmd[4];
+ u8 addr_wait;
+ u8 term;
+ u8 dummy;
+ u8 dummy2;
+ u8 data;
+};
+
+static u8 hwctl;
+static struct alpr_ndfc_regs *alpr_ndfc = NULL;
+
+#define readb(addr) (u8)(*(volatile u8 *)(addr))
+#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d))
+
+/*
+ * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
+ * the NAND devices. The NDFC has command, address and data registers that
+ * when accessed will set up the NAND flash pins appropriately. We'll use the
+ * hwcontrol function to save the configuration in a global variable.
+ * We can then use this information in the read and write functions to
+ * determine which NDFC register to access.
+ *
+ * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
+ */
+static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if ( ctrl & NAND_CLE )
+ hwctl |= 0x1;
+ else
+ hwctl &= ~0x1;
+ if ( ctrl & NAND_ALE )
+ hwctl |= 0x2;
+ else
+ hwctl &= ~0x2;
+ if ( (ctrl & NAND_NCE) != NAND_NCE)
+ writeb(0x00, &(alpr_ndfc->term));
+ }
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+static u_char alpr_nand_read_byte(struct mtd_info *mtd)
+{
+ return readb(&(alpr_ndfc->data));
+}
+
+static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ struct nand_chip *nand = mtd->priv;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (hwctl & 0x1)
+ /*
+ * IO_ADDR_W used as CMD[i] reg to support multiple NAND
+ * chips.
+ */
+ writeb(buf[i], nand->IO_ADDR_W);
+ else if (hwctl & 0x2)
+ writeb(buf[i], &(alpr_ndfc->addr_wait));
+ else
+ writeb(buf[i], &(alpr_ndfc->data));
+ }
+}
+
+static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ buf[i] = readb(&(alpr_ndfc->data));
+ }
+}
+
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
+static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ if (buf[i] != readb(&(alpr_ndfc->data)))
+ return i;
+
+ return 0;
+}
+#endif
+
+static int alpr_nand_dev_ready(struct mtd_info *mtd)
+{
+ /*
+ * Blocking read to wait for NAND to be ready
+ */
+ (void)readb(&(alpr_ndfc->addr_wait));
+
+ /*
+ * Return always true
+ */
+ return 1;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE;
+
+ nand->ecc.mode = NAND_ECC_SOFT;
+
+ /* Reference hardware control function */
+ nand->cmd_ctrl = alpr_nand_hwcontrol;
+ nand->read_byte = alpr_nand_read_byte;
+ nand->write_buf = alpr_nand_write_buf;
+ nand->read_buf = alpr_nand_read_buf;
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
+ nand->verify_buf = alpr_nand_verify_buf;
+#endif
+ nand->dev_ready = alpr_nand_dev_ready;
+
+ return 0;
+}
+#endif
diff --git a/board/prodrive/p3p440/Kconfig b/board/prodrive/p3p440/Kconfig
new file mode 100644
index 0000000..cf53aac
--- /dev/null
+++ b/board/prodrive/p3p440/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_P3P440
+
+config SYS_BOARD
+ default "p3p440"
+
+config SYS_VENDOR
+ default "prodrive"
+
+config SYS_CONFIG_NAME
+ default "p3p440"
+
+endif
diff --git a/board/prodrive/p3p440/MAINTAINERS b/board/prodrive/p3p440/MAINTAINERS
new file mode 100644
index 0000000..68fd1a9
--- /dev/null
+++ b/board/prodrive/p3p440/MAINTAINERS
@@ -0,0 +1,6 @@
+P3P440 BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/prodrive/p3p440/
+F: include/configs/p3p440.h
+F: configs/p3p440_defconfig
diff --git a/board/prodrive/p3p440/Makefile b/board/prodrive/p3p440/Makefile
new file mode 100644
index 0000000..d62f75d
--- /dev/null
+++ b/board/prodrive/p3p440/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = p3p440.o
+extra-y += init.o
diff --git a/board/prodrive/p3p440/config.mk b/board/prodrive/p3p440/config.mk
new file mode 100644
index 0000000..f18b097
--- /dev/null
+++ b/board/prodrive/p3p440/config.mk
@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S
new file mode 100644
index 0000000..35b1afa
--- /dev/null
+++ b/board/prodrive/p3p440/init.S
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+ tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX )
+ tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX )
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
+ tlbtab_end
diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
new file mode 100644
index 0000000..929e8eb
--- /dev/null
+++ b/board/prodrive/p3p440/p3p440.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+
+#include "p3p440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void set_led(int color)
+{
+ switch (color) {
+ case LED_OFF:
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED);
+ break;
+
+ case LED_GREEN:
+ out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED);
+ break;
+
+ case LED_RED:
+ out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN);
+ break;
+
+ case LED_ORANGE:
+ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED);
+ break;
+ }
+}
+
+static int is_monarch(void)
+{
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY);
+ udelay(1000);
+
+ if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO)
+ return 0;
+ else
+ return 1;
+}
+
+static void wait_for_pci_ready(void)
+{
+ /*
+ * Configure EREADY_IO as input
+ */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO);
+ udelay(1000);
+
+ for (;;) {
+ if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO)
+ return;
+ }
+
+}
+
+int board_early_init_f(void)
+{
+ uint reg;
+
+ /*--------------------------------------------------------------------
+ * Setup the external bus controller/chip selects
+ *-------------------------------------------------------------------*/
+ mtdcr(EBC0_CFGADDR, EBC0_CFG);
+ reg = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
+
+ /*--------------------------------------------------------------------
+ * Setup pin multiplexing (GPIO/IRQ...)
+ *-------------------------------------------------------------------*/
+ mtdcr(CPC0_GPIO, 0x03F01F80);
+
+ out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN);
+ out32(GPIO0_OR, CONFIG_SYS_GPIO_RDY);
+
+ /*--------------------------------------------------------------------
+ * Setup the interrupt controller polarities, triggers, etc.
+ *-------------------------------------------------------------------*/
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */
+ mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: P3P440");
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+
+ if (is_monarch()) {
+ puts(", Monarch");
+ } else {
+ puts(", None-Monarch");
+ }
+
+ putc('\n');
+
+ return (0);
+}
+
+int misc_init_r (void)
+{
+ /*
+ * Adjust flash start and offset to detected values
+ */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /*
+ * Check if only one FLASH bank is available
+ */
+ if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
+ mtebc(PB1CR, 0); /* disable cs */
+ mtebc(PB1AP, 0);
+ mtebc(PB2CR, 0); /* disable cs */
+ mtebc(PB2AP, 0);
+ mtebc(PB3CR, 0); /* disable cs */
+ mtebc(PB3AP, 0);
+ }
+
+ return 0;
+}
+
+/*************************************************************************
+ * Override weak is_pci_host()
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+ if (is_monarch()) {
+ wait_for_pci_ready();
+ return 1; /* return 1 for host controller */
+ } else {
+ return 0; /* return 0 for adapter controller */
+ }
+}
+#endif /* defined(CONFIG_PCI) */
diff --git a/board/prodrive/p3p440/p3p440.h b/board/prodrive/p3p440/p3p440.h
new file mode 100644
index 0000000..a164f95
--- /dev/null
+++ b/board/prodrive/p3p440/p3p440.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __P3P440_H__
+#define __P3P440_H__
+
+#define CONFIG_SYS_GPIO_RDY (0x80000000 >> 11)
+#define CONFIG_SYS_MONARCH_IO (0x80000000 >> 18)
+#define CONFIG_SYS_EREADY_IO (0x80000000 >> 20)
+#define CONFIG_SYS_LED_GREEN (0x80000000 >> 21)
+#define CONFIG_SYS_LED_RED (0x80000000 >> 22)
+
+#define LED_OFF 1
+#define LED_GREEN 2
+#define LED_RED 3
+#define LED_ORANGE 4
+
+long int fixed_sdram(void);
+
+#endif /* __P3P440_H__ */
diff --git a/board/pxa255_idp/Kconfig b/board/pxa255_idp/Kconfig
new file mode 100644
index 0000000..5448311
--- /dev/null
+++ b/board/pxa255_idp/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_PXA255_IDP
+
+config SYS_BOARD
+ default "pxa255_idp"
+
+config SYS_CONFIG_NAME
+ default "pxa255_idp"
+
+endif
diff --git a/board/pxa255_idp/MAINTAINERS b/board/pxa255_idp/MAINTAINERS
new file mode 100644
index 0000000..24d7236
--- /dev/null
+++ b/board/pxa255_idp/MAINTAINERS
@@ -0,0 +1,6 @@
+PXA255_IDP BOARD
+M: Cliff Brake <cliff.brake@gmail.com>
+S: Maintained
+F: board/pxa255_idp/
+F: include/configs/pxa255_idp.h
+F: configs/pxa255_idp_defconfig
diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile
new file mode 100644
index 0000000..59d6967
--- /dev/null
+++ b/board/pxa255_idp/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := pxa_idp.o
diff --git a/board/pxa255_idp/README b/board/pxa255_idp/README
new file mode 100644
index 0000000..0cc2f2a
--- /dev/null
+++ b/board/pxa255_idp/README
@@ -0,0 +1,11 @@
+Tested:
+
+- MMC
+- Ethernet
+- BL console (on serial port connector J5)
+- flash support
+
+Todo:
+
+- display support
+- PCMCIA support
diff --git a/board/pxa255_idp/idp_notes.txt b/board/pxa255_idp/idp_notes.txt
new file mode 100644
index 0000000..4746748
--- /dev/null
+++ b/board/pxa255_idp/idp_notes.txt
@@ -0,0 +1,46 @@
+Notes on the Vibren PXA255 IDP.
+
+Chip select usage:
+
+CS0 - flash
+CS1 - alt flash (Mdoc or main flash)
+CS2 - high speed expansion bus
+CS3 - Media Q, low speed exp bus
+CS4 - low speed exp bus
+CS5 - low speed exp bus
+ - IDE: offset 0x03000000 (abs: 0x17000000)
+ - Eth: offset 0x03400000 (abs: 0x17400000)
+ - core voltage latch: offset 0x03800000 (abs: 0x17800000)
+ - CPLD: offset 0x03C00000 (abs: 0x17C00000)
+
+PCMCIA Power control
+
+MAX1602EE w/ code pulled high (Cirrus code)
+vx = 5v
+vy = 3v
+
+ Bit pattern
+ PWR 3,2,1,0
+vcc vpp A1VCC A0VCC A1VPP A0VPP
+=====================================================
+0 0 0 0 0 0 0x0
+3 (vy) 0 1 0 1 1 0xB
+3 (vy) 3 (vy) 1 0 0 1 0x9
+3 (vy) 12(12in) 1 0 1 0 0xA
+5 (vx) 0 0 1 1 1 0x7
+5 (vx) 5 (vx) 0 1 0 1 0x5
+5 (vx 12(12in) 0 1 1 0 0x6
+
+Display power sequencing:
+
+- VDD applied
+- within 1sec, activate scanning signals
+- wait at least 50mS - scanning signals must be active before activating DISP
+
+Signal mapping:
+Schematic LV8V31 signal name
+=========================================
+LCD_ENAVLCD DISP
+LCD_PWR Applies VDD to board
+
+Both of the above signals are controlled by the CPLD
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
new file mode 100644
index 0000000..197ff3e
--- /dev/null
+++ b/board/pxa255_idp/pxa_idp.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2004
+ * BEC Systems <http://bec-systems.com>
+ * Cliff Brake <cliff.brake@gmail.com>
+ * Support for Accelent/Vibren PXA255 IDP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/arch/pxa.h>
+#include <asm/arch/regs-mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* arch number of Lubbock-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* turn on serial ports */
+ *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C0002c) = 0x13;
+
+ /* set PWM for LCD */
+ /* a value that works is 60Hz, 77% duty cycle */
+ writel(readl(CKEN) | CKEN0_PWM0, CKEN);
+ writel(0x3f, PWM_CTRL0);
+ writel(0x3ff, PWM_PERVAL0);
+ writel(792, PWM_PWDUTY0);
+
+ /* clear reset to AC97 codec */
+ writel(readl(CKEN) | CKEN2_AC97, CKEN);
+ writel(GCR_COLD_RST, GCR);
+
+ /* enable LCD backlight */
+ /* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
+
+ /* test display */
+ /* lcd_puts("This is a test\nTest #2\n"); */
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ return 0;
+}
+
+int dram_init(void)
+{
+ pxa2xx_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef DEBUG_BLINKC_ENABLE
+
+void delay_c(void)
+{
+ /* reset OSCR to 0 */
+ writel(0, OSCR);
+ while (readl(OSCR) > 0x10000)
+ ;
+
+ while (readl(OSCR) < 0xd4000)
+ ;
+}
+
+void blink_c(void)
+{
+ int led_bit = (1<<10);
+
+ writel(led_bit, GPDR0);
+ writel(led_bit, GPCR0);
+ delay_c();
+ writel(led_bit, GPSR0);
+ delay_c();
+ writel(led_bit, GPCR0);
+}
+
+int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ printf("IDPCMD started\n");
+ return 0;
+}
+
+U_BOOT_CMD(idpcmd, CONFIG_SYS_MAXARGS, 0, do_idpcmd,
+ "custom IDP command",
+ "no args at this time"
+);
+
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/pxa255_idp/pxa_reg_calcs.out b/board/pxa255_idp/pxa_reg_calcs.out
new file mode 100644
index 0000000..39295fb
--- /dev/null
+++ b/board/pxa255_idp/pxa_reg_calcs.out
@@ -0,0 +1,119 @@
+gafr0_l: 0x80001005
+gafr0_u: 0xa5128012
+gafr1_l: 0x699a9558
+gafr1_u: 0xaaa5aa6a
+gafr2_l: 0xaaaaaaaa
+gafr2_u: 0x2
+gpcr0: 0x1800400
+gpcr1: 0x0
+gpcr2: 0x0
+gpdr0: 0xc1818440
+gpdr1: 0xfcffab82
+gpdr2: 0x1ffff
+gpsr0: 0x8000
+gpsr1: 0x3f0002
+gpsr2: 0x1c000
+
+
+#define CONFIG_SYS_GAFR0_L_VAL 0x80001005
+#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012
+#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558
+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a
+#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL 0x2
+#define CONFIG_SYS_GPCR0_VAL 0x1800400
+#define CONFIG_SYS_GPCR1_VAL 0x0
+#define CONFIG_SYS_GPCR2_VAL 0x0
+#define CONFIG_SYS_GPDR0_VAL 0xc1818440
+#define CONFIG_SYS_GPDR1_VAL 0xfcffab82
+#define CONFIG_SYS_GPDR2_VAL 0x1ffff
+#define CONFIG_SYS_GPSR0_VAL 0x8000
+#define CONFIG_SYS_GPSR1_VAL 0x3f0002
+#define CONFIG_SYS_GPSR2_VAL 0x1c000
+
+
+GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET#
+GPIO: 1, dir=0, set=0, clr=0, alt=gpio reset, desc=USER_RESET#
+GPIO: 2, dir=0, set=0, clr=0, alt=gpio, desc=BAT_DATA
+GPIO: 3, dir=0, set=0, clr=0, alt=gpio, desc=MQ_IRQ#
+GPIO: 4, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_ETH
+GPIO: 5, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_TOUCH#
+GPIO: 6, dir=1, set=0, clr=0, alt=MMC clk, desc=MMC_CLK
+GPIO: 7, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S0_CD#
+GPIO: 8, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S1_CD#
+GPIO: 9, dir=0, set=0, clr=0, alt=gpio, desc=MMC_CD#
+GPIO: 10, dir=1, set=0, clr=1, alt=gpio, desc=GPIO_10/RTC_CLK/debug LED
+GPIO: 11, dir=0, set=0, clr=0, alt=gpio, desc=3M6_CLK
+GPIO: 12, dir=0, set=0, clr=0, alt=gpio, desc=GPIO_12/32K_CLK
+GPIO: 13, dir=0, set=0, clr=0, alt=gpio, desc=MBGNT
+GPIO: 14, dir=0, set=0, clr=0, alt=gpio, desc=MBREQ
+GPIO: 15, dir=1, set=1, clr=0, alt=nCS_1, desc=CS1#
+GPIO: 16, dir=1, set=0, clr=0, alt=PWM0, desc=PWM0
+GPIO: 17, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_AXB
+GPIO: 18, dir=0, set=0, clr=0, alt=RDY, desc=RDY
+GPIO: 19, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ1, PCC_SO_IRQ_O#
+GPIO: 20, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ0
+GPIO: 21, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_IDE, PFI
+GPIO: 22, dir=0, set=0, clr=0, alt=gpio, desc=Consumer IR, PCC_S1_IRQ_O#
+GPIO: 23, dir=1, set=0, clr=1, alt=SSP SCLK, desc=SSP_SCLK
+GPIO: 24, dir=1, set=0, clr=1, alt=SSP SFRM, desc=SSP_SFRM
+GPIO: 25, dir=0, set=0, clr=0, alt=gpio, desc=SSP_TXD
+GPIO: 26, dir=0, set=0, clr=0, alt=SSP RXD, desc=SSP_RXD
+GPIO: 27, dir=0, set=0, clr=0, alt=gpio, desc=SSP_EXTCLK
+GPIO: 28, dir=0, set=0, clr=0, alt=AC97 bitclk in, I2S bitclock out, desc=AC_BITCLK
+GPIO: 29, dir=0, set=0, clr=0, alt=AC97 SDATA_IN0, desc=AUD_SDIN0
+GPIO: 30, dir=1, set=0, clr=0, alt=AC97 SDATA_OUT, desc=AC_SDOUT
+GPIO: 31, dir=1, set=0, clr=0, alt=AC97 SYNC, desc=AC_SYNC
+GPIO: 32, dir=0, set=0, clr=0, alt=gpio, desc=AUD_SDIN1
+GPIO: 33, dir=1, set=1, clr=0, alt=nCS_5, desc=CS5#
+GPIO: 34, dir=0, set=0, clr=0, alt=FF RXD, desc=FF_RXD
+GPIO: 35, dir=0, set=0, clr=0, alt=FF CTS, desc=FF_CTS
+GPIO: 36, dir=0, set=0, clr=0, alt=FF DCD, desc=FF_DCD
+GPIO: 37, dir=0, set=0, clr=0, alt=FF DSR, desc=FF_DSR
+GPIO: 38, dir=0, set=0, clr=0, alt=FF RI, desc=FF_RI
+GPIO: 39, dir=1, set=0, clr=0, alt=FF TXD, desc=FF_TXD
+GPIO: 40, dir=1, set=0, clr=0, alt=FF DTR, desc=FF_DTR
+GPIO: 41, dir=1, set=0, clr=0, alt=FF RTS, desc=FF_RTS
+GPIO: 42, dir=0, set=0, clr=0, alt=BT RXD, desc=BT_RXD
+GPIO: 43, dir=1, set=0, clr=0, alt=BT TXD, desc=BT_TXD
+GPIO: 44, dir=0, set=0, clr=0, alt=BT CTS, desc=BT_CTS
+GPIO: 45, dir=1, set=0, clr=0, alt=BT RTS, desc=BT_RTS
+GPIO: 46, dir=0, set=0, clr=0, alt=STD RXD, desc=IR_RXD
+GPIO: 47, dir=1, set=0, clr=0, alt=STD TXD, desc=IR_TXD
+GPIO: 48, dir=1, set=1, clr=0, alt=nPOE, desc=PCC_OE#
+GPIO: 49, dir=1, set=1, clr=0, alt=nPWE, desc=PCC_WE#
+GPIO: 50, dir=1, set=1, clr=0, alt=nPIOR, desc=PCC_IOR#
+GPIO: 51, dir=1, set=1, clr=0, alt=nPIOW, desc=PCC_IOW#
+GPIO: 52, dir=1, set=1, clr=0, alt=nPCE[1], desc=PCC_CE1#
+GPIO: 53, dir=1, set=1, clr=0, alt=nPCE[2], desc=PCC_CE2#
+GPIO: 54, dir=1, set=0, clr=0, alt=nPSKSEL, desc=PCC_SCKSEL
+GPIO: 55, dir=1, set=0, clr=0, alt=nPREG, desc=PCC_REG#
+GPIO: 56, dir=0, set=0, clr=0, alt=nPWAIT, desc=PCC_WAIT#
+GPIO: 57, dir=0, set=0, clr=0, alt=nIOIS16, desc=PCC_IOIS16#
+GPIO: 58, dir=1, set=0, clr=0, alt=LDD[0], desc=LDD0
+GPIO: 59, dir=1, set=0, clr=0, alt=LDD[1], desc=LDD1
+GPIO: 60, dir=1, set=0, clr=0, alt=LDD[2], desc=LDD2
+GPIO: 61, dir=1, set=0, clr=0, alt=LDD[3], desc=LDD3
+GPIO: 62, dir=1, set=0, clr=0, alt=LDD[4], desc=LDD4
+GPIO: 63, dir=1, set=0, clr=0, alt=LDD[5], desc=LDD5
+GPIO: 64, dir=1, set=0, clr=0, alt=LDD[6], desc=LDD6
+GPIO: 65, dir=1, set=0, clr=0, alt=LDD[7], desc=LDD7
+GPIO: 66, dir=1, set=0, clr=0, alt=LDD[8], desc=LDD8
+GPIO: 67, dir=1, set=0, clr=0, alt=LDD[9], desc=LDD9
+GPIO: 68, dir=1, set=0, clr=0, alt=LDD[10], desc=LDD10
+GPIO: 69, dir=1, set=0, clr=0, alt=LDD[11], desc=LDD11
+GPIO: 70, dir=1, set=0, clr=0, alt=LDD[12], desc=LDD12
+GPIO: 71, dir=1, set=0, clr=0, alt=LDD[13], desc=LDD13
+GPIO: 72, dir=1, set=0, clr=0, alt=LDD[14], desc=LDD14
+GPIO: 73, dir=1, set=0, clr=0, alt=LDD[15], desc=LDD15
+GPIO: 74, dir=1, set=0, clr=0, alt=LCD_FCLK, desc=FCLK
+GPIO: 75, dir=1, set=0, clr=0, alt=LCD_LCLK, desc=LCLK
+GPIO: 76, dir=1, set=0, clr=0, alt=LCD_PCLK, desc=PCLK
+GPIO: 77, dir=1, set=0, clr=0, alt=LCD_ACBIAS, desc=ACBIAS
+GPIO: 78, dir=1, set=1, clr=0, alt=nCS_2, desc=CS2#
+GPIO: 79, dir=1, set=1, clr=0, alt=nCS_3, desc=CS3#
+GPIO: 80, dir=1, set=1, clr=0, alt=nCS_4, desc=CS4#
+GPIO: 81, dir=0, set=0, clr=0, alt=gpio, desc=
+GPIO: 82, dir=0, set=0, clr=0, alt=gpio, desc=
+GPIO: 83, dir=0, set=0, clr=0, alt=gpio, desc=
+GPIO: 84, dir=0, set=0, clr=0, alt=gpio, desc=
diff --git a/board/pxa255_idp/pxa_reg_calcs.py b/board/pxa255_idp/pxa_reg_calcs.py
new file mode 100644
index 0000000..4a721d1
--- /dev/null
+++ b/board/pxa255_idp/pxa_reg_calcs.py
@@ -0,0 +1,298 @@
+#!/usr/bin/python
+
+# (C) Copyright 2004
+# BEC Systems <http://bec-systems.com>
+# Cliff Brake <cliff.brake@gmail.com>
+
+# SPDX-License-Identifier: GPL-2.0+
+
+# calculations for PXA255 registers
+
+class gpio:
+ dir = '0'
+ set = '0'
+ clr = '0'
+ alt = '0'
+ desc = ''
+
+ def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
+ self.dir = dir
+ self.set = set
+ self.clr = clr
+ self.alt = alt
+ self.desc = desc
+
+
+# the following is a dictionary of all GPIOs in the system
+# the key is the GPIO number
+
+
+pxa255_alt_func = {
+ 0: ['gpio', 'none', 'none', 'none'],
+ 1: ['gpio', 'gpio reset', 'none', 'none'],
+ 2: ['gpio', 'none', 'none', 'none'],
+ 3: ['gpio', 'none', 'none', 'none'],
+ 4: ['gpio', 'none', 'none', 'none'],
+ 5: ['gpio', 'none', 'none', 'none'],
+ 6: ['gpio', 'MMC clk', 'none', 'none'],
+ 7: ['gpio', '48MHz clock', 'none', 'none'],
+ 8: ['gpio', 'MMC CS0', 'none', 'none'],
+ 9: ['gpio', 'MMC CS1', 'none', 'none'],
+ 10: ['gpio', 'RTC Clock', 'none', 'none'],
+ 11: ['gpio', '3.6MHz', 'none', 'none'],
+ 12: ['gpio', '32KHz', 'none', 'none'],
+ 13: ['gpio', 'none', 'MBGNT', 'none'],
+ 14: ['gpio', 'MBREQ', 'none', 'none'],
+ 15: ['gpio', 'none', 'nCS_1', 'none'],
+ 16: ['gpio', 'none', 'PWM0', 'none'],
+ 17: ['gpio', 'none', 'PWM1', 'none'],
+ 18: ['gpio', 'RDY', 'none', 'none'],
+ 19: ['gpio', 'DREQ[1]', 'none', 'none'],
+ 20: ['gpio', 'DREQ[0]', 'none', 'none'],
+ 21: ['gpio', 'none', 'none', 'none'],
+ 22: ['gpio', 'none', 'none', 'none'],
+ 23: ['gpio', 'none', 'SSP SCLK', 'none'],
+ 24: ['gpio', 'none', 'SSP SFRM', 'none'],
+ 25: ['gpio', 'none', 'SSP TXD', 'none'],
+ 26: ['gpio', 'SSP RXD', 'none', 'none'],
+ 27: ['gpio', 'SSP EXTCLK', 'none', 'none'],
+ 28: ['gpio', 'AC97 bitclk in, I2S bitclock out', 'I2S bitclock in', 'none'],
+ 29: ['gpio', 'AC97 SDATA_IN0', 'I2S SDATA_IN', 'none'],
+ 30: ['gpio', 'I2S SDATA_OUT', 'AC97 SDATA_OUT', 'none'],
+ 31: ['gpio', 'I2S SYNC', 'AC97 SYNC', 'none'],
+ 32: ['gpio', 'AC97 SDATA_IN1', 'I2S SYSCLK', 'none'],
+ 33: ['gpio', 'none', 'nCS_5', 'none'],
+ 34: ['gpio', 'FF RXD', 'MMC CS0', 'none'],
+ 35: ['gpio', 'FF CTS', 'none', 'none'],
+ 36: ['gpio', 'FF DCD', 'none', 'none'],
+ 37: ['gpio', 'FF DSR', 'none', 'none'],
+ 38: ['gpio', 'FF RI', 'none', 'none'],
+ 39: ['gpio', 'MMC CS1', 'FF TXD', 'none'],
+ 40: ['gpio', 'none', 'FF DTR', 'none'],
+ 41: ['gpio', 'none', 'FF RTS', 'none'],
+ 42: ['gpio', 'BT RXD', 'none', 'HW RXD'],
+ 43: ['gpio', 'none', 'BT TXD', 'HW TXD'],
+ 44: ['gpio', 'BT CTS', 'none', 'HW CTS'],
+ 45: ['gpio', 'none', 'BT RTS', 'HW RTS'],
+ 46: ['gpio', 'ICP_RXD', 'STD RXD', 'none'],
+ 47: ['gpio', 'STD TXD', 'ICP_TXD', 'none'],
+ 48: ['gpio', 'HW TXD', 'nPOE', 'none'],
+ 49: ['gpio', 'HW RXD', 'nPWE', 'none'],
+ 50: ['gpio', 'HW CTS', 'nPIOR', 'none'],
+ 51: ['gpio', 'nPIOW', 'HW RTS', 'none'],
+ 52: ['gpio', 'none', 'nPCE[1]', 'none'],
+ 53: ['gpio', 'MMC CLK', 'nPCE[2]', 'none'],
+ 54: ['gpio', 'MMC CLK', 'nPSKSEL', 'none'],
+ 55: ['gpio', 'none', 'nPREG', 'none'],
+ 56: ['gpio', 'nPWAIT', 'none', 'none'],
+ 57: ['gpio', 'nIOIS16', 'none', 'none'],
+ 58: ['gpio', 'none', 'LDD[0]', 'none'],
+ 59: ['gpio', 'none', 'LDD[1]', 'none'],
+ 60: ['gpio', 'none', 'LDD[2]', 'none'],
+ 61: ['gpio', 'none', 'LDD[3]', 'none'],
+ 62: ['gpio', 'none', 'LDD[4]', 'none'],
+ 63: ['gpio', 'none', 'LDD[5]', 'none'],
+ 64: ['gpio', 'none', 'LDD[6]', 'none'],
+ 65: ['gpio', 'none', 'LDD[7]', 'none'],
+ 66: ['gpio', 'MBREQ', 'LDD[8]', 'none'],
+ 67: ['gpio', 'MMC CS0', 'LDD[9]', 'none'],
+ 68: ['gpio', 'MMC CS1', 'LDD[10]', 'none'],
+ 69: ['gpio', 'MMC CLK', 'LDD[11]', 'none'],
+ 70: ['gpio', 'RTC CLK', 'LDD[12]', 'none'],
+ 71: ['gpio', '3.6 MHz', 'LDD[13]', 'none'],
+ 72: ['gpio', '32 KHz', 'LDD[14]', 'none'],
+ 73: ['gpio', 'MBGNT', 'LDD[15]', 'none'],
+ 74: ['gpio', 'none', 'LCD_FCLK', 'none'],
+ 75: ['gpio', 'none', 'LCD_LCLK', 'none'],
+ 76: ['gpio', 'none', 'LCD_PCLK', 'none'],
+ 77: ['gpio', 'none', 'LCD_ACBIAS', 'none'],
+ 78: ['gpio', 'none', 'nCS_2', 'none'],
+ 79: ['gpio', 'none', 'nCS_3', 'none'],
+ 80: ['gpio', 'none', 'nCS_4', 'none'],
+ 81: ['gpio', 'NSSPSCLK', 'none', 'none'],
+ 82: ['gpio', 'NSSPSFRM', 'none', 'none'],
+ 83: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
+ 84: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
+}
+
+
+#def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
+
+gpio_list = []
+
+for i in range(0,85):
+ gpio_list.append(gpio())
+
+#chip select GPIOs
+gpio_list[18] = gpio(0, 0, 0, 1, 'RDY')
+gpio_list[33] = gpio(1, 1, 0, 2, 'CS5#')
+gpio_list[80] = gpio(1, 1, 0, 2, 'CS4#')
+gpio_list[79] = gpio(1, 1, 0, 2, 'CS3#')
+gpio_list[78] = gpio(1, 1, 0, 2, 'CS2#')
+gpio_list[15] = gpio(1, 1, 0, 2, 'CS1#')
+gpio_list[22] = gpio(0, 0, 0, 0, 'Consumer IR, PCC_S1_IRQ_O#')
+gpio_list[21] = gpio(0, 0, 0, 0, 'IRQ_IDE, PFI')
+gpio_list[19] = gpio(0, 0, 0, 0, 'XB_DREQ1, PCC_SO_IRQ_O#')
+gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
+gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
+gpio_list[17] = gpio(0, 0, 0, 0, 'IRQ_AXB')
+gpio_list[16] = gpio(1, 0, 0, 2, 'PWM0')
+
+# PCMCIA stuff
+gpio_list[57] = gpio(0, 0, 0, 1, 'PCC_IOIS16#')
+gpio_list[56] = gpio(0, 0, 0, 1, 'PCC_WAIT#')
+gpio_list[55] = gpio(1, 0, 0, 2, 'PCC_REG#')
+gpio_list[54] = gpio(1, 0, 0, 2, 'PCC_SCKSEL')
+gpio_list[53] = gpio(1, 1, 0, 2, 'PCC_CE2#')
+gpio_list[52] = gpio(1, 1, 0, 2, 'PCC_CE1#')
+gpio_list[51] = gpio(1, 1, 0, 1, 'PCC_IOW#')
+gpio_list[50] = gpio(1, 1, 0, 2, 'PCC_IOR#')
+gpio_list[49] = gpio(1, 1, 0, 2, 'PCC_WE#')
+gpio_list[48] = gpio(1, 1, 0, 2, 'PCC_OE#')
+
+# SSP port
+gpio_list[26] = gpio(0, 0, 0, 1, 'SSP_RXD')
+gpio_list[25] = gpio(0, 0, 0, 0, 'SSP_TXD')
+gpio_list[24] = gpio(1, 0, 1, 2, 'SSP_SFRM')
+gpio_list[23] = gpio(1, 0, 1, 2, 'SSP_SCLK')
+gpio_list[27] = gpio(0, 0, 0, 0, 'SSP_EXTCLK')
+
+# audio codec
+gpio_list[32] = gpio(0, 0, 0, 0, 'AUD_SDIN1')
+gpio_list[31] = gpio(1, 0, 0, 2, 'AC_SYNC')
+gpio_list[30] = gpio(1, 0, 0, 2, 'AC_SDOUT')
+gpio_list[29] = gpio(0, 0, 0, 1, 'AUD_SDIN0')
+gpio_list[28] = gpio(0, 0, 0, 1, 'AC_BITCLK')
+
+# serial ports
+gpio_list[39] = gpio(1, 0, 0, 2, 'FF_TXD')
+gpio_list[34] = gpio(0, 0, 0, 1, 'FF_RXD')
+gpio_list[41] = gpio(1, 0, 0, 2, 'FF_RTS')
+gpio_list[35] = gpio(0, 0, 0, 1, 'FF_CTS')
+gpio_list[40] = gpio(1, 0, 0, 2, 'FF_DTR')
+gpio_list[37] = gpio(0, 0, 0, 1, 'FF_DSR')
+gpio_list[38] = gpio(0, 0, 0, 1, 'FF_RI')
+gpio_list[36] = gpio(0, 0, 0, 1, 'FF_DCD')
+
+gpio_list[43] = gpio(1, 0, 0, 2, 'BT_TXD')
+gpio_list[42] = gpio(0, 0, 0, 1, 'BT_RXD')
+gpio_list[45] = gpio(1, 0, 0, 2, 'BT_RTS')
+gpio_list[44] = gpio(0, 0, 0, 1, 'BT_CTS')
+
+gpio_list[47] = gpio(1, 0, 0, 1, 'IR_TXD')
+gpio_list[46] = gpio(0, 0, 0, 2, 'IR_RXD')
+
+# misc GPIO signals
+gpio_list[14] = gpio(0, 0, 0, 0, 'MBREQ')
+gpio_list[13] = gpio(0, 0, 0, 0, 'MBGNT')
+gpio_list[12] = gpio(0, 0, 0, 0, 'GPIO_12/32K_CLK')
+gpio_list[11] = gpio(0, 0, 0, 0, '3M6_CLK')
+gpio_list[10] = gpio(1, 0, 1, 0, 'GPIO_10/RTC_CLK/debug LED')
+gpio_list[9] = gpio(0, 0, 0, 0, 'MMC_CD#')
+gpio_list[8] = gpio(0, 0, 0, 0, 'PCC_S1_CD#')
+gpio_list[7] = gpio(0, 0, 0, 0, 'PCC_S0_CD#')
+gpio_list[6] = gpio(1, 0, 0, 1, 'MMC_CLK')
+gpio_list[5] = gpio(0, 0, 0, 0, 'IRQ_TOUCH#')
+gpio_list[4] = gpio(0, 0, 0, 0, 'IRQ_ETH')
+gpio_list[3] = gpio(0, 0, 0, 0, 'MQ_IRQ#')
+gpio_list[2] = gpio(0, 0, 0, 0, 'BAT_DATA')
+gpio_list[1] = gpio(0, 0, 0, 1, 'USER_RESET#')
+gpio_list[0] = gpio(0, 0, 0, 1, 'USER_RESET#')
+
+# LCD GPIOs
+gpio_list[58] = gpio(1, 0, 0, 2, 'LDD0')
+gpio_list[59] = gpio(1, 0, 0, 2, 'LDD1')
+gpio_list[60] = gpio(1, 0, 0, 2, 'LDD2')
+gpio_list[61] = gpio(1, 0, 0, 2, 'LDD3')
+gpio_list[62] = gpio(1, 0, 0, 2, 'LDD4')
+gpio_list[63] = gpio(1, 0, 0, 2, 'LDD5')
+gpio_list[64] = gpio(1, 0, 0, 2, 'LDD6')
+gpio_list[65] = gpio(1, 0, 0, 2, 'LDD7')
+gpio_list[66] = gpio(1, 0, 0, 2, 'LDD8')
+gpio_list[67] = gpio(1, 0, 0, 2, 'LDD9')
+gpio_list[68] = gpio(1, 0, 0, 2, 'LDD10')
+gpio_list[69] = gpio(1, 0, 0, 2, 'LDD11')
+gpio_list[70] = gpio(1, 0, 0, 2, 'LDD12')
+gpio_list[71] = gpio(1, 0, 0, 2, 'LDD13')
+gpio_list[72] = gpio(1, 0, 0, 2, 'LDD14')
+gpio_list[73] = gpio(1, 0, 0, 2, 'LDD15')
+gpio_list[74] = gpio(1, 0, 0, 2, 'FCLK')
+gpio_list[75] = gpio(1, 0, 0, 2, 'LCLK')
+gpio_list[76] = gpio(1, 0, 0, 2, 'PCLK')
+gpio_list[77] = gpio(1, 0, 0, 2, 'ACBIAS')
+
+# calculate registers
+pxa_regs = {
+ 'gpdr0':0, 'gpdr1':0, 'gpdr2':0,
+ 'gpsr0':0, 'gpsr1':0, 'gpsr2':0,
+ 'gpcr0':0, 'gpcr1':0, 'gpcr2':0,
+ 'gafr0_l':0, 'gafr0_u':0,
+ 'gafr1_l':0, 'gafr1_u':0,
+ 'gafr2_l':0, 'gafr2_u':0,
+}
+
+# U-boot define names
+uboot_reg_names = {
+ 'gpdr0':'CONFIG_SYS_GPDR0_VAL', 'gpdr1':'CONFIG_SYS_GPDR1_VAL', 'gpdr2':'CONFIG_SYS_GPDR2_VAL',
+ 'gpsr0':'CONFIG_SYS_GPSR0_VAL', 'gpsr1':'CONFIG_SYS_GPSR1_VAL', 'gpsr2':'CONFIG_SYS_GPSR2_VAL',
+ 'gpcr0':'CONFIG_SYS_GPCR0_VAL', 'gpcr1':'CONFIG_SYS_GPCR1_VAL', 'gpcr2':'CONFIG_SYS_GPCR2_VAL',
+ 'gafr0_l':'CONFIG_SYS_GAFR0_L_VAL', 'gafr0_u':'CONFIG_SYS_GAFR0_U_VAL',
+ 'gafr1_l':'CONFIG_SYS_GAFR1_L_VAL', 'gafr1_u':'CONFIG_SYS_GAFR1_U_VAL',
+ 'gafr2_l':'CONFIG_SYS_GAFR2_L_VAL', 'gafr2_u':'CONFIG_SYS_GAFR2_U_VAL',
+}
+
+# bit mappings
+
+bit_mappings = [
+
+{ 'gpio':(0,32), 'shift':1, 'regs':{'dir':'gpdr0', 'set':'gpsr0', 'clr':'gpcr0'} },
+{ 'gpio':(32,64), 'shift':1, 'regs':{'dir':'gpdr1', 'set':'gpsr1', 'clr':'gpcr1'} },
+{ 'gpio':(64,85), 'shift':1, 'regs':{'dir':'gpdr2', 'set':'gpsr2', 'clr':'gpcr2'} },
+{ 'gpio':(0,16), 'shift':2, 'regs':{'alt':'gafr0_l'} },
+{ 'gpio':(16,32), 'shift':2, 'regs':{'alt':'gafr0_u'} },
+{ 'gpio':(32,48), 'shift':2, 'regs':{'alt':'gafr1_l'} },
+{ 'gpio':(48,64), 'shift':2, 'regs':{'alt':'gafr1_u'} },
+{ 'gpio':(64,80), 'shift':2, 'regs':{'alt':'gafr2_l'} },
+{ 'gpio':(80,85), 'shift':2, 'regs':{'alt':'gafr2_u'} },
+
+]
+
+def stuff_bits(bit_mapping, gpio_list):
+ gpios = range( bit_mapping['gpio'][0], bit_mapping['gpio'][1])
+
+ for gpio in gpios:
+ for reg in bit_mapping['regs'].keys():
+ value = eval( 'gpio_list[gpio].%s' % (reg) )
+ if ( value ):
+ # we have a high bit
+ bit_shift = (gpio - bit_mapping['gpio'][0]) * bit_mapping['shift']
+ bit = value << (bit_shift)
+ pxa_regs[bit_mapping['regs'][reg]] |= bit
+
+for i in bit_mappings:
+ stuff_bits(i, gpio_list)
+
+# now print out all regs
+registers = pxa_regs.keys()
+registers.sort()
+for reg in registers:
+ print '%s: 0x%x' % (reg, pxa_regs[reg])
+
+# print define to past right into U-Boot source code
+
+print
+print
+
+for reg in registers:
+ print '#define %s 0x%x' % (uboot_reg_names[reg], pxa_regs[reg])
+
+# print all GPIOS
+print
+print
+
+for i in range(len(gpio_list)):
+ gpio_i = gpio_list[i]
+ alt_func_desc = pxa255_alt_func[i][gpio_i.alt]
+ print 'GPIO: %i, dir=%i, set=%i, clr=%i, alt=%s, desc=%s' % (i, gpio_i.dir, gpio_i.set, gpio_i.clr, alt_func_desc, gpio_i.desc)
+
+
diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
new file mode 100644
index 0000000..18d78b5
--- /dev/null
+++ b/board/qemu-mips/Kconfig
@@ -0,0 +1,10 @@
+if TARGET_QEMU_MIPS
+
+config SYS_BOARD
+ default "qemu-mips"
+
+config SYS_CONFIG_NAME
+ default "qemu-mips" if 32BIT
+ default "qemu-mips64" if 64BIT
+
+endif
diff --git a/board/qemu-mips/MAINTAINERS b/board/qemu-mips/MAINTAINERS
new file mode 100644
index 0000000..334f9d8
--- /dev/null
+++ b/board/qemu-mips/MAINTAINERS
@@ -0,0 +1,14 @@
+QEMU-MIPS BOARD
+M: Vlad Lungu <vlad.lungu@windriver.com>
+S: Maintained
+F: board/qemu-mips/
+F: include/configs/qemu-mips.h
+F: configs/qemu_mips_defconfig
+
+QEMU_MIPSEL BOARD
+#M: -
+S: Maintained
+F: configs/qemu_mipsel_defconfig
+F: include/configs/qemu-mips64.h
+F: configs/qemu_mips64_defconfig
+F: configs/qemu_mips64el_defconfig
diff --git a/board/qemu-mips/Makefile b/board/qemu-mips/Makefile
new file mode 100644
index 0000000..8040573
--- /dev/null
+++ b/board/qemu-mips/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = qemu-mips.o
+obj-y += lowlevel_init.o
diff --git a/board/qemu-mips/lowlevel_init.S b/board/qemu-mips/lowlevel_init.S
new file mode 100644
index 0000000..b0f7072
--- /dev/null
+++ b/board/qemu-mips/lowlevel_init.S
@@ -0,0 +1,40 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+ .text
+ .set noreorder
+ .set mips32
+
+ .globl lowlevel_init
+lowlevel_init:
+
+ /*
+ * Step 2) Establish Status Register
+ * (set BEV, clear ERL, clear EXL, clear IE)
+ */
+ li t1, 0x00400000
+ mtc0 t1, CP0_STATUS
+
+ /*
+ * Step 3) Establish CP0 Config0
+ * (set K0=3)
+ */
+ li t1, 0x00000003
+ mtc0 t1, CP0_CONFIG
+
+ /*
+ * Step 7) Establish Cause
+ * (set IV bit)
+ */
+ li t1, 0x00800000
+ mtc0 t1, CP0_CAUSE
+
+ /* Establish Wired (and Random) */
+ mtc0 zero, CP0_WIRED
+ nop
+
+ jr ra
+ nop
diff --git a/board/qemu-mips/qemu-mips.c b/board/qemu-mips/qemu-mips.c
new file mode 100644
index 0000000..563044e
--- /dev/null
+++ b/board/qemu-mips/qemu-mips.c
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2007
+ * Vlad Lungu vlad.lungu@windriver.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mipsregs.h>
+#include <asm/io.h>
+#include <netdev.h>
+
+phys_size_t initdram(int board_type)
+{
+ /* Sdram is setup by assembler code */
+ /* If memory could be changed, we should return the true value here */
+ return MEM_SIZE*1024*1024;
+}
+
+int checkboard(void)
+{
+ u32 proc_id;
+ u32 config1;
+
+ proc_id = read_c0_prid();
+ printf("Board: Qemu -M mips CPU: ");
+ switch (proc_id) {
+ case 0x00018000:
+ printf("4Kc");
+ break;
+ case 0x00018400:
+ printf("4KEcR1");
+ break;
+ case 0x00019000:
+ printf("4KEc");
+ break;
+ case 0x00019300:
+ config1 = read_c0_config1();
+ if (config1 & 1)
+ printf("24Kf");
+ else
+ printf("24Kc");
+ break;
+ case 0x00019500:
+ printf("34Kf");
+ break;
+ case 0x00000400:
+ printf("R4000");
+ break;
+ case 0x00018100:
+ config1 = read_c0_config1();
+ if (config1 & 1)
+ printf("5Kf");
+ else
+ printf("5Kc");
+ break;
+ case 0x000182a0:
+ printf("20Kc");
+ break;
+
+ default:
+ printf("unknown");
+ }
+ printf(" proc_id=0x%x\n", proc_id);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ set_io_port_base(0);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return ne2k_register();
+}
diff --git a/board/raidsonic/ib62x0/Kconfig b/board/raidsonic/ib62x0/Kconfig
new file mode 100644
index 0000000..129aac8
--- /dev/null
+++ b/board/raidsonic/ib62x0/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IB62X0
+
+config SYS_BOARD
+ default "ib62x0"
+
+config SYS_VENDOR
+ default "raidsonic"
+
+config SYS_CONFIG_NAME
+ default "ib62x0"
+
+endif
diff --git a/board/raidsonic/ib62x0/MAINTAINERS b/board/raidsonic/ib62x0/MAINTAINERS
new file mode 100644
index 0000000..423aa0c
--- /dev/null
+++ b/board/raidsonic/ib62x0/MAINTAINERS
@@ -0,0 +1,6 @@
+IB62X0 BOARD
+M: Luka Perkov <luka@openwrt.org>
+S: Maintained
+F: board/raidsonic/ib62x0/
+F: include/configs/ib62x0.h
+F: configs/ib62x0_defconfig
diff --git a/board/raidsonic/ib62x0/Makefile b/board/raidsonic/ib62x0/Makefile
new file mode 100644
index 0000000..c3b4e69
--- /dev/null
+++ b/board/raidsonic/ib62x0/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ib62x0.o
diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c
new file mode 100644
index 0000000..f01fb1c
--- /dev/null
+++ b/board/raidsonic/ib62x0/ib62x0.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011-2012
+ * Gerald Kerma <dreagle@doukki.net>
+ * Luka Perkov <luka@openwrt.org>
+ * Simon Baatz <gmbnomis@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "ib62x0.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(IB62x0_OE_VAL_LOW,
+ IB62x0_OE_VAL_HIGH,
+ IB62x0_OE_LOW, IB62x0_OE_HIGH);
+
+ /* Set SATA activity LEDs to default off */
+ writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_SATA1_ACTn,
+ MPP21_SATA0_ACTn,
+ MPP22_GPIO, /* Power LED red */
+ MPP24_GPIO, /* Power off device */
+ MPP25_GPIO, /* Power LED green */
+ MPP27_GPIO, /* USB transfer LED */
+ MPP28_GPIO, /* Reset button */
+ MPP29_GPIO, /* USB Copy button */
+ 0
+ };
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
diff --git a/board/raidsonic/ib62x0/ib62x0.h b/board/raidsonic/ib62x0/ib62x0.h
new file mode 100644
index 0000000..11278a8
--- /dev/null
+++ b/board/raidsonic/ib62x0/ib62x0.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2011-2012
+ * Gerald Kerma <dreagle@doukki.net>
+ * Simon Baatz <gmbnomis@gmail.com>
+ * Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IB62x0_H
+#define __IB62x0_H
+
+#define IB62x0_OE_LOW (~(1 << 22 | 1 << 24 | 1 << 25 | 1 << 27))
+#define IB62x0_OE_HIGH (~(0))
+#define IB62x0_OE_VAL_LOW 0
+#define IB62x0_OE_VAL_HIGH 0
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+/* SATAHC related */
+#define MVSATAHC_LED_CONF_REG (MV_SATA_BASE + 0x2C)
+#define MVSATAHC_LED_POLARITY_CTRL (1 << 3)
+
+#endif /* __IB62x0_H */
diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg
new file mode 100644
index 0000000..596071f
--- /dev/null
+++ b/board/raidsonic/ib62x0/kwbimage.cfg
@@ -0,0 +1,155 @@
+#
+# Copyright (C) 2011-2012
+# Gerald Kerma <dreagle@doukki.net>
+# Simon Baatz <gmbnomis@gmail.com>
+# Luka Perkov <luka@openwrt.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand # change from nand to uart if building UART image
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xffd100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xffd01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
+# bit23-14: 0x0,
+# bit24: 0x1, enable exit self refresh mode on DDR access
+# bit25: 0x1, required
+# bit29-26: 0x0,
+# bit31-30: 0x1,
+
+DATA 0xffd01404 0x37543000 # DDR Controller Control Low
+# bit4: 0x0, addr/cmd in smame cycle
+# bit5: 0x0, clk is driven during self refresh, we don't care for APX
+# bit6: 0x0, use recommended falling edge of clk for addr/cmd
+# bit14: 0x0, input buffer always powered up
+# bit18: 0x1, cpu lock transaction enabled
+# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 0x3, required
+# bit31: 0x0, no additional STARTBURST delay
+
+DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11-8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: 0x0, required
+
+DATA 0xffd01410 0x0000000c # DDR Address Control
+# bit1-0: 00, Cs0width (x8)
+# bit3-2: 11, Cs0size (1Gb)
+# bit5-4: 00, Cs1width (x8)
+# bit7-6: 11, Cs1size (1Gb)
+# bit9-8: 00, Cs2width (nonexistent
+# bit11-10: 00, Cs2size (nonexistent
+# bit13-12: 00, Cs3width (nonexistent
+# bit15-14: 00, Cs3size (nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0x0, required
+
+DATA 0xffd01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0x0, required
+
+DATA 0xffd01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0x0, required
+
+DATA 0xffd0141c 0x00000c52 # DDR Mode
+# bit2-0: 0x2, BurstLen=2 required
+# bit3: 0x0, BurstType=0 required
+# bit6-4: 0x4, CL=5
+# bit7: 0x0, TestMode=0 normal
+# bit8: 0x0, DLL reset=0 normal
+# bit11-9: 0x6, auto-precharge write recovery ????????????
+# bit12: 0x0, PD must be zero
+# bit31-13: 0x0, required
+
+DATA 0xffd01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 1, DDR ODT control lsd (disabled)
+# bit5-3: 0x0, required
+# bit6: 0, DDR ODT control msb, (disabled)
+# bit9-7: 0x0, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0x0, required
+
+DATA 0xffd01424 0x0000f17f # DDR Controller Control High
+# bit2-0: 0x7, required
+# bit3: 0x1, MBUS Burst Chop disabled
+# bit6-4: 0x7, required
+# bit7: 0x0,
+# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9: 0x0, no half clock cycle addition to dataout
+# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf, required
+# bit31-16: 0, required
+
+DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
+# bit0: 0x1, Window enabled
+# bit1: 0x0, Write Protect disabled
+# bit3-2: 0x0, CS0 hit selected
+# bit23-4: 0xfffff, required
+# bit31-24: 0x0f, Size (i.e. 256MB)
+
+DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled
+
+DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
+# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 0x1, ODT1 active NEVER!
+# bit31-4: 0x0, required
+
+DATA 0xffd0149c 0x0000e803 # CPU ODT Control
+DATA 0xffd01480 0x00000001 # DDR Initialization Control
+# bit0: 0x1, enable DDR init upon this register write
+
+DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
+DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/raspberrypi/rpi/Kconfig b/board/raspberrypi/rpi/Kconfig
new file mode 100644
index 0000000..6a538cf
--- /dev/null
+++ b/board/raspberrypi/rpi/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_RPI
+
+config SYS_BOARD
+ default "rpi"
+
+config SYS_VENDOR
+ default "raspberrypi"
+
+config SYS_SOC
+ default "bcm2835"
+
+config SYS_CONFIG_NAME
+ default "rpi"
+
+endif
diff --git a/board/raspberrypi/rpi/MAINTAINERS b/board/raspberrypi/rpi/MAINTAINERS
new file mode 100644
index 0000000..6dcb7bd
--- /dev/null
+++ b/board/raspberrypi/rpi/MAINTAINERS
@@ -0,0 +1,6 @@
+RPI BOARD
+M: Stephen Warren <swarren@wwwdotorg.org>
+S: Maintained
+F: board/raspberrypi/rpi/
+F: include/configs/rpi.h
+F: configs/rpi_defconfig
diff --git a/board/raspberrypi/rpi/Makefile b/board/raspberrypi/rpi/Makefile
new file mode 100644
index 0000000..c53c92b
--- /dev/null
+++ b/board/raspberrypi/rpi/Makefile
@@ -0,0 +1,15 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# version 2 as published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+obj-y := rpi.o
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
new file mode 100644
index 0000000..c18271f
--- /dev/null
+++ b/board/raspberrypi/rpi/rpi.c
@@ -0,0 +1,324 @@
+/*
+ * (C) Copyright 2012-2013 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <asm/gpio.h>
+#include <asm/arch/mbox.h>
+#include <asm/arch/sdhci.h>
+#include <asm/global_data.h>
+#include <dm/platform_data/serial_pl01x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct bcm2835_gpio_platdata gpio_platdata = {
+ .base = BCM2835_GPIO_BASE,
+};
+
+U_BOOT_DEVICE(bcm2835_gpios) = {
+ .name = "gpio_bcm2835",
+ .platdata = &gpio_platdata,
+};
+
+static const struct pl01x_serial_platdata serial_platdata = {
+ .base = 0x20201000,
+ .type = TYPE_PL011,
+ .clock = 3000000,
+};
+
+U_BOOT_DEVICE(bcm2835_serials) = {
+ .name = "serial_pl01x",
+ .platdata = &serial_platdata,
+};
+
+struct msg_get_arm_mem {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
+ u32 end_tag;
+};
+
+struct msg_get_board_rev {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_board_rev get_board_rev;
+ u32 end_tag;
+};
+
+struct msg_get_mac_address {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_mac_address get_mac_address;
+ u32 end_tag;
+};
+
+struct msg_set_power_state {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_set_power_state set_power_state;
+ u32 end_tag;
+};
+
+struct msg_get_clock_rate {
+ struct bcm2835_mbox_hdr hdr;
+ struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
+ u32 end_tag;
+};
+
+/* See comments in mbox.h for data source */
+static const struct {
+ const char *name;
+ const char *fdtfile;
+ bool has_onboard_eth;
+} models[] = {
+ [0] = {
+ "Unknown model",
+ "bcm2835-rpi-other.dtb",
+ false,
+ },
+ [BCM2835_BOARD_REV_B_I2C0_2] = {
+ "Model B (no P5)",
+ "bcm2835-rpi-b-i2c0.dtb",
+ true,
+ },
+ [BCM2835_BOARD_REV_B_I2C0_3] = {
+ "Model B (no P5)",
+ "bcm2835-rpi-b-i2c0.dtb",
+ true,
+ },
+ [BCM2835_BOARD_REV_B_I2C1_4] = {
+ "Model B",
+ "bcm2835-rpi-b.dtb",
+ true,
+ },
+ [BCM2835_BOARD_REV_B_I2C1_5] = {
+ "Model B",
+ "bcm2835-rpi-b.dtb",
+ true,
+ },
+ [BCM2835_BOARD_REV_B_I2C1_6] = {
+ "Model B",
+ "bcm2835-rpi-b.dtb",
+ true,
+ },
+ [BCM2835_BOARD_REV_A_7] = {
+ "Model A",
+ "bcm2835-rpi-a.dtb",
+ false,
+ },
+ [BCM2835_BOARD_REV_A_8] = {
+ "Model A",
+ "bcm2835-rpi-a.dtb",
+ false,
+ },
+ [BCM2835_BOARD_REV_A_9] = {
+ "Model A",
+ "bcm2835-rpi-a.dtb",
+ false,
+ },
+ [BCM2835_BOARD_REV_B_REV2_d] = {
+ "Model B rev2",
+ "bcm2835-rpi-b-rev2.dtb",
+ true,
+ },
+ [BCM2835_BOARD_REV_B_REV2_e] = {
+ "Model B rev2",
+ "bcm2835-rpi-b-rev2.dtb",
+ true,
+ },
+ [BCM2835_BOARD_REV_B_REV2_f] = {
+ "Model B rev2",
+ "bcm2835-rpi-b-rev2.dtb",
+ true,
+ },
+ [BCM2835_BOARD_REV_B_PLUS] = {
+ "Model B+",
+ "bcm2835-rpi-b-plus.dtb",
+ true,
+ },
+ [BCM2835_BOARD_REV_CM] = {
+ "Compute Module",
+ "bcm2835-rpi-cm.dtb",
+ false,
+ },
+ [BCM2835_BOARD_REV_A_PLUS] = {
+ "Model A+",
+ "bcm2835-rpi-a-plus.dtb",
+ false,
+ },
+};
+
+u32 rpi_board_rev = 0;
+
+int dram_init(void)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 16);
+ int ret;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret) {
+ printf("bcm2835: Could not query ARM memory size\n");
+ return -1;
+ }
+
+ gd->ram_size = msg->get_arm_mem.body.resp.mem_size;
+
+ return 0;
+}
+
+static void set_fdtfile(void)
+{
+ const char *fdtfile;
+
+ if (getenv("fdtfile"))
+ return;
+
+ fdtfile = models[rpi_board_rev].fdtfile;
+ setenv("fdtfile", fdtfile);
+}
+
+static void set_usbethaddr(void)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16);
+ int ret;
+
+ if (!models[rpi_board_rev].has_onboard_eth)
+ return;
+
+ if (getenv("usbethaddr"))
+ return;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_mac_address, GET_MAC_ADDRESS);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret) {
+ printf("bcm2835: Could not query MAC address\n");
+ /* Ignore error; not critical */
+ return;
+ }
+
+ eth_setenv_enetaddr("usbethaddr", msg->get_mac_address.body.resp.mac);
+
+ return;
+}
+
+int misc_init_r(void)
+{
+ set_fdtfile();
+ set_usbethaddr();
+ return 0;
+}
+
+static int power_on_module(u32 module)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1, 16);
+ int ret;
+
+ BCM2835_MBOX_INIT_HDR(msg_pwr);
+ BCM2835_MBOX_INIT_TAG(&msg_pwr->set_power_state,
+ SET_POWER_STATE);
+ msg_pwr->set_power_state.body.req.device_id = module;
+ msg_pwr->set_power_state.body.req.state =
+ BCM2835_MBOX_SET_POWER_STATE_REQ_ON |
+ BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT;
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN,
+ &msg_pwr->hdr);
+ if (ret) {
+ printf("bcm2835: Could not set module %u power state\n",
+ module);
+ return -1;
+ }
+
+ return 0;
+}
+
+static void get_board_rev(void)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1, 16);
+ int ret;
+ const char *name;
+
+ BCM2835_MBOX_INIT_HDR(msg);
+ BCM2835_MBOX_INIT_TAG(&msg->get_board_rev, GET_BOARD_REV);
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr);
+ if (ret) {
+ printf("bcm2835: Could not query board revision\n");
+ /* Ignore error; not critical */
+ return;
+ }
+
+ rpi_board_rev = msg->get_board_rev.body.resp.rev;
+ if (rpi_board_rev >= ARRAY_SIZE(models)) {
+ printf("RPI: Board rev %u outside known range\n",
+ rpi_board_rev);
+ rpi_board_rev = 0;
+ }
+ if (!models[rpi_board_rev].name) {
+ printf("RPI: Board rev %u unknown\n", rpi_board_rev);
+ rpi_board_rev = 0;
+ }
+
+ name = models[rpi_board_rev].name;
+ printf("RPI model: %s\n", name);
+}
+
+int board_init(void)
+{
+ get_board_rev();
+
+ gd->bd->bi_boot_params = 0x100;
+
+ return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16);
+ int ret;
+
+ power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI);
+
+ BCM2835_MBOX_INIT_HDR(msg_clk);
+ BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_CLOCK_RATE);
+ msg_clk->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC;
+
+ ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_clk->hdr);
+ if (ret) {
+ printf("bcm2835: Could not query eMMC clock rate\n");
+ return -1;
+ }
+
+ return bcm2835_sdhci_init(BCM2835_SDHCI_BASE,
+ msg_clk->get_clock_rate.body.resp.rate_hz);
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /*
+ * For now, we simply always add the simplefb DT node. Later, we
+ * should be more intelligent, and e.g. only do this if no enabled DT
+ * node exists for the "real" graphics driver.
+ */
+ lcd_dt_simplefb_add_node(blob);
+
+ return 0;
+}
diff --git a/board/renesas/MigoR/Kconfig b/board/renesas/MigoR/Kconfig
new file mode 100644
index 0000000..25b170a
--- /dev/null
+++ b/board/renesas/MigoR/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MIGOR
+
+config SYS_BOARD
+ default "MigoR"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "MigoR"
+
+endif
diff --git a/board/renesas/MigoR/MAINTAINERS b/board/renesas/MigoR/MAINTAINERS
new file mode 100644
index 0000000..21ee5e2
--- /dev/null
+++ b/board/renesas/MigoR/MAINTAINERS
@@ -0,0 +1,6 @@
+MIGOR BOARD
+#M: -
+S: Maintained
+F: board/renesas/MigoR/
+F: include/configs/MigoR.h
+F: configs/MigoR_defconfig
diff --git a/board/renesas/MigoR/Makefile b/board/renesas/MigoR/Makefile
new file mode 100644
index 0000000..b4691a1
--- /dev/null
+++ b/board/renesas/MigoR/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2007
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# Copyright (C) 2007
+# Kenati Technologies, Inc.
+#
+# board/MigoR/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := migo_r.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S
new file mode 100644
index 0000000..63ea70a
--- /dev/null
+++ b/board/renesas/MigoR/lowlevel_init.S
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2007-2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/MigoR/lowlevel_init.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+ write32 CCR_A, CCR_D ! Address of Cache Control Register
+ ! Instruction Cache Invalidate
+
+ write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register
+ ! TI == TLB Invalidate bit
+
+ write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0
+
+ write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2
+
+ write16 PFC_PULCR_A, PFC_PULCR_D
+
+ write16 PFC_DRVCR_A, PFC_DRVCR_D
+
+ write16 SBSCR_A, SBSCR_D
+
+ write16 PSCR_A, PSCR_D
+
+ write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register)
+ ! 0xA507 -> timer_STOP / WDT_CLK = max
+
+ write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register)
+ ! 0x5A00 -> Clear
+
+ write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register)
+ ! 0xA504 -> timer_STOP / CLK = 500ms
+
+ write32 DLLFRQ_A, DLLFRQ_D ! 20080115
+ ! 20080115
+
+ write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register
+ ! 20080115
+
+ write32 CCR_A, CCR_D_2 ! Address of Cache Control Register
+ ! ??
+
+bsc_init:
+ write32 CMNCR_A, CMNCR_D
+
+ write32 CS0BCR_A, CS0BCR_D
+
+ write32 CS4BCR_A, CS4BCR_D
+
+ write32 CS5ABCR_A, CS5ABCR_D
+
+ write32 CS5BBCR_A, CS5BBCR_D
+
+ write32 CS6ABCR_A, CS6ABCR_D
+
+ write32 CS0WCR_A, CS0WCR_D
+
+ write32 CS4WCR_A, CS4WCR_D
+
+ write32 CS5AWCR_A, CS5AWCR_D
+
+ write32 CS5BWCR_A, CS5BWCR_D
+
+ write32 CS6AWCR_A, CS6AWCR_D
+
+ ! SDRAM initialization
+ write32 SDCR_A, SDCR_D
+
+ write32 SDWCR_A, SDWCR_D
+
+ write32 SDPCR_A, SDPCR_D
+
+ write32 RTCOR_A, RTCOR_D
+
+ write32 RTCNT_A, RTCNT_D
+
+ write32 RTCSR_A, RTCSR_D
+
+ write32 RFCR_A, RFCR_D
+
+ write8 SDMR3_A, SDMR3_D
+
+ ! BL bit off (init = ON) (?!?)
+
+ stc sr, r0 ! BL bit off(init=ON)
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+ mov #0, r0
+
+ .align 4
+
+CCR_A: .long CCR
+MMUCR_A: .long MMUCR
+MSTPCR0_A: .long MSTPCR0
+MSTPCR2_A: .long MSTPCR2
+PFC_PULCR_A: .long PULCR
+PFC_DRVCR_A: .long DRVCR
+SBSCR_A: .long SBSCR
+PSCR_A: .long PSCR
+RWTCSR_A: .long RWTCSR
+RWTCNT_A: .long RWTCNT
+FRQCR_A: .long FRQCR
+PLLCR_A: .long PLLCR
+DLLFRQ_A: .long DLLFRQ
+
+CCR_D: .long 0x00000800
+CCR_D_2: .long 0x00000103
+MMUCR_D: .long 0x00000004
+MSTPCR0_D: .long 0x00001001
+MSTPCR2_D: .long 0xffffffff
+PFC_PULCR_D: .long 0x6000
+PFC_DRVCR_D: .long 0x0464
+FRQCR_D: .long 0x07033639
+PLLCR_D: .long 0x00005000
+DLLFRQ_D: .long 0x000004F6
+
+CMNCR_A: .long CMNCR
+CMNCR_D: .long 0x0000001B
+CS0BCR_A: .long CS0BCR
+CS0BCR_D: .long 0x24920400
+CS4BCR_A: .long CS4BCR
+CS4BCR_D: .long 0x00003400
+CS5ABCR_A: .long CS5ABCR
+CS5ABCR_D: .long 0x24920400
+CS5BBCR_A: .long CS5BBCR
+CS5BBCR_D: .long 0x24920400
+CS6ABCR_A: .long CS6ABCR
+CS6ABCR_D: .long 0x24920400
+
+CS0WCR_A: .long CS0WCR
+CS0WCR_D: .long 0x00000380
+CS4WCR_A: .long CS4WCR
+CS4WCR_D: .long 0x00110080
+CS5AWCR_A: .long CS5AWCR
+CS5AWCR_D: .long 0x00000300
+CS5BWCR_A: .long CS5BWCR
+CS5BWCR_D: .long 0x00000300
+CS6AWCR_A: .long CS6AWCR
+CS6AWCR_D: .long 0x00000300
+
+SDCR_A: .long SBSC_SDCR
+SDCR_D: .long 0x80160809
+SDWCR_A: .long SBSC_SDWCR
+SDWCR_D: .long 0x0014450C
+SDPCR_A: .long SBSC_SDPCR
+SDPCR_D: .long 0x00000087
+RTCOR_A: .long SBSC_RTCOR
+RTCNT_A: .long SBSC_RTCNT
+RTCNT_D: .long 0xA55A0012
+RTCOR_D: .long 0xA55A001C
+RTCSR_A: .long SBSC_RTCSR
+RFCR_A: .long SBSC_RFCR
+RFCR_D: .long 0xA55A0221
+RTCSR_D: .long 0xA55A009a
+SDMR3_A: .long 0xFE581180
+SDMR3_D: .long 0x0
+
+SR_MASK_D: .long 0xEFFFFF0F
+
+ .align 2
+
+SBSCR_D: .word 0x0044
+PSCR_D: .word 0x0000
+RWTCSR_D_1: .word 0xA507
+RWTCSR_D_2: .word 0xA504
+RWTCNT_D: .word 0x5A00
diff --git a/board/renesas/MigoR/migo_r.c b/board/renesas/MigoR/migo_r.c
new file mode 100644
index 0000000..fa2bf78
--- /dev/null
+++ b/board/renesas/MigoR/migo_r.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2007
+ * Kenati Technologies, Inc.
+ *
+ * board/MigoR/migo_r.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas MigoR\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state (unsigned short value)
+{
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/renesas/alt/Kconfig b/board/renesas/alt/Kconfig
new file mode 100644
index 0000000..957962d
--- /dev/null
+++ b/board/renesas/alt/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ALT
+
+config SYS_BOARD
+ default "alt"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "alt"
+
+endif
diff --git a/board/renesas/alt/MAINTAINERS b/board/renesas/alt/MAINTAINERS
new file mode 100644
index 0000000..6ec140b
--- /dev/null
+++ b/board/renesas/alt/MAINTAINERS
@@ -0,0 +1,6 @@
+ALT BOARD
+M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+S: Maintained
+F: board/renesas/alt/
+F: include/configs/alt.h
+F: configs/alt_defconfig
diff --git a/board/renesas/alt/Makefile b/board/renesas/alt/Makefile
new file mode 100644
index 0000000..6904e39
--- /dev/null
+++ b/board/renesas/alt/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/alt/Makefile
+#
+# Copyright (C) 2014 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := alt.o qos.o ../rcar-gen2-common/common.o
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
new file mode 100644
index 0000000..8cc17e9
--- /dev/null
+++ b/board/renesas/alt/alt.c
@@ -0,0 +1,161 @@
+/*
+ * board/renesas/alt/alt.c
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <div64.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ /* QoS */
+ qos_init();
+}
+
+#define TMU0_MSTP125 (1 << 25)
+#define SCIF2_MSTP719 (1 << 19)
+#define ETHER_MSTP813 (1 << 13)
+#define IIC1_MSTP323 (1 << 23)
+#define MMC0_MSTP315 (1 << 15)
+
+int board_early_init_f(void)
+{
+ /* TMU */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+ /* SCIF2 */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
+
+ /* ETHER */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
+ /* IIC1 / sh-i2c ch1 */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
+
+#ifdef CONFIG_SH_MMCIF
+ /* MMC */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ /* Init PFC controller */
+ r8a7794_pinmux_init();
+
+ /* Ether Enable */
+ gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+ gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+ gpio_request(GPIO_FN_ETH_RXD0, NULL);
+ gpio_request(GPIO_FN_ETH_RXD1, NULL);
+ gpio_request(GPIO_FN_ETH_LINK, NULL);
+ gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+ gpio_request(GPIO_FN_ETH_MDIO, NULL);
+ gpio_request(GPIO_FN_ETH_TXD1, NULL);
+ gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+ gpio_request(GPIO_FN_ETH_MAGIC, NULL);
+ gpio_request(GPIO_FN_ETH_TXD0, NULL);
+ gpio_request(GPIO_FN_ETH_MDC, NULL);
+ gpio_request(GPIO_FN_IRQ8, NULL);
+
+ /* PHY reset */
+ gpio_request(GPIO_GP_1_24, NULL);
+ gpio_direction_output(GPIO_GP_1_24, 0);
+ mdelay(20);
+ gpio_set_value(GPIO_GP_1_24, 1);
+ udelay(1);
+
+ return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SH_ETHER
+ int ret = -ENODEV;
+ u32 val;
+ unsigned char enetaddr[6];
+
+ ret = sh_eth_initialize(bis);
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ return ret;
+
+ /* Set Mac address */
+ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+ enetaddr[2] << 8 | enetaddr[3];
+ writel(val, CXR24);
+
+ val = enetaddr[4] << 8 | enetaddr[5];
+ writel(val, CXR25);
+
+ return ret;
+#else
+ return 0;
+#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret = 0;
+
+#ifdef CONFIG_SH_MMCIF
+ gpio_request(GPIO_GP_4_31, NULL);
+ gpio_set_value(GPIO_GP_4_31, 1);
+
+ ret = mmcif_mmc_init();
+#endif
+ return ret;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
+{
+ u8 val;
+
+ i2c_set_bus_num(1); /* PowerIC connected to ch1 */
+ i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ val |= 0x02;
+ i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}
diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c
new file mode 100644
index 0000000..f0b349f
--- /dev/null
+++ b/board/renesas/alt/qos.c
@@ -0,0 +1,950 @@
+/*
+ * board/renesas/alt/qos.c
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+/* QoS version 0.11 */
+
+enum {
+ DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+ DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+ DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+ DBSC3_15,
+ DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+ int i;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
+
+ /* DBSC DBADJ2 */
+ writel(0x20042004, DBSC3_0_DBADJ2);
+
+ /* S3C -QoS */
+ s3c = (struct rcar_s3c *)S3C_BASE;
+ writel(0x1F0D0B0A, &s3c->s3crorr);
+ writel(0x1F0D0B09, &s3c->s3cworr);
+
+ /* QoS Control Registers */
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+ writel(0x80928092, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20DC, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20DC, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+ writel(0x00820082, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20FA, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20FA, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ /* DBSC -QoS */
+ /* DBSC0 - Read */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x0000207D, &qos_addr->dbtmval0);
+ writel(0x00002053, &qos_addr->dbtmval1);
+ writel(0x0000202A, &qos_addr->dbtmval2);
+ writel(0x00001FBD, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002064, &qos_addr->dbthres0);
+ writel(0x0000203E, &qos_addr->dbthres1);
+ writel(0x00002019, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* DBSC0 - Write */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x0000207D, &qos_addr->dbtmval0);
+ writel(0x00002053, &qos_addr->dbtmval1);
+ writel(0x00002043, &qos_addr->dbtmval2);
+ writel(0x00002030, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002064, &qos_addr->dbthres0);
+ writel(0x0000203E, &qos_addr->dbthres1);
+ writel(0x00002031, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* CCI-400 -QoS */
+ writel(0x20000800, CCI_400_MAXOT_1);
+ writel(0x20000800, CCI_400_MAXOT_2);
+ writel(0x0000000C, CCI_400_QOSCNTL_1);
+ writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+ /* MXI -QoS */
+ /* Transaction Control (MXI) */
+ mxi = (struct rcar_mxi *)MXI_BASE;
+ writel(0x00000013, &mxi->mxrtcr);
+ writel(0x00000013, &mxi->mxwtcr);
+ writel(0x00780080, &mxi->mxsaar0);
+ writel(0x02000800, &mxi->mxsaar1);
+
+ /* QoS Control (MXI) */
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+ writel(0x0000000C, &mxi_qos->vspdu0);
+ writel(0x0000000E, &mxi_qos->du0);
+
+ /* AXI -QoS */
+ /* Transaction Control (MXI) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (RT-AXI) */
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (MP-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002037, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000206E, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (SYS-AXI256) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (CCI-AXI) */
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (Media-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020DC, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020DC, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/alt/qos.h b/board/renesas/alt/qos.h
new file mode 100644
index 0000000..9a6c046
--- /dev/null
+++ b/board/renesas/alt/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/board/renesas/ap325rxa/Kconfig b/board/renesas/ap325rxa/Kconfig
new file mode 100644
index 0000000..c8f2de2
--- /dev/null
+++ b/board/renesas/ap325rxa/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AP325RXA
+
+config SYS_BOARD
+ default "ap325rxa"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "ap325rxa"
+
+endif
diff --git a/board/renesas/ap325rxa/MAINTAINERS b/board/renesas/ap325rxa/MAINTAINERS
new file mode 100644
index 0000000..bdc49c5
--- /dev/null
+++ b/board/renesas/ap325rxa/MAINTAINERS
@@ -0,0 +1,7 @@
+AP325RXA BOARD
+M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S: Maintained
+F: board/renesas/ap325rxa/
+F: include/configs/ap325rxa.h
+F: configs/ap325rxa_defconfig
diff --git a/board/renesas/ap325rxa/Makefile b/board/renesas/ap325rxa/Makefile
new file mode 100644
index 0000000..ff72de9
--- /dev/null
+++ b/board/renesas/ap325rxa/Makefile
@@ -0,0 +1,12 @@
+#########################################################################
+#
+# Copyright (C) 2008 Renesas Solutions Corp.
+# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+#
+# board/ap325rxa/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ap325rxa.o cpld-ap325rxa.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/ap325rxa/ap325rxa.c b/board/renesas/ap325rxa/ap325rxa.c
new file mode 100644
index 0000000..518ad7b
--- /dev/null
+++ b/board/renesas/ap325rxa/ap325rxa.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PRI control register */
+#define PRPRICR5 0xFF800048 /* LMB */
+#define PRPRICR5_D 0x2a
+
+/* FPGA control */
+#define FPGA_NAND_CTL 0xB410020C
+#define FPGA_NAND_RST 0x0008
+#define FPGA_NAND_INIT 0x0000
+#define FPGA_NAND_RST_WAIT 10000
+
+/* I/O port data */
+#define PACR_D 0x0000
+#define PBCR_D 0x0000
+#define PCCR_D 0x1000
+#define PDCR_D 0x0000
+#define PECR_D 0x0410
+#define PFCR_D 0xffff
+#define PGCR_D 0x0000
+#define PHCR_D 0x5011
+#define PJCR_D 0x4400
+#define PKCR_D 0x7c00
+#define PLCR_D 0x0000
+#define PMCR_D 0x0000
+#define PNCR_D 0x0000
+#define PQCR_D 0x0000
+#define PRCR_D 0x0000
+#define PSCR_D 0x0000
+#define PTCR_D 0x0010
+#define PUCR_D 0x0fff
+#define PVCR_D 0xffff
+#define PWCR_D 0x0000
+#define PXCR_D 0x7500
+#define PYCR_D 0x0000
+#define PZCR_D 0x5540
+
+/* Pin Function Controler data */
+#define PSELA_D 0x1410
+#define PSELB_D 0x0140
+#define PSELC_D 0x0000
+#define PSELD_D 0x0400
+
+/* I/O Buffer Hi-Z data */
+#define HIZCRA_D 0x0000
+#define HIZCRB_D 0x1000
+#define HIZCRC_D 0x0000
+#define HIZCRD_D 0x0000
+
+/* Module select reg data */
+#define MSELCRA_D 0x0014
+#define MSELCRB_D 0x0018
+
+/* Module Stop reg Data */
+#define MSTPCR2_D 0xFFD9F280
+
+/* CPLD loader */
+extern void init_cpld(void);
+
+int checkboard(void)
+{
+ puts("BOARD: AP325RXA\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Pin Function Controler Init */
+ outw(PSELA_D, PSELA);
+ outw(PSELB_D, PSELB);
+ outw(PSELC_D, PSELC);
+ outw(PSELD_D, PSELD);
+
+ /* I/O Buffer Hi-Z Init */
+ outw(HIZCRA_D, HIZCRA);
+ outw(HIZCRB_D, HIZCRB);
+ outw(HIZCRC_D, HIZCRC);
+ outw(HIZCRD_D, HIZCRD);
+
+ /* Module select reg Init */
+ outw(MSELCRA_D, MSELCRA);
+ outw(MSELCRB_D, MSELCRB);
+
+ /* Module Stop reg Init */
+ outl(MSTPCR2_D, MSTPCR2);
+
+ /* I/O ports */
+ outw(PACR_D, PACR);
+ outw(PBCR_D, PBCR);
+ outw(PCCR_D, PCCR);
+ outw(PDCR_D, PDCR);
+ outw(PECR_D, PECR);
+ outw(PFCR_D, PFCR);
+ outw(PGCR_D, PGCR);
+ outw(PHCR_D, PHCR);
+ outw(PJCR_D, PJCR);
+ outw(PKCR_D, PKCR);
+ outw(PLCR_D, PLCR);
+ outw(PMCR_D, PMCR);
+ outw(PNCR_D, PNCR);
+ outw(PQCR_D, PQCR);
+ outw(PRCR_D, PRCR);
+ outw(PSCR_D, PSCR);
+ outw(PTCR_D, PTCR);
+ outw(PUCR_D, PUCR);
+ outw(PVCR_D, PVCR);
+ outw(PWCR_D, PWCR);
+ outw(PXCR_D, PXCR);
+ outw(PYCR_D, PYCR);
+ outw(PZCR_D, PZCR);
+
+ /* PRI control register Init */
+ outl(PRPRICR5_D, PRPRICR5);
+
+ /* cpld init */
+ init_cpld();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
+
+void ide_set_reset(int idereset)
+{
+ outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */
+ udelay(FPGA_NAND_RST_WAIT);
+ outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/renesas/ap325rxa/cpld-ap325rxa.c b/board/renesas/ap325rxa/cpld-ap325rxa.c
new file mode 100644
index 0000000..16fadcb
--- /dev/null
+++ b/board/renesas/ap325rxa/cpld-ap325rxa.c
@@ -0,0 +1,206 @@
+/***************************************************************
+ * Project:
+ * CPLD SlaveSerial Configuration via embedded microprocessor.
+ *
+ * Copyright info:
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it as you like.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Description:
+ *
+ * This is the main source file that will allow a microprocessor
+ * to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II,
+ * and Spartan-II devices via the SlaveSerial Configuration Mode.
+ * This code is discussed in Xilinx Application Note, XAPP502.
+ *
+ * History:
+ * 3-October-2001 MN/MP - Created
+ * 20-August-2008 Renesas Solutions - Modified to SH7723
+ ****************************************************************/
+
+#include <common.h>
+
+/* Serial */
+#define SCIF_BASE 0xffe00000 /* SCIF0 */
+#define SCSMR (vu_short *)(SCIF_BASE + 0x00)
+#define SCBRR (vu_char *)(SCIF_BASE + 0x04)
+#define SCSCR (vu_short *)(SCIF_BASE + 0x08)
+#define SC_TDR (vu_char *)(SCIF_BASE + 0x0C)
+#define SC_SR (vu_short *)(SCIF_BASE + 0x10)
+#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
+#define RFCR (vu_long *)0xFE400020
+
+#define SCSCR_INIT 0x0038
+#define SCSCR_CLR 0x0000
+#define SCFCR_INIT 0x0006
+#define SCSMR_INIT 0x0080
+#define RFCR_CLR 0xA400
+#define SCI_TD_E 0x0020
+#define SCI_TDRE_CLEAR 0x00df
+
+#define BPS_SETTING_VALUE 1 /* 12.5MHz */
+#define WAIT_RFCR_COUNTER 500
+
+/* CPLD data size */
+#define CPLD_DATA_SIZE 169216
+
+/* out */
+#define CPLD_PFC_ADR ((vu_short *)0xA4050112)
+
+#define CPLD_PROG_ADR ((vu_char *)0xA4050132)
+#define CPLD_PROG_DAT 0x80
+
+/* in */
+#define CPLD_INIT_ADR ((vu_char *)0xA4050132)
+#define CPLD_INIT_DAT 0x40
+#define CPLD_DONE_ADR ((vu_char *)0xA4050132)
+#define CPLD_DONE_DAT 0x20
+
+#define HIZCRB ((vu_short *)0xA405015A)
+
+/* data */
+#define CPLD_NOMAL_START 0xA0A80000
+#define CPLD_SAFE_START 0xA0AC0000
+#define MODE_SW (vu_char *)0xA405012A
+
+static void init_cpld_loader(void)
+{
+
+ *SCSCR = SCSCR_CLR;
+ *SCFCR = SCFCR_INIT;
+ *SCSMR = SCSMR_INIT;
+
+ *SCBRR = BPS_SETTING_VALUE;
+
+ *RFCR = RFCR_CLR; /* Refresh counter clear */
+
+ while (*RFCR < WAIT_RFCR_COUNTER)
+ ;
+
+ *SCFCR = 0x0; /* RTRG=00, TTRG=00 */
+ /* MCE=0,TFRST=0,RFRST=0,LOOP=0 */
+ *SCSCR = SCSCR_INIT;
+}
+
+static int check_write_ready(void)
+{
+ u16 status = *SC_SR;
+ return status & SCI_TD_E;
+}
+
+static void write_cpld_data(char ch)
+{
+ while (!check_write_ready())
+ ;
+
+ *SC_TDR = ch;
+ *SC_SR;
+ *SC_SR = SCI_TDRE_CLEAR;
+}
+
+static int delay(void)
+{
+ int i;
+ int c = 0;
+ for (i = 0; i < 200; i++) {
+ c = *(volatile int *)0xa0000000;
+ }
+ return c;
+}
+
+/***********************************************************************
+ *
+ * Function: slave_serial
+ *
+ * Description: Initiates SlaveSerial Configuration.
+ * Calls ShiftDataOut() to output serial data
+ *
+ ***********************************************************************/
+static void slave_serial(void)
+{
+ int i;
+ unsigned char *flash;
+
+ *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
+ delay();
+
+ /*
+ * Toggle Program Pin by Toggling Program_OE bit
+ * This is accomplished by writing to the Program Register in the CPLD
+ *
+ * NOTE: The Program_OE bit should be driven high to bring the Virtex
+ * Program Pin low. Likewise, it should be driven low
+ * to bring the Virtex Program Pin to High-Z
+ */
+
+ *CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */
+ delay();
+
+ /*
+ * Bring Program High-Z
+ * (Drive Program_OE bit low to bring Virtex Program Pin to High-Z
+ */
+
+ /* Program_OE bit Low brings the Virtex Program Pin to High Z: */
+ *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */
+
+ while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0)
+ delay();
+
+ /* Begin Slave-Serial Configuration */
+ flash = (unsigned char *)CPLD_NOMAL_START;
+
+ for (i = 0; i < CPLD_DATA_SIZE; i++)
+ write_cpld_data(*flash++);
+}
+
+/***********************************************************************
+ *
+ * Function: check_done_bit
+ *
+ * Description: This function takes monitors the CPLD Input Register
+ * by checking the status of the DONE bit in that Register.
+ * By doing so, it monitors the Xilinx Virtex device's DONE
+ * Pin to see if configuration bitstream has been properly
+ * loaded
+ *
+ ***********************************************************************/
+static void check_done_bit(void)
+{
+ while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT))
+ ;
+}
+
+/***********************************************************************
+ *
+ * Function: init_cpld
+ *
+ * Description: Begins Slave Serial configuration of Xilinx FPGA
+ *
+ ***********************************************************************/
+void init_cpld(void)
+{
+ /* Init serial device */
+ init_cpld_loader();
+
+ if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */
+ return;
+
+ *HIZCRB = 0x0000;
+ *CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */
+
+ /* write CPLD data from NOR flash to device */
+ slave_serial();
+
+ /*
+ * Monitor the DONE bit in the CPLD Input Register to see if
+ * configuration successful
+ */
+
+ check_done_bit();
+}
diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S
new file mode 100644
index 0000000..ead5310
--- /dev/null
+++ b/board/renesas/ap325rxa/lowlevel_init.S
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * board/ap325rxa/lowlevel_init.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+ write16 DRVCRA_A, DRVCRA_D
+
+ write16 DRVCRB_A, DRVCRB_D
+
+ write16 RWTCSR_A, RWTCSR_D1
+
+ write16 RWTCNT_A, RWTCNT_D
+
+ write16 RWTCSR_A, RWTCSR_D2
+
+ write32 FRQCR_A, FRQCR_D
+
+ write32 CMNCR_A, CMNCR_D
+
+ write32 CS0BCR_A, CS0BCR_D
+
+ write32 CS4BCR_A, CS4BCR_D
+
+ write32 CS5ABCR_A, CS5ABCR_D
+
+ write32 CS5BBCR_A, CS5BBCR_D
+
+ write32 CS6ABCR_A, CS6ABCR_D
+
+ write32 CS6BBCR_A, CS6BBCR_D
+
+ write32 CS0WCR_A, CS0WCR_D
+
+ write32 CS4WCR_A, CS4WCR_D
+
+ write32 CS5AWCR_A, CS5AWCR_D
+
+ write32 CS5BWCR_A, CS5BWCR_D
+
+ write32 CS6AWCR_A, CS6AWCR_D
+
+ write32 CS6BWCR_A, CS6BWCR_D
+
+ write32 SBSC_SDCR_A, SBSC_SDCR_D1
+
+ write32 SBSC_SDWCR_A, SBSC_SDWCR_D
+
+ write32 SBSC_SDPCR_A, SBSC_SDPCR_D
+
+ write32 SBSC_RTCSR_A, SBSC_RTCSR_D
+
+ write32 SBSC_RTCNT_A, SBSC_RTCNT_D
+
+ write32 SBSC_RTCOR_A, SBSC_RTCOR_D
+
+ write8 SBSC_SDMR3_A1, SBSC_SDMR3_D
+
+ write8 SBSC_SDMR3_A2, SBSC_SDMR3_D
+
+ mov.l SLEEP_CNT, r1
+2: tst r1, r1
+ nop
+ bf/s 2b
+ dt r1
+
+ write8 SBSC_SDMR3_A3, SBSC_SDMR3_D
+
+ write32 SBSC_SDCR_A, SBSC_SDCR_D2
+
+ write32 CCR_A, CCR_D
+
+ ! BL bit off (init = ON) (?!?)
+
+ stc sr, r0 ! BL bit off(init=ON)
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+ mov #0, r0
+
+ .align 2
+
+DRVCRA_A: .long DRVCRA
+DRVCRB_A: .long DRVCRB
+DRVCRA_D: .word 0x4555
+DRVCRB_D: .word 0x0005
+
+RWTCSR_A: .long RWTCSR
+RWTCNT_A: .long RWTCNT
+FRQCR_A: .long FRQCR
+RWTCSR_D1: .word 0xa507
+RWTCSR_D2: .word 0xa504
+RWTCNT_D: .word 0x5a00
+.align 2
+FRQCR_D: .long 0x0b04474a
+
+SBSC_SDCR_A: .long SBSC_SDCR
+SBSC_SDWCR_A: .long SBSC_SDWCR
+SBSC_SDPCR_A: .long SBSC_SDPCR
+SBSC_RTCSR_A: .long SBSC_RTCSR
+SBSC_RTCNT_A: .long SBSC_RTCNT
+SBSC_RTCOR_A: .long SBSC_RTCOR
+SBSC_SDMR3_A1: .long 0xfe510000
+SBSC_SDMR3_A2: .long 0xfe500242
+SBSC_SDMR3_A3: .long 0xfe5c0042
+
+SBSC_SDCR_D1: .long 0x92810112
+SBSC_SDCR_D2: .long 0x92810912
+SBSC_SDWCR_D: .long 0x05162482
+SBSC_SDPCR_D: .long 0x00300087
+SBSC_RTCSR_D: .long 0xa55a0212
+SBSC_RTCNT_D: .long 0xa55a0000
+SBSC_RTCOR_D: .long 0xa55a0040
+SBSC_SDMR3_D: .long 0x00
+
+CMNCR_A: .long CMNCR
+CS0BCR_A: .long CS0BCR
+CS4BCR_A: .long CS4BCR
+CS5ABCR_A: .long CS5ABCR
+CS5BBCR_A: .long CS5BBCR
+CS6ABCR_A: .long CS6ABCR
+CS6BBCR_A: .long CS6BBCR
+CS0WCR_A: .long CS0WCR
+CS4WCR_A: .long CS4WCR
+CS5AWCR_A: .long CS5AWCR
+CS5BWCR_A: .long CS5BWCR
+CS6AWCR_A: .long CS6AWCR
+CS6BWCR_A: .long CS6BWCR
+
+CMNCR_D: .long 0x00000013
+CS0BCR_D: .long 0x24920400
+CS4BCR_D: .long 0x24920400
+CS5ABCR_D: .long 0x24920400
+CS5BBCR_D: .long 0x7fff0600
+CS6ABCR_D: .long 0x24920400
+CS6BBCR_D: .long 0x24920600
+CS0WCR_D: .long 0x00000480
+CS4WCR_D: .long 0x00000480
+CS5AWCR_D: .long 0x00000380
+CS5BWCR_D: .long 0x00000080
+CS6AWCR_D: .long 0x00000300
+CS6BWCR_D: .long 0x00000540
+
+CCR_A: .long 0xff00001c
+CCR_D: .long 0x0000090d
+
+SLEEP_CNT: .long 0x00000800
+SR_MASK_D: .long 0xEFFFFF0F
diff --git a/board/renesas/ecovec/Kconfig b/board/renesas/ecovec/Kconfig
new file mode 100644
index 0000000..08cde83
--- /dev/null
+++ b/board/renesas/ecovec/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ECOVEC
+
+config SYS_BOARD
+ default "ecovec"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "ecovec"
+
+endif
diff --git a/board/renesas/ecovec/MAINTAINERS b/board/renesas/ecovec/MAINTAINERS
new file mode 100644
index 0000000..439b528
--- /dev/null
+++ b/board/renesas/ecovec/MAINTAINERS
@@ -0,0 +1,7 @@
+ECOVEC BOARD
+M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S: Maintained
+F: board/renesas/ecovec/
+F: include/configs/ecovec.h
+F: configs/ecovec_defconfig
diff --git a/board/renesas/ecovec/Makefile b/board/renesas/ecovec/Makefile
new file mode 100644
index 0000000..943fa47
--- /dev/null
+++ b/board/renesas/ecovec/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := ecovec.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c
new file mode 100644
index 0000000..d862d99
--- /dev/null
+++ b/board/renesas/ecovec/ecovec.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2009, 2011 Renesas Solutions Corp.
+ * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <netdev.h>
+
+/* USB power management register */
+#define UPONCR0 0xA40501D4
+
+int checkboard(void)
+{
+ puts("BOARD: ecovec\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+static void debug_led(u8 led)
+{
+ /* PDGR[0-4] is debug LED */
+ outb((inb(PGDR) & ~0x0F) | (led & 0x0F), PGDR);
+}
+
+int board_late_init(void)
+{
+ u8 mac[6];
+ char env_mac[18];
+
+ udelay(1000);
+
+ /* SH-Eth (PLCR, PNCR, PXCR, PSELx )*/
+ outw(inw(PLCR) & ~0xFFF0, PLCR);
+ outw(inw(PNCR) & ~0x000F, PNCR);
+ outw(inw(PXCR) & ~0x0FC0, PXCR);
+ outw((inw(PSELB) & ~0x030F) | 0x020A, PSELB);
+ outw((inw(PSELC) & ~0x0307) | 0x0207, PSELC);
+ outw((inw(PSELE) & ~0x00c0) | 0x0080, PSELE);
+
+ debug_led(1 << 3);
+
+ outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2);
+
+ i2c_set_bus_num(1); /* Use I2C 1 */
+
+ /* Read MAC address */
+ i2c_read(0x50, 0x10, 0, mac, 6);
+
+ /* Set MAC address */
+ sprintf(env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ setenv("ethaddr", env_mac);
+
+ debug_led(0x0F);
+
+ return 0;
+}
+
+int board_init(void)
+{
+
+ /* LED (PTG) */
+ outw((inw(PGCR) & ~0xFF) | 0x55, PGCR);
+ outw((inw(HIZCRA) & ~0x02), HIZCRA);
+
+ debug_led(1 << 0);
+
+ /* SCIF0 (PTF, PTM) */
+ outw(inw(PFCR) & ~0x30, PFCR);
+ outw(inw(PMCR) & ~0x0C, PMCR);
+ outw((inw(PSELA) & ~0x40) | 0x40, PSELA);
+
+ debug_led(1 << 1);
+
+ /* RMII (PTA) */
+ outw((inw(PACR) & ~0x0C) | 0x04, PACR);
+ outb((inb(PADR) & ~0x02) | 0x02, PADR);
+
+ debug_led(1 << 2);
+
+ /* USB host */
+ outw((inw(PBCR) & ~0x300) | 0x100, PBCR);
+ outb((inb(PBDR) & ~0x10) | 0x10, PBDR);
+ outl(inl(MSTPCR2) & ~0x100000, MSTPCR2);
+ outw(0x0600, UPONCR0);
+
+ debug_led(1 << 3);
+
+ /* debug switch */
+ outw((inw(PVCR) & ~0x03) | 0x02 , PVCR);
+
+ return 0;
+}
diff --git a/board/renesas/ecovec/lowlevel_init.S b/board/renesas/ecovec/lowlevel_init.S
new file mode 100644
index 0000000..e4c40c8
--- /dev/null
+++ b/board/renesas/ecovec/lowlevel_init.S
@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
+ *
+ * board/renesas/ecovec/lowlevel_init.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+#include <configs/ecovec.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ /* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */
+ mov.l PVDR_A, r1
+ mov.l PVDR_D, r2
+ mov.b @r1, r0
+ tst r0, r2
+ bt 1f
+ mov.l JUMP_A, r1
+ jmp @r1
+ nop
+
+1:
+ /* Disable watchdog */
+ write16 RWTCSR_A, RWTCSR_D
+
+ /* MMU Disable */
+ write32 MMUCR_A, MMUCR_D
+
+ /* Setup clocks */
+ write32 PLLCR_A, PLLCR_D
+ write32 FRQCRA_A, FRQCRA_D
+ write32 FRQCRB_A, FRQCRB_D
+
+ wait_timer TIMER_D
+
+ write32 MMSELR_A, MMSELR_D
+
+ /* Srtup BSC */
+ write32 CMNCR_A, CMNCR_D
+ write32 CS0BCR_A, CS0BCR_D
+ write32 CS0WCR_A, CS0WCR_D
+
+ wait_timer TIMER_D
+
+ /* Setup SDRAM */
+ write32 DBPDCNT0_A, DBPDCNT0_D0
+ write32 DBCONF_A, DBCONF_D
+ write32 DBTR0_A, DBTR0_D
+ write32 DBTR1_A, DBTR1_D
+ write32 DBTR2_A, DBTR2_D
+ write32 DBTR3_A, DBTR3_D
+ write32 DBKIND_A, DBKIND_D
+ write32 DBCKECNT_A, DBCKECNT_D
+
+ wait_timer TIMER_D
+
+ write32 DBCMDCNT_A, DBCMDCNT_D0
+ write32 DBMRCNT_A, DBMRCNT_D0
+ write32 DBMRCNT_A, DBMRCNT_D1
+ write32 DBMRCNT_A, DBMRCNT_D2
+ write32 DBMRCNT_A, DBMRCNT_D3
+ write32 DBCMDCNT_A, DBCMDCNT_D0
+ write32 DBCMDCNT_A, DBCMDCNT_D1
+ write32 DBCMDCNT_A, DBCMDCNT_D1
+ write32 DBMRCNT_A, DBMRCNT_D4
+ write32 DBMRCNT_A, DBMRCNT_D5
+ write32 DBMRCNT_A, DBMRCNT_D6
+
+ wait_timer TIMER_D
+
+ write32 DBEN_A, DBEN_D
+ write32 DBRFPDN1_A, DBRFPDN1_D
+ write32 DBRFPDN2_A, DBRFPDN2_D
+ write32 DBCMDCNT_A, DBCMDCNT_D0
+
+
+ /* Dummy read */
+ mov.l DUMMY_A ,r1
+ synco
+ mov.l @r1, r0
+ synco
+
+ mov.l SDRAM_A ,r1
+ synco
+ mov.l @r1, r0
+ synco
+ wait_timer TIMER_D
+
+ add #4, r1
+ synco
+ mov.l @r1, r0
+ synco
+ wait_timer TIMER_D
+
+ add #4, r1
+ synco
+ mov.l @r1, r0
+ synco
+ wait_timer TIMER_D
+
+ add #4, r1
+ synco
+ mov.l @r1, r0
+ synco
+ wait_timer TIMER_D
+
+ write32 DBCMDCNT_A, DBCMDCNT_D0
+ write32 DBCMDCNT_A, DBCMDCNT_D1
+ write32 DBPDCNT0_A, DBPDCNT0_D1
+ write32 DBRFPDN0_A, DBRFPDN0_D
+
+ wait_timer TIMER_D
+
+ write32 CCR_A, CCR_D
+
+ stc sr, r0
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+
+ .align 2
+
+PVDR_A: .long PVDR
+PVDR_D: .long 0x00000001
+JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR
+TIMER_D: .long 64
+RWTCSR_A: .long RWTCSR
+RWTCSR_D: .long 0x0000A507
+MMUCR_A: .long MMUCR
+MMUCR_D: .long 0x00000004
+PLLCR_A: .long PLLCR
+PLLCR_D: .long 0x00004000
+FRQCRA_A: .long FRQCRA
+FRQCRA_D: .long 0x8E003508
+FRQCRB_A: .long FRQCRB
+FRQCRB_D: .long 0x0
+MMSELR_A: .long MMSELR
+MMSELR_D: .long 0xA5A50000
+CMNCR_A: .long CMNCR
+CMNCR_D: .long 0x00000013
+CS0BCR_A: .long CS0BCR
+CS0BCR_D: .long 0x11110400
+CS0WCR_A: .long CS0WCR
+CS0WCR_D: .long 0x00000440
+DBPDCNT0_A: .long DBPDCNT0
+DBPDCNT0_D0: .long 0x00000181
+DBPDCNT0_D1: .long 0x00000080
+DBCONF_A: .long DBCONF
+DBCONF_D: .long 0x015B0002
+DBTR0_A: .long DBTR0
+DBTR0_D: .long 0x03061502
+DBTR1_A: .long DBTR1
+DBTR1_D: .long 0x02020102
+DBTR2_A: .long DBTR2
+DBTR2_D: .long 0x01090305
+DBTR3_A: .long DBTR3
+DBTR3_D: .long 0x00000002
+DBKIND_A: .long DBKIND
+DBKIND_D: .long 0x00000005
+DBCKECNT_A: .long DBCKECNT
+DBCKECNT_D: .long 0x00000001
+DBCMDCNT_A: .long DBCMDCNT
+DBCMDCNT_D0:.long 0x2
+DBCMDCNT_D1:.long 0x4
+DBMRCNT_A: .long DBMRCNT
+DBMRCNT_D0: .long 0x00020000
+DBMRCNT_D1: .long 0x00030000
+DBMRCNT_D2: .long 0x00010040
+DBMRCNT_D3: .long 0x00000532
+DBMRCNT_D4: .long 0x00000432
+DBMRCNT_D5: .long 0x000103C0
+DBMRCNT_D6: .long 0x00010040
+DBEN_A: .long DBEN
+DBEN_D: .long 0x01
+DBRFPDN0_A: .long DBRFPDN0
+DBRFPDN1_A: .long DBRFPDN1
+DBRFPDN2_A: .long DBRFPDN2
+DBRFPDN0_D: .long 0x00010000
+DBRFPDN1_D: .long 0x00000613
+DBRFPDN2_D: .long 0x238C003A
+SDRAM_A: .long 0xa8000000
+DUMMY_A: .long 0x0c400000
+CCR_A: .long CCR
+CCR_D: .long 0x0000090B
+SR_MASK_D: .long 0xEFFFFF0F
diff --git a/board/renesas/gose/Kconfig b/board/renesas/gose/Kconfig
new file mode 100644
index 0000000..930a445
--- /dev/null
+++ b/board/renesas/gose/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_GOSE
+
+config SYS_BOARD
+ default "gose"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "gose"
+
+endif
diff --git a/board/renesas/gose/MAINTAINERS b/board/renesas/gose/MAINTAINERS
new file mode 100644
index 0000000..cad5be9
--- /dev/null
+++ b/board/renesas/gose/MAINTAINERS
@@ -0,0 +1,6 @@
+ALT BOARD
+M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+S: Maintained
+F: board/renesas/gose/
+F: include/configs/gose.h
+F: configs/gose_defconfig
diff --git a/board/renesas/gose/Makefile b/board/renesas/gose/Makefile
new file mode 100644
index 0000000..2dac748
--- /dev/null
+++ b/board/renesas/gose/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/alt/Makefile
+#
+# Copyright (C) 2014 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := gose.o qos.o ../rcar-gen2-common/common.o
diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
new file mode 100644
index 0000000..677b976
--- /dev/null
+++ b/board/renesas/gose/gose.c
@@ -0,0 +1,146 @@
+/*
+ * board/renesas/gose/gose.c
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+ u32 stc;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ /* CPU frequency setting. Set to 1.5GHz */
+ stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+ /* QoS */
+ qos_init();
+}
+
+#define TMU0_MSTP125 (1 << 25)
+#define SCIF0_MSTP721 (1 << 21)
+#define ETHER_MSTP813 (1 << 13)
+
+int board_early_init_f(void)
+{
+ /* TMU0 */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+ /* SCIF0 */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+ /* ETHER */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
+ return 0;
+}
+
+#define PUPR5 0xE6060114
+#define PUPR5_ETH 0x3FFC0000
+#define PUPR5_ETH_MAGIC (1 << 27)
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ /* Init PFC controller */
+ r8a7793_pinmux_init();
+
+ /* ETHER Enable */
+ gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+ gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+ gpio_request(GPIO_FN_ETH_RXD0, NULL);
+ gpio_request(GPIO_FN_ETH_RXD1, NULL);
+ gpio_request(GPIO_FN_ETH_LINK, NULL);
+ gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+ gpio_request(GPIO_FN_ETH_MDIO, NULL);
+ gpio_request(GPIO_FN_ETH_TXD1, NULL);
+ gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+ gpio_request(GPIO_FN_ETH_TXD0, NULL);
+ gpio_request(GPIO_FN_ETH_MDC, NULL);
+ gpio_request(GPIO_FN_IRQ0, NULL);
+
+ mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
+ gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
+ mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
+
+ gpio_direction_output(GPIO_GP_5_22, 0);
+ mdelay(20);
+ gpio_set_value(GPIO_GP_5_22, 1);
+ udelay(1);
+
+ return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = -ENODEV;
+ u32 val;
+ unsigned char enetaddr[6];
+
+#ifdef CONFIG_SH_ETHER
+ ret = sh_eth_initialize(bis);
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ return ret;
+
+ /* Set Mac address */
+ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+ enetaddr[2] << 8 | enetaddr[3];
+ writel(val, CXR24);
+
+ val = enetaddr[4] << 8 | enetaddr[5];
+ writel(val, CXR25);
+#endif
+
+ return ret;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
+{
+ u8 val;
+
+ i2c_set_bus_num(2); /* PowerIC connected to ch2 */
+ i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ val |= 0x02;
+ i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}
diff --git a/board/renesas/gose/qos.c b/board/renesas/gose/qos.c
new file mode 100644
index 0000000..64e52cf
--- /dev/null
+++ b/board/renesas/gose/qos.c
@@ -0,0 +1,1155 @@
+/*
+ * board/renesas/gose/qos.c
+ * This file is gose QoS setting.
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+/* QoS version 0.20 */
+enum {
+ DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+ DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+ DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+ DBSC3_15,
+ DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+ int i;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
+
+ /* DBSC DBADJ2 */
+ writel(0x20042004, DBSC3_0_DBADJ2);
+
+ /* S3C -QoS */
+ s3c = (struct rcar_s3c *)S3C_BASE;
+ writel(0x00000000, &s3c->s3cadsplcr);
+ writel(0x1F0B0908, &s3c->s3crorr);
+ writel(0x1F0C0A08, &s3c->s3cworr);
+
+ /* QoS Control Registers */
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+ writel(0x00820082, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20DC, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20DC, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+ writel(0x00820082, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20FA, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20FA, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ /* DBSC -QoS */
+ /* DBSC0 - Read */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002032, &qos_addr->dbtmval2);
+ writel(0x00001FB0, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000201E, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* DBSC0 - Write */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002050, &qos_addr->dbtmval2);
+ writel(0x0000203A, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000203C, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* CCI-400 -QoS */
+ writel(0x20001000, CCI_400_MAXOT_1);
+ writel(0x20001000, CCI_400_MAXOT_2);
+ writel(0x0000000C, CCI_400_QOSCNTL_1);
+ writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+ /* MXI -QoS */
+ /* Transaction Control (MXI) */
+ mxi = (struct rcar_mxi *)MXI_BASE;
+ writel(0x00000013, &mxi->mxrtcr);
+ writel(0x00000013, &mxi->mxwtcr);
+ writel(0x00200000, &mxi->mxs3cracr);
+ writel(0x00200000, &mxi->mxs3cwacr);
+ writel(0x00200000, &mxi->mxaxiracr);
+ writel(0x00200000, &mxi->mxaxiwacr);
+
+ /* QoS Control (MXI) */
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+ writel(0x0000000C, &mxi_qos->vspdu0);
+ writel(0x0000000C, &mxi_qos->vspdu1);
+ writel(0x0000000E, &mxi_qos->du0);
+
+ /* AXI -QoS */
+ /* Transaction Control (MXI) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002037, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (RT-AXI) */
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002299, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (MP-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002037, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000206E, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (SYS-AXI256) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (CCI-AXI) */
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (Media-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020DC, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020DC, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/gose/qos.h b/board/renesas/gose/qos.h
new file mode 100644
index 0000000..ffd4047
--- /dev/null
+++ b/board/renesas/gose/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/board/renesas/koelsch/Kconfig b/board/renesas/koelsch/Kconfig
new file mode 100644
index 0000000..6475f02
--- /dev/null
+++ b/board/renesas/koelsch/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_KOELSCH
+
+config SYS_BOARD
+ default "koelsch"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "koelsch"
+
+endif
diff --git a/board/renesas/koelsch/MAINTAINERS b/board/renesas/koelsch/MAINTAINERS
new file mode 100644
index 0000000..5267b9f
--- /dev/null
+++ b/board/renesas/koelsch/MAINTAINERS
@@ -0,0 +1,6 @@
+KOELSCH BOARD
+M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+S: Maintained
+F: board/renesas/koelsch/
+F: include/configs/koelsch.h
+F: configs/koelsch_defconfig
diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile
new file mode 100644
index 0000000..c10bba5
--- /dev/null
+++ b/board/renesas/koelsch/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/koelsch/Makefile
+#
+# Copyright (C) 2013 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := koelsch.o qos.o ../rcar-gen2-common/common.o
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
new file mode 100644
index 0000000..10fa571
--- /dev/null
+++ b/board/renesas/koelsch/koelsch.c
@@ -0,0 +1,162 @@
+/*
+ * board/renesas/koelsch/koelsch.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <div64.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+ u32 stc;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ /* CPU frequency setting. Set to 1.5GHz */
+ stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+ /* QoS */
+ qos_init();
+}
+
+#define TMU0_MSTP125 (1 << 25)
+#define SCIF0_MSTP721 (1 << 21)
+#define ETHER_MSTP813 (1 << 13)
+
+int board_early_init_f(void)
+{
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+ /* SCIF0 */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+ /* ETHER */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
+ return 0;
+}
+
+/* LSI pin pull-up control */
+#define PUPR5 0xe6060114
+#define PUPR5_ETH 0x3FFC0000
+#define PUPR5_ETH_MAGIC (1 << 27)
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ /* Init PFC controller */
+ r8a7791_pinmux_init();
+
+ /* ETHER Enable */
+ gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+ gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+ gpio_request(GPIO_FN_ETH_RXD0, NULL);
+ gpio_request(GPIO_FN_ETH_RXD1, NULL);
+ gpio_request(GPIO_FN_ETH_LINK, NULL);
+ gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+ gpio_request(GPIO_FN_ETH_MDIO, NULL);
+ gpio_request(GPIO_FN_ETH_TXD1, NULL);
+ gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+ gpio_request(GPIO_FN_ETH_TXD0, NULL);
+ gpio_request(GPIO_FN_ETH_MDC, NULL);
+ gpio_request(GPIO_FN_IRQ0, NULL);
+
+ mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
+ gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
+ mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
+
+ gpio_direction_output(GPIO_GP_5_22, 0);
+ mdelay(20);
+ gpio_set_value(GPIO_GP_5_22, 1);
+ udelay(1);
+
+ return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SH_ETHER
+ int ret = -ENODEV;
+ u32 val;
+ unsigned char enetaddr[6];
+
+ ret = sh_eth_initialize(bis);
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ return ret;
+
+ /* Set Mac address */
+ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+ enetaddr[2] << 8 | enetaddr[3];
+ writel(val, CXR24);
+
+ val = enetaddr[4] << 8 | enetaddr[5];
+ writel(val, CXR25);
+
+ return ret;
+#else
+ return 0;
+#endif
+}
+
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+/* koelsch has KSZ8041NL/RNL */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
+#define PHY_LED_MODE_ACK 0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+ ret &= ~PHY_LED_MODE;
+ ret |= PHY_LED_MODE_ACK;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+ return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
+{
+ u8 val;
+
+ i2c_set_bus_num(2); /* PowerIC connected to ch2 */
+ i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ val |= 0x02;
+ i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}
diff --git a/board/renesas/koelsch/qos.c b/board/renesas/koelsch/qos.c
new file mode 100644
index 0000000..d293e3d
--- /dev/null
+++ b/board/renesas/koelsch/qos.c
@@ -0,0 +1,1311 @@
+/*
+ * board/renesas/koelsch/qos.c
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.240 for ES1 and version 0.334 for ES2 */
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+enum {
+ DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+ DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+ DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+ DBSC3_15,
+ DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_1_QOS_R0_BASE,
+ [DBSC3_01] = DBSC3_1_QOS_R1_BASE,
+ [DBSC3_02] = DBSC3_1_QOS_R2_BASE,
+ [DBSC3_03] = DBSC3_1_QOS_R3_BASE,
+ [DBSC3_04] = DBSC3_1_QOS_R4_BASE,
+ [DBSC3_05] = DBSC3_1_QOS_R5_BASE,
+ [DBSC3_06] = DBSC3_1_QOS_R6_BASE,
+ [DBSC3_07] = DBSC3_1_QOS_R7_BASE,
+ [DBSC3_08] = DBSC3_1_QOS_R8_BASE,
+ [DBSC3_09] = DBSC3_1_QOS_R9_BASE,
+ [DBSC3_10] = DBSC3_1_QOS_R10_BASE,
+ [DBSC3_11] = DBSC3_1_QOS_R11_BASE,
+ [DBSC3_12] = DBSC3_1_QOS_R12_BASE,
+ [DBSC3_13] = DBSC3_1_QOS_R13_BASE,
+ [DBSC3_14] = DBSC3_1_QOS_R14_BASE,
+ [DBSC3_15] = DBSC3_1_QOS_R15_BASE,
+};
+
+static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_1_QOS_W0_BASE,
+ [DBSC3_01] = DBSC3_1_QOS_W1_BASE,
+ [DBSC3_02] = DBSC3_1_QOS_W2_BASE,
+ [DBSC3_03] = DBSC3_1_QOS_W3_BASE,
+ [DBSC3_04] = DBSC3_1_QOS_W4_BASE,
+ [DBSC3_05] = DBSC3_1_QOS_W5_BASE,
+ [DBSC3_06] = DBSC3_1_QOS_W6_BASE,
+ [DBSC3_07] = DBSC3_1_QOS_W7_BASE,
+ [DBSC3_08] = DBSC3_1_QOS_W8_BASE,
+ [DBSC3_09] = DBSC3_1_QOS_W9_BASE,
+ [DBSC3_10] = DBSC3_1_QOS_W10_BASE,
+ [DBSC3_11] = DBSC3_1_QOS_W11_BASE,
+ [DBSC3_12] = DBSC3_1_QOS_W12_BASE,
+ [DBSC3_13] = DBSC3_1_QOS_W13_BASE,
+ [DBSC3_14] = DBSC3_1_QOS_W14_BASE,
+ [DBSC3_15] = DBSC3_1_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+ int i;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
+
+ /* DBSC DBADJ2 */
+ writel(0x20042004, DBSC3_0_DBADJ2);
+ writel(0x20042004, DBSC3_1_DBADJ2);
+
+ /* S3C -QoS */
+ s3c = (struct rcar_s3c *)S3C_BASE;
+ if (IS_R8A7791_ES2()) {
+ /* Linear All mode */
+ /* writel(0x00000000, &s3c->s3cadsplcr); */
+ /* Linear Linear 0x7000 to 0x7800 mode */
+ writel(0x00BF1B0C, &s3c->s3cadsplcr);
+ /* Split Linear 0x6800 t 0x7000 mode */
+ /* writel(0x00DF1B0C, &s3c->s3cadsplcr); */
+ /* Ssplit All mode */
+ /* writel(0x00FF1B0C, &s3c->s3cadsplcr); */
+ writel(0x1F0B0908, &s3c->s3crorr);
+ writel(0x1F0C0A08, &s3c->s3cworr);
+ } else {
+ writel(0x00FF1B1D, &s3c->s3cadsplcr);
+ writel(0x1F0D0C0C, &s3c->s3crorr);
+ writel(0x1F0D0C0A, &s3c->s3cworr);
+ }
+ /* QoS Control Registers */
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+ writel(0x00820082, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20DC, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20DC, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+ writel(0x00820082, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20FA, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20FA, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ /* DBSC -QoS */
+ /* DBSC0 - Read */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002032, &qos_addr->dbtmval2);
+ writel(0x00001FB0, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000201E, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* DBSC0 - Write */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002050, &qos_addr->dbtmval2);
+ writel(0x0000203A, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000203C, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* DBSC1 - Read */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002032, &qos_addr->dbtmval2);
+ writel(0x00001FB0, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000201E, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* DBSC1 - Write */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002050, &qos_addr->dbtmval2);
+ writel(0x0000203A, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000203C, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* CCI-400 -QoS */
+ writel(0x20001000, CCI_400_MAXOT_1);
+ writel(0x20001000, CCI_400_MAXOT_2);
+ writel(0x0000000C, CCI_400_QOSCNTL_1);
+ writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+ /* MXI -QoS */
+ /* Transaction Control (MXI) */
+ mxi = (struct rcar_mxi *)MXI_BASE;
+ writel(0x00000013, &mxi->mxrtcr);
+ writel(0x00000013, &mxi->mxwtcr);
+
+ /* QoS Control (MXI) */
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+ writel(0x0000000C, &mxi_qos->vspdu0);
+ writel(0x0000000C, &mxi_qos->vspdu1);
+ writel(0x0000000E, &mxi_qos->du0);
+ writel(0x0000000D, &mxi_qos->du1);
+
+ /* AXI -QoS */
+ /* Transaction Control (MXI) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002037, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (RT-AXI) */
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002299, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (MP-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002037, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000206E, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (SYS-AXI256) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ if (IS_R8A7791_ES2())
+ writel(0x000020EB, &axi_qos->qosctset0);
+ else
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ if (IS_R8A7791_ES2())
+ writel(0x000020EB, &axi_qos->qosctset0);
+ else
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ if (IS_R8A7791_ES2())
+ writel(0x000020EB, &axi_qos->qosctset0);
+ else
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (CCI-AXI) */
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (Media-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020DC, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020DC, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ if (IS_R8A7791_ES2())
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ else
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ if (IS_R8A7791_ES2())
+ writel(0x00002001, &axi_qos->qosthres2);
+ else
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000000, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/koelsch/qos.h b/board/renesas/koelsch/qos.h
new file mode 100644
index 0000000..9a6c046
--- /dev/null
+++ b/board/renesas/koelsch/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/board/renesas/lager/Kconfig b/board/renesas/lager/Kconfig
new file mode 100644
index 0000000..e990c20
--- /dev/null
+++ b/board/renesas/lager/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_LAGER
+
+config SYS_BOARD
+ default "lager"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "lager"
+
+endif
diff --git a/board/renesas/lager/MAINTAINERS b/board/renesas/lager/MAINTAINERS
new file mode 100644
index 0000000..a098686
--- /dev/null
+++ b/board/renesas/lager/MAINTAINERS
@@ -0,0 +1,6 @@
+LAGER BOARD
+M: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+S: Maintained
+F: board/renesas/lager/
+F: include/configs/lager.h
+F: configs/lager_defconfig
diff --git a/board/renesas/lager/Makefile b/board/renesas/lager/Makefile
new file mode 100644
index 0000000..8d03461
--- /dev/null
+++ b/board/renesas/lager/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/lager/Makefile
+#
+# Copyright (C) 2013 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := lager.o qos.o ../rcar-gen2-common/common.o
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
new file mode 100644
index 0000000..d1e29d2
--- /dev/null
+++ b/board/renesas/lager/lager.c
@@ -0,0 +1,191 @@
+/*
+ * board/renesas/lager/lager.c
+ * This file is lager board support.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <mmc.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
+void s_init(void)
+{
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+ /* Watchdog init */
+ writel(0xA5A5A500, &rwdt->rwtcsra);
+ writel(0xA5A5A500, &swdt->swtcsra);
+
+ /* CPU frequency setting. Set to 1.4GHz */
+ if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
+ u32 stat = 0;
+ u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
+ << PLL0_STC_BIT;
+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+ do {
+ stat = readl(PLLECR) & PLL0ST;
+ } while (stat == 0x0);
+ }
+
+ /* QoS(Quality-of-Service) Init */
+ qos_init();
+}
+
+#define TMU0_MSTP125 (1 << 25)
+#define SCIF0_MSTP721 (1 << 21)
+#define ETHER_MSTP813 (1 << 13)
+#define MMC1_MSTP305 (1 << 5)
+
+int board_early_init_f(void)
+{
+ /* TMU0 */
+ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+ /* SCIF0 */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+ /* ETHER */
+ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+ /* eMMC */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305);
+
+ return 0;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ /* Init PFC controller */
+ r8a7790_pinmux_init();
+
+ /* ETHER Enable */
+ gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+ gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+ gpio_request(GPIO_FN_ETH_RXD0, NULL);
+ gpio_request(GPIO_FN_ETH_RXD1, NULL);
+ gpio_request(GPIO_FN_ETH_LINK, NULL);
+ gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
+ gpio_request(GPIO_FN_ETH_MDIO, NULL);
+ gpio_request(GPIO_FN_ETH_TXD1, NULL);
+ gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+ gpio_request(GPIO_FN_ETH_MAGIC, NULL);
+ gpio_request(GPIO_FN_ETH_TXD0, NULL);
+ gpio_request(GPIO_FN_ETH_MDC, NULL);
+ gpio_request(GPIO_FN_IRQ0, NULL);
+
+ gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */
+ gpio_direction_output(GPIO_GP_5_31, 0);
+ mdelay(20);
+ gpio_set_value(GPIO_GP_5_31, 1);
+ udelay(1);
+
+ return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+ int ret = -ENODEV;
+
+#ifdef CONFIG_SH_ETHER
+ u32 val;
+ unsigned char enetaddr[6];
+
+ ret = sh_eth_initialize(bis);
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ return ret;
+
+ /* Set Mac address */
+ val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+ enetaddr[2] << 8 | enetaddr[3];
+ writel(val, CXR24);
+
+ val = enetaddr[4] << 8 | enetaddr[5];
+ writel(val, CXR25);
+
+#endif
+
+ return ret;
+}
+
+/* lager has KSZ8041NL/RNL */
+#define PHY_CONTROL1 0x1E
+#define PHY_LED_MODE 0xC0000
+#define PHY_LED_MODE_ACK 0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+ ret &= ~PHY_LED_MODE;
+ ret |= PHY_LED_MODE_ACK;
+ ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret = 0;
+
+#ifdef CONFIG_SH_MMCIF
+ gpio_request(GPIO_FN_MMC1_D0, NULL);
+ gpio_request(GPIO_FN_MMC1_D1, NULL);
+ gpio_request(GPIO_FN_MMC1_D2, NULL);
+ gpio_request(GPIO_FN_MMC1_D3, NULL);
+ gpio_request(GPIO_FN_MMC1_D4, NULL);
+ gpio_request(GPIO_FN_MMC1_D5, NULL);
+ gpio_request(GPIO_FN_MMC1_D6, NULL);
+ gpio_request(GPIO_FN_MMC1_D7, NULL);
+ gpio_request(GPIO_FN_MMC1_CLK, NULL);
+ gpio_request(GPIO_FN_MMC1_CMD, NULL);
+
+ ret = mmcif_mmc_init();
+#endif
+ return ret;
+}
+
+
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+ CONFIG_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
+{
+ u8 val;
+
+ i2c_set_bus_num(3); /* PowerIC connected to ch3 */
+ i2c_init(400000, 0);
+ i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+ val |= 0x02;
+ i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+}
diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c
new file mode 100644
index 0000000..dec37d2
--- /dev/null
+++ b/board/renesas/lager/qos.c
@@ -0,0 +1,2388 @@
+/*
+ * board/renesas/lager/qos.c
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.955 for ES1 and version 0.963 for ES2 */
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+enum {
+ DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+ DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+ DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+ DBSC3_15,
+ DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+ [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+ [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+ [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+ [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+ [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+ [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+ [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+ [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+ [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+ [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+ [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+ [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+ [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+ [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+ [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+ [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+/* QoS version 0.955 for ES1 */
+static void qos_init_es1(void)
+{
+ int i;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
+
+ /* DBSC DBADJ2 */
+ writel(0x20042004, DBSC3_0_DBADJ2);
+
+ /* S3C -QoS */
+ s3c = (struct rcar_s3c *)S3C_BASE;
+ writel(0x80FF1C1E, &s3c->s3cadsplcr);
+ writel(0x1F060505, &s3c->s3crorr);
+ writel(0x1F020100, &s3c->s3cworr);
+
+ /* QoS Control Registers */
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+ writel(0x00800080, &s3c_qos->s3cqos0);
+ writel(0x22000010, &s3c_qos->s3cqos1);
+ writel(0x22002200, &s3c_qos->s3cqos2);
+ writel(0x2F002200, &s3c_qos->s3cqos3);
+ writel(0x2F002F00, &s3c_qos->s3cqos4);
+ writel(0x22000010, &s3c_qos->s3cqos5);
+ writel(0x22002200, &s3c_qos->s3cqos6);
+ writel(0x2F002200, &s3c_qos->s3cqos7);
+ writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+ writel(0x00800080, &s3c_qos->s3cqos0);
+ writel(0x22000010, &s3c_qos->s3cqos1);
+ writel(0x22002200, &s3c_qos->s3cqos2);
+ writel(0x2F002200, &s3c_qos->s3cqos3);
+ writel(0x2F002F00, &s3c_qos->s3cqos4);
+ writel(0x22000010, &s3c_qos->s3cqos5);
+ writel(0x22002200, &s3c_qos->s3cqos6);
+ writel(0x2F002200, &s3c_qos->s3cqos7);
+ writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+ writel(0x80918099, &s3c_qos->s3cqos0);
+ writel(0x20410010, &s3c_qos->s3cqos1);
+ writel(0x200A2023, &s3c_qos->s3cqos2);
+ writel(0x20502001, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20410FFF, &s3c_qos->s3cqos5);
+ writel(0x200A2023, &s3c_qos->s3cqos6);
+ writel(0x20502001, &s3c_qos->s3cqos7);
+ writel(0x20142032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+ writel(0x00810089, &s3c_qos->s3cqos0);
+ writel(0x20410001, &s3c_qos->s3cqos1);
+ writel(0x200A2023, &s3c_qos->s3cqos2);
+ writel(0x20502001, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20410FFF, &s3c_qos->s3cqos5);
+ writel(0x200A2023, &s3c_qos->s3cqos6);
+ writel(0x20502001, &s3c_qos->s3cqos7);
+ writel(0x20142032, &s3c_qos->s3cqos8);
+
+ writel(0x00200808, &s3c->s3carcr11);
+
+ /* DBSC -QoS */
+ /* DBSC0 - Read */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+ writel(0x00000203, &qos_addr->dblgcnt);
+ writel(0x00002064, &qos_addr->dbtmval0);
+ writel(0x00002048, &qos_addr->dbtmval1);
+ writel(0x00002032, &qos_addr->dbtmval2);
+ writel(0x00002019, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002019, &qos_addr->dbthres0);
+ writel(0x00002019, &qos_addr->dbthres1);
+ writel(0x00002019, &qos_addr->dbthres2);
+ writel(0x00000000, &qos_addr->dblgqon);
+ }
+
+ /* DBSC0 - Write */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+ writel(0x00000203, &qos_addr->dblgcnt);
+ writel(0x00002064, &qos_addr->dbtmval0);
+ writel(0x00002048, &qos_addr->dbtmval1);
+ writel(0x00002032, &qos_addr->dbtmval2);
+ writel(0x00002019, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002019, &qos_addr->dbthres0);
+ writel(0x00002019, &qos_addr->dbthres1);
+ writel(0x00002019, &qos_addr->dbthres2);
+ writel(0x00000000, &qos_addr->dblgqon);
+ }
+
+ /* CCI-400 -QoS */
+ writel(0x20001000, CCI_400_MAXOT_1);
+ writel(0x20001000, CCI_400_MAXOT_2);
+ writel(0x0000000C, CCI_400_QOSCNTL_1);
+ writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+ /* MXI -QoS */
+ /* Transaction Control (MXI) */
+ mxi = (struct rcar_mxi *)MXI_BASE;
+ writel(0x00000013, &mxi->mxrtcr);
+ writel(0x00000013, &mxi->mxwtcr);
+ writel(0x00B800C0, &mxi->mxsaar0);
+ writel(0x02000800, &mxi->mxsaar1);
+ writel(0x00200000, &mxi->mxs3cracr);
+ writel(0x00200000, &mxi->mxs3cwacr);
+ writel(0x00200000, &mxi->mxaxiracr);
+ writel(0x00200000, &mxi->mxaxiwacr);
+
+ /* QoS Control (MXI) */
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+ writel(0x0000000C, &mxi_qos->vspdu0);
+ writel(0x0000000C, &mxi_qos->vspdu1);
+ writel(0x0000000D, &mxi_qos->du0);
+ writel(0x0000000D, &mxi_qos->du1);
+
+ /* AXI -QoS */
+ /* Transaction Control (MXI) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200A, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200A, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002002, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002002, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002002, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200A, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200A, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (RT-AXI) */
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002005, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002003, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (MP-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200D, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (SYS-AXI256) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (CCI-AXI) */
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x0000200F, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002001, &axi_qos->qosctset0);
+ writel(0x00002009, &axi_qos->qosctset1);
+ writel(0x00002003, &axi_qos->qosctset2);
+ writel(0x00002003, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (Media-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002018, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000200C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002007, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002006, &axi_qos->qosthres0);
+ writel(0x00002001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000000, &axi_qos->qosqon);
+}
+
+/* QoS version 0.963 for ES2 */
+static void qos_init_es2(void)
+{
+ int i;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
+
+ /* DBSC DBADJ2 */
+ writel(0x20042004, DBSC3_0_DBADJ2);
+
+ /* S3C -QoS */
+ s3c = (struct rcar_s3c *)S3C_BASE;
+ writel(0x80000000, &s3c->s3cadsplcr);
+ writel(0x1F060504, &s3c->s3crorr);
+ writel(0x1F060503, &s3c->s3cworr);
+
+ /* QoS Control Registers */
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+ writel(0x00890089, &s3c_qos->s3cqos0);
+ writel(0x20960010, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA2200, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960010, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA2200, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+ writel(0x80928092, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20DC, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20DC, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+ writel(0x00820082, &s3c_qos->s3cqos0);
+ writel(0x20960020, &s3c_qos->s3cqos1);
+ writel(0x20302030, &s3c_qos->s3cqos2);
+ writel(0x20AA20FA, &s3c_qos->s3cqos3);
+ writel(0x00002032, &s3c_qos->s3cqos4);
+ writel(0x20960020, &s3c_qos->s3cqos5);
+ writel(0x20302030, &s3c_qos->s3cqos6);
+ writel(0x20AA20FA, &s3c_qos->s3cqos7);
+ writel(0x00002032, &s3c_qos->s3cqos8);
+
+ writel(0x00200808, &s3c->s3carcr11);
+
+ /* DBSC -QoS */
+ /* DBSC0 - Read */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002032, &qos_addr->dbtmval2);
+ writel(0x00001FB0, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000201E, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* DBSC0 - Write */
+ for (i = DBSC3_00; i < DBSC3_NR; i++) {
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+ writel(0x00000002, &qos_addr->dblgcnt);
+ writel(0x00002096, &qos_addr->dbtmval0);
+ writel(0x00002064, &qos_addr->dbtmval1);
+ writel(0x00002050, &qos_addr->dbtmval2);
+ writel(0x0000203A, &qos_addr->dbtmval3);
+ writel(0x00000001, &qos_addr->dbrqctr);
+ writel(0x00002078, &qos_addr->dbthres0);
+ writel(0x0000204B, &qos_addr->dbthres1);
+ writel(0x0000203C, &qos_addr->dbthres2);
+ writel(0x00000001, &qos_addr->dblgqon);
+ }
+
+ /* MXI -QoS */
+ /* Transaction Control (MXI) */
+ mxi = (struct rcar_mxi *)MXI_BASE;
+ writel(0x00000013, &mxi->mxrtcr);
+ writel(0x00000013, &mxi->mxwtcr);
+ writel(0x00B800C0, &mxi->mxsaar0);
+ writel(0x02000800, &mxi->mxsaar1);
+
+ /* QoS Control (MXI) */
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+ writel(0x0000000C, &mxi_qos->vspdu0);
+ writel(0x0000000C, &mxi_qos->vspdu1);
+ writel(0x0000000E, &mxi_qos->du0);
+ writel(0x0000000E, &mxi_qos->du1);
+
+ /* AXI -QoS */
+ /* Transaction Control (MXI) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002037, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002021, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000214C, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x000020A6, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (RT-AXI) */
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002299, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002029, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (MP-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002037, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002014, &axi_qos->qosctset0);
+ writel(0x00000040, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x00002053, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+ writel(0x00000000, &axi_qos->qosconf);
+ writel(0x0000206E, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (SYS-AXI256) */
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020EB, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (CCI-AXI) */
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x00002245, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002004, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ /* QoS Register (Media-AXI) */
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020dc, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+ writel(0x00000002, &axi_qos->qosconf);
+ writel(0x000020dc, &axi_qos->qosctset0);
+ writel(0x00002096, &axi_qos->qosctset1);
+ writel(0x00002030, &axi_qos->qosctset2);
+ writel(0x00002030, &axi_qos->qosctset3);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x000020AA, &axi_qos->qosthres0);
+ writel(0x00002032, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00002001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE;
+ writel(0x00000003, &axi_qos->qosconf);
+ writel(0x00002063, &axi_qos->qosctset0);
+ writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002004, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+}
+
+void qos_init(void)
+{
+ if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X)
+ qos_init_es2();
+ else
+ qos_init_es1();
+}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/lager/qos.h b/board/renesas/lager/qos.h
new file mode 100644
index 0000000..9a6c046
--- /dev/null
+++ b/board/renesas/lager/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/board/renesas/r0p7734/Kconfig b/board/renesas/r0p7734/Kconfig
new file mode 100644
index 0000000..7f24f41
--- /dev/null
+++ b/board/renesas/r0p7734/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_R0P7734
+
+config SYS_BOARD
+ default "r0p7734"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "r0p7734"
+
+endif
diff --git a/board/renesas/r0p7734/MAINTAINERS b/board/renesas/r0p7734/MAINTAINERS
new file mode 100644
index 0000000..c169ad7
--- /dev/null
+++ b/board/renesas/r0p7734/MAINTAINERS
@@ -0,0 +1,7 @@
+R0P7734 BOARD
+M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S: Maintained
+F: board/renesas/r0p7734/
+F: include/configs/r0p7734.h
+F: configs/r0p7734_defconfig
diff --git a/board/renesas/r0p7734/Makefile b/board/renesas/r0p7734/Makefile
new file mode 100644
index 0000000..1f24d92
--- /dev/null
+++ b/board/renesas/r0p7734/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := r0p7734.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/r0p7734/lowlevel_init.S b/board/renesas/r0p7734/lowlevel_init.S
new file mode 100644
index 0000000..62668a7
--- /dev/null
+++ b/board/renesas/r0p7734/lowlevel_init.S
@@ -0,0 +1,593 @@
+/*
+ * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+#include <asm/processor.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ /* WDT */
+ write32 WDTCSR_A, WDTCSR_D
+
+ /* MMU */
+ write32 MMUCR_A, MMUCR_D
+
+ write32 FRQCR2_A, FRQCR2_D
+ write32 FRQCR0_A, FRQCR0_D
+
+ write32 CS0CTRL_A, CS0CTRL_D
+ write32 CS1CTRL_A, CS1CTRL_D
+ write32 CS0CTRL2_A, CS0CTRL2_D
+
+ write32 CSPWCR0_A, CSPWCR0_D
+ write32 CSPWCR1_A, CSPWCR1_D
+ write32 CS1GDST_A, CS1GDST_D
+
+ # clock mode check
+ mov.l MODEMR, r1
+ mov.l @r1, r0
+ and #6, r0 /* Check 1 and 2 bit.*/
+ cmp/eq #2, r0 /* 0x02 is 533Mhz mode */
+ bt init_lbsc_533
+
+init_lbsc_400:
+
+ write32 CSWCR0_A, CSWCR0_D_400
+ write32 CSWCR1_A, CSWCR1_D
+
+ bra init_dbsc3_400_pad
+ nop
+
+ .align 2
+
+MODEMR: .long 0xFFCC0020
+WDTCSR_A: .long 0xFFCC0004
+WDTCSR_D: .long 0xA5000000
+MMUCR_A: .long 0xFF000010
+MMUCR_D: .long 0x00000004
+
+FRQCR2_A: .long 0xFFC80008
+FRQCR2_D: .long 0x00000000
+FRQCR0_A: .long 0xFFC80000
+FRQCR0_D: .long 0xCF000001
+
+CS0CTRL_A: .long 0xFF800200
+CS0CTRL_D: .long 0x00000020
+CS1CTRL_A: .long 0xFF800204
+CS1CTRL_D: .long 0x00000020
+
+CS0CTRL2_A: .long 0xFF800220
+CS0CTRL2_D: .long 0x00004000
+
+CSPWCR0_A: .long 0xFF800280
+CSPWCR0_D: .long 0x00000000
+CSPWCR1_A: .long 0xFF800284
+CSPWCR1_D: .long 0x00000000
+CS1GDST_A: .long 0xFF8002C0
+CS1GDST_D: .long 0x00000011
+
+init_lbsc_533:
+
+ write32 CSWCR0_A, CSWCR0_D_533
+ write32 CSWCR1_A, CSWCR1_D
+
+ bra init_dbsc3_533_pad
+ nop
+
+ .align 2
+
+CSWCR0_A: .long 0xFF800230
+CSWCR0_D_533: .long 0x01120104
+CSWCR0_D_400: .long 0x02120114
+/* CSWCR0_D_400: .long 0x01160116 */
+CSWCR1_A: .long 0xFF800234
+CSWCR1_D: .long 0x077F077F
+/* CSWCR1_D_400: .long 0x00120012 */
+
+init_dbsc3_400_pad:
+
+ write32 DBPDCNT3_A, DBPDCNT3_D
+ wait_timer WAIT_200US_400
+
+ write32 DBPDCNT0_A, DBPDCNT0_D_400
+ write32 DBPDCNT3_A, DBPDCNT3_D0
+ write32 DBPDCNT1_A, DBPDCNT1_D
+
+ write32 DBPDCNT3_A, DBPDCNT3_D1
+ wait_timer WAIT_32MCLK
+
+ write32 DBPDCNT3_A, DBPDCNT3_D2
+ wait_timer WAIT_100US_400
+
+ write32 DBPDCNT3_A, DBPDCNT3_D3
+ wait_timer WAIT_16MCLK
+
+ write32 DBPDCNT3_A, DBPDCNT3_D4
+ wait_timer WAIT_200US_400
+
+ write32 DBPDCNT3_A, DBPDCNT3_D5
+ wait_timer WAIT_1MCLK
+
+ write32 DBPDCNT3_A, DBPDCNT3_D6
+ wait_timer WAIT_10KMCLK
+
+ bra init_dbsc3_ctrl_400
+ nop
+
+ .align 2
+
+init_dbsc3_533_pad:
+
+ write32 DBPDCNT3_A, DBPDCNT3_D
+ wait_timer WAIT_200US_533
+
+ write32 DBPDCNT0_A, DBPDCNT0_D_533
+ write32 DBPDCNT3_A, DBPDCNT3_D0
+ write32 DBPDCNT1_A, DBPDCNT1_D
+
+ write32 DBPDCNT3_A, DBPDCNT3_D1
+ wait_timer WAIT_32MCLK
+
+ write32 DBPDCNT3_A, DBPDCNT3_D2
+ wait_timer WAIT_100US_533
+
+ write32 DBPDCNT3_A, DBPDCNT3_D3
+ wait_timer WAIT_16MCLK
+
+ write32 DBPDCNT3_A, DBPDCNT3_D4
+ wait_timer WAIT_200US_533
+
+ write32 DBPDCNT3_A, DBPDCNT3_D5
+ wait_timer WAIT_1MCLK
+
+ write32 DBPDCNT3_A, DBPDCNT3_D6
+ wait_timer WAIT_10KMCLK
+
+ bra init_dbsc3_ctrl_533
+ nop
+
+ .align 2
+
+WAIT_200US_400: .long 40000
+WAIT_200US_533: .long 53300
+WAIT_100US_400: .long 20000
+WAIT_100US_533: .long 26650
+WAIT_32MCLK: .long 32
+WAIT_16MCLK: .long 16
+WAIT_1MCLK: .long 1
+WAIT_10KMCLK: .long 10000
+
+DBPDCNT0_A: .long 0xFE800200
+DBPDCNT0_D_533: .long 0x00010245
+DBPDCNT0_D_400: .long 0x00010235
+DBPDCNT1_A: .long 0xFE800204
+DBPDCNT1_D: .long 0x00000014
+DBPDCNT3_A: .long 0xFE80020C
+DBPDCNT3_D: .long 0x80000000
+DBPDCNT3_D0: .long 0x800F0000
+DBPDCNT3_D1: .long 0x800F1000
+DBPDCNT3_D2: .long 0x820F1000
+DBPDCNT3_D3: .long 0x860F1000
+DBPDCNT3_D4: .long 0x870F1000
+DBPDCNT3_D5: .long 0x870F3000
+DBPDCNT3_D6: .long 0x870F7000
+
+init_dbsc3_ctrl_400:
+
+ write32 DBKIND_A, DBKIND_D
+ write32 DBCONF_A, DBCONF_D
+
+ write32 DBTR0_A, DBTR0_D_400
+ write32 DBTR1_A, DBTR1_D_400
+ write32 DBTR2_A, DBTR2_D
+ write32 DBTR3_A, DBTR3_D_400
+ write32 DBTR4_A, DBTR4_D_400
+ write32 DBTR5_A, DBTR5_D_400
+ write32 DBTR6_A, DBTR6_D_400
+ write32 DBTR7_A, DBTR7_D
+ write32 DBTR8_A, DBTR8_D_400
+ write32 DBTR9_A, DBTR9_D
+ write32 DBTR10_A, DBTR10_D_400
+ write32 DBTR11_A, DBTR11_D
+ write32 DBTR12_A, DBTR12_D_400
+ write32 DBTR13_A, DBTR13_D_400
+ write32 DBTR14_A, DBTR14_D
+ write32 DBTR15_A, DBTR15_D
+ write32 DBTR16_A, DBTR16_D_400
+ write32 DBTR17_A, DBTR17_D_400
+ write32 DBTR18_A, DBTR18_D_400
+
+ write32 DBBL_A, DBBL_D
+ write32 DBRNK0_A, DBRNK0_D
+
+ write32 DBCMD_A, DBCMD_D0_400
+ write32 DBCMD_A, DBCMD_D1
+ write32 DBCMD_A, DBCMD_D2
+ write32 DBCMD_A, DBCMD_D3
+ write32 DBCMD_A, DBCMD_D4
+ write32 DBCMD_A, DBCMD_D5_400
+ write32 DBCMD_A, DBCMD_D6
+ write32 DBCMD_A, DBCMD_D7
+ write32 DBCMD_A, DBCMD_D8
+ write32 DBCMD_A, DBCMD_D9_400
+ write32 DBCMD_A, DBCMD_D10
+ write32 DBCMD_A, DBCMD_D11
+ write32 DBCMD_A, DBCMD_D12
+
+ write32 DBBS0CNT1_A, DBBS0CNT1_D
+ write32 DBPDNCNF_A, DBPDNCNF_D
+
+ write32 DBRFCNF0_A, DBRFCNF0_D
+ write32 DBRFCNF1_A, DBRFCNF1_D_400
+ write32 DBRFCNF2_A, DBRFCNF2_D
+ write32 DBRFEN_A, DBRFEN_D
+ write32 DBACEN_A, DBACEN_D
+ write32 DBACEN_A, DBACEN_D
+
+ /* Dummy read */
+ mov.l DBWAIT_A, r1
+ synco
+ mov.l @r1, r0
+ synco
+
+ /* Dummy read */
+ mov.l SDRAM_A, r1
+ synco
+ mov.l @r1, r0
+ synco
+
+ /* need sleep 186A0 */
+
+ bra init_pfc_sh7734
+ nop
+
+ .align 2
+
+init_dbsc3_ctrl_533:
+
+ write32 DBKIND_A, DBKIND_D
+ write32 DBCONF_A, DBCONF_D
+
+ write32 DBTR0_A, DBTR0_D_533
+ write32 DBTR1_A, DBTR1_D_533
+ write32 DBTR2_A, DBTR2_D
+ write32 DBTR3_A, DBTR3_D_533
+ write32 DBTR4_A, DBTR4_D_533
+ write32 DBTR5_A, DBTR5_D_533
+ write32 DBTR6_A, DBTR6_D_533
+ write32 DBTR7_A, DBTR7_D
+ write32 DBTR8_A, DBTR8_D_533
+ write32 DBTR9_A, DBTR9_D
+ write32 DBTR10_A, DBTR10_D_533
+ write32 DBTR11_A, DBTR11_D
+ write32 DBTR12_A, DBTR12_D_533
+ write32 DBTR13_A, DBTR13_D_533
+ write32 DBTR14_A, DBTR14_D
+ write32 DBTR15_A, DBTR15_D
+ write32 DBTR16_A, DBTR16_D_533
+ write32 DBTR17_A, DBTR17_D_533
+ write32 DBTR18_A, DBTR18_D_533
+
+ write32 DBBL_A, DBBL_D
+ write32 DBRNK0_A, DBRNK0_D
+
+ write32 DBCMD_A, DBCMD_D0_533
+ write32 DBCMD_A, DBCMD_D1
+ write32 DBCMD_A, DBCMD_D2
+ write32 DBCMD_A, DBCMD_D3
+ write32 DBCMD_A, DBCMD_D4
+ write32 DBCMD_A, DBCMD_D5_533
+ write32 DBCMD_A, DBCMD_D6
+ write32 DBCMD_A, DBCMD_D7
+ write32 DBCMD_A, DBCMD_D8
+ write32 DBCMD_A, DBCMD_D9_533
+ write32 DBCMD_A, DBCMD_D10
+ write32 DBCMD_A, DBCMD_D11
+ write32 DBCMD_A, DBCMD_D12
+
+ write32 DBBS0CNT1_A, DBBS0CNT1_D
+ write32 DBPDNCNF_A, DBPDNCNF_D
+
+ write32 DBRFCNF0_A, DBRFCNF0_D
+ write32 DBRFCNF1_A, DBRFCNF1_D_533
+ write32 DBRFCNF2_A, DBRFCNF2_D
+ write32 DBRFEN_A, DBRFEN_D
+ write32 DBACEN_A, DBACEN_D
+ write32 DBACEN_A, DBACEN_D
+
+ /* Dummy read */
+ mov.l DBWAIT_A, r1
+ synco
+ mov.l @r1, r0
+ synco
+
+ /* Dummy read */
+ mov.l SDRAM_A, r1
+ synco
+ mov.l @r1, r0
+ synco
+
+ /* need sleep 186A0 */
+
+ bra init_pfc_sh7734
+ nop
+
+ .align 2
+
+DBKIND_A: .long 0xFE800020
+DBKIND_D: .long 0x00000005
+DBCONF_A: .long 0xFE800024
+DBCONF_D: .long 0x0D030A01
+
+DBTR0_A: .long 0xFE800040
+DBTR0_D_533:.long 0x00000004
+DBTR0_D_400:.long 0x00000003
+DBTR1_A: .long 0xFE800044
+DBTR1_D_533:.long 0x00000003
+DBTR1_D_400:.long 0x00000002
+DBTR2_A: .long 0xFE800048
+DBTR2_D: .long 0x00000000
+DBTR3_A: .long 0xFE800050
+DBTR3_D_533:.long 0x00000004
+DBTR3_D_400:.long 0x00000003
+
+DBTR4_A: .long 0xFE800054
+DBTR4_D_533:.long 0x00050004
+DBTR4_D_400:.long 0x00050003
+
+DBTR5_A: .long 0xFE800058
+DBTR5_D_533:.long 0x0000000F
+DBTR5_D_400:.long 0x0000000B
+
+DBTR6_A: .long 0xFE80005C
+DBTR6_D_533:.long 0x0000000B
+DBTR6_D_400:.long 0x00000008
+
+DBTR7_A: .long 0xFE800060
+DBTR7_D: .long 0x00000002 /* common value */
+
+DBTR8_A: .long 0xFE800064
+DBTR8_D_533:.long 0x0000000D
+DBTR8_D_400:.long 0x0000000A
+
+DBTR9_A: .long 0xFE800068
+DBTR9_D: .long 0x00000002 /* common value */
+
+DBTR10_A: .long 0xFE80006C
+DBTR10_D_533:.long 0x00000004
+DBTR10_D_400:.long 0x00000003
+
+DBTR11_A: .long 0xFE800070
+DBTR11_D: .long 0x00000008 /* common value */
+
+DBTR12_A: .long 0xFE800074
+DBTR12_D_533:.long 0x00000009
+DBTR12_D_400:.long 0x00000008
+
+DBTR13_A: .long 0xFE800078
+DBTR13_D_533:.long 0x00000022
+DBTR13_D_400:.long 0x0000001A
+
+DBTR14_A: .long 0xFE80007C
+DBTR14_D: .long 0x00070002 /* common value */
+
+DBTR15_A: .long 0xFE800080
+DBTR15_D: .long 0x00000003 /* common value */
+
+DBTR16_A: .long 0xFE800084
+DBTR16_D_533:.long 0x120A1001
+DBTR16_D_400:.long 0x12091001
+
+DBTR17_A: .long 0xFE800088
+DBTR17_D_533:.long 0x00040000
+DBTR17_D_400:.long 0x00030000
+
+DBTR18_A: .long 0xFE80008C
+DBTR18_D_533:.long 0x02010200
+DBTR18_D_400:.long 0x02000207
+
+DBBL_A: .long 0xFE8000B0
+DBBL_D: .long 0x00000000
+
+DBRNK0_A: .long 0xFE800100
+DBRNK0_D: .long 0x00000001
+
+DBCMD_A: .long 0xFE800018
+DBCMD_D0_533: .long 0x1100006B
+DBCMD_D0_400: .long 0x11000050
+DBCMD_D1: .long 0x0B000000 /* common value */
+DBCMD_D2: .long 0x2A004000 /* common value */
+DBCMD_D3: .long 0x2B006000 /* common value */
+DBCMD_D4: .long 0x29002004 /* common value */
+DBCMD_D5_533: .long 0x28000743
+DBCMD_D5_400: .long 0x28000533
+DBCMD_D6: .long 0x0B000000 /* common value */
+DBCMD_D7: .long 0x0C000000 /* common value */
+DBCMD_D8: .long 0x0C000000 /* common value */
+DBCMD_D9_533: .long 0x28000643
+DBCMD_D9_400: .long 0x28000433
+DBCMD_D10: .long 0x000000C8 /* common value */
+DBCMD_D11: .long 0x29002384 /* common value */
+DBCMD_D12: .long 0x29002004 /* common value */
+
+DBBS0CNT1_A: .long 0xFE800304
+DBBS0CNT1_D: .long 0x00000000
+DBPDNCNF_A: .long 0xFE800180
+DBPDNCNF_D: .long 0x00000200
+
+DBRFCNF0_A: .long 0xFE8000E0
+DBRFCNF0_D: .long 0x000001FF
+DBRFCNF1_A: .long 0xFE8000E4
+DBRFCNF1_D_533: .long 0x00000805
+DBRFCNF1_D_400: .long 0x00000618
+
+DBRFCNF2_A: .long 0xFE8000E8
+DBRFCNF2_D: .long 0x00000000
+
+DBRFEN_A: .long 0xFE800014
+DBRFEN_D: .long 0x00000001
+
+DBACEN_A: .long 0xFE800010
+DBACEN_D: .long 0x00000001
+
+DBWAIT_A: .long 0xFE80001C
+SDRAM_A: .long 0x0C000000
+
+init_pfc_sh7734:
+ write32 PFC_PMMR_A, PFC_PMMR_MODESEL1
+ write32 PFC_MODESEL1_A, PFC_MODESEL1_D
+
+ write32 PFC_PMMR_A, PFC_PMMR_MODESEL2
+ write32 PFC_MODESEL2_A, PFC_MODESEL2_D
+
+ write32 PFC_PMMR_A, PFC_PMMR_IPSR3
+ write32 PFC_IPSR3_A, PFC_IPSR3_D
+
+ write32 PFC_PMMR_A, PFC_PMMR_IPSR4
+ write32 PFC_IPSR4_A, PFC_IPSR4_D
+
+ write32 PFC_PMMR_A, PFC_PMMR_IPSR11
+ write32 PFC_IPSR11_A, PFC_IPSR11_D
+
+ write32 PFC_PMMR_A, PFC_PMMR_GPSR0
+ write32 PFC_GPSR0_A, PFC_GPSR0_D
+
+ write32 PFC_PMMR_A, PFC_PMMR_GPSR1
+ write32 PFC_GPSR1_A, PFC_GPSR1_D
+
+ write32 PFC_PMMR_A, PFC_PMMR_GPSR2
+ write32 PFC_GPSR2_A, PFC_GPSR2_D
+
+ write32 PFC_PMMR_A, PFC_PMMR_GPSR3
+ write32 PFC_GPSR3_A, PFC_GPSR3_D
+
+ write32 PFC_PMMR_A, PFC_PMMR_GPSR4
+ write32 PFC_GPSR4_A, PFC_GPSR4_D
+
+ write32 PFC_PMMR_A, PFC_PMMR_GPSR5
+ write32 PFC_GPSR5_A, PFC_GPSR5_D
+
+ /* sleep 186A0 */
+
+ write32 GPIO2_INOUTSEL1_A, GPIO2_INOUTSEL1_D
+ write32 GPIO1_OUTDT1_A, GPIO1_OUTDT1_D
+ write32 GPIO2_INOUTSEL2_A, GPIO2_INOUTSEL2_D
+ write32 GPIO2_OUTDT2_A, GPIO2_OUTDT2_D
+ write32 GPIO4_INOUTSEL4_A, GPIO4_INOUTSEL4_D
+ write32 GPIO4_OUTDT4_A, GPIO4_OUTDT4_D
+
+ write32 CCR_A, CCR_D
+
+ stc sr, r0
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+ nop
+
+ .align 2
+
+PFC_PMMR_A: .long 0xFFFC0000
+
+/* MODESEL
+ * 28: Select IEBUS Group B
+ */
+PFC_MODESEL1_A: .long 0xFFFC004C
+PFC_MODESEL1_D: .long 0x10000000
+PFC_PMMR_MODESEL1: .long 0xEFFFFFFF
+
+/* MODESEL
+ * 9: Select SCIF3 Group B
+ * 7: Select SCIF2 Group B
+ * 4: Select SCIF1 Group B
+ */
+PFC_MODESEL2_A: .long 0xFFFC0050
+PFC_MODESEL2_D: .long 0x00000290
+PFC_PMMR_MODESEL2: .long 0xFFFFFD6F
+
+# Enable functios
+# SD1_DAT2_A SD1_DAT1_A, SD1_DAT0_A,
+# EXWAIT0, RDW/RW, SD1_CMD_A, SD1_WP_A,
+# SD1_CD_A, TX3_B, RX3_B, CS1, D15
+PFC_IPSR3_A: .long 0xFFFC0028
+PFC_IPSR3_D: .long 0x09209248
+PFC_PMMR_IPSR3: .long 0xF6DF6DB7
+
+# Enable functios
+# RMII0_MDIO_A , RMII0_MDC_A,
+# RMII0_CRS_DV_A, RMII0_RX_ER_A,
+# RMII0_TXD_EN_A, MII0_RXD1_A
+PFC_IPSR4_A: .long 0xFFFC002C
+PFC_IPSR4_D: .long 0x0001B6DB
+PFC_PMMR_IPSR4: .long 0xFFFE4924
+
+# Enable functios
+# DACK1, DREQ1, SD1_DAT3_A, SD1_CLK_A, IERX_B,
+# IETX_B, TX0_A, RMII0_TXD0_A,
+# RMII0_TXD1_A, RMII0_TXD0_A, SDSEL, SDA0, SDA1, SCL1
+PFC_IPSR11_A: .long 0xFFFC0048
+PFC_IPSR11_D: .long 0x002C89B0
+PFC_PMMR_IPSR11:.long 0xFFD3764F
+
+PFC_GPSR0_A: .long 0xFFFC0004
+PFC_GPSR0_D: .long 0xFFFFFFFF
+PFC_PMMR_GPSR0: .long 0x00000000
+
+PFC_GPSR1_A: .long 0xFFFC0008
+PFC_GPSR1_D: .long 0x7FBF7FFF
+PFC_PMMR_GPSR1: .long 0x80408000
+
+PFC_GPSR2_A: .long 0xFFFC000C
+PFC_GPSR2_D: .long 0xBFC07EDF
+PFC_PMMR_GPSR2: .long 0x403F8120
+
+PFC_GPSR3_A: .long 0xFFFC0010
+PFC_GPSR3_D: .long 0xFFFFFFFF
+PFC_PMMR_GPSR3: .long 0x00000000
+
+PFC_GPSR4_A: .long 0xFFFC0014
+#if 0 /* orig */
+PFC_GPSR4_D: .long 0xFFFFFFFF
+PFC_PMMR_GPSR4: .long 0x00000000
+#else
+PFC_GPSR4_D: .long 0xFBFFFFFF
+PFC_PMMR_GPSR4: .long 0x04000000
+#endif
+
+PFC_GPSR5_A: .long 0xFFFC0018
+PFC_GPSR5_D: .long 0x00000C01
+PFC_PMMR_GPSR5: .long 0xFFFFF3FE
+
+I2C_ICCR2_A: .long 0xFFC70001
+I2C_ICCR2_D: .long 0x00
+I2C_ICCR2_D1: .long 0x20
+
+GPIO2_INOUTSEL1_A: .long 0xFFC41004
+GPIO2_INOUTSEL1_D: .long 0x80408000
+GPIO1_OUTDT1_A: .long 0xFFC41008 /* bit15: LED4, bit22: LED5 */
+GPIO1_OUTDT1_D: .long 0x80408000
+GPIO2_INOUTSEL2_A: .long 0xFFC42004
+GPIO2_INOUTSEL2_D: .long 0x40000120
+GPIO2_OUTDT2_A: .long 0xFFC42008
+GPIO2_OUTDT2_D: .long 0x40000120
+GPIO4_INOUTSEL4_A: .long 0xFFC44004
+GPIO4_INOUTSEL4_D: .long 0x04000000
+GPIO4_OUTDT4_A: .long 0xFFC44008
+GPIO4_OUTDT4_D: .long 0x04000000
+
+CCR_A: .long 0xFF00001C
+CCR_D: .long 0x0000090B
+SR_MASK_D: .long 0xEFFFFF0F
diff --git a/board/renesas/r0p7734/r0p7734.c b/board/renesas/r0p7734/r0p7734.c
new file mode 100644
index 0000000..5687ad4
--- /dev/null
+++ b/board/renesas/r0p7734/r0p7734.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <netdev.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MODEMR (0xFFCC0020)
+#define MODEMR_MASK (0x6)
+#define MODEMR_533MHZ (0x2)
+
+int checkboard(void)
+{
+ u32 r = readl(MODEMR);
+ if ((r & MODEMR_MASK) & MODEMR_533MHZ)
+ puts("CPU Clock: 533MHz\n");
+ else
+ puts("CPU Clock: 400MHz\n");
+
+ puts("BOARD: Renesas Technology Corp. R0P7734C00000RZ\n");
+ return 0;
+}
+
+#define MSTPSR1 (0xFFC80044)
+#define MSTPCR1 (0xFFC80034)
+#define MSTPSR1_GETHER (1 << 14)
+
+int board_init(void)
+{
+#if defined(CONFIG_SH_ETHER)
+ u32 r = readl(MSTPSR1);
+ if (r & MSTPSR1_GETHER)
+ writel((r & ~MSTPSR1_GETHER), MSTPCR1);
+#endif
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ u8 mac[6];
+
+ /* Read Mac Address and set*/
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
+
+ /* Read MAC address */
+ i2c_read(0x50, 0x10, 0, mac, 6);
+
+ if (is_valid_ether_addr(mac))
+ eth_setenv_enetaddr("ethaddr", mac);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+
+ return 0;
+}
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ return rc;
+}
+#endif
diff --git a/board/renesas/r2dplus/Kconfig b/board/renesas/r2dplus/Kconfig
new file mode 100644
index 0000000..6597870
--- /dev/null
+++ b/board/renesas/r2dplus/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_R2DPLUS
+
+config SYS_BOARD
+ default "r2dplus"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "r2dplus"
+
+endif
diff --git a/board/renesas/r2dplus/MAINTAINERS b/board/renesas/r2dplus/MAINTAINERS
new file mode 100644
index 0000000..58877c5
--- /dev/null
+++ b/board/renesas/r2dplus/MAINTAINERS
@@ -0,0 +1,7 @@
+R2DPLUS BOARD
+M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S: Maintained
+F: board/renesas/r2dplus/
+F: include/configs/r2dplus.h
+F: configs/r2dplus_defconfig
diff --git a/board/renesas/r2dplus/Makefile b/board/renesas/r2dplus/Makefile
new file mode 100644
index 0000000..acffb6d
--- /dev/null
+++ b/board/renesas/r2dplus/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007,2008
+# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := r2dplus.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S
new file mode 100644
index 0000000..f3392f0
--- /dev/null
+++ b/board/renesas/r2dplus/lowlevel_init.S
@@ -0,0 +1,118 @@
+/*
+ * modified from SH-IPL+g (init-r0p751rlc0011rl.S)
+ * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
+ * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+*/
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+ .global lowlevel_init
+ .text
+ .align 2
+
+lowlevel_init:
+
+ write32 CCR_A, CCR_D_D
+
+ write32 MMUCR_A, MMUCR_D
+
+ write32 BCR1_A, BCR1_D
+
+ write16 BCR2_A, BCR2_D
+
+ write16 BCR3_A, BCR3_D
+
+ write32 BCR4_A, BCR4_D
+
+ write32 WCR1_A, WCR1_D
+
+ write32 WCR2_A, WCR2_D
+
+ write32 WCR3_A, WCR3_D
+
+ write16 PCR_A, PCR_D
+
+ write16 LED_A, LED_D
+
+ write32 MCR_A, MCR_D1
+
+ write16 RTCNT_A, RTCNT_D
+
+ write16 RTCOR_A, RTCOR_D
+
+ write16 RFCR_A, RFCR_D
+
+ write16 RTCSR_A, RTCSR_D
+
+ write8 SDMR3_A, SDMR3_D0
+
+ /* Wait DRAM refresh 30 times */
+ mov.l RFCR_A, r1
+ mov #30, r3
+1:
+ mov.w @r1, r0
+ extu.w r0, r2
+ cmp/hi r3, r2
+ bf 1b
+
+ write32 MCR_A, MCR_D2
+
+ write8 SDMR3_A, SDMR3_D1
+
+ write32 IRLMASK_A, IRLMASK_D
+
+ write32 CCR_A, CCR_D_E
+
+ rts
+ nop
+
+ .align 2
+CCR_A: .long CCR /* Cache Control Register */
+CCR_D_D: .long 0x0808 /* Flush the cache, disable */
+CCR_D_E: .long 0x8000090B
+
+FRQCR_A: .long FRQCR /* FRQCR Address */
+FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */
+BCR1_A: .long BCR1 /* BCR1 Address */
+BCR1_D: .long 0x00180008
+BCR2_A: .long BCR2 /* BCR2 Address */
+BCR2_D: .long 0xabe8
+BCR3_A: .long BCR3 /* BCR3 Address */
+BCR3_D: .long 0x0000
+BCR4_A: .long BCR4 /* BCR4 Address */
+BCR4_D: .long 0x00000010
+WCR1_A: .long WCR1 /* WCR1 Address */
+WCR1_D: .long 0x33343333
+WCR2_A: .long WCR2 /* WCR2 Address */
+WCR2_D: .long 0xcff86fbf
+WCR3_A: .long WCR3 /* WCR3 Address */
+WCR3_D: .long 0x07777707
+LED_A: .long 0x04000036 /* LED Address */
+LED_D: .long 0xFF /* LED Data */
+RTCNT_A: .long RTCNT /* RTCNT Address */
+RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
+.align 2
+RTCOR_A: .long RTCOR /* RTCOR Address */
+RTCOR_D: .word 0xA534 /* RTCOR Write Code */
+.align 2
+RTCSR_A: .long RTCSR /* RTCSR Address */
+RTCSR_D: .word 0xA510 /* RTCSR Write Code */
+.align 2
+SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */
+SDMR3_D0: .long 0x55
+SDMR3_D1: .long 0x00
+MCR_A: .long MCR /* MCR Address */
+MCR_D1: .long 0x081901F4 /* MRSET:'0' */
+MCR_D2: .long 0x481901F4 /* MRSET:'1' */
+RFCR_A: .long RFCR /* RFCR Address */
+RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
+PCR_A: .long PCR /* PCR Address */
+PCR_D: .long 0x0000
+MMUCR_A: .long MMUCR /* MMUCCR Address */
+MMUCR_D: .long 0x00000000 /* MMUCCR Data */
+IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */
+IRLMASK_D: .long 0x00000000 /* IRLMASK Data */
diff --git a/board/renesas/r2dplus/r2dplus.c b/board/renesas/r2dplus/r2dplus.c
new file mode 100644
index 0000000..249c35f
--- /dev/null
+++ b/board/renesas/r2dplus/r2dplus.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2007,2008
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas Solutions R2D Plus\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+#define FPGA_BASE 0xA4000000
+#define FPGA_CFCTL (FPGA_BASE + 0x04)
+#define CFCTL_EN (0x432)
+#define FPGA_CFPOW (FPGA_BASE + 0x06)
+#define CFPOW_ON (0x02)
+#define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
+#define CFCDINTCLR_EN (0x01)
+
+void ide_set_reset(int idereset)
+{
+ /* if reset = 1 IDE reset will be asserted */
+ if (idereset) {
+ outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */
+ outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
+ outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
+ }
+}
+
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+ pci_sh7751_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
diff --git a/board/renesas/r7780mp/Kconfig b/board/renesas/r7780mp/Kconfig
new file mode 100644
index 0000000..050cc4c
--- /dev/null
+++ b/board/renesas/r7780mp/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_R7780MP
+
+config SYS_BOARD
+ default "r7780mp"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "r7780mp"
+
+endif
diff --git a/board/renesas/r7780mp/MAINTAINERS b/board/renesas/r7780mp/MAINTAINERS
new file mode 100644
index 0000000..56ec21f
--- /dev/null
+++ b/board/renesas/r7780mp/MAINTAINERS
@@ -0,0 +1,7 @@
+R7780MP BOARD
+M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S: Maintained
+F: board/renesas/r7780mp/
+F: include/configs/r7780mp.h
+F: configs/r7780mp_defconfig
diff --git a/board/renesas/r7780mp/Makefile b/board/renesas/r7780mp/Makefile
new file mode 100644
index 0000000..8dab435
--- /dev/null
+++ b/board/renesas/r7780mp/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+#
+# board/r7780mp/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := r7780mp.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/r7780mp/lowlevel_init.S b/board/renesas/r7780mp/lowlevel_init.S
new file mode 100644
index 0000000..471af1d
--- /dev/null
+++ b/board/renesas/r7780mp/lowlevel_init.S
@@ -0,0 +1,358 @@
+/*
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+ *
+ * u-boot/board/r7780mp/lowlevel_init.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+/*
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
+ *
+ * (Note: As no stack is available, no subroutines can be called...).
+ */
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ write32 CCR_A, CCR_D /* Address of Cache Control Register */
+ /* Instruction Cache Invalidate */
+
+ write32 FRQCR_A, FRQCR_D /* Frequency control register */
+
+ /* pin_multi_setting */
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
+
+ write32 BBG_PMSR1_A, BBG_PMSR1_D
+
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
+
+ write32 BBG_PMSR2_A, BBG_PMSR2_D
+
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
+
+ write32 BBG_PMSR3_A, BBG_PMSR3_D
+
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
+
+ write32 BBG_PMSR4_A, BBG_PMSR4_D
+
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
+
+ write32 BBG_PMSRG_A, BBG_PMSRG_D
+
+ /* cpg_setting */
+ write32 FRQCR_A, FRQCR_D
+
+ write32 DLLCSR_A, DLLCSR_D
+
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /* wait 200us */
+ mov.l REPEAT0_R3, r3
+ mov #0, r2
+repeat0:
+ add #1, r2
+ cmp/hs r3, r2
+ bf repeat0
+ nop
+
+ /* bsc_setting */
+ write32 MMSELR_A, MMSELR_D
+
+ write32 BCR_A, BCR_D
+
+ write32 CS0BCR_A, CS0BCR_D
+
+ write32 CS1BCR_A, CS1BCR_D
+
+ write32 CS2BCR_A, CS2BCR_D
+
+ write32 CS4BCR_A, CS4BCR_D
+
+ write32 CS5BCR_A, CS5BCR_D
+
+ write32 CS6BCR_A, CS6BCR_D
+
+ write32 CS0WCR_A, CS0WCR_D
+
+ write32 CS1WCR_A, CS1WCR_D
+
+ write32 CS2WCR_A, CS2WCR_D
+
+ write32 CS4WCR_A, CS4WCR_D
+
+ write32 CS5WCR_A, CS5WCR_D
+
+ write32 CS6WCR_A, CS6WCR_D
+
+ write32 CS5PCR_A, CS5PCR_D
+
+ write32 CS6PCR_A, CS6PCR_D
+
+ /* ddr_setting */
+ /* wait 200us */
+ mov.l REPEAT0_R3, r3
+ mov #0, r2
+repeat1:
+ add #1, r2
+ cmp/hs r3, r2
+ bf repeat1
+ nop
+
+ mov.l MIM_U_A, r0
+ mov.l MIM_U_D, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ mov.l MIM_L_A, r0
+ mov.l MIM_L_D0, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ mov.l STR_L_A, r0
+ mov.l STR_L_D, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ mov.l SDR_L_A, r0
+ mov.l SDR_L_D, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ nop
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A, r0
+ mov.l SCR_L_D0, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ mov.l SCR_L_A, r0
+ mov.l SCR_L_D1, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l EMRS_A, r0
+ mov.l EMRS_D, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l MRS1_A, r0
+ mov.l MRS1_D, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A, r0
+ mov.l SCR_L_D2, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A, r0
+ mov.l SCR_L_D3, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A, r0
+ mov.l SCR_L_D4, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l MRS2_A, r0
+ mov.l MRS2_D, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ nop
+ nop
+ nop
+
+ mov.l SCR_L_A, r0
+ mov.l SCR_L_D5, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ /* wait 200us */
+ mov.l REPEAT0_R1, r3
+ mov #0, r2
+repeat2:
+ add #1, r2
+ cmp/hs r3, r2
+ bf repeat2
+
+ synco
+
+ mov.l MIM_L_A, r0
+ mov.l MIM_L_D1, r1
+ synco
+ mov.l r1, @r0
+ synco
+
+ rts
+ nop
+ .align 4
+
+RWTCSR_D_1: .word 0xA507
+RWTCSR_D_2: .word 0xA507
+RWTCNT_D: .word 0x5A00
+ .align 2
+
+BBG_PMMR_A: .long 0xFF800010
+BBG_PMSR1_A: .long 0xFF800014
+BBG_PMSR2_A: .long 0xFF800018
+BBG_PMSR3_A: .long 0xFF80001C
+BBG_PMSR4_A: .long 0xFF800020
+BBG_PMSRG_A: .long 0xFF800024
+
+BBG_PMMR_D_PMSR1: .long 0xffffbffd
+BBG_PMSR1_D: .long 0x00004002
+BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
+BBG_PMSR2_D: .long 0x03de5800
+BBG_PMMR_D_PMSR3: .long 0xfffffff8
+BBG_PMSR3_D: .long 0x00000007
+BBG_PMMR_D_PMSR4: .long 0xdffdfff9
+BBG_PMSR4_D: .long 0x20020006
+BBG_PMMR_D_PMSRG: .long 0xffffffff
+BBG_PMSRG_D: .long 0x00000000
+
+FRQCR_A: .long FRQCR
+DLLCSR_A: .long 0xffc40010
+FRQCR_D: .long 0x40233035
+DLLCSR_D: .long 0x00000000
+
+/* for DDR-SDRAM */
+MIM_U_A: .long MIM_1
+MIM_L_A: .long MIM_2
+SCR_U_A: .long SCR_1
+SCR_L_A: .long SCR_2
+STR_U_A: .long STR_1
+STR_L_A: .long STR_2
+SDR_U_A: .long SDR_1
+SDR_L_A: .long SDR_2
+
+EMRS_A: .long 0xFEC02000
+MRS1_A: .long 0xFEC00B08
+MRS2_A: .long 0xFEC00308
+
+MIM_U_D: .long 0x00004000
+MIM_L_D0: .long 0x03e80009
+MIM_L_D1: .long 0x03e80209
+SCR_L_D0: .long 0x3
+SCR_L_D1: .long 0x2
+SCR_L_D2: .long 0x2
+SCR_L_D3: .long 0x4
+SCR_L_D4: .long 0x4
+SCR_L_D5: .long 0x0
+STR_L_D: .long 0x000f0000
+SDR_L_D: .long 0x00000400
+EMRS_D: .long 0x0
+MRS1_D: .long 0x0
+MRS2_D: .long 0x0
+
+/* Cache Controller */
+CCR_A: .long CCR
+MMUCR_A: .long MMUCR
+RWTCNT_A: .long WTCNT
+
+CCR_D: .long 0x0000090b
+CCR_D_2: .long 0x00000103
+MMUCR_D: .long 0x00000004
+MSTPCR0_D: .long 0x00001001
+MSTPCR2_D: .long 0xffffffff
+
+/* local Bus State Controller */
+MMSELR_A: .long MMSELR
+BCR_A: .long BCR
+CS0BCR_A: .long CS0BCR
+CS1BCR_A: .long CS1BCR
+CS2BCR_A: .long CS2BCR
+CS4BCR_A: .long CS4BCR
+CS5BCR_A: .long CS5BCR
+CS6BCR_A: .long CS6BCR
+CS0WCR_A: .long CS0WCR
+CS1WCR_A: .long CS1WCR
+CS2WCR_A: .long CS2WCR
+CS4WCR_A: .long CS4WCR
+CS5WCR_A: .long CS5WCR
+CS6WCR_A: .long CS6WCR
+CS5PCR_A: .long CS5PCR
+CS6PCR_A: .long CS6PCR
+
+MMSELR_D: .long 0xA5A50003
+BCR_D: .long 0x00000000
+CS0BCR_D: .long 0x77777770
+CS1BCR_D: .long 0x77777670
+CS2BCR_D: .long 0x77777770
+CS4BCR_D: .long 0x77777770
+CS5BCR_D: .long 0x77777670
+CS6BCR_D: .long 0x77777770
+CS0WCR_D: .long 0x00020006
+CS1WCR_D: .long 0x00232304
+CS2WCR_D: .long 0x7777770F
+CS4WCR_D: .long 0x7777770F
+CS5WCR_D: .long 0x00101006
+CS6WCR_D: .long 0x77777703
+CS5PCR_D: .long 0x77000000
+CS6PCR_D: .long 0x77000000
+
+REPEAT0_R3: .long 0x00002000
+REPEAT0_R1: .long 0x0000200
diff --git a/board/renesas/r7780mp/r7780mp.c b/board/renesas/r7780mp/r7780mp.c
new file mode 100644
index 0000000..783352d
--- /dev/null
+++ b/board/renesas/r7780mp/r7780mp.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <netdev.h>
+#include "r7780mp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+#if defined(CONFIG_R7780MP)
+ puts("BOARD: Renesas Solutions R7780MP\n");
+#else
+ puts("BOARD: Renesas Solutions R7780RP\n");
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ /* SCIF Enable */
+ writew(0x0, PHCR);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+
+}
+
+void ide_set_reset(int idereset)
+{
+ /* if reset = 1 IDE reset will be asserted */
+ if (idereset) {
+ writew(0x432, FPGA_CFCTL);
+#if defined(CONFIG_R7780MP)
+ writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW);
+#else
+ writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW);
+#endif
+ writew(0x01, FPGA_CFCDINTCLR);
+ }
+}
+
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+ pci_sh7780_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ /* return >= 0 if a chip is found, the board's AX88796L is n2k-based */
+ return ne2k_register() + pci_eth_init(bis);
+}
diff --git a/board/renesas/r7780mp/r7780mp.h b/board/renesas/r7780mp/r7780mp.h
new file mode 100644
index 0000000..1102689
--- /dev/null
+++ b/board/renesas/r7780mp/r7780mp.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * u-boot/board/r7780mp/r7780mp.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_R7780MP_R7780MP_H_
+#define _BOARD_R7780MP_R7780MP_H_
+
+/* R7780MP's FPGA register map */
+#define FPGA_BASE 0xa4000000
+#define FPGA_IRLMSK (FPGA_BASE + 0x00)
+#define FPGA_IRLMON (FPGA_BASE + 0x02)
+#define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
+#define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
+#define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
+#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
+#define FPGA_RSTCTL (FPGA_BASE + 0x0C)
+#define FPGA_PCIBD (FPGA_BASE + 0x0E)
+#define FPGA_PCICD (FPGA_BASE + 0x10)
+#define FPGA_EXTGIO (FPGA_BASE + 0x16)
+#define FPGA_IVDRMON (FPGA_BASE + 0x18)
+#define FPGA_IVDRCR (FPGA_BASE + 0x1A)
+#define FPGA_OBLED (FPGA_BASE + 0x1C)
+#define FPGA_OBSW (FPGA_BASE + 0x1E)
+#define FPGA_TPCTL (FPGA_BASE + 0x100)
+#define FPGA_TPDCKCTL (FPGA_BASE + 0x102)
+#define FPGA_TPCLR (FPGA_BASE + 0x104)
+#define FPGA_TPXPOS (FPGA_BASE + 0x106)
+#define FPGA_TPYPOS (FPGA_BASE + 0x108)
+#define FPGA_DBSW (FPGA_BASE + 0x200)
+#define FPGA_VERSION (FPGA_BASE + 0x700)
+#define FPGA_CFCTL (FPGA_BASE + 0x300)
+#define FPGA_CFPOW (FPGA_BASE + 0x302)
+#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304)
+#define FPGA_PMR (FPGA_BASE + 0x900)
+
+#endif /* _BOARD_R7780RP_R7780RP_H_ */
diff --git a/board/renesas/rcar-gen2-common/common.c b/board/renesas/rcar-gen2-common/common.c
new file mode 100644
index 0000000..0103f42
--- /dev/null
+++ b/board/renesas/rcar-gen2-common/common.c
@@ -0,0 +1,59 @@
+/*
+ * board/renesas/rcar-gen2-common/common.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+
+#define TSTR0 0x04
+#define TSTR0_STR0 0x01
+
+static struct mstp_ctl mstptbl[] = {
+ { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA,
+ RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA },
+ { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA,
+ RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA },
+ { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA,
+ RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA },
+ { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA,
+ RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA },
+ { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA,
+ RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
+ { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
+ RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
+ /* No MSTP6 */
+ { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
+ RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
+ { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
+ RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA },
+ { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA,
+ RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA },
+ { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA,
+ RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA },
+ { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA,
+ RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA },
+};
+
+void arch_preboot_os(void)
+{
+ int i;
+
+ /* stop TMU0 */
+ mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
+
+ /* Stop module clock */
+ for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
+ mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis,
+ mstptbl[i].s_ena);
+ mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis,
+ mstptbl[i].r_ena);
+ }
+}
diff --git a/board/renesas/rsk7203/Kconfig b/board/renesas/rsk7203/Kconfig
new file mode 100644
index 0000000..10b8786
--- /dev/null
+++ b/board/renesas/rsk7203/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_RSK7203
+
+config SYS_BOARD
+ default "rsk7203"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "rsk7203"
+
+endif
diff --git a/board/renesas/rsk7203/MAINTAINERS b/board/renesas/rsk7203/MAINTAINERS
new file mode 100644
index 0000000..18d3663
--- /dev/null
+++ b/board/renesas/rsk7203/MAINTAINERS
@@ -0,0 +1,7 @@
+RSK7203 BOARD
+M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S: Maintained
+F: board/renesas/rsk7203/
+F: include/configs/rsk7203.h
+F: configs/rsk7203_defconfig
diff --git a/board/renesas/rsk7203/Makefile b/board/renesas/rsk7203/Makefile
new file mode 100644
index 0000000..16acfaf
--- /dev/null
+++ b/board/renesas/rsk7203/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+# Copyright (C) 2008 Renesas Solutions Corp.
+#
+# u-boot/board/rsk7203/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := rsk7203.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S
new file mode 100644
index 0000000..c8494cc
--- /dev/null
+++ b/board/renesas/rsk7203/lowlevel_init.S
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+ /* Cache setting */
+ write32 CCR1_A ,CCR1_D
+
+ /* ConfigurePortPins */
+ write16 PECRL3_A, PECRL3_D
+
+ write16 PCCRL4_A, PCCRL4_D0
+
+ write16 PECRL4_A, PECRL4_D0
+
+ write16 PEIORL_A, PEIORL_D0
+
+ write16 PCIORL_A, PCIORL_D
+
+ write16 PFCRH2_A, PFCRH2_D
+
+ write16 PFCRH3_A, PFCRH3_D
+
+ write16 PFCRH1_A, PFCRH1_D
+
+ write16 PFIORH_A, PFIORH_D
+
+ write16 PECRL1_A, PECRL1_D0
+
+ write16 PEIORL_A, PEIORL_D1
+
+ /* Configure Operating Frequency */
+ write16 WTCSR_A, WTCSR_D0
+
+ write16 WTCSR_A, WTCSR_D1
+
+ write16 WTCNT_A, WTCNT_D
+
+ /* Set clock mode*/
+ write16 FRQCR_A, FRQCR_D
+
+ /* Configure Bus And Memory */
+init_bsc_cs0:
+ write16 PCCRL4_A, PCCRL4_D1
+
+ write16 PECRL1_A, PECRL1_D1
+
+ write32 CMNCR_A, CMNCR_D
+
+ write32 CS0BCR_A, CS0BCR_D
+
+ write32 CS0WCR_A, CS0WCR_D
+
+init_bsc_cs1:
+ write16 PECRL4_A, PECRL4_D1
+
+ write32 CS1WCR_A, CS1WCR_D
+
+init_sdram:
+ write16 PCCRL2_A, PCCRL2_D
+
+ write16 PCCRL4_A, PCCRL4_D2
+
+ write16 PCCRL1_A, PCCRL1_D
+
+ write16 PCCRL3_A, PCCRL3_D
+
+ write32 CS3BCR_A, CS3BCR_D
+
+ write32 CS3WCR_A, CS3WCR_D
+
+ write32 SDCR_A, SDCR_D
+
+ write32 RTCOR_A, RTCOR_D
+
+ write32 RTCSR_A, RTCSR_D
+
+ /* wait 200us */
+ mov.l REPEAT_D, r3
+ mov #0, r2
+repeat0:
+ add #1, r2
+ cmp/hs r3, r2
+ bf repeat0
+ nop
+
+ mov.l SDRAM_MODE, r1
+ mov #0, r0
+ mov.l r0, @r1
+
+ nop
+ rts
+
+ .align 4
+
+CCR1_A: .long CCR1
+CCR1_D: .long 0x0000090B
+PCCRL4_A: .long 0xFFFE3910
+PCCRL4_D0: .word 0x0000
+.align 2
+PECRL4_A: .long 0xFFFE3A10
+PECRL4_D0: .word 0x0000
+.align 2
+PECRL3_A: .long 0xFFFE3A12
+PECRL3_D: .word 0x0000
+.align 2
+PEIORL_A: .long 0xFFFE3A06
+PEIORL_D0: .word 0x1C00
+PEIORL_D1: .word 0x1C02
+PCIORL_A: .long 0xFFFE3906
+PCIORL_D: .word 0x4000
+.align 2
+PFCRH2_A: .long 0xFFFE3A8C
+PFCRH2_D: .word 0x0000
+.align 2
+PFCRH3_A: .long 0xFFFE3A8A
+PFCRH3_D: .word 0x0000
+.align 2
+PFCRH1_A: .long 0xFFFE3A8E
+PFCRH1_D: .word 0x0000
+.align 2
+PFIORH_A: .long 0xFFFE3A84
+PFIORH_D: .word 0x0729
+.align 2
+PECRL1_A: .long 0xFFFE3A16
+PECRL1_D0: .word 0x0033
+.align 2
+
+
+WTCSR_A: .long 0xFFFE0000
+WTCSR_D0: .word 0xA518
+WTCSR_D1: .word 0xA51D
+WTCNT_A: .long 0xFFFE0002
+WTCNT_D: .word 0x5A84
+.align 2
+FRQCR_A: .long 0xFFFE0010
+FRQCR_D: .word 0x0104
+.align 2
+
+PCCRL4_D1: .word 0x0010
+PECRL1_D1: .word 0x0133
+
+CMNCR_A: .long 0xFFFC0000
+CMNCR_D: .long 0x00001810
+CS0BCR_A: .long 0xFFFC0004
+CS0BCR_D: .long 0x10000400
+CS0WCR_A: .long 0xFFFC0028
+CS0WCR_D: .long 0x00000B41
+PECRL4_D1: .word 0x0100
+.align 2
+CS1WCR_A: .long 0xFFFC002C
+CS1WCR_D: .long 0x00000B01
+PCCRL4_D2: .word 0x0011
+.align 2
+PCCRL3_A: .long 0xFFFE3912
+PCCRL3_D: .word 0x0011
+.align 2
+PCCRL2_A: .long 0xFFFE3914
+PCCRL2_D: .word 0x1111
+.align 2
+PCCRL1_A: .long 0xFFFE3916
+PCCRL1_D: .word 0x1010
+.align 2
+PDCRL4_A: .long 0xFFFE3990
+PDCRL4_D: .word 0x0011
+.align 2
+PDCRL3_A: .long 0xFFFE3992
+PDCRL3_D: .word 0x00011
+.align 2
+PDCRL2_A: .long 0xFFFE3994
+PDCRL2_D: .word 0x1111
+.align 2
+PDCRL1_A: .long 0xFFFE3996
+PDCRL1_D: .word 0x1000
+.align 2
+CS3BCR_A: .long 0xFFFC0010
+CS3BCR_D: .long 0x00004400
+CS3WCR_A: .long 0xFFFC0034
+CS3WCR_D: .long 0x00002892
+SDCR_A: .long 0xFFFC004C
+SDCR_D: .long 0x00000809
+RTCOR_A: .long 0xFFFC0058
+RTCOR_D: .long 0xA55A0041
+RTCSR_A: .long 0xFFFC0050
+RTCSR_D: .long 0xa55a0010
+
+SDRAM_MODE: .long 0xFFFC5040
+REPEAT_D: .long 0x00009C40
diff --git a/board/renesas/rsk7203/rsk7203.c b/board/renesas/rsk7203/rsk7203.c
new file mode 100644
index 0000000..8800371
--- /dev/null
+++ b/board/renesas/rsk7203/rsk7203.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * u-boot/board/rsk7203/rsk7203.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas Technology RSK7203\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
+
+/*
+ * The RSK board has the SMSC9118 wired up 'incorrectly'.
+ * Byte-swapping is necessary, and so poor performance is inevitable.
+ * This problem cannot evade by the swap function of CHIP, this can
+ * evade by software Byte-swapping.
+ * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
+ * functions necessary to solve this problem.
+ */
+u32 pkt_data_pull(struct eth_device *dev, u32 addr)
+{
+ volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
+ return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
+ | swab16(*(addr_16 + 1));
+}
+
+void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
+{
+ addr += dev->iobase;
+ *(volatile u16 *)(addr + 2) = swab16((u16)val);
+ *(volatile u16 *)(addr) = swab16((u16)(val >> 16));
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/renesas/rsk7264/Kconfig b/board/renesas/rsk7264/Kconfig
new file mode 100644
index 0000000..755d289
--- /dev/null
+++ b/board/renesas/rsk7264/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_RSK7264
+
+config SYS_BOARD
+ default "rsk7264"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "rsk7264"
+
+endif
diff --git a/board/renesas/rsk7264/MAINTAINERS b/board/renesas/rsk7264/MAINTAINERS
new file mode 100644
index 0000000..f6202b7
--- /dev/null
+++ b/board/renesas/rsk7264/MAINTAINERS
@@ -0,0 +1,6 @@
+RSK7264 BOARD
+M: Phil Edworthy <phil.edworthy@renesas.com>
+S: Maintained
+F: board/renesas/rsk7264/
+F: include/configs/rsk7264.h
+F: configs/rsk7264_defconfig
diff --git a/board/renesas/rsk7264/Makefile b/board/renesas/rsk7264/Makefile
new file mode 100644
index 0000000..7ada697
--- /dev/null
+++ b/board/renesas/rsk7264/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011 Renesas Electronics Europe Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := rsk7264.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/rsk7264/lowlevel_init.S b/board/renesas/rsk7264/lowlevel_init.S
new file mode 100644
index 0000000..1a7d27d
--- /dev/null
+++ b/board/renesas/rsk7264/lowlevel_init.S
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2011 Renesas Electronics Europe Ltd.
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ *
+ * Based on board/renesas/rsk7203/lowlevel_init.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+ /* Cache setting */
+ write32 CCR1_A ,CCR1_D
+
+ /* io_set_cpg */
+ write8 STBCR3_A, STBCR3_D
+ write8 STBCR4_A, STBCR4_D
+ write8 STBCR5_A, STBCR5_D
+ write8 STBCR6_A, STBCR6_D
+ write8 STBCR7_A, STBCR7_D
+ write8 STBCR8_A, STBCR8_D
+
+ /* ConfigurePortPins */
+
+ /* Leaving LED1 ON for sanity test */
+ write16 PJCR1_A, PJCR1_D1
+ write16 PJCR2_A, PJCR2_D
+ write16 PJIOR0_A, PJIOR0_D1
+ write16 PJDR0_A, PJDR0_D
+ write16 PJPR0_A, PJPR0_D
+
+ /* Configure EN_PIN & RS_PIN */
+ write16 PGCR2_A, PGCR2_D
+ write16 PGIOR0_A, PGIOR0_D
+
+ /* Configure the port pins connected to UART */
+ write16 PJCR1_A, PJCR1_D2
+ write16 PJIOR0_A, PJIOR0_D2
+
+ /* Configure Operating Frequency */
+ write16 WTCSR_A, WTCSR_D0
+ write16 WTCSR_A, WTCSR_D1
+ write16 WTCNT_A, WTCNT_D
+
+ /* Control of RESBANK */
+ write16 IBNR_A, IBNR_D
+ /* Enable SCIF3 module */
+ write16 STBCR4_A, STBCR4_D
+
+ /* Set clock mode*/
+ write16 FRQCR_A, FRQCR_D
+
+ /* Configure Bus And Memory */
+init_bsc_cs0:
+
+pfc_settings:
+ write16 PCCR2_A, PCCR2_D
+ write16 PCCR1_A, PCCR1_D
+ write16 PCCR0_A, PCCR0_D
+
+ write16 PBCR0_A, PBCR0_D
+ write16 PBCR1_A, PBCR1_D
+ write16 PBCR2_A, PBCR2_D
+ write16 PBCR3_A, PBCR3_D
+ write16 PBCR4_A, PBCR4_D
+ write16 PBCR5_A, PBCR5_D
+
+ write16 PDCR0_A, PDCR0_D
+ write16 PDCR1_A, PDCR1_D
+ write16 PDCR2_A, PDCR2_D
+ write16 PDCR3_A, PDCR3_D
+
+ write32 CS0WCR_A, CS0WCR_D
+ write32 CS0BCR_A, CS0BCR_D
+
+init_bsc_cs2:
+ write16 PJCR0_A, PJCR0_D
+ write32 CS2WCR_A, CS2WCR_D
+
+init_sdram:
+ write32 CS3BCR_A, CS3BCR_D
+ write32 CS3WCR_A, CS3WCR_D
+ write32 SDCR_A, SDCR_D
+ write32 RTCOR_A, RTCOR_D
+ write32 RTCSR_A, RTCSR_D
+
+ /* wait 200us */
+ mov.l REPEAT_D, r3
+ mov #0, r2
+repeat0:
+ add #1, r2
+ cmp/hs r3, r2
+ bf repeat0
+ nop
+
+ mov.l SDRAM_MODE, r1
+ mov #0, r0
+ mov.l r0, @r1
+
+ nop
+ rts
+
+ .align 4
+
+CCR1_A: .long CCR1
+CCR1_D: .long 0x0000090B
+FRQCR_A: .long 0xFFFE0010
+FRQCR_D: .word 0x1003
+.align 2
+STBCR3_A: .long 0xFFFE0408
+STBCR3_D: .long 0x00000002
+STBCR4_A: .long 0xFFFE040C
+STBCR4_D: .word 0x0000
+.align 2
+STBCR5_A: .long 0xFFFE0410
+STBCR5_D: .long 0x00000010
+STBCR6_A: .long 0xFFFE0414
+STBCR6_D: .long 0x00000002
+STBCR7_A: .long 0xFFFE0418
+STBCR7_D: .long 0x0000002A
+STBCR8_A: .long 0xFFFE041C
+STBCR8_D: .long 0x0000007E
+PJCR1_A: .long 0xFFFE390C
+PJCR1_D1: .word 0x0000
+PJCR1_D2: .word 0x0022
+PJCR2_A: .long 0xFFFE390A
+PJCR2_D: .word 0x0000
+.align 2
+PJIOR0_A: .long 0xFFFE3912
+PJIOR0_D1: .word 0x0FC0
+PJIOR0_D2: .word 0x0FE0
+PJDR0_A: .long 0xFFFE3916
+PJDR0_D: .word 0x0FBF
+.align 2
+PJPR0_A: .long 0xFFFE391A
+PJPR0_D: .long 0x00000FBF
+PGCR2_A: .long 0xFFFE38CA
+PGCR2_D: .word 0x0000
+.align 2
+PGIOR0_A: .long 0xFFFE38D2
+PGIOR0_D: .word 0x03F0
+.align 2
+WTCSR_A: .long 0xFFFE0000
+WTCSR_D0: .word 0x0000
+WTCSR_D1: .word 0x0000
+WTCNT_A: .long 0xFFFE0002
+WTCNT_D: .word 0x0000
+.align 2
+PCCR0_A: .long 0xFFFE384E
+PDCR0_A: .long 0xFFFE386E
+PDCR1_A: .long 0xFFFE386C
+PDCR2_A: .long 0xFFFE386A
+PDCR3_A: .long 0xFFFE3868
+PBCR0_A: .long 0xFFFE382E
+PBCR1_A: .long 0xFFFE382C
+PBCR2_A: .long 0xFFFE382A
+PBCR3_A: .long 0xFFFE3828
+PBCR4_A: .long 0xFFFE3826
+PBCR5_A: .long 0xFFFE3824
+PCCR0_D: .word 0x1111
+PDCR0_D: .word 0x1111
+PDCR1_D: .word 0x1111
+PDCR2_D: .word 0x1111
+PDCR3_D: .word 0x1111
+PBCR0_D: .word 0x1110
+PBCR1_D: .word 0x1111
+PBCR2_D: .word 0x1111
+PBCR3_D: .word 0x1111
+PBCR4_D: .word 0x1111
+PBCR5_D: .word 0x0111
+.align 2
+CS0WCR_A: .long 0xFFFC0028
+CS0WCR_D: .long 0x00000B41
+CS0BCR_A: .long 0xFFFC0004
+CS0BCR_D: .long 0x10000400
+PJCR0_A: .long 0xFFFE390E
+PJCR0_D: .word 0x3300
+.align 2
+CS2WCR_A: .long 0xFFFC0030
+CS2WCR_D: .long 0x00000B01
+PCCR2_A: .long 0xFFFE384A
+PCCR2_D: .word 0x0001
+.align 2
+PCCR1_A: .long 0xFFFE384C
+PCCR1_D: .word 0x1111
+.align 2
+CS3BCR_A: .long 0xFFFC0010
+CS3BCR_D: .long 0x00004400
+CS3WCR_A: .long 0xFFFC0034
+CS3WCR_D: .long 0x0000288A
+SDCR_A: .long 0xFFFC004C
+SDCR_D: .long 0x00000812
+RTCOR_A: .long 0xFFFC0058
+RTCOR_D: .long 0xA55A0046
+RTCSR_A: .long 0xFFFC0050
+RTCSR_D: .long 0xA55A0010
+IBNR_A: .long 0xFFFE080E
+IBNR_D: .word 0x0000
+.align 2
+SDRAM_MODE: .long 0xFFFC5040
+REPEAT_D: .long 0x00000085
diff --git a/board/renesas/rsk7264/rsk7264.c b/board/renesas/rsk7264/rsk7264.c
new file mode 100644
index 0000000..d938b3a
--- /dev/null
+++ b/board/renesas/rsk7264/rsk7264.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2011 Renesas Electronics Europe Ltd.
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ *
+ * Based on u-boot/board/rsk7264/rsk7203.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas Technology RSK7264\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
+
+/*
+ * The RSK board has the SMSC89218 wired up 'incorrectly'.
+ * Byte-swapping is necessary, and so poor performance is inevitable.
+ * This problem cannot evade by the swap function of CHIP, this can
+ * evade by software Byte-swapping.
+ * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
+ * functions necessary to solve this problem.
+ */
+u32 pkt_data_pull(struct eth_device *dev, u32 addr)
+{
+ volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
+ return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
+ | swab16(*(addr_16 + 1));
+}
+
+void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
+{
+ addr += dev->iobase;
+ *(volatile u16 *)(addr + 2) = swab16((u16)val);
+ *(volatile u16 *)(addr) = swab16((u16)(val >> 16));
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/renesas/rsk7269/Kconfig b/board/renesas/rsk7269/Kconfig
new file mode 100644
index 0000000..ab5cd0e
--- /dev/null
+++ b/board/renesas/rsk7269/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_RSK7269
+
+config SYS_BOARD
+ default "rsk7269"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "rsk7269"
+
+endif
diff --git a/board/renesas/rsk7269/MAINTAINERS b/board/renesas/rsk7269/MAINTAINERS
new file mode 100644
index 0000000..698fbdb
--- /dev/null
+++ b/board/renesas/rsk7269/MAINTAINERS
@@ -0,0 +1,6 @@
+RSK7269 BOARD
+#M: -
+S: Maintained
+F: board/renesas/rsk7269/
+F: include/configs/rsk7269.h
+F: configs/rsk7269_defconfig
diff --git a/board/renesas/rsk7269/Makefile b/board/renesas/rsk7269/Makefile
new file mode 100644
index 0000000..0f053d8
--- /dev/null
+++ b/board/renesas/rsk7269/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2012 Renesas Electronics Europe Ltd.
+# Copyright (C) 2012 Phil Edworthy
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := rsk7269.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/rsk7269/lowlevel_init.S b/board/renesas/rsk7269/lowlevel_init.S
new file mode 100644
index 0000000..a2b174b
--- /dev/null
+++ b/board/renesas/rsk7269/lowlevel_init.S
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2012 Renesas Electronics Europe Ltd.
+ * Copyright (C) 2012 Phil Edworthy
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ *
+ * Based on board/renesas/rsk7264/lowlevel_init.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+ /* Flush and enable caches (data cache in write-through mode) */
+ write32 CCR1_A ,CCR1_D
+
+ /* Disable WDT */
+ write16 WTCSR_A, WTCSR_D
+ write16 WTCNT_A, WTCNT_D
+
+ /* Disable Register Bank interrupts */
+ write16 IBNR_A, IBNR_D
+
+ /* Set clocks based on 13.225MHz xtal */
+ write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */
+
+ /* Enable all peripherals */
+ write8 STBCR3_A, STBCR3_D
+ write8 STBCR4_A, STBCR4_D
+ write8 STBCR5_A, STBCR5_D
+ write8 STBCR6_A, STBCR6_D
+ write8 STBCR7_A, STBCR7_D
+ write8 STBCR8_A, STBCR8_D
+ write8 STBCR9_A, STBCR9_D
+ write8 STBCR10_A, STBCR10_D
+
+ /* SCIF7 and IIC2 */
+ write16 PJCR3_A, PJCR3_D /* TXD7 */
+ write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */
+
+ /* Configure bus (CS0) */
+ write16 PFCR3_A, PFCR3_D /* A24 */
+ write16 PFCR2_A, PFCR2_D /* A23 and CS1# */
+ write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */
+ write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
+ write32 CS0WCR_A, CS0WCR_D
+ write32 CS0BCR_A, CS0BCR_D
+
+ /* Configure SDRAM (CS3) */
+ write16 PCCR2_A, PCCR2_D /* CS3# */
+ write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */
+ write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
+ write32 CS3BCR_A, CS3BCR_D
+ write32 CS3WCR_A, CS3WCR_D
+ write32 SDCR_A, SDCR_D
+ write32 RTCOR_A, RTCOR_D
+ write32 RTCSR_A, RTCSR_D
+
+ /* Configure ethernet (CS1) */
+ write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */
+ write16 PHCR0_A, PHCR0_D
+ write16 PFCR2_A, PFCR2_D /* CS1# */
+ write32 CS1BCR_A, CS1BCR_D /* Big endian */
+ write32 CS1WCR_A, CS1WCR_D /* 1 cycle */
+ write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */
+ write16 PJIOR1_A, PJIOR1_D
+
+ /* wait 200us */
+ mov.l REPEAT_D, r3
+ mov #0, r2
+repeat0:
+ add #1, r2
+ cmp/hs r3, r2
+ bf repeat0
+ nop
+
+ mov.l SDRAM_MODE, r1
+ mov #0, r0
+ mov.l r0, @r1
+
+ nop
+ rts
+
+ .align 4
+
+CCR1_A: .long CCR1
+CCR1_D: .long 0x0000090B
+
+STBCR3_A: .long 0xFFFE0408
+STBCR4_A: .long 0xFFFE040C
+STBCR5_A: .long 0xFFFE0410
+STBCR6_A: .long 0xFFFE0414
+STBCR7_A: .long 0xFFFE0418
+STBCR8_A: .long 0xFFFE041C
+STBCR9_A: .long 0xFFFE0440
+STBCR10_A: .long 0xFFFE0444
+STBCR3_D: .long 0x0000001A
+STBCR4_D: .long 0x00000000
+STBCR5_D: .long 0x00000000
+STBCR6_D: .long 0x00000000
+STBCR7_D: .long 0x00000012
+STBCR8_D: .long 0x00000009
+STBCR9_D: .long 0x00000000
+STBCR10_D: .long 0x00000010
+
+WTCSR_A: .long 0xFFFE0000
+WTCNT_A: .long 0xFFFE0002
+WTCSR_D: .word 0xA518
+WTCNT_D: .word 0x5A00
+
+IBNR_A: .long 0xFFFE080E
+IBNR_D: .word 0x0000
+.align 2
+FRQCR_A: .long 0xFFFE0010
+FRQCR_D: .word 0x0015
+.align 2
+
+PJCR3_A: .long 0xFFFE3908
+PJCR3_D: .word 0x5000
+.align 2
+PECR1_A: .long 0xFFFE388C
+PECR1_D: .word 0x2011
+.align 2
+
+PFCR3_A: .long 0xFFFE38A8
+PFCR2_A: .long 0xFFFE38AA
+PBCR5_A: .long 0xFFFE3824
+PFCR3_D: .word 0x0010
+PFCR2_D: .word 0x0101
+PBCR5_D: .word 0x0111
+.align 2
+CS0WCR_A: .long 0xFFFC0028
+CS0WCR_D: .long 0x00000341
+CS0BCR_A: .long 0xFFFC0004
+CS0BCR_D: .long 0x00000400
+
+PCCR2_A: .long 0xFFFE384A
+PCCR1_A: .long 0xFFFE384C
+PCCR0_A: .long 0xFFFE384E
+PCCR2_D: .word 0x0001
+PCCR1_D: .word 0x1111
+PCCR0_D: .word 0x1111
+.align 2
+CS3BCR_A: .long 0xFFFC0010
+CS3BCR_D: .long 0x00004400
+CS3WCR_A: .long 0xFFFC0034
+CS3WCR_D: .long 0x00004912
+SDCR_A: .long 0xFFFC004C
+SDCR_D: .long 0x00000811
+RTCOR_A: .long 0xFFFC0058
+RTCOR_D: .long 0xA55A0035
+RTCSR_A: .long 0xFFFC0050
+RTCSR_D: .long 0xA55A0010
+.align 2
+SDRAM_MODE: .long 0xFFFC5460
+REPEAT_D: .long 0x000033F1
+
+PHCR1_A: .long 0xFFFE38EC
+PHCR0_A: .long 0xFFFE38EE
+PHCR1_D: .word 0x2222
+PHCR0_D: .word 0x2222
+.align 2
+CS1BCR_A: .long 0xFFFC0008
+CS1BCR_D: .long 0x00000400
+CS1WCR_A: .long 0xFFFC002C
+CS1WCR_D: .long 0x00000080
+PJDR1_A: .long 0xFFFE3914
+PJDR1_D: .word 0x0000
+.align 2
+PJIOR1_A: .long 0xFFFE3910
+PJIOR1_D: .word 0x8000
+.align 2
diff --git a/board/renesas/rsk7269/rsk7269.c b/board/renesas/rsk7269/rsk7269.c
new file mode 100644
index 0000000..ae32b6a
--- /dev/null
+++ b/board/renesas/rsk7269/rsk7269.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2012 Renesas Electronics Europe Ltd.
+ * Copyright (C) 2012 Phil Edworthy
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ *
+ * Based on u-boot/board/rsk7264/rsk7264.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas RSK7269\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
+
+/*
+ * The RSK board has the SMSC89218 wired up 'incorrectly'.
+ * Byte-swapping is necessary, and so poor performance is inevitable.
+ * This problem cannot evade by the swap function of CHIP, this can
+ * evade by software Byte-swapping.
+ * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
+ * functions necessary to solve this problem.
+ */
+u32 pkt_data_pull(struct eth_device *dev, u32 addr)
+{
+ volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
+ return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
+ | swab16(*(addr_16 + 1));
+}
+
+void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
+{
+ addr += dev->iobase;
+ *(volatile u16 *)(addr + 2) = swab16((u16)val);
+ *(volatile u16 *)(addr) = swab16((u16)(val >> 16));
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/renesas/sh7752evb/Kconfig b/board/renesas/sh7752evb/Kconfig
new file mode 100644
index 0000000..7f40888
--- /dev/null
+++ b/board/renesas/sh7752evb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SH7752EVB
+
+config SYS_BOARD
+ default "sh7752evb"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "sh7752evb"
+
+endif
diff --git a/board/renesas/sh7752evb/MAINTAINERS b/board/renesas/sh7752evb/MAINTAINERS
new file mode 100644
index 0000000..9840477
--- /dev/null
+++ b/board/renesas/sh7752evb/MAINTAINERS
@@ -0,0 +1,6 @@
+SH7752EVB BOARD
+#M: -
+S: Maintained
+F: board/renesas/sh7752evb/
+F: include/configs/sh7752evb.h
+F: configs/sh7752evb_defconfig
diff --git a/board/renesas/sh7752evb/Makefile b/board/renesas/sh7752evb/Makefile
new file mode 100644
index 0000000..856af81
--- /dev/null
+++ b/board/renesas/sh7752evb/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := sh7752evb.o spi-boot.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/sh7752evb/lowlevel_init.S b/board/renesas/sh7752evb/lowlevel_init.S
new file mode 100644
index 0000000..5643a69
--- /dev/null
+++ b/board/renesas/sh7752evb/lowlevel_init.S
@@ -0,0 +1,447 @@
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+.macro or32, addr, data
+ mov.l \addr, r1
+ mov.l \data, r0
+ mov.l @r1, r2
+ or r2, r0
+ mov.l r0, @r1
+.endm
+
+.macro wait_DBCMD
+ mov.l DBWAIT_A, r0
+ mov.l @r0, r1
+.endm
+
+ .global lowlevel_init
+ .section .spiboot1.text
+ .align 2
+
+lowlevel_init:
+ /*------- GPIO -------*/
+ write16 PDCR_A, PDCR_D ! SPI0
+ write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1)
+ write16 PJCR_A, PJCR_D ! SCIF4
+ write16 PTCR_A, PTCR_D ! STATUS
+ write16 PSEL1_A, PSEL1_D ! SPI0
+ write16 PSEL2_A, PSEL2_D ! SPI0
+ write16 PSEL5_A, PSEL5_D ! STATUS
+
+ bra exit_gpio
+ nop
+
+ .align 2
+
+/*------- GPIO -------*/
+PDCR_A: .long 0xffec0006
+PGCR_A: .long 0xffec000c
+PJCR_A: .long 0xffec0012
+PTCR_A: .long 0xffec0026
+PSEL1_A: .long 0xffec0072
+PSEL2_A: .long 0xffec0074
+PSEL5_A: .long 0xffec007a
+
+PDCR_D: .long 0x0000
+PGCR_D: .long 0x0004
+PJCR_D: .long 0x0000
+PTCR_D: .long 0x0000
+PSEL1_D: .long 0x0000
+PSEL2_D: .long 0x3000
+PSEL5_D: .long 0x0ffc
+
+ .align 2
+
+exit_gpio:
+ mov #0, r14
+ mova 2f, r0
+ mov.l PC_MASK, r1
+ tst r0, r1
+ bf 2f
+
+ bra exit_pmb
+ nop
+
+ .align 2
+
+/* If CPU runs on SDRAM (PC=0x5???????) or not. */
+PC_MASK: .long 0x20000000
+
+2:
+ mov #1, r14
+
+ mov.l EXPEVT_A, r0
+ mov.l @r0, r0
+ mov.l EXPEVT_POWER_ON_RESET, r1
+ cmp/eq r0, r1
+ bt 1f
+
+ /*
+ * If EXPEVT value is manual reset or tlb multipul-hit,
+ * initialization of DDR3IF is not necessary.
+ */
+ bra exit_ddr
+ nop
+
+1:
+ /*------- Reset -------*/
+ write32 MRSTCR0_A, MRSTCR0_D
+ write32 MRSTCR1_A, MRSTCR1_D
+
+ /* For Core Reset */
+ mov.l DBACEN_A, r0
+ mov.l @r0, r0
+ cmp/eq #0, r0
+ bt 3f
+
+ /*
+ * If DBACEN == 1(DBSC was already enabled), we have to avoid the
+ * initialization of DDR3-SDRAM.
+ */
+ bra exit_ddr
+ nop
+
+3:
+ /*------- DDR3IF -------*/
+ /* oscillation stabilization time */
+ wait_timer WAIT_OSC_TIME
+
+ /* step 3 */
+ write32 DBCMD_A, DBCMD_RSTL_VAL
+ wait_timer WAIT_30US
+
+ /* step 4 */
+ write32 DBCMD_A, DBCMD_PDEN_VAL
+
+ /* step 5 */
+ write32 DBKIND_A, DBKIND_D
+
+ /* step 6 */
+ write32 DBCONF_A, DBCONF_D
+ write32 DBTR0_A, DBTR0_D
+ write32 DBTR1_A, DBTR1_D
+ write32 DBTR2_A, DBTR2_D
+ write32 DBTR3_A, DBTR3_D
+ write32 DBTR4_A, DBTR4_D
+ write32 DBTR5_A, DBTR5_D
+ write32 DBTR6_A, DBTR6_D
+ write32 DBTR7_A, DBTR7_D
+ write32 DBTR8_A, DBTR8_D
+ write32 DBTR9_A, DBTR9_D
+ write32 DBTR10_A, DBTR10_D
+ write32 DBTR11_A, DBTR11_D
+ write32 DBTR12_A, DBTR12_D
+ write32 DBTR13_A, DBTR13_D
+ write32 DBTR14_A, DBTR14_D
+ write32 DBTR15_A, DBTR15_D
+ write32 DBTR16_A, DBTR16_D
+ write32 DBTR17_A, DBTR17_D
+ write32 DBTR18_A, DBTR18_D
+ write32 DBTR19_A, DBTR19_D
+ write32 DBRNK0_A, DBRNK0_D
+
+ /* step 7 */
+ write32 DBPDCNT3_A, DBPDCNT3_D
+
+ /* step 8 */
+ write32 DBPDCNT1_A, DBPDCNT1_D
+ write32 DBPDCNT2_A, DBPDCNT2_D
+ write32 DBPDLCK_A, DBPDLCK_D
+ write32 DBPDRGA_A, DBPDRGA_D
+ write32 DBPDRGD_A, DBPDRGD_D
+
+ /* step 9 */
+ wait_timer WAIT_30US
+
+ /* step 10 */
+ write32 DBPDCNT0_A, DBPDCNT0_D
+
+ /* step 11 */
+ wait_timer WAIT_30US
+ wait_timer WAIT_30US
+
+ /* step 12 */
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ wait_DBCMD
+
+ /* step 13 */
+ write32 DBCMD_A, DBCMD_RSTH_VAL
+ wait_DBCMD
+
+ /* step 14 */
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+
+ /* step 15 */
+ write32 DBCMD_A, DBCMD_PDXT_VAL
+
+ /* step 16 */
+ write32 DBCMD_A, DBCMD_MRS2_VAL
+
+ /* step 17 */
+ write32 DBCMD_A, DBCMD_MRS3_VAL
+
+ /* step 18 */
+ write32 DBCMD_A, DBCMD_MRS1_VAL
+
+ /* step 19 */
+ write32 DBCMD_A, DBCMD_MRS0_VAL
+
+ /* step 20 */
+ write32 DBCMD_A, DBCMD_ZQCL_VAL
+
+ write32 DBCMD_A, DBCMD_REF_VAL
+ write32 DBCMD_A, DBCMD_REF_VAL
+ wait_DBCMD
+
+ /* step 21 */
+ write32 DBADJ0_A, DBADJ0_D
+ write32 DBADJ1_A, DBADJ1_D
+ write32 DBADJ2_A, DBADJ2_D
+
+ /* step 22 */
+ write32 DBRFCNF0_A, DBRFCNF0_D
+ write32 DBRFCNF1_A, DBRFCNF1_D
+ write32 DBRFCNF2_A, DBRFCNF2_D
+
+ /* step 23 */
+ write32 DBCALCNF_A, DBCALCNF_D
+
+ /* step 24 */
+ write32 DBRFEN_A, DBRFEN_D
+ write32 DBCMD_A, DBCMD_SRXT_VAL
+
+ /* step 25 */
+ write32 DBACEN_A, DBACEN_D
+
+ /* step 26 */
+ wait_DBCMD
+
+ bra exit_ddr
+ nop
+
+ .align 2
+
+EXPEVT_A: .long 0xff000024
+EXPEVT_POWER_ON_RESET: .long 0x00000000
+
+/*------- Reset -------*/
+MRSTCR0_A: .long 0xffd50030
+MRSTCR0_D: .long 0xfe1ffe7f
+MRSTCR1_A: .long 0xffd50034
+MRSTCR1_D: .long 0xfff3ffff
+
+/*------- DDR3IF -------*/
+DBCMD_A: .long 0xfe800018
+DBKIND_A: .long 0xfe800020
+DBCONF_A: .long 0xfe800024
+DBTR0_A: .long 0xfe800040
+DBTR1_A: .long 0xfe800044
+DBTR2_A: .long 0xfe800048
+DBTR3_A: .long 0xfe800050
+DBTR4_A: .long 0xfe800054
+DBTR5_A: .long 0xfe800058
+DBTR6_A: .long 0xfe80005c
+DBTR7_A: .long 0xfe800060
+DBTR8_A: .long 0xfe800064
+DBTR9_A: .long 0xfe800068
+DBTR10_A: .long 0xfe80006c
+DBTR11_A: .long 0xfe800070
+DBTR12_A: .long 0xfe800074
+DBTR13_A: .long 0xfe800078
+DBTR14_A: .long 0xfe80007c
+DBTR15_A: .long 0xfe800080
+DBTR16_A: .long 0xfe800084
+DBTR17_A: .long 0xfe800088
+DBTR18_A: .long 0xfe80008c
+DBTR19_A: .long 0xfe800090
+DBRNK0_A: .long 0xfe800100
+DBPDCNT0_A: .long 0xfe800200
+DBPDCNT1_A: .long 0xfe800204
+DBPDCNT2_A: .long 0xfe800208
+DBPDCNT3_A: .long 0xfe80020c
+DBPDLCK_A: .long 0xfe800280
+DBPDRGA_A: .long 0xfe800290
+DBPDRGD_A: .long 0xfe8002a0
+DBADJ0_A: .long 0xfe8000c0
+DBADJ1_A: .long 0xfe8000c4
+DBADJ2_A: .long 0xfe8000c8
+DBRFCNF0_A: .long 0xfe8000e0
+DBRFCNF1_A: .long 0xfe8000e4
+DBRFCNF2_A: .long 0xfe8000e8
+DBCALCNF_A: .long 0xfe8000f4
+DBRFEN_A: .long 0xfe800014
+DBACEN_A: .long 0xfe800010
+DBWAIT_A: .long 0xfe80001c
+
+WAIT_OSC_TIME: .long 6000
+WAIT_30US: .long 13333
+
+DBCMD_RSTL_VAL: .long 0x20000000
+DBCMD_PDEN_VAL: .long 0x1000d73c
+DBCMD_WAIT_VAL: .long 0x0000d73c
+DBCMD_RSTH_VAL: .long 0x2100d73c
+DBCMD_PDXT_VAL: .long 0x110000c8
+DBCMD_MRS0_VAL: .long 0x28000930
+DBCMD_MRS1_VAL: .long 0x29000004
+DBCMD_MRS2_VAL: .long 0x2a000008
+DBCMD_MRS3_VAL: .long 0x2b000000
+DBCMD_ZQCL_VAL: .long 0x03000200
+DBCMD_REF_VAL: .long 0x0c000000
+DBCMD_SRXT_VAL: .long 0x19000000
+DBKIND_D: .long 0x00000007
+DBCONF_D: .long 0x0f030a01
+DBTR0_D: .long 0x00000007
+DBTR1_D: .long 0x00000006
+DBTR2_D: .long 0x00000000
+DBTR3_D: .long 0x00000007
+DBTR4_D: .long 0x00070007
+DBTR5_D: .long 0x0000001b
+DBTR6_D: .long 0x00000014
+DBTR7_D: .long 0x00000005
+DBTR8_D: .long 0x00000015
+DBTR9_D: .long 0x00000006
+DBTR10_D: .long 0x00000008
+DBTR11_D: .long 0x00000007
+DBTR12_D: .long 0x0000000e
+DBTR13_D: .long 0x00000056
+DBTR14_D: .long 0x00000006
+DBTR15_D: .long 0x00000004
+DBTR16_D: .long 0x00150002
+DBTR17_D: .long 0x000c0017
+DBTR18_D: .long 0x00000200
+DBTR19_D: .long 0x00000040
+DBRNK0_D: .long 0x00000001
+DBPDCNT0_D: .long 0x00000001
+DBPDCNT1_D: .long 0x00000001
+DBPDCNT2_D: .long 0x00000000
+DBPDCNT3_D: .long 0x00004010
+DBPDLCK_D: .long 0x0000a55a
+DBPDRGA_D: .long 0x00000028
+DBPDRGD_D: .long 0x00017100
+
+DBADJ0_D: .long 0x00000000
+DBADJ1_D: .long 0x00000000
+DBADJ2_D: .long 0x18061806
+DBRFCNF0_D: .long 0x000001ff
+DBRFCNF1_D: .long 0x08001000
+DBRFCNF2_D: .long 0x00000000
+DBCALCNF_D: .long 0x0000ffff
+DBRFEN_D: .long 0x00000001
+DBACEN_D: .long 0x00000001
+
+ .align 2
+exit_ddr:
+#if defined(CONFIG_SH_32BIT)
+ /*------- set PMB -------*/
+ write32 PASCR_A, PASCR_29BIT_D
+ write32 MMUCR_A, MMUCR_D
+
+ /*****************************************************************
+ * ent virt phys v sz c wt
+ * 0 0xa0000000 0x00000000 1 128M 0 1
+ * 1 0xa8000000 0x48000000 1 128M 0 1
+ * 5 0x88000000 0x48000000 1 128M 1 1
+ */
+ write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
+ write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
+ write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
+ write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
+ write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
+ write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
+
+ write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
+
+ write32 PASCR_A, PASCR_INIT
+ mov.l DUMMY_ADDR, r0
+ icbi @r0
+#endif /* if defined(CONFIG_SH_32BIT) */
+
+exit_pmb:
+ /* CPU is running on ILRAM? */
+ mov r14, r0
+ tst #1, r0
+ bt 1f
+
+ mov.l _stack_ilram, r15
+ mov.l _spiboot_main, r0
+100: bsrf r0
+ nop
+
+ .align 2
+_spiboot_main: .long (spiboot_main - (100b + 4))
+_stack_ilram: .long 0xe5204000
+
+1:
+ write32 CCR_A, CCR_D
+
+ rts
+ nop
+
+ .align 2
+
+#if defined(CONFIG_SH_32BIT)
+/*------- set PMB -------*/
+PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
+PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
+PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
+PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
+PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
+PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
+PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
+PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
+PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
+PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
+PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
+PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
+PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
+PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
+PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
+PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
+
+PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
+PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
+PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
+PMB_ADDR_NOT_USE_D: .long 0x00000000
+
+PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
+PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
+PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
+
+/* ppn ub v s1 s0 c wt */
+PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
+
+PASCR_A: .long 0xff000070
+DUMMY_ADDR: .long 0xa0000000
+PASCR_29BIT_D: .long 0x00000000
+PASCR_INIT: .long 0x80000080
+MMUCR_A: .long 0xff000010
+MMUCR_D: .long 0x00000004 /* clear ITLB */
+#endif /* CONFIG_SH_32BIT */
+
+CCR_A: .long CCR
+CCR_D: .long CCR_CACHE_INIT
diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c
new file mode 100644
index 0000000..3aad532
--- /dev/null
+++ b/board/renesas/sh7752evb/sh7752evb.c
@@ -0,0 +1,315 @@
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmc.h>
+#include <spi.h>
+#include <spi_flash.h>
+
+int checkboard(void)
+{
+ puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
+
+ return 0;
+}
+
+static void init_gpio(void)
+{
+ struct gpio_regs *gpio = GPIO_BASE;
+ struct sermux_regs *sermux = SERMUX_BASE;
+
+ /* GPIO */
+ writew(0x0000, &gpio->pacr); /* GETHER */
+ writew(0x0001, &gpio->pbcr); /* INTC */
+ writew(0x0000, &gpio->pccr); /* PWMU, INTC */
+ writew(0xeaff, &gpio->pecr); /* GPIO */
+ writew(0x0000, &gpio->pfcr); /* WDT */
+ writew(0x0000, &gpio->phcr); /* SPI1 */
+ writew(0x0000, &gpio->picr); /* SDHI */
+ writew(0x0003, &gpio->pkcr); /* SerMux */
+ writew(0x0000, &gpio->plcr); /* SerMux */
+ writew(0x0000, &gpio->pmcr); /* RIIC */
+ writew(0x0000, &gpio->pncr); /* USB, SGPIO */
+ writew(0x0000, &gpio->pocr); /* SGPIO */
+ writew(0xd555, &gpio->pqcr); /* GPIO */
+ writew(0x0000, &gpio->prcr); /* RIIC */
+ writew(0x0000, &gpio->pscr); /* RIIC */
+ writeb(0x00, &gpio->pudr);
+ writew(0x5555, &gpio->pucr); /* Debug LED */
+ writew(0x0000, &gpio->pvcr); /* RSPI */
+ writew(0x0000, &gpio->pwcr); /* EVC */
+ writew(0x0000, &gpio->pxcr); /* LBSC */
+ writew(0x0000, &gpio->pycr); /* LBSC */
+ writew(0x0000, &gpio->pzcr); /* eMMC */
+ writew(0xfe00, &gpio->psel0);
+ writew(0xff00, &gpio->psel3);
+ writew(0x771f, &gpio->psel4);
+ writew(0x00ff, &gpio->psel6);
+ writew(0xfc00, &gpio->psel7);
+
+ writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
+}
+
+static void init_usb_phy(void)
+{
+ struct usb_common_regs *common0 = USB0_COMMON_BASE;
+ struct usb_common_regs *common1 = USB1_COMMON_BASE;
+ struct usb0_phy_regs *phy = USB0_PHY_BASE;
+ struct usb1_port_regs *port = USB1_PORT_BASE;
+ struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
+
+ writew(0x0100, &phy->reset); /* set reset */
+ /* port0 = USB0, port1 = USB1 */
+ writew(0x0002, &phy->portsel);
+ writel(0x0001, &port->port1sel); /* port1 = Host */
+ writew(0x0111, &phy->reset); /* clear reset */
+
+ writew(0x4000, &common0->suspmode);
+ writew(0x4000, &common1->suspmode);
+
+#if defined(__LITTLE_ENDIAN)
+ writel(0x00000000, &align->ehcidatac);
+ writel(0x00000000, &align->ohcidatac);
+#endif
+}
+
+static void init_gether_mdio(void)
+{
+ struct gpio_regs *gpio = GPIO_BASE;
+
+ writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
+ writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
+}
+
+static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
+{
+ struct ether_mac_regs *ether;
+ unsigned char mac[6];
+ unsigned long val;
+
+ eth_parse_enetaddr(mac_string, mac);
+
+ if (!channel)
+ ether = GETHER0_MAC_BASE;
+ else
+ ether = GETHER1_MAC_BASE;
+
+ val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+ writel(val, ðer->mahr);
+ val = (mac[4] << 8) | mac[5];
+ writel(val, ðer->malr);
+}
+
+/*****************************************************************
+ * This PMB must be set on this timing. The lowlevel_init is run on
+ * Area 0(phys 0x00000000), so we have to map it.
+ *
+ * The new PMB table is following:
+ * ent virt phys v sz c wt
+ * 0 0xa0000000 0x40000000 1 128M 0 1
+ * 1 0xa8000000 0x48000000 1 128M 0 1
+ * 2 0xb0000000 0x50000000 1 128M 0 1
+ * 3 0xb8000000 0x58000000 1 128M 0 1
+ * 4 0x80000000 0x40000000 1 128M 1 1
+ * 5 0x88000000 0x48000000 1 128M 1 1
+ * 6 0x90000000 0x50000000 1 128M 1 1
+ * 7 0x98000000 0x58000000 1 128M 1 1
+ */
+static void set_pmb_on_board_init(void)
+{
+ struct mmu_regs *mmu = MMU_BASE;
+
+ /* clear ITLB */
+ writel(0x00000004, &mmu->mmucr);
+
+ /* delete PMB for SPIBOOT */
+ writel(0, PMB_ADDR_BASE(0));
+ writel(0, PMB_DATA_BASE(0));
+
+ /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
+ /* ppn ub v s1 s0 c wt */
+ writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
+ writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
+ writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
+ writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
+ writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
+ writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
+ writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
+ writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
+ writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
+ writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
+ writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
+ writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
+}
+
+int board_init(void)
+{
+ init_gpio();
+ set_pmb_on_board_init();
+
+ init_usb_phy();
+ init_gether_mdio();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ struct gpio_regs *gpio = GPIO_BASE;
+
+ writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
+ writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
+ udelay(1);
+ writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
+ udelay(200);
+
+ return mmcif_mmc_init();
+}
+
+static int get_sh_eth_mac_raw(unsigned char *buf, int size)
+{
+ struct spi_flash *spi;
+ int ret;
+
+ spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (spi == NULL) {
+ printf("%s: spi_flash probe failed.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
+ if (ret) {
+ printf("%s: spi_flash read failed.\n", __func__);
+ spi_flash_free(spi);
+ return 1;
+ }
+ spi_flash_free(spi);
+
+ return 0;
+}
+
+static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
+{
+ memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
+ SH7752EVB_ETHERNET_MAC_SIZE);
+ mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
+
+ return 0;
+}
+
+static void init_ethernet_mac(void)
+{
+ char mac_string[64];
+ char env_string[64];
+ int i;
+ unsigned char *buf;
+
+ buf = malloc(256);
+ if (!buf) {
+ printf("%s: malloc failed.\n", __func__);
+ return;
+ }
+ get_sh_eth_mac_raw(buf, 256);
+
+ /* Gigabit Ethernet */
+ for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
+ get_sh_eth_mac(i, mac_string, buf);
+ if (i == 0)
+ setenv("ethaddr", mac_string);
+ else {
+ sprintf(env_string, "eth%daddr", i);
+ setenv(env_string, mac_string);
+ }
+ set_mac_to_sh_giga_eth_register(i, mac_string);
+ }
+
+ free(buf);
+}
+
+int board_late_init(void)
+{
+ init_ethernet_mac();
+
+ return 0;
+}
+
+int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i, ret;
+ char mac_string[256];
+ struct spi_flash *spi;
+ unsigned char *buf;
+
+ if (argc != 3) {
+ buf = malloc(256);
+ if (!buf) {
+ printf("%s: malloc failed.\n", __func__);
+ return 1;
+ }
+
+ get_sh_eth_mac_raw(buf, 256);
+
+ /* print current MAC address */
+ for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
+ get_sh_eth_mac(i, mac_string, buf);
+ printf("GETHERC ch%d = %s\n", i, mac_string);
+ }
+ free(buf);
+ return 0;
+ }
+
+ /* new setting */
+ memset(mac_string, 0xff, sizeof(mac_string));
+ sprintf(mac_string, "%s\t%s",
+ argv[1], argv[2]);
+
+ /* write MAC data to SPI rom */
+ spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!spi) {
+ printf("%s: spi_flash probe failed.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
+ SH7752EVB_SPI_SECTOR_SIZE);
+ if (ret) {
+ printf("%s: spi_flash erase failed.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
+ sizeof(mac_string), mac_string);
+ if (ret) {
+ printf("%s: spi_flash write failed.\n", __func__);
+ spi_flash_free(spi);
+ return 1;
+ }
+ spi_flash_free(spi);
+
+ puts("The writing of the MAC address to SPI ROM was completed.\n");
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ write_mac, 3, 1, do_write_mac,
+ "write MAC address for GETHERC",
+ "[GETHERC ch0] [GETHERC ch1]\n"
+);
diff --git a/board/renesas/sh7752evb/spi-boot.c b/board/renesas/sh7752evb/spi-boot.c
new file mode 100644
index 0000000..91565d4
--- /dev/null
+++ b/board/renesas/sh7752evb/spi-boot.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License. See the file "COPYING.LIB" in the main
+ * directory of this archive for more details.
+ */
+
+#include <common.h>
+
+#define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPI_ADDR 0x00000000
+#define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN
+#define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE
+
+#define SPIWDMADR 0xFE001018
+#define SPIWDMCNTR 0xFE001020
+#define SPIDMCOR 0xFE001028
+#define SPIDMINTSR 0xFE001188
+#define SPIDMINTMR 0xFE001190
+
+#define SPIDMINTSR_DMEND 0x00000004
+
+#define TBR 0xFE002000
+#define RBR 0xFE002000
+
+#define CR1 0xFE002008
+#define CR2 0xFE002010
+#define CR3 0xFE002018
+#define CR4 0xFE002020
+
+/* CR1 */
+#define SPI_TBE 0x80
+#define SPI_TBF 0x40
+#define SPI_RBE 0x20
+#define SPI_RBF 0x10
+#define SPI_PFONRD 0x08
+#define SPI_SSDB 0x04
+#define SPI_SSD 0x02
+#define SPI_SSA 0x01
+
+/* CR2 */
+#define SPI_RSTF 0x80
+#define SPI_LOOPBK 0x40
+#define SPI_CPOL 0x20
+#define SPI_CPHA 0x10
+#define SPI_L1M0 0x08
+
+/* CR4 */
+#define SPI_TBEI 0x80
+#define SPI_TBFI 0x40
+#define SPI_RBEI 0x20
+#define SPI_RBFI 0x10
+#define SPI_SpiS0 0x02
+#define SPI_SSS 0x01
+
+#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
+#define spi_read(addr) (*(volatile unsigned long *)(addr))
+
+/* M25P80 */
+#define M25_READ 0x03
+
+#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
+static void __uses_spiboot2 spi_reset(void)
+{
+ int timeout = 0x00100000;
+
+ /* Make sure the last transaction is finalized */
+ spi_write(0x00, CR3);
+ spi_write(0x02, CR1);
+ while (!(spi_read(CR4) & SPI_SpiS0)) {
+ if (timeout-- < 0)
+ break;
+ }
+ spi_write(0x00, CR1);
+
+ spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
+ spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
+
+ spi_write(0, SPIDMCOR);
+}
+
+static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
+ unsigned long len)
+{
+ spi_write(M25_READ, TBR);
+ spi_write((addr >> 16) & 0xFF, TBR);
+ spi_write((addr >> 8) & 0xFF, TBR);
+ spi_write(addr & 0xFF, TBR);
+
+ spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
+ spi_write((unsigned long)buf, SPIWDMADR);
+ spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
+ spi_write(1, SPIDMCOR);
+
+ spi_write(0xff, CR3);
+ spi_write(spi_read(CR1) | SPI_SSDB, CR1);
+ spi_write(spi_read(CR1) | SPI_SSA, CR1);
+
+ while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
+ ;
+
+ /* Nagate SP0-SS0 */
+ spi_write(0, CR1);
+}
+
+void __uses_spiboot2 spiboot_main(void)
+{
+ void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
+
+ spi_reset();
+ spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
+ CONFIG_SPI_LENGTH);
+
+ _start();
+}
diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds
new file mode 100644
index 0000000..053df64
--- /dev/null
+++ b/board/renesas/sh7752evb/u-boot.lds
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2012
+ * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ * entry and reloct_dst will be provided via ldflags
+ */
+ . = .;
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ KEEP(arch/sh/cpu/sh4/start.o (.text))
+ *(.spiboot1.text)
+ *(.spiboot2.text)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenv)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss (NOLOAD) :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (__bss_end = .);
+}
diff --git a/board/renesas/sh7753evb/Kconfig b/board/renesas/sh7753evb/Kconfig
new file mode 100644
index 0000000..be88924
--- /dev/null
+++ b/board/renesas/sh7753evb/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SH7753EVB
+
+config SYS_BOARD
+ default "sh7753evb"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "sh7753evb"
+
+endif
diff --git a/board/renesas/sh7753evb/MAINTAINERS b/board/renesas/sh7753evb/MAINTAINERS
new file mode 100644
index 0000000..b6c85ee
--- /dev/null
+++ b/board/renesas/sh7753evb/MAINTAINERS
@@ -0,0 +1,6 @@
+SH7753EVB BOARD
+#M: -
+S: Maintained
+F: board/renesas/sh7753evb/
+F: include/configs/sh7753evb.h
+F: configs/sh7753evb_defconfig
diff --git a/board/renesas/sh7753evb/Makefile b/board/renesas/sh7753evb/Makefile
new file mode 100644
index 0000000..f7c8e94
--- /dev/null
+++ b/board/renesas/sh7753evb/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := sh7753evb.o spi-boot.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/sh7753evb/lowlevel_init.S b/board/renesas/sh7753evb/lowlevel_init.S
new file mode 100644
index 0000000..21987a5
--- /dev/null
+++ b/board/renesas/sh7753evb/lowlevel_init.S
@@ -0,0 +1,416 @@
+/*
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+.macro or32, addr, data
+ mov.l \addr, r1
+ mov.l \data, r0
+ mov.l @r1, r2
+ or r2, r0
+ mov.l r0, @r1
+.endm
+
+.macro wait_DBCMD
+ mov.l DBWAIT_A, r0
+ mov.l @r0, r1
+.endm
+
+ .global lowlevel_init
+ .section .spiboot1.text
+ .align 2
+
+lowlevel_init:
+ mov #0, r14
+ mova 2f, r0
+ mov.l PC_MASK, r1
+ tst r0, r1
+ bf 2f
+
+ bra exit_pmb
+ nop
+
+ .align 2
+
+/* If CPU runs on SDRAM (PC=0x5???????) or not. */
+PC_MASK: .long 0x20000000
+
+2:
+ mov #1, r14
+
+ mov.l EXPEVT_A, r0
+ mov.l @r0, r0
+ mov.l EXPEVT_POWER_ON_RESET, r1
+ cmp/eq r0, r1
+ bt 1f
+
+ /*
+ * If EXPEVT value is manual reset or tlb multipul-hit,
+ * initialization of DBSC3 is not necessary.
+ */
+ bra exit_ddr
+ nop
+
+1:
+ /*------- Reset -------*/
+ write32 MRSTCR0_A, MRSTCR0_D
+ write32 MRSTCR1_A, MRSTCR1_D
+
+ /* For Core Reset */
+ mov.l DBACEN_A, r0
+ mov.l @r0, r0
+ cmp/eq #0, r0
+ bt 3f
+
+ /*
+ * If DBACEN == 1(DBSC was already enabled), we have to avoid the
+ * initialization of DDR3-SDRAM.
+ */
+ bra exit_ddr
+ nop
+
+3:
+ /*------- DBSC3 -------*/
+ /* oscillation stabilization time */
+ wait_timer WAIT_OSC_TIME
+
+ /* step 3 */
+ write32 DBKIND_A, DBKIND_D
+
+ /* step 4 */
+ write32 DBCONF_A, DBCONF_D
+ write32 DBTR0_A, DBTR0_D
+ write32 DBTR1_A, DBTR1_D
+ write32 DBTR2_A, DBTR2_D
+ write32 DBTR3_A, DBTR3_D
+ write32 DBTR4_A, DBTR4_D
+ write32 DBTR5_A, DBTR5_D
+ write32 DBTR6_A, DBTR6_D
+ write32 DBTR7_A, DBTR7_D
+ write32 DBTR8_A, DBTR8_D
+ write32 DBTR9_A, DBTR9_D
+ write32 DBTR10_A, DBTR10_D
+ write32 DBTR11_A, DBTR11_D
+ write32 DBTR12_A, DBTR12_D
+ write32 DBTR13_A, DBTR13_D
+ write32 DBTR14_A, DBTR14_D
+ write32 DBTR15_A, DBTR15_D
+ write32 DBTR16_A, DBTR16_D
+ write32 DBTR17_A, DBTR17_D
+ write32 DBTR18_A, DBTR18_D
+ write32 DBTR19_A, DBTR19_D
+ write32 DBRNK0_A, DBRNK0_D
+ write32 DBADJ0_A, DBADJ0_D
+ write32 DBADJ2_A, DBADJ2_D
+
+ /* step 5 */
+ write32 DBCMD_A, DBCMD_RSTL_VAL
+ wait_timer WAIT_30US
+
+ /* step 6 */
+ write32 DBCMD_A, DBCMD_PDEN_VAL
+
+ /* step 7 */
+ write32 DBPDCNT3_A, DBPDCNT3_D
+
+ /* step 8 */
+ write32 DBPDCNT1_A, DBPDCNT1_D
+ write32 DBPDCNT2_A, DBPDCNT2_D
+ write32 DBPDLCK_A, DBPDLCK_D
+ write32 DBPDRGA_A, DBPDRGA_D
+ write32 DBPDRGD_A, DBPDRGD_D
+
+ /* step 9 */
+ wait_timer WAIT_30US
+
+ /* step 10 */
+ write32 DBPDCNT0_A, DBPDCNT0_D
+
+ /* step 11 */
+ wait_timer WAIT_30US
+ wait_timer WAIT_30US
+
+ /* step 12 */
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ wait_DBCMD
+
+ /* step 13 */
+ write32 DBCMD_A, DBCMD_RSTH_VAL
+ wait_DBCMD
+
+ /* step 14 */
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+
+ /* step 15 */
+ write32 DBCMD_A, DBCMD_PDXT_VAL
+
+ /* step 16 */
+ write32 DBCMD_A, DBCMD_MRS2_VAL
+
+ /* step 17 */
+ write32 DBCMD_A, DBCMD_MRS3_VAL
+
+ /* step 18 */
+ write32 DBCMD_A, DBCMD_MRS1_VAL
+
+ /* step 19 */
+ write32 DBCMD_A, DBCMD_MRS0_VAL
+ write32 DBPDNCNF_A, DBPDNCNF_D
+
+ /* step 20 */
+ write32 DBCMD_A, DBCMD_ZQCL_VAL
+
+ write32 DBCMD_A, DBCMD_REF_VAL
+ write32 DBCMD_A, DBCMD_REF_VAL
+ wait_DBCMD
+
+ /* step 21 */
+ write32 DBCALTR_A, DBCALTR_D
+
+ /* step 22 */
+ write32 DBRFCNF0_A, DBRFCNF0_D
+ write32 DBRFCNF1_A, DBRFCNF1_D
+ write32 DBRFCNF2_A, DBRFCNF2_D
+
+ /* step 23 */
+ write32 DBCALCNF_A, DBCALCNF_D
+
+ /* step 24 */
+ write32 DBRFEN_A, DBRFEN_D
+ write32 DBCMD_A, DBCMD_SRXT_VAL
+
+ /* step 25 */
+ write32 DBACEN_A, DBACEN_D
+
+ /* step 26 */
+ wait_DBCMD
+
+ bra exit_ddr
+ nop
+
+ .align 2
+
+EXPEVT_A: .long 0xff000024
+EXPEVT_POWER_ON_RESET: .long 0x00000000
+
+/*------- Reset -------*/
+MRSTCR0_A: .long 0xffd50030
+MRSTCR0_D: .long 0xfe1ffe7f
+MRSTCR1_A: .long 0xffd50034
+MRSTCR1_D: .long 0xfff3ffff
+
+/*------- DBSC3 -------*/
+DBCMD_A: .long 0xfe800018
+DBKIND_A: .long 0xfe800020
+DBCONF_A: .long 0xfe800024
+DBTR0_A: .long 0xfe800040
+DBTR1_A: .long 0xfe800044
+DBTR2_A: .long 0xfe800048
+DBTR3_A: .long 0xfe800050
+DBTR4_A: .long 0xfe800054
+DBTR5_A: .long 0xfe800058
+DBTR6_A: .long 0xfe80005c
+DBTR7_A: .long 0xfe800060
+DBTR8_A: .long 0xfe800064
+DBTR9_A: .long 0xfe800068
+DBTR10_A: .long 0xfe80006c
+DBTR11_A: .long 0xfe800070
+DBTR12_A: .long 0xfe800074
+DBTR13_A: .long 0xfe800078
+DBTR14_A: .long 0xfe80007c
+DBTR15_A: .long 0xfe800080
+DBTR16_A: .long 0xfe800084
+DBTR17_A: .long 0xfe800088
+DBTR18_A: .long 0xfe80008c
+DBTR19_A: .long 0xfe800090
+DBRNK0_A: .long 0xfe800100
+DBPDCNT0_A: .long 0xfe800200
+DBPDCNT1_A: .long 0xfe800204
+DBPDCNT2_A: .long 0xfe800208
+DBPDCNT3_A: .long 0xfe80020c
+DBPDLCK_A: .long 0xfe800280
+DBPDRGA_A: .long 0xfe800290
+DBPDRGD_A: .long 0xfe8002a0
+DBADJ0_A: .long 0xfe8000c0
+DBADJ2_A: .long 0xfe8000c8
+DBRFCNF0_A: .long 0xfe8000e0
+DBRFCNF1_A: .long 0xfe8000e4
+DBRFCNF2_A: .long 0xfe8000e8
+DBCALCNF_A: .long 0xfe8000f4
+DBRFEN_A: .long 0xfe800014
+DBACEN_A: .long 0xfe800010
+DBWAIT_A: .long 0xfe80001c
+DBCALTR_A: .long 0xfe8000f8
+DBPDNCNF_A: .long 0xfe800180
+
+WAIT_OSC_TIME: .long 6000
+WAIT_30US: .long 13333
+
+DBCMD_RSTL_VAL: .long 0x20000000
+DBCMD_PDEN_VAL: .long 0x1000d73c
+DBCMD_WAIT_VAL: .long 0x0000d73c
+DBCMD_RSTH_VAL: .long 0x2100d73c
+DBCMD_PDXT_VAL: .long 0x110000c8
+DBCMD_MRS0_VAL: .long 0x28000930
+DBCMD_MRS1_VAL: .long 0x29000004
+DBCMD_MRS2_VAL: .long 0x2a000008
+DBCMD_MRS3_VAL: .long 0x2b000000
+DBCMD_ZQCL_VAL: .long 0x03000200
+DBCMD_REF_VAL: .long 0x0c000000
+DBCMD_SRXT_VAL: .long 0x19000000
+DBKIND_D: .long 0x00000007
+DBCONF_D: .long 0x0f030a01
+DBTR0_D: .long 0x00000007
+DBTR1_D: .long 0x00000006
+DBTR2_D: .long 0x00000000
+DBTR3_D: .long 0x00000007
+DBTR4_D: .long 0x00070007
+DBTR5_D: .long 0x0000001b
+DBTR6_D: .long 0x00000014
+DBTR7_D: .long 0x00000004
+DBTR8_D: .long 0x00000014
+DBTR9_D: .long 0x00000004
+DBTR10_D: .long 0x00000008
+DBTR11_D: .long 0x00000007
+DBTR12_D: .long 0x0000000e
+DBTR13_D: .long 0x000000a0
+DBTR14_D: .long 0x00060006
+DBTR15_D: .long 0x00000003
+DBTR16_D: .long 0x00160002
+DBTR17_D: .long 0x000c0000
+DBTR18_D: .long 0x00000200
+DBTR19_D: .long 0x00000040
+DBRNK0_D: .long 0x00000001
+DBPDCNT0_D: .long 0x00000001
+DBPDCNT1_D: .long 0x00000001
+DBPDCNT2_D: .long 0x00000000
+DBPDCNT3_D: .long 0x00004010
+DBPDLCK_D: .long 0x0000a55a
+DBPDRGA_D: .long 0x00000028
+DBPDRGD_D: .long 0x00017100
+
+DBADJ0_D: .long 0x00010000
+DBADJ2_D: .long 0x18061806
+DBRFCNF0_D: .long 0x000001ff
+DBRFCNF1_D: .long 0x00081040
+DBRFCNF2_D: .long 0x00000000
+DBCALCNF_D: .long 0x0000ffff
+DBRFEN_D: .long 0x00000001
+DBACEN_D: .long 0x00000001
+DBCALTR_D: .long 0x08200820
+DBPDNCNF_D: .long 0x00000001
+
+ .align 2
+exit_ddr:
+#if defined(CONFIG_SH_32BIT)
+ /*------- set PMB -------*/
+ write32 PASCR_A, PASCR_29BIT_D
+ write32 MMUCR_A, MMUCR_D
+
+ /*****************************************************************
+ * ent virt phys v sz c wt
+ * 0 0xa0000000 0x00000000 1 128M 0 1
+ * 1 0xa8000000 0x48000000 1 128M 0 1
+ * 5 0x88000000 0x48000000 1 128M 1 1
+ */
+ write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
+ write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
+ write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
+ write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
+ write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
+ write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
+
+ write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
+
+ write32 PASCR_A, PASCR_INIT
+ mov.l DUMMY_ADDR, r0
+ icbi @r0
+#endif /* if defined(CONFIG_SH_32BIT) */
+
+exit_pmb:
+ /* CPU is running on ILRAM? */
+ mov r14, r0
+ tst #1, r0
+ bt 1f
+
+ mov.l _stack_ilram, r15
+ mov.l _spiboot_main, r0
+100: bsrf r0
+ nop
+
+ .align 2
+_spiboot_main: .long (spiboot_main - (100b + 4))
+_stack_ilram: .long 0xe5204000
+
+1:
+ write32 CCR_A, CCR_D
+
+ rts
+ nop
+
+ .align 2
+
+#if defined(CONFIG_SH_32BIT)
+/*------- set PMB -------*/
+PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
+PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
+PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
+PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
+PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
+PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
+PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
+PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
+PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
+PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
+PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
+PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
+PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
+PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
+PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
+PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
+
+PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
+PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
+PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
+PMB_ADDR_NOT_USE_D: .long 0x00000000
+
+PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
+PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
+PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
+
+/* ppn ub v s1 s0 c wt */
+PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
+
+PASCR_A: .long 0xff000070
+DUMMY_ADDR: .long 0xa0000000
+PASCR_29BIT_D: .long 0x00000000
+PASCR_INIT: .long 0x80000080
+MMUCR_A: .long 0xff000010
+MMUCR_D: .long 0x00000004 /* clear ITLB */
+#endif /* CONFIG_SH_32BIT */
+
+CCR_A: .long CCR
+CCR_D: .long CCR_CACHE_INIT
diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c
new file mode 100644
index 0000000..9f64945
--- /dev/null
+++ b/board/renesas/sh7753evb/sh7753evb.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmc.h>
+#include <spi.h>
+#include <spi_flash.h>
+
+int checkboard(void)
+{
+ puts("BOARD: SH7753 EVB\n");
+
+ return 0;
+}
+
+static void init_gpio(void)
+{
+ struct gpio_regs *gpio = GPIO_BASE;
+ struct sermux_regs *sermux = SERMUX_BASE;
+
+ /* GPIO */
+ writew(0x0000, &gpio->pacr); /* GETHER */
+ writew(0x0001, &gpio->pbcr); /* INTC */
+ writew(0x0000, &gpio->pccr); /* PWMU, INTC */
+ writew(0x0000, &gpio->pdcr); /* SPI0 */
+ writew(0xeaff, &gpio->pecr); /* GPIO */
+ writew(0x0000, &gpio->pfcr); /* WDT */
+ writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */
+ writew(0x0000, &gpio->phcr); /* SPI1 */
+ writew(0x0000, &gpio->picr); /* SDHI */
+ writew(0x0000, &gpio->pjcr); /* SCIF4 */
+ writew(0x0003, &gpio->pkcr); /* SerMux */
+ writew(0x0000, &gpio->plcr); /* SerMux */
+ writew(0x0000, &gpio->pmcr); /* RIIC */
+ writew(0x0000, &gpio->pncr); /* USB, SGPIO */
+ writew(0x0000, &gpio->pocr); /* SGPIO */
+ writew(0xd555, &gpio->pqcr); /* GPIO */
+ writew(0x0000, &gpio->prcr); /* RIIC */
+ writew(0x0000, &gpio->pscr); /* RIIC */
+ writew(0x0000, &gpio->ptcr); /* STATUS */
+ writeb(0x00, &gpio->pudr);
+ writew(0x5555, &gpio->pucr); /* Debug LED */
+ writew(0x0000, &gpio->pvcr); /* RSPI */
+ writew(0x0000, &gpio->pwcr); /* EVC */
+ writew(0x0000, &gpio->pxcr); /* LBSC */
+ writew(0x0000, &gpio->pycr); /* LBSC */
+ writew(0x0000, &gpio->pzcr); /* eMMC */
+ writew(0xfe00, &gpio->psel0);
+ writew(0x0000, &gpio->psel1);
+ writew(0x3000, &gpio->psel2);
+ writew(0xff00, &gpio->psel3);
+ writew(0x771f, &gpio->psel4);
+ writew(0x0ffc, &gpio->psel5);
+ writew(0x00ff, &gpio->psel6);
+ writew(0xfc00, &gpio->psel7);
+
+ writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
+}
+
+static void init_usb_phy(void)
+{
+ struct usb_common_regs *common0 = USB0_COMMON_BASE;
+ struct usb_common_regs *common1 = USB1_COMMON_BASE;
+ struct usb0_phy_regs *phy = USB0_PHY_BASE;
+ struct usb1_port_regs *port = USB1_PORT_BASE;
+ struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
+
+ writew(0x0100, &phy->reset); /* set reset */
+ /* port0 = USB0, port1 = USB1 */
+ writew(0x0002, &phy->portsel);
+ writel(0x0001, &port->port1sel); /* port1 = Host */
+ writew(0x0111, &phy->reset); /* clear reset */
+
+ writew(0x4000, &common0->suspmode);
+ writew(0x4000, &common1->suspmode);
+
+#if defined(__LITTLE_ENDIAN)
+ writel(0x00000000, &align->ehcidatac);
+ writel(0x00000000, &align->ohcidatac);
+#endif
+}
+
+static void init_gether_mdio(void)
+{
+ struct gpio_regs *gpio = GPIO_BASE;
+
+ writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
+ writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
+}
+
+static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
+{
+ struct ether_mac_regs *ether;
+ unsigned char mac[6];
+ unsigned long val;
+
+ eth_parse_enetaddr(mac_string, mac);
+
+ if (!channel)
+ ether = GETHER0_MAC_BASE;
+ else
+ ether = GETHER1_MAC_BASE;
+
+ val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+ writel(val, ðer->mahr);
+ val = (mac[4] << 8) | mac[5];
+ writel(val, ðer->malr);
+}
+
+/*****************************************************************
+ * This PMB must be set on this timing. The lowlevel_init is run on
+ * Area 0(phys 0x00000000), so we have to map it.
+ *
+ * The new PMB table is following:
+ * ent virt phys v sz c wt
+ * 0 0xa0000000 0x40000000 1 128M 0 1
+ * 1 0xa8000000 0x48000000 1 128M 0 1
+ * 2 0xb0000000 0x50000000 1 128M 0 1
+ * 3 0xb8000000 0x58000000 1 128M 0 1
+ * 4 0x80000000 0x40000000 1 128M 1 1
+ * 5 0x88000000 0x48000000 1 128M 1 1
+ * 6 0x90000000 0x50000000 1 128M 1 1
+ * 7 0x98000000 0x58000000 1 128M 1 1
+ */
+static void set_pmb_on_board_init(void)
+{
+ struct mmu_regs *mmu = MMU_BASE;
+
+ /* clear ITLB */
+ writel(0x00000004, &mmu->mmucr);
+
+ /* delete PMB for SPIBOOT */
+ writel(0, PMB_ADDR_BASE(0));
+ writel(0, PMB_DATA_BASE(0));
+
+ /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
+ /* ppn ub v s1 s0 c wt */
+ writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
+ writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
+ writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
+ writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
+ writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
+ writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
+ writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
+ writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
+ writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
+ writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
+ writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
+ writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
+}
+
+int board_init(void)
+{
+ struct gether_control_regs *gether = GETHER_CONTROL_BASE;
+
+ init_gpio();
+ set_pmb_on_board_init();
+
+ /* Sets TXnDLY to B'010 */
+ writel(0x00000202, &gether->gbecont);
+
+ init_usb_phy();
+ init_gether_mdio();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ struct gpio_regs *gpio = GPIO_BASE;
+
+ writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
+ writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
+ udelay(1);
+ writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
+ udelay(200);
+
+ return mmcif_mmc_init();
+}
+
+static int get_sh_eth_mac_raw(unsigned char *buf, int size)
+{
+ struct spi_flash *spi;
+ int ret;
+
+ spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (spi == NULL) {
+ printf("%s: spi_flash probe failed.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
+ if (ret) {
+ printf("%s: spi_flash read failed.\n", __func__);
+ spi_flash_free(spi);
+ return 1;
+ }
+ spi_flash_free(spi);
+
+ return 0;
+}
+
+static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
+{
+ memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
+ SH7753EVB_ETHERNET_MAC_SIZE);
+ mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
+
+ return 0;
+}
+
+static void init_ethernet_mac(void)
+{
+ char mac_string[64];
+ char env_string[64];
+ int i;
+ unsigned char *buf;
+
+ buf = malloc(256);
+ if (!buf) {
+ printf("%s: malloc failed.\n", __func__);
+ return;
+ }
+ get_sh_eth_mac_raw(buf, 256);
+
+ /* Gigabit Ethernet */
+ for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
+ get_sh_eth_mac(i, mac_string, buf);
+ if (i == 0)
+ setenv("ethaddr", mac_string);
+ else {
+ sprintf(env_string, "eth%daddr", i);
+ setenv(env_string, mac_string);
+ }
+ set_mac_to_sh_giga_eth_register(i, mac_string);
+ }
+
+ free(buf);
+}
+
+int board_late_init(void)
+{
+ init_ethernet_mac();
+
+ return 0;
+}
+
+int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i, ret;
+ char mac_string[256];
+ struct spi_flash *spi;
+ unsigned char *buf;
+
+ if (argc != 3) {
+ buf = malloc(256);
+ if (!buf) {
+ printf("%s: malloc failed.\n", __func__);
+ return 1;
+ }
+
+ get_sh_eth_mac_raw(buf, 256);
+
+ /* print current MAC address */
+ for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
+ get_sh_eth_mac(i, mac_string, buf);
+ printf("GETHERC ch%d = %s\n", i, mac_string);
+ }
+ free(buf);
+ return 0;
+ }
+
+ /* new setting */
+ memset(mac_string, 0xff, sizeof(mac_string));
+ sprintf(mac_string, "%s\t%s",
+ argv[1], argv[2]);
+
+ /* write MAC data to SPI rom */
+ spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!spi) {
+ printf("%s: spi_flash probe failed.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
+ SH7753EVB_SPI_SECTOR_SIZE);
+ if (ret) {
+ printf("%s: spi_flash erase failed.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
+ sizeof(mac_string), mac_string);
+ if (ret) {
+ printf("%s: spi_flash write failed.\n", __func__);
+ spi_flash_free(spi);
+ return 1;
+ }
+ spi_flash_free(spi);
+
+ puts("The writing of the MAC address to SPI ROM was completed.\n");
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ write_mac, 3, 1, do_write_mac,
+ "write MAC address for GETHERC",
+ "[GETHERC ch0] [GETHERC ch1]\n"
+);
diff --git a/board/renesas/sh7753evb/spi-boot.c b/board/renesas/sh7753evb/spi-boot.c
new file mode 100644
index 0000000..21903d9
--- /dev/null
+++ b/board/renesas/sh7753evb/spi-boot.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#define CONFIG_SPI_ADDR 0x00000000
+#define PHYADDR(_addr) ((_addr & 0x1fffffff) | 0x40000000)
+#define CONFIG_RAM_BOOT_PHYS PHYADDR(CONFIG_SYS_TEXT_BASE)
+
+#define SPIWDMADR 0xFE001018
+#define SPIWDMCNTR 0xFE001020
+#define SPIDMCOR 0xFE001028
+#define SPIDMINTSR 0xFE001188
+#define SPIDMINTMR 0xFE001190
+
+#define SPIDMINTSR_DMEND 0x00000004
+
+#define TBR 0xFE002000
+#define RBR 0xFE002000
+
+#define CR1 0xFE002008
+#define CR2 0xFE002010
+#define CR3 0xFE002018
+#define CR4 0xFE002020
+#define CR7 0xFE002038
+#define CR8 0xFE002040
+
+/* CR1 */
+#define SPI_TBE 0x80
+#define SPI_TBF 0x40
+#define SPI_RBE 0x20
+#define SPI_RBF 0x10
+#define SPI_PFONRD 0x08
+#define SPI_SSDB 0x04
+#define SPI_SSD 0x02
+#define SPI_SSA 0x01
+
+/* CR2 */
+#define SPI_RSTF 0x80
+#define SPI_LOOPBK 0x40
+#define SPI_CPOL 0x20
+#define SPI_CPHA 0x10
+#define SPI_L1M0 0x08
+
+/* CR4 */
+#define SPI_TBEI 0x80
+#define SPI_TBFI 0x40
+#define SPI_RBEI 0x20
+#define SPI_RBFI 0x10
+#define SPI_SpiS0 0x02
+#define SPI_SSS 0x01
+
+/* CR7 */
+#define CR7_IDX_OR12 0x12
+#define OR12_ADDR32 0x00000001
+
+#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
+#define spi_read(addr) (*(volatile unsigned long *)(addr))
+
+/* M25P80 */
+#define M25_READ 0x03
+#define M25_READ_4BYTE 0x13
+
+extern void bss_start(void);
+
+#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
+static void __uses_spiboot2 spi_reset(void)
+{
+ int timeout = 0x00100000;
+
+ /* Make sure the last transaction is finalized */
+ spi_write(0x00, CR3);
+ spi_write(0x02, CR1);
+ while (!(spi_read(CR4) & SPI_SpiS0)) {
+ if (timeout-- < 0)
+ break;
+ }
+ spi_write(0x00, CR1);
+
+ spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
+ spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
+
+ spi_write(0, SPIDMCOR);
+}
+
+static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
+ unsigned long len)
+{
+ spi_write(CR7_IDX_OR12, CR7);
+ if (spi_read(CR8) & OR12_ADDR32) {
+ /* 4-bytes address mode */
+ spi_write(M25_READ_4BYTE, TBR);
+ spi_write((addr >> 24) & 0xFF, TBR); /* ADDR31-24 */
+ } else {
+ /* 3-bytes address mode */
+ spi_write(M25_READ, TBR);
+ }
+ spi_write((addr >> 16) & 0xFF, TBR); /* ADDR23-16 */
+ spi_write((addr >> 8) & 0xFF, TBR); /* ADDR15-8 */
+ spi_write(addr & 0xFF, TBR); /* ADDR7-0 */
+
+ spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
+ spi_write((unsigned long)buf, SPIWDMADR);
+ spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
+ spi_write(1, SPIDMCOR);
+
+ spi_write(0xff, CR3);
+ spi_write(spi_read(CR1) | SPI_SSDB, CR1);
+ spi_write(spi_read(CR1) | SPI_SSA, CR1);
+
+ while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
+ ;
+
+ /* Nagate SP0-SS0 */
+ spi_write(0, CR1);
+}
+
+void __uses_spiboot2 spiboot_main(void)
+{
+ /*
+ * This code rounds len up for SPIWDMCNTR. We should set it to 0 in
+ * lower 5-bits.
+ */
+ void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
+ volatile unsigned long len = (bss_start - _start + 31) & 0xffffffe0;
+
+ spi_reset();
+ spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, len);
+
+ _start();
+}
diff --git a/board/renesas/sh7753evb/u-boot.lds b/board/renesas/sh7753evb/u-boot.lds
new file mode 100644
index 0000000..053df64
--- /dev/null
+++ b/board/renesas/sh7753evb/u-boot.lds
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2012
+ * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ * entry and reloct_dst will be provided via ldflags
+ */
+ . = .;
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ KEEP(arch/sh/cpu/sh4/start.o (.text))
+ *(.spiboot1.text)
+ *(.spiboot2.text)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenv)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss (NOLOAD) :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (__bss_end = .);
+}
diff --git a/board/renesas/sh7757lcr/Kconfig b/board/renesas/sh7757lcr/Kconfig
new file mode 100644
index 0000000..3fba80d
--- /dev/null
+++ b/board/renesas/sh7757lcr/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SH7757LCR
+
+config SYS_BOARD
+ default "sh7757lcr"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "sh7757lcr"
+
+endif
diff --git a/board/renesas/sh7757lcr/MAINTAINERS b/board/renesas/sh7757lcr/MAINTAINERS
new file mode 100644
index 0000000..20aca67
--- /dev/null
+++ b/board/renesas/sh7757lcr/MAINTAINERS
@@ -0,0 +1,6 @@
+SH7757LCR BOARD
+#M: -
+S: Maintained
+F: board/renesas/sh7757lcr/
+F: include/configs/sh7757lcr.h
+F: configs/sh7757lcr_defconfig
diff --git a/board/renesas/sh7757lcr/Makefile b/board/renesas/sh7757lcr/Makefile
new file mode 100644
index 0000000..1fa3992
--- /dev/null
+++ b/board/renesas/sh7757lcr/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2011 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := sh7757lcr.o spi-boot.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/sh7757lcr/README.sh7757lcr b/board/renesas/sh7757lcr/README.sh7757lcr
new file mode 100644
index 0000000..3e9c1c1
--- /dev/null
+++ b/board/renesas/sh7757lcr/README.sh7757lcr
@@ -0,0 +1,77 @@
+========================================
+Renesas R0P7757LC0030RL board
+========================================
+
+This board specification:
+=========================
+
+The R0P7757LC0030RL(board config name:sh7757lcr) has the following device:
+
+ - SH7757 (SH-4A)
+ - DDR3-SDRAM 256MB (with ECC)
+ - SPI ROM 8MB
+ - 2D Graphic controller
+ - Ethernet controller
+ - eMMC 2GB
+
+
+configuration for This board:
+=============================
+
+You can select the configuration as follows:
+
+ - make sh7785lcr_config
+
+
+This board specific command:
+============================
+
+This board has the following its specific command:
+
+ - sh_g200
+ - write_mac
+
+
+1. sh_g200
+
+If we run this command, SH4 can control the G200.
+The default setting is that SH4 cannot control the G200.
+
+
+2. write_mac
+
+You can write MAC address to SPI ROM.
+
+ Usage 1) Write MAC address
+
+ write_mac [ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]
+
+ For example)
+ => write_mac 00:00:87:6c:21:80 00:00:87:6c:21:81 00:00:87:6c:21:82 00:00:87:6c:21:83
+ *) We have to input the command as a single line
+ (without carriage return)
+ *) We have to reset after input the command.
+
+ Usage 2) Show current data
+
+ write_mac
+
+ For example)
+ => write_mac
+ ETHERC ch0 = 00:00:87:6c:21:80
+ ETHERC ch1 = 00:00:87:6c:21:81
+ GETHERC ch0 = 00:00:87:6c:21:82
+ GETHERC ch1 = 00:00:87:6c:21:83
+
+
+Update SPI ROM:
+============================
+
+1. Copy u-boot image to RAM area.
+2. Probe SPI device.
+ => sf probe 0
+ 8192 KiB M25P64 at 0:0 is now current device
+3. Erase SPI ROM.
+ => sf erase 0 80000
+4. Write u-boot image to SPI ROM.
+ => sf write 0x89000000 0 80000
diff --git a/board/renesas/sh7757lcr/lowlevel_init.S b/board/renesas/sh7757lcr/lowlevel_init.S
new file mode 100644
index 0000000..e4c5ea8
--- /dev/null
+++ b/board/renesas/sh7757lcr/lowlevel_init.S
@@ -0,0 +1,546 @@
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+.macro or32, addr, data
+ mov.l \addr, r1
+ mov.l \data, r0
+ mov.l @r1, r2
+ or r2, r0
+ mov.l r0, @r1
+.endm
+
+.macro wait_DBCMD
+ mov.l DBWAIT_A, r0
+ mov.l @r0, r1
+.endm
+
+ .global lowlevel_init
+ .section .spiboot1.text
+ .align 2
+
+lowlevel_init:
+
+ /*------- GPIO -------*/
+ write8 PGDR_A, PGDR_D /* eMMC power off */
+
+ write16 PACR_A, PACR_D
+ write16 PBCR_A, PBCR_D
+ write16 PCCR_A, PCCR_D
+ write16 PDCR_A, PDCR_D
+ write16 PECR_A, PECR_D
+ write16 PFCR_A, PFCR_D
+ write16 PGCR_A, PGCR_D
+ write16 PHCR_A, PHCR_D
+ write16 PICR_A, PICR_D
+ write16 PJCR_A, PJCR_D
+ write16 PKCR_A, PKCR_D
+ write16 PLCR_A, PLCR_D
+ write16 PMCR_A, PMCR_D
+ write16 PNCR_A, PNCR_D
+ write16 POCR_A, POCR_D
+ write16 PQCR_A, PQCR_D
+ write16 PRCR_A, PRCR_D
+ write16 PSCR_A, PSCR_D
+ write16 PTCR_A, PTCR_D
+ write16 PUCR_A, PUCR_D
+ write16 PVCR_A, PVCR_D
+ write16 PWCR_A, PWCR_D
+ write16 PXCR_A, PXCR_D
+ write16 PYCR_A, PYCR_D
+ write16 PZCR_A, PZCR_D
+ write16 PSEL0_A, PSEL0_D
+ write16 PSEL1_A, PSEL1_D
+ write16 PSEL2_A, PSEL2_D
+ write16 PSEL3_A, PSEL3_D
+ write16 PSEL4_A, PSEL4_D
+ write16 PSEL5_A, PSEL5_D
+ write16 PSEL6_A, PSEL6_D
+ write16 PSEL7_A, PSEL7_D
+ write16 PSEL8_A, PSEL8_D
+
+ bra exit_gpio
+ nop
+
+ .align 4
+
+/*------- GPIO -------*/
+PGDR_A: .long 0xffec0040
+PACR_A: .long 0xffec0000
+PBCR_A: .long 0xffec0002
+PCCR_A: .long 0xffec0004
+PDCR_A: .long 0xffec0006
+PECR_A: .long 0xffec0008
+PFCR_A: .long 0xffec000a
+PGCR_A: .long 0xffec000c
+PHCR_A: .long 0xffec000e
+PICR_A: .long 0xffec0010
+PJCR_A: .long 0xffec0012
+PKCR_A: .long 0xffec0014
+PLCR_A: .long 0xffec0016
+PMCR_A: .long 0xffec0018
+PNCR_A: .long 0xffec001a
+POCR_A: .long 0xffec001c
+PQCR_A: .long 0xffec0020
+PRCR_A: .long 0xffec0022
+PSCR_A: .long 0xffec0024
+PTCR_A: .long 0xffec0026
+PUCR_A: .long 0xffec0028
+PVCR_A: .long 0xffec002a
+PWCR_A: .long 0xffec002c
+PXCR_A: .long 0xffec002e
+PYCR_A: .long 0xffec0030
+PZCR_A: .long 0xffec0032
+PSEL0_A: .long 0xffec0070
+PSEL1_A: .long 0xffec0072
+PSEL2_A: .long 0xffec0074
+PSEL3_A: .long 0xffec0076
+PSEL4_A: .long 0xffec0078
+PSEL5_A: .long 0xffec007a
+PSEL6_A: .long 0xffec007c
+PSEL7_A: .long 0xffec0082
+PSEL8_A: .long 0xffec0084
+
+PGDR_D: .long 0x80
+PACR_D: .long 0x0000
+PBCR_D: .long 0x0001
+PCCR_D: .long 0x0000
+PDCR_D: .long 0x0000
+PECR_D: .long 0x0000
+PFCR_D: .long 0x0000
+PGCR_D: .long 0x0000
+PHCR_D: .long 0x0000
+PICR_D: .long 0x0000
+PJCR_D: .long 0x0000
+PKCR_D: .long 0x0003
+PLCR_D: .long 0x0000
+PMCR_D: .long 0x0000
+PNCR_D: .long 0x0000
+POCR_D: .long 0x0000
+PQCR_D: .long 0xc000
+PRCR_D: .long 0x0000
+PSCR_D: .long 0x0000
+PTCR_D: .long 0x0000
+#if defined(CONFIG_SH7757_OFFSET_SPI)
+PUCR_D: .long 0x0055
+#else
+PUCR_D: .long 0x0000
+#endif
+PVCR_D: .long 0x0000
+PWCR_D: .long 0x0000
+PXCR_D: .long 0x0000
+PYCR_D: .long 0x0000
+PZCR_D: .long 0x0000
+PSEL0_D: .long 0xfe00
+PSEL1_D: .long 0x0000
+PSEL2_D: .long 0x3000
+PSEL3_D: .long 0xff00
+PSEL4_D: .long 0x771f
+PSEL5_D: .long 0x0ffc
+PSEL6_D: .long 0x00ff
+PSEL7_D: .long 0xfc00
+PSEL8_D: .long 0x0000
+
+ .align 2
+
+exit_gpio:
+ mov #0, r14
+ mova 2f, r0
+ mov.l PC_MASK, r1
+ tst r0, r1
+ bf 2f
+
+ bra exit_pmb
+ nop
+
+ .align 2
+
+/* If CPU runs on SDRAM, PC is 0x8???????. */
+PC_MASK: .long 0x20000000
+
+2:
+ mov #1, r14
+
+ mov.l EXPEVT_A, r0
+ mov.l @r0, r0
+ mov.l EXPEVT_POWER_ON_RESET, r1
+ cmp/eq r0, r1
+ bt 1f
+
+ /*
+ * If EXPEVT value is manual reset or tlb multipul-hit,
+ * initialization of DDR3IF is not necessary.
+ */
+ bra exit_ddr
+ nop
+
+1:
+ /* For Core Reset */
+ mov.l DBACEN_A, r0
+ mov.l @r0, r0
+ cmp/eq #0, r0
+ bt 3f
+
+ /*
+ * If DBACEN == 1(DBSC was already enabled), we have to avoid the
+ * initialization of DDR3-SDRAM.
+ */
+ bra exit_ddr
+ nop
+
+3:
+ /*------- DDR3IF -------*/
+ /* oscillation stabilization time */
+ wait_timer WAIT_OSC_TIME
+
+ /* step 3 */
+ write32 DBCMD_A, DBCMD_RSTL_VAL
+ wait_timer WAIT_30US
+
+ /* step 4 */
+ write32 DBCMD_A, DBCMD_PDEN_VAL
+
+ /* step 5 */
+ write32 DBKIND_A, DBKIND_D
+
+ /* step 6 */
+ write32 DBCONF_A, DBCONF_D
+ write32 DBTR0_A, DBTR0_D
+ write32 DBTR1_A, DBTR1_D
+ write32 DBTR2_A, DBTR2_D
+ write32 DBTR3_A, DBTR3_D
+ write32 DBTR4_A, DBTR4_D
+ write32 DBTR5_A, DBTR5_D
+ write32 DBTR6_A, DBTR6_D
+ write32 DBTR7_A, DBTR7_D
+ write32 DBTR8_A, DBTR8_D
+ write32 DBTR9_A, DBTR9_D
+ write32 DBTR10_A, DBTR10_D
+ write32 DBTR11_A, DBTR11_D
+ write32 DBTR12_A, DBTR12_D
+ write32 DBTR13_A, DBTR13_D
+ write32 DBTR14_A, DBTR14_D
+ write32 DBTR15_A, DBTR15_D
+ write32 DBTR16_A, DBTR16_D
+ write32 DBTR17_A, DBTR17_D
+ write32 DBTR18_A, DBTR18_D
+ write32 DBTR19_A, DBTR19_D
+ write32 DBRNK0_A, DBRNK0_D
+
+ /* step 7 */
+ write32 DBPDCNT3_A, DBPDCNT3_D
+
+ /* step 8 */
+ write32 DBPDCNT1_A, DBPDCNT1_D
+ write32 DBPDCNT2_A, DBPDCNT2_D
+ write32 DBPDLCK_A, DBPDLCK_D
+ write32 DBPDRGA_A, DBPDRGA_D
+ write32 DBPDRGD_A, DBPDRGD_D
+
+ /* step 9 */
+ wait_timer WAIT_30US
+
+ /* step 10 */
+ write32 DBPDCNT0_A, DBPDCNT0_D
+
+ /* step 11 */
+ wait_timer WAIT_30US
+ wait_timer WAIT_30US
+
+ /* step 12 */
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ wait_DBCMD
+
+ /* step 13 */
+ write32 DBCMD_A, DBCMD_RSTH_VAL
+ wait_DBCMD
+
+ /* step 14 */
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+ write32 DBCMD_A, DBCMD_WAIT_VAL
+
+ /* step 15 */
+ write32 DBCMD_A, DBCMD_PDXT_VAL
+
+ /* step 16 */
+ write32 DBCMD_A, DBCMD_MRS2_VAL
+
+ /* step 17 */
+ write32 DBCMD_A, DBCMD_MRS3_VAL
+
+ /* step 18 */
+ write32 DBCMD_A, DBCMD_MRS1_VAL
+
+ /* step 19 */
+ write32 DBCMD_A, DBCMD_MRS0_VAL
+
+ /* step 20 */
+ write32 DBCMD_A, DBCMD_ZQCL_VAL
+
+ write32 DBCMD_A, DBCMD_REF_VAL
+ write32 DBCMD_A, DBCMD_REF_VAL
+ wait_DBCMD
+
+ /* step 21 */
+ write32 DBADJ0_A, DBADJ0_D
+ write32 DBADJ1_A, DBADJ1_D
+ write32 DBADJ2_A, DBADJ2_D
+
+ /* step 22 */
+ write32 DBRFCNF0_A, DBRFCNF0_D
+ write32 DBRFCNF1_A, DBRFCNF1_D
+ write32 DBRFCNF2_A, DBRFCNF2_D
+
+ /* step 23 */
+ write32 DBCALCNF_A, DBCALCNF_D
+
+ /* step 24 */
+ write32 DBRFEN_A, DBRFEN_D
+ write32 DBCMD_A, DBCMD_SRXT_VAL
+
+ /* step 25 */
+ write32 DBACEN_A, DBACEN_D
+
+ /* step 26 */
+ wait_DBCMD
+
+#if defined(CONFIG_SH7757LCR_DDR_ECC)
+ /* enable DDR-ECC */
+ write32 ECD_ECDEN_A, ECD_ECDEN_D
+ write32 ECD_INTSR_A, ECD_INTSR_D
+ write32 ECD_SPACER_A, ECD_SPACER_D
+ write32 ECD_MCR_A, ECD_MCR_D
+#endif
+ bra exit_ddr
+ nop
+
+ .align 4
+
+EXPEVT_A: .long 0xff000024
+EXPEVT_POWER_ON_RESET: .long 0x00000000
+
+/*------- DDR3IF -------*/
+DBCMD_A: .long 0xfe800018
+DBKIND_A: .long 0xfe800020
+DBCONF_A: .long 0xfe800024
+DBTR0_A: .long 0xfe800040
+DBTR1_A: .long 0xfe800044
+DBTR2_A: .long 0xfe800048
+DBTR3_A: .long 0xfe800050
+DBTR4_A: .long 0xfe800054
+DBTR5_A: .long 0xfe800058
+DBTR6_A: .long 0xfe80005c
+DBTR7_A: .long 0xfe800060
+DBTR8_A: .long 0xfe800064
+DBTR9_A: .long 0xfe800068
+DBTR10_A: .long 0xfe80006c
+DBTR11_A: .long 0xfe800070
+DBTR12_A: .long 0xfe800074
+DBTR13_A: .long 0xfe800078
+DBTR14_A: .long 0xfe80007c
+DBTR15_A: .long 0xfe800080
+DBTR16_A: .long 0xfe800084
+DBTR17_A: .long 0xfe800088
+DBTR18_A: .long 0xfe80008c
+DBTR19_A: .long 0xfe800090
+DBRNK0_A: .long 0xfe800100
+DBPDCNT0_A: .long 0xfe800200
+DBPDCNT1_A: .long 0xfe800204
+DBPDCNT2_A: .long 0xfe800208
+DBPDCNT3_A: .long 0xfe80020c
+DBPDLCK_A: .long 0xfe800280
+DBPDRGA_A: .long 0xfe800290
+DBPDRGD_A: .long 0xfe8002a0
+DBADJ0_A: .long 0xfe8000c0
+DBADJ1_A: .long 0xfe8000c4
+DBADJ2_A: .long 0xfe8000c8
+DBRFCNF0_A: .long 0xfe8000e0
+DBRFCNF1_A: .long 0xfe8000e4
+DBRFCNF2_A: .long 0xfe8000e8
+DBCALCNF_A: .long 0xfe8000f4
+DBRFEN_A: .long 0xfe800014
+DBACEN_A: .long 0xfe800010
+DBWAIT_A: .long 0xfe80001c
+
+WAIT_OSC_TIME: .long 6000
+WAIT_30US: .long 13333
+
+DBCMD_RSTL_VAL: .long 0x20000000
+DBCMD_PDEN_VAL: .long 0x1000d73c
+DBCMD_WAIT_VAL: .long 0x0000d73c
+DBCMD_RSTH_VAL: .long 0x2100d73c
+DBCMD_PDXT_VAL: .long 0x110000c8
+DBCMD_MRS0_VAL: .long 0x28000930
+DBCMD_MRS1_VAL: .long 0x29000004
+DBCMD_MRS2_VAL: .long 0x2a000008
+DBCMD_MRS3_VAL: .long 0x2b000000
+DBCMD_ZQCL_VAL: .long 0x03000200
+DBCMD_REF_VAL: .long 0x0c000000
+DBCMD_SRXT_VAL: .long 0x19000000
+DBKIND_D: .long 0x00000007
+DBCONF_D: .long 0x0f030a01
+DBTR0_D: .long 0x00000007
+DBTR1_D: .long 0x00000006
+DBTR2_D: .long 0x00000000
+DBTR3_D: .long 0x00000007
+DBTR4_D: .long 0x00070007
+DBTR5_D: .long 0x0000001b
+DBTR6_D: .long 0x00000014
+DBTR7_D: .long 0x00000005
+DBTR8_D: .long 0x00000015
+DBTR9_D: .long 0x00000006
+DBTR10_D: .long 0x00000008
+DBTR11_D: .long 0x00000007
+DBTR12_D: .long 0x0000000e
+DBTR13_D: .long 0x00000056
+DBTR14_D: .long 0x00000006
+DBTR15_D: .long 0x00000004
+DBTR16_D: .long 0x00150002
+DBTR17_D: .long 0x000c0017
+DBTR18_D: .long 0x00000200
+DBTR19_D: .long 0x00000040
+DBRNK0_D: .long 0x00000001
+DBPDCNT0_D: .long 0x00000001
+DBPDCNT1_D: .long 0x00000001
+DBPDCNT2_D: .long 0x00000000
+DBPDCNT3_D: .long 0x00004010
+DBPDLCK_D: .long 0x0000a55a
+DBPDRGA_D: .long 0x00000028
+DBPDRGD_D: .long 0x00017100
+
+DBADJ0_D: .long 0x00000000
+DBADJ1_D: .long 0x00000000
+DBADJ2_D: .long 0x18061806
+DBRFCNF0_D: .long 0x000001ff
+DBRFCNF1_D: .long 0x08001000
+DBRFCNF2_D: .long 0x00000000
+DBCALCNF_D: .long 0x0000ffff
+DBRFEN_D: .long 0x00000001
+DBACEN_D: .long 0x00000001
+
+/*------- DDR-ECC -------*/
+ECD_ECDEN_A: .long 0xffc1012c
+ECD_ECDEN_D: .long 0x00000001
+ECD_INTSR_A: .long 0xfe900024
+ECD_INTSR_D: .long 0xffffffff
+ECD_SPACER_A: .long 0xfe900018
+ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING
+ECD_MCR_A: .long 0xfe900010
+ECD_MCR_D: .long 0x00000001
+
+ .align 2
+exit_ddr:
+
+#if defined(CONFIG_SH_32BIT)
+ /*------- set PMB -------*/
+ write32 PASCR_A, PASCR_29BIT_D
+ write32 MMUCR_A, MMUCR_D
+
+ /*****************************************************************
+ * ent virt phys v sz c wt
+ * 0 0xa0000000 0x00000000 1 128M 0 1
+ * 1 0xa8000000 0x48000000 1 128M 0 1
+ * 5 0x88000000 0x48000000 1 128M 1 1
+ */
+ write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
+ write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
+ write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
+ write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
+ write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
+ write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
+
+ write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
+ write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
+
+ write32 PASCR_A, PASCR_INIT
+ mov.l DUMMY_ADDR, r0
+ icbi @r0
+#endif /* if defined(CONFIG_SH_32BIT) */
+
+exit_pmb:
+ /* CPU is running on ILRAM? */
+ mov r14, r0
+ tst #1, r0
+ bt 1f
+
+ mov.l _bss_start, r15
+ mov.l _spiboot_main, r0
+100: bsrf r0
+ nop
+
+ .align 2
+_spiboot_main: .long (spiboot_main - (100b + 4))
+_bss_start: .long bss_start
+
+1:
+
+ write32 CCR_A, CCR_D
+
+ rts
+ nop
+
+ .align 4
+
+#if defined(CONFIG_SH_32BIT)
+/*------- set PMB -------*/
+PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
+PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
+PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
+PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
+PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
+PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
+PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
+PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
+PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
+PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
+PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
+PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
+PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
+PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
+PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
+PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
+
+PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
+PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
+PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
+PMB_ADDR_NOT_USE_D: .long 0x00000000
+
+PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
+PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
+PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
+
+/* ppn ub v s1 s0 c wt */
+PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
+
+PASCR_A: .long 0xff000070
+DUMMY_ADDR: .long 0xa0000000
+PASCR_29BIT_D: .long 0x00000000
+PASCR_INIT: .long 0x80000080
+MMUCR_A: .long 0xff000010
+MMUCR_D: .long 0x00000004 /* clear ITLB */
+#endif /* CONFIG_SH_32BIT */
+
+CCR_A: .long CCR
+CCR_D: .long CCR_CACHE_INIT
diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c
new file mode 100644
index 0000000..ddcf275
--- /dev/null
+++ b/board/renesas/sh7757lcr/sh7757lcr.c
@@ -0,0 +1,445 @@
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmc.h>
+#include <spi.h>
+#include <spi_flash.h>
+
+int checkboard(void)
+{
+ puts("BOARD: R0P7757LC0030RL board\n");
+
+ return 0;
+}
+
+static void init_gctrl(void)
+{
+ struct gctrl_regs *gctrl = GCTRL_BASE;
+ unsigned long graofst;
+
+ graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
+ writel(graofst | 0x20000f00, &gctrl->gracr3);
+}
+
+static int init_pcie_bridge_from_spi(void *buf, size_t size)
+{
+ struct spi_flash *spi;
+ int ret;
+ unsigned long pcie_addr;
+
+ spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!spi) {
+ printf("%s: spi_flash probe error.\n", __func__);
+ return 1;
+ }
+
+ if (is_sh7757_b0())
+ pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
+ else
+ pcie_addr = SH7757LCR_PCIEBRG_ADDR;
+
+ ret = spi_flash_read(spi, pcie_addr, size, buf);
+ if (ret) {
+ printf("%s: spi_flash read error.\n", __func__);
+ spi_flash_free(spi);
+ return 1;
+ }
+ spi_flash_free(spi);
+
+ return 0;
+}
+
+static void init_pcie_bridge(void)
+{
+ struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
+ struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
+ int i;
+ unsigned char *data;
+ unsigned short tmp;
+ unsigned long pcie_size;
+
+ if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
+ return;
+
+ if (is_sh7757_b0())
+ pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
+ else
+ pcie_size = SH7757LCR_PCIEBRG_SIZE;
+
+ data = malloc(pcie_size);
+ if (!data) {
+ printf("%s: malloc error.\n", __func__);
+ return;
+ }
+ if (init_pcie_bridge_from_spi(data, pcie_size)) {
+ free(data);
+ return;
+ }
+
+ if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
+ data[3] == 0xff) {
+ free(data);
+ printf("%s: skipped initialization\n", __func__);
+ return;
+ }
+
+ writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
+ writew(0x0000, &pciebrg->cp_ctrl);
+ writew(0x0000, &pciebrg->cp_addr);
+
+ for (i = 0; i < pcie_size; i += 2) {
+ tmp = (data[i] << 8) | data[i + 1];
+ writew(tmp, &pciebrg->cp_data);
+ }
+
+ writew(0xa500, &pciebrg->ctrl_h8s); /* start */
+ if (!is_sh7757_b0())
+ writel(0x00000001, &pcie_setup->pbictl3);
+
+ free(data);
+}
+
+static void init_usb_phy(void)
+{
+ struct usb_common_regs *common0 = USB0_COMMON_BASE;
+ struct usb_common_regs *common1 = USB1_COMMON_BASE;
+ struct usb0_phy_regs *phy = USB0_PHY_BASE;
+ struct usb1_port_regs *port = USB1_PORT_BASE;
+ struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
+
+ writew(0x0100, &phy->reset); /* set reset */
+ /* port0 = USB0, port1 = USB1 */
+ writew(0x0002, &phy->portsel);
+ writel(0x0001, &port->port1sel); /* port1 = Host */
+ writew(0x0111, &phy->reset); /* clear reset */
+
+ writew(0x4000, &common0->suspmode);
+ writew(0x4000, &common1->suspmode);
+
+#if defined(__LITTLE_ENDIAN)
+ writel(0x00000000, &align->ehcidatac);
+ writel(0x00000000, &align->ohcidatac);
+#endif
+}
+
+static void set_mac_to_sh_eth_register(int channel, char *mac_string)
+{
+ struct ether_mac_regs *ether;
+ unsigned char mac[6];
+ unsigned long val;
+
+ eth_parse_enetaddr(mac_string, mac);
+
+ if (!channel)
+ ether = ETHER0_MAC_BASE;
+ else
+ ether = ETHER1_MAC_BASE;
+
+ val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+ writel(val, ðer->mahr);
+ val = (mac[4] << 8) | mac[5];
+ writel(val, ðer->malr);
+}
+
+static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
+{
+ struct ether_mac_regs *ether;
+ unsigned char mac[6];
+ unsigned long val;
+
+ eth_parse_enetaddr(mac_string, mac);
+
+ if (!channel)
+ ether = GETHER0_MAC_BASE;
+ else
+ ether = GETHER1_MAC_BASE;
+
+ val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+ writel(val, ðer->mahr);
+ val = (mac[4] << 8) | mac[5];
+ writel(val, ðer->malr);
+}
+
+/*****************************************************************
+ * This PMB must be set on this timing. The lowlevel_init is run on
+ * Area 0(phys 0x00000000), so we have to map it.
+ *
+ * The new PMB table is following:
+ * ent virt phys v sz c wt
+ * 0 0xa0000000 0x40000000 1 128M 0 1
+ * 1 0xa8000000 0x48000000 1 128M 0 1
+ * 2 0xb0000000 0x50000000 1 128M 0 1
+ * 3 0xb8000000 0x58000000 1 128M 0 1
+ * 4 0x80000000 0x40000000 1 128M 1 1
+ * 5 0x88000000 0x48000000 1 128M 1 1
+ * 6 0x90000000 0x50000000 1 128M 1 1
+ * 7 0x98000000 0x58000000 1 128M 1 1
+ */
+static void set_pmb_on_board_init(void)
+{
+ struct mmu_regs *mmu = MMU_BASE;
+
+ /* clear ITLB */
+ writel(0x00000004, &mmu->mmucr);
+
+ /* delete PMB for SPIBOOT */
+ writel(0, PMB_ADDR_BASE(0));
+ writel(0, PMB_DATA_BASE(0));
+
+ /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
+ /* ppn ub v s1 s0 c wt */
+ writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
+ writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
+ writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
+ writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
+ writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
+ writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
+ writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
+ writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
+ writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
+ writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
+ writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
+ writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
+}
+
+int board_init(void)
+{
+ struct gether_control_regs *gether = GETHER_CONTROL_BASE;
+
+ set_pmb_on_board_init();
+
+ /* enable RMII's MDIO (disable GRMII's MDIO) */
+ writel(0x00030000, &gether->gbecont);
+
+ init_gctrl();
+ init_usb_phy();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ printf(" Physical address\n");
+ printf(" 0x%08x - 0x%08x : Accessible Space as ECC Area\n",
+ SH7757LCR_SDRAM_PHYS_TOP,
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1);
+ printf(" 0x%08x - 0x%08x : No Access Area\n",
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE,
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1);
+ printf(" 0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n",
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2,
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 +
+ SH7757LCR_SDRAM_DVC_SIZE - 1);
+ printf(" 0x%08x - 0x%08x : Non-ECC Area for G200eR2\n",
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET,
+ SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff);
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ return mmcif_mmc_init();
+}
+
+static int get_sh_eth_mac_raw(unsigned char *buf, int size)
+{
+ struct spi_flash *spi;
+ int ret;
+
+ spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (spi == NULL) {
+ printf("%s: spi_flash probe error.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
+ if (ret) {
+ printf("%s: spi_flash read error.\n", __func__);
+ spi_flash_free(spi);
+ return 1;
+ }
+ spi_flash_free(spi);
+
+ return 0;
+}
+
+static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
+{
+ memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
+ SH7757LCR_ETHERNET_MAC_SIZE);
+ mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
+
+ return 0;
+}
+
+static void init_ethernet_mac(void)
+{
+ char mac_string[64];
+ char env_string[64];
+ int i;
+ unsigned char *buf;
+
+ buf = malloc(256);
+ if (!buf) {
+ printf("%s: malloc error.\n", __func__);
+ return;
+ }
+ get_sh_eth_mac_raw(buf, 256);
+
+ /* Fast Ethernet */
+ for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
+ get_sh_eth_mac(i, mac_string, buf);
+ if (i == 0)
+ setenv("ethaddr", mac_string);
+ else {
+ sprintf(env_string, "eth%daddr", i);
+ setenv(env_string, mac_string);
+ }
+
+ set_mac_to_sh_eth_register(i, mac_string);
+ }
+
+ /* Gigabit Ethernet */
+ for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
+ get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
+ sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
+ setenv(env_string, mac_string);
+
+ set_mac_to_sh_giga_eth_register(i, mac_string);
+ }
+
+ free(buf);
+}
+
+static void init_pcie(void)
+{
+ struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
+ struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
+
+ writel(0x00000ff2, &pcie_setup->ladmsk0);
+ writel(0x00000001, &pcie_setup->barmap);
+ writel(0xffcaa000, &pcie_setup->lad0);
+ writel(0x00030000, &pcie_sysbus->endictl0);
+ writel(0x00000003, &pcie_sysbus->endictl1);
+ writel(0x00000004, &pcie_setup->pbictl2);
+}
+
+static void finish_spiboot(void)
+{
+ struct gctrl_regs *gctrl = GCTRL_BASE;
+ /*
+ * SH7757 B0 does not use LBSC.
+ * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
+ * This setting is not cleared by manual reset, So we have to set it
+ * to 0.
+ */
+ writel(0x00000000, &gctrl->spibootcan);
+}
+
+int board_late_init(void)
+{
+ init_ethernet_mac();
+ init_pcie_bridge();
+ init_pcie();
+ finish_spiboot();
+
+ return 0;
+}
+
+int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct gctrl_regs *gctrl = GCTRL_BASE;
+ unsigned long graofst;
+
+ writel(0xfedcba98, &gctrl->wprotect);
+ graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
+ writel(graofst | 0xa0000f00, &gctrl->gracr3);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ sh_g200, 1, 1, do_sh_g200,
+ "enable sh-g200",
+ "enable SH-G200 bus (disable PCIe-G200)"
+);
+
+int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i, ret;
+ char mac_string[256];
+ struct spi_flash *spi;
+ unsigned char *buf;
+
+ if (argc != 5) {
+ buf = malloc(256);
+ if (!buf) {
+ printf("%s: malloc error.\n", __func__);
+ return 1;
+ }
+
+ get_sh_eth_mac_raw(buf, 256);
+
+ /* print current MAC address */
+ for (i = 0; i < 4; i++) {
+ get_sh_eth_mac(i, mac_string, buf);
+ if (i < 2)
+ printf(" ETHERC ch%d = %s\n", i, mac_string);
+ else
+ printf("GETHERC ch%d = %s\n", i-2, mac_string);
+ }
+ free(buf);
+ return 0;
+ }
+
+ /* new setting */
+ memset(mac_string, 0xff, sizeof(mac_string));
+ sprintf(mac_string, "%s\t%s\t%s\t%s",
+ argv[1], argv[2], argv[3], argv[4]);
+
+ /* write MAC data to SPI rom */
+ spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ if (!spi) {
+ printf("%s: spi_flash probe error.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
+ SH7757LCR_SPI_SECTOR_SIZE);
+ if (ret) {
+ printf("%s: spi_flash erase error.\n", __func__);
+ return 1;
+ }
+
+ ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
+ sizeof(mac_string), mac_string);
+ if (ret) {
+ printf("%s: spi_flash write error.\n", __func__);
+ spi_flash_free(spi);
+ return 1;
+ }
+ spi_flash_free(spi);
+
+ puts("The writing of the MAC address to SPI ROM was completed.\n");
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ write_mac, 5, 1, do_write_mac,
+ "write MAC address for ETHERC/GETHERC",
+ "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
+);
diff --git a/board/renesas/sh7757lcr/spi-boot.c b/board/renesas/sh7757lcr/spi-boot.c
new file mode 100644
index 0000000..71dcf5d
--- /dev/null
+++ b/board/renesas/sh7757lcr/spi-boot.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License. See the file "COPYING.LIB" in the main
+ * directory of this archive for more details.
+ */
+
+#include <common.h>
+
+#define CONFIG_RAM_BOOT_PHYS 0x4ef80000
+#if defined(CONFIG_SH7757_OFFSET_SPI)
+#define CONFIG_SPI_ADDR 0x00010000
+#else
+#define CONFIG_SPI_ADDR 0x00000000
+#endif
+#define CONFIG_SPI_LENGTH 0x00030000
+#define CONFIG_RAM_BOOT 0x8ef80000
+
+#define SPIWDMADR 0xFE001018
+#define SPIWDMCNTR 0xFE001020
+#define SPIDMCOR 0xFE001028
+#define SPIDMINTSR 0xFE001188
+#define SPIDMINTMR 0xFE001190
+
+#define SPIDMINTSR_DMEND 0x00000004
+
+#define TBR 0xFE002000
+#define RBR 0xFE002000
+
+#define CR1 0xFE002008
+#define CR2 0xFE002010
+#define CR3 0xFE002018
+#define CR4 0xFE002020
+
+/* CR1 */
+#define SPI_TBE 0x80
+#define SPI_TBF 0x40
+#define SPI_RBE 0x20
+#define SPI_RBF 0x10
+#define SPI_PFONRD 0x08
+#define SPI_SSDB 0x04
+#define SPI_SSD 0x02
+#define SPI_SSA 0x01
+
+/* CR2 */
+#define SPI_RSTF 0x80
+#define SPI_LOOPBK 0x40
+#define SPI_CPOL 0x20
+#define SPI_CPHA 0x10
+#define SPI_L1M0 0x08
+
+/* CR4 */
+#define SPI_TBEI 0x80
+#define SPI_TBFI 0x40
+#define SPI_RBEI 0x20
+#define SPI_RBFI 0x10
+#define SPI_SSS 0x01
+
+#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val
+#define spi_read(addr) (*(volatile unsigned long *)(addr))
+
+/* M25P80 */
+#define M25_READ 0x03
+
+#define __uses_spiboot2 __attribute__((section(".spiboot2.text")))
+static void __uses_spiboot2 spi_reset(void)
+{
+ spi_write(0xfe, CR1);
+
+ spi_write(0, SPIDMCOR);
+ spi_write(0x00, CR1);
+
+ spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */
+ spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
+}
+
+static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
+ unsigned long len)
+{
+ spi_write(M25_READ, TBR);
+ spi_write((addr >> 16) & 0xFF, TBR);
+ spi_write((addr >> 8) & 0xFF, TBR);
+ spi_write(addr & 0xFF, TBR);
+
+ spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
+ spi_write((unsigned long)buf, SPIWDMADR);
+ spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
+ spi_write(1, SPIDMCOR);
+
+ spi_write(0xff, CR3);
+ spi_write(spi_read(CR1) | SPI_SSDB, CR1);
+ spi_write(spi_read(CR1) | SPI_SSA, CR1);
+
+ while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
+ ;
+}
+
+void __uses_spiboot2 spiboot_main(void)
+{
+ void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
+
+ spi_reset();
+ spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
+ CONFIG_SPI_LENGTH);
+
+ _start();
+}
diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds
new file mode 100644
index 0000000..4027fe3
--- /dev/null
+++ b/board/renesas/sh7757lcr/u-boot.lds
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2011
+ * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ /*
+ * entry and reloct_dst will be provided via ldflags
+ */
+ . = .;
+
+ PROVIDE (_ftext = .);
+ PROVIDE (_fcode = .);
+ PROVIDE (_start = .);
+
+ .text :
+ {
+ KEEP(arch/sh/cpu/sh4/start.o (.text))
+ *(.spiboot1.text)
+ *(.spiboot2.text)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenv)
+ . = ALIGN(8192);
+ common/env_embedded.o (.ppcenvr)
+ . = ALIGN(8192);
+ *(.text)
+ . = ALIGN(4);
+ } =0xFF
+ PROVIDE (_ecode = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ . = ALIGN(4);
+ }
+ PROVIDE (_etext = .);
+
+
+ PROVIDE (_fdata = .);
+ .data :
+ {
+ *(.data)
+ . = ALIGN(4);
+ }
+ PROVIDE (_edata = .);
+
+ PROVIDE (_fgot = .);
+ .got :
+ {
+ *(.got)
+ . = ALIGN(4);
+ }
+ PROVIDE (_egot = .);
+
+
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ PROVIDE (reloc_dst_end = .);
+ /* _reloc_dst_end = .; */
+
+ PROVIDE (bss_start = .);
+ PROVIDE (__bss_start = .);
+ .bss (NOLOAD) :
+ {
+ *(.bss)
+ . = ALIGN(4);
+ }
+ PROVIDE (bss_end = .);
+
+ PROVIDE (__bss_end = .);
+}
diff --git a/board/renesas/sh7763rdp/Kconfig b/board/renesas/sh7763rdp/Kconfig
new file mode 100644
index 0000000..101d2b5
--- /dev/null
+++ b/board/renesas/sh7763rdp/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SH7763RDP
+
+config SYS_BOARD
+ default "sh7763rdp"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "sh7763rdp"
+
+endif
diff --git a/board/renesas/sh7763rdp/MAINTAINERS b/board/renesas/sh7763rdp/MAINTAINERS
new file mode 100644
index 0000000..6ee8f9f
--- /dev/null
+++ b/board/renesas/sh7763rdp/MAINTAINERS
@@ -0,0 +1,7 @@
+SH7763RDP BOARD
+M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S: Maintained
+F: board/renesas/sh7763rdp/
+F: include/configs/sh7763rdp.h
+F: configs/sh7763rdp_defconfig
diff --git a/board/renesas/sh7763rdp/Makefile b/board/renesas/sh7763rdp/Makefile
new file mode 100644
index 0000000..cbf38bb
--- /dev/null
+++ b/board/renesas/sh7763rdp/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2008 Renesas Solutions Corp.
+# Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+# Copyright (C) 2007 Kenati Technologies, Inc.
+#
+# board/sh7763rdp/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := sh7763rdp.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S
new file mode 100644
index 0000000..e45fbbe
--- /dev/null
+++ b/board/renesas/sh7763rdp/lowlevel_init.S
@@ -0,0 +1,261 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ * Copyright (C) 2007 Kenati Technologies, Inc.
+ *
+ * board/sh7763rdp/lowlevel_init.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */
+
+ write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */
+
+ write32 WDTBST_A, WDTBST_D /*
+ * 0xFFCC0008
+ * Watchdog Base Stop Time Register
+ */
+
+ write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */
+ /* Instruction Cache Invalidate */
+
+ write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */
+ /* TI == TLB Invalidate bit */
+
+ write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */
+
+ write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */
+
+ write32 RAMCR_A, RAMCR_D
+
+ mov.l MMSELR_A, r1
+ mov.l MMSELR_D, r0
+ synco
+ mov.l r0, @r1
+
+ mov.l @r1, r2 /* execute two reads after setting MMSELR */
+ mov.l @r1, r2
+ synco
+
+ /* issue memory read */
+ mov.l DDRSD_START_A, r1 /* memory address to read*/
+ mov.l @r1, r0
+ synco
+
+ write32 MIM8_A, MIM8_D
+
+ write32 MIMC_A, MIMC_D1
+
+ write32 STRC_A, STRC_D
+
+ write32 SDR4_A, SDR4_D
+
+ write32 MIMC_A, MIMC_D2
+
+ nop
+ nop
+ nop
+
+ write32 SCR4_A, SCR4_D3
+
+ write32 SCR4_A, SCR4_D2
+
+ write32 SDMR02000_A, SDMR02000_D
+
+ write32 SDMR00B08_A, SDMR00B08_D
+
+ write32 SCR4_A, SCR4_D2
+
+ write32 SCR4_A, SCR4_D4
+
+ nop
+ nop
+ nop
+ nop
+
+ write32 SCR4_A, SCR4_D4
+
+ nop
+ nop
+ nop
+ nop
+
+ write32 SDMR00308_A, SDMR00308_D
+
+ write32 MIMC_A, MIMC_D3
+
+ mov.l SCR4_A, r1
+ mov.l SCR4_D1, r0
+ mov.l DELAY60_D, r3
+
+delay_loop_60:
+ mov.l r0, @r1
+ dt r3
+ bf delay_loop_60
+ nop
+
+ write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */
+
+bsc_init:
+ write32 BCR_A, BCR_D
+
+ write32 CS0BCR_A, CS0BCR_D
+
+ write32 CS1BCR_A, CS1BCR_D
+
+ write32 CS2BCR_A, CS2BCR_D
+
+ write32 CS4BCR_A, CS4BCR_D
+
+ write32 CS5BCR_A, CS5BCR_D
+
+ write32 CS6BCR_A, CS6BCR_D
+
+ write32 CS0WCR_A, CS0WCR_D
+
+ write32 CS1WCR_A, CS1WCR_D
+
+ write32 CS2WCR_A, CS2WCR_D
+
+ write32 CS4WCR_A, CS4WCR_D
+
+ write32 CS5WCR_A, CS5WCR_D
+
+ write32 CS6WCR_A, CS6WCR_D
+
+ write32 CS5PCR_A, CS5PCR_D
+
+ write32 CS6PCR_A, CS6PCR_D
+
+ mov.l DELAY200_D, r3
+
+delay_loop_200:
+ dt r3
+ bf delay_loop_200
+ nop
+
+ write16 PSEL0_A, PSEL0_D
+
+ write16 PSEL1_A, PSEL1_D
+
+ write32 ICR0_A, ICR0_D
+
+ stc sr, r0 /* BL bit off(init=ON) */
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+ nop
+
+ .align 2
+
+DELAY60_D: .long 60
+DELAY200_D: .long 17800
+
+CCR_A: .long 0xFF00001C
+MMUCR_A: .long 0xFF000010
+RAMCR_A: .long 0xFF000074
+
+/* Low power mode control */
+MSTPCR0_A: .long 0xFFC80030
+MSTPCR1_A: .long 0xFFC80038
+
+/* RWBT */
+WDTST_A: .long 0xFFCC0000
+WDTCSR_A: .long 0xFFCC0004
+WDTBST_A: .long 0xFFCC0008
+
+/* BSC */
+MMSELR_A: .long 0xFE600020
+BCR_A: .long 0xFF801000
+CS0BCR_A: .long 0xFF802000
+CS1BCR_A: .long 0xFF802010
+CS2BCR_A: .long 0xFF802020
+CS4BCR_A: .long 0xFF802040
+CS5BCR_A: .long 0xFF802050
+CS6BCR_A: .long 0xFF802060
+CS0WCR_A: .long 0xFF802008
+CS1WCR_A: .long 0xFF802018
+CS2WCR_A: .long 0xFF802028
+CS4WCR_A: .long 0xFF802048
+CS5WCR_A: .long 0xFF802058
+CS6WCR_A: .long 0xFF802068
+CS5PCR_A: .long 0xFF802070
+CS6PCR_A: .long 0xFF802080
+DDRSD_START_A: .long 0xAC000000
+
+/* INTC */
+ICR0_A: .long 0xFFD00000
+
+/* DDR I/F */
+MIM8_A: .long 0xFE800008
+MIMC_A: .long 0xFE80000C
+SCR4_A: .long 0xFE800014
+STRC_A: .long 0xFE80001C
+SDR4_A: .long 0xFE800034
+SDMR00308_A: .long 0xFE900308
+SDMR00B08_A: .long 0xFE900B08
+SDMR02000_A: .long 0xFE902000
+
+/* GPIO */
+PSEL0_A: .long 0xFFEF0070
+PSEL1_A: .long 0xFFEF0072
+
+CCR_CACHE_ICI_D:.long 0x00000800
+CCR_CACHE_D_2: .long 0x00000103
+MMU_CONTROL_TI_D:.long 0x00000004
+RAMCR_D: .long 0x00000200
+MSTPCR0_D: .long 0x00000000
+MSTPCR1_D: .long 0x00000000
+
+MMSELR_D: .long 0xa5a50000
+BCR_D: .long 0x00000000
+CS0BCR_D: .long 0x77777770
+CS1BCR_D: .long 0x77777670
+CS2BCR_D: .long 0x77777670
+CS4BCR_D: .long 0x77777670
+CS5BCR_D: .long 0x77777670
+CS6BCR_D: .long 0x77777670
+CS0WCR_D: .long 0x7777770F
+CS1WCR_D: .long 0x22000002
+CS2WCR_D: .long 0x7777770F
+CS4WCR_D: .long 0x7777770F
+CS5WCR_D: .long 0x7777770F
+CS6WCR_D: .long 0x7777770F
+CS5PCR_D: .long 0x77000000
+CS6PCR_D: .long 0x77000000
+ICR0_D: .long 0x00E00000
+MIM8_D: .long 0x00000000
+MIMC_D1: .long 0x01d10008
+MIMC_D2: .long 0x01d10009
+MIMC_D3: .long 0x01d10209
+SCR4_D1: .long 0x00000001
+SCR4_D2: .long 0x00000002
+SCR4_D3: .long 0x00000003
+SCR4_D4: .long 0x00000004
+STRC_D: .long 0x000f3980
+SDR4_D: .long 0x00000300
+SDMR00308_D: .long 0x00000000
+SDMR00B08_D: .long 0x00000000
+SDMR02000_D: .long 0x00000000
+PSEL0_D: .word 0x00000001
+PSEL1_D: .word 0x00000244
+SR_MASK_D: .long 0xEFFFFF0F
+WDTST_D: .long 0x5A000FFF
+WDTCSR_D: .long 0xA5000000
+WDTBST_D: .long 0x55000000
diff --git a/board/renesas/sh7763rdp/sh7763rdp.c b/board/renesas/sh7763rdp/sh7763rdp.c
new file mode 100644
index 0000000..9658a5e
--- /dev/null
+++ b/board/renesas/sh7763rdp/sh7763rdp.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ * Copyright (C) 2007 Kenati Technologies, Inc.
+ *
+ * board/sh7763rdp/sh7763rdp.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPU_CMDREG 0xB1000006
+#define PDCR 0xffef0006
+#define PECR 0xffef0008
+#define PFCR 0xffef000a
+#define PGCR 0xffef000c
+#define PHCR 0xffef000e
+#define PJCR 0xffef0012
+#define PKCR 0xffef0014
+#define PLCR 0xffef0016
+#define PMCR 0xffef0018
+#define PSEL1 0xffef0072
+#define PSEL2 0xffef0074
+#define PSEL3 0xffef0076
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas SH7763 RDP\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ vu_short dat;
+
+ /* Enable mode */
+ writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG);
+
+ /* GPIO Setting (eth1) */
+ dat = inw(PSEL1);
+ writew(((dat & ~0xff00) | 0x2400), PSEL1);
+ writew(0, PFCR);
+ writew(0, PGCR);
+ writew(0, PHCR);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+void led_set_state(unsigned short value)
+{
+}
diff --git a/board/renesas/sh7785lcr/Kconfig b/board/renesas/sh7785lcr/Kconfig
new file mode 100644
index 0000000..e204c76
--- /dev/null
+++ b/board/renesas/sh7785lcr/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SH7785LCR
+
+config SYS_BOARD
+ default "sh7785lcr"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "sh7785lcr"
+
+endif
diff --git a/board/renesas/sh7785lcr/MAINTAINERS b/board/renesas/sh7785lcr/MAINTAINERS
new file mode 100644
index 0000000..17578e0
--- /dev/null
+++ b/board/renesas/sh7785lcr/MAINTAINERS
@@ -0,0 +1,7 @@
+SH7785LCR BOARD
+#M: -
+S: Maintained
+F: board/renesas/sh7785lcr/
+F: include/configs/sh7785lcr.h
+F: configs/sh7785lcr_defconfig
+F: configs/sh7785lcr_32bit_defconfig
diff --git a/board/renesas/sh7785lcr/Makefile b/board/renesas/sh7785lcr/Makefile
new file mode 100644
index 0000000..e8cfb05
--- /dev/null
+++ b/board/renesas/sh7785lcr/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := sh7785lcr.o selfcheck.o rtl8169_mac.o
+obj-y += lowlevel_init.o
diff --git a/board/renesas/sh7785lcr/README.sh7785lcr b/board/renesas/sh7785lcr/README.sh7785lcr
new file mode 100644
index 0000000..56455fc
--- /dev/null
+++ b/board/renesas/sh7785lcr/README.sh7785lcr
@@ -0,0 +1,123 @@
+========================================
+Renesas Technology R0P7785LC0011RL board
+========================================
+
+This board specification:
+=========================
+
+The R0P7785LC0011RL(board config name:sh7785lcr) has the following device:
+
+ - SH7785 (SH-4A)
+ - DDR2-SDRAM 512MB
+ - NOR Flash 64MB
+ - 2D Graphic controller
+ - SATA controller
+ - Ethernet controller
+ - USB host/peripheral controller
+ - SD controller
+ - I2C controller
+ - RTC
+
+This board has 2 physical memory maps. It can be changed with DIP switch(S2-5).
+
+ phys address | S2-5 = OFF | S2-5 = ON
+ -------------------------------+---------------+---------------
+ 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
+ 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
+ 0x06000000 - 0x07ffffff(CS1) | reserved | I2C
+ 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
+ 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
+ 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
+ 0x14000000 - 0x17ffffff(CS5) | I2C | USB
+ 0x18000000 - 0x1bffffff(CS6) | reserved | SD
+ 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
+
+
+configuration for This board:
+=============================
+
+You can choose configuration as follows:
+
+ - make sh7785lcr_config
+ - make sh7785lcr_32bit_config
+
+When you use "make sh7785lcr_config", there is build U-Boot for 29-bit
+address mode. This mode can use 128MB DDR-SDRAM.
+
+When you use "make sh7785lcr_32bit_config", there is build U-Boot for 32-bit
+extended address mode. This mode can use 384MB DDR-SDRAM. And if you run
+"pmb" command, this mode can use 512MB DDR-SDRAM.
+
+ * 32-bit extended address mode PMB mapping *
+ a) on start-up
+ virt | phys | size | device
+ -------------+---------------+---------------+---------------
+ 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
+ 0xa0000000 | 0x00000000 | 64MB | NOR Flash
+ 0xa4000000 | 0x04000000 | 16MB | PLD
+ 0xa6000000 | 0x08000000 | 16MB | USB
+ 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)
+
+ b) after "pmb" command
+ virt | phys | size | device
+ -------------+---------------+---------------+---------------
+ 0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable)
+ 0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable)
+
+
+This board specific command:
+============================
+
+This board has the following its specific command:
+
+ - hwtest
+ - printmac
+ - setmac
+ - pmb (sh7785lcr_32bit_config only)
+
+
+1. hwtest
+
+This is self-check command. This command has the following options:
+
+ - all : test all hardware
+ - pld : output PLD version
+ - led : turn on LEDs
+ - dipsw : test DIP switch
+ - sm107 : output SM107 version
+ - net : check RTL8110 ID
+ - sata : check SiI3512 ID
+ - net : output PCI slot device ID
+
+i.e)
+=> hwtest led
+turn on LEDs 3, 5, 7, 9
+turn on LEDs 4, 6, 8, 10
+
+=> hwtest net
+Ethernet OK
+
+
+2. printmac
+
+This command outputs MAC address of this board.
+
+i.e)
+=> printmac
+MAC = 00:00:87:**:**:**
+
+
+3. setmac
+
+This command writes MAC address of this board.
+
+i.e)
+=> setmac 00:00:87:**:**:**
+
+
+4. pmb
+
+This command change PMB for DDR-SDRAM all mapping. However you cannot use
+NOR Flash and USB Host on U-Boot when you run this command.
+i.e)
+=> pmb
diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S
new file mode 100644
index 0000000..8b729ac
--- /dev/null
+++ b/board/renesas/sh7785lcr/lowlevel_init.S
@@ -0,0 +1,363 @@
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+#include <asm/processor.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+ wait_timer WAIT_200US
+ wait_timer WAIT_200US
+
+ /*------- LBSC -------*/
+ write32 MMSELR_A, MMSELR_D
+
+ /*------- DBSC2 -------*/
+ write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D
+ write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D
+ write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D
+ write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D
+ write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1
+ write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2
+ wait_timer WAIT_200US
+
+ write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D
+ write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H
+ wait_timer WAIT_200US
+ write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
+ write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2
+ write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3
+ write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
+ write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1
+ write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
+ write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
+ write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
+ write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2
+ wait_timer WAIT_200US
+
+ write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2
+ write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
+
+ write32 DBSC2_DBEN_A, DBSC2_DBEN_D
+ write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D
+ write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D
+ write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D
+ wait_timer WAIT_200US
+
+ /*------- GPIO -------*/
+ write16 PACR_A, PXCR_D
+ write16 PBCR_A, PXCR_D
+ write16 PCCR_A, PXCR_D
+ write16 PDCR_A, PXCR_D
+ write16 PECR_A, PXCR_D
+ write16 PFCR_A, PXCR_D
+ write16 PGCR_A, PXCR_D
+ write16 PHCR_A, PHCR_D
+ write16 PJCR_A, PJCR_D
+ write16 PKCR_A, PKCR_D
+ write16 PLCR_A, PXCR_D
+ write16 PMCR_A, PMCR_D
+ write16 PNCR_A, PNCR_D
+ write16 PPCR_A, PXCR_D
+ write16 PQCR_A, PXCR_D
+ write16 PRCR_A, PXCR_D
+
+ write8 PEPUPR_A, PEPUPR_D
+ write8 PHPUPR_A, PHPUPR_D
+ write8 PJPUPR_A, PJPUPR_D
+ write8 PKPUPR_A, PKPUPR_D
+ write8 PLPUPR_A, PLPUPR_D
+ write8 PMPUPR_A, PMPUPR_D
+ write8 PNPUPR_A, PNPUPR_D
+ write16 PPUPR1_A, PPUPR1_D
+ write16 PPUPR2_A, PPUPR2_D
+ write16 P1MSELR_A, P1MSELR_D
+ write16 P2MSELR_A, P2MSELR_D
+
+ /*------- LBSC -------*/
+ write32 BCR_A, BCR_D
+ write32 CS0BCR_A, CS0BCR_D
+ write32 CS0WCR_A, CS0WCR_D
+ write32 CS1BCR_A, CS1BCR_D
+ write32 CS1WCR_A, CS1WCR_D
+ write32 CS4BCR_A, CS4BCR_D
+ write32 CS4WCR_A, CS4WCR_D
+
+ mov.l PASCR_A, r0
+ mov.l @r0, r2
+ mov.l PASCR_32BIT_MODE, r1
+ tst r1, r2
+ bt lbsc_29bit
+
+ write32 CS2BCR_A, CS_USB_BCR_D
+ write32 CS2WCR_A, CS_USB_WCR_D
+ write32 CS3BCR_A, CS_SD_BCR_D
+ write32 CS3WCR_A, CS_SD_WCR_D
+ write32 CS5BCR_A, CS_I2C_BCR_D
+ write32 CS5WCR_A, CS_I2C_WCR_D
+ write32 CS6BCR_A, CS0BCR_D
+ write32 CS6WCR_A, CS0WCR_D
+ bra lbsc_end
+ nop
+
+lbsc_29bit:
+ write32 CS5BCR_A, CS_USB_BCR_D
+ write32 CS5WCR_A, CS_USB_WCR_D
+ write32 CS6BCR_A, CS_SD_BCR_D
+ write32 CS6WCR_A, CS_SD_WCR_D
+
+lbsc_end:
+#if defined(CONFIG_SH_32BIT)
+ /*------- set PMB -------*/
+ write32 PASCR_A, PASCR_29BIT_D
+ write32 MMUCR_A, MMUCR_D
+
+ /*****************************************************************
+ * ent virt phys v sz c wt
+ * 0 0xa0000000 0x00000000 1 64M 0 0
+ * 1 0xa4000000 0x04000000 1 16M 0 0
+ * 2 0xa6000000 0x08000000 1 16M 0 0
+ * 9 0x88000000 0x48000000 1 128M 1 1
+ * 10 0x90000000 0x50000000 1 128M 1 1
+ * 11 0x98000000 0x58000000 1 128M 1 1
+ * 13 0xa8000000 0x48000000 1 128M 0 0
+ * 14 0xb0000000 0x50000000 1 128M 0 0
+ * 15 0xb8000000 0x58000000 1 128M 0 0
+ */
+ write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D
+ write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D
+ write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D
+ write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D
+ write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D
+ write32 PMB_DATA_USB_A, PMB_DATA_USB_D
+ write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
+ write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
+ write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D
+ write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D
+ write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D
+ write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D
+ write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
+ write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
+ write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D
+ write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D
+ write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D
+ write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D
+
+ write32 PASCR_A, PASCR_INIT
+ mov.l DUMMY_ADDR, r0
+ icbi @r0
+#endif
+
+ write32 CCR_A, CCR_D
+
+ rts
+ nop
+
+ .align 4
+
+/*------- GPIO -------*/
+/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */
+PXCR_D: .word 0x0000
+
+PHCR_D: .word 0x00c0
+PJCR_D: .word 0xc3fc
+PKCR_D: .word 0x03ff
+PMCR_D: .word 0xffff
+PNCR_D: .word 0xf0c3
+
+PEPUPR_D: .long 0xff
+PHPUPR_D: .long 0x00
+PJPUPR_D: .long 0x00
+PKPUPR_D: .long 0x00
+PLPUPR_D: .long 0x00
+PMPUPR_D: .long 0xfc
+PNPUPR_D: .long 0x00
+PPUPR1_D: .word 0xffbf
+PPUPR2_D: .word 0xff00
+P1MSELR_D: .word 0x3780
+P2MSELR_D: .word 0x0000
+
+#define GPIO_BASE 0xffe70000
+PACR_A: .long GPIO_BASE + 0x00
+PBCR_A: .long GPIO_BASE + 0x02
+PCCR_A: .long GPIO_BASE + 0x04
+PDCR_A: .long GPIO_BASE + 0x06
+PECR_A: .long GPIO_BASE + 0x08
+PFCR_A: .long GPIO_BASE + 0x0a
+PGCR_A: .long GPIO_BASE + 0x0c
+PHCR_A: .long GPIO_BASE + 0x0e
+PJCR_A: .long GPIO_BASE + 0x10
+PKCR_A: .long GPIO_BASE + 0x12
+PLCR_A: .long GPIO_BASE + 0x14
+PMCR_A: .long GPIO_BASE + 0x16
+PNCR_A: .long GPIO_BASE + 0x18
+PPCR_A: .long GPIO_BASE + 0x1a
+PQCR_A: .long GPIO_BASE + 0x1c
+PRCR_A: .long GPIO_BASE + 0x1e
+PEPUPR_A: .long GPIO_BASE + 0x48
+PHPUPR_A: .long GPIO_BASE + 0x4e
+PJPUPR_A: .long GPIO_BASE + 0x50
+PKPUPR_A: .long GPIO_BASE + 0x52
+PLPUPR_A: .long GPIO_BASE + 0x54
+PMPUPR_A: .long GPIO_BASE + 0x56
+PNPUPR_A: .long GPIO_BASE + 0x58
+PPUPR1_A: .long GPIO_BASE + 0x60
+PPUPR2_A: .long GPIO_BASE + 0x62
+P1MSELR_A: .long GPIO_BASE + 0x80
+P2MSELR_A: .long GPIO_BASE + 0x82
+
+MMSELR_A: .long 0xfc400020
+#if defined(CONFIG_SH_32BIT)
+MMSELR_D: .long 0xa5a50005
+#else
+MMSELR_D: .long 0xa5a50002
+#endif
+
+/*------- DBSC2 -------*/
+#define DBSC2_BASE 0xfe800000
+DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
+DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
+DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
+DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
+DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
+DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
+DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
+DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
+DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
+DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
+DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
+DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
+DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54
+DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
+DDR_DUMMY_ACCESS_A: .long 0x40000000
+
+DBSC2_DBCONF_D: .long 0x00630002
+DBSC2_DBTR0_D: .long 0x050b1f04
+DBSC2_DBTR1_D: .long 0x00040204
+DBSC2_DBTR2_D: .long 0x02100308
+DBSC2_DBFREQ_D1: .long 0x00000000
+DBSC2_DBFREQ_D2: .long 0x00000100
+DBSC2_DBDICODTOCD_D:.long 0x000f0907
+
+DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
+DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
+DBSC2_DBCMDCNT_D_REF: .long 0x00000004
+
+DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
+DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
+DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
+DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
+DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
+DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
+
+DBSC2_DBEN_D: .long 0x00000001
+
+DBSC2_DBPDCNT0_D3: .long 0x00000080
+DBSC2_DBRFCNT1_D: .long 0x00000926
+DBSC2_DBRFCNT2_D: .long 0x00fe00fe
+DBSC2_DBRFCNT0_D: .long 0x00010000
+
+WAIT_200US: .long 33333
+
+/*------- LBSC -------*/
+PASCR_A: .long 0xff000070
+PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
+
+BCR_A: .long BCR
+CS0BCR_A: .long CS0BCR
+CS0WCR_A: .long CS0WCR
+CS1BCR_A: .long CS1BCR
+CS1WCR_A: .long CS1WCR
+CS2BCR_A: .long CS2BCR
+CS2WCR_A: .long CS2WCR
+CS3BCR_A: .long CS3BCR
+CS3WCR_A: .long CS3WCR
+CS4BCR_A: .long CS4BCR
+CS4WCR_A: .long CS4WCR
+CS5BCR_A: .long CS5BCR
+CS5WCR_A: .long CS5WCR
+CS6BCR_A: .long CS6BCR
+CS6WCR_A: .long CS6WCR
+
+BCR_D: .long 0x80000003
+CS0BCR_D: .long 0x22222340
+CS0WCR_D: .long 0x00111118
+CS1BCR_D: .long 0x11111100
+CS1WCR_D: .long 0x33333303
+CS4BCR_D: .long 0x11111300
+CS4WCR_D: .long 0x00101012
+
+/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
+CS_USB_BCR_D: .long 0x11111200
+CS_USB_WCR_D: .long 0x00020005
+
+/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
+CS_SD_BCR_D: .long 0x00000300
+CS_SD_WCR_D: .long 0x00030108
+
+/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
+CS_I2C_BCR_D: .long 0x11111100
+CS_I2C_WCR_D: .long 0x00000003
+
+#if defined(CONFIG_SH_32BIT)
+/*------- set PMB -------*/
+PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0)
+PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1)
+PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2)
+PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9)
+PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10)
+PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11)
+PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13)
+PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14)
+PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15)
+
+PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0)
+PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4)
+PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6)
+PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
+PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90)
+PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98)
+PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
+PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0)
+PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8)
+
+PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0)
+PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1)
+PMB_DATA_USB_A: .long PMB_DATA_BASE(2)
+PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9)
+PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10)
+PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11)
+PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13)
+PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14)
+PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15)
+
+/* ppn ub v s1 s0 c wt */
+PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
+PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
+PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
+PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
+
+DUMMY_ADDR: .long 0xa0000000
+PASCR_29BIT_D: .long 0x00000000
+PASCR_INIT: .long 0x80000080 /* check booting mode */
+MMUCR_A: .long 0xff000010
+MMUCR_D: .long 0x00000004 /* clear ITLB */
+#endif /* CONFIG_SH_32BIT */
+
+CCR_A: .long 0xff00001c
+CCR_D: .long 0x0000090b
diff --git a/board/renesas/sh7785lcr/rtl8169.h b/board/renesas/sh7785lcr/rtl8169.h
new file mode 100644
index 0000000..888de48
--- /dev/null
+++ b/board/renesas/sh7785lcr/rtl8169.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define PCIREG_8(_adr) (*(volatile unsigned char *)(_adr))
+#define PCIREG_32(_adr) (*(volatile unsigned long *)(_adr))
+#define PCI_PAR PCIREG_32(0xfe0401c0)
+#define PCI_PDR PCIREG_32(0xfe040220)
+#define PCI_CR PCIREG_32(0xfe040100)
+#define PCI_CONF1 PCIREG_32(0xfe040004)
+
+#define HIGH 1
+#define LOW 0
+
+#define PCI_PROG 0x80
+#define PCI_EEP_ADDRESS (unsigned short)0x0007
+#define PCI_MAC_ADDRESS_SIZE 3
+
+#define TIME1 100
+#define TIME2 20000
+
+#define BIT_DUMMY 0
+#define MAC_EEP_READ 1
+#define MAC_EEP_WRITE 2
+#define MAC_EEP_ERACE 3
+#define MAC_EEP_EWEN 4
+#define MAC_EEP_EWDS 5
+
+/* RTL8169 */
+const unsigned short EEPROM_W_Data_8169_A[] = {
+ 0x8129, 0x10ec, 0x8169, 0x1154, 0x032b,
+ 0x4020, 0xa101
+};
+const unsigned short EEPROM_W_Data_8169_B[] = {
+ 0x4d15, 0xf7c2, 0x8000, 0x0000, 0x0000, 0x1300,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+};
diff --git a/board/renesas/sh7785lcr/rtl8169_mac.c b/board/renesas/sh7785lcr/rtl8169_mac.c
new file mode 100644
index 0000000..c91ebdc
--- /dev/null
+++ b/board/renesas/sh7785lcr/rtl8169_mac.c
@@ -0,0 +1,331 @@
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "rtl8169.h"
+
+static unsigned char *PCI_MEMR;
+
+static void mac_delay(unsigned int cnt)
+{
+ udelay(cnt);
+}
+
+static void mac_pci_setup(void)
+{
+ unsigned long pci_data;
+
+ PCI_PAR = 0x00000010;
+ PCI_PDR = 0x00001000;
+ PCI_PAR = 0x00000004;
+ pci_data = PCI_PDR;
+ PCI_PDR = pci_data | 0x00000007;
+ PCI_PAR = 0x00000010;
+
+ PCI_MEMR = (unsigned char *)((PCI_PDR | 0xFE240050) & 0xFFFFFFF0);
+}
+
+static void EECS(int level)
+{
+ unsigned char data = *PCI_MEMR;
+
+ if (level)
+ *PCI_MEMR = data | 0x08;
+ else
+ *PCI_MEMR = data & 0xf7;
+}
+
+static void EECLK(int level)
+{
+ unsigned char data = *PCI_MEMR;
+
+ if (level)
+ *PCI_MEMR = data | 0x04;
+ else
+ *PCI_MEMR = data & 0xfb;
+}
+
+static void EEDI(int level)
+{
+ unsigned char data = *PCI_MEMR;
+
+ if (level)
+ *PCI_MEMR = data | 0x02;
+ else
+ *PCI_MEMR = data & 0xfd;
+}
+
+static inline void sh7785lcr_bitset(unsigned short bit)
+{
+ if (bit)
+ EEDI(HIGH);
+ else
+ EEDI(LOW);
+
+ EECLK(LOW);
+ mac_delay(TIME1);
+ EECLK(HIGH);
+ mac_delay(TIME1);
+ EEDI(LOW);
+}
+
+static inline unsigned char sh7785lcr_bitget(void)
+{
+ unsigned char bit;
+
+ EECLK(LOW);
+ mac_delay(TIME1);
+ bit = *PCI_MEMR & 0x01;
+ EECLK(HIGH);
+ mac_delay(TIME1);
+
+ return bit;
+}
+
+static inline void sh7785lcr_setcmd(unsigned char command)
+{
+ sh7785lcr_bitset(BIT_DUMMY);
+ switch (command) {
+ case MAC_EEP_READ:
+ sh7785lcr_bitset(1);
+ sh7785lcr_bitset(1);
+ sh7785lcr_bitset(0);
+ break;
+ case MAC_EEP_WRITE:
+ sh7785lcr_bitset(1);
+ sh7785lcr_bitset(0);
+ sh7785lcr_bitset(1);
+ break;
+ case MAC_EEP_ERACE:
+ sh7785lcr_bitset(1);
+ sh7785lcr_bitset(1);
+ sh7785lcr_bitset(1);
+ break;
+ case MAC_EEP_EWEN:
+ sh7785lcr_bitset(1);
+ sh7785lcr_bitset(0);
+ sh7785lcr_bitset(0);
+ break;
+ case MAC_EEP_EWDS:
+ sh7785lcr_bitset(1);
+ sh7785lcr_bitset(0);
+ sh7785lcr_bitset(0);
+ break;
+ default:
+ break;
+ }
+}
+
+static inline unsigned short sh7785lcr_getdt(void)
+{
+ unsigned short data = 0;
+ int i;
+
+ sh7785lcr_bitget(); /* DUMMY */
+ for (i = 0 ; i < 16 ; i++) {
+ data <<= 1;
+ data |= sh7785lcr_bitget();
+ }
+ return data;
+}
+
+static inline void sh7785lcr_setadd(unsigned short address)
+{
+ sh7785lcr_bitset(address & 0x0020); /* A5 */
+ sh7785lcr_bitset(address & 0x0010); /* A4 */
+ sh7785lcr_bitset(address & 0x0008); /* A3 */
+ sh7785lcr_bitset(address & 0x0004); /* A2 */
+ sh7785lcr_bitset(address & 0x0002); /* A1 */
+ sh7785lcr_bitset(address & 0x0001); /* A0 */
+}
+
+static inline void sh7785lcr_setdata(unsigned short data)
+{
+ sh7785lcr_bitset(data & 0x8000);
+ sh7785lcr_bitset(data & 0x4000);
+ sh7785lcr_bitset(data & 0x2000);
+ sh7785lcr_bitset(data & 0x1000);
+ sh7785lcr_bitset(data & 0x0800);
+ sh7785lcr_bitset(data & 0x0400);
+ sh7785lcr_bitset(data & 0x0200);
+ sh7785lcr_bitset(data & 0x0100);
+ sh7785lcr_bitset(data & 0x0080);
+ sh7785lcr_bitset(data & 0x0040);
+ sh7785lcr_bitset(data & 0x0020);
+ sh7785lcr_bitset(data & 0x0010);
+ sh7785lcr_bitset(data & 0x0008);
+ sh7785lcr_bitset(data & 0x0004);
+ sh7785lcr_bitset(data & 0x0002);
+ sh7785lcr_bitset(data & 0x0001);
+}
+
+static void sh7785lcr_datawrite(const unsigned short *data, unsigned short address,
+ unsigned int count)
+{
+ unsigned int i;
+
+ for (i = 0; i < count; i++) {
+ EECS(HIGH);
+ EEDI(LOW);
+ mac_delay(TIME1);
+
+ sh7785lcr_setcmd(MAC_EEP_WRITE);
+ sh7785lcr_setadd(address++);
+ sh7785lcr_setdata(*(data + i));
+
+ EECLK(LOW);
+ EEDI(LOW);
+ EECS(LOW);
+ mac_delay(TIME2);
+ }
+}
+
+static void sh7785lcr_macerase(void)
+{
+ unsigned int i;
+ unsigned short pci_address = 7;
+
+ for (i = 0; i < 3; i++) {
+ EECS(HIGH);
+ EEDI(LOW);
+ mac_delay(TIME1);
+ sh7785lcr_setcmd(MAC_EEP_ERACE);
+ sh7785lcr_setadd(pci_address++);
+ mac_delay(TIME1);
+ EECLK(LOW);
+ EEDI(LOW);
+ EECS(LOW);
+ }
+
+ mac_delay(TIME2);
+
+ printf("\n\nErace End\n");
+ for (i = 0; i < 10; i++)
+ mac_delay(TIME2);
+}
+
+static void sh7785lcr_macwrite(unsigned short *data)
+{
+ sh7785lcr_macerase();
+
+ sh7785lcr_datawrite(EEPROM_W_Data_8169_A, 0x0000, 7);
+ sh7785lcr_datawrite(data, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE);
+ sh7785lcr_datawrite(EEPROM_W_Data_8169_B, 0x000a, 54);
+}
+
+void sh7785lcr_macdtrd(unsigned char *buf, unsigned short address, unsigned int count)
+{
+ unsigned int i;
+ unsigned short wk;
+
+ for (i = 0 ; i < count; i++) {
+ EECS(HIGH);
+ EEDI(LOW);
+ mac_delay(TIME1);
+ sh7785lcr_setcmd(MAC_EEP_READ);
+ sh7785lcr_setadd(address++);
+ wk = sh7785lcr_getdt();
+
+ *buf++ = (unsigned char)(wk & 0xff);
+ *buf++ = (unsigned char)((wk >> 8) & 0xff);
+ EECLK(LOW);
+ EEDI(LOW);
+ EECS(LOW);
+ }
+}
+
+static void sh7785lcr_macadrd(unsigned char *buf)
+{
+ *PCI_MEMR = PCI_PROG;
+
+ sh7785lcr_macdtrd(buf, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE);
+}
+
+static void sh7785lcr_eepewen(void)
+{
+ *PCI_MEMR = PCI_PROG;
+ mac_delay(TIME1);
+ EECS(LOW);
+ EECLK(LOW);
+ EEDI(LOW);
+ EECS(HIGH);
+ mac_delay(TIME1);
+
+ sh7785lcr_setcmd(MAC_EEP_EWEN);
+ sh7785lcr_bitset(1);
+ sh7785lcr_bitset(1);
+ sh7785lcr_bitset(BIT_DUMMY);
+ sh7785lcr_bitset(BIT_DUMMY);
+ sh7785lcr_bitset(BIT_DUMMY);
+ sh7785lcr_bitset(BIT_DUMMY);
+
+ EECLK(LOW);
+ EEDI(LOW);
+ EECS(LOW);
+ mac_delay(TIME1);
+}
+
+void mac_write(unsigned short *data)
+{
+ mac_pci_setup();
+ sh7785lcr_eepewen();
+ sh7785lcr_macwrite(data);
+}
+
+void mac_read(void)
+{
+ unsigned char data[6];
+
+ mac_pci_setup();
+ sh7785lcr_macadrd(data);
+ printf("Mac = %02x:%02x:%02x:%02x:%02x:%02x\n",
+ data[0], data[1], data[2], data[3], data[4], data[5]);
+}
+
+int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i;
+ unsigned char mac[6];
+ char *s, *e;
+
+ if (argc != 2)
+ return cmd_usage(cmdtp);
+
+ s = argv[1];
+
+ for (i = 0; i < 6; i++) {
+ mac[i] = s ? simple_strtoul(s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+ mac_write((unsigned short *)mac);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ setmac, 2, 1, do_set_mac,
+ "write MAC address for RTL8110SCL",
+ "\n"
+ "setmac <mac address> - write MAC address for RTL8110SCL"
+);
+
+int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc != 1)
+ return cmd_usage(cmdtp);
+
+ mac_read();
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ printmac, 1, 1, do_print_mac,
+ "print MAC address for RTL8110",
+ "\n"
+ " - print MAC address for RTL8110"
+);
diff --git a/board/renesas/sh7785lcr/selfcheck.c b/board/renesas/sh7785lcr/selfcheck.c
new file mode 100644
index 0000000..d520750
--- /dev/null
+++ b/board/renesas/sh7785lcr/selfcheck.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/pci.h>
+
+#if defined(CONFIG_CPU_32BIT)
+#define NOCACHE_OFFSET 0x00000000
+#else
+#define NOCACHE_OFFSET 0xa0000000
+#endif
+#define PLD_LEDCR (0x04000008 + NOCACHE_OFFSET)
+#define PLD_SWSR (0x0400000a + NOCACHE_OFFSET)
+#define PLD_VERSR (0x0400000c + NOCACHE_OFFSET)
+
+#define SM107_DEVICEID (0x13e00060 + NOCACHE_OFFSET)
+
+static void test_pld(void)
+{
+ printf("PLD version = %04x\n", readb(PLD_VERSR));
+}
+
+static void test_sm107(void)
+{
+ printf("SM107 device ID = %04x\n", readl(SM107_DEVICEID));
+}
+
+static void test_led(void)
+{
+ printf("turn on LEDs 3, 5, 7, 9\n");
+ writeb(0x55, PLD_LEDCR);
+ mdelay(2000);
+ printf("turn on LEDs 4, 6, 8, 10\n");
+ writeb(0xaa, PLD_LEDCR);
+ mdelay(2000);
+ writeb(0x00, PLD_LEDCR);
+}
+
+static void test_dipsw(void)
+{
+ printf("Please DIPSW set = B'0101\n");
+ while (readb(PLD_SWSR) != 0x05) {
+ if (ctrlc())
+ return;
+ }
+ printf("Please DIPSW set = B'1010\n");
+ while (readb(PLD_SWSR) != 0x0A) {
+ if (ctrlc())
+ return;
+ }
+ printf("DIPSW OK\n");
+}
+
+static void test_net(void)
+{
+ unsigned long data;
+
+ writel(0x80000000, 0xfe0401c0);
+ data = readl(0xfe040220);
+ if (data == 0x816910ec)
+ printf("Ethernet OK\n");
+ else
+ printf("Ethernet NG, data = %08x\n", (unsigned int)data);
+}
+
+static void test_sata(void)
+{
+ unsigned long data;
+
+ writel(0x80000800, 0xfe0401c0);
+ data = readl(0xfe040220);
+ if (data == 0x35121095)
+ printf("SATA OK\n");
+ else
+ printf("SATA NG, data = %08x\n", (unsigned int)data);
+}
+
+static void test_pci(void)
+{
+ writel(0x80001800, 0xfe0401c0);
+ printf("PCI CN1 ID = %08x\n", readl(0xfe040220));
+
+ writel(0x80001000, 0xfe0401c0);
+ printf("PCI CN2 ID = %08x\n", readl(0xfe040220));
+}
+
+int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *cmd;
+
+ if (argc != 2)
+ return cmd_usage(cmdtp);
+
+ cmd = argv[1];
+ switch (cmd[0]) {
+ case 'a': /* all */
+ test_pld();
+ test_led();
+ test_dipsw();
+ test_sm107();
+ test_net();
+ test_sata();
+ test_pci();
+ break;
+ case 'p': /* pld or pci */
+ if (cmd[1] == 'l')
+ test_pld();
+ else
+ test_pci();
+ break;
+ case 'l': /* led */
+ test_led();
+ break;
+ case 'd': /* dipsw */
+ test_dipsw();
+ break;
+ case 's': /* sm107 or sata */
+ if (cmd[1] == 'm')
+ test_sm107();
+ else
+ test_sata();
+ break;
+ case 'n': /* net */
+ test_net();
+ break;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ hwtest, 2, 1, do_hw_test,
+ "hardware test for R0P7785LC0011RL board",
+ "\n"
+ "hwtest all - test all hardware\n"
+ "hwtest pld - output PLD version\n"
+ "hwtest led - turn on LEDs\n"
+ "hwtest dipsw - test DIP switch\n"
+ "hwtest sm107 - output SM107 version\n"
+ "hwtest net - check RTL8110 ID\n"
+ "hwtest sata - check SiI3512 ID\n"
+ "hwtest pci - output PCI slot device ID"
+);
diff --git a/board/renesas/sh7785lcr/sh7785lcr.c b/board/renesas/sh7785lcr/sh7785lcr.c
new file mode 100644
index 0000000..622e602
--- /dev/null
+++ b/board/renesas/sh7785lcr/sh7785lcr.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/pci.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+static struct pci_controller hose;
+void pci_init_board(void)
+{
+ pci_sh7780_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_SH_32BIT)
+int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ /* clear ITLB */
+ writel(0x00000004, 0xff000010);
+
+ /* delete PMB for peripheral */
+ writel(0, PMB_ADDR_BASE(0));
+ writel(0, PMB_DATA_BASE(0));
+ writel(0, PMB_ADDR_BASE(1));
+ writel(0, PMB_DATA_BASE(1));
+ writel(0, PMB_ADDR_BASE(2));
+ writel(0, PMB_DATA_BASE(2));
+
+ /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
+ writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8));
+ writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8));
+ writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12));
+ writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12));
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ pmb, 1, 1, do_pmb,
+ "pmb - PMB setting\n",
+ "\n"
+ " - PMB setting for all SDRAM mapping"
+);
+#endif
diff --git a/board/ronetix/pm9261/Kconfig b/board/ronetix/pm9261/Kconfig
new file mode 100644
index 0000000..a4934c5
--- /dev/null
+++ b/board/ronetix/pm9261/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PM9261
+
+config SYS_BOARD
+ default "pm9261"
+
+config SYS_VENDOR
+ default "ronetix"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "pm9261"
+
+endif
diff --git a/board/ronetix/pm9261/MAINTAINERS b/board/ronetix/pm9261/MAINTAINERS
new file mode 100644
index 0000000..a09b6c0
--- /dev/null
+++ b/board/ronetix/pm9261/MAINTAINERS
@@ -0,0 +1,6 @@
+PM9261 BOARD
+M: Ilko Iliev <iliev@ronetix.at>
+S: Maintained
+F: board/ronetix/pm9261/
+F: include/configs/pm9261.h
+F: configs/pm9261_defconfig
diff --git a/board/ronetix/pm9261/Makefile b/board/ronetix/pm9261/Makefile
new file mode 100644
index 0000000..3860283
--- /dev/null
+++ b/board/ronetix/pm9261/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+# Ilko Iliev <www.ronetix.at>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += pm9261.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c
new file mode 100644
index 0000000..cc4c2a0
--- /dev/null
+++ b/board/ronetix/pm9261/led.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+
+void coloured_LED_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+
+ gpio_direction_output(CONFIG_RED_LED, 1);
+ gpio_direction_output(CONFIG_GREEN_LED, 1);
+ gpio_direction_output(CONFIG_YELLOW_LED, 1);
+
+ gpio_set_value(CONFIG_RED_LED, 0);
+ gpio_set_value(CONFIG_GREEN_LED, 1);
+ gpio_set_value(CONFIG_YELLOW_LED, 1);
+}
diff --git a/board/ronetix/pm9261/partition.c b/board/ronetix/pm9261/partition.c
new file mode 100644
index 0000000..23ab8cf
--- /dev/null
+++ b/board/ronetix/pm9261/partition.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+};
+
+/*define the area offsets*/
+#ifdef CONFIG_SYS_USE_DATAFLASH
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
+};
+#else
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, ""},
+};
+
+#endif
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
new file mode 100644
index 0000000..1f7679a
--- /dev/null
+++ b/board/ronetix/pm9261/pm9261.c
@@ -0,0 +1,311 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
+ * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#include <dataflash.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void pm9261_nand_hw_init(void)
+{
+ unsigned long csa;
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+ writel(1 << ATMEL_ID_PIOA |
+ 1 << ATMEL_ID_PIOC,
+ &pmc->pcer);
+
+ /* Configure RDY/BSY */
+ gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+ /* Enable NandFlash */
+ gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
+}
+#endif
+
+
+#ifdef CONFIG_DRIVER_DM9000
+static void pm9261_dm9000_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Configure SMC CS2 for DM9000 */
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[2].setup);
+
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
+ &smc->cs[2].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
+ &smc->cs[2].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
+ AT91_SMC_MODE_TDF_CYCLE(1),
+ &smc->cs[2].mode);
+
+ /* Configure Interrupt pin as input, no pull-up */
+ writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
+ at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 240,
+ .vl_row = 320,
+ .vl_clk = 4965000,
+ .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = 3,
+ .vl_tft = 1,
+ .vl_hsync_len = 5,
+ .vl_left_margin = 1,
+ .vl_right_margin = 33,
+ .vl_vsync_len = 1,
+ .vl_upper_margin = 1,
+ .vl_lower_margin = 0,
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+ at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */
+}
+
+static void pm9261_lcd_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */
+ at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */
+ at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */
+ at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */
+ at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */
+ at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */
+ at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */
+ at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */
+ at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */
+ at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */
+
+ writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
+
+ gd->fb_base = ATMEL_BASE_SRAM;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+extern flash_info_t flash_info[];
+
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size, flash_size, dataflash_size;
+ int i;
+ char temp[32];
+
+ lcd_printf ("%s\n", U_BOOT_VERSION);
+ lcd_printf ("(C) 2009 Ronetix GmbH\n");
+ lcd_printf ("support@ronetix.at\n");
+ lcd_printf ("%s CPU at %s MHz",
+ CONFIG_SYS_AT91_CPU_NAME,
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+
+ flash_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+ flash_size += flash_info[i].size;
+
+ dataflash_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
+ dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
+ dataflash_info[i].Device.pages_size;
+
+ lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
+ "%ld MB DataFlash\n",
+ dram_size >> 20,
+ nand_size >> 20,
+ flash_size >> 20,
+ dataflash_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+
+#endif /* CONFIG_LCD */
+
+int board_early_init_f(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clocks for some PIOs */
+ writel(1 << ATMEL_ID_PIOA |
+ 1 << ATMEL_ID_PIOC,
+ &pmc->pcer);
+
+ at91_seriald_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of PM9261-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_PM9261;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ pm9261_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+ pm9261_dm9000_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ pm9261_lcd_hw_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_DRIVER_DM9000
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard (void)
+{
+ char buf[32];
+
+ printf ("Board : Ronetix PM9261\n");
+ printf ("Crystal frequency: %8s MHz\n",
+ strmhz(buf, get_main_clk_rate()));
+ printf ("CPU clock : %8s MHz\n",
+ strmhz(buf, get_cpu_clk_rate()));
+ printf ("Master clock : %8s MHz\n",
+ strmhz(buf, get_mck_clk_rate()));
+
+ return 0;
+}
+#endif
diff --git a/board/ronetix/pm9263/Kconfig b/board/ronetix/pm9263/Kconfig
new file mode 100644
index 0000000..339a6ea
--- /dev/null
+++ b/board/ronetix/pm9263/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PM9263
+
+config SYS_BOARD
+ default "pm9263"
+
+config SYS_VENDOR
+ default "ronetix"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "pm9263"
+
+endif
diff --git a/board/ronetix/pm9263/MAINTAINERS b/board/ronetix/pm9263/MAINTAINERS
new file mode 100644
index 0000000..f26e82a
--- /dev/null
+++ b/board/ronetix/pm9263/MAINTAINERS
@@ -0,0 +1,6 @@
+PM9263 BOARD
+M: Ilko Iliev <iliev@ronetix.at>
+S: Maintained
+F: board/ronetix/pm9263/
+F: include/configs/pm9263.h
+F: configs/pm9263_defconfig
diff --git a/board/ronetix/pm9263/Makefile b/board/ronetix/pm9263/Makefile
new file mode 100644
index 0000000..43ea599
--- /dev/null
+++ b/board/ronetix/pm9263/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+# Ilko Iliev <www.ronetix.at>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += pm9263.o
+obj-y += led.o
+obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c
new file mode 100644
index 0000000..bfc2310
--- /dev/null
+++ b/board/ronetix/pm9263/led.c
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+
+void coloured_LED_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
+
+ gpio_direction_output(CONFIG_RED_LED, 1);
+ gpio_direction_output(CONFIG_GREEN_LED, 1);
+
+ gpio_set_value(CONFIG_RED_LED, 0);
+ gpio_set_value(CONFIG_GREEN_LED, 1);
+}
diff --git a/board/ronetix/pm9263/partition.c b/board/ronetix/pm9263/partition.c
new file mode 100644
index 0000000..9cc4214
--- /dev/null
+++ b/board/ronetix/pm9263/partition.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+};
+
+/*define the area offsets*/
+#ifdef CONFIG_SYS_USE_DATAFLASH
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+ {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
+};
+#else
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, ""},
+};
+
+#endif
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
new file mode 100644
index 0000000..1b00f08
--- /dev/null
+++ b/board/ronetix/pm9263/pm9263.c
@@ -0,0 +1,418 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#include <dataflash.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void pm9263_nand_hw_init(void)
+{
+ unsigned long csa;
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa[0]);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+ /* Configure RDY/BSY */
+ gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+ /* Enable NandFlash */
+ gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void pm9263_macb_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /*
+ * PB27 enables the 50MHz oscillator for Ethernet PHY
+ * 1 - enable
+ * 0 - disable
+ */
+ at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
+ at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PC25) => PHY normal mode (not Test mode)
+ * ERX0 (PE25) => PHY ADDR0
+ * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+
+ at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
+
+ /* Re-enable pull-up */
+ at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
+
+ at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ .vl_col = 240,
+ .vl_row = 320,
+ .vl_clk = 4965000,
+ .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = 3,
+ .vl_tft = 1,
+ .vl_hsync_len = 5,
+ .vl_left_margin = 1,
+ .vl_right_margin = 33,
+ .vl_vsync_len = 1,
+ .vl_upper_margin = 1,
+ .vl_lower_margin = 0,
+ .mmio = ATMEL_BASE_LCDC,
+};
+
+void lcd_enable(void)
+{
+ at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
+}
+
+#ifdef CONFIG_LCD_IN_PSRAM
+
+#define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
+#define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
+
+/* Initialize the PSRAM memory */
+static int pm9263_lcd_hw_psram_init(void)
+{
+ unsigned long csa;
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+ /* Enable CS3 3.3v, no pull-ups */
+ csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
+ AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
+
+ writel(csa, &matrix->csa[1]);
+
+ /* Configure SMC1 CS0 for PSRAM - 16-bit */
+ writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[0].setup);
+
+ writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
+ AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
+ &smc->cs[0].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+ &smc->cs[0].cycle);
+
+ writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
+ &smc->cs[0].mode);
+
+ /* setup PB29 as output */
+ at91_set_pio_output(PSRAM_CRE_PIN, 1);
+
+ at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
+
+ /* PSRAM: write BCR */
+ readw(PSRAM_CTRL_REG);
+ readw(PSRAM_CTRL_REG);
+ writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
+ writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
+
+ /* write RCR of the PSRAM */
+ readw(PSRAM_CTRL_REG);
+ readw(PSRAM_CTRL_REG);
+ writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
+ /* set RCR; 0x10-async mode,0x90-page mode */
+ writew(0x90, PSRAM_CTRL_REG);
+
+ /*
+ * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
+ * MT45W2M16B - CRE must be 0
+ * MT45W2M16A - CRE must be 1
+ */
+ writew(0x1234, PHYS_PSRAM);
+ writew(0x5678, PHYS_PSRAM + 2);
+
+ /* test if the chip is MT45W2M16B */
+ if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
+ /* try with CRE=1 (MT45W2M16A) */
+ at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
+
+ /* write RCR of the PSRAM */
+ readw(PSRAM_CTRL_REG);
+ readw(PSRAM_CTRL_REG);
+ writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
+ /* set RCR;0x10-async mode,0x90-page mode */
+ writew(0x90, PSRAM_CTRL_REG);
+
+
+ writew(0x1234, PHYS_PSRAM);
+ writew(0x5678, PHYS_PSRAM+2);
+ if ((readw(PHYS_PSRAM) != 0x1234)
+ || (readw(PHYS_PSRAM + 2) != 0x5678))
+ return 1;
+
+ }
+
+ /* Bus matrix */
+ writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
+ writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
+
+ return 0;
+}
+#endif
+
+static void pm9263_lcd_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
+ at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
+ at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
+ at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
+ at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
+
+ writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+
+ /* Power Control */
+ at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
+ at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
+
+#ifdef CONFIG_LCD_IN_PSRAM
+ /* initialize te PSRAM */
+ int stat = pm9263_lcd_hw_psram_init();
+
+ gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
+#else
+ gd->fb_base = ATMEL_BASE_SRAM0;
+#endif
+
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+extern flash_info_t flash_info[];
+
+void lcd_show_board_info(void)
+{
+ ulong dram_size, nand_size, flash_size, dataflash_size;
+ int i;
+ char temp[32];
+
+ lcd_printf ("%s\n", U_BOOT_VERSION);
+ lcd_printf ("(C) 2009 Ronetix GmbH\n");
+ lcd_printf ("support@ronetix.at\n");
+ lcd_printf ("%s CPU at %s MHz",
+ CONFIG_SYS_AT91_CPU_NAME,
+ strmhz(temp, get_cpu_clk_rate()));
+
+ dram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ dram_size += gd->bd->bi_dram[i].size;
+
+ nand_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+ nand_size += nand_info[i].size;
+
+ flash_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+ flash_size += flash_info[i].size;
+
+ dataflash_size = 0;
+ for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
+ dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
+ dataflash_info[i].Device.pages_size;
+
+ lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
+ "4 MB PSRAM, %ld MB DataFlash\n",
+ dram_size >> 20,
+ nand_size >> 20,
+ flash_size >> 20,
+ dataflash_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+
+#endif /* CONFIG_LCD */
+
+int board_early_init_f(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clocks for all PIOs */
+ writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOCDE),
+ &pmc->pcer);
+
+ at91_seriald_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of AT91SAM9263EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_PM9263;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ pm9263_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+ pm9263_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+ at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ pm9263_lcd_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
+#endif
+ return rc;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard (void)
+{
+ char *ss;
+
+ printf ("Board : Ronetix PM9263\n");
+
+ switch (gd->fb_base) {
+ case PHYS_PSRAM:
+ ss = "(PSRAM)";
+ break;
+
+ case ATMEL_BASE_SRAM0:
+ ss = "(Internal SRAM)";
+ break;
+
+ default:
+ ss = "";
+ break;
+ }
+ printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
+
+ printf ("\n");
+ return 0;
+}
+#endif
diff --git a/board/ronetix/pm9g45/Kconfig b/board/ronetix/pm9g45/Kconfig
new file mode 100644
index 0000000..65fc5c4
--- /dev/null
+++ b/board/ronetix/pm9g45/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PM9G45
+
+config SYS_BOARD
+ default "pm9g45"
+
+config SYS_VENDOR
+ default "ronetix"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "pm9g45"
+
+endif
diff --git a/board/ronetix/pm9g45/MAINTAINERS b/board/ronetix/pm9g45/MAINTAINERS
new file mode 100644
index 0000000..255a357f
--- /dev/null
+++ b/board/ronetix/pm9g45/MAINTAINERS
@@ -0,0 +1,6 @@
+PM9G45 BOARD
+M: Ilko Iliev <iliev@ronetix.at>
+S: Maintained
+F: board/ronetix/pm9g45/
+F: include/configs/pm9g45.h
+F: configs/pm9g45_defconfig
diff --git a/board/ronetix/pm9g45/Makefile b/board/ronetix/pm9g45/Makefile
new file mode 100644
index 0000000..0a00279
--- /dev/null
+++ b/board/ronetix/pm9g45/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += pm9g45.o
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
new file mode 100644
index 0000000..15aa4ac
--- /dev/null
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2010
+ * Ilko Iliev <iliev@ronetix.at>
+ * Asen Dimov <dimov@ronetix.at>
+ * Ronetix GmbH <www.ronetix.at>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void pm9g45_nand_hw_init(void)
+{
+ unsigned long csa;
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->ccr[6]);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
+ &smc->cs[3].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+
+ writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+
+#ifdef CONFIG_SYS_NAND_READY_PIN
+ /* Configure RDY/BSY */
+ gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+#endif
+
+ /* Enable NandFlash */
+ gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void pm9g45_macb_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /*
+ * PD2 enables the 50MHz oscillator for Ethernet PHY
+ * 1 - enable
+ * 0 - disable
+ */
+ at91_set_pio_output(AT91_PIO_PORTD, 2, 1);
+ at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA15) => PHY normal mode (not Test mode)
+ * ERX0 (PA12) => PHY ADDR0
+ * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
+
+ /* Re-enable pull-up */
+ at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
+
+ at91_macb_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clocks for all PIOs */
+ writel((1 << ATMEL_ID_PIOA) |
+ (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOC) |
+ (1 << ATMEL_ID_PIODE), &pmc->pcer);
+
+ at91_seriald_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of AT91SAM9M10G45EK-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_PM9G45;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ pm9g45_nand_hw_init();
+#endif
+
+#ifdef CONFIG_MACB
+ pm9g45_macb_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
+#endif
+ return rc;
+}
diff --git a/board/samsung/arndale/Kconfig b/board/samsung/arndale/Kconfig
new file mode 100644
index 0000000..b620974
--- /dev/null
+++ b/board/samsung/arndale/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ARNDALE
+
+config SYS_BOARD
+ default "arndale"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "arndale"
+
+endif
diff --git a/board/samsung/arndale/MAINTAINERS b/board/samsung/arndale/MAINTAINERS
new file mode 100644
index 0000000..7dc1785
--- /dev/null
+++ b/board/samsung/arndale/MAINTAINERS
@@ -0,0 +1,6 @@
+ARNDALE BOARD
+M: Chander Kashyap <k.chander@samsung.com>
+S: Maintained
+F: board/samsung/arndale/
+F: include/configs/arndale.h
+F: configs/arndale_defconfig
diff --git a/board/samsung/arndale/Makefile b/board/samsung/arndale/Makefile
new file mode 100644
index 0000000..be2b366
--- /dev/null
+++ b/board/samsung/arndale/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2013 Samsung Electronics
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += arndale_spl.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += arndale.o
+endif
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
new file mode 100644
index 0000000..881d080
--- /dev/null
+++ b/board/samsung/arndale/arndale.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/power.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB_EHCI_EXYNOS
+int board_usb_init(int index, enum usb_init_type init)
+{
+ /* Configure gpios for usb 3503 hub:
+ * disconnect, toggle reset and connect
+ */
+ gpio_request(EXYNOS5_GPIO_D17, "usb_connect");
+ gpio_request(EXYNOS5_GPIO_X35, "usb_reset");
+ gpio_direction_output(EXYNOS5_GPIO_D17, 0);
+ gpio_direction_output(EXYNOS5_GPIO_X35, 0);
+
+ gpio_direction_output(EXYNOS5_GPIO_X35, 1);
+ gpio_direction_output(EXYNOS5_GPIO_D17, 1);
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+ return 0;
+}
+
+int dram_init(void)
+{
+ int i;
+ u32 addr;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+ }
+ return 0;
+}
+
+int power_init_board(void)
+{
+ set_ps_hold_ctrl();
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ int i;
+ u32 addr, size;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+ gd->bd->bi_dram[i].start = addr;
+ gd->bd->bi_dram[i].size = size;
+ }
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ /* dwmmc initializattion for available channels */
+ ret = exynos_dwmmc_init(gd->fdt_blob);
+ if (ret)
+ debug("dwmmc init failed\n");
+
+ return ret;
+}
+#endif
+
+static int board_uart_init(void)
+{
+ int err = 0, uart_id;
+
+ for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+ err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART%d not configured\n",
+ (uart_id - PERIPH_ID_UART0));
+ return err;
+ }
+ }
+ return err;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ int err;
+
+ err = board_uart_init();
+ if (err) {
+ debug("UART init failed\n");
+ return err;
+ }
+ return err;
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("\nBoard: Arndale\n");
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_S5P_PA_SYSRAM
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ writel(addr, CONFIG_S5P_PA_SYSRAM);
+
+ /* make sure this write is really executed */
+ __asm__ volatile ("dsb\n");
+}
+#endif
diff --git a/board/samsung/arndale/arndale_spl.c b/board/samsung/arndale/arndale_spl.c
new file mode 100644
index 0000000..2949c08
--- /dev/null
+++ b/board/samsung/arndale/arndale_spl.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/spl.h>
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(".machine_param"))) = {
+ .signature = SIGNATURE,
+ .version = 1,
+ .params = "vmubfasirM",
+ .size = sizeof(machine_param),
+
+ .mem_iv_size = 0x1f,
+ .mem_type = DDR_MODE_DDR3,
+
+ /*
+ * Set uboot_size to 0x100000 bytes.
+ *
+ * This is an overly conservative value chosen to accommodate all
+ * possible U-Boot image. You are advised to set this value to a
+ * smaller realistic size via scripts that modifies the .machine_param
+ * section of output U-Boot image.
+ */
+ .uboot_size = 0x100000,
+
+ .boot_source = BOOT_MODE_OM,
+ .frequency_mhz = 800,
+ .arm_freq_mhz = 1000,
+ .serial_base = 0x12c30000,
+ .i2c_base = 0x12c60000,
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+ if (machine_param.signature != SIGNATURE) {
+ /* Will hang if SIGNATURE dont match */
+ while (1)
+ ;
+ }
+
+ return &machine_param;
+}
diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile
new file mode 100644
index 0000000..93347ef
--- /dev/null
+++ b/board/samsung/common/Makefile
@@ -0,0 +1,14 @@
+#
+# Copyright (C) 2012 Samsung Electronics
+# Lukasz Majewski <l.majewski@samsung.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
+obj-$(CONFIG_USBDOWNLOAD_GADGET) += gadget.o
+obj-$(CONFIG_MISC_COMMON) += misc.o
+
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_BOARD_COMMON) += board.o
+endif
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
new file mode 100644
index 0000000..8b4c8e9
--- /dev/null
+++ b/board/samsung/common/board.c
@@ -0,0 +1,357 @@
+/*
+ * (C) Copyright 2013 SAMSUNG Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <spi.h>
+#include <tmu.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/board.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/system.h>
+#include <power/pmic.h>
+#include <asm/arch/sromc.h>
+#include <lcd.h>
+#include <samsung/misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int exynos_early_init_f(void)
+{
+ return 0;
+}
+
+__weak int exynos_power_init(void)
+{
+ return 0;
+}
+
+#if defined CONFIG_EXYNOS_TMU
+/* Boot Time Thermal Analysis for SoC temperature threshold breach */
+static void boot_temp_check(void)
+{
+ int temp;
+
+ switch (tmu_monitor(&temp)) {
+ case TMU_STATUS_NORMAL:
+ break;
+ case TMU_STATUS_TRIPPED:
+ /*
+ * Status TRIPPED ans WARNING means corresponding threshold
+ * breach
+ */
+ puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
+ set_ps_hold_ctrl();
+ hang();
+ break;
+ case TMU_STATUS_WARNING:
+ puts("EXYNOS_TMU: WARNING! Temperature very high\n");
+ break;
+ case TMU_STATUS_INIT:
+ /*
+ * TMU_STATUS_INIT means something is wrong with temperature
+ * sensing and TMU status was changed back from NORMAL to INIT.
+ */
+ puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n");
+ break;
+ default:
+ debug("EXYNOS_TMU: Unknown TMU state\n");
+ }
+}
+#endif
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#if defined CONFIG_EXYNOS_TMU
+ if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
+ debug("%s: Failed to init TMU\n", __func__);
+ return -1;
+ }
+ boot_temp_check();
+#endif
+
+ return exynos_init();
+}
+
+int dram_init(void)
+{
+ int i;
+ u32 addr;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+ }
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ int i;
+ u32 addr, size;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+ size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+ gd->bd->bi_dram[i].start = addr;
+ gd->bd->bi_dram[i].size = size;
+ }
+}
+
+static int board_uart_init(void)
+{
+ int err, uart_id, ret = 0;
+
+ for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+ err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART%d not configured\n",
+ (uart_id - PERIPH_ID_UART0));
+ ret |= err;
+ }
+ }
+ return ret;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ int err;
+#ifdef CONFIG_BOARD_TYPES
+ set_board_type();
+#endif
+ err = board_uart_init();
+ if (err) {
+ debug("UART init failed\n");
+ return err;
+ }
+
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+ board_i2c_init(gd->fdt_blob);
+#endif
+
+#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_EXYNOS_FB)
+/*
+ * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
+ * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve
+ * FB memory at a very early stage. So, we need to fill panel_info.vl_col,
+ * panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called.
+ */
+ err = exynos_lcd_early_init(gd->fdt_blob);
+ if (err) {
+ debug("LCD early init failed\n");
+ return err;
+ }
+#endif
+
+ return exynos_early_init_f();
+}
+#endif
+
+#if defined(CONFIG_POWER)
+int power_init_board(void)
+{
+ set_ps_hold_ctrl();
+
+ return exynos_power_init();
+}
+#endif
+
+#ifdef CONFIG_OF_CONTROL
+#ifdef CONFIG_SMC911X
+static int decode_sromc(const void *blob, struct fdt_sromc *config)
+{
+ int err;
+ int node;
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
+ if (node < 0) {
+ debug("Could not find SROMC node\n");
+ return node;
+ }
+
+ config->bank = fdtdec_get_int(blob, node, "bank", 0);
+ config->width = fdtdec_get_int(blob, node, "width", 2);
+
+ err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
+ FDT_SROM_TIMING_COUNT);
+ if (err < 0) {
+ debug("Could not decode SROMC configuration Error: %s\n",
+ fdt_strerror(err));
+ return -FDT_ERR_NOTFOUND;
+ }
+ return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SMC911X
+ u32 smc_bw_conf, smc_bc_conf;
+ struct fdt_sromc config;
+ fdt_addr_t base_addr;
+ int node;
+
+ node = decode_sromc(gd->fdt_blob, &config);
+ if (node < 0) {
+ debug("%s: Could not find sromc configuration\n", __func__);
+ return 0;
+ }
+ node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
+ if (node < 0) {
+ debug("%s: Could not find lan9215 configuration\n", __func__);
+ return 0;
+ }
+
+ /* We now have a node, so any problems from now on are errors */
+ base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+ if (base_addr == FDT_ADDR_T_NONE) {
+ debug("%s: Could not find lan9215 address\n", __func__);
+ return -1;
+ }
+
+ /* Ethernet needs data bus width of 16 bits */
+ if (config.width != 2) {
+ debug("%s: Unsupported bus width %d\n", __func__,
+ config.width);
+ return -1;
+ }
+ smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
+ | SROMC_BYTE_ENABLE(config.bank);
+
+ smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
+ SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
+ SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
+ SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
+ SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
+ SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
+ SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
+
+ /* Select and configure the SROMC bank */
+ exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
+ s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
+ return smc911x_initialize(0, base_addr);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+static int init_mmc(void)
+{
+#ifdef CONFIG_SDHCI
+ return exynos_mmc_init(gd->fdt_blob);
+#else
+ return 0;
+#endif
+}
+
+static int init_dwmmc(void)
+{
+#ifdef CONFIG_DWMMC
+ return exynos_dwmmc_init(gd->fdt_blob);
+#else
+ return 0;
+#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ if (get_boot_mode() == BOOT_MODE_SD) {
+ ret = init_mmc();
+ ret |= init_dwmmc();
+ } else {
+ ret = init_dwmmc();
+ ret |= init_mmc();
+ }
+
+ if (ret)
+ debug("mmc init failed\n");
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ const char *board_info;
+
+ board_info = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+ printf("Board: %s\n", board_info ? board_info : "unknown");
+#ifdef CONFIG_BOARD_TYPES
+ board_info = get_board_type();
+
+ printf("Model: %s\n", board_info ? board_info : "unknown");
+#endif
+ return 0;
+}
+#endif
+#endif /* CONFIG_OF_CONTROL */
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ stdio_print_current_devices();
+
+ if (cros_ec_get_error()) {
+ /* Force console on */
+ gd->flags &= ~GD_FLG_SILENT;
+
+ printf("cros-ec communications failure %d\n",
+ cros_ec_get_error());
+ puts("\nPlease reset with Power+Refresh\n\n");
+ panic("Cannot init cros-ec device");
+ return -1;
+ }
+ return 0;
+}
+#endif
+
+int arch_early_init_r(void)
+{
+#ifdef CONFIG_CROS_EC
+ if (cros_ec_board_init()) {
+ printf("%s: Failed to init EC\n", __func__);
+ return 0;
+ }
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_SET_DFU_ALT_INFO
+ set_dfu_alt_info();
+#endif
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ set_board_info();
+#endif
+#ifdef CONFIG_LCD_MENU
+ keys_init();
+ check_boot_mode();
+#endif
+#ifdef CONFIG_CMD_BMP
+ if (panel_info.logo_on)
+ draw_logo();
+#endif
+ return 0;
+}
+#endif
diff --git a/board/samsung/common/dfu_sample_env.txt b/board/samsung/common/dfu_sample_env.txt
new file mode 100644
index 0000000..d6ee8a2
--- /dev/null
+++ b/board/samsung/common/dfu_sample_env.txt
@@ -0,0 +1,9 @@
+mmcboot=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} ${rootfstype} rootwait ${console}; run loaduimage; bootm 0x40007FC0
+rootfstype=ext4
+loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage
+mmcdev=0
+mmcbootpart=2
+mmcrootpart=5
+console=console=ttySAC2,115200n8
+bootcmd=run mmcboot
+dfu_alt_info=u-boot mmc 80 800;params.bin mmc 0x38 0x8;uImage ext4 0 2
diff --git a/board/samsung/common/exynos-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds
new file mode 100644
index 0000000..4a933c8
--- /dev/null
+++ b/board/samsung/common/exynos-uboot-spl.lds
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Based on arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+ LENGTH = CONFIG_SPL_MAX_FOOTPRINT }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ *(.vectors)
+ arch/arm/cpu/armv7/start.o (.text*)
+ *(.text*)
+ } >.sram
+ . = ALIGN(4);
+
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+ . = ALIGN(4);
+
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+ . = ALIGN(4);
+
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ } >.sram
+ . = ALIGN(4);
+
+ /* Align .machine_param on 256 byte boundary for easier searching */
+ .machine_param ALIGN(0x100) : { *(.machine_param) } >.sram
+ . = ALIGN(4);
+
+ __image_copy_end = .;
+
+ .end :
+ {
+ *(.__end)
+ } >.sram
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } >.sram
+}
diff --git a/board/samsung/common/gadget.c b/board/samsung/common/gadget.c
new file mode 100644
index 0000000..6a1e57f
--- /dev/null
+++ b/board/samsung/common/gadget.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/usb/ch9.h>
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+ if (!strcmp(name, "usb_dnl_thor")) {
+ put_unaligned(CONFIG_G_DNL_THOR_VENDOR_NUM, &dev->idVendor);
+ put_unaligned(CONFIG_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct);
+ } else if (!strcmp(name, "usb_dnl_ums")) {
+ put_unaligned(CONFIG_G_DNL_UMS_VENDOR_NUM, &dev->idVendor);
+ put_unaligned(CONFIG_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct);
+ } else {
+ put_unaligned(CONFIG_G_DNL_VENDOR_NUM, &dev->idVendor);
+ put_unaligned(CONFIG_G_DNL_PRODUCT_NUM, &dev->idProduct);
+ }
+ return 0;
+}
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
new file mode 100644
index 0000000..4538ac7
--- /dev/null
+++ b/board/samsung/common/misc.c
@@ -0,0 +1,451 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <libtizen.h>
+#include <samsung/misc.h>
+#include <errno.h>
+#include <version.h>
+#include <malloc.h>
+#include <linux/sizes.h>
+#include <asm/arch/cpu.h>
+#include <asm/gpio.h>
+#include <linux/input.h>
+#include <power/pmic.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SET_DFU_ALT_INFO
+void set_dfu_alt_info(void)
+{
+ size_t buf_size = CONFIG_SET_DFU_ALT_BUF_LEN;
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, buf_size);
+ char *alt_info = "Settings not found!";
+ char *status = "error!\n";
+ char *alt_setting;
+ char *alt_sep;
+ int offset = 0;
+
+ puts("DFU alt info setting: ");
+
+ alt_setting = get_dfu_alt_boot();
+ if (alt_setting) {
+ setenv("dfu_alt_boot", alt_setting);
+ offset = snprintf(buf, buf_size, "%s", alt_setting);
+ }
+
+ alt_setting = get_dfu_alt_system();
+ if (alt_setting) {
+ if (offset)
+ alt_sep = ";";
+ else
+ alt_sep = "";
+
+ offset += snprintf(buf + offset, buf_size - offset,
+ "%s%s", alt_sep, alt_setting);
+ }
+
+ if (offset) {
+ alt_info = buf;
+ status = "done\n";
+ }
+
+ setenv("dfu_alt_info", alt_info);
+ puts(status);
+}
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+void set_board_info(void)
+{
+ char info[64];
+
+ snprintf(info, ARRAY_SIZE(info), "%u.%u", (s5p_cpu_rev & 0xf0) >> 4,
+ s5p_cpu_rev & 0xf);
+ setenv("soc_rev", info);
+
+ snprintf(info, ARRAY_SIZE(info), "%x", s5p_cpu_id);
+ setenv("soc_id", info);
+
+#ifdef CONFIG_REVISION_TAG
+ snprintf(info, ARRAY_SIZE(info), "%x", get_board_rev());
+ setenv("board_rev", info);
+#endif
+#ifdef CONFIG_OF_LIBFDT
+ const char *bdtype = "";
+ const char *bdname = CONFIG_SYS_BOARD;
+
+#ifdef CONFIG_BOARD_TYPES
+ bdtype = get_board_type();
+ sprintf(info, "%s%s", bdname, bdtype);
+ setenv("boardname", info);
+#endif
+ snprintf(info, ARRAY_SIZE(info), "%s%x-%s%s.dtb",
+ CONFIG_SYS_SOC, s5p_cpu_id, bdname, bdtype);
+ setenv("fdtfile", info);
+#endif
+}
+#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */
+
+#ifdef CONFIG_LCD_MENU
+static int power_key_pressed(u32 reg)
+{
+ struct pmic *pmic;
+ u32 status;
+ u32 mask;
+
+ pmic = pmic_get(KEY_PWR_PMIC_NAME);
+ if (!pmic) {
+ printf("%s: Not found\n", KEY_PWR_PMIC_NAME);
+ return 0;
+ }
+
+ if (pmic_probe(pmic))
+ return 0;
+
+ if (reg == KEY_PWR_STATUS_REG)
+ mask = KEY_PWR_STATUS_MASK;
+ else
+ mask = KEY_PWR_INTERRUPT_MASK;
+
+ if (pmic_reg_read(pmic, reg, &status))
+ return 0;
+
+ return !!(status & mask);
+}
+
+static int key_pressed(int key)
+{
+ int value;
+
+ switch (key) {
+ case KEY_POWER:
+ value = power_key_pressed(KEY_PWR_INTERRUPT_REG);
+ break;
+ case KEY_VOLUMEUP:
+ value = !gpio_get_value(KEY_VOL_UP_GPIO);
+ break;
+ case KEY_VOLUMEDOWN:
+ value = !gpio_get_value(KEY_VOL_DOWN_GPIO);
+ break;
+ default:
+ value = 0;
+ break;
+ }
+
+ return value;
+}
+
+static int check_keys(void)
+{
+ int keys = 0;
+
+ if (key_pressed(KEY_POWER))
+ keys += KEY_POWER;
+ if (key_pressed(KEY_VOLUMEUP))
+ keys += KEY_VOLUMEUP;
+ if (key_pressed(KEY_VOLUMEDOWN))
+ keys += KEY_VOLUMEDOWN;
+
+ return keys;
+}
+
+/*
+ * 0 BOOT_MODE_INFO
+ * 1 BOOT_MODE_THOR
+ * 2 BOOT_MODE_UMS
+ * 3 BOOT_MODE_DFU
+ * 4 BOOT_MODE_EXIT
+ */
+static char *
+mode_name[BOOT_MODE_EXIT + 1][2] = {
+ {"DEVICE", ""},
+ {"THOR", "thor"},
+ {"UMS", "ums"},
+ {"DFU", "dfu"},
+ {"GPT", "gpt"},
+ {"ENV", "env"},
+ {"EXIT", ""},
+};
+
+static char *
+mode_info[BOOT_MODE_EXIT + 1] = {
+ "info",
+ "downloader",
+ "mass storage",
+ "firmware update",
+ "restore",
+ "default",
+ "and run normal boot"
+};
+
+static char *
+mode_cmd[BOOT_MODE_EXIT + 1] = {
+ "",
+ "thor 0 mmc 0",
+ "ums 0 mmc 0",
+ "dfu 0 mmc 0",
+ "gpt write mmc 0 $partitions",
+ "env default -a; saveenv",
+ "",
+};
+
+static void display_board_info(void)
+{
+#ifdef CONFIG_GENERIC_MMC
+ struct mmc *mmc = find_mmc_device(0);
+#endif
+ vidinfo_t *vid = &panel_info;
+
+ lcd_position_cursor(4, 4);
+
+ lcd_printf("%s\n\t", U_BOOT_VERSION);
+ lcd_puts("\n\t\tBoard Info:\n");
+#ifdef CONFIG_SYS_BOARD
+ lcd_printf("\tBoard name: %s\n", CONFIG_SYS_BOARD);
+#endif
+#ifdef CONFIG_REVISION_TAG
+ lcd_printf("\tBoard rev: %u\n", get_board_rev());
+#endif
+ lcd_printf("\tDRAM banks: %u\n", CONFIG_NR_DRAM_BANKS);
+ lcd_printf("\tDRAM size: %u MB\n", gd->ram_size / SZ_1M);
+
+#ifdef CONFIG_GENERIC_MMC
+ if (mmc) {
+ if (!mmc->capacity)
+ mmc_init(mmc);
+
+ lcd_printf("\teMMC size: %llu MB\n", mmc->capacity / SZ_1M);
+ }
+#endif
+ if (vid)
+ lcd_printf("\tDisplay resolution: %u x % u\n",
+ vid->vl_col, vid->vl_row);
+
+ lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix);
+}
+
+static int mode_leave_menu(int mode)
+{
+ char *exit_option;
+ char *exit_reset = "reset";
+ char *exit_back = "back";
+ cmd_tbl_t *cmd;
+ int cmd_result;
+ int leave;
+
+ lcd_clear();
+
+ switch (mode) {
+ case BOOT_MODE_EXIT:
+ return 1;
+ case BOOT_MODE_INFO:
+ display_board_info();
+ exit_option = exit_back;
+ leave = 0;
+ break;
+ default:
+ cmd = find_cmd(mode_name[mode][1]);
+ if (cmd) {
+ printf("Enter: %s %s\n", mode_name[mode][0],
+ mode_info[mode]);
+ lcd_printf("\n\n\t%s %s\n", mode_name[mode][0],
+ mode_info[mode]);
+ lcd_puts("\n\tDo not turn off device before finish!\n");
+
+ cmd_result = run_command(mode_cmd[mode], 0);
+
+ if (cmd_result == CMD_RET_SUCCESS) {
+ printf("Command finished\n");
+ lcd_clear();
+ lcd_printf("\n\n\t%s finished\n",
+ mode_name[mode][0]);
+
+ exit_option = exit_reset;
+ leave = 1;
+ } else {
+ printf("Command error\n");
+ lcd_clear();
+ lcd_printf("\n\n\t%s command error\n",
+ mode_name[mode][0]);
+
+ exit_option = exit_back;
+ leave = 0;
+ }
+ } else {
+ lcd_puts("\n\n\tThis mode is not supported.\n");
+ exit_option = exit_back;
+ leave = 0;
+ }
+ }
+
+ lcd_printf("\n\n\tPress POWER KEY to %s\n", exit_option);
+
+ /* Clear PWR button Rising edge interrupt status flag */
+ power_key_pressed(KEY_PWR_INTERRUPT_REG);
+
+ /* Wait for PWR key */
+ while (!key_pressed(KEY_POWER))
+ mdelay(1);
+
+ lcd_clear();
+ return leave;
+}
+
+static void display_download_menu(int mode)
+{
+ char *selection[BOOT_MODE_EXIT + 1];
+ int i;
+
+ for (i = 0; i <= BOOT_MODE_EXIT; i++)
+ selection[i] = "[ ]";
+
+ selection[mode] = "[=>]";
+
+ lcd_clear();
+ lcd_printf("\n\n\t\tDownload Mode Menu\n\n");
+
+ for (i = 0; i <= BOOT_MODE_EXIT; i++)
+ lcd_printf("\t%s %s - %s\n\n", selection[i],
+ mode_name[i][0],
+ mode_info[i]);
+}
+
+static void download_menu(void)
+{
+ int mode = 0;
+ int last_mode = 0;
+ int run;
+ int key = 0;
+ int timeout = 15; /* sec */
+ int i;
+
+ display_download_menu(mode);
+
+ lcd_puts("\n");
+
+ /* Start count if no key is pressed */
+ while (check_keys())
+ continue;
+
+ while (timeout--) {
+ lcd_printf("\r\tNormal boot will start in: %2.d seconds.",
+ timeout);
+
+ /* about 1000 ms in for loop */
+ for (i = 0; i < 10; i++) {
+ mdelay(100);
+ key = check_keys();
+ if (key)
+ break;
+ }
+ if (key)
+ break;
+ }
+
+ if (!key) {
+ lcd_clear();
+ return;
+ }
+
+ while (1) {
+ run = 0;
+
+ if (mode != last_mode)
+ display_download_menu(mode);
+
+ last_mode = mode;
+ mdelay(200);
+
+ key = check_keys();
+ switch (key) {
+ case KEY_POWER:
+ run = 1;
+ break;
+ case KEY_VOLUMEUP:
+ if (mode > 0)
+ mode--;
+ break;
+ case KEY_VOLUMEDOWN:
+ if (mode < BOOT_MODE_EXIT)
+ mode++;
+ break;
+ default:
+ break;
+ }
+
+ if (run) {
+ if (mode_leave_menu(mode))
+ run_command("reset", 0);
+
+ display_download_menu(mode);
+ }
+ }
+
+ lcd_clear();
+}
+
+void check_boot_mode(void)
+{
+ int pwr_key;
+
+ pwr_key = power_key_pressed(KEY_PWR_STATUS_REG);
+ if (!pwr_key)
+ return;
+
+ /* Clear PWR button Rising edge interrupt status flag */
+ power_key_pressed(KEY_PWR_INTERRUPT_REG);
+
+ if (key_pressed(KEY_VOLUMEUP))
+ download_menu();
+ else if (key_pressed(KEY_VOLUMEDOWN))
+ mode_leave_menu(BOOT_MODE_THOR);
+}
+
+void keys_init(void)
+{
+ /* Set direction to input */
+ gpio_request(KEY_VOL_UP_GPIO, "volume-up");
+ gpio_request(KEY_VOL_DOWN_GPIO, "volume-down");
+ gpio_direction_input(KEY_VOL_UP_GPIO);
+ gpio_direction_input(KEY_VOL_DOWN_GPIO);
+}
+#endif /* CONFIG_LCD_MENU */
+
+#ifdef CONFIG_CMD_BMP
+void draw_logo(void)
+{
+ int x, y;
+ ulong addr;
+
+ addr = panel_info.logo_addr;
+ if (!addr) {
+ error("There is no logo data.");
+ return;
+ }
+
+ if (panel_info.vl_width >= panel_info.logo_width) {
+ x = ((panel_info.vl_width - panel_info.logo_width) >> 1);
+ x += panel_info.logo_x_offset; /* For X center align */
+ } else {
+ x = 0;
+ printf("Warning: image width is bigger than display width\n");
+ }
+
+ if (panel_info.vl_height >= panel_info.logo_height) {
+ y = ((panel_info.vl_height - panel_info.logo_height) >> 1);
+ y += panel_info.logo_y_offset; /* For Y center align */
+ } else {
+ y = 0;
+ printf("Warning: image height is bigger than display height\n");
+ }
+
+ bmp_display(addr, x, y);
+}
+#endif /* CONFIG_CMD_BMP */
diff --git a/board/samsung/common/multi_i2c.c b/board/samsung/common/multi_i2c.c
new file mode 100644
index 0000000..71c32c0
--- /dev/null
+++ b/board/samsung/common/multi_i2c.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#ifndef CONFIG_SOFT_I2C_I2C10_SCL
+#define CONFIG_SOFT_I2C_I2C10_SCL 0
+#endif
+
+#ifndef CONFIG_SOFT_I2C_I2C10_SDA
+#define CONFIG_SOFT_I2C_I2C10_SDA 0
+#endif
+
+/* Handle multiple I2C buses instances */
+int get_multi_scl_pin(void)
+{
+ unsigned int bus = i2c_get_bus_num();
+
+ switch (bus) {
+ case I2C_0:
+ return CONFIG_SOFT_I2C_I2C5_SCL;
+ case I2C_1:
+ return CONFIG_SOFT_I2C_I2C9_SCL;
+ case I2C_2:
+ return CONFIG_SOFT_I2C_I2C10_SCL;
+ default:
+ printf("I2C_%d not supported!\n", bus);
+ };
+
+ return 0;
+}
+
+int get_multi_sda_pin(void)
+{
+ unsigned int bus = i2c_get_bus_num();
+
+ switch (bus) {
+ case I2C_0:
+ return CONFIG_SOFT_I2C_I2C5_SDA;
+ case I2C_1:
+ return CONFIG_SOFT_I2C_I2C9_SDA;
+ case I2C_2:
+ return CONFIG_SOFT_I2C_I2C10_SDA;
+ default:
+ printf("I2C_%d not supported!\n", bus);
+ };
+
+ return 0;
+}
+
+int multi_i2c_init(void)
+{
+ return 0;
+}
diff --git a/board/samsung/goni/Kconfig b/board/samsung/goni/Kconfig
new file mode 100644
index 0000000..cbbf5a9
--- /dev/null
+++ b/board/samsung/goni/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_S5P_GONI
+
+config SYS_BOARD
+ default "goni"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_SOC
+ default "s5pc1xx"
+
+config SYS_CONFIG_NAME
+ default "s5p_goni"
+
+endif
diff --git a/board/samsung/goni/MAINTAINERS b/board/samsung/goni/MAINTAINERS
new file mode 100644
index 0000000..248ec3c
--- /dev/null
+++ b/board/samsung/goni/MAINTAINERS
@@ -0,0 +1,6 @@
+GONI BOARD
+M: Robert Baldyga <r.baldyga@samsung.com>
+S: Maintained
+F: board/samsung/goni/
+F: include/configs/s5p_goni.h
+F: configs/s5p_goni_defconfig
diff --git a/board/samsung/goni/Makefile b/board/samsung/goni/Makefile
new file mode 100644
index 0000000..2cdc21d
--- /dev/null
+++ b/board/samsung/goni/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := goni.o onenand.o
+obj-y += lowlevel_init.o
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
new file mode 100644
index 0000000..58cf96e
--- /dev/null
+++ b/board/samsung/goni/goni.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mmc.h>
+#include <power/pmic.h>
+#include <usb/s3c_udc.h>
+#include <asm/arch/cpu.h>
+#include <power/max8998_pmic.h>
+#include <samsung/misc.h>
+#include <usb.h>
+#include <usb_mass_storage.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_board_rev(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Set Initial global variables */
+ gd->bd->bi_arch_number = MACH_TYPE_GONI;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+void i2c_init_board(void)
+{
+ gpio_request(S5PC110_GPIO_J43, "i2c_clk");
+ gpio_request(S5PC110_GPIO_J40, "i2c_data");
+ gpio_direction_output(S5PC110_GPIO_J43, 1);
+ gpio_direction_output(S5PC110_GPIO_J40, 1);
+}
+#endif
+
+int power_init_board(void)
+{
+ int ret;
+
+ /*
+ * For PMIC the I2C bus is named as I2C5, but it is connected
+ * to logical I2C adapter 0
+ */
+ ret = pmic_init(I2C_0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
+ PHYS_SDRAM_3_SIZE;
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ puts("Board:\tGoni\n");
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret, ret_sd = 0;
+
+ /* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
+ gpio_request(S5PC110_GPIO_J27, "massmemory_en");
+ gpio_direction_output(S5PC110_GPIO_J27, 1);
+
+ /*
+ * MMC0 GPIO
+ * GPG0[0] SD_0_CLK
+ * GPG0[1] SD_0_CMD
+ * GPG0[2] SD_0_CDn -> Not used
+ * GPG0[3:6] SD_0_DATA[0:3]
+ */
+ for (i = S5PC110_GPIO_G00; i < S5PC110_GPIO_G07; i++) {
+ if (i == S5PC110_GPIO_G02)
+ continue;
+ /* GPG0[0:6] special function 2 */
+ gpio_cfg_pin(i, 0x2);
+ /* GPG0[0:6] pull disable */
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ /* GPG0[0:6] drv 4x */
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+
+ ret = s5p_mmc_init(0, 4);
+ if (ret)
+ error("MMC: Failed to init MMC:0.\n");
+
+ /*
+ * SD card (T_FLASH) detect and init
+ * T_FLASH_DETECT: EINT28: GPH3[4] input mode
+ */
+ gpio_request(S5PC110_GPIO_H34, "t_flash_detect");
+ gpio_cfg_pin(S5PC110_GPIO_H34, S5P_GPIO_INPUT);
+ gpio_set_pull(S5PC110_GPIO_H34, S5P_GPIO_PULL_UP);
+
+ if (!gpio_get_value(S5PC110_GPIO_H34)) {
+ for (i = S5PC110_GPIO_G20; i < S5PC110_GPIO_G27; i++) {
+ if (i == S5PC110_GPIO_G22)
+ continue;
+
+ /* GPG2[0:6] special function 2 */
+ gpio_cfg_pin(i, 0x2);
+ /* GPG2[0:6] pull disable */
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ /* GPG2[0:6] drv 4x */
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ }
+
+ ret_sd = s5p_mmc_init(2, 4);
+ if (ret_sd)
+ error("MMC: Failed to init SD card (MMC:2).\n");
+ }
+
+ return ret & ret_sd;
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET
+static int s5pc1xx_phy_control(int on)
+{
+ int ret;
+ static int status;
+ struct pmic *p = pmic_get("MAX8998_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return -1;
+
+ if (on && !status) {
+ ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
+ MAX8998_LDO3, LDO_ON);
+ ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
+ MAX8998_LDO8, LDO_ON);
+ if (ret) {
+ puts("MAX8998 LDO setting error!\n");
+ return -1;
+ }
+ status = 1;
+ } else if (!on && status) {
+ ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
+ MAX8998_LDO3, LDO_OFF);
+ ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
+ MAX8998_LDO8, LDO_OFF);
+ if (ret) {
+ puts("MAX8998 LDO setting error!\n");
+ return -1;
+ }
+ status = 0;
+ }
+ udelay(10000);
+
+ return 0;
+}
+
+struct s3c_plat_otg_data s5pc110_otg_data = {
+ .phy_control = s5pc1xx_phy_control,
+ .regs_phy = S5PC110_PHY_BASE,
+ .regs_otg = S5PC110_OTG_BASE,
+ .usb_phy_ctrl = S5PC110_USB_PHY_CONTROL,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ debug("USB_udc_probe\n");
+ return s3c_udc_probe(&s5pc110_otg_data);
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ set_board_info();
+#endif
+ return 0;
+}
+#endif
diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S
new file mode 100644
index 0000000..d52bc09
--- /dev/null
+++ b/board/samsung/goni/lowlevel_init.S
@@ -0,0 +1,446 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/power.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has S5PC100 GPIO base, 0xE0300000
+ * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
+ * r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
+ */
+
+ .globl lowlevel_init
+lowlevel_init:
+ mov r11, lr
+
+ /* r5 has always zero */
+ mov r5, #0
+
+ ldr r7, =S5PC100_GPIO_BASE
+ ldr r8, =S5PC100_GPIO_BASE
+ /* Read CPU ID */
+ ldr r2, =S5PC110_PRO_ID
+ ldr r0, [r2]
+ mov r1, #0x00010000
+ and r0, r0, r1
+ cmp r0, r5
+ beq 100f
+ ldr r8, =S5PC110_GPIO_BASE
+100:
+ /* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
+ cmp r7, r8
+ beq skip_check_didle @ Support C110 only
+
+ ldr r0, =S5PC110_RST_STAT
+ ldr r1, [r0]
+ and r1, r1, #0x000D0000
+ cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP
+ beq didle_wakeup
+ cmp r7, r8
+
+skip_check_didle:
+ addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
+ addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
+ ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
+ bic r1, r1, #(0xf << 4) @ 1 * 4-bit
+ orr r1, r1, #(0x1 << 4)
+ str r1, [r0, #0x0] @ GPIO_CON_OFFSET
+
+ ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
+ bic r1, r1, #(1 << 1)
+ str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
+
+ /* Don't setup at s5pc100 */
+ beq 100f
+
+ /*
+ * Initialize Async Register Setting for EVT1
+ * Because we are setting EVT1 as the default value of EVT0,
+ * setting EVT0 as well does not make things worse.
+ * Thus, for the simplicity, we set for EVT0, too
+ *
+ * The "Async Registers" are:
+ * 0xE0F0_0000
+ * 0xE1F0_0000
+ * 0xF180_0000
+ * 0xF190_0000
+ * 0xF1A0_0000
+ * 0xF1B0_0000
+ * 0xF1C0_0000
+ * 0xF1D0_0000
+ * 0xF1E0_0000
+ * 0xF1F0_0000
+ * 0xFAF0_0000
+ */
+ ldr r0, =0xe0f00000
+ ldr r1, [r0]
+ bic r1, r1, #0x1
+ str r1, [r0]
+
+ ldr r0, =0xe1f00000
+ ldr r1, [r0]
+ bic r1, r1, #0x1
+ str r1, [r0]
+
+ ldr r0, =0xf1800000
+ ldr r1, [r0]
+ bic r1, r1, #0x1
+ str r1, [r0]
+
+ ldr r0, =0xf1900000
+ ldr r1, [r0]
+ bic r1, r1, #0x1
+ str r1, [r0]
+
+ ldr r0, =0xf1a00000
+ ldr r1, [r0]
+ bic r1, r1, #0x1
+ str r1, [r0]
+
+ ldr r0, =0xf1b00000
+ ldr r1, [r0]
+ bic r1, r1, #0x1
+ str r1, [r0]
+
+ ldr r0, =0xf1c00000
+ ldr r1, [r0]
+ bic r1, r1, #0x1
+ str r1, [r0]
+
+ ldr r0, =0xf1d00000
+ ldr r1, [r0]
+ bic r1, r1, #0x1
+ str r1, [r0]
+
+ ldr r0, =0xf1e00000
+ ldr r1, [r0]
+ bic r1, r1, #0x1
+ str r1, [r0]
+
+ ldr r0, =0xf1f00000
+ ldr r1, [r0]
+ bic r1, r1, #0x1
+ str r1, [r0]
+
+ ldr r0, =0xfaf00000
+ ldr r1, [r0]
+ bic r1, r1, #0x1
+ str r1, [r0]
+
+ /*
+ * Diable ABB block to reduce sleep current at low temperature
+ * Note that it's hidden register setup don't modify it
+ */
+ ldr r0, =0xE010C300
+ ldr r1, =0x00800000
+ str r1, [r0]
+
+100:
+ /* IO retension release */
+ ldreq r0, =S5PC100_OTHERS @ 0xE0108200
+ ldrne r0, =S5PC110_OTHERS @ 0xE010E000
+ ldr r1, [r0]
+ ldreq r2, =(1 << 31) @ IO_RET_REL
+ ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
+ orr r1, r1, r2
+ /* Do not release retention here for S5PC110 */
+ streq r1, [r0]
+
+ /* Disable Watchdog */
+ ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
+ ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
+ str r5, [r0]
+
+ /* setting SRAM */
+ ldreq r0, =S5PC100_SROMC_BASE
+ ldrne r0, =S5PC110_SROMC_BASE
+ ldr r1, =0x9
+ str r1, [r0]
+
+ /* S5PC100 has 3 groups of interrupt sources */
+ ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
+ ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000
+ add r1, r0, #0x00100000
+ add r2, r0, #0x00200000
+
+ /* Disable all interrupts (VIC0, VIC1 and VIC2) */
+ mvn r3, #0x0
+ str r3, [r0, #0x14] @ INTENCLEAR
+ str r3, [r1, #0x14] @ INTENCLEAR
+ str r3, [r2, #0x14] @ INTENCLEAR
+
+ /* Set all interrupts as IRQ */
+ str r5, [r0, #0xc] @ INTSELECT
+ str r5, [r1, #0xc] @ INTSELECT
+ str r5, [r2, #0xc] @ INTSELECT
+
+ /* Pending Interrupt Clear */
+ str r5, [r0, #0xf00] @ INTADDRESS
+ str r5, [r1, #0xf00] @ INTADDRESS
+ str r5, [r2, #0xf00] @ INTADDRESS
+
+ /* for UART */
+ bl uart_asm_init
+
+ bl internal_ram_init
+
+ cmp r7, r8
+ /* Clear wakeup status register */
+ ldreq r0, =S5PC100_WAKEUP_STAT
+ ldrne r0, =S5PC110_WAKEUP_STAT
+ ldr r1, [r0]
+ str r1, [r0]
+
+ /* IO retension release */
+ ldreq r0, =S5PC100_OTHERS @ 0xE0108200
+ ldrne r0, =S5PC110_OTHERS @ 0xE010E000
+ ldr r1, [r0]
+ ldreq r2, =(1 << 31) @ IO_RET_REL
+ ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
+ orr r1, r1, r2
+ str r1, [r0]
+
+ b 1f
+
+didle_wakeup:
+ /* Wait when APLL is locked */
+ ldr r0, =0xE0100100 @ S5PC110_APLL_CON
+lockloop:
+ ldr r1, [r0]
+ and r1, r1, #(1 << 29)
+ cmp r1, #(1 << 29)
+ bne lockloop
+
+ ldr r0, =S5PC110_INFORM0
+ ldr r1, [r0]
+ mov pc, r1
+ nop
+ nop
+ nop
+ nop
+ nop
+
+1:
+ mov lr, r11
+ mov pc, lr
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+ ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
+
+ /* Check S5PC100 */
+ cmp r7, r8
+ bne 110f
+100:
+ /* Set Lock Time */
+ ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
+ str r1, [r0, #0x000] @ S5PC100_APLL_LOCK
+ str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK
+ str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK
+ str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK
+
+ /* S5P_APLL_CON */
+ ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
+ str r1, [r0, #0x100]
+ /* S5P_MPLL_CON */
+ ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
+ str r1, [r0, #0x104]
+ /* S5P_EPLL_CON */
+ ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
+ str r1, [r0, #0x108]
+ /* S5P_HPLL_CON */
+ ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
+ str r1, [r0, #0x10C]
+
+ ldr r1, [r0, #0x300]
+ ldr r2, =0x00003fff
+ bic r1, r1, r2
+ ldr r2, =0x00011301
+
+ orr r1, r1, r2
+ str r1, [r0, #0x300]
+ ldr r1, [r0, #0x304]
+ ldr r2, =0x00011110
+ orr r1, r1, r2
+ str r1, [r0, #0x304]
+ ldr r1, =0x00000001
+ str r1, [r0, #0x308]
+
+ /* Set Source Clock */
+ ldr r1, =0x00001111 @ A, M, E, HPLL Muxing
+ str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
+
+ b 200f
+110:
+ ldr r0, =0xE010C000 @ S5PC110_PWR_CFG
+
+ /* Set OSC_FREQ value */
+ ldr r1, =0xf
+ str r1, [r0, #0x100] @ S5PC110_OSC_FREQ
+
+ /* Set MTC_STABLE value */
+ ldr r1, =0xffffffff
+ str r1, [r0, #0x110] @ S5PC110_MTC_STABLE
+
+ /* Set CLAMP_STABLE value */
+ ldr r1, =0x3ff03ff
+ str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE
+
+ ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
+
+ /* Set Clock divider */
+ ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5
+ str r1, [r0, #0x300]
+ ldr r1, =0x11110111 @ UART[3210]: MMC[3210]
+ str r1, [r0, #0x310]
+
+ /* Set Lock Time */
+ ldr r1, =0x2cf @ Locktime : 30us
+ str r1, [r0, #0x000] @ S5PC110_APLL_LOCK
+ ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
+ str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK
+ str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK
+ str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK
+
+ /* S5PC110_APLL_CON */
+ ldr r1, =0x80C80601 @ 800MHz
+ str r1, [r0, #0x100]
+ /* S5PC110_MPLL_CON */
+ ldr r1, =0x829B0C01 @ 667MHz
+ str r1, [r0, #0x108]
+ /* S5PC110_EPLL_CON */
+ ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
+ str r1, [r0, #0x110]
+ /* S5PC110_VPLL_CON */
+ ldr r1, =0x806C0603 @ 54MHz
+ str r1, [r0, #0x120]
+
+ /* Set Source Clock */
+ ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
+ str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
+
+ /* OneDRAM(DMC0) clock setting */
+ ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL
+ str r1, [r0, #0x218] @ S5PC110_CLK_SRC6
+ ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1
+ str r1, [r0, #0x318] @ S5PC110_CLK_DIV6
+
+ /* XCLKOUT = XUSBXTI 24MHz */
+ add r2, r0, #0xE000 @ S5PC110_OTHERS
+ ldr r1, [r2]
+ orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI
+ str r1, [r2]
+
+ /* CLK_IP0 */
+ ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5]
+ str r1, [r0, #0x460] @ S5PC110_CLK_IP0
+
+ /* CLK_IP1 */
+ ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16]
+ @ NANDXL[24]
+ str r1, [r0, #0x464] @ S5PC110_CLK_IP1
+
+ /* CLK_IP2 */
+ ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9]
+ @ HOSTIF[10] HSMMC0[16]
+ @ HSMMC2[18] VIC[27:24]
+ str r1, [r0, #0x468] @ S5PC110_CLK_IP2
+
+ /* CLK_IP3 */
+ ldr r1, =0x8eff038c @ I2C[8:6]
+ @ SYSTIMER[16] UART0[17]
+ @ UART1[18] UART2[19]
+ @ UART3[20] WDT[22]
+ @ PWM[23] GPIO[26] SYSCON[27]
+ str r1, [r0, #0x46c] @ S5PC110_CLK_IP3
+
+ /* CLK_IP4 */
+ ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5]
+ str r1, [r0, #0x470] @ S5PC110_CLK_IP3
+
+200:
+ /* wait at least 200us to stablize all clock */
+ mov r2, #0x10000
+1: subs r2, r2, #1
+ bne 1b
+
+ mov pc, lr
+
+internal_ram_init:
+ ldreq r0, =0xE3800000
+ ldrne r0, =0xF1500000
+ ldr r1, =0x0
+ str r1, [r0]
+
+ mov pc, lr
+
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+ /* set GPIO to enable UART0-UART4 */
+ mov r0, r8
+ ldr r1, =0x22222222
+ str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET
+ ldr r1, =0x00002222
+ str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET
+
+ /* Check S5PC100 */
+ cmp r7, r8
+ bne 110f
+
+ /* UART_SEL GPK0[5] at S5PC100 */
+ add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET
+ ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
+ bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit
+ orr r1, r1, #(0x1 << 20) @ Output
+ str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
+
+ ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
+ bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit
+ orr r1, r1, #(0x2 << 10) @ Pull-up enabled
+ str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
+
+ ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
+ orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit
+ str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
+
+ b 200f
+110:
+ /*
+ * Note that the following address
+ * 0xE020'0360 is reserved address at S5PC100
+ */
+ /* UART_SEL MP0_5[7] at S5PC110 */
+ add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET
+ ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
+ bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
+ orr r1, r1, #(0x1 << 28) @ Output
+ str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
+
+ ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
+ bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
+ orr r1, r1, #(0x2 << 14) @ Pull-up enabled
+ str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
+
+ ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
+ orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
+ str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
+200:
+ mov pc, lr
diff --git a/board/samsung/goni/onenand.c b/board/samsung/goni/onenand.c
new file mode 100644
index 0000000..b74d8e8
--- /dev/null
+++ b/board/samsung/goni/onenand.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+#include <onenand_uboot.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+
+ this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+ this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
+ this->chip_probe = s5pc110_chip_probe;
+}
diff --git a/board/samsung/odroid/Kconfig b/board/samsung/odroid/Kconfig
new file mode 100644
index 0000000..8b52a0d
--- /dev/null
+++ b/board/samsung/odroid/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ODROID
+
+config SYS_BOARD
+ default "odroid"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "odroid"
+
+endif
diff --git a/board/samsung/odroid/MAINTAINERS b/board/samsung/odroid/MAINTAINERS
new file mode 100644
index 0000000..2131d36
--- /dev/null
+++ b/board/samsung/odroid/MAINTAINERS
@@ -0,0 +1,6 @@
+ODROID BOARD
+M: Przemyslaw Marczak <p.marczak@samsung.com>
+S: Maintained
+F: board/samsung/odroid/
+F: include/configs/odroid.h
+F: configs/odroid_defconfig
diff --git a/board/samsung/odroid/Makefile b/board/samsung/odroid/Makefile
new file mode 100644
index 0000000..b98aaeb
--- /dev/null
+++ b/board/samsung/odroid/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved.
+# Przemyslaw Marczak <p.marczak@samsung.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := odroid.o
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
new file mode 100644
index 0000000..b7d2381
--- /dev/null
+++ b/board/samsung/odroid/odroid.c
@@ -0,0 +1,525 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <asm/arch/cpu.h>
+#include <power/pmic.h>
+#include <power/max77686_pmic.h>
+#include <errno.h>
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <samsung/misc.h>
+#include "setup.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_BOARD_TYPES
+/* Odroid board types */
+enum {
+ ODROID_TYPE_U3,
+ ODROID_TYPE_X2,
+ ODROID_TYPES,
+};
+
+void set_board_type(void)
+{
+ /* Set GPA1 pin 1 to HI - enable XCL205 output */
+ writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON);
+ writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4);
+ writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8);
+ writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc);
+
+ /* Set GPC1 pin 2 to IN - check XCL205 output state */
+ writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON);
+ writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8);
+
+ /* XCL205 - needs some latch time */
+ sdelay(200000);
+
+ /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
+ if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN))
+ gd->board_type = ODROID_TYPE_X2;
+ else
+ gd->board_type = ODROID_TYPE_U3;
+}
+
+const char *get_board_type(void)
+{
+ const char *board_type[] = {"u3", "x2"};
+
+ return board_type[gd->board_type];
+}
+#endif
+
+#ifdef CONFIG_SET_DFU_ALT_INFO
+char *get_dfu_alt_system(void)
+{
+ return getenv("dfu_alt_system");
+}
+
+char *get_dfu_alt_boot(void)
+{
+ char *alt_boot;
+
+ switch (get_boot_mode()) {
+ case BOOT_MODE_SD:
+ alt_boot = CONFIG_DFU_ALT_BOOT_SD;
+ break;
+ case BOOT_MODE_EMMC:
+ case BOOT_MODE_EMMC_SD:
+ alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
+ break;
+ default:
+ alt_boot = NULL;
+ break;
+ }
+ return alt_boot;
+}
+#endif
+
+static void board_clock_init(void)
+{
+ unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
+ struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
+ samsung_get_base_clock();
+
+ /*
+ * CMU_CPU clocks src to MPLL
+ * Bit values: 0 ; 1
+ * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
+ * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
+ * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
+ * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
+ */
+ clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
+ MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
+ set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
+ MUX_MPLL_USER_SEL_C(1);
+
+ clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
+
+ /* Wait for mux change */
+ while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
+ continue;
+
+ /* Set APLL to 1000MHz */
+ clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
+ set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
+
+ clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
+
+ /* Wait for PLL to be locked */
+ while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
+ continue;
+
+ /* Set CMU_CPU clocks src to APLL */
+ set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
+ MUX_MPLL_USER_SEL_C(1);
+ clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
+
+ /* Wait for mux change */
+ while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
+ continue;
+
+ set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
+ PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
+ APLL_RATIO(0) | CORE2_RATIO(0);
+ /*
+ * Set dividers for MOUTcore = 1000 MHz
+ * coreout = MOUT / (ratio + 1) = 1000 MHz (0)
+ * corem0 = armclk / (ratio + 1) = 333 MHz (2)
+ * corem1 = armclk / (ratio + 1) = 166 MHz (5)
+ * periph = armclk / (ratio + 1) = 1000 MHz (0)
+ * atbout = MOUT / (ratio + 1) = 200 MHz (4)
+ * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
+ * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
+ * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
+ */
+ clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
+ PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
+ APLL_RATIO(7) | CORE2_RATIO(7);
+
+ clrsetbits_le32(&clk->div_cpu0, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
+ continue;
+
+ /*
+ * For MOUThpm = 1000 MHz (MOUTapll)
+ * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
+ * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
+ * cores_out = armclk / (ratio + 1) = 200 (4)
+ */
+ clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
+ set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
+
+ clrsetbits_le32(&clk->div_cpu1, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
+ continue;
+
+ /*
+ * Set CMU_DMC clocks src to APLL
+ * Bit values: 0 ; 1
+ * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
+ * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
+ * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
+ * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
+ * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
+ * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
+ * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
+ * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
+ */
+ clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
+ MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
+ MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
+ MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
+ set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
+ MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
+ MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
+
+ clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
+
+ /* Wait for mux change */
+ while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
+ continue;
+
+ /* Set MPLL to 800MHz */
+ set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
+
+ clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
+
+ /* Wait for PLL to be locked */
+ while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
+ continue;
+
+ /* Switch back CMU_DMC mux */
+ set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
+ MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
+ MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
+
+ clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
+
+ /* Wait for mux change */
+ while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
+ continue;
+
+ /* CLK_DIV_DMC0 */
+ clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
+ DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
+ /*
+ * For:
+ * MOUTdmc = 800 MHz
+ * MOUTdphy = 800 MHz
+ *
+ * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
+ * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
+ * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
+ * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
+ * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
+ * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
+ */
+ set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
+ DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
+
+ clrsetbits_le32(&clk->div_dmc0, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
+ continue;
+
+ /* CLK_DIV_DMC1 */
+ clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
+ C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
+ /*
+ * For:
+ * MOUTg2d = 800 MHz
+ * MOUTc2c = 800 Mhz
+ * MOUTpwi = 108 MHz
+ *
+ * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1)
+ * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
+ * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
+ * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
+ */
+ set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) |
+ C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
+
+ clrsetbits_le32(&clk->div_dmc1, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
+ continue;
+
+ /* CLK_SRC_PERIL0 */
+ clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
+ UART3_SEL(15) | UART4_SEL(15);
+ /*
+ * Set CLK_SRC_PERIL0 clocks src to MPLL
+ * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
+ * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
+ * 8(SCLK_VPLL)
+ *
+ * Set all to SCLK_MPLL_USER_T
+ */
+ set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
+ UART4_SEL(6);
+
+ clrsetbits_le32(&clk->src_peril0, clr, set);
+
+ /* CLK_DIV_PERIL0 */
+ clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
+ UART3_RATIO(15) | UART4_RATIO(15);
+ /*
+ * For MOUTuart0-4: 800MHz
+ *
+ * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
+ */
+ set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
+ UART3_RATIO(7) | UART4_RATIO(7);
+
+ clrsetbits_le32(&clk->div_peril0, clr, set);
+
+ while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
+ continue;
+
+ /* CLK_DIV_FSYS1 */
+ clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
+ MMC1_PRE_RATIO(255);
+ /*
+ * For MOUTmmc0-3 = 800 MHz (MPLL)
+ *
+ * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
+ * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
+ * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
+ * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
+ */
+ set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
+ MMC1_PRE_RATIO(1);
+
+ clrsetbits_le32(&clk->div_fsys1, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
+ continue;
+
+ /* CLK_DIV_FSYS2 */
+ clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
+ MMC3_PRE_RATIO(255);
+ /*
+ * For MOUTmmc0-3 = 800 MHz (MPLL)
+ *
+ * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
+ * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
+ * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
+ * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
+ */
+ set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
+ MMC3_PRE_RATIO(1);
+
+ clrsetbits_le32(&clk->div_fsys2, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
+ continue;
+
+ /* CLK_DIV_FSYS3 */
+ clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
+ /*
+ * For MOUTmmc4 = 800 MHz (MPLL)
+ *
+ * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
+ * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
+ */
+ set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
+
+ clrsetbits_le32(&clk->div_fsys3, clr, set);
+
+ /* Wait for divider ready status */
+ while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
+ continue;
+
+ return;
+}
+
+static void board_gpio_init(void)
+{
+ /* eMMC Reset Pin */
+ gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
+
+ gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
+ gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
+
+ /* Enable FAN (Odroid U3) */
+ gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
+
+ gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
+ gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
+ gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
+
+ /* OTG Vbus output (Odroid U3+) */
+ gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
+
+ gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
+ gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
+ gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
+
+ /* OTG INT (Odroid U3+) */
+ gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
+
+ gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
+ gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
+ gpio_direction_input(EXYNOS4X12_GPIO_X31);
+
+ /* Blue LED (Odroid X2/U2/U3) */
+ gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
+
+ gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
+
+#ifdef CONFIG_CMD_USB
+ /* USB3503A Reference frequency */
+ gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
+
+ /* USB3503A Connect */
+ gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
+
+ /* USB3503A Reset */
+ gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
+#endif
+}
+
+static int pmic_init_max77686(void)
+{
+ struct pmic *p = pmic_get("MAX77686_PMIC");
+
+ if (pmic_probe(p))
+ return -ENODEV;
+
+ /* Set LDO Voltage */
+ max77686_set_ldo_voltage(p, 20, 1800000); /* LDO20 eMMC */
+ max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 SD */
+ max77686_set_ldo_voltage(p, 22, 2800000); /* LDO22 eMMC */
+
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+static void board_init_i2c(void)
+{
+ /* I2C_0 */
+ if (exynos_pinmux_config(PERIPH_ID_I2C0, PINMUX_FLAG_NONE))
+ debug("I2C%d not configured\n", (I2C_0));
+}
+#endif
+
+int exynos_early_init_f(void)
+{
+ board_clock_init();
+
+ return 0;
+}
+
+int exynos_init(void)
+{
+ /* The last MB of memory is reserved for secure firmware */
+ gd->ram_size -= SZ_1M;
+ gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
+
+ board_gpio_init();
+
+ return 0;
+}
+
+int exynos_power_init(void)
+{
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+ board_init_i2c();
+#endif
+ pmic_init(I2C_0);
+ pmic_init_max77686();
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_GADGET
+static int s5pc210_phy_control(int on)
+{
+ struct pmic *p_pmic;
+
+ p_pmic = pmic_get("MAX77686_PMIC");
+ if (!p_pmic)
+ return -ENODEV;
+
+ if (pmic_probe(p_pmic))
+ return -1;
+
+ if (on)
+ return max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON);
+ else
+ return max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM);
+}
+
+struct s3c_plat_otg_data s5pc210_otg_data = {
+ .phy_control = s5pc210_phy_control,
+ .regs_phy = EXYNOS4X12_USBPHY_BASE,
+ .regs_otg = EXYNOS4X12_USBOTG_BASE,
+ .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
+ .usb_flags = PHY0_SLEEP,
+};
+#endif
+
+#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+#ifdef CONFIG_CMD_USB
+ struct pmic *p_pmic;
+
+ /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
+ /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
+ if (gd->board_type == ODROID_TYPE_U3)
+ gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
+ else
+ gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
+
+ /* Disconnect, Reset, Connect */
+ gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
+ gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
+ gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
+ gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
+
+ /* Power off and on BUCK8 for LAN9730 */
+ debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
+
+ p_pmic = pmic_get("MAX77686_PMIC");
+ if (p_pmic && !pmic_probe(p_pmic)) {
+ max77686_set_buck_voltage(p_pmic, 8, 750000);
+ max77686_set_buck_voltage(p_pmic, 8, 3300000);
+ }
+
+#endif
+
+ debug("USB_udc_probe\n");
+ return s3c_udc_probe(&s5pc210_otg_data);
+}
+#endif
+
+void reset_misc(void)
+{
+ /* Reset eMMC*/
+ gpio_set_value(EXYNOS4X12_GPIO_K12, 0);
+ mdelay(10);
+ gpio_set_value(EXYNOS4X12_GPIO_K12, 1);
+}
diff --git a/board/samsung/odroid/setup.h b/board/samsung/odroid/setup.h
new file mode 100644
index 0000000..3e48dad
--- /dev/null
+++ b/board/samsung/odroid/setup.h
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ODROIDU3_SETUP__
+#define __ODROIDU3_SETUP__
+
+/* A/M PLL_CON0 */
+#define SDIV(x) ((x) & 0x7)
+#define PDIV(x) (((x) & 0x3f) << 8)
+#define MDIV(x) (((x) & 0x3ff) << 16)
+#define FSEL(x) (((x) & 0x1) << 27)
+#define PLL_LOCKED_BIT (0x1 << 29)
+#define PLL_ENABLE(x) (((x) & 0x1) << 31)
+
+/* CLK_SRC_CPU */
+#define MUX_APLL_SEL(x) ((x) & 0x1)
+#define MUX_CORE_SEL(x) (((x) & 0x1) << 16)
+#define MUX_HPM_SEL(x) (((x) & 0x1) << 20)
+#define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24)
+
+#define MUX_STAT_CHANGING 0x100
+
+/* CLK_MUX_STAT_CPU */
+#define APLL_SEL(x) ((x) & 0x7)
+#define CORE_SEL(x) (((x) & 0x7) << 16)
+#define HPM_SEL(x) (((x) & 0x7) << 20)
+#define MPLL_USER_SEL_C(x) (((x) & 0x7) << 24)
+#define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) | \
+ CORE_SEL(MUX_STAT_CHANGING) | \
+ HPM_SEL(MUX_STAT_CHANGING) | \
+ MPLL_USER_SEL_C(MUX_STAT_CHANGING))
+
+/* CLK_DIV_CPU0 */
+#define CORE_RATIO(x) ((x) & 0x7)
+#define COREM0_RATIO(x) (((x) & 0x7) << 4)
+#define COREM1_RATIO(x) (((x) & 0x7) << 8)
+#define PERIPH_RATIO(x) (((x) & 0x7) << 12)
+#define ATB_RATIO(x) (((x) & 0x7) << 16)
+#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20)
+#define APLL_RATIO(x) (((x) & 0x7) << 24)
+#define CORE2_RATIO(x) (((x) & 0x7) << 28)
+
+/* CLK_DIV_STAT_CPU0 */
+#define DIV_CORE(x) ((x) & 0x1)
+#define DIV_COREM0(x) (((x) & 0x1) << 4)
+#define DIV_COREM1(x) (((x) & 0x1) << 8)
+#define DIV_PERIPH(x) (((x) & 0x1) << 12)
+#define DIV_ATB(x) (((x) & 0x1) << 16)
+#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20)
+#define DIV_APLL(x) (((x) & 0x1) << 24)
+#define DIV_CORE2(x) (((x) & 0x1) << 28)
+
+#define DIV_STAT_CHANGING 0x1
+#define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \
+ DIV_COREM0(DIV_STAT_CHANGING) | \
+ DIV_COREM1(DIV_STAT_CHANGING) | \
+ DIV_PERIPH(DIV_STAT_CHANGING) | \
+ DIV_ATB(DIV_STAT_CHANGING) | \
+ DIV_PCLK_DBG(DIV_STAT_CHANGING) | \
+ DIV_APLL(DIV_STAT_CHANGING) | \
+ DIV_CORE2(DIV_STAT_CHANGING))
+
+/* CLK_DIV_CPU1 */
+#define COPY_RATIO(x) ((x) & 0x7)
+#define HPM_RATIO(x) (((x) & 0x7) << 4)
+#define CORES_RATIO(x) (((x) & 0x7) << 8)
+
+/* CLK_DIV_STAT_CPU1 */
+#define DIV_COPY(x) ((x) & 0x7)
+#define DIV_HPM(x) (((x) & 0x1) << 4)
+#define DIV_CORES(x) (((x) & 0x1) << 8)
+
+#define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \
+ DIV_HPM(DIV_STAT_CHANGING) | \
+ DIV_CORES(DIV_STAT_CHANGING))
+
+/* CLK_SRC_DMC */
+#define MUX_C2C_SEL(x) ((x) & 0x1)
+#define MUX_DMC_BUS_SEL(x) (((x) & 0x1) << 4)
+#define MUX_DPHY_SEL(x) (((x) & 0x1) << 8)
+#define MUX_MPLL_SEL(x) (((x) & 0x1) << 12)
+#define MUX_PWI_SEL(x) (((x) & 0xf) << 16)
+#define MUX_G2D_ACP0_SEL(x) (((x) & 0x1) << 20)
+#define MUX_G2D_ACP1_SEL(x) (((x) & 0x1) << 24)
+#define MUX_G2D_ACP_SEL(x) (((x) & 0x1) << 28)
+
+/* CLK_MUX_STAT_DMC */
+#define C2C_SEL(x) (((x)) & 0x7)
+#define DMC_BUS_SEL(x) (((x) & 0x7) << 4)
+#define DPHY_SEL(x) (((x) & 0x7) << 8)
+#define MPLL_SEL(x) (((x) & 0x7) << 12)
+/* #define PWI_SEL(x) (((x) & 0xf) << 16) - Reserved */
+#define G2D_ACP0_SEL(x) (((x) & 0x7) << 20)
+#define G2D_ACP1_SEL(x) (((x) & 0x7) << 24)
+#define G2D_ACP_SEL(x) (((x) & 0x7) << 28)
+
+#define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) | \
+ DMC_BUS_SEL(MUX_STAT_CHANGING) | \
+ DPHY_SEL(MUX_STAT_CHANGING) | \
+ MPLL_SEL(MUX_STAT_CHANGING) |\
+ G2D_ACP0_SEL(MUX_STAT_CHANGING) | \
+ G2D_ACP1_SEL(MUX_STAT_CHANGING) | \
+ G2D_ACP_SEL(MUX_STAT_CHANGING))
+
+/* CLK_DIV_DMC0 */
+#define ACP_RATIO(x) ((x) & 0x7)
+#define ACP_PCLK_RATIO(x) (((x) & 0x7) << 4)
+#define DPHY_RATIO(x) (((x) & 0x7) << 8)
+#define DMC_RATIO(x) (((x) & 0x7) << 12)
+#define DMCD_RATIO(x) (((x) & 0x7) << 16)
+#define DMCP_RATIO(x) (((x) & 0x7) << 20)
+
+/* CLK_DIV_STAT_DMC0 */
+#define DIV_ACP(x) ((x) & 0x1)
+#define DIV_ACP_PCLK(x) (((x) & 0x1) << 4)
+#define DIV_DPHY(x) (((x) & 0x1) << 8)
+#define DIV_DMC(x) (((x) & 0x1) << 12)
+#define DIV_DMCD(x) (((x) & 0x1) << 16)
+#define DIV_DMCP(x) (((x) & 0x1) << 20)
+
+#define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \
+ DIV_ACP_PCLK(DIV_STAT_CHANGING) | \
+ DIV_DPHY(DIV_STAT_CHANGING) | \
+ DIV_DMC(DIV_STAT_CHANGING) | \
+ DIV_DMCD(DIV_STAT_CHANGING) | \
+ DIV_DMCP(DIV_STAT_CHANGING))
+
+/* CLK_DIV_DMC1 */
+#define G2D_ACP_RATIO(x) ((x) & 0xf)
+#define C2C_RATIO(x) (((x) & 0x7) << 4)
+#define PWI_RATIO(x) (((x) & 0xf) << 8)
+#define C2C_ACLK_RATIO(x) (((x) & 0x7) << 12)
+#define DVSEM_RATIO(x) (((x) & 0x7f) << 16)
+#define DPM_RATIO(x) (((x) & 0x7f) << 24)
+
+/* CLK_DIV_STAT_DMC1 */
+#define DIV_G2D_ACP(x) ((x) & 0x1)
+#define DIV_C2C(x) (((x) & 0x1) << 4)
+#define DIV_PWI(x) (((x) & 0x1) << 8)
+#define DIV_C2C_ACLK(x) (((x) & 0x1) << 12)
+#define DIV_DVSEM(x) (((x) & 0x1) << 16)
+#define DIV_DPM(x) (((x) & 0x1) << 24)
+
+#define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \
+ DIV_C2C(DIV_STAT_CHANGING) | \
+ DIV_PWI(DIV_STAT_CHANGING) | \
+ DIV_C2C_ACLK(DIV_STAT_CHANGING) | \
+ DIV_DVSEM(DIV_STAT_CHANGING) | \
+ DIV_DPM(DIV_STAT_CHANGING))
+
+/* Set CLK_SRC_PERIL0 */
+#define UART4_SEL(x) (((x) & 0xf) << 16)
+#define UART3_SEL(x) (((x) & 0xf) << 12)
+#define UART2_SEL(x) (((x) & 0xf) << 8)
+#define UART1_SEL(x) (((x) & 0xf) << 4)
+#define UART0_SEL(x) ((x) & 0xf)
+
+/* Set CLK_DIV_PERIL0 */
+#define UART4_RATIO(x) (((x) & 0xf) << 16)
+#define UART3_RATIO(x) (((x) & 0xf) << 12)
+#define UART2_RATIO(x) (((x) & 0xf) << 8)
+#define UART1_RATIO(x) (((x) & 0xf) << 4)
+#define UART0_RATIO(x) ((x) & 0xf)
+
+/* Set CLK_DIV_STAT_PERIL0 */
+#define DIV_UART4(x) (((x) & 0x1) << 16)
+#define DIV_UART3(x) (((x) & 0x1) << 12)
+#define DIV_UART2(x) (((x) & 0x1) << 8)
+#define DIV_UART1(x) (((x) & 0x1) << 4)
+#define DIV_UART0(x) ((x) & 0x1)
+
+#define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
+ DIV_UART3(DIV_STAT_CHANGING) | \
+ DIV_UART2(DIV_STAT_CHANGING) | \
+ DIV_UART1(DIV_STAT_CHANGING) | \
+ DIV_UART0(DIV_STAT_CHANGING))
+
+/* CLK_DIV_FSYS1 */
+#define MMC0_RATIO(x) ((x) & 0xf)
+#define MMC0_PRE_RATIO(x) (((x) & 0xff) << 8)
+#define MMC1_RATIO(x) (((x) & 0xf) << 16)
+#define MMC1_PRE_RATIO(x) (((x) & 0xff) << 24)
+
+/* CLK_DIV_STAT_FSYS1 */
+#define DIV_MMC0(x) ((x) & 1)
+#define DIV_MMC0_PRE(x) (((x) & 1) << 8)
+#define DIV_MMC1(x) (((x) & 1) << 16)
+#define DIV_MMC1_PRE(x) (((x) & 1) << 24)
+
+#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
+ DIV_MMC0_PRE(DIV_STAT_CHANGING) | \
+ DIV_MMC1(DIV_STAT_CHANGING) | \
+ DIV_MMC1_PRE(DIV_STAT_CHANGING))
+
+/* CLK_DIV_FSYS2 */
+#define MMC2_RATIO(x) ((x) & 0xf)
+#define MMC2_PRE_RATIO(x) (((x) & 0xff) << 8)
+#define MMC3_RATIO(x) (((x) & 0xf) << 16)
+#define MMC3_PRE_RATIO(x) (((x) & 0xff) << 24)
+
+/* CLK_DIV_STAT_FSYS2 */
+#define DIV_MMC2(x) ((x) & 0x1)
+#define DIV_MMC2_PRE(x) (((x) & 0x1) << 8)
+#define DIV_MMC3(x) (((x) & 0x1) << 16)
+#define DIV_MMC3_PRE(x) (((x) & 0x1) << 24)
+
+#define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \
+ DIV_MMC2_PRE(DIV_STAT_CHANGING) | \
+ DIV_MMC3(DIV_STAT_CHANGING) | \
+ DIV_MMC3_PRE(DIV_STAT_CHANGING))
+
+/* CLK_DIV_FSYS3 */
+#define MMC4_RATIO(x) ((x) & 0x7)
+#define MMC4_PRE_RATIO(x) (((x) & 0xff) << 8)
+
+/* CLK_DIV_STAT_FSYS3 */
+#define DIV_MMC4(x) ((x) & 0x1)
+#define DIV_MMC4_PRE(x) (((x) & 0x1) << 8)
+
+#define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \
+ DIV_MMC4_PRE(DIV_STAT_CHANGING))
+
+/* XCL205 GPIO config - Odroid U3 */
+#define XCL205_GPIO_BASE EXYNOS4X12_GPIO_PART1_BASE
+#define XCL205_EN_GPIO_OFFSET 0x20 /* GPA1 */
+#define XCL205_EN_GPIO_PIN 1
+#define XCL205_EN_GPIO_CON (XCL205_GPIO_BASE + \
+ XCL205_EN_GPIO_OFFSET)
+#define XCL205_EN_GPIO_CON_CFG (S5P_GPIO_OUTPUT << \
+ 4 * XCL205_EN_GPIO_PIN)
+#define XCL205_EN_GPIO_DAT_CFG (0x1 << XCL205_EN_GPIO_PIN)
+#define XCL205_EN_GPIO_PUD_CFG (S5P_GPIO_PULL_UP << \
+ 2 * XCL205_EN_GPIO_PIN)
+#define XCL205_EN_GPIO_DRV_CFG (S5P_GPIO_DRV_4X << \
+ 2 * XCL205_EN_GPIO_PIN)
+
+#define XCL205_STATE_GPIO_OFFSET 0x80 /* GPC1 */
+#define XCL205_STATE_GPIO_PIN 2
+#define XCL205_STATE_GPIO_CON (XCL205_GPIO_BASE + \
+ XCL205_STATE_GPIO_OFFSET)
+#define XCL205_STATE_GPIO_DAT XCL205_STATE_GPIO_CON + 0x4
+#define XCL205_STATE_GPIO_CON_CFG (S5P_GPIO_INPUT << \
+ 4 * XCL205_STATE_GPIO_PIN)
+#define XCL205_STATE_GPIO_PUD_CFG (S5P_GPIO_PULL_NONE << \
+ 2 * XCL205_STATE_GPIO_PIN)
+
+#ifdef CONFIG_BOARD_TYPES
+extern void sdelay(unsigned long);
+#endif
+
+#endif /*__ODROIDU3_SETUP__ */
diff --git a/board/samsung/origen/Kconfig b/board/samsung/origen/Kconfig
new file mode 100644
index 0000000..63e3efe
--- /dev/null
+++ b/board/samsung/origen/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ORIGEN
+
+config SYS_BOARD
+ default "origen"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "origen"
+
+endif
diff --git a/board/samsung/origen/MAINTAINERS b/board/samsung/origen/MAINTAINERS
new file mode 100644
index 0000000..8bf373e
--- /dev/null
+++ b/board/samsung/origen/MAINTAINERS
@@ -0,0 +1,6 @@
+ORIGEN BOARD
+M: Chander Kashyap <k.chander@samsung.com>
+S: Maintained
+F: board/samsung/origen/
+F: include/configs/origen.h
+F: configs/origen_defconfig
diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile
new file mode 100644
index 0000000..1add9fe
--- /dev/null
+++ b/board/samsung/origen/Makefile
@@ -0,0 +1,22 @@
+#
+# Copyright (C) 2011 Samsung Electronics
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+
+hostprogs-y := tools/mkorigenspl
+always := $(hostprogs-y)
+
+# omit -O2 option to suppress
+# warning: dereferencing type-punned pointer will break strict-aliasing rules
+#
+# TODO:
+# Fix the root cause in tools/mkorigenspl.c and delete the following work-around
+$(obj)/tools/mkorigenspl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS))
+else
+obj-y += origen.o
+endif
diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c
new file mode 100644
index 0000000..99a2fac
--- /dev/null
+++ b/board/samsung/origen/origen.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_board_rev(void)
+{
+ return 0;
+}
+
+int exynos_init(void)
+{
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int exynos_early_init_f(void)
+{
+ return 0;
+}
+#endif
diff --git a/board/samsung/origen/tools/mkorigenspl.c b/board/samsung/origen/tools/mkorigenspl.c
new file mode 100644
index 0000000..3ed20ef
--- /dev/null
+++ b/board/samsung/origen/tools/mkorigenspl.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <string.h>
+#include <sys/stat.h>
+
+#define BUFSIZE (16*1024)
+#define IMG_SIZE (16*1024)
+#define SPL_HEADER_SIZE 16
+#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \
+ | S_IWGRP | S_IROTH | S_IWOTH)
+#define SPL_HEADER "S5PC210 HEADER "
+/*
+* Requirement:
+* IROM code reads first 14K bytes from boot device.
+* It then calculates the checksum of 14K-4 bytes and compare with data at
+* 14K-4 offset.
+*
+* This function takes two filenames:
+* IN "u-boot-spl.bin" and
+* OUT "$(BOARD)-spl.bin as filenames.
+* It reads the "u-boot-spl.bin" in 16K buffer.
+* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer.
+* It writes the buffer to "$(BOARD)-spl.bin" file.
+*/
+
+int main(int argc, char **argv)
+{
+ int i, len;
+ unsigned char buffer[BUFSIZE] = {0};
+ int ifd, ofd;
+ unsigned int checksum = 0, count;
+
+ if (argc != 3) {
+ printf(" %d Wrong number of arguments\n", argc);
+ exit(EXIT_FAILURE);
+ }
+
+ ifd = open(argv[1], O_RDONLY);
+ if (ifd < 0) {
+ fprintf(stderr, "%s: Can't open %s: %s\n",
+ argv[0], argv[1], strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
+ if (ifd < 0) {
+ fprintf(stderr, "%s: Can't open %s: %s\n",
+ argv[0], argv[2], strerror(errno));
+ if (ifd)
+ close(ifd);
+ exit(EXIT_FAILURE);
+ }
+
+ len = lseek(ifd, 0, SEEK_END);
+ lseek(ifd, 0, SEEK_SET);
+
+ memcpy(&buffer[0], SPL_HEADER, SPL_HEADER_SIZE);
+
+ count = (len < (IMG_SIZE - SPL_HEADER_SIZE))
+ ? len : (IMG_SIZE - SPL_HEADER_SIZE);
+
+ if (read(ifd, buffer + SPL_HEADER_SIZE, count) != count) {
+ fprintf(stderr, "%s: Can't read %s: %s\n",
+ argv[0], argv[1], strerror(errno));
+
+ if (ifd)
+ close(ifd);
+ if (ofd)
+ close(ofd);
+
+ exit(EXIT_FAILURE);
+ }
+
+ for (i = 0; i < IMG_SIZE - SPL_HEADER_SIZE; i++)
+ checksum += buffer[i+16];
+
+ *(ulong *)buffer ^= 0x1f;
+ *(ulong *)(buffer+4) ^= checksum;
+
+ for (i = 1; i < SPL_HEADER_SIZE; i++)
+ buffer[i] ^= buffer[i-1];
+
+ if (write(ofd, buffer, BUFSIZE) != BUFSIZE) {
+ fprintf(stderr, "%s: Can't write %s: %s\n",
+ argv[0], argv[2], strerror(errno));
+
+ if (ifd)
+ close(ifd);
+ if (ofd)
+ close(ofd);
+
+ exit(EXIT_FAILURE);
+ }
+
+ if (ifd)
+ close(ifd);
+ if (ofd)
+ close(ofd);
+
+ return EXIT_SUCCESS;
+}
diff --git a/board/samsung/smdk2410/Kconfig b/board/samsung/smdk2410/Kconfig
new file mode 100644
index 0000000..e987b64
--- /dev/null
+++ b/board/samsung/smdk2410/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SMDK2410
+
+config SYS_BOARD
+ default "smdk2410"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_SOC
+ default "s3c24x0"
+
+config SYS_CONFIG_NAME
+ default "smdk2410"
+
+endif
diff --git a/board/samsung/smdk2410/MAINTAINERS b/board/samsung/smdk2410/MAINTAINERS
new file mode 100644
index 0000000..12a25e8
--- /dev/null
+++ b/board/samsung/smdk2410/MAINTAINERS
@@ -0,0 +1,6 @@
+SMDK2410 BOARD
+M: David Müller <d.mueller@elsoft.ch>
+S: Maintained
+F: board/samsung/smdk2410/
+F: include/configs/smdk2410.h
+F: configs/smdk2410_defconfig
diff --git a/board/samsung/smdk2410/Makefile b/board/samsung/smdk2410/Makefile
new file mode 100644
index 0000000..1939a21
--- /dev/null
+++ b/board/samsung/smdk2410/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := smdk2410.o
+obj-y += lowlevel_init.o
diff --git a/board/samsung/smdk2410/lowlevel_init.S b/board/samsung/smdk2410/lowlevel_init.S
new file mode 100644
index 0000000..5de04f1
--- /dev/null
+++ b/board/samsung/smdk2410/lowlevel_init.S
@@ -0,0 +1,148 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
+ *
+ * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
+ *
+ */
+
+#define BWSCON 0x48000000
+
+/* BWSCON */
+#define DW8 (0x0)
+#define DW16 (0x1)
+#define DW32 (0x2)
+#define WAIT (0x1<<2)
+#define UBLB (0x1<<3)
+
+#define B1_BWSCON (DW32)
+#define B2_BWSCON (DW16)
+#define B3_BWSCON (DW16 + WAIT + UBLB)
+#define B4_BWSCON (DW16)
+#define B5_BWSCON (DW16)
+#define B6_BWSCON (DW32)
+#define B7_BWSCON (DW32)
+
+/* BANK0CON */
+#define B0_Tacs 0x0 /* 0clk */
+#define B0_Tcos 0x0 /* 0clk */
+#define B0_Tacc 0x7 /* 14clk */
+#define B0_Tcoh 0x0 /* 0clk */
+#define B0_Tah 0x0 /* 0clk */
+#define B0_Tacp 0x0
+#define B0_PMC 0x0 /* normal */
+
+/* BANK1CON */
+#define B1_Tacs 0x0 /* 0clk */
+#define B1_Tcos 0x0 /* 0clk */
+#define B1_Tacc 0x7 /* 14clk */
+#define B1_Tcoh 0x0 /* 0clk */
+#define B1_Tah 0x0 /* 0clk */
+#define B1_Tacp 0x0
+#define B1_PMC 0x0
+
+#define B2_Tacs 0x0
+#define B2_Tcos 0x0
+#define B2_Tacc 0x7
+#define B2_Tcoh 0x0
+#define B2_Tah 0x0
+#define B2_Tacp 0x0
+#define B2_PMC 0x0
+
+#define B3_Tacs 0x0 /* 0clk */
+#define B3_Tcos 0x3 /* 4clk */
+#define B3_Tacc 0x7 /* 14clk */
+#define B3_Tcoh 0x1 /* 1clk */
+#define B3_Tah 0x0 /* 0clk */
+#define B3_Tacp 0x3 /* 6clk */
+#define B3_PMC 0x0 /* normal */
+
+#define B4_Tacs 0x0 /* 0clk */
+#define B4_Tcos 0x0 /* 0clk */
+#define B4_Tacc 0x7 /* 14clk */
+#define B4_Tcoh 0x0 /* 0clk */
+#define B4_Tah 0x0 /* 0clk */
+#define B4_Tacp 0x0
+#define B4_PMC 0x0 /* normal */
+
+#define B5_Tacs 0x0 /* 0clk */
+#define B5_Tcos 0x0 /* 0clk */
+#define B5_Tacc 0x7 /* 14clk */
+#define B5_Tcoh 0x0 /* 0clk */
+#define B5_Tah 0x0 /* 0clk */
+#define B5_Tacp 0x0
+#define B5_PMC 0x0 /* normal */
+
+#define B6_MT 0x3 /* SDRAM */
+#define B6_Trcd 0x1
+#define B6_SCAN 0x1 /* 9bit */
+
+#define B7_MT 0x3 /* SDRAM */
+#define B7_Trcd 0x1 /* 3clk */
+#define B7_SCAN 0x1 /* 9bit */
+
+/* REFRESH parameter */
+#define REFEN 0x1 /* Refresh enable */
+#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
+#define Trp 0x0 /* 2clk */
+#define Trc 0x3 /* 7clk */
+#define Tchr 0x2 /* 3clk */
+#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+.globl lowlevel_init
+lowlevel_init:
+ /* memory control configuration */
+ /* make r0 relative the current location so that it */
+ /* reads SMRDATA out of FLASH rather than memory ! */
+ ldr r0, =SMRDATA
+ ldr r1, =CONFIG_SYS_TEXT_BASE
+ sub r0, r0, r1
+ ldr r1, =BWSCON /* Bus Width Status Controller */
+ add r2, r0, #13*4
+0:
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ cmp r2, r0
+ bne 0b
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+/* the literal pools origin */
+
+SMRDATA:
+ .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+ .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+ .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+ .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+ .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+ .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+ .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+ .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+ .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+ .word 0x32
+ .word 0x30
+ .word 0x30
diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c
new file mode 100644
index 0000000..b75a0e3
--- /dev/null
+++ b/board/samsung/smdk2410/smdk2410.c
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002, 2010
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV 0xC3
+#define M_PDIV 0x4
+#define M_SDIV 0x1
+#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
+#define M_MDIV 0xA1
+#define M_PDIV 0x3
+#define M_SDIV 0x1
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV 0xA1
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV 0x48
+#define U_M_PDIV 0x3
+#define U_M_SDIV 0x2
+#endif
+
+static inline void pll_delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_early_init_f(void)
+{
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+ /* to reduce PLL lock time, adjust the LOCKTIME register */
+ writel(0xFFFFFF, &clk_power->locktime);
+
+ /* configure MPLL */
+ writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
+ &clk_power->mpllcon);
+
+ /* some delay between MPLL and UPLL */
+ pll_delay(4000);
+
+ /* configure UPLL */
+ writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
+ &clk_power->upllcon);
+
+ /* some delay between MPLL and UPLL */
+ pll_delay(8000);
+
+ /* set up the I/O ports */
+ writel(0x007FFFFF, &gpio->gpacon);
+ writel(0x00044555, &gpio->gpbcon);
+ writel(0x000007FF, &gpio->gpbup);
+ writel(0xAAAAAAAA, &gpio->gpccon);
+ writel(0x0000FFFF, &gpio->gpcup);
+ writel(0xAAAAAAAA, &gpio->gpdcon);
+ writel(0x0000FFFF, &gpio->gpdup);
+ writel(0xAAAAAAAA, &gpio->gpecon);
+ writel(0x0000FFFF, &gpio->gpeup);
+ writel(0x000055AA, &gpio->gpfcon);
+ writel(0x000000FF, &gpio->gpfup);
+ writel(0xFF95FFBA, &gpio->gpgcon);
+ writel(0x0000FFFF, &gpio->gpgup);
+ writel(0x002AFAAA, &gpio->gphcon);
+ writel(0x000007FF, &gpio->gphup);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* arch number of SMDK2410-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x30000100;
+
+ icache_enable();
+ dcache_enable();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_CS8900
+ rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+ return rc;
+}
+#endif
+
+/*
+ * Hardcoded flash setup:
+ * Flash 0 is a non-CFI AMD AM29LV800BB flash.
+ */
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return 1;
+}
diff --git a/board/samsung/smdk5250/Kconfig b/board/samsung/smdk5250/Kconfig
new file mode 100644
index 0000000..698ee91
--- /dev/null
+++ b/board/samsung/smdk5250/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_SMDK5250
+
+config SYS_BOARD
+ default "smdk5250"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "smdk5250"
+
+endif
+
+if TARGET_SNOW
+
+config SYS_BOARD
+ default "smdk5250"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "snow"
+
+endif
diff --git a/board/samsung/smdk5250/MAINTAINERS b/board/samsung/smdk5250/MAINTAINERS
new file mode 100644
index 0000000..070593e
--- /dev/null
+++ b/board/samsung/smdk5250/MAINTAINERS
@@ -0,0 +1,12 @@
+SMDK5250 BOARD
+M: Chander Kashyap <k.chander@samsung.com>
+S: Maintained
+F: board/samsung/smdk5250/
+F: include/configs/smdk5250.h
+F: configs/smdk5250_defconfig
+
+SNOW BOARD
+M: Akshay Saraswat <akshay.s@samsung.com>
+S: Maintained
+F: include/configs/snow.h
+F: configs/snow_defconfig
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
new file mode 100644
index 0000000..3d96b07
--- /dev/null
+++ b/board/samsung/smdk5250/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2012 Samsung Electronics
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += smdk5250_spl.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += exynos5-dt.o
+endif
diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c
new file mode 100644
index 0000000..53ff706
--- /dev/null
+++ b/board/samsung/smdk5250/exynos5-dt.c
@@ -0,0 +1,306 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <spi.h>
+#include <asm/gpio.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/sromc.h>
+#include <power/pmic.h>
+#include <power/max77686_pmic.h>
+#include <power/tps65090_pmic.h>
+#include <tmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SOUND_MAX98095
+static void board_enable_audio_codec(void)
+{
+ /* Enable MAX98095 Codec */
+ gpio_request(EXYNOS5_GPIO_X17, "max98095_enable");
+ gpio_direction_output(EXYNOS5_GPIO_X17, 1);
+ gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
+}
+#endif
+
+int exynos_init(void)
+{
+#ifdef CONFIG_SOUND_MAX98095
+ board_enable_audio_codec();
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_POWER)
+#ifdef CONFIG_POWER_MAX77686
+static int pmic_reg_update(struct pmic *p, int reg, uint regval)
+{
+ u32 val;
+ int ret = 0;
+
+ ret = pmic_reg_read(p, reg, &val);
+ if (ret) {
+ debug("%s: PMIC %d register read failed\n", __func__, reg);
+ return -1;
+ }
+ val |= regval;
+ ret = pmic_reg_write(p, reg, val);
+ if (ret) {
+ debug("%s: PMIC %d register write failed\n", __func__, reg);
+ return -1;
+ }
+ return 0;
+}
+
+static int max77686_init(void)
+{
+ struct pmic *p;
+
+ if (pmic_init(I2C_PMIC))
+ return -1;
+
+ p = pmic_get("MAX77686_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
+ return -1;
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
+ MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
+ return -1;
+
+ /* VDD_MIF */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
+ MAX77686_BUCK1OUT_1V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK1OUT);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
+ MAX77686_BUCK1CTRL_EN))
+ return -1;
+
+ /* VDD_ARM */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
+ MAX77686_BUCK2DVS1_1_3V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK2DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
+ MAX77686_BUCK2CTRL_ON))
+ return -1;
+
+ /* VDD_INT */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
+ MAX77686_BUCK3DVS1_1_0125V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK3DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_G3D */
+ if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
+ MAX77686_BUCK4DVS1_1_2V)) {
+ debug("%s: PMIC %d register write failed\n", __func__,
+ MAX77686_REG_PMIC_BUCK4DVS1);
+ return -1;
+ }
+
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
+ MAX77686_BUCK3CTRL_ON))
+ return -1;
+
+ /* VDD_LDO2 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
+ MAX77686_LD02CTRL1_1_5V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO3 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
+ MAX77686_LD03CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO5 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
+ MAX77686_LD05CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ /* VDD_LDO10 */
+ if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
+ MAX77686_LD10CTRL1_1_8V | EN_LDO))
+ return -1;
+
+ return 0;
+}
+#endif /* CONFIG_POWER_MAX77686 */
+
+int exynos_power_init(void)
+{
+ int ret = 0;
+
+#ifdef CONFIG_POWER_MAX77686
+ ret = max77686_init();
+ if (ret)
+ return ret;
+#endif
+#ifdef CONFIG_POWER_TPS65090
+ /*
+ * The TPS65090 may not be in the device tree. If so, it is not
+ * an error.
+ */
+ ret = tps65090_init();
+ if (ret == 0 || ret == -ENODEV)
+ return 0;
+#endif
+
+ return ret;
+}
+#endif /* CONFIG_POWER */
+
+#ifdef CONFIG_LCD
+static int board_dp_bridge_setup(void)
+{
+ const int max_tries = 10;
+ int num_tries, node;
+
+ /*
+ * TODO(sjg): Use device tree for GPIOs when exynos GPIO
+ * numbering patch is in mainline.
+ */
+ debug("%s\n", __func__);
+ node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_NXP_PTN3460);
+ if (node < 0) {
+ debug("%s: No node for DP bridge in device tree\n", __func__);
+ return -ENODEV;
+ }
+
+ /* Setup the GPIOs */
+
+ /* PD is ACTIVE_LOW, and initially de-asserted */
+ gpio_request(EXYNOS5_GPIO_Y25, "dp_bridge_pd");
+ gpio_set_pull(EXYNOS5_GPIO_Y25, S5P_GPIO_PULL_NONE);
+ gpio_direction_output(EXYNOS5_GPIO_Y25, 1);
+
+ /* Reset is ACTIVE_LOW */
+ gpio_request(EXYNOS5_GPIO_X15, "dp_bridge_reset");
+ gpio_set_pull(EXYNOS5_GPIO_X15, S5P_GPIO_PULL_NONE);
+ gpio_direction_output(EXYNOS5_GPIO_X15, 0);
+
+ udelay(10);
+ gpio_set_value(EXYNOS5_GPIO_X15, 1);
+
+ gpio_request(EXYNOS5_GPIO_X07, "dp_bridge_hpd");
+ gpio_direction_input(EXYNOS5_GPIO_X07);
+
+ /*
+ * We need to wait for 90ms after bringing up the bridge since there
+ * is a phantom "high" on the HPD chip during its bootup. The phantom
+ * high comes within 7ms of de-asserting PD and persists for at least
+ * 15ms. The real high comes roughly 50ms after PD is de-asserted. The
+ * phantom high makes it hard for us to know when the NXP chip is up.
+ */
+ mdelay(90);
+
+ for (num_tries = 0; num_tries < max_tries; num_tries++) {
+ /* Check HPD. If it's high, we're all good. */
+ if (gpio_get_value(EXYNOS5_GPIO_X07))
+ return 0;
+
+ debug("%s: eDP bridge failed to come up; try %d of %d\n",
+ __func__, num_tries, max_tries);
+ }
+
+ /* Immediately go into bridge reset if the hp line is not high */
+ return -ENODEV;
+}
+
+void exynos_cfg_lcd_gpio(void)
+{
+ /* For Backlight */
+ gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight");
+ gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5_GPIO_B20, 1);
+
+ /* LCD power on */
+ gpio_request(EXYNOS5_GPIO_X15, "lcd_power");
+ gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
+ gpio_set_value(EXYNOS5_GPIO_X15, 1);
+
+ /* Set Hotplug detect for DP */
+ gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
+}
+
+void exynos_set_dp_phy(unsigned int onoff)
+{
+ set_dp_phy_ctrl(onoff);
+}
+
+void exynos_backlight_on(unsigned int on)
+{
+ debug("%s(%u)\n", __func__, on);
+
+ if (!on)
+ return;
+
+#ifdef CONFIG_POWER_TPS65090
+ int ret;
+
+ ret = tps65090_fet_enable(1); /* Enable FET1, backlight */
+ if (ret)
+ return;
+
+ /* T5 in the LCD timing spec (defined as > 10ms) */
+ mdelay(10);
+
+ /* board_dp_backlight_pwm */
+ gpio_direction_output(EXYNOS5_GPIO_B20, 1);
+
+ /* T6 in the LCD timing spec (defined as > 10ms) */
+ mdelay(10);
+
+ /* board_dp_backlight_en */
+ gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en");
+ gpio_direction_output(EXYNOS5_GPIO_X30, 1);
+#endif
+}
+
+void exynos_lcd_power_on(void)
+{
+ int ret;
+
+ debug("%s\n", __func__);
+
+#ifdef CONFIG_POWER_TPS65090
+ /* board_dp_lcd_vdd */
+ tps65090_fet_enable(6); /* Enable FET6, lcd panel */
+#endif
+
+ ret = board_dp_bridge_setup();
+ if (ret && ret != -ENODEV)
+ printf("LCD bridge failed to enable: %d\n", ret);
+}
+
+#endif
diff --git a/board/samsung/smdk5250/smdk5250_spl.c b/board/samsung/smdk5250/smdk5250_spl.c
new file mode 100644
index 0000000..7f3916a
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250_spl.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/clk.h>
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(".machine_param"))) = {
+ .signature = SIGNATURE,
+ .version = 1,
+ .params = "vmubfasirM",
+ .size = sizeof(machine_param),
+
+ .mem_iv_size = 0x1f,
+ .mem_type = DDR_MODE_DDR3,
+
+ /*
+ * Set uboot_size to 0x100000 bytes.
+ *
+ * This is an overly conservative value chosen to accommodate all
+ * possible U-Boot image. You are advised to set this value to a
+ * smaller realistic size via scripts that modifies the .machine_param
+ * section of output U-Boot image.
+ */
+ .uboot_size = 0x100000,
+
+ .boot_source = BOOT_MODE_OM,
+ .frequency_mhz = 800,
+ .arm_freq_mhz = 1700,
+ .serial_base = 0x12c30000,
+ .i2c_base = 0x12c60000,
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+ if (machine_param.signature != SIGNATURE) {
+ /* Will hang if SIGNATURE dont match */
+ while (1)
+ ;
+ }
+
+ return &machine_param;
+}
diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig
new file mode 100644
index 0000000..a9d62ff
--- /dev/null
+++ b/board/samsung/smdk5420/Kconfig
@@ -0,0 +1,51 @@
+if TARGET_ODROID_XU3
+
+config SYS_BOARD
+ default "smdk5420"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "odroid_xu3"
+
+endif
+
+if TARGET_PEACH_PI
+
+config SYS_BOARD
+ default "smdk5420"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "peach-pi"
+
+endif
+
+if TARGET_PEACH_PIT
+
+config SYS_BOARD
+ default "smdk5420"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "peach-pit"
+
+endif
+
+if TARGET_SMDK5420
+
+config SYS_BOARD
+ default "smdk5420"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "smdk5420"
+
+endif
diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS
new file mode 100644
index 0000000..1423f83
--- /dev/null
+++ b/board/samsung/smdk5420/MAINTAINERS
@@ -0,0 +1,10 @@
+SMDK5420 BOARD
+M: Akshay Saraswat <akshay.s@samsung.com>
+S: Maintained
+F: board/samsung/smdk5420/
+F: include/configs/peach-pit.h
+F: configs/peach-pit_defconfig
+F: include/configs/smdk5420.h
+F: configs/smdk5420_defconfig
+F: include/configs/peach-pi.h
+F: configs/peach-pi_defconfig
diff --git a/board/samsung/smdk5420/Makefile b/board/samsung/smdk5420/Makefile
new file mode 100644
index 0000000..c2f8886
--- /dev/null
+++ b/board/samsung/smdk5420/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2013 Samsung Electronics
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += smdk5420_spl.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += smdk5420.o
+endif
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c
new file mode 100644
index 0000000..1aca9fa
--- /dev/null
+++ b/board/samsung/smdk5420/smdk5420.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <lcd.h>
+#include <parade.h>
+#include <spi.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/arch/board.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/system.h>
+#include <asm/arch/dp_info.h>
+#include <power/tps65090_pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int exynos_init(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_LCD
+static int has_edp_bridge(void)
+{
+ int node;
+
+ node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_PARADE_PS8625);
+
+ /* No node for bridge in device tree. */
+ if (node <= 0)
+ return 0;
+
+ /* Default is with bridge ic */
+ return 1;
+}
+
+void exynos_lcd_power_on(void)
+{
+ int ret;
+
+#ifdef CONFIG_POWER_TPS65090
+ ret = tps65090_init();
+ if (ret < 0) {
+ printf("%s: tps65090_init() failed\n", __func__);
+ return;
+ }
+
+ tps65090_fet_enable(6);
+#endif
+
+ mdelay(5);
+
+ /* TODO(ajaykumar.rs@samsung.com): Use device tree */
+ gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
+ gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
+ mdelay(10);
+ gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
+ gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
+ gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
+ gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
+ gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
+
+ if (has_edp_bridge())
+ if (parade_init(gd->fdt_blob))
+ printf("%s: ps8625_init() failed\n", __func__);
+}
+
+void exynos_backlight_on(unsigned int onoff)
+{
+ /* For PWM */
+ gpio_request(EXYNOS5420_GPIO_B20, "backlight_on");
+ gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(0x1));
+ gpio_set_value(EXYNOS5420_GPIO_B20, 1);
+
+#ifdef CONFIG_POWER_TPS65090
+ tps65090_fet_enable(1);
+#endif
+}
+#endif
+
+int board_get_revision(void)
+{
+ return 0;
+}
diff --git a/board/samsung/smdk5420/smdk5420_spl.c b/board/samsung/smdk5420/smdk5420_spl.c
new file mode 100644
index 0000000..73359f7
--- /dev/null
+++ b/board/samsung/smdk5420/smdk5420_spl.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2013 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/clk.h>
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(".machine_param"))) = {
+ .signature = SIGNATURE,
+ .version = 1,
+ .params = "vmubfasirM",
+ .size = sizeof(machine_param),
+
+ .mem_iv_size = 0x1f,
+ .mem_type = DDR_MODE_DDR3,
+
+ /*
+ * Set uboot_size to 0x100000 bytes.
+ *
+ * This is an overly conservative value chosen to accommodate all
+ * possible U-Boot image. You are advised to set this value to a
+ * smaller realistic size via scripts that modifies the .machine_param
+ * section of output U-Boot image.
+ */
+ .uboot_size = 0x100000,
+
+ .boot_source = BOOT_MODE_OM,
+ .frequency_mhz = 800,
+ .arm_freq_mhz = 900,
+ .serial_base = 0x12c30000,
+ .i2c_base = 0x12c60000,
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+ if (machine_param.signature != SIGNATURE) {
+ /* Will hang if SIGNATURE dont match */
+ while (1)
+ ;
+ }
+
+ return &machine_param;
+}
diff --git a/board/samsung/smdkc100/Kconfig b/board/samsung/smdkc100/Kconfig
new file mode 100644
index 0000000..d2157b4
--- /dev/null
+++ b/board/samsung/smdkc100/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SMDKC100
+
+config SYS_BOARD
+ default "smdkc100"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_SOC
+ default "s5pc1xx"
+
+config SYS_CONFIG_NAME
+ default "smdkc100"
+
+endif
diff --git a/board/samsung/smdkc100/MAINTAINERS b/board/samsung/smdkc100/MAINTAINERS
new file mode 100644
index 0000000..39949e4
--- /dev/null
+++ b/board/samsung/smdkc100/MAINTAINERS
@@ -0,0 +1,6 @@
+SMDKC100 BOARD
+M: Minkyu Kang <mk7.kang@samsung.com>
+S: Maintained
+F: board/samsung/smdkc100/
+F: include/configs/smdkc100.h
+F: configs/smdkc100_defconfig
diff --git a/board/samsung/smdkc100/Makefile b/board/samsung/smdkc100/Makefile
new file mode 100644
index 0000000..0bcf4e5
--- /dev/null
+++ b/board/samsung/smdkc100/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := smdkc100.o
+obj-$(CONFIG_SAMSUNG_ONENAND) += onenand.o
+obj-y += lowlevel_init.o
diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S
new file mode 100644
index 0000000..65e6b7a
--- /dev/null
+++ b/board/samsung/smdkc100/lowlevel_init.S
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/power.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ */
+
+ .globl lowlevel_init
+lowlevel_init:
+ mov r9, lr
+
+ /* r5 has always zero */
+ mov r5, #0
+
+ ldr r8, =S5PC100_GPIO_BASE
+
+ /* Disable Watchdog */
+ ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
+ orr r0, r0, #0x0
+ str r5, [r0]
+
+ /* setting SRAM */
+ ldr r0, =S5PC100_SROMC_BASE
+ ldr r1, =0x9
+ str r1, [r0]
+
+ /* S5PC100 has 3 groups of interrupt sources */
+ ldr r0, =S5PC100_VIC0_BASE @0xE4000000
+ ldr r1, =S5PC100_VIC1_BASE @0xE4000000
+ ldr r2, =S5PC100_VIC2_BASE @0xE4000000
+
+ /* Disable all interrupts (VIC0, VIC1 and VIC2) */
+ mvn r3, #0x0
+ str r3, [r0, #0x14] @INTENCLEAR
+ str r3, [r1, #0x14] @INTENCLEAR
+ str r3, [r2, #0x14] @INTENCLEAR
+
+ /* Set all interrupts as IRQ */
+ str r5, [r0, #0xc] @INTSELECT
+ str r5, [r1, #0xc] @INTSELECT
+ str r5, [r2, #0xc] @INTSELECT
+
+ /* Pending Interrupt Clear */
+ str r5, [r0, #0xf00] @INTADDRESS
+ str r5, [r1, #0xf00] @INTADDRESS
+ str r5, [r2, #0xf00] @INTADDRESS
+
+ /* for UART */
+ bl uart_asm_init
+
+ /* for TZPC */
+ bl tzpc_asm_init
+
+1:
+ mov lr, r9
+ mov pc, lr
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+ ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000
+
+ /* Set Clock divider */
+ ldr r1, =0x00011110
+ str r1, [r8, #0x304]
+ ldr r1, =0x1
+ str r1, [r8, #0x308]
+ ldr r1, =0x00011301
+ str r1, [r8, #0x300]
+
+ /* Set Lock Time */
+ ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
+ str r1, [r8, #0x000] @ APLL_LOCK
+ str r1, [r8, #0x004] @ MPLL_LOCK
+ str r1, [r8, #0x008] @ EPLL_LOCK
+ str r1, [r8, #0x00C] @ HPLL_LOCK
+
+ /* APLL_CON */
+ ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
+ str r1, [r8, #0x100]
+ /* MPLL_CON */
+ ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
+ str r1, [r8, #0x104]
+ /* EPLL_CON */
+ ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
+ str r1, [r8, #0x108]
+ /* HPLL_CON */
+ ldr r1, =0x80600603
+ str r1, [r8, #0x10C]
+
+ /* Set Source Clock */
+ ldr r1, =0x1111 @ A, M, E, HPLL Muxing
+ str r1, [r8, #0x200] @ CLK_SRC0
+
+ ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
+ str r1, [r8, #0x204] @ CLK_SRC1
+
+ ldr r1, =0x9000 @ ARMCLK/4
+ str r1, [r8, #0x400] @ CLK_OUT
+
+ /* wait at least 200us to stablize all clock */
+ mov r2, #0x10000
+1: subs r2, r2, #1
+ bne 1b
+
+ mov pc, lr
+
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+ mov r0, r8
+ ldr r1, =0x22222222
+ str r1, [r0, #0x0] @ GPA0_CON
+ ldr r1, =0x00022222
+ str r1, [r0, #0x20] @ GPA1_CON
+
+ mov pc, lr
+
+/*
+ * tzpc_asm_init: Initialize TZPC
+ */
+tzpc_asm_init:
+ ldr r0, =0xE3800000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x804]
+ str r1, [r0, #0x810]
+
+ ldr r0, =0xE2800000
+ str r1, [r0, #0x804]
+ str r1, [r0, #0x810]
+ str r1, [r0, #0x81C]
+
+ ldr r0, =0xE2900000
+ str r1, [r0, #0x804]
+ str r1, [r0, #0x810]
+
+ mov pc, lr
diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c
new file mode 100644
index 0000000..577c1a5
--- /dev/null
+++ b/board/samsung/smdkc100/onenand.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+
+#include <onenand_uboot.h>
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+ struct s5pc100_clock *clk =
+ (struct s5pc100_clock *)samsung_get_base_clock();
+ struct samsung_onenand *onenand;
+ int value;
+
+ this->base = (void *)S5PC100_ONENAND_BASE;
+ onenand = (struct samsung_onenand *)this->base;
+
+ /* D0 Domain memory clock gating */
+ value = readl(&clk->gate_d01);
+ value &= ~(1 << 2); /* CLK_ONENANDC */
+ value |= (1 << 2);
+ writel(value, &clk->gate_d01);
+
+ value = readl(&clk->src0);
+ value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */
+ value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */
+ writel(value, &clk->src0);
+
+ value = readl(&clk->div1);
+ value &= ~(3 << 16); /* PCLKD1_RATIO */
+ value |= (1 << 16);
+ writel(value, &clk->div1);
+
+ writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
+
+ while (!(readl(&onenand->int_err_stat) & RST_CMP))
+ continue;
+
+ writel(RST_CMP, &onenand->int_err_ack);
+
+ /*
+ * Access_Clock [2:0]
+ * 166 MHz, 134 Mhz : 3
+ * 100 Mhz, 60 Mhz : 2
+ */
+ writel(0x3, &onenand->acc_clock);
+
+ writel(INT_ERR_ALL, &onenand->int_err_mask);
+ writel(1 << 0, &onenand->int_pin_en); /* Enable */
+
+ value = readl(&onenand->int_err_mask);
+ value &= ~RDY_ACT;
+ writel(value, &onenand->int_err_mask);
+
+ s3c_onenand_init(mtd);
+}
diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
new file mode 100644
index 0000000..66b6a98
--- /dev/null
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/sromc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+static void smc9115_pre_init(void)
+{
+ u32 smc_bw_conf, smc_bc_conf;
+
+ /* gpio configuration GPK0CON */
+ gpio_cfg_pin(S5PC100_GPIO_K00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
+
+ /* Ethernet needs bus width of 16 bits */
+ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+ smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe)
+ | SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4)
+ | SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
+
+ /* Select and configure the SROMC bank */
+ s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+}
+
+int board_init(void)
+{
+ smc9115_pre_init();
+
+ gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("Board:\tSMDKC100\n");
+ return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/samsung/smdkv310/Kconfig b/board/samsung/smdkv310/Kconfig
new file mode 100644
index 0000000..a6fd657
--- /dev/null
+++ b/board/samsung/smdkv310/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SMDKV310
+
+config SYS_BOARD
+ default "smdkv310"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "smdkv310"
+
+endif
diff --git a/board/samsung/smdkv310/MAINTAINERS b/board/samsung/smdkv310/MAINTAINERS
new file mode 100644
index 0000000..1e058cb
--- /dev/null
+++ b/board/samsung/smdkv310/MAINTAINERS
@@ -0,0 +1,6 @@
+SMDKV310 BOARD
+M: Chander Kashyap <k.chander@samsung.com>
+S: Maintained
+F: board/samsung/smdkv310/
+F: include/configs/smdkv310.h
+F: configs/smdkv310_defconfig
diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile
new file mode 100644
index 0000000..de0da16
--- /dev/null
+++ b/board/samsung/smdkv310/Makefile
@@ -0,0 +1,15 @@
+#
+# Copyright (C) 2011 Samsung Electronics
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+
+hostprogs-y := tools/mksmdkv310spl
+always := $(hostprogs-y)
+else
+obj-y += smdkv310.o
+endif
diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c
new file mode 100644
index 0000000..cb7f9b0
--- /dev/null
+++ b/board/samsung/smdkv310/smdkv310.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/sromc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void smc9115_pre_init(void)
+{
+ u32 smc_bw_conf, smc_bc_conf;
+
+ /* gpio configuration GPK0CON */
+ gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
+
+ /* Ethernet needs bus width of 16 bits */
+ smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+ smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F)
+ | SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F)
+ | SROMC_BC_TAH(0x0F) | SROMC_BC_TACP(0x0F)
+ | SROMC_BC_PMC(0x0F);
+
+ /* Select and configure the SROMC bank */
+ s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+}
+
+int board_init(void)
+{
+ smc9115_pre_init();
+
+ gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
+ PHYS_SDRAM_1_SIZE);
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
+ PHYS_SDRAM_2_SIZE);
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
+ PHYS_SDRAM_3_SIZE);
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
+ PHYS_SDRAM_4_SIZE);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("\nBoard: SMDKV310\n");
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ int i, err;
+
+ /*
+ * MMC2 SD card GPIO:
+ *
+ * GPK2[0] SD_2_CLK(2)
+ * GPK2[1] SD_2_CMD(2)
+ * GPK2[2] SD_2_CDn
+ * GPK2[3:6] SD_2_DATA[0:3](2)
+ */
+ for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) {
+ /* GPK2[0:6] special function 2 */
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
+
+ /* GPK2[0:6] drv 4x */
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+
+ /* GPK2[0:1] pull disable */
+ if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) {
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ continue;
+ }
+
+ /* GPK2[2:6] pull up */
+ gpio_set_pull(i, S5P_GPIO_PULL_UP);
+ }
+ err = s5p_mmc_init(2, 4);
+ return err;
+}
+#endif
+
+static int board_uart_init(void)
+{
+ int err;
+
+ err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART0 not configured\n");
+ return err;
+ }
+
+ err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART1 not configured\n");
+ return err;
+ }
+
+ err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART2 not configured\n");
+ return err;
+ }
+
+ err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("UART3 not configured\n");
+ return err;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ int err;
+ err = board_uart_init();
+ if (err) {
+ debug("UART init failed\n");
+ return err;
+ }
+ return err;
+}
+#endif
diff --git a/board/samsung/smdkv310/tools/mksmdkv310spl.c b/board/samsung/smdkv310/tools/mksmdkv310spl.c
new file mode 100644
index 0000000..9a64ca6
--- /dev/null
+++ b/board/samsung/smdkv310/tools/mksmdkv310spl.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <string.h>
+#include <sys/stat.h>
+
+#define CHECKSUM_OFFSET (14*1024-4)
+#define BUFSIZE (16*1024)
+#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \
+ | S_IWGRP | S_IROTH | S_IWOTH)
+/*
+* Requirement:
+* IROM code reads first 14K bytes from boot device.
+* It then calculates the checksum of 14K-4 bytes and compare with data at
+* 14K-4 offset.
+*
+* This function takes two filenames:
+* IN "u-boot-spl.bin" and
+* OUT "u-boot-mmc-spl.bin" as filenames.
+* It reads the "u-boot-spl.bin" in 16K buffer.
+* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer.
+* It writes the buffer to "u-boot-mmc-spl.bin" file.
+*/
+
+int main(int argc, char **argv)
+{
+ int i, len;
+ unsigned char buffer[BUFSIZE] = {0};
+ int ifd, ofd;
+ unsigned int checksum = 0, count;
+
+ if (argc != 3) {
+ printf(" %d Wrong number of arguments\n", argc);
+ exit(EXIT_FAILURE);
+ }
+
+ ifd = open(argv[1], O_RDONLY);
+ if (ifd < 0) {
+ fprintf(stderr, "%s: Can't open %s: %s\n",
+ argv[0], argv[1], strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
+ if (ifd < 0) {
+ fprintf(stderr, "%s: Can't open %s: %s\n",
+ argv[0], argv[2], strerror(errno));
+ if (ifd)
+ close(ifd);
+ exit(EXIT_FAILURE);
+ }
+
+ len = lseek(ifd, 0, SEEK_END);
+ lseek(ifd, 0, SEEK_SET);
+
+ count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET;
+
+ if (read(ifd, buffer, count) != count) {
+ fprintf(stderr, "%s: Can't read %s: %s\n",
+ argv[0], argv[1], strerror(errno));
+
+ if (ifd)
+ close(ifd);
+ if (ofd)
+ close(ofd);
+
+ exit(EXIT_FAILURE);
+ }
+
+ for (i = 0, checksum = 0; i < CHECKSUM_OFFSET; i++)
+ checksum += buffer[i];
+
+ memcpy(&buffer[CHECKSUM_OFFSET], &checksum, sizeof(checksum));
+
+ if (write(ofd, buffer, BUFSIZE) != BUFSIZE) {
+ fprintf(stderr, "%s: Can't write %s: %s\n",
+ argv[0], argv[2], strerror(errno));
+
+ if (ifd)
+ close(ifd);
+ if (ofd)
+ close(ofd);
+
+ exit(EXIT_FAILURE);
+ }
+
+ if (ifd)
+ close(ifd);
+ if (ofd)
+ close(ofd);
+
+ return EXIT_SUCCESS;
+}
diff --git a/board/samsung/trats/Kconfig b/board/samsung/trats/Kconfig
new file mode 100644
index 0000000..7e8377b
--- /dev/null
+++ b/board/samsung/trats/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TRATS
+
+config SYS_BOARD
+ default "trats"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "trats"
+
+endif
diff --git a/board/samsung/trats/MAINTAINERS b/board/samsung/trats/MAINTAINERS
new file mode 100644
index 0000000..1b219b4
--- /dev/null
+++ b/board/samsung/trats/MAINTAINERS
@@ -0,0 +1,6 @@
+TRATS BOARD
+M: Lukasz Majewski <l.majewski@samsung.com>
+S: Maintained
+F: board/samsung/trats/
+F: include/configs/trats.h
+F: configs/trats_defconfig
diff --git a/board/samsung/trats/Makefile b/board/samsung/trats/Makefile
new file mode 100644
index 0000000..5dc8a1f
--- /dev/null
+++ b/board/samsung/trats/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2011 Samsung Electronics
+# Heungjun Kim <riverful.kim@samsung.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += trats.o
diff --git a/board/samsung/trats/setup.h b/board/samsung/trats/setup.h
new file mode 100644
index 0000000..2f5ccb1
--- /dev/null
+++ b/board/samsung/trats/setup.h
@@ -0,0 +1,621 @@
+/*
+ * Machine Specific Values for TRATS board based on EXYNOS4210
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TRATS_SETUP_H
+#define _TRATS_SETUP_H
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+/* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */
+#define MUX_HPM_SEL_MOUTAPLL 0x0
+#define MUX_HPM_SEL_SCLKMPLL 0x1
+#define MUX_CORE_SEL_MOUTAPLL 0x0
+#define MUX_CORE_SEL_SCLKMPLL 0x1
+#define MUX_MPLL_SEL_FILPLL 0x0
+#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
+#define MUX_APLL_SEL_FILPLL 0x0
+#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
+#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
+ | (MUX_CORE_SEL_MOUTAPLL << 16) \
+ | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
+ | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
+
+/* CLK_DIV_CPU0 */
+#define APLL_RATIO 0x0
+#define PCLK_DBG_RATIO 0x1
+#define ATB_RATIO 0x3
+#define PERIPH_RATIO 0x3
+#define COREM1_RATIO 0x7
+#define COREM0_RATIO 0x3
+#define CORE_RATIO 0x0
+#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
+ | (PCLK_DBG_RATIO << 20) \
+ | (ATB_RATIO << 16) \
+ | (PERIPH_RATIO << 12) \
+ | (COREM1_RATIO << 8) \
+ | (COREM0_RATIO << 4) \
+ | (CORE_RATIO << 0))
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO 0x0
+#define COPY_RATIO 0x3
+#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO))
+
+/* CLK_DIV_DMC0 */
+#define CORE_TIMERS_RATIO 0x1
+#define COPY2_RATIO 0x3
+#define DMCP_RATIO 0x1
+#define DMCD_RATIO 0x1
+#define DMC_RATIO 0x1
+#define DPHY_RATIO 0x1
+#define ACP_PCLK_RATIO 0x1
+#define ACP_RATIO 0x3
+#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
+ | (COPY2_RATIO << 24) \
+ | (DMCP_RATIO << 20) \
+ | (DMCD_RATIO << 16) \
+ | (DMC_RATIO << 12) \
+ | (DPHY_RATIO << 8) \
+ | (ACP_PCLK_RATIO << 4) \
+ | (ACP_RATIO << 0))
+
+/* CLK_DIV_DMC1 */
+#define DPM_RATIO 0x1
+#define DVSEM_RATIO 0x1
+#define PWI_RATIO 0x1
+#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
+ | (DVSEM_RATIO << 16) \
+ | (PWI_RATIO << 8))
+
+/* CLK_SRC_TOP0 */
+#define MUX_ONENAND_SEL_ACLK_133 0x0
+#define MUX_ONENAND_SEL_ACLK_160 0x1
+#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
+#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
+#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
+#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
+#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
+#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
+#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
+#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
+#define MUX_VPLL_SEL_FINPLL 0x0
+#define MUX_VPLL_SEL_FOUTVPLL 0x1
+#define MUX_EPLL_SEL_FINPLL 0x0
+#define MUX_EPLL_SEL_FOUTEPLL 0x1
+#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
+#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
+#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_160 << 28) \
+ | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
+ | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
+ | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
+ | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
+ | (MUX_VPLL_SEL_FOUTVPLL << 8) \
+ | (MUX_EPLL_SEL_FOUTEPLL << 4) \
+ | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
+
+/* CLK_DIV_TOP */
+#define ONENAND_RATIO 0x0
+#define ACLK_133_RATIO 0x5
+#define ACLK_160_RATIO 0x4
+#define ACLK_100_RATIO 0x7
+#define ACLK_200_RATIO 0x3
+#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
+ | (ACLK_133_RATIO << 12)\
+ | (ACLK_160_RATIO << 8) \
+ | (ACLK_100_RATIO << 4) \
+ | (ACLK_200_RATIO << 0))
+
+/* CLK_DIV_LEFTBUS */
+#define GPL_RATIO 0x1
+#define GDL_RATIO 0x3
+#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO))
+
+/* CLK_DIV_RIGHTBUS */
+#define GPR_RATIO 0x1
+#define GDR_RATIO 0x3
+#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO))
+
+/* CLK_SRS_FSYS: 6 = SCLKMPLL */
+#define SATA_SEL_SCLKMPLL 0
+#define SATA_SEL_SCLKAPLL 1
+
+#define MMC_SEL_XXTI 0
+#define MMC_SEL_XUSBXTI 1
+#define MMC_SEL_SCLK_HDMI24M 2
+#define MMC_SEL_SCLK_USBPHY0 3
+#define MMC_SEL_SCLK_USBPHY1 4
+#define MMC_SEL_SCLK_HDMIPHY 5
+#define MMC_SEL_SCLKMPLL 6
+#define MMC_SEL_SCLKEPLL 7
+#define MMC_SEL_SCLKVPLL 8
+
+#define MMCC0_SEL MMC_SEL_SCLKMPLL
+#define MMCC1_SEL MMC_SEL_SCLKMPLL
+#define MMCC2_SEL MMC_SEL_SCLKMPLL
+#define MMCC3_SEL MMC_SEL_SCLKMPLL
+#define MMCC4_SEL MMC_SEL_SCLKMPLL
+#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
+ | (MMCC4_SEL << 16) \
+ | (MMCC3_SEL << 12) \
+ | (MMCC2_SEL << 8) \
+ | (MMCC1_SEL << 4) \
+ | (MMCC0_SEL << 0))
+
+/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
+/* CLK_DIV_FSYS1: 800(MPLL) / (15 + 1) */
+#define MMC0_RATIO 0xF
+#define MMC0_PRE_RATIO 0x0
+#define MMC1_RATIO 0xF
+#define MMC1_PRE_RATIO 0x0
+#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
+ | (MMC1_RATIO << 16) \
+ | (MMC0_PRE_RATIO << 8) \
+ | (MMC0_RATIO << 0))
+
+/* CLK_DIV_FSYS2: 800(MPLL) / (15 + 1) */
+#define MMC2_RATIO 0xF
+#define MMC2_PRE_RATIO 0x0
+#define MMC3_RATIO 0xF
+#define MMC3_PRE_RATIO 0x0
+#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
+ | (MMC3_RATIO << 16) \
+ | (MMC2_PRE_RATIO << 8) \
+ | (MMC2_RATIO << 0))
+
+/* CLK_DIV_FSYS3: 800(MPLL) / (15 + 1) */
+#define MMC4_RATIO 0xF
+#define MMC4_PRE_RATIO 0x0
+#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
+ | (MMC4_RATIO << 0))
+
+/* CLK_SRC_PERIL0 */
+#define UART_SEL_XXTI 0
+#define UART_SEL_XUSBXTI 1
+#define UART_SEL_SCLK_HDMI24M 2
+#define UART_SEL_SCLK_USBPHY0 3
+#define UART_SEL_SCLK_USBPHY1 4
+#define UART_SEL_SCLK_HDMIPHY 5
+#define UART_SEL_SCLKMPLL 6
+#define UART_SEL_SCLKEPLL 7
+#define UART_SEL_SCLKVPLL 8
+
+#define UART0_SEL UART_SEL_SCLKMPLL
+#define UART1_SEL UART_SEL_SCLKMPLL
+#define UART2_SEL UART_SEL_SCLKMPLL
+#define UART3_SEL UART_SEL_SCLKMPLL
+#define UART4_SEL UART_SEL_SCLKMPLL
+#define UART5_SEL UART_SEL_SCLKMPLL
+#define CLK_SRC_PERIL0_VAL ((UART5_SEL << 16) \
+ | (UART4_SEL << 12) \
+ | (UART3_SEL << 12) \
+ | (UART2_SEL << 8) \
+ | (UART1_SEL << 4) \
+ | (UART0_SEL << 0))
+
+/* SCLK_UART[0-4] = MOUTUART[0-4] / (UART[0-4]_RATIO + 1) */
+/* CLK_DIV_PERIL0 */
+#define UART0_RATIO 7
+#define UART1_RATIO 7
+#define UART2_RATIO 7
+#define UART3_RATIO 4
+#define UART4_RATIO 7
+#define UART5_RATIO 7
+#define CLK_DIV_PERIL0_VAL ((UART5_RATIO << 16) \
+ | (UART4_RATIO << 12) \
+ | (UART3_RATIO << 12) \
+ | (UART2_RATIO << 8) \
+ | (UART1_RATIO << 4) \
+ | (UART0_RATIO << 0))
+
+/* CLK_DIV_PERIL3 */
+#define SLIMBUS_RATIO 0x0
+#define PWM_RATIO 0x8
+#define CLK_DIV_PERIL3_VAL ((SLIMBUS_RATIO << 4) \
+ | (PWM_RATIO << 0))
+
+/* Required period to generate a stable clock output */
+/* PLL_LOCK_TIME */
+#define PLL_LOCKTIME 0x1C20
+
+/* PLL Values */
+#define DISABLE 0
+#define ENABLE 1
+#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
+ | (mdiv << 16) \
+ | (pdiv << 8) \
+ | (sdiv << 0))
+
+/* APLL_CON0: 800MHz */
+#define APLL_MDIV 0xC8
+#define APLL_PDIV 0x6
+#define APLL_SDIV 0x1
+#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
+
+/* APLL_CON1 */
+#define APLL_AFC_ENB 0x1
+#define APLL_AFC 0x1C
+#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
+
+/* MPLL_CON0: 800MHz */
+#define MPLL_MDIV 0xC8
+#define MPLL_PDIV 0x6
+#define MPLL_SDIV 0x1
+#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
+
+/* MPLL_CON1 */
+#define MPLL_AFC_ENB 0x1
+#define MPLL_AFC 0x1C
+#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
+
+/* EPLL_CON0: 96MHz */
+#define EPLL_MDIV 0x30
+#define EPLL_PDIV 0x3
+#define EPLL_SDIV 0x2
+#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
+
+/* EPLL_CON1 */
+#define EPLL_K 0x0
+#define EPLL_CON1_VAL (EPLL_K >> 0)
+
+/* VPLL_CON0: 108MHz */
+#define VPLL_MDIV 0x35
+#define VPLL_PDIV 0x3
+#define VPLL_SDIV 0x2
+#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
+
+/* VPLL_CON1 */
+#define VPLL_SSCG_EN DISABLE
+#define VPLL_SEL_PF_DN_SPREAD 0x0
+#define VPLL_MRR 0x11
+#define VPLL_MFR 0x0
+#define VPLL_K 0x400
+#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
+ | (VPLL_SEL_PF_DN_SPREAD << 29) \
+ | (VPLL_MRR << 24) \
+ | (VPLL_MFR << 16) \
+ | (VPLL_K << 0))
+
+/* CLOCK GATE */
+#define CLK_DIS 0x0
+#define CLK_EN 0x1
+
+#define BIT_CAM_CLK_PIXELASYNCM1 18
+#define BIT_CAM_CLK_PIXELASYNCM0 17
+#define BIT_CAM_CLK_PPMUCAMIF 16
+#define BIT_CAM_CLK_QEFIMC3 15
+#define BIT_CAM_CLK_QEFIMC2 14
+#define BIT_CAM_CLK_QEFIMC1 13
+#define BIT_CAM_CLK_QEFIMC0 12
+#define BIT_CAM_CLK_SMMUJPEG 11
+#define BIT_CAM_CLK_SMMUFIMC3 10
+#define BIT_CAM_CLK_SMMUFIMC2 9
+#define BIT_CAM_CLK_SMMUFIMC1 8
+#define BIT_CAM_CLK_SMMUFIMC0 7
+#define BIT_CAM_CLK_JPEG 6
+#define BIT_CAM_CLK_CSIS1 5
+#define BIT_CAM_CLK_CSIS0 4
+#define BIT_CAM_CLK_FIMC3 3
+#define BIT_CAM_CLK_FIMC2 2
+#define BIT_CAM_CLK_FIMC1 1
+#define BIT_CAM_CLK_FIMC0 0
+#define CLK_GATE_IP_CAM_ALL_EN ((CLK_EN << BIT_CAM_CLK_PIXELASYNCM1)\
+ | (CLK_EN << BIT_CAM_CLK_PIXELASYNCM0)\
+ | (CLK_EN << BIT_CAM_CLK_PPMUCAMIF)\
+ | (CLK_EN << BIT_CAM_CLK_QEFIMC3)\
+ | (CLK_EN << BIT_CAM_CLK_QEFIMC2)\
+ | (CLK_EN << BIT_CAM_CLK_QEFIMC1)\
+ | (CLK_EN << BIT_CAM_CLK_QEFIMC0)\
+ | (CLK_EN << BIT_CAM_CLK_SMMUJPEG)\
+ | (CLK_EN << BIT_CAM_CLK_SMMUFIMC3)\
+ | (CLK_EN << BIT_CAM_CLK_SMMUFIMC2)\
+ | (CLK_EN << BIT_CAM_CLK_SMMUFIMC1)\
+ | (CLK_EN << BIT_CAM_CLK_SMMUFIMC0)\
+ | (CLK_EN << BIT_CAM_CLK_JPEG)\
+ | (CLK_EN << BIT_CAM_CLK_CSIS1)\
+ | (CLK_EN << BIT_CAM_CLK_CSIS0)\
+ | (CLK_EN << BIT_CAM_CLK_FIMC3)\
+ | (CLK_EN << BIT_CAM_CLK_FIMC2)\
+ | (CLK_EN << BIT_CAM_CLK_FIMC1)\
+ | (CLK_EN << BIT_CAM_CLK_FIMC0))
+#define CLK_GATE_IP_CAM_ALL_DIS ~CLK_GATE_IP_CAM_ALL_EN
+
+#define BIT_VP_CLK_PPMUTV 5
+#define BIT_VP_CLK_SMMUTV 4
+#define BIT_VP_CLK_HDMI 3
+#define BIT_VP_CLK_TVENC 2
+#define BIT_VP_CLK_MIXER 1
+#define BIT_VP_CLK_VP 0
+#define CLK_GATE_IP_VP_ALL_EN ((CLK_EN << BIT_VP_CLK_PPMUTV)\
+ | (CLK_EN << BIT_VP_CLK_SMMUTV)\
+ | (CLK_EN << BIT_VP_CLK_HDMI)\
+ | (CLK_EN << BIT_VP_CLK_TVENC)\
+ | (CLK_EN << BIT_VP_CLK_MIXER)\
+ | (CLK_EN << BIT_VP_CLK_VP))
+#define CLK_GATE_IP_VP_ALL_DIS ~CLK_GATE_IP_VP_ALL_EN
+
+#define BIT_MFC_CLK_PPMUMFC_R 4
+#define BIT_MFC_CLK_PPMUMFC_L 3
+#define BIT_MFC_CLK_SMMUMFC_R 2
+#define BIT_MFC_CLK_SMMUMFC_L 1
+#define BIT_MFC_CLK_MFC 0
+#define CLK_GATE_IP_MFC_ALL_EN ((CLK_EN << BIT_MFC_CLK_PPMUMFC_R)\
+ | (CLK_EN << BIT_MFC_CLK_PPMUMFC_L)\
+ | (CLK_EN << BIT_MFC_CLK_SMMUMFC_R)\
+ | (CLK_EN << BIT_MFC_CLK_SMMUMFC_L)\
+ | (CLK_EN << BIT_MFC_CLK_MFC))
+#define CLK_GATE_IP_MFC_ALL_DIS ~CLK_GATE_IP_MFC_ALL_EN
+
+#define BIT_G3D_CLK_QEG3D 2
+#define BIT_G3D_CLK_PPMUG3D 1
+#define BIT_G3D_CLK_G3D 0
+#define CLK_GATE_IP_G3D_ALL_EN ((CLK_EN << BIT_G3D_CLK_QEG3D)\
+ | (CLK_EN << BIT_G3D_CLK_PPMUG3D)\
+ | (CLK_EN << BIT_G3D_CLK_G3D))
+#define CLK_GATE_IP_G3D_ALL_DIS ~CLK_GATE_IP_G3D_ALL_EN
+
+#define BIT_IMAGE_CLK_PPMUIMAGE 9
+#define BIT_IMAGE_CLK_QEMDMA 8
+#define BIT_IMAGE_CLK_QEROTATOR 7
+#define BIT_IMAGE_CLK_QEG2D 6
+#define BIT_IMAGE_CLK_SMMUMDMA 5
+#define BIT_IMAGE_CLK_SMMUROTATOR 4
+#define BIT_IMAGE_CLK_SMMUG2D 3
+#define BIT_IMAGE_CLK_MDMA 2
+#define BIT_IMAGE_CLK_ROTATOR 1
+#define BIT_IMAGE_CLK_G2D 0
+#define CLK_GATE_IP_IMAGE_ALL_EN ((CLK_EN << BIT_IMAGE_CLK_PPMUIMAGE)\
+ | (CLK_EN << BIT_IMAGE_CLK_QEMDMA)\
+ | (CLK_EN << BIT_IMAGE_CLK_QEROTATOR)\
+ | (CLK_EN << BIT_IMAGE_CLK_QEG2D)\
+ | (CLK_EN << BIT_IMAGE_CLK_SMMUMDMA)\
+ | (CLK_EN << BIT_IMAGE_CLK_SMMUROTATOR)\
+ | (CLK_EN << BIT_IMAGE_CLK_SMMUG2D)\
+ | (CLK_EN << BIT_IMAGE_CLK_MDMA)\
+ | (CLK_EN << BIT_IMAGE_CLK_ROTATOR)\
+ | (CLK_EN << BIT_IMAGE_CLK_G2D))
+#define CLK_GATE_IP_IMAGE_ALL_DIS ~CLK_GATE_IP_IMAGE_ALL_EN
+
+#define BIT_LCD0_CLK_PPMULCD0 5
+#define BIT_LCD0_CLK_SMMUFIMD0 4
+#define BIT_LCD0_CLK_DSIM0 3
+#define BIT_LCD0_CLK_MDNIE0 2
+#define BIT_LCD0_CLK_MIE0 1
+#define BIT_LCD0_CLK_FIMD0 0
+#define CLK_GATE_IP_LCD0_ALL_EN ((CLK_EN << BIT_LCD0_CLK_PPMULCD0)\
+ | (CLK_EN << BIT_LCD0_CLK_SMMUFIMD0)\
+ | (CLK_EN << BIT_LCD0_CLK_DSIM0)\
+ | (CLK_EN << BIT_LCD0_CLK_MDNIE0)\
+ | (CLK_EN << BIT_LCD0_CLK_MIE0)\
+ | (CLK_EN << BIT_LCD0_CLK_FIMD0))
+#define CLK_GATE_IP_LCD0_ALL_DIS ~CLK_GATE_IP_LCD0_ALL_EN
+
+#define BIT_LCD1_CLK_PPMULCD1 5
+#define BIT_LCD1_CLK_SMMUFIMD1 4
+#define BIT_LCD1_CLK_DSIM1 3
+#define BIT_LCD1_CLK_MDNIE1 2
+#define BIT_LCD1_CLK_MIE1 1
+#define BIT_LCD1_CLK_FIMD1 0
+#define CLK_GATE_IP_LCD1_ALL_EN ((CLK_EN << BIT_LCD1_CLK_PPMULCD1)\
+ | (CLK_EN << BIT_LCD1_CLK_SMMUFIMD1)\
+ | (CLK_EN << BIT_LCD1_CLK_DSIM1)\
+ | (CLK_EN << BIT_LCD1_CLK_MDNIE1)\
+ | (CLK_EN << BIT_LCD1_CLK_MIE1)\
+ | (CLK_EN << BIT_LCD1_CLK_FIMD1))
+#define CLK_GATE_IP_LCD1_ALL_DIS ~CLK_GATE_IP_LCD1_ALL_EN
+
+#define BIT_FSYS_CLK_SMMUPCIE 18
+#define BIT_FSYS_CLK_PPMUFILE 17
+#define BIT_FSYS_CLK_NFCON 16
+#define BIT_FSYS_CLK_ONENAND 15
+#define BIT_FSYS_CLK_PCIE 14
+#define BIT_FSYS_CLK_USBDEVICE 13
+#define BIT_FSYS_CLK_USBHOST 12
+#define BIT_FSYS_CLK_SROMC 11
+#define BIT_FSYS_CLK_SATA 10
+#define BIT_FSYS_CLK_SDMMC4 9
+#define BIT_FSYS_CLK_SDMMC3 8
+#define BIT_FSYS_CLK_SDMMC2 7
+#define BIT_FSYS_CLK_SDMMC1 6
+#define BIT_FSYS_CLK_SDMMC0 5
+#define BIT_FSYS_CLK_TSI 4
+#define BIT_FSYS_CLK_SATAPHY 3
+#define BIT_FSYS_CLK_PCIEPHY 2
+#define BIT_FSYS_CLK_PDMA1 1
+#define BIT_FSYS_CLK_PDMA0 0
+#define CLK_GATE_IP_FSYS_ALL_EN ((CLK_EN << BIT_FSYS_CLK_SMMUPCIE)\
+ | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
+ | (CLK_EN << BIT_FSYS_CLK_NFCON)\
+ | (CLK_EN << BIT_FSYS_CLK_ONENAND)\
+ | (CLK_EN << BIT_FSYS_CLK_PCIE)\
+ | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
+ | (CLK_EN << BIT_FSYS_CLK_USBHOST)\
+ | (CLK_EN << BIT_FSYS_CLK_SROMC)\
+ | (CLK_EN << BIT_FSYS_CLK_SATA)\
+ | (CLK_EN << BIT_FSYS_CLK_SDMMC4)\
+ | (CLK_EN << BIT_FSYS_CLK_SDMMC3)\
+ | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
+ | (CLK_EN << BIT_FSYS_CLK_SDMMC1)\
+ | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
+ | (CLK_EN << BIT_FSYS_CLK_TSI)\
+ | (CLK_EN << BIT_FSYS_CLK_SATAPHY)\
+ | (CLK_EN << BIT_FSYS_CLK_PCIEPHY)\
+ | (CLK_EN << BIT_FSYS_CLK_PDMA1)\
+ | (CLK_EN << BIT_FSYS_CLK_PDMA0))
+#define CLK_GATE_IP_FSYS_ALL_DIS ~CLK_GATE_IP_FSYS_ALL_EN
+
+#define BIT_GPS_CLK_SMMUGPS 1
+#define BIT_GPS_CLK_GPS 0
+#define CLK_GATE_IP_GPS_ALL_EN ((CLK_EN << BIT_GPS_CLK_SMMUGPS)\
+ | (CLK_EN << BIT_GPS_CLK_GPS))
+#define CLK_GATE_IP_GPS_ALL_DIS ~CLK_GATE_IP_GPS_ALL_EN
+
+#define BIT_PERIL_CLK_MODEMIF 28
+#define BIT_PERIL_CLK_AC97 27
+#define BIT_PERIL_CLK_SPDIF 26
+#define BIT_PERIL_CLK_SLIMBUS 25
+#define BIT_PERIL_CLK_PWM 24
+#define BIT_PERIL_CLK_PCM2 23
+#define BIT_PERIL_CLK_PCM1 22
+#define BIT_PERIL_CLK_I2S2 21
+#define BIT_PERIL_CLK_I2S1 20
+#define BIT_PERIL_CLK_RESERVED0 19
+#define BIT_PERIL_CLK_SPI2 18
+#define BIT_PERIL_CLK_SPI1 17
+#define BIT_PERIL_CLK_SPI0 16
+#define BIT_PERIL_CLK_TSADC 15
+#define BIT_PERIL_CLK_I2CHDMI 14
+#define BIT_PERIL_CLK_I2C7 13
+#define BIT_PERIL_CLK_I2C6 12
+#define BIT_PERIL_CLK_I2C5 11
+#define BIT_PERIL_CLK_I2C4 10
+#define BIT_PERIL_CLK_I2C3 9
+#define BIT_PERIL_CLK_I2C2 8
+#define BIT_PERIL_CLK_I2C1 7
+#define BIT_PERIL_CLK_I2C0 6
+#define BIT_PERIL_CLK_RESERVED1 5
+#define BIT_PERIL_CLK_UART4 4
+#define BIT_PERIL_CLK_UART3 3
+#define BIT_PERIL_CLK_UART2 2
+#define BIT_PERIL_CLK_UART1 1
+#define BIT_PERIL_CLK_UART0 0
+#define CLK_GATE_IP_PERIL_ALL_EN ((CLK_EN << BIT_PERIL_CLK_MODEMIF)\
+ | (CLK_EN << BIT_PERIL_CLK_AC97)\
+ | (CLK_EN << BIT_PERIL_CLK_SPDIF)\
+ | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)\
+ | (CLK_EN << BIT_PERIL_CLK_PWM)\
+ | (CLK_EN << BIT_PERIL_CLK_PCM2)\
+ | (CLK_EN << BIT_PERIL_CLK_PCM1)\
+ | (CLK_EN << BIT_PERIL_CLK_I2S2)\
+ | (CLK_EN << BIT_PERIL_CLK_I2S1)\
+ | (CLK_EN << BIT_PERIL_CLK_RESERVED0)\
+ | (CLK_EN << BIT_PERIL_CLK_SPI2)\
+ | (CLK_EN << BIT_PERIL_CLK_SPI1)\
+ | (CLK_EN << BIT_PERIL_CLK_SPI0)\
+ | (CLK_EN << BIT_PERIL_CLK_TSADC)\
+ | (CLK_EN << BIT_PERIL_CLK_I2CHDMI)\
+ | (CLK_EN << BIT_PERIL_CLK_I2C7)\
+ | (CLK_EN << BIT_PERIL_CLK_I2C6)\
+ | (CLK_EN << BIT_PERIL_CLK_I2C5)\
+ | (CLK_EN << BIT_PERIL_CLK_I2C4)\
+ | (CLK_EN << BIT_PERIL_CLK_I2C3)\
+ | (CLK_EN << BIT_PERIL_CLK_I2C2)\
+ | (CLK_EN << BIT_PERIL_CLK_I2C1)\
+ | (CLK_EN << BIT_PERIL_CLK_I2C0)\
+ | (CLK_EN << BIT_PERIL_CLK_RESERVED1)\
+ | (CLK_EN << BIT_PERIL_CLK_UART4)\
+ | (CLK_EN << BIT_PERIL_CLK_UART3)\
+ | (CLK_EN << BIT_PERIL_CLK_UART2)\
+ | (CLK_EN << BIT_PERIL_CLK_UART1)\
+ | (CLK_EN << BIT_PERIL_CLK_UART0))
+#define CLK_GATE_IP_PERIL_ALL_DIS ~CLK_GATE_IP_PERIL_ALL_EN
+
+#define BIT_PERIR_CLK_TMU_APBIF 17
+#define BIT_PERIR_CLK_KEYIF 16
+#define BIT_PERIR_CLK_RTC 15
+#define BIT_PERIR_CLK_WDT 14
+#define BIT_PERIR_CLK_MCT 13
+#define BIT_PERIR_CLK_SECKEY 12
+#define BIT_PERIR_CLK_HDMI_CEC 11
+#define BIT_PERIR_CLK_TZPC5 10
+#define BIT_PERIR_CLK_TZPC4 9
+#define BIT_PERIR_CLK_TZPC3 8
+#define BIT_PERIR_CLK_TZPC2 7
+#define BIT_PERIR_CLK_TZPC1 6
+#define BIT_PERIR_CLK_TZPC0 5
+#define BIT_PERIR_CLK_CMU_DMCPART 4
+#define BIT_PERIR_CLK_RESERVED 3
+#define BIT_PERIR_CLK_CMU_APBIF 2
+#define BIT_PERIR_CLK_SYSREG 1
+#define BIT_PERIR_CLK_CHIP_ID 0
+#define CLK_GATE_IP_PERIR_ALL_EN ((CLK_EN << BIT_PERIR_CLK_TMU_APBIF)\
+ | (CLK_EN << BIT_PERIR_CLK_KEYIF)\
+ | (CLK_EN << BIT_PERIR_CLK_RTC)\
+ | (CLK_EN << BIT_PERIR_CLK_WDT)\
+ | (CLK_EN << BIT_PERIR_CLK_MCT)\
+ | (CLK_EN << BIT_PERIR_CLK_SECKEY)\
+ | (CLK_EN << BIT_PERIR_CLK_HDMI_CEC)\
+ | (CLK_EN << BIT_PERIR_CLK_TZPC5)\
+ | (CLK_EN << BIT_PERIR_CLK_TZPC4)\
+ | (CLK_EN << BIT_PERIR_CLK_TZPC3)\
+ | (CLK_EN << BIT_PERIR_CLK_TZPC2)\
+ | (CLK_EN << BIT_PERIR_CLK_TZPC1)\
+ | (CLK_EN << BIT_PERIR_CLK_TZPC0)\
+ | (CLK_EN << BIT_PERIR_CLK_CMU_DMCPART)\
+ | (CLK_EN << BIT_PERIR_CLK_RESERVED)\
+ | (CLK_EN << BIT_PERIR_CLK_CMU_APBIF)\
+ | (CLK_EN << BIT_PERIR_CLK_SYSREG)\
+ | (CLK_EN << BIT_PERIR_CLK_CHIP_ID))
+#define CLK_GATE_IP_PERIR_ALL_DIS ~CLK_GATE_IP_PERIR_ALL_EN
+
+#define BIT_BLOCK_CLK_GPS 7
+#define BIT_BLOCK_CLK_RESERVED 6
+#define BIT_BLOCK_CLK_LCD1 5
+#define BIT_BLOCK_CLK_LCD0 4
+#define BIT_BLOCK_CLK_G3D 3
+#define BIT_BLOCK_CLK_MFC 2
+#define BIT_BLOCK_CLK_TV 1
+#define BIT_BLOCK_CLK_CAM 0
+#define CLK_GATE_BLOCK_ALL_EN ((CLK_EN << BIT_BLOCK_CLK_GPS)\
+ | (CLK_EN << BIT_BLOCK_CLK_RESERVED)\
+ | (CLK_EN << BIT_BLOCK_CLK_LCD1)\
+ | (CLK_EN << BIT_BLOCK_CLK_LCD0)\
+ | (CLK_EN << BIT_BLOCK_CLK_G3D)\
+ | (CLK_EN << BIT_BLOCK_CLK_MFC)\
+ | (CLK_EN << BIT_BLOCK_CLK_TV)\
+ | (CLK_EN << BIT_BLOCK_CLK_CAM))
+#define CLK_GATE_BLOCK_ALL_DIS ~CLK_GATE_BLOCK_ALL_EN
+
+/*
+ * GATE CAM : All block
+ * GATE VP : All block
+ * GATE MFC : All block
+ * GATE G3D : All block
+ * GATE IMAGE : All block
+ * GATE LCD0 : All block
+ * GATE LCD1 : All block
+ * GATE FSYS : Enable - PDMA0,1, SDMMC0,2, USBHOST, USBDEVICE, PPMUFILE
+ * GATE GPS : All block
+ * GATE PERI Left : All Enable, Block - SLIMBUS, SPDIF, AC97
+ * GATE PERI Right : All Enable, Block - KEYIF
+ * GATE Block : All block
+ */
+#define CLK_GATE_IP_CAM_VAL CLK_GATE_IP_CAM_ALL_DIS
+#define CLK_GATE_IP_VP_VAL CLK_GATE_IP_VP_ALL_DIS
+#define CLK_GATE_IP_MFC_VAL CLK_GATE_IP_MFC_ALL_DIS
+#define CLK_GATE_IP_G3D_VAL CLK_GATE_IP_G3D_ALL_DIS
+#define CLK_GATE_IP_IMAGE_VAL CLK_GATE_IP_IMAGE_ALL_DIS
+#define CLK_GATE_IP_LCD0_VAL CLK_GATE_IP_LCD0_ALL_DIS
+#define CLK_GATE_IP_LCD1_VAL CLK_GATE_IP_LCD1_ALL_DIS
+#define CLK_GATE_IP_FSYS_VAL (CLK_GATE_IP_FSYS_ALL_DIS \
+ | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
+ | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
+ | (CLK_EN << BIT_FSYS_CLK_USBHOST)\
+ | (CLK_EN << BIT_FSYS_CLK_SROMC)\
+ | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
+ | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
+ | (CLK_EN << BIT_FSYS_CLK_PDMA1)\
+ | (CLK_EN << BIT_FSYS_CLK_PDMA0))
+#define CLK_GATE_IP_GPS_VAL CLK_GATE_IP_GPS_ALL_DIS
+#define CLK_GATE_IP_PERIL_VAL (CLK_GATE_IP_PERIL_ALL_DIS \
+ | ~((CLK_EN << BIT_PERIL_CLK_AC97)\
+ | (CLK_EN << BIT_PERIL_CLK_SPDIF)\
+ | (CLK_EN << BIT_PERIL_CLK_I2C2)\
+ | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)))
+#define CLK_GATE_IP_PERIR_VAL (CLK_GATE_IP_PERIR_ALL_DIS \
+ | ~((CLK_EN << BIT_PERIR_CLK_KEYIF)))
+#define CLK_GATE_BLOCK_VAL CLK_GATE_BLOCK_ALL_DIS
+
+/* PS_HOLD: Data Hight, Output En */
+#define BIT_DAT 8
+#define BIT_EN 9
+#define EXYNOS4_PS_HOLD_CON_VAL (0x1 << BIT_DAT | 0x1 << BIT_EN)
+
+#endif
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
new file mode 100644
index 0000000..e163e45
--- /dev/null
+++ b/board/samsung/trats/trats.c
@@ -0,0 +1,608 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mipi_dsim.h>
+#include <asm/arch/watchdog.h>
+#include <asm/arch/power.h>
+#include <power/pmic.h>
+#include <usb/s3c_udc.h>
+#include <power/max8997_pmic.h>
+#include <power/max8997_muic.h>
+#include <power/battery.h>
+#include <power/max17042_fg.h>
+#include <libtizen.h>
+#include <usb.h>
+#include <usb_mass_storage.h>
+
+#include "setup.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int board_rev;
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+ return board_rev;
+}
+#endif
+
+static void check_hw_revision(void);
+struct s3c_plat_otg_data s5pc210_otg_data;
+
+int exynos_init(void)
+{
+ check_hw_revision();
+ printf("HW Revision:\t0x%x\n", board_rev);
+
+ return 0;
+}
+
+void i2c_init_board(void)
+{
+ int err;
+
+ /* I2C_5 -> PMIC */
+ err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("I2C%d not configured\n", (I2C_5));
+ return;
+ }
+
+ /* I2C_8 -> FG */
+ gpio_request(EXYNOS4_GPIO_Y40, "i2c_clk");
+ gpio_request(EXYNOS4_GPIO_Y41, "i2c_data");
+ gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
+ gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
+}
+
+static void trats_low_power_mode(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ struct exynos4_power *pwr =
+ (struct exynos4_power *)samsung_get_base_power();
+
+ /* Power down CORE1 */
+ /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
+ writel(0x0, &pwr->arm_core1_configuration);
+
+ /* Change the APLL frequency */
+ /* ENABLE (1 enable) | LOCKED (1 locked) */
+ /* [31] | [29] */
+ /* FSEL | MDIV | PDIV | SDIV */
+ /* [27] | [25:16] | [13:8] | [2:0] */
+ writel(0xa0c80604, &clk->apll_con0);
+
+ /* Change CPU0 clock divider */
+ /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
+ /* [30:28] | [26:24] | [22:20] | [18:16] */
+ /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
+ /* [14:12] | [10:8] | [6:4] | [2:0] */
+ writel(0x00000100, &clk->div_cpu0);
+
+ /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
+ while (readl(&clk->div_stat_cpu0) & 0x1111111)
+ continue;
+
+ /* Change clock divider ratio for DMC */
+ /* DMCP_RATIO | DMCD_RATIO */
+ /* [22:20] | [18:16] */
+ /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
+ /* [14:12] | [10:8] | [6:4] | [2:0] */
+ writel(0x13113117, &clk->div_dmc0);
+
+ /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
+ while (readl(&clk->div_stat_dmc0) & 0x11111111)
+ continue;
+
+ /* Turn off unnecessary power domains */
+ writel(0x0, &pwr->xxti_configuration); /* XXTI */
+ writel(0x0, &pwr->cam_configuration); /* CAM */
+ writel(0x0, &pwr->tv_configuration); /* TV */
+ writel(0x0, &pwr->mfc_configuration); /* MFC */
+ writel(0x0, &pwr->g3d_configuration); /* G3D */
+ writel(0x0, &pwr->gps_configuration); /* GPS */
+ writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
+
+ /* Turn off unnecessary clocks */
+ writel(0x0, &clk->gate_ip_cam); /* CAM */
+ writel(0x0, &clk->gate_ip_tv); /* TV */
+ writel(0x0, &clk->gate_ip_mfc); /* MFC */
+ writel(0x0, &clk->gate_ip_g3d); /* G3D */
+ writel(0x0, &clk->gate_ip_image); /* IMAGE */
+ writel(0x0, &clk->gate_ip_gps); /* GPS */
+}
+
+static int pmic_init_max8997(void)
+{
+ struct pmic *p = pmic_get("MAX8997_PMIC");
+ int i = 0, ret = 0;
+ u32 val;
+
+ if (pmic_probe(p))
+ return -1;
+
+ /* BUCK1 VARM: 1.2V */
+ val = (1200000 - 650000) / 25000;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
+ val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
+
+ /* BUCK2 VINT: 1.1V */
+ val = (1100000 - 650000) / 25000;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
+ val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
+
+
+ /* BUCK3 G3D: 1.1V - OFF */
+ ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
+ val &= ~ENBUCK;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
+
+ val = (1100000 - 750000) / 50000;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
+
+ /* BUCK4 CAMISP: 1.2V - OFF */
+ ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
+ val &= ~ENBUCK;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
+
+ val = (1200000 - 650000) / 25000;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
+
+ /* BUCK5 VMEM: 1.2V */
+ val = (1200000 - 650000) / 25000;
+ for (i = 0; i < 8; i++)
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
+
+ val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
+
+ /* BUCK6 CAM AF: 2.8V */
+ /* No Voltage Setting Register */
+ /* GNSLCT 3.0X */
+ val = GNSLCT;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
+
+ /* BUCK7 VCC_SUB: 2.0V */
+ val = (2000000 - 750000) / 50000;
+ ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
+
+ /* LDO1 VADC: 3.3V */
+ val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
+
+ /* LDO1 Disable active discharging */
+ ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
+ val &= ~LDO_ADE;
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
+
+ /* LDO2 VALIVE: 1.1V */
+ val = max8997_reg_ldo(1100000) | EN_LDO;
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
+
+ /* LDO3 VUSB/MIPI: 1.1V */
+ val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
+
+ /* LDO4 VMIPI: 1.8V */
+ val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
+
+ /* LDO5 VHSIC: 1.2V */
+ val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
+
+ /* LDO6 VCC_1.8V_PDA: 1.8V */
+ val = max8997_reg_ldo(1800000) | EN_LDO;
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
+
+ /* LDO7 CAM_ISP: 1.8V */
+ val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
+
+ /* LDO8 VDAC/VUSB: 3.3V */
+ val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
+
+ /* LDO9 VCC_2.8V_PDA: 2.8V */
+ val = max8997_reg_ldo(2800000) | EN_LDO;
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
+
+ /* LDO10 VPLL: 1.1V */
+ val = max8997_reg_ldo(1100000) | EN_LDO;
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
+
+ /* LDO11 TOUCH: 2.8V */
+ val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
+
+ /* LDO12 VTCAM: 1.8V */
+ val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
+
+ /* LDO13 VCC_3.0_LCD: 3.0V */
+ val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
+
+ /* LDO14 MOTOR: 3.0V */
+ val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
+
+ /* LDO15 LED_A: 2.8V */
+ val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
+
+ /* LDO16 CAM_SENSOR: 1.8V */
+ val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
+
+ /* LDO17 VTF: 2.8V */
+ val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
+
+ /* LDO18 TOUCH_LED 3.3V */
+ val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
+
+ /* LDO21 VDDQ: 1.2V */
+ val = max8997_reg_ldo(1200000) | EN_LDO;
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
+
+ /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
+ val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
+ ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
+ ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
+
+ if (ret) {
+ puts("MAX8997 PMIC setting error!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int exynos_power_init(void)
+{
+ int chrg, ret;
+ struct power_battery *pb;
+ struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
+
+ /*
+ * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
+ * to logical I2C adapter 0
+ *
+ * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
+ * to logical I2C adapter 1
+ */
+ ret = pmic_init(I2C_5);
+ ret |= pmic_init_max8997();
+ ret |= power_fg_init(I2C_9);
+ ret |= power_muic_init(I2C_5);
+ ret |= power_bat_init(0);
+ if (ret)
+ return ret;
+
+ p_fg = pmic_get("MAX17042_FG");
+ if (!p_fg) {
+ puts("MAX17042_FG: Not found\n");
+ return -ENODEV;
+ }
+
+ p_chrg = pmic_get("MAX8997_PMIC");
+ if (!p_chrg) {
+ puts("MAX8997_PMIC: Not found\n");
+ return -ENODEV;
+ }
+
+ p_muic = pmic_get("MAX8997_MUIC");
+ if (!p_muic) {
+ puts("MAX8997_MUIC: Not found\n");
+ return -ENODEV;
+ }
+
+ p_bat = pmic_get("BAT_TRATS");
+ if (!p_bat) {
+ puts("BAT_TRATS: Not found\n");
+ return -ENODEV;
+ }
+
+ p_fg->parent = p_bat;
+ p_chrg->parent = p_bat;
+ p_muic->parent = p_bat;
+
+ p_bat->low_power_mode = trats_low_power_mode;
+ p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
+
+ pb = p_bat->pbat;
+ chrg = p_muic->chrg->chrg_type(p_muic);
+ debug("CHARGER TYPE: %d\n", chrg);
+
+ if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
+ puts("No battery detected\n");
+ return 0;
+ }
+
+ p_fg->fg->fg_battery_check(p_fg, p_bat);
+
+ if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
+ puts("CHARGE Battery !\n");
+
+ return 0;
+}
+
+static unsigned int get_hw_revision(void)
+{
+ int hwrev = 0;
+ char str[10];
+ int i;
+
+ /* hw_rev[3:0] == GPE1[3:0] */
+ for (i = 0; i < 4; i++) {
+ int pin = i + EXYNOS4_GPIO_E10;
+
+ sprintf(str, "hw_rev%d", i);
+ gpio_request(pin, str);
+ gpio_cfg_pin(pin, S5P_GPIO_INPUT);
+ gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
+ }
+
+ udelay(1);
+
+ for (i = 0; i < 4; i++)
+ hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);
+
+ debug("hwrev 0x%x\n", hwrev);
+
+ return hwrev;
+}
+
+static void check_hw_revision(void)
+{
+ int hwrev;
+
+ hwrev = get_hw_revision();
+
+ board_rev |= hwrev;
+}
+
+
+#ifdef CONFIG_USB_GADGET
+static int s5pc210_phy_control(int on)
+{
+ int ret = 0;
+ u32 val = 0;
+ struct pmic *p = pmic_get("MAX8997_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return -1;
+
+ if (on) {
+ ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
+ ENSAFEOUT1, LDO_ON);
+ ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
+
+ ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
+ } else {
+ ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
+
+ ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
+ ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
+ ENSAFEOUT1, LDO_OFF);
+ }
+
+ if (ret) {
+ puts("MAX8997 LDO setting error!\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+struct s3c_plat_otg_data s5pc210_otg_data = {
+ .phy_control = s5pc210_phy_control,
+ .regs_phy = EXYNOS4_USBPHY_BASE,
+ .regs_otg = EXYNOS4_USBOTG_BASE,
+ .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
+ .usb_flags = PHY0_SLEEP,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ debug("USB_udc_probe\n");
+ return s3c_udc_probe(&s5pc210_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+ struct pmic *muic = pmic_get("MAX8997_MUIC");
+ if (!muic)
+ return 0;
+
+ return !!muic->chrg->chrg_type(muic);
+}
+#endif
+
+static void pmic_reset(void)
+{
+ gpio_direction_output(EXYNOS4_GPIO_X07, 1);
+ gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
+}
+
+static void board_clock_init(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+
+ writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
+ writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
+ writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
+ writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
+
+ writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
+ writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
+ writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
+ writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
+ writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
+ writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
+ writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
+ writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
+ writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
+ writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
+ writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
+ writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
+
+ writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
+ writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
+ writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
+ writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
+ writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
+ writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
+ writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
+ writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
+ writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
+ writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
+ writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
+ writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
+
+ writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
+ writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
+ writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
+ writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
+ writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
+ writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
+ writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
+ writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
+ writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
+ writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
+ writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
+ writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
+}
+
+static void board_power_init(void)
+{
+ struct exynos4_power *pwr =
+ (struct exynos4_power *)samsung_get_base_power();
+
+ /* PS HOLD */
+ writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
+
+ /* Set power down */
+ writel(0, (unsigned int)&pwr->cam_configuration);
+ writel(0, (unsigned int)&pwr->tv_configuration);
+ writel(0, (unsigned int)&pwr->mfc_configuration);
+ writel(0, (unsigned int)&pwr->g3d_configuration);
+ writel(0, (unsigned int)&pwr->lcd1_configuration);
+ writel(0, (unsigned int)&pwr->gps_configuration);
+ writel(0, (unsigned int)&pwr->gps_alive_configuration);
+
+ /* It is necessary to power down core 1 */
+ /* to successfully boot CPU1 in kernel */
+ writel(0, (unsigned int)&pwr->arm_core1_configuration);
+}
+
+static void exynos_uart_init(void)
+{
+ /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
+ gpio_request(EXYNOS4_GPIO_Y47, "uart_sel");
+ gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
+ gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
+}
+
+int exynos_early_init_f(void)
+{
+ wdt_stop();
+ pmic_reset();
+ board_clock_init();
+ exynos_uart_init();
+ board_power_init();
+
+ return 0;
+}
+
+void exynos_reset_lcd(void)
+{
+ gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
+ gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
+ udelay(10000);
+ gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
+ udelay(10000);
+ gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
+}
+
+int lcd_power(void)
+{
+ int ret = 0;
+ struct pmic *p = pmic_get("MAX8997_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return 0;
+
+ /* LDO15 voltage: 2.2v */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
+ /* LDO13 voltage: 3.0v */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
+
+ if (ret) {
+ puts("MAX8997 LDO setting error!\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+int mipi_power(void)
+{
+ int ret = 0;
+ struct pmic *p = pmic_get("MAX8997_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return 0;
+
+ /* LDO3 voltage: 1.1v */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
+ /* LDO4 voltage: 1.8v */
+ ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
+
+ if (ret) {
+ puts("MAX8997 LDO setting error!\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+void exynos_lcd_misc_init(vidinfo_t *vid)
+{
+#ifdef CONFIG_TIZEN
+ get_tizen_logo_info(vid);
+#endif
+#ifdef CONFIG_S6E8AX0
+ s6e8ax0_init();
+ setenv("lcdinfo", "lcd=s6e8ax0");
+#endif
+}
diff --git a/board/samsung/trats2/Kconfig b/board/samsung/trats2/Kconfig
new file mode 100644
index 0000000..5670e14
--- /dev/null
+++ b/board/samsung/trats2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TRATS2
+
+config SYS_BOARD
+ default "trats2"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "trats2"
+
+endif
diff --git a/board/samsung/trats2/MAINTAINERS b/board/samsung/trats2/MAINTAINERS
new file mode 100644
index 0000000..7018300
--- /dev/null
+++ b/board/samsung/trats2/MAINTAINERS
@@ -0,0 +1,6 @@
+TRATS2 BOARD
+M: Lukasz Majewski <l.majewski@samsung.com>
+S: Maintained
+F: board/samsung/trats2/
+F: include/configs/trats2.h
+F: configs/trats2_defconfig
diff --git a/board/samsung/trats2/Makefile b/board/samsung/trats2/Makefile
new file mode 100644
index 0000000..f501761
--- /dev/null
+++ b/board/samsung/trats2/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2000 - 2013 Samsung Electronics Co., Ltd. All rights reserved.
+# Sanghee Kim <sh0130.kim@samsung.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := trats2.o
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
new file mode 100644
index 0000000..a737749
--- /dev/null
+++ b/board/samsung/trats2/trats2.c
@@ -0,0 +1,433 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved.
+ * Sanghee Kim <sh0130.kim@samsung.com>
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/mipi_dsim.h>
+#include <power/pmic.h>
+#include <power/max77686_pmic.h>
+#include <power/battery.h>
+#include <power/max77693_pmic.h>
+#include <power/max77693_muic.h>
+#include <power/max77693_fg.h>
+#include <libtizen.h>
+#include <errno.h>
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <usb_mass_storage.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static unsigned int board_rev = -1;
+
+static inline u32 get_model_rev(void);
+
+static void check_hw_revision(void)
+{
+ int modelrev = 0;
+ char str[12];
+ int i;
+
+ /*
+ * GPM1[1:0]: MODEL_REV[1:0]
+ * Don't set as pull-none for these N/C pin.
+ * TRM say that it may cause unexcepted state and leakage current.
+ * and pull-none is only for output function.
+ */
+ for (i = 0; i < 2; i++) {
+ int pin = i + EXYNOS4X12_GPIO_M10;
+
+ sprintf(str, "model_rev%d", i);
+ gpio_request(pin, str);
+ gpio_cfg_pin(pin, S5P_GPIO_INPUT);
+ }
+
+ /* GPM1[5:2]: HW_REV[3:0] */
+ for (i = 0; i < 4; i++) {
+ int pin = i + EXYNOS4X12_GPIO_M12;
+
+ sprintf(str, "hw_rev%d", i);
+ gpio_request(pin, str);
+ gpio_cfg_pin(pin, S5P_GPIO_INPUT);
+ gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
+ }
+
+ /* GPM1[1:0]: MODEL_REV[1:0] */
+ for (i = 0; i < 2; i++)
+ modelrev |= (gpio_get_value(EXYNOS4X12_GPIO_M10 + i) << i);
+
+ /* board_rev[15:8] = model */
+ board_rev = modelrev << 8;
+}
+
+u32 get_board_rev(void)
+{
+ return board_rev;
+}
+
+static inline u32 get_model_rev(void)
+{
+ return (board_rev >> 8) & 0xff;
+}
+
+static void board_external_gpio_init(void)
+{
+ /*
+ * some pins which in alive block are connected with external pull-up
+ * but it's default setting is pull-down.
+ * if that pin set as input then that floated
+ */
+
+ gpio_set_pull(EXYNOS4X12_GPIO_X02, S5P_GPIO_PULL_NONE); /* PS_ALS_INT */
+ gpio_set_pull(EXYNOS4X12_GPIO_X04, S5P_GPIO_PULL_NONE); /* TSP_nINT */
+ gpio_set_pull(EXYNOS4X12_GPIO_X07, S5P_GPIO_PULL_NONE); /* AP_PMIC_IRQ*/
+ gpio_set_pull(EXYNOS4X12_GPIO_X15, S5P_GPIO_PULL_NONE); /* IF_PMIC_IRQ*/
+ gpio_set_pull(EXYNOS4X12_GPIO_X20, S5P_GPIO_PULL_NONE); /* VOL_UP */
+ gpio_set_pull(EXYNOS4X12_GPIO_X21, S5P_GPIO_PULL_NONE); /* VOL_DOWN */
+ gpio_set_pull(EXYNOS4X12_GPIO_X23, S5P_GPIO_PULL_NONE); /* FUEL_ALERT */
+ gpio_set_pull(EXYNOS4X12_GPIO_X24, S5P_GPIO_PULL_NONE); /* ADC_INT */
+ gpio_set_pull(EXYNOS4X12_GPIO_X27, S5P_GPIO_PULL_NONE); /* nPOWER */
+ gpio_set_pull(EXYNOS4X12_GPIO_X30, S5P_GPIO_PULL_NONE); /* WPC_INT */
+ gpio_set_pull(EXYNOS4X12_GPIO_X35, S5P_GPIO_PULL_NONE); /* OK_KEY */
+ gpio_set_pull(EXYNOS4X12_GPIO_X37, S5P_GPIO_PULL_NONE); /* HDMI_HPD */
+}
+
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+static void board_init_i2c(void)
+{
+ int err;
+
+ /* I2C_7 */
+ err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
+ if (err) {
+ debug("I2C%d not configured\n", (I2C_7));
+ return;
+ }
+
+ /* I2C_8 */
+ gpio_request(EXYNOS4X12_GPIO_F14, "i2c8_clk");
+ gpio_request(EXYNOS4X12_GPIO_F15, "i2c8_data");
+ gpio_direction_output(EXYNOS4X12_GPIO_F14, 1);
+ gpio_direction_output(EXYNOS4X12_GPIO_F15, 1);
+
+ /* I2C_9 */
+ gpio_request(EXYNOS4X12_GPIO_M21, "i2c9_clk");
+ gpio_request(EXYNOS4X12_GPIO_M20, "i2c9_data");
+ gpio_direction_output(EXYNOS4X12_GPIO_M21, 1);
+ gpio_direction_output(EXYNOS4X12_GPIO_M20, 1);
+}
+#endif
+
+#ifdef CONFIG_SYS_I2C_SOFT
+int get_soft_i2c_scl_pin(void)
+{
+ if (I2C_ADAP_HWNR)
+ return EXYNOS4X12_GPIO_M21; /* I2C9 */
+ else
+ return EXYNOS4X12_GPIO_F14; /* I2C8 */
+}
+
+int get_soft_i2c_sda_pin(void)
+{
+ if (I2C_ADAP_HWNR)
+ return EXYNOS4X12_GPIO_M20; /* I2C9 */
+ else
+ return EXYNOS4X12_GPIO_F15; /* I2C8 */
+}
+#endif
+
+int exynos_early_init_f(void)
+{
+ board_external_gpio_init();
+
+ return 0;
+}
+
+static int pmic_init_max77686(void);
+
+int exynos_init(void)
+{
+ struct exynos4_power *pwr =
+ (struct exynos4_power *)samsung_get_base_power();
+
+ check_hw_revision();
+ printf("HW Revision:\t0x%04x\n", board_rev);
+
+ /*
+ * First bootloader on the TRATS2 platform uses
+ * INFORM4 and INFORM5 registers for recovery
+ *
+ * To indicate correct boot chain - those two
+ * registers must be cleared out
+ */
+ writel(0, &pwr->inform4);
+ writel(0, &pwr->inform5);
+
+ return 0;
+}
+
+int exynos_power_init(void)
+{
+ int chrg;
+ struct power_battery *pb;
+ struct pmic *p_chrg, *p_muic, *p_fg, *p_bat;
+
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+ board_init_i2c();
+#endif
+ pmic_init(I2C_7); /* I2C adapter 7 - bus name s3c24x0_7 */
+ pmic_init_max77686();
+ pmic_init_max77693(I2C_10); /* I2C adapter 10 - bus name soft1 */
+ power_muic_init(I2C_10); /* I2C adapter 10 - bus name soft1 */
+ power_fg_init(I2C_9); /* I2C adapter 9 - bus name soft0 */
+ power_bat_init(0);
+
+ p_chrg = pmic_get("MAX77693_PMIC");
+ if (!p_chrg) {
+ puts("MAX77693_PMIC: Not found\n");
+ return -ENODEV;
+ }
+
+ p_muic = pmic_get("MAX77693_MUIC");
+ if (!p_muic) {
+ puts("MAX77693_MUIC: Not found\n");
+ return -ENODEV;
+ }
+
+ p_fg = pmic_get("MAX77693_FG");
+ if (!p_fg) {
+ puts("MAX17042_FG: Not found\n");
+ return -ENODEV;
+ }
+
+ if (p_chrg->chrg->chrg_bat_present(p_chrg) == 0)
+ puts("No battery detected\n");
+
+ p_bat = pmic_get("BAT_TRATS2");
+ if (!p_bat) {
+ puts("BAT_TRATS2: Not found\n");
+ return -ENODEV;
+ }
+
+ p_fg->parent = p_bat;
+ p_chrg->parent = p_bat;
+ p_muic->parent = p_bat;
+
+ p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
+
+ pb = p_bat->pbat;
+ chrg = p_muic->chrg->chrg_type(p_muic);
+ debug("CHARGER TYPE: %d\n", chrg);
+
+ if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
+ puts("No battery detected\n");
+ return 0;
+ }
+
+ p_fg->fg->fg_battery_check(p_fg, p_bat);
+
+ if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
+ puts("CHARGE Battery !\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_GADGET
+static int s5pc210_phy_control(int on)
+{
+ int ret = 0;
+ unsigned int val;
+ struct pmic *p, *p_pmic, *p_muic;
+
+ p_pmic = pmic_get("MAX77686_PMIC");
+ if (!p_pmic)
+ return -ENODEV;
+
+ if (pmic_probe(p_pmic))
+ return -1;
+
+ p_muic = pmic_get("MAX77693_MUIC");
+ if (!p_muic)
+ return -ENODEV;
+
+ if (pmic_probe(p_muic))
+ return -1;
+
+ if (on) {
+ ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON);
+ if (ret)
+ return -1;
+
+ p = pmic_get("MAX77693_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return -1;
+
+ /* SAFEOUT */
+ ret = pmic_reg_read(p, MAX77693_SAFEOUT, &val);
+ if (ret)
+ return -1;
+
+ val |= MAX77693_ENSAFEOUT1;
+ ret = pmic_reg_write(p, MAX77693_SAFEOUT, val);
+ if (ret)
+ return -1;
+
+ /* PATH: USB */
+ ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1,
+ MAX77693_MUIC_CTRL1_DN1DP2);
+
+ } else {
+ ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM);
+ if (ret)
+ return -1;
+
+ /* PATH: UART */
+ ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1,
+ MAX77693_MUIC_CTRL1_UT1UR2);
+ }
+
+ if (ret)
+ return -1;
+
+ return 0;
+}
+
+struct s3c_plat_otg_data s5pc210_otg_data = {
+ .phy_control = s5pc210_phy_control,
+ .regs_phy = EXYNOS4X12_USBPHY_BASE,
+ .regs_otg = EXYNOS4X12_USBOTG_BASE,
+ .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
+ .usb_flags = PHY0_SLEEP,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ debug("USB_udc_probe\n");
+ return s3c_udc_probe(&s5pc210_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+ struct pmic *muic = pmic_get("MAX77693_MUIC");
+ if (!muic)
+ return 0;
+
+ return !!muic->chrg->chrg_type(muic);
+}
+#endif
+
+static int pmic_init_max77686(void)
+{
+ struct pmic *p = pmic_get("MAX77686_PMIC");
+
+ if (pmic_probe(p))
+ return -1;
+
+ /* BUCK/LDO Output Voltage */
+ max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 VTF_2.8V */
+ max77686_set_ldo_voltage(p, 23, 3300000); /* LDO23 TSP_AVDD_3.3V*/
+ max77686_set_ldo_voltage(p, 24, 1800000); /* LDO24 TSP_VDD_1.8V */
+
+ /* BUCK/LDO Output Mode */
+ max77686_set_buck_mode(p, 1, OPMODE_STANDBY); /* BUCK1 VMIF_1.1V_AP */
+ max77686_set_buck_mode(p, 2, OPMODE_ON); /* BUCK2 VARM_1.0V_AP */
+ max77686_set_buck_mode(p, 3, OPMODE_ON); /* BUCK3 VINT_1.0V_AP */
+ max77686_set_buck_mode(p, 4, OPMODE_ON); /* BUCK4 VG3D_1.0V_AP */
+ max77686_set_buck_mode(p, 5, OPMODE_ON); /* BUCK5 VMEM_1.2V_AP */
+ max77686_set_buck_mode(p, 6, OPMODE_ON); /* BUCK6 VCC_SUB_1.35V*/
+ max77686_set_buck_mode(p, 7, OPMODE_ON); /* BUCK7 VCC_SUB_2.0V */
+ max77686_set_buck_mode(p, 8, OPMODE_OFF); /* VMEM_VDDF_2.85V */
+ max77686_set_buck_mode(p, 9, OPMODE_OFF); /* CAM_ISP_CORE_1.2V*/
+
+ max77686_set_ldo_mode(p, 1, OPMODE_LPM); /* LDO1 VALIVE_1.0V_AP*/
+ max77686_set_ldo_mode(p, 2, OPMODE_STANDBY); /* LDO2 VM1M2_1.2V_AP */
+ max77686_set_ldo_mode(p, 3, OPMODE_LPM); /* LDO3 VCC_1.8V_AP */
+ max77686_set_ldo_mode(p, 4, OPMODE_LPM); /* LDO4 VCC_2.8V_AP */
+ max77686_set_ldo_mode(p, 5, OPMODE_OFF); /* LDO5_VCC_1.8V_IO */
+ max77686_set_ldo_mode(p, 6, OPMODE_STANDBY); /* LDO6 VMPLL_1.0V_AP */
+ max77686_set_ldo_mode(p, 7, OPMODE_STANDBY); /* LDO7 VPLL_1.0V_AP */
+ max77686_set_ldo_mode(p, 8, OPMODE_LPM); /* LDO8 VMIPI_1.0V_AP */
+ max77686_set_ldo_mode(p, 9, OPMODE_OFF); /* CAM_ISP_MIPI_1.2*/
+ max77686_set_ldo_mode(p, 10, OPMODE_LPM); /* LDO10 VMIPI_1.8V_AP*/
+ max77686_set_ldo_mode(p, 11, OPMODE_STANDBY); /* LDO11 VABB1_1.8V_AP*/
+ max77686_set_ldo_mode(p, 12, OPMODE_LPM); /* LDO12 VUOTG_3.0V_AP*/
+ max77686_set_ldo_mode(p, 13, OPMODE_OFF); /* LDO13 VC2C_1.8V_AP */
+ max77686_set_ldo_mode(p, 14, OPMODE_STANDBY); /* VABB02_1.8V_AP */
+ max77686_set_ldo_mode(p, 15, OPMODE_STANDBY); /* LDO15 VHSIC_1.0V_AP*/
+ max77686_set_ldo_mode(p, 16, OPMODE_STANDBY); /* LDO16 VHSIC_1.8V_AP*/
+ max77686_set_ldo_mode(p, 17, OPMODE_OFF); /* CAM_SENSOR_CORE_1.2*/
+ max77686_set_ldo_mode(p, 18, OPMODE_OFF); /* CAM_ISP_SEN_IO_1.8V*/
+ max77686_set_ldo_mode(p, 19, OPMODE_OFF); /* LDO19 VT_CAM_1.8V */
+ max77686_set_ldo_mode(p, 20, OPMODE_ON); /* LDO20 VDDQ_PRE_1.8V*/
+ max77686_set_ldo_mode(p, 21, OPMODE_OFF); /* LDO21 VTF_2.8V */
+ max77686_set_ldo_mode(p, 22, OPMODE_OFF); /* LDO22 VMEM_VDD_2.8V*/
+ max77686_set_ldo_mode(p, 23, OPMODE_OFF); /* LDO23 TSP_AVDD_3.3V*/
+ max77686_set_ldo_mode(p, 24, OPMODE_OFF); /* LDO24 TSP_VDD_1.8V */
+ max77686_set_ldo_mode(p, 25, OPMODE_OFF); /* LDO25 VCC_3.3V_LCD */
+ max77686_set_ldo_mode(p, 26, OPMODE_OFF); /*LDO26 VCC_3.0V_MOTOR*/
+
+ return 0;
+}
+
+/*
+ * LCD
+ */
+
+#ifdef CONFIG_LCD
+int mipi_power(void)
+{
+ struct pmic *p = pmic_get("MAX77686_PMIC");
+
+ /* LDO8 VMIPI_1.0V_AP */
+ max77686_set_ldo_mode(p, 8, OPMODE_ON);
+ /* LDO10 VMIPI_1.8V_AP */
+ max77686_set_ldo_mode(p, 10, OPMODE_ON);
+
+ return 0;
+}
+
+void exynos_lcd_power_on(void)
+{
+ struct pmic *p = pmic_get("MAX77686_PMIC");
+
+ /* LCD_2.2V_EN: GPC0[1] */
+ gpio_request(EXYNOS4X12_GPIO_C01, "lcd_2v2_en");
+ gpio_set_pull(EXYNOS4X12_GPIO_C01, S5P_GPIO_PULL_UP);
+ gpio_direction_output(EXYNOS4X12_GPIO_C01, 1);
+
+ /* LDO25 VCC_3.1V_LCD */
+ pmic_probe(p);
+ max77686_set_ldo_voltage(p, 25, 3100000);
+ max77686_set_ldo_mode(p, 25, OPMODE_LPM);
+}
+
+void exynos_reset_lcd(void)
+{
+ /* reset lcd */
+ gpio_request(EXYNOS4X12_GPIO_F21, "lcd_reset");
+ gpio_direction_output(EXYNOS4X12_GPIO_F21, 0);
+ udelay(10);
+ gpio_set_value(EXYNOS4X12_GPIO_F21, 1);
+}
+
+void exynos_lcd_misc_init(vidinfo_t *vid)
+{
+#ifdef CONFIG_TIZEN
+ get_tizen_logo_info(vid);
+#endif
+#ifdef CONFIG_S6E8AX0
+ s6e8ax0_init();
+#endif
+}
+#endif /* LCD */
diff --git a/board/samsung/universal_c210/Kconfig b/board/samsung/universal_c210/Kconfig
new file mode 100644
index 0000000..e692668
--- /dev/null
+++ b/board/samsung/universal_c210/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_S5PC210_UNIVERSAL
+
+config SYS_BOARD
+ default "universal_c210"
+
+config SYS_VENDOR
+ default "samsung"
+
+config SYS_CONFIG_NAME
+ default "s5pc210_universal"
+
+endif
diff --git a/board/samsung/universal_c210/MAINTAINERS b/board/samsung/universal_c210/MAINTAINERS
new file mode 100644
index 0000000..6760678
--- /dev/null
+++ b/board/samsung/universal_c210/MAINTAINERS
@@ -0,0 +1,6 @@
+UNIVERSAL_C210 BOARD
+M: Przemyslaw Marczak <p.marczak@samsung.com>
+S: Maintained
+F: board/samsung/universal_c210/
+F: include/configs/s5pc210_universal.h
+F: configs/s5pc210_universal_defconfig
diff --git a/board/samsung/universal_c210/Makefile b/board/samsung/universal_c210/Makefile
new file mode 100644
index 0000000..4ceeeb6
--- /dev/null
+++ b/board/samsung/universal_c210/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2010 Samsung Electronics
+# Minkyu Kang <mk7.kang@samsung.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := universal.o onenand.o
diff --git a/board/samsung/universal_c210/onenand.c b/board/samsung/universal_c210/onenand.c
new file mode 100644
index 0000000..28bc811
--- /dev/null
+++ b/board/samsung/universal_c210/onenand.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+
+ this->base = (void *)CONFIG_SYS_ONENAND_BASE;
+ this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
+ this->chip_probe = s5pc210_chip_probe;
+}
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
new file mode 100644
index 0000000..df46713
--- /dev/null
+++ b/board/samsung/universal_c210/universal.c
@@ -0,0 +1,381 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <lcd.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/adc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/watchdog.h>
+#include <ld9040.h>
+#include <power/pmic.h>
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <asm/arch/cpu.h>
+#include <power/max8998_pmic.h>
+#include <libtizen.h>
+#include <samsung/misc.h>
+#include <usb_mass_storage.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int board_rev;
+
+u32 get_board_rev(void)
+{
+ return board_rev;
+}
+
+static int get_hwrev(void)
+{
+ return board_rev & 0xFF;
+}
+
+static void init_pmic_lcd(void);
+
+int exynos_power_init(void)
+{
+ int ret;
+
+ /*
+ * For PMIC the I2C bus is named as I2C5, but it is connected
+ * to logical I2C adapter 0
+ */
+ ret = pmic_init(I2C_0);
+ if (ret)
+ return ret;
+
+ init_pmic_lcd();
+
+ return 0;
+}
+
+static unsigned short get_adc_value(int channel)
+{
+ struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
+ unsigned short ret = 0;
+ unsigned int reg;
+ unsigned int loop = 0;
+
+ writel(channel & 0xF, &adc->adcmux);
+ writel((1 << 14) | (49 << 6), &adc->adccon);
+ writel(1000 & 0xffff, &adc->adcdly);
+ writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */
+ udelay(10);
+ writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */
+ udelay(10);
+
+ do {
+ udelay(1);
+ reg = readl(&adc->adccon);
+ } while (!(reg & (1 << 15)) && (loop++ < 1000));
+
+ ret = readl(&adc->adcdat0) & 0xFFF;
+
+ return ret;
+}
+
+static int adc_power_control(int on)
+{
+ int ret;
+ struct pmic *p = pmic_get("MAX8998_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return -1;
+
+ ret = pmic_set_output(p,
+ MAX8998_REG_ONOFF1,
+ MAX8998_LDO4, !!on);
+
+ return ret;
+}
+
+static unsigned int get_hw_revision(void)
+{
+ int hwrev, mode0, mode1;
+
+ adc_power_control(1);
+
+ mode0 = get_adc_value(1); /* HWREV_MODE0 */
+ mode1 = get_adc_value(2); /* HWREV_MODE1 */
+
+ /*
+ * XXX Always set the default hwrev as the latest board
+ * ADC = (voltage) / 3.3 * 4096
+ */
+ hwrev = 3;
+
+#define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max))
+ if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200))
+ hwrev = 0x0; /* 0.01V 0.01V */
+ if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200))
+ hwrev = 0x1; /* 610mV 0.01V */
+ if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200))
+ hwrev = 0x2; /* 1.16V 0.01V */
+ if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200))
+ hwrev = 0x3; /* 1.79V 0.01V */
+#undef IS_RANGE
+
+ debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
+
+ adc_power_control(0);
+
+ return hwrev;
+}
+
+static void check_hw_revision(void)
+{
+ int hwrev;
+
+ hwrev = get_hw_revision();
+
+ board_rev |= hwrev;
+}
+
+#ifdef CONFIG_USB_GADGET
+static int s5pc210_phy_control(int on)
+{
+ int ret = 0;
+ struct pmic *p = pmic_get("MAX8998_PMIC");
+ if (!p)
+ return -ENODEV;
+
+ if (pmic_probe(p))
+ return -1;
+
+ if (on) {
+ ret |= pmic_set_output(p,
+ MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
+ MAX8998_SAFEOUT1, LDO_ON);
+ ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
+ MAX8998_LDO3, LDO_ON);
+ ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
+ MAX8998_LDO8, LDO_ON);
+
+ } else {
+ ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
+ MAX8998_LDO8, LDO_OFF);
+ ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
+ MAX8998_LDO3, LDO_OFF);
+ ret |= pmic_set_output(p,
+ MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
+ MAX8998_SAFEOUT1, LDO_OFF);
+ }
+
+ if (ret) {
+ puts("MAX8998 LDO setting error!\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+struct s3c_plat_otg_data s5pc210_otg_data = {
+ .phy_control = s5pc210_phy_control,
+ .regs_phy = EXYNOS4_USBPHY_BASE,
+ .regs_otg = EXYNOS4_USBOTG_BASE,
+ .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
+ .usb_flags = PHY0_SLEEP,
+};
+#endif
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ debug("USB_udc_probe\n");
+ return s3c_udc_probe(&s5pc210_otg_data);
+}
+
+int exynos_early_init_f(void)
+{
+ wdt_stop();
+
+ return 0;
+}
+
+static void init_pmic_lcd(void)
+{
+ unsigned char val;
+ int ret = 0;
+
+ struct pmic *p = pmic_get("MAX8998_PMIC");
+
+ if (!p)
+ return;
+
+ if (pmic_probe(p))
+ return;
+
+ /* LDO7 1.8V */
+ val = 0x02; /* (1800 - 1600) / 100; */
+ ret |= pmic_reg_write(p, MAX8998_REG_LDO7, val);
+
+ /* LDO17 3.0V */
+ val = 0xe; /* (3000 - 1600) / 100; */
+ ret |= pmic_reg_write(p, MAX8998_REG_LDO17, val);
+
+ /* Disable unneeded regulators */
+ /*
+ * ONOFF1
+ * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
+ * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
+ */
+ val = 0xB9;
+ ret |= pmic_reg_write(p, MAX8998_REG_ONOFF1, val);
+
+ /* ONOFF2
+ * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
+ * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
+ */
+ val = 0x50;
+ ret |= pmic_reg_write(p, MAX8998_REG_ONOFF2, val);
+
+ /* ONOFF3
+ * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
+ * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
+ */
+ val = 0x00;
+ ret |= pmic_reg_write(p, MAX8998_REG_ONOFF3, val);
+
+ if (ret)
+ puts("LCD pmic initialisation error!\n");
+}
+
+void exynos_cfg_lcd_gpio(void)
+{
+ unsigned int i, f3_end = 4;
+
+ for (i = 0; i < 8; i++) {
+ /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
+ gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2));
+ gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2));
+ /* pull-up/down disable */
+ gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE);
+ gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE);
+ gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE);
+
+ /* drive strength to max (24bit) */
+ gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X);
+ gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
+ gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X);
+ gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW);
+ gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X);
+ gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
+ }
+
+ for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) {
+ /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
+ gpio_cfg_pin(i, S5P_GPIO_FUNC(2));
+ /* pull-up/down disable */
+ gpio_set_pull(i, S5P_GPIO_PULL_NONE);
+ /* drive strength to max (24bit) */
+ gpio_set_drv(i, S5P_GPIO_DRV_4X);
+ gpio_set_rate(i, S5P_GPIO_DRV_SLOW);
+ }
+
+ /* gpio pad configuration for LCD reset. */
+ gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
+ gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT);
+}
+
+int mipi_power(void)
+{
+ return 0;
+}
+
+void exynos_reset_lcd(void)
+{
+ gpio_set_value(EXYNOS4_GPIO_Y45, 1);
+ udelay(10000);
+ gpio_set_value(EXYNOS4_GPIO_Y45, 0);
+ udelay(10000);
+ gpio_set_value(EXYNOS4_GPIO_Y45, 1);
+ udelay(100);
+}
+
+void exynos_lcd_power_on(void)
+{
+ struct pmic *p = pmic_get("MAX8998_PMIC");
+
+ if (!p)
+ return;
+
+ if (pmic_probe(p))
+ return;
+
+ pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON);
+ pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
+}
+
+void exynos_cfg_ldo(void)
+{
+ ld9040_cfg_ldo();
+}
+
+void exynos_enable_ldo(unsigned int onoff)
+{
+ ld9040_enable_ldo(onoff);
+}
+
+int exynos_init(void)
+{
+ char buf[16];
+
+ gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
+
+ switch (get_hwrev()) {
+ case 0:
+ /*
+ * Set the low to enable LDO_EN
+ * But when you use the test board for eMMC booting
+ * you should set it HIGH since it removes the inverter
+ */
+ /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
+ gpio_request(EXYNOS4_GPIO_E36, "ldo_en");
+ gpio_direction_output(EXYNOS4_GPIO_E36, 0);
+ break;
+ default:
+ /*
+ * Default reset state is High and there's no inverter
+ * But set it as HIGH to ensure
+ */
+ /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
+ gpio_request(EXYNOS4_GPIO_E13, "massmemory_en");
+ gpio_direction_output(EXYNOS4_GPIO_E13, 1);
+ break;
+ }
+
+ /* Request soft I2C gpios */
+ sprintf(buf, "soft_i2c_scl");
+ gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf);
+
+ sprintf(buf, "soft_i2c_sda");
+ gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf);
+
+ check_hw_revision();
+ printf("HW Revision:\t0x%x\n", board_rev);
+
+ return 0;
+}
+
+void exynos_lcd_misc_init(vidinfo_t *vid)
+{
+#ifdef CONFIG_TIZEN
+ get_tizen_logo_info(vid);
+#endif
+
+ /* for LD9040. */
+ vid->pclk_name = 1; /* MPLL */
+ vid->sclk_div = 1;
+
+ setenv("lcdinfo", "lcd=ld9040");
+}
diff --git a/board/sandbox/MAINTAINERS b/board/sandbox/MAINTAINERS
new file mode 100644
index 0000000..10d88a2
--- /dev/null
+++ b/board/sandbox/MAINTAINERS
@@ -0,0 +1,6 @@
+SANDBOX BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/sandbox/
+F: include/configs/sandbox.h
+F: configs/sandbox_defconfig
diff --git a/board/sandbox/Makefile b/board/sandbox/Makefile
new file mode 100644
index 0000000..a0b9880
--- /dev/null
+++ b/board/sandbox/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := sandbox.o
diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox
new file mode 100644
index 0000000..5f879f5
--- /dev/null
+++ b/board/sandbox/README.sandbox
@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) 2014 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+Native Execution of U-Boot
+==========================
+
+The 'sandbox' architecture is designed to allow U-Boot to run under Linux on
+almost any hardware. To achieve this it builds U-Boot (so far as possible)
+as a normal C application with a main() and normal C libraries.
+
+All of U-Boot's architecture-specific code therefore cannot be built as part
+of the sandbox U-Boot. The purpose of running U-Boot under Linux is to test
+all the generic code, not specific to any one architecture. The idea is to
+create unit tests which we can run to test this upper level code.
+
+CONFIG_SANDBOX is defined when building a native board.
+
+The chosen vendor and board names are also 'sandbox', so there is a single
+board in board/sandbox.
+
+CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian
+machines.
+
+Note that standalone/API support is not available at present.
+
+
+Basic Operation
+---------------
+
+To run sandbox U-Boot use something like:
+
+ make sandbox_defconfig all
+ ./u-boot
+
+Note:
+ If you get errors about 'sdl-config: Command not found' you may need to
+ install libsdl1.2-dev or similar to get SDL support. Alternatively you can
+ build sandbox without SDL (i.e. no display/keyboard support) by removing
+ the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using:
+
+ make sandbox_defconfig all NO_SDL=1
+ ./u-boot
+
+
+U-Boot will start on your computer, showing a sandbox emulation of the serial
+console:
+
+
+U-Boot 2014.04 (Mar 20 2014 - 19:06:00)
+
+DRAM: 128 MiB
+Using default environment
+
+In: serial
+Out: lcd
+Err: lcd
+=>
+
+You can issue commands as your would normally. If the command you want is
+not supported you can add it to include/configs/sandbox.h.
+
+To exit, type 'reset' or press Ctrl-C.
+
+
+Console / LCD support
+---------------------
+
+Assuming that CONFIG_SANDBOX_SDL is defined when building, you can run the
+sandbox with LCD and keyboard emulation, using something like:
+
+ ./u-boot -d u-boot.dtb -l
+
+This will start U-Boot with a window showing the contents of the LCD. If
+that window has the focus then you will be able to type commands as you
+would on the console. You can adjust the display settings in the device
+tree file - see arch/sandbox/dts/sandbox.dts.
+
+
+Command-line Options
+--------------------
+
+Various options are available, mostly for test purposes. Use -h to see
+available options. Some of these are described below.
+
+The terminal is normally in what is called 'raw-with-sigs' mode. This means
+that you can use arrow keys for command editing and history, but if you
+press Ctrl-C, U-Boot will exit instead of handling this as a keypress.
+
+Other options are 'raw' (so Ctrl-C is handled within U-Boot) and 'cooked'
+(where the terminal is in cooked mode and cursor keys will not work, Ctrl-C
+will exit).
+
+As mentioned above, -l causes the LCD emulation window to be shown.
+
+A device tree binary file can be provided with -d. If you edit the source
+(it is stored at arch/sandbox/dts/sandbox.dts) you must rebuild U-Boot to
+recreate the binary file.
+
+To execute commands directly, use the -c option. You can specify a single
+command, or multiple commands separated by a semicolon, as is normal in
+U-Boot. Be careful with quoting as the shall will normally process and
+swallow quotes. When -c is used, U-Boot exists after the command is complete,
+but you can force it to go to interactive mode instead with -i.
+
+
+Memory Emulation
+----------------
+
+Memory emulation is supported, with the size set by CONFIG_SYS_SDRAM_SIZE.
+The -m option can be used to read memory from a file on start-up and write
+it when shutting down. This allows preserving of memory contents across
+test runs. You can tell U-Boot to remove the memory file after it is read
+(on start-up) with the --rm_memory option.
+
+To access U-Boot's emulated memory within the code, use map_sysmem(). This
+function is used throughout U-Boot to ensure that emulated memory is used
+rather than the U-Boot application memory. This provides memory starting
+at 0 and extending to the size of the emulation.
+
+
+Storing State
+-------------
+
+With sandbox you can write drivers which emulate the operation of drivers on
+real devices. Some of these drivers may want to record state which is
+preserved across U-Boot runs. This is particularly useful for testing. For
+example, the contents of a SPI flash chip should not disappear just because
+U-Boot exits.
+
+State is stored in a device tree file in a simple format which is driver-
+specific. You then use the -s option to specify the state file. Use -r to
+make U-Boot read the state on start-up (otherwise it starts empty) and -w
+to write it on exit (otherwise the stored state is left unchanged and any
+changes U-Boot made will be lost). You can also use -n to tell U-Boot to
+ignore any problems with missing state. This is useful when first running
+since the state file will be empty.
+
+The device tree file has one node for each driver - the driver can store
+whatever properties it likes in there. See 'Writing Sandbox Drivers' below
+for more details on how to get drivers to read and write their state.
+
+
+Running and Booting
+-------------------
+
+Since there is no machine architecture, sandbox U-Boot cannot actually boot
+a kernel, but it does support the bootm command. Filesystems, memory
+commands, hashing, FIT images, verified boot and many other features are
+supported.
+
+When 'bootm' runs a kernel, sandbox will exit, as U-Boot does on a real
+machine. Of course in this case, no kernel is run.
+
+It is also possible to tell U-Boot that it has jumped from a temporary
+previous U-Boot binary, with the -j option. That binary is automatically
+removed by the U-Boot that gets the -j option. This allows you to write
+tests which emulate the action of chain-loading U-Boot, typically used in
+a situation where a second 'updatable' U-Boot is stored on your board. It
+is very risky to overwrite or upgrade the only U-Boot on a board, since a
+power or other failure will brick the board and require return to the
+manufacturer in the case of a consumer device.
+
+
+Supported Drivers
+-----------------
+
+U-Boot sandbox supports these emulations:
+
+- Block devices
+- Chrome OS EC
+- GPIO
+- Host filesystem (access files on the host from within U-Boot)
+- Keyboard (Chrome OS)
+- LCD
+- Serial (for console only)
+- Sound (incomplete - see sandbox_sdl_sound_init() for details)
+- SPI
+- SPI flash
+- TPM (Trusted Platform Module)
+
+Notable omissions are networking and I2C.
+
+A wide range of commands is implemented. Filesystems which use a block
+device are supported.
+
+Also sandbox uses generic board (CONFIG_SYS_GENERIC_BOARD) and supports
+driver model (CONFIG_DM) and associated commands.
+
+
+SPI Emulation
+-------------
+
+Sandbox supports SPI and SPI flash emulation.
+
+This is controlled by the spi_sf argument, the format of which is:
+
+ bus:cs:device:file
+
+ bus - SPI bus number
+ cs - SPI chip select number
+ device - SPI device emulation name
+ file - File on disk containing the data
+
+For example:
+
+ dd if=/dev/zero of=spi.bin bs=1M count=4
+ ./u-boot --spi_sf 0:0:M25P16:spi.bin
+
+With this setup you can issue SPI flash commands as normal:
+
+=>sf probe
+SF: Detected M25P16 with page size 64 KiB, total 2 MiB
+=>sf read 0 0 10000
+SF: 65536 bytes @ 0x0 Read: OK
+=>
+
+Since this is a full SPI emulation (rather than just flash), you can
+also use low-level SPI commands:
+
+=>sspi 0:0 32 9f
+FF202015
+
+This is issuing a READ_ID command and getting back 20 (ST Micro) part
+0x2015 (the M25P16).
+
+Drivers are connected to a particular bus/cs using sandbox's state
+structure (see the 'spi' member). A set of operations must be provided
+for each driver.
+
+
+Configuration settings for the curious are:
+
+CONFIG_SANDBOX_SPI_MAX_BUS
+ The maximum number of SPI buses supported by the driver (default 1).
+
+CONFIG_SANDBOX_SPI_MAX_CS
+ The maximum number of chip selects supported by the driver
+ (default 10).
+
+CONFIG_SPI_IDLE_VAL
+ The idle value on the SPI bus
+
+
+Writing Sandbox Drivers
+-----------------------
+
+Generally you should put your driver in a file containing the word 'sandbox'
+and put it in the same directory as other drivers of its type. You can then
+implement the same hooks as the other drivers.
+
+To access U-Boot's emulated memory, use map_sysmem() as mentioned above.
+
+If your driver needs to store configuration or state (such as SPI flash
+contents or emulated chip registers), you can use the device tree as
+described above. Define handlers for this with the SANDBOX_STATE_IO macro.
+See arch/sandbox/include/asm/state.h for documentation. In short you provide
+a node name, compatible string and functions to read and write the state.
+Since writing the state can expand the device tree, you may need to use
+state_setprop() which does this automatically and avoids running out of
+space. See existing code for examples.
+
+
+Testing
+-------
+
+U-Boot sandbox can be used to run various tests, mostly in the test/
+directory. These include:
+
+ command_ut
+ - Unit tests for command parsing and handling
+ compression
+ - Unit tests for U-Boot's compression algorithms, useful for
+ security checking. It supports gzip, bzip2, lzma and lzo.
+ driver model
+ - test/dm/test-dm.sh to run these.
+ image
+ - Unit tests for images:
+ test/image/test-imagetools.sh - multi-file images
+ test/image/test-fit.py - FIT images
+ tracing
+ - test/trace/test-trace.sh tests the tracing system (see README.trace)
+ verified boot
+ - See test/vboot/vboot_test.sh for this
+
+If you change or enhance any of the above subsystems, you shold write or
+expand a test and include it with your patch series submission. Test
+coverage in U-Boot is limited, as we need to work to improve it.
+
+Note that many of these tests are implemented as commands which you can
+run natively on your board if desired (and enabled).
+
+It would be useful to have a central script to run all of these.
+
+--
+Simon Glass <sjg@chromium.org>
+Updated 22-Mar-14
diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c
new file mode 100644
index 0000000..e4d4e02
--- /dev/null
+++ b/board/sandbox/sandbox.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+#include <dm.h>
+#include <os.h>
+#include <asm/u-boot-sandbox.h>
+
+/*
+ * Pointer to initial global data area
+ *
+ * Here we initialize it.
+ */
+gd_t *gd;
+
+/* Add a simple GPIO device */
+U_BOOT_DEVICE(gpio_sandbox) = {
+ .name = "gpio_sandbox",
+};
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+}
+
+unsigned long timer_read_counter(void)
+{
+ return os_get_nsec() / 1000;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_VIDEO_SANDBOX_SDL
+ int ret;
+
+ ret = sandbox_lcd_sdl_early_init();
+ if (ret) {
+ puts("Could not init sandbox LCD emulation\n");
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+#endif
+
+int arch_early_init_r(void)
+{
+#ifdef CONFIG_CROS_EC
+ if (cros_ec_board_init()) {
+ printf("%s: Failed to init EC\n", __func__);
+ return 0;
+ }
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ if (cros_ec_get_error()) {
+ /* Force console on */
+ gd->flags &= ~GD_FLG_SILENT;
+
+ printf("cros-ec communications failure %d\n",
+ cros_ec_get_error());
+ puts("\nPlease reset with Power+Refresh\n\n");
+ panic("Cannot init cros-ec device");
+ return -1;
+ }
+ return 0;
+}
+#endif
diff --git a/board/sandisk/sansa_fuze_plus/Kconfig b/board/sandisk/sansa_fuze_plus/Kconfig
new file mode 100644
index 0000000..ab4a292
--- /dev/null
+++ b/board/sandisk/sansa_fuze_plus/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SANSA_FUZE_PLUS
+
+config SYS_BOARD
+ default "sansa_fuze_plus"
+
+config SYS_VENDOR
+ default "sandisk"
+
+config SYS_SOC
+ default "mxs"
+
+config SYS_CONFIG_NAME
+ default "sansa_fuze_plus"
+
+endif
diff --git a/board/sandisk/sansa_fuze_plus/MAINTAINERS b/board/sandisk/sansa_fuze_plus/MAINTAINERS
new file mode 100644
index 0000000..ccfd399
--- /dev/null
+++ b/board/sandisk/sansa_fuze_plus/MAINTAINERS
@@ -0,0 +1,6 @@
+SANSA_FUZE_PLUS BOARD
+M: Marek Vasut <marek.vasut@gmail.com>
+S: Maintained
+F: board/sandisk/sansa_fuze_plus/
+F: include/configs/sansa_fuze_plus.h
+F: configs/sansa_fuze_plus_defconfig
diff --git a/board/sandisk/sansa_fuze_plus/Makefile b/board/sandisk/sansa_fuze_plus/Makefile
new file mode 100644
index 0000000..667600d
--- /dev/null
+++ b/board/sandisk/sansa_fuze_plus/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := sfp.o
+else
+obj-y := spl_boot.o
+endif
diff --git a/board/sandisk/sansa_fuze_plus/sfp.c b/board/sandisk/sansa_fuze_plus/sfp.c
new file mode 100644
index 0000000..a3865ad
--- /dev/null
+++ b/board/sandisk/sansa_fuze_plus/sfp.c
@@ -0,0 +1,388 @@
+/*
+ * SanDisk Sansa Fuze Plus board
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * Hardware investigation done by:
+ *
+ * Amaury Pouly <amaury.pouly@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+#ifdef CONFIG_CMD_MMC
+static int xfi3_mmc_cd(int id)
+{
+ switch (id) {
+ case 0:
+ /* The SSP_DETECT is inverted on this board. */
+ return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
+ case 1:
+ /* Internal eMMC always present */
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+
+ /* MicroSD slot */
+ gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
+ gpio_direction_output(MX23_PAD_GPMI_D08__GPIO_0_8, 0);
+ ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
+ if (ret)
+ return ret;
+
+ /* Internal eMMC */
+ gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0);
+ ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+const iomux_cfg_t iomux_lcd_gpio[] = {
+ MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D06__GPIO_1_6 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D07__GPIO_1_7 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D08__GPIO_1_8 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D09__GPIO_1_9 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D10__GPIO_1_10 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D11__GPIO_1_11 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D12__GPIO_1_12 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D13__GPIO_1_13 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D14__GPIO_1_14 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D15__GPIO_1_15 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D16__GPIO_1_16 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D17__GPIO_1_17 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_RS__GPIO_1_19 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_WR__GPIO_1_20 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_CS__GPIO_1_21 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_ENABLE__GPIO_1_23 | MUX_CONFIG_LCD,
+};
+
+const iomux_cfg_t iomux_lcd_lcd[] = {
+ MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+};
+
+static int mxsfb_read_register(uint32_t reg, uint32_t *value)
+{
+ iomux_cfg_t mux;
+ uint32_t val = 0;
+ int i;
+
+ /* Mangle the register offset. */
+ reg = ((reg & 0xff) << 1) | (((reg >> 8) & 0xff) << 10);
+
+ /*
+ * The SmartLCD interface on MX233 can only do WRITE operation
+ * via the LCDIF controller. Implement the READ operation by
+ * fiddling with bits.
+ */
+ mxs_iomux_setup_multiple_pads(iomux_lcd_gpio,
+ ARRAY_SIZE(iomux_lcd_gpio));
+
+ gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1);
+ gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1);
+ gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1);
+ gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1);
+
+ for (i = 0; i < 18; i++) {
+ mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO);
+ gpio_direction_output(mux, 0);
+ }
+
+ udelay(2);
+ gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 0);
+ udelay(1);
+ gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 0);
+ udelay(1);
+ gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 0);
+ udelay(1);
+
+ for (i = 0; i < 18; i++) {
+ mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO);
+ gpio_direction_output(mux, (reg >> i) & 1);
+ }
+ udelay(1);
+
+ gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1);
+ udelay(3);
+
+ for (i = 0; i < 18; i++) {
+ mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO);
+ gpio_direction_input(mux);
+ }
+ udelay(2);
+
+ gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0);
+ udelay(1);
+ gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1);
+ udelay(1);
+ gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1);
+ udelay(3);
+ gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0);
+ udelay(2);
+
+ for (i = 0; i < 18; i++) {
+ mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO);
+ val |= !!gpio_get_value(mux) << i;
+ }
+ udelay(1);
+
+ gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1);
+ udelay(1);
+ gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1);
+ udelay(1);
+
+ mxs_iomux_setup_multiple_pads(iomux_lcd_lcd,
+ ARRAY_SIZE(iomux_lcd_lcd));
+
+ /* Demangle the register value. */
+ *value = ((val >> 1) & 0xff) | ((val >> 2) & 0xff00);
+
+ writel(val, 0x2000);
+ return 0;
+}
+
+static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
+{
+ struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+ const unsigned int timeout = 0x10000;
+
+ /* What is going on here I do not know. FIXME */
+ payload = ((payload & 0xff) << 1) | (((payload >> 8) & 0xff) << 10);
+
+ if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
+ timeout))
+ return -ETIMEDOUT;
+
+ writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
+ (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
+ ®s->hw_lcdif_transfer_count);
+
+ writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
+ ®s->hw_lcdif_ctrl_clr);
+
+ if (data)
+ writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set);
+
+ writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
+
+ if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29,
+ timeout))
+ return -ETIMEDOUT;
+
+ writel(payload, ®s->hw_lcdif_data);
+ return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
+ timeout);
+}
+
+static void mxsfb_write_register(uint32_t reg, uint32_t data)
+{
+ mxsfb_write_byte(reg, 0);
+ mxsfb_write_byte(data, 1);
+}
+
+static const struct {
+ uint8_t reg;
+ uint8_t delay;
+ uint16_t val;
+} lcd_regs[] = {
+ { 0xe5, 0 , 0x78f0 },
+ { 0xe3, 0 , 0x3008 },
+ { 0xe7, 0 , 0x0012 },
+ { 0xef, 0 , 0x1231 },
+ { 0x00, 0 , 0x0001 },
+ { 0x01, 0 , 0x0100 },
+ { 0x02, 0 , 0x0700 },
+ { 0x03, 0 , 0x1030 },
+ { 0x04, 0 , 0x0000 },
+ { 0x08, 0 , 0x0207 },
+ { 0x09, 0 , 0x0000 },
+ { 0x0a, 0 , 0x0000 },
+ { 0x0c, 0 , 0x0000 },
+ { 0x0d, 0 , 0x0000 },
+ { 0x0f, 0 , 0x0000 },
+ { 0x10, 0 , 0x0000 },
+ { 0x11, 0 , 0x0007 },
+ { 0x12, 0 , 0x0000 },
+ { 0x13, 20 , 0x0000 },
+ /* Wait 20 mS here. */
+ { 0x10, 0 , 0x1290 },
+ { 0x11, 50 , 0x0007 },
+ /* Wait 50 mS here. */
+ { 0x12, 50 , 0x0019 },
+ /* Wait 50 mS here. */
+ { 0x13, 0 , 0x1700 },
+ { 0x29, 50 , 0x0014 },
+ /* Wait 50 mS here. */
+ { 0x20, 0 , 0x0000 },
+ { 0x21, 0 , 0x0000 },
+ { 0x30, 0 , 0x0504 },
+ { 0x31, 0 , 0x0007 },
+ { 0x32, 0 , 0x0006 },
+ { 0x35, 0 , 0x0106 },
+ { 0x36, 0 , 0x0202 },
+ { 0x37, 0 , 0x0504 },
+ { 0x38, 0 , 0x0500 },
+ { 0x39, 0 , 0x0706 },
+ { 0x3c, 0 , 0x0204 },
+ { 0x3d, 0 , 0x0202 },
+ { 0x50, 0 , 0x0000 },
+ { 0x51, 0 , 0x00ef },
+ { 0x52, 0 , 0x0000 },
+ { 0x53, 0 , 0x013f },
+ { 0x60, 0 , 0xa700 },
+ { 0x61, 0 , 0x0001 },
+ { 0x6a, 0 , 0x0000 },
+ { 0x2b, 50 , 0x000d },
+ /* Wait 50 mS here. */
+ { 0x90, 0 , 0x0011 },
+ { 0x92, 0 , 0x0600 },
+ { 0x93, 0 , 0x0003 },
+ { 0x95, 0 , 0x0110 },
+ { 0x97, 0 , 0x0000 },
+ { 0x98, 0 , 0x0000 },
+ { 0x07, 0 , 0x0173 },
+};
+
+void board_mxsfb_system_setup(void)
+{
+ struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+ uint32_t id;
+ int i;
+
+ /* Switch the LCDIF into System-Mode */
+ writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
+ LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr);
+
+ /* To program the LCD, switch to 18bit bus + 18bit data. */
+ clrsetbits_le32(®s->hw_lcdif_ctrl,
+ LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK,
+ LCDIF_CTRL_WORD_LENGTH_18BIT |
+ LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT);
+
+ mxsfb_read_register(0, &id);
+ writel(id, 0x2004);
+
+ /* Restart the SmartLCD controller */
+ mdelay(50);
+ writel(1, ®s->hw_lcdif_ctrl1_set);
+ mdelay(50);
+ writel(1, ®s->hw_lcdif_ctrl1_clr);
+ mdelay(50);
+ writel(1, ®s->hw_lcdif_ctrl1_set);
+ mdelay(50);
+
+ /* Program the SmartLCD controller */
+ writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set);
+
+ writel((0x02 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
+ (0x02 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
+ (0x02 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
+ (0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET),
+ ®s->hw_lcdif_timing);
+
+ /*
+ * ILI9325 init and configuration sequence.
+ */
+ for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
+ mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
+ if (lcd_regs[i].delay)
+ mdelay(lcd_regs[i].delay);
+ }
+ /* Turn on Framebuffer Upload Mode */
+ mxsfb_write_byte(0x22, 0);
+
+ writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
+ ®s->hw_lcdif_ctrl_set);
+
+ /* Operate the framebuffer in 16bit mode. */
+ clrsetbits_le32(®s->hw_lcdif_ctrl,
+ LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK,
+ LCDIF_CTRL_WORD_LENGTH_16BIT |
+ LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT);
+}
+#endif
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ /* Turn on PWM backlight */
+ gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ usb_eth_initialize(bis);
+ return 0;
+}
diff --git a/board/sandisk/sansa_fuze_plus/spl_boot.c b/board/sandisk/sansa_fuze_plus/spl_boot.c
new file mode 100644
index 0000000..825be82
--- /dev/null
+++ b/board/sandisk/sansa_fuze_plus/spl_boot.c
@@ -0,0 +1,140 @@
+/*
+ * SanDisk Sansa Fuze Plus setup
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* EMI */
+ MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
+
+ MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+
+ MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+
+ MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+ MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+
+ MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
+ MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D08__GPIO_0_8 | MUX_CONFIG_SSP,
+
+ MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D04__SSP2_DATA4 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D05__SSP2_DATA5 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D06__SSP2_DATA6 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_D07__SSP2_DATA7 | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP,
+ MX23_PAD_GPMI_WRN__SSP2_SCK |
+ (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL),
+ MX23_PAD_PWM3__GPIO_1_29 | MUX_CONFIG_SSP,
+
+ /* PWM -- FIXME */
+ MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP,
+};
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ /* mDDR configuration values */
+ const uint32_t regs[] = {
+ 0x01010001, 0x00010000, 0x01000000, 0x00000001,
+ 0x00010101, 0x00000001, 0x00010000, 0x01000001,
+ 0x01010000, 0x00000001, 0x07000200, 0x04070203,
+ 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d,
+ 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313,
+ 0x03061323, 0x0000000a, 0x00080008, 0x00200020,
+ 0x00200020, 0x00200020, 0x000003f7, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000020, 0x00000000,
+ 0x001023cd, 0x20410010, 0x00006665, 0x00000000,
+ 0x00000101, 0x00000001, 0x00000000, 0x00000000,
+ };
+ memcpy(dram_vals, regs, sizeof(regs));
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/sbc405/Kconfig b/board/sbc405/Kconfig
new file mode 100644
index 0000000..4e7e843
--- /dev/null
+++ b/board/sbc405/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SBC405
+
+config SYS_BOARD
+ default "sbc405"
+
+config SYS_CONFIG_NAME
+ default "sbc405"
+
+endif
diff --git a/board/sbc405/MAINTAINERS b/board/sbc405/MAINTAINERS
new file mode 100644
index 0000000..2abad25
--- /dev/null
+++ b/board/sbc405/MAINTAINERS
@@ -0,0 +1,6 @@
+SBC405 BOARD
+#M: -
+S: Maintained
+F: board/sbc405/
+F: include/configs/sbc405.h
+F: configs/sbc405_defconfig
diff --git a/board/sbc405/Makefile b/board/sbc405/Makefile
new file mode 100644
index 0000000..3f2b0e2
--- /dev/null
+++ b/board/sbc405/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = sbc405.o strataflash.o
diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c
new file mode 100644
index 0000000..cafc844
--- /dev/null
+++ b/board/sbc405/sbc405.c
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2001
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+#include <spd_sdram.h>
+
+
+int board_early_init_f (void)
+{
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+ */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /*
+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ */
+ mtebc (EBC0_CFG, 0xa8400000);
+
+ return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+ return 0; /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+ return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof(str));
+
+ puts ("Board: ");
+
+ if (i == -1) {
+ puts ("### No HW ID - assuming sbc405");
+ } else {
+ puts(str);
+ }
+
+ putc ('\n');
+
+ return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+ /* TODO: XXX XXX XXX */
+ printf ("test: 64 MB - ok\n");
+
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/sbc405/strataflash.c b/board/sbc405/strataflash.c
new file mode 100644
index 0000000..7ddc97c
--- /dev/null
+++ b/board/sbc405/strataflash.c
@@ -0,0 +1,774 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI 0x98
+#define FLASH_CMD_READ_ID 0x90
+#define FLASH_CMD_RESET 0xff
+#define FLASH_CMD_BLOCK_ERASE 0x20
+#define FLASH_CMD_ERASE_CONFIRM 0xD0
+#define FLASH_CMD_WRITE 0x40
+#define FLASH_CMD_PROTECT 0x60
+#define FLASH_CMD_PROTECT_SET 0x01
+#define FLASH_CMD_PROTECT_CLEAR 0xD0
+#define FLASH_CMD_CLEAR_STATUS 0x50
+#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
+
+#define FLASH_STATUS_DONE 0x80
+#define FLASH_STATUS_ESS 0x40
+#define FLASH_STATUS_ECLBS 0x20
+#define FLASH_STATUS_PSLBS 0x10
+#define FLASH_STATUS_VPENS 0x08
+#define FLASH_STATUS_PSS 0x04
+#define FLASH_STATUS_DPS 0x02
+#define FLASH_STATUS_R 0x01
+#define FLASH_STATUS_PROTECT 0x01
+
+#define FLASH_OFFSET_CFI 0x55
+#define FLASH_OFFSET_CFI_RESP 0x10
+#define FLASH_OFFSET_WTOUT 0x1F
+#define FLASH_OFFSET_WBTOUT 0x20
+#define FLASH_OFFSET_ETOUT 0x21
+#define FLASH_OFFSET_CETOUT 0x22
+#define FLASH_OFFSET_WMAX_TOUT 0x23
+#define FLASH_OFFSET_WBMAX_TOUT 0x24
+#define FLASH_OFFSET_EMAX_TOUT 0x25
+#define FLASH_OFFSET_CEMAX_TOUT 0x26
+#define FLASH_OFFSET_SIZE 0x27
+#define FLASH_OFFSET_INTERFACE 0x28
+#define FLASH_OFFSET_BUFFER_SIZE 0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
+#define FLASH_OFFSET_ERASE_REGIONS 0x2D
+#define FLASH_OFFSET_PROTECT 0x02
+#define FLASH_OFFSET_USER_PROTECTION 0x85
+#define FLASH_OFFSET_INTEL_PROTECTION 0x81
+
+
+#define FLASH_MAN_CFI 0x01000000
+
+
+typedef union {
+ unsigned char c;
+ unsigned short w;
+ unsigned long l;
+} cfiword_t;
+
+typedef union {
+ unsigned char * cp;
+ unsigned short *wp;
+ unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+ return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+ uchar *cp;
+ cp = flash_make_addr(info, 0, offset);
+ return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
+{
+ uchar * addr;
+
+ addr = flash_make_addr(info, sect, offset);
+ return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
+{
+ uchar * addr;
+
+ addr = flash_make_addr(info, sect, offset);
+ return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+ (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+ unsigned long size;
+ int i;
+ unsigned long address;
+
+
+ /* The flash is positioned back to back, with the demultiplexing of the chip
+ * based on the A24 address line.
+ *
+ */
+
+ address = CONFIG_SYS_FLASH_BASE;
+ size = 0;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ size += flash_info[i].size = flash_get_size(address, i);
+ address += CONFIG_SYS_FLASH_INCREMENT;
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+ flash_info[0].size, flash_info[i].size<<20);
+ }
+ }
+
+#if 0 /* test-only */
+ /* Monitor protection ON by default */
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+ for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++)
+ (void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#else
+ /* monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ - CONFIG_SYS_MONITOR_LEN,
+ - 1, &flash_info[1]);
+#endif
+
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int rcode = 0;
+ int prot;
+ int sect;
+
+ if( info->flash_id != FLASH_MAN_CFI) {
+ printf ("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+ if ((s_first < 0) || (s_first > s_last)) {
+ printf ("- no sectors to erase\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+ flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+ if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+ rcode = 1;
+ } else
+ printf(".");
+ }
+ }
+ printf (" done\n");
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id != FLASH_MAN_CFI) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ printf("CFI conformant FLASH (%d x %d)",
+ (info->portwidth << 3 ), (info->chipwidth << 3 ));
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+ printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+ info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count-1))
+ size = info->start[i+1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k=0; k<size; k++)
+ {
+ if (*flash++ != 0xffffffff)
+ {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf ("\n ");
+ /* print empty and read-only info */
+ printf (" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " ");
+#else
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+#endif
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong wp;
+ ulong cp;
+ int aln;
+ cfiword_t cword;
+ int i, rc;
+
+ /* get lower aligned address */
+ wp = (addr & ~(info->portwidth - 1));
+
+ /* handle unaligned start */
+ if((aln = addr - wp) != 0) {
+ cword.l = 0;
+ cp = wp;
+ for(i=0;i<aln; ++i, ++cp)
+ flash_add_byte(info, &cword, (*(uchar *)cp));
+
+ for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+ flash_add_byte(info, &cword, *src++);
+ cnt--;
+ cp++;
+ }
+ for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+ flash_add_byte(info, &cword, (*(uchar *)cp));
+ if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+ return rc;
+ wp = cp;
+ }
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+ while(cnt >= info->portwidth) {
+ i = info->buffer_size > cnt? cnt: info->buffer_size;
+ if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+ return rc;
+ wp += i;
+ src += i;
+ cnt -=i;
+ }
+#else
+ /* handle the aligned part */
+ while(cnt >= info->portwidth) {
+ cword.l = 0;
+ for(i = 0; i < info->portwidth; i++) {
+ flash_add_byte(info, &cword, *src++);
+ }
+ if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+ return rc;
+ wp += info->portwidth;
+ cnt -= info->portwidth;
+ }
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ cword.l = 0;
+ for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+ flash_add_byte(info, &cword, *src++);
+ --cnt;
+ }
+ for (; i<info->portwidth; ++i, ++cp) {
+ flash_add_byte(info, & cword, (*(uchar *)cp));
+ }
+
+ return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+ int retcode = 0;
+
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+ if(prot)
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+ else
+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+ if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+ prot?"protect":"unprotect")) == 0) {
+
+ info->protect[sector] = prot;
+ /* Intel's unprotect unprotects all locking */
+ if(prot == 0) {
+ int i;
+ for(i = 0 ; i<info->sector_count; i++) {
+ if(info->protect[i])
+ flash_real_protect(info, i, 1);
+ }
+ }
+ }
+
+ return retcode;
+}
+/*-----------------------------------------------------------------------
+ * wait for XSR.7 to be set. Time out with an error if it does not.
+ * This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+ ulong start;
+
+ /* Wait for command completion */
+ start = get_timer (0);
+ while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+ if (get_timer(start) > info->erase_blk_tout) {
+ printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+ return ERR_TIMOUT;
+ }
+ }
+ return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+ int retcode;
+ retcode = flash_status_check(info, sector, tout, prompt);
+ if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+ retcode = ERR_INVAL;
+ printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+ if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+ printf("Command Sequence Error.\n");
+ } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+ printf("Block Erase Error.\n");
+ retcode = ERR_NOT_ERASED;
+ } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+ printf("Locking Error\n");
+ }
+ if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+ printf("Block locked.\n");
+ retcode = ERR_PROTECTED;
+ }
+ if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+ printf("Vpp Low Error.\n");
+ }
+ flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+ return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cword->c = c;
+ break;
+ case FLASH_CFI_16BIT:
+ cword->w = (cword->w << 8) | c;
+ break;
+ case FLASH_CFI_32BIT:
+ cword->l = (cword->l << 8) | c;
+ }
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+ int i;
+ uchar *cp = (uchar *)cmdbuf;
+ for(i=0; i< info->portwidth; i++)
+ *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+ volatile cfiptr_t addr;
+ cfiword_t cword;
+ addr.cp = flash_make_addr(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ *addr.cp = cword.c;
+ break;
+ case FLASH_CFI_16BIT:
+ *addr.wp = cword.w;
+ break;
+ case FLASH_CFI_32BIT:
+ *addr.lp = cword.l;
+ break;
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+ cfiptr_t cptr;
+ cfiword_t cword;
+ int retval;
+ cptr.cp = flash_make_addr(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ retval = (cptr.cp[0] == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ retval = (cptr.wp[0] == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ retval = (cptr.lp[0] == cword.l);
+ break;
+ default:
+ retval = 0;
+ break;
+ }
+ return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+ cfiptr_t cptr;
+ cfiword_t cword;
+ int retval;
+ cptr.cp = flash_make_addr(info, sect, offset);
+ flash_make_cmd(info, cmd, &cword);
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ retval = ((cptr.cp[0] & cword.c) == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ retval = ((cptr.wp[0] & cword.w) == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ retval = ((cptr.lp[0] & cword.l) == cword.l);
+ break;
+ default:
+ retval = 0;
+ break;
+ }
+ return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+ for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+ info->portwidth <<= 1) {
+ for(info->chipwidth =FLASH_CFI_BY8;
+ info->chipwidth <= info->portwidth;
+ info->chipwidth <<= 1) {
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+ flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+ if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+ flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+ flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+ return 1;
+ }
+ }
+ return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+ flash_info_t * info = &flash_info[banknum];
+ int i, j;
+ int sect_cnt;
+ unsigned long sector;
+ unsigned long tmp;
+ int size_ratio;
+ uchar num_erase_regions;
+ int erase_region_size;
+ int erase_region_count;
+
+ info->start[0] = base;
+
+ if(flash_detect_cfi(info)){
+#ifdef DEBUG_FLASH
+ printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+ size_ratio = info->portwidth / info->chipwidth;
+ num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+ printf("found %d erase regions\n", num_erase_regions);
+#endif
+ sect_cnt = 0;
+ sector = base;
+ for(i = 0 ; i < num_erase_regions; i++) {
+ if(i > NUM_ERASE_REGIONS) {
+ printf("%d erase regions found, only %d used\n",
+ num_erase_regions, NUM_ERASE_REGIONS);
+ break;
+ }
+ tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+ erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+ tmp >>= 16;
+ erase_region_count = (tmp & 0xffff) +1;
+ for(j = 0; j< erase_region_count; j++) {
+ info->start[sect_cnt] = sector;
+ sector += (erase_region_size * size_ratio);
+ info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+ sect_cnt++;
+ }
+ }
+
+ info->sector_count = sect_cnt;
+ /* multiply the size by the number of chips */
+ info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+ info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+ info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+ info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+ info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+ info->flash_id = FLASH_MAN_CFI;
+ }
+
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+ return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+ cfiptr_t cptr;
+ int flag;
+
+ cptr.cp = (uchar *)dest;
+
+ /* Check if Flash is (sufficiently) erased */
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ flag = ((cptr.cp[0] & cword.c) == cword.c);
+ break;
+ case FLASH_CFI_16BIT:
+ flag = ((cptr.wp[0] & cword.w) == cword.w);
+ break;
+ case FLASH_CFI_32BIT:
+ flag = ((cptr.lp[0] & cword.l) == cword.l);
+ break;
+ default:
+ return 2;
+ }
+ if(!flag)
+ return 2;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cptr.cp[0] = cword.c;
+ break;
+ case FLASH_CFI_16BIT:
+ cptr.wp[0] = cword.w;
+ break;
+ case FLASH_CFI_32BIT:
+ cptr.lp[0] = cword.l;
+ break;
+ }
+
+ /* re-enable interrupts if necessary */
+ if(flag)
+ enable_interrupts();
+
+ return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+ int sector;
+ for(sector = info->sector_count - 1; sector >= 0; sector--) {
+ if(addr >= info->start[sector])
+ break;
+ }
+ return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+ int sector;
+ int cnt;
+ int retcode;
+ volatile cfiptr_t src;
+ volatile cfiptr_t dst;
+
+ src.cp = cp;
+ dst.cp = (uchar *)dest;
+ sector = find_sector(info, dest);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+ if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+ "write to buffer")) == ERR_OK) {
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ cnt = len;
+ break;
+ case FLASH_CFI_16BIT:
+ cnt = len >> 1;
+ break;
+ case FLASH_CFI_32BIT:
+ cnt = len >> 2;
+ break;
+ default:
+ return ERR_INVAL;
+ break;
+ }
+ flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+ while(cnt-- > 0) {
+ switch(info->portwidth) {
+ case FLASH_CFI_8BIT:
+ *dst.cp++ = *src.cp++;
+ break;
+ case FLASH_CFI_16BIT:
+ *dst.wp++ = *src.wp++;
+ break;
+ case FLASH_CFI_32BIT:
+ *dst.lp++ = *src.lp++;
+ break;
+ default:
+ return ERR_INVAL;
+ break;
+ }
+ }
+ flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+ retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+ "buffer write");
+ }
+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+ return retcode;
+}
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/board/sbc8349/Kconfig b/board/sbc8349/Kconfig
new file mode 100644
index 0000000..129d6b9
--- /dev/null
+++ b/board/sbc8349/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SBC8349
+
+config SYS_BOARD
+ default "sbc8349"
+
+config SYS_CONFIG_NAME
+ default "sbc8349"
+
+endif
diff --git a/board/sbc8349/MAINTAINERS b/board/sbc8349/MAINTAINERS
new file mode 100644
index 0000000..af95c1d
--- /dev/null
+++ b/board/sbc8349/MAINTAINERS
@@ -0,0 +1,8 @@
+SBC8349 BOARD
+M: Paul Gortmaker <paul.gortmaker@windriver.com>
+S: Maintained
+F: board/sbc8349/
+F: include/configs/sbc8349.h
+F: configs/sbc8349_defconfig
+F: configs/sbc8349_PCI_33_defconfig
+F: configs/sbc8349_PCI_66_defconfig
diff --git a/board/sbc8349/Makefile b/board/sbc8349/Makefile
new file mode 100644
index 0000000..3b2c389
--- /dev/null
+++ b/board/sbc8349/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2006 Wind River Systems, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sbc8349.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/sbc8349/README b/board/sbc8349/README
new file mode 100644
index 0000000..e2d60cc
--- /dev/null
+++ b/board/sbc8349/README
@@ -0,0 +1,127 @@
+
+
+ U-Boot for Wind River SBC834x Boards
+ ====================================
+
+
+The Wind River SBC834x board is a 6U form factor (not CPCI) reference
+design that uses the MPC8347E or MPC8349E processor. U-Boot support
+for this board is heavily based on the existing U-Boot support for
+Freescale MPC8349 reference boards.
+
+Support has been primarily tested on the SBC8349 version of the board,
+although earlier versions were also tested on the SBC8347. The primary
+difference in the two is the level of PCI functionality.
+
+ http://www.windriver.com/products/OCD/SBC8347E_49E/
+
+
+Flash Details:
+==============
+
+The flash type is intel 28F640Jx (4096x16) [one device]. Base address
+is 0xFF80_0000 which is also where the Hardware Reset Configuration
+Word (HRCW) is stored. Caution should be used to not reset the
+board without having a valid HRCW in place (i.e. erased flash) as
+then a Wind River ICE will be required to restore the HRCW and flash
+image.
+
+
+Restoring a corrupted or missing flash image:
+=============================================
+
+Note that U-boot versions up to and including 2009.06 had essentially
+two copies of u-boot in flash; one at the very beginning, which set
+the HRCW, and one at the very end, which was the image that was run.
+As of this point in time, the two have been combined into just one
+at the beginning of flash, which provides both the HRCW, and the image
+that is executed. This frees up the remainder of flash for other uses.
+Use of the u-boot command "fli" will indicate what parts are in use.
+Details for storing U-boot to flash using a Wind River ICE can be found
+on page 19 of the board manual (request ERG-00328-001). The following
+is a summary of that information:
+
+ - Connect ICE and establish connection to it from WorkBench/OCD.
+ - Ensure you have background mode (BKM) in the OCD terminal window.
+ - Select the appropriate flash type (listed above)
+ - Prepare a u-boot image by using the Wind River Convert utility;
+ by using "Convert and Add file" on the ELF file from your build.
+ Convert from FF80_0000 to FFFF_FFFF (or to FF83_FFFF if you are
+ trying to preserve your old environment settings and user flash).
+ - Set the start address of the erase/flash process to FF80_0000
+ - Set the target RAM required to 64kB.
+ - Select sectors for erasing (see note on environment below)
+ - Select Erase and Reprogram.
+
+Note that some versions of the register files used with Workbench
+would zero some TSEC registers, which inhibits ethernet operation
+by u-boot when this register file is played to the target. Using
+"INN" in the OCD terminal window instead of "IN" before the "GO"
+will not play the register file, and allow u-boot to use the TSEC
+interface while executed from the ICE "GO" command.
+
+Alternatively, you can locate the register file which will be named
+WRS_SBC8349_PCT00328001.reg or similar) and "REM" out all the lines
+beginning with "SCGA TSEC1" and "SCGA TSEC2". This allows you to
+use all the remaining register file content.
+
+If you wish to preserve your prior U-Boot environment settings,
+then convert (and erase to) 0xFF83FFFF instead of 0xFFFFFFFF.
+The size for converting (and erasing) must be at least as large
+as u-boot.bin.
+
+
+Updating U-Boot with U-Boot:
+============================
+
+This procedure is very similar to other boards that have u-boot installed.
+Assuming that the network has been configured, and that the new u-boot.bin
+has been copied to the TFTP server, the commands are:
+
+ tftp 200000 u-boot.bin
+ protect off all
+ erase ff800000 ff83ffff
+ cp.b 200000 ff800000 40000
+ protect on all
+
+You may wish to do a "md ff800000 20" operation as a prefix and postfix
+to the above steps to inspect/compare the HRCW before/after as an extra
+safety check before resetting the board upon completion of the reflash.
+
+PCI:
+====
+
+There are three configuration choices:
+ sbc8349_config
+ sbc8349_PCI_33_config
+ sbc8349_PCI_66_config
+
+The 1st does not enable CONFIG_PCI, and assumes that the PCI slot
+will be left empty (M66EN high), and so the board will operate with
+a base clock of 66MHz. Note that you need both PCI enabled in u-boot
+and linux in order to have functional PCI under linux. The only
+reason for choosing to not enable PCI would be if you had a very
+early (rev 1.0) CPU with possible PCI issues.
+
+The second enables PCI support and builds for a 33MHz clock rate. Note
+that if a 33MHz 32bit card is inserted in the slot, then the whole board
+will clock down to a 33MHz base clock instead of the default 66MHz. This
+will change the baud clocks and mess up your serial console output if you
+were previously running at 66MHz. If you want to use a 33MHz PCI card,
+then you should build a U-Boot with sbc8349_PCI_33_config and store this
+to flash prior to powering down the board and inserting the 33MHz PCI
+card.
+
+The third option builds PCI support in, and leaves the clocking at the
+default 66MHz. This has been tested with an intel PCI-X e1000 card.
+This is also the appropriate choice for people with a recent (non 1.0)
+CPU who currently have the PCI slot physically empty, but intend to
+possibly add a PCI-X card at a later date.
+
+ => pci
+ Scanning PCI devices on bus 0
+ BusDevFun VendorId DeviceId Device Class Sub-Class
+ _____________________________________________________________
+ 00.00.00 0x1957 0x0080 Processor 0x20
+ 00.11.00 0x8086 0x1026 Network controller 0x00
+ =>
diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c
new file mode 100644
index 0000000..e792fe3
--- /dev/null
+++ b/board/sbc8349/pci.c
@@ -0,0 +1,71 @@
+/*
+ * pci.c -- WindRiver SBC8349 PCI board support.
+ * Copyright (c) 2006 Wind River Systems, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * Based on MPC8349 PCI support but w/o PIB related code.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
+
+/*
+ * pci_init_board()
+ *
+ * NOTICE: PCI2 is not supported. There is only one
+ * physical PCI slot on the board.
+ *
+ */
+void
+pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci1_regions };
+
+ /* Enable all 8 PCI_CLK_OUTPUTS */
+ clk->occr = 0xff000000;
+ udelay(2000);
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
+
+ udelay(2000);
+
+ mpc83xx_pci_init(1, reg);
+}
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
new file mode 100644
index 0000000..72786d2
--- /dev/null
+++ b/board/sbc8349/sbc8349.c
@@ -0,0 +1,226 @@
+/*
+ * sbc8349.c -- WindRiver SBC8349 board support.
+ * Copyright (c) 2006-2007 Wind River Systems, Inc.
+ *
+ * Paul Gortmaker <paul.gortmaker@windriver.com>
+ * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spd_sdram.h>
+#include <miiphy.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+int fixed_sdram(void);
+void sdram_init(void);
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f (void)
+{
+ return 0;
+}
+#endif
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
+
+phys_size_t initdram (int board_type)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+ msize = spd_sdram();
+#else
+ msize = fixed_sdram();
+#endif
+ /*
+ * Initialize SDRAM if it is on local bus.
+ */
+ sdram_init();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE;
+ u32 ddr_size = msize << 20; /* DDR size in bytes */
+ u32 ddr_size_log2 = __ilog2(msize);
+
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+
+#if (CONFIG_SYS_DDR_SIZE != 256)
+#warning Currently any ddr size other than 256 is not supported
+#endif
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ im->ddr.csbnds[2].csbnds =
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+ CSBNDS_EA_SHIFT) & CSBNDS_EA);
+ im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
+
+ /* currently we use only one CS, so disable the other banks */
+ im->ddr.cs_config[0] = 0;
+ im->ddr.cs_config[1] = 0;
+ im->ddr.cs_config[3] = 0;
+
+ im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+
+ im->ddr.sdram_cfg =
+ SDRAM_CFG_SREN
+#if defined(CONFIG_DDR_2T_TIMING)
+ | SDRAM_CFG_2T_EN
+#endif
+ | SDRAM_CFG_SDRAM_TYPE_DDR1;
+#if defined (CONFIG_DDR_32BIT)
+ /* for 32-bit mode burst length is 8 */
+ im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
+#endif
+ im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+
+ im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ udelay(200);
+
+ /* enable DDR controller */
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+ return msize;
+}
+#endif/*!CONFIG_SYS_SPD_EEPROM*/
+
+
+int checkboard (void)
+{
+ puts("Board: Wind River SBC834x\n");
+ return 0;
+}
+
+/*
+ * if board is fitted with SDRAM
+ */
+#if defined(CONFIG_SYS_BR2_PRELIM) \
+ && defined(CONFIG_SYS_OR2_PRELIM) \
+ && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
+ && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void sdram_init(void)
+{
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile fsl_lbc_t *lbc = &immap->im_lbc;
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+
+ puts("\n SDRAM on Local Bus: ");
+ print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+ */
+
+ /* setup mtrpt, lsrt and lbcr for LB bus */
+ lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+ lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+ lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+ asm("sync");
+
+ /*
+ * Configure the SDRAM controller Machine Mode Register.
+ */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+ asm("sync");
+ /*1 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*2 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*3 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*4 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*5 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*6 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*7 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+ /*8 times*/
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ /* 0x58636733; mode register write operation */
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+
+ lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+ asm("sync");
+ *sdram_addr = 0xff;
+ udelay(100);
+}
+#else
+void sdram_init(void)
+{
+ puts(" SDRAM on Local Bus: Disabled in config\n");
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/board/sbc8548/Kconfig b/board/sbc8548/Kconfig
new file mode 100644
index 0000000..626cbdf
--- /dev/null
+++ b/board/sbc8548/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SBC8548
+
+config SYS_BOARD
+ default "sbc8548"
+
+config SYS_CONFIG_NAME
+ default "sbc8548"
+
+endif
diff --git a/board/sbc8548/MAINTAINERS b/board/sbc8548/MAINTAINERS
new file mode 100644
index 0000000..ba1f247
--- /dev/null
+++ b/board/sbc8548/MAINTAINERS
@@ -0,0 +1,10 @@
+SBC8548 BOARD
+M: Paul Gortmaker <paul.gortmaker@windriver.com>
+S: Maintained
+F: board/sbc8548/
+F: include/configs/sbc8548.h
+F: configs/sbc8548_defconfig
+F: configs/sbc8548_PCI_33_defconfig
+F: configs/sbc8548_PCI_33_PCIE_defconfig
+F: configs/sbc8548_PCI_66_defconfig
+F: configs/sbc8548_PCI_66_PCIE_defconfig
diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile
new file mode 100644
index 0000000..4c9b6cd
--- /dev/null
+++ b/board/sbc8548/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2004-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2007 Wind River Systems Inc <www.windriver.com>.
+# Added support for Wind River SBC8548 board
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sbc8548.o
+obj-y += law.o
+obj-y += tlb.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/sbc8548/README b/board/sbc8548/README
new file mode 100644
index 0000000..feac5e3
--- /dev/null
+++ b/board/sbc8548/README
@@ -0,0 +1,269 @@
+Intro:
+======
+
+The SBC8548 is a stand alone single board computer with a 1GHz
+MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz
+memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
+and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC
+ethernet connections.
+
+U-boot Configuration:
+=====================
+
+The following possible u-boot configuration targets are available:
+
+ 1) sbc8548_config
+ 2) sbc8548_PCI_33_config
+ 3) sbc8548_PCI_66_config
+ 4) sbc8548_PCI_33_PCIE_config
+ 5) sbc8548_PCI_66_PCIE_config
+
+Generally speaking, most people should choose to use #5. Details
+of each choice are listed below.
+
+Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
+will be left empty (M66EN high), and so the board will operate with
+a base clock of 66MHz. Note that you need both PCI enabled in u-boot
+and linux in order to have functional PCI under linux.
+
+The second enables PCI support and builds for a 33MHz clock rate. Note
+that if a 33MHz 32bit card is inserted in the slot, then the whole board
+will clock down to a 33MHz base clock instead of the default 66MHz. This
+will change the baud clocks and mess up your serial console output if you
+were previously running at 66MHz. If you want to use a 33MHz PCI card,
+then you should build a U-Boot with a _PCI_33_ config and store this
+to flash prior to powering down the board and inserting the 33MHz PCI
+card. [The above discussion assumes that the SW2[1-4] has not been changed
+to reflect a different CCB:SYSCLK ratio]
+
+The third option builds PCI support in, and leaves the clocking at the
+default 66MHz. Options four and five are just repeats of option two
+and three, but with PCI-e support enabled as well.
+
+PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
+is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
+a 33MHz PCI configuration is currently untested.)
+
+ => pci 0
+ Scanning PCI devices on bus 0
+ BusDevFun VendorId DeviceId Device Class Sub-Class
+ _____________________________________________________________
+ 00.00.00 0x1057 0x0012 Processor 0x20
+ 00.01.00 0x8086 0x1026 Network controller 0x00
+ => pci 1
+ Scanning PCI devices on bus 1
+ BusDevFun VendorId DeviceId Device Class Sub-Class
+ _____________________________________________________________
+ 01.00.00 0x1957 0x0012 Processor 0x20
+ => pci 2
+ Scanning PCI devices on bus 2
+ BusDevFun VendorId DeviceId Device Class Sub-Class
+ _____________________________________________________________
+ 02.00.00 0x1148 0x9e00 Network controller 0x00
+ =>
+
+Memory Size and using SPD:
+==========================
+
+The default configuration uses hard coded memory configuration settings
+for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD
+EEPROM data to read what memory is installed.
+
+There is a hardware errata, which causes the older local bus SDRAM
+SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
+that the SPD data can not be read reliably. You can test if your
+board has the errata fix by running "i2c probe". If you see 0x53
+as a valid device, it has been fixed. If you only see 0x50, 0x51
+then your board does not have the fix.
+
+You can also visually inspect the board to see if this hardware
+fix has been applied:
+
+ 1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
+ the back of the PCB behind the DDR SDRAM SODIMM connector.
+ 2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
+ to R313 pin 2. Pin 2 for each resistor is the end of the
+ resistor closest to the CPU.
+
+Boards without the mod will have R314 and R313 in parallel, like "||".
+After the mod, they will be touching and form an "L" shape.
+
+If you want to upgrade to larger RAM size, you can simply enable
+ #define CONFIG_SPD_EEPROM
+ #define CONFIG_DDR_SPD
+in include/configs/sbc8548.h file. (The lines are already there
+but listed as #undef).
+
+If you did the i2c test, and your board does not have the errata
+fix, then you will have to physically remove the LBC 128MB DIMM
+from the board's socket to resolve the above i2c address overlap
+issue and allow SPD autodetection of RAM to work.
+
+
+Updating U-boot with U-boot:
+============================
+
+Note that versions of u-boot up to and including 2009.08 had u-boot stored
+at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from
+0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to
+update u-boot with u-boot and it uses the old address, you will render
+your board inoperable, and you will require JTAG recovery.
+
+The following steps list how to update with the current address:
+
+ tftp u-boot.bin
+ md 200000 10
+ protect off all
+ erase fffa0000 ffffffff
+ cp.b 200000 fffa0000 60000
+ md fffa0000 10
+ protect on all
+
+The "md" steps in the above are just a precautionary step that allow
+you to confirm the u-boot version that was downloaded, and then confirm
+that it was copied to flash.
+
+The above assumes that you are using the default board settings which
+have u-boot in the 8MB flash, tied to /CS0.
+
+If you are running the default 8MB /CS0 settings but want to store an
+image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled,
+(as a backup, etc) then the steps will become:
+
+ tftp u-boot.bin
+ md 200000 10
+ protect off all
+ era eff00000 efffffff
+ cp.b 200000 eff00000 100000
+ md eff00000 10
+ protect on all
+
+Finally, if you are running the alternate 64MB /CS0 settings and want
+to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT
+enabled) the steps will become:
+
+ tftp u-boot.bin
+ md 200000 10
+ protect off all
+ era fff00000 ffffffff
+ cp.b 200000 fff00000 100000
+ md fff00000 10
+ protect on all
+
+
+Hardware Reference:
+===================
+
+The following contains some summary information on hardware settings
+that are relevant to u-boot, based on the board manual. For the
+most up to date and complete details of the board, please request the
+reference manual ERG-00327-001.pdf from www.windriver.com
+
+Boot flash:
+ intel V28F640Jx, 8192x8 (one device) at 0xff80_0000
+
+Sodimm flash:
+ intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000
+ Note that this address reflects the default setting for
+ the JTAG debugging tools, but since the alignment is
+ rather inconvenient, u-boot puts it at 0xec00_0000.
+
+
+ Jumpers:
+
+Jumper Name ON OFF
+----------------------------------------------------------------
+JP12 CS0/CS6 swap see note[*] see note[*]
+
+JP13 SODIMM flash write OK writes disabled
+ write prot.
+
+JP14 HRESET/TRST joined isolated
+
+JP15 PWR ON when AC pwr use S1 for on/off
+
+JP16 Demo LEDs lit not lit
+
+JP19 PCI mode PCI PCI-X
+
+
+[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash
+onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
+is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
+SODIMM flash and /CS6 is for the boot flash. Note that in this
+alternate setting, you also need to switch SW2.8 to ON.
+See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting
+and boot u-boot from the 64MB SODIMM
+
+
+ Switches:
+
+The defaults are marked with a *
+
+Name Desc. ON OFF
+------------------------------------------------------------------
+S1 Pwr toggle n/a n/a
+
+SW2.1 CFG_SYS_PLL0 1 0*
+SW2.2 CFG_SYS_PLL1 1* 0
+SW2.3 CFG_SYS_PLL2 1* 0
+SW2.4 CFG_SYS_PLL3 1 0*
+SW2.5 CFG_CORE_PLL0 1* 0
+SW2.6 CFG_CORE_PLL1 1 0*
+SW2.7 CFG_CORE_PLL2 1* 0
+SW2.8 CFG_ROM_LOC1 1 0*
+
+SW3.1 CFG_HOST_AGT0 1* 0
+SW3.2 CFG_HOST_AGT1 1* 0
+SW3.3 CFG_HOST_AGT2 1* 0
+SW3.4 CFG_IO_PORTS0 1* 0
+SW3.5 CFG_IO_PORTS0 1 0*
+SW3.6 CFG_IO_PORTS0 1 0*
+
+SerDes CLK(MHz) SW5.1 SW5.2
+----------------------------------------------
+25 0 0
+100* 1 0
+125 0 1
+200 1 1
+
+SerDes CLK spread SW5.3 SW5.4
+----------------------------------------------
++/- 0.25% 0 0
+-0.50% 1 0
+-0.75% 0 1
+No Spread* 1 1
+
+SW4 settings are readable from the EPLD and are currently not used for
+any hardware settings (i.e. user configuration switches).
+
+ LEDs:
+
+Name Desc. ON OFF
+------------------------------------------------------------------
+D13 PCI/PCI-X PCI-X PCI
+D14 3.3V PWR 3.3V no power
+D15 SYSCLK 66MHz 33MHz
+
+
+ Default Memory Map:
+
+start end CS<n> width Desc.
+----------------------------------------------------------------------
+0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB)
+f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB)
+f800_0000 f8b0_1fff CS5 - EPLD
+fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*]
+ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
+
+[*] fb80 represents the default programmed by WR JTAG register files,
+ but u-boot places the flash at either ec00 or fc00 based on JP12.
+
+The EPLD on CS5 demuxes the following devices at the following offsets:
+
+offset size width device
+--------------------------------------------------------
+0 1fff 8 7 segment display LED
+10_0000 1fff 4 user switches
+30_0000 1fff 4 HW Rev. register
+b0_0000 1fff 8 8kB EEPROM
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
new file mode 100644
index 0000000..24cc776
--- /dev/null
+++ b/board/sbc8548/ddr.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 10;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
+
+#ifdef CONFIG_SPD_EEPROM
+/*
+ * Workaround for hardware errata. An i2c address conflict
+ * existed on earlier boards; the workaround moved the DDR
+ * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and
+ * if that fails, then fall back to reading at 0x51.
+ */
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+ int ret;
+
+#ifdef ALT_SPD_EEPROM_ADDRESS
+ if (i2c_address == SPD_EEPROM_ADDRESS) {
+ ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
+ if (ret == 0)
+ return; /* Good data at 0x53 */
+ memset(spd, 0, sizeof(generic_spd_eeprom_t));
+ }
+#endif
+ ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
+ sizeof(generic_spd_eeprom_t));
+ if (ret) {
+ printf("DDR: failed to read SPD from addr %u\n", i2c_address);
+ memset(spd, 0, sizeof(generic_spd_eeprom_t));
+ }
+}
+
+#else
+/*
+ * fixed_sdram init -- doesn't use serial presence detect.
+ * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
+ */
+phys_size_t fixed_sdram(void)
+{
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+
+ out_be32(&ddr->cs0_bnds, 0x0000007f);
+ out_be32(&ddr->cs1_bnds, 0x008000ff);
+ out_be32(&ddr->cs2_bnds, 0x00000000);
+ out_be32(&ddr->cs3_bnds, 0x00000000);
+
+ out_be32(&ddr->cs0_config, 0x80010101);
+ out_be32(&ddr->cs1_config, 0x80010101);
+ out_be32(&ddr->cs2_config, 0x00000000);
+ out_be32(&ddr->cs3_config, 0x00000000);
+
+ out_be32(&ddr->timing_cfg_3, 0x00000000);
+ out_be32(&ddr->timing_cfg_0, 0x00220802);
+ out_be32(&ddr->timing_cfg_1, 0x38377322);
+ out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
+
+ out_be32(&ddr->sdram_cfg, 0x4300C000);
+ out_be32(&ddr->sdram_cfg_2, 0x24401000);
+
+ out_be32(&ddr->sdram_mode, 0x23C00542);
+ out_be32(&ddr->sdram_mode_2, 0x00000000);
+
+ out_be32(&ddr->sdram_interval, 0x05080100);
+ out_be32(&ddr->sdram_md_cntl, 0x00000000);
+ out_be32(&ddr->sdram_data_init, 0x00000000);
+ out_be32(&ddr->sdram_clk_cntl, 0x03800000);
+ asm("sync;isync;msync");
+ udelay(500);
+
+ #ifdef CONFIG_DDR_ECC
+ /* Enable ECC checking */
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
+ #else
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+ #endif
+
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
new file mode 100644
index 0000000..e1f90a0
--- /dev/null
+++ b/board/sbc8548/law.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x0fff_ffff DDR 256M
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe27f_ffff PCI1 IO 8M
+ * 0xe280_0000 0xe2ff_ffff PCIe IO 8M
+ * 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf8b0_0000 0xf80f_ffff EEPROM 1M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * If swapped CS0/CS6 via JP12+SW2.8:
+ * 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M
+ * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifdef CONFIG_SYS_ALT_BOOT
+ SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
+#else
+ SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#endif
+#ifndef CONFIG_SPD_EEPROM
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
+#endif
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#else
+ /* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
+ SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
new file mode 100644
index 0000000..25329e4
--- /dev/null
+++ b/board/sbc8548/sbc8548.c
@@ -0,0 +1,314 @@
+/*
+ * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
+ *
+ * Copyright 2007 Embedded Specialties, Inc.
+ *
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <spd_sdram.h>
+#include <netdev.h>
+#include <tsec.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void local_bus_init(void);
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
+
+ printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
+ in_8(rev) >> 4);
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
+ out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
+ return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+
+ lbc_mhz = sysinfo.freq_localbus / 1000000;
+ clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
+
+ debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
+
+ out_be32(&gur->lbiuiplldcr1, 0x00078080);
+ if (clkdiv == 16) {
+ out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
+ } else if (clkdiv == 8) {
+ out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
+ } else if (clkdiv == 4) {
+ out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
+ }
+
+ /*
+ * Local Bus Clock > 83.3 MHz. According to timing
+ * specifications set LCRR[EADC] to 2 delay cycles.
+ */
+ if (lbc_mhz > 83) {
+ lcrr &= ~LCRR_EADC;
+ lcrr |= LCRR_EADC_2;
+ }
+
+ /*
+ * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
+ * disable PLL bypass for Local Bus Clock > 83 MHz.
+ */
+ if (lbc_mhz >= 66)
+ lcrr &= (~LCRR_DBYP); /* DLL Enabled */
+
+ else
+ lcrr |= LCRR_DBYP; /* DLL Bypass */
+
+ out_be32(&lbc->lcrr, lcrr);
+ asm("sync;isync;msync");
+
+ /*
+ * According to MPC8548ERMAD Rev.1.3 read back LCRR
+ * and terminate with isync
+ */
+ lcrr = in_be32(&lbc->lcrr);
+ asm ("isync;");
+
+ /* let DLL stabilize */
+ udelay(500);
+
+ out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
+ out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void lbc_sdram_init(void)
+{
+#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
+
+ uint idx;
+ const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+ uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
+
+ puts(" SDRAM: ");
+
+ print_size(size, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
+ set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+ set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
+ set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
+
+ out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+ asm("msync");
+
+ out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
+ out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+ asm("msync");
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
+ udelay(100);
+
+ /*
+ * Issue RFEN command.
+ */
+ out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ *sdram_addr2 = 0xff;
+ ppcDcbf((unsigned long) sdram_addr2);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+ uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CONFIG_SYS_MEMTEST_START,
+ CONFIG_SYS_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif /* CONFIG_PCI1 */
+
+#ifdef CONFIG_PCI
+void
+pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int first_free_busno = 0;
+
+#ifdef CONFIG_PCI1
+ struct fsl_pci_info pci_info;
+ u32 devdisr = in_be32(&gur->devdisr);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 porpllsr = in_be32(&gur->porpllsr);
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
+ uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+ uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
+
+ printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33000000) ? "33" :
+ (pci_speed == 66000000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_arb ? "arbiter" : "external-arbiter");
+
+ SET_STD_PCI_INFO(pci_info, 1);
+ set_next_law(pci_info.mem_phys,
+ law_size_bits(pci_info.mem_size), pci_info.law);
+ set_next_law(pci_info.io_phys,
+ law_size_bits(pci_info.io_size), pci_info.law);
+
+ first_free_busno = fsl_pci_init_port(&pci_info,
+ &pci1_hose, first_free_busno);
+ } else {
+ printf("PCI: disabled\n");
+ }
+
+ puts("\n");
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
+#endif
+
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
+
+ fsl_pcie_init_board(first_free_busno);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ tsec_standard_init(bis);
+ pci_eth_init(bis);
+ return 0; /* otherwise cpu_eth_init gets run */
+}
+
+int last_stage_init(void)
+{
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_FSL_PCI_INIT
+ FT_FSL_PCI_SETUP;
+#endif
+
+ return 0;
+}
+#endif
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
new file mode 100644
index 0000000..2f7e4c5
--- /dev/null
+++ b/board/sbc8548/tlb.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /*
+ * TLB 0: 64M Non-cacheable, guarded
+ * 0xfc000000 56M unused
+ * 0xff800000 8M boot FLASH
+ * .... or ....
+ * 0xfc000000 64M user flash
+ *
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 1: 1G Non-cacheable, guarded
+ * 0x80000000 512M PCI1 MEM
+ * 0xa0000000 512M PCIe MEM
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1G, 1),
+
+ /*
+ * TLB 2: 64M Non-cacheable, guarded
+ * 0xe0000000 1M CCSRBAR
+ * 0xe2000000 8M PCI1 IO
+ * 0xe2800000 8M PCIe IO
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_64M, 1),
+
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
+ /*
+ * TLB 3: 64M Cacheable, non-guarded
+ * 0xf0000000 64M LBC SDRAM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 3, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 4: 64M Cacheable, non-guarded
+ * 0xf4000000 64M LBC SDRAM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
+ CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 4, BOOKE_PAGESZ_64M, 1),
+#endif
+
+ /*
+ * TLB 5: 16M Cacheable, non-guarded
+ * 0xf8000000 1M 7-segment LED display
+ * 0xf8100000 1M User switches
+ * 0xf8300000 1M Board revision
+ * 0xf8b00000 1M EEPROM
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+
+#ifndef CONFIG_SYS_ALT_BOOT
+ /*
+ * TLB 6: 64M Non-cacheable, guarded
+ * 0xec000000 64M 64MB user FLASH
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_64M, 1),
+#else
+ /*
+ * TLB 6: 4M Non-cacheable, guarded
+ * 0xef800000 4M 1st 1/2 8MB soldered FLASH
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_4M, 1),
+
+ /*
+ * TLB 7: 4M Non-cacheable, guarded
+ * 0xefc00000 4M 2nd half 8MB soldered FLASH
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
+ CONFIG_SYS_ALT_FLASH + 0x400000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_4M, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/sbc8641d/Kconfig b/board/sbc8641d/Kconfig
new file mode 100644
index 0000000..8dfc90c
--- /dev/null
+++ b/board/sbc8641d/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SBC8641D
+
+config SYS_BOARD
+ default "sbc8641d"
+
+config SYS_CONFIG_NAME
+ default "sbc8641d"
+
+endif
diff --git a/board/sbc8641d/MAINTAINERS b/board/sbc8641d/MAINTAINERS
new file mode 100644
index 0000000..a50b541
--- /dev/null
+++ b/board/sbc8641d/MAINTAINERS
@@ -0,0 +1,6 @@
+SBC8641D BOARD
+M: Paul Gortmaker <paul.gortmaker@windriver.com>
+S: Maintained
+F: board/sbc8641d/
+F: include/configs/sbc8641d.h
+F: configs/sbc8641d_defconfig
diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile
new file mode 100644
index 0000000..a9b2026
--- /dev/null
+++ b/board/sbc8641d/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sbc8641d.o
+obj-y += law.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/sbc8641d/README b/board/sbc8641d/README
new file mode 100644
index 0000000..a051466
--- /dev/null
+++ b/board/sbc8641d/README
@@ -0,0 +1,28 @@
+Wind River SBC8641D reference board
+===========================
+
+Created 06/14/2007 Joe Hamman
+Copyright 2007, Embedded Specialties, Inc.
+Copyright 2007 Wind River Systemes, Inc.
+-----------------------------
+
+1. Building U-Boot
+------------------
+The SBC8641D code is known to build using ELDK 4.1.
+
+ $ make sbc8641d_config
+ Configuring for sbc8641d board...
+
+ $ make
+
+
+2. Switch and Jumper Settings
+-----------------------------
+All Jumpers & Switches are in their default positions. Please refer to
+the board documentation for details. Some settings control CPU voltages
+and settings may change with board revisions.
+
+3. Known limitations
+--------------------
+PCI:
+ The PCI command may hang if no boards are present in either slot.
diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c
new file mode 100644
index 0000000..b31ea34
--- /dev/null
+++ b/board/sbc8641d/ddr.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 10;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
new file mode 100644
index 0000000..c4e736b
--- /dev/null
+++ b/board/sbc8641d/law.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW (Local Access Window) configuration:
+ *
+ * 0x0000_0000 DDR 256M
+ * 0x1000_0000 DDR2 256M
+ * 0x8000_0000 PCIE1 MEM 512M
+ * 0xa000_0000 PCIE2 MEM 512M
+ * 0xc000_0000 RapidIO 512M
+ * 0xe200_0000 PCIE1 IO 16M
+ * 0xe300_0000 PCIE2 IO 16M
+ * 0xf800_0000 CCSRBAR 2M
+ * 0xfe00_0000 FLASH (boot bank) 32M
+ *
+ */
+
+
+struct law_entry law_table[] = {
+#if !defined(CONFIG_SPD_EEPROM)
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+ LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
+#endif
+ SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
+ SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
new file mode 100644
index 0000000..6bdf1a2
--- /dev/null
+++ b/board/sbc8641d/sbc8641d.c
@@ -0,0 +1,261 @@
+/*
+ * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Joe Hamman joe.hamman@embeddedspecialties.com
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+long int fixed_sdram (void);
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ puts ("Board: Wind River SBC8641D\n");
+
+ return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = fsl_ddr_sdram();
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+ debug (" DDR: ");
+ return dram_size;
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+ uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+ uint *p;
+
+ puts ("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ puts ("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ puts ("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+long int fixed_sdram (void)
+{
+#if !defined(CONFIG_SYS_RAMBOOT)
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
+
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
+ ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
+ ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+ ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
+ ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
+ ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
+ ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
+ ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+ ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+ ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+
+ asm ("sync;isync");
+
+ udelay (500);
+
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
+ asm ("sync; isync");
+
+ udelay (500);
+ ddr = &immap->im_ddr2;
+
+ ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
+ ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
+ ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
+ ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
+ ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
+ ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
+ ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
+ ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
+ ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
+ ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
+ ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
+ ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
+ ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
+ ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
+ ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
+ ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
+
+ asm ("sync;isync");
+
+ udelay (500);
+
+ ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
+ asm ("sync; isync");
+
+ udelay (500);
+#endif
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif /* CONFIG_PCI */
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ FT_FSL_PCI_SETUP;
+
+ return 0;
+}
+#endif
+
+void sbc8641d_reset_board (void)
+{
+ puts ("Resetting board....\n");
+}
+
+/*
+ * get_board_sys_clk
+ * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long get_board_sys_clk (ulong dummy)
+{
+ int i;
+ ulong val = 0;
+
+ i = 5;
+ i &= 0x07;
+
+ switch (i) {
+ case 0:
+ val = 33000000;
+ break;
+ case 1:
+ val = 40000000;
+ break;
+ case 2:
+ val = 50000000;
+ break;
+ case 3:
+ val = 66000000;
+ break;
+ case 4:
+ val = 83000000;
+ break;
+ case 5:
+ val = 100000000;
+ break;
+ case 6:
+ val = 134000000;
+ break;
+ case 7:
+ val = 166000000;
+ break;
+ }
+
+ return val;
+}
+
+void board_reset(void)
+{
+#ifdef CONFIG_SYS_RESET_ADDRESS
+ ulong addr = CONFIG_SYS_RESET_ADDRESS;
+
+ /* flush and disable I/D cache */
+ __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
+ __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
+ __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
+ __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("mtspr 1008, 4");
+ __asm__ __volatile__ ("isync");
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("mtspr 1008, 5");
+ __asm__ __volatile__ ("isync");
+ __asm__ __volatile__ ("sync");
+
+ /*
+ * SRR0 has system reset vector, SRR1 has default MSR value
+ * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
+ */
+ __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
+ __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
+ __asm__ __volatile__ ("mtspr 27, 4");
+ __asm__ __volatile__ ("rfi");
+#endif
+}
diff --git a/board/sc3/Kconfig b/board/sc3/Kconfig
new file mode 100644
index 0000000..88a6d86
--- /dev/null
+++ b/board/sc3/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SC3
+
+config SYS_BOARD
+ default "sc3"
+
+config SYS_CONFIG_NAME
+ default "sc3"
+
+endif
diff --git a/board/sc3/MAINTAINERS b/board/sc3/MAINTAINERS
new file mode 100644
index 0000000..b86c6e6
--- /dev/null
+++ b/board/sc3/MAINTAINERS
@@ -0,0 +1,6 @@
+SC3 BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: board/sc3/
+F: include/configs/sc3.h
+F: configs/sc3_defconfig
diff --git a/board/sc3/Makefile b/board/sc3/Makefile
new file mode 100644
index 0000000..c1d163e
--- /dev/null
+++ b/board/sc3/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = sc3.o sc3nand.o
+obj-y += init.o
diff --git a/board/sc3/init.S b/board/sc3/init.S
new file mode 100644
index 0000000..097aa4a
--- /dev/null
+++ b/board/sc3/init.S
@@ -0,0 +1,360 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0 IBM-pibs
+ */
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+/**
+ * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
+ *
+ * IMPORTANT: For pass1 this code must run from cache since you can not
+ * reliably change a peripheral banks timing register (pbxap) while running
+ * code from that bank. For ex., since we are running from ROM on bank 0, we
+ * can NOT execute the code that modifies bank 0 timings from ROM, so
+ * we run it from cache.
+ *
+ * Bank 0 - Boot-Flash
+ * Bank 1 - NAND-Flash
+ * Bank 2 - ISA bus
+ * Bank 3 - Second Flash
+ * Bank 4 - USB controller
+ */
+ .globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+/*
+ * We need the current boot up configuration to set correct
+ * timings into internal flash and external flash
+ */
+ mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
+ 0 0 -> 8 bit external ROM
+ 0 1 -> 16 bit internal ROM */
+ addi r4,0,2
+ srw r24,r24,r4 /* shift right r24 two positions */
+ andi. r24,r24,0x06000
+/*
+ * All calculations are based on 33MHz EBC clock.
+ *
+ * First, create a "very slow" timing (~250ns) with burst mode enabled
+ * This is need for the external flash access
+ */
+ lis r25,0x0800
+ /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
+ ori r25,r25,0x0280
+/*
+ * Second, create a fast timing:
+ * 90ns first cycle - 3 clock access
+ * and 90ns burst cycle, plus 1 clock after the last access
+ * This is used for the internal access
+ */
+ lis r26,0x8900
+ /* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
+ ori r26,r26,0x0280
+/*
+ * We can't change settings on CS# if we currently use them.
+ * -> load a few instructions into cache and run this code from cache
+ */
+ mflr r4 /* save link register */
+ bl ..getAddr
+..getAddr:
+ mflr r3 /* get address of ..getAddr */
+ mtlr r4 /* restore link register */
+ addi r4,0,14 /* set ctr to 10; used to prefetch */
+ mtctr r4 /* 10 cache lines to fit this function
+ in cache (gives us 8x10=80 instructions) */
+..ebcloop:
+ icbt r0,r3 /* prefetch cache line for addr in r3 */
+ addi r3,r3,32 /* move to next cache line */
+ bdnz ..ebcloop /* continue for 10 cache lines */
+/*
+ * Delay to ensure all accesses to ROM are complete before changing
+ * bank 0 timings. 200usec should be enough.
+ * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+ */
+ lis r3,0x0
+ ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
+ mtctr r3
+..spinlp:
+ bdnz ..spinlp /* spin loop */
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 0 (BOOT-ROM) initialization
+ * 0xFFEF00000....0xFFFFFFF
+ * We only have to change the timing. Mapping is ok by boot-strapping
+ *----------------------------------------------------------------------- */
+
+ li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */
+ mtdcr EBC0_CFGADDR,r4
+
+ mr r4,r26 /* assume internal fast flash is boot flash */
+ cmpwi r24,0x2000 /* assumption true? ... */
+ beq 1f /* ...yes! */
+ mr r4,r25 /* ...no, use the slow variant */
+ mr r25,r26 /* use this for the other flash */
+1:
+ mtdcr EBC0_CFGDATA,r4 /* change timing now */
+
+ li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */
+ mtdcr EBC0_CFGADDR,r4
+ mfdcr r4,EBC0_CFGDATA
+ lis r3,0x0001
+ ori r3,r3,0x8000 /* allow reads and writes */
+ or r4,r4,r3
+ mtdcr EBC0_CFGDATA,r4
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 3 (Second-Flash) initialization
+ * 0xF0000000...0xF01FFFFF -> 2MB
+ *----------------------------------------------------------------------- */
+
+ li r4,PB3AP /* Peripheral Bank 1 Access Parameter */
+ mtdcr EBC0_CFGADDR,r4
+ mtdcr EBC0_CFGDATA,r2 /* change timing */
+
+ li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */
+ mtdcr EBC0_CFGADDR,r4
+
+ lis r4,0xF003
+ ori r4,r4,0x8000
+/*
+ * Consider boot configuration
+ */
+ xori r24,r24,0x2000 /* invert current bus width */
+ or r4,r4,r24
+ mtdcr EBC0_CFGDATA,r4
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 1 (NAND-Flash) initialization
+ * 0x77D00000...0x77DFFFFF -> 1MB
+ * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
+ * - the setup time is 0ns
+ * - the hold time is 15ns
+ * ->
+ * - TWT = 0
+ * - CSN = 0
+ * - OEN = 0
+ * - WBN = 0
+ * - WBF = 0
+ * - TH = 1
+ * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
+ *----------------------------------------------------------------------- */
+
+ li r4,PB1AP /* Peripheral Bank 1 Access Parameter */
+ mtdcr EBC0_CFGADDR,r4
+
+ lis r4,0x0000
+ ori r4,r4,0x0200
+ mtdcr EBC0_CFGDATA,r4
+
+ li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */
+ mtdcr EBC0_CFGADDR,r4
+
+ lis r4,0x77D1
+ ori r4,r4,0x8000
+ mtdcr EBC0_CFGDATA,r4
+
+
+/* USB init (without acceleration) */
+#ifndef CONFIG_ISP1161_PRESENT
+ li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
+ mtdcr EBC0_CFGADDR,r4
+ lis r4,0x0180
+ ori r4,r4,0x5940
+ mtdcr EBC0_CFGDATA,r4
+#endif
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
+ * 0x78000000...0x7BFFFFFF -> 64 MB
+ * Wir arbeiten bei 33 MHz -> 30ns
+ *-----------------------------------------------------------------------
+
+ A7 (ppc notation) or A24 (standard notation) decides about
+ the type of access:
+ A7/A24=0 -> memory cycle
+ A7/ /A24=1 -> I/O cycle
+*/
+ li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */
+ mtdcr EBC0_CFGADDR,r4
+/*
+ We emulate an ISA access
+
+ 1. Address active
+ 2. wait 0 EBC clocks -> CSN=0
+ 3. set CS#
+ 4. wait 0 EBC clock -> OEN/WBN=0
+ 5. set OE#/WE#
+ 6. wait 4 clocks (ca. 90ns) and for Ready signal
+ 7. hold for 4 clocks -> TH=4
+*/
+
+#if 1
+/* faster access to isa-bus */
+ lis r4,0x0180
+ ori r4,r4,0x5940
+#else
+ lis r4,0x0100
+ ori r4,r4,0x0340
+#endif
+ mtdcr EBC0_CFGDATA,r4
+
+#ifdef IDE_USES_ISA_EMULATION
+ li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */
+ mtdcr EBC0_CFGADDR,r25
+ mtdcr EBC0_CFGDATA,r4
+#endif
+
+ li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */
+ mtdcr EBC0_CFGADDR,r25
+ mtdcr EBC0_CFGDATA,r4
+ li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */
+ mtdcr EBC0_CFGADDR,r25
+ mtdcr EBC0_CFGDATA,r4
+
+ li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */
+ mtdcr EBC0_CFGADDR,r25
+
+ lis r4,0x780B
+ ori r4,r4,0xA000
+ mtdcr EBC0_CFGDATA,r4
+/*
+ * the other areas are only 1MiB in size
+ */
+ lis r4,0x7401
+ ori r4,r4,0xA000
+
+ li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */
+ mtdcr EBC0_CFGADDR,r25
+ lis r4,0x7401
+ ori r4,r4,0xA000
+ mtdcr EBC0_CFGDATA,r4
+
+ li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */
+ mtdcr EBC0_CFGADDR,r25
+ lis r4,0x7411
+ ori r4,r4,0xA000
+ mtdcr EBC0_CFGDATA,r4
+
+#ifndef CONFIG_ISP1161_PRESENT
+ li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */
+ mtdcr EBC0_CFGADDR,r25
+ lis r4,0x7421
+ ori r4,r4,0xA000
+ mtdcr EBC0_CFGDATA,r4
+#endif
+#ifdef IDE_USES_ISA_EMULATION
+ li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */
+ mtdcr EBC0_CFGADDR,r25
+ lis r4,0x0000
+ ori r4,r4,0x0000
+ mtdcr EBC0_CFGDATA,r4
+#endif
+
+/*-----------------------------------------------------------------------
+ * Memory bank 4: USB controller Philips ISP6111
+ * 0x77C00000 ... 0x77CFFFFF
+ *
+ * The chip is connected to:
+ * - CPU CS#4
+ * - CPU IRQ#2
+ * - CPU DMA 3
+ *
+ * Timing:
+ * - command to first data: 300ns. Software must ensure this timing!
+ * - Write pulse: 26ns
+ * - Read pulse: 33ns
+ * - read cycle time: 150ns
+ * - write cycle time: 140ns
+ *
+ * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
+ *
+ * |- 300ns --|
+ * |---- 420ns ---|---- 420ns ---| cycle
+ * CS ############:###____#######:###____#######
+ * OE ############:####___#######:####___#######
+ * WE ############:####__########:####__########
+ *
+ * ----> 2 clocks RD/WR pulses: 60ns
+ * ----> CSN: 3 clock, 90ns
+ * ----> OEN: 1 clocks (read cycle)
+ * ----> WBN: 1 clocks (write cycle)
+ * ----> WBE: 2 clocks
+ * ----> TH: 7 clock, 210ns
+ * ----> TWT: 7 clocks
+ *----------------------------------------------------------------------- */
+
+#ifdef CONFIG_ISP1161_PRESENT
+
+ li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
+ mtdcr EBC0_CFGADDR,r4
+
+ lis r4,0x030D
+ ori r4,r4,0x5E80
+ mtdcr EBC0_CFGDATA,r4
+
+ li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */
+ mtdcr EBC0_CFGADDR,r4
+
+ lis r4,0x77C1
+ ori r4,r4,0xA000
+ mtdcr EBC0_CFGDATA,r4
+
+#endif
+
+#ifndef IDE_USES_ISA_EMULATION
+
+/*-----------------------------------------------------------------------
+ * Memory Bank 5 used for IDE access
+ *
+ * Timings for IDE Interface
+ *
+ * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
+ * 70 165 30 PIO-Mode 0, [ns]
+ * 3 6 1 [Cycles] ----> AP=0x040C0200
+ * 50 125 20 PIO-Mode 1, [ns]
+ * 2 5 1 [Cycles] ----> AP=0x03080200
+ * 30 100 15 PIO-Mode 2, [ns]
+ * 1 4 1 [Cycles] ----> AP=0x02040200
+ * 30 80 10 PIO-Mode 3, [ns]
+ * 1 3 1 [Cycles] ----> AP=0x01840200
+ * 25 70 10 PIO-Mode 4, [ns]
+ * 1 3 1 [Cycles] ----> AP=0x01840200
+ *
+ *----------------------------------------------------------------------- */
+
+ li r4,PB5AP
+ mtdcr EBC0_CFGADDR,r4
+ lis r4,0x040C
+ ori r4,r4,0x0200
+ mtdcr EBC0_CFGDATA,r4
+
+ li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */
+ mtdcr EBC0_CFGADDR,r4
+
+ lis r4,0x7A01
+ ori r4,r4,0xA000
+ mtdcr EBC0_CFGDATA,r4
+#endif
+/*
+ * External Peripheral Control Register
+ */
+ li r4,EBC0_CFG
+ mtdcr EBC0_CFGADDR,r4
+
+ lis r4,0xB84E
+ ori r4,r4,0xF000
+ mtdcr EBC0_CFGDATA,r4
+/*
+ * drive POST code
+ */
+ lis r4,0x7900
+ ori r4,r4,0x0080
+ li r3,0x0001
+ stb r3,0(r4) /* 01 -> external bus controller is initialized */
+ nop /* pass2 DCR errata #8 */
+ blr
diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c
new file mode 100644
index 0000000..0216a37
--- /dev/null
+++ b/board/sc3/sc3.c
@@ -0,0 +1,769 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
+ *
+ * (C) Copyright 2003
+ * Juergen Beisert, EuroDesign embedded technologies, info@eurodsn.de
+ * Derived from walnut.c
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "sc3.h"
+#include <pci.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <netdev.h>
+
+#undef writel
+#undef writeb
+#define writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
+#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
+
+/* write only register to configure things in our CPLD */
+#define CPLD_CONTROL_1 0x79000102
+#define CPLD_VERSION 0x79000103
+
+#define IS_CAMERON ((*(unsigned char *)(CPLD_VERSION)== 0x32) ? 1 : 0)
+
+static struct pci_controller hose={0,};
+
+/************************************************************
+ * Standard definition
+ ************************************************************/
+
+/* CPC0_CR0 Function ISA bus
+ - GPIO0
+ - GPIO1 -> Output: NAND-Command Latch Enable
+ - GPIO2 -> Output: NAND Address Latch Enable
+ - GPIO3 -> IRQ input ISA-IRQ #5 (through CPLD)
+ - GPIO4 -> Output: NAND-Chip Enable
+ - GPIO5 -> IRQ input ISA-IRQ#7 (through CPLD)
+ - GPIO6 -> IRQ input ISA-IRQ#9 (through CPLD)
+ - GPIO7 -> IRQ input ISA-IRQ#10 (through CPLD)
+ - GPIO8 -> IRQ input ISA-IRQ#11 (through CPLD)
+ - GPIO9 -> IRQ input ISA-IRQ#12 (through CPLD)
+ - GPIO10/CS1# -> CS1# NAND ISA-CS#0
+ - GPIO11/CS2# -> CS2# ISA emulation ISA-CS#1
+ - GPIO12/CS3# -> CS3# 2nd Flash-Bank ISA-CS#2 or ISA-CS#7
+ - GPIO13/CS4# -> CS4# USB HC or ISA emulation ISA-CS#3
+ - GPIO14/CS5# -> CS5# Boosted IDE access ISA-CS#4
+ - GPIO15/CS6# -> CS6# ISA emulation ISA-CS#5
+ - GPIO16/CS7# -> CS7# ISA emulation ISA-CS#6
+ - GPIO17/IRQ0 -> GPIO, in, NAND-Ready/Busy# line ISA-IRQ#3
+ - GPIO18/IRQ1 -> IRQ input ISA-IRQ#14
+ - GPIO19/IRQ2 -> IRQ input or USB ISA-IRQ#4
+ - GPIO20/IRQ3 -> IRQ input PCI-IRQ#D
+ - GPIO21/IRQ4 -> IRQ input PCI-IRQ#C
+ - GPIO22/IRQ5 -> IRQ input PCI-IRQ#B
+ - GPIO23/IRQ6 -> IRQ input PCI-IRQ#A
+ - GPIO24 -> if GPIO output: 0=JTAG CPLD activ, 1=JTAG CPLD inactiv
+*/
+/*
+| CPLD register: io-space at offset 0x102 (write only)
+| 0
+| 1
+| 2 0=CS#4 USB CS#, 1=ISA or GP bus
+| 3
+| 4
+| 5
+| 6 1=enable faster IDE access
+| 7
+*/
+#define USB_CHIP_ENABLE 0x04
+#define IDE_BOOSTING 0x40
+
+/* --------------- USB stuff ------------------------------------- */
+#ifdef CONFIG_ISP1161_PRESENT
+/**
+ * initUsbHost- Initialize the Philips isp1161 HC part if present
+ * @cpldConfig: Pointer to value in write only CPLD register
+ *
+ * Initialize the USB host controller if present and fills the
+ * scratch register to inform the driver about used resources
+ */
+
+static void initUsbHost (unsigned char *cpldConfig)
+{
+ int i;
+ unsigned long usbBase;
+ /*
+ * Read back where init.S has located the USB chip
+ */
+ mtdcr (0x012, 0x04);
+ usbBase = mfdcr (0x013);
+ if (!(usbBase & 0x18000)) /* enabled? */
+ return;
+ usbBase &= 0xFFF00000;
+
+ /*
+ * to test for the USB controller enable using of CS#4 and DMA 3 for USB access
+ */
+ writeb (*cpldConfig | USB_CHIP_ENABLE,CPLD_CONTROL_1);
+
+ /*
+ * first check: is the controller assembled?
+ */
+ hcWriteWord (usbBase, 0x5555, HcScratch);
+ if (hcReadWord (usbBase, HcScratch) == 0x5555) {
+ hcWriteWord (usbBase, 0xAAAA, HcScratch);
+ if (hcReadWord (usbBase, HcScratch) == 0xAAAA) {
+ if ((hcReadWord (usbBase, HcChipID) & 0xFF00) != 0x6100)
+ return; /* this is not our controller */
+ /*
+ * try a software reset. This needs up to 10 seconds (see datasheet)
+ */
+ hcWriteDWord (usbBase, 0x00000001, HcCommandStatus);
+ for (i = 1000; i > 0; i--) { /* loop up to 10 seconds */
+ udelay (10);
+ if (!(hcReadDWord (usbBase, HcCommandStatus) & 0x01))
+ break;
+ }
+
+ if (!i)
+ return; /* the controller doesn't responding. Broken? */
+ /*
+ * OK. USB controller is ready. Initialize it in such way the later driver
+ * can us it (without any knowing about specific implementation)
+ */
+ hcWriteDWord (usbBase, 0x00000000, HcControl);
+ /*
+ * disable all interrupt sources. Because we
+ * don't know where we come from (hard reset, cold start, soft reset...)
+ */
+ hcWriteDWord (usbBase, 0x8000007D, HcInterruptDisable);
+ /*
+ * our current setup hardware configuration
+ * - every port power supply can switched indepently
+ * - every port can signal overcurrent
+ * - every port is "outside" and the devices are removeable
+ */
+ hcWriteDWord (usbBase, 0x32000902, HcRhDescriptorA);
+ hcWriteDWord (usbBase, 0x00060000, HcRhDescriptorB);
+ /*
+ * don't forget to switch off power supply of each port
+ * The later running driver can reenable them to find and use
+ * the (maybe) connected devices.
+ *
+ */
+ hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus1);
+ hcWriteDWord (usbBase, 0x00000200, HcRhPortStatus2);
+ hcWriteWord (usbBase, 0x0428, HcHardwareConfiguration);
+ hcWriteWord (usbBase, 0x0040, HcDMAConfiguration);
+ hcWriteWord (usbBase, 0x0000, HcuPInterruptEnable);
+ hcWriteWord (usbBase, 0xA000 | (0x03 << 8) | 27, HcScratch);
+ /*
+ * controller is present and usable
+ */
+ *cpldConfig |= USB_CHIP_ENABLE;
+ }
+ }
+}
+#endif
+
+#if defined(CONFIG_START_IDE)
+int board_start_ide(void)
+{
+ if (IS_CAMERON) {
+ puts ("no IDE on cameron board.\n");
+ return 0;
+ }
+ return 1;
+}
+#endif
+
+static int sc3_cameron_init (void)
+{
+ /* Set up the Memory Controller for the CAMERON version */
+ mtebc (PB4AP, 0x01805940);
+ mtebc (PB4CR, 0x7401a000);
+ mtebc (PB5AP, 0x01805940);
+ mtebc (PB5CR, 0x7401a000);
+ mtebc (PB6AP, 0x0);
+ mtebc (PB6CR, 0x0);
+ mtebc (PB7AP, 0x0);
+ mtebc (PB7CR, 0x0);
+ return 0;
+}
+
+void sc3_read_eeprom (void)
+{
+ uchar i2c_buffer[18];
+
+ i2c_read (0x50, 0x03, 1, i2c_buffer, 9);
+ i2c_buffer[9] = 0;
+ setenv ("serial#", (char *)i2c_buffer);
+
+ /* read mac-address from eeprom */
+ i2c_read (0x50, 0x11, 1, i2c_buffer, 15);
+ i2c_buffer[17] = 0;
+ i2c_buffer[16] = i2c_buffer[14];
+ i2c_buffer[15] = i2c_buffer[13];
+ i2c_buffer[14] = ':';
+ i2c_buffer[13] = i2c_buffer[12];
+ i2c_buffer[12] = i2c_buffer[11];
+ i2c_buffer[11] = ':';
+ i2c_buffer[8] = ':';
+ i2c_buffer[5] = ':';
+ i2c_buffer[2] = ':';
+ setenv ("ethaddr", (char *)i2c_buffer);
+}
+
+int board_early_init_f (void)
+{
+ /* write only register to configure things in our CPLD */
+ unsigned char cpldConfig_1=0x00;
+
+/*-------------------------------------------------------------------------+
+| Interrupt controller setup for the SolidCard III CPU card (plus Evaluation board).
+|
+| Note: IRQ 0 UART 0, active high; level sensitive
+| IRQ 1 UART 1, active high; level sensitive
+| IRQ 2 IIC, active high; level sensitive
+| IRQ 3 Ext. master, rising edge, edge sensitive
+| IRQ 4 PCI, active high; level sensitive
+| IRQ 5 DMA Channel 0, active high; level sensitive
+| IRQ 6 DMA Channel 1, active high; level sensitive
+| IRQ 7 DMA Channel 2, active high; level sensitive
+| IRQ 8 DMA Channel 3, active high; level sensitive
+| IRQ 9 Ethernet Wakeup, active high; level sensitive
+| IRQ 10 MAL System Error (SERR), active high; level sensitive
+| IRQ 11 MAL Tx End of Buffer, active high; level sensitive
+| IRQ 12 MAL Rx End of Buffer, active high; level sensitive
+| IRQ 13 MAL Tx Descriptor Error, active high; level sensitive
+| IRQ 14 MAL Rx Descriptor Error, active high; level sensitive
+| IRQ 15 Ethernet, active high; level sensitive
+| IRQ 16 External PCI SERR, active high; level sensitive
+| IRQ 17 ECC Correctable Error, active high; level sensitive
+| IRQ 18 PCI Power Management, active high; level sensitive
+|
+| IRQ 19 (EXT IRQ7 405GPr only)
+| IRQ 20 (EXT IRQ8 405GPr only)
+| IRQ 21 (EXT IRQ9 405GPr only)
+| IRQ 22 (EXT IRQ10 405GPr only)
+| IRQ 23 (EXT IRQ11 405GPr only)
+| IRQ 24 (EXT IRQ12 405GPr only)
+|
+| IRQ 25 (EXT IRQ 0) NAND-Flash R/B# (raising edge means flash is ready)
+| IRQ 26 (EXT IRQ 1) IDE0 interrupt (x86 = IRQ14). Active high (edge sensitive)
+| IRQ 27 (EXT IRQ 2) USB controller
+| IRQ 28 (EXT IRQ 3) INT D, VGA; active low; level sensitive
+| IRQ 29 (EXT IRQ 4) INT C, Ethernet; active low; level sensitive
+| IRQ 30 (EXT IRQ 5) INT B, PC104+ SLOT; active low; level sensitive
+| IRQ 31 (EXT IRQ 6) INT A, PC104+ SLOT; active low; level sensitive
+|
+| Direct Memory Access Controller Signal Polarities
+| DRQ0 active high (like ISA)
+| ACK0 active low (like ISA)
+| EOT0 active high (like ISA)
+| DRQ1 active high (like ISA)
+| ACK1 active low (like ISA)
+| EOT1 active high (like ISA)
+| DRQ2 active high (like ISA)
+| ACK2 active low (like ISA)
+| EOT2 active high (like ISA)
+| DRQ3 active high (like ISA)
+| ACK3 active low (like ISA)
+| EOT3 active high (like ISA)
+|
++-------------------------------------------------------------------------*/
+
+ writeb (cpldConfig_1, CPLD_CONTROL_1); /* disable everything in CPLD */
+
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
+
+ if (IS_CAMERON) {
+ sc3_cameron_init();
+ mtdcr (0x0B6, 0x18000000);
+ mtdcr (UIC0PR, 0xFFFFFFF0);
+ mtdcr (UIC0TR, 0x10001030);
+ } else {
+ mtdcr (0x0B6, 0x0000000);
+ mtdcr (UIC0PR, 0xFFFFFFE0);
+ mtdcr (UIC0TR, 0x10000020);
+ }
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+ /* setup other implementation specific details */
+ mtdcr (CPC0_ECR, 0x60606000);
+
+ mtdcr (CPC0_CR1, 0x000042C0);
+
+ if (IS_CAMERON) {
+ mtdcr (CPC0_CR0, 0x01380000);
+ /* Setup the GPIOs */
+ writel (0x08008000, 0xEF600700); /* Output states */
+ writel (0x00000000, 0xEF600718); /* Open Drain control */
+ writel (0x68098000, 0xEF600704); /* Output control */
+ } else {
+ mtdcr (CPC0_CR0,0x00080000);
+ /* Setup the GPIOs */
+ writel (0x08000000, 0xEF600700); /* Output states */
+ writel (0x14000000, 0xEF600718); /* Open Drain control */
+ writel (0x7C000000, 0xEF600704); /* Output control */
+ }
+
+ /* Code decompression disabled */
+ mtdcr (DCP0_CFGADDR, KCONF);
+ mtdcr (DCP0_CFGDATA, 0x2B);
+
+ /* CPC0_ER: enable sleep mode of (currently) unused components */
+ /* CPC0_FR: force unused components into sleep mode */
+ mtdcr (CPC0_ER, 0x3F800000);
+ mtdcr (CPC0_FR, 0x14000000);
+
+ /* set PLB priority */
+ mtdcr (PLB0_ACR, 0x08000000);
+
+ /* --------------- DMA stuff ------------------------------------- */
+ mtdcr (0x126, 0x49200000);
+
+#ifndef IDE_USES_ISA_EMULATION
+ cpldConfig_1 |= IDE_BOOSTING; /* enable faster IDE */
+ /* cpldConfig |= 0x01; */ /* enable 8.33MHz output, if *not* present on your baseboard */
+ writeb (cpldConfig_1, CPLD_CONTROL_1);
+#endif
+
+#ifdef CONFIG_ISP1161_PRESENT
+ initUsbHost (&cpldConfig_1);
+ writeb (cpldConfig_1, CPLD_CONTROL_1);
+#endif
+ /* FIXME: for what must we do this */
+ *(unsigned long *)0x79000080 = 0x0001;
+ return(0);
+}
+
+int misc_init_r (void)
+{
+ char *s1;
+ int i, xilinx_val;
+ volatile char *xilinx_adr;
+ xilinx_adr = (char *)0x79000102;
+
+ *xilinx_adr = 0x00;
+
+/* customer settings ***************************************** */
+/*
+ s1 = getenv ("function");
+ if (s1) {
+ if (!strcmp (s1, "Rosho")) {
+ printf ("function 'Rosho' activated\n");
+ *xilinx_adr = 0x40;
+ }
+ else {
+ printf (">>>>>>>>>> function %s not recognized\n",s1);
+ }
+ }
+*/
+
+/* individual settings ***************************************** */
+ if ((s1 = getenv ("xilinx"))) {
+ i=0;
+ xilinx_val = 0;
+ while (i < 3 && s1[i]) {
+ if (s1[i] >= '0' && s1[i] <= '9')
+ xilinx_val = (xilinx_val << 4) + s1[i] - '0';
+ else
+ if (s1[i] >= 'A' && s1[i] <= 'F')
+ xilinx_val = (xilinx_val << 4) + s1[i] - 'A' + 10;
+ else
+ if (s1[i] >= 'a' && s1[i] <= 'f')
+ xilinx_val = (xilinx_val << 4) + s1[i] - 'a' + 10;
+ else {
+ xilinx_val = -1;
+ break;
+ }
+ i++;
+ }
+ if (xilinx_val >= 0 && xilinx_val <=255 && i < 3) {
+ printf ("Xilinx: set to %s\n", s1);
+ *xilinx_adr = (unsigned char) xilinx_val;
+ } else
+ printf ("Xilinx: rejected value %s\n", s1);
+ }
+ return 0;
+}
+
+/* -------------------------------------------------------------------------
+ * printCSConfig
+ *
+ * Print some informations about chips select configurations
+ * Only used while debugging.
+ *
+ * Params:
+ * - No. of CS pin
+ * - AP of this CS
+ * - CR of this CS
+ *
+ * Returns
+ * nothing
+ ------------------------------------------------------------------------- */
+
+#ifdef SC3_DEBUGOUT
+static void printCSConfig(int reg,unsigned long ap,unsigned long cr)
+{
+ const char *bsize[4] = {"8","16","32","?"};
+ const unsigned char banks[8] = {1, 2, 4, 8, 16, 32, 64, 128};
+ const char *bankaccess[4] = {"disabled", "RO", "WO", "RW"};
+
+#define CYCLE 30 /* time of one clock (based on 33MHz) */
+
+ printf("\nCS#%d",reg);
+ if (!(cr & 0x00018000))
+ puts(" unused");
+ else {
+ if (((cr&0xFFF00000U) & ((banks[(cr & 0x000E0000) >> 17]-1) << 20)))
+ puts(" Address is not multiple of bank size!");
+
+ printf("\n -%s bit device",
+ bsize[(cr & 0x00006000) >> 13]);
+ printf(" at 0x%08lX", cr & 0xFFF00000U);
+ printf(" size: %u MB", banks[(cr & 0x000E0000) >> 17]);
+ printf(" rights: %s", bankaccess[(cr & 0x00018000) >> 15]);
+ if (ap & 0x80000000) {
+ printf("\n -Burst device (%luns/%luns)",
+ (((ap & 0x7C000000) >> 26) + 1) * CYCLE,
+ (((ap & 0x03800000) >> 23) + 1) * CYCLE);
+ } else {
+ printf("\n -Non burst device, active cycle %luns",
+ (((ap & 0x7F800000) >> 23) + 1) * CYCLE);
+ printf("\n -Address setup %luns",
+ ((ap & 0xC0000) >> 18) * CYCLE);
+ printf("\n -CS active to RD %luns/WR %luns",
+ ((ap & 0x30000) >> 16) * CYCLE,
+ ((ap & 0xC000) >> 14) * CYCLE);
+ printf("\n -WR to CS inactive %luns",
+ ((ap & 0x3000) >> 12) * CYCLE);
+ printf("\n -Hold after access %luns",
+ ((ap & 0xE00) >> 9) * CYCLE);
+ printf("\n -Ready is %sabled",
+ ap & 0x100 ? "en" : "dis");
+ }
+ }
+}
+#endif
+
+#ifdef SC3_DEBUGOUT
+
+static unsigned int ap[] = {PB0AP, PB1AP, PB2AP, PB3AP, PB4AP,
+ PB5AP, PB6AP, PB7AP};
+static unsigned int cr[] = {PB0CR, PB1CR, PB2CR, PB3CR, PB4CR,
+ PB5CR, PB6CR, PB7CR};
+
+static int show_reg (int nr)
+{
+ unsigned long ul1, ul2;
+
+ mtdcr (EBC0_CFGADDR, ap[nr]);
+ ul1 = mfdcr (EBC0_CFGDATA);
+ mtdcr (EBC0_CFGADDR, cr[nr]);
+ ul2 = mfdcr(EBC0_CFGDATA);
+ printCSConfig(nr, ul1, ul2);
+ return 0;
+}
+#endif
+
+int checkboard (void)
+{
+#ifdef SC3_DEBUGOUT
+ unsigned long ul1;
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ show_reg (i);
+ }
+
+ mtdcr (EBC0_CFGADDR, EBC0_CFG);
+ ul1 = mfdcr (EBC0_CFGDATA);
+
+ puts ("\nGeneral configuration:\n");
+
+ if (ul1 & 0x80000000)
+ printf(" -External Bus is always driven\n");
+
+ if (ul1 & 0x400000)
+ printf(" -CS signals are always driven\n");
+
+ if (ul1 & 0x20000)
+ printf(" -PowerDown after %lu clocks\n",
+ (ul1 & 0x1F000) >> 7);
+
+ switch (ul1 & 0xC0000)
+ {
+ case 0xC0000:
+ printf(" -No external master present\n");
+ break;
+ case 0x00000:
+ printf(" -8 bit external master present\n");
+ break;
+ case 0x40000:
+ printf(" -16 bit external master present\n");
+ break;
+ case 0x80000:
+ printf(" -32 bit external master present\n");
+ break;
+ }
+
+ switch (ul1 & 0x300000)
+ {
+ case 0x300000:
+ printf(" -Prefetch: Illegal setting!\n");
+ break;
+ case 0x000000:
+ printf(" -1 doubleword prefetch\n");
+ break;
+ case 0x100000:
+ printf(" -2 doublewords prefetch\n");
+ break;
+ case 0x200000:
+ printf(" -4 doublewords prefetch\n");
+ break;
+ }
+ putc ('\n');
+#endif
+ printf("Board: SolidCard III %s %s version.\n",
+ (IS_CAMERON ? "Cameron" : "Eurodesign"), CONFIG_SC3_VERSION);
+ return 0;
+}
+
+static int printSDRAMConfig(char reg, unsigned long cr)
+{
+ const int bisize[8]={4, 8, 16, 32, 64, 128, 256, 0};
+#ifdef SC3_DEBUGOUT
+ const char *basize[8]=
+ {"4", "8", "16", "32", "64", "128", "256", "Reserved"};
+
+ printf("SDRAM bank %d",reg);
+
+ if (!(cr & 0x01))
+ puts(" disabled\n");
+ else {
+ printf(" at 0x%08lX, size %s MB",cr & 0xFFC00000,basize[(cr&0xE0000)>>17]);
+ printf(" mode %lu\n",((cr & 0xE000)>>13)+1);
+ }
+#endif
+
+ if (cr & 0x01)
+ return(bisize[(cr & 0xE0000) >> 17]);
+
+ return 0;
+}
+
+#ifdef SC3_DEBUGOUT
+static unsigned int mbcf[] = {SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR};
+#endif
+
+phys_size_t initdram (int board_type)
+{
+ unsigned int mems=0;
+ unsigned long ul1;
+
+#ifdef SC3_DEBUGOUT
+ unsigned long ul2;
+ int i;
+
+ puts("\nSDRAM configuration:\n");
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
+ ul1 = mfdcr(SDRAM0_CFGDATA);
+
+ if (!(ul1 & 0x80000000)) {
+ puts(" Controller disabled\n");
+ return 0;
+ }
+ for (i = 0; i < 4; i++) {
+ mtdcr (SDRAM0_CFGADDR, mbcf[i]);
+ ul1 = mfdcr (SDRAM0_CFGDATA);
+ mems += printSDRAMConfig (i, ul1);
+ }
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
+ ul1 = mfdcr(SDRAM0_CFGDATA);
+
+ printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1);
+ printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1);
+ printf (" -R/W to Precharge %lu (CTP)\n", ((ul1 & 0x30000) >> 16) + 1);
+ printf (" -Leadoff %lu\n", ((ul1 & 0xC000) >> 14) + 1);
+ printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4);
+ printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1));
+ puts ("Misc:\n");
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
+ ul1 = mfdcr(SDRAM0_CFGDATA);
+ printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7);
+
+ mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT);
+ ul2=mfdcr(SDRAM0_CFGDATA);
+
+ mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG);
+ ul1=mfdcr(SDRAM0_CFGDATA);
+
+ if (ul1 & 0x20000000)
+ printf(" -Power Down after: %luns\n",
+ ((ul2 & 0xFFC00000) >> 22) * 7);
+ else
+ puts(" -Power Down disabled\n");
+
+ if (ul1 & 0x40000000)
+ printf(" -Self refresh feature active\n");
+ else
+ puts(" -Self refresh disabled\n");
+
+ if (ul1 & 0x10000000)
+ puts(" -ECC enabled\n");
+ else
+ puts(" -ECC disabled\n");
+
+ if (ul1 & 0x8000000)
+ puts(" -Using registered SDRAM\n");
+
+ if (!(ul1 & 0x6000000))
+ puts(" -Using 32 bit data width\n");
+ else
+ puts(" -Illegal data width!\n");
+
+ if (ul1 & 0x400000)
+ puts(" -ECC drivers inactive\n");
+ else
+ puts(" -ECC drivers active\n");
+
+ if (ul1 & 0x200000)
+ puts(" -Memory lines always active outputs\n");
+ else
+ puts(" -Memory lines only at write cycles active outputs\n");
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_STATUS);
+ ul1 = mfdcr (SDRAM0_CFGDATA);
+ if (ul1 & 0x80000000)
+ puts(" -SDRAM Controller ready\n");
+ else
+ puts(" -SDRAM Controller not ready\n");
+
+ if (ul1 & 0x4000000)
+ puts(" -SDRAM in self refresh mode!\n");
+
+ return (mems * 1024 * 1024);
+#else
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+ ul1 = mfdcr (SDRAM0_CFGDATA);
+ mems = printSDRAMConfig (0, ul1);
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+ ul1 = mfdcr (SDRAM0_CFGDATA);
+ mems += printSDRAMConfig (1, ul1);
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+ ul1 = mfdcr(SDRAM0_CFGDATA);
+ mems += printSDRAMConfig (2, ul1);
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+ ul1 = mfdcr(SDRAM0_CFGDATA);
+ mems += printSDRAMConfig (3, ul1);
+
+ return (mems * 1024 * 1024);
+#endif
+}
+
+static void pci_solidcard3_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+/*-------------------------------------------------------------------------+
+ | ,-. ,-. ,-. ,-. ,-.
+ | INTD# ----|B|-----|P|-. ,-|P|-. ,-| |-. ,-|G|
+ | |R| |C| \ / |C| \ / |E| \ / |r|
+ | INTC# ----|I|-----|1|-. `/---|1|-. `/---|t|-. `/---|a|
+ | |D| |0| \/ |0| \/ |h| \/ |f|
+ | INTB# ----|G|-----|4|-./`----|4|-./`----|e|-./`----|i|
+ | |E| |+| /\ |+| /\ |r| /\ |k|
+ | INTA# ----| |-----| |- `----| |- `----| |- `----| |
+ | `-' `-' `-' `-' `-'
+ | Slot 0 10 11 12 13
+ | REQ# 0 1 2 *
+ | GNT# 0 1 2 *
+ +-------------------------------------------------------------------------*/
+ unsigned char int_line = 0xff;
+
+ switch (PCI_DEV(dev)) {
+ case 10:
+ int_line = 31; /* INT A */
+ POST_OUT(0x42);
+ break;
+
+ case 11:
+ int_line = 30; /* INT B */
+ POST_OUT(0x43);
+ break;
+
+ case 12:
+ int_line = 29; /* INT C */
+ POST_OUT(0x44);
+ break;
+
+ case 13:
+ int_line = 28; /* INT D */
+ POST_OUT(0x45);
+ break;
+ }
+ pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+extern void pci_405gp_init(struct pci_controller *hose);
+extern void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev);
+extern void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,struct pci_config_table *entry);
+/*
+ * The following table is used when there is a special need to setup a PCI device.
+ * For every PCI device found in this table is called the given init function with given
+ * parameters. So never let all IDs at PCI_ANY_ID. In this case any found device gets the same
+ * parameters!
+ *
+*/
+static struct pci_config_table pci_solidcard3_config_table[] =
+{
+/* Host to PCI Bridge device (405GP) */
+ {
+ vendor: 0x1014,
+ device: 0x0156,
+ class: PCI_CLASS_BRIDGE_HOST,
+ bus: 0,
+ dev: 0,
+ func: 0,
+ config_device: pci_405gp_setup_bridge
+ },
+ { }
+};
+
+/*-------------------------------------------------------------------------+
+ | pci_init_board (Called from pci_init() in drivers/pci/pci.c)
+ |
+ | Init the PCI part of the SolidCard III
+ |
+ | Params:
+ * - Pointer to current PCI hose
+ * - Current Device
+ *
+ * Returns
+ * nothing
+ +-------------------------------------------------------------------------*/
+
+void pci_init_board(void)
+{
+ POST_OUT(0x41);
+/*
+ * we want the ptrs to RAM not flash (ie don't use init list)
+ */
+ hose.fixup_irq = pci_solidcard3_fixup_irq;
+ hose.config_table = pci_solidcard3_config_table;
+ pci_405gp_init(&hose);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
diff --git a/board/sc3/sc3.h b/board/sc3/sc3.h
new file mode 100644
index 0000000..7178cd0
--- /dev/null
+++ b/board/sc3/sc3.h
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/**
+ * hcWriteWord - write a 16 bit value into the USB controller
+ * @base: base address to access the chip registers
+ * @value: 16 bit value to write into register @offset
+ * @offset: register to write the @value into
+ *
+ */
+static void inline hcWriteWord (unsigned long base, unsigned int value,
+ unsigned int offset)
+{
+ out_le16 ((volatile u16*)(base + 2), offset | 0x80);
+ out_le16 ((volatile u16*)base, value);
+}
+
+/**
+ * hcWriteDWord - write a 32 bit value into the USB controller
+ * @base: base address to access the chip registers
+ * @value: 32 bit value to write into register @offset
+ * @offset: register to write the @value into
+ *
+ */
+
+static void inline hcWriteDWord (unsigned long base, unsigned long value,
+ unsigned int offset)
+{
+ out_le16 ((volatile u16*)(base + 2), offset | 0x80);
+ out_le16 ((volatile u16*)base, value);
+ out_le16 ((volatile u16*)base, value >> 16);
+}
+
+/**
+ * hcReadWord - read a 16 bit value from the USB controller
+ * @base: base address to access the chip registers
+ * @offset: register to read from
+ *
+ * Returns the readed register value
+ */
+
+static unsigned int inline hcReadWord (unsigned long base, unsigned int offset)
+{
+ out_le16 ((volatile u16*)(base + 2), offset);
+ return (in_le16 ((volatile u16*)base));
+}
+
+/**
+ * hcReadDWord - read a 32 bit value from the USB controller
+ * @base: base address to access the chip registers
+ * @offset: register to read from
+ *
+ * Returns the readed register value
+ */
+
+static unsigned long inline hcReadDWord (unsigned long base, unsigned int offset)
+{
+ unsigned long val, val16;
+
+ out_le16 ((volatile u16*)(base + 2), offset);
+ val = in_le16((volatile u16*)base);
+ val16 = in_le16((volatile u16*)base);
+ return (val | (val16 << 16));
+}
+
+/* control and status registers isp1161 */
+#define HcRevision 0x00
+#define HcControl 0x01
+#define HcCommandStatus 0x02
+#define HcInterruptStatus 0x03
+#define HcInterruptEnable 0x04
+#define HcInterruptDisable 0x05
+#define HcFmInterval 0x0D
+#define HcFmRemaining 0x0E
+#define HcFmNumber 0x0F
+#define HcLSThreshold 0x11
+#define HcRhDescriptorA 0x12
+#define HcRhDescriptorB 0x13
+#define HcRhStatus 0x14
+#define HcRhPortStatus1 0x15
+#define HcRhPortStatus2 0x16
+
+#define HcHardwareConfiguration 0x20
+#define HcDMAConfiguration 0x21
+#define HcTransferCounter 0x22
+#define HcuPInterrupt 0x24
+#define HcuPInterruptEnable 0x25
+#define HcChipID 0x27
+#define HcScratch 0x28
+#define HcSoftwareReset 0x29
+#define HcITLBufferLength 0x2A
+#define HcATLBufferLength 0x2B
+#define HcBufferStatus 0x2C
+#define HcReadBackITL0Length 0x2D
+#define HcReadBackITL1Length 0x2E
+#define HcITLBufferPort 0x40
+#define HcATLBufferPort 0x41
diff --git a/board/sc3/sc3nand.c b/board/sc3/sc3nand.c
new file mode 100644
index 0000000..a26cd79
--- /dev/null
+++ b/board/sc3/sc3nand.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <nand.h>
+#include <asm/processor.h>
+
+#define readb(addr) *(volatile u_char *)(addr)
+#define readl(addr) *(volatile u_long *)(addr)
+#define writeb(d,addr) *(volatile u_char *)(addr) = (d)
+
+#define SC3_NAND_ALE 29 /* GPIO PIN 3 */
+#define SC3_NAND_CLE 30 /* GPIO PIN 2 */
+#define SC3_NAND_CE 27 /* GPIO PIN 5 */
+
+static void *sc3_io_base;
+static void *sc3_control_base = (void *)0xEF600700;
+
+static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if ( ctrl & NAND_CLE )
+ set_bit (SC3_NAND_CLE, sc3_control_base);
+ else
+ clear_bit (SC3_NAND_CLE, sc3_control_base);
+ if ( ctrl & NAND_ALE )
+ set_bit (SC3_NAND_ALE, sc3_control_base);
+ else
+ clear_bit (SC3_NAND_ALE, sc3_control_base);
+ if ( ctrl & NAND_NCE )
+ set_bit (SC3_NAND_CE, sc3_control_base);
+ else
+ clear_bit (SC3_NAND_CE, sc3_control_base);
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+static int sc3_nand_dev_ready(struct mtd_info *mtd)
+{
+ if (!(readl(sc3_control_base + 0x1C) & 0x4000))
+ return 0;
+ return 1;
+}
+
+static void sc3_select_chip(struct mtd_info *mtd, int chip)
+{
+ clear_bit (SC3_NAND_CE, sc3_control_base);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ nand->ecc.mode = NAND_ECC_SOFT;
+
+ sc3_io_base = (void *) CONFIG_SYS_NAND_BASE;
+ /* Set address of NAND IO lines (Using Linear Data Access Region) */
+ nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
+ nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
+ /* Reference hardware control function */
+ nand->cmd_ctrl = sc3_nand_hwcontrol;
+ nand->dev_ready = sc3_nand_dev_ready;
+ nand->select_chip = sc3_select_chip;
+ return 0;
+}
+#endif
diff --git a/board/scb9328/Kconfig b/board/scb9328/Kconfig
new file mode 100644
index 0000000..68e99ea
--- /dev/null
+++ b/board/scb9328/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SCB9328
+
+config SYS_BOARD
+ default "scb9328"
+
+config SYS_SOC
+ default "imx"
+
+config SYS_CONFIG_NAME
+ default "scb9328"
+
+endif
diff --git a/board/scb9328/MAINTAINERS b/board/scb9328/MAINTAINERS
new file mode 100644
index 0000000..0917266
--- /dev/null
+++ b/board/scb9328/MAINTAINERS
@@ -0,0 +1,6 @@
+SCB9328 BOARD
+M: Torsten Koschorrek <koschorrek@synertronixx.de>
+S: Maintained
+F: board/scb9328/
+F: include/configs/scb9328.h
+F: configs/scb9328_defconfig
diff --git a/board/scb9328/Makefile b/board/scb9328/Makefile
new file mode 100644
index 0000000..0b08f1a
--- /dev/null
+++ b/board/scb9328/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := scb9328.o flash.o
+obj-y += lowlevel_init.o
diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c
new file mode 100644
index 0000000..73bfa00
--- /dev/null
+++ b/board/scb9328/flash.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright (C) 2003 ETC s.r.o.
+ *
+ * This code was inspired by Marius Groeger and Kyle Harris code
+ * available in other board ports for U-Boot
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Written by Peter Figuli <peposh@etc.sk>, 2003.
+ */
+
+#include <common.h>
+#include "intel.h"
+
+
+/*
+ * This code should handle CFI FLASH memory device. This code is very
+ * minimalistic approach without many essential error handling code as well.
+ * Because U-Boot actually is missing smart handling of FLASH device,
+ * we just set flash_id to anything else to FLASH_UNKNOW, so common code
+ * can call us without any restrictions.
+ * TODO: Add CFI Query, to be able to determine FLASH device.
+ * TODO: Add error handling code
+ * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
+ * hopefully may work with other configurations.
+ */
+
+#if ( SCB9328_FLASH_BUS_WIDTH == 1 )
+# define FLASH_BUS vu_char
+# define FLASH_BUS_RET u_char
+# if ( SCB9328_FLASH_INTERLEAVE == 1 )
+# define FLASH_CMD( x ) x
+# else
+# error "With 8bit bus only one chip is allowed"
+# endif
+
+
+#elif ( SCB9328_FLASH_BUS_WIDTH == 2 )
+# define FLASH_BUS vu_short
+# define FLASH_BUS_RET u_short
+# if ( SCB9328_FLASH_INTERLEAVE == 1 )
+# define FLASH_CMD( x ) x
+# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
+# define FLASH_CMD( x ) (( x << 8 )| x )
+# else
+# error "With 16bit bus only 1 or 2 chip(s) are allowed"
+# endif
+
+
+#elif ( SCB9328_FLASH_BUS_WIDTH == 4 )
+# define FLASH_BUS vu_long
+# define FLASH_BUS_RET u_long
+# if ( SCB9328_FLASH_INTERLEAVE == 1 )
+# define FLASH_CMD( x ) x
+# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
+# define FLASH_CMD( x ) (( x << 16 )| x )
+# elif ( SCB9328_FLASH_INTERLEAVE == 4 )
+# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
+# else
+# error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
+# endif
+
+#else
+# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
+#endif
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+static FLASH_BUS_RET flash_status_reg (void)
+{
+
+ FLASH_BUS *addr = (FLASH_BUS *) 0;
+
+ /* cppcheck-suppress nullPointer */
+ *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
+
+ /* cppcheck-suppress nullPointer */
+ return *addr;
+}
+
+static int flash_ready (ulong timeout)
+{
+ int ok = 1;
+ ulong start;
+
+ start = get_timer(0);
+ while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
+ FLASH_CMD (CFI_INTEL_SR_READY)) {
+ if (get_timer(start) > timeout && timeout != 0) {
+ ok = 0;
+ break;
+ }
+ }
+ return ok;
+}
+
+#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
+# error "SCB9328 platform has only one flash bank!"
+#endif
+
+
+ulong flash_init (void)
+{
+ int i;
+ unsigned long address = SCB9328_FLASH_BASE;
+
+ flash_info[0].size = SCB9328_FLASH_BANK_SIZE;
+ flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ flash_info[0].flash_id = INTEL_MANUFACT;
+ memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
+ flash_info[0].start[i] = address;
+#ifdef SCB9328_FLASH_UNLOCK
+ /* Some devices are hw locked after start. */
+ *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
+ *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
+ flash_ready (0);
+ *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+#endif
+ address += SCB9328_FLASH_SECT_SIZE;
+ }
+
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+ &flash_info[0]);
+
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+
+ return SCB9328_FLASH_BANK_SIZE;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ printf (" Intel vendor\n");
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+ if (!(i % 5)) {
+ printf ("\n");
+ }
+
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+}
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ int flag, non_protected = 0, sector;
+ int rc = ERR_OK;
+
+ FLASH_BUS *address;
+
+ for (sector = s_first; sector <= s_last; sector++) {
+ if (!info->protect[sector]) {
+ non_protected++;
+ }
+ }
+
+ if (!non_protected) {
+ return ERR_PROTECTED;
+ }
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ flag = disable_interrupts ();
+
+
+ /* Start erase on unprotected sectors */
+ for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
+ if (info->protect[sector]) {
+ printf ("Protected sector %2d skipping...\n", sector);
+ continue;
+ } else {
+ printf ("Erasing sector %2d ... ", sector);
+ }
+
+ address = (FLASH_BUS *) (info->start[sector]);
+
+ *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
+ *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
+ if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
+ *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
+ printf ("ok.\n");
+ } else {
+ *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
+ rc = ERR_TIMOUT;
+ printf ("timeout! Aborting...\n");
+ break;
+ }
+ *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+ }
+ if (ctrlc ())
+ printf ("User Interrupt!\n");
+
+ /* allow flash to settle - wait 10 ms */
+ udelay_masked (10000);
+ if (flag) {
+ enable_interrupts ();
+ }
+
+ return rc;
+}
+
+static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
+{
+ FLASH_BUS *address = (FLASH_BUS *) dest;
+ int rc = ERR_OK;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*address & data) != data) {
+ return ERR_NOT_ERASED;
+ }
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+
+ flag = disable_interrupts ();
+
+ *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
+ *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
+ *address = data;
+
+ if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
+ *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
+ rc = ERR_TIMOUT;
+ printf ("timeout! Aborting...\n");
+ }
+
+ *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+ if (flag) {
+ enable_interrupts ();
+ }
+
+ return rc;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong read_addr, write_addr;
+ FLASH_BUS data;
+ int i, result = ERR_OK;
+
+
+ read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
+ write_addr = read_addr;
+ if (read_addr != addr) {
+ data = 0;
+ for (i = 0; i < sizeof (FLASH_BUS); i++) {
+ if (read_addr < addr || cnt == 0) {
+ data |= *((uchar *) read_addr) << i * 8;
+ } else {
+ data |= (*src++) << i * 8;
+ cnt--;
+ }
+ read_addr++;
+ }
+ if ((result = write_data (info, write_addr, data)) != ERR_OK) {
+ return result;
+ }
+ write_addr += sizeof (FLASH_BUS);
+ }
+ for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
+ if ((result = write_data (info, write_addr,
+ *((FLASH_BUS *) src))) != ERR_OK) {
+ return result;
+ }
+ write_addr += sizeof (FLASH_BUS);
+ src += sizeof (FLASH_BUS);
+ }
+ if (cnt > 0) {
+ read_addr = write_addr;
+ data = 0;
+ for (i = 0; i < sizeof (FLASH_BUS); i++) {
+ if (cnt > 0) {
+ data |= (*src++) << i * 8;
+ cnt--;
+ } else {
+ data |= *((uchar *) read_addr) << i * 8;
+ }
+ read_addr++;
+ }
+ if ((result = write_data (info, write_addr, data)) != 0) {
+ return result;
+ }
+ }
+ return ERR_OK;
+}
diff --git a/board/scb9328/intel.h b/board/scb9328/intel.h
new file mode 100644
index 0000000..5596d27
--- /dev/null
+++ b/board/scb9328/intel.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2002 ETC s.r.o.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Written by Marcel Telka <marcel@telka.sk>, 2002.
+ *
+ * Documentation:
+ * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
+ * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
+ * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
+ * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
+ *
+ * This file is taken from OpenWinCE project hosted by SourceForge.net
+ *
+ */
+
+#ifndef FLASH_INTEL_H
+#define FLASH_INTEL_H
+
+#include <common.h>
+
+/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
+
+#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
+
+/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
+
+#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
+
+/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
+
+#define CFI_CHIP_INTEL_28F320J3A 0x0016
+#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
+#define CFI_CHIP_INTEL_28F640J3A 0x0017
+#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
+#define CFI_CHIP_INTEL_28F128J3A 0x0018
+#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
+
+/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
+
+#define CFI_CHIP_INTEL_28F640K3 0x8801
+#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
+#define CFI_CHIP_INTEL_28F128K3 0x8802
+#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
+#define CFI_CHIP_INTEL_28F256K3 0x8803
+#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
+#define CFI_CHIP_INTEL_28F640K18 0x8805
+#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
+#define CFI_CHIP_INTEL_28F128K18 0x8806
+#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
+#define CFI_CHIP_INTEL_28F256K18 0x8807
+#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
+
+#endif /* FLASH_INTEL_H */
diff --git a/board/scb9328/lowlevel_init.S b/board/scb9328/lowlevel_init.S
new file mode 100644
index 0000000..2475ae8
--- /dev/null
+++ b/board/scb9328/lowlevel_init.S
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx-regs.h>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ mov r10, lr
+
+/* Change PERCLK1DIV to 14 ie 14+1 */
+ ldr r0, =PCDR
+ ldr r1, =CONFIG_SYS_PCDR_VAL
+ str r1, [r0]
+
+/* set MCU PLL Control Register 0 */
+
+ ldr r0, =MPCTL0
+ ldr r1, =CONFIG_SYS_MPCTL0_VAL
+ str r1, [r0]
+
+/* set mpll restart bit */
+ ldr r0, =CSCR
+ ldr r1, [r0]
+ orr r1,r1,#(1<<21)
+ str r1, [r0]
+
+ mov r2,#0x10
+1:
+ mov r3,#0x2000
+2:
+ subs r3,r3,#1
+ bne 2b
+
+ subs r2,r2,#1
+ bne 1b
+
+/* set System PLL Control Register 0 */
+
+ ldr r0, =SPCTL0
+ ldr r1, =CONFIG_SYS_SPCTL0_VAL
+ str r1, [r0]
+
+/* set spll restart bit */
+ ldr r0, =CSCR
+ ldr r1, [r0]
+ orr r1,r1,#(1<<22)
+ str r1, [r0]
+
+ mov r2,#0x10
+1:
+ mov r3,#0x2000
+2:
+ subs r3,r3,#1
+ bne 2b
+
+ subs r2,r2,#1
+ bne 1b
+
+ ldr r0, =CSCR
+ ldr r1, =CONFIG_SYS_CSCR_VAL
+ str r1, [r0]
+
+/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
+ *this.....
+ *
+ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
+ * register 1, this stops it using the output of the PLL and thus runs at the
+ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
+ * use the value set in the CM_OSC registers...regardless of what you set it
+ * too! Thus, although i thought i was running at 140MHz, i'm actually running
+ * at 40!..
+
+ * Slapping this into my bootloader does the trick...
+
+ * MRC p15,0,r0,c1,c0,0 ; read core configuration register
+ * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
+ * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
+ * register
+ */
+ MRC p15,0,r0,c1,c0,0
+ ORR r0,r0,#0xC0000000
+ MCR p15,0,r0,c1,c0,0
+
+ ldr r0, =GPR(0)
+ ldr r1, =CONFIG_SYS_GPR_A_VAL
+ str r1, [r0]
+
+ ldr r0, =GIUS(0)
+ ldr r1, =CONFIG_SYS_GIUS_A_VAL
+ str r1, [r0]
+
+/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
+
+ ldr r0, =FMCR
+ ldr r1, =CONFIG_SYS_FMCR_VAL
+ str r1, [r0]
+
+ ldr r0, =CS0U
+ ldr r1, =CONFIG_SYS_CS0U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS0L
+ ldr r1, =CONFIG_SYS_CS0L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS1U
+ ldr r1, =CONFIG_SYS_CS1U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS1L
+ ldr r1, =CONFIG_SYS_CS1L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS2U
+ ldr r1, =CONFIG_SYS_CS2U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS2L
+ ldr r1, =CONFIG_SYS_CS2L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS3U
+ ldr r1, =CONFIG_SYS_CS3U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS3L
+ ldr r1, =CONFIG_SYS_CS3L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS4U
+ ldr r1, =CONFIG_SYS_CS4U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS4L
+ ldr r1, =CONFIG_SYS_CS4L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS5U
+ ldr r1, =CONFIG_SYS_CS5U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS5L
+ ldr r1, =CONFIG_SYS_CS5L_VAL
+ str r1, [r0]
+
+/* SDRAM Setup */
+
+ ldr r0, =SDCTL0
+ ldr r1, =PRECHARGE_CMD
+ str r1, [r0]
+
+ ldr r0, =0x08200000
+ ldr r1, =0x0 /* Issue Precharge all Command */
+ str r1, [r0]
+
+ ldr r0, =SDCTL0
+ ldr r1, =AUTOREFRESH_CMD
+ str r1, [r0]
+
+ ldr r0, =0x08000000
+ ldr r1, =0x0 /* Issue AutoRefresh Command */
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+
+ ldr r0, =SDCTL0
+ ldr r1, =0xb10a8300
+ str r1, [r0]
+
+ ldr r0, =0x08223000 /* CAS Latency 2 */
+ ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */
+ str r1, [r0]
+
+ ldr r0, =SDCTL0
+ ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
+ str r1, [r0]
+
+ mov pc,r10
diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c
new file mode 100644
index 0000000..3463f52
--- /dev/null
+++ b/board/scb9328/scb9328.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init (void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_SCB9328;
+ gd->bd->bi_boot_params = 0x08000100;
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)SCB9328_SDRAM_1,
+ SCB9328_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = SCB9328_SDRAM_1;
+ gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE;
+}
+
+/**
+ * show_boot_progress: - indicate state of the boot process
+ *
+ * @param status: Status number - see README for details.
+ *
+ * The CSB226 does only have 3 LEDs, so we switch them on at the most
+ * important states (1, 5, 15).
+ */
+
+void show_boot_progress (int status)
+{
+ return;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
diff --git a/board/schulercontrol/sc_sps_1/Kconfig b/board/schulercontrol/sc_sps_1/Kconfig
new file mode 100644
index 0000000..2461d0c
--- /dev/null
+++ b/board/schulercontrol/sc_sps_1/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SC_SPS_1
+
+config SYS_BOARD
+ default "sc_sps_1"
+
+config SYS_VENDOR
+ default "schulercontrol"
+
+config SYS_SOC
+ default "mxs"
+
+config SYS_CONFIG_NAME
+ default "sc_sps_1"
+
+endif
diff --git a/board/schulercontrol/sc_sps_1/MAINTAINERS b/board/schulercontrol/sc_sps_1/MAINTAINERS
new file mode 100644
index 0000000..74849cd
--- /dev/null
+++ b/board/schulercontrol/sc_sps_1/MAINTAINERS
@@ -0,0 +1,6 @@
+SC_SPS_1 BOARD
+M: Marek Vasut <marek.vasut@gmail.com>
+S: Maintained
+F: board/schulercontrol/sc_sps_1/
+F: include/configs/sc_sps_1.h
+F: configs/sc_sps_1_defconfig
diff --git a/board/schulercontrol/sc_sps_1/Makefile b/board/schulercontrol/sc_sps_1/Makefile
new file mode 100644
index 0000000..df72fc9
--- /dev/null
+++ b/board/schulercontrol/sc_sps_1/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2012
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := sc_sps_1.o
+else
+obj-y := spl_boot.o
+endif
diff --git a/board/schulercontrol/sc_sps_1/sc_sps_1.c b/board/schulercontrol/sc_sps_1/sc_sps_1.c
new file mode 100644
index 0000000..7f0b591
--- /dev/null
+++ b/board/schulercontrol/sc_sps_1/sc_sps_1.c
@@ -0,0 +1,97 @@
+/*
+ * SchulerControl GmbH, SC_SPS_1 module
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+ /* IO0 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK0, 480000);
+ /* IO1 clock at 480MHz */
+ mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+ /* SSP0 clock at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+ /* SSP2 clock at 96MHz */
+ mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
+
+#ifdef CONFIG_CMD_USB
+ mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT);
+ mxs_iomux_setup_pad(MX28_PAD_AUART2_TX__GPIO_3_9 |
+ MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
+ gpio_direction_output(MX28_PAD_AUART2_TX__GPIO_3_9, 1);
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ return mxs_dram_init();
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ return mxsmmc_initialize(bis, 0, NULL, NULL);
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ int ret;
+
+ ret = cpu_eth_init(bis);
+
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+ CLKCTRL_ENET_TIME_SEL_MASK,
+ CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN);
+
+ ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC0\n");
+ return ret;
+ }
+
+ ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
+ if (ret) {
+ printf("FEC MXS: Unable to init FEC1\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+#endif
diff --git a/board/schulercontrol/sc_sps_1/spl_boot.c b/board/schulercontrol/sc_sps_1/spl_boot.c
new file mode 100644
index 0000000..60195c3
--- /dev/null
+++ b/board/schulercontrol/sc_sps_1/spl_boot.c
@@ -0,0 +1,149 @@
+/*
+ * SchulerControl GmbH, SC_SPS_1 module setup
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+ /* -- Strick 3 -- */
+
+ /* FEC Ethernet */
+ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+
+ MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* ENET INT */
+
+ MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
+ MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+ /* -- Strick 4 -- */
+
+ /* EMI */
+ MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+
+ MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+ MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+
+ /* -- Strick 5 -- */
+
+ /* MMC0 */
+ MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+ MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+ MX28_PAD_SSP0_SCK__SSP0_SCK |
+ (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+
+ /* SPI2 (for flash) */
+ MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
+ MX28_PAD_SSP2_SS0__SSP2_D3 |
+ (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+
+ /* -- Strick 6 -- */
+
+ /* I2C */
+ MX28_PAD_I2C0_SCL__I2C0_SCL,
+ MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+ /* AUART0 */
+ MX28_PAD_AUART0_TX__AUART0_TX,
+ MX28_PAD_AUART0_RX__AUART0_RX,
+
+ /* MEGA interface */
+
+ /* Debug UART */
+ MX28_PAD_PWM0__DUART_RX,
+ MX28_PAD_PWM1__DUART_TX,
+
+ /* LED */
+ MX28_PAD_GPMI_D00__GPIO_0_0 | MUX_CONFIG_LED,
+ MX28_PAD_GPMI_D03__GPIO_0_3 | MUX_CONFIG_LED,
+ MX28_PAD_GPMI_D06__GPIO_0_6 | MUX_CONFIG_LED,
+};
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+ mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+ dram_vals[0x74 >> 2] = 0x0f02010a;
+}
diff --git a/board/shmin/Kconfig b/board/shmin/Kconfig
new file mode 100644
index 0000000..467580c
--- /dev/null
+++ b/board/shmin/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SHMIN
+
+config SYS_BOARD
+ default "shmin"
+
+config SYS_CONFIG_NAME
+ default "shmin"
+
+endif
diff --git a/board/shmin/MAINTAINERS b/board/shmin/MAINTAINERS
new file mode 100644
index 0000000..5dee37b
--- /dev/null
+++ b/board/shmin/MAINTAINERS
@@ -0,0 +1,7 @@
+SHMIN BOARD
+M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S: Maintained
+F: board/shmin/
+F: include/configs/shmin.h
+F: configs/shmin_defconfig
diff --git a/board/shmin/Makefile b/board/shmin/Makefile
new file mode 100644
index 0000000..daf36de
--- /dev/null
+++ b/board/shmin/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2010 Nobuhiro Iwamatsu
+# Copyright (C) 2008 Renesas Solutions Corp.
+#
+# u-boot/board/shmin/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := shmin.o
+obj-y += lowlevel_init.o
diff --git a/board/shmin/lowlevel_init.S b/board/shmin/lowlevel_init.S
new file mode 100644
index 0000000..35c0945
--- /dev/null
+++ b/board/shmin/lowlevel_init.S
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2008, 2010 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+ /* Use setting of original bootloader */
+ rts
+ nop
+ .align 2
diff --git a/board/shmin/shmin.c b/board/shmin/shmin.c
new file mode 100644
index 0000000..74d1e39
--- /dev/null
+++ b/board/shmin/shmin.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2007 - 2010
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * board/shmin/shmin.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copy board_flash_get_legacy() from board/freescale/m54455evb/m54455evb.c
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <netdev.h>
+
+int checkboard(void)
+{
+ puts("BOARD: T-SH7706LAN ");
+ if(readb(0xb0008006) == 0xab)
+ puts("v2\n");
+ else
+ puts("v1\n");
+ return 0;
+}
+
+int board_init(void)
+{
+ writew(0x2980, BCR2);
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return ne2k_register();
+}
+
+void led_set_state(unsigned short value)
+{
+
+}
+
+#if defined(CONFIG_FLASH_CFI_LEGACY)
+#include <flash.h>
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ int sect[] = CONFIG_SYS_ATMEL_SECT;
+ int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
+ int i, j, k;
+
+ if (base != CONFIG_SYS_ATMEL_BASE)
+ return 0;
+
+ info->flash_id = 0x01000000;
+ info->portwidth = 1;
+ info->chipwidth = 1;
+ info->buffer_size = 1;
+ info->erase_blk_tout = 16384;
+ info->write_tout = 2;
+ info->buffer_write_tout = 5;
+ info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
+ info->cmd_reset = 0x00F0;
+ info->interface = FLASH_CFI_X8;
+ info->legacy_unlock = 0;
+ info->manufacturer_id = (u16) ATM_MANUFACT;
+ info->device_id = ATM_ID_LV040;
+ info->device_id2 = 0;
+ info->ext_addr = 0;
+ info->cfi_version = 0x3133;
+ info->cfi_offset = 0x0000;
+ info->addr_unlock1 = 0x00000555;
+ info->addr_unlock2 = 0x000002AA;
+ info->name = "CFI conformant";
+ info->size = 0;
+ info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
+ info->start[0] = base;
+
+ for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
+ info->size += sect[i] * sectsz[i];
+ for (j = 0; j < sect[i]; j++, k++) {
+ info->start[k + 1] = info->start[k] + sectsz[i];
+ info->protect[k] = 0;
+ }
+ }
+
+ return 1;
+}
+#endif /* CONFIG_FLASH_CFI_LEGACY */
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
new file mode 100644
index 0000000..cc0ac6b
--- /dev/null
+++ b/board/siemens/common/board.c
@@ -0,0 +1,187 @@
+/*
+ * Common board functions for siemens AM335X based boards
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/board/ti/am335x/board.c
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <watchdog.h>
+#include "../common/factoryset.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ /* Initalize the board header */
+ enable_i2c0_pin_mux();
+ i2c_set_bus_num(0);
+ if (read_eeprom() < 0)
+ puts("Could not get board ID.\n");
+
+ enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+ spl_siemens_board_init();
+ board_init_ddr();
+
+ return;
+}
+#endif /* #ifdef CONFIG_SPL_BUILD */
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif /* defined(CONFIG_HW_WATCHDOG) */
+ i2c_set_bus_num(0);
+ if (read_eeprom() < 0)
+ puts("Could not get board ID.\n");
+
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_FACTORYSET
+ factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR);
+#endif
+ gpmc_init();
+
+#ifdef CONFIG_VIDEO
+ board_video_init();
+#endif
+
+ return 0;
+}
+#endif /* #ifndef CONFIG_SPL_BUILD */
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+ DDR_PLL_FREQ, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ return &dpll_ddr;
+}
+
+#ifndef CONFIG_SPL_BUILD
+#if defined(BOARD_DFU_BUTTON_GPIO)
+/*
+ * This command returns the status of the user button on
+ * Input - none
+ * Returns - 1 if button is held down
+ * 0 if button is not held down
+ */
+static int
+do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int button = 0;
+ int gpio;
+
+ gpio = BOARD_DFU_BUTTON_GPIO;
+ gpio_request(gpio, "DFU");
+ gpio_direction_input(gpio);
+ if (gpio_get_value(gpio))
+ button = 1;
+ else
+ button = 0;
+
+ gpio_free(gpio);
+
+ return button;
+}
+
+U_BOOT_CMD(
+ dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton,
+ "Return the status of the DFU button",
+ ""
+);
+#endif
+/*
+ * This command sets led
+ * Input - name of led
+ * value of led
+ * Returns - 1 if input does not match
+ * 0 if led was set
+ */
+static int
+do_setled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int gpio = 0;
+ if (argc != 3)
+ goto exit;
+#if defined(BOARD_STATUS_LED)
+ if (!strcmp(argv[1], "stat"))
+ gpio = BOARD_STATUS_LED;
+#endif
+#if defined(BOARD_DFU_BUTTON_LED)
+ if (!strcmp(argv[1], "dfu"))
+ gpio = BOARD_DFU_BUTTON_LED;
+#endif
+ /* If argument does not mach exit */
+ if (gpio == 0)
+ goto exit;
+ gpio_request(gpio, "");
+ gpio_direction_output(gpio, 1);
+ if (!strcmp(argv[2], "1"))
+ gpio_set_value(gpio, 1);
+ else
+ gpio_set_value(gpio, 0);
+ return 0;
+exit:
+ return 1;
+}
+
+U_BOOT_CMD(
+ led, CONFIG_SYS_MAXARGS, 2, do_setled,
+ "Set led on or off",
+ "dfu val - set dfu led\nled stat val - set status led"
+);
+
+static int
+do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ printf("\n\n\n Go into infinite loop\n\n\n");
+ while (1)
+ ;
+ return 0;
+};
+
+U_BOOT_CMD(
+ testwdt, CONFIG_SYS_MAXARGS, 1, do_usertestwdt,
+ "Sends U-Boot into infinite loop",
+ ""
+);
+#endif /* !CONFIG_SPL_BUILD */
diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c
new file mode 100644
index 0000000..7baac3d
--- /dev/null
+++ b/board/siemens/common/factoryset.c
@@ -0,0 +1,322 @@
+/*
+ *
+ * Read FactorySet information from EEPROM into global structure.
+ * (C) Copyright 2013 Siemens Schweiz AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/unaligned.h>
+#include <net.h>
+#include <errno.h>
+#include <g_dnl.h>
+#include "factoryset.h"
+
+#define EEPR_PG_SZ 0x80
+#define EEPROM_FATORYSET_OFFSET 0x400
+#define OFF_PG EEPROM_FATORYSET_OFFSET/EEPR_PG_SZ
+
+/* Global variable that contains necessary information from FactorySet */
+struct factorysetcontainer factory_dat;
+
+#define fact_get_char(i) *((char *)&eeprom_buf[i])
+
+static int fact_match(unsigned char *eeprom_buf, uchar *s1, int i2)
+{
+ if (s1 == NULL)
+ return -1;
+
+ while (*s1 == fact_get_char(i2++))
+ if (*s1++ == '=')
+ return i2;
+
+ if (*s1 == '\0' && fact_get_char(i2-1) == '=')
+ return i2;
+
+ return -1;
+}
+
+static int get_factory_val(unsigned char *eeprom_buf, int size, uchar *name,
+ uchar *buf, int len)
+{
+ int i, nxt = 0;
+
+ for (i = 0; fact_get_char(i) != '\0'; i = nxt + 1) {
+ int val, n;
+
+ for (nxt = i; fact_get_char(nxt) != '\0'; ++nxt) {
+ if (nxt >= size)
+ return -1;
+ }
+
+ val = fact_match(eeprom_buf, (uchar *)name, i);
+ if (val < 0)
+ continue;
+
+ /* found; copy out */
+ for (n = 0; n < len; ++n, ++buf) {
+ *buf = fact_get_char(val++);
+ if (*buf == '\0')
+ return n;
+ }
+
+ if (n)
+ *--buf = '\0';
+
+ printf("env_buf [%d bytes] too small for value of \"%s\"\n",
+ len, name);
+
+ return n;
+ }
+ return -1;
+}
+
+static
+int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record,
+ uchar *name, uchar *buf, int len)
+{
+ int ret = -1;
+ int i, nxt = 0;
+ int c;
+ unsigned char end = 0xff;
+ unsigned char tmp;
+
+ for (i = 0; fact_get_char(i) != end; i = nxt) {
+ nxt = i + 1;
+ if (fact_get_char(i) == '>') {
+ int pos;
+ int endpos;
+ int z;
+ int level = 0;
+
+ c = strncmp((char *)&eeprom_buf[i + 1], (char *)record,
+ strlen((char *)record));
+ if (c == 0) {
+ /* record found */
+ pos = i + strlen((char *)record) + 2;
+ nxt = pos;
+ /* search for "<" */
+ c = -1;
+ for (z = pos; fact_get_char(z) != end; z++) {
+ if (fact_get_char(z) == '<') {
+ if (level == 0) {
+ endpos = z;
+ nxt = endpos;
+ c = 0;
+ break;
+ } else {
+ level--;
+ }
+ }
+ if (fact_get_char(z) == '>')
+ level++;
+ }
+ } else {
+ continue;
+ }
+ if (c == 0) {
+ /* end found -> call get_factory_val */
+ tmp = eeprom_buf[endpos];
+ eeprom_buf[endpos] = end;
+ ret = get_factory_val(&eeprom_buf[pos],
+ endpos - pos, name, buf, len);
+ /* fix buffer */
+ eeprom_buf[endpos] = tmp;
+ debug("%s: %s.%s = %s\n",
+ __func__, record, name, buf);
+ return ret;
+ }
+ }
+ }
+ return ret;
+}
+
+int factoryset_read_eeprom(int i2c_addr)
+{
+ int i, pages = 0, size = 0;
+ unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH];
+ unsigned char *cp, *cp1;
+
+#if defined(CONFIG_DFU_FUNCTION)
+ factory_dat.usb_vendor_id = CONFIG_G_DNL_VENDOR_NUM;
+ factory_dat.usb_product_id = CONFIG_G_DNL_PRODUCT_NUM;
+#endif
+ if (i2c_probe(i2c_addr))
+ goto err;
+
+ if (i2c_read(i2c_addr, EEPROM_FATORYSET_OFFSET, 2, hdr, sizeof(hdr)))
+ goto err;
+
+ if ((hdr[0] != 0x99) || (hdr[1] != 0x80)) {
+ printf("FactorySet is not right in eeprom.\n");
+ return 1;
+ }
+
+ /* get FactorySet size */
+ size = (hdr[2] << 8) + hdr[3] + sizeof(hdr);
+ if (size > 0x3bfa)
+ size = 0x3bfa;
+
+ pages = size / EEPR_PG_SZ;
+
+ /*
+ * read the eeprom using i2c
+ * I can not read entire eeprom in once, so separate into several
+ * times. Furthermore, fetch eeprom take longer time, so we fetch
+ * data after every time we got a record from eeprom
+ */
+ debug("Read eeprom page :\n");
+ for (i = 0; i < pages; i++)
+ if (i2c_read(i2c_addr, (OFF_PG + i) * EEPR_PG_SZ, 2,
+ eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ))
+ goto err;
+
+ if (size % EEPR_PG_SZ)
+ if (i2c_read(i2c_addr, (OFF_PG + pages) * EEPR_PG_SZ, 2,
+ eeprom_buf + (pages * EEPR_PG_SZ),
+ (size % EEPR_PG_SZ)))
+ goto err;
+
+ /* we do below just for eeprom align */
+ for (i = 0; i < size; i++)
+ if (eeprom_buf[i] == '\n')
+ eeprom_buf[i] = 0;
+
+ /* skip header */
+ size -= sizeof(hdr);
+ cp = (uchar *)eeprom_buf + sizeof(hdr);
+
+ /* get mac address */
+ get_factory_record_val(cp, size, (uchar *)"ETH1", (uchar *)"mac",
+ buf, MAX_STRING_LENGTH);
+ cp1 = buf;
+ for (i = 0; i < 6; i++) {
+ factory_dat.mac[i] = simple_strtoul((char *)cp1, NULL, 16);
+ cp1 += 3;
+ }
+
+#if defined(CONFIG_DFU_FUNCTION)
+ /* read vid and pid for dfu mode */
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1",
+ (uchar *)"vid", buf,
+ MAX_STRING_LENGTH)) {
+ factory_dat.usb_vendor_id = simple_strtoul((char *)buf,
+ NULL, 16);
+ }
+
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1",
+ (uchar *)"pid", buf,
+ MAX_STRING_LENGTH)) {
+ factory_dat.usb_product_id = simple_strtoul((char *)buf,
+ NULL, 16);
+ }
+ printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id,
+ factory_dat.usb_product_id);
+#endif
+#if defined(CONFIG_VIDEO)
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1",
+ (uchar *)"name", factory_dat.disp_name,
+ MAX_STRING_LENGTH)) {
+ debug("display name: %s\n", factory_dat.disp_name);
+ }
+#endif
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+ (uchar *)"num", factory_dat.serial,
+ MAX_STRING_LENGTH)) {
+ debug("serial number: %s\n", factory_dat.serial);
+ }
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+ (uchar *)"ver", buf,
+ MAX_STRING_LENGTH)) {
+ factory_dat.version = simple_strtoul((char *)buf,
+ NULL, 16);
+ debug("version number: %d\n", factory_dat.version);
+ }
+ /* Get ASN from factory set if available */
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+ (uchar *)"id", factory_dat.asn,
+ MAX_STRING_LENGTH)) {
+ debug("factoryset asn: %s\n", factory_dat.asn);
+ } else {
+ factory_dat.asn[0] = 0;
+ }
+ /* Get COMP/ver from factory set if available */
+ if (0 <= get_factory_record_val(cp, size, (uchar *)"COMP",
+ (uchar *)"ver",
+ factory_dat.comp_version,
+ MAX_STRING_LENGTH)) {
+ debug("factoryset COMP/ver: %s\n", factory_dat.comp_version);
+ } else {
+ strcpy((char *)factory_dat.comp_version, "1.0");
+ }
+
+ return 0;
+
+err:
+ printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
+ return 1;
+}
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static int factoryset_mac_setenv(void)
+{
+ uint8_t mac_addr[6];
+
+ debug("FactorySet: Set mac address\n");
+ if (is_valid_ether_addr(factory_dat.mac)) {
+ memcpy(mac_addr, factory_dat.mac, 6);
+ } else {
+ uint32_t mac_hi, mac_lo;
+
+ debug("Warning: FactorySet: <ethaddr> not set. Fallback to E-fuse\n");
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+ if (!is_valid_ether_addr(mac_addr)) {
+ printf("Warning: ethaddr not set by FactorySet or E-fuse. Set <ethaddr> variable to overcome this.\n");
+ return -1;
+ }
+ }
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ return 0;
+}
+
+int factoryset_setenv(void)
+{
+ int ret = 0;
+
+ if (factoryset_mac_setenv() < 0)
+ ret = -1;
+
+ return ret;
+}
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+ put_unaligned(factory_dat.usb_vendor_id, &dev->idVendor);
+ put_unaligned(factory_dat.usb_product_id, &dev->idProduct);
+ g_dnl_set_serialnumber((char *)factory_dat.serial);
+
+ return 0;
+}
+
+int g_dnl_get_board_bcd_device_number(int gcnum)
+{
+ return factory_dat.version;
+}
+#endif /* defined(CONFIG_SPL_BUILD) */
diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h
new file mode 100644
index 0000000..3f23d5e
--- /dev/null
+++ b/board/siemens/common/factoryset.h
@@ -0,0 +1,31 @@
+/*
+ * Common board functions for siemens AM335X based boards
+ * (C) Copyright 2013 Siemens Schweiz AG
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FACTORYSET_H
+#define __FACTORYSET_H
+
+#define MAX_STRING_LENGTH 32
+
+struct factorysetcontainer {
+ uchar mac[6];
+ int usb_vendor_id;
+ int usb_product_id;
+ int pxm50;
+#if defined(CONFIG_VIDEO)
+ unsigned char disp_name[MAX_STRING_LENGTH];
+#endif
+ unsigned char serial[MAX_STRING_LENGTH];
+ int version;
+ uchar asn[MAX_STRING_LENGTH];
+ uchar comp_version[MAX_STRING_LENGTH];
+};
+
+int factoryset_read_eeprom(int i2c_addr);
+int factoryset_setenv(void);
+extern struct factorysetcontainer factory_dat;
+
+#endif /* __FACTORYSET_H */
diff --git a/board/siemens/corvus/Kconfig b/board/siemens/corvus/Kconfig
new file mode 100644
index 0000000..7b505aa
--- /dev/null
+++ b/board/siemens/corvus/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CORVUS
+
+config SYS_BOARD
+ default "corvus"
+
+config SYS_VENDOR
+ default "siemens"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "corvus"
+
+endif
diff --git a/board/siemens/corvus/MAINTAINERS b/board/siemens/corvus/MAINTAINERS
new file mode 100644
index 0000000..59176aa
--- /dev/null
+++ b/board/siemens/corvus/MAINTAINERS
@@ -0,0 +1,6 @@
+CORVUS BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: board/siemens/corvus/
+F: include/configs/corvus.h
+F: configs/corvus_defconfig
diff --git a/board/siemens/corvus/Makefile b/board/siemens/corvus/Makefile
new file mode 100644
index 0000000..f3ebf77
--- /dev/null
+++ b/board/siemens/corvus/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for siemens CORVUS (AT91SAM9G45) based board
+# (C) Copyright 2013 Siemens AG
+#
+# Based on:
+# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
new file mode 100644
index 0000000..0a11540
--- /dev/null
+++ b/board/siemens/corvus/board.c
@@ -0,0 +1,280 @@
+/*
+ * Board functions for Siemens CORVUS (AT91SAM9G45) based board
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void corvus_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+ /*
+ * For on the sam9m10g45ek board, the chip wm9711 stay in the test
+ * mode, so it need do some action to exit mode.
+ */
+ at91_set_gpio_output(AT91_PIN_PD7, 0);
+ at91_set_gpio_output(AT91_PIN_PD8, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+
+ corvus_nand_hw_init();
+
+ /* Configure recovery button PINs */
+ at91_set_gpio_input(AT91_PIN_PB7, 1);
+
+ /* check if button is pressed */
+ if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
+ u32 boot_device;
+
+ debug("Recovery button pressed\n");
+ boot_device = spl_boot_device();
+ switch (boot_device) {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ case BOOT_DEVICE_NAND:
+ nand_init();
+ spl_nand_erase_one(0, 0);
+ break;
+#endif
+ }
+ }
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_14 |
+ ATMEL_MPDDRC_CR_DIC_DS |
+ ATMEL_MPDDRC_CR_DQMS_SHARED |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+ ddr2->rtr = 0x24b;
+
+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */
+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+ 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+ 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct atmel_mpddr ddr2;
+ unsigned long csa;
+
+ ddr2_conf(&ddr2);
+
+ /* enable DDR2 clock */
+ writel(0x4, &pmc->scer);
+
+ /* Chip select 1 is for DDR2/SDRAM */
+ csa = readl(&mat->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+ csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
+ writel(csa, &mat->ebicsa);
+
+ /* DDRAM2 Controller initialize */
+ ddr2_init(ATMEL_BASE_CS6, &ddr2);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void taurus_usb_hw_init(void)
+{
+ at91_periph_clk_enable(ATMEL_ID_PIODE);
+
+ at91_set_gpio_output(AT91_PIN_PD1, 0);
+ at91_set_gpio_output(AT91_PIN_PD3, 0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void corvus_macb_hw_init(void)
+{
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_EMAC);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA15) => PHY normal mode (not Test mode)
+ * ERX0 (PA12) => PHY ADDR0
+ * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
+
+ at91_phy_reset();
+
+ /* Re-enable pull-up */
+ at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
+
+ /* And the pins. */
+ at91_macb_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+ at91_seriald_hw_init();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ corvus_nand_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SPI
+ at91_spi0_hw_init(1 << 4);
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+ corvus_macb_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+ taurus_usb_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
+
+/* SPI chip select control */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 1:
+ at91_set_gpio_output(AT91_PIN_PB18, 0);
+ break;
+ case 0:
+ default:
+ at91_set_gpio_output(AT91_PIN_PB3, 0);
+ break;
+ }
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ switch (slave->cs) {
+ case 1:
+ at91_set_gpio_output(AT91_PIN_PB18, 1);
+ break;
+ case 0:
+ default:
+ at91_set_gpio_output(AT91_PIN_PB3, 1);
+ break;
+ }
+}
diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig
new file mode 100644
index 0000000..d138ece
--- /dev/null
+++ b/board/siemens/draco/Kconfig
@@ -0,0 +1,31 @@
+if TARGET_DRACO
+
+config SYS_BOARD
+ default "draco"
+
+config SYS_VENDOR
+ default "siemens"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "draco"
+
+endif
+
+if TARGET_DXR2
+
+config SYS_BOARD
+ default "draco"
+
+config SYS_VENDOR
+ default "siemens"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "dxr2"
+
+endif
diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS
new file mode 100644
index 0000000..f6b68ca
--- /dev/null
+++ b/board/siemens/draco/MAINTAINERS
@@ -0,0 +1,8 @@
+DRACO BOARD
+M: Roger Meier <r.meier@siemens.com>
+S: Maintained
+F: board/siemens/draco/
+F: include/configs/draco.h
+F: configs/draco_defconfig
+F: include/configs/dxr2.h
+F: configs/dxr2_defconfig
diff --git a/board/siemens/draco/Makefile b/board/siemens/draco/Makefile
new file mode 100644
index 0000000..f159932
--- /dev/null
+++ b/board/siemens/draco/Makefile
@@ -0,0 +1,21 @@
+#
+# Makefile
+#
+# (C) Copyright 2013 Siemens Schweiz AG
+# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# Based on:
+# u-boot:/board/ti/am335x/Makefile
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := mux.o
+endif
+
+obj-y += board.o
+ifndef CONFIG_SPL_BUILD
+obj-y += ../common/factoryset.o
+endif
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
new file mode 100644
index 0000000..ede73ba
--- /dev/null
+++ b/board/siemens/draco/board.c
@@ -0,0 +1,292 @@
+/*
+ * Board functions for TI AM335X based draco board
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ *
+ * Board functions for TI AM335X based boards
+ * u-boot:/board/ti/am335x/board.c
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <watchdog.h>
+#include "board.h"
+#include "../common/factoryset.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+static struct draco_baseboard_id __attribute__((section(".data"))) settings;
+
+#if DDR_PLL_FREQ == 303
+/* Default@303MHz-i0 */
+const struct ddr3_data ddr3_default = {
+ 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
+ 0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
+ 0x0000093B, 0x0000014A,
+ "default name @303MHz \0",
+ "default marking \0",
+};
+#elif DDR_PLL_FREQ == 400
+/* Default@400MHz-i0 */
+const struct ddr3_data ddr3_default = {
+ 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
+ 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
+ 0x00000618, 0x0000014A,
+ "default name @400MHz \0",
+ "default marking \0",
+};
+#endif
+
+static void set_default_ddr3_timings(void)
+{
+ printf("Set default DDR3 settings\n");
+ settings.ddr3 = ddr3_default;
+}
+
+static void print_ddr3_timings(void)
+{
+ printf("\nDDR3\n");
+ printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
+ printf("device:\t\t%s\n", settings.ddr3.manu_name);
+ printf("marking:\t%s\n", settings.ddr3.manu_marking);
+ printf("timing parameters\n");
+ printf("diff\teeprom\tdefault\n");
+ PRINTARGS(magic);
+ PRINTARGS(version);
+ PRINTARGS(ddr3_sratio);
+ PRINTARGS(iclkout);
+
+ PRINTARGS(dt0rdsratio0);
+ PRINTARGS(dt0wdsratio0);
+ PRINTARGS(dt0fwsratio0);
+ PRINTARGS(dt0wrsratio0);
+
+ PRINTARGS(sdram_tim1);
+ PRINTARGS(sdram_tim2);
+ PRINTARGS(sdram_tim3);
+
+ PRINTARGS(emif_ddr_phy_ctlr_1);
+
+ PRINTARGS(sdram_config);
+ PRINTARGS(ref_ctrl);
+ PRINTARGS(ioctr_val);
+}
+
+static void print_chip_data(void)
+{
+ printf("\nCPU BOARD\n");
+ printf("device: \t'%s'\n", settings.chip.sdevname);
+ printf("hw version: \t'%s'\n", settings.chip.shwver);
+}
+#endif /* CONFIG_SPL_BUILD */
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+ printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
+ return 1;
+ }
+
+#ifdef CONFIG_SPL_BUILD
+ /* Read Siemens eeprom data (DDR3) */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
+ (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
+ printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
+ set_default_ddr3_timings();
+ }
+ /* Read Siemens eeprom data (CHIP) */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
+ (uchar *)&settings.chip, sizeof(settings.chip)))
+ printf("Could not read chip settings\n");
+
+ if (ddr3_default.magic == settings.ddr3.magic &&
+ ddr3_default.version == settings.ddr3.version) {
+ printf("Using DDR3 settings from EEPROM\n");
+ } else {
+ if (ddr3_default.magic != settings.ddr3.magic)
+ printf("Warning: No valid DDR3 data in eeprom.\n");
+ if (ddr3_default.version != settings.ddr3.version)
+ printf("Warning: DDR3 data version does not match.\n");
+
+ printf("Using default settings\n");
+ set_default_ddr3_timings();
+ }
+
+ if (MAGIC_CHIP == settings.chip.magic)
+ print_chip_data();
+ else
+ printf("Warning: No chip data in eeprom\n");
+
+ print_ddr3_timings();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+static void board_init_ddr(void)
+{
+struct emif_regs draco_ddr3_emif_reg_data = {
+ .zq_config = 0x50074BE4,
+};
+
+struct ddr_data draco_ddr3_data = {
+};
+
+struct cmd_control draco_ddr3_cmd_ctrl_data = {
+};
+
+struct ctrl_ioregs draco_ddr3_ioregs = {
+};
+
+ /* pass values from eeprom */
+ draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
+ draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
+ draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
+ draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
+ settings.ddr3.emif_ddr_phy_ctlr_1;
+ draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
+ draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
+
+ draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
+ draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
+ draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
+ draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
+
+ draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
+ draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
+ draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
+ draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
+ draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
+ draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
+
+ draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
+ draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
+ draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
+ draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
+ draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
+
+ config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
+ &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
+}
+
+static void spl_siemens_board_init(void)
+{
+ return;
+}
+#endif /* if def CONFIG_SPL_BUILD */
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ .phy_if = PHY_INTERFACE_MODE_MII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 4,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+ (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+int board_eth_init(bd_t *bis)
+{
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+ int n = 0;
+ int rv;
+
+ factoryset_setenv();
+
+ /* Set rgmii mode and enable rmii clock to be sourced from chip */
+ writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+ return n;
+}
+
+static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ /* Reset SMSC LAN9303 switch for default configuration */
+ gpio_request(GPIO_LAN9303_NRST, "nRST");
+ gpio_direction_output(GPIO_LAN9303_NRST, 0);
+ /* assert active low reset for 200us */
+ udelay(200);
+ gpio_set_value(GPIO_LAN9303_NRST, 1);
+
+ return 0;
+};
+
+U_BOOT_CMD(
+ switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
+ "Reset LAN9303 switch via its reset pin",
+ ""
+);
+#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ omap_nand_switch_ecc(1, 8);
+
+ return 0;
+}
+#endif
+
+#include "../common/board.c"
diff --git a/board/siemens/draco/board.h b/board/siemens/draco/board.h
new file mode 100644
index 0000000..ff8ab76
--- /dev/null
+++ b/board/siemens/draco/board.h
@@ -0,0 +1,72 @@
+/*
+ * board.h
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ * u-boot:/board/ti/am335x/board.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \
+ settings.ddr3.x, ddr3_default.x
+#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y))
+#define MAGIC_CHIP 0x50494843
+
+/* Automatic generated definition */
+/* Wed, 16 Apr 2014 16:50:41 +0200 */
+/* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */
+struct ddr3_data {
+ unsigned int magic; /* 0x33524444 */
+ unsigned int version; /* 0x56312e35 */
+ unsigned short int ddr3_sratio; /* 0x0080 */
+ unsigned short int iclkout; /* 0x0000 */
+ unsigned short int dt0rdsratio0; /* 0x003A */
+ unsigned short int dt0wdsratio0; /* 0x003F */
+ unsigned short int dt0fwsratio0; /* 0x009F */
+ unsigned short int dt0wrsratio0; /* 0x0079 */
+ unsigned int sdram_tim1; /* 0x0888A39B */
+ unsigned int sdram_tim2; /* 0x26247FDA */
+ unsigned int sdram_tim3; /* 0x501F821F */
+ unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */
+ unsigned int sdram_config; /* 0x61A44A32 */
+ unsigned int ref_ctrl; /* 0x0000093B */
+ unsigned int ioctr_val; /* 0x0000014A */
+ char manu_name[32]; /* "default@303MHz \0" */
+ char manu_marking[32]; /* "default \0" */
+};
+
+struct chip_data {
+ unsigned int magic;
+ char sdevname[16];
+ char shwver[7];
+};
+
+struct draco_baseboard_id {
+ struct ddr3_data ddr3;
+ struct chip_data chip;
+};
+
+/*
+ * We have three pin mux functions that must exist. We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c
new file mode 100644
index 0000000..eaa3c70
--- /dev/null
+++ b/board/siemens/draco/mux.c
@@ -0,0 +1,272 @@
+/*
+ * pinmux setup for siemens draco board
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/mux.c
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+ {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
+static struct module_pin_mux gpios_pin_mux[] = {
+ /* DFU button GPIO0_27*/
+ {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)},
+ {OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */
+ {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */
+ /* Triacs in HW Rev 2 */
+ {OFFSET(uart1_ctsn), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y5 GPIO0_12*/
+ {OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/
+ {OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/
+ /* Triacs initial HW Rev */
+ {OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_30 Y0 */
+ {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */
+ {OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */
+ {OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */
+ {OFFSET(lcd_data14), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_10 Y4 */
+ {OFFSET(gpmc_clk), MODE(7) | RXACTIVE | PULLUDDIS}, /* 2_1 Y5 */
+ {OFFSET(emu1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 3_8 Y6 */
+ {OFFSET(gpmc_ad15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_15 Y7 */
+ /* Remaining pins that were not used in this file */
+ {OFFSET(gpmc_ad8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_ad9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_data9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_vsync), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_hsync), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_pclk), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_dat3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_dat0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_clk), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mmc0_cmd), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_sclk), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(spi0_cs0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart1_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart1_rxd), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(uart1_txd), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_aclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_fsx), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_axr0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_ahclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_aclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_fsr), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_axr1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(mcasp0_ahclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(xdma_event_intr0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(xdma_event_intr1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(nresetin_out), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(porz), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(nnmi), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc0_in), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc0_out), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(rsvd1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tms), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tdi), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tdo), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(tck), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ntrst), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc1_in), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(osc1_out), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(pmic_power_en), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(rtc_porz), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(rsvd2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ext_wakeup), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(enz_kaldo_1p8v), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_id), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb0_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_id), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(usb1_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_resetn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_csn0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_cke), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ck), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_nck), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_casn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_rasn), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_wen), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ba0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ba1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_ba2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a12), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a13), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a14), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_a15), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_odt), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d8), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d9), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d10), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d11), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d12), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d13), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d14), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_d15), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqm0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqm1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqs0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqsn0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqs1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_dqsn1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_vref), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_vtp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_strben0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ddr_strben1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain7), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain6), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain5), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain4), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain3), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain2), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain1), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
+ {OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
+ /* nRST for SMSC LAN9303 switch - GPIO2_24 */
+ {OFFSET(lcd_pclk), MODE(7) }, /* LAN9303 nRST */
+ {-1},
+};
+
+static struct module_pin_mux ethernet_pin_mux[] = {
+ {OFFSET(mii1_col), (MODE(3) | RXACTIVE)},
+ {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_txen), (MODE(1))},
+ {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)},
+ {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_txd1), (MODE(1))},
+ {OFFSET(mii1_txd0), (MODE(1))},
+ {OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxd2), (MODE(1))},
+ {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)},
+ {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)},
+ {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+ configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ enable_uart3_pin_mux();
+ configure_module_pin_mux(nand_pin_mux);
+ configure_module_pin_mux(ethernet_pin_mux);
+ configure_module_pin_mux(gpios_pin_mux);
+}
diff --git a/board/siemens/pxm2/Kconfig b/board/siemens/pxm2/Kconfig
new file mode 100644
index 0000000..62604ec
--- /dev/null
+++ b/board/siemens/pxm2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PXM2
+
+config SYS_BOARD
+ default "pxm2"
+
+config SYS_VENDOR
+ default "siemens"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "pxm2"
+
+endif
diff --git a/board/siemens/pxm2/MAINTAINERS b/board/siemens/pxm2/MAINTAINERS
new file mode 100644
index 0000000..fa734c9
--- /dev/null
+++ b/board/siemens/pxm2/MAINTAINERS
@@ -0,0 +1,6 @@
+PXM2 BOARD
+M: Roger Meier <r.meier@siemens.com>
+S: Maintained
+F: board/siemens/pxm2/
+F: include/configs/pxm2.h
+F: configs/pxm2_defconfig
diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile
new file mode 100644
index 0000000..f159932
--- /dev/null
+++ b/board/siemens/pxm2/Makefile
@@ -0,0 +1,21 @@
+#
+# Makefile
+#
+# (C) Copyright 2013 Siemens Schweiz AG
+# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# Based on:
+# u-boot:/board/ti/am335x/Makefile
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := mux.o
+endif
+
+obj-y += board.o
+ifndef CONFIG_SPL_BUILD
+obj-y += ../common/factoryset.o
+endif
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
new file mode 100644
index 0000000..264ba02
--- /dev/null
+++ b/board/siemens/pxm2/board.c
@@ -0,0 +1,465 @@
+/*
+ * Board functions for TI AM335X based pxm2 board
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/board.c
+ *
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include "../../../drivers/video/da8xx-fb.h"
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <watchdog.h>
+#include "board.h"
+#include "../common/factoryset.h"
+#include "pmic.h"
+#include <nand.h>
+#include <bmp_layout.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+static void board_init_ddr(void)
+{
+struct emif_regs pxm2_ddr3_emif_reg_data = {
+ .sdram_config = 0x41805332,
+ .sdram_tim1 = 0x666b3c9,
+ .sdram_tim2 = 0x243631ca,
+ .sdram_tim3 = 0x33f,
+ .emif_ddr_phy_ctlr_1 = 0x100005,
+ .zq_config = 0,
+ .ref_ctrl = 0x81a,
+};
+
+struct ddr_data pxm2_ddr3_data = {
+ .datardsratio0 = 0x81204812,
+ .datawdsratio0 = 0,
+ .datafwsratio0 = 0x8020080,
+ .datawrsratio0 = 0x4010040,
+};
+
+struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
+ .cmd0csratio = 0x80,
+ .cmd0iclkout = 0,
+ .cmd1csratio = 0x80,
+ .cmd1iclkout = 0,
+ .cmd2csratio = 0x80,
+ .cmd2iclkout = 0,
+};
+
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = DDR_IOCTRL_VAL,
+ .cm1ioctl = DDR_IOCTRL_VAL,
+ .cm2ioctl = DDR_IOCTRL_VAL,
+ .dt0ioctl = DDR_IOCTRL_VAL,
+ .dt1ioctl = DDR_IOCTRL_VAL,
+};
+
+ config_ddr(DDR_PLL_FREQ, &ioregs, &pxm2_ddr3_data,
+ &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
+}
+
+/*
+ * voltage switching for MPU frequency switching.
+ * @module = mpu - 0, core - 1
+ * @vddx_op_vol_sel = vdd voltage to set
+ */
+
+#define MPU 0
+#define CORE 1
+
+int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
+{
+ uchar buf[4];
+ unsigned int reg_offset;
+
+ if (module == MPU)
+ reg_offset = PMIC_VDD1_OP_REG;
+ else
+ reg_offset = PMIC_VDD2_OP_REG;
+
+ /* Select VDDx OP */
+ if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+ return 1;
+
+ buf[0] &= ~PMIC_OP_REG_CMD_MASK;
+
+ if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+ return 1;
+
+ /* Configure VDDx OP Voltage */
+ if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+ return 1;
+
+ buf[0] &= ~PMIC_OP_REG_SEL_MASK;
+ buf[0] |= vddx_op_vol_sel;
+
+ if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+ return 1;
+
+ if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
+ return 1;
+
+ if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
+ return 1;
+
+ return 0;
+}
+
+#define OSC (V_OSCK/1000000)
+
+const struct dpll_params dpll_mpu_pxm2 = {
+ 720, OSC-1, 1, -1, -1, -1, -1};
+
+void spl_siemens_board_init(void)
+{
+ uchar buf[4];
+ /*
+ * pxm2 PMIC code. All boards currently want an MPU voltage
+ * of 1.2625V and CORE voltage of 1.1375V to operate at
+ * 720MHz.
+ */
+ if (i2c_probe(PMIC_CTRL_I2C_ADDR))
+ return;
+
+ /* VDD1/2 voltage selection register access by control i/f */
+ if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
+ return;
+
+ buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
+
+ if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
+ return;
+
+ /* Frequency switching for OPP 120 */
+ if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
+ voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
+ printf("voltage update failed\n");
+ }
+}
+#endif /* if def CONFIG_SPL_BUILD */
+
+int read_eeprom(void)
+{
+ /* nothing ToDo here for this board */
+
+ return 0;
+}
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ .phy_if = PHY_INTERFACE_MODE_RMII,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ .phy_if = PHY_INTERFACE_MODE_RMII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 4,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+ (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+int board_eth_init(bd_t *bis)
+{
+ int n = 0;
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+#ifdef CONFIG_FACTORYSET
+ int rv;
+ if (!is_valid_ether_addr(factory_dat.mac))
+ printf("Error: no valid mac address\n");
+ else
+ eth_setenv_enetaddr("ethaddr", factory_dat.mac);
+#endif /* #ifdef CONFIG_FACTORYSET */
+
+ /* Set rgmii mode and enable rmii clock to be sourced from chip */
+ writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+#endif
+ return n;
+}
+#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+static struct da8xx_panel lcd_panels[] = {
+ /* AUO G156XW01 V1 */
+ [0] = {
+ .name = "AUO_G156XW01_V1",
+ .width = 1376,
+ .height = 768,
+ .hfp = 14,
+ .hbp = 64,
+ .hsw = 56,
+ .vfp = 1,
+ .vbp = 28,
+ .vsw = 3,
+ .pxl_clk = 60000000,
+ .invert_pxl_clk = 0,
+ },
+ /* AUO B101EVN06 V0 */
+ [1] = {
+ .name = "AUO_B101EVN06_V0",
+ .width = 1280,
+ .height = 800,
+ .hfp = 52,
+ .hbp = 84,
+ .hsw = 36,
+ .vfp = 3,
+ .vbp = 14,
+ .vsw = 6,
+ .pxl_clk = 60000000,
+ .invert_pxl_clk = 0,
+ },
+ /*
+ * Settings from factoryset
+ * stored in EEPROM
+ */
+ [2] = {
+ .name = "factoryset",
+ .width = 0,
+ .height = 0,
+ .hfp = 0,
+ .hbp = 0,
+ .hsw = 0,
+ .vfp = 0,
+ .vbp = 0,
+ .vsw = 0,
+ .pxl_clk = 60000000,
+ .invert_pxl_clk = 0,
+ },
+};
+
+static const struct display_panel disp_panel = {
+ WVGA,
+ 32,
+ 16,
+ COLOR_ACTIVE,
+};
+
+static const struct lcd_ctrl_config lcd_cfg = {
+ &disp_panel,
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 32,
+ .fdd = 0x80,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+};
+
+static int set_gpio(int gpio, int state)
+{
+ gpio_request(gpio, "temp");
+ gpio_direction_output(gpio, state);
+ gpio_set_value(gpio, state);
+ gpio_free(gpio);
+ return 0;
+}
+
+static int enable_backlight(void)
+{
+ set_gpio(BOARD_LCD_POWER, 1);
+ set_gpio(BOARD_BACK_LIGHT, 1);
+ set_gpio(BOARD_TOUCH_POWER, 1);
+ return 0;
+}
+
+static int enable_pwm(void)
+{
+ struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
+ struct pwmss_ecap_regs *ecap;
+ int ticks = PWM_TICKS;
+ int duty = PWM_DUTY;
+
+ ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
+ /* enable clock */
+ setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
+ /* TimeStam Counter register */
+ writel(0xdb9, &ecap->tsctr);
+ /* config period */
+ writel(ticks - 1, &ecap->cap3);
+ writel(ticks - 1, &ecap->cap1);
+ setbits_le16(&ecap->ecctl2,
+ (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
+ /* config duty */
+ writel(duty, &ecap->cap2);
+ writel(duty, &ecap->cap4);
+ /* start */
+ setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
+ return 0;
+}
+
+static struct dpll_regs dpll_lcd_regs = {
+ .cm_clkmode_dpll = CM_WKUP + 0x98,
+ .cm_idlest_dpll = CM_WKUP + 0x48,
+ .cm_clksel_dpll = CM_WKUP + 0x54,
+};
+
+/* no console on this board */
+int board_cfb_skip(void)
+{
+ return 1;
+}
+
+#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
+#define PLL_GET_N(v) (v & 0x7f)
+
+static int get_clk(struct dpll_regs *dpll_regs)
+{
+ unsigned int val;
+ unsigned int m, n;
+ int f = 0;
+
+ val = readl(dpll_regs->cm_clksel_dpll);
+ m = PLL_GET_M(val);
+ n = PLL_GET_N(val);
+ f = (m * V_OSCK) / n;
+
+ return f;
+};
+
+int clk_get(int clk)
+{
+ return get_clk(&dpll_lcd_regs);
+};
+
+static int conf_disp_pll(int m, int n)
+{
+ struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
+ struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+ struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
+
+ u32 *const clk_domains[] = {
+ &cmper->lcdclkctrl,
+ 0
+ };
+ u32 *const clk_modules_explicit_en[] = {
+ &cmper->lcdclkctrl,
+ &cmper->lcdcclkstctrl,
+ &cmper->epwmss0clkctrl,
+ 0
+ };
+ do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+ writel(0x0, &cmdpll->clklcdcpixelclk);
+
+ do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
+
+ return 0;
+}
+
+static int board_video_init(void)
+{
+ conf_disp_pll(24, 1);
+ if (factory_dat.pxm50)
+ da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
+ else
+ da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
+
+ enable_pwm();
+ enable_backlight();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+
+ omap_nand_switch_ecc(1, 8);
+
+#ifdef CONFIG_FACTORYSET
+ if (factory_dat.asn[0] != 0) {
+ char tmp[2 * MAX_STRING_LENGTH + 2];
+
+ if (strncmp((const char *)factory_dat.asn, "PXM50", 5) == 0)
+ factory_dat.pxm50 = 1;
+ else
+ factory_dat.pxm50 = 0;
+ sprintf(tmp, "%s_%s", factory_dat.asn,
+ factory_dat.comp_version);
+ ret = setenv("boardid", tmp);
+ if (ret)
+ printf("error setting board id\n");
+ } else {
+ factory_dat.pxm50 = 1;
+ ret = setenv("boardid", "PXM50_1.0");
+ if (ret)
+ printf("error setting board id\n");
+ }
+ debug("PXM50: %d\n", factory_dat.pxm50);
+#endif
+
+ return 0;
+}
+#endif
+
+#include "../common/board.c"
diff --git a/board/siemens/pxm2/board.h b/board/siemens/pxm2/board.h
new file mode 100644
index 0000000..0362612
--- /dev/null
+++ b/board/siemens/pxm2/board.h
@@ -0,0 +1,22 @@
+/*
+ * board.h
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ * u-boot:/board/ti/am335x/board.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/board/siemens/pxm2/mux.c b/board/siemens/pxm2/mux.c
new file mode 100644
index 0000000..c64b0d2
--- /dev/null
+++ b/board/siemens/pxm2/mux.c
@@ -0,0 +1,186 @@
+/*
+ * pinmux setup for siemens pxm2 board
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */
+ {-1},
+};
+
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUP_EN}, /* RGMII2_RD0 */
+ {OFFSET(mcasp0_ahclkx), MODE(7) | PULLUDEN}, /* MCASP0_AHCLKX */
+ {-1},
+};
+#endif
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+ {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
+ {-1},
+};
+
+#ifndef CONFIG_NO_ETH
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux rgmii2_pin_mux[] = {
+ {OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */
+ {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */
+ {OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */
+ {OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */
+ {OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */
+ {OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */
+ {OFFSET(gpmc_a6), MODE(7)}, /* RGMII2_TCLK */
+ {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */
+ {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */
+ {OFFSET(gpmc_a9), MODE(7)}, /* RGMII2_RD2 */
+ {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+#endif
+
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDEN)}, /* MMC0_CD */
+ {-1},
+};
+#endif
+
+static struct module_pin_mux lcdc_pin_mux[] = {
+ {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD_DAT0 */
+ {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD_DAT1 */
+ {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD_DAT2 */
+ {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD_DAT3 */
+ {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD_DAT4 */
+ {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD_DAT5 */
+ {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD_DAT6 */
+ {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD_DAT7 */
+ {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD_DAT8 */
+ {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD_DAT9 */
+ {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD_DAT10 */
+ {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD_DAT11 */
+ {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD_DAT12 */
+ {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD_DAT13 */
+ {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD_DAT14 */
+ {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD_DAT15 */
+ {OFFSET(gpmc_ad8), (MODE(1))}, /* LCD_DAT16 */
+ {OFFSET(gpmc_ad9), (MODE(1))}, /* LCD_DAT17 */
+ {OFFSET(gpmc_ad10), (MODE(1))}, /* LCD_DAT18 */
+ {OFFSET(gpmc_ad11), (MODE(1))}, /* LCD_DAT19 */
+ {OFFSET(gpmc_ad12), (MODE(1))}, /* LCD_DAT20 */
+ {OFFSET(gpmc_ad13), (MODE(1))}, /* LCD_DAT21 */
+ {OFFSET(gpmc_ad14), (MODE(1))}, /* LCD_DAT22 */
+ {OFFSET(gpmc_ad15), (MODE(1))}, /* LCD_DAT23 */
+ {OFFSET(lcd_vsync), (MODE(0))}, /* LCD_VSYNC */
+ {OFFSET(lcd_hsync), (MODE(0))}, /* LCD_HSYNC */
+ {OFFSET(lcd_pclk), (MODE(0))}, /* LCD_PCLK */
+ {OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD_AC_BIAS_EN */
+ {-1},
+};
+
+static struct module_pin_mux ecap0_pin_mux[] = {
+ {OFFSET(ecap0_in_pwm0_out), (MODE(0))},
+ {-1},
+};
+
+static struct module_pin_mux gpio_pin_mux[] = {
+ {OFFSET(mcasp0_fsx), MODE(7)}, /* GPIO3_15 LCD power*/
+ {OFFSET(mcasp0_axr0), MODE(7)}, /* GPIO3_16 Backlight */
+ {OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25 Touch power */
+ {-1},
+};
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+ configure_module_pin_mux(i2c1_pin_mux);
+#ifdef CONFIG_NAND
+ configure_module_pin_mux(nand_pin_mux);
+#endif
+#ifndef CONFIG_NO_ETH
+ configure_module_pin_mux(rgmii1_pin_mux);
+ configure_module_pin_mux(rgmii2_pin_mux);
+#endif
+#ifdef CONFIG_MMC
+ configure_module_pin_mux(mmc0_pin_mux);
+#endif
+ configure_module_pin_mux(lcdc_pin_mux);
+ configure_module_pin_mux(gpio_pin_mux);
+ configure_module_pin_mux(ecap0_pin_mux);
+}
diff --git a/board/siemens/pxm2/pmic.h b/board/siemens/pxm2/pmic.h
new file mode 100644
index 0000000..c6347e5
--- /dev/null
+++ b/board/siemens/pxm2/pmic.h
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef PMIC_H
+#define PMIC_H
+
+/*
+ * The PMIC on this board is a TPS65910.
+ */
+
+#define PMIC_SR_I2C_ADDR 0x12
+#define PMIC_CTRL_I2C_ADDR 0x2D
+/* PMIC Register offsets */
+#define PMIC_VDD1_REG 0x21
+#define PMIC_VDD1_OP_REG 0x22
+#define PMIC_VDD2_REG 0x24
+#define PMIC_VDD2_OP_REG 0x25
+#define PMIC_DEVCTRL_REG 0x3f
+
+/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
+#define PMIC_VGAIN_SEL_MASK (0x3 << 6)
+#define PMIC_ILMAX_MASK (0x1 << 5)
+#define PMIC_TSTEP_MASK (0x7 << 2)
+#define PMIC_ST_MASK (0x3)
+
+#define PMIC_REG_VGAIN_SEL_X1 (0x0 << 6)
+#define PMIC_REG_VGAIN_SEL_X1_0 (0x1 << 6)
+#define PMIC_REG_VGAIN_SEL_X3 (0x2 << 6)
+#define PMIC_REG_VGAIN_SEL_X4 (0x3 << 6)
+
+#define PMIC_REG_ILMAX_1_0_A (0x0 << 5)
+#define PMIC_REG_ILMAX_1_5_A (0x1 << 5)
+
+#define PMIC_REG_TSTEP_ (0x0 << 2)
+#define PMIC_REG_TSTEP_12_5 (0x1 << 2)
+#define PMIC_REG_TSTEP_9_4 (0x2 << 2)
+#define PMIC_REG_TSTEP_7_5 (0x3 << 2)
+#define PMIC_REG_TSTEP_6_25 (0x4 << 2)
+#define PMIC_REG_TSTEP_4_7 (0x5 << 2)
+#define PMIC_REG_TSTEP_3_12 (0x6 << 2)
+#define PMIC_REG_TSTEP_2_5 (0x7 << 2)
+
+#define PMIC_REG_ST_OFF (0x0)
+#define PMIC_REG_ST_ON_HI_POW (0x1)
+#define PMIC_REG_ST_OFF_1 (0x2)
+#define PMIC_REG_ST_ON_LOW_POW (0x3)
+
+
+/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
+#define PMIC_OP_REG_SEL (0x7F)
+
+#define PMIC_OP_REG_CMD_MASK (0x1 << 7)
+#define PMIC_OP_REG_CMD_OP (0x0 << 7)
+#define PMIC_OP_REG_CMD_SR (0x1 << 7)
+
+#define PMIC_OP_REG_SEL_MASK (0x7F)
+#define PMIC_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */
+#define PMIC_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */
+
+/* Device control register . (DEVCTRL_REG) */
+#define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4)
+#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4)
+#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4)
+
+#endif
diff --git a/board/siemens/rut/Kconfig b/board/siemens/rut/Kconfig
new file mode 100644
index 0000000..3371077
--- /dev/null
+++ b/board/siemens/rut/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_RUT
+
+config SYS_BOARD
+ default "rut"
+
+config SYS_VENDOR
+ default "siemens"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "rut"
+
+endif
diff --git a/board/siemens/rut/MAINTAINERS b/board/siemens/rut/MAINTAINERS
new file mode 100644
index 0000000..8c1b770
--- /dev/null
+++ b/board/siemens/rut/MAINTAINERS
@@ -0,0 +1,6 @@
+RUT BOARD
+M: Roger Meier <r.meier@siemens.com>
+S: Maintained
+F: board/siemens/rut/
+F: include/configs/rut.h
+F: configs/rut_defconfig
diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile
new file mode 100644
index 0000000..f159932
--- /dev/null
+++ b/board/siemens/rut/Makefile
@@ -0,0 +1,21 @@
+#
+# Makefile
+#
+# (C) Copyright 2013 Siemens Schweiz AG
+# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+#
+# Based on:
+# u-boot:/board/ti/am335x/Makefile
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := mux.o
+endif
+
+obj-y += board.o
+ifndef CONFIG_SPL_BUILD
+obj-y += ../common/factoryset.o
+endif
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
new file mode 100644
index 0000000..fb840f7
--- /dev/null
+++ b/board/siemens/rut/board.c
@@ -0,0 +1,493 @@
+/*
+ * Board functions for TI AM335X based rut board
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/board.c
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spi.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <video.h>
+#include <watchdog.h>
+#include "board.h"
+#include "../common/factoryset.h"
+#include "../../../drivers/video/da8xx-fb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+static void board_init_ddr(void)
+{
+struct emif_regs rut_ddr3_emif_reg_data = {
+ .sdram_config = 0x61C04AB2,
+ .sdram_tim1 = 0x0888A39B,
+ .sdram_tim2 = 0x26337FDA,
+ .sdram_tim3 = 0x501F830F,
+ .emif_ddr_phy_ctlr_1 = 0x6,
+ .zq_config = 0x50074BE4,
+ .ref_ctrl = 0x93B,
+};
+
+struct ddr_data rut_ddr3_data = {
+ .datardsratio0 = 0x3b,
+ .datawdsratio0 = 0x85,
+ .datafwsratio0 = 0x100,
+ .datawrsratio0 = 0xc1,
+};
+
+struct cmd_control rut_ddr3_cmd_ctrl_data = {
+ .cmd0csratio = 0x40,
+ .cmd0iclkout = 1,
+ .cmd1csratio = 0x40,
+ .cmd1iclkout = 1,
+ .cmd2csratio = 0x40,
+ .cmd2iclkout = 1,
+};
+
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = RUT_IOCTRL_VAL,
+ .cm1ioctl = RUT_IOCTRL_VAL,
+ .cm2ioctl = RUT_IOCTRL_VAL,
+ .dt0ioctl = RUT_IOCTRL_VAL,
+ .dt1ioctl = RUT_IOCTRL_VAL,
+};
+
+ config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
+ &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
+}
+
+static int request_and_pulse_reset(int gpio, const char *name)
+{
+ int ret;
+ const int delay_us = 2000; /* 2ms */
+
+ ret = gpio_request(gpio, name);
+ if (ret < 0) {
+ printf("%s: Unable to request %s\n", __func__, name);
+ goto err;
+ }
+
+ ret = gpio_direction_output(gpio, 0);
+ if (ret < 0) {
+ printf("%s: Unable to set %s as output\n", __func__, name);
+ goto err_free_gpio;
+ }
+
+ udelay(delay_us);
+
+ gpio_set_value(gpio, 1);
+
+ return 0;
+
+err_free_gpio:
+ gpio_free(gpio);
+err:
+ return ret;
+}
+
+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
+#define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18)
+#define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18)
+#define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19)
+
+#define REQUEST_AND_PULSE_RESET(N) \
+ request_and_pulse_reset(N, #N);
+
+static void spl_siemens_board_init(void)
+{
+ REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
+ REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
+ REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
+}
+#endif /* if def CONFIG_SPL_BUILD */
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 1,
+ .phy_if = PHY_INTERFACE_MODE_RMII,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 0,
+ .phy_if = PHY_INTERFACE_MODE_RMII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+ (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+int board_eth_init(bd_t *bis)
+{
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+ int n = 0;
+ int rv;
+
+#ifndef CONFIG_SPL_BUILD
+ factoryset_setenv();
+#endif
+
+ /* Set rgmii mode and enable rmii clock to be sourced from chip */
+ writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+ return n;
+}
+#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
+#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
+
+#if defined(CONFIG_HW_WATCHDOG)
+static bool hw_watchdog_init_done;
+static int hw_watchdog_trigger_level;
+
+void hw_watchdog_reset(void)
+{
+ if (!hw_watchdog_init_done)
+ return;
+
+ hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
+ gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
+}
+
+void hw_watchdog_init(void)
+{
+ gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
+ gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
+
+ hw_watchdog_reset();
+
+ hw_watchdog_init_done = 1;
+}
+#endif /* defined(CONFIG_HW_WATCHDOG) */
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+static struct da8xx_panel lcd_panels[] = {
+ /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
+ [0] = {
+ .name = "KWH043MC17-F01",
+ .width = 480,
+ .height = 800,
+ .hfp = 50, /* no spec, "don't care" values */
+ .hbp = 50,
+ .hsw = 50,
+ .vfp = 50,
+ .vbp = 50,
+ .vsw = 50,
+ .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
+ .invert_pxl_clk = 1,
+ },
+ /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
+ [1] = {
+ .name = "KWH043ST20-F01",
+ .width = 480,
+ .height = 800,
+ .hfp = 50, /* no spec, "don't care" values */
+ .hbp = 50,
+ .hsw = 50,
+ .vfp = 50,
+ .vbp = 50,
+ .vsw = 50,
+ .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
+ .invert_pxl_clk = 1,
+ },
+ /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
+ [2] = {
+ .name = "MI0430VT-1",
+ .width = 480,
+ .height = 800,
+ .hfp = 50, /* no spec, "don't care" values */
+ .hbp = 50,
+ .hsw = 50,
+ .vfp = 50,
+ .vbp = 50,
+ .vsw = 50,
+ .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
+ .invert_pxl_clk = 1,
+ },
+};
+
+static const struct display_panel disp_panels[] = {
+ [0] = {
+ WVGA,
+ 16, /* RGB 888 */
+ 16,
+ COLOR_ACTIVE,
+ },
+ [1] = {
+ WVGA,
+ 16, /* RGB 888 */
+ 16,
+ COLOR_ACTIVE,
+ },
+ [2] = {
+ WVGA,
+ 24, /* RGB 888 */
+ 16,
+ COLOR_ACTIVE,
+ },
+};
+
+static const struct lcd_ctrl_config lcd_cfgs[] = {
+ [0] = {
+ &disp_panels[0],
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 16,
+ .fdd = 0x80,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+ },
+ [1] = {
+ &disp_panels[1],
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 16,
+ .fdd = 0x80,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+ },
+ [2] = {
+ &disp_panels[2],
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 24,
+ .fdd = 0x80,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+ },
+
+};
+
+/* no console on this board */
+int board_cfb_skip(void)
+{
+ return 1;
+}
+
+#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
+#define PLL_GET_N(v) (v & 0x7f)
+
+static struct dpll_regs dpll_lcd_regs = {
+ .cm_clkmode_dpll = CM_WKUP + 0x98,
+ .cm_idlest_dpll = CM_WKUP + 0x48,
+ .cm_clksel_dpll = CM_WKUP + 0x54,
+};
+
+static int get_clk(struct dpll_regs *dpll_regs)
+{
+ unsigned int val;
+ unsigned int m, n;
+ int f = 0;
+
+ val = readl(dpll_regs->cm_clksel_dpll);
+ m = PLL_GET_M(val);
+ n = PLL_GET_N(val);
+ f = (m * V_OSCK) / n;
+
+ return f;
+};
+
+int clk_get(int clk)
+{
+ return get_clk(&dpll_lcd_regs);
+};
+
+static int conf_disp_pll(int m, int n)
+{
+ struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
+ struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
+#if defined(DISPL_PLL_SPREAD_SPECTRUM)
+ struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
+#endif
+
+ u32 *const clk_domains[] = {
+ &cmper->lcdclkctrl,
+ 0
+ };
+ u32 *const clk_modules_explicit_en[] = {
+ &cmper->lcdclkctrl,
+ &cmper->lcdcclkstctrl,
+ &cmper->spi1clkctrl,
+ 0
+ };
+ do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+
+ do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
+
+#if defined(DISPL_PLL_SPREAD_SPECTRUM)
+ writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
+ writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
+ writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
+ &cmwkup->clkmoddplldisp); /* 0x98 */
+#endif
+ return 0;
+}
+
+static int set_gpio(int gpio, int state)
+{
+ gpio_request(gpio, "temp");
+ gpio_direction_output(gpio, state);
+ gpio_set_value(gpio, state);
+ gpio_free(gpio);
+ return 0;
+}
+
+static int enable_lcd(void)
+{
+ unsigned char buf[1];
+
+ set_gpio(BOARD_LCD_RESET, 0);
+ mdelay(1);
+ set_gpio(BOARD_LCD_RESET, 1);
+ mdelay(1);
+
+ /* spi lcd init */
+ kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
+
+ /* backlight on */
+ buf[0] = 0xf;
+ i2c_write(0x24, 0x7, 1, buf, 1);
+ buf[0] = 0x3f;
+ i2c_write(0x24, 0x8, 1, buf, 1);
+ return 0;
+}
+
+int arch_early_init_r(void)
+{
+ enable_lcd();
+ return 0;
+}
+
+static int board_video_init(void)
+{
+ int i;
+ int anzdisp = ARRAY_SIZE(lcd_panels);
+ int display = 1;
+
+ for (i = 0; i < anzdisp; i++) {
+ if (strncmp((const char *)factory_dat.disp_name,
+ lcd_panels[i].name,
+ strlen((const char *)factory_dat.disp_name)) == 0) {
+ printf("DISPLAY: %s\n", factory_dat.disp_name);
+ break;
+ }
+ }
+ if (i == anzdisp) {
+ i = 1;
+ printf("%s: %s not found, using default %s\n", __func__,
+ factory_dat.disp_name, lcd_panels[i].name);
+ }
+ conf_disp_pll(24, 1);
+ da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
+ lcd_cfgs[display].bpp);
+
+ return 0;
+}
+#endif /* ifdef CONFIG_VIDEO */
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ int ret;
+ char tmp[2 * MAX_STRING_LENGTH + 2];
+
+ omap_nand_switch_ecc(1, 8);
+
+ if (factory_dat.asn[0] != 0)
+ sprintf(tmp, "%s_%s", factory_dat.asn,
+ factory_dat.comp_version);
+ else
+ sprintf(tmp, "QMX7.E38_4.0");
+
+ ret = setenv("boardid", tmp);
+ if (ret)
+ printf("error setting board id\n");
+
+ return 0;
+}
+#endif
+
+#include "../common/board.c"
diff --git a/board/siemens/rut/board.h b/board/siemens/rut/board.h
new file mode 100644
index 0000000..0362612
--- /dev/null
+++ b/board/siemens/rut/board.h
@@ -0,0 +1,22 @@
+/*
+ * board.h
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ * u-boot:/board/ti/am335x/board.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+#endif
diff --git a/board/siemens/rut/mux.c b/board/siemens/rut/mux.c
new file mode 100644
index 0000000..1eced01
--- /dev/null
+++ b/board/siemens/rut/mux.c
@@ -0,0 +1,347 @@
+/*
+ * pinmux setup for siemens rut board
+ *
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * u-boot:/board/ti/am335x/mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux ddr_pin_mux[] = {
+ {OFFSET(ddr_resetn), (MODE(0))},
+ {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_ck), (MODE(0))},
+ {OFFSET(ddr_nck), (MODE(0))},
+ {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_ba1), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_ba2), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a0), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a1), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a2), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a3), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a4), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a5), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a6), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a7), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a8), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a9), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a10), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a11), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a12), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a13), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a14), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_a15), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_odt), (MODE(0))},
+ {OFFSET(ddr_d0), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d1), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d2), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d3), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d4), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d5), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d6), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d7), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d8), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d9), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d10), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d11), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d12), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d13), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d14), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_d15), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_dqm0), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_dqm1), (MODE(0) | PULLUP_EN)},
+ {OFFSET(ddr_dqs0), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_dqsn0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(ddr_dqs1), (MODE(0) | RXACTIVE)},
+ {OFFSET(ddr_dqsn1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(ddr_vref), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ddr_vtp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux lcd_pin_mux[] = {
+ {OFFSET(gpmc_ad8), (MODE(1))},
+ {OFFSET(gpmc_ad9), (MODE(1))},
+ {OFFSET(gpmc_ad10), (MODE(1))},
+ {OFFSET(gpmc_ad11), (MODE(1))},
+ {OFFSET(gpmc_ad12), (MODE(1))},
+ {OFFSET(gpmc_ad13), (MODE(1))},
+ {OFFSET(gpmc_ad14), (MODE(1))},
+ {OFFSET(gpmc_ad15), (MODE(1))},
+ {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},
+ {OFFSET(lcd_vsync), (MODE(0))},
+ {OFFSET(lcd_hsync), (MODE(0))},
+ {OFFSET(lcd_pclk), (MODE(0))},
+ {OFFSET(lcd_ac_bias_en), (MODE(0))},
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux mii_pin_mux[] = {
+ {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_txen), (MODE(1))},
+ {OFFSET(mii1_txd1), (MODE(1))},
+ {OFFSET(mii1_txd0), (MODE(1))},
+ {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
+ {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)},
+ {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)},
+ {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux gpio_pin_mux[] = {
+ {OFFSET(mii1_col), (MODE(7) | RXACTIVE)},
+ {OFFSET(uart1_ctsn), (MODE(7) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(uart1_rtsn), (MODE(7) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(uart1_txd), (MODE(7) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_txclk), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_rxclk), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_rxd3), (MODE(7) | RXACTIVE)},
+ {OFFSET(mii1_rxd2), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a0), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a1), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a4), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a5), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a6), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a7), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE)},
+ {OFFSET(gpmc_wpn), (MODE(7) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(gpmc_be1n), (MODE(7) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(gpmc_csn1), (MODE(7) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(gpmc_csn2), (MODE(7) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(gpmc_csn3), (MODE(7) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mcasp0_aclkr), (MODE(7) | RXACTIVE)},
+ {OFFSET(mcasp0_fsr), (MODE(7))},
+ {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)},
+ {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE)},
+ {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(xdma_event_intr1), (MODE(7) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+ {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux usb0_pin_mux[] = {
+ {OFFSET(usb0_dm), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb0_dp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb0_ce), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb0_id), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb0_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb0_drvvbus), (MODE(0))},
+ {-1},
+};
+
+static struct module_pin_mux usb1_pin_mux[] = {
+ {OFFSET(usb1_dm), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb1_dp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb1_ce), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb1_id), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb1_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(usb1_drvvbus), (MODE(0))},
+ {-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(spi0_cs1), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux spi1_pin_mux[] = {
+ {OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux jtag_pin_mux[] = {
+ {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(tdo), (MODE(0) | PULLUP_EN)},
+ {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(ntrst), (MODE(0) | RXACTIVE)},
+ {-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)},
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUP_EN)},
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUP_EN)},
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)},
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux ainx_pin_mux[] = {
+ {OFFSET(ain7), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain6), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain5), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain4), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain3), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain2), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain1), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ain0), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux rtc_pin_mux[] = {
+ {OFFSET(osc1_in), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(osc1_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux gpmc_pin_mux[] = {
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(gpmc_clk), (MODE(0) | RXACTIVE)},
+ {-1},
+};
+
+static struct module_pin_mux pmic_pin_mux[] = {
+ {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux osc_pin_mux[] = {
+ {OFFSET(osc0_in), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(osc0_out), (MODE(0) | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux pwm_pin_mux[] = {
+ {OFFSET(ecap0_in_pwm0_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(gpmc_a2), (MODE(6))},
+ {OFFSET(gpmc_a3), (MODE(6))},
+ {-1},
+};
+
+static struct module_pin_mux emu_pin_mux[] = {
+ {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+ {-1},
+};
+
+static struct module_pin_mux vref_pin_mux[] = {
+ {OFFSET(vrefp), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(vrefn), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {-1},
+};
+
+static struct module_pin_mux misc_pin_mux[] = {
+ {OFFSET(porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)},
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(ddr_pin_mux);
+ configure_module_pin_mux(lcd_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(mii_pin_mux);
+ configure_module_pin_mux(gpio_pin_mux);
+ configure_module_pin_mux(i2c1_pin_mux);
+ configure_module_pin_mux(usb0_pin_mux);
+ configure_module_pin_mux(usb1_pin_mux);
+ configure_module_pin_mux(spi0_pin_mux);
+ configure_module_pin_mux(spi1_pin_mux);
+ configure_module_pin_mux(jtag_pin_mux);
+ configure_module_pin_mux(nand_pin_mux);
+ configure_module_pin_mux(ainx_pin_mux);
+ configure_module_pin_mux(rtc_pin_mux);
+ configure_module_pin_mux(gpmc_pin_mux);
+ configure_module_pin_mux(pmic_pin_mux);
+ configure_module_pin_mux(osc_pin_mux);
+ configure_module_pin_mux(pwm_pin_mux);
+ configure_module_pin_mux(emu_pin_mux);
+ configure_module_pin_mux(vref_pin_mux);
+ configure_module_pin_mux(misc_pin_mux);
+}
diff --git a/board/siemens/taurus/Kconfig b/board/siemens/taurus/Kconfig
new file mode 100644
index 0000000..c07d244
--- /dev/null
+++ b/board/siemens/taurus/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TAURUS
+
+config SYS_BOARD
+ default "taurus"
+
+config SYS_VENDOR
+ default "siemens"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "taurus"
+
+endif
diff --git a/board/siemens/taurus/MAINTAINERS b/board/siemens/taurus/MAINTAINERS
new file mode 100644
index 0000000..74e3518
--- /dev/null
+++ b/board/siemens/taurus/MAINTAINERS
@@ -0,0 +1,7 @@
+TAURUS BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: board/siemens/taurus/
+F: include/configs/taurus.h
+F: configs/axm_defconfig
+F: configs/taurus_defconfig
diff --git a/board/siemens/taurus/Makefile b/board/siemens/taurus/Makefile
new file mode 100644
index 0000000..a26fb92
--- /dev/null
+++ b/board/siemens/taurus/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for Siemens TAURUS (AT91SAM9G20) based board
+# (C) Copyright 2013 Siemens AG
+#
+# Based on:
+# U-Boot file: board/atmel/at91sam9260ek/Makefile
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += taurus.o
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
new file mode 100644
index 0000000..b8ff478
--- /dev/null
+++ b/board/siemens/taurus/taurus.c
@@ -0,0 +1,240 @@
+/*
+ * Board functions for Siemens TAURUS (AT91SAM9G20) based boards
+ * (C) Copyright Siemens AG
+ *
+ * Based on:
+ * U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91sam9_sdramc.h>
+#include <asm/arch/clk.h>
+#include <linux/mtd/nand.h>
+#include <atmel_mci.h>
+#include <asm/arch/at91_spi.h>
+#include <spi.h>
+
+#include <net.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void taurus_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Assign CS3 to NAND/SmartMedia Interface */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(3),
+ &smc->cs[3].mode);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void matrix_init(void)
+{
+ struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+ writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
+ | AT91_MATRIX_SLOT_CYCLE_(0x40),
+ &mat->scfg[3]);
+}
+
+void at91_spl_board_init(void)
+{
+ taurus_nand_hw_init();
+
+ /* Configure recovery button PINs */
+ at91_set_gpio_input(AT91_PIN_PA31, 1);
+
+ /* check if button is pressed */
+ if (at91_get_gpio_value(AT91_PIN_PA31) == 0) {
+ u32 boot_device;
+
+ debug("Recovery button pressed\n");
+ boot_device = spl_boot_device();
+ switch (boot_device) {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ case BOOT_DEVICE_NAND:
+ nand_init();
+ spl_nand_erase_one(0, 0);
+ break;
+#endif
+ }
+ }
+}
+
+void mem_init(void)
+{
+ struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct sdramc_reg setting;
+
+ at91_sdram_hw_init();
+ setting.cr = (AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_CAS_3 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_DBW_32 |
+ AT91_SDRAMC_TWR_VAL(3) |
+ AT91_SDRAMC_TRC_VAL(9) |
+ AT91_SDRAMC_TRP_VAL(3) |
+ AT91_SDRAMC_TRCD_VAL(3) |
+ AT91_SDRAMC_TRAS_VAL(6) |
+ AT91_SDRAMC_TXSR_VAL(10));
+ setting.mdr = AT91_SDRAMC_MD_SDRAM;
+ setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
+
+
+ writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC |
+ AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL,
+ &ma->ebicsa);
+ sdramc_initialize(ATMEL_BASE_CS1, &setting);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void taurus_macb_hw_init(void)
+{
+ /* Enable EMAC clock */
+ at91_periph_clk_enable(ATMEL_ID_EMAC0);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA17) => PHY normal mode (not Test mode)
+ * ERX0 (PA14) => PHY ADDR0
+ * ERX1 (PA15) => PHY ADDR1
+ * ERX2 (PA25) => PHY ADDR2
+ * ERX3 (PA26) => PHY ADDR3
+ * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0);
+
+ at91_phy_reset();
+
+ at91_set_gpio_input(AT91_PIN_PA25, 1); /* ERST tri-state */
+
+ /* Re-enable pull-up */
+ at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1);
+
+ /* Initialize EMAC=MACB hardware */
+ at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+ at91_mci_hw_init();
+
+ return atmel_mci_init((void *)ATMEL_BASE_MCI);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ /* Enable clocks for all PIOs */
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+ at91_seriald_hw_init();
+
+ return 0;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1);
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+ taurus_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+ taurus_macb_hw_init();
+#endif
+ at91_spi0_hw_init(TAURUS_SPI_MASK);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
+#endif
+ return rc;
+}
diff --git a/board/silica/pengwyn/Kconfig b/board/silica/pengwyn/Kconfig
new file mode 100644
index 0000000..f2e1098
--- /dev/null
+++ b/board/silica/pengwyn/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PENGWYN
+
+config SYS_BOARD
+ default "pengwyn"
+
+config SYS_VENDOR
+ default "silica"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "pengwyn"
+
+endif
diff --git a/board/silica/pengwyn/MAINTAINERS b/board/silica/pengwyn/MAINTAINERS
new file mode 100644
index 0000000..14ef775
--- /dev/null
+++ b/board/silica/pengwyn/MAINTAINERS
@@ -0,0 +1,6 @@
+PENGWYN BOARD
+M: Lothar Felten <lothar.felten@gmail.com>
+S: Maintained
+F: board/silica/pengwyn/
+F: include/configs/pengwyn.h
+F: configs/pengwyn_defconfig
diff --git a/board/silica/pengwyn/Makefile b/board/silica/pengwyn/Makefile
new file mode 100644
index 0000000..804ac37
--- /dev/null
+++ b/board/silica/pengwyn/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y := mux.o
+endif
+
+obj-y += board.o
diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c
new file mode 100644
index 0000000..ee88b6f
--- /dev/null
+++ b/board/silica/pengwyn/board.c
@@ -0,0 +1,207 @@
+/*
+ * board.c
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <phy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#if defined(CONFIG_SPL_BUILD)
+
+/* DDR3 RAM timings */
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41K128MJT187E_RD_DQS,
+ .datawdsratio0 = MT41K128MJT187E_WR_DQS,
+ .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41K128MJT187E_RATIO,
+ .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+ .cmd1csratio = MT41K128MJT187E_RATIO,
+ .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+ .cmd2csratio = MT41K128MJT187E_RATIO,
+ .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41K128MJT187E_EMIF_SDCFG,
+ .ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
+ .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
+ .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
+ .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
+ .zq_config = MT41K128MJT187E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
+};
+
+const struct ctrl_ioregs ddr3_ioregs = {
+ .cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr_266 = {
+ 266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_303 = {
+ 303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_400 = {
+ 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ /*
+ * The pengwyn board uses the TPS650250 PMIC without I2C
+ * interface and will output the following fixed voltages:
+ * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
+ * VLDO1=1V8 (IO) VLDO2=1V8(IO)
+ * Vcore=1V1 is fixed, generated by TPS62231
+ */
+
+ /* Get the frequency */
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* 720MHz cpu, this might change on newer board revisions */
+ dpll_mpu_opp100.m = MPUPLL_M_720;
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ /* future configs can return other clock settings */
+ return &dpll_ddr_303;
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+ config_ddr(303, &ddr3_ioregs, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif /* if CONFIG_SPL_BUILD */
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gpmc_init();
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ .phy_if = PHY_INTERFACE_MODE_MII,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ .phy_if = PHY_INTERFACE_MODE_MII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ printf("<ethaddr> not set. Reading from E-fuse\n");
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ else
+ return n;
+ }
+
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+ return n;
+}
+#endif /* if CONFIG_DRIVER_TI_CPSW */
diff --git a/board/silica/pengwyn/board.h b/board/silica/pengwyn/board.h
new file mode 100644
index 0000000..05addf6
--- /dev/null
+++ b/board/silica/pengwyn/board.h
@@ -0,0 +1,15 @@
+/*
+ * board.h
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+
+#endif
diff --git a/board/silica/pengwyn/mux.c b/board/silica/pengwyn/mux.c
new file mode 100644
index 0000000..c8be440
--- /dev/null
+++ b/board/silica/pengwyn/mux.c
@@ -0,0 +1,98 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
+
+/* I2C pins C16(scl)/C17(sda) */
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */
+ {-1},
+};
+
+/* MMC0 pins */
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+
+/* MII pins */
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+/* NAND pins */
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux()
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(uart0_pin_mux);
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(nand_pin_mux);
+}
diff --git a/board/socrates/Kconfig b/board/socrates/Kconfig
new file mode 100644
index 0000000..ca945c2
--- /dev/null
+++ b/board/socrates/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SOCRATES
+
+config SYS_BOARD
+ default "socrates"
+
+config SYS_CONFIG_NAME
+ default "socrates"
+
+endif
diff --git a/board/socrates/MAINTAINERS b/board/socrates/MAINTAINERS
new file mode 100644
index 0000000..293b8e6
--- /dev/null
+++ b/board/socrates/MAINTAINERS
@@ -0,0 +1,6 @@
+SOCRATES BOARD
+#M: -
+S: Maintained
+F: board/socrates/
+F: include/configs/socrates.h
+F: configs/socrates_defconfig
diff --git a/board/socrates/Makefile b/board/socrates/Makefile
new file mode 100644
index 0000000..79bda71
--- /dev/null
+++ b/board/socrates/Makefile
@@ -0,0 +1,15 @@
+#
+# (C) Copyright 2008
+# Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += socrates.o
+obj-y += law.o
+obj-y += tlb.o
+obj-y += nand.o
+obj-y += sdram.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c
new file mode 100644
index 0000000..6bad4da
--- /dev/null
+++ b/board/socrates/ddr.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 0;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/socrates/law.c b/board/socrates/law.c
new file mode 100644
index 0000000..449a030
--- /dev/null
+++ b/board/socrates/law.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x2fff_ffff DDR 512M
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xc000_0000 0xc00f_ffff FPGA 1M
+ * 0xc800_0000 0xcbff_ffff LIME 64M
+ * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR)
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xfc00_0000 0xffff_ffff FLASH 64M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+#if defined(CONFIG_SYS_FPGA_BASE)
+ SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
+ SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
new file mode 100644
index 0000000..7394478
--- /dev/null
+++ b/board/socrates/nand.c
@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_SYS_NAND_BASE)
+#include <nand.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+static int state;
+static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte);
+static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
+static u_char sc_nand_read_byte(struct mtd_info *mtd);
+static u16 sc_nand_read_word(struct mtd_info *mtd);
+static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
+static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
+#endif
+static int sc_nand_device_ready(struct mtd_info *mtdinfo);
+
+#define FPGA_NAND_CMD_MASK (0x7 << 28)
+#define FPGA_NAND_CMD_COMMAND (0x0 << 28)
+#define FPGA_NAND_CMD_ADDR (0x1 << 28)
+#define FPGA_NAND_CMD_READ (0x2 << 28)
+#define FPGA_NAND_CMD_WRITE (0x3 << 28)
+#define FPGA_NAND_BUSY (0x1 << 15)
+#define FPGA_NAND_ENABLE (0x1 << 31)
+#define FPGA_NAND_DATA_SHIFT 16
+
+/**
+ * sc_nand_write_byte - write one byte to the chip
+ * @mtd: MTD device structure
+ * @byte: pointer to data byte to write
+ */
+static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ sc_nand_write_buf(mtd, (const uchar *)&byte, sizeof(byte));
+}
+
+/**
+ * sc_nand_write_buf - write buffer to chip
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ */
+static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ int i;
+ struct nand_chip *this = mtd->priv;
+
+ for (i = 0; i < len; i++) {
+ out_be32(this->IO_ADDR_W,
+ state | (buf[i] << FPGA_NAND_DATA_SHIFT));
+ }
+}
+
+
+/**
+ * sc_nand_read_byte - read one byte from the chip
+ * @mtd: MTD device structure
+ */
+static u_char sc_nand_read_byte(struct mtd_info *mtd)
+{
+ u8 byte;
+ sc_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
+ return byte;
+}
+
+/**
+ * sc_nand_read_word - read one word from the chip
+ * @mtd: MTD device structure
+ */
+static u16 sc_nand_read_word(struct mtd_info *mtd)
+{
+ u16 word;
+ sc_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
+ return word;
+}
+
+/**
+ * sc_nand_read_buf - read chip data into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ */
+static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ int i;
+ struct nand_chip *this = mtd->priv;
+ int val;
+
+ val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ;
+
+ out_be32(this->IO_ADDR_W, val);
+ for (i = 0; i < len; i++) {
+ buf[i] = (in_be32(this->IO_ADDR_R) >> FPGA_NAND_DATA_SHIFT) & 0xff;
+ }
+}
+
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
+/**
+ * sc_nand_verify_buf - Verify chip data against buffer
+ * @mtd: MTD device structure
+ * @buf: buffer containing the data to compare
+ * @len: number of bytes to compare
+ */
+static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (buf[i] != sc_nand_read_byte(mtd));
+ return -EFAULT;
+ }
+ return 0;
+}
+#endif
+
+/**
+ * sc_nand_device_ready - Check the NAND device is ready for next command.
+ * @mtd: MTD device structure
+ */
+static int sc_nand_device_ready(struct mtd_info *mtdinfo)
+{
+ struct nand_chip *this = mtdinfo->priv;
+
+ if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY)
+ return 0; /* busy */
+ return 1;
+}
+
+/**
+ * sc_nand_hwcontrol - NAND control functions wrapper.
+ * @mtd: MTD device structure
+ * @cmd: Command
+ */
+static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+ if (ctrl & NAND_CTRL_CHANGE) {
+ state &= ~(FPGA_NAND_CMD_MASK | FPGA_NAND_ENABLE);
+
+ switch (ctrl & (NAND_ALE | NAND_CLE)) {
+ case 0:
+ state |= FPGA_NAND_CMD_WRITE;
+ break;
+
+ case NAND_ALE:
+ state |= FPGA_NAND_CMD_ADDR;
+ break;
+
+ case NAND_CLE:
+ state |= FPGA_NAND_CMD_COMMAND;
+ break;
+
+ default:
+ printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl);
+ }
+
+ if (ctrl & NAND_NCE)
+ state |= FPGA_NAND_ENABLE;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ sc_nand_write_byte(mtdinfo, cmd);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ nand->cmd_ctrl = sc_nand_hwcontrol;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->dev_ready = sc_nand_device_ready;
+ nand->read_byte = sc_nand_read_byte;
+ nand->read_word = sc_nand_read_word;
+ nand->write_buf = sc_nand_write_buf;
+ nand->read_buf = sc_nand_read_buf;
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
+ nand->verify_buf = sc_nand_verify_buf;
+#endif
+
+ return 0;
+}
+
+#endif
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
new file mode 100644
index 0000000..aebd02f
--- /dev/null
+++ b/board/socrates/sdram.c
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <spd_sdram.h>
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Autodetect onboard DDR SDRAM on 85xx platforms
+ *
+ * NOTE: Some of the hardcoded values are hardware dependant,
+ * so this should be extended for other future boards
+ * using this routine!
+ */
+phys_size_t fixed_sdram(void)
+{
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+
+ /*
+ * Disable memory controller.
+ */
+ ddr->cs0_config = 0;
+ ddr->sdram_cfg = 0;
+
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+ ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
+
+ asm ("sync;isync;msync");
+ udelay(1000);
+
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
+ asm ("sync; isync; msync");
+ udelay(1000);
+
+ if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
+ /*
+ * OK, size detected -> all done
+ */
+ return CONFIG_SYS_SDRAM_SIZE<<20;
+ }
+
+ return 0; /* nothing found ! */
+}
+#endif
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+ uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+ uint *p;
+
+ printf ("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf ("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf ("SDRAM test passed.\n");
+ return 0;
+}
+#endif
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
new file mode 100644
index 0000000..953a43f
--- /dev/null
+++ b/board/socrates/socrates.c
@@ -0,0 +1,434 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <flash.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include <mb862xx.h>
+#include <video_fb.h>
+#include "upm_table.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[]; /* FLASH chips info */
+extern GraphicDevice mb862xx;
+
+void local_bus_init (void);
+ulong flash_get_size (ulong base, int banknum);
+
+int checkboard (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ char buf[64];
+ int f;
+ int i = getenv_f("serial#", buf, sizeof(buf));
+#ifdef CONFIG_PCI
+ char *src;
+#endif
+
+ puts("Board: Socrates");
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+#ifdef CONFIG_PCI
+ /* Check the PCI_clk sel bit */
+ if (in_be32(&gur->porpllsr) & (1<<15)) {
+ src = "SYSCLK";
+ f = CONFIG_SYS_CLK_FREQ;
+ } else {
+ src = "PCI_CLK";
+ f = CONFIG_PCI_CLK_FREQ;
+ }
+ printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
+#else
+ printf ("PCI1: disabled\n");
+#endif
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+ return 0;
+}
+
+int misc_init_r (void)
+{
+ /*
+ * Adjust flash start and offset to detected values
+ */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
+ /*
+ * Check if boot FLASH isn't max size
+ */
+ if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
+ set_lbc_or(0, gd->bd->bi_flashstart |
+ (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+ set_lbc_br(0, gd->bd->bi_flashstart |
+ (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
+ }
+
+ /*
+ * Check if only one FLASH bank is available
+ */
+ if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
+ set_lbc_or(1, 0);
+ set_lbc_br(1, 0);
+
+ /*
+ * Re-do flash protection upon new addresses
+ */
+ flash_protect (FLAG_PROTECT_CLEAR,
+ gd->bd->bi_flashstart, 0xffffffff,
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+ /* Monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+ /* Environment protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+ /* Redundant environment protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+ }
+
+ return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init (void)
+{
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ sys_info_t sysinfo;
+ uint clkdiv;
+ uint lbc_mhz;
+ uint lcrr = CONFIG_SYS_LBC_LCRR;
+
+ get_sys_info (&sysinfo);
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
+ lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
+
+ /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
+ if (lbc_mhz >= 66)
+ lcrr &= ~LCRR_DBYP; /* DLL Enabled */
+ else
+ lcrr |= LCRR_DBYP; /* DLL Bypass */
+
+ out_be32 (&lbc->lcrr, lcrr);
+ asm ("sync;isync;msync");
+
+ out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
+ out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
+ out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
+ out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
+
+ /* Init UPMA for FPGA access */
+ out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
+ upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
+
+ /* Init UPMB for Lime controller access */
+ out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
+ upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER}},
+ {}
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table:pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+
+void pci_init_board (void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init (&hose);
+#endif /* CONFIG_PCI */
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ /* set and reset the GPIO pin 2 which will reset the W83782G chip */
+ out_8((unsigned char*)&gur->gpoutdr, 0x3F );
+ out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
+ udelay(200);
+ out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
+
+ return (0);
+}
+#endif /* CONFIG_BOARD_EARLY_INIT_R */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[12];
+ int rc, i = 0;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR FLASH mapping */
+ val[i++] = 0; /* chip select number */
+ val[i++] = 0; /* always 0 */
+ val[i++] = gd->bd->bi_flashstart;
+ val[i++] = gd->bd->bi_flashsize;
+
+ if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
+ /* Fixup LIME mapping */
+ val[i++] = 2; /* chip select number */
+ val[i++] = 0; /* always 0 */
+ val[i++] = CONFIG_SYS_LIME_BASE;
+ val[i++] = CONFIG_SYS_LIME_SIZE;
+ }
+
+ /* Fixup FPGA mapping */
+ val[i++] = 3; /* chip select number */
+ val[i++] = 0; /* always 0 */
+ val[i++] = CONFIG_SYS_FPGA_BASE;
+ val[i++] = CONFIG_SYS_FPGA_SIZE;
+
+ rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
+ val, i * sizeof(u32), 1);
+ if (rc)
+ printf("Unable to update localbus ranges, err=%s\n",
+ fdt_strerror(rc));
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#define DEFAULT_BRIGHTNESS 25
+#define BACKLIGHT_ENABLE (1 << 31)
+
+static const gdc_regs init_regs [] =
+{
+ {0x0100, 0x00010f00},
+ {0x0020, 0x801901df},
+ {0x0024, 0x00000000},
+ {0x0028, 0x00000000},
+ {0x002c, 0x00000000},
+ {0x0110, 0x00000000},
+ {0x0114, 0x00000000},
+ {0x0118, 0x01df0320},
+ {0x0004, 0x041f0000},
+ {0x0008, 0x031f031f},
+ {0x000c, 0x017f0349},
+ {0x0010, 0x020c0000},
+ {0x0014, 0x01df01e9},
+ {0x0018, 0x00000000},
+ {0x001c, 0x01e00320},
+ {0x0100, 0x80010f00},
+ {0x0, 0x0}
+};
+
+const gdc_regs *board_get_regs (void)
+{
+ return init_regs;
+}
+
+int lime_probe(void)
+{
+ uint cfg_br2;
+ uint cfg_or2;
+ int type;
+
+ cfg_br2 = get_lbc_br(2);
+ cfg_or2 = get_lbc_or(2);
+
+ /* Configure GPCM for CS2 */
+ set_lbc_br(2, 0);
+ set_lbc_or(2, 0xfc000410);
+ set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
+
+ /* Get controller type */
+ type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
+
+ /* Restore previous CS2 configuration */
+ set_lbc_br(2, 0);
+ set_lbc_or(2, cfg_or2);
+ set_lbc_br(2, cfg_br2);
+
+ return (type == MB862XX_TYPE_LIME) ? 1 : 0;
+}
+
+/* Returns Lime base address */
+unsigned int board_video_init (void)
+{
+ if (!lime_probe())
+ return 0;
+
+ mb862xx.winSizeX = 800;
+ mb862xx.winSizeY = 480;
+ mb862xx.gdfIndex = GDF_15BIT_555RGB;
+ mb862xx.gdfBytesPP = 2;
+
+ return CONFIG_SYS_LIME_BASE;
+}
+
+#define W83782D_REG_CFG 0x40
+#define W83782D_REG_BANK_SEL 0x4e
+#define W83782D_REG_ADCCLK 0x4b
+#define W83782D_REG_BEEP_CTRL 0x4d
+#define W83782D_REG_BEEP_CTRL2 0x57
+#define W83782D_REG_PWMOUT1 0x5b
+#define W83782D_REG_VBAT 0x5d
+
+static int w83782d_hwmon_init(void)
+{
+ u8 buf;
+
+ if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
+ return -1;
+
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);
+
+ buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
+ buf | 0x80);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);
+
+ buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG,
+ (buf & 0xf4) | 0x01);
+ return 0;
+}
+
+static void board_backlight_brightness(int br)
+{
+ u32 reg;
+ u8 buf;
+ u8 old_buf;
+
+ /* Select bank 0 */
+ if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
+ goto err;
+ else
+ buf = old_buf & 0xf8;
+
+ if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
+ goto err;
+
+ if (br > 0) {
+ /* PWMOUT1 duty cycle ctrl */
+ buf = 255 / (100 / br);
+ if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
+ goto err;
+
+ /* LEDs on */
+ reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
+ if (!(reg & BACKLIGHT_ENABLE));
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c),
+ reg | BACKLIGHT_ENABLE);
+ } else {
+ buf = 0;
+ if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
+ goto err;
+
+ /* LEDs off */
+ reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
+ reg &= ~BACKLIGHT_ENABLE;
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg);
+ }
+ /* Restore previous bank setting */
+ if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
+ goto err;
+
+ return;
+err:
+ printf("W83782G I2C access failed\n");
+}
+
+void board_backlight_switch (int flag)
+{
+ char * param;
+ int rc;
+
+ if (w83782d_hwmon_init())
+ printf ("hwmon IC init failed\n");
+
+ if (flag) {
+ param = getenv("brightness");
+ rc = param ? simple_strtol(param, NULL, 10) : -1;
+ if (rc < 0)
+ rc = DEFAULT_BRIGHTNESS;
+ } else {
+ rc = 0;
+ }
+ board_backlight_brightness(rc);
+}
+
+#if defined(CONFIG_CONSOLE_EXTRA_INFO)
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+ if (line_number == 1) {
+ strcpy (info, " Board: Socrates");
+ } else {
+ info [0] = '\0';
+ }
+}
+#endif
diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c
new file mode 100644
index 0000000..f3b093a
--- /dev/null
+++ b/board/socrates/tlb.c
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+
+ /*
+ * TLB 1: 64M Non-cacheable, guarded
+ * 0xfc000000 64M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+#if defined(CONFIG_SYS_FPGA_BASE)
+ /*
+ * TLB 4: 1M Non-cacheable, guarded
+ * 0xc0000000 1M FPGA and NAND
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_1M, 1),
+#endif
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xc8000000 16M LIME GDC framebuffer
+ * 0xc9fc0000 256K LIME GDC MMIO
+ * (0xcbfc0000 256K LIME GDC MMIO)
+ * MMIO is relocatable and could be at 0xcbfc0000
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 6: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_64M, 1),
+
+#if !defined(CONFIG_SPD_EEPROM)
+ /*
+ * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
+ * 0x00000000 512M DDR System memory
+ * Without SPD EEPROM configured DDR, this must be setup manually.
+ * Make sure the TLB count at the top of this table is correct.
+ * Likely it needs to be increased by two for these entries.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_256M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h
new file mode 100644
index 0000000..600d5f0
--- /dev/null
+++ b/board/socrates/upm_table.h
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __UPM_TABLE_H
+#define __UPM_TABLE_H
+
+/* UPM Table Configuration Code for FPGA access */
+static const unsigned int UPMTableA[] =
+{
+ 0x00fcec00, 0x00fcec00, 0x00fcec00, 0x00fcec00, /* Words 0 to 3 */
+ 0x00fcec00, 0x00fcfc00, 0x00fcfc00, 0x00fcec05, /* Words 4 to 7 */
+ 0x00fcec00, 0x00fcec00, 0x00fcec04, 0x00fcec04, /* Words 8 to 11 */
+ 0x00fcec04, 0x00fcec04, 0x00fcec04, 0x00fcec04, /* Words 12 to 15 */
+ 0x00fcec04, 0x00fcec04, 0x0fffec00, 0xffffec00, /* Words 16 to 19 */
+ 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 20 to 23 */
+ 0x00ffec00, 0x00ffec00, 0x00f3ec00, 0x0fffec00, /* Words 24 to 27 */
+ 0x0ffffc04, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 28 to 31 */
+ 0x00ffec00, 0x00ffec00, 0x00f3ec04, 0x00f3ec04, /* Words 32 to 35 */
+ 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, /* Words 36 to 39 */
+ 0x00f3ec04, 0x00f3ec04, 0x0fffec00, 0xffffec00, /* Words 40 to 43 */
+ 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 44 to 47 */
+ 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 48 to 51 */
+ 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 52 to 55 */
+ 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 56 to 59 */
+ 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01 /* Words 60 to 63 */
+};
+
+/* LIME UPM B Table Configuration Code */
+static unsigned int UPMTableB[] =
+{
+ 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */
+ 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffffc01, /* Words 4 to 7 */
+ 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 8 to 11 */
+ 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffcfc04, /* Words 12 to 15 */
+ 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, /* Words 16 to 19 */
+ 0x0ffcfc04, 0x0ffcfc04, 0x0ffffc00, 0xfffffc01, /* Words 20 to 23 */
+ 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */
+ 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x0ffffc01, /* Words 28 to 31 */
+ 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 32 to 35 */
+ 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x00fffc04, /* Words 36 to 39 */
+ 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x00fffc04, /* Words 40 to 43 */
+ 0x00fffc04, 0x00fffc04, 0x0ffffc00, 0xfffffc01, /* Words 44 to 47 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
+ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */
+};
+#endif
diff --git a/board/solidrun/hummingboard/Kconfig b/board/solidrun/hummingboard/Kconfig
new file mode 100644
index 0000000..36b7904
--- /dev/null
+++ b/board/solidrun/hummingboard/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HUMMINGBOARD
+
+config SYS_BOARD
+ default "hummingboard"
+
+config SYS_VENDOR
+ default "solidrun"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "hummingboard"
+
+endif
diff --git a/board/solidrun/hummingboard/MAINTAINERS b/board/solidrun/hummingboard/MAINTAINERS
new file mode 100644
index 0000000..c0c062a
--- /dev/null
+++ b/board/solidrun/hummingboard/MAINTAINERS
@@ -0,0 +1,6 @@
+HUMMINGBOARD BOARD
+M: Jon Nettleton <jon.nettleton@gmail.com>
+S: Maintained
+F: board/solidrun/hummingboard/
+F: include/configs/hummingboard.h
+F: configs/hummingboard_solo_defconfig
diff --git a/board/solidrun/hummingboard/Makefile b/board/solidrun/hummingboard/Makefile
new file mode 100644
index 0000000..042a2f0
--- /dev/null
+++ b/board/solidrun/hummingboard/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+# Copyright (C) 2013, Jon Nettleton <jon.nettleton@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := hummingboard.o
diff --git a/board/solidrun/hummingboard/README b/board/solidrun/hummingboard/README
new file mode 100644
index 0000000..cfd62d4
--- /dev/null
+++ b/board/solidrun/hummingboard/README
@@ -0,0 +1,40 @@
+U-Boot for SolidRun Hummingboard
+--------------------------------
+
+This file contains information for the port of U-Boot to the Hummingboard.
+
+For more details about Hummingboard, please refer to:
+http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware
+
+(Carrier-One was the previous name of Hummingboard).
+
+Building U-boot for Hummingboard
+--------------------------------
+
+To build U-Boot for the Hummingboard Solo version:
+
+$ make hummingboard_solo_config
+$ make
+
+Flashing U-boot into the SD card
+--------------------------------
+
+- After the 'make' command completes, the generated 'u-boot.imx' binary must be
+flashed into the SD card:
+
+$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=1k seek=1; sync
+
+(Note - the SD card node may vary, so adjust this as needed).
+
+Also, a more detailed explanation on how to format the SD card is available
+at doc/README.imximage.
+
+- Insert the micro SD card into the slot located in the bottom of the board
+
+- Connect a 3.3V USB to serial converter cable to the host PC. The MX6 UART
+signals are available in the 26 pin connector as shown at:
+http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware
+(Check for "26 pin header layout").
+
+- Power up the board via USB cable (CON201) and U-boot messages will appear in
+the serial console.
diff --git a/board/solidrun/hummingboard/hummingboard.c b/board/solidrun/hummingboard/hummingboard.c
new file mode 100644
index 0000000..52c384b
--- /dev/null
+++ b/board/solidrun/hummingboard/hummingboard.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
+ *
+ * Authors: Fabio Estevam <fabio.estevam@freescale.com>
+ Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
+ PAD_CTL_HYS)
+
+#define USDHC_PAD_GPIO_CTRL (PAD_CTL_PUS_22K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define ETH_PHY_RESET IMX_GPIO_NR(4, 15)
+
+int dram_init(void)
+{
+ gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(USDHC_PAD_GPIO_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ { USDHC2_BASE_ADDR },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1; /* SD card is the boot medium, so always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* AR8035 reset */
+ MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ /* AR8035 interrupt */
+ MX6_PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* GPIO16 -> AR8035 25MHz */
+ MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ gpio_direction_output(ETH_PHY_RESET, 0);
+ mdelay(2);
+ gpio_set_value(ETH_PHY_RESET, 1);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ int ret = enable_fec_anatop_clock(ENET_25MHZ);
+ if (ret)
+ return ret;
+
+ /* set gpr1[ENET_CLK_SEL] */
+ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+ setup_iomux_enet();
+
+ return cpu_eth_init(bis);
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Hummingboard\n");
+
+ return 0;
+}
diff --git a/board/solidrun/hummingboard/solo.cfg b/board/solidrun/hummingboard/solo.cfg
new file mode 100644
index 0000000..28dd750
--- /dev/null
+++ b/board/solidrun/hummingboard/solo.cfg
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "../mx6-microsom/ddr-800mhz-32bit-setup.cfg"
+#include "../mx6-microsom/800mhz_2x128mx16.cfg"
+#include "../mx6-microsom/clocks.cfg"
diff --git a/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg b/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg
new file mode 100644
index 0000000..40747ab
--- /dev/null
+++ b/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* ZQ Calibrations */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
+/* write leveling */
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x005a0057
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x004a0052
+/*
+ * DQS gating, read delay, write delay calibration values
+ * based on calibration compare of 0x00ffff00
+ */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x02480240
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02340230
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40404440
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x38343034
+/* read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+/* Complete calibration by forced measurement */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/*
+ * MMDC init:
+ * in DDR3, 32-bit mode, only MMDC0 is initiated:
+ */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333040
+
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x3f435313
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8b63
+
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+/* CS0_END - 0x2fffffff, 512M */
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+
+/* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled */
+DATA 4, 0x021b0400, 0x11420000
+
+/* MMDC0_MDCTL- row-14bits; col-10bits; burst length 8;32-bit data bus */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+
+/*
+ * Initialize 2GB DDR3 - Hynix H5TQ2G63BFR-H9C
+ * MR2
+ */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
+/* MR3 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+/* MR1 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
+/* MR0 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+/* final DDR setup */
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/board/solidrun/mx6-microsom/clocks.cfg b/board/solidrun/mx6-microsom/clocks.cfg
new file mode 100644
index 0000000..1288811
--- /dev/null
+++ b/board/solidrun/mx6-microsom/clocks.cfg
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg b/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg
new file mode 100644
index 0000000..f92fc19
--- /dev/null
+++ b/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6DL ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 32 bits x16/x32
+ */
+/* DDR IO TYPE */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* Clock */
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
+/* Address */
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000010
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000010
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000010
+/* Control */
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000010
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000010
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000010
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000010
+
+/*
+ * Data Strobe: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS,
+ * CMOS mode saves power, but have less timing margin in case of DDR
+ * timing issue on your board you can try DDR_MODE: [= 0x00020000]
+ */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
+
+/*
+ * DATA:IOMUXC_SW_PAD_CTL_GRP_DDRMODE - DDR_INPUT=0, CMOS,
+ * CMOS mode saves power, but have less timing margin in case of DDR
+ * timing issue on your board you can try DDR_MODE: [= 0x00020000]
+ */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile
new file mode 100644
index 0000000..b0ba320
--- /dev/null
+++ b/board/spear/common/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-y := spr_misc.o
+obj-y += spr_lowlevel_init.o
+endif
diff --git a/board/spear/common/spr_lowlevel_init.S b/board/spear/common/spr_lowlevel_init.S
new file mode 100644
index 0000000..23a0369
--- /dev/null
+++ b/board/spear/common/spr_lowlevel_init.S
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2006
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+/*
+ * platform specific initializations are already done in Xloader
+ * Initializations already done include
+ * DDR, PLLs, IP's clock enable and reset release etc
+ */
+.globl lowlevel_init
+lowlevel_init:
+ /* By default, U-Boot switches CPU to low-vector */
+ /* Revert this as we work in high vector even in U-Boot */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x00002000
+ mcr p15, 0, r0, c1, c0, 0
+ mov pc, lr
+
+/* void setfreq(unsigned int device, unsigned int frequency) */
+.global setfreq
+setfreq:
+ stmfd sp!,{r14}
+ stmfd sp!,{r0-r12}
+
+ mov r8,sp
+ ldr sp,SRAM_STACK_V
+
+ /* Saving the function arguements for later use */
+ mov r4,r0
+ mov r5,r1
+
+ /* Putting DDR into self refresh */
+ ldr r0,DDR_07_V
+ ldr r1,[r0]
+ ldr r2,DDR_ACTIVE_V
+ bic r1, r1, r2
+ str r1,[r0]
+ ldr r0,DDR_57_V
+ ldr r1,[r0]
+ ldr r2,CYCLES_MASK_V
+ bic r1, r1, r2
+ ldr r2,REFRESH_CYCLES_V
+ orr r1, r1, r2, lsl #16
+ str r1,[r0]
+ ldr r0,DDR_07_V
+ ldr r1,[r0]
+ ldr r2,SREFRESH_MASK_V
+ orr r1, r1, r2
+ str r1,[r0]
+
+ /* flush pipeline */
+ b flush
+ .align 5
+flush:
+ /* Delay to ensure self refresh mode */
+ ldr r0,SREFRESH_DELAY_V
+delay:
+ sub r0,r0,#1
+ cmp r0,#0
+ bne delay
+
+ /* Putting system in slow mode */
+ ldr r0,SCCTRL_V
+ mov r1,#2
+ str r1,[r0]
+
+ /* Changing PLL(1/2) frequency */
+ mov r0,r4
+ mov r1,r5
+
+ cmp r4,#0
+ beq pll1_freq
+
+ /* Change PLL2 (DDR frequency) */
+ ldr r6,PLL2_FREQ_V
+ ldr r7,PLL2_CNTL_V
+ b pll2_freq
+
+pll1_freq:
+ /* Change PLL1 (CPU frequency) */
+ ldr r6,PLL1_FREQ_V
+ ldr r7,PLL1_CNTL_V
+
+pll2_freq:
+ mov r0,r6
+ ldr r1,[r0]
+ ldr r2,PLLFREQ_MASK_V
+ bic r1,r1,r2
+ mov r2,r5,lsr#1
+ orr r1,r1,r2,lsl#24
+ str r1,[r0]
+
+ mov r0,r7
+ ldr r1,P1C0A_V
+ str r1,[r0]
+ ldr r1,P1C0E_V
+ str r1,[r0]
+ ldr r1,P1C06_V
+ str r1,[r0]
+ ldr r1,P1C0E_V
+ str r1,[r0]
+
+lock:
+ ldr r1,[r0]
+ and r1,r1,#1
+ cmp r1,#0
+ beq lock
+
+ /* Putting system back to normal mode */
+ ldr r0,SCCTRL_V
+ mov r1,#4
+ str r1,[r0]
+
+ /* Putting DDR back to normal */
+ ldr r0,DDR_07_V
+ ldr r1,[R0]
+ ldr r2,SREFRESH_MASK_V
+ bic r1, r1, r2
+ str r1,[r0]
+ ldr r2,DDR_ACTIVE_V
+ orr r1, r1, r2
+ str r1,[r0]
+
+ /* Delay to ensure self refresh mode */
+ ldr r0,SREFRESH_DELAY_V
+1:
+ sub r0,r0,#1
+ cmp r0,#0
+ bne 1b
+
+ mov sp,r8
+ /* Resuming back to code */
+ ldmia sp!,{r0-r12}
+ ldmia sp!,{pc}
+
+SCCTRL_V:
+ .word 0xfca00000
+PLL1_FREQ_V:
+ .word 0xfca8000C
+PLL1_CNTL_V:
+ .word 0xfca80008
+PLL2_FREQ_V:
+ .word 0xfca80018
+PLL2_CNTL_V:
+ .word 0xfca80014
+PLLFREQ_MASK_V:
+ .word 0xff000000
+P1C0A_V:
+ .word 0x1C0A
+P1C0E_V:
+ .word 0x1C0E
+P1C06_V:
+ .word 0x1C06
+
+SREFRESH_DELAY_V:
+ .word 0x9999
+SRAM_STACK_V:
+ .word 0xD2800600
+DDR_07_V:
+ .word 0xfc60001c
+DDR_ACTIVE_V:
+ .word 0x01000000
+DDR_57_V:
+ .word 0xfc6000e4
+CYCLES_MASK_V:
+ .word 0xffff0000
+REFRESH_CYCLES_V:
+ .word 0xf0f0
+SREFRESH_MASK_V:
+ .word 0x00010000
+
+.global setfreq_sz
+setfreq_sz:
+ .word setfreq_sz - setfreq
diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
new file mode 100644
index 0000000..bc92cd6
--- /dev/null
+++ b/board/spear/common/spr_misc.c
@@ -0,0 +1,247 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <net.h>
+#include <linux/mtd/st_smi.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_emi.h>
+#include <asm/arch/spr_defs.h>
+
+#define CPU 0
+#define DDR 1
+#define SRAM_REL 0xD2801000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static int i2c_read_mac(uchar *buffer);
+#endif
+
+int dram_init(void)
+{
+ /* Store complete RAM size and return */
+ gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+int board_early_init_f()
+{
+#if defined(CONFIG_ST_SMI)
+ smi_init();
+#endif
+ return 0;
+}
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_NET)
+ uchar mac_id[6];
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
+ eth_setenv_enetaddr("ethaddr", mac_id);
+#endif
+ setenv("verify", "n");
+
+#if defined(CONFIG_SPEAR_USBTTY)
+ setenv("stdin", "usbtty");
+ setenv("stdout", "usbtty");
+ setenv("stderr", "usbtty");
+
+#ifndef CONFIG_SYS_NO_DCACHE
+ dcache_enable();
+#endif
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SPEAR_EMI
+struct cust_emi_para {
+ unsigned int tap;
+ unsigned int tsdp;
+ unsigned int tdpw;
+ unsigned int tdpr;
+ unsigned int tdcs;
+};
+
+/* EMI timing setting of m28w640hc of linux kernel */
+const struct cust_emi_para emi_timing_m28w640hc = {
+ .tap = 0x10,
+ .tsdp = 0x05,
+ .tdpw = 0x0a,
+ .tdpr = 0x0a,
+ .tdcs = 0x05,
+};
+
+/* EMI timing setting of bootrom */
+const struct cust_emi_para emi_timing_bootrom = {
+ .tap = 0xf,
+ .tsdp = 0x0,
+ .tdpw = 0xff,
+ .tdpr = 0x111,
+ .tdcs = 0x02,
+};
+
+void spear_emi_init(void)
+{
+ const struct cust_emi_para *p = &emi_timing_m28w640hc;
+ struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
+ unsigned int cs;
+ unsigned int val, tmp;
+
+ val = readl(CONFIG_SPEAR_RASBASE);
+
+ if (val & EMI_ACKMSK)
+ tmp = 0x3f;
+ else
+ tmp = 0x0;
+
+ writel(tmp, &emi_regs_p->ack);
+
+ for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
+ writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
+ writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
+ writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
+ writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
+ writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
+ writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
+ &emi_regs_p->bank_regs[cs].control);
+ }
+}
+#endif
+
+int spear_board_init(ulong mach_type)
+{
+ gd->bd->bi_arch_number = mach_type;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
+
+#ifdef CONFIG_SPEAR_EMI
+ spear_emi_init();
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_CMD_NET)
+static int i2c_read_mac(uchar *buffer)
+{
+ u8 buf[2];
+
+ i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+ /* Check if mac in i2c memory is valid */
+ if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
+ /* Valid mac address is saved in i2c eeprom */
+ i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN);
+ return 0;
+ }
+
+ return -1;
+}
+
+static int write_mac(uchar *mac)
+{
+ u8 buf[2];
+
+ buf[0] = (u8)MAGIC_BYTE0;
+ buf[1] = (u8)MAGIC_BYTE1;
+ i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+ buf[0] = (u8)~MAGIC_BYTE0;
+ buf[1] = (u8)~MAGIC_BYTE1;
+
+ i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+ /* check if valid MAC address is saved in I2C EEPROM or not? */
+ if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
+ i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN);
+ puts("I2C EEPROM written with mac address \n");
+ return 0;
+ }
+
+ puts("I2C EEPROM writing failed\n");
+ return -1;
+}
+#endif
+
+int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ void (*sram_setfreq) (unsigned int, unsigned int);
+ unsigned int frequency;
+#if defined(CONFIG_CMD_NET)
+ unsigned char mac[6];
+#endif
+
+ if ((argc > 3) || (argc < 2))
+ return cmd_usage(cmdtp);
+
+ if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
+
+ frequency = simple_strtoul(argv[2], NULL, 0);
+
+ if (frequency > 333) {
+ printf("Frequency is limited to 333MHz\n");
+ return 1;
+ }
+
+ sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz);
+
+ if (!strcmp(argv[1], "cpufreq")) {
+ sram_setfreq(CPU, frequency);
+ printf("CPU frequency changed to %u\n", frequency);
+ } else {
+ sram_setfreq(DDR, frequency);
+ printf("DDR frequency changed to %u\n", frequency);
+ }
+
+ return 0;
+
+#if defined(CONFIG_CMD_NET)
+ } else if (!strcmp(argv[1], "ethaddr")) {
+
+ u32 reg;
+ char *e, *s = argv[2];
+ for (reg = 0; reg < 6; ++reg) {
+ mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+ write_mac(mac);
+
+ return 0;
+#endif
+ } else if (!strcmp(argv[1], "print")) {
+#if defined(CONFIG_CMD_NET)
+ if (!i2c_read_mac(mac)) {
+ printf("Ethaddr (from i2c mem) = %pM\n", mac);
+ } else {
+ printf("Ethaddr (from i2c mem) = Not set\n");
+ }
+#endif
+ return 0;
+ }
+
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
+ "configure chip",
+ "chip_config cpufreq/ddrfreq frequency\n"
+#if defined(CONFIG_CMD_NET)
+ "chip_config ethaddr XX:XX:XX:XX:XX:XX\n"
+#endif
+ "chip_config print");
diff --git a/board/spear/spear300/Kconfig b/board/spear/spear300/Kconfig
new file mode 100644
index 0000000..27360f3
--- /dev/null
+++ b/board/spear/spear300/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SPEAR300
+
+config SYS_BOARD
+ default "spear300"
+
+config SYS_VENDOR
+ default "spear"
+
+config SYS_SOC
+ default "spear"
+
+config SYS_CONFIG_NAME
+ default "spear3xx_evb"
+
+endif
diff --git a/board/spear/spear300/MAINTAINERS b/board/spear/spear300/MAINTAINERS
new file mode 100644
index 0000000..07152ae
--- /dev/null
+++ b/board/spear/spear300/MAINTAINERS
@@ -0,0 +1,13 @@
+SPEAR300 BOARD
+M: Vipin Kumar <vipin.kumar@st.com>
+S: Maintained
+F: board/spear/spear300/
+F: include/configs/spear3xx_evb.h
+F: configs/spear300_defconfig
+
+SPEAR300_NAND BOARD
+#M: -
+S: Maintained
+F: configs/spear300_nand_defconfig
+F: configs/spear300_usbtty_defconfig
+F: configs/spear300_usbtty_nand_defconfig
diff --git a/board/spear/spear300/Makefile b/board/spear/spear300/Makefile
new file mode 100644
index 0000000..84d05e3
--- /dev/null
+++ b/board/spear/spear300/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := spear300.o
diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c
new file mode 100644
index 0000000..6b6bd9f
--- /dev/null
+++ b/board/spear/spear300/spear300.c
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+int board_init(void)
+{
+ return spear_board_init(MACH_TYPE_SPEAR300);
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand: mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+void board_nand_init()
+{
+ struct misc_regs *const misc_regs_p =
+ (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ struct nand_chip *nand = &nand_chip[0];
+
+#if defined(CONFIG_NAND_FSMC)
+ if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+ MISC_SOCCFG30) ||
+ ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+ MISC_SOCCFG31)) {
+
+ fsmc_nand_init(nand);
+ }
+#endif
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_DESIGNWARE_ETH)
+ u32 interface = PHY_INTERFACE_MODE_MII;
+ if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
+ ret++;
+#endif
+ return ret;
+}
diff --git a/board/spear/spear310/Kconfig b/board/spear/spear310/Kconfig
new file mode 100644
index 0000000..0c95fa3
--- /dev/null
+++ b/board/spear/spear310/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SPEAR310
+
+config SYS_BOARD
+ default "spear310"
+
+config SYS_VENDOR
+ default "spear"
+
+config SYS_SOC
+ default "spear"
+
+config SYS_CONFIG_NAME
+ default "spear3xx_evb"
+
+endif
diff --git a/board/spear/spear310/MAINTAINERS b/board/spear/spear310/MAINTAINERS
new file mode 100644
index 0000000..4f9aa15
--- /dev/null
+++ b/board/spear/spear310/MAINTAINERS
@@ -0,0 +1,15 @@
+SPEAR310 BOARD
+M: Vipin Kumar <vipin.kumar@st.com>
+S: Maintained
+F: board/spear/spear310/
+F: include/configs/spear3xx_evb.h
+F: configs/spear310_defconfig
+
+SPEAR310_NAND BOARD
+#M: -
+S: Maintained
+F: configs/spear310_nand_defconfig
+F: configs/spear310_pnor_defconfig
+F: configs/spear310_usbtty_defconfig
+F: configs/spear310_usbtty_nand_defconfig
+F: configs/spear310_usbtty_pnor_defconfig
diff --git a/board/spear/spear310/Makefile b/board/spear/spear310/Makefile
new file mode 100644
index 0000000..3a2e3ac
--- /dev/null
+++ b/board/spear/spear310/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := spear310.o
diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c
new file mode 100644
index 0000000..a4c6a8e
--- /dev/null
+++ b/board/spear/spear310/spear310.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2009
+ * Ryan Chen, ST Micoelectronics, ryan.chen@st.com.
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+int board_init(void)
+{
+ return spear_board_init(MACH_TYPE_SPEAR310);
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand: mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+void board_nand_init()
+{
+ struct misc_regs *const misc_regs_p =
+ (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ struct nand_chip *nand = &nand_chip[0];
+
+#if defined(CONFIG_NAND_FSMC)
+ if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+ MISC_SOCCFG30) ||
+ ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+ MISC_SOCCFG31)) {
+
+ fsmc_nand_init(nand);
+ }
+#endif
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_DESIGNWARE_ETH)
+ u32 interface = PHY_INTERFACE_MODE_MII;
+ if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
+ ret++;
+#endif
+#if defined(CONFIG_MACB)
+ if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
+ CONFIG_MACB0_PHY) >= 0)
+ ret++;
+
+ if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE,
+ CONFIG_MACB1_PHY) >= 0)
+ ret++;
+
+ if (macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE,
+ CONFIG_MACB2_PHY) >= 0)
+ ret++;
+
+ if (macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE,
+ CONFIG_MACB3_PHY) >= 0)
+ ret++;
+#endif
+ return ret;
+}
diff --git a/board/spear/spear320/Kconfig b/board/spear/spear320/Kconfig
new file mode 100644
index 0000000..df17623
--- /dev/null
+++ b/board/spear/spear320/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SPEAR320
+
+config SYS_BOARD
+ default "spear320"
+
+config SYS_VENDOR
+ default "spear"
+
+config SYS_SOC
+ default "spear"
+
+config SYS_CONFIG_NAME
+ default "spear3xx_evb"
+
+endif
diff --git a/board/spear/spear320/MAINTAINERS b/board/spear/spear320/MAINTAINERS
new file mode 100644
index 0000000..bf78092
--- /dev/null
+++ b/board/spear/spear320/MAINTAINERS
@@ -0,0 +1,15 @@
+SPEAR320 BOARD
+M: Vipin Kumar <vipin.kumar@st.com>
+S: Maintained
+F: board/spear/spear320/
+F: include/configs/spear3xx_evb.h
+F: configs/spear320_defconfig
+
+SPEAR320_NAND BOARD
+#M: -
+S: Maintained
+F: configs/spear320_nand_defconfig
+F: configs/spear320_pnor_defconfig
+F: configs/spear320_usbtty_defconfig
+F: configs/spear320_usbtty_nand_defconfig
+F: configs/spear320_usbtty_pnor_defconfig
diff --git a/board/spear/spear320/Makefile b/board/spear/spear320/Makefile
new file mode 100644
index 0000000..f01116e
--- /dev/null
+++ b/board/spear/spear320/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := spear320.o
diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c
new file mode 100644
index 0000000..ab732a7
--- /dev/null
+++ b/board/spear/spear320/spear320.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2009
+ * Ryan Chen, ST Micoelectronics, ryan.chen@st.com.
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+
+#define PLGPIO_SEL_36 0xb3000028
+#define PLGPIO_IO_36 0xb3000038
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+static void spear_phy_reset(void)
+{
+ writel(0x10, PLGPIO_IO_36);
+ writel(0x10, PLGPIO_SEL_36);
+}
+
+int board_init(void)
+{
+ spear_phy_reset();
+ return spear_board_init(MACH_TYPE_SPEAR320);
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand: mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+void board_nand_init()
+{
+ struct misc_regs *const misc_regs_p =
+ (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ struct nand_chip *nand = &nand_chip[0];
+
+#if defined(CONFIG_NAND_FSMC)
+ if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+ MISC_SOCCFG30) ||
+ ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+ MISC_SOCCFG31)) {
+
+ fsmc_nand_init(nand);
+ }
+#endif
+
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_DESIGNWARE_ETH)
+ u32 interface = PHY_INTERFACE_MODE_MII;
+ if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
+ ret++;
+#endif
+#if defined(CONFIG_MACB)
+ if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE,
+ CONFIG_MACB0_PHY) >= 0)
+ ret++;
+#endif
+ return ret;
+}
diff --git a/board/spear/spear600/Kconfig b/board/spear/spear600/Kconfig
new file mode 100644
index 0000000..d562e64
--- /dev/null
+++ b/board/spear/spear600/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SPEAR600
+
+config SYS_BOARD
+ default "spear600"
+
+config SYS_VENDOR
+ default "spear"
+
+config SYS_SOC
+ default "spear"
+
+config SYS_CONFIG_NAME
+ default "spear6xx_evb"
+
+endif
diff --git a/board/spear/spear600/MAINTAINERS b/board/spear/spear600/MAINTAINERS
new file mode 100644
index 0000000..ddcd11a
--- /dev/null
+++ b/board/spear/spear600/MAINTAINERS
@@ -0,0 +1,13 @@
+SPEAR600 BOARD
+M: Vipin Kumar <vipin.kumar@st.com>
+S: Maintained
+F: board/spear/spear600/
+F: include/configs/spear6xx_evb.h
+F: configs/spear600_defconfig
+
+SPEAR600_NAND BOARD
+#M: -
+S: Maintained
+F: configs/spear600_nand_defconfig
+F: configs/spear600_usbtty_defconfig
+F: configs/spear600_usbtty_nand_defconfig
diff --git a/board/spear/spear600/Makefile b/board/spear/spear600/Makefile
new file mode 100644
index 0000000..7abfb9a
--- /dev/null
+++ b/board/spear/spear600/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := spear600.o
+endif
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
new file mode 100644
index 0000000..8472002
--- /dev/null
+++ b/board/spear/spear600/spear600.c
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <linux/mtd/fsmc_nand.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+int board_init(void)
+{
+ return spear_board_init(MACH_TYPE_SPEAR600);
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand: mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+void board_nand_init()
+{
+ struct misc_regs *const misc_regs_p =
+ (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ struct nand_chip *nand = &nand_chip[0];
+
+#if defined(CONFIG_NAND_FSMC)
+ if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
+ fsmc_nand_init(nand);
+#endif
+ return;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_DESIGNWARE_ETH)
+ u32 interface = PHY_INTERFACE_MODE_MII;
+#if defined(CONFIG_DW_AUTONEG)
+ interface = PHY_INTERFACE_MODE_GMII;
+#endif
+ if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
+ ret++;
+#endif
+ return ret;
+}
diff --git a/board/spear/x600/Kconfig b/board/spear/x600/Kconfig
new file mode 100644
index 0000000..6a1c5c7
--- /dev/null
+++ b/board/spear/x600/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_X600
+
+config SYS_BOARD
+ default "x600"
+
+config SYS_VENDOR
+ default "spear"
+
+config SYS_SOC
+ default "spear"
+
+config SYS_CONFIG_NAME
+ default "x600"
+
+endif
diff --git a/board/spear/x600/MAINTAINERS b/board/spear/x600/MAINTAINERS
new file mode 100644
index 0000000..bff6824
--- /dev/null
+++ b/board/spear/x600/MAINTAINERS
@@ -0,0 +1,6 @@
+X600 BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/spear/x600/
+F: include/configs/x600.h
+F: configs/x600_defconfig
diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile
new file mode 100644
index 0000000..18d3dd2
--- /dev/null
+++ b/board/spear/x600/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-y := fpga.o x600.o
+endif
diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c
new file mode 100644
index 0000000..b256222
--- /dev/null
+++ b/board/spear/x600/fpga.c
@@ -0,0 +1,264 @@
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_ssp.h>
+
+/*
+ * FPGA program pin configuration on X600:
+ *
+ * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
+ * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
+ * 16bit serial writes via this SSP port to write the data bits into the
+ * FPGA.
+ */
+#define CONFIG_SYS_FPGA_PROG 2
+#define CONFIG_SYS_FPGA_DONE 3
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+static void fpga_reset(int assert)
+{
+ /*
+ * On x600 we have no means to toggle the FPGA reset signal
+ */
+ debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
+}
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+static int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+ debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
+
+ gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
+
+ return assert;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
+ * asserted (low).
+ */
+static int fpga_init_fn(int cookie)
+{
+ static int state;
+
+ debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
+
+ /*
+ * On x600, the FPGA INIT signal is not connected to the SoC.
+ * We can't read the INIT status. Let's return the "correct"
+ * INIT signal state generated via a local state-machine.
+ */
+ if (++state == 1) {
+ return 1;
+ } else {
+ state = 0;
+ return 0;
+ }
+}
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+static int fpga_done_fn(int cookie)
+{
+ struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+
+ /*
+ * Wait for Tx-FIFO to become empty before looking for DONE
+ */
+ while (!(readl(&ssp->sspsr) & SSPSR_TFE))
+ ;
+
+ if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
+ return 1;
+ else
+ return 0;
+}
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+static int fpga_pre_config_fn(int cookie)
+{
+ debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
+ fpga_reset(true);
+
+ return 0;
+}
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+static int fpga_post_config_fn(int cookie)
+{
+ int rc = 0;
+
+ debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
+
+ fpga_reset(true);
+ udelay(100);
+ fpga_reset(false);
+ udelay(100);
+
+ return rc;
+}
+
+static int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ /*
+ * No dedicated clock signal on x600 (data & clock generated)
+ * in SSP interface. So we don't have to do anything here.
+ */
+ return assert_clk;
+}
+
+static int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+ struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+ static int count;
+ static u16 data;
+
+ /*
+ * First collect 16 bits of data
+ */
+ data = data << 1;
+ if (assert_write)
+ data |= 1;
+
+ /*
+ * If 16 bits are not available, return for more bits
+ */
+ count++;
+ if (count != 16)
+ return assert_write;
+
+ count = 0;
+
+ /*
+ * Wait for Tx-FIFO to become ready
+ */
+ while (!(readl(&ssp->sspsr) & SSPSR_TNF))
+ ;
+
+ /* Send 16 bits to FPGA via SSP bus */
+ writel(data, &ssp->sspdr);
+
+ return assert_write;
+}
+
+static xilinx_spartan3_slave_serial_fns x600_fpga_fns = {
+ fpga_pre_config_fn,
+ fpga_pgm_fn,
+ fpga_clk_fn,
+ fpga_init_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_post_config_fn,
+};
+
+static xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+ XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
+};
+
+/*
+ * Initialize the SelectMap interface. We assume that the mode and the
+ * initial state of all of the port pins have already been set!
+ */
+static void fpga_serialslave_init(void)
+{
+ debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
+ fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
+}
+
+static int expi_setup(int freq)
+{
+ struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
+
+ pll2_m = (freq * 2) / 1000;
+ pll2_n = 15;
+ pll2_p = 1;
+ expi_x = 1;
+ expi_y = 2;
+
+ /*
+ * Disable reset, Low compression, Disable retiming, Enable Expi,
+ * Enable soft reset, DMA, PLL2, Internal
+ */
+ writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
+ EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
+ EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
+ &misc->expi_clk_cfg);
+
+ /*
+ * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
+ * Enable PLL2, Disable reset
+ */
+ writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
+ writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
+ PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
+
+ /*
+ * Disable soft reset
+ */
+ clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
+
+ return 0;
+}
+
+/*
+ * Initialize the fpga
+ */
+int x600_init_fpga(void)
+{
+ struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+ struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+ /* Enable SSP2 clock */
+ writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
+ &misc->periph1_clken);
+
+ /* Set EXPI clock to 45 MHz */
+ expi_setup(45000);
+
+ /* Configure GPIO directions */
+ gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
+ gpio_direction_input(CONFIG_SYS_FPGA_DONE);
+
+ writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
+ writel(SSPCR1_SSE, &ssp->sspcr1);
+
+ /*
+ * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
+ * speed.
+ *
+ * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
+ * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
+ */
+ writel(2, &ssp->sspcpsr);
+
+ fpga_init();
+ fpga_serialslave_init();
+
+ debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
+ fpga_add(fpga_xilinx, &fpga[0]);
+
+ return 0;
+}
diff --git a/board/spear/x600/fpga.h b/board/spear/x600/fpga.h
new file mode 100644
index 0000000..3d519a5
--- /dev/null
+++ b/board/spear/x600/fpga.h
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+int x600_init_fpga(void);
diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c
new file mode 100644
index 0000000..b8edfcd
--- /dev/null
+++ b/board/spear/x600/x600.c
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <netdev.h>
+#include <phy.h>
+#include <rtc.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <linux/mtd/fsmc_nand.h>
+#include "fpga.h"
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+int board_init(void)
+{
+ /*
+ * X600 is equipped with an M41T82 RTC. This RTC has the
+ * HT bit (Halt Update), which needs to be cleared upon
+ * power-up. Otherwise the RTC is halted.
+ */
+ rtc_reset();
+
+ return spear_board_init(MACH_TYPE_SPEAR600);
+}
+
+int board_late_init(void)
+{
+ /*
+ * Monitor and env protection on by default
+ */
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
+ CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
+ 2 * CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+
+ /* Init FPGA subsystem */
+ x600_init_fpga();
+
+ return 0;
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand: mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+void board_nand_init(void)
+{
+ struct misc_regs *const misc_regs_p =
+ (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+ struct nand_chip *nand = &nand_chip[0];
+
+ if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
+ fsmc_nand_init(nand);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* Extended PHY control 1, select GMII */
+ phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
+
+ /* Software reset necessary after GMII mode selction */
+ phy_reset(phydev);
+
+ /* Enable extended page register access */
+ phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
+
+ /* 17e: Enhanced LED behavior, needs to be written twice */
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+
+ /* 16e: Enhanced LED method select */
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
+
+ /* Disable extended page register access */
+ phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
+
+ /* Enable clock output pin */
+ phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+ if (designware_initialize(CONFIG_SPEAR_ETHBASE,
+ PHY_INTERFACE_MODE_GMII) >= 0)
+ ret++;
+
+ return ret;
+}
diff --git a/board/st-ericsson/snowball/Kconfig b/board/st-ericsson/snowball/Kconfig
new file mode 100644
index 0000000..0b3a0cc
--- /dev/null
+++ b/board/st-ericsson/snowball/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SNOWBALL
+
+config SYS_BOARD
+ default "snowball"
+
+config SYS_VENDOR
+ default "st-ericsson"
+
+config SYS_SOC
+ default "u8500"
+
+config SYS_CONFIG_NAME
+ default "snowball"
+
+endif
diff --git a/board/st-ericsson/snowball/MAINTAINERS b/board/st-ericsson/snowball/MAINTAINERS
new file mode 100644
index 0000000..132fc52
--- /dev/null
+++ b/board/st-ericsson/snowball/MAINTAINERS
@@ -0,0 +1,6 @@
+SNOWBALL BOARD
+M: Mathieu Poirier <mathieu.poirier@linaro.org>
+S: Maintained
+F: board/st-ericsson/snowball/
+F: include/configs/snowball.h
+F: configs/snowball_defconfig
diff --git a/board/st-ericsson/snowball/Makefile b/board/st-ericsson/snowball/Makefile
new file mode 100644
index 0000000..f0605e2
--- /dev/null
+++ b/board/st-ericsson/snowball/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) ST-Ericsson SA 2009
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ccflags-y += -D__RELEASE -D__STN_8500
+
+obj-y := snowball.o
diff --git a/board/st-ericsson/snowball/db8500_pins.h b/board/st-ericsson/snowball/db8500_pins.h
new file mode 100644
index 0000000..e339cb8
--- /dev/null
+++ b/board/st-ericsson/snowball/db8500_pins.h
@@ -0,0 +1,745 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
+ * The purpose is that GPIO config found in kernel should work by simply
+ * copy-paste it to U-boot.
+ *
+ * Ported to U-boot by:
+ * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
+ **
+ * License terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com>
+ */
+
+#ifndef __DB8500_PINS_H
+#define __DB8500_PINS_H
+
+#include <asm/arch/db8500_pincfg.h>
+
+#define GPIO0_GPIO PIN_CFG(0, GPIO)
+#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A)
+#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B)
+#define GPIO0_IP_TDO PIN_CFG(0, ALT_C)
+
+#define GPIO1_GPIO PIN_CFG(1, GPIO)
+#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A)
+#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B)
+#define GPIO1_IP_TDI PIN_CFG(1, ALT_C)
+
+#define GPIO2_GPIO PIN_CFG(2, GPIO)
+#define GPIO2_U0_RXD PIN_CFG(2, ALT_A)
+#define GPIO2_NONE PIN_CFG(2, ALT_B)
+#define GPIO2_IP_TMS PIN_CFG(2, ALT_C)
+
+#define GPIO3_GPIO PIN_CFG(3, GPIO)
+#define GPIO3_U0_TXD PIN_CFG(3, ALT_A)
+#define GPIO3_NONE PIN_CFG(3, ALT_B)
+#define GPIO3_IP_TCK PIN_CFG(3, ALT_C)
+
+#define GPIO4_GPIO PIN_CFG(4, GPIO)
+#define GPIO4_U1_RXD PIN_CFG(4, ALT_A)
+#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP)
+#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C)
+
+#define GPIO5_GPIO PIN_CFG(5, GPIO)
+#define GPIO5_U1_TXD PIN_CFG(5, ALT_A)
+#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP)
+#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C)
+
+#define GPIO6_GPIO PIN_CFG(6, GPIO)
+#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A)
+#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP)
+#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C)
+
+#define GPIO7_GPIO PIN_CFG(7, GPIO)
+#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A)
+#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP)
+#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C)
+
+#define GPIO8_GPIO PIN_CFG(8, GPIO)
+#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP)
+#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP)
+
+#define GPIO9_GPIO PIN_CFG(9, GPIO)
+#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP)
+#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP)
+
+#define GPIO10_GPIO PIN_CFG(10, GPIO)
+#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP)
+#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP)
+#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C)
+
+#define GPIO11_GPIO PIN_CFG(11, GPIO)
+#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP)
+#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP)
+#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C)
+
+#define GPIO12_GPIO PIN_CFG(12, GPIO)
+#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A)
+#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B)
+
+#define GPIO13_GPIO PIN_CFG(13, GPIO)
+#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A)
+
+#define GPIO14_GPIO PIN_CFG(14, GPIO)
+#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A)
+
+#define GPIO15_GPIO PIN_CFG(15, GPIO)
+#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A)
+#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B)
+
+#define GPIO16_GPIO PIN_CFG(16, GPIO)
+#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A)
+#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP)
+#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C)
+
+#define GPIO17_GPIO PIN_CFG(17, GPIO)
+#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A)
+#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP)
+#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C)
+
+#define GPIO18_GPIO PIN_CFG(18, GPIO)
+#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A)
+#define GPIO18_U2_RXD PIN_CFG(18, ALT_B)
+#define GPIO18_MS_IEP PIN_CFG(18, ALT_C)
+
+#define GPIO19_GPIO PIN_CFG(19, GPIO)
+#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A)
+#define GPIO19_U2_TXD PIN_CFG(19, ALT_B)
+#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C)
+
+#define GPIO20_GPIO PIN_CFG(20, GPIO)
+#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A)
+#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B)
+#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C)
+
+#define GPIO21_GPIO PIN_CFG(21, GPIO)
+#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A)
+#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B)
+#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C)
+
+#define GPIO22_GPIO PIN_CFG(22, GPIO)
+#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A)
+#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B)
+#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C)
+
+#define GPIO23_GPIO PIN_CFG(23, GPIO)
+#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A)
+#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B)
+#define GPIO23_MS_CLK PIN_CFG(23, ALT_C)
+
+#define GPIO24_GPIO PIN_CFG(24, GPIO)
+#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A)
+#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B)
+#define GPIO24_MS_BS PIN_CFG(24, ALT_C)
+
+#define GPIO25_GPIO PIN_CFG(25, GPIO)
+#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A)
+#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B)
+#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C)
+
+#define GPIO26_GPIO PIN_CFG(26, GPIO)
+#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A)
+#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B)
+#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C)
+
+#define GPIO27_GPIO PIN_CFG(27, GPIO)
+#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A)
+#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B)
+#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C)
+
+#define GPIO28_GPIO PIN_CFG(28, GPIO)
+#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A)
+#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B)
+#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C)
+
+#define GPIO29_GPIO PIN_CFG(29, GPIO)
+#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A)
+#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B)
+#define GPIO29_U2_RXD PIN_CFG(29, ALT_C)
+
+#define GPIO30_GPIO PIN_CFG(30, GPIO)
+#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A)
+#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B)
+#define GPIO30_U2_TXD PIN_CFG(30, ALT_C)
+
+#define GPIO31_GPIO PIN_CFG(31, GPIO)
+#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A)
+#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B)
+#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C)
+
+#define GPIO32_GPIO PIN_CFG(32, GPIO)
+#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A)
+#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B)
+#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C)
+
+#define GPIO33_GPIO PIN_CFG(33, GPIO)
+#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A)
+#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B)
+#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C)
+
+#define GPIO34_GPIO PIN_CFG(34, GPIO)
+#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A)
+#define GPIO34_NONE PIN_CFG(34, ALT_B)
+#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C)
+
+#define GPIO35_GPIO PIN_CFG(35, GPIO)
+#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A)
+#define GPIO35_NONE PIN_CFG(35, ALT_B)
+#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C)
+
+#define GPIO36_GPIO PIN_CFG(36, GPIO)
+#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A)
+#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B)
+#define GPIO36_U0_RIn PIN_CFG(36, ALT_C)
+
+#define GPIO64_GPIO PIN_CFG(64, GPIO)
+#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A)
+#define GPIO64_KP_O1 PIN_CFG(64, ALT_B)
+#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C)
+
+#define GPIO65_GPIO PIN_CFG(65, GPIO)
+#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A)
+#define GPIO65_KP_O0 PIN_CFG(65, ALT_B)
+#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C)
+
+#define GPIO66_GPIO PIN_CFG(66, GPIO)
+#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A)
+#define GPIO66_KP_I1 PIN_CFG(66, ALT_B)
+#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C)
+
+#define GPIO67_GPIO PIN_CFG(67, GPIO)
+#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A)
+#define GPIO67_KP_I0 PIN_CFG(67, ALT_B)
+#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C)
+
+#define GPIO68_GPIO PIN_CFG(68, GPIO)
+#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A)
+#define GPIO68_KP_O7 PIN_CFG(68, ALT_B)
+#define GPIO68_SM_CLE PIN_CFG(68, ALT_C)
+
+#define GPIO69_GPIO PIN_CFG(69, GPIO)
+#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A)
+#define GPIO69_KP_I7 PIN_CFG(69, ALT_B)
+#define GPIO69_SM_ALE PIN_CFG(69, ALT_C)
+
+#define GPIO70_GPIO PIN_CFG(70, GPIO)
+#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A)
+#define GPIO70_KP_O5 PIN_CFG(70, ALT_B)
+#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C)
+
+#define GPIO71_GPIO PIN_CFG(71, GPIO)
+#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A)
+#define GPIO71_KP_O4 PIN_CFG(71, ALT_B)
+#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C)
+
+#define GPIO72_GPIO PIN_CFG(72, GPIO)
+#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A)
+#define GPIO72_KP_O3 PIN_CFG(72, ALT_B)
+#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C)
+
+#define GPIO73_GPIO PIN_CFG(73, GPIO)
+#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A)
+#define GPIO73_KP_O2 PIN_CFG(73, ALT_B)
+#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C)
+
+#define GPIO74_GPIO PIN_CFG(74, GPIO)
+#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A)
+#define GPIO74_KP_I5 PIN_CFG(74, ALT_B)
+#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C)
+
+#define GPIO75_GPIO PIN_CFG(75, GPIO)
+#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A)
+#define GPIO75_KP_I4 PIN_CFG(75, ALT_B)
+#define GPIO75_U2_RXD PIN_CFG(75, ALT_C)
+
+#define GPIO76_GPIO PIN_CFG(76, GPIO)
+#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A)
+#define GPIO76_KP_I3 PIN_CFG(76, ALT_B)
+#define GPIO76_U2_TXD PIN_CFG(76, ALT_C)
+
+#define GPIO77_GPIO PIN_CFG(77, GPIO)
+#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A)
+#define GPIO77_KP_I2 PIN_CFG(77, ALT_B)
+#define GPIO77_NONE PIN_CFG(77, ALT_C)
+
+#define GPIO78_GPIO PIN_CFG(78, GPIO)
+#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A)
+#define GPIO78_KP_O6 PIN_CFG(78, ALT_B)
+#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C)
+
+#define GPIO79_GPIO PIN_CFG(79, GPIO)
+#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A)
+#define GPIO79_KP_I6 PIN_CFG(79, ALT_B)
+#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C)
+
+#define GPIO80_GPIO PIN_CFG(80, GPIO)
+#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A)
+#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B)
+#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C)
+
+#define GPIO81_GPIO PIN_CFG(81, GPIO)
+#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A)
+#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B)
+#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C)
+
+#define GPIO82_GPIO PIN_CFG(82, GPIO)
+#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A)
+#define GPIO82_KP_O5 PIN_CFG(82, ALT_B)
+
+#define GPIO83_GPIO PIN_CFG(83, GPIO)
+#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A)
+#define GPIO83_KP_O4 PIN_CFG(83, ALT_B)
+
+#define GPIO84_GPIO PIN_CFG_PULL(84, GPIO, UP)
+#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A)
+#define GPIO84_KP_I5 PIN_CFG(84, ALT_B)
+
+#define GPIO85_GPIO PIN_CFG(85, GPIO)
+#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A)
+#define GPIO85_KP_I4 PIN_CFG(85, ALT_B)
+
+#define GPIO86_GPIO PIN_CFG(86, GPIO)
+#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A)
+#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B)
+#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C)
+
+#define GPIO87_GPIO PIN_CFG(87, GPIO)
+#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A)
+#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B)
+#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C)
+
+#define GPIO88_GPIO PIN_CFG(88, GPIO)
+#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A)
+#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B)
+#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C)
+
+#define GPIO89_GPIO PIN_CFG(89, GPIO)
+#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A)
+#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B)
+#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C)
+
+#define GPIO90_GPIO PIN_CFG(90, GPIO)
+#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A)
+#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B)
+#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C)
+
+#define GPIO91_GPIO PIN_CFG(91, GPIO)
+#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A)
+#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B)
+#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C)
+
+#define GPIO92_GPIO PIN_CFG(92, GPIO)
+#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A)
+#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B)
+#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C)
+
+#define GPIO93_GPIO PIN_CFG(93, GPIO)
+#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A)
+#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B)
+#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C)
+
+#define GPIO94_GPIO PIN_CFG(94, GPIO)
+#define GPIO94_KP_O7 PIN_CFG(94, ALT_A)
+#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B)
+#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C)
+
+#define GPIO95_GPIO PIN_CFG(95, GPIO)
+#define GPIO95_KP_I7 PIN_CFG(95, ALT_A)
+#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B)
+#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C)
+
+#define GPIO96_GPIO PIN_CFG(96, GPIO)
+#define GPIO96_KP_O6 PIN_CFG(96, ALT_A)
+#define GPIO96_SM_OEn PIN_CFG(96, ALT_B)
+#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C)
+
+#define GPIO97_GPIO PIN_CFG(97, GPIO)
+#define GPIO97_KP_I6 PIN_CFG(97, ALT_A)
+#define GPIO97_SM_WEn PIN_CFG(97, ALT_B)
+#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C)
+
+#define GPIO128_GPIO PIN_CFG(128, GPIO)
+#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A)
+#define GPIO128_SM_CKO PIN_CFG(128, ALT_B)
+
+#define GPIO129_GPIO PIN_CFG(129, GPIO)
+#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A)
+#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B)
+
+#define GPIO130_GPIO PIN_CFG(130, GPIO)
+#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A)
+#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B)
+#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C)
+
+#define GPIO131_GPIO PIN_CFG(131, GPIO)
+#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A)
+#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B)
+
+#define GPIO132_GPIO PIN_CFG(132, GPIO)
+#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A)
+#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B)
+
+#define GPIO133_GPIO PIN_CFG(133, GPIO)
+#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A)
+#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B)
+
+#define GPIO134_GPIO PIN_CFG(134, GPIO)
+#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A)
+#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B)
+
+#define GPIO135_GPIO PIN_CFG(135, GPIO)
+#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A)
+#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B)
+
+#define GPIO136_GPIO PIN_CFG(136, GPIO)
+#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A)
+#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B)
+
+#define GPIO137_GPIO PIN_CFG(137, GPIO)
+#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A)
+#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B)
+
+#define GPIO138_GPIO PIN_CFG(138, GPIO)
+#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A)
+#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B)
+
+#define GPIO139_GPIO PIN_CFG(139, GPIO)
+#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A)
+#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B)
+#define GPIO139_KP_O8 PIN_CFG(139, ALT_C)
+
+#define GPIO140_GPIO PIN_CFG(140, GPIO)
+#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A)
+#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B)
+#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C)
+
+#define GPIO141_GPIO PIN_CFG(141, GPIO)
+#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A)
+#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B)
+#define GPIO141_KP_O9 PIN_CFG(141, ALT_C)
+
+#define GPIO142_GPIO PIN_CFG(142, GPIO)
+#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A)
+#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B)
+#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C)
+
+#define GPIO143_GPIO PIN_CFG(143, GPIO)
+#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A)
+
+#define GPIO144_GPIO PIN_CFG(144, GPIO)
+#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A)
+
+#define GPIO145_GPIO PIN_CFG(145, GPIO)
+#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A)
+
+#define GPIO146_GPIO PIN_CFG(146, GPIO)
+#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A)
+
+#define GPIO147_GPIO PIN_CFG(147, GPIO)
+#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP)
+
+#define GPIO148_GPIO PIN_CFG(148, GPIO)
+#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP)
+
+#define GPIO149_GPIO PIN_CFG(149, GPIO)
+#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A)
+#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B)
+#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C)
+
+#define GPIO150_GPIO PIN_CFG(150, GPIO)
+#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A)
+#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B)
+
+#define GPIO151_GPIO PIN_CFG(151, GPIO)
+#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A)
+#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B)
+#define GPIO151_KP_O8 PIN_CFG(151, ALT_C)
+
+#define GPIO152_GPIO PIN_CFG(152, GPIO)
+#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A)
+#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B)
+#define GPIO152_KP_O9 PIN_CFG(152, ALT_C)
+
+#define GPIO153_GPIO PIN_CFG(153, GPIO)
+#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN)
+#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B)
+#define GPIO153_U2_RXD PIN_CFG(153, ALT_C)
+
+#define GPIO154_GPIO PIN_CFG(154, GPIO)
+#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN)
+#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B)
+#define GPIO154_U2_TXD PIN_CFG(154, ALT_C)
+
+#define GPIO155_GPIO PIN_CFG(155, GPIO)
+#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN)
+#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B)
+#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C)
+
+#define GPIO156_GPIO PIN_CFG(156, GPIO)
+#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN)
+#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B)
+#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C)
+
+#define GPIO157_GPIO PIN_CFG(157, GPIO)
+#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP)
+#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B)
+#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C)
+
+#define GPIO158_GPIO PIN_CFG(158, GPIO)
+#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP)
+#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B)
+#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C)
+
+#define GPIO159_GPIO PIN_CFG(159, GPIO)
+#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP)
+#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B)
+#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C)
+
+#define GPIO160_GPIO PIN_CFG(160, GPIO)
+#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP)
+#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B)
+#define GPIO160_NONE PIN_CFG(160, ALT_C)
+
+#define GPIO161_GPIO PIN_CFG(161, GPIO)
+#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN)
+#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B)
+#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C)
+
+#define GPIO162_GPIO PIN_CFG(162, GPIO)
+#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN)
+#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B)
+#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C)
+
+#define GPIO163_GPIO PIN_CFG(163, GPIO)
+#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN)
+#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B)
+#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C)
+
+#define GPIO164_GPIO PIN_CFG(164, GPIO)
+#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP)
+#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B)
+#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C)
+
+#define GPIO165_GPIO PIN_CFG(165, GPIO)
+#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP)
+#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B)
+#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C)
+
+#define GPIO166_GPIO PIN_CFG(166, GPIO)
+#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP)
+#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B)
+#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C)
+
+#define GPIO167_GPIO PIN_CFG(167, GPIO)
+#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP)
+#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B)
+#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C)
+
+#define GPIO168_GPIO PIN_CFG(168, GPIO)
+#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP)
+#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B)
+#define GPIO168_NONE PIN_CFG(168, ALT_C)
+
+#define GPIO169_GPIO PIN_CFG(169, GPIO)
+#define GPIO169_RF_PURn PIN_CFG(169, ALT_A)
+#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B)
+#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C)
+
+#define GPIO170_GPIO PIN_CFG(170, GPIO)
+#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A)
+#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B)
+#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C)
+
+#define GPIO171_GPIO PIN_CFG(171, GPIO)
+#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A)
+#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B)
+#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C)
+
+#define GPIO192_GPIO PIN_CFG(192, GPIO)
+#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A)
+
+#define GPIO193_GPIO PIN_CFG(193, GPIO)
+#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A)
+
+#define GPIO194_GPIO PIN_CFG(194, GPIO)
+#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A)
+
+#define GPIO195_GPIO PIN_CFG(195, GPIO)
+#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A)
+
+#define GPIO196_GPIO PIN_CFG(196, GPIO)
+#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A)
+
+#define GPIO197_GPIO PIN_CFG(197, GPIO)
+#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A)
+
+#define GPIO198_GPIO PIN_CFG(198, GPIO)
+#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A)
+
+#define GPIO199_GPIO PIN_CFG(199, GPIO)
+#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A)
+
+#define GPIO200_GPIO PIN_CFG(200, GPIO)
+#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A)
+
+#define GPIO201_GPIO PIN_CFG(201, GPIO)
+#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A)
+
+#define GPIO202_GPIO PIN_CFG(202, GPIO)
+#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A)
+#define GPIO202_PWL PIN_CFG(202, ALT_B)
+#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C)
+
+#define GPIO203_GPIO PIN_CFG(203, GPIO)
+#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A)
+
+#define GPIO204_GPIO PIN_CFG(204, GPIO)
+#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A)
+
+#define GPIO205_GPIO PIN_CFG(205, GPIO)
+#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A)
+
+#define GPIO206_GPIO PIN_CFG(206, GPIO)
+#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A)
+
+#define GPIO207_GPIO PIN_CFG(207, GPIO)
+#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A)
+
+#define GPIO208_GPIO PIN_CFG(208, GPIO)
+#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A)
+
+#define GPIO209_GPIO PIN_CFG(209, GPIO)
+#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A)
+#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B)
+
+#define GPIO210_GPIO PIN_CFG(210, GPIO)
+#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A)
+
+#define GPIO211_GPIO PIN_CFG(211, GPIO)
+#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A)
+
+#define GPIO212_GPIO PIN_CFG(212, GPIO)
+#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A)
+#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B)
+
+#define GPIO213_GPIO PIN_CFG(213, GPIO)
+#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A)
+#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B)
+
+#define GPIO214_GPIO PIN_CFG(214, GPIO)
+#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A)
+#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B)
+
+#define GPIO215_GPIO PIN_CFG(215, GPIO)
+#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A)
+#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B)
+#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C)
+
+#define GPIO216_GPIO PIN_CFG(216, GPIO)
+#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A)
+#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B)
+#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP)
+
+#define GPIO217_GPIO PIN_CFG(217, GPIO)
+#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A)
+#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B)
+#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C)
+
+#define GPIO218_GPIO PIN_CFG(218, GPIO)
+#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A)
+#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B)
+#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP)
+
+#define GPIO219_GPIO PIN_CFG(219, GPIO)
+#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A)
+#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B)
+
+#define GPIO220_GPIO PIN_CFG(220, GPIO)
+#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A)
+#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B)
+#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C)
+
+#define GPIO221_GPIO PIN_CFG(221, GPIO)
+#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A)
+#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B)
+
+#define GPIO222_GPIO PIN_CFG(222, GPIO)
+#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A)
+#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B)
+
+#define GPIO223_GPIO PIN_CFG(223, GPIO)
+#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A)
+#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B)
+#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C)
+
+#define GPIO224_GPIO PIN_CFG(224, GPIO)
+#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A)
+#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B)
+#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C)
+
+#define GPIO225_GPIO PIN_CFG(225, GPIO)
+#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A)
+#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B)
+#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C)
+
+#define GPIO226_GPIO PIN_CFG(226, GPIO)
+#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A)
+#define GPIO226_PWL PIN_CFG(226, ALT_B)
+#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C)
+
+#define GPIO227_GPIO PIN_CFG(227, GPIO)
+#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A)
+
+#define GPIO228_GPIO PIN_CFG(228, GPIO)
+#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A)
+
+#define GPIO229_GPIO PIN_CFG(229, GPIO)
+#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A)
+#define GPIO229_PWL PIN_CFG(229, ALT_B)
+#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP)
+
+#define GPIO230_GPIO PIN_CFG(230, GPIO)
+#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A)
+#define GPIO230_PWL PIN_CFG(230, ALT_B)
+#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP)
+
+#define GPIO256_GPIO PIN_CFG(256, GPIO)
+#define GPIO256_USB_NXT PIN_CFG(256, ALT_A)
+
+#define GPIO257_GPIO PIN_CFG(257, GPIO)
+#define GPIO257_USB_STP PIN_CFG(257, ALT_A)
+
+#define GPIO258_GPIO PIN_CFG(258, GPIO)
+#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A)
+#define GPIO258_NONE PIN_CFG(258, ALT_B)
+#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C)
+
+#define GPIO259_GPIO PIN_CFG(259, GPIO)
+#define GPIO259_USB_DIR PIN_CFG(259, ALT_A)
+
+#define GPIO260_GPIO PIN_CFG(260, GPIO)
+#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A)
+
+#define GPIO261_GPIO PIN_CFG(261, GPIO)
+#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A)
+
+#define GPIO262_GPIO PIN_CFG(262, GPIO)
+#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A)
+
+#define GPIO263_GPIO PIN_CFG(263, GPIO)
+#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A)
+
+#define GPIO264_GPIO PIN_CFG(264, GPIO)
+#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A)
+
+#define GPIO265_GPIO PIN_CFG(265, GPIO)
+#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A)
+
+#define GPIO266_GPIO PIN_CFG(266, GPIO)
+#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A)
+
+#define GPIO267_GPIO PIN_CFG(267, GPIO)
+#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A)
+
+#endif
diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c
new file mode 100644
index 0000000..c3061e2
--- /dev/null
+++ b/board/st-ericsson/snowball/snowball.c
@@ -0,0 +1,340 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/db8500_pincfg.h>
+#include <asm/arch/prcmu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_MMC
+#include "../../../drivers/mmc/arm_pl180_mmci.h"
+#endif
+#include "db8500_pins.h"
+
+/*
+ * Get a global data pointer
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Memory controller register
+ */
+#define DMC_BASE_ADDR 0x80156000
+#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184)
+
+/*
+ * GPIO pin config common for MOP500/HREF boards
+ */
+unsigned long gpio_cfg_common[] = {
+ /* I2C */
+ GPIO147_I2C0_SCL,
+ GPIO148_I2C0_SDA,
+ GPIO16_I2C1_SCL,
+ GPIO17_I2C1_SDA,
+ GPIO10_I2C2_SDA,
+ GPIO11_I2C2_SCL,
+ GPIO229_I2C3_SDA,
+ GPIO230_I2C3_SCL,
+
+ /* SSP0, to AB8500 */
+ GPIO143_SSP0_CLK,
+ GPIO144_SSP0_FRM,
+ GPIO145_SSP0_RXD | PIN_PULL_DOWN,
+ GPIO146_SSP0_TXD,
+
+ /* MMC0 (MicroSD card) */
+ GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH,
+ GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH,
+ GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH,
+ GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH,
+ GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL,
+ GPIO23_MC0_CLK | PIN_OUTPUT_LOW,
+ GPIO24_MC0_CMD | PIN_INPUT_PULLUP,
+ GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP,
+ GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP,
+ GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP,
+ GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP,
+
+ /* MMC4 (On-board eMMC) */
+ GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP,
+ GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP,
+ GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP,
+ GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP,
+ GPIO201_MC4_CMD | PIN_INPUT_PULLUP,
+ GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL,
+ GPIO203_MC4_CLK | PIN_OUTPUT_LOW,
+ GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP,
+ GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP,
+ GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP,
+ GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP,
+
+ /* UART2, console */
+ GPIO29_U2_RXD | PIN_INPUT_PULLUP,
+ GPIO30_U2_TXD | PIN_OUTPUT_HIGH,
+ GPIO31_U2_CTSn | PIN_INPUT_PULLUP,
+ GPIO32_U2_RTSn | PIN_OUTPUT_HIGH,
+
+ /*
+ * USB, pin 256-267 USB, Is probably already setup correctly from
+ * BootROM/boot stages, but we don't trust that and set it up anyway
+ */
+ GPIO256_USB_NXT,
+ GPIO257_USB_STP,
+ GPIO258_USB_XCLK,
+ GPIO259_USB_DIR,
+ GPIO260_USB_DAT7,
+ GPIO261_USB_DAT6,
+ GPIO262_USB_DAT5,
+ GPIO263_USB_DAT4,
+ GPIO264_USB_DAT3,
+ GPIO265_USB_DAT2,
+ GPIO266_USB_DAT1,
+ GPIO267_USB_DAT0,
+};
+
+unsigned long gpio_cfg_snowball[] = {
+ /* MMC0 (MicroSD card) */
+ GPIO217_GPIO | PIN_OUTPUT_HIGH, /* MMC_EN */
+ GPIO218_GPIO | PIN_INPUT_NOPULL, /* MMC_CD */
+ GPIO228_GPIO | PIN_OUTPUT_HIGH, /* SD_SEL */
+
+ /* eMMC */
+ GPIO167_GPIO | PIN_OUTPUT_HIGH, /* RSTn_MLC */
+
+ /* LAN */
+ GPIO131_SM_ADQ8,
+ GPIO132_SM_ADQ9,
+ GPIO133_SM_ADQ10,
+ GPIO134_SM_ADQ11,
+ GPIO135_SM_ADQ12,
+ GPIO136_SM_ADQ13,
+ GPIO137_SM_ADQ14,
+ GPIO138_SM_ADQ15,
+
+ /* RSTn_LAN */
+ GPIO141_GPIO | PIN_OUTPUT_HIGH,
+};
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /*
+ * Setup board (bd) and board-info (bi).
+ * bi_arch_number: Unique id for this board. It will passed in r1 to
+ * Linux startup code and is the machine_id.
+ * bi_boot_params: Where this board expects params.
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL;
+ gd->bd->bi_boot_params = 0x00000100;
+
+ /* Configure GPIO pins needed by U-boot */
+ db8500_gpio_config_pins(gpio_cfg_common, ARRAY_SIZE(gpio_cfg_common));
+
+ db8500_gpio_config_pins(gpio_cfg_snowball,
+ ARRAY_SIZE(gpio_cfg_snowball));
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->ram_size = gd->bd->bi_dram[0].size =
+ get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+
+ return 0;
+}
+
+static int raise_ab8500_gpio16(void)
+{
+ int ret;
+
+ /* selection */
+ ret = ab8500_read(AB8500_MISC, AB8500_GPIO_SEL2_REG);
+ if (ret < 0)
+ goto out;
+
+ ret |= 0x80;
+ ret = ab8500_write(AB8500_MISC, AB8500_GPIO_SEL2_REG, ret);
+ if (ret < 0)
+ goto out;
+
+ /* direction */
+ ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR2_REG);
+ if (ret < 0)
+ goto out;
+
+ ret |= 0x80;
+ ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR2_REG, ret);
+ if (ret < 0)
+ goto out;
+
+ /* out */
+ ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT2_REG);
+ if (ret < 0)
+ goto out;
+
+ ret |= 0x80;
+ ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT2_REG, ret);
+
+out:
+ return ret;
+}
+
+static int raise_ab8500_gpio26(void)
+{
+ int ret;
+
+ /* selection */
+ ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR4_REG);
+ if (ret < 0)
+ goto out;
+
+ ret |= 0x2;
+ ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR4_REG, ret);
+ if (ret < 0)
+ goto out;
+
+ /* out */
+ ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT4_REG);
+ if (ret < 0)
+ goto out;
+
+ ret |= 0x2;
+ ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT4_REG, ret);
+
+out:
+ return ret;
+}
+
+int board_late_init(void)
+{
+ /* enable 3V3 for LAN controller */
+ if (raise_ab8500_gpio26() >= 0) {
+ /* Turn on FSMC device */
+ writel(0x1, 0x8000f000);
+ writel(0x1, 0x8000f008);
+
+ /* setup FSMC for LAN controler */
+ writel(0x305b, 0x80000000);
+
+ /* run at the highest possible speed */
+ writel(0x01010210, 0x80000004);
+ } else
+ printf("error: can't raise GPIO26\n");
+
+ /* enable 3v6 for GBF chip */
+ if ((raise_ab8500_gpio16() < 0))
+ printf("error: cant' raise GPIO16\n");
+
+ /* empty UART RX FIFO */
+ while (tstc())
+ (void) getc();
+
+ return 0;
+}
+
+#ifdef CONFIG_MMC
+/*
+ * emmc_host_init - initialize the emmc controller.
+ * Configure GPIO settings, set initial clock and power for emmc slot.
+ * Initialize mmc struct and register with mmc framework.
+ */
+static int emmc_host_init(void)
+{
+ struct pl180_mmc_host *host;
+
+ host = malloc(sizeof(struct pl180_mmc_host));
+ if (!host)
+ return -ENOMEM;
+ memset(host, 0, sizeof(*host));
+
+ host->base = (struct sdi_registers *)CFG_EMMC_BASE;
+ host->pwr_init = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON;
+ host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 |
+ SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN;
+ strcpy(host->name, "EMMC");
+ host->caps = MMC_MODE_8BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
+ host->voltages = VOLTAGE_WINDOW_MMC;
+ host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
+ host->clock_max = ARM_MCLK / 2;
+ host->clock_in = ARM_MCLK;
+ host->version2 = 1;
+
+ return arm_pl180_mmci_init(host);
+}
+
+/*
+ * mmc_host_init - initialize the external mmc controller.
+ * Configure GPIO settings, set initial clock and power for mmc slot.
+ * Initialize mmc struct and register with mmc framework.
+ */
+static int mmc_host_init(void)
+{
+ struct pl180_mmc_host *host;
+ u32 sdi_u32;
+
+ host = malloc(sizeof(struct pl180_mmc_host));
+ if (!host)
+ return -ENOMEM;
+ memset(host, 0, sizeof(*host));
+
+ host->base = (struct sdi_registers *)CFG_MMC_BASE;
+ sdi_u32 = 0xBF;
+ writel(sdi_u32, &host->base->power);
+ host->pwr_init = 0xBF;
+ host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 |
+ SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN;
+ strcpy(host->name, "MMC");
+ host->caps = MMC_MODE_8BIT;
+ host->b_max = 0;
+ host->voltages = VOLTAGE_WINDOW_SD;
+ host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2);
+ host->clock_max = ARM_MCLK / 2;
+ host->clock_in = ARM_MCLK;
+ host->version2 = 1;
+
+ return arm_pl180_mmci_init(host);
+}
+
+/*
+ * board_mmc_init - initialize all the mmc/sd host controllers.
+ * Called by generic mmc framework.
+ */
+int board_mmc_init(bd_t *bis)
+{
+ int error;
+
+ (void) bis;
+
+ error = emmc_host_init();
+ if (error) {
+ printf("emmc_host_init() %d\n", error);
+ return -1;
+ }
+
+ u8500_mmc_power_init();
+
+ error = mmc_host_init();
+ if (error) {
+ printf("mmc_host_init() %d\n", error);
+ return -1;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_MMC */
diff --git a/board/st-ericsson/u8500/Kconfig b/board/st-ericsson/u8500/Kconfig
new file mode 100644
index 0000000..909f30d
--- /dev/null
+++ b/board/st-ericsson/u8500/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_U8500_HREF
+
+config SYS_BOARD
+ default "u8500"
+
+config SYS_VENDOR
+ default "st-ericsson"
+
+config SYS_SOC
+ default "u8500"
+
+config SYS_CONFIG_NAME
+ default "u8500_href"
+
+endif
diff --git a/board/st-ericsson/u8500/MAINTAINERS b/board/st-ericsson/u8500/MAINTAINERS
new file mode 100644
index 0000000..e2581eb
--- /dev/null
+++ b/board/st-ericsson/u8500/MAINTAINERS
@@ -0,0 +1,6 @@
+U8500 BOARD
+#M: -
+S: Maintained
+F: board/st-ericsson/u8500/
+F: include/configs/u8500_href.h
+F: configs/u8500_href_defconfig
diff --git a/board/st-ericsson/u8500/Makefile b/board/st-ericsson/u8500/Makefile
new file mode 100644
index 0000000..d6c4280
--- /dev/null
+++ b/board/st-ericsson/u8500/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) ST-Ericsson SA 2009
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ccflags-y += -D__RELEASE -D__STN_8500
+
+obj-y := u8500_href.o gpio.o
diff --git a/board/st-ericsson/u8500/gpio.c b/board/st-ericsson/u8500/gpio.c
new file mode 100644
index 0000000..2ddc7af
--- /dev/null
+++ b/board/st-ericsson/u8500/gpio.c
@@ -0,0 +1,331 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+
+static struct gpio_register *addr_gpio_register[] = {
+ (void *)U8500_GPIO_0_BASE,
+ (void *)U8500_GPIO_1_BASE,
+ (void *)U8500_GPIO_2_BASE,
+ (void *)U8500_GPIO_3_BASE,
+ (void *)U8500_GPIO_4_BASE,
+ (void *)U8500_GPIO_5_BASE,
+ (void *)U8500_GPIO_6_BASE,
+ (void *)U8500_GPIO_7_BASE,
+ (void *)U8500_GPIO_8_BASE,
+};
+
+struct gpio_altfun_data altfun_table[] = {
+ {
+ .altfun = GPIO_ALT_I2C_0,
+ .start = 147,
+ .end = 148,
+ .cont = 0,
+ .type = GPIO_ALTF_A,
+ },
+ {
+ .altfun = GPIO_ALT_I2C_1,
+ .start = 16,
+ .end = 17,
+ .cont = 0,
+ .type = GPIO_ALTF_B,
+ },
+ {
+ .altfun = GPIO_ALT_I2C_2,
+ .start = 10,
+ .end = 11,
+ .cont = 0,
+ .type = GPIO_ALTF_B,
+ },
+ {
+ .altfun = GPIO_ALT_I2C_3,
+ .start = 229,
+ .end = 230,
+ .cont = 0,
+ .type = GPIO_ALTF_C,
+ },
+ {
+ .altfun = GPIO_ALT_UART_0_MODEM,
+ .start = 0,
+ .end = 3,
+ .cont = 1,
+ .type = GPIO_ALTF_A,
+ },
+ {
+ .altfun = GPIO_ALT_UART_0_MODEM,
+ .start = 33,
+ .end = 36,
+ .cont = 0,
+ .type = GPIO_ALTF_C,
+ },
+ {
+ .altfun = GPIO_ALT_UART_1,
+ .start = 4,
+ .end = 7,
+ .cont = 0,
+ .type =
+ GPIO_ALTF_A,
+ },
+ {
+ .altfun = GPIO_ALT_UART_2,
+ .start = 18,
+ .end = 19,
+ .cont = 1,
+ .type = GPIO_ALTF_B,
+ },
+ {
+ .altfun = GPIO_ALT_UART_2,
+ .start = 29,
+ .end = 32,
+ .cont = 0,
+ .type = GPIO_ALTF_C,
+ },
+ {
+ .altfun = GPIO_ALT_MSP_0,
+ .start = 12,
+ .end = 17,
+ .cont = 1,
+ .type = GPIO_ALTF_A,
+ },
+ {
+ .altfun = GPIO_ALT_MSP_0,
+ .start = 21,
+ .end = 21,
+ .cont = 0,
+ .type = GPIO_ALTF_B,
+ },
+ {
+ .altfun = GPIO_ALT_MSP_1,
+ .start = 33,
+ .end = 36,
+ .cont = 0,
+ .type = GPIO_ALTF_A,
+ },
+ {
+ .altfun = GPIO_ALT_MSP_2,
+ .start = 192,
+ .end = 196,
+ .cont = 0,
+ .type = GPIO_ALTF_A,
+ },
+ {
+ .altfun = GPIO_ALT_LCD_PANEL,
+ .start = 64,
+ .end = 93,
+ .cont = 1,
+ .type = GPIO_ALTF_A,
+ },
+ {
+ .altfun = GPIO_ALT_LCD_PANEL,
+ .start = 150,
+ .end = 171,
+ .cont = 0,
+ .type = GPIO_ALTF_B,
+ },
+ {
+ .altfun = GPIO_ALT_SD_CARD0,
+ .start = 18,
+ .end = 28,
+ .cont = 0,
+ .type = GPIO_ALTF_A,
+ },
+ {
+ .altfun = GPIO_ALT_MM_CARD0,
+ .start = 18,
+ .end = 32,
+ .cont = 0,
+ .type = GPIO_ALTF_A,
+ },
+ {
+ .altfun = GPIO_ALT_USB_OTG,
+ .start = 256,
+ .end = 267,
+ .cont = 0,
+ .type = GPIO_ALTF_A,
+ },
+ {
+ .altfun = GPIO_ALT_EMMC,
+ .start = 197,
+ .end = 207,
+ .cont = 0,
+ .type = GPIO_ALTF_A,
+ },
+ {
+ .altfun = GPIO_ALT_POP_EMMC,
+ .start = 128,
+ .end = 138,
+ .cont = 0,
+ .type = GPIO_ALTF_A,
+ },
+};
+
+/*
+ * Static Function declarations
+ */
+enum gpio_error gpio_setpinconfig(int pin_id, struct gpio_config *config)
+{
+ struct gpio_register *p_gpio_register =
+ addr_gpio_register[GPIO_BLOCK(pin_id)];
+ u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
+ enum gpio_error error = GPIO_OK;
+ u32 temp_reg;
+
+ switch (config->mode) {
+ case GPIO_ALTF_A:
+ temp_reg = readl(&p_gpio_register->gpio_afsa);
+ temp_reg |= mask;
+ writel(temp_reg, &p_gpio_register->gpio_afsa);
+ temp_reg = readl(&p_gpio_register->gpio_afsb);
+ temp_reg &= ~mask;
+ writel(temp_reg, &p_gpio_register->gpio_afsb);
+ break;
+ case GPIO_ALTF_B:
+ temp_reg = readl(&p_gpio_register->gpio_afsa);
+ temp_reg &= ~mask;
+ writel(temp_reg, &p_gpio_register->gpio_afsa);
+ temp_reg = readl(&p_gpio_register->gpio_afsb);
+ temp_reg |= mask;
+ writel(temp_reg, &p_gpio_register->gpio_afsb);
+ break;
+ case GPIO_ALTF_C:
+ temp_reg = readl(&p_gpio_register->gpio_afsa);
+ temp_reg |= mask;
+ writel(temp_reg, &p_gpio_register->gpio_afsa);
+ temp_reg = readl(&p_gpio_register->gpio_afsb);
+ temp_reg |= mask;
+ writel(temp_reg, &p_gpio_register->gpio_afsb);
+ break;
+ case GPIO_MODE_SOFTWARE:
+ temp_reg = readl(&p_gpio_register->gpio_afsa);
+ temp_reg &= ~mask;
+ writel(temp_reg, &p_gpio_register->gpio_afsa);
+ temp_reg = readl(&p_gpio_register->gpio_afsb);
+ temp_reg &= ~mask;
+ writel(temp_reg, &p_gpio_register->gpio_afsb);
+
+ switch (config->direction) {
+ case GPIO_DIR_INPUT:
+ writel(mask, &p_gpio_register->gpio_dirc);
+ break;
+ case GPIO_DIR_OUTPUT:
+ writel(mask, &p_gpio_register->gpio_dirs);
+ break;
+ case GPIO_DIR_LEAVE_UNCHANGED:
+ break;
+ default:
+ return GPIO_INVALID_PARAMETER;
+ }
+
+ break;
+ case GPIO_MODE_LEAVE_UNCHANGED:
+ break;
+ default:
+ return GPIO_INVALID_PARAMETER;
+ }
+ return error;
+}
+
+enum gpio_error gpio_resetgpiopin(int pin_id, char *dev_name)
+{
+ struct gpio_register *p_gpio_register =
+ addr_gpio_register[GPIO_BLOCK(pin_id)];
+ u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
+ enum gpio_error error = GPIO_OK;
+ u32 temp_reg;
+
+ temp_reg = readl(&p_gpio_register->gpio_afsa);
+ temp_reg &= ~mask;
+ writel(temp_reg, &p_gpio_register->gpio_afsa);
+ temp_reg = readl(&p_gpio_register->gpio_afsb);
+ temp_reg &= ~mask;
+ writel(temp_reg, &p_gpio_register->gpio_afsb);
+ writel(mask, &p_gpio_register->gpio_dirc);
+
+ return error;
+}
+
+struct gpio_config altfun_pinconfig;
+enum gpio_error gpio_altfunction(enum gpio_alt_function alt_func,
+ int which_altfunc, char *dev_name)
+{
+ int i, j, start, end;
+ enum gpio_error error = -1;
+
+ for (i = 0; i < ARRAY_SIZE(altfun_table); i++) {
+ if (altfun_table[i].altfun != alt_func)
+ continue;
+
+ start = altfun_table[i].start;
+ end = altfun_table[i].end;
+ for (j = start; j <= end; j++) {
+ if (which_altfunc == GPIO_ALTF_FIND)
+ altfun_pinconfig.mode = altfun_table[i].type;
+ else
+ altfun_pinconfig.mode = which_altfunc;
+ altfun_pinconfig.direction = GPIO_DIR_OUTPUT;
+ altfun_pinconfig.dev_name = dev_name;
+
+ if (which_altfunc != GPIO_ALTF_DISABLE)
+ error = gpio_setpinconfig(j, &altfun_pinconfig);
+ else
+ error = gpio_resetgpiopin(j, dev_name);
+ if (!error)
+ continue;
+ printf("GPIO %d configuration failure (nmdk_error:%d)",
+ j, error);
+ error = GPIO_INVALID_PARAMETER;
+ return error;
+ }
+
+ if (!altfun_table[i].cont)
+ break;
+ }
+ return error;
+}
+
+int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name)
+{
+ struct gpio_register *p_gpio_register =
+ addr_gpio_register[GPIO_BLOCK(pin_id)];
+ u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
+
+ switch (value) {
+ case GPIO_DATA_HIGH:
+ writel(mask, &p_gpio_register->gpio_dats);
+ break;
+ case GPIO_DATA_LOW:
+ writel(mask, &p_gpio_register->gpio_datc);
+ break;
+ default:
+ printf("Invalid value passed in %s", __FUNCTION__);
+ return GPIO_INVALID_PARAMETER;
+ }
+ return GPIO_OK;
+}
+
+int gpio_readpin(int pin_id, enum gpio_data *rv)
+{
+ struct gpio_register *p_gpio_register =
+ addr_gpio_register[GPIO_BLOCK(pin_id)];
+ u32 mask = 1UL << (pin_id % GPIO_PINS_PER_BLOCK);
+
+ if ((readl(&p_gpio_register->gpio_dat) & mask) != 0)
+ *rv = GPIO_DATA_HIGH;
+ else
+ *rv = GPIO_DATA_LOW;
+ return GPIO_OK;
+}
+
+int gpio_altfuncenable(enum gpio_alt_function altfunc, char *dev_name)
+{
+ return (int)gpio_altfunction(altfunc, GPIO_ALTF_FIND, dev_name);
+}
+
+int gpio_altfuncdisable(enum gpio_alt_function altfunc, char *dev_name)
+{
+ return (int)gpio_altfunction(altfunc, GPIO_ALTF_DISABLE, dev_name);
+}
diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c
new file mode 100644
index 0000000..9df499b
--- /dev/null
+++ b/board/st-ericsson/u8500/u8500_href.c
@@ -0,0 +1,477 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <i2c.h>
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/prcmu.h>
+#ifdef CONFIG_MMC
+#include "../../../drivers/mmc/arm_pl180_mmci.h"
+#endif
+
+#define NOMADIK_PER4_BASE (0x80150000)
+#define NOMADIK_BACKUPRAM0_BASE (NOMADIK_PER4_BASE + 0x00000)
+#define NOMADIK_BACKUPRAM1_BASE (NOMADIK_PER4_BASE + 0x01000)
+
+/* Power, Reset, Clock Management Unit */
+/*
+ * SVA: Smart Video Accelerator
+ * SIA: Smart Imaging Accelerator
+ * SGA: Smart Graphic accelerator
+ * B2R2: Graphic blitter
+ */
+#define PRCM_ARMCLKFIX_MGT_REG (PRCMU_BASE + 0x000)
+#define PRCM_ACLK_MGT_REG (PRCMU_BASE + 0x004)
+#define PRCM_SVAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x008)
+#define PRCM_SIAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x00C)
+#define PRCM_SAAMMDSPCLK_MGT_REG (PRCMU_BASE + 0x010)
+#define PRCM_SGACLK_MGT_REG (PRCMU_BASE + 0x014)
+#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
+#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
+#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
+#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024)
+#define PRCM_SLIMCLK_MGT_REG (PRCMU_BASE + 0x028)
+#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C)
+#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030)
+#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034)
+#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
+#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
+#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
+#define PRCM_DMACLK_MGT_REG (PRCMU_BASE + 0x074)
+#define PRCM_B2R2CLK_MGT_REG (PRCMU_BASE + 0x078)
+
+#define PRCM_PLLSOC0_FREQ_REG (PRCMU_BASE + 0x080)
+#define PRCM_PLLSOC1_FREQ_REG (PRCMU_BASE + 0x084)
+#define PRCM_PLLARM_FREQ_REG (PRCMU_BASE + 0x088)
+#define PRCM_PLLDDR_FREQ_REG (PRCMU_BASE + 0x08C)
+#define PRCM_ARM_CHGCLKREQ_REG (PRCMU_BASE + 0x114)
+
+#define PRCM_TCR (PRCMU_BASE + 0x1C8)
+
+/*
+ * Memory controller register
+ */
+#define DMC_BASE_ADDR 0x80156000
+#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184)
+
+int board_id; /* set in board_late_init() */
+
+/* PLLs for clock management registers */
+enum {
+ GATED = 0,
+ PLLSOC0, /* pllsw = 001, ffs() = 1 */
+ PLLSOC1, /* pllsw = 010, ffs() = 2 */
+ PLLDDR, /* pllsw = 100, ffs() = 3 */
+ PLLARM,
+};
+
+static struct pll_freq_regs {
+ int idx; /* index fror pll_name and pll_khz arrays */
+ uint32_t addr;
+} pll_freq_regs[] = {
+ {PLLSOC0, PRCM_PLLSOC0_FREQ_REG},
+ {PLLSOC1, PRCM_PLLSOC1_FREQ_REG},
+ {PLLDDR, PRCM_PLLDDR_FREQ_REG},
+ {PLLARM, PRCM_PLLARM_FREQ_REG},
+ {0, 0},
+};
+
+static const char *pll_name[5] = {"GATED", "SOC0", "SOC1", "DDR", "ARM"};
+static uint32_t pll_khz[5]; /* use ffs(pllsw(reg)) as index for 0..3 */
+
+static struct clk_mgt_regs {
+ uint32_t addr;
+ uint32_t val;
+ const char *descr;
+} clk_mgt_regs[] = {
+ /* register content taken from bootrom settings */
+ {PRCM_ARMCLKFIX_MGT_REG, 0x0120, "ARMCLKFIX"}, /* ena, SOC0/0, ??? */
+ {PRCM_ACLK_MGT_REG, 0x0125, "ACLK"}, /* ena, SOC0/5, 160 MHz */
+ {PRCM_SVAMMDSPCLK_MGT_REG, 0x1122, "SVA"}, /* ena, SOC0/2, 400 MHz */
+ {PRCM_SIAMMDSPCLK_MGT_REG, 0x0022, "SIA"}, /* dis, SOC0/2, 400 MHz */
+ {PRCM_SAAMMDSPCLK_MGT_REG, 0x0822, "SAA"}, /* dis, SOC0/4, 200 MHz */
+ {PRCM_SGACLK_MGT_REG, 0x0024, "SGA"}, /* dis, SOC0/4, 200 MHz */
+ {PRCM_UARTCLK_MGT_REG, 0x0300, "UART"}, /* ena, GATED, CLK38 */
+ {PRCM_MSPCLK_MGT_REG, 0x0200, "MSP"}, /* dis, GATED, CLK38 */
+ {PRCM_I2CCLK_MGT_REG, 0x0130, "I2C"}, /* ena, SOC0/16, 50 MHz */
+ {PRCM_SDMMCCLK_MGT_REG, 0x0130, "SDMMC"}, /* ena, SOC0/16, 50 MHz */
+ {PRCM_PER1CLK_MGT_REG, 0x126, "PER1"}, /* ena, SOC0/6, 133 MHz */
+ {PRCM_PER2CLK_MGT_REG, 0x126, "PER2"}, /* ena, SOC0/6, 133 MHz */
+ {PRCM_PER3CLK_MGT_REG, 0x126, "PER3"}, /* ena, SOC0/6, 133 MHz */
+ {PRCM_PER5CLK_MGT_REG, 0x126, "PER5"}, /* ena, SOC0/6, 133 MHz */
+ {PRCM_PER6CLK_MGT_REG, 0x126, "PER6"}, /* ena, SOC0/6, 133 MHz */
+ {PRCM_PER7CLK_MGT_REG, 0x128, "PER7"}, /* ena, SOC0/8, 100 MHz */
+ {PRCM_DMACLK_MGT_REG, 0x125, "DMA"}, /* ena, SOC0/5, 160 MHz */
+ {PRCM_B2R2CLK_MGT_REG, 0x025, "B2R2"}, /* dis, SOC0/5, 160 MHz */
+ {0, 0, NULL},
+};
+
+static void init_regs(void);
+
+DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+ printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_early_init_f(void)
+{
+ init_regs();
+ return 0;
+}
+
+int board_init(void)
+{
+ uint32_t unused_cols_rows;
+ unsigned int nrows;
+ unsigned int ncols;
+
+ gd->bd->bi_arch_number = 0x1A4;
+ gd->bd->bi_boot_params = 0x00000100;
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+
+ /*
+ * Assumption: 2 CS active, both CS have same layout.
+ * 15 rows max, 11 cols max (controller spec).
+ * memory chip has 8 banks, I/O width 32 bit.
+ * The correct way would be to read MR#8: I/O width and density,
+ * but this requires locking against the PRCMU firmware.
+ * Simplified approach:
+ * Read number of unused rows and columns from mem controller.
+ * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes
+ */
+ unused_cols_rows = readl(DMC_CTL_97);
+ nrows = 15 - (unused_cols_rows & 0x07);
+ ncols = 11 - ((unused_cols_rows & 0x0700) >> 8);
+ gd->bd->bi_dram[0].size = 2 * (1 << (nrows + ncols)) * 8 * 4;
+
+ icache_enable();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE_1;
+
+ return 0;
+}
+
+unsigned int addr_vall_arr[] = {
+ 0x8011F000, 0x0000FFFF, /* Clocks for HSI TODO: Enable reqd only */
+ 0x8011F008, 0x00001CFF, /* Clocks for HSI TODO: Enable reqd only */
+ 0x8000F000, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
+ 0x8000F008, 0x00007FFF, /* Clocks for I2C TODO: Enable reqd only */
+ 0x80157020, 0x00000150, /* I2C 48MHz clock */
+ 0x8012F000, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
+ 0x8012F008, 0x00007FFF, /* Clocks for SD TODO: Enable reqd only */
+ 0xA03DF000, 0x0000000D, /* Clock for MTU Timers */
+ 0x8011E00C, 0x00000000, /* GPIO ALT FUNC for EMMC */
+ 0x8011E004, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
+ 0x8011E020, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */
+ 0x8011E024, 0x00000000, /* GPIO ALT FUNC for EMMC */
+ 0x8012E000, 0x20000000, /* GPIO ALT FUNC for UART */
+ 0x8012E00C, 0x00000000, /* GPIO ALT FUNC for SD */
+ 0x8012E004, 0x0FFC0000, /* GPIO ALT FUNC for SD */
+ 0x8012E020, 0x60000000, /* GPIO ALT FUNC for SD */
+ 0x8012E024, 0x60000000, /* GPIO ALT FUNC for SD */
+ 0x801571E4, 0x0000000C, /* PRCMU settings for B2R2,
+ PRCM_APE_RESETN_SET_REG */
+ 0x80157024, 0x00000130, /* PRCMU settings for EMMC/SD */
+ 0xA03FF000, 0x00000003, /* USB */
+ 0xA03FF008, 0x00000001, /* USB */
+ 0xA03FE00C, 0x00000000, /* USB */
+ 0xA03FE020, 0x00000FFF, /* USB */
+ 0xA03FE024, 0x00000000 /* USB */
+};
+
+#ifdef CONFIG_BOARD_LATE_INIT
+/*
+ * called after all initialisation were done, but before the generic
+ * mmc_initialize().
+ */
+int board_late_init(void)
+{
+ uchar byte;
+
+ /*
+ * Determine and set board_id environment variable
+ * 0: mop500, 1: href500
+ * Above boards have different GPIO expander chips which we can
+ * distinguish by the chip id.
+ *
+ * The board_id environment variable is needed for the Linux bootargs.
+ */
+ (void) i2c_set_bus_num(0);
+ (void) i2c_read(CONFIG_SYS_I2C_GPIOE_ADDR, 0x80, 1, &byte, 1);
+ if (byte == 0x01) {
+ board_id = 0;
+ setenv("board_id", "0");
+ } else {
+ board_id = 1;
+ setenv("board_id", "1");
+ }
+#ifdef CONFIG_MMC
+ u8500_mmc_power_init();
+
+ /*
+ * config extended GPIO pins for level shifter and
+ * SDMMC_ENABLE
+ */
+ if (board_id == 0) {
+ /* MOP500 */
+ byte = 0x0c;
+ (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x89, 1, &byte, 1);
+ (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0x83, 1, &byte, 1);
+ } else {
+ /* HREF */
+ /* set the direction of GPIO KPY9 and KPY10 */
+ byte = 0x06;
+ (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC8, 1, &byte, 1);
+ /* must be a multibyte access */
+ (void) i2c_write(CONFIG_SYS_I2C_GPIOE_ADDR, 0xC4, 1,
+ (uchar []) {0x06, 0x06}, 2);
+ }
+#endif /* CONFIG_MMC */
+ /*
+ * Create a memargs variable which points uses either the memargs256 or
+ * memargs512 environment variable, depending on the memory size.
+ * memargs is used to build the bootargs, memargs256 and memargs512 are
+ * stored in the environment.
+ */
+ if (gd->bd->bi_dram[0].size == 0x10000000) {
+ setenv("memargs", "setenv bootargs ${bootargs} ${memargs256}");
+ setenv("mem", "256M");
+ } else {
+ setenv("memargs", "setenv bootargs ${bootargs} ${memargs512}");
+ setenv("mem", "512M");
+ }
+
+ return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
+
+static void early_gpio_setup(struct gpio_register *gpio_reg, u32 bits)
+{
+ writel(readl(&gpio_reg->gpio_dats) | bits, &gpio_reg->gpio_dats);
+ writel(readl(&gpio_reg->gpio_pdis) & ~bits, &gpio_reg->gpio_pdis);
+}
+
+static void init_regs(void)
+{
+ /* FIXME Remove magic register array settings for ED also */
+ struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE;
+
+ /* Enable timers */
+ writel(1 << 17, &prcmu->tcr);
+
+ u8500_prcmu_enable(&prcmu->per1clk_mgt);
+ u8500_prcmu_enable(&prcmu->per2clk_mgt);
+ u8500_prcmu_enable(&prcmu->per3clk_mgt);
+ u8500_prcmu_enable(&prcmu->per5clk_mgt);
+ u8500_prcmu_enable(&prcmu->per6clk_mgt);
+ u8500_prcmu_enable(&prcmu->per7clk_mgt);
+
+ u8500_prcmu_enable(&prcmu->uartclk_mgt);
+ u8500_prcmu_enable(&prcmu->i2cclk_mgt);
+
+ u8500_prcmu_enable(&prcmu->sdmmcclk_mgt);
+
+ u8500_clock_enable(1, 9, -1); /* GPIO0 */
+
+ u8500_clock_enable(2, 11, -1); /* GPIO1 */
+
+ u8500_clock_enable(3, 8, -1); /* GPIO2 */
+ u8500_clock_enable(5, 1, -1); /* GPIO3 */
+
+ u8500_clock_enable(3, 6, 6); /* UART2 */
+
+ gpio_altfuncenable(GPIO_ALT_I2C_0, "I2C0");
+ u8500_clock_enable(3, 3, 3); /* I2C0 */
+
+ early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x60000000);
+ gpio_altfuncenable(GPIO_ALT_UART_2, "UART2");
+
+ early_gpio_setup((struct gpio_register *)U8500_GPIO_6_BASE, 0x0000ffe0);
+ gpio_altfuncenable(GPIO_ALT_EMMC, "EMMC");
+
+ early_gpio_setup((struct gpio_register *)U8500_GPIO_0_BASE, 0x0000ffe0);
+ gpio_altfuncenable(GPIO_ALT_SD_CARD0, "SDCARD");
+
+ u8500_clock_enable(1, 5, 5); /* SDI0 */
+ u8500_clock_enable(2, 4, 2); /* SDI4 */
+
+ u8500_clock_enable(6, 7, -1); /* MTU0 */
+ u8500_clock_enable(3, 4, 4); /* SDI2 */
+
+ early_gpio_setup((struct gpio_register *)U8500_GPIO_4_BASE, 0x000007ff);
+ gpio_altfuncenable(GPIO_ALT_POP_EMMC, "EMMC");
+
+ /*
+ * Enabling clocks for all devices which are AMBA devices in the
+ * kernel. Otherwise they will not get probe()'d because the
+ * peripheral ID register will not be powered.
+ */
+
+ /* XXX: some of these differ between ED/V1 */
+
+ u8500_clock_enable(1, 1, 1); /* UART1 */
+ u8500_clock_enable(1, 0, 0); /* UART0 */
+
+ u8500_clock_enable(3, 2, 2); /* SSP1 */
+ u8500_clock_enable(3, 1, 1); /* SSP0 */
+
+ u8500_clock_enable(2, 8, -1); /* SPI0 */
+ u8500_clock_enable(2, 5, 3); /* MSP2 */
+}
+
+#ifdef CONFIG_MMC
+static int u8500_mmci_board_init(void)
+{
+ enum gpio_error error;
+ struct gpio_register *gpio_base_address;
+
+ gpio_base_address = (void *)(U8500_GPIO_0_BASE);
+ gpio_base_address->gpio_dats |= 0xFFC0000;
+ gpio_base_address->gpio_pdis &= ~0xFFC0000;
+
+ /* save the GPIO0 AFSELA register */
+ error = gpio_altfuncenable(GPIO_ALT_SD_CARD0, "MMC");
+ if (error != GPIO_OK) {
+ printf("u8500_mmci_board_init() gpio_altfuncenable failed\n");
+ return -ENODEV;
+ }
+ return 0;
+}
+
+int board_mmc_init(bd_t *bd)
+{
+ struct pl180_mmc_host *host;
+
+ if (u8500_mmci_board_init())
+ return -ENODEV;
+
+ host = malloc(sizeof(struct pl180_mmc_host));
+ if (!host)
+ return -ENOMEM;
+ memset(host, 0, sizeof(*host));
+
+ strcpy(host->name, "MMC");
+ host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
+ host->pwr_init = INIT_PWR;
+ host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
+ host->voltages = VOLTAGE_WINDOW_MMC;
+ host->caps = 0;
+ host->clock_in = ARM_MCLK;
+ host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
+ host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
+
+ return arm_pl180_mmci_init(host);
+}
+#endif
+
+
+/*
+ * get_pll_freq_khz - return PLL frequency in kHz
+ */
+static uint32_t get_pll_freq_khz(uint32_t inclk_khz, uint32_t freq_reg)
+{
+ uint32_t idf, ldf, odf, seldiv, phi;
+
+ /*
+ * PLLOUTCLK = PHI = (INCLK*LDF)/(2*ODF*IDF) if SELDIV2=0
+ * PLLOUTCLK = PHI = (INCLK*LDF)/(4*ODF*IDF) if SELDIV2=1
+ * where:
+ * IDF=R(2:0) (when R=000, IDF=1d)
+ * LDF = 2*D(7:0) (D must be greater than or equal to 6)
+ * ODF = N(5:0) (when N=000000, 0DF=1d)
+ */
+
+ idf = (freq_reg & 0x70000) >> 16;
+ ldf = (freq_reg & 0xff) * 2;
+ odf = (freq_reg & 0x3f00) >> 8;
+ seldiv = (freq_reg & 0x01000000) >> 24;
+ phi = (inclk_khz * ldf) / (2 * odf * idf);
+ if (seldiv)
+ phi = phi/2;
+
+ return phi;
+}
+
+int do_clkinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ uint32_t inclk_khz;
+ uint32_t reg, phi;
+ uint32_t clk_khz;
+ unsigned int clk_sel;
+ struct clk_mgt_regs *clks = clk_mgt_regs;
+ struct pll_freq_regs *plls = pll_freq_regs;
+
+ /*
+ * Go through list of PLLs.
+ * Initialise pll out frequency array (pll_khz) and print frequency.
+ */
+ inclk_khz = 38400; /* 38.4 MHz */
+ while (plls->addr) {
+ reg = readl(plls->addr);
+ phi = get_pll_freq_khz(inclk_khz, reg);
+ pll_khz[plls->idx] = phi;
+ printf("%s PLL out frequency: %d.%d Mhz\n",
+ pll_name[plls->idx], phi/1000, phi % 1000);
+ plls++;
+ }
+
+ /* check ARM clock source */
+ reg = readl(PRCM_ARM_CHGCLKREQ_REG);
+ printf("A9 running on %s\n",
+ (reg & 1) ? "external clock" : "ARM PLL");
+
+ /* go through list of clk_mgt_reg */
+ printf("\n%19s %9s %7s %9s enabled\n",
+ "name(addr)", "value", "PLL", "CLK[MHz]");
+ while (clks->addr) {
+ reg = readl(clks->addr);
+
+ /* convert bit position into array index */
+ clk_sel = ffs((reg >> 5) & 0x7); /* PLLSW[2:0] */
+
+ if (reg & 0x200)
+ clk_khz = 38400; /* CLK38 is set */
+ else if ((reg & 0x1f) == 0)
+ /* ARMCLKFIX_MGT is 0x120, e.g. div = 0 ! */
+ clk_khz = 0;
+ else
+ clk_khz = pll_khz[clk_sel] / (reg & 0x1f);
+
+ printf("%9s(%08x): %08x, %6s, %4d.%03d, %s\n",
+ clks->descr, clks->addr, reg, pll_name[clk_sel],
+ clk_khz / 1000, clk_khz % 1000,
+ (reg & 0x100) ? "ena" : "dis");
+ clks++;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clkinfo, 1, 1, do_clkinfo,
+ "print clock info",
+ ""
+);
diff --git a/board/st/nhk8815/Kconfig b/board/st/nhk8815/Kconfig
new file mode 100644
index 0000000..94547dc
--- /dev/null
+++ b/board/st/nhk8815/Kconfig
@@ -0,0 +1,12 @@
+if NOMADIK_NHK8815
+
+config SYS_BOARD
+ default "nhk8815"
+
+config SYS_VENDOR
+ default "st"
+
+config SYS_CONFIG_NAME
+ default "nhk8815"
+
+endif
diff --git a/board/st/nhk8815/MAINTAINERS b/board/st/nhk8815/MAINTAINERS
new file mode 100644
index 0000000..72c3a8d
--- /dev/null
+++ b/board/st/nhk8815/MAINTAINERS
@@ -0,0 +1,8 @@
+NHK8815 BOARD
+M: Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
+M: Alessandro Rubini <rubini@unipv.it>
+S: Maintained
+F: board/st/nhk8815/
+F: include/configs/nhk8815.h
+F: configs/nhk8815_defconfig
+F: configs/nhk8815_onenand_defconfig
diff --git a/board/st/nhk8815/Makefile b/board/st/nhk8815/Makefile
new file mode 100644
index 0000000..dd56944
--- /dev/null
+++ b/board/st/nhk8815/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# ARM Ltd.
+# Philippe Robin, <philippe.robin@arm.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nhk8815.o
diff --git a/board/st/nhk8815/README.nhk8815 b/board/st/nhk8815/README.nhk8815
new file mode 100644
index 0000000..9008e39
--- /dev/null
+++ b/board/st/nhk8815/README.nhk8815
@@ -0,0 +1,32 @@
+
+The Nomadik 8815 CPU has a "secure" boot mode where no external access
+(not even JTAG) is allowed. The "remap" bits in the evaluation board
+are configured in order to boot from the internal ROM memory (in
+secure mode).
+
+The boot process as defined by the manufacturer executes external code
+(loaded from NAND or OneNAND) that that disables such "security" in
+order to run u-boot and later the kernel without constraints. Such
+code is a proprietary initial boot loader, called "X-Loader" (in case
+anyone wonders, it has no relations with other loaders with the same
+name and there is no GPL code inside the ST X-Loader).
+
+SDRAM configuration, PLL setup and initial loading from NAND is
+implemented in the X-Loader, so U-Boot is already running in SDRAM
+when control is handed over to it.
+
+The Makefile offers two different configurations to be used if you
+boot from Nand or OneNand.
+
+ make nhk8815_config
+ make nhk8815_onenand_config
+
+Both support OneNand and Nand. Since U-Boot, running in RAM, can't know
+where it was loaded from, the configurations differ in where the filesystem
+is looked for by default.
+
+
+On www.st.com/nomadik and on www.stnwireless.com there are documents,
+summary data and white papers on Nomadik. The full datasheet for
+STn8815 is not currently available on line but under specific request
+to the local ST sales offices.
diff --git a/board/st/nhk8815/nhk8815.c b/board/st/nhk8815/nhk8815.c
new file mode 100644
index 0000000..94d0f76
--- /dev/null
+++ b/board/st/nhk8815/nhk8815.c
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2005
+ * STMicrolelctronics, <www.st.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int progress)
+{
+ printf("%i\n", progress);
+}
+#endif
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_NOMADIK;
+ gd->bd->bi_boot_params = 0x00000100;
+ writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20);
+ writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24);
+ writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28);
+ writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE);
+
+ /* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */
+ writel(0x0000305b, REG_FSMC_BCR1);
+ writel(0x00033f33, REG_FSMC_BTR1);
+
+ /* Set up SMCS0 for OneNand: sram-like once again */
+ writel(0x000030db, NOMADIK_FSMC_BASE + 0x00); /* FSMC_BCR0 */
+ writel(0x02100551, NOMADIK_FSMC_BASE + 0x04); /* FSMC_BTR0 */
+
+ icache_enable();
+ return 0;
+}
+
+int board_late_init(void)
+{
+ /* Set the two I2C gpio lines to be gpio high */
+ nmk_gpio_set(__SCL, 1); nmk_gpio_set(__SDA, 1);
+ nmk_gpio_dir(__SCL, 1); nmk_gpio_dir(__SDA, 1);
+ nmk_gpio_af(__SCL, GPIO_GPIO); nmk_gpio_af(__SDA, GPIO_GPIO);
+
+ /* Reset the I2C port expander, on GPIO77 */
+ nmk_gpio_af(77, GPIO_GPIO);
+ nmk_gpio_dir(77, 1);
+ nmk_gpio_set(77, 0);
+ udelay(10);
+ nmk_gpio_set(77, 1);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/st/stv0991/Kconfig b/board/st/stv0991/Kconfig
new file mode 100644
index 0000000..007712f
--- /dev/null
+++ b/board/st/stv0991/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_STV0991
+
+config SYS_BOARD
+ default "stv0991"
+
+config SYS_VENDOR
+ default "st"
+
+config SYS_SOC
+ default "stv0991"
+
+config SYS_CONFIG_NAME
+ default "stv0991"
+
+endif
diff --git a/board/st/stv0991/MAINTAINERS b/board/st/stv0991/MAINTAINERS
new file mode 100644
index 0000000..e7a2cca
--- /dev/null
+++ b/board/st/stv0991/MAINTAINERS
@@ -0,0 +1,6 @@
+STV0991 APPLICATION BOARD
+M: Vikas Manocha <vikas.manocha@st.com>
+S: Maintained
+F: board/st/stv0991/
+F: include/configs/stv0991.h
+F: configs/stv0991_defconfig
diff --git a/board/st/stv0991/Makefile b/board/st/stv0991/Makefile
new file mode 100644
index 0000000..fb5169a
--- /dev/null
+++ b/board/st/stv0991/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014
+# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := stv0991.o
diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c
new file mode 100644
index 0000000..f465699
--- /dev/null
+++ b/board/st/stv0991/stv0991.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2014
+ * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/stv0991_periph.h>
+#include <asm/arch/stv0991_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_pl01x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct gpio_regs *const gpioa_regs =
+ (struct gpio_regs *) GPIOA_BASE_ADDR;
+
+static const struct pl01x_serial_platdata serial_platdata = {
+ .base = 0x80406000,
+ .type = TYPE_PL011,
+ .clock = 2700 * 1000,
+};
+
+U_BOOT_DEVICE(stv09911_serials) = {
+ .name = "serial_pl01x",
+ .platdata = &serial_platdata,
+};
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int progress)
+{
+ printf("%i\n", progress);
+}
+#endif
+
+void enable_eth_phy(void)
+{
+ /* Set GPIOA_06 pad HIGH (Appli board)*/
+ writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
+ writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
+}
+int board_eth_enable(void)
+{
+ stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
+ clock_setup(ETH_CLOCK_CFG);
+ enable_eth_phy();
+ return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ board_eth_enable();
+ return 0;
+}
+
+int board_uart_init(void)
+{
+ stv0991_pinmux_config(UART_GPIOC_30_31);
+ clock_setup(UART_CLOCK_CFG);
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ board_uart_init();
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#if defined(CONFIG_DESIGNWARE_ETH)
+ u32 interface = PHY_INTERFACE_MODE_MII;
+ if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
+ ret++;
+#endif
+ return ret;
+}
+#endif
diff --git a/board/stx/stxgp3/Kconfig b/board/stx/stxgp3/Kconfig
new file mode 100644
index 0000000..910b31b
--- /dev/null
+++ b/board/stx/stxgp3/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_STXGP3
+
+config SYS_BOARD
+ default "stxgp3"
+
+config SYS_VENDOR
+ default "stx"
+
+config SYS_CONFIG_NAME
+ default "stxgp3"
+
+endif
diff --git a/board/stx/stxgp3/MAINTAINERS b/board/stx/stxgp3/MAINTAINERS
new file mode 100644
index 0000000..bd5743c
--- /dev/null
+++ b/board/stx/stxgp3/MAINTAINERS
@@ -0,0 +1,6 @@
+STXGP3 BOARD
+#M: Dan Malek <dan@embeddedalley.com>
+S: Orphan (since 2014-06)
+F: board/stx/stxgp3/
+F: include/configs/stxgp3.h
+F: configs/stxgp3_defconfig
diff --git a/board/stx/stxgp3/Makefile b/board/stx/stxgp3/Makefile
new file mode 100644
index 0000000..78e2d6c
--- /dev/null
+++ b/board/stx/stxgp3/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += stxgp3.o
+obj-y += law.o
+obj-y += tlb.o
+obj-y += flash.o
+obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o
diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c
new file mode 100644
index 0000000..41d4cfe
--- /dev/null
+++ b/board/stx/stxgp3/ddr.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 0;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /* 2T timing enable */
+ popts->twot_en = 1;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/stx/stxgp3/flash.c b/board/stx/stxgp3/flash.c
new file mode 100644
index 0000000..61066a4
--- /dev/null
+++ b/board/stx/stxgp3/flash.c
@@ -0,0 +1,499 @@
+/*
+ * (C) Copyright 2003, Dan Malek, Embedded Edge, LLC. <dan@embeddededge.com>
+ * Copied from ADS85xx.
+ * Updated to support the Silicon Tx GP3 8560. We should only find
+ * two Intel 28F640 parts in 16-bit mode (i.e. 32-bit wide flash),
+ * but I left other code here in case people order custom boards.
+ *
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef CONFIG_ENV_ADDR
+# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef CONFIG_ENV_SIZE
+# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+# endif
+# ifndef CONFIG_ENV_SECT_SIZE
+# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
+# endif
+#endif
+
+#undef DEBUG
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size;
+ int i;
+
+ /* Init: enable write,
+ * or we cannot even write flash commands
+ */
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+
+ /* set the default sector offset */
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size, size<<20);
+ }
+
+ /* Re-do sizing to get full correct info */
+ size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+
+ flash_info[0].size = size;
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+ &flash_info[0]);
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
+ &flash_info[0]);
+#endif
+#endif
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL: printf ("Intel "); break;
+ case FLASH_MAN_SHARP: printf ("Sharp "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F640C3T: printf ("28F640C3T (64 Mbit x 2, 128 x 128k)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ ulong value;
+ ulong base = (ulong)addr;
+ ulong sector_offset;
+
+#ifdef DEBUG
+ printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+ /* Write "Intelligent Identifier" command: read Manufacturer ID */
+ *addr = 0x90909090;
+ udelay(20);
+ asm("sync");
+
+ value = addr[0] & 0x00FF00FF;
+
+#ifdef DEBUG
+ printf("manufacturer=0x%x\n",(uint)value);
+#endif
+ switch (value) {
+ case MT_MANUFACT: /* SHARP, MT or => Intel */
+ case INTEL_ALT_MANU:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ printf("unknown manufacturer: %x\n", (unsigned int)value);
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr[1]; /* device ID */
+
+#ifdef DEBUG
+ printf("deviceID=0x%x\n",(uint)value);
+#endif
+ switch (value) {
+
+ case (INTEL_ID_28F640C3T):
+ info->flash_id += FLASH_28F640C3T;
+ info->sector_count = 135;
+ info->size = 0x01000000;
+ sector_offset = 0x20000;
+ break; /* => 2x8 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table
+ * The first 127 blocks are large, the last 8 are small.
+ */
+ for (i = 0; i < 127; i++) {
+ info->start[i] = base;
+ base += sector_offset;
+ /* Sectors are locked upon reset */
+ info->protect[i] = 0;
+ }
+ for (i = 127; i < 135; i++) {
+ info->start[i] = base;
+ base += 0x4000;
+ /* Sectors are locked upon reset */
+ info->protect[i] = 0;
+ }
+
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr = (vu_long *)info->start[0];
+ *addr = 0xFFFFFF; /* reset bank to read array mode */
+ asm("sync");
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+ && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+#ifdef DEBUG
+ printf("\nFlash Erase:\n");
+#endif
+ /* Make Sure Block Lock Bit is not set. */
+ if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+ return 1;
+ }
+
+ /* Start erase on unprotected sectors */
+#if defined(DEBUG)
+ printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_long *addr = (vu_long *)(info->start[sect]);
+ asm("sync");
+
+ last = start = get_timer (0);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ asm("sync");
+ /* Clear Status Register */
+ *addr = 0x50505050;
+ asm("sync");
+ /* Single Block Erase Command */
+ *addr = 0x20202020;
+ asm("sync");
+ /* Confirm */
+ *addr = 0xD0D0D0D0;
+ asm("sync");
+
+ if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+ /* Resume Command, as per errata update */
+ *addr = 0xD0D0D0D0;
+ asm("sync");
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+ while ((*addr & 0x00800080) != 0x00800080) {
+ if(*addr & 0x00200020){
+ printf("Error in Block Erase - Lock Bit may be set!\n");
+ printf("Status Register = 0x%X\n", (uint)*addr);
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+ /* reset to read mode */
+ *addr = 0xFFFFFFFF;
+ asm("sync");
+ }
+ }
+
+ printf ("flash erase done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long *)dest;
+ ulong start, csr;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Write Command */
+ *addr = 0x10101010;
+ asm("sync");
+
+ /* Write Data */
+ *addr = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ flag = 0;
+
+ while (((csr = *addr) & 0x00800080) != 0x00800080) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ flag = 1;
+ break;
+ }
+ }
+ if (csr & 0x40404040) {
+ printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+ flag = 1;
+ }
+
+ /* Clear Status Registers Command */
+ *addr = 0x50505050;
+ asm("sync");
+ /* Reset to read array mode */
+ *addr = 0xFFFFFFFF;
+ asm("sync");
+
+ return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long * addr)
+{
+ ulong start, now;
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ asm("sync");
+ /* Clear Status Register */
+ *addr = 0x50505050;
+ asm("sync");
+
+ *addr = 0x60606060;
+ asm("sync");
+ *addr = 0xd0d0d0d0;
+ asm("sync");
+
+ start = get_timer (0);
+ while((*addr & 0x00800080) != 0x00800080){
+ if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout on clearing Block Lock Bit\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ }
+ return 0;
+}
+
+#endif /* !CONFIG_SYS_NO_FLASH */
diff --git a/board/stx/stxgp3/law.c b/board/stx/stxgp3/law.c
new file mode 100644
index 0000000..611fa4b
--- /dev/null
+++ b/board/stx/stxgp3/law.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xfc00_0000 0xfc00_ffff Config Latch 64K
+ * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#endif
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ /* This is not so much the SDRAM map as it is the whole localbus map. */
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c
new file mode 100644
index 0000000..c80d525
--- /dev/null
+++ b/board/stx/stxgp3/stxgp3.c
@@ -0,0 +1,331 @@
+/*
+ * (C) Copyright 2003, Embedded Edge, LLC
+ * Dan Malek, <dan@embeddededge.com>
+ * Copied from ADS85xx.
+ * Updates for Silicon Tx GP3 8560
+ *
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <fsl_ddr_sdram.h>
+#include <ioports.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <miiphy.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
+ /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+static uint64_t next_led_update;
+static uint led_bit;
+
+int
+board_early_init_f(void)
+{
+#if defined(CONFIG_PCI)
+ volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
+
+ pci->peer &= 0xfffffffdf; /* disable master abort */
+#endif
+ return 0;
+}
+
+void
+reset_phy(void)
+{
+ volatile uint *blatch;
+
+ blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE;
+
+ /* reset Giga bit Ethernet port if needed here */
+
+ *blatch &= ~0x000000c0;
+ udelay(100);
+ *blatch = 0x000000c1; /* Light one led, too */
+ udelay(1000);
+
+#if 0 /* This is the port we really want to use for debugging. */
+ /* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+ bcsr->bcsr2 &= ~FETH2_RST;
+ udelay(2);
+ bcsr->bcsr2 |= FETH2_RST;
+ udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+ bcsr->bcsr3 &= ~FETH3_RST;
+ udelay(2);
+ bcsr->bcsr3 |= FETH3_RST;
+ udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+ /* reset PHY */
+ miiphy_reset("FCC1", 0x0);
+
+ /* change PHY address to 0x02 */
+ bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
+
+ bb_miiphy_write(NULL, 0x02, MII_BMCR,
+ BMCR_ANENABLE | BMCR_ANRESTART);
+#endif /* CONFIG_MII */
+#endif
+}
+
+int
+checkboard(void)
+{
+ printf ("Board: Silicon Tx GPPP 8560 Board\n");
+ return (0);
+}
+
+/* Blinkin' LEDS for Robert.
+*/
+void
+show_activity(int flag)
+{
+ volatile uint *blatch;
+
+ if (next_led_update > get_ticks())
+ return;
+
+ blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE;
+
+ led_bit >>= 1;
+ if (led_bit == 0)
+ led_bit = 0x08;
+ *blatch = (0xc0 | led_bit);
+ eieio();
+ next_led_update += (get_tbclk() / 4);
+}
+
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+ uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+ uint *p;
+
+ printf("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_stxgp3_config_table[] = {
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+ } },
+ { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table: pci_stxgp3_config_table,
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
diff --git a/board/stx/stxgp3/tlb.c b/board/stx/stxgp3/tlb.c
new file mode 100644
index 0000000..7c877b2
--- /dev/null
+++ b/board/stx/stxgp3/tlb.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_16M, 1),
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xc0000000 256M Rapid IO MEM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xd0000000 256M Rapid IO MEM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 7: 16K Non-cacheable, guarded
+ * 0xfc000000 16K Configuration Latch register
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE, CONFIG_SYS_LBC_LCLDEVS_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_16K, 1),
+
+#if !defined(CONFIG_SPD_EEPROM)
+ /*
+ * TLB 8, 9: 128M DDR
+ * 0x00000000 64M DDR System memory
+ * 0x04000000 64M DDR System memory
+ * Without SPD EEPROM configured DDR, this must be setup manually.
+ * Make sure the TLB count at the top of this table is correct.
+ * Likely it needs to be increased by two for these entries.
+ */
+#error("Update the number of table entries in tlb1_entry")
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_64M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_64M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/stx/stxssa/Kconfig b/board/stx/stxssa/Kconfig
new file mode 100644
index 0000000..bd47b04
--- /dev/null
+++ b/board/stx/stxssa/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_STXSSA
+
+config SYS_BOARD
+ default "stxssa"
+
+config SYS_VENDOR
+ default "stx"
+
+config SYS_CONFIG_NAME
+ default "stxssa"
+
+endif
diff --git a/board/stx/stxssa/MAINTAINERS b/board/stx/stxssa/MAINTAINERS
new file mode 100644
index 0000000..b7cc89b
--- /dev/null
+++ b/board/stx/stxssa/MAINTAINERS
@@ -0,0 +1,7 @@
+STXSSA BOARD
+#M: Dan Malek <dan@embeddedalley.com>
+S: Orphan (since 2014-06)
+F: board/stx/stxssa/
+F: include/configs/stxssa.h
+F: configs/stxssa_defconfig
+F: configs/stxssa_4M_defconfig
diff --git a/board/stx/stxssa/Makefile b/board/stx/stxssa/Makefile
new file mode 100644
index 0000000..b1d4b0a
--- /dev/null
+++ b/board/stx/stxssa/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += stxssa.o
+obj-y += law.o
+obj-y += tlb.o
+obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o
diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c
new file mode 100644
index 0000000..1ccd4c5
--- /dev/null
+++ b/board/stx/stxssa/ddr.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 0;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /* 2T timing enable */
+ popts->twot_en = 1;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/stx/stxssa/law.c b/board/stx/stxssa/law.c
new file mode 100644
index 0000000..72373f5
--- /dev/null
+++ b/board/stx/stxssa/law.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
+ * 0xf000_0000 0xfaff_ffff Local bus 128M
+ * 0xfb00_0000 0xfb00_ffff Config Latch 64K
+ * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#endif
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+ /* Map the whole localbus, including flash and reset latch. */
+ SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c
new file mode 100644
index 0000000..6e4eed8
--- /dev/null
+++ b/board/stx/stxssa/stxssa.c
@@ -0,0 +1,370 @@
+/*
+ * (C) Copyright 2005, Embedded Alley Solutions, Inc.
+ * Dan Malek, <dan@embeddedalley.com>
+ * Copied from STx GP3.
+ * Updates for Silicon Tx GP3 SSA
+ *
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <fsl_ddr_sdram.h>
+#include <ioports.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
+ /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+static uint64_t next_led_update;
+static uint led_bit;
+
+void
+reset_phy(void)
+{
+ volatile uint *blatch;
+#if 0
+ int i;
+#endif
+ blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
+
+ /* reset Giga bit Ethernet port if needed here */
+
+#if 1
+ *blatch &= ~0x000000c0;
+ udelay(100);
+#else
+ *blatch = 0;
+ asm("eieio");
+ for (i=0; i<1000; i++)
+ udelay(1000);
+#endif
+ *blatch = 0x000000c1; /* Light one led, too */
+ udelay(1000);
+
+#if 0 /* This is the port we really want to use for debugging. */
+ /* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+ bcsr->bcsr2 &= ~FETH2_RST;
+ udelay(2);
+ bcsr->bcsr2 |= FETH2_RST;
+ udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+ bcsr->bcsr3 &= ~FETH3_RST;
+ udelay(2);
+ bcsr->bcsr3 |= FETH3_RST;
+ udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+ /* reset PHY */
+ miiphy_reset("FCC1", 0x0);
+
+ /* change PHY address to 0x02 */
+ bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
+
+ bb_miiphy_write(NULL, 0x02, MII_BMCR,
+ BMCR_ANENABLE | BMCR_ANRESTART);
+#endif /* CONFIG_MII */
+#endif
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup (blob, bd);
+
+ return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+int
+board_early_init_f(void)
+{
+#if defined(CONFIG_PCI)
+ volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
+
+ pci->peer &= 0xffffffdf; /* disable master abort */
+#endif
+
+ /* Why is the phy reset done _after_ the ethernet
+ * initialization in arch/powerpc/lib/board.c?
+ * Do it here so it's done before the TSECs are used.
+ */
+ reset_phy();
+
+ return 0;
+}
+
+int
+checkboard(void)
+{
+ printf ("Board: Silicon Tx GPPP SSA Board\n");
+ return (0);
+}
+
+/* Blinkin' LEDS for Robert.
+*/
+void
+show_activity(int flag)
+{
+ volatile uint *blatch;
+
+ if (next_led_update > get_ticks())
+ return;
+
+ blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
+
+ led_bit >>= 1;
+ if (led_bit == 0)
+ led_bit = 0x08;
+ *blatch = (0xc0 | led_bit);
+ eieio();
+ next_led_update += (get_tbclk() / 4);
+}
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+ uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
+ uint *p;
+
+ printf("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_stxgp3_config_table[] = {
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+ } },
+ { }
+};
+#endif
+
+
+static struct pci_controller hose[] = {
+#ifndef CONFIG_PCI_PNP
+ { config_table: pci_stxgp3_config_table,},
+#else
+ {},
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+ pci_mpc85xx_init(hose);
+#endif /* CONFIG_PCI */
+}
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Initialize TSECs first */
+ return pci_eth_init(bis);
+}
diff --git a/board/stx/stxssa/tlb.c b/board/stx/stxssa/tlb.c
new file mode 100644
index 0000000..49c630c
--- /dev/null
+++ b/board/stx/stxssa/tlb.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /*
+ * TLB 0: 64M Non-cacheable, guarded
+ * 0xfc000000 6M4 FLASH
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xa0000000 256M PCI2 MEM First half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xb0000000 256M PCI2 MEM Second half
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ * 0xe300_0000 16M PCI2 IO
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 6: 256M Non-cacheable, guarded
+ * 0xf0000000 Local bus expansion option.
+ * 0xfb000000 Configuration Latch register (one word)
+ * 0xfc000000 Up to 64M flash
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, CONFIG_SYS_LBC_OPTION_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
new file mode 100644
index 0000000..5ae491d
--- /dev/null
+++ b/board/sunxi/Kconfig
@@ -0,0 +1,232 @@
+if ARCH_SUNXI
+
+choice
+ prompt "Sunxi SoC Variant"
+
+config MACH_SUN4I
+ bool "sun4i (Allwinner A10)"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config MACH_SUN5I
+ bool "sun5i (Allwinner A13)"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config MACH_SUN6I
+ bool "sun6i (Allwinner A31)"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config MACH_SUN7I
+ bool "sun7i (Allwinner A20)"
+ select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select SUPPORT_SPL
+ select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+
+config MACH_SUN8I
+ bool "sun8i (Allwinner A23)"
+ select CPU_V7
+
+endchoice
+
+config SYS_CONFIG_NAME
+ default "sun4i" if MACH_SUN4I
+ default "sun5i" if MACH_SUN5I
+ default "sun6i" if MACH_SUN6I
+ default "sun7i" if MACH_SUN7I
+ default "sun8i" if MACH_SUN8I
+
+choice
+ prompt "Board"
+
+config TARGET_A10_OLINUXINO_L
+ bool "A10_OLINUXINO_L"
+ depends on MACH_SUN4I
+
+config TARGET_A10S_OLINUXINO_M
+ bool "A10S_OLINUXINO_M"
+ depends on MACH_SUN5I
+
+config TARGET_A13_OLINUXINOM
+ bool "A13_OLINUXINOM"
+ depends on MACH_SUN5I
+
+config TARGET_A13_OLINUXINO
+ bool "A13_OLINUXINO"
+ depends on MACH_SUN5I
+
+config TARGET_A20_OLINUXINO_L2
+ bool "A20_OLINUXINO_L2"
+ depends on MACH_SUN7I
+
+config TARGET_A20_OLINUXINO_L
+ bool "A20_OLINUXINO_L"
+ depends on MACH_SUN7I
+
+config TARGET_A20_OLINUXINO_M
+ bool "A20_OLINUXINO_M"
+ depends on MACH_SUN7I
+
+config TARGET_AUXTEK_T004
+ bool "AUXTEK_T004"
+ depends on MACH_SUN5I
+
+config TARGET_BANANAPI
+ bool "BANANAPI"
+ depends on MACH_SUN7I
+
+config TARGET_COLOMBUS
+ bool "COLOMBUS"
+ depends on MACH_SUN6I
+
+config TARGET_CUBIEBOARD2
+ bool "CUBIEBOARD2"
+ depends on MACH_SUN7I
+
+config TARGET_CUBIEBOARD
+ bool "CUBIEBOARD"
+ depends on MACH_SUN4I
+
+config TARGET_CUBIETRUCK
+ bool "CUBIETRUCK"
+ depends on MACH_SUN7I
+
+config TARGET_IPPO_Q8H_V5
+ bool "IPPO_Q8H_V5"
+ depends on MACH_SUN8I
+
+config TARGET_PCDUINO3
+ bool "PCDUINO3"
+ depends on MACH_SUN7I
+
+config TARGET_MELE_A1000G
+ bool "MELE_A1000G"
+ depends on MACH_SUN4I
+
+config TARGET_MELE_A1000
+ bool "MELE_A1000"
+ depends on MACH_SUN4I
+
+config TARGET_MELE_M3
+ bool "MELE_M3"
+ depends on MACH_SUN7I
+
+config TARGET_MELE_M9
+ bool "MELE_M9"
+ depends on MACH_SUN6I
+
+config TARGET_MINI_X_1GB
+ bool "MINI_X_1GB"
+ depends on MACH_SUN4I
+
+config TARGET_MINI_X
+ bool "MINI_X"
+ depends on MACH_SUN4I
+
+config TARGET_BA10_TV_BOX
+ bool "BA10_TV_BOX"
+ depends on MACH_SUN4I
+
+config TARGET_I12_TVBOX
+ bool "I12_TVBOX"
+ depends on MACH_SUN7I
+
+config TARGET_QT840A
+ bool "QT840A"
+ depends on MACH_SUN7I
+
+config TARGET_R7DONGLE
+ bool "R7DONGLE"
+ depends on MACH_SUN5I
+
+endchoice
+
+config SYS_BOARD
+ default "sunxi"
+
+config SYS_SOC
+ default "sunxi"
+
+config SPL_FEL
+ bool "SPL/FEL mode support"
+ depends on SPL
+ default n
+
+config FDTFILE
+ string "Default fdtfile env setting for this board"
+
+config OLD_SUNXI_KERNEL_COMPAT
+ boolean "Enable workarounds for booting old kernels"
+ default n
+ ---help---
+ Set this to enable various workarounds for old kernels, this results in
+ sub-optimal settings for newer kernels, only enable if needed.
+
+config MMC0_CD_PIN
+ string "Card detect pin for mmc0"
+ default ""
+ ---help---
+ Set the card detect pin for mmc0, leave empty to not use cd. This
+ takes a string in the format understood by sunxi_name_to_gpio, e.g.
+ PH1 for pin 1 of port H.
+
+config MMC1_CD_PIN
+ string "Card detect pin for mmc1"
+ default ""
+ ---help---
+ See MMC0_CD_PIN help text.
+
+config MMC2_CD_PIN
+ string "Card detect pin for mmc2"
+ default ""
+ ---help---
+ See MMC0_CD_PIN help text.
+
+config MMC3_CD_PIN
+ string "Card detect pin for mmc3"
+ default ""
+ ---help---
+ See MMC0_CD_PIN help text.
+
+config MMC_SUNXI_SLOT_EXTRA
+ int "mmc extra slot number"
+ default -1
+ ---help---
+ sunxi builds always enable mmc0, some boards also have a second sdcard
+ slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
+ support for this.
+
+config USB1_VBUS_PIN
+ string "Vbus enable pin for usb1 (ehci0)"
+ default "PH6" if MACH_SUN4I || MACH_SUN7I
+ default "PH27" if MACH_SUN6I
+ ---help---
+ Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
+ a string in the format understood by sunxi_name_to_gpio, e.g.
+ PH1 for pin 1 of port H.
+
+config USB2_VBUS_PIN
+ string "Vbus enable pin for usb2 (ehci1)"
+ default "PH3" if MACH_SUN4I || MACH_SUN7I
+ default "PH24" if MACH_SUN6I
+ ---help---
+ See USB1_VBUS_PIN help text.
+
+config VIDEO
+ boolean "Enable graphical uboot console on HDMI"
+ default y
+ ---help---
+ Say Y here to add support for using a cfb console on the HDMI output
+ found on most sunxi devices.
+
+config USB_KEYBOARD
+ boolean "Enable USB keyboard support"
+ default y
+ ---help---
+ Say Y here to add support for using a USB keyboard (typically used
+ in combination with a graphical console on HDMI).
+
+endif
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
new file mode 100644
index 0000000..ca03002
--- /dev/null
+++ b/board/sunxi/MAINTAINERS
@@ -0,0 +1,59 @@
+SUNXI BOARD
+M: Hans de Goede <hdegoede@redhat.com>
+S: Maintained
+F: board/sunxi/
+F: include/configs/sun4i.h
+F: configs/A10-OLinuXino-Lime_defconfig
+F: configs/ba10_tv_box_defconfig
+F: configs/Cubieboard_defconfig
+F: configs/Mele_A1000_defconfig
+F: configs/Mele_A1000G_defconfig
+F: configs/Mele_M3_defconfig
+F: configs/Mele_M9_defconfig
+F: configs/Mini-X_defconfig
+F: configs/Mini-X-1Gb_defconfig
+F: include/configs/sun5i.h
+F: configs/A10s-OLinuXino-M_defconfig
+F: configs/A13-OLinuXino_defconfig
+F: configs/A13-OLinuXinoM_defconfig
+F: configs/Auxtek-T004_defconfig
+F: configs/r7-tv-dongle_defconfig
+F: include/configs/sun7i.h
+F: configs/A20-OLinuXino_MICRO_defconfig
+F: configs/Bananapi_defconfig
+F: configs/i12-tvbox_defconfig
+F: configs/Linksprite_pcDuino3_defconfig
+F: configs/Linksprite_pcDuino3_fdt_defconfig
+F: configs/qt840a_defconfig
+
+CUBIEBOARD2 BOARD
+M: Ian Campbell <ijc@hellion.org.uk>
+M: Hans de Goede <hdegoede@redhat.com>
+S: Maintained
+F: include/configs/sun7i.h
+F: configs/Cubieboard2_defconfig
+F: configs/Cubieboard2_FEL_defconfig
+F: configs/Cubietruck_defconfig
+F: configs/Cubietruck_FEL_defconfig
+
+A20-OLINUXINO-LIME BOARD
+M: FUKAUMI Naoki <naobsd@gmail.com>
+S: Maintained
+F: board/sunxi/dram_a20_olinuxino_l.c
+F: configs/A20-OLinuXino-Lime_defconfig
+
+A20-OLINUXINO-LIME2 BOARD
+M: Iain Paton <ipaton0@gmail.com>
+S: Maintained
+F: board/sunxi/dram_a20_olinuxino_l2.c
+F: configs/A20-OLinuXino-Lime2_defconfig
+
+COLOMBUS BOARD
+M: Maxime Ripard <maxime.ripard@free-electrons.com>
+S: Maintained
+F: configs/Colombus_defconfig
+
+IPPO-Q8H-V5 BOARD
+M: Chen-Yu Tsai <wens@csie.org>
+S: Maintained
+F: configs/Ippo_q8h_v5_defconfig
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
new file mode 100644
index 0000000..b84ff9b
--- /dev/null
+++ b/board/sunxi/Makefile
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+#
+# Based on some other board Makefile
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-y += board.o
+obj-$(CONFIG_SUNXI_GMAC) += gmac.o
+obj-$(CONFIG_SUNXI_AHCI) += ahci.o
+obj-$(CONFIG_TARGET_A10_OLINUXINO_L) += dram_a10_olinuxino_l.o
+obj-$(CONFIG_TARGET_A10S_OLINUXINO_M) += dram_a10s_olinuxino_m.o
+obj-$(CONFIG_TARGET_A13_OLINUXINO) += dram_a13_olinuxino.o
+obj-$(CONFIG_TARGET_A13_OLINUXINOM) += dram_a13_oli_micro.o
+obj-$(CONFIG_TARGET_A20_OLINUXINO_L) += dram_a20_olinuxino_l.o
+obj-$(CONFIG_TARGET_A20_OLINUXINO_L2) += dram_a20_olinuxino_l2.o
+obj-$(CONFIG_TARGET_A20_OLINUXINO_M) += dram_sun7i_384_1024_iow16.o
+# This is not a typo, uses the same mem settings as the a10s-olinuxino-m
+obj-$(CONFIG_TARGET_AUXTEK_T004) += dram_a10s_olinuxino_m.o
+obj-$(CONFIG_TARGET_BA10_TV_BOX) += dram_sun4i_384_1024_iow8.o
+obj-$(CONFIG_TARGET_BANANAPI) += dram_bananapi.o
+obj-$(CONFIG_TARGET_CUBIEBOARD) += dram_cubieboard.o
+obj-$(CONFIG_TARGET_CUBIEBOARD2) += dram_cubieboard2.o
+obj-$(CONFIG_TARGET_CUBIETRUCK) += dram_cubietruck.o
+obj-$(CONFIG_TARGET_I12_TVBOX) += dram_sun7i_384_1024_iow16.o
+obj-$(CONFIG_TARGET_MELE_A1000) += dram_sun4i_360_512.o
+obj-$(CONFIG_TARGET_MELE_A1000G) += dram_sun4i_360_1024_iow8.o
+obj-$(CONFIG_TARGET_MELE_M3) += dram_sun7i_384_1024_iow16.o
+obj-$(CONFIG_TARGET_MINI_X) += dram_sun4i_360_512.o
+obj-$(CONFIG_TARGET_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o
+obj-$(CONFIG_TARGET_PCDUINO3) += dram_linksprite_pcduino3.o
+obj-$(CONFIG_TARGET_QT840A) += dram_sun7i_384_512_busw16_iow16.o
+obj-$(CONFIG_TARGET_R7DONGLE) += dram_r7dongle.o
diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c
new file mode 100644
index 0000000..b7f0dda
--- /dev/null
+++ b/board/sunxi/ahci.c
@@ -0,0 +1,87 @@
+#include <common.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#define AHCI_PHYCS0R 0x00c0
+#define AHCI_PHYCS1R 0x00c4
+#define AHCI_PHYCS2R 0x00c8
+#define AHCI_RWCR 0x00fc
+
+/* This magic PHY initialisation was taken from the Allwinner releases
+ * and Linux driver, but is completely undocumented.
+ */
+static int sunxi_ahci_phy_init(u32 base)
+{
+ u8 *reg_base = (u8 *)base;
+ u32 reg_val;
+ int timeout;
+
+ writel(0, reg_base + AHCI_RWCR);
+ mdelay(5);
+
+ setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R,
+ (0x7 << 24),
+ (0x5 << 24) | (0x1 << 23) | (0x1 << 18));
+ clrsetbits_le32(reg_base + AHCI_PHYCS1R,
+ (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
+ (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
+ setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));
+ clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
+ clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
+ mdelay(5);
+
+ setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
+
+ timeout = 250; /* Power up takes approx 50 us */
+ for (;;) {
+ reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28);
+ if (reg_val == (0x2 << 28))
+ break;
+ if (--timeout == 0) {
+ printf("AHCI PHY power up failed.\n");
+ return -EIO;
+ }
+ udelay(1);
+ };
+
+ setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
+
+ timeout = 100; /* Calibration takes approx 10 us */
+ for (;;) {
+ reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24);
+ if (reg_val == 0x0)
+ break;
+ if (--timeout == 0) {
+ printf("AHCI PHY calibration failed.\n");
+ return -EIO;
+ }
+ udelay(1);
+ }
+
+ mdelay(15);
+
+ writel(0x7, reg_base + AHCI_RWCR);
+
+ return 0;
+}
+
+void scsi_init(void)
+{
+ printf("SUNXI SCSI INIT\n");
+#ifdef CONFIG_SATAPWR
+ gpio_request(CONFIG_SATAPWR, "satapwr");
+ gpio_direction_output(CONFIG_SATAPWR, 1);
+ /* Give attached sata device time to power-up to avoid link timeouts */
+ mdelay(500);
+#endif
+
+ if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
+ return;
+
+ ahci_init(SUNXI_SATA_BASE);
+}
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
new file mode 100644
index 0000000..4c1c69a
--- /dev/null
+++ b/board/sunxi/board.c
@@ -0,0 +1,249 @@
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Some board init for the Allwinner A10-evb board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#ifdef CONFIG_AXP152_POWER
+#include <axp152.h>
+#endif
+#ifdef CONFIG_AXP209_POWER
+#include <axp209.h>
+#endif
+#ifdef CONFIG_AXP221_POWER
+#include <axp221.h>
+#endif
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/display.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/io.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* add board specific code here */
+int board_init(void)
+{
+ int id_pfr1;
+
+ gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
+
+ asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
+ debug("id_pfr1: 0x%08x\n", id_pfr1);
+ /* Generic Timer Extension available? */
+ if ((id_pfr1 >> 16) & 0xf) {
+ debug("Setting CNTFRQ\n");
+ /* CNTFRQ == 24 MHz */
+ asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
+ }
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
+
+ return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+static void mmc_pinmux_setup(int sdc)
+{
+ unsigned int pin;
+
+ switch (sdc) {
+ case 0:
+ /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
+ for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ break;
+
+ case 1:
+ /* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */
+ for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ break;
+
+ case 2:
+ /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
+ for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ break;
+
+ case 3:
+ /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
+ for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ break;
+
+ default:
+ printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
+ break;
+ }
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ __maybe_unused struct mmc *mmc0, *mmc1;
+ __maybe_unused char buf[512];
+
+ mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
+ mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
+ if (!mmc0)
+ return -1;
+
+#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
+ mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
+ mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
+ if (!mmc1)
+ return -1;
+#endif
+
+#if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
+ /*
+ * Both mmc0 and mmc2 are bootable, figure out where we're booting
+ * from. Try mmc0 first, just like the brom does.
+ */
+ if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 &&
+ mmc0->block_dev.block_read(0, 16, 1, buf) == 1) {
+ buf[12] = 0;
+ if (strcmp(&buf[4], "eGON.BT0") == 0)
+ return 0;
+ }
+
+ /* no bootable card in mmc0, so we must be booting from mmc2, swap */
+ mmc0->block_dev.dev = 1;
+ mmc1->block_dev.dev = 0;
+#endif
+
+ return 0;
+}
+#endif
+
+void i2c_init_board(void)
+{
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
+ clock_twi_onoff(0, 1);
+}
+
+#ifdef CONFIG_SPL_BUILD
+void sunxi_board_init(void)
+{
+ int power_failed = 0;
+ unsigned long ramsize;
+
+#ifdef CONFIG_AXP152_POWER
+ power_failed = axp152_init();
+ power_failed |= axp152_set_dcdc2(1400);
+ power_failed |= axp152_set_dcdc3(1500);
+ power_failed |= axp152_set_dcdc4(1250);
+ power_failed |= axp152_set_ldo2(3000);
+#endif
+#ifdef CONFIG_AXP209_POWER
+ power_failed |= axp209_init();
+ power_failed |= axp209_set_dcdc2(1400);
+ power_failed |= axp209_set_dcdc3(1250);
+ power_failed |= axp209_set_ldo2(3000);
+ power_failed |= axp209_set_ldo3(2800);
+ power_failed |= axp209_set_ldo4(2800);
+#endif
+#ifdef CONFIG_AXP221_POWER
+ power_failed = axp221_init();
+ power_failed |= axp221_set_dcdc1(3000);
+ power_failed |= axp221_set_dcdc2(1200);
+ power_failed |= axp221_set_dcdc3(1200);
+ power_failed |= axp221_set_dcdc4(1200);
+ power_failed |= axp221_set_dcdc5(1500);
+#if CONFIG_AXP221_DLDO1_VOLT != -1
+ power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT);
+#endif
+#if CONFIG_AXP221_DLDO4_VOLT != -1
+ power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO1_VOLT != -1
+ power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO2_VOLT != -1
+ power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO3_VOLT != -1
+ power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
+#endif
+#endif
+
+ printf("DRAM:");
+ ramsize = sunxi_dram_init();
+ printf(" %lu MiB\n", ramsize >> 20);
+ if (!ramsize)
+ hang();
+
+ /*
+ * Only clock up the CPU to full speed if we are reasonably
+ * assured it's being powered with suitable core voltage
+ */
+ if (!power_failed)
+ clock_set_pll1(CONFIG_CLK_FULL_SPEED);
+ else
+ printf("Failed to set core voltage! Can't set CPU frequency\n");
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ if (!getenv("ethaddr")) {
+ uint32_t reg_val = readl(SUNXI_SID_BASE);
+
+ if (reg_val) {
+ uint8_t mac_addr[6];
+
+ mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
+ mac_addr[1] = (reg_val >> 0) & 0xff;
+ reg_val = readl(SUNXI_SID_BASE + 0x0c);
+ mac_addr[2] = (reg_val >> 24) & 0xff;
+ mac_addr[3] = (reg_val >> 16) & 0xff;
+ mac_addr[4] = (reg_val >> 8) & 0xff;
+ mac_addr[5] = (reg_val >> 0) & 0xff;
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_VIDEO_DT_SIMPLEFB
+ return sunxi_simplefb_setup(blob);
+#endif
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/sunxi/dram_a10_olinuxino_l.c b/board/sunxi/dram_a10_olinuxino_l.c
new file mode 100644
index 0000000..24a1bd9
--- /dev/null
+++ b/board/sunxi/dram_a10_olinuxino_l.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 480,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 16,
+ .cas = 6,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 512,
+ .tpr0 = 0x30926692,
+ .tpr1 = 0x1090,
+ .tpr2 = 0x1a0c8,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0x4,
+ .emr2 = 0,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_a10s_olinuxino_m.c b/board/sunxi/dram_a10s_olinuxino_m.c
new file mode 100644
index 0000000..8900539
--- /dev/null
+++ b/board/sunxi/dram_a10s_olinuxino_m.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 432,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 16,
+ .cas = 9,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 512,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_a13_oli_micro.c b/board/sunxi/dram_a13_oli_micro.c
new file mode 100644
index 0000000..8154ea2
--- /dev/null
+++ b/board/sunxi/dram_a13_oli_micro.c
@@ -0,0 +1,32 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 408,
+ .type = 3,
+ .rank_num = 1,
+ .density = 2048,
+ .io_width = 16,
+ .bus_width = 16,
+ .cas = 9,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 256,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0,
+ .emr2 = 0x10,
+ .emr3 = 0,
+
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_a13_olinuxino.c b/board/sunxi/dram_a13_olinuxino.c
new file mode 100644
index 0000000..ca96260
--- /dev/null
+++ b/board/sunxi/dram_a13_olinuxino.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 408,
+ .type = 3,
+ .rank_num = 1,
+ .density = 2048,
+ .io_width = 8,
+ .bus_width = 16,
+ .cas = 9,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 512,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0,
+ .emr2 = 0x10,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_a20_olinuxino_l.c b/board/sunxi/dram_a20_olinuxino_l.c
new file mode 100644
index 0000000..2c74999
--- /dev/null
+++ b/board/sunxi/dram_a20_olinuxino_l.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include "common.h"
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 480,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 16,
+ .cas = 9,
+ .zq = 0x7f,
+ .odt_en = 0,
+ .size = 512,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_a20_olinuxino_l2.c b/board/sunxi/dram_a20_olinuxino_l2.c
new file mode 100644
index 0000000..2115d37
--- /dev/null
+++ b/board/sunxi/dram_a20_olinuxino_l2.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 480,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 0x7f,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_bananapi.c b/board/sunxi/dram_bananapi.c
new file mode 100644
index 0000000..0ed7943
--- /dev/null
+++ b/board/sunxi/dram_bananapi.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 432,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 0x7f,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0x0,
+ .tpr4 = 0x1,
+ .tpr5 = 0x0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0x0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_cubieboard.c b/board/sunxi/dram_cubieboard.c
new file mode 100644
index 0000000..399028c
--- /dev/null
+++ b/board/sunxi/dram_cubieboard.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 480,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 6,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x30926692,
+ .tpr1 = 0x1090,
+ .tpr2 = 0x1a0c8,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0,
+ .emr2 = 0,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_cubieboard2.c b/board/sunxi/dram_cubieboard2.c
new file mode 100644
index 0000000..9e75367
--- /dev/null
+++ b/board/sunxi/dram_cubieboard2.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 480,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 0x7f,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0x0,
+ .tpr4 = 0x1,
+ .tpr5 = 0x0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0x0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_cubietruck.c b/board/sunxi/dram_cubietruck.c
new file mode 100644
index 0000000..fbcd687
--- /dev/null
+++ b/board/sunxi/dram_cubietruck.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 432,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 8,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 0x7f,
+ .odt_en = 0,
+ .size = 2048,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0x0,
+ .tpr4 = 0x1,
+ .tpr5 = 0x0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0x0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_linksprite_pcduino3.c b/board/sunxi/dram_linksprite_pcduino3.c
new file mode 100644
index 0000000..9cc6e19
--- /dev/null
+++ b/board/sunxi/dram_linksprite_pcduino3.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 480,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 0x7a,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0x0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_r7dongle.c b/board/sunxi/dram_r7dongle.c
new file mode 100644
index 0000000..59343cb
--- /dev/null
+++ b/board/sunxi/dram_r7dongle.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 384,
+ .type = 3,
+ .rank_num = 1,
+ .density = 2048,
+ .io_width = 8,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0x04,
+ .emr2 = 0x10,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_sun4i_360_1024_iow16.c b/board/sunxi/dram_sun4i_360_1024_iow16.c
new file mode 100644
index 0000000..3763713
--- /dev/null
+++ b/board/sunxi/dram_sun4i_360_1024_iow16.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 360,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 6,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x30926692,
+ .tpr1 = 0x1090,
+ .tpr2 = 0x1a0c8,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0,
+ .emr2 = 0,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_sun4i_360_1024_iow8.c b/board/sunxi/dram_sun4i_360_1024_iow8.c
new file mode 100644
index 0000000..2a5c9ed
--- /dev/null
+++ b/board/sunxi/dram_sun4i_360_1024_iow8.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 360,
+ .type = 3,
+ .rank_num = 1,
+ .density = 2048,
+ .io_width = 8,
+ .bus_width = 32,
+ .cas = 6,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x30926692,
+ .tpr1 = 0x1090,
+ .tpr2 = 0x1a0c8,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0,
+ .emr2 = 0,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_sun4i_360_512.c b/board/sunxi/dram_sun4i_360_512.c
new file mode 100644
index 0000000..48aa6e2
--- /dev/null
+++ b/board/sunxi/dram_sun4i_360_512.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 360,
+ .type = 3,
+ .rank_num = 1,
+ .density = 2048,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 6,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 512,
+ .tpr0 = 0x30926692,
+ .tpr1 = 0x1090,
+ .tpr2 = 0x1a0c8,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0,
+ .emr2 = 0,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_sun4i_384_1024_iow8.c b/board/sunxi/dram_sun4i_384_1024_iow8.c
new file mode 100644
index 0000000..b0fcc55
--- /dev/null
+++ b/board/sunxi/dram_sun4i_384_1024_iow8.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include <common.h>
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 384,
+ .type = 3,
+ .rank_num = 1,
+ .density = 2048,
+ .io_width = 8,
+ .bus_width = 32,
+ .cas = 6,
+ .zq = 123,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x30926692,
+ .tpr1 = 0x1090,
+ .tpr2 = 0x1a0c8,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0x4,
+ .emr2 = 0,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_sun7i_384_1024_iow16.c b/board/sunxi/dram_sun7i_384_1024_iow16.c
new file mode 100644
index 0000000..04e4b1e
--- /dev/null
+++ b/board/sunxi/dram_sun7i_384_1024_iow16.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include "common.h"
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 384,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 32,
+ .cas = 9,
+ .zq = 0x7f,
+ .odt_en = 0,
+ .size = 1024,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/dram_sun7i_384_512_busw16_iow16.c b/board/sunxi/dram_sun7i_384_512_busw16_iow16.c
new file mode 100644
index 0000000..2e36011
--- /dev/null
+++ b/board/sunxi/dram_sun7i_384_512_busw16_iow16.c
@@ -0,0 +1,31 @@
+/* this file is generated, don't edit it yourself */
+
+#include "common.h"
+#include <asm/arch/dram.h>
+
+static struct dram_para dram_para = {
+ .clock = 384,
+ .type = 3,
+ .rank_num = 1,
+ .density = 4096,
+ .io_width = 16,
+ .bus_width = 16,
+ .cas = 9,
+ .zq = 0x7f,
+ .odt_en = 0,
+ .size = 512,
+ .tpr0 = 0x42d899b7,
+ .tpr1 = 0xa090,
+ .tpr2 = 0x22a00,
+ .tpr3 = 0,
+ .tpr4 = 0,
+ .tpr5 = 0,
+ .emr1 = 0x4,
+ .emr2 = 0x10,
+ .emr3 = 0,
+};
+
+unsigned long sunxi_dram_init(void)
+{
+ return dramc_init(&dram_para);
+}
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
new file mode 100644
index 0000000..571bc9e
--- /dev/null
+++ b/board/sunxi/gmac.c
@@ -0,0 +1,97 @@
+#include <common.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+
+int sunxi_gmac_initialize(bd_t *bis)
+{
+ int pin;
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* Set up clock gating */
+#ifndef CONFIG_MACH_SUN6I
+ setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
+#else
+ setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
+ setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
+#endif
+
+ /* Set MII clock */
+#ifdef CONFIG_RGMII
+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+ CCM_GMAC_CTRL_GPIT_RGMII);
+#else
+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
+ CCM_GMAC_CTRL_GPIT_MII);
+#endif
+
+ /*
+ * In order for the gmac nic to work reliable on the Bananapi, we
+ * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain"
+ * of the GMAC clk register to 3.
+ */
+#ifdef CONFIG_TARGET_BANANAPI
+ setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
+#endif
+
+#ifndef CONFIG_MACH_SUN6I
+ /* Configure pin mux settings for GMAC */
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#ifdef CONFIG_RGMII
+ /* skip unused pins in RGMII mode */
+ if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
+ continue;
+#endif
+ sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+#elif defined CONFIG_RGMII
+ /* Configure sun6i RGMII mode pin mux settings */
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+ for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+ for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+ for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 3);
+ }
+#elif defined CONFIG_GMII
+ /* Configure sun6i GMII mode pin mux settings */
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+#else
+ /* Configure sun6i MII mode pin mux settings */
+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+ for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
+ sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+#endif
+
+#ifdef CONFIG_RGMII
+ return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
+#elif defined CONFIG_GMII
+ return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
+#else
+ return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
+#endif
+}
diff --git a/board/synopsys/Kconfig b/board/synopsys/Kconfig
new file mode 100644
index 0000000..a54d3df
--- /dev/null
+++ b/board/synopsys/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_ARCANGEL4
+
+config SYS_CPU
+ default "arc700"
+
+config SYS_VENDOR
+ default "synopsys"
+
+config SYS_CONFIG_NAME
+ default "arcangel4"
+
+endif
+
+if TARGET_ARCANGEL4_BE
+
+config SYS_CPU
+ default "arc700"
+
+config SYS_VENDOR
+ default "synopsys"
+
+config SYS_CONFIG_NAME
+ default "arcangel4-be"
+
+endif
diff --git a/board/synopsys/MAINTAINERS b/board/synopsys/MAINTAINERS
new file mode 100644
index 0000000..720edd8
--- /dev/null
+++ b/board/synopsys/MAINTAINERS
@@ -0,0 +1,7 @@
+- BOARD
+M: Alexey Brodkin <abrodkin@synopsys.com>
+S: Maintained
+F: include/configs/arcangel4.h
+F: configs/arcangel4_defconfig
+F: include/configs/arcangel4-be.h
+F: configs/arcangel4-be_defconfig
diff --git a/board/synopsys/axs101/Kconfig b/board/synopsys/axs101/Kconfig
new file mode 100644
index 0000000..8448265
--- /dev/null
+++ b/board/synopsys/axs101/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AXS101
+
+config SYS_CPU
+ default "arc700"
+
+config SYS_BOARD
+ default "axs101"
+
+config SYS_VENDOR
+ default "synopsys"
+
+config SYS_CONFIG_NAME
+ default "axs101"
+
+endif
diff --git a/board/synopsys/axs101/MAINTAINERS b/board/synopsys/axs101/MAINTAINERS
new file mode 100644
index 0000000..481bbcc
--- /dev/null
+++ b/board/synopsys/axs101/MAINTAINERS
@@ -0,0 +1,6 @@
+AXS101 BOARD
+M: Alexey Brodkin <abrodkin@synopsys.com>
+S: Maintained
+F: board/synopsys/axs101/
+F: include/configs/axs101.h
+F: configs/axs101_defconfig
diff --git a/board/synopsys/axs101/Makefile b/board/synopsys/axs101/Makefile
new file mode 100644
index 0000000..f0965f7
--- /dev/null
+++ b/board/synopsys/axs101/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += axs101.o
+obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
new file mode 100644
index 0000000..d1271ff
--- /dev/null
+++ b/board/synopsys/axs101/axs101.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dwmmc.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_mmc_init(bd_t *bis)
+{
+ struct dwmci_host *host = NULL;
+
+ host = malloc(sizeof(struct dwmci_host));
+ if (!host) {
+ printf("dwmci_host malloc fail!\n");
+ return 1;
+ }
+
+ memset(host, 0, sizeof(struct dwmci_host));
+ host->name = "Synopsys Mobile storage";
+ host->ioaddr = (void *)ARC_DWMMC_BASE;
+ host->buswidth = 4;
+ host->dev_index = 0;
+ host->bus_hz = 25000000;
+
+ add_dwmci(host, 52000000, 400000);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ if (designware_initialize(ARC_DWGMAC_BASE,
+ PHY_INTERFACE_MODE_RGMII) >= 0)
+ return 1;
+
+ return 0;
+}
diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c
new file mode 100644
index 0000000..ff35286
--- /dev/null
+++ b/board/synopsys/axs101/nand.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <bouncebuf.h>
+#include <common.h>
+#include <malloc.h>
+#include <nand.h>
+#include <asm/io.h>
+
+#define BUS_WIDTH 8 /* AXI data bus width in bytes */
+
+/* DMA buffer descriptor bits & masks */
+#define BD_STAT_OWN (1 << 31)
+#define BD_STAT_BD_FIRST (1 << 3)
+#define BD_STAT_BD_LAST (1 << 2)
+#define BD_SIZES_BUFFER1_MASK 0xfff
+
+#define BD_STAT_BD_COMPLETE (BD_STAT_BD_FIRST | BD_STAT_BD_LAST)
+
+/* Controller command flags */
+#define B_WFR (1 << 19) /* 1b - Wait for ready */
+#define B_LC (1 << 18) /* 1b - Last cycle */
+#define B_IWC (1 << 13) /* 1b - Interrupt when complete */
+
+/* NAND cycle types */
+#define B_CT_ADDRESS (0x0 << 16) /* Address operation */
+#define B_CT_COMMAND (0x1 << 16) /* Command operation */
+#define B_CT_WRITE (0x2 << 16) /* Write operation */
+#define B_CT_READ (0x3 << 16) /* Write operation */
+
+enum nand_isr_t {
+ NAND_ISR_DATAREQUIRED = 0,
+ NAND_ISR_TXUNDERFLOW,
+ NAND_ISR_TXOVERFLOW,
+ NAND_ISR_DATAAVAILABLE,
+ NAND_ISR_RXUNDERFLOW,
+ NAND_ISR_RXOVERFLOW,
+ NAND_ISR_TXDMACOMPLETE,
+ NAND_ISR_RXDMACOMPLETE,
+ NAND_ISR_DESCRIPTORUNAVAILABLE,
+ NAND_ISR_CMDDONE,
+ NAND_ISR_CMDAVAILABLE,
+ NAND_ISR_CMDERROR,
+ NAND_ISR_DATATRANSFEROVER,
+ NAND_ISR_NONE
+};
+
+enum nand_regs_t {
+ AC_FIFO = 0, /* address and command fifo */
+ IDMAC_BDADDR = 0x18, /* idmac descriptor list base address */
+ INT_STATUS = 0x118, /* interrupt status register */
+ INT_CLR_STATUS = 0x120, /* interrupt clear status register */
+};
+
+struct nand_bd {
+ uint32_t status; /* DES0 */
+ uint32_t sizes; /* DES1 */
+ uint32_t buffer_ptr0; /* DES2 */
+ uint32_t buffer_ptr1; /* DES3 */
+};
+
+#define NAND_REG_WRITE(r, v) \
+ writel(v, (volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
+#define NAND_REG_READ(r) \
+ readl((const volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
+
+static struct nand_bd *bd; /* DMA buffer descriptors */
+
+/**
+ * axs101_nand_write_buf - write buffer to chip
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ */
+static uint32_t nand_flag_is_set(uint32_t flag)
+{
+ uint32_t reg = NAND_REG_READ(INT_STATUS);
+
+ if (reg & (1 << NAND_ISR_CMDERROR))
+ return 0;
+
+ if (reg & (1 << flag)) {
+ NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag);
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * axs101_nand_write_buf - write buffer to chip
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ */
+static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
+ int len)
+{
+ struct bounce_buffer bbstate;
+
+ bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ);
+
+ /* Setup buffer descriptor */
+ writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
+ writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
+ writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
+ writel(0, &bd->buffer_ptr1);
+
+ /* Flush modified buffer descriptor */
+ flush_dcache_range((unsigned long)bd,
+ (unsigned long)bd + sizeof(struct nand_bd));
+
+ /* Issue "write" command */
+ NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
+
+ /* Wait for NAND command and DMA to complete */
+ while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+ ;
+ while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE))
+ ;
+
+ bounce_buffer_stop(&bbstate);
+}
+
+/**
+ * axs101_nand_read_buf - read chip data into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store data
+ * @len: number of bytes to read
+ */
+static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ struct bounce_buffer bbstate;
+
+ bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE);
+
+ /* Setup buffer descriptor */
+ writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
+ writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
+ writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
+ writel(0, &bd->buffer_ptr1);
+
+ /* Flush modified buffer descriptor */
+ flush_dcache_range((unsigned long)bd,
+ (unsigned long)bd + sizeof(struct nand_bd));
+
+ /* Issue "read" command */
+ NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));
+
+ /* Wait for NAND command and DMA to complete */
+ while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+ ;
+ while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE))
+ ;
+
+ bounce_buffer_stop(&bbstate);
+}
+
+/**
+ * axs101_nand_read_byte - read one byte from the chip
+ * @mtd: MTD device structure
+ */
+static u_char axs101_nand_read_byte(struct mtd_info *mtd)
+{
+ u8 byte;
+
+ axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
+ return byte;
+}
+
+/**
+ * axs101_nand_read_word - read one word from the chip
+ * @mtd: MTD device structure
+ */
+static u16 axs101_nand_read_word(struct mtd_info *mtd)
+{
+ u16 word;
+
+ axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
+ return word;
+}
+
+/**
+ * axs101_nand_hwcontrol - NAND control functions wrapper.
+ * @mtd: MTD device structure
+ * @cmd: Command
+ */
+static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd,
+ unsigned int ctrl)
+{
+ if (cmd == NAND_CMD_NONE)
+ return;
+
+ cmd = cmd & 0xff;
+
+ switch (ctrl & (NAND_ALE | NAND_CLE)) {
+ /* Address */
+ case NAND_ALE:
+ cmd |= B_CT_ADDRESS;
+ break;
+
+ /* Command */
+ case NAND_CLE:
+ cmd |= B_CT_COMMAND | B_WFR;
+
+ break;
+
+ default:
+ debug("%s: unknown ctrl %#x\n", __func__, ctrl);
+ }
+
+ NAND_REG_WRITE(AC_FIFO, cmd | B_LC);
+ while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+ ;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,
+ sizeof(struct nand_bd));
+
+ /* Set buffer descriptor address in IDMAC */
+ NAND_REG_WRITE(IDMAC_BDADDR, bd);
+
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = axs101_nand_hwcontrol;
+ nand->read_byte = axs101_nand_read_byte;
+ nand->read_word = axs101_nand_read_word;
+ nand->write_buf = axs101_nand_write_buf;
+ nand->read_buf = axs101_nand_read_buf;
+
+ return 0;
+}
diff --git a/board/syteco/jadecpu/Kconfig b/board/syteco/jadecpu/Kconfig
new file mode 100644
index 0000000..6e9392e
--- /dev/null
+++ b/board/syteco/jadecpu/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_JADECPU
+
+config SYS_BOARD
+ default "jadecpu"
+
+config SYS_VENDOR
+ default "syteco"
+
+config SYS_SOC
+ default "mb86r0x"
+
+config SYS_CONFIG_NAME
+ default "jadecpu"
+
+endif
diff --git a/board/syteco/jadecpu/MAINTAINERS b/board/syteco/jadecpu/MAINTAINERS
new file mode 100644
index 0000000..b53e7ca
--- /dev/null
+++ b/board/syteco/jadecpu/MAINTAINERS
@@ -0,0 +1,6 @@
+JADECPU BOARD
+M: Matthias Weisser <weisserm@arcor.de>
+S: Maintained
+F: board/syteco/jadecpu/
+F: include/configs/jadecpu.h
+F: configs/jadecpu_defconfig
diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile
new file mode 100644
index 0000000..7426436
--- /dev/null
+++ b/board/syteco/jadecpu/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += jadecpu.o
+obj-y += lowlevel_init.o
diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c
new file mode 100644
index 0000000..6c60a41
--- /dev/null
+++ b/board/syteco/jadecpu/jadecpu.c
@@ -0,0 +1,160 @@
+/*
+ * (c) 2010 Graf-Syteco, Matthias Weisser
+ * <weisserm@arcor.de>
+ *
+ * (C) Copyright 2007, mycable GmbH
+ * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/mb86r0x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *)
+ MB86R0x_CCNT_BASE;
+
+ /* We select mode 0 for group 2 and mode 1 for group 4 */
+ writel(0x00000010, &ccnt->cmux_md);
+
+ gd->flags = 0;
+ gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
+
+ icache_enable();
+ dcache_enable();
+
+ return 0;
+}
+
+static void setup_display_power(uint32_t pwr_bit, char *pwm_opts,
+ unsigned long pwm_base)
+{
+ struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
+ MB86R0x_GPIO_BASE;
+ struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base;
+ const char *e;
+
+ writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2);
+
+ e = getenv(pwm_opts);
+ if (e != NULL) {
+ const char *s;
+ uint32_t freq, init;
+
+ freq = 0;
+ init = 0;
+
+ s = strchr(e, 'f');
+ if (s != NULL)
+ freq = simple_strtol(s + 2, NULL, 0);
+
+ s = strchr(e, 'i');
+ if (s != NULL)
+ init = simple_strtol(s + 2, NULL, 0);
+
+ if (freq > 0) {
+ writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
+ &pwm->bcr);
+ writel(1002, &pwm->tpr);
+ writel(1, &pwm->pr);
+ writel(init * 10 + 1, &pwm->dr);
+ writel(1, &pwm->cr);
+ writel(1, &pwm->sr);
+ }
+ }
+}
+
+int board_late_init(void)
+{
+ struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
+ MB86R0x_GPIO_BASE;
+ uint32_t in_word;
+
+#ifdef CONFIG_VIDEO_MB86R0xGDC
+ /* Check if we have valid display settings and turn on power if so */
+ /* Display 0 */
+ if (getenv("gs_dsp_0_param") || getenv("videomode"))
+ setup_display_power((1 << 3), "gs_dsp_0_pwm",
+ MB86R0x_PWM0_BASE);
+
+ /* The corresponding GPIO is always an output */
+ writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
+
+ /* Display 1 */
+ if (getenv("gs_dsp_1_param") || getenv("videomode1"))
+ setup_display_power((1 << 4), "gs_dsp_1_pwm",
+ MB86R0x_PWM1_BASE);
+
+ /* The corresponding GPIO is always an output */
+ writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2);
+#endif /* CONFIG_VIDEO_MB86R0xGDC */
+
+ /* 5V enable */
+ writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1);
+ writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1);
+
+ /* We have special boot options if told by GPIOs */
+ in_word = readl(&gpio->gpdr1);
+
+ if ((in_word & 0xC0) == 0xC0) {
+ setenv("stdin", "serial");
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ setenv("preboot", "run gs_slow_boot");
+ } else if ((in_word & 0xC0) != 0) {
+ setenv("stdout", "vga");
+ setenv("preboot", "run gs_slow_boot");
+ } else {
+ setenv("stdin", "serial");
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ if (getenv("gs_devel")) {
+ setenv("preboot", "run gs_slow_boot");
+ } else {
+ setenv("preboot", "run gs_fast_boot");
+ }
+ }
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+/*
+ * DRAM configuration
+ */
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+ PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S
new file mode 100644
index 0000000..9568cec
--- /dev/null
+++ b/board/syteco/jadecpu/lowlevel_init.S
@@ -0,0 +1,249 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2007, mycable GmbH
+ * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <asm/arch/mb86r0x.h>
+#include <generated/asm-offsets.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+/*
+ * Initialize Clock Reset Generator (CRG)
+ */
+
+ ldr r0, =MB86R0x_CRG_BASE
+
+ /* Not change the initial value that is set by external pin.*/
+WAIT_PLL:
+ ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */
+ tst r2, #MB86R0x_CRG_CRPR_PLLRDY
+ beq WAIT_PLL
+
+ /* Set clock gate control */
+ ldr r1, =CONFIG_SYS_CRG_CRHA_INIT
+ str r1, [r0, #CRG_CRHA]
+ ldr r1, =CONFIG_SYS_CRG_CRPA_INIT
+ str r1, [r0, #CRG_CRPA]
+ ldr r1, =CONFIG_SYS_CRG_CRPB_INIT
+ str r1, [r0, #CRG_CRPB]
+ ldr r1, =CONFIG_SYS_CRG_CRHB_INIT
+ str r1, [r0, #CRG_CRHB]
+ ldr r1, =CONFIG_SYS_CRG_CRAM_INIT
+ str r1, [r0, #CRG_CRAM]
+
+/*
+ * Initialize External Bus Interface
+ */
+ ldr r0, =MB86R0x_MEMC_BASE
+
+ ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT
+ str r1, [r0, #MEMC_MCFMODE0]
+ ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT
+ str r1, [r0, #MEMC_MCFMODE2]
+ ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT
+ str r1, [r0, #MEMC_MCFMODE4]
+
+ ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT
+ str r1, [r0, #MEMC_MCFTIM0]
+ ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT
+ str r1, [r0, #MEMC_MCFTIM2]
+ ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT
+ str r1, [r0, #MEMC_MCFTIM4]
+
+ ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT
+ str r1, [r0, #MEMC_MCFAREA0]
+ ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT
+ str r1, [r0, #MEMC_MCFAREA2]
+ ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT
+ str r1, [r0, #MEMC_MCFAREA4]
+
+/*
+ * Initialize DDR2 Controller
+ */
+
+ /* Wait for PLL LOCK up time or more */
+ wait_timer 20
+
+ /*
+ * (2) Initialize DDRIF
+ */
+ ldr r0, =MB86R0x_DDR2_BASE
+ ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT
+ strh r1, [r0, #DDR2_DRIMS]
+
+ /*
+ * (3) Wait for 20MCKPs(120nsec) or more
+ */
+ wait_timer 20
+
+ /*
+ * (4) IRESET/IUSRRST release
+ */
+ ldr r0, =MB86R0x_CCNT_BASE
+ ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1
+ str r1, [r0, #CCNT_CDCRC]
+
+ /*
+ * (5) Wait for 20MCKPs(120nsec) or more
+ */
+ wait_timer 20
+
+ /*
+ * (6) IDLLRST release
+ */
+ ldr r0, =MB86R0x_CCNT_BASE
+ ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2
+ str r1, [r0, #CCNT_CDCRC]
+
+ /*
+ * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
+ */
+ wait_timer 33536
+
+ /*
+ * (9) MCKE ON
+ */
+ ldr r0, =MB86R0x_DDR2_BASE
+ ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT
+ strh r1, [r0, #DDR2_DRCA]
+ ldr r1, =MB86R0x_DDR2_DRCI_INIT
+ strh r1, [r0, #DDR2_DRIC]
+
+ /*
+ * (10) Initialize SDRAM
+ */
+
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ wait_timer 67 /* 400ns wait */
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ wait_timer 200
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ wait_timer 18 /* 105ns wait */
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ wait_timer 200 /* MRS to OCD: 200clock */
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10
+ strh r1, [r0, #DDR2_DRIC1]
+ ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10
+ strh r1, [r0, #DDR2_DRIC2]
+ ldr r1, =MB86R0x_DDR2_DRCI_CMD
+ strh r1, [r0, #DDR2_DRIC]
+
+ ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT
+ strh r1, [r0, #DDR2_DRCM]
+
+ ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT
+ strh r1, [r0, #DDR2_DRCST1]
+
+ ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT
+ strh r1, [r0, #DDR2_DRCST2]
+
+ ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT
+ strh r1, [r0, #DDR2_DRCR]
+
+ ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT
+ strh r1, [r0, #DDR2_DRCF]
+
+ ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT
+ strh r1, [r0, #DDR2_DRASR]
+
+ /*
+ * (11) ODT setting
+ */
+ ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT
+ strh r1, [r0, #DDR2_DROBS]
+ ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT
+ strh r1, [r0, #DDR2_DROABA]
+ ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT
+ strh r1, [r0, #DDR2_DRIBSODT1]
+
+ /*
+ * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode
+ */
+ ldr r1, =CONFIG_SYS_DDR2_DROS_INIT
+ strh r1, [r0, #DDR2_DROS]
+ ldr r1, =MB86R0x_DDR2_DRCI_NORMAL
+ strh r1, [r0, #DDR2_DRIC]
+
+ mov pc, lr
diff --git a/board/syteco/zmx25/Kconfig b/board/syteco/zmx25/Kconfig
new file mode 100644
index 0000000..59a415d
--- /dev/null
+++ b/board/syteco/zmx25/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ZMX25
+
+config SYS_BOARD
+ default "zmx25"
+
+config SYS_VENDOR
+ default "syteco"
+
+config SYS_SOC
+ default "mx25"
+
+config SYS_CONFIG_NAME
+ default "zmx25"
+
+endif
diff --git a/board/syteco/zmx25/MAINTAINERS b/board/syteco/zmx25/MAINTAINERS
new file mode 100644
index 0000000..90f9fab
--- /dev/null
+++ b/board/syteco/zmx25/MAINTAINERS
@@ -0,0 +1,6 @@
+ZMX25 BOARD
+M: Matthias Weisser <weisserm@arcor.de>
+S: Maintained
+F: board/syteco/zmx25/
+F: include/configs/zmx25.h
+F: configs/zmx25_defconfig
diff --git a/board/syteco/zmx25/Makefile b/board/syteco/zmx25/Makefile
new file mode 100644
index 0000000..d5edb48
--- /dev/null
+++ b/board/syteco/zmx25/Makefile
@@ -0,0 +1,9 @@
+#
+# (c) 2010 Graf-Syteco, Matthias Weisser
+# <weisserm@arcor.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += zmx25.o
+obj-y += lowlevel_init.o
diff --git a/board/syteco/zmx25/lowlevel_init.S b/board/syteco/zmx25/lowlevel_init.S
new file mode 100644
index 0000000..5eccf09
--- /dev/null
+++ b/board/syteco/zmx25/lowlevel_init.S
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2011
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on U-Boot and RedBoot sources for several different i.mx
+ * platforms.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/macro.h>
+#include <asm/arch/macro.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * clocks
+ */
+.macro init_clocks
+
+ /* disable clock output */
+ write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
+ write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
+
+ /*
+ * enable all implemented clocks in all three
+ * clock control registers
+ */
+ write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
+ write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
+ write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
+
+ /* Devide NAND clock by 32 */
+ write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
+.endm
+
+/*
+ * sdram controller init
+ */
+.macro init_lpddr
+ ldr r0, =IMX_ESDRAMC_BASE
+ ldr r2, =IMX_SDRAM_BANK0_BASE
+
+ /*
+ * reset SDRAM controller
+ * then wait for initialization to complete
+ */
+ ldr r1, =(1 << 1) | (1 << 2)
+ str r1, [r0, #ESDRAMC_ESDMISC]
+1: ldr r3, [r0, #ESDRAMC_ESDMISC]
+ tst r3, #(1 << 31)
+ beq 1b
+ ldr r1, =(1 << 2)
+ str r1, [r0, #ESDRAMC_ESDMISC]
+
+ ldr r1, =0x002a7420
+ str r1, [r0, #ESDRAMC_ESDCFG0]
+
+ /* control | precharge */
+ ldr r1, =0x92216008
+ str r1, [r0, #ESDRAMC_ESDCTL0]
+ /* dram command encoded in address */
+ str r1, [r2, #0x400]
+
+ /* auto refresh */
+ ldr r1, =0xa2216008
+ str r1, [r0, #ESDRAMC_ESDCTL0]
+ /* read dram twice to auto refresh */
+ ldr r3, [r2]
+ ldr r3, [r2]
+
+ /* control | load mode */
+ ldr r1, =0xb2216008
+ str r1, [r0, #ESDRAMC_ESDCTL0]
+
+ /* mode register of lpddram */
+ strb r1, [r2, #0x33]
+
+ /* extended mode register of lpddrram */
+ ldr r2, =0x81000000
+ strb r1, [r2]
+
+ /* control | normal */
+ ldr r1, =0x82216008
+ str r1, [r0, #ESDRAMC_ESDCTL0]
+.endm
+
+.globl lowlevel_init
+lowlevel_init:
+ init_aips
+ init_max
+ init_clocks
+ init_lpddr
+ mov pc, lr
diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c
new file mode 100644
index 0000000..bdbf02a
--- /dev/null
+++ b/board/syteco/zmx25/zmx25.c
@@ -0,0 +1,174 @@
+/*
+ * (c) 2011 Graf-Syteco, Matthias Weisser
+ * <weisserm@arcor.de>
+ *
+ * Based on tx25.c:
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Based on imx27lite.c:
+ * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ * And:
+ * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx25.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init()
+{
+ static const iomux_v3_cfg_t sdhc1_pads[] = {
+ NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
+ };
+
+ static const iomux_v3_cfg_t dig_out_pads[] = {
+ MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */
+ MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */
+ NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */
+ NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */
+ };
+
+ static const iomux_v3_cfg_t led_pads[] = {
+ MX25_PAD_CSI_D9__GPIO_4_21,
+ MX25_PAD_CSI_D4__GPIO_1_29,
+ };
+
+ static const iomux_v3_cfg_t can_pads[] = {
+ NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL),
+ };
+
+ static const iomux_v3_cfg_t i2c3_pads[] = {
+ MX25_PAD_CSPI1_SS1__I2C3_DAT,
+ MX25_PAD_GPIO_E__I2C3_CLK,
+ };
+
+ icache_enable();
+
+ /* Setup of core voltage selection pin to run at 1.4V */
+ imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */
+ gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
+
+ /* Setup of SD card pins*/
+ imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
+
+ /* Setup of digital output for USB power and OC */
+ imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */
+ gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
+
+ imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */
+ gpio_direction_input(IMX_GPIO_NR(1, 18));
+
+ /* Setup of digital output control pins */
+ imx_iomux_v3_setup_multiple_pads(dig_out_pads,
+ ARRAY_SIZE(dig_out_pads));
+
+ /* Switch both output drivers off */
+ gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
+ gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
+
+ /* Setup of key input pin */
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0));
+ gpio_direction_input(IMX_GPIO_NR(2, 29));
+
+ /* Setup of status LED outputs */
+ imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
+
+ /* Switch both LEDs off */
+ gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
+ gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
+
+ /* Setup of CAN1 and CAN2 signals */
+ imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads));
+
+ /* Setup of I2C3 signals */
+ imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
+
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ const char *e;
+
+#ifdef CONFIG_FEC_MXC
+/*
+ * FIXME: need to revisit this
+ * The original code enabled PUE and 100-k pull-down without PKE, so the right
+ * value here is likely:
+ * 0 for no pull
+ * or:
+ * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
+ */
+#define FEC_OUT_PAD_CTRL 0
+
+ static const iomux_v3_cfg_t fec_pads[] = {
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+ NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
+ NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
+ MX25_PAD_FEC_MDIO__FEC_MDIO,
+ MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+ NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
+
+ MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */
+ MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+
+ /* assert PHY reset (low) */
+ gpio_direction_output(IMX_GPIO_NR(3, 16), 0);
+
+ udelay(5000);
+
+ /* deassert PHY reset */
+ gpio_set_value(IMX_GPIO_NR(3, 16), 1);
+
+ udelay(5000);
+#endif
+
+ e = getenv("gs_base_board");
+ if (e != NULL) {
+ if (strcmp(e, "G283") == 0) {
+ int key = gpio_get_value(IMX_GPIO_NR(2, 29));
+
+ if (key) {
+ /* Switch on both LEDs to inidcate boot mode */
+ gpio_set_value(IMX_GPIO_NR(1, 29), 0);
+ gpio_set_value(IMX_GPIO_NR(4, 21), 0);
+
+ setenv("preboot", "run gs_slow_boot");
+ } else
+ setenv("preboot", "run gs_fast_boot");
+ }
+ }
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
+ PHYS_SDRAM_SIZE);
+ return 0;
+}
diff --git a/board/t3corp/Kconfig b/board/t3corp/Kconfig
new file mode 100644
index 0000000..82ed4c9
--- /dev/null
+++ b/board/t3corp/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_T3CORP
+
+config SYS_BOARD
+ default "t3corp"
+
+config SYS_CONFIG_NAME
+ default "t3corp"
+
+endif
diff --git a/board/t3corp/MAINTAINERS b/board/t3corp/MAINTAINERS
new file mode 100644
index 0000000..eaf28c4
--- /dev/null
+++ b/board/t3corp/MAINTAINERS
@@ -0,0 +1,6 @@
+T3CORP BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/t3corp/
+F: include/configs/t3corp.h
+F: configs/t3corp_defconfig
diff --git a/board/t3corp/Makefile b/board/t3corp/Makefile
new file mode 100644
index 0000000..928d895
--- /dev/null
+++ b/board/t3corp/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2010
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := t3corp.o
+obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
+extra-y += init.o
diff --git a/board/t3corp/chip_config.c b/board/t3corp/chip_config.c
new file mode 100644
index 0000000..3a6c514
--- /dev/null
+++ b/board/t3corp/chip_config.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx_config.h>
+
+struct ppc4xx_config ppc4xx_config_val[] = {
+ {
+ "600-67", "CPU: 600 PLB: 200 OPB: 67 EBC: 67",
+ {
+ 0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "667", "CPU: 667 PLB: 166 OPB: 83 EBC: 83",
+ {
+ 0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0,
+ 0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1000", "CPU:1000 PLB: 200 OPB: 100 EBC: 100",
+ {
+ 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "1066", "CPU:1066 PLB: 266 OPB: 88 EBC: 88",
+ {
+ 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+};
+
+int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/t3corp/config.mk b/board/t3corp/config.mk
new file mode 100644
index 0000000..f7ac755
--- /dev/null
+++ b/board/t3corp/config.mk
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2010
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/t3corp/init.S b/board/t3corp/init.S
new file mode 100644
index 0000000..7ae9c43
--- /dev/null
+++ b/board/t3corp/init.S
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ *
+ */
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
+ * use the speed up boot process. It is patched after relocation to
+ * enable SA_I
+ */
+ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M,
+ CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the DDR(2) detection
+ * routine.
+ */
+
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0,
+ AC_RWX | SA_G)
+#endif
+
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xc,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xc,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xd,
+ AC_RW | SA_IG)
+
+ tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xd,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xd,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xd,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xd,
+ AC_RW | SA_IG)
+
+ /* PCIe UTL register */
+ tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
+
+ /* TLB-entry for FPGA(s) */
+ tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
+ CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
+ AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
+ AC_RW | SA_IG)
+
+ /* TLB-entry for OCM */
+ tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
+ AC_RWX | SA_I)
+
+ /* TLB-entry for Local Configuration registers => peripherals */
+ tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M,
+ CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
+
+ tlbtab_end
diff --git a/board/t3corp/t3corp.c b/board/t3corp/t3corp.c
new file mode 100644
index 0000000..586c6f9
--- /dev/null
+++ b/board/t3corp/t3corp.c
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc440.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <mtd/cfi_flash.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/4xx_pcie.h>
+#include <asm/ppc4xx-gpio.h>
+
+int board_early_init_f(void)
+{
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0x7fffffff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC3SR, 0xffffffff); /* clear all */
+ mtdcr(UIC3ER, 0x00000000); /* disable all */
+ mtdcr(UIC3CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC3SR, 0xffffffff); /* clear all */
+
+ /*
+ * Configure PFC (Pin Function Control) registers
+ * enable GPIO 49-63
+ * UART0: 4 pins
+ */
+ mtsdr(SDR0_PFC0, 0x00007fff);
+ mtsdr(SDR0_PFC1, 0x00040000);
+
+ /* Enable PCI host functionality in SDR0_PCI0 */
+ mtsdr(SDR0_PCI0, 0xe0000000);
+
+ mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
+
+ /* Setup PLB4-AHB bridge based on the system address map */
+ mtdcr(AHB_TOP, 0x8000004B);
+ mtdcr(AHB_BOT, 0x8000004B);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ printf("Board: T3CORP");
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ /*
+ * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
+ * boot EBC mapping only supports a maximum of 16MBytes
+ * (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the flash has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfn00.0000 -> 4.cn00.0000
+ */
+
+ /* Remap the NOR flash to 0xcn00.0000 ... 0xcfff.ffff */
+ mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | EBC_BXCR_BS_64MB |
+ EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+ /* Remove TLB entry of boot EBC mapping */
+ remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
+
+ /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
+ program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
+
+ /*
+ * Now accessing of the whole 64Mbytes of NOR flash at virtual address
+ * 0xfc00.0000 is possible
+ */
+
+ /*
+ * Clear potential errors resulting from auto-calibration.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u32 sdr0_srst1 = 0;
+ u32 eth_cfg;
+
+ /*
+ * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
+ * This is board specific, so let's do it here.
+ */
+ mfsdr(SDR0_ETH_CFG, eth_cfg);
+ /* disable SGMII mode */
+ eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
+ SDR0_ETH_CFG_SGMII1_ENABLE |
+ SDR0_ETH_CFG_SGMII0_ENABLE);
+ /* Set the for 2 RGMII mode */
+ /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
+ eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
+ eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
+ mtsdr(SDR0_ETH_CFG, eth_cfg);
+
+ /*
+ * The AHB Bridge core is held in reset after power-on or reset
+ * so enable it now
+ */
+ mfsdr(SDR0_SRST1, sdr0_srst1);
+ sdr0_srst1 &= ~SDR0_SRST1_AHB;
+ mtsdr(SDR0_SRST1, sdr0_srst1);
+
+ return 0;
+}
+
+int board_pcie_last(void)
+{
+ /*
+ * Only PCIe0 for now, PCIe1 hangs on this board
+ */
+ return 0;
+}
+
+/*
+ * Board specific WRDTR and CLKTR values used by the auto-
+ * calibration code (4xx_ibm_ddr2_autocalib.c).
+ */
+static struct sdram_timing board_scan_options[] = {
+ {1, 2},
+ {-1, -1}
+};
+
+struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val)
+{
+ return board_scan_options;
+}
+
+/*
+ * Accessor functions replacing the "weak" functions in
+ * drivers/mtd/cfi_flash.c
+ *
+ * The NOR flash devices "behind" the FPGA's (Xilinx DS617)
+ * can only be read correctly in 16bit mode. We need to emulate
+ * 8bit and 32bit reads here in the board specific code.
+ */
+u8 flash_read8(void *addr)
+{
+ u16 val = __raw_readw((void *)((u32)addr & ~1));
+
+ if ((u32)addr & 1)
+ return val;
+
+ return val >> 8;
+}
+
+u32 flash_read32(void *addr)
+{
+ return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2));
+}
+
+void flash_cmd_reset(flash_info_t *info)
+{
+ /*
+ * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
+ * needs the Spansion type reset commands. The other flash chip
+ * is located behind a FPGA (Xilinx DS617) and needs the Intel type
+ * reset command.
+ */
+ if (info->start[0] == CONFIG_SYS_FLASH_BASE)
+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+ else
+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+}
diff --git a/board/taskit/stamp9g20/Kconfig b/board/taskit/stamp9g20/Kconfig
new file mode 100644
index 0000000..3139f9a
--- /dev/null
+++ b/board/taskit/stamp9g20/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_STAMP9G20
+
+config SYS_BOARD
+ default "stamp9g20"
+
+config SYS_VENDOR
+ default "taskit"
+
+config SYS_SOC
+ default "at91"
+
+config SYS_CONFIG_NAME
+ default "stamp9g20"
+
+endif
diff --git a/board/taskit/stamp9g20/MAINTAINERS b/board/taskit/stamp9g20/MAINTAINERS
new file mode 100644
index 0000000..a91c196
--- /dev/null
+++ b/board/taskit/stamp9g20/MAINTAINERS
@@ -0,0 +1,7 @@
+STAMP9G20 BOARD
+M: Markus Hubig <mhubig@imko.de>
+S: Maintained
+F: board/taskit/stamp9g20/
+F: include/configs/stamp9g20.h
+F: configs/portuxg20_defconfig
+F: configs/stamp9g20_defconfig
diff --git a/board/taskit/stamp9g20/Makefile b/board/taskit/stamp9g20/Makefile
new file mode 100644
index 0000000..d015e0f
--- /dev/null
+++ b/board/taskit/stamp9g20/Makefile
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2012
+# Markus Hubig <mhubig@imko.de>
+# IMKO GmbH <www.imko.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += stamp9g20.o
+obj-y += led.o
diff --git a/board/taskit/stamp9g20/led.c b/board/taskit/stamp9g20/led.c
new file mode 100644
index 0000000..c583125
--- /dev/null
+++ b/board/taskit/stamp9g20/led.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ * (C) Copyright 2009
+ * Eric Benard <eric@eukrea.com>
+ *
+ * (C) Copyright 2012
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pmc.h>
+#include <status_led.h>
+
+static unsigned int saved_state[3] = {STATUS_LED_OFF,
+ STATUS_LED_OFF, STATUS_LED_OFF};
+
+void coloured_LED_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable the clock */
+ writel(ATMEL_ID_PIOC, &pmc->pcer);
+
+ at91_set_gpio_output(CONFIG_RED_LED, 1);
+ at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+ at91_set_gpio_value(CONFIG_RED_LED, 0);
+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+ at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
+}
+
+void red_led_on(void)
+{
+ at91_set_gpio_value(CONFIG_RED_LED, 1);
+ saved_state[STATUS_LED_RED] = STATUS_LED_ON;
+}
+
+void red_led_off(void)
+{
+ at91_set_gpio_value(CONFIG_RED_LED, 0);
+ saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
+}
+
+void green_led_on(void)
+{
+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+ saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
+}
+
+void green_led_off(void)
+{
+ at91_set_gpio_value(CONFIG_GREEN_LED, 0);
+ saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
+}
+
+void yellow_led_on(void)
+{
+ at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+ saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
+}
+
+void yellow_led_off(void)
+{
+ at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
+ saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
+}
+
+void __led_init(led_id_t mask, int state)
+{
+ __led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+ if (STATUS_LED_RED == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
+ red_led_off();
+ else
+ red_led_on();
+
+ } else if (STATUS_LED_GREEN == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
+ green_led_off();
+ else
+ green_led_on();
+
+ } else if (STATUS_LED_YELLOW == mask) {
+ if (STATUS_LED_ON == saved_state[STATUS_LED_YELLOW])
+ yellow_led_off();
+ else
+ yellow_led_on();
+ }
+}
+
+void __led_set(led_id_t mask, int state)
+{
+ if (STATUS_LED_RED == mask) {
+ if (STATUS_LED_ON == state)
+ red_led_on();
+ else
+ red_led_off();
+
+ } else if (STATUS_LED_GREEN == mask) {
+ if (STATUS_LED_ON == state)
+ green_led_on();
+ else
+ green_led_off();
+
+ } else if (STATUS_LED_YELLOW == mask) {
+ if (STATUS_LED_ON == state)
+ yellow_led_on();
+ else
+ yellow_led_off();
+ }
+}
diff --git a/board/taskit/stamp9g20/stamp9g20.c b/board/taskit/stamp9g20/stamp9g20.c
new file mode 100644
index 0000000..27cdf77
--- /dev/null
+++ b/board/taskit/stamp9g20/stamp9g20.c
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Achim Ehrlich <aehrlich@taskit.de>
+ * taskit GmbH <www.taskit.de>
+ *
+ * (C) Copyright 2012-
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <watchdog.h>
+
+#ifdef CONFIG_MACB
+# include <net.h>
+# include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void stamp9G20_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Assign CS3 to NAND/SmartMedia Interface */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
+ AT91_SMC_MODE_DBW_8 |
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+
+#ifdef CONFIG_MACB
+static void stamp9G20_macb_hw_init(void)
+{
+ struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+ /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
+ at91_set_gpio_output(AT91_PIN_PA26, 0);
+
+ /*
+ * Disable pull-up on:
+ * RXDV (PA17) => PHY normal mode (not Test mode)
+ * ERX0 (PA14) => PHY ADDR0
+ * ERX1 (PA15) => PHY ADDR1
+ * ERX2 (PA25) => PHY ADDR2
+ * ERX3 (PA26) => PHY ADDR3
+ * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
+ *
+ * PHY has internal pull-down
+ */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA18) |
+ pin_to_mask(AT91_PIN_PA28),
+ &pioa->pudr);
+
+ at91_phy_reset();
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PA14) |
+ pin_to_mask(AT91_PIN_PA15) |
+ pin_to_mask(AT91_PIN_PA17) |
+ pin_to_mask(AT91_PIN_PA18) |
+ pin_to_mask(AT91_PIN_PA28),
+ &pioa->puer);
+
+ /* Initialize EMAC=MACB hardware */
+ at91_macb_hw_init();
+}
+#endif /* CONFIG_MACB */
+
+int board_early_init_f(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ /* Enable clocks for all PIOs */
+ writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+ (1 << ATMEL_ID_PIOC), &pmc->pcer);
+
+ return 0;
+}
+
+int board_postclk_init(void)
+{
+ /*
+ * Initialize the serial interface here, because be need a running
+ * timer to set PC9 to high and wait for some time to enable the
+ * level converter of the RS232 interface on the PortuxG20 board.
+ */
+
+#ifdef CONFIG_PORTUXG20
+ at91_set_gpio_output(AT91_PIN_PC9, 1);
+ mdelay(1);
+#endif
+ at91_seriald_hw_init();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ stamp9G20_nand_hw_init();
+#ifdef CONFIG_MACB
+ stamp9G20_macb_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size(
+ (void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+#ifdef CONFIG_MACB
+int board_eth_init(bd_t *bis)
+{
+ return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
+}
+#endif /* CONFIG_MACB */
diff --git a/board/tbs/tbs2910/Kconfig b/board/tbs/tbs2910/Kconfig
new file mode 100644
index 0000000..84b243e
--- /dev/null
+++ b/board/tbs/tbs2910/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TBS2910
+
+config SYS_BOARD
+ default "tbs2910"
+
+config SYS_VENDOR
+ default "tbs"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "tbs2910"
+
+endif
diff --git a/board/tbs/tbs2910/MAINTAINERS b/board/tbs/tbs2910/MAINTAINERS
new file mode 100644
index 0000000..bf17655
--- /dev/null
+++ b/board/tbs/tbs2910/MAINTAINERS
@@ -0,0 +1,6 @@
+TBS2910 BOARD
+M: Soeren Moch <smoch@web.de>
+S: Maintained
+F: board/tbs/tbs2910/
+F: configs/tbs2910_defconfig
+F: include/configs/tbs2910.h
diff --git a/board/tbs/tbs2910/Makefile b/board/tbs/tbs2910/Makefile
new file mode 100644
index 0000000..9d9eb87
--- /dev/null
+++ b/board/tbs/tbs2910/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014 Soeren Moch <smoch@web.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := tbs2910.o
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
new file mode 100644
index 0000000..dfa430e
--- /dev/null
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -0,0 +1,397 @@
+/*
+ * Copyright (C) 2014 Soeren Moch <smoch@web.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sata.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_SRE_SLOW)
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#ifdef CONFIG_SYS_I2C
+/* I2C1, SGTL5000 */
+static struct i2c_pads_info i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+/* I2C2 HDMI */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+/* I2C3, CON11, DS1307, PCIe_SMB */
+static struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+#endif /* CONFIG_SYS_I2C */
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* AR8035 PHY Reset */
+ MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pcie_pads[] = {
+ /* W_DISABLE# */
+ MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* PERST# */
+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int dram_init(void)
+{
+ gd->ram_size = 2048ul * 1024 * 1024;
+ return 0;
+}
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* Reset AR8035 PHY */
+ gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
+ udelay(500);
+ gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+}
+
+static void setup_pcie(void)
+{
+ imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC2_BASE_ADDR},
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = 1; /* eMMC/uSDHC4 is always present */
+ break;
+ }
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ /*
+ * (U-boot device node) (Physical Port)
+ * mmc0 SD2
+ * mmc1 SD3
+ * mmc2 eMMC
+ */
+ int i, ret;
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return -EINVAL;
+ }
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+ return 0;
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+#ifdef CONFIG_VIDEO_IPUV3
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ /* 1024x768@60Hz (VESA)*/
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15384,
+ .left_margin = 160,
+ .right_margin = 24,
+ .upper_margin = 29,
+ .lower_margin = 3,
+ .hsync_len = 136,
+ .vsync_len = 6,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+ s32 timeout = 100000;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
+ reg = readl(&ccm->analog_pll_video);
+ reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
+ writel(reg, &ccm->analog_pll_video);
+
+ reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
+ reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
+ writel(reg, &ccm->analog_pll_video);
+
+ writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+ writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+ reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
+ writel(reg, &ccm->analog_pll_video);
+
+ while (timeout--)
+ if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+ break;
+ if (timeout < 0)
+ printf("Warning: video pll lock timeout!\n");
+
+ reg = readl(&ccm->analog_pll_video);
+ reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
+ reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
+ writel(reg, &ccm->analog_pll_video);
+
+ /* select video pll for ldb_di0_clk */
+ reg = readl(&ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
+ writel(reg, &ccm->cs2cdr);
+
+ /* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */
+ reg = readl(&ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, &ccm->cscmr2);
+
+ /* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */
+ reg = readl(&ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &ccm->chsccdr);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+ setup_pcie();
+ return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ /* 8 bit bus width */
+ {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_VIDEO_IPUV3
+ setup_display();
+#endif
+#ifdef CONFIG_SYS_I2C
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+#endif
+#ifdef CONFIG_DWC_AHSATA
+ setup_sata();
+#endif
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: TBS2910 Matrix ARM mini PC\n");
+ return 0;
+}
diff --git a/board/tcm-bf518/Kconfig b/board/tcm-bf518/Kconfig
new file mode 100644
index 0000000..558c2fe
--- /dev/null
+++ b/board/tcm-bf518/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_TCM_BF518
+
+config SYS_BOARD
+ default "tcm-bf518"
+
+config SYS_CONFIG_NAME
+ default "tcm-bf518"
+
+endif
diff --git a/board/tcm-bf518/MAINTAINERS b/board/tcm-bf518/MAINTAINERS
new file mode 100644
index 0000000..1690122
--- /dev/null
+++ b/board/tcm-bf518/MAINTAINERS
@@ -0,0 +1,6 @@
+TCM-BF518 BOARD
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+S: Orphan (since 2014-03)
+F: board/tcm-bf518/
+F: include/configs/tcm-bf518.h
+F: configs/tcm-bf518_defconfig
diff --git a/board/tcm-bf518/Makefile b/board/tcm-bf518/Makefile
new file mode 100644
index 0000000..2e029f5
--- /dev/null
+++ b/board/tcm-bf518/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := tcm-bf518.o
diff --git a/board/tcm-bf518/tcm-bf518.c b/board/tcm-bf518/tcm-bf518.c
new file mode 100644
index 0000000..5d25fcd
--- /dev/null
+++ b/board/tcm-bf518/tcm-bf518.c
@@ -0,0 +1,77 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/otp.h>
+#include <asm/sdh.h>
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix TCM-BF518 board\n");
+ printf(" Support: http://www.bluetechnix.com/\n");
+ printf(" http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+#if defined(CONFIG_BFIN_MAC)
+static void board_init_enetaddr(uchar *mac_addr)
+{
+ bool valid_mac = false;
+
+#if 0
+ /* the MAC is stored in OTP memory page 0xDF */
+ uint32_t ret;
+ uint64_t otp_mac;
+
+ ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
+ if (!(ret & OTP_MASTER_ERROR)) {
+ uchar *otp_mac_p = (uchar *)&otp_mac;
+
+ for (ret = 0; ret < 6; ++ret)
+ mac_addr[ret] = otp_mac_p[5 - ret];
+
+ if (is_valid_ether_addr(mac_addr))
+ valid_mac = true;
+ }
+#endif
+
+ if (!valid_mac) {
+ puts("Warning: Generating 'random' MAC address\n");
+ eth_random_addr(mac_addr);
+ }
+
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+ uchar enetaddr[6];
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ board_init_enetaddr(enetaddr);
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_BFIN_SDH
+int board_mmc_init(bd_t *bis)
+{
+ return bfin_mmc_init(bis);
+}
+#endif
diff --git a/board/tcm-bf537/Kconfig b/board/tcm-bf537/Kconfig
new file mode 100644
index 0000000..e0127c6
--- /dev/null
+++ b/board/tcm-bf537/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_TCM_BF537
+
+config SYS_BOARD
+ default "tcm-bf537"
+
+config SYS_CONFIG_NAME
+ default "tcm-bf537"
+
+endif
diff --git a/board/tcm-bf537/MAINTAINERS b/board/tcm-bf537/MAINTAINERS
new file mode 100644
index 0000000..1cd4845
--- /dev/null
+++ b/board/tcm-bf537/MAINTAINERS
@@ -0,0 +1,6 @@
+TCM-BF537 BOARD
+#M: Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
+S: Orphan (since 2014-03)
+F: board/tcm-bf537/
+F: include/configs/tcm-bf537.h
+F: configs/tcm-bf537_defconfig
diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile
new file mode 100644
index 0000000..93a01e4
--- /dev/null
+++ b/board/tcm-bf537/Makefile
@@ -0,0 +1,12 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := tcm-bf537.o gpio_cfi_flash.o
diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk
new file mode 100644
index 0000000..7f9138b
--- /dev/null
+++ b/board/tcm-bf537/config.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/tcm-bf537/gpio_cfi_flash.c b/board/tcm-bf537/gpio_cfi_flash.c
new file mode 100644
index 0000000..c4fef9f
--- /dev/null
+++ b/board/tcm-bf537/gpio_cfi_flash.c
@@ -0,0 +1,3 @@
+#define GPIO_PIN_1 GPIO_PF4
+#define GPIO_PIN_2 GPIO_PF5
+#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c
new file mode 100644
index 0000000..a4f0f71
--- /dev/null
+++ b/board/tcm-bf537/tcm-bf537.c
@@ -0,0 +1,59 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include "../cm-bf537e/gpio_cfi_flash.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: Bluetechnix TCM-BF537 board\n");
+ printf(" Support: http://www.bluetechnix.at/\n");
+ return 0;
+}
+
+static void board_init_enetaddr(char *var)
+{
+ uchar enetaddr[6];
+
+ if (eth_getenv_enetaddr(var, enetaddr))
+ return;
+
+ printf("Warning: %s: generating 'random' MAC address\n", var);
+ eth_random_addr(enetaddr);
+ eth_setenv_enetaddr(var, enetaddr);
+}
+
+#ifndef CONFIG_BFIN_MAC
+# define bfin_EMAC_initialize(x) 1
+#endif
+#ifndef CONFIG_SMC911X
+# define smc911x_initialize(n, x) 1
+#endif
+int board_eth_init(bd_t *bis)
+{
+ /* return ok if at least 1 eth device works */
+ return bfin_EMAC_initialize(bis) &
+ smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+
+int misc_init_r(void)
+{
+ board_init_enetaddr("ethaddr");
+ board_init_enetaddr("eth1addr");
+
+ gpio_cfi_flash_init();
+
+ return 0;
+}
diff --git a/board/technexion/tao3530/Kconfig b/board/technexion/tao3530/Kconfig
new file mode 100644
index 0000000..27bc91f
--- /dev/null
+++ b/board/technexion/tao3530/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TAO3530
+
+config SYS_BOARD
+ default "tao3530"
+
+config SYS_VENDOR
+ default "technexion"
+
+config SYS_CONFIG_NAME
+ default "tao3530"
+
+endif
diff --git a/board/technexion/tao3530/MAINTAINERS b/board/technexion/tao3530/MAINTAINERS
new file mode 100644
index 0000000..ad02b46
--- /dev/null
+++ b/board/technexion/tao3530/MAINTAINERS
@@ -0,0 +1,11 @@
+TAO3530 BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/technexion/tao3530/
+F: include/configs/tao3530.h
+F: configs/omap3_ha_defconfig
+
+TAO3530 BOARD
+M: Tapani Utriainen <linuxfae@technexion.com>
+S: Maintained
+F: configs/tao3530_defconfig
diff --git a/board/technexion/tao3530/Makefile b/board/technexion/tao3530/Makefile
new file mode 100644
index 0000000..2aff383
--- /dev/null
+++ b/board/technexion/tao3530/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := tao3530.o
diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c
new file mode 100644
index 0000000..744ff44
--- /dev/null
+++ b/board/technexion/tao3530/tao3530.c
@@ -0,0 +1,222 @@
+/*
+ * Maintainer :
+ * Tapani Utriainen <linuxfae@technexion.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+
+#include <usb.h>
+#include <asm/ehci-omap.h>
+
+#include "tao3530.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int tao3530_revision(void)
+{
+ int ret = 0;
+
+ /* char *label argument is unused in gpio_request() */
+ ret = gpio_request(65, "");
+ if (ret) {
+ puts("Error: GPIO 65 not available\n");
+ goto out;
+ }
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4));
+
+ ret = gpio_request(1, "");
+ if (ret) {
+ puts("Error: GPIO 1 not available\n");
+ goto out2;
+ }
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4));
+
+ ret = gpio_direction_input(65);
+ if (ret) {
+ puts("Error: GPIO 65 not available for input\n");
+ goto out3;
+ }
+
+ ret = gpio_direction_input(1);
+ if (ret) {
+ puts("Error: GPIO 1 not available for input\n");
+ goto out3;
+ }
+
+ ret = gpio_get_value(65) << 1 | gpio_get_value(1);
+
+out3:
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M0));
+ gpio_free(1);
+out2:
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0));
+ gpio_free(65);
+out:
+
+ return ret;
+}
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
+ /*
+ * Switch baseboard LED to red upon power-on
+ */
+ MUX_OMAP3_HA();
+
+ /* Request a gpio before using it */
+ gpio_request(111, "");
+ /* Sets the gpio as output and its value to 1, switch LED to red */
+ gpio_direction_output(111, 1);
+#endif
+
+ if (tao3530_revision() < 3) {
+ /* 256MB / Bank */
+ timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */
+ timings->ctrla = HYNIX_V_ACTIMA_165;
+ timings->ctrlb = HYNIX_V_ACTIMB_165;
+ } else {
+ /* 128MB / Bank */
+ timings->mcfg = MCFG(128 << 20, 13); /* RAS-width 13 */
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ }
+
+ timings->mr = MICRON_V_MR_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+}
+#endif
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+
+ twl4030_power_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+
+ /* Configure GPIOs to output */
+ /* GPIO23 */
+ writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
+ writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 |
+ GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
+
+ /* Set GPIOs */
+ writel(GPIO10 | GPIO8 | GPIO2 | GPIO1,
+ &gpio6_base->setdataout);
+ writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+ GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
+
+ switch (tao3530_revision()) {
+ case 0:
+ puts("TAO-3530 REV Reserve 1\n");
+ break;
+ case 1:
+ puts("TAO-3530 REV Reserve 2\n");
+ break;
+ case 2:
+ puts("TAO-3530 REV Cx\n");
+ break;
+ case 3:
+ puts("TAO-3530 REV Ax/Bx\n");
+ break;
+ default:
+ puts("Unknown board revision\n");
+ }
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_TAO3530();
+#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
+ MUX_OMAP3_HA();
+#endif
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
+#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
+/* Call usb_stop() before starting the kernel */
+void show_boot_progress(int val)
+{
+ if (val == BOOTSTAGE_ID_RUN_OS)
+ usb_stop();
+}
+
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(int index)
+{
+ return omap_ehci_hcd_stop();
+}
+#endif /* CONFIG_USB_EHCI */
diff --git a/board/technexion/tao3530/tao3530.h b/board/technexion/tao3530/tao3530.h
new file mode 100644
index 0000000..4a94399
--- /dev/null
+++ b/board/technexion/tao3530/tao3530.h
@@ -0,0 +1,371 @@
+/*
+ * (C) Copyright TechNexion 2010
+ * Edward Lin <linuxfae@technexion.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _TAO3530_H_
+#define _TAO3530_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+#if defined(CONFIG_SYS_BOARD_OMAP3_HA)
+ "HEAD acoustics OMAP3-HA",
+#else
+ "OMAP3 TAO-3530 board",
+#endif
+ "NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_TAO3530() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) \
+ /* - CAM_RESET*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
+ /*Expansion card */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) \
+ /* MMC2 WLAN */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | EN | M4)) \
+ MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \
+ /*LocalBus LAN Reset*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) \
+ /*LocalBus LAN IRQ*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) \
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) \
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) \
+ /* USB EHCI (port 2) */\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) \
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) \
+ /* - VIO_1V8*/\
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M1)) \
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M1)) \
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M1)) \
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M1)) \
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M1)) \
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) \
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) \
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(ETK_D14_ES2), (IEN|PTU|DIS|M3)) \
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) \
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0))
+
+#define MUX_OMAP3_HA() \
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M4)) /* GPIO_111 */
+
+#endif
diff --git a/board/technexion/twister/Kconfig b/board/technexion/twister/Kconfig
new file mode 100644
index 0000000..4c0ace8
--- /dev/null
+++ b/board/technexion/twister/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TWISTER
+
+config SYS_BOARD
+ default "twister"
+
+config SYS_VENDOR
+ default "technexion"
+
+config SYS_CONFIG_NAME
+ default "twister"
+
+endif
diff --git a/board/technexion/twister/MAINTAINERS b/board/technexion/twister/MAINTAINERS
new file mode 100644
index 0000000..1ce2b37
--- /dev/null
+++ b/board/technexion/twister/MAINTAINERS
@@ -0,0 +1,6 @@
+TWISTER BOARD
+M: Stefano Babic <sbabic@denx.de>
+S: Maintained
+F: board/technexion/twister/
+F: include/configs/twister.h
+F: configs/twister_defconfig
diff --git a/board/technexion/twister/Makefile b/board/technexion/twister/Makefile
new file mode 100644
index 0000000..2a91021
--- /dev/null
+++ b/board/technexion/twister/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+#
+# Based on ti/evm/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := twister.o
diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c
new file mode 100644
index 0000000..a4aed3b
--- /dev/null
+++ b/board/technexion/twister/twister.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2009 TechNexion Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <i2c.h>
+#include <spl.h>
+#include <mmc.h>
+#include <asm/gpio.h>
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/ehci-omap.h>
+#endif
+#include "twister.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timing definitions for Ethernet Controller */
+static const u32 gpmc_smc911[] = {
+ NET_GPMC_CONFIG1,
+ NET_GPMC_CONFIG2,
+ NET_GPMC_CONFIG3,
+ NET_GPMC_CONFIG4,
+ NET_GPMC_CONFIG5,
+ NET_GPMC_CONFIG6,
+};
+
+static const u32 gpmc_XR16L2751[] = {
+ XR16L2751_GPMC_CONFIG1,
+ XR16L2751_GPMC_CONFIG2,
+ XR16L2751_GPMC_CONFIG3,
+ XR16L2751_GPMC_CONFIG4,
+ XR16L2751_GPMC_CONFIG5,
+ XR16L2751_GPMC_CONFIG6,
+};
+
+#ifdef CONFIG_USB_EHCI
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(int index)
+{
+ return omap_ehci_hcd_stop();
+}
+#endif
+
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ /* Chip select 1 and 3 are used for XR16L2751 UART controller */
+ enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[1],
+ XR16L2751_UART1_BASE, GPMC_SIZE_16M);
+
+ enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[3],
+ XR16L2751_UART2_BASE, GPMC_SIZE_16M);
+
+ gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB_PHY1_RESET");
+ gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1);
+
+ return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+int misc_init_r(void)
+{
+ char *eth_addr;
+ struct tam3517_module_info info;
+ int ret;
+
+ dieid_num_r();
+
+ eth_addr = getenv("ethaddr");
+ if (eth_addr)
+ return 0;
+
+ TAM3517_READ_EEPROM(&info, ret);
+ if (!ret)
+ TAM3517_READ_MAC_FROM_EEPROM(&info);
+
+ return 0;
+}
+#endif
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_TWISTER();
+}
+
+int board_eth_init(bd_t *bis)
+{
+ davinci_emac_initialize();
+
+ /* init cs for extern lan */
+ enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
+ CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+ if (smc911x_initialize(0, CONFIG_SMC911X_BASE) <= 0)
+ printf("\nError initializing SMC911x controlleri\n");
+
+ return 0;
+}
+
+#if defined(CONFIG_OMAP_HSMMC) && \
+ !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * Do board specific preperation before SPL
+ * Linux boot
+ */
+void spl_board_prepare_for_linux(void)
+{
+ /* init cs for extern lan */
+ enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
+ CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+}
+int spl_start_uboot(void)
+{
+ int val = 0;
+ if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
+ gpio_direction_input(SPL_OS_BOOT_KEY);
+ val = gpio_get_value(SPL_OS_BOOT_KEY);
+ gpio_free(SPL_OS_BOOT_KEY);
+ }
+ return val;
+}
+#endif
diff --git a/board/technexion/twister/twister.h b/board/technexion/twister/twister.h
new file mode 100644
index 0000000..e286bd4
--- /dev/null
+++ b/board/technexion/twister/twister.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2010 TechNexion Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TAM3517_H_
+#define _TAM3517_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "TAM3517 TWISTER Board",
+ "NAND",
+};
+
+#define XR16L2751_GPMC_CONFIG1 0x00000000
+#define XR16L2751_GPMC_CONFIG2 0x001e1e01
+#define XR16L2751_GPMC_CONFIG3 0x00080300
+#define XR16L2751_GPMC_CONFIG4 0x1c091c09
+#define XR16L2751_GPMC_CONFIG5 0x04181f1f
+#define XR16L2751_GPMC_CONFIG6 0x00000FCF
+
+#define XR16L2751_UART1_BASE 0x21000000
+#define XR16L2751_UART2_BASE 0x23000000
+
+/* GPIO used to select between U-Boot and kernel */
+#define SPL_OS_BOOT_KEY 55
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_TWISTER() \
+ /* SDRC */\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_CKE0), (M0)) \
+ MUX_VAL(CP(SDRC_CKE1), (M0)) \
+ MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
+ /*sdrc_strben_dly0*/\
+ MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
+ /*sdrc_strben_dly1*/\
+ /* GPMC */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M2)) /*PWM9*/\
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
+ /* DSS */\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
+ /* CAMERA */\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
+ /* MMC */\
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
+ /* CardDetect */\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
+ \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
+ /* McBSP */\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) /*GPIO_116*/ \
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
+ \
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
+ \
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_152*/\
+ MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) /*GPIO_155*/\
+ /* UART */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \
+ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) /*GPIO_163*/ \
+ MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) /*GPIO_164*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
+ /* I2C */\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
+ /* McSPI */\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \
+ \
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \
+ /* CCDC */\
+ MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
+ MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
+ /* RMII */\
+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
+ MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
+ MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
+ /* HECC */\
+ MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
+ /* HSUSB */\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
+ /* HDQ */\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
+ /* Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
+ /* - GPIO30 */\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+ /* - VIO_1V8*/\
+ MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
+ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
+ /* JTAG */\
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \
+ MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \
+ /* ETK (ES2 onwards) */\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
+ /* hsusb1_stp */ \
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
+ /* hsusb1_clk */\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
+ /* hsusb1_dir */\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
+ /* hsusb1_nxt */\
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
+ /* Die to Die */\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
+
+#endif
diff --git a/board/teejet/mt_ventoux/Kconfig b/board/teejet/mt_ventoux/Kconfig
new file mode 100644
index 0000000..fd7196a
--- /dev/null
+++ b/board/teejet/mt_ventoux/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MT_VENTOUX
+
+config SYS_BOARD
+ default "mt_ventoux"
+
+config SYS_VENDOR
+ default "teejet"
+
+config SYS_CONFIG_NAME
+ default "mt_ventoux"
+
+endif
diff --git a/board/teejet/mt_ventoux/MAINTAINERS b/board/teejet/mt_ventoux/MAINTAINERS
new file mode 100644
index 0000000..d23464c
--- /dev/null
+++ b/board/teejet/mt_ventoux/MAINTAINERS
@@ -0,0 +1,6 @@
+MT_VENTOUX BOARD
+M: Stefano Babic <sbabic@denx.de>
+S: Maintained
+F: board/teejet/mt_ventoux/
+F: include/configs/mt_ventoux.h
+F: configs/mt_ventoux_defconfig
diff --git a/board/teejet/mt_ventoux/Makefile b/board/teejet/mt_ventoux/Makefile
new file mode 100644
index 0000000..66f56fd
--- /dev/null
+++ b/board/teejet/mt_ventoux/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+#
+# Based on ti/evm/Makefile
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mt_ventoux.o
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c
new file mode 100644
index 0000000..b4a0a72
--- /dev/null
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -0,0 +1,343 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2009 TechNexion Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fpga.h>
+#include <video_fb.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/dss.h>
+#include <asm/arch/clock.h>
+#include <i2c.h>
+#include <spartan3.h>
+#include <asm/gpio.h>
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/ehci-omap.h>
+#endif
+#include "mt_ventoux.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BUZZER 140
+#define SPEAKER 141
+#define USB1_PWR 127
+#define USB2_PWR 149
+
+#ifndef CONFIG_FPGA
+#error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
+#endif
+
+#define FPGA_RESET 62
+#define FPGA_PROG 116
+#define FPGA_CCLK 117
+#define FPGA_DIN 118
+#define FPGA_INIT 119
+#define FPGA_DONE 154
+
+#define LCD_PWR 138
+#define LCD_PON_PIN 139
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+static struct {
+ u32 xres;
+ u32 yres;
+} panel_resolution[] = {
+ { 480, 272 },
+ { 800, 480 }
+};
+
+static struct panel_config lcd_cfg[] = {
+ {
+ .timing_h = PANEL_TIMING_H(40, 5, 2),
+ .timing_v = PANEL_TIMING_V(8, 8, 2),
+ .pol_freq = 0x00003000, /* Pol Freq */
+ .divisor = 0x00010033, /* 9 Mhz Pixel Clock */
+ .panel_type = 0x01, /* TFT */
+ .data_lines = 0x03, /* 24 Bit RGB */
+ .load_mode = 0x02, /* Frame Mode */
+ .panel_color = 0,
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
+ },
+ {
+ .timing_h = PANEL_TIMING_H(20, 192, 4),
+ .timing_v = PANEL_TIMING_V(2, 20, 10),
+ .pol_freq = 0x00004000, /* Pol Freq */
+ .divisor = 0x0001000E, /* 36Mhz Pixel Clock */
+ .panel_type = 0x01, /* TFT */
+ .data_lines = 0x03, /* 24 Bit RGB */
+ .load_mode = 0x02, /* Frame Mode */
+ .panel_color = 0,
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
+ }
+};
+#endif
+
+/* Timing definitions for FPGA */
+static const u32 gpmc_fpga[] = {
+ FPGA_GPMC_CONFIG1,
+ FPGA_GPMC_CONFIG2,
+ FPGA_GPMC_CONFIG3,
+ FPGA_GPMC_CONFIG4,
+ FPGA_GPMC_CONFIG5,
+ FPGA_GPMC_CONFIG6,
+};
+
+#ifdef CONFIG_USB_EHCI
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(int index)
+{
+ return omap_ehci_hcd_stop();
+}
+#endif
+
+
+static inline void fpga_reset(int nassert)
+{
+ gpio_set_value(FPGA_RESET, !nassert);
+}
+
+int fpga_pgm_fn(int nassert, int nflush, int cookie)
+{
+ debug("%s:%d: FPGA PROGRAM ", __func__, __LINE__);
+
+ gpio_set_value(FPGA_PROG, !nassert);
+
+ return nassert;
+}
+
+int fpga_init_fn(int cookie)
+{
+ return !gpio_get_value(FPGA_INIT);
+}
+
+int fpga_done_fn(int cookie)
+{
+ return gpio_get_value(FPGA_DONE);
+}
+
+int fpga_pre_config_fn(int cookie)
+{
+ debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
+
+ /* Setting GPIOs for programming Mode */
+ gpio_request(FPGA_RESET, "FPGA_RESET");
+ gpio_direction_output(FPGA_RESET, 1);
+ gpio_request(FPGA_PROG, "FPGA_PROG");
+ gpio_direction_output(FPGA_PROG, 1);
+ gpio_request(FPGA_CCLK, "FPGA_CCLK");
+ gpio_direction_output(FPGA_CCLK, 1);
+ gpio_request(FPGA_DIN, "FPGA_DIN");
+ gpio_direction_output(FPGA_DIN, 0);
+ gpio_request(FPGA_INIT, "FPGA_INIT");
+ gpio_direction_input(FPGA_INIT);
+ gpio_request(FPGA_DONE, "FPGA_DONE");
+ gpio_direction_input(FPGA_DONE);
+
+ /* Be sure that signal are deasserted */
+ gpio_set_value(FPGA_RESET, 1);
+ gpio_set_value(FPGA_PROG, 1);
+
+ return 0;
+}
+
+int fpga_post_config_fn(int cookie)
+{
+ debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
+
+ fpga_reset(true);
+ udelay(100);
+ fpga_reset(false);
+
+ return 0;
+}
+
+/* Write program to the FPGA */
+int fpga_wr_fn(int nassert_write, int flush, int cookie)
+{
+ gpio_set_value(FPGA_DIN, nassert_write);
+
+ return nassert_write;
+}
+
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ gpio_set_value(FPGA_CCLK, assert_clk);
+
+ return assert_clk;
+}
+
+xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
+ fpga_pre_config_fn,
+ fpga_pgm_fn,
+ fpga_clk_fn,
+ fpga_init_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_post_config_fn,
+};
+
+xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
+ (void *)&mt_ventoux_fpga_fns, 0);
+
+/* Initialize the FPGA */
+static void mt_ventoux_init_fpga(void)
+{
+ fpga_pre_config_fn(0);
+
+ /* Setting CS1 for FPGA access */
+ enable_gpmc_cs_config(gpmc_fpga, &gpmc_cfg->cs[1],
+ FPGA_BASE_ADDR, GPMC_SIZE_128M);
+
+ fpga_init();
+ fpga_add(fpga_xilinx, &fpga);
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ mt_ventoux_init_fpga();
+
+ /* GPIO_140: speaker #mute */
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4))
+ /* GPIO_141: Buzz Hi */
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4))
+
+ /* Turning off the buzzer */
+ gpio_request(BUZZER, "BUZZER_MUTE");
+ gpio_request(SPEAKER, "SPEAKER");
+ gpio_direction_output(BUZZER, 0);
+ gpio_direction_output(SPEAKER, 0);
+
+ /* Activate USB power */
+ gpio_request(USB1_PWR, "USB1_PWR");
+ gpio_request(USB2_PWR, "USB2_PWR");
+ gpio_direction_output(USB1_PWR, 1);
+ gpio_direction_output(USB2_PWR, 1);
+
+ return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+int misc_init_r(void)
+{
+ char *eth_addr;
+ struct tam3517_module_info info;
+ int ret;
+
+ TAM3517_READ_EEPROM(&info, ret);
+ dieid_num_r();
+
+ if (ret)
+ return 0;
+ eth_addr = getenv("ethaddr");
+ if (!eth_addr)
+ TAM3517_READ_MAC_FROM_EEPROM(&info);
+
+ TAM3517_PRINT_SOM_INFO(&info);
+ return 0;
+}
+#endif
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_MT_VENTOUX();
+}
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int board_eth_init(bd_t *bis)
+{
+ davinci_emac_initialize();
+ return 0;
+}
+
+#if defined(CONFIG_OMAP_HSMMC) && \
+ !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+int board_video_init(void)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ struct panel_config *panel = &lcd_cfg[0];
+ char *s;
+ u32 index = 0;
+
+ void *fb;
+
+ fb = (void *)0x88000000;
+
+ s = getenv("panel");
+ if (s) {
+ index = simple_strtoul(s, NULL, 10);
+ if (index < ARRAY_SIZE(lcd_cfg))
+ panel = &lcd_cfg[index];
+ else
+ return 0;
+ }
+
+ panel->frame_buffer = fb;
+ printf("Panel: %dx%d\n", panel_resolution[index].xres,
+ panel_resolution[index].yres);
+ panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
+ (panel_resolution[index].xres - 1);
+
+ gpio_request(LCD_PWR, "LCD Power");
+ gpio_request(LCD_PON_PIN, "LCD Pon");
+ gpio_direction_output(LCD_PWR, 0);
+ gpio_direction_output(LCD_PON_PIN, 1);
+
+
+ setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
+ setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
+
+ omap3_dss_panel_config(panel);
+ omap3_dss_enable();
+
+ return 0;
+}
+#endif
diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h
new file mode 100644
index 0000000..bc85ad4
--- /dev/null
+++ b/board/teejet/mt_ventoux/mt_ventoux.h
@@ -0,0 +1,404 @@
+/*
+ * Copyright (C) 2011 Stefano Babic <sbabic@denx.de>
+ *
+ * Author: Hardy Weng <hardy.weng@technexion.com>
+ *
+ * Copyright (C) 2010 TechNexion Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MT_VENTOUX_H_
+#define _MT_VENTOUX_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "Teejet MT_VENTOUX Board",
+ "NAND",
+};
+
+/* FPGA CS1 configuration */
+#define FPGA_GPMC_CONFIG1 0x00001200
+#define FPGA_GPMC_CONFIG2 0x00161f00
+#define FPGA_GPMC_CONFIG3 0x00040400
+#define FPGA_GPMC_CONFIG4 0x120c1f08
+#define FPGA_GPMC_CONFIG5 0x001e161f
+#define FPGA_GPMC_CONFIG6 0x96080fcf
+
+#define FPGA_BASE_ADDR 0x20000000
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_MT_VENTOUX() \
+ /* SDRC */\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SDRC_CKE0), (M0)) \
+ MUX_VAL(CP(SDRC_CKE1), (M0)) \
+ MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
+ /* GPMC */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M4))/* GPIO 53 */\
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /* GPIO 54 */\
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
+ /* GPIO 55 : NFS */\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M4)) \
+ /*GPIO_62: FPGA_RESET */ \
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
+ /* GPIO_64*/ \
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
+ /* DSS */\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
+ /* CAMERA */\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \
+ /* MMC */\
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
+ /* GPIO_126: CardDetect */\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
+ /*GPIO_128 */ \
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
+ \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \
+ /* GPIO_138: LCD_ENVD */\
+ MUX_VAL(CP(MMC2_DAT7), (IDIS | PTD | EN | M4)) \
+ /* GPIO_139: LCD_PON */\
+ /* McBSP */\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
+ \
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) \
+ /* GPIO_116: FPGA_PROG */ \
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \
+ /* GPIO_117: FPGA_CCLK */ \
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \
+ /* GPIO_118: FPGA_DIN */ \
+ MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \
+ /* GPIO_119: FPGA_INIT */ \
+ \
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \
+ \
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) \
+ /*GPIO_152: Ignition Sense */ \
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M4)) \
+ /*GPIO_153: Power Button Sense */ \
+ MUX_VAL(CP(MCBSP4_DX), (IEN | PTU | DIS | M4)) \
+ /* GPIO_154: FPGA_DONE */ \
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) \
+ /* GPIO_155: CA8_irq */ \
+ /* UART */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \
+ /* GPIO_149: USB status 2 */\
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \
+ /* GPIO_150: USB status 1 */\
+ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M2)) \
+ /* gpt9_pwm */\
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M2)) \
+ /* gpt10_pwm */\
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M2)) \
+ /* gpt8_pwm */\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M2)) \
+ /* gpt11_pwm */\
+ \
+ MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) \
+ /*GPIO_163 : TS_PENIRQ*/ \
+ MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) \
+ /*GPIO_164 : MMC */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
+ /* I2C */\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
+ /* McSPI */\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \
+ \
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) \
+ /* CCDC */\
+ MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M4)) \
+ /* GPIO94 */\
+ MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M4)) \
+ /* GPIO95: #Enable Output */\
+ MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M4)) \
+ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M4)) \
+ /* GPIO 99: #SOM_PWR_OFF */\
+ MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M4)) \
+ /* GPIO_100: #power out */\
+ MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M4)) \
+ /* GPIO_102 */\
+ MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M4)) \
+ /* RMII */\
+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
+ MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
+ MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
+ MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
+ MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
+ /* HECC */\
+ MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
+ /* HSUSB */\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_STP), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
+ /* HDQ */\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
+ /* GPIO_170: auto update */\
+ /* Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \
+ /* - GPIO30 */\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+ MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \
+ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) \
+ /* gpio_10 */\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
+ /* JTAG */\
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \
+ MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \
+ /* ETK (ES2 onwards) */\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
+ /* hsusb1_stp */ \
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
+ /* hsusb1_clk */\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | EN | M4)) \
+ /* gpio_24 */\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
+ /* gpio_26 */\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) \
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
+ /* gpio_29 */\
+ /* Die to Die */\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
+
+#endif
diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig
new file mode 100644
index 0000000..1ddbb2c
--- /dev/null
+++ b/board/ti/am335x/Kconfig
@@ -0,0 +1,40 @@
+if TARGET_AM335X_EVM
+
+config SYS_BOARD
+ default "am335x"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "am335x_evm"
+
+config CONS_INDEX
+ int "UART used for console"
+ range 1 6
+ default 1
+ help
+ The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+ in documentation, etc) available to it. Depending on your specific
+ board you may want something other than UART0 as for example the IDK
+ uses UART3 so enter 4 here.
+
+config NOR
+ bool "Support for NOR flash"
+ help
+ The AM335x SoC supports having a NOR flash connected to the GPMC.
+ In practice this is seen as a NOR flash module connected to the
+ "memory cape" for the BeagleBone family.
+
+config NOR_BOOT
+ bool "Support for booting from NOR flash"
+ depends on NOR
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via NOR. In this case we will enable certain pinmux early
+ as the ROM only partially sets up pinmux. We also default to using
+ NOR for environment.
+endif
diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS
new file mode 100644
index 0000000..d166fa0
--- /dev/null
+++ b/board/ti/am335x/MAINTAINERS
@@ -0,0 +1,17 @@
+AM335X BOARD
+M: Tom Rini <trini@ti.com>
+S: Maintained
+F: board/ti/am335x/
+F: include/configs/am335x_evm.h
+F: configs/am335x_boneblack_defconfig
+F: configs/am335x_boneblack_vboot_defconfig
+F: configs/am335x_evm_defconfig
+F: configs/am335x_evm_nor_defconfig
+F: configs/am335x_evm_norboot_defconfig
+F: configs/am335x_evm_spiboot_defconfig
+F: configs/am335x_evm_uart1_defconfig
+F: configs/am335x_evm_uart2_defconfig
+F: configs/am335x_evm_uart3_defconfig
+F: configs/am335x_evm_uart4_defconfig
+F: configs/am335x_evm_uart5_defconfig
+F: configs/am335x_evm_usbspl_defconfig
diff --git a/board/ti/am335x/Makefile b/board/ti/am335x/Makefile
new file mode 100644
index 0000000..804ac37
--- /dev/null
+++ b/board/ti/am335x/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y := mux.o
+endif
+
+obj-y += board.o
diff --git a/board/ti/am335x/README b/board/ti/am335x/README
new file mode 100644
index 0000000..19e0ecc
--- /dev/null
+++ b/board/ti/am335x/README
@@ -0,0 +1,205 @@
+Summary
+=======
+
+This document covers various features of the 'am335x_evm' build, and some of
+the related build targets (am335x_evm_uartN, etc).
+
+Hardware
+========
+
+The binary produced by this board supports, based on parsing of the EEPROM
+documented in TI's reference designs:
+- AM335x GP EVM
+- AM335x EVM SK
+- Beaglebone White
+- Beaglebone Black
+
+Customization
+=============
+
+Given that all of the above boards are reference platforms (and the
+Beaglebone platforms are OSHA), it is likely that this platform code and
+configuration will be used as the basis of a custom platform. It is
+worth noting that aside from things such as NAND or MMC only being
+required if a custom platform makes use of these blocks, the following
+are required, depending on design:
+
+- GPIO is only required if DDR3 power is controlled in a way similar to
+ EVM SK
+- SPI is only required for SPI flash, or exposing the SPI bus.
+
+The following blocks are required:
+- I2C, to talk with the PMIC and ensure that we do not run afoul of
+ errata 1.0.24.
+
+When removing options as part of customization,
+CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
+needs and to remove no longer relevant options as in some cases we
+define additional text blocks (such as for NAND or DFU strings). Also
+note that all of the SPL options are grouped together, rather than with
+the IP blocks, so both areas will need their choices updated to reflect
+the custom design.
+
+NAND
+====
+
+The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In
+this example to program the NAND we assume that an SD card has been
+inserted with the files to write in the first SD slot and that mtdparts
+have been configured correctly for the board. All images are first loaded
+into memory, then written to NAND.
+
+Step-1: Building u-boot for NAND boot
+ Set following CONFIGxx options for NAND device.
+ CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page
+ CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page
+ CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block
+ CONFIG_SYS_NAND_ECCPOS ECC map for NAND page
+ CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand)
+
+Step-2: Flashing NAND via MMC/SD
+ # select BOOTSEL to MMC/SD boot and boot from MMC/SD card
+ U-Boot # mmc rescan
+ # erase flash
+ U-Boot # nand erase.chip
+ U-Boot # env default -f -a
+ U-Boot # saveenv
+ # flash MLO. Redundant copies of MLO are kept for failsafe
+ U-Boot # load mmc 0 0x82000000 MLO
+ U-Boot # nand write 0x82000000 0x00000 0x20000
+ U-Boot # nand write 0x82000000 0x20000 0x20000
+ U-Boot # nand write 0x82000000 0x40000 0x20000
+ U-Boot # nand write 0x82000000 0x60000 0x20000
+ # flash u-boot.img
+ U-Boot # load mmc 0 0x82000000 u-boot.img
+ U-Boot # nand write 0x82000000 0x80000 0x60000
+ # flash kernel image
+ U-Boot # load mmc 0 0x82000000 uImage
+ U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize}
+ # flash filesystem image
+ U-Boot # load mmc 0 0x82000000 filesystem.img
+ U-Boot # nand write 0x82000000 ${loadaddress} 0x300000
+
+Step-3: Set BOOTSEL pin to select NAND boot, and POR the device.
+ The device should boot from images flashed on NAND device.
+
+NOR
+===
+
+The Beaglebone White can be equipped with a "memory cape" that in turn can
+have a NOR module plugged into it. In this case it is then possible to
+program and boot from NOR. Note that due to how U-Boot is designed we
+must build a specific version of U-Boot that knows we have NOR flash. This
+build is named 'am335x_evm_nor'. Further, we have a 'am335x_evm_norboot'
+build that will assume that the environment is on NOR rather than NAND. In
+the following example we assume that and SD card has been populated with
+MLO and u-boot.img from a 'am335x_evm_nor' build and also contains the
+'u-boot.bin' from a 'am335x_evm_norboot' build. When booting from NOR, a
+binary must be written to the start of NOR, with no header or similar
+prepended. In the following example we use a size of 512KiB (0x80000)
+as that is how much space we set aside before the environment, as per
+the config file.
+
+U-Boot # mmc rescan
+U-Boot # load mmc 0 ${loadaddr} u-boot.bin
+U-Boot # protect off 08000000 +80000
+U-Boot # erase 08000000 +80000
+U-Boot # cp.b ${loadaddr} 08000000 ${filesize}
+
+Falcon Mode
+===========
+
+The default build includes "Falcon Mode" (see doc/README.falcon) via NAND,
+eMMC (or raw SD cards) and FAT SD cards. Our default behavior currently is
+to read a 'c' on the console while in SPL at any point prior to loading the
+OS payload (so as soon as possible) to opt to booting full U-Boot. Also
+note that while one can program Falcon Mode "in place" great care needs to
+be taken by the user to not 'brick' their setup. As these are all eval
+boards with multiple boot methods, recovery should not be an issue in this
+worst-case however.
+
+Falcon Mode: eMMC
+=================
+
+The recommended layout in this case is:
+
+MMC BLOCKS |--------------------------------| LOCATION IN BYTES
+0x0000 - 0x007F : MBR or GPT table : 0x000000 - 0x020000
+0x0080 - 0x00FF : ARGS or FDT file : 0x010000 - 0x020000
+0x0100 - 0x01FF : SPL.backup1 (first copy used) : 0x020000 - 0x040000
+0x0200 - 0x02FF : SPL.backup2 (second copy used) : 0x040000 - 0x060000
+0x0300 - 0x06FF : U-Boot : 0x060000 - 0x0e0000
+0x0700 - 0x08FF : U-Boot Env + Redundant : 0x0e0000 - 0x120000
+0x0900 - 0x28FF : Kernel : 0x120000 - 0x520000
+
+Note that when we run 'spl export' it will prepare to boot the kernel.
+This includes relocation of the uImage from where we loaded it to the entry
+point defined in the header. As these locations overlap by default, it
+would leave us with an image that if written to MMC will not boot, so
+instead of using the loadaddr variable we use 0x81000000 in the following
+example. In this example we are loading from the network, for simplicity,
+and assume a valid partition table already exists and 'mmc dev' has already
+been run to select the correct device. Also note that if you previously
+had a FAT partition (such as on a Beaglebone Black) it is not enough to
+write garbage into the area, you must delete it from the partition table
+first.
+
+# Ensure we are able to talk with this mmc device
+U-Boot # mmc rescan
+U-Boot # tftp 81000000 am335x/MLO
+# Write to two of the backup locations ROM uses
+U-Boot # mmc write 81000000 100 100
+U-Boot # mmc write 81000000 200 100
+# Write U-Boot to the location set in the config
+U-Boot # tftp 81000000 am335x/u-boot.img
+U-Boot # mmc write 81000000 300 400
+# Load kernel and device tree into memory, perform export
+U-Boot # tftp 81000000 am335x/uImage
+U-Boot # run findfdt
+U-Boot # tftp ${fdtaddr} am335x/${fdtfile}
+U-Boot # run mmcargs
+U-Boot # spl export fdt 81000000 - ${fdtaddr}
+# Write the updated device tree to MMC
+U-Boot # mmc write ${fdtaddr} 80 80
+# Write the uImage to MMC
+U-Boot # mmc write 81000000 900 2000
+
+Falcon Mode: FAT SD cards
+=========================
+
+In this case the additional file is written to the filesystem. In this
+example we assume that the uImage and device tree to be used are already on
+the FAT filesystem (only the uImage MUST be for this to function
+afterwards) along with a Falcon Mode aware MLO and the FAT partition has
+already been created and marked bootable:
+
+U-Boot # mmc rescan
+# Load kernel and device tree into memory, perform export
+U-Boot # load mmc 0:1 ${loadaddr} uImage
+U-Boot # run findfdt
+U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile}
+U-Boot # run mmcargs
+U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+
+This will print a number of lines and then end with something like:
+ Using Device Tree in place at 80f80000, end 80f85928
+ Using Device Tree in place at 80f80000, end 80f88928
+So then you:
+
+U-Boot # fatwrite mmc 0:1 0x80f80000 args 8928
+
+Falcon Mode: NAND
+=================
+
+In this case the additional data is written to another partition of the
+NAND. In this example we assume that the uImage and device tree to be are
+already located on the NAND somewhere (such as filesystem or mtd partition)
+along with a Falcon Mode aware MLO written to the correct locations for
+booting and mtdparts have been configured correctly for the board:
+
+U-Boot # nand read ${loadaddr} kernel
+U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb
+U-Boot # run nandargs
+U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+U-Boot # nand erase.part u-boot-spl-os
+U-Boot # nand write ${fdtaddr} u-boot-spl-os
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
new file mode 100644
index 0000000..0739e60
--- /dev/null
+++ b/board/ti/am335x/board.c
@@ -0,0 +1,672 @@
+/*
+ * board.c
+ *
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65910.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <environment.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_DDR_VTT_EN 7
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(struct am335x_baseboard_id *header)
+{
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+ puts("Could not probe the EEPROM; something fundamentally "
+ "wrong on the I2C bus.\n");
+ return -ENODEV;
+ }
+
+ /* read the eeprom using i2c */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
+ sizeof(struct am335x_baseboard_id))) {
+ puts("Could not read the EEPROM; something fundamentally"
+ " wrong on the I2C bus.\n");
+ return -EIO;
+ }
+
+ if (header->magic != 0xEE3355AA) {
+ /*
+ * read the eeprom using i2c again,
+ * but use only a 1 byte address
+ */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+ sizeof(struct am335x_baseboard_id))) {
+ puts("Could not read the EEPROM; something "
+ "fundamentally wrong on the I2C bus.\n");
+ return -EIO;
+ }
+
+ if (header->magic != 0xEE3355AA) {
+ printf("Incorrect magic number (0x%x) in EEPROM\n",
+ header->magic);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static const struct ddr_data ddr2_data = {
+ .datardsratio0 = MT47H128M16RT25E_RD_DQS,
+ .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+ .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+ .cmd0csratio = MT47H128M16RT25E_RATIO,
+
+ .cmd1csratio = MT47H128M16RT25E_RATIO,
+
+ .cmd2csratio = MT47H128M16RT25E_RATIO,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+ .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+ .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+ .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+ .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+ .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41J128MJT125_RD_DQS,
+ .datawdsratio0 = MT41J128MJT125_WR_DQS,
+ .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
+ .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
+};
+
+static const struct ddr_data ddr3_beagleblack_data = {
+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct ddr_data ddr3_evm_data = {
+ .datardsratio0 = MT41J512M8RH125_RD_DQS,
+ .datawdsratio0 = MT41J512M8RH125_WR_DQS,
+ .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
+ .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41J128MJT125_RATIO,
+ .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41J128MJT125_RATIO,
+ .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41J128MJT125_RATIO,
+ .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
+};
+
+static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
+ .cmd0csratio = MT41K256M16HA125E_RATIO,
+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41K256M16HA125E_RATIO,
+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41K256M16HA125E_RATIO,
+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
+ .cmd0csratio = MT41J512M8RH125_RATIO,
+ .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41J512M8RH125_RATIO,
+ .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41J512M8RH125_RATIO,
+ .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41J128MJT125_EMIF_SDCFG,
+ .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
+ .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
+ .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
+ .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
+ .zq_config = MT41J128MJT125_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
+};
+
+static struct emif_regs ddr3_beagleblack_emif_reg_data = {
+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static struct emif_regs ddr3_evm_emif_reg_data = {
+ .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
+ .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
+ .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
+ .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
+ .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
+ .zq_config = MT41J512M8RH125_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
+ PHY_EN_DYN_PWRDN,
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
+}
+#endif
+
+#define OSC (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+ 266, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_evm_sk = {
+ 303, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_bone_black = {
+ 400, OSC-1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ struct am335x_baseboard_id header;
+ int mpu_vdd;
+
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
+
+ /* Get the frequency */
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+ if (board_is_bone(&header) || board_is_bone_lt(&header)) {
+ /* BeagleBone PMIC Code */
+ int usb_cur_lim;
+
+ /*
+ * Only perform PMIC configurations if board rev > A1
+ * on Beaglebone White
+ */
+ if (board_is_bone(&header) && !strncmp(header.version,
+ "00A1", 4))
+ return;
+
+ if (i2c_probe(TPS65217_CHIP_PM))
+ return;
+
+ /*
+ * On Beaglebone White we need to ensure we have AC power
+ * before increasing the frequency.
+ */
+ if (board_is_bone(&header)) {
+ uchar pmic_status_reg;
+ if (tps65217_reg_read(TPS65217_STATUS,
+ &pmic_status_reg))
+ return;
+ if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
+ puts("No AC power, disabling frequency switch\n");
+ return;
+ }
+ }
+
+ /*
+ * Override what we have detected since we know if we have
+ * a Beaglebone Black it supports 1GHz.
+ */
+ if (board_is_bone_lt(&header))
+ dpll_mpu_opp100.m = MPUPLL_M_1000;
+
+ /*
+ * Increase USB current limit to 1300mA or 1800mA and set
+ * the MPU voltage controller as needed.
+ */
+ if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+ } else {
+ usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+ mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+ }
+
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+ TPS65217_POWER_PATH,
+ usb_cur_lim,
+ TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+ puts("tps65217_reg_write failure\n");
+
+ /* Set DCDC3 (CORE) voltage to 1.125V */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+ TPS65217_DCDC_VOLT_SEL_1125MV)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set DCDC2 (MPU) voltage */
+ if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+ puts("tps65217_voltage_update failure\n");
+ return;
+ }
+
+ /*
+ * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
+ * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
+ */
+ if (board_is_bone(&header)) {
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+ TPS65217_DEFLS1,
+ TPS65217_LDO_VOLTAGE_OUT_3_3,
+ TPS65217_LDO_MASK))
+ puts("tps65217_reg_write failure\n");
+ } else {
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+ TPS65217_DEFLS1,
+ TPS65217_LDO_VOLTAGE_OUT_1_8,
+ TPS65217_LDO_MASK))
+ puts("tps65217_reg_write failure\n");
+ }
+
+ if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+ TPS65217_DEFLS2,
+ TPS65217_LDO_VOLTAGE_OUT_3_3,
+ TPS65217_LDO_MASK))
+ puts("tps65217_reg_write failure\n");
+ } else {
+ int sil_rev;
+
+ /*
+ * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
+ * MPU frequencies we support we use a CORE voltage of
+ * 1.1375V. For MPU voltage we need to switch based on
+ * the frequency we are running at.
+ */
+ if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
+ return;
+
+ /*
+ * Depending on MPU clock and PG we will need a different
+ * VDD to drive at that speed.
+ */
+ sil_rev = readl(&cdev->deviceid) >> 28;
+ mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
+ dpll_mpu_opp100.m);
+
+ /* Tell the TPS65910 to use i2c */
+ tps65910_set_i2c_control();
+
+ /* First update MPU voltage. */
+ if (tps65910_voltage_update(MPU, mpu_vdd))
+ return;
+
+ /* Second, update the CORE voltage. */
+ if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
+ return;
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+ }
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ struct am335x_baseboard_id header;
+
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
+
+ if (board_is_evm_sk(&header))
+ return &dpll_ddr_evm_sk;
+ else if (board_is_bone_lt(&header))
+ return &dpll_ddr_bone_black;
+ else if (board_is_evm_15_or_later(&header))
+ return &dpll_ddr_evm_sk;
+ else
+ return &dpll_ddr;
+}
+
+void set_uart_mux_conf(void)
+{
+#if CONFIG_CONS_INDEX == 1
+ enable_uart0_pin_mux();
+#elif CONFIG_CONS_INDEX == 2
+ enable_uart1_pin_mux();
+#elif CONFIG_CONS_INDEX == 3
+ enable_uart2_pin_mux();
+#elif CONFIG_CONS_INDEX == 4
+ enable_uart3_pin_mux();
+#elif CONFIG_CONS_INDEX == 5
+ enable_uart4_pin_mux();
+#elif CONFIG_CONS_INDEX == 6
+ enable_uart5_pin_mux();
+#endif
+}
+
+void set_mux_conf_regs(void)
+{
+ __maybe_unused struct am335x_baseboard_id header;
+
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
+
+ enable_board_pin_mux(&header);
+}
+
+const struct ctrl_ioregs ioregs_evmsk = {
+ .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
+ .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_bonelt = {
+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_evm15 = {
+ .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+ .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+ .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+ .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+ .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+ __maybe_unused struct am335x_baseboard_id header;
+
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
+
+ if (board_is_evm_sk(&header)) {
+ /*
+ * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
+ * This is safe enough to do on older revs.
+ */
+ gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+ gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+ }
+
+ if (board_is_evm_sk(&header))
+ config_ddr(303, &ioregs_evmsk, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+ else if (board_is_bone_lt(&header))
+ config_ddr(400, &ioregs_bonelt,
+ &ddr3_beagleblack_data,
+ &ddr3_beagleblack_cmd_ctrl_data,
+ &ddr3_beagleblack_emif_reg_data, 0);
+ else if (board_is_evm_15_or_later(&header))
+ config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
+ &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
+ else
+ config_ddr(266, &ioregs, &ddr2_data,
+ &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
+ gpmc_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ char safe_string[HDR_NAME_LEN + 1];
+ struct am335x_baseboard_id header;
+
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
+
+ /* Now set variables based on the header. */
+ strncpy(safe_string, (char *)header.name, sizeof(header.name));
+ safe_string[sizeof(header.name)] = 0;
+ setenv("board_name", safe_string);
+
+ strncpy(safe_string, (char *)header.version, sizeof(header.version));
+ safe_string[sizeof(header.version)] = 0;
+ setenv("board_rev", safe_string);
+#endif
+
+ return 0;
+}
+#endif
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 0,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif
+
+/*
+ * This function will:
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
+ * in the environment
+ * Perform fixups to the PHY present on certain boards. We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
+ && defined(CONFIG_SPL_BUILD)) || \
+ ((defined(CONFIG_DRIVER_TI_CPSW) || \
+ defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+ !defined(CONFIG_SPL_BUILD))
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+ __maybe_unused struct am335x_baseboard_id header;
+
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+ mac_lo = readl(&cdev->macid1l);
+ mac_hi = readl(&cdev->macid1h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (!getenv("eth1addr")) {
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("eth1addr", mac_addr);
+ }
+
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
+
+ if (board_is_bone(&header) || board_is_bone_lt(&header) ||
+ board_is_idk(&header)) {
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
+ PHY_INTERFACE_MODE_MII;
+ } else {
+ writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
+ PHY_INTERFACE_MODE_RGMII;
+ }
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+#endif
+
+ /*
+ *
+ * CPSW RGMII Internal Delay Mode is not supported in all PVT
+ * operating points. So we must set the TX clock delay feature
+ * in the AR8051 PHY. Since we only support a single ethernet
+ * device in U-Boot, we only do this for the first instance.
+ */
+#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
+#define AR8051_PHY_DEBUG_DATA_REG 0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
+#define AR8051_RGMII_TX_CLK_DLY 0x100
+
+ if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
+ const char *devname;
+ devname = miiphy_get_current_dev();
+
+ miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
+ AR8051_DEBUG_RGMII_CLK_DLY_REG);
+ miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
+ AR8051_RGMII_TX_CLK_DLY);
+ }
+#endif
+#if defined(CONFIG_USB_ETHER) && \
+ (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
+
+ rv = usb_eth_initialize(bis);
+ if (rv < 0)
+ printf("Error %d registering USB_ETHER\n", rv);
+ else
+ n += rv;
+#endif
+ return n;
+}
+#endif
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
new file mode 100644
index 0000000..bc700d5
--- /dev/null
+++ b/board/ti/am335x/board.h
@@ -0,0 +1,77 @@
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * TI AM335x parts define a system EEPROM that defines certain sub-fields.
+ * We use these fields to in turn see what board we are on, and what
+ * that might require us to set or not set.
+ */
+#define HDR_NO_OF_MAC_ADDR 3
+#define HDR_ETH_ALEN 6
+#define HDR_NAME_LEN 8
+
+struct am335x_baseboard_id {
+ unsigned int magic;
+ char name[HDR_NAME_LEN];
+ char version[4];
+ char serial[12];
+ char config[32];
+ char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
+static inline int board_is_bone(struct am335x_baseboard_id *header)
+{
+ return !strncmp(header->name, "A335BONE", HDR_NAME_LEN);
+}
+
+static inline int board_is_bone_lt(struct am335x_baseboard_id *header)
+{
+ return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_sk(struct am335x_baseboard_id *header)
+{
+ return !strncmp("A335X_SK", header->name, HDR_NAME_LEN);
+}
+
+static inline int board_is_idk(struct am335x_baseboard_id *header)
+{
+ return !strncmp(header->config, "SKU#02", 6);
+}
+
+static inline int board_is_gp_evm(struct am335x_baseboard_id *header)
+{
+ return !strncmp("A33515BB", header->name, HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
+{
+ return (board_is_gp_evm(header) &&
+ strncmp("1.5", header->version, 3) <= 0);
+}
+
+/*
+ * We have three pin mux functions that must exist. We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(struct am335x_baseboard_id *header);
+#endif
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
new file mode 100644
index 0000000..680f656
--- /dev/null
+++ b/board/ti/am335x/mux.c
@@ -0,0 +1,373 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
+ {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+ {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+ {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
+ {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+ {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
+ {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
+ {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
+ {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+ {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+static struct module_pin_mux spi0_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
+ {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
+ PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
+ {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
+ {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
+ PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
+ {-1},
+};
+
+static struct module_pin_mux gpio0_7_pin_mux[] = {
+ {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
+ {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+ {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
+ {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
+ {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
+ {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
+ {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
+ {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
+ {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
+ {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
+ {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
+ {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
+ {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
+ {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
+ {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
+ {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
+ {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
+ {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
+ {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
+ {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
+#endif
+ {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
+ {-1},
+};
+#elif defined(CONFIG_NOR)
+static struct module_pin_mux bone_norcape_pin_mux[] = {
+ {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */
+ {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */
+ {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */
+ {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */
+ {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */
+ {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */
+ {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */
+ {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */
+ {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */
+ {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */
+ {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */
+ {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */
+ {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */
+ {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */
+ {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */
+ {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */
+ {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */
+ {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */
+ {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */
+ {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */
+ {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */
+ {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */
+ {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */
+ {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */
+ {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
+ {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
+ {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
+ {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
+ {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
+ {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
+ {-1},
+};
+#endif
+
+#if defined(CONFIG_NOR_BOOT)
+void enable_norboot_pin_mux(void)
+{
+ configure_module_pin_mux(bone_norcape_pin_mux);
+}
+#endif
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+ configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+ configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+ configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+ configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+ configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+/*
+ * The AM335x GP EVM, if daughter card(s) are connected, can have 8
+ * different profiles. These profiles determine what peripherals are
+ * valid and need pinmux to be configured.
+ */
+#define PROFILE_NONE 0x0
+#define PROFILE_0 (1 << 0)
+#define PROFILE_1 (1 << 1)
+#define PROFILE_2 (1 << 2)
+#define PROFILE_3 (1 << 3)
+#define PROFILE_4 (1 << 4)
+#define PROFILE_5 (1 << 5)
+#define PROFILE_6 (1 << 6)
+#define PROFILE_7 (1 << 7)
+#define PROFILE_MASK 0x7
+#define PROFILE_ALL 0xFF
+
+/* CPLD registers */
+#define I2C_CPLD_ADDR 0x35
+#define CFG_REG 0x10
+
+static unsigned short detect_daughter_board_profile(void)
+{
+ unsigned short val;
+
+ if (i2c_probe(I2C_CPLD_ADDR))
+ return PROFILE_NONE;
+
+ if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
+ return PROFILE_NONE;
+
+ return (1 << (val & PROFILE_MASK));
+}
+
+void enable_board_pin_mux(struct am335x_baseboard_id *header)
+{
+ /* Do board-specific muxes. */
+ if (board_is_bone(header)) {
+ /* Beaglebone pinmux */
+ configure_module_pin_mux(i2c1_pin_mux);
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+#if defined(CONFIG_NAND)
+ configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_NOR)
+ configure_module_pin_mux(bone_norcape_pin_mux);
+#else
+ configure_module_pin_mux(mmc1_pin_mux);
+#endif
+ } else if (board_is_gp_evm(header)) {
+ /* General Purpose EVM */
+ unsigned short profile = detect_daughter_board_profile();
+ configure_module_pin_mux(rgmii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ /* In profile #2 i2c1 and spi0 conflict. */
+ if (profile & ~PROFILE_2)
+ configure_module_pin_mux(i2c1_pin_mux);
+ /* Profiles 2 & 3 don't have NAND */
+#ifdef CONFIG_NAND
+ if (profile & ~(PROFILE_2 | PROFILE_3))
+ configure_module_pin_mux(nand_pin_mux);
+#endif
+ else if (profile == PROFILE_2) {
+ configure_module_pin_mux(mmc1_pin_mux);
+ configure_module_pin_mux(spi0_pin_mux);
+ }
+ } else if (board_is_idk(header)) {
+ /* Industrial Motor Control (IDK) */
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(mmc0_no_cd_pin_mux);
+ } else if (board_is_evm_sk(header)) {
+ /* Starter Kit EVM */
+ configure_module_pin_mux(i2c1_pin_mux);
+ configure_module_pin_mux(gpio0_7_pin_mux);
+ configure_module_pin_mux(rgmii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux_sk_evm);
+ } else if (board_is_bone_lt(header)) {
+ /* Beaglebone LT pinmux */
+ configure_module_pin_mux(i2c1_pin_mux);
+ configure_module_pin_mux(mii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
+ configure_module_pin_mux(nand_pin_mux);
+#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
+ configure_module_pin_mux(bone_norcape_pin_mux);
+#else
+ configure_module_pin_mux(mmc1_pin_mux);
+#endif
+ } else {
+ puts("Unknown board, cannot configure pinmux.");
+ hang();
+ }
+}
diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds
new file mode 100644
index 0000000..78f294a
--- /dev/null
+++ b/board/ti/am335x/u-boot.lds
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.__image_copy_start)
+ *(.vectors)
+ CPUDIR/start.o (.text*)
+ board/ti/am335x/built-in.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+ . = ALIGN(4);
+
+ .image_copy_end :
+ {
+ *(.__image_copy_end)
+ }
+
+ .rel_dyn_start :
+ {
+ *(.__rel_dyn_start)
+ }
+
+ .rel.dyn : {
+ *(.rel*)
+ }
+
+ .rel_dyn_end :
+ {
+ *(.__rel_dyn_end)
+ }
+
+ .hash : { *(.hash*) }
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ __bss_base = .;
+ }
+
+ .bss __bss_base (OVERLAY) : {
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_limit = .;
+ }
+
+ .bss_end __bss_limit (OVERLAY) : {
+ KEEP(*(.__bss_end));
+ }
+
+ .dynsym _image_binary_end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .gnu.hash : { *(.gnu.hash) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
+}
diff --git a/board/ti/am3517crane/Kconfig b/board/ti/am3517crane/Kconfig
new file mode 100644
index 0000000..ad025a3
--- /dev/null
+++ b/board/ti/am3517crane/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_AM3517_CRANE
+
+config SYS_BOARD
+ default "am3517crane"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "am3517_crane"
+
+endif
diff --git a/board/ti/am3517crane/MAINTAINERS b/board/ti/am3517crane/MAINTAINERS
new file mode 100644
index 0000000..cbc3213
--- /dev/null
+++ b/board/ti/am3517crane/MAINTAINERS
@@ -0,0 +1,6 @@
+AM3517CRANE BOARD
+M: Nagendra T S <nagendra@mistralsolutions.com>
+S: Maintained
+F: board/ti/am3517crane/
+F: include/configs/am3517_crane.h
+F: configs/am3517_crane_defconfig
diff --git a/board/ti/am3517crane/Makefile b/board/ti/am3517crane/Makefile
new file mode 100644
index 0000000..9da795d
--- /dev/null
+++ b/board/ti/am3517crane/Makefile
@@ -0,0 +1,11 @@
+#
+# Author: Srinath R <srinath@mistralsolutions.com>
+#
+# Based on logicpd/am3517evm/Makefile
+#
+# Copyright (C) 2011 Mistral Solutions Pvt Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := am3517crane.o
diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c
new file mode 100644
index 0000000..a649697
--- /dev/null
+++ b/board/ti/am3517crane/am3517crane.c
@@ -0,0 +1,71 @@
+/*
+ * am3517crane.c - board file for AM3517 CraneBoard
+ *
+ * Author: Srinath.R <srinath@mistralsolutions.com>
+ *
+ * Based on logicpd/am3517evm/am3517evm.c
+ *
+ * Copyright (C) 2011 Mistral Solutions Pvt Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include "am3517crane.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_CRANEBOARD;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init i2c, ethernet, etc... (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+#endif
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_AM3517CRANE();
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
diff --git a/board/ti/am3517crane/am3517crane.h b/board/ti/am3517crane/am3517crane.h
new file mode 100644
index 0000000..6289ca7
--- /dev/null
+++ b/board/ti/am3517crane/am3517crane.h
@@ -0,0 +1,344 @@
+/*
+ * am3517crane.h - Header file for the AM3517 CraneBoard.
+ *
+ * Author: Srinath R <srinath@mistralsolutions.com>
+ *
+ * Based on logicpd/am3517evm/am3517evm.h
+ *
+ * Copyright (C) 2011 Mistral Solutions Pvt Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _AM3517CRANE_H_
+#define _AM3517CRANE_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "CraneBoard",
+ "NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_AM3517CRANE()\
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_CKE0), (M0))\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SDRC_CKE0), (M0))\
+ MUX_VAL(CP(SDRC_CKE1), (M0))\
+ /*sdrc_strben_dly0*/\
+ MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0))\
+ /*sdrc_strben_dly1*/\
+ MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0))\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (M7))\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A6), (M7))\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_A9), (M7))\
+ MUX_VAL(CP(GPMC_A10), (M7))\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_NCS2), (M7))\
+ MUX_VAL(CP(GPMC_NCS3), (M7))\
+ MUX_VAL(CP(GPMC_NCS4), (M7))\
+ MUX_VAL(CP(GPMC_NCS5), (M7))\
+ MUX_VAL(CP(GPMC_NCS6), (M7))\
+ MUX_VAL(CP(GPMC_NCS7), (M7))\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0))/*TP*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NBE1), (M7))\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_WAIT1), (M7))\
+ MUX_VAL(CP(GPMC_WAIT2), (M7))\
+ MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4))/*GPIO_65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0))\
+ /*MMC1*/\
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M0))\
+ /*MMC2*/\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | DIS | M0))\
+ /*McBSP*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0))\
+ \
+ MUX_VAL(CP(MCBSP2_FSX), (M7))\
+ MUX_VAL(CP(MCBSP2_CLKX), (M7))\
+ MUX_VAL(CP(MCBSP2_DR), (M7))\
+ MUX_VAL(CP(MCBSP2_DX), (M7))\
+ \
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0))\
+ \
+ MUX_VAL(CP(MCBSP4_CLKX), (M7))\
+ MUX_VAL(CP(MCBSP4_DR), (M7))\
+ MUX_VAL(CP(MCBSP4_DX), (M7))\
+ MUX_VAL(CP(MCBSP4_FSX), (M7))\
+ /*UART*/\
+ MUX_VAL(CP(UART1_TX), (M7))\
+ MUX_VAL(CP(UART1_RTS), (M7))\
+ MUX_VAL(CP(UART1_CTS), (M7))\
+ MUX_VAL(CP(UART1_RX), (M7))\
+ \
+ MUX_VAL(CP(UART2_CTS), (M7))\
+ MUX_VAL(CP(UART2_RTS), (M7))\
+ MUX_VAL(CP(UART2_TX), (M7))\
+ MUX_VAL(CP(UART2_RX), (M7))\
+ \
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0))\
+ /*I2C 1, 2, 3*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
+ /*McSPI*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4))/*GPIO_171 TP*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4))/*GPIO_172 TP*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4))/*GPIO_173 TP*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTU | EN | M4))/*GPIO_174 TP*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4))/*GPIO_175 TP*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4))/*GPIO_176 TP*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4))/*GPIO_176 TP*/\
+ \
+ MUX_VAL(CP(MCSPI2_CLK), (M7))\
+ MUX_VAL(CP(MCSPI2_SIMO), (M7))\
+ MUX_VAL(CP(MCSPI2_SOMI), (M7))\
+ MUX_VAL(CP(MCSPI2_CS0), (M7))\
+ MUX_VAL(CP(MCSPI2_CS1), (M7))\
+ /*CCDC*/\
+ MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1))/*CCDC_DATA8*/\
+ MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1))/*CCDC_DATA9 */\
+ MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0))\
+ /*RMII*/\
+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0))\
+ MUX_VAL(CP(RMII_MDIO_CLK), (M0))\
+ MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0))\
+ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0))\
+ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0))\
+ MUX_VAL(CP(RMII_RXER), (PTD | M0))\
+ MUX_VAL(CP(RMII_TXD0), (PTD | M0))\
+ MUX_VAL(CP(RMII_TXD1), (PTD | M0))\
+ MUX_VAL(CP(RMII_TXEN), (PTD | M0))\
+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0))\
+ /*HECC*/\
+ MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0))\
+ /*HSUSB*/\
+ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0))\
+ /*HDQ*/\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4))\
+ /*Control and debug*/\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M4))/*GPIO_1 TPS_SLEEP*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0))\
+ /*SYS_nRESWARM*/\
+ MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | EN | M0))/*GPIO_30 ToExp*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))/*GPIO_10 TP*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0))\
+ /*JTAG*/\
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0))\
+ /*ETK (ES2 onwards)*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M3))\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3))\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3))\
+ MUX_VAL(CP(ETK_D10_ES2), (M7))\
+ MUX_VAL(CP(ETK_D11_ES2), (M7))\
+ MUX_VAL(CP(ETK_D12_ES2), (M7))\
+ MUX_VAL(CP(ETK_D13_ES2), (M7))\
+ MUX_VAL(CP(ETK_D14_ES2), (M7))\
+ MUX_VAL(CP(ETK_D15_ES2), (M7))\
+ /*Die to Die*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0))\
+
+#endif /* _AM3517CRANE_H_ */
diff --git a/board/ti/am43xx/Kconfig b/board/ti/am43xx/Kconfig
new file mode 100644
index 0000000..8d1c168
--- /dev/null
+++ b/board/ti/am43xx/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AM43XX_EVM
+
+config SYS_BOARD
+ default "am43xx"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "am43xx_evm"
+
+endif
diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS
new file mode 100644
index 0000000..d375278
--- /dev/null
+++ b/board/ti/am43xx/MAINTAINERS
@@ -0,0 +1,7 @@
+AM43XX BOARD
+M: Lokesh Vutla <lokeshvutla@ti.com>
+S: Maintained
+F: board/ti/am43xx/
+F: include/configs/am43xx_evm.h
+F: configs/am43xx_evm_defconfig
+F: configs/am43xx_evm_qspiboot_defconfig
diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile
new file mode 100644
index 0000000..36ecb30
--- /dev/null
+++ b/board/ti/am43xx/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y := mux.o
+endif
+
+obj-y += board.o
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
new file mode 100644
index 0000000..a1c3c17
--- /dev/null
+++ b/board/ti/am43xx/board.c
@@ -0,0 +1,786 @@
+/*
+ * board.c
+ *
+ * Board functions for TI AM43XX based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/errno.h>
+#include <spl.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/emif.h>
+#include "board.h"
+#include <power/pmic.h>
+#include <power/tps65218.h>
+#include <miiphy.h>
+#include <cpsw.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(struct am43xx_board_id *header)
+{
+ /* Check if baseboard eeprom is available */
+ if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+ printf("Could not probe the EEPROM at 0x%x\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR);
+ return -ENODEV;
+ }
+
+ /* read the eeprom using i2c */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
+ sizeof(struct am43xx_board_id))) {
+ printf("Could not read the EEPROM\n");
+ return -EIO;
+ }
+
+ if (header->magic != 0xEE3355AA) {
+ /*
+ * read the eeprom using i2c again,
+ * but use only a 1 byte address
+ */
+ if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+ sizeof(struct am43xx_board_id))) {
+ printf("Could not read the EEPROM at 0x%x\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR);
+ return -EIO;
+ }
+
+ if (header->magic != 0xEE3355AA) {
+ printf("Incorrect magic number (0x%x) in EEPROM\n",
+ header->magic);
+ return -EINVAL;
+ }
+ }
+
+ strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
+ am43xx_board_name[sizeof(header->name)] = 0;
+
+ strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version));
+ am43xx_board_rev[sizeof(header->version)] = 0;
+
+ return 0;
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+#define NUM_OPPS 6
+
+const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
+ { /* 19.2 MHz */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */
+ {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */
+ },
+ { /* 24 MHz */
+ {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
+ {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
+ {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
+ {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
+ {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
+ },
+ { /* 25 MHz */
+ {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
+ {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
+ {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
+ {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
+ {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
+ },
+ { /* 26 MHz */
+ {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
+ {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
+ {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
+ {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
+ {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
+ },
+};
+
+const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
+ {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
+ {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
+ {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
+};
+
+const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
+ {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */
+ {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */
+ {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */
+};
+
+const struct dpll_params epos_evm_dpll_ddr = {
+ 266, 24, 1, -1, 1, -1, -1};
+
+const struct dpll_params gp_evm_dpll_ddr = {
+ 400, 23, 1, -1, 1, -1, -1};
+
+const struct ctrl_ioregs ioregs_lpddr2 = {
+ .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
+ .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
+ .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
+ .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
+ .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
+ .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
+ .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
+ .emif_sdram_config_ext = 0x1,
+};
+
+const struct emif_regs emif_regs_lpddr2 = {
+ .sdram_config = 0x808012BA,
+ .ref_ctrl = 0x0000040D,
+ .sdram_tim1 = 0xEA86B411,
+ .sdram_tim2 = 0x103A094A,
+ .sdram_tim3 = 0x0F6BA37F,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x50074BE4,
+ .temp_alert_config = 0x0,
+ .emif_rd_wr_lvl_rmp_win = 0x0,
+ .emif_rd_wr_lvl_rmp_ctl = 0x0,
+ .emif_rd_wr_lvl_ctl = 0x0,
+ .emif_ddr_phy_ctlr_1 = 0x0E084006,
+ .emif_rd_wr_exec_thresh = 0x80000405,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
+ .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
+ .emif_prio_class_serv_map = 0x80000001,
+ .emif_connect_id_serv_1_map = 0x80000094,
+ .emif_connect_id_serv_2_map = 0x00000000,
+ .emif_cos_config = 0x000FFFFF
+};
+
+const u32 ext_phy_ctrl_const_base_lpddr2[] = {
+ 0x00500050,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40001000,
+ 0x08102040
+};
+
+const struct ctrl_ioregs ioregs_ddr3 = {
+ .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
+ .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
+ .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
+ .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
+ .emif_sdram_config_ext = 0x0143,
+};
+
+const struct emif_regs ddr3_emif_regs_400Mhz = {
+ .sdram_config = 0x638413B2,
+ .ref_ctrl = 0x00000C30,
+ .sdram_tim1 = 0xEAAAD4DB,
+ .sdram_tim2 = 0x266B7FDA,
+ .sdram_tim3 = 0x107F8678,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x50074BE4,
+ .temp_alert_config = 0x0,
+ .emif_ddr_phy_ctlr_1 = 0x0E004008,
+ .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
+ .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
+ .emif_rd_wr_lvl_rmp_win = 0x0,
+ .emif_rd_wr_lvl_rmp_ctl = 0x0,
+ .emif_rd_wr_lvl_ctl = 0x0,
+ .emif_rd_wr_exec_thresh = 0x80000405,
+ .emif_prio_class_serv_map = 0x80000001,
+ .emif_connect_id_serv_1_map = 0x80000094,
+ .emif_connect_id_serv_2_map = 0x00000000,
+ .emif_cos_config = 0x000FFFFF
+};
+
+/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
+const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
+ .sdram_config = 0x638413B2,
+ .ref_ctrl = 0x00000C30,
+ .sdram_tim1 = 0xEAAAD4DB,
+ .sdram_tim2 = 0x266B7FDA,
+ .sdram_tim3 = 0x107F8678,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x50074BE4,
+ .temp_alert_config = 0x0,
+ .emif_ddr_phy_ctlr_1 = 0x0E004008,
+ .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
+ .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
+ .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
+ .emif_rd_wr_exec_thresh = 0x80000405,
+ .emif_prio_class_serv_map = 0x80000001,
+ .emif_connect_id_serv_1_map = 0x80000094,
+ .emif_connect_id_serv_2_map = 0x00000000,
+ .emif_cos_config = 0x000FFFFF
+};
+
+/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
+const struct emif_regs ddr3_emif_regs_400Mhz_production = {
+ .sdram_config = 0x638413B2,
+ .ref_ctrl = 0x00000C30,
+ .sdram_tim1 = 0xEAAAD4DB,
+ .sdram_tim2 = 0x266B7FDA,
+ .sdram_tim3 = 0x107F8678,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x50074BE4,
+ .temp_alert_config = 0x0,
+ .emif_ddr_phy_ctlr_1 = 0x0E004008,
+ .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
+ .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
+ .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
+ .emif_rd_wr_exec_thresh = 0x80000405,
+ .emif_prio_class_serv_map = 0x80000001,
+ .emif_connect_id_serv_1_map = 0x80000094,
+ .emif_connect_id_serv_2_map = 0x00000000,
+ .emif_cos_config = 0x000FFFFF
+};
+
+static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
+ .sdram_config = 0x638413b2,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x00000c30,
+ .sdram_tim1 = 0xeaaad4db,
+ .sdram_tim2 = 0x266b7fda,
+ .sdram_tim3 = 0x107f8678,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x50074be4,
+ .temp_alert_config = 0x0,
+ .emif_ddr_phy_ctlr_1 = 0x0e084008,
+ .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x89,
+ .emif_ddr_ext_phy_ctrl_3 = 0x90,
+ .emif_ddr_ext_phy_ctrl_4 = 0x8e,
+ .emif_ddr_ext_phy_ctrl_5 = 0x8d,
+ .emif_rd_wr_lvl_rmp_win = 0x0,
+ .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x80000000,
+ .emif_prio_class_serv_map = 0x80000001,
+ .emif_connect_id_serv_1_map = 0x80000094,
+ .emif_connect_id_serv_2_map = 0x00000000,
+ .emif_cos_config = 0x000FFFFF
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3[] = {
+ 0x00400040,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00340034,
+ 0x00340034,
+ 0x00340034,
+ 0x00340034,
+ 0x00340034,
+ 0x0,
+ 0x0,
+ 0x40000000,
+ 0x08102040
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3_beta[] = {
+ 0x00000000,
+ 0x00000045,
+ 0x00000046,
+ 0x00000048,
+ 0x00000047,
+ 0x00000000,
+ 0x0000004C,
+ 0x00000070,
+ 0x00000085,
+ 0x000000A3,
+ 0x00000000,
+ 0x0000000C,
+ 0x00000030,
+ 0x00000045,
+ 0x00000063,
+ 0x00000000,
+ 0x0,
+ 0x0,
+ 0x40000000,
+ 0x08102040
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3_production[] = {
+ 0x00000000,
+ 0x00000044,
+ 0x00000044,
+ 0x00000046,
+ 0x00000046,
+ 0x00000000,
+ 0x00000059,
+ 0x00000077,
+ 0x00000093,
+ 0x000000A8,
+ 0x00000000,
+ 0x00000019,
+ 0x00000037,
+ 0x00000053,
+ 0x00000068,
+ 0x00000000,
+ 0x0,
+ 0x0,
+ 0x40000000,
+ 0x08102040
+};
+
+static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
+ /* first 5 are taken care by emif_regs */
+ 0x00700070,
+
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+ 0x00350035,
+
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+
+ 0x00150015,
+ 0x00150015,
+ 0x00150015,
+ 0x00150015,
+ 0x00150015,
+
+ 0x00800080,
+ 0x00800080,
+
+ 0x40000000,
+
+ 0x08102040,
+
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+ if (board_is_eposevm()) {
+ *regs = ext_phy_ctrl_const_base_lpddr2;
+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+ } else if (board_is_evm_14_or_later()) {
+ *regs = ext_phy_ctrl_const_base_ddr3_production;
+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production);
+ } else if (board_is_evm_12_or_later()) {
+ *regs = ext_phy_ctrl_const_base_ddr3_beta;
+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta);
+ } else if (board_is_gpevm()) {
+ *regs = ext_phy_ctrl_const_base_ddr3;
+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
+ } else if (board_is_sk()) {
+ *regs = ext_phy_ctrl_const_base_ddr3_sk;
+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk);
+ }
+
+ return;
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ if (board_is_eposevm())
+ return &epos_evm_dpll_ddr;
+ else if (board_is_gpevm() || board_is_sk())
+ return &gp_evm_dpll_ddr;
+
+ printf(" Board '%s' not supported\n", am43xx_board_name);
+ return NULL;
+}
+
+/*
+ * get_sys_clk_index : returns the index of the sys_clk read from
+ * ctrl status register. This value is either
+ * read from efuse or sysboot pins.
+ */
+static u32 get_sys_clk_index(void)
+{
+ struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
+ u32 ind = readl(&ctrl->statusreg), src;
+
+ src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
+ if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
+ return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
+ CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
+ else /* Value read from SYS BOOT pins */
+ return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
+ CTRL_SYSBOOT_15_14_SHIFT);
+}
+
+/*
+ * get_opp_offset:
+ * Returns the index for safest OPP of the device to boot.
+ * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
+ * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
+ * This data is read from dev_attribute register which is e-fused.
+ * A'1' in bit indicates OPP disabled and not available, a '0' indicates
+ * OPP available. Lowest OPP starts with min_off. So returning the
+ * bit with rightmost '0'.
+ */
+static int get_opp_offset(int max_off, int min_off)
+{
+ struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
+ int opp, offset, i;
+
+ /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
+ opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
+
+ for (i = max_off; i >= min_off; i--) {
+ offset = opp & (1 << i);
+ if (!offset)
+ return i;
+ }
+
+ return min_off;
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+ int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
+ u32 ind = get_sys_clk_index();
+
+ return &dpll_mpu[ind][opp];
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+ int ind = get_sys_clk_index();
+
+ return &dpll_core[ind];
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+ int ind = get_sys_clk_index();
+
+ return &dpll_per[ind];
+}
+
+void scale_vcores(void)
+{
+ const struct dpll_params *mpu_params;
+ int mpu_vdd;
+ struct am43xx_board_id header;
+
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
+
+ /* Get the frequency */
+ mpu_params = get_dpll_mpu_params();
+
+ if (i2c_probe(TPS65218_CHIP_PM))
+ return;
+
+ if (mpu_params->m == 1000) {
+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
+ } else if (mpu_params->m == 600) {
+ mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
+ } else {
+ puts("Unknown MPU clock, not scaling\n");
+ return;
+ }
+
+ /* Set DCDC1 (CORE) voltage to 1.1V */
+ if (tps65218_voltage_update(TPS65218_DCDC1,
+ TPS65218_DCDC_VOLT_SEL_1100MV)) {
+ puts("tps65218_voltage_update failure\n");
+ return;
+ }
+
+ /* Set DCDC2 (MPU) voltage */
+ if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
+ puts("tps65218_voltage_update failure\n");
+ return;
+ }
+}
+
+void set_uart_mux_conf(void)
+{
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ enable_board_pin_mux();
+}
+
+static void enable_vtt_regulator(void)
+{
+ u32 temp;
+
+ /* enable module */
+ writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
+
+ /* enable output for GPIO5_7 */
+ writel(GPIO_SETDATAOUT(7),
+ AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
+ temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+ temp = temp & ~(GPIO_OE_ENABLE(7));
+ writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
+}
+
+void sdram_init(void)
+{
+ /*
+ * EPOS EVM has 1GB LPDDR2 connected to EMIF.
+ * GP EMV has 1GB DDR3 connected to EMIF
+ * along with VTT regulator.
+ */
+ if (board_is_eposevm()) {
+ config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
+ } else if (board_is_evm_14_or_later()) {
+ enable_vtt_regulator();
+ config_ddr(0, &ioregs_ddr3, NULL, NULL,
+ &ddr3_emif_regs_400Mhz_production, 0);
+ } else if (board_is_evm_12_or_later()) {
+ enable_vtt_regulator();
+ config_ddr(0, &ioregs_ddr3, NULL, NULL,
+ &ddr3_emif_regs_400Mhz_beta, 0);
+ } else if (board_is_gpevm()) {
+ enable_vtt_regulator();
+ config_ddr(0, &ioregs_ddr3, NULL, NULL,
+ &ddr3_emif_regs_400Mhz, 0);
+ } else if (board_is_sk()) {
+ config_ddr(400, &ioregs_ddr3, NULL, NULL,
+ &ddr3_sk_emif_regs_400Mhz, 0);
+ }
+}
+#endif
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+ struct pmic *p;
+
+ power_tps65218_init(I2C_PMIC);
+ p = pmic_get("TPS65218_PMIC");
+ if (p && !pmic_probe(p))
+ puts("PMIC: TPS65218\n");
+
+ return 0;
+}
+
+int board_init(void)
+{
+ struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
+ u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
+ modena_init0_bw_integer, modena_init0_watermark_0;
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ gpmc_init();
+
+ /* Clear all important bits for DSS errata that may need to be tweaked*/
+ mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
+ MREQPRIO_0_SAB_INIT0_MASK;
+
+ mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
+
+ modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
+ BW_LIMITER_BW_FRAC_MASK;
+
+ modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
+ BW_LIMITER_BW_INT_MASK;
+
+ modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
+ BW_LIMITER_BW_WATERMARK_MASK;
+
+ /* Setting MReq Priority of the DSS*/
+ mreqprio_0 |= 0x77;
+
+ /*
+ * Set L3 Fast Configuration Register
+ * Limiting bandwith for ARM core to 700 MBPS
+ */
+ modena_init0_bw_fractional |= 0x10;
+ modena_init0_bw_integer |= 0x3;
+
+ writel(mreqprio_0, &cdev->mreqprio_0);
+ writel(mreqprio_1, &cdev->mreqprio_1);
+
+ writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
+ writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
+ writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ char safe_string[HDR_NAME_LEN + 1];
+ struct am43xx_board_id header;
+
+ if (read_eeprom(&header) < 0)
+ puts("Could not get board ID.\n");
+
+ /* Now set variables based on the header. */
+ strncpy(safe_string, (char *)header.name, sizeof(header.name));
+ safe_string[sizeof(header.name)] = 0;
+ setenv("board_name", safe_string);
+
+ strncpy(safe_string, (char *)header.version, sizeof(header.version));
+ safe_string[sizeof(header.version)] = 0;
+ setenv("board_rev", safe_string);
+#endif
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+static void cpsw_control(int enabled)
+{
+ /* Additional controls can be added here */
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 16,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 1,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int rv;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (!getenv("ethaddr")) {
+ puts("<ethaddr> not set. Validating first E-fuse MAC\n");
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ mac_lo = readl(&cdev->macid1l);
+ mac_hi = readl(&cdev->macid1h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (!getenv("eth1addr")) {
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("eth1addr", mac_addr);
+ }
+
+ if (board_is_eposevm()) {
+ writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+ cpsw_slaves[0].phy_addr = 16;
+ } else if (board_is_sk()) {
+ writel(RGMII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
+ cpsw_slaves[0].phy_addr = 4;
+ cpsw_slaves[1].phy_addr = 5;
+ } else {
+ writel(RGMII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
+ cpsw_slaves[0].phy_addr = 0;
+ }
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+
+ return rv;
+}
+#endif
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
new file mode 100644
index 0000000..8e12191
--- /dev/null
+++ b/board/ti/am43xx/board.h
@@ -0,0 +1,69 @@
+/*
+ * board.h
+ *
+ * TI AM437x boards information header
+ * Derived from AM335x board.
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include <asm/arch/omap.h>
+
+static char *const am43xx_board_name = (char *)AM4372_BOARD_NAME_START;
+static char *const am43xx_board_rev = (char *)AM4372_BOARD_VERSION_START;
+
+/*
+ * TI AM437x EVMs define a system EEPROM that defines certain sub-fields.
+ * We use these fields to in turn see what board we are on, and what
+ * that might require us to set or not set.
+ */
+#define HDR_NO_OF_MAC_ADDR 3
+#define HDR_ETH_ALEN 6
+#define HDR_NAME_LEN 8
+
+#define DEV_ATTR_MAX_OFFSET 5
+#define DEV_ATTR_MIN_OFFSET 0
+
+struct am43xx_board_id {
+ unsigned int magic;
+ char name[HDR_NAME_LEN];
+ char version[4];
+ char serial[12];
+ char config[32];
+ char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
+};
+
+static inline int board_is_eposevm(void)
+{
+ return !strncmp(am43xx_board_name, "AM43EPOS", HDR_NAME_LEN);
+}
+
+static inline int board_is_gpevm(void)
+{
+ return !strncmp(am43xx_board_name, "AM43__GP", HDR_NAME_LEN);
+}
+
+static inline int board_is_sk(void)
+{
+ return !strncmp(am43xx_board_name, "AM43__SK", HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_14_or_later(void)
+{
+ return (board_is_gpevm() && strncmp("1.4", am43xx_board_rev, 3) <= 0);
+}
+
+static inline int board_is_evm_12_or_later(void)
+{
+ return (board_is_gpevm() && strncmp("1.2", am43xx_board_rev, 3) <= 0);
+}
+
+void enable_uart0_pin_mux(void);
+void enable_board_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+#endif
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
new file mode 100644
index 0000000..a670b0b
--- /dev/null
+++ b/board/ti/am43xx/mux.c
@@ -0,0 +1,153 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include "board.h"
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
+ {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
+ {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */
+ {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+ {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
+ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
+ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
+ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
+ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
+ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
+ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
+ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
+ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
+ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
+ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
+ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
+ {-1},
+};
+
+static struct module_pin_mux mdio_pin_mux[] = {
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {-1},
+};
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */
+ {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+ {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
+ {-1},
+};
+
+static struct module_pin_mux gpio5_7_pin_mux[] = {
+ {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */
+ {-1},
+};
+
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
+ {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
+ {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
+ {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
+ {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
+ {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
+ {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
+ {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
+#endif
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* Write Protect */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* Chip-Select */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* Write Enable */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* Read Enable */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */
+ {-1},
+};
+#endif
+
+static __maybe_unused struct module_pin_mux qspi_pin_mux[] = {
+ {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
+ {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
+ {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
+ {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
+ {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
+ {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(mdio_pin_mux);
+
+ if (board_is_gpevm()) {
+ configure_module_pin_mux(gpio5_7_pin_mux);
+ configure_module_pin_mux(rgmii1_pin_mux);
+#if defined(CONFIG_NAND)
+ configure_module_pin_mux(nand_pin_mux);
+#endif
+ } else if (board_is_sk()) {
+ configure_module_pin_mux(rgmii1_pin_mux);
+#if defined(CONFIG_NAND)
+ printf("Error: NAND flash not present on this board\n");
+#endif
+ configure_module_pin_mux(qspi_pin_mux);
+ } else if (board_is_eposevm()) {
+ configure_module_pin_mux(rmii1_pin_mux);
+#if defined(CONFIG_NAND)
+ configure_module_pin_mux(nand_pin_mux);
+#else
+ configure_module_pin_mux(qspi_pin_mux);
+#endif
+ }
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
diff --git a/board/ti/beagle/Kconfig b/board/ti/beagle/Kconfig
new file mode 100644
index 0000000..c2eff9e
--- /dev/null
+++ b/board/ti/beagle/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP3_BEAGLE
+
+config SYS_BOARD
+ default "beagle"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "omap3_beagle"
+
+endif
diff --git a/board/ti/beagle/MAINTAINERS b/board/ti/beagle/MAINTAINERS
new file mode 100644
index 0000000..2225fb6
--- /dev/null
+++ b/board/ti/beagle/MAINTAINERS
@@ -0,0 +1,6 @@
+BEAGLE BOARD
+M: Tom Rini <trini@ti.com>
+S: Maintained
+F: board/ti/beagle/
+F: include/configs/omap3_beagle.h
+F: configs/omap3_beagle_defconfig
diff --git a/board/ti/beagle/Makefile b/board/ti/beagle/Makefile
new file mode 100644
index 0000000..7a858be
--- /dev/null
+++ b/board/ti/beagle/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := beagle.o
+obj-$(CONFIG_STATUS_LED) += led.o
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
new file mode 100644
index 0000000..7b37fbe
--- /dev/null
+++ b/board/ti/beagle/beagle.c
@@ -0,0 +1,576 @@
+/*
+ * (C) Copyright 2004-2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
+#include <twl4030.h>
+#include <linux/mtd/nand.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/omap_musb.h>
+#include <asm/errno.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
+#include "beagle.h"
+#include <command.h>
+
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/ehci-omap.h>
+#endif
+
+#define TWL4030_I2C_BUS 0
+#define EXPANSION_EEPROM_I2C_BUS 1
+#define EXPANSION_EEPROM_I2C_ADDRESS 0x50
+
+#define TINCANTOOLS_ZIPPY 0x01000100
+#define TINCANTOOLS_ZIPPY2 0x02000100
+#define TINCANTOOLS_TRAINER 0x04000100
+#define TINCANTOOLS_SHOWDOG 0x03000100
+#define KBADC_BEAGLEFPGA 0x01000600
+#define LW_BEAGLETOUCH 0x01000700
+#define BRAINMUX_LCDOG 0x01000800
+#define BRAINMUX_LCDOGTOUCH 0x02000800
+#define BBTOYS_WIFI 0x01000B00
+#define BBTOYS_VGA 0x02000B00
+#define BBTOYS_LCD 0x03000B00
+#define BCT_BRETTL3 0x01000F00
+#define BCT_BRETTL4 0x02000F00
+#define LSR_COM6L_ADPT 0x01001300
+#define BEAGLE_NO_EEPROM 0xffffffff
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct {
+ unsigned int device_vendor;
+ unsigned char revision;
+ unsigned char content;
+ char fab_revision[8];
+ char env_var[16];
+ char env_setting[64];
+} expansion_config;
+
+static const struct ns16550_platdata beagle_serial = {
+ OMAP34XX_UART3,
+ 2,
+ V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(beagle_uart) = {
+ "serial_omap",
+ &beagle_serial
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+
+ return 0;
+}
+
+/*
+ * Routine: get_board_revision
+ * Description: Detect if we are running on a Beagle revision Ax/Bx,
+ * C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading
+ * the level of GPIO173, GPIO172 and GPIO171. This should
+ * result in
+ * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
+ * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
+ * GPIO173, GPIO172, GPIO171: 1 0 1 => C4
+ * GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx
+ * GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx
+ */
+static int get_board_revision(void)
+{
+ static int revision = -1;
+
+ if (revision == -1) {
+ if (!gpio_request(171, "rev0") &&
+ !gpio_request(172, "rev1") &&
+ !gpio_request(173, "rev2")) {
+ gpio_direction_input(171);
+ gpio_direction_input(172);
+ gpio_direction_input(173);
+
+ revision = gpio_get_value(173) << 2 |
+ gpio_get_value(172) << 1 |
+ gpio_get_value(171);
+ } else {
+ printf("Error: unable to acquire board revision GPIOs\n");
+ }
+ }
+
+ return revision;
+}
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ int pop_mfr, pop_id;
+
+ /*
+ * We need to identify what PoP memory is on the board so that
+ * we know what timings to use. If we can't identify it then
+ * we know it's an xM. To map the ID values please see nand_ids.c
+ */
+ identify_nand_chip(&pop_mfr, &pop_id);
+
+ timings->mr = MICRON_V_MR_165;
+ switch (get_board_revision()) {
+ case REVISION_C4:
+ if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
+ /* 512MB DDR */
+ timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_165;
+ timings->ctrlb = NUMONYX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ break;
+ } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
+ /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ break;
+ } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
+ /* Beagleboard Rev C5, 256MB DDR */
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ break;
+ }
+ case REVISION_XM_AB:
+ case REVISION_XM_C:
+ if (pop_mfr == 0) {
+ /* 256MB DDR */
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ } else {
+ /* 512MB DDR */
+ timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_165;
+ timings->ctrlb = NUMONYX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ }
+ break;
+ default:
+ /* Assume 128MB and Micron/165MHz timings to be safe */
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ }
+}
+#endif
+
+/*
+ * Routine: get_expansion_id
+ * Description: This function checks for expansion board by checking I2C
+ * bus 1 for the availability of an AT24C01B serial EEPROM.
+ * returns the device_vendor field from the EEPROM
+ */
+static unsigned int get_expansion_id(void)
+{
+ i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
+
+ /* return BEAGLE_NO_EEPROM if eeprom doesn't respond */
+ if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
+ i2c_set_bus_num(TWL4030_I2C_BUS);
+ return BEAGLE_NO_EEPROM;
+ }
+
+ /* read configuration data */
+ i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
+ sizeof(expansion_config));
+
+ /* retry reading configuration data with 16bit addressing */
+ if ((expansion_config.device_vendor == 0xFFFFFF00) ||
+ (expansion_config.device_vendor == 0xFFFFFFFF)) {
+ printf("EEPROM is blank or 8bit addressing failed: retrying with 16bit:\n");
+ i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 2, (u8 *)&expansion_config,
+ sizeof(expansion_config));
+ }
+
+ i2c_set_bus_num(TWL4030_I2C_BUS);
+
+ return expansion_config.device_vendor;
+}
+
+#ifdef CONFIG_VIDEO_OMAP3
+/*
+ * Configure DSS to display background color on DVID
+ * Configure VENC to display color bar on S-Video
+ */
+static void beagle_display_init(void)
+{
+ omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
+ switch (get_board_revision()) {
+ case REVISION_AXBX:
+ case REVISION_CX:
+ case REVISION_C4:
+ omap3_dss_panel_config(&dvid_cfg);
+ break;
+ case REVISION_XM_AB:
+ case REVISION_XM_C:
+ default:
+ omap3_dss_panel_config(&dvid_cfg_xm);
+ break;
+ }
+}
+
+/*
+ * Enable DVI power
+ */
+static void beagle_dvi_pup(void)
+{
+ uchar val;
+
+ switch (get_board_revision()) {
+ case REVISION_AXBX:
+ case REVISION_CX:
+ case REVISION_C4:
+ gpio_request(170, "dvi");
+ gpio_direction_output(170, 0);
+ gpio_set_value(170, 1);
+ break;
+ case REVISION_XM_AB:
+ case REVISION_XM_C:
+ default:
+ #define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3)
+ #define GPIODATAOUT1 (TWL4030_BASEADD_GPIO+6)
+
+ i2c_read(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
+ val |= 4;
+ i2c_write(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
+
+ i2c_read(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
+ val |= 4;
+ i2c_write(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
+ break;
+ }
+}
+#endif
+
+#ifdef CONFIG_USB_MUSB_OMAP2PLUS
+static struct musb_hdrc_config musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12,
+};
+
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+};
+
+static struct musb_hdrc_platform_data musb_plat = {
+#if defined(CONFIG_MUSB_HOST)
+ .mode = MUSB_HOST,
+#elif defined(CONFIG_MUSB_GADGET)
+ .mode = MUSB_PERIPHERAL,
+#else
+#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET"
+#endif
+ .config = &musb_config,
+ .power = 100,
+ .platform_ops = &omap2430_ops,
+ .board_data = &musb_board_data,
+};
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+ struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
+ bool generate_fake_mac = false;
+ u32 value;
+
+ /* Enable i2c2 pullup resisters */
+ value = readl(&prog_io_base->io1);
+ value &= ~(PRG_I2C2_PULLUPRESX);
+ writel(value, &prog_io_base->io1);
+
+ switch (get_board_revision()) {
+ case REVISION_AXBX:
+ printf("Beagle Rev Ax/Bx\n");
+ setenv("beaglerev", "AxBx");
+ break;
+ case REVISION_CX:
+ printf("Beagle Rev C1/C2/C3\n");
+ setenv("beaglerev", "Cx");
+ MUX_BEAGLE_C();
+ break;
+ case REVISION_C4:
+ printf("Beagle Rev C4\n");
+ setenv("beaglerev", "C4");
+ MUX_BEAGLE_C();
+ /* Set VAUX2 to 1.8V for EHCI PHY */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+ TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ break;
+ case REVISION_XM_AB:
+ printf("Beagle xM Rev A/B\n");
+ setenv("beaglerev", "xMAB");
+ MUX_BEAGLE_XM();
+ /* Set VAUX2 to 1.8V for EHCI PHY */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+ TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ generate_fake_mac = true;
+ break;
+ case REVISION_XM_C:
+ printf("Beagle xM Rev C\n");
+ setenv("beaglerev", "xMC");
+ MUX_BEAGLE_XM();
+ /* Set VAUX2 to 1.8V for EHCI PHY */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+ TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ generate_fake_mac = true;
+ break;
+ default:
+ printf("Beagle unknown 0x%02x\n", get_board_revision());
+ MUX_BEAGLE_XM();
+ /* Set VAUX2 to 1.8V for EHCI PHY */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
+ TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
+ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ generate_fake_mac = true;
+ }
+
+ switch (get_expansion_id()) {
+ case TINCANTOOLS_ZIPPY:
+ printf("Recognized Tincantools Zippy board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_TINCANTOOLS_ZIPPY();
+ setenv("buddy", "zippy");
+ break;
+ case TINCANTOOLS_ZIPPY2:
+ printf("Recognized Tincantools Zippy2 board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_TINCANTOOLS_ZIPPY();
+ setenv("buddy", "zippy2");
+ break;
+ case TINCANTOOLS_TRAINER:
+ printf("Recognized Tincantools Trainer board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ MUX_TINCANTOOLS_ZIPPY();
+ MUX_TINCANTOOLS_TRAINER();
+ setenv("buddy", "trainer");
+ break;
+ case TINCANTOOLS_SHOWDOG:
+ printf("Recognized Tincantools Showdow board (rev %d %s)\n",
+ expansion_config.revision,
+ expansion_config.fab_revision);
+ /* Place holder for DSS2 definition for showdog lcd */
+ setenv("defaultdisplay", "showdoglcd");
+ setenv("buddy", "showdog");
+ break;
+ case KBADC_BEAGLEFPGA:
+ printf("Recognized KBADC Beagle FPGA board\n");
+ MUX_KBADC_BEAGLEFPGA();
+ setenv("buddy", "beaglefpga");
+ break;
+ case LW_BEAGLETOUCH:
+ printf("Recognized Liquidware BeagleTouch board\n");
+ setenv("buddy", "beagletouch");
+ break;
+ case BRAINMUX_LCDOG:
+ printf("Recognized Brainmux LCDog board\n");
+ setenv("buddy", "lcdog");
+ break;
+ case BRAINMUX_LCDOGTOUCH:
+ printf("Recognized Brainmux LCDog Touch board\n");
+ setenv("buddy", "lcdogtouch");
+ break;
+ case BBTOYS_WIFI:
+ printf("Recognized BeagleBoardToys WiFi board\n");
+ MUX_BBTOYS_WIFI()
+ setenv("buddy", "bbtoys-wifi");
+ break;;
+ case BBTOYS_VGA:
+ printf("Recognized BeagleBoardToys VGA board\n");
+ break;;
+ case BBTOYS_LCD:
+ printf("Recognized BeagleBoardToys LCD board\n");
+ break;;
+ case BCT_BRETTL3:
+ printf("Recognized bct electronic GmbH brettl3 board\n");
+ break;
+ case BCT_BRETTL4:
+ printf("Recognized bct electronic GmbH brettl4 board\n");
+ break;
+ case LSR_COM6L_ADPT:
+ printf("Recognized LSR COM6L Adapter Board\n");
+ MUX_BBTOYS_WIFI()
+ setenv("buddy", "lsr-com6l-adpt");
+ break;
+ case BEAGLE_NO_EEPROM:
+ printf("No EEPROM on expansion board\n");
+ setenv("buddy", "none");
+ break;
+ default:
+ printf("Unrecognized expansion board: %x\n",
+ expansion_config.device_vendor);
+ setenv("buddy", "unknown");
+ }
+
+ if (expansion_config.content == 1)
+ setenv(expansion_config.env_var, expansion_config.env_setting);
+
+ twl4030_power_init();
+ switch (get_board_revision()) {
+ case REVISION_XM_AB:
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
+ break;
+ default:
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+ break;
+ }
+
+ /* Set GPIO states before they are made outputs */
+ writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
+ &gpio6_base->setdataout);
+ writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+ GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
+
+ /* Configure GPIOs to output */
+ writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
+ writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+ GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
+
+ dieid_num_r();
+
+#ifdef CONFIG_VIDEO_OMAP3
+ beagle_dvi_pup();
+ beagle_display_init();
+ omap3_dss_enable();
+#endif
+
+#ifdef CONFIG_USB_MUSB_OMAP2PLUS
+ musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
+#endif
+
+ if (generate_fake_mac) {
+ u32 id[4];
+
+ get_dieid(id);
+ usb_fake_mac_from_die_id(id);
+ }
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_BEAGLE();
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
+#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
+/* Call usb_stop() before starting the kernel */
+void show_boot_progress(int val)
+{
+ if (val == BOOTSTAGE_ID_RUN_OS)
+ usb_stop();
+}
+
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(int index)
+{
+ return omap_ehci_hcd_stop();
+}
+
+#endif /* CONFIG_USB_EHCI */
+
+#if defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)
+int board_eth_init(bd_t *bis)
+{
+ return usb_eth_initialize(bis);
+}
+#endif
diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
new file mode 100644
index 0000000..6dd2ffe
--- /dev/null
+++ b/board/ti/beagle/beagle.h
@@ -0,0 +1,546 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _BEAGLE_H_
+#define _BEAGLE_H_
+
+#include <asm/arch/dss.h>
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "OMAP3 Beagle board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+ "OneNAND",
+#else
+ "NAND",
+#endif
+};
+
+/* BeagleBoard revisions */
+#define REVISION_AXBX 0x7
+#define REVISION_CX 0x6
+#define REVISION_C4 0x5
+#define REVISION_XM_AB 0x0
+#define REVISION_XM_C 0x2
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_BEAGLE() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
+ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+ /* USB EHCI (port 2) */\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)) /*HSUSB2_DATA2*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)) /*HSUSB2_DATA7*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)) /*HSUSB2_DATA4*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)) /*HSUSB2_DATA5*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)) /*HSUSB2_DATA6*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)) /*HSUSB2_DATA3*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DIR*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_NXT*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA0*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DATA1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+#define MUX_BEAGLE_C() \
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+ MUX_VAL(CP(UART2_RX), (IDIS | PTU | EN | M4)) /*GPIO_147*/
+
+#define MUX_BEAGLE_XM() \
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | EN | M4)) /*GPIO_56*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IDIS | PTU | EN | M4)) /*GPIO_63*/\
+ MUX_VAL(CP(MMC1_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_129*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+ MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+ MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+ MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+ MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
+
+#define MUX_TINCANTOOLS_ZIPPY() \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | EN | M1)) /*MCSPI4_CLK*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M1)) /*MCSPI4_SIMO*/\
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) /*MCSPI4_SOMI*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) /*MCSPI4_CS0*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/
+
+#define MUX_TINCANTOOLS_TRAINER() \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) /*GPIO_162*/
+
+#define MUX_KBADC_BEAGLEFPGA() \
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | DIS | M1)) /*MCSPI4_CLK*/\
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | EN | M1)) /*MCSPI4_SOMI*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/
+
+#define MUX_BBTOYS_WIFI() \
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) /*GPIO_136 FM_EN/BT_WU*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137 WLAN_IRQ*/\
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) /*GPIO_138 BT_EN*/\
+ MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_139 WLAN_EN*/
+
+/*
+ * Display Configuration
+ */
+
+#define DVI_BEAGLE_ORANGE_COL 0x00FF8000
+#define VENC_HEIGHT 0x00ef
+#define VENC_WIDTH 0x027f
+
+/*
+ * Configure VENC in DSS for Beagle to generate Color Bar
+ *
+ * Kindly refer to OMAP TRM for definition of these values.
+ */
+static const struct venc_regs venc_config_std_tv = {
+ .status = 0x0000001B,
+ .f_control = 0x00000040,
+ .vidout_ctrl = 0x00000000,
+ .sync_ctrl = 0x00008000,
+ .llen = 0x00008359,
+ .flens = 0x0000020C,
+ .hfltr_ctrl = 0x00000000,
+ .cc_carr_wss_carr = 0x043F2631,
+ .c_phase = 0x00000024,
+ .gain_u = 0x00000130,
+ .gain_v = 0x00000198,
+ .gain_y = 0x000001C0,
+ .black_level = 0x0000006A,
+ .blank_level = 0x0000005C,
+ .x_color = 0x00000000,
+ .m_control = 0x00000001,
+ .bstamp_wss_data = 0x0000003F,
+ .s_carr = 0x21F07C1F,
+ .line21 = 0x00000000,
+ .ln_sel = 0x00000015,
+ .l21__wc_ctl = 0x00001400,
+ .htrigger_vtrigger = 0x00000000,
+ .savid__eavid = 0x069300F4,
+ .flen__fal = 0x0016020C,
+ .lal__phase_reset = 0x00060107,
+ .hs_int_start_stop_x = 0x008D034E,
+ .hs_ext_start_stop_x = 0x000F0359,
+ .vs_int_start_x = 0x01A00000,
+ .vs_int_stop_x__vs_int_start_y = 0x020501A0,
+ .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
+ .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
+ .vs_ext_stop_y = 0x00000006,
+ .avid_start_stop_x = 0x03480079,
+ .avid_start_stop_y = 0x02040024,
+ .fid_int_start_x__fid_int_start_y = 0x0001008A,
+ .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
+ .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
+ .tvdetgp_int_start_stop_x = 0x00140001,
+ .tvdetgp_int_start_stop_y = 0x00010001,
+ .gen_ctrl = 0x00FF0000,
+ .output_control = 0x0000000D,
+ .dac_b__dac_c = 0x00000000
+};
+
+/*
+ * Configure Timings for DVI D
+ */
+static const struct panel_config dvid_cfg = {
+ .timing_h = 0x0ff03f31, /* Horizontal timing */
+ .timing_v = 0x01400504, /* Vertical timing */
+ .pol_freq = 0x00007028, /* Pol Freq */
+ .divisor = 0x00010006, /* 72Mhz Pixel Clock */
+ .lcd_size = 0x02ff03ff, /* 1024x768 */
+ .panel_type = 0x01, /* TFT */
+ .data_lines = 0x03, /* 24 Bit RGB */
+ .load_mode = 0x02, /* Frame Mode */
+ .panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
+};
+
+static const struct panel_config dvid_cfg_xm = {
+ .timing_h = 0x1a4024c9, /* Horizontal timing */
+ .timing_v = 0x02c00509, /* Vertical timing */
+ .pol_freq = 0x00007028, /* Pol Freq */
+ .divisor = 0x00010001, /* 96MHz Pixel Clock */
+ .lcd_size = 0x02ff03ff, /* 1024x768 */
+ .panel_type = 0x01, /* TFT */
+ .data_lines = 0x03, /* 24 Bit RGB */
+ .load_mode = 0x02, /* Frame Mode */
+ .panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
+};
+#endif
diff --git a/board/ti/beagle/led.c b/board/ti/beagle/led.c
new file mode 100644
index 0000000..a913a4c
--- /dev/null
+++ b/board/ti/beagle/led.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2010 Texas Instruments, Inc.
+ * Jason Kridner <jkridner@beagleboard.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <status_led.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+
+/* GPIO pins for the LEDs */
+#define BEAGLE_LED_USR0 150
+#define BEAGLE_LED_USR1 149
+
+#ifdef STATUS_LED_GREEN
+void green_led_off(void)
+{
+ __led_set (STATUS_LED_GREEN, 0);
+}
+
+void green_led_on(void)
+{
+ __led_set (STATUS_LED_GREEN, 1);
+}
+#endif
+
+static int get_led_gpio(led_id_t mask)
+{
+#ifdef STATUS_LED_BIT
+ if (STATUS_LED_BIT & mask)
+ return BEAGLE_LED_USR0;
+#endif
+#ifdef STATUS_LED_BIT1
+ if (STATUS_LED_BIT1 & mask)
+ return BEAGLE_LED_USR1;
+#endif
+
+ return 0;
+}
+
+void __led_init (led_id_t mask, int state)
+{
+ int toggle_gpio;
+
+ toggle_gpio = get_led_gpio(mask);
+
+ if (toggle_gpio && !gpio_request(toggle_gpio, "led"))
+ __led_set(mask, state);
+}
+
+void __led_toggle (led_id_t mask)
+{
+ int state, toggle_gpio;
+
+ toggle_gpio = get_led_gpio(mask);
+ if (toggle_gpio) {
+ state = gpio_get_value(toggle_gpio);
+ gpio_direction_output(toggle_gpio, !state);
+ }
+}
+
+void __led_set (led_id_t mask, int state)
+{
+ int toggle_gpio;
+
+ toggle_gpio = get_led_gpio(mask);
+ if (toggle_gpio)
+ gpio_direction_output(toggle_gpio, state);
+}
diff --git a/board/ti/beagle_x15/Kconfig b/board/ti/beagle_x15/Kconfig
new file mode 100644
index 0000000..a305ff1
--- /dev/null
+++ b/board/ti/beagle_x15/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BEAGLE_X15
+
+config SYS_BOARD
+ default "beagle_x15"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "beagle_x15"
+
+endif
diff --git a/board/ti/beagle_x15/MAINTAINERS b/board/ti/beagle_x15/MAINTAINERS
new file mode 100644
index 0000000..3f84def
--- /dev/null
+++ b/board/ti/beagle_x15/MAINTAINERS
@@ -0,0 +1,6 @@
+BEAGLE X15
+M: Felipe Balbi <balbi@ti.com>
+S: Maintained
+F: board/ti/beagle_x15/
+F: include/configs/beagle_x15.h
+F: configs/beagle_x15_defconfig
diff --git a/board/ti/beagle_x15/Makefile b/board/ti/beagle_x15/Makefile
new file mode 100644
index 0000000..5cd6873
--- /dev/null
+++ b/board/ti/beagle_x15/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014
+# Texas Instruments, <www.ti.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c
new file mode 100644
index 0000000..db96e34
--- /dev/null
+++ b/board/ti/beagle_x15/board.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Felipe Balbi <balbi@ti.com>
+ *
+ * Based on board/ti/dra7xx/evm.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <palmas.h>
+#include <sata.h>
+#include <usb.h>
+#include <asm/omap_common.h>
+#include <asm/emif.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sata.h>
+#include <asm/arch/gpio.h>
+#include <environment.h>
+
+#include "mux_data.h"
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+#include <cpsw.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: BeagleBoard x15\n"
+};
+
+static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
+ .dmm_lisa_map_3 = 0x80740300,
+ .is_ma_present = 0x1
+};
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+{
+ *dmm_lisa_regs = &beagle_x15_lisa_regs;
+}
+
+static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xceef266b,
+ .sdram_tim2 = 0x328f7fda,
+ .sdram_tim3 = 0x027f88a8,
+ .read_idle_ctrl = 0x00050001,
+ .zq_config = 0x0007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
+ .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
+ .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x00800080,
+ 0x00360036,
+ 0x00340034,
+ 0x00360036,
+ 0x00350035,
+ 0x00350035,
+
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+
+ 0x00430043,
+ 0x003e003e,
+ 0x004a004a,
+ 0x00470047,
+ 0x00400040,
+
+ 0x00000000,
+ 0x00600020,
+ 0x40010080,
+ 0x08102040,
+
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040
+};
+
+static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
+ .sdram_config_init = 0x61851b32,
+ .sdram_config = 0x61851b32,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xceef266b,
+ .sdram_tim2 = 0x328f7fda,
+ .sdram_tim3 = 0x027f88a8,
+ .read_idle_ctrl = 0x00050001,
+ .zq_config = 0x0007190b,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
+ .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
+ .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
+static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x00800080,
+ 0x00370037,
+ 0x00390039,
+ 0x00360036,
+ 0x00370037,
+ 0x00350035,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x01ff01ff,
+ 0x00540054,
+ 0x00540054,
+ 0x004e004e,
+ 0x004c004c,
+ 0x00400040,
+
+ 0x00000000,
+ 0x00600020,
+ 0x40010080,
+ 0x08102040,
+
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040,
+ 0x00400040
+};
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+ switch (emif_nr) {
+ case 1:
+ *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
+ break;
+ case 2:
+ *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
+ break;
+ }
+}
+
+void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
+{
+ switch (emif_nr) {
+ case 1:
+ *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
+ *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
+ break;
+ case 2:
+ *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
+ *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
+ break;
+ }
+}
+
+struct vcores_data beagle_x15_volts = {
+ .mpu.value = VDD_MPU_DRA752,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12,
+ .mpu.pmic = &tps659038,
+
+ .eve.value = VDD_EVE_DRA752,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45,
+ .eve.pmic = &tps659038,
+
+ .gpu.value = VDD_GPU_DRA752,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS45,
+ .gpu.pmic = &tps659038,
+
+ .core.value = VDD_CORE_DRA752,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS659038_REG_ADDR_SMPS6,
+ .core.pmic = &tps659038,
+
+ .iva.value = VDD_IVA_DRA752,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS659038_REG_ADDR_SMPS45,
+ .iva.pmic = &tps659038,
+};
+
+void hw_data_init(void)
+{
+ *prcm = &dra7xx_prcm;
+ *dplls_data = &dra7xx_dplls;
+ *omap_vcores = &beagle_x15_volts;
+ *ctrl = &dra7xx_ctrl;
+}
+
+int board_init(void)
+{
+ gpmc_init();
+ gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ init_sata(0);
+ /*
+ * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
+ * This is the POWERHOLD-in-Low behavior.
+ */
+ palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
+ return 0;
+}
+
+static void do_set_mux32(u32 base,
+ struct pad_conf_entry const *array, int size)
+{
+ int i;
+ struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
+
+ for (i = 0; i < size; i++, pad++)
+ writel(pad->val, base + pad->offset);
+}
+
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+/* Delay value to add to calibrated value */
+#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
+#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
+#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
+#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
+#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
+#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
+#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
+#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
+#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
+#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
+
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 1,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 2,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+ uint32_t ctrl_val;
+
+ /* try reading mac address from efuse */
+ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
+ mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = mac_hi & 0xFF;
+ mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+ mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+ mac_addr[5] = mac_lo & 0xFF;
+
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
+ mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = mac_hi & 0xFF;
+ mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+ mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+ mac_addr[5] = mac_lo & 0xFF;
+
+ if (!getenv("eth1addr")) {
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("eth1addr", mac_addr);
+ }
+
+ ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
+ ctrl_val |= 0x22;
+ writel(ctrl_val, (*ctrl)->control_core_control_io1);
+
+ ret = cpsw_register(&cpsw_data);
+ if (ret < 0)
+ printf("Error %d registering CPSW switch\n", ret);
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_OMAP
+int board_usb_init(int index, enum usb_init_type init)
+{
+ setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
+ OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);
+
+ return 0;
+}
+#endif
diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h
new file mode 100644
index 0000000..2294abe
--- /dev/null
+++ b/board/ti/beagle_x15/mux_data.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Felipe Balbi <balbi@ti.com>
+ *
+ * Based on board/ti/dra7xx/evm.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _MUX_DATA_BEAGLE_X15_H_
+#define _MUX_DATA_BEAGLE_X15_H_
+
+#include <asm/arch/mux_dra7xx.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+ {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
+ {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
+ {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
+ {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
+ {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
+ {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
+ {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
+ {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
+ {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
+ {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
+ {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
+ {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
+ {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
+ {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
+ {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
+ {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
+ {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
+ {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
+ {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
+ {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
+ {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
+ {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
+ {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
+ {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
+ {RGMII0_TXC, (M0) },
+ {RGMII0_TXCTL, (M0) },
+ {RGMII0_TXD3, (M0) },
+ {RGMII0_TXD2, (M0) },
+ {RGMII0_TXD1, (M0) },
+ {RGMII0_TXD0, (M0) },
+ {RGMII0_RXC, (IEN | M0) },
+ {RGMII0_RXCTL, (IEN | M0) },
+ {RGMII0_RXD3, (IEN | M0) },
+ {RGMII0_RXD2, (IEN | M0) },
+ {RGMII0_RXD1, (IEN | M0) },
+ {RGMII0_RXD0, (IEN | M0) },
+ {USB1_DRVVBUS, (M0 | FSC) },
+ {SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */
+};
+#endif /* _MUX_DATA_BEAGLE_X15_H_ */
diff --git a/board/ti/dra7xx/Kconfig b/board/ti/dra7xx/Kconfig
new file mode 100644
index 0000000..3bbd866
--- /dev/null
+++ b/board/ti/dra7xx/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DRA7XX_EVM
+
+config SYS_BOARD
+ default "dra7xx"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "dra7xx_evm"
+
+endif
diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS
new file mode 100644
index 0000000..5ec6769
--- /dev/null
+++ b/board/ti/dra7xx/MAINTAINERS
@@ -0,0 +1,8 @@
+DRA7XX BOARD
+M: Lokesh Vutla <lokeshvutla@ti.com>
+S: Maintained
+F: board/ti/dra7xx/
+F: include/configs/dra7xx_evm.h
+F: configs/dra7xx_evm_defconfig
+F: configs/dra7xx_evm_qspiboot_defconfig
+F: configs/dra7xx_evm_uart3_defconfig
diff --git a/board/ti/dra7xx/Makefile b/board/ti/dra7xx/Makefile
new file mode 100644
index 0000000..434e8d1
--- /dev/null
+++ b/board/ti/dra7xx/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2013
+# Texas Instruments, <www.ti.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := evm.o
diff --git a/board/ti/dra7xx/README b/board/ti/dra7xx/README
new file mode 100644
index 0000000..533da01
--- /dev/null
+++ b/board/ti/dra7xx/README
@@ -0,0 +1,26 @@
+Summary
+=======
+
+This document covers various features of the 'dra7xx_evm' build and some
+related uses.
+
+eMMC boot partition use
+=======================
+
+It is possible, depending on SYSBOOT configuration to boot from the eMMC
+boot partitions using (name depending on documentation referenced)
+Alternative Boot operation mode or Boot Sequence Option 1/2. In this
+example we load MLO and u-boot.img from the build into DDR and then use
+'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
+set boot0 as the boot device.
+U-Boot # setenv autoload no
+U-Boot # usb start
+U-Boot # dhcp
+U-Boot # mmc dev 1 1
+U-Boot # tftp ${loadaddr} dra7xx/MLO
+U-Boot # mmc write ${loadaddr} 0 100
+U-Boot # tftp ${loadaddr} dra7xx/u-boot.img
+U-Boot # mmc write ${loadaddr} 300 400
+U-Boot # mmc bootbus 1 2 0 2
+U-Boot # mmc partconf 1 1 1 0
+U-Boot # mmc rst-function 1 1
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
new file mode 100644
index 0000000..6522241
--- /dev/null
+++ b/board/ti/dra7xx/evm.c
@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ * Based on previous work by:
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <palmas.h>
+#include <sata.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sata.h>
+#include <environment.h>
+
+#include "mux_data.h"
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+#include <cpsw.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO 7_11 */
+#define GPIO_DDR_VTT_EN 203
+
+const struct omap_sysinfo sysinfo = {
+ "Board: DRA7xx\n"
+};
+
+/*
+ * Adjust I/O delays on the Tx control and data lines of each MAC port. This
+ * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
+ * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
+ * essentially need to counteract the DRA7xx internal delay, and we do this
+ * by delaying the control and data lines. If not using this PHY, you probably
+ * don't need to do this stuff!
+ */
+static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
+{
+ int i = 0;
+ u32 reg_val;
+ u32 delta;
+ u32 coarse;
+ u32 fine;
+
+ writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
+
+ while(io_dly[i].addr) {
+ writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
+ io_dly[i].addr);
+ delta = io_dly[i].dly;
+ reg_val = readl(io_dly[i].addr) & 0x3ff;
+ coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
+ coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
+ fine = (reg_val & 0x1F) + (delta & 0x1F);
+ fine = (fine > 0x1F) ? (0x1F) : (fine);
+ reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
+ CFG_IO_DELAY_LOCK_MASK |
+ ((coarse << 5) | (fine));
+ writel(reg_val, io_dly[i].addr);
+ i++;
+ }
+
+ writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
+}
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gpmc_init();
+ gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if (omap_revision() == DRA722_ES1_0)
+ setenv("board_name", "dra72x");
+ else
+ setenv("board_name", "dra7xx");
+#endif
+ return 0;
+}
+
+static void do_set_mux32(u32 base,
+ struct pad_conf_entry const *array, int size)
+{
+ int i;
+ struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
+
+ for (i = 0; i < size; i++, pad++)
+ writel(pad->val, base + pad->offset);
+}
+
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ if (getenv_yesno("boot_os") != 1)
+ return 1;
+#endif
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+/* Delay value to add to calibrated value */
+#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
+#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
+#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
+#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
+#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
+#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
+#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
+#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
+#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
+#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
+
+extern u32 *const omap_si_rev;
+
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_addr = 2,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_addr = 3,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 2,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+ uint32_t ctrl_val;
+ const struct io_delay io_dly[] = {
+ {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
+ {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
+ {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
+ {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
+ {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
+ {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
+ {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
+ {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
+ {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
+ {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
+ {0}
+ };
+
+ /* Adjust IO delay for RGMII tx path */
+ dra7xx_adj_io_delay(io_dly);
+
+ /* try reading mac address from efuse */
+ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
+ mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = mac_hi & 0xFF;
+ mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+ mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+ mac_addr[5] = mac_lo & 0xFF;
+
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ }
+
+ mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
+ mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
+ mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = mac_hi & 0xFF;
+ mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
+ mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+ mac_addr[5] = mac_lo & 0xFF;
+
+ if (!getenv("eth1addr")) {
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("eth1addr", mac_addr);
+ }
+
+ ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
+ ctrl_val |= 0x22;
+ writel(ctrl_val, (*ctrl)->control_core_control_io1);
+
+ if (*omap_si_rev == DRA722_ES1_0)
+ cpsw_data.active_slave = 1;
+
+ ret = cpsw_register(&cpsw_data);
+ if (ret < 0)
+ printf("Error %d registering CPSW switch\n", ret);
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+/* VTT regulator enable */
+static inline void vtt_regulator_enable(void)
+{
+ if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+ return;
+
+ /* Do not enable VTT for DRA722 */
+ if (omap_revision() == DRA722_ES1_0)
+ return;
+
+ /*
+ * EVM Rev G and later use gpio7_11 for DDR3 termination.
+ * This is safe enough to do on older revs.
+ */
+ gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+ gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+}
+
+int board_early_init_f(void)
+{
+ vtt_regulator_enable();
+ return 0;
+}
+#endif
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
new file mode 100644
index 0000000..4824077
--- /dev/null
+++ b/board/ti/dra7xx/mux_data.h
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ * Nishant Kamat <nskamat@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _MUX_DATA_DRA7XX_H_
+#define _MUX_DATA_DRA7XX_H_
+
+#include <asm/arch/mux_dra7xx.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+ {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
+ {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
+ {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
+ {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
+ {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
+ {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
+ {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
+ {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
+#if defined(CONFIG_NOR)
+ /* NOR only pin-mux */
+ {GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */
+ {GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */
+ {GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */
+ {GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */
+ {GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */
+ {GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */
+ {GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */
+ {GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */
+ {GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */
+ {GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */
+ {GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */
+ {GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */
+ {GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */
+ {GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */
+ {GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */
+ {GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */
+ {GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */
+ {GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */
+ {GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */
+ {GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */
+ {GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */
+ {GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */
+ {GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */
+ {GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */
+ {GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */
+ {GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */
+ {GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */
+#else
+ /* eMMC pinmux */
+ {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
+ {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
+ {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
+ {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
+ {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
+ {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
+ {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
+ {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
+ {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
+ {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
+#endif
+#if (CONFIG_CONS_INDEX == 1)
+ {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
+ {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
+ {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */
+ {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
+#elif (CONFIG_CONS_INDEX == 3)
+ {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
+ {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
+#endif
+ {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
+ {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
+ {MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
+ {MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
+ {RGMII0_TXC, (M0) },
+ {RGMII0_TXCTL, (M0) },
+ {RGMII0_TXD3, (M0) },
+ {RGMII0_TXD2, (M0) },
+ {RGMII0_TXD1, (M0) },
+ {RGMII0_TXD0, (M0) },
+ {RGMII0_RXC, (IEN | M0) },
+ {RGMII0_RXCTL, (IEN | M0) },
+ {RGMII0_RXD3, (IEN | M0) },
+ {RGMII0_RXD2, (IEN | M0) },
+ {RGMII0_RXD1, (IEN | M0) },
+ {RGMII0_RXD0, (IEN | M0) },
+ {VIN2A_D12, (M3) },
+ {VIN2A_D13, (M3) },
+ {VIN2A_D14, (M3) },
+ {VIN2A_D15, (M3) },
+ {VIN2A_D16, (M3) },
+ {VIN2A_D17, (M3) },
+ {VIN2A_D18, (IEN | M3)},
+ {VIN2A_D19, (IEN | M3)},
+ {VIN2A_D20, (IEN | M3)},
+ {VIN2A_D21, (IEN | M3)},
+ {VIN2A_D22, (IEN | M3)},
+ {VIN2A_D23, (IEN | M3)},
+#if defined(CONFIG_NAND) || defined(CONFIG_NOR)
+ /* NAND / NOR pin-mux */
+ {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */
+ {GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */
+ {GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */
+ {GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */
+ {GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */
+ {GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */
+ {GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */
+ {GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */
+ {GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */
+ {GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */
+ {GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */
+ {GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */
+ {GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */
+ {GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */
+ {GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */
+ {GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */
+ {GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */
+ {GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */
+ {GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */
+ {GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */
+ {GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */
+ {GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */
+ /* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
+#else
+ /* QSPI pin-mux */
+ {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
+ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
+ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
+ {GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
+ {GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
+ {GPMC_A18, (M1)}, /* QSPI1_SCLK */
+ {GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
+ {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
+ {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
+ {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
+#endif /* CONFIG_NAND || CONFIG_NOR */
+ {USB2_DRVVBUS, (M0 | IEN | FSC) },
+ {SPI1_CS1, (PEN | IDIS | M14) },
+};
+#endif /* _MUX_DATA_DRA7XX_H_ */
diff --git a/board/ti/evm/Kconfig b/board/ti/evm/Kconfig
new file mode 100644
index 0000000..f02aa31
--- /dev/null
+++ b/board/ti/evm/Kconfig
@@ -0,0 +1,38 @@
+if TARGET_OMAP3_EVM
+
+config SYS_BOARD
+ default "evm"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "omap3_evm"
+
+endif
+
+if TARGET_OMAP3_EVM_QUICK_MMC
+
+config SYS_BOARD
+ default "evm"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "omap3_evm_quick_mmc"
+
+endif
+
+if TARGET_OMAP3_EVM_QUICK_NAND
+
+config SYS_BOARD
+ default "evm"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "omap3_evm_quick_nand"
+
+endif
diff --git a/board/ti/evm/MAINTAINERS b/board/ti/evm/MAINTAINERS
new file mode 100644
index 0000000..d0b2788
--- /dev/null
+++ b/board/ti/evm/MAINTAINERS
@@ -0,0 +1,14 @@
+EVM BOARD
+M: Tom Rini <trini@ti.com>
+S: Maintained
+F: board/ti/evm/
+F: include/configs/omap3_evm.h
+F: configs/omap3_evm_defconfig
+
+OMAP3_EVM_QUICK_MMC BOARD
+#M: -
+S: Maintained
+F: include/configs/omap3_evm_quick_mmc.h
+F: configs/omap3_evm_quick_mmc_defconfig
+F: include/configs/omap3_evm_quick_nand.h
+F: configs/omap3_evm_quick_nand_defconfig
diff --git a/board/ti/evm/Makefile b/board/ti/evm/Makefile
new file mode 100644
index 0000000..b88ab8f
--- /dev/null
+++ b/board/ti/evm/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := evm.o
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
new file mode 100644
index 0000000..3f93d9c
--- /dev/null
+++ b/board/ti/evm/evm.c
@@ -0,0 +1,274 @@
+/*
+ * (C) Copyright 2004-2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <twl4030.h>
+#include <asm/mach-types.h>
+#include <linux/mtd/nand.h>
+#include "evm.h"
+
+#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
+#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 omap3_evm_version;
+
+u32 get_omap3_evm_rev(void)
+{
+ return omap3_evm_version;
+}
+
+static void omap3_evm_get_revision(void)
+{
+#if defined(CONFIG_CMD_NET)
+ /*
+ * Board revision can be ascertained only by identifying
+ * the Ethernet chipset.
+ */
+ unsigned int smsc_id;
+
+ /* Ethernet PHY ID is stored at ID_REV register */
+ smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
+ printf("Read back SMSC id 0x%x\n", smsc_id);
+
+ switch (smsc_id) {
+ /* SMSC9115 chipset */
+ case 0x01150000:
+ omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
+ break;
+ /* SMSC 9220 chipset */
+ case 0x92200000:
+ default:
+ omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
+ }
+#else
+#if defined(CONFIG_STATIC_BOARD_REV)
+ /*
+ * Look for static defintion of the board revision
+ */
+ omap3_evm_version = CONFIG_STATIC_BOARD_REV;
+#else
+ /*
+ * Fallback to the default above.
+ */
+ omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
+#endif
+#endif /* CONFIG_CMD_NET */
+}
+
+#ifdef CONFIG_USB_OMAP3
+/*
+ * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
+ */
+u8 omap3_evm_need_extvbus(void)
+{
+ u8 retval = 0;
+
+ if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
+ retval = 1;
+
+ return retval;
+}
+#endif
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank. This
+ * provides the timing values back to the function that configures
+ * the memory.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ int pop_mfr, pop_id;
+
+ /*
+ * We need to identify what PoP memory is on the board so that
+ * we know what timings to use. To map the ID values please see
+ * nand_ids.c
+ */
+ identify_nand_chip(&pop_mfr, &pop_id);
+
+ if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
+ /* 256MB DDR */
+ timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+ timings->ctrla = HYNIX_V_ACTIMA_200;
+ timings->ctrlb = HYNIX_V_ACTIMB_200;
+ } else {
+ /* 128MB DDR */
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ }
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mr = MICRON_V_MR_165;
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+#endif
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif
+ omap3_evm_get_revision();
+
+#if defined(CONFIG_CMD_NET)
+ reset_net_chip();
+#endif
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_EVM();
+}
+
+#ifdef CONFIG_CMD_NET
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Configure GPMC registers */
+ writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
+ writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
+ writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
+ writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
+ writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
+ writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
+ writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+}
+
+/**
+ * Reset the ethernet chip.
+ */
+static void reset_net_chip(void)
+{
+ int ret;
+ int rst_gpio;
+
+ if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
+ rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
+ } else {
+ rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
+ }
+
+ ret = gpio_request(rst_gpio, "");
+ if (ret < 0) {
+ printf("Unable to get GPIO %d\n", rst_gpio);
+ return ;
+ }
+
+ /* Configure as output */
+ gpio_direction_output(rst_gpio, 0);
+
+ /* Send a pulse on the GPIO pin */
+ gpio_set_value(rst_gpio, 1);
+ udelay(1);
+ gpio_set_value(rst_gpio, 0);
+ udelay(1);
+ gpio_set_value(rst_gpio, 1);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+#define STR_ENV_ETHADDR "ethaddr"
+
+ struct eth_device *dev;
+ uchar eth_addr[6];
+
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+
+ if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
+ dev = eth_get_dev_by_index(0);
+ if (dev) {
+ eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
+ } else {
+ printf("omap3evm: Couldn't get eth device\n");
+ rc = -1;
+ }
+ }
+#endif
+ return rc;
+}
+#endif /* CONFIG_CMD_NET */
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
diff --git a/board/ti/evm/evm.h b/board/ti/evm/evm.h
new file mode 100644
index 0000000..91e9b88
--- /dev/null
+++ b/board/ti/evm/evm.h
@@ -0,0 +1,394 @@
+/*
+ * (C) Copyright 2008
+ * Nishanth Menon <menon.nishanth@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _EVM_H_
+#define _EVM_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 EVM board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+ "OneNAND",
+#else
+ "NAND",
+#endif
+};
+
+/*
+ * OMAP35x EVM revision
+ * Run time detection of EVM revision is done by reading Ethernet
+ * PHY ID -
+ * GEN_1 = 0x01150000
+ * GEN_2 = 0x92200000
+ */
+enum {
+ OMAP3EVM_BOARD_GEN_1 = 0, /* EVM Rev between A - D */
+ OMAP3EVM_BOARD_GEN_2, /* EVM Rev >= Rev E */
+};
+
+u32 get_omap3_evm_rev(void);
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+static void reset_net_chip(void);
+#endif
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_EVM() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
+ /* - ETH_nRESET*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ /* - CAM_RESET*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M0)) /*MMC2_DAT4*/\
+ MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M0)) /*MMC2_DAT5*/\
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M0)) /*MMC2_DAT6 */\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX */\
+ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+ /* - LCD_INI*/\
+ MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+ /* - LCD_ENVDD */\
+ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+ /* - LCD_QVGA/nVGA */\
+ MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+ /* - LCD_RESB */\
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*MCBSP1_CLKR */\
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) /*MCBSP1_FSR*/\
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /*MCBSP1_DX*/\
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*MCBSP1_DR*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*MCBSP_CLKS */\
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*MCBSP1_FSX*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*MCBSP1_CLKX */\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_*/\
+ /* RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
+ /* TS_PEN_IRQ */\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
+ /* - LAN_INTR*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*McSPI1_CS3*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ /* - PEN_IRQ */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+ /* - VIO_1V8*/\
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) /*SYS_CLKOUT2*/\
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) /*ETK_CLK*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) /*ETK_CTL*/\
+ MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D0*/\
+ MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D1*/\
+ MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | EN | M0)) /*ETK_D2*/\
+ MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D3*/\
+ MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D4*/\
+ MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D5*/\
+ MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D6*/\
+ MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D7*/\
+ MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D8*/\
+ MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M0)) /*ETK_D9*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) /*ETK_D10*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) /*ETK_D11*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) /*ETK_D12*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) /*ETK_D13*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) /*ETK_D14*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) /*ETK_D15*/\
+ /*Die to Die */\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\
+
+#endif
diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig
new file mode 100644
index 0000000..384b175
--- /dev/null
+++ b/board/ti/ks2_evm/Kconfig
@@ -0,0 +1,38 @@
+if TARGET_K2E_EVM
+
+config SYS_BOARD
+ default "ks2_evm"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "k2e_evm"
+
+endif
+
+if TARGET_K2HK_EVM
+
+config SYS_BOARD
+ default "ks2_evm"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "k2hk_evm"
+
+endif
+
+if TARGET_K2L_EVM
+
+config SYS_BOARD
+ default "ks2_evm"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "k2l_evm"
+
+endif
diff --git a/board/ti/ks2_evm/MAINTAINERS b/board/ti/ks2_evm/MAINTAINERS
new file mode 100644
index 0000000..87c36c9
--- /dev/null
+++ b/board/ti/ks2_evm/MAINTAINERS
@@ -0,0 +1,10 @@
+KS2_EVM BOARD
+M: Vitaly Andrianov <vitalya@ti.com>
+S: Maintained
+F: board/ti/ks2_evm/
+F: include/configs/k2hk_evm.h
+F: configs/k2hk_evm_defconfig
+F: include/configs/k2e_evm.h
+F: configs/k2e_evm_defconfig
+F: include/configs/k2l_evm.h
+F: configs/k2l_evm_defconfig
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
new file mode 100644
index 0000000..071dbee
--- /dev/null
+++ b/board/ti/ks2_evm/Makefile
@@ -0,0 +1,15 @@
+#
+# KS2-EVM: board Makefile
+# (C) Copyright 2012-2014
+# Texas Instruments Incorporated, <www.ti.com>
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += board.o
+obj-y += ddr3_cfg.o
+obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
+obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
+obj-$(CONFIG_K2E_EVM) += board_k2e.o
+obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
+obj-$(CONFIG_K2L_EVM) += board_k2l.o
+obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README
new file mode 100644
index 0000000..9ee90a4
--- /dev/null
+++ b/board/ti/ks2_evm/README
@@ -0,0 +1,171 @@
+U-Boot port for Texas Instruments Keystone II EVM boards
+========================================================
+
+Author: Murali Karicheri <m-karicheri2@ti.com>
+
+This README has information on the u-boot port for K2HK, K2E, and K2L EVM boards.
+Documentation for this board can be found at
+http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
+https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html
+https://www.einfochips.com/index.php/partnerships/texas-instruments/k2l-evm.html
+
+The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K.
+More details on these SoCs are available at company websites
+ K2K: http://www.ti.com/product/tci6638k2k
+ K2H: http://www.ti.com/product/tci6638k2h
+
+The K2E SoC details are available at
+ http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
+
+The K2L SoC details are available at
+ http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf
+
+Board configuration:
+====================
+
+Some of the peripherals that are configured by u-boot
++------+-------+-------+-----------+-----------+-------+-------+----+
+| |DDR3 |NAND |MSM SRAM |ETH ports |UART |I2C |SPI |
++------+-------+-------+-----------+-----------+-------+-------+----+
+|K2HK |2 |512MB |6MB |4(2) |2 |3 |3 |
+|K2E |4 |512MB |2MB |8(2) |2 |3 |3 |
+|K2L |2 |512MB |2MB |4(2) |4 |3 |3 |
++------+-------+-------+-----------+-----------+-------+-------+----+
+
+There are only 2 eth port installed on the boards.
+
+There are separate PLLs to drive clocks to Tetris ARM and Peripherals.
+To bring up SMP Linux on this board, there is a boot monitor
+code that will be installed in MSMC SRAM. There is command available
+to install this image from u-boot.
+
+The port related files can be found at following folders
+ keystone2 SoC related files: arch/arm/cpu/armv7/keystone/
+ EVMs board files: board/ti/k2s_evm/
+
+Board configuration files:
+include/configs/k2hk_evm.h
+include/configs/k2e_evm.h
+include/configs/k2l_evm.h
+include/configs/k2l_evm.h
+
+As u-boot is migrating to Kconfig there is also board defconfig files
+configs/k2e_evm_defconfig
+configs/k2hk_evm_defconfig
+configs/k2l_evm_defconfig
+
+Supported boot modes:
+ - SPI NOR boot
+ - AEMIF NAND boot
+
+Supported image formats:
+ - u-boot.bin: for loading and running u-boot.bin through Texas instruments
+ code composure studio (CCS)
+ - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
+ - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot
+
+Build instructions:
+===================
+Examples for k2hk, for k2e and k2l just replace k2hk prefix accordingly.
+Don't forget to add ARCH=arm and CROSS_COMPILE.
+
+To build u-boot.bin
+ >make k2hk_evm_defconfig
+ >make u-boot-spi.gph
+
+To build u-boot-spi.gph
+ >make k2hk_evm_defconfig
+ >make u-boot-spi.gph
+
+To build u-boot-nand.gph
+ >make k2hk_evm_defconfig
+ >make u-boot-nand.gph
+
+Load and Run U-Boot on keystone EVMs using CCS
+=========================================
+
+Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin
+on EVM. See instructions at below link for installing CCS on a Windows PC.
+http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started#
+Installing_Code_Composer_Studio
+Use u-boot.bin from the build folder for loading and running u-boot binary
+on EVM. Follow instructions at
+K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
+K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup
+K2L http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup
+
+to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
+and Power ON the EVM. Follow instructions to connect serial port of EVM to
+PC and start TeraTerm or Hyper Terminal.
+
+Start CCS on a Windows machine and Launch Target
+configuration as instructed at http://processors.wiki.ti.com/index.php/
+MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS.
+The instructions provided in the above link uses a script for
+loading the u-boot binary on the target EVM. Instead do the following:-
+
+1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D
+ is connected: Unknown)" at the debug window (This is created once Target
+ configuration is launched) and select "Connect Target".
+2. Once target connect is successful, choose Tools->Load Memory option from the
+ top level menu. At the Load Memory window, choose the file u-boot.bin
+ through "Browse" button and click "next >" button. In the next window, enter
+ Start address as 0xc001000, choose Type-size "32 bits" and click "Finish"
+ button.
+3. Click View -> Registers from the top level menu to view registers window.
+4. From Registers, window expand "Core Registers" to view PC. Edit PC value
+ to be 0xc001000. From the "Run" top level menu, select "Free Run"
+5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as
+ below and type any key to stop autoboot as instructed :=
+
+U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59)
+
+I2C: ready
+Detected SO-DIMM [SQR-SD3T-2G1333SED]
+DRAM: 1.1 GiB
+NAND: 512 MiB
+Net: K2HK_EMAC
+Warning: K2HK_EMAC using MAC address from net device
+, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3
+Hit any key to stop autoboot: 0
+
+SPI NOR Flash programming instructions
+======================================
+U-Boot image can be flashed to first 512KB of the NOR flash using following
+instructions:
+
+1. Start CCS and run U-boot as described above.
+2. Suspend Target. Select Run -> Suspend from top level menu
+ CortexA15_1 (Free Running)"
+3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
+ through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E/K2L
+ EVM using CCS", but using address 0x87000000.
+4. Free Run the target as described earlier (step 4) to get u-boot prompt
+5. At the U-Boot console type following to setup u-boot environment variables.
+ setenv addr_uboot 0x87000000
+ setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
+ run burn_uboot_spi
+ Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
+ to "SPI Little Endian Boot mode" as per instruction at
+ http://processors.wiki.ti.com/index.php/*_Hardware_Setup.
+6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash.
+
+AEMIF NAND Flash programming instructions
+======================================
+U-Boot image can be flashed to first 1024KB of the NAND flash using following
+instructions:
+
+1. Start CCS and run U-boot as described above.
+2. Suspend Target. Select Run -> Suspend from top level menu
+ CortexA15_1 (Free Running)"
+3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000
+ through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM
+ using CCS", but using address 0x87000000.
+4. Free Run the target as described earlier (step 4) to get u-boot prompt
+5. At the U-Boot console type following to setup u-boot environment variables.
+ setenv filesize <size in hex of u-boot-nand.gph rounded to hex 0x10000>
+ run burn_uboot_nand
+ Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch
+ to "ARM NAND Boot mode" as per instruction at
+ http://processors.wiki.ti.com/index.php/*_Hardware_Setup.
+6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash.
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
new file mode 100644
index 0000000..04ec675
--- /dev/null
+++ b/board/ti/ks2_evm/board.c
@@ -0,0 +1,260 @@
+/*
+ * Keystone : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "board.h"
+#include <common.h>
+#include <spl.h>
+#include <exports.h>
+#include <fdt_support.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/ti-common/ti-aemif.h>
+#include <asm/ti-common/keystone_net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct aemif_config aemif_configs[] = {
+ { /* CS0 */
+ .mode = AEMIF_MODE_NAND,
+ .wr_setup = 0xf,
+ .wr_strobe = 0x3f,
+ .wr_hold = 7,
+ .rd_setup = 0xf,
+ .rd_strobe = 0x3f,
+ .rd_hold = 7,
+ .turn_around = 3,
+ .width = AEMIF_WIDTH_8,
+ },
+};
+
+int dram_init(void)
+{
+ ddr3_init();
+
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_MAX_RAM_BANK_SIZE);
+ aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+ ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE);
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR;
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+int get_eth_env_param(char *env_name)
+{
+ char *env;
+ int res = -1;
+
+ env = getenv(env_name);
+ if (env)
+ res = simple_strtol(env, NULL, 0);
+
+ return res;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int j;
+ int res;
+ int port_num;
+ char link_type_name[32];
+
+ /* By default, select PA PLL clock as PA clock source */
+ if (psc_enable_module(KS2_LPSC_PA))
+ return -1;
+ if (psc_enable_module(KS2_LPSC_CPGMAC))
+ return -1;
+ if (psc_enable_module(KS2_LPSC_CRYPTO))
+ return -1;
+ pass_pll_pa_clk_enable();
+
+ port_num = get_num_eth_ports();
+
+ for (j = 0; j < port_num; j++) {
+ sprintf(link_type_name, "sgmii%d_link_type", j);
+ res = get_eth_env_param(link_type_name);
+ if (res >= 0)
+ eth_priv_cfg[j].sgmii_link_type = res;
+
+ keystone2_emac_initialize(ð_priv_cfg[j]);
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+ spl_init_keystone_plls();
+ preloader_console_init();
+}
+
+u32 spl_boot_device(void)
+{
+#if defined(CONFIG_SPL_SPI_LOAD)
+ return BOOT_DEVICE_SPI;
+#else
+ puts("Unknown boot device\n");
+ hang();
+#endif
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int lpae;
+ char *env;
+ char *endp;
+ int nbanks;
+ u64 size[2];
+ u64 start[2];
+ int nodeoffset;
+ u32 ddr3a_size;
+ int unitrd_fixup = 0;
+
+ env = getenv("mem_lpae");
+ lpae = env && simple_strtol(env, NULL, 0);
+ env = getenv("uinitrd_fixup");
+ unitrd_fixup = env && simple_strtol(env, NULL, 0);
+
+ ddr3a_size = 0;
+ if (lpae) {
+ env = getenv("ddr3a_size");
+ if (env)
+ ddr3a_size = simple_strtol(env, NULL, 10);
+ if ((ddr3a_size != 8) && (ddr3a_size != 4))
+ ddr3a_size = 0;
+ }
+
+ nbanks = 1;
+ start[0] = bd->bi_dram[0].start;
+ size[0] = bd->bi_dram[0].size;
+
+ /* adjust memory start address for LPAE */
+ if (lpae) {
+ start[0] -= CONFIG_SYS_SDRAM_BASE;
+ start[0] += CONFIG_SYS_LPAE_SDRAM_BASE;
+ }
+
+ if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
+ size[1] = ((u64)ddr3a_size - 2) << 30;
+ start[1] = 0x880000000;
+ nbanks++;
+ }
+
+ /* reserve memory at start of bank */
+ env = getenv("mem_reserve_head");
+ if (env) {
+ start[0] += ustrtoul(env, &endp, 0);
+ size[0] -= ustrtoul(env, &endp, 0);
+ }
+
+ env = getenv("mem_reserve");
+ if (env)
+ size[0] -= ustrtoul(env, &endp, 0);
+
+ fdt_fixup_memory_banks(blob, start, size, nbanks);
+
+ /* Fix up the initrd */
+ if (lpae && unitrd_fixup) {
+ int err;
+ u32 *prop1, *prop2;
+ u64 initrd_start, initrd_end;
+
+ nodeoffset = fdt_path_offset(blob, "/chosen");
+ if (nodeoffset >= 0) {
+ prop1 = (u32 *)fdt_getprop(blob, nodeoffset,
+ "linux,initrd-start", NULL);
+ prop2 = (u32 *)fdt_getprop(blob, nodeoffset,
+ "linux,initrd-end", NULL);
+ if (prop1 && prop2) {
+ initrd_start = __be32_to_cpu(*prop1);
+ initrd_start -= CONFIG_SYS_SDRAM_BASE;
+ initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_start = __cpu_to_be64(initrd_start);
+ initrd_end = __be32_to_cpu(*prop2);
+ initrd_end -= CONFIG_SYS_SDRAM_BASE;
+ initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE;
+ initrd_end = __cpu_to_be64(initrd_end);
+
+ err = fdt_delprop(blob, nodeoffset,
+ "linux,initrd-start");
+ if (err < 0)
+ puts("error deleting initrd-start\n");
+
+ err = fdt_delprop(blob, nodeoffset,
+ "linux,initrd-end");
+ if (err < 0)
+ puts("error deleting initrd-end\n");
+
+ err = fdt_setprop(blob, nodeoffset,
+ "linux,initrd-start",
+ &initrd_start,
+ sizeof(initrd_start));
+ if (err < 0)
+ puts("error adding initrd-start\n");
+
+ err = fdt_setprop(blob, nodeoffset,
+ "linux,initrd-end",
+ &initrd_end,
+ sizeof(initrd_end));
+ if (err < 0)
+ puts("error adding linux,initrd-end\n");
+ }
+ }
+ }
+
+ return 0;
+}
+
+void ft_board_setup_ex(void *blob, bd_t *bd)
+{
+ int lpae;
+ u64 size;
+ char *env;
+ u64 *reserve_start;
+
+ env = getenv("mem_lpae");
+ lpae = env && simple_strtol(env, NULL, 0);
+
+ if (lpae) {
+ /*
+ * the initrd and other reserved memory areas are
+ * embedded in in the DTB itslef. fix up these addresses
+ * to 36 bit format
+ */
+ reserve_start = (u64 *)((char *)blob +
+ fdt_off_mem_rsvmap(blob));
+ while (1) {
+ *reserve_start = __cpu_to_be64(*reserve_start);
+ size = __cpu_to_be64(*(reserve_start + 1));
+ if (size) {
+ *reserve_start -= CONFIG_SYS_SDRAM_BASE;
+ *reserve_start +=
+ CONFIG_SYS_LPAE_SDRAM_BASE;
+ *reserve_start =
+ __cpu_to_be64(*reserve_start);
+ } else {
+ break;
+ }
+ reserve_start += 2;
+ }
+ }
+
+ ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
+}
+#endif
diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
new file mode 100644
index 0000000..2bbd792
--- /dev/null
+++ b/board/ti/ks2_evm/board.h
@@ -0,0 +1,20 @@
+/*
+ * K2HK EVM : Board common header
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _KS2_BOARD
+#define _KS2_BOARD
+
+#include <asm/ti-common/keystone_net.h>
+
+extern struct eth_priv_t eth_priv_cfg[];
+
+int get_num_eth_ports(void);
+void spl_init_keystone_plls(void);
+
+#endif
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
new file mode 100644
index 0000000..43dfc48
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -0,0 +1,131 @@
+/*
+ * K2E EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/keystone_net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 100000000,
+ [alt_core_clk] = 100000000,
+ [pa_clk] = 100000000,
+ [ddr3_clk] = 100000000,
+ [mcm_clk] = 312500000,
+ [pcie_clk] = 100000000,
+ [sgmii_clk] = 156250000,
+ [xgmii_clk] = 156250000,
+ [usb_clk] = 100000000,
+};
+
+static struct pll_init_data core_pll_config[] = {
+ CORE_PLL_800,
+ CORE_PLL_850,
+ CORE_PLL_1000,
+ CORE_PLL_1250,
+ CORE_PLL_1350,
+ CORE_PLL_1400,
+ CORE_PLL_1500,
+};
+
+static struct pll_init_data pa_pll_config =
+ PASS_PLL_1000;
+
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+ {
+ .int_name = "K2E_EMAC0",
+ .rx_flow = 0,
+ .phy_addr = 0,
+ .slave_port = 1,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2E_EMAC1",
+ .rx_flow = 8,
+ .phy_addr = 1,
+ .slave_port = 2,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2E_EMAC2",
+ .rx_flow = 16,
+ .phy_addr = 2,
+ .slave_port = 3,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2E_EMAC3",
+ .rx_flow = 24,
+ .phy_addr = 3,
+ .slave_port = 4,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2E_EMAC4",
+ .rx_flow = 32,
+ .phy_addr = 4,
+ .slave_port = 5,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2E_EMAC5",
+ .rx_flow = 40,
+ .phy_addr = 5,
+ .slave_port = 6,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2E_EMAC6",
+ .rx_flow = 48,
+ .phy_addr = 6,
+ .slave_port = 7,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2E_EMAC7",
+ .rx_flow = 56,
+ .phy_addr = 7,
+ .slave_port = 8,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+};
+
+int get_num_eth_ports(void)
+{
+ return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+ int speed;
+
+ speed = get_max_dev_speed();
+ init_pll(&core_pll_config[speed]);
+
+ init_pll(&pa_pll_config);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_800,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
new file mode 100644
index 0000000..ed181f4
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -0,0 +1,114 @@
+/*
+ * K2HK EVM : Board initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/keystone_net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 122880000,
+ [alt_core_clk] = 125000000,
+ [pa_clk] = 122880000,
+ [tetris_clk] = 125000000,
+ [ddr3a_clk] = 100000000,
+ [ddr3b_clk] = 100000000,
+ [mcm_clk] = 312500000,
+ [pcie_clk] = 100000000,
+ [sgmii_srio_clk] = 156250000,
+ [xgmii_clk] = 156250000,
+ [usb_clk] = 100000000,
+ [rp1_clk] = 123456789
+};
+
+static struct pll_init_data core_pll_config[] = {
+ CORE_PLL_799,
+ CORE_PLL_999,
+ CORE_PLL_1200,
+};
+
+static struct pll_init_data tetris_pll_config[] = {
+ TETRIS_PLL_800,
+ TETRIS_PLL_1000,
+ TETRIS_PLL_1200,
+ TETRIS_PLL_1350,
+ TETRIS_PLL_1400,
+};
+
+static struct pll_init_data pa_pll_config =
+ PASS_PLL_983;
+
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+ {
+ .int_name = "K2HK_EMAC",
+ .rx_flow = 22,
+ .phy_addr = 0,
+ .slave_port = 1,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2HK_EMAC1",
+ .rx_flow = 23,
+ .phy_addr = 1,
+ .slave_port = 2,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2HK_EMAC2",
+ .rx_flow = 24,
+ .phy_addr = 2,
+ .slave_port = 3,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2HK_EMAC3",
+ .rx_flow = 25,
+ .phy_addr = 3,
+ .slave_port = 4,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+};
+
+int get_num_eth_ports(void)
+{
+ return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ int speed;
+
+ speed = get_max_dev_speed();
+ init_pll(&core_pll_config[speed]);
+
+ init_pll(&pa_pll_config);
+
+ speed = get_max_arm_speed();
+ init_pll(&tetris_pll_config[speed]);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_799,
+ TETRIS_PLL_500,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
new file mode 100644
index 0000000..729a193
--- /dev/null
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -0,0 +1,110 @@
+/*
+ * K2L EVM : Board initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+#include <asm/ti-common/keystone_net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int external_clk[ext_clk_count] = {
+ [sys_clk] = 122880000,
+ [alt_core_clk] = 100000000,
+ [pa_clk] = 122880000,
+ [tetris_clk] = 122880000,
+ [ddr3_clk] = 100000000,
+ [pcie_clk] = 100000000,
+ [sgmii_clk] = 156250000,
+ [usb_clk] = 100000000,
+};
+
+static struct pll_init_data core_pll_config[] = {
+ CORE_PLL_799,
+ CORE_PLL_1000,
+ CORE_PLL_1198,
+};
+
+static struct pll_init_data tetris_pll_config[] = {
+ TETRIS_PLL_799,
+ TETRIS_PLL_1000,
+ TETRIS_PLL_1198,
+ TETRIS_PLL_1352,
+ TETRIS_PLL_1401,
+};
+
+static struct pll_init_data pa_pll_config =
+ PASS_PLL_983;
+
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+ {
+ .int_name = "K2L_EMAC",
+ .rx_flow = 0,
+ .phy_addr = 0,
+ .slave_port = 1,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2L_EMAC1",
+ .rx_flow = 8,
+ .phy_addr = 1,
+ .slave_port = 2,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2L_EMAC2",
+ .rx_flow = 16,
+ .phy_addr = 2,
+ .slave_port = 3,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2L_EMAC3",
+ .rx_flow = 32,
+ .phy_addr = 3,
+ .slave_port = 4,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+};
+
+int get_num_eth_ports(void)
+{
+ return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ int speed;
+
+ speed = get_max_dev_speed();
+ init_pll(&core_pll_config[speed]);
+
+ init_pll(&pa_pll_config);
+
+ speed = get_max_arm_speed();
+ init_pll(&tetris_pll_config[speed]);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+static struct pll_init_data spl_pll_config[] = {
+ CORE_PLL_799,
+ TETRIS_PLL_491,
+};
+
+void spl_init_keystone_plls(void)
+{
+ init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+}
+#endif
diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c
new file mode 100644
index 0000000..ab44676
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_cfg.c
@@ -0,0 +1,206 @@
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <i2c.h>
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* DDR3 PHY configuration data with 1600M rate, 8GB size */
+struct ddr3_phy_config ddr3phy_1600_8g = {
+ .pllcr = 0x0001C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0D861A80ul,
+ .ptr4 = 0x0C827100ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0xA19DBB66ul,
+ .dtpr1 = 0x32868300ul,
+ .dtpr2 = 0x50035200ul,
+ .mr0 = 0x00001C70ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x730035C7ul,
+ .pgcr2 = 0x00F07A12ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1600M rate, 8GB size */
+struct ddr3_emif_config ddr3_1600_8g = {
+ .sdcfg = 0x6200CE6Aul,
+ .sdtim1 = 0x16709C55ul,
+ .sdtim2 = 0x00001D4Aul,
+ .sdtim3 = 0x435DFF54ul,
+ .sdtim4 = 0x553F0CFFul,
+ .zqcfg = 0xF0073200ul,
+ .sdrfc = 0x00001869ul,
+};
+
+#ifdef CONFIG_K2HK_EVM
+/* DDR3 PHY configuration data with 1333M rate, and 2GB size */
+struct ddr3_phy_config ddr3phy_1333_2g = {
+ .pllcr = 0x0005C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0B4515C2ul,
+ .ptr4 = 0x0A6E08B4ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x8558AA55ul,
+ .dtpr1 = 0x32857280ul,
+ .dtpr2 = 0x5002C200ul,
+ .mr0 = 0x00001A60ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000010ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F065B8ul,
+ .zq0cr1 = 0x0000005Dul,
+ .zq1cr1 = 0x0000005Bul,
+ .zq2cr1 = 0x0000005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */
+struct ddr3_emif_config ddr3_1333_2g = {
+ .sdcfg = 0x62008C62ul,
+ .sdtim1 = 0x125C8044ul,
+ .sdtim2 = 0x00001D29ul,
+ .sdtim3 = 0x32CDFF43ul,
+ .sdtim4 = 0x543F0ADFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001457ul,
+};
+#endif
+
+#ifdef CONFIG_K2E_EVM
+/* DDR3 PHY configuration data with 1600M rate, and 4GB size */
+struct ddr3_phy_config ddr3phy_1600_4g = {
+ .pllcr = 0x0001C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x08861A80ul,
+ .ptr4 = 0x0C827100ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x9D9CBB66ul,
+ .dtpr1 = 0x12840300ul,
+ .dtpr2 = 0x5002D200ul,
+ .mr0 = 0x00001C70ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F07A12ul,
+ .zq0cr1 = 0x0001005Dul,
+ .zq1cr1 = 0x0001005Bul,
+ .zq2cr1 = 0x0001005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+/* DDR3 EMIF configuration data with 1600M rate, and 4GB size */
+struct ddr3_emif_config ddr3_1600_4g = {
+ .sdcfg = 0x6200CE62ul,
+ .sdtim1 = 0x166C9855ul,
+ .sdtim2 = 0x00001D4Aul,
+ .sdtim3 = 0x421DFF53ul,
+ .sdtim4 = 0x543F07FFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001869ul,
+};
+#endif
+
+struct ddr3_phy_config ddr3phy_1600_2g = {
+ .pllcr = 0x0001C000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0, /* not set in gel */
+ .ptr3 = 0x0D861A80ul,
+ .ptr4 = 0x0C827100ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x9D5CBB66ul,
+ .dtpr1 = 0x12868300ul,
+ .dtpr2 = 0x5002D200ul,
+ .mr0 = 0x00001C70ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F07A12ul,
+ .zq0cr1 = 0x0001005Dul,
+ .zq1cr1 = 0x0001005Bul,
+ .zq2cr1 = 0x0001005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x0000FF81ul,
+};
+
+struct ddr3_emif_config ddr3_1600_2g = {
+ .sdcfg = 0x6200CE62ul,
+ .sdtim1 = 0x166C9855ul,
+ .sdtim2 = 0x00001D4Aul,
+ .sdtim3 = 0x435DFF53ul,
+ .sdtim4 = 0x543F0CFFul,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00001869ul,
+};
+
+int ddr3_get_dimm_params(char *dimm_name)
+{
+ int ret;
+ int old_bus;
+ u8 spd_params[256];
+
+ i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
+
+ old_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ ret = i2c_read(0x53, 0, 1, spd_params, 256);
+
+ i2c_set_bus_num(old_bus);
+
+ dimm_name[0] = '\0';
+
+ if (ret) {
+ puts("Cannot read DIMM params\n");
+ return 1;
+ }
+
+ /*
+ * We need to convert spd data to dimm parameters
+ * and to DDR3 EMIF and PHY regirsters values.
+ * For now we just return DIMM type string value.
+ * Caller may use this value to choose appropriate
+ * a pre-set DDR3 configuration
+ */
+
+ strncpy(dimm_name, (char *)&spd_params[0x80], 18);
+ dimm_name[18] = '\0';
+
+ return 0;
+}
diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h
new file mode 100644
index 0000000..5bd786c
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_cfg.h
@@ -0,0 +1,27 @@
+/*
+ * Keystone2: DDR3 configuration
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR3_CFG_H
+#define __DDR3_CFG_H
+
+extern struct ddr3_phy_config ddr3phy_1600_8g;
+extern struct ddr3_emif_config ddr3_1600_8g;
+
+extern struct ddr3_phy_config ddr3phy_1333_2g;
+extern struct ddr3_emif_config ddr3_1333_2g;
+
+extern struct ddr3_phy_config ddr3phy_1600_4g;
+extern struct ddr3_emif_config ddr3_1600_4g;
+
+extern struct ddr3_phy_config ddr3phy_1600_2g;
+extern struct ddr3_emif_config ddr3_1600_2g;
+
+int ddr3_get_dimm_params(char *dimm_name);
+
+#endif /* __DDR3_CFG_H */
diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c
new file mode 100644
index 0000000..40fd966
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_k2e.c
@@ -0,0 +1,55 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+
+static int ddr3_size;
+static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+
+void ddr3_init(void)
+{
+ char dimm_name[32];
+
+ if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
+ init_pll(&ddr3_400);
+
+ ddr3_get_dimm_params(dimm_name);
+
+ printf("Detected SO-DIMM [%s]\n", dimm_name);
+
+ /* Reset DDR3 PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+
+ if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
+ /* 8G SO-DIMM */
+ ddr3_size = 8;
+ printf("DRAM: 8 GiB\n");
+ ddr3phy_1600_8g.zq0cr1 |= 0x10000;
+ ddr3phy_1600_8g.zq1cr1 |= 0x10000;
+ ddr3phy_1600_8g.zq2cr1 |= 0x10000;
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g);
+ } else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) {
+ /* 4G SO-DIMM */
+ ddr3_size = 4;
+ printf("DRAM: 4 GiB\n");
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
+ }
+}
+
+/**
+ * ddr3_get_size - return ddr3 size in GiB
+ */
+int ddr3_get_size(void)
+{
+ return ddr3_size;
+}
diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c
new file mode 100644
index 0000000..a1c3d05
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_k2hk.c
@@ -0,0 +1,104 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+#include <asm/arch/hardware.h>
+
+static int ddr3_size;
+
+struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
+struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
+
+void ddr3_init(void)
+{
+ char dimm_name[32];
+
+ ddr3_get_dimm_params(dimm_name);
+
+ printf("Detected SO-DIMM [%s]\n", dimm_name);
+
+ if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
+ init_pll(&ddr3a_400);
+ if (cpu_revision() > 0) {
+ if (cpu_revision() > 1) {
+ /* PG 2.0 */
+ /* Reset DDR3A PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+ ddr3phy_1600_8g.zq0cr1 |= 0x10000;
+ ddr3phy_1600_8g.zq1cr1 |= 0x10000;
+ ddr3phy_1600_8g.zq2cr1 |= 0x10000;
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+ &ddr3phy_1600_8g);
+ } else {
+ /* PG 1.1 */
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+ &ddr3phy_1600_8g);
+ }
+
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1600_8g);
+ printf("DRAM: Capacity 8 GiB (includes reported below)\n");
+ ddr3_size = 8;
+ } else {
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
+ ddr3_1600_8g.sdcfg |= 0x1000;
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1600_8g);
+ printf("DRAM: Capacity 4 GiB (includes reported below)\n");
+ ddr3_size = 4;
+ }
+ } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
+ init_pll(&ddr3a_333);
+ if (cpu_revision() > 0) {
+ if (cpu_revision() > 1) {
+ /* PG 2.0 */
+ /* Reset DDR3A PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+ ddr3phy_1333_2g.zq0cr1 |= 0x10000;
+ ddr3phy_1333_2g.zq1cr1 |= 0x10000;
+ ddr3phy_1333_2g.zq2cr1 |= 0x10000;
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+ &ddr3phy_1333_2g);
+ } else {
+ /* PG 1.1 */
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
+ &ddr3phy_1333_2g);
+ }
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1333_2g);
+ ddr3_size = 2;
+ printf("DRAM: 2 GiB");
+ } else {
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
+ ddr3_1333_2g.sdcfg |= 0x1000;
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
+ &ddr3_1333_2g);
+ ddr3_size = 1;
+ printf("DRAM: 1 GiB");
+ }
+ } else {
+ printf("Unknown SO-DIMM. Cannot configure DDR3\n");
+ while (1)
+ ;
+ }
+
+ /* Apply the workaround for PG 1.0 and 1.1 Silicons */
+ if (cpu_revision() <= 1)
+ ddr3_err_reset_workaround();
+}
+
+/**
+ * ddr3_get_size - return ddr3 size in GiB
+ */
+int ddr3_get_size(void)
+{
+ return ddr3_size;
+}
diff --git a/board/ti/ks2_evm/ddr3_k2l.c b/board/ti/ks2_evm/ddr3_k2l.c
new file mode 100644
index 0000000..15a14f2
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_k2l.c
@@ -0,0 +1,38 @@
+/*
+ * Keystone2: DDR3 initialization
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+
+static int ddr3_size;
+static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+
+void ddr3_init(void)
+{
+ init_pll(&ddr3_400);
+
+ /* No SO-DIMM, 2GB discreet DDR */
+ printf("DRAM: 2 GiB\n");
+ ddr3_size = 2;
+
+ /* Reset DDR3 PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);
+}
+
+/**
+ * ddr3_get_size - return ddr3 size in GiB
+ */
+int ddr3_get_size(void)
+{
+ return ddr3_size;
+}
diff --git a/board/ti/omap5_uevm/Kconfig b/board/ti/omap5_uevm/Kconfig
new file mode 100644
index 0000000..aa13844
--- /dev/null
+++ b/board/ti/omap5_uevm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP5_UEVM
+
+config SYS_BOARD
+ default "omap5_uevm"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "omap5_uevm"
+
+endif
diff --git a/board/ti/omap5_uevm/MAINTAINERS b/board/ti/omap5_uevm/MAINTAINERS
new file mode 100644
index 0000000..280ea2f
--- /dev/null
+++ b/board/ti/omap5_uevm/MAINTAINERS
@@ -0,0 +1,6 @@
+OMAP5_UEVM BOARD
+M: Lokesh Vutla <lokeshvutla@ti.com>
+S: Maintained
+F: board/ti/omap5_uevm/
+F: include/configs/omap5_uevm.h
+F: configs/omap5_uevm_defconfig
diff --git a/board/ti/omap5_uevm/Makefile b/board/ti/omap5_uevm/Makefile
new file mode 100644
index 0000000..b88ab8f
--- /dev/null
+++ b/board/ti/omap5_uevm/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := evm.o
diff --git a/board/ti/omap5_uevm/README b/board/ti/omap5_uevm/README
new file mode 100644
index 0000000..970e2ec
--- /dev/null
+++ b/board/ti/omap5_uevm/README
@@ -0,0 +1,25 @@
+Summary
+=======
+
+This document covers various features of the 'omap5_uevm' build and some
+related uses.
+
+eMMC boot partition use
+=======================
+
+It is possible, depending on SYSBOOT configuration to boot from the eMMC
+boot partitions using (name depending on documentation referenced)
+Alternative Boot operation mode or Boot Sequence Option 1/2. In this
+example we load MLO and u-boot.img from the build into DDR and then use
+'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
+set boot0 as the boot device.
+U-Boot # setenv autoload no
+U-Boot # usb start
+U-Boot # dhcp
+U-Boot # mmc dev 1 1
+U-Boot # tftp ${loadaddr} omap5uevm/MLO
+U-Boot # mmc write ${loadaddr} 0 100
+U-Boot # tftp ${loadaddr} omap5uevm/u-boot.img
+U-Boot # mmc write ${loadaddr} 300 400
+U-Boot # mmc bootbus 1 2 0 2
+U-Boot # mmc partconf 1 1 1 0
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
new file mode 100644
index 0000000..833ffe9
--- /dev/null
+++ b/board/ti/omap5_uevm/evm.c
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <palmas.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <tca642x.h>
+
+#include "mux_data.h"
+
+#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
+#include <sata.h>
+#include <usb.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ehci.h>
+#include <asm/ehci-omap.h>
+#include <asm/arch/sata.h>
+
+#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
+#define DIE_ID_REG_OFFSET 0x200
+
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: OMAP5432 uEVM\n"
+};
+
+/**
+ * @brief tca642x_init - uEVM default values for the GPIO expander
+ * input reg, output reg, polarity reg, configuration reg
+ */
+struct tca642x_bank_info tca642x_init[] = {
+ { .input_reg = 0x00,
+ .output_reg = 0x04,
+ .polarity_reg = 0x00,
+ .configuration_reg = 0x80 },
+ { .input_reg = 0x00,
+ .output_reg = 0x00,
+ .polarity_reg = 0x00,
+ .configuration_reg = 0xff },
+ { .input_reg = 0x00,
+ .output_reg = 0x00,
+ .polarity_reg = 0x00,
+ .configuration_reg = 0x40 },
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gpmc_init();
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
+ gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+ tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
+static void enable_host_clocks(void)
+{
+ int auxclk;
+ int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
+ OPTFCLKEN_HSIC480M_P3_CLK |
+ OPTFCLKEN_HSIC60M_P2_CLK |
+ OPTFCLKEN_HSIC480M_P2_CLK |
+ OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
+
+ /* Enable port 2 and 3 clocks*/
+ setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
+
+ /* Enable port 2 and 3 usb host ports tll clocks*/
+ setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
+ (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
+#ifdef CONFIG_USB_XHCI_OMAP
+ /* Enable the USB OTG Super speed clocks */
+ setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
+ (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW));
+#endif
+
+ auxclk = readl((*prcm)->scrm_auxclk1);
+ /* Request auxilary clock */
+ auxclk |= AUXCLK_ENABLE_MASK;
+ writel(auxclk, (*prcm)->scrm_auxclk1);
+}
+#endif
+
+/**
+ * @brief misc_init_r - Configure EVM board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+ int reg;
+ u32 id[4];
+
+#ifdef CONFIG_PALMAS_POWER
+ palmas_init_settings();
+#endif
+
+ reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
+
+ id[0] = readl(reg);
+ id[1] = readl(reg + 0x8);
+ id[2] = readl(reg + 0xC);
+ id[3] = readl(reg + 0x10);
+ usb_fake_mac_from_die_id(id);
+
+ return 0;
+}
+
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_essential,
+ sizeof(wkup_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
+ .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ int ret;
+
+ enable_host_clocks();
+
+ ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+ if (ret < 0) {
+ puts("Failed to initialize ehci\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+ int ret;
+
+ ret = omap_ehci_hcd_stop();
+ return ret;
+}
+
+void usb_hub_reset_devices(int port)
+{
+ /* The LAN9730 needs to be reset after the port power has been set. */
+ if (port == 3) {
+ gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
+ udelay(10);
+ gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
+ }
+}
+#endif
+
+#ifdef CONFIG_USB_XHCI_OMAP
+/**
+ * @brief board_usb_init - Configure EVM board specific configurations
+ * for the LDO's and clocks for the USB blocks.
+ *
+ * @return 0
+ */
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int ret;
+#ifdef CONFIG_PALMAS_USB_SS_PWR
+ ret = palmas_enable_ss_ldo();
+#endif
+
+ enable_host_clocks();
+
+ return 0;
+}
+#endif
diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h
new file mode 100644
index 0000000..de7ce9f
--- /dev/null
+++ b/board/ti/omap5_uevm/mux_data.h
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _EVM5430_MUX_DATA_H
+#define _EVM5430_MUX_DATA_H
+
+#include <asm/arch/mux_omap5.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+ {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
+ {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
+ {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */
+ {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */
+ {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */
+ {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */
+ {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */
+ {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */
+ {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */
+ {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */
+ {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */
+ {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */
+ {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0*/
+ {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1*/
+ {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2*/
+ {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/
+ {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */
+ {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */
+ {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */
+ {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */
+ {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */
+ {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */
+ {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/
+ {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */
+ {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */
+ {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */
+ {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */
+ {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
+ {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
+ {HSI2_ACWAKE, (PTU | M6)}, /* HSI2_ACWAKE */
+ {HSI2_CAFLAG, (PTU | M6)}, /* HSI2_CAFLAG */
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+ {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
+ {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
+ {SYS_32K, (IEN | M0)}, /* SYS_32K */
+ {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */
+
+};
+
+#endif /* _EVM4430_MUX_DATA_H */
diff --git a/board/ti/panda/Kconfig b/board/ti/panda/Kconfig
new file mode 100644
index 0000000..8f277b6
--- /dev/null
+++ b/board/ti/panda/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP4_PANDA
+
+config SYS_BOARD
+ default "panda"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "omap4_panda"
+
+endif
diff --git a/board/ti/panda/MAINTAINERS b/board/ti/panda/MAINTAINERS
new file mode 100644
index 0000000..2142368
--- /dev/null
+++ b/board/ti/panda/MAINTAINERS
@@ -0,0 +1,6 @@
+PANDA BOARD
+M: Lokesh Vutla <lokeshvutla@ti.com>
+S: Maintained
+F: board/ti/panda/
+F: include/configs/omap4_panda.h
+F: configs/omap4_panda_defconfig
diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile
new file mode 100644
index 0000000..c89f80d
--- /dev/null
+++ b/board/ti/panda/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := panda.o
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
new file mode 100644
index 0000000..783ba35
--- /dev/null
+++ b/board/ti/panda/panda.c
@@ -0,0 +1,339 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+
+#include "panda_mux_data.h"
+
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/arch/ehci.h>
+#include <asm/ehci-omap.h>
+#endif
+
+#define PANDA_ULPI_PHY_TYPE_GPIO 182
+#define PANDA_BOARD_ID_1_GPIO 101
+#define PANDA_ES_BOARD_ID_1_GPIO 48
+#define PANDA_BOARD_ID_2_GPIO 171
+#define PANDA_ES_BOARD_ID_3_GPIO 3
+#define PANDA_ES_BOARD_ID_4_GPIO 2
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: OMAP4 Panda\n"
+};
+
+struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gpmc_init();
+
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
+ gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+/*
+* Routine: get_board_revision
+* Description: Detect if we are running on a panda revision A1-A6,
+* or an ES panda board. This can be done by reading
+* the level of GPIOs and checking the processor revisions.
+* This should result in:
+* Panda 4430:
+* GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
+* GPIO171, GPIO101, GPIO182: 1 0 1 => A6
+* Panda ES:
+* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
+* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
+*/
+int get_board_revision(void)
+{
+ int board_id0, board_id1, board_id2;
+ int board_id3, board_id4;
+ int board_id;
+
+ int processor_rev = omap_revision();
+
+ /* Setup the mux for the common board ID pins (gpio 171 and 182) */
+ writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
+ writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);
+
+ board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
+ board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
+
+ if ((processor_rev >= OMAP4460_ES1_0 &&
+ processor_rev <= OMAP4460_ES1_1)) {
+ /*
+ * Setup the mux for the ES specific board ID pins (gpio 101,
+ * 2 and 3.
+ */
+ writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+ GPMC_A24);
+ writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+ UNIPRO_RY0);
+ writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+ UNIPRO_RX1);
+
+ board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
+ board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
+ board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
+#endif
+ board_id = ((board_id4 << 4) | (board_id3 << 3) |
+ (board_id2 << 2) | (board_id1 << 1) | (board_id0));
+ } else {
+ /* Setup the mux for the Ax specific board ID pins (gpio 101) */
+ writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+ FREF_CLK2_OUT);
+
+ board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
+ board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0));
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
+ setenv("board_name", strcat(CONFIG_SYS_BOARD, "-a4"));
+#endif
+ }
+
+ return board_id;
+}
+
+/**
+ * is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES
+ *
+ *
+ * Detect if we are running on B3 version of ES panda board,
+ * This can be done by reading the level of GPIO 171 and checking the
+ * processor revisions.
+ * GPIO171: 1 => Panda ES Rev B3
+ *
+ * Return : return 1 if Panda ES Rev B3 , else return 0
+ */
+u8 is_panda_es_rev_b3(void)
+{
+ int processor_rev = omap_revision();
+ int ret = 0;
+
+ if ((processor_rev >= OMAP4460_ES1_0 &&
+ processor_rev <= OMAP4460_ES1_1)) {
+
+ /* Setup the mux for the common board ID pins (gpio 171) */
+ writew((IEN | M3),
+ (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
+
+ /* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */
+ ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
+ }
+ return ret;
+}
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+/*
+ * emif_get_reg_dump() - emif_get_reg_dump strong function
+ *
+ * @emif_nr - emif base
+ * @regs - reg dump of timing values
+ *
+ * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c
+ */
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+ u32 omap4_rev = omap_revision();
+
+ /* Same devices and geometry on both EMIFs */
+ if (omap4_rev == OMAP4430_ES1_0)
+ *regs = &emif_regs_elpida_380_mhz_1cs;
+ else if (omap4_rev == OMAP4430_ES2_0)
+ *regs = &emif_regs_elpida_200_mhz_2cs;
+ else if (omap4_rev == OMAP4430_ES2_3)
+ *regs = &emif_regs_elpida_400_mhz_1cs;
+ else if (omap4_rev < OMAP4470_ES1_0) {
+ if(is_panda_es_rev_b3())
+ *regs = &emif_regs_elpida_400_mhz_1cs;
+ else
+ *regs = &emif_regs_elpida_400_mhz_2cs;
+ }
+ else
+ *regs = &emif_regs_elpida_400_mhz_1cs;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs
+ **dmm_lisa_regs)
+{
+ u32 omap_rev = omap_revision();
+
+ if (omap_rev == OMAP4430_ES1_0)
+ *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
+ else if (omap_rev == OMAP4430_ES2_3)
+ *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+ else if (omap_rev < OMAP4460_ES1_0)
+ *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+ else
+ *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
+}
+
+#endif
+
+/**
+ * @brief misc_init_r - Configure Panda board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+ int phy_type;
+ u32 auxclk, altclksrc;
+ u32 id[4];
+
+ /* EHCI is not supported on ES1.0 */
+ if (omap_revision() == OMAP4430_ES1_0)
+ return 0;
+
+ get_board_revision();
+
+ gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
+ phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
+
+ if (phy_type == 1) {
+ /* ULPI PHY supplied by auxclk3 derived from sys_clk */
+ debug("ULPI PHY supplied by auxclk3\n");
+
+ auxclk = readl(&scrm->auxclk3);
+ /* Select sys_clk */
+ auxclk &= ~AUXCLK_SRCSELECT_MASK;
+ auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
+ /* Set the divisor to 2 */
+ auxclk &= ~AUXCLK_CLKDIV_MASK;
+ auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
+ /* Request auxilary clock #3 */
+ auxclk |= AUXCLK_ENABLE_MASK;
+
+ writel(auxclk, &scrm->auxclk3);
+ } else {
+ /* ULPI PHY supplied by auxclk1 derived from PER dpll */
+ debug("ULPI PHY supplied by auxclk1\n");
+
+ auxclk = readl(&scrm->auxclk1);
+ /* Select per DPLL */
+ auxclk &= ~AUXCLK_SRCSELECT_MASK;
+ auxclk |= AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
+ /* Set the divisor to 16 */
+ auxclk &= ~AUXCLK_CLKDIV_MASK;
+ auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
+ /* Request auxilary clock #3 */
+ auxclk |= AUXCLK_ENABLE_MASK;
+
+ writel(auxclk, &scrm->auxclk1);
+ }
+
+ altclksrc = readl(&scrm->altclksrc);
+
+ /* Activate alternate system clock supplier */
+ altclksrc &= ~ALTCLKSRC_MODE_MASK;
+ altclksrc |= ALTCLKSRC_MODE_ACTIVE;
+
+ /* enable clocks */
+ altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
+
+ writel(altclksrc, &scrm->altclksrc);
+
+ id[0] = readl(STD_FUSE_DIE_ID_0);
+ id[1] = readl(STD_FUSE_DIE_ID_1);
+ id[2] = readl(STD_FUSE_DIE_ID_2);
+ id[3] = readl(STD_FUSE_DIE_ID_3);
+ usb_fake_mac_from_die_id(id);
+
+ return 0;
+}
+
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_essential,
+ sizeof(wkup_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ if (omap_revision() >= OMAP4460_ES1_0)
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_essential_4460,
+ sizeof(wkup_padconf_array_essential_4460) /
+ sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI
+
+static struct omap_usbhs_board_data usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ int ret;
+ unsigned int utmi_clk;
+
+ /* Now we can enable our port clocks */
+ utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
+ utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
+ setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
+
+ ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+int ehci_hcd_stop(int index)
+{
+ return omap_ehci_hcd_stop();
+}
+#endif
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+ return 0x20;
+}
diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h
new file mode 100644
index 0000000..53c7080
--- /dev/null
+++ b/board/ti/panda/panda_mux_data.h
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Balaji Krishnamoorthy <balajitk@ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _PANDA_MUX_DATA_H_
+#define _PANDA_MUX_DATA_H_
+
+#include <asm/arch/mux_omap4.h>
+
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
+{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
+{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
+{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
+{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
+{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
+{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
+{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
+{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
+{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
+{UART3_TX_IRTX, (M0)}, /* uart3_tx */
+{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
+{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
+{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
+{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
+{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
+{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
+{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
+{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
+{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
+{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
+{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
+{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
+{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */
+{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
+{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
+{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
+{UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */
+{GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */
+{FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */
+{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
+
+{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
+
+};
+
+#endif /* _PANDA_MUX_DATA_H_ */
diff --git a/board/ti/sdp3430/Kconfig b/board/ti/sdp3430/Kconfig
new file mode 100644
index 0000000..7e73d99
--- /dev/null
+++ b/board/ti/sdp3430/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP3_SDP3430
+
+config SYS_BOARD
+ default "sdp3430"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "omap3_sdp3430"
+
+endif
diff --git a/board/ti/sdp3430/MAINTAINERS b/board/ti/sdp3430/MAINTAINERS
new file mode 100644
index 0000000..943c196
--- /dev/null
+++ b/board/ti/sdp3430/MAINTAINERS
@@ -0,0 +1,6 @@
+SDP3430 BOARD
+M: Nishanth Menon <nm@ti.com>
+S: Maintained
+F: board/ti/sdp3430/
+F: include/configs/omap3_sdp3430.h
+F: configs/omap3_sdp3430_defconfig
diff --git a/board/ti/sdp3430/Makefile b/board/ti/sdp3430/Makefile
new file mode 100644
index 0000000..753f099
--- /dev/null
+++ b/board/ti/sdp3430/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := sdp.o
diff --git a/board/ti/sdp3430/config.mk b/board/ti/sdp3430/config.mk
new file mode 100644
index 0000000..e4d9be1
--- /dev/null
+++ b/board/ti/sdp3430/config.mk
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2006-2009
+# Texas Instruments Incorporated, <www.ti.com>
+#
+# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c
new file mode 100644
index 0000000..7171363
--- /dev/null
+++ b/board/ti/sdp3430/sdp.c
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "sdp.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 SDP3430 board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+ "OneNAND",
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+ "NAND",
+#else
+ "NOR",
+#endif
+};
+
+/* Timing definitions for GPMC controller for Sibley NOR */
+static const u32 gpmc_sdp_nor[] = {
+ SDP3430_NOR_GPMC_CONF1,
+ SDP3430_NOR_GPMC_CONF2,
+ SDP3430_NOR_GPMC_CONF3,
+ SDP3430_NOR_GPMC_CONF4,
+ SDP3430_NOR_GPMC_CONF5,
+ SDP3430_NOR_GPMC_CONF6,
+ /*CONF7- computed as params */
+};
+
+/*
+ * Timing definitions for GPMC controller for Debug Board
+ * Debug board contains access to ethernet and DIP Switch setting
+ * information etc.
+ */
+static const u32 gpmc_sdp_debug[] = {
+ SDP3430_DEBUG_GPMC_CONF1,
+ SDP3430_DEBUG_GPMC_CONF2,
+ SDP3430_DEBUG_GPMC_CONF3,
+ SDP3430_DEBUG_GPMC_CONF4,
+ SDP3430_DEBUG_GPMC_CONF5,
+ SDP3430_DEBUG_GPMC_CONF6,
+ /*CONF7- computed as params */
+};
+
+/* Timing defintions for GPMC OneNAND */
+static const u32 gpmc_sdp_onenand[] = {
+ SDP3430_ONENAND_GPMC_CONF1,
+ SDP3430_ONENAND_GPMC_CONF2,
+ SDP3430_ONENAND_GPMC_CONF3,
+ SDP3430_ONENAND_GPMC_CONF4,
+ SDP3430_ONENAND_GPMC_CONF5,
+ SDP3430_ONENAND_GPMC_CONF6,
+ /*CONF7- computed as params */
+};
+
+/* GPMC definitions for GPMC NAND */
+static const u32 gpmc_sdp_nand[] = {
+ SDP3430_NAND_GPMC_CONF1,
+ SDP3430_NAND_GPMC_CONF2,
+ SDP3430_NAND_GPMC_CONF3,
+ SDP3430_NAND_GPMC_CONF4,
+ SDP3430_NAND_GPMC_CONF5,
+ SDP3430_NAND_GPMC_CONF6,
+ /*CONF7- computed as params */
+};
+
+/* gpmc_cfg is initialized by gpmc_init and we use it here */
+extern struct gpmc *gpmc_cfg;
+
+/**
+ * @brief board_init - gpmc and basic setup as phase1 of boot sequence
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* TODO: Dynamically pop out CS mapping and program accordingly */
+ /* Configure devices for default ON ON ON settings */
+ enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
+ CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
+ enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
+ GPMC_SIZE_16M);
+ enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
+ GPMC_SIZE_16M);
+ enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
+ GPMC_SIZE_16M);
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+#define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c)
+#define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b)
+
+/**
+ * @brief board_eth_init Take the Ethernet controller out of reset and wait
+ * for the EEPROM load to complete.
+ */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
+ int cnt = 20;
+
+ writew(0x0, LAN_RESET_REGISTER);
+ do {
+ writew(0x1, LAN_RESET_REGISTER);
+ udelay(100);
+ if (cnt == 0)
+ goto reset_err_out;
+ --cnt;
+ } while (readw(LAN_RESET_REGISTER) != 0x1);
+
+ cnt = 20;
+
+ do {
+ writew(0x0, LAN_RESET_REGISTER);
+ udelay(100);
+ if (cnt == 0)
+ goto reset_err_out;
+ --cnt;
+ } while (readw(LAN_RESET_REGISTER) != 0x0000);
+ udelay(1000);
+
+ writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
+ udelay(1000);
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+reset_err_out:
+
+#endif
+ return rc;
+}
+
+/**
+ * @brief misc_init_r - Configure SDP board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+ /* Partial setup:
+ * VAUX3 - 2.8V for DVI
+ * VPLL1 - 1.8V
+ * VDAC - 1.8V
+ * and turns on LEDA/LEDB (not needed ... NOP?)
+ */
+ twl4030_power_init();
+
+ /* FIXME finish setup:
+ * VAUX1 - 2.8V for mainboard I/O
+ * VAUX2 - 2.8V for camera
+ * VAUX4 - 1.8V for OMAP3 CSI
+ * VMMC1 - 3.15V (init, variable) for MMC1
+ * VMMC2 - 1.85V for MMC2
+ * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM
+ * VPLL2 - 1.8V
+ */
+
+ return 0;
+}
+
+/**
+ * @brief set_muxconf_regs Setting up the configuration Mux registers
+ * specific to the hardware. Many pins need to be moved from protect
+ * to primary mode.
+ */
+void set_muxconf_regs(void)
+{
+ /* platform specific muxes */
+ MUX_SDP3430();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
diff --git a/board/ti/sdp3430/sdp.h b/board/ti/sdp3430/sdp.h
new file mode 100644
index 0000000..0e63189
--- /dev/null
+++ b/board/ti/sdp3430/sdp.h
@@ -0,0 +1,401 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _BOARD_SDP_H_
+#define _BOARD_SDP_H_
+
+#define OFF_IN_PD 0
+#define OFF_OUT_PD 0
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_SDP3430()\
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\
+ MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\
+ MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\
+ MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\
+ MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\
+ MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\
+ MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\
+ MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\
+ MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\
+ MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ /*Audio InterfACe */\
+ MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ /*Expansion Card */\
+ MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ /*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\
+ MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\
+ MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\
+ MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\
+ MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\
+ MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\
+ MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\
+ MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ /* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\
+ MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\
+ MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\
+ MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\
+ MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\
+ MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\
+ MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\
+ MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\
+ MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\
+ MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ /*Die to Die */\
+ MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/
+
+/*
+ * GPMC Timing definitions for SDP3430
+ * at L3 = 166Mhz
+ */
+
+/* Timing definitions for GPMC controller for Sibley NOR */
+#define SDP3430_NOR_GPMC_CONF1 0x00001200
+#define SDP3430_NOR_GPMC_CONF2 0x001F1F00
+#define SDP3430_NOR_GPMC_CONF3 0x00080802
+#define SDP3430_NOR_GPMC_CONF4 0x1C091C09
+#define SDP3430_NOR_GPMC_CONF5 0x01131F1F
+#define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2
+
+/*
+ * Timing definitions for GPMC controller for Debug Board
+ * Debug board contains access to ethernet and DIP Switch setting
+ * information etc.
+ */
+#define SDP3430_DEBUG_GPMC_CONF1 0x00611200
+#define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01
+#define SDP3430_DEBUG_GPMC_CONF3 0x00080803
+#define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09
+#define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F
+#define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4
+
+/* Timing defintions for GPMC OneNAND */
+#define SDP3430_ONENAND_GPMC_CONF1 0x00001200
+#define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01
+#define SDP3430_ONENAND_GPMC_CONF3 0x00030301
+#define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04
+#define SDP3430_ONENAND_GPMC_CONF5 0x010F1010
+#define SDP3430_ONENAND_GPMC_CONF6 0x1F060000
+
+/* GPMC definitions for GPMC NAND */
+#define SDP3430_NAND_GPMC_CONF1 0x00000800
+#define SDP3430_NAND_GPMC_CONF2 0x00141400
+#define SDP3430_NAND_GPMC_CONF3 0x00141400
+#define SDP3430_NAND_GPMC_CONF4 0x0F010F01
+#define SDP3430_NAND_GPMC_CONF5 0x010C1414
+#define SDP3430_NAND_GPMC_CONF6 0x1F040A80
+
+#endif /* _BOARD_SDP_H_ */
diff --git a/board/ti/sdp4430/Kconfig b/board/ti/sdp4430/Kconfig
new file mode 100644
index 0000000..5826d8f
--- /dev/null
+++ b/board/ti/sdp4430/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_OMAP4_SDP4430
+
+config SYS_BOARD
+ default "sdp4430"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "omap4_sdp4430"
+
+endif
diff --git a/board/ti/sdp4430/MAINTAINERS b/board/ti/sdp4430/MAINTAINERS
new file mode 100644
index 0000000..ac4d0cc
--- /dev/null
+++ b/board/ti/sdp4430/MAINTAINERS
@@ -0,0 +1,6 @@
+SDP4430 BOARD
+M: Lokesh Vutla <lokeshvutla@ti.com>
+S: Maintained
+F: board/ti/sdp4430/
+F: include/configs/omap4_sdp4430.h
+F: configs/omap4_sdp4430_defconfig
diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile
new file mode 100644
index 0000000..79e67b6
--- /dev/null
+++ b/board/ti/sdp4430/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := sdp.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y += cmd_bat.o
+endif
diff --git a/board/ti/sdp4430/cmd_bat.c b/board/ti/sdp4430/cmd_bat.c
new file mode 100644
index 0000000..7e8dbb1
--- /dev/null
+++ b/board/ti/sdp4430/cmd_bat.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+
+#ifdef CONFIG_CMD_BAT
+#include <twl6030.h>
+
+int do_vbat(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc == 2) {
+ if (strncmp(argv[1], "startcharge", 12) == 0)
+ twl6030_start_usb_charging();
+ else if (strncmp(argv[1], "stopcharge", 11) == 0)
+ twl6030_stop_usb_charging();
+ else if (strncmp(argv[1], "status", 7) == 0) {
+ twl6030_get_battery_voltage();
+ twl6030_get_battery_current();
+ } else {
+ goto bat_cmd_usage;
+ }
+ } else {
+ goto bat_cmd_usage;
+ }
+ return 0;
+
+bat_cmd_usage:
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+ bat, 2, 1, do_vbat,
+ "battery charging, voltage/current measurements",
+ "status - display battery voltage and current\n"
+ "bat startcharge - start charging via USB\n"
+ "bat stopcharge - stop charging\n"
+);
+#endif /* CONFIG_BAT_CMD */
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
new file mode 100644
index 0000000..1e9ef9e
--- /dev/null
+++ b/board/ti/sdp4430/sdp.c
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <twl6030.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+
+#include "sdp4430_mux_data.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: OMAP4430 SDP\n"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gpmc_init();
+
+ gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure SDP board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_TWL6030_POWER
+ twl6030_init_battery_charging();
+#endif
+ return 0;
+}
+
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_essential,
+ sizeof(wkup_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+
+ if ((omap_revision() >= OMAP4460_ES1_0) &&
+ (omap_revision() < OMAP4470_ES1_0))
+ do_set_mux((*ctrl)->control_padconf_wkup_base,
+ wkup_padconf_array_essential_4460,
+ sizeof(wkup_padconf_array_essential_4460) /
+ sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
+ return 0;
+}
+#endif
+
+/*
+ * get_board_rev() - get board revision
+ */
+u32 get_board_rev(void)
+{
+ return 0x20;
+}
diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h
new file mode 100644
index 0000000..9a9efe7
--- /dev/null
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Balaji Krishnamoorthy <balajitk@ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
+
+#include <asm/arch/mux_omap4.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+
+{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
+{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
+{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
+{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
+{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
+{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
+{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
+{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
+{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
+{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
+{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
+{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
+{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
+{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
+{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
+{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
+{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
+{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
+{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
+{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
+{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
+{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
+{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
+{UART3_TX_IRTX, (M0)}, /* uart3_tx */
+{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
+{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
+{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
+{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
+{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */
+{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
+{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
+{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
+{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
+{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
+{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential[] = {
+
+{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
+{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
+{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */
+
+};
+
+const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
+
+{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
+
+};
+
+#endif /* _SDP4430_MUX_DATA_H */
diff --git a/board/ti/ti814x/Kconfig b/board/ti/ti814x/Kconfig
new file mode 100644
index 0000000..2960099
--- /dev/null
+++ b/board/ti/ti814x/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TI814X_EVM
+
+config SYS_BOARD
+ default "ti814x"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "ti814x_evm"
+
+endif
diff --git a/board/ti/ti814x/MAINTAINERS b/board/ti/ti814x/MAINTAINERS
new file mode 100644
index 0000000..e39b253
--- /dev/null
+++ b/board/ti/ti814x/MAINTAINERS
@@ -0,0 +1,6 @@
+TI814X BOARD
+M: Matt Porter <matt.porter@linaro.org>
+S: Maintained
+F: board/ti/ti814x/
+F: include/configs/ti814x_evm.h
+F: configs/ti814x_evm_defconfig
diff --git a/board/ti/ti814x/Makefile b/board/ti/ti814x/Makefile
new file mode 100644
index 0000000..93155de
--- /dev/null
+++ b/board/ti/ti814x/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := mux.o
+endif
+
+obj-y += evm.o
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
new file mode 100644
index 0000000..54b3dfb
--- /dev/null
+++ b/board/ti/ti814x/evm.c
@@ -0,0 +1,188 @@
+/*
+ * evm.c
+ *
+ * Board functions for TI814x EVM
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpsw.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include "evm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* UART Defines */
+#ifdef CONFIG_SPL_BUILD
+static const struct cmd_control evm_ddr2_cctrl_data = {
+ .cmd0csratio = 0x80,
+ .cmd0iclkout = 0x00,
+
+ .cmd1csratio = 0x80,
+ .cmd1iclkout = 0x00,
+
+ .cmd2csratio = 0x80,
+ .cmd2iclkout = 0x00,
+};
+
+static const struct emif_regs evm_ddr2_emif0_regs = {
+ .sdram_config = 0x40801ab2,
+ .ref_ctrl = 0x10000c30,
+ .sdram_tim1 = 0x0aaaf552,
+ .sdram_tim2 = 0x043631d2,
+ .sdram_tim3 = 0x00000327,
+ .emif_ddr_phy_ctlr_1 = 0x00000007
+};
+
+static const struct emif_regs evm_ddr2_emif1_regs = {
+ .sdram_config = 0x40801ab2,
+ .ref_ctrl = 0x10000c30,
+ .sdram_tim1 = 0x0aaaf552,
+ .sdram_tim2 = 0x043631d2,
+ .sdram_tim3 = 0x00000327,
+ .emif_ddr_phy_ctlr_1 = 0x00000007
+};
+
+const struct dmm_lisa_map_regs evm_lisa_map_regs = {
+ .dmm_lisa_map_0 = 0x00000000,
+ .dmm_lisa_map_1 = 0x00000000,
+ .dmm_lisa_map_2 = 0x806c0300,
+ .dmm_lisa_map_3 = 0x806c0300,
+};
+
+static const struct ddr_data evm_ddr2_data = {
+ .datardsratio0 = ((0x35<<10) | (0x35<<0)),
+ .datawdsratio0 = ((0x20<<10) | (0x20<<0)),
+ .datawiratio0 = ((0<<10) | (0<<0)),
+ .datagiratio0 = ((0<<10) | (0<<0)),
+ .datafwsratio0 = ((0x90<<10) | (0x90<<0)),
+ .datawrsratio0 = ((0x50<<10) | (0x50<<0)),
+};
+
+void set_uart_mux_conf(void)
+{
+ /* Set UART pins */
+ enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+ /* Set MMC pins */
+ enable_mmc1_pin_mux();
+
+ /* Set Ethernet pins */
+ enable_enet_pin_mux();
+}
+
+void sdram_init(void)
+{
+ config_dmm(&evm_lisa_map_regs);
+
+ config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+ &evm_ddr2_emif0_regs, 0);
+ config_ddr(0, NULL, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+ &evm_ddr2_emif1_regs, 1);
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ return 0;
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(1, 0, 0, -1, -1);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x50,
+ .sliver_reg_ofs = 0x700,
+ .phy_addr = 1,
+ },
+ {
+ .slave_reg_ofs = 0x90,
+ .sliver_reg_ofs = 0x740,
+ .phy_addr = 0,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = CPSW_MDIO_BASE,
+ .cpsw_base = CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x100,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0x600,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x28,
+ .hw_stats_reg_ofs = 0x400,
+ .bd_ram_ofs = 0x2000,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_1,
+};
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ printf("<ethaddr> not set. Reading from E-fuse\n");
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ else
+ printf("Unable to read MAC address. Set <ethaddr>\n");
+ }
+
+ return cpsw_register(&cpsw_data);
+}
diff --git a/board/ti/ti814x/evm.h b/board/ti/ti814x/evm.h
new file mode 100644
index 0000000..6aebec6
--- /dev/null
+++ b/board/ti/ti814x/evm.h
@@ -0,0 +1,8 @@
+#ifndef _EVM_H
+#define _EVM_H
+
+void enable_uart0_pin_mux(void);
+void enable_mmc1_pin_mux(void);
+void enable_enet_pin_mux(void);
+
+#endif /* _EVM_H */
diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c
new file mode 100644
index 0000000..fd9f364
--- /dev/null
+++ b/board/ti/ti814x/mux.c
@@ -0,0 +1,86 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "evm.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(pincntl70), PULLUP_EN | MODE(0x01)}, /* UART0_RXD */
+ {OFFSET(pincntl71), PULLUP_EN | MODE(0x01)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+ {OFFSET(pincntl1), PULLUP_EN | MODE(0x01)}, /* SD1_CLK */
+ {OFFSET(pincntl2), PULLUP_EN | MODE(0x01)}, /* SD1_CMD */
+ {OFFSET(pincntl3), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[0] */
+ {OFFSET(pincntl4), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[1] */
+ {OFFSET(pincntl5), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[2] */
+ {OFFSET(pincntl6), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[3] */
+ {OFFSET(pincntl74), PULLUP_EN | MODE(0x40)}, /* SD1_POW */
+ {OFFSET(pincntl75), MODE(0x40)}, /* SD1_SDWP */
+ {OFFSET(pincntl80), PULLUP_EN | MODE(0x02)}, /* SD1_SDCD */
+ {-1},
+};
+
+static struct module_pin_mux enet_pin_mux[] = {
+ {OFFSET(pincntl232), MODE(0x01)}, /* EMAC_RMREFCLK */
+ {OFFSET(pincntl233), PULLUP_EN | MODE(0x01)}, /* MDCLK */
+ {OFFSET(pincntl234), PULLUP_EN | MODE(0x01)}, /* MDIO */
+ {OFFSET(pincntl235), MODE(0x01)}, /* EMAC[0]_MTCLK */
+ {OFFSET(pincntl236), MODE(0x01)}, /* EMAC[0]_MCOL */
+ {OFFSET(pincntl237), MODE(0x01)}, /* EMAC[0]_MCRS */
+ {OFFSET(pincntl238), MODE(0x01)}, /* EMAC[0]_MRXER */
+ {OFFSET(pincntl239), MODE(0x01)}, /* EMAC[0]_MRCLK */
+ {OFFSET(pincntl240), MODE(0x01)}, /* EMAC[0]_MRXD[0] */
+ {OFFSET(pincntl241), MODE(0x01)}, /* EMAC[0]_MRXD[1] */
+ {OFFSET(pincntl242), MODE(0x01)}, /* EMAC[0]_MRXD[2] */
+ {OFFSET(pincntl243), MODE(0x01)}, /* EMAC[0]_MRXD[3] */
+ {OFFSET(pincntl244), MODE(0x01)}, /* EMAC[0]_MRXD[4] */
+ {OFFSET(pincntl245), MODE(0x01)}, /* EMAC[0]_MRXD[5] */
+ {OFFSET(pincntl246), MODE(0x01)}, /* EMAC[0]_MRXD[6] */
+ {OFFSET(pincntl247), MODE(0x01)}, /* EMAC[0]_MRXD[7] */
+ {OFFSET(pincntl248), MODE(0x01)}, /* EMAC[0]_MRXDV */
+ {OFFSET(pincntl249), MODE(0x01)}, /* EMAC[0]_GMTCLK */
+ {OFFSET(pincntl250), MODE(0x01)}, /* EMAC[0]_MTXD[0] */
+ {OFFSET(pincntl251), MODE(0x01)}, /* EMAC[0]_MTXD[1] */
+ {OFFSET(pincntl252), MODE(0x01)}, /* EMAC[0]_MTXD[2] */
+ {OFFSET(pincntl253), MODE(0x01)}, /* EMAC[0]_MTXD[3] */
+ {OFFSET(pincntl254), MODE(0x01)}, /* EMAC[0]_MTXD[4] */
+ {OFFSET(pincntl255), MODE(0x01)}, /* EMAC[0]_MTXD[5] */
+ {OFFSET(pincntl256), MODE(0x01)}, /* EMAC[0]_MTXD[6] */
+ {OFFSET(pincntl257), MODE(0x01)}, /* EMAC[0]_MTXD[7] */
+ {OFFSET(pincntl258), MODE(0x01)}, /* EMAC[0]_MTXEN */
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_mmc1_pin_mux(void)
+{
+ configure_module_pin_mux(mmc1_pin_mux);
+}
+
+void enable_enet_pin_mux(void)
+{
+ configure_module_pin_mux(enet_pin_mux);
+}
diff --git a/board/ti/ti816x/Kconfig b/board/ti/ti816x/Kconfig
new file mode 100644
index 0000000..95973b4
--- /dev/null
+++ b/board/ti/ti816x/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TI816X_EVM
+
+config SYS_BOARD
+ default "ti816x"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "ti816x_evm"
+
+endif
diff --git a/board/ti/ti816x/MAINTAINERS b/board/ti/ti816x/MAINTAINERS
new file mode 100644
index 0000000..d3de144
--- /dev/null
+++ b/board/ti/ti816x/MAINTAINERS
@@ -0,0 +1,6 @@
+TI816X BOARD
+#M: -
+S: Maintained
+F: board/ti/ti816x/
+F: include/configs/ti816x_evm.h
+F: configs/ti816x_evm_defconfig
diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile
new file mode 100644
index 0000000..f1cc3d5
--- /dev/null
+++ b/board/ti/ti816x/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+# Antoine Tenart, <atenart@adeneo-embedded.com>
+#
+# Based on TI-PSP-04.00.02.14 :
+#
+# Copyright (C) 2009, Texas Instruments, Incorporated
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := evm.o
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
new file mode 100644
index 0000000..b6bf162
--- /dev/null
+++ b/board/ti/ti816x/evm.c
@@ -0,0 +1,216 @@
+/*
+ * evm.c
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+
+static struct module_pin_mux mmc_pin_mux[] = {
+ { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
+ { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
+ { -1 },
+};
+
+const struct dmm_lisa_map_regs evm_lisa_map_regs = {
+ .dmm_lisa_map_0 = 0x00000000,
+ .dmm_lisa_map_1 = 0x00000000,
+ .dmm_lisa_map_2 = 0x80640300,
+ .dmm_lisa_map_3 = 0xC0640320,
+};
+
+/*
+ * DDR2 related definitions
+ */
+#ifdef CONFIG_TI816X_EVM_DDR2
+static struct ddr_data ddr2_data = {
+ .datardsratio0 = ((0x40<<10) | (0x40<<0)),
+ .datawdsratio0 = ((0x4A<<10) | (0x4A<<0)),
+ .datawiratio0 = ((0x0<<10) | (0x0<<0)),
+ .datagiratio0 = ((0x0<<10) | (0x0<<0)),
+ .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)),
+ .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)),
+};
+
+static struct cmd_control ddr2_ctrl = {
+ .cmd0csratio = 0x80,
+ .cmd0iclkout = 0x00,
+
+ .cmd1csratio = 0x80,
+ .cmd1iclkout = 0x00,
+
+ .cmd2csratio = 0x80,
+ .cmd2iclkout = 0x00,
+
+};
+
+static struct emif_regs ddr2_emif0_regs = {
+ .sdram_config = 0x43801A3A,
+ .ref_ctrl = 0x10000C30,
+ .sdram_tim1 = 0x0AAB15E2,
+ .sdram_tim2 = 0x423631D2,
+ .sdram_tim3 = 0x0080032F,
+ .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
+};
+
+static struct emif_regs ddr2_emif1_regs = {
+ .sdram_config = 0x43801A3A,
+ .ref_ctrl = 0x10000C30,
+ .sdram_tim1 = 0x0AAB15E2,
+ .sdram_tim2 = 0x423631D2,
+ .sdram_tim3 = 0x0080032F,
+ .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */
+};
+#endif
+
+/*
+ * DDR3 related definitions
+ */
+
+#if defined(CONFIG_TI816X_DDR_PLL_400)
+#define RD_DQS 0x03B
+#define WR_DQS 0x0A6
+#define RD_DQS_GATE 0x12A
+#define EMIF_SDCFG 0x62A41032
+#define EMIF_SDREF 0x10000C30
+#define EMIF_TIM1 0x0CCCE524
+#define EMIF_TIM2 0x30308023
+#define EMIF_TIM3 0x009F82CF
+#define EMIF_PHYCFG 0x0000010B
+#elif defined(CONFIG_TI816X_DDR_PLL_531)
+#define RD_DQS 0x039
+#define WR_DQS 0x0B4
+#define RD_DQS_GATE 0x13D
+#define EMIF_SDCFG 0x62A51832
+#define EMIF_SDREF 0x1000102E
+#define EMIF_TIM1 0x0EF136AC
+#define EMIF_TIM2 0x30408063
+#define EMIF_TIM3 0x009F83AF
+#define EMIF_PHYCFG 0x0000010C
+#elif defined(CONFIG_TI816X_DDR_PLL_675)
+#define RD_DQS 0x039
+#define WR_DQS 0x091
+#define RD_DQS_GATE 0x196
+#define EMIF_SDCFG 0x62A63032
+#define EMIF_SDREF 0x10001491
+#define EMIF_TIM1 0x13358875
+#define EMIF_TIM2 0x5051806C
+#define EMIF_TIM3 0x009F84AF
+#define EMIF_PHYCFG 0x0000010F
+#elif defined(CONFIG_TI816X_DDR_PLL_796)
+#define RD_DQS 0x035
+#define WR_DQS 0x093
+#define RD_DQS_GATE 0x1B3
+#define EMIF_SDCFG 0x62A73832
+#define EMIF_SDREF 0x10001841
+#define EMIF_TIM1 0x1779C9FE
+#define EMIF_TIM2 0x50608074
+#define EMIF_TIM3 0x009F857F
+#define EMIF_PHYCFG 0x00000110
+#endif
+
+static struct ddr_data ddr3_data = {
+ .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
+ .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
+ .datawiratio0 = ((0x20<<10) | 0x20<<0),
+ .datagiratio0 = ((0x20<<10) | 0x20<<0),
+ .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
+ .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
+};
+
+static const struct cmd_control ddr3_ctrl = {
+ .cmd0csratio = 0x100,
+ .cmd0iclkout = 0x001,
+
+ .cmd1csratio = 0x100,
+ .cmd1iclkout = 0x001,
+
+ .cmd2csratio = 0x100,
+ .cmd2iclkout = 0x001,
+};
+
+static const struct emif_regs ddr3_emif0_regs = {
+ .sdram_config = EMIF_SDCFG,
+ .ref_ctrl = EMIF_SDREF,
+ .sdram_tim1 = EMIF_TIM1,
+ .sdram_tim2 = EMIF_TIM2,
+ .sdram_tim3 = EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
+};
+
+static const struct emif_regs ddr3_emif1_regs = {
+ .sdram_config = EMIF_SDCFG,
+ .ref_ctrl = EMIF_SDREF,
+ .sdram_tim1 = EMIF_TIM1,
+ .sdram_tim2 = EMIF_TIM2,
+ .sdram_tim3 = EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
+};
+
+void set_uart_mux_conf(void) {}
+
+void set_mux_conf_regs(void)
+{
+ configure_module_pin_mux(mmc_pin_mux);
+}
+
+void sdram_init(void)
+{
+ config_dmm(&evm_lisa_map_regs);
+
+#ifdef CONFIG_TI816X_EVM_DDR2
+ if (CONFIG_TI816X_USE_EMIF0) {
+ ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
+ (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
+ config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs,
+ 0);
+ }
+
+ if (CONFIG_TI816X_USE_EMIF1) {
+ ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
+ (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
+ config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs,
+ 1);
+ }
+#endif
+
+#ifdef CONFIG_TI816X_EVM_DDR3
+ if (CONFIG_TI816X_USE_EMIF0)
+ config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs,
+ 0);
+
+ if (CONFIG_TI816X_USE_EMIF1)
+ config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs,
+ 1);
+#endif
+}
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/ti/tnetv107xevm/Kconfig b/board/ti/tnetv107xevm/Kconfig
new file mode 100644
index 0000000..637f20e
--- /dev/null
+++ b/board/ti/tnetv107xevm/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TNETV107X_EVM
+
+config SYS_BOARD
+ default "tnetv107xevm"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_SOC
+ default "tnetv107x"
+
+config SYS_CONFIG_NAME
+ default "tnetv107x_evm"
+
+endif
diff --git a/board/ti/tnetv107xevm/MAINTAINERS b/board/ti/tnetv107xevm/MAINTAINERS
new file mode 100644
index 0000000..8a92c6b
--- /dev/null
+++ b/board/ti/tnetv107xevm/MAINTAINERS
@@ -0,0 +1,6 @@
+TNETV107XEVM BOARD
+#M: Chan-Taek Park <c-park@ti.com>
+S: Orphan (since 2014-06)
+F: board/ti/tnetv107xevm/
+F: include/configs/tnetv107x_evm.h
+F: configs/tnetv107x_evm_defconfig
diff --git a/board/ti/tnetv107xevm/Makefile b/board/ti/tnetv107xevm/Makefile
new file mode 100644
index 0000000..0a6128f
--- /dev/null
+++ b/board/ti/tnetv107xevm/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sdb_board.o
diff --git a/board/ti/tnetv107xevm/config.mk b/board/ti/tnetv107xevm/config.mk
new file mode 100644
index 0000000..51c2886
--- /dev/null
+++ b/board/ti/tnetv107xevm/config.mk
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0x83FC0000
diff --git a/board/ti/tnetv107xevm/sdb_board.c b/board/ti/tnetv107xevm/sdb_board.c
new file mode 100644
index 0000000..a84ec84
--- /dev/null
+++ b/board/ti/tnetv107xevm/sdb_board.c
@@ -0,0 +1,134 @@
+/*
+ * TNETV107X-EVM: Board initialization
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <linux/mtd/nand.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/ti-common/davinci_nand.h>
+#include <asm/arch/mux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
+ { /* CS0 */
+ .mode = ASYNC_EMIF_MODE_NAND,
+ .wr_setup = 5,
+ .wr_strobe = 5,
+ .wr_hold = 2,
+ .rd_setup = 5,
+ .rd_strobe = 5,
+ .rd_hold = 2,
+ .turn_around = 5,
+ .width = ASYNC_EMIF_8,
+ },
+ { /* CS1 */
+ .mode = ASYNC_EMIF_MODE_NOR,
+ .wr_setup = 2,
+ .wr_strobe = 27,
+ .wr_hold = 4,
+ .rd_setup = 2,
+ .rd_strobe = 27,
+ .rd_hold = 4,
+ .turn_around = 2,
+ .width = ASYNC_EMIF_PRESERVE,
+ },
+ { /* CS2 */
+ .mode = ASYNC_EMIF_MODE_NOR,
+ .wr_setup = 2,
+ .wr_strobe = 27,
+ .wr_hold = 4,
+ .rd_setup = 2,
+ .rd_strobe = 27,
+ .rd_hold = 4,
+ .turn_around = 2,
+ .width = ASYNC_EMIF_PRESERVE,
+ },
+ { /* CS3 */
+ .mode = ASYNC_EMIF_MODE_NOR,
+ .wr_setup = 1,
+ .wr_strobe = 90,
+ .wr_hold = 3,
+ .rd_setup = 1,
+ .rd_strobe = 26,
+ .rd_hold = 3,
+ .turn_around = 1,
+ .width = ASYNC_EMIF_8,
+ },
+};
+
+static struct pll_init_data pll_config[] = {
+ {
+ .pll = ETH_PLL,
+ .internal_osc = 1,
+ .pll_freq = 500000000,
+ .div_freq = {
+ 5000000, 50000000, 125000000, 250000000, 25000000,
+ },
+ },
+};
+
+static const short sdio1_pins[] = {
+ TNETV107X_PIN_SDIO1_CLK_1, TNETV107X_PIN_SDIO1_CMD_1,
+ TNETV107X_PIN_SDIO1_DATA0_1, TNETV107X_PIN_SDIO1_DATA1_1,
+ TNETV107X_PIN_SDIO1_DATA2_1, TNETV107X_PIN_SDIO1_DATA3_1,
+ -1
+};
+
+static const short uart1_pins[] = {
+ TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1
+};
+
+static const short ssp_pins[] = {
+ TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2,
+ TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2,
+ TNETV107X_PIN_SSP1_3, -1
+};
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+ __raw_writel(0, INTC_GLB_EN); /* Global disable */
+ __raw_writel(0, INTC_HINT_EN); /* Disable host ints */
+ __raw_writel(0, INTC_EN_CLR0 + 0); /* Clear enable */
+ __raw_writel(0, INTC_EN_CLR0 + 4); /* Clear enable */
+ __raw_writel(0, INTC_EN_CLR0 + 8); /* Clear enable */
+#endif
+
+ gd->bd->bi_arch_number = MACH_TYPE_TNETV107X;
+ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+ init_plls(ARRAY_SIZE(pll_config), pll_config);
+
+ init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
+
+ mux_select_pin(TNETV107X_PIN_ASR_CS3);
+ mux_select_pins(sdio1_pins);
+ mux_select_pins(uart1_pins);
+ mux_select_pins(ssp_pins);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_NAND_DAVINCI
+int board_nand_init(struct nand_chip *nand)
+{
+ davinci_nand_init(nand);
+
+ return 0;
+}
+#endif
diff --git a/board/timll/devkit3250/Kconfig b/board/timll/devkit3250/Kconfig
new file mode 100644
index 0000000..e3bd456
--- /dev/null
+++ b/board/timll/devkit3250/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_DEVKIT3250
+
+config SYS_BOARD
+ default "devkit3250"
+
+config SYS_VENDOR
+ default "timll"
+
+config SYS_SOC
+ default "lpc32xx"
+
+config SYS_CONFIG_NAME
+ default "devkit3250"
+
+endif
diff --git a/board/timll/devkit3250/MAINTAINERS b/board/timll/devkit3250/MAINTAINERS
new file mode 100644
index 0000000..cb93563
--- /dev/null
+++ b/board/timll/devkit3250/MAINTAINERS
@@ -0,0 +1,6 @@
+DEVKIT3250 BOARD
+M: Vladimir Zapolskiy <vz@mleia.com>
+S: Maintained
+F: board/timll/devkit3250/
+F: include/configs/devkit3250.h
+F: configs/devkit3250_defconfig
diff --git a/board/timll/devkit3250/Makefile b/board/timll/devkit3250/Makefile
new file mode 100644
index 0000000..4722986
--- /dev/null
+++ b/board/timll/devkit3250/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := devkit3250.o
diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c
new file mode 100644
index 0000000..6acc416
--- /dev/null
+++ b/board/timll/devkit3250/devkit3250.c
@@ -0,0 +1,52 @@
+/*
+ * Embest/Timll DevKit3250 board support
+ *
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/emc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
+
+int board_early_init_f(void)
+{
+ lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_SYS_FLASH_CFI
+ /* Use 16-bit memory interface for NOR Flash */
+ emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
+
+ /* Change the NOR timings to optimum value to get maximum bandwidth */
+ emc->stat[0].waitwen = EMC_STAT_WAITWEN(1);
+ emc->stat[0].waitoen = EMC_STAT_WAITOEN(1);
+ emc->stat[0].waitrd = EMC_STAT_WAITRD(12);
+ emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12);
+ emc->stat[0].waitwr = EMC_STAT_WAITWR(5);
+ emc->stat[0].waitturn = EMC_STAT_WAITTURN(2);
+#endif
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+
+ return 0;
+}
diff --git a/board/timll/devkit8000/Kconfig b/board/timll/devkit8000/Kconfig
new file mode 100644
index 0000000..3c63ced
--- /dev/null
+++ b/board/timll/devkit8000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DEVKIT8000
+
+config SYS_BOARD
+ default "devkit8000"
+
+config SYS_VENDOR
+ default "timll"
+
+config SYS_CONFIG_NAME
+ default "devkit8000"
+
+endif
diff --git a/board/timll/devkit8000/MAINTAINERS b/board/timll/devkit8000/MAINTAINERS
new file mode 100644
index 0000000..c490757
--- /dev/null
+++ b/board/timll/devkit8000/MAINTAINERS
@@ -0,0 +1,6 @@
+DEVKIT8000 BOARD
+M: Thomas Weber <weber@corscience.de>
+S: Maintained
+F: board/timll/devkit8000/
+F: include/configs/devkit8000.h
+F: configs/devkit8000_defconfig
diff --git a/board/timll/devkit8000/Makefile b/board/timll/devkit8000/Makefile
new file mode 100644
index 0000000..104b63b
--- /dev/null
+++ b/board/timll/devkit8000/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2009
+# Frederik Kriewitz <frederik@kriewitz.eu>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := devkit8000.o
diff --git a/board/timll/devkit8000/README b/board/timll/devkit8000/README
new file mode 100644
index 0000000..609bf51
--- /dev/null
+++ b/board/timll/devkit8000/README
@@ -0,0 +1,15 @@
+DevKit8000
+==========
+
+The OMAP3 DevKit8000 from Embest/Timll is a clone of the OMAP3 beagle board
+with Ethernet and Touch Screen controller on board.
+
+For more information go to:
+http://www.embedinfo.com/English/Product/devkit8000.asp
+
+There's no real MAC address available.
+If ethaddr is not set, 5 Bytes of the OMAP Die ID will be used.
+
+Build:
+make devkit8000_config
+make
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
new file mode 100644
index 0000000..b978044
--- /dev/null
+++ b/board/timll/devkit8000/devkit8000.c
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/mach-types.h>
+#include "devkit8000.h"
+#include <asm/gpio.h>
+#ifdef CONFIG_DRIVER_DM9000
+#include <net.h>
+#include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 gpmc_net_config[GPMC_MAX_REG] = {
+ NET_GPMC_CONFIG1,
+ NET_GPMC_CONFIG2,
+ NET_GPMC_CONFIG3,
+ NET_GPMC_CONFIG4,
+ NET_GPMC_CONFIG5,
+ NET_GPMC_CONFIG6,
+ 0
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/* Configure GPMC registers for DM9000 */
+static void gpmc_dm9000_config(void)
+{
+ enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
+ CONFIG_DM9000_BASE, GPMC_SIZE_16M);
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
+#ifdef CONFIG_DRIVER_DM9000
+ uchar enetaddr[6];
+ u32 die_id_0;
+#endif
+
+ twl4030_power_init();
+#ifdef CONFIG_TWL4030_LED
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+ /* Configure GPMC registers for DM9000 */
+ enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
+ CONFIG_DM9000_BASE, GPMC_SIZE_16M);
+
+ /* Use OMAP DIE_ID as MAC address */
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ printf("ethaddr not set, using Die ID\n");
+ die_id_0 = readl(&id_base->die_id_0);
+ enetaddr[0] = 0x02; /* locally administered */
+ enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
+ enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
+ enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
+ enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
+ enetaddr[5] = (die_id_0 & 0x000000ff);
+ eth_setenv_enetaddr("ethaddr", enetaddr);
+ }
+#endif
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_DEVKIT8000();
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC)
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
+
+#if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
+/*
+ * Routine: board_eth_init
+ * Description: Setting up the Ethernet hardware.
+ */
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * Do board specific preperation before SPL
+ * Linux boot
+ */
+void spl_board_prepare_for_linux(void)
+{
+ gpmc_dm9000_config();
+}
+
+/*
+ * devkit8000 specific implementation of spl_start_uboot()
+ *
+ * RETURN
+ * 0 if the button is not pressed
+ * 1 if the button is pressed
+ */
+int spl_start_uboot(void)
+{
+ int val = 0;
+ if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
+ gpio_direction_input(SPL_OS_BOOT_KEY);
+ val = gpio_get_value(SPL_OS_BOOT_KEY);
+ gpio_free(SPL_OS_BOOT_KEY);
+ }
+ return !val;
+}
+#endif
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank. This
+ * provides the timing values back to the function that configures
+ * the memory. We have either one or two banks of 128MB DDR.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ /* General SDRC config */
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+
+ /* AC timings */
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+
+ timings->mr = MICRON_V_MR_165;
+}
diff --git a/board/timll/devkit8000/devkit8000.h b/board/timll/devkit8000/devkit8000.h
new file mode 100644
index 0000000..a7a37fe
--- /dev/null
+++ b/board/timll/devkit8000/devkit8000.h
@@ -0,0 +1,360 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _DEVKIT8000_H_
+#define _DEVKIT8000_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "OMAP3 DevKit8000",
+ "NAND",
+};
+
+/* GPIO used to select between U-Boot and kernel */
+#define SPL_OS_BOOT_KEY 26
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+#define MUX_DEVKIT8000() \
+ /* SDRC */\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /* GPMC */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0 NAND*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6 DM9000*/\
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ /* DSS */\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /* CAMERA */\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /* Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /* MMC Slot */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
+ /* Expansion Header */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\
+ MUX_VAL(CP(UART2_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_144*/\
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*GPIO_148*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*GPIO_151*/\
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*GPIO_152*/\
+ MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*GPIO_153*/\
+ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*GPIO_154*/\
+ MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*GPIO_155*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*GPIO_160*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /* Serial Interface */\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | EN | M4)) /*GPIO_163 - LED2*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)) /*GPIO_164 - LED3*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ /* Host USB0 */\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IDIS | PTU | DIS | M4)) /*GPIO_168*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | DIS | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTD | DIS | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*MCSPI1_SOMI*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | DIS | M0)) /*MCSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | DIS | M0)) /*MCSPI1_CS1*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+ /* USB EHCI (port 2) */\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*HSUSB2_DATA2*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA7*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA4*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*HSUSB2_DATA5*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*HSUSB2_DATA6*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*HSUSB2_DATA3*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | EN | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | EN | M4)) /*GPIO_186 - LED1*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | EN | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTU | EN | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | EN | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | EN | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | EN | M4)) /*GPIO_29*/\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*D2D_MCAD1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*D2D_MCAD2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*D2D_MCAD3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*D2D_MCAD4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*D2D_MCAD5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*D2D_MCAD6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*D2D_MCAD7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*D2D_MCAD8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*D2D_MCAD9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*D2D_MCAD10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*D2D_MCAD11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*D2D_MCAD12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*D2D_MCAD13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*D2D_MCAD14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*D2D_MCAD15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*D2D_MCAD16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*D2D_MCAD17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*D2D_MCAD18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*D2D_MCAD19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*D2D_MCAD20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*D2D_MCAD21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*D2D_MCAD22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*D2D_MCAD23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*D2D_MCAD24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*D2D_MCAD25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*D2D_MCAD26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*D2D_MCAD27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*D2D_MCAD28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*D2D_MCAD29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*D2D_MCAD30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*D2D_MCAD31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*D2D_MCAD32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*D2D_MCAD33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*D2D_MCAD34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*D2D_MCAD35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*D2D_MCAD36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*D2D_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*D2D_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*D2D_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*D2D_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*D2D_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*D2D_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*D2D_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*D2D_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*D2D_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*D2D_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*D2D_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*D2D_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*D2D_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*D2D_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*D2D_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*D2D_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*D2D_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*D2D_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*D2D_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*D2D_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*D2D_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*D2D_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*D2D_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*D2D_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*D2D_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*D2D_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+
+#endif
diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig
new file mode 100644
index 0000000..f1dcda5
--- /dev/null
+++ b/board/toradex/apalis_t30/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_APALIS_T30
+
+config SYS_BOARD
+ default "apalis_t30"
+
+config SYS_VENDOR
+ default "toradex"
+
+config SYS_CONFIG_NAME
+ default "apalis_t30"
+
+endif
diff --git a/board/toradex/apalis_t30/MAINTAINERS b/board/toradex/apalis_t30/MAINTAINERS
new file mode 100644
index 0000000..01bc73e
--- /dev/null
+++ b/board/toradex/apalis_t30/MAINTAINERS
@@ -0,0 +1,7 @@
+Apalis T30
+M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
+S: Maintained
+F: board/toradex/apalis_t30/
+F: include/configs/apalis_t30.h
+F: configs/apalis_t30_defconfig
+F: arch/arm/dts/tegra30-apalis.dtb
diff --git a/board/toradex/apalis_t30/Makefile b/board/toradex/apalis_t30/Makefile
new file mode 100644
index 0000000..a968e6b
--- /dev/null
+++ b/board/toradex/apalis_t30/Makefile
@@ -0,0 +1,6 @@
+# Copyright (c) 2014 Marcel Ziswiler
+# SPDX-License-Identifier: GPL-2.0+
+
+include $(srctree)/board/nvidia/common/common.mk
+
+obj-y += apalis_t30.o
diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c
new file mode 100644
index 0000000..5d2c024
--- /dev/null
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2014
+ * Marcel Ziswiler <marcel@ziswiler.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <netdev.h>
+
+#include "pinmux-config-apalis_t30.h"
+
+#define PMU_I2C_ADDRESS 0x2D
+#define MAX_I2C_RETRY 3
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_config_pingrp_table(tegra3_pinmux_common,
+ ARRAY_SIZE(tegra3_pinmux_common));
+
+ pinmux_config_pingrp_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
+
+ /* Initialize any non-default pad configs (APB_MISC_GP regs) */
+ pinmux_config_drvgrp_table(apalis_t30_padctrl,
+ ARRAY_SIZE(apalis_t30_padctrl));
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+ struct udevice *dev;
+ u8 addr, data[1];
+ int err;
+
+ err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
+ if (err) {
+ debug("%s: Cannot find PMIC I2C chip\n", __func__);
+ return err;
+ }
+ /* TPS659110: VDD2_OP_REG = 1.05V */
+ data[0] = 0x27;
+ addr = 0x25;
+
+ err = i2c_write(dev, addr, data, 1);
+ if (err) {
+ debug("failed to set VDD supply\n");
+ return err;
+ }
+
+ /* TPS659110: VDD2_REG 7.5 mV/us, ACTIVE */
+ data[0] = 0x0D;
+ addr = 0x24;
+
+ err = i2c_write(dev, addr, data, 1);
+ if (err) {
+ debug("failed to enable VDD supply\n");
+ return err;
+ }
+
+ /* TPS659110: LDO6_REG = 1.1V, ACTIVE */
+ data[0] = 0x0D;
+ addr = 0x35;
+
+ err = i2c_write(dev, addr, data, 1);
+ if (err) {
+ debug("failed to set AVDD supply\n");
+ return err;
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+#endif /* CONFIG_PCI_TEGRA */
diff --git a/board/toradex/apalis_t30/pinmux-config-apalis_t30.h b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
new file mode 100644
index 0000000..c988d39
--- /dev/null
+++ b/board/toradex/apalis_t30/pinmux-config-apalis_t30.h
@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2014, Marcel Ziswiler
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PINMUX_CONFIG_APALIS_T30_H_
+#define _PINMUX_CONFIG_APALIS_T30_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static struct pmux_pingrp_config tegra3_pinmux_common[] = {
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, NORMAL, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, NORMAL, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux (eMMC) */
+ LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* I2C1 pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C2 pinmux */
+ I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C3 pinmux */
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
+
+ /* I2C4 pinmux */
+ I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* Power I2C pinmux */
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+ /* UARTA RX, make sure we don't get input form a floating Pin */
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
+ LV_PINMUX(VI_D0_PT4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1_PD5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2_PL0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3_PL1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5_PL3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7_PL5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10_PT2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D11_PT3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC_PD7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, PWM0, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU0, RSVD1, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(PU1, RSVD1, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(PU2, RSVD1, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(PU3, PWM0, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU6, PWM3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(GMI_AD10_PH2, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(GMI_A17_PB0, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(GMI_A19_PK7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */
+
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
+
+ /* multiplexed VI_D2, VI_D3, VI_D4, VI_D5, VI_D6, VI_D7, VI_D8 and VI_D9
+ */
+ DEFAULT_PINMUX(KB_ROW0_PR0, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, TRISTATE, INPUT),
+
+ /* GPIOs */
+ DEFAULT_PINMUX(KB_ROW10_PS2, SDMMC2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11_PS3, SDMMC2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12_PS4, SDMMC2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, SDMMC2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, SDMMC2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15_PS7, SDMMC2, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(PV0, RSVD1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT),
+ /* multiplexed KB_COL0 */
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, TRISTATE, OUTPUT),
+
+ DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(GMI_AD12_PH4, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
+ DEFAULT_PINMUX(GMI_AD14_PH6, NAND, DOWN, TRISTATE, OUTPUT), /* NC */
+
+ DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, NORMAL, INPUT),
+};
+
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+ DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD0_PG0, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4_PG4, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, DOWN, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_DQS_PI2, NAND, DOWN, TRISTATE, OUTPUT),
+};
+
+static struct pmux_drvgrp_config apalis_t30_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+ DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+ SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif /* _PINMUX_CONFIG_APALIS_T30_H_ */
diff --git a/board/toradex/colibri_pxa270/Kconfig b/board/toradex/colibri_pxa270/Kconfig
new file mode 100644
index 0000000..949407a
--- /dev/null
+++ b/board/toradex/colibri_pxa270/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_COLIBRI_PXA270
+
+config SYS_BOARD
+ default "colibri_pxa270"
+
+config SYS_VENDOR
+ default "toradex"
+
+config SYS_CONFIG_NAME
+ default "colibri_pxa270"
+
+endif
diff --git a/board/toradex/colibri_pxa270/MAINTAINERS b/board/toradex/colibri_pxa270/MAINTAINERS
new file mode 100644
index 0000000..b378d7b
--- /dev/null
+++ b/board/toradex/colibri_pxa270/MAINTAINERS
@@ -0,0 +1,6 @@
+COLIBRI_PXA270 BOARD
+M: Marek Vasut <marek.vasut@gmail.com>
+S: Maintained
+F: board/toradex/colibri_pxa270/
+F: include/configs/colibri_pxa270.h
+F: configs/colibri_pxa270_defconfig
diff --git a/board/toradex/colibri_pxa270/Makefile b/board/toradex/colibri_pxa270/Makefile
new file mode 100644
index 0000000..57cfe9b
--- /dev/null
+++ b/board/toradex/colibri_pxa270/Makefile
@@ -0,0 +1,9 @@
+#
+# Toradex Colibri PXA270 Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := colibri_pxa270.o
diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c
new file mode 100644
index 0000000..8d95e4d
--- /dev/null
+++ b/board/toradex/colibri_pxa270/colibri_pxa270.c
@@ -0,0 +1,107 @@
+/*
+ * Toradex Colibri PXA270 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/regs-mmc.h>
+#include <asm/arch/pxa.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* arch number of vpac270 */
+ gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ pxa2xx_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_CMD_USB
+int board_usb_init(int index, enum usb_init_type init)
+{
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
+
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+ while (UHCHR & UHCHR_FSBIR)
+ ;
+
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+ /* Clear any OTG Pin Hold */
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+ /* Set port power control mask bits, only 3 ports. */
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+ /* enable port 2 */
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+void usb_board_stop(void)
+{
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+ udelay(11);
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
+ udelay(10);
+
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+ return;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.c b/board/toradex/colibri_t20-common/colibri_t20-common.c
new file mode 100644
index 0000000..58a9916
--- /dev/null
+++ b/board/toradex/colibri_t20-common/colibri_t20-common.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2012 Lucas Stach
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/board.h>
+
+#include "colibri_t20-common.h"
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+void colibri_t20_common_pin_mux_usb(void)
+{
+ /* module internal USB bus to connect ethernet chipset */
+ funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+ /* ULPI reference clock output */
+ pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+ pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+ /* PHY reset GPIO */
+ pinmux_tristate_disable(PMUX_PINGRP_UAC);
+ /* VBus GPIO */
+ pinmux_tristate_disable(PMUX_PINGRP_DTE);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_NAND
+void pin_mux_nand(void)
+{
+ funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT);
+}
+#endif
diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.h b/board/toradex/colibri_t20-common/colibri_t20-common.h
new file mode 100644
index 0000000..1fe53f6
--- /dev/null
+++ b/board/toradex/colibri_t20-common/colibri_t20-common.h
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2012 Lucas Stach
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+void colibri_t20_common_pin_mux_usb(void);
diff --git a/board/toradex/colibri_t20_iris/Kconfig b/board/toradex/colibri_t20_iris/Kconfig
new file mode 100644
index 0000000..4bf7278
--- /dev/null
+++ b/board/toradex/colibri_t20_iris/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_COLIBRI_T20_IRIS
+
+config SYS_BOARD
+ default "colibri_t20_iris"
+
+config SYS_VENDOR
+ default "toradex"
+
+config SYS_CONFIG_NAME
+ default "colibri_t20_iris"
+
+endif
diff --git a/board/toradex/colibri_t20_iris/MAINTAINERS b/board/toradex/colibri_t20_iris/MAINTAINERS
new file mode 100644
index 0000000..c68955b
--- /dev/null
+++ b/board/toradex/colibri_t20_iris/MAINTAINERS
@@ -0,0 +1,6 @@
+COLIBRI_T20_IRIS BOARD
+M: Lucas Stach <dev@lynxeye.de>
+S: Maintained
+F: board/toradex/colibri_t20_iris/
+F: include/configs/colibri_t20_iris.h
+F: configs/colibri_t20_iris_defconfig
diff --git a/board/toradex/colibri_t20_iris/Makefile b/board/toradex/colibri_t20_iris/Makefile
new file mode 100644
index 0000000..ebeac70
--- /dev/null
+++ b/board/toradex/colibri_t20_iris/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2012 Lucas Stach
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ../../nvidia/common/board.o
+obj-y += ../colibri_t20-common/colibri_t20-common.o
+obj-y += colibri_t20_iris.o
diff --git a/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/board/toradex/colibri_t20_iris/colibri_t20_iris.c
new file mode 100644
index 0000000..49c74f3
--- /dev/null
+++ b/board/toradex/colibri_t20_iris/colibri_t20_iris.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2012 Lucas Stach
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch-tegra/board.h>
+
+#include "../colibri_t20-common/colibri_t20-common.h"
+
+#ifdef CONFIG_USB_EHCI_TEGRA
+void pin_mux_usb(void)
+{
+ colibri_t20_common_pin_mux_usb();
+
+ /* USB 1 aka Tegra USB port 3 VBus*/
+ pinmux_tristate_disable(PMUX_PINGRP_SPIG);
+}
+#endif
+
+#ifdef CONFIG_TEGRA_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
+{
+ funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
+ pinmux_tristate_disable(PMUX_PINGRP_GMB);
+}
+#endif
diff --git a/board/toradex/colibri_t30/Kconfig b/board/toradex/colibri_t30/Kconfig
new file mode 100644
index 0000000..3e436a2
--- /dev/null
+++ b/board/toradex/colibri_t30/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_COLIBRI_T30
+
+config SYS_BOARD
+ default "colibri_t30"
+
+config SYS_VENDOR
+ default "toradex"
+
+config SYS_CONFIG_NAME
+ default "colibri_t30"
+
+endif
diff --git a/board/toradex/colibri_t30/MAINTAINERS b/board/toradex/colibri_t30/MAINTAINERS
new file mode 100644
index 0000000..73b8e5d
--- /dev/null
+++ b/board/toradex/colibri_t30/MAINTAINERS
@@ -0,0 +1,7 @@
+Colibri T30
+M: Stefan Agner <stefan.agner@toradex.com>
+S: Maintained
+F: board/toradex/colibri_t30/
+F: include/configs/colibri_t30.h
+F: configs/colibri_t30_defconfig
+F: arch/arm/dts/tegra30-colibri.dtb
diff --git a/board/toradex/colibri_t30/Makefile b/board/toradex/colibri_t30/Makefile
new file mode 100644
index 0000000..3d58a4b
--- /dev/null
+++ b/board/toradex/colibri_t30/Makefile
@@ -0,0 +1,6 @@
+# Copyright (c) 2013-2014 Stefan Agner
+# SPDX-License-Identifier: GPL-2.0+
+
+include $(srctree)/board/nvidia/common/common.mk
+
+obj-y += colibri_t30.o
diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c
new file mode 100644
index 0000000..f4bc7d8
--- /dev/null
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2014
+ * Stefan Agner <stefan@agner.ch>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include "pinmux-config-colibri_t30.h"
+#include <i2c.h>
+#include <asm/gpio.h>
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_config_pingrp_table(tegra3_pinmux_common,
+ ARRAY_SIZE(tegra3_pinmux_common));
+
+ pinmux_config_pingrp_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
+
+ /* Initialize any non-default pad configs (APB_MISC_GP regs) */
+ pinmux_config_drvgrp_table(colibri_t30_padctrl,
+ ARRAY_SIZE(colibri_t30_padctrl));
+}
+
+/*
+ * Enable AX88772B USB to LAN controller
+ */
+void pin_mux_usb(void)
+{
+ /* Reset ASIX using LAN_RESET */
+ gpio_request(GPIO_PDD0, "LAN_RESET");
+ gpio_direction_output(GPIO_PDD0, 0);
+ udelay(5);
+ gpio_set_value(GPIO_PDD0, 1);
+}
diff --git a/board/toradex/colibri_t30/pinmux-config-colibri_t30.h b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h
new file mode 100644
index 0000000..4e73c07
--- /dev/null
+++ b/board/toradex/colibri_t30/pinmux-config-colibri_t30.h
@@ -0,0 +1,360 @@
+/*
+ * Copyright (c) 2013-2014, Stefan Agner
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PINMUX_CONFIG_COLIBRI_T30_H_
+#define _PINMUX_CONFIG_COLIBRI_T30_H_
+
+#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingrp = PMUX_PINGRP_##_pingrp, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+ { \
+ .drvgrp = PMUX_DRVGRP_##_drvgrp, \
+ .slwf = _slwf, \
+ .slwr = _slwr, \
+ .drvup = _drvup, \
+ .drvdn = _drvdn, \
+ .lpmd = PMUX_LPMD_##_lpmd, \
+ .schmt = PMUX_SCHMT_##_schmt, \
+ .hsm = PMUX_HSM_##_hsm, \
+ }
+
+static struct pmux_pingrp_config tegra3_pinmux_common[] = {
+ /* SDMMC1 disabled */
+ DEFAULT_PINMUX(SDMMC1_CLK_PZ0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD_PZ1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3_PY4, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2_PY5, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1_PY6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0_PY7, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux (eMMC) */
+ LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* I2C1 pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C2 pinmux */
+ DEFAULT_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT),
+
+ /* I2C3 pinmux, muliplexed with KB_ROW13/KB_ROW14 */
+ I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE),
+
+ /* I2C4 pinmux */
+ I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* Power I2C pinmux */
+ I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
+ /* UARTA RX, make sure we don't get input form a floating Pin */
+ DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
+ LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
+ DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
+ DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
+ DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A17_PB0, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18_PB1, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19_PK7, UARTD, NORMAL, NORMAL, INPUT),
+
+
+ /* Multiplexed with KB_ROW10/KB_ROW11/KB_ROW12/KB_ROW15 */
+ DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, UP, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(PBB3, VGP3, NORMAL, TRISTATE, INPUT),
+
+ DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
+
+ /* KBC keys */
+ DEFAULT_PINMUX(KB_ROW0_PR0, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW1_PR1, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW2_PR2, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW3_PR3, RSVD2, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW4_PR4, RSVD3, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, TRISTATE, INPUT),
+
+ /* SDMMC2 pinmux */
+ DEFAULT_PINMUX(KB_ROW10_PS2, SDMMC2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11_PS3, SDMMC2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12_PS4, SDMMC2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13_PS5, SDMMC2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14_PS6, SDMMC2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15_PS7, SDMMC2, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
+
+ /* LAN_RESET */
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, RSVD2, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
+
+ /* LAN_VBUS */
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, RSVD2, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
+
+ /* GPIOs */
+ /* SDMMC1 CD gpio */
+ DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
+ /* SDMMC1 WP gpio */
+ LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* Touch panel GPIO */
+ /* Touch IRQ */
+ DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
+
+ /* Touch RESET */
+ DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
+
+ /* Power rails GPIO */
+ DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
+
+ LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+};
+
+static struct pmux_pingrp_config unused_pins_lowpower[] = {
+ DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+static struct pmux_drvgrp_config colibri_t30_padctrl[] = {
+ /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+ DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+ SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif /* _PINMUX_CONFIG_COLIBRI_T30_H_ */
diff --git a/board/total5200/Kconfig b/board/total5200/Kconfig
new file mode 100644
index 0000000..ffa9516
--- /dev/null
+++ b/board/total5200/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_TOTAL5200
+
+config SYS_BOARD
+ default "total5200"
+
+config SYS_CONFIG_NAME
+ default "Total5200"
+
+endif
diff --git a/board/total5200/MAINTAINERS b/board/total5200/MAINTAINERS
new file mode 100644
index 0000000..afb0058
--- /dev/null
+++ b/board/total5200/MAINTAINERS
@@ -0,0 +1,9 @@
+TOTAL5200 BOARD
+#M: -
+S: Maintained
+F: board/total5200/
+F: include/configs/Total5200.h
+F: configs/Total5200_defconfig
+F: configs/Total5200_lowboot_defconfig
+F: configs/Total5200_Rev2_defconfig
+F: configs/Total5200_Rev2_lowboot_defconfig
diff --git a/board/total5200/Makefile b/board/total5200/Makefile
new file mode 100644
index 0000000..527557c
--- /dev/null
+++ b/board/total5200/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := total5200.o sdram.o
diff --git a/board/total5200/mt48lc16m16a2-75.h b/board/total5200/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..068a9a6
--- /dev/null
+++ b/board/total5200/mt48lc16m16a2-75.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 0 /* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/total5200/mt48lc32m16a2-75.h b/board/total5200/mt48lc32m16a2-75.h
new file mode 100644
index 0000000..0377417
--- /dev/null
+++ b/board/total5200/mt48lc32m16a2-75.h
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Micron MT48LC32M16A2-75 is compatible to:
+ * - Infineon HYB39S512160AT-75
+ */
+
+#define SDRAM_DDR 0 /* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x514F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c
new file mode 100644
index 0000000..dbe3587
--- /dev/null
+++ b/board/total5200/sdram.c
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+#include "sdram.h"
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ if (sdram_conf->ddr) {
+ /* set mode register: extended mode */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->emode;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode | 0x04000000;
+ __asm__ volatile ("sync");
+ }
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
+ __asm__ volatile ("sync");
+
+ if (sdram_conf->ddr) {
+ /* set tap delay */
+ *(vu_long *)MPC5XXX_CDM_PORCFG = sdram_conf->tapdelay;
+ __asm__ volatile ("sync");
+ }
+
+ /* find RAM size using SDRAM CS0 only */
+ mpc5xxx_sdram_start(sdram_conf, 0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ mpc5xxx_sdram_start(sdram_conf, 1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ mpc5xxx_sdram_start(sdram_conf, 0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ }
+
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+ /* find RAM size using SDRAM CS1 only */
+ mpc5xxx_sdram_start(sdram_conf, 0);
+ test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ mpc5xxx_sdram_start(sdram_conf, 1);
+ test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ if (test1 > test2) {
+ mpc5xxx_sdram_start(sdram_conf, 0);
+ dramsize2 = test1;
+ } else {
+ dramsize2 = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20)) {
+ dramsize2 = 0;
+ }
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+ | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13) {
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ } else {
+ dramsize = 0;
+ }
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ if (dramsize2 >= 0x13) {
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ } else {
+ dramsize2 = 0;
+ }
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ return dramsize + dramsize2;
+}
diff --git a/board/total5200/sdram.h b/board/total5200/sdram.h
new file mode 100644
index 0000000..3758f5c9
--- /dev/null
+++ b/board/total5200/sdram.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+typedef struct {
+ ulong ddr;
+ ulong mode;
+ ulong emode;
+ ulong control;
+ ulong config1;
+ ulong config2;
+ ulong tapdelay;
+} sdram_conf_t;
+
+long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf);
diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c
new file mode 100644
index 0000000..345a186
--- /dev/null
+++ b/board/total5200/total5200.c
@@ -0,0 +1,276 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <netdev.h>
+
+#include "sdram.h"
+
+#if CONFIG_TOTAL5200_REV==2
+#include "mt48lc32m16a2-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+phys_size_t initdram (int board_type)
+{
+ sdram_conf_t sdram_conf;
+
+ sdram_conf.ddr = SDRAM_DDR;
+ sdram_conf.mode = SDRAM_MODE;
+ sdram_conf.emode = 0;
+ sdram_conf.control = SDRAM_CONTROL;
+ sdram_conf.config1 = SDRAM_CONFIG1;
+ sdram_conf.config2 = SDRAM_CONFIG2;
+ sdram_conf.tapdelay = 0;
+ return mpc5xxx_sdram_init (&sdram_conf);
+}
+
+int checkboard (void)
+{
+#if CONFIG_TOTAL5200_REV==2
+ puts ("Board: Total5200 Rev.2 ");
+#else
+ puts ("Board: Total5200 ");
+#endif
+
+ /*
+ * Retrieve FPGA Revision.
+ */
+ printf ("(FPGA %08lX)\n", *(vu_long *) (CONFIG_SYS_FPGA_BASE + 0x400));
+
+ /*
+ * Take all peripherals in power-up mode.
+ */
+#if CONFIG_TOTAL5200_REV==2
+ *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x46) = 0x70;
+#else
+ *(vu_long *) (CONFIG_SYS_CPLD_BASE + 0x400) = 0x70;
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+/* IRDA_1 aka PSC6_3 (pin C13) */
+#define GPIO_IRDA_1 0x20000000UL
+
+void init_ide_reset (void)
+{
+ debug ("init_ide_reset\n");
+
+ /* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1;
+ *(vu_long *) MPC5XXX_GPIO_DIR |= GPIO_IRDA_1;
+}
+
+void ide_set_reset (int idereset)
+{
+ debug ("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ *(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1;
+ } else {
+ *(vu_long *) MPC5XXX_GPIO_DATA_O |= GPIO_IRDA_1;
+ }
+}
+#endif
+
+#ifdef CONFIG_VIDEO_SED13806
+#include <sed13806.h>
+
+#define DISPLAY_WIDTH 640
+#define DISPLAY_HEIGHT 480
+
+#ifdef CONFIG_VIDEO_SED13806_8BPP
+#error CONFIG_VIDEO_SED13806_8BPP not supported.
+#endif /* CONFIG_VIDEO_SED13806_8BPP */
+
+#ifdef CONFIG_VIDEO_SED13806_16BPP
+static const S1D_REGS init_regs [] =
+{
+ {0x0001,0x00}, /* Miscellaneous Register */
+ {0x01FC,0x00}, /* Display Mode Register */
+ {0x0004,0x00}, /* General IO Pins Configuration Register 0 */
+ {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
+ {0x0008,0x00}, /* General IO Pins Control Register 0 */
+ {0x0009,0x00}, /* General IO Pins Control Register 1 */
+ {0x0010,0x02}, /* Memory Clock Configuration Register */
+ {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */
+ {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
+ {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
+ {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
+ {0x0021,0x03}, /* DRAM Refresh Rate Register */
+ {0x002A,0x00}, /* DRAM Timings Control Register 0 */
+ {0x002B,0x01}, /* DRAM Timings Control Register 1 */
+ {0x0020,0x80}, /* Memory Configuration Register */
+ {0x0030,0x25}, /* Panel Type Register */
+ {0x0031,0x00}, /* MOD Rate Register */
+ {0x0032,0x4F}, /* LCD Horizontal Display Width Register */
+ {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
+ {0x0035,0x01}, /* TFT FPLINE Start Position Register */
+ {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
+ {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
+ {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
+ {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
+ {0x003B,0x0A}, /* TFT FPFRAME Start Position Register */
+ {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
+ {0x0040,0x05}, /* LCD Display Mode Register */
+ {0x0041,0x00}, /* LCD Miscellaneous Register */
+ {0x0042,0x00}, /* LCD Display Start Address Register 0 */
+ {0x0043,0x00}, /* LCD Display Start Address Register 1 */
+ {0x0044,0x00}, /* LCD Display Start Address Register 2 */
+ {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
+ {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
+ {0x0048,0x00}, /* LCD Pixel Panning Register */
+ {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
+ {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
+ {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
+ {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
+ {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
+ {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
+ {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
+ {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
+ {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
+ {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
+ {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
+ {0x005B,0x10}, /* TV Output Control Register */
+ {0x0060,0x05}, /* CRT/TV Display Mode Register */
+ {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
+ {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
+ {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
+ {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
+ {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
+ {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
+ {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
+ {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
+ {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
+ {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */
+ {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
+ {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
+ {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
+ {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
+ {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
+ {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
+ {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
+ {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
+ {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
+ {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
+ {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
+ {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
+ {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */
+ {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
+ {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
+ {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
+ {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
+ {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
+ {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
+ {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
+ {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
+ {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
+ {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
+ {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
+ {0x0100,0x00}, /* BitBlt Control Register 0 */
+ {0x0101,0x00}, /* BitBlt Control Register 1 */
+ {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
+ {0x0103,0x00}, /* BitBlt Operation Register */
+ {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
+ {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
+ {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
+ {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
+ {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
+ {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
+ {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
+ {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
+ {0x0110,0x00}, /* BitBlt Width Register 0 */
+ {0x0111,0x00}, /* BitBlt Width Register 1 */
+ {0x0112,0x00}, /* BitBlt Height Register 0 */
+ {0x0113,0x00}, /* BitBlt Height Register 1 */
+ {0x0114,0x00}, /* BitBlt Background Color Register 0 */
+ {0x0115,0x00}, /* BitBlt Background Color Register 1 */
+ {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
+ {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
+ {0x01E0,0x00}, /* Look-Up Table Mode Register */
+ {0x01E2,0x00}, /* Look-Up Table Address Register */
+ {0x01E4,0x00}, /* Look-Up Table Data Register */
+ {0x01F0,0x00}, /* Power Save Configuration Register */
+ {0x01F1,0x00}, /* Power Save Status Register */
+ {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
+ {0x01FC,0x01}, /* Display Mode Register */
+ {0, 0}
+};
+#endif /* CONFIG_VIDEO_SED13806_16BPP */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/* Return text to be printed besides the logo. */
+void video_get_info_str (int line_number, char *info)
+{
+ if (line_number == 1) {
+#if CONFIG_TOTAL5200_REV==1
+ strcpy (info, " Total5200");
+#elif CONFIG_TOTAL5200_REV==2
+ strcpy (info, " Total5200 Rev.2");
+#else
+#error CONFIG_TOTAL5200_REV must be 1 or 2.
+#endif
+ } else {
+ info [0] = '\0';
+ }
+}
+#endif
+
+/* Returns SED13806 base address. First thing called in the driver. */
+unsigned int board_video_init (void)
+{
+ return CONFIG_SYS_LCD_BASE;
+}
+
+/* Called after initializing the SED13806 and before clearing the screen. */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/* Return a pointer to the initialization sequence. */
+const S1D_REGS *board_get_regs (void)
+{
+ return init_regs;
+}
+
+int board_get_width (void)
+{
+ return DISPLAY_WIDTH;
+}
+
+int board_get_height (void)
+{
+ return DISPLAY_HEIGHT;
+}
+
+#endif /* CONFIG_VIDEO_SED13806 */
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
diff --git a/board/tqc/tqm5200/Kconfig b/board/tqc/tqm5200/Kconfig
new file mode 100644
index 0000000..0e4cd69
--- /dev/null
+++ b/board/tqc/tqm5200/Kconfig
@@ -0,0 +1,51 @@
+if TARGET_AEV
+
+config SYS_BOARD
+ default "tqm5200"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "aev"
+
+endif
+
+if TARGET_CHARON
+
+config SYS_BOARD
+ default "tqm5200"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "charon"
+
+endif
+
+if TARGET_TB5200
+
+config SYS_BOARD
+ default "tqm5200"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TB5200"
+
+endif
+
+if TARGET_TQM5200
+
+config SYS_BOARD
+ default "tqm5200"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM5200"
+
+endif
diff --git a/board/tqc/tqm5200/MAINTAINERS b/board/tqc/tqm5200/MAINTAINERS
new file mode 100644
index 0000000..d3eb543
--- /dev/null
+++ b/board/tqc/tqm5200/MAINTAINERS
@@ -0,0 +1,26 @@
+TQM5200 BOARD
+#M: -
+S: Maintained
+F: board/tqc/tqm5200/
+F: include/configs/aev.h
+F: configs/aev_defconfig
+F: include/configs/TQM5200.h
+F: configs/cam5200_defconfig
+F: configs/cam5200_niosflash_defconfig
+F: configs/fo300_defconfig
+F: configs/MiniFAP_defconfig
+F: include/configs/TB5200.h
+F: configs/TB5200_defconfig
+F: configs/TB5200_B_defconfig
+F: configs/TQM5200_defconfig
+F: configs/TQM5200_B_defconfig
+F: configs/TQM5200_B_HIGHBOOT_defconfig
+F: configs/TQM5200_STK100_defconfig
+F: configs/TQM5200S_defconfig
+F: configs/TQM5200S_HIGHBOOT_defconfig
+
+CHARON BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: include/configs/charon.h
+F: configs/charon_defconfig
diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile
new file mode 100644
index 0000000..80c1eba
--- /dev/null
+++ b/board/tqc/tqm5200/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := tqm5200.o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o
diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c
new file mode 100644
index 0000000..c3ae5c0
--- /dev/null
+++ b/board/tqc/tqm5200/cam5200_flash.c
@@ -0,0 +1,768 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <asm/processor.h>
+
+#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
+
+#if 0
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif
+
+#define swap16(x) __swab16(x)
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * CAM5200 is a TQM5200B based board. Additionally it also features
+ * a NIOS cpu. The NIOS CPU peripherals are accessible through MPC5xxx
+ * Local Bus on CS5. This includes 32 bit wide RAM and SRAM as well as
+ * 16 bit wide flash device. Big Endian order on a 32 bit CS5 makes
+ * access to flash chip slightly more complicated as additional byte
+ * swapping is necessary within each 16 bit wide flash 'word'.
+ *
+ * This driver's task is to handle both flash devices: 32 bit TQM5200B
+ * flash chip and 16 bit NIOS cpu flash chip. In the below
+ * flash_addr_table table we use least significant address bit to mark
+ * 16 bit flash bank and two sets of routines *_32 and *_16 to handle
+ * specifics of both flashes.
+ */
+static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
+ {CONFIG_SYS_BOOTCS_START, CONFIG_SYS_CS5_START | 1}
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word_32(flash_info_t * info, ulong dest, ulong data);
+static int write_word_16(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_32(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_16(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_32(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_16(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+ int i, k;
+ int size, erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_S29GL128N:
+ printf ("S29GL128N (256 Mbit, uniform sector size)\n");
+ break;
+ case FLASH_AM320B:
+ printf ("29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T:
+ printf ("29LV320T (32 Mbit, top boot sect)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ break;
+ }
+
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf("\n ");
+
+ printf(" %08lX%s%s", info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " ");
+ }
+ printf("\n");
+ return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+
+ DEBUGF("get_size: FLASH ADDR %08lx\n", addr);
+
+ /* bit 0 used for big flash marking */
+ if ((ulong)addr & 0x1)
+ return flash_get_size_16((vu_long *)((ulong)addr & 0xfffffffe), info);
+ else
+ return flash_get_size_32(addr, info);
+}
+
+static ulong flash_get_size_32(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+ short i;
+ CONFIG_SYS_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+ udelay(1000);
+
+ value = addr2[0];
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr2[1]; /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case AMD_ID_MIRROR:
+ DEBUGF("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
+ addr[14], addr[15]);
+ switch(addr[14]) {
+ case AMD_ID_GL128N_2:
+ if (addr[15] != AMD_ID_GL128N_3) {
+ DEBUGF("Chip: S29GL128N -> unknown\n");
+ info->flash_id = FLASH_UNKNOWN;
+ } else {
+ DEBUGF("Chip: S29GL128N\n");
+ info->flash_id += FLASH_S29GL128N;
+ info->sector_count = 128;
+ info->size = 0x02000000;
+ }
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return(0);
+ }
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ /* set up sector start address table */
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00040000);
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+ return (info->size);
+}
+
+static int wait_for_DQ7_32(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+ (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+ (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
+ return flash_erase_16(info, s_first, s_last);
+ } else {
+ return flash_erase_32(info, s_first, s_last);
+ }
+}
+
+static int flash_erase_32(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!", prot);
+
+ printf("\n");
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
+
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_32(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+
+ for (; cnt == 0 && i < 4; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ if ((rc = write_word(info, wp, data)) != 0)
+ return (rc);
+
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i)
+ data = (data << 8) | *src++;
+
+ if ((rc = write_word(info, wp, data)) != 0)
+ return (rc);
+
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0)
+ return (0);
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < 4; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
+ return write_word_16(info, dest, data);
+ } else {
+ return write_word_32(info, dest, data);
+ }
+}
+
+static int write_word_32(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+ ulong *datap = &data;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
+ (volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
+ ulong start;
+ int i, flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_long *)dest) & data) != data)
+ return (2);
+
+ for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+ (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+ return (1);
+ }
+ }
+
+ return (0);
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+
+#undef CONFIG_SYS_FLASH_WORD_SIZE
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_16(vu_long * addr, flash_info_t * info)
+{
+ short i;
+ CONFIG_SYS_FLASH_WORD_SIZE value;
+ ulong base = (ulong) addr;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+ DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr);
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90009000;
+ udelay(1000);
+
+ value = swap16(addr2[0]);
+ DEBUGF("FLASH MANUFACT: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = swap16(addr2[1]); /* device ID */
+ DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+ switch (value) {
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+ }
+
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00002000;
+ info->start[2] = base + 0x00004000;
+ info->start[3] = base + 0x00006000;
+ info->start[4] = base + 0x00008000;
+ info->start[5] = base + 0x0000a000;
+ info->start[6] = base + 0x0000c000;
+ info->start[7] = base + 0x0000e000;
+
+ for (i = 8; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000) - 0x00070000;
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00002000;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ info->start[i--] = base + info->size - 0x0000a000;
+ info->start[i--] = base + info->size - 0x0000c000;
+ info->start[i--] = base + info->size - 0x0000e000;
+
+ for (; i >= 0; i--)
+ info->start[i] = base + i * 0x00010000;
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ /* D0 = 1 if protected */
+ addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+ info->protect[i] = addr2[2] & 1;
+ }
+
+ /* issue bank reset to return to read mode */
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
+
+ return (info->size);
+}
+
+static int wait_for_DQ7_16(flash_info_t * info, int sect)
+{
+ ulong start, now, last;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+ (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ start = get_timer(0);
+ last = start;
+ while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
+ (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+ return 0;
+}
+
+static int flash_erase_16(flash_info_t * info, int s_first, int s_last)
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+ int flag, prot, sect;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
+ return 1;
+ }
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot)
+ printf("- Warning: %d protected sectors will not be erased!", prot);
+
+ printf("\n");
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000; /* sector erase */
+
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ */
+ wait_for_DQ7_16(info, sect);
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+ addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; /* reset bank */
+
+ printf(" done\n");
+ return 0;
+}
+
+static int write_word_16(flash_info_t * info, ulong dest, ulong data)
+{
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+ ulong *datap = &data;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
+ (volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
+ ulong start;
+ int i;
+
+ /* Check if Flash is (sufficiently) erased */
+ for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+ if ((dest2[i] & swap16(data2[i])) != swap16(data2[i]))
+ return (2);
+ }
+
+ for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+ int flag;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA000A000;
+
+ dest2[i] = swap16(data2[i]);
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer(0);
+ while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
+ (swap16(data2[i]) & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000)) {
+
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
+
+ return (0);
+}
+#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+ unsigned long total_b = 0;
+ unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+ unsigned short index = 0;
+ int i;
+
+ DEBUGF("\n");
+ DEBUGF("FLASH: Index: %d\n", index);
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+
+ /* check whether the address is 0 */
+ if (flash_addr_table[index][i] == 0)
+ continue;
+
+ /* call flash_get_size() to initialize sector address */
+ size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+ &flash_info[i]);
+
+ flash_info[i].size = size_b[i];
+
+ if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+ i+1, size_b[i], size_b[i] << 20);
+ flash_info[i].sector_count = -1;
+ flash_info[i].size = 0;
+ }
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+ &flash_info[i]);
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#if defined(CONFIG_ENV_ADDR_REDUND)
+ (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[i]);
+#endif
+#endif
+ total_b += flash_info[i].size;
+ }
+
+ return total_b;
+}
+#endif /* if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) */
diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c
new file mode 100644
index 0000000..5f905d5
--- /dev/null
+++ b/board/tqc/tqm5200/cmd_stk52xx.c
@@ -0,0 +1,1227 @@
+/*
+ * (C) Copyright 2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * STK52XX specific functions
+ */
+/*#define DEBUG*/
+
+#include <common.h>
+#include <command.h>
+
+#if defined(CONFIG_CMD_BSP)
+
+#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+#define DEFAULT_VOL 45
+#define DEFAULT_FREQ 500
+#define DEFAULT_DURATION 200
+#define LEFT 1
+#define RIGHT 2
+#define LEFT_RIGHT 3
+#define BL_OFF 0
+#define BL_ON 1
+
+#define SM501_GPIO_CTRL_LOW 0x00000008UL
+#define SM501_GPIO_CTRL_HIGH 0x0000000CUL
+#define SM501_POWER_MODE0_GATE 0x00000040UL
+#define SM501_POWER_MODE1_GATE 0x00000048UL
+#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
+#define SM501_GPIO_DATA_LOW 0x00010000UL
+#define SM501_GPIO_DATA_HIGH 0x00010004UL
+#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL
+#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
+#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL
+
+static int i2s_squarewave(unsigned long duration, unsigned int freq,
+ unsigned int channel);
+static int i2s_sawtooth(unsigned long duration, unsigned int freq,
+ unsigned int channel);
+static void spi_init(void);
+static int spi_transmit(unsigned char data);
+static void pcm1772_write_reg(unsigned char addr, unsigned char data);
+static void set_attenuation(unsigned char attenuation);
+
+static void spi_init(void)
+{
+ struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+ /* PSC3 as SPI and GPIOs */
+ gpio->port_config &= 0xFFFFF0FF;
+ gpio->port_config |= 0x00000800;
+ /*
+ * Its important to use the correct order when initializing the
+ * registers
+ */
+ spi->ddr = 0x0F; /* set all SPI pins as output */
+ spi->pdr = 0x08; /* set SS high */
+ spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */
+ spi->cr2 = 0x00; /* normal operation */
+ spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */
+}
+
+static int spi_transmit(unsigned char data)
+{
+ struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+
+ spi->dr = data;
+ /* wait for SPI transmission completed */
+ while (!(spi->sr & 0x80)) {
+ if (spi->sr & 0x40) { /* if write collision occured */
+ int dummy;
+
+ /* do dummy read to clear status register */
+ dummy = spi->dr;
+ printf("SPI write collision: dr=0x%x\n", dummy);
+ return -1;
+ }
+ }
+ return (spi->dr);
+}
+
+static void pcm1772_write_reg(unsigned char addr, unsigned char data)
+{
+ struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+
+ spi->pdr = 0x00; /* Set SS low */
+ spi_transmit(addr);
+ spi_transmit(data);
+ /* wait some time to meet MS# hold time of PCM1772 */
+ udelay (1);
+ spi->pdr = 0x08; /* set SS high */
+}
+
+static void set_attenuation(unsigned char attenuation)
+{
+ pcm1772_write_reg(0x01, attenuation); /* left channel */
+ debug ("PCM1772 attenuation left set to %d.\n", attenuation);
+ pcm1772_write_reg(0x02, attenuation); /* right channel */
+ debug ("PCM1772 attenuation right set to %d.\n", attenuation);
+}
+
+void amplifier_init(void)
+{
+ static int init_done = 0;
+ int i;
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+ /* Do this only once, because of the long time delay */
+ if (!init_done) {
+ /* configure PCM1772 audio format as I2S */
+ pcm1772_write_reg(0x03, 0x01);
+ /* enable audio amplifier */
+ gpio->sint_gpioe |= 0x02; /* PSC3_5 as GPIO */
+ gpio->sint_ode &= ~0x02; /* PSC3_5 is not open Drain */
+ gpio->sint_dvo &= ~0x02; /* PSC3_5 is LOW */
+ gpio->sint_ddr |= 0x02; /* PSC3_5 as output */
+ /*
+ * wait some time to allow amplifier to recover from shutdown
+ * mode.
+ */
+ for(i = 0; i < 350; i++)
+ udelay(1000);
+ /*
+ * The used amplifier (LM4867) has a so called "pop and click"
+ * elmination filter. The input signal of the amplifier must
+ * exceed a certain level once after power up to activate the
+ * generation of the output signal. This is achieved by
+ * sending a low frequent (nearly inaudible) sawtooth with a
+ * sufficient signal level.
+ */
+ set_attenuation(50);
+ i2s_sawtooth (200, 5, LEFT_RIGHT);
+ init_done = 1;
+ }
+}
+
+static void i2s_init(void)
+{
+ unsigned long i;
+ struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;;
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+ gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */
+ psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+ psc->sicr = 0x22E00000; /* 16 bit data; I2S */
+
+ *(vu_long *)(CONFIG_SYS_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK
+ * 5.617 MHz */
+ *(vu_long *)(CONFIG_SYS_MBAR + 0x214) |= 0x00000040; /* CDM clock enable
+ * register */
+ psc->ccr = 0x1F03; /* 16 bit data width; 5.617MHz MCLK */
+ psc->ctur = 0x0F; /* 16 bit frame width */
+
+ for (i = 0; i < 128; i++)
+ psc->psc_buffer_32 = 0; /* clear tx fifo */
+}
+
+static int i2s_play_wave(unsigned long addr, unsigned long len)
+{
+ unsigned long i;
+ unsigned char *wave_file = (uchar *)addr + 44; /* quick'n dirty: skip
+ * wav header*/
+ struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+ /*
+ * play wave file in memory; bytes/words are be swapped
+ */
+ psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+ for(i = 0;i < (len / 4); i++) {
+ unsigned char swapped[4];
+ unsigned long *p = (unsigned long*)swapped;
+
+ swapped[3] = *wave_file++;
+ swapped[2] = *wave_file++;
+ swapped[1] = *wave_file++;
+ swapped[0] = *wave_file++;
+
+ psc->psc_buffer_32 = *p;
+
+ while (psc->tfnum > 400) {
+ if(ctrlc())
+ return 0;
+ }
+ }
+ while (psc->tfnum > 0); /* wait for fifo empty */
+ udelay (100);
+ psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+ return 0;
+}
+
+static int i2s_sawtooth(unsigned long duration, unsigned int freq,
+ unsigned int channel)
+{
+ long i,j;
+ unsigned long data;
+ struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+ psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+ /*
+ * Generate sawtooth. Start with middle level up to highest level. Then
+ * go to lowest level and back to middle level.
+ */
+ for(j = 0; j < ((duration * freq) / 1000); j++) {
+ for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4)))) {
+ data = (i & 0xFFFF);
+ /* data format: right data left data) */
+ if (channel == LEFT_RIGHT)
+ data |= (data<<16);
+ if (channel == RIGHT)
+ data = (data<<16);
+ psc->psc_buffer_32 = data;
+ while (psc->tfnum > 400);
+ }
+ for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) {
+ data = (i & 0xFFFF);
+ /* data format: right data left data) */
+ if (channel == LEFT_RIGHT)
+ data |= (data<<16);
+ if (channel == RIGHT)
+ data = (data<<16);
+ psc->psc_buffer_32 = data;
+ while (psc->tfnum > 400);
+ }
+ for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) {
+ data = (i & 0xFFFF);
+ /* data format: right data left data) */
+ if (channel == LEFT_RIGHT)
+ data |= (data<<16);
+ if (channel == RIGHT)
+ data = (data<<16);
+ psc->psc_buffer_32 = data;
+ while (psc->tfnum > 400);
+ }
+ }
+ while (psc->tfnum > 0); /* wait for fifo empty */
+ udelay (100);
+ psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+
+ return 0;
+}
+
+static int i2s_squarewave(unsigned long duration, unsigned int freq,
+ unsigned int channel)
+{
+ long i,j;
+ unsigned long data;
+ struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+ psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+ /*
+ * Generate sqarewave. Start with high level, duty cycle 1:1.
+ */
+ for(j = 0; j < ((duration * freq) / 1000); j++) {
+ for(i = 0; i < (44100/(freq*2)); i ++) {
+ data = 0x7FFF;
+ /* data format: right data left data) */
+ if (channel == LEFT_RIGHT)
+ data |= (data<<16);
+ if (channel == RIGHT)
+ data = (data<<16);
+ psc->psc_buffer_32 = data;
+ while (psc->tfnum > 400);
+ }
+ for(i = 0; i < (44100/(freq*2)); i ++) {
+ data = 0x8000;
+ /* data format: right data left data) */
+ if (channel == LEFT_RIGHT)
+ data |= (data<<16);
+ if (channel == RIGHT)
+ data = (data<<16);
+ psc->psc_buffer_32 = data;
+ while (psc->tfnum > 400);
+ }
+ }
+ while (psc->tfnum > 0); /* wait for fifo empty */
+ udelay (100);
+ psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+
+ return 0;
+}
+
+static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned long reg, val, duration;
+ char *tmp;
+ unsigned int freq, channel;
+ unsigned char volume;
+ int rcode = 1;
+
+#ifdef CONFIG_STK52XX_REV100
+ printf ("Revision 100 of STK52XX not supported!\n");
+ return 1;
+#endif
+ spi_init();
+ i2s_init();
+ amplifier_init();
+
+ if ((tmp = getenv ("volume")) != NULL) {
+ volume = simple_strtoul (tmp, NULL, 10);
+ } else {
+ volume = DEFAULT_VOL;
+ }
+ set_attenuation(volume);
+
+ switch (argc) {
+ case 0:
+ case 1:
+ return cmd_usage(cmdtp);
+ case 2:
+ if (strncmp(argv[1],"saw",3) == 0) {
+ printf ("Play sawtooth\n");
+ rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ,
+ LEFT_RIGHT);
+ return rcode;
+ } else if (strncmp(argv[1],"squ",3) == 0) {
+ printf ("Play squarewave\n");
+ rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ,
+ LEFT_RIGHT);
+ return rcode;
+ }
+
+ return cmd_usage(cmdtp);
+ case 3:
+ if (strncmp(argv[1],"saw",3) == 0) {
+ duration = simple_strtoul(argv[2], NULL, 10);
+ printf ("Play sawtooth\n");
+ rcode = i2s_sawtooth (duration, DEFAULT_FREQ,
+ LEFT_RIGHT);
+ return rcode;
+ } else if (strncmp(argv[1],"squ",3) == 0) {
+ duration = simple_strtoul(argv[2], NULL, 10);
+ printf ("Play squarewave\n");
+ rcode = i2s_squarewave (duration, DEFAULT_FREQ,
+ LEFT_RIGHT);
+ return rcode;
+ }
+ return cmd_usage(cmdtp);
+ case 4:
+ if (strncmp(argv[1],"saw",3) == 0) {
+ duration = simple_strtoul(argv[2], NULL, 10);
+ freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+ printf ("Play sawtooth\n");
+ rcode = i2s_sawtooth (duration, freq,
+ LEFT_RIGHT);
+ return rcode;
+ } else if (strncmp(argv[1],"squ",3) == 0) {
+ duration = simple_strtoul(argv[2], NULL, 10);
+ freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+ printf ("Play squarewave\n");
+ rcode = i2s_squarewave (duration, freq,
+ LEFT_RIGHT);
+ return rcode;
+ } else if (strcmp(argv[1],"pcm1772") == 0) {
+ reg = simple_strtoul(argv[2], NULL, 10);
+ val = simple_strtoul(argv[3], NULL, 10);
+ printf("Set PCM1772 %lu. %lu\n", reg, val);
+ pcm1772_write_reg((uchar)reg, (uchar)val);
+ return 0;
+ }
+ return cmd_usage(cmdtp);
+ case 5:
+ if (strncmp(argv[1],"saw",3) == 0) {
+ duration = simple_strtoul(argv[2], NULL, 10);
+ freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+ if (strncmp(argv[4],"l",1) == 0)
+ channel = LEFT;
+ else if (strncmp(argv[4],"r",1) == 0)
+ channel = RIGHT;
+ else
+ channel = LEFT_RIGHT;
+ printf ("Play squarewave\n");
+ rcode = i2s_sawtooth (duration, freq,
+ channel);
+ return rcode;
+ } else if (strncmp(argv[1],"squ",3) == 0) {
+ duration = simple_strtoul(argv[2], NULL, 10);
+ freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+ if (strncmp(argv[4],"l",1) == 0)
+ channel = LEFT;
+ else if (strncmp(argv[4],"r",1) == 0)
+ channel = RIGHT;
+ else
+ channel = LEFT_RIGHT;
+ printf ("Play squarewave\n");
+ rcode = i2s_squarewave (duration, freq,
+ channel);
+ return rcode;
+ }
+ return cmd_usage(cmdtp);
+ }
+ printf ("Usage:\nsound cmd [arg1] [arg2] ...\n");
+ return 1;
+}
+
+static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned long length, addr;
+ unsigned char volume;
+ int rcode = 1;
+ char *tmp;
+
+#ifdef CONFIG_STK52XX_REV100
+ printf ("Revision 100 of STK52XX not supported!\n");
+ return 1;
+#endif
+ spi_init();
+ i2s_init();
+ amplifier_init();
+
+ switch (argc) {
+
+ case 3:
+ length = simple_strtoul(argv[2], NULL, 16);
+ addr = simple_strtoul(argv[1], NULL, 16);
+ break;
+
+ case 2:
+ if ((tmp = getenv ("filesize")) != NULL) {
+ length = simple_strtoul (tmp, NULL, 16);
+ } else {
+ puts ("No filesize provided\n");
+ return 1;
+ }
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ case 1:
+ if ((tmp = getenv ("filesize")) != NULL) {
+ length = simple_strtoul (tmp, NULL, 16);
+ } else {
+ puts ("No filesize provided\n");
+ return 1;
+ }
+ if ((tmp = getenv ("loadaddr")) != NULL) {
+ addr = simple_strtoul (tmp, NULL, 16);
+ } else {
+ puts ("No loadaddr provided\n");
+ return 1;
+ }
+ break;
+
+ default:
+ printf("Usage:\nwav <addr> <length[s]\n");
+ return 1;
+ break;
+ }
+
+ if ((tmp = getenv ("volume")) != NULL) {
+ volume = simple_strtoul (tmp, NULL, 10);
+ } else {
+ volume = DEFAULT_VOL;
+ }
+ set_attenuation(volume);
+
+ printf("Play wave file at %lX with length %lX\n", addr, length);
+ rcode = i2s_play_wave(addr, length);
+
+ return rcode;
+}
+
+static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned char volume;
+ unsigned int channel;
+ int rcode;
+ char *tmp;
+
+#ifdef CONFIG_STK52XX_REV100
+ printf ("Revision 100 of STK52XX not supported!\n");
+ return 1;
+#endif
+ spi_init();
+ i2s_init();
+ amplifier_init();
+
+ switch (argc) {
+ case 0:
+ case 1:
+ channel = LEFT_RIGHT;
+ break;
+ case 2:
+ if (strncmp(argv[1],"l",1) == 0)
+ channel = LEFT;
+ else if (strncmp(argv[1],"r",1) == 0)
+ channel = RIGHT;
+ else
+ channel = LEFT_RIGHT;
+ break;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ if ((tmp = getenv ("volume")) != NULL) {
+ volume = simple_strtoul (tmp, NULL, 10);
+ } else {
+ volume = DEFAULT_VOL;
+ }
+ set_attenuation(volume);
+
+ printf("Beep on ");
+ if (channel == LEFT)
+ printf ("left ");
+ else if (channel == RIGHT)
+ printf ("right ");
+ else
+ printf ("left and right ");
+ printf ("channel\n");
+
+ rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, channel);
+
+ return rcode;
+}
+#endif
+
+#if defined(CONFIG_STK52XX)
+void led_init(void)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+ /* configure PSC3 for SPI and GPIO */
+ gpio->port_config &= ~(0x00000F00);
+ gpio->port_config |= 0x00000800;
+
+ gpio->simple_gpioe &= ~(0x00000F00);
+ gpio->simple_gpioe |= 0x00000F00;
+
+ gpio->simple_ddr &= ~(0x00000F00);
+ gpio->simple_ddr |= 0x00000F00;
+
+ /* configure timer 4-7 for simple GPIO output */
+ gpt->gpt4.emsr |= 0x00000024;
+ gpt->gpt5.emsr |= 0x00000024;
+ gpt->gpt6.emsr |= 0x00000024;
+ gpt->gpt7.emsr |= 0x00000024;
+
+#ifndef CONFIG_TQM5200S
+ /* enable SM501 GPIO control (in both power modes) */
+ *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
+ POWER_MODE_GATE_GPIO_PWM_I2C;
+ *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
+ POWER_MODE_GATE_GPIO_PWM_I2C;
+
+ /* configure SM501 gpio pins 24-27 as output */
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24);
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24);
+
+ /* configure SM501 gpio pins 48-51 as output */
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16);
+#endif /* !CONFIG_TQM5200S */
+}
+
+/*
+ * return 1 if led number unknown
+ * return 0 else
+ */
+int do_led(char * const argv[])
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+ switch (simple_strtoul(argv[2], NULL, 10)) {
+
+ case 0:
+ if (strcmp (argv[3], "on") == 0) {
+ gpio->simple_dvo |= (1 << 8);
+ } else {
+ gpio->simple_dvo &= ~(1 << 8);
+ }
+ break;
+
+ case 1:
+ if (strcmp (argv[3], "on") == 0) {
+ gpio->simple_dvo |= (1 << 9);
+ } else {
+ gpio->simple_dvo &= ~(1 << 9);
+ }
+ break;
+
+ case 2:
+ if (strcmp (argv[3], "on") == 0) {
+ gpio->simple_dvo |= (1 << 10);
+ } else {
+ gpio->simple_dvo &= ~(1 << 10);
+ }
+ break;
+
+ case 3:
+ if (strcmp (argv[3], "on") == 0) {
+ gpio->simple_dvo |= (1 << 11);
+ } else {
+ gpio->simple_dvo &= ~(1 << 11);
+ }
+ break;
+
+ case 4:
+ if (strcmp (argv[3], "on") == 0) {
+ gpt->gpt4.emsr |= (1 << 4);
+ } else {
+ gpt->gpt4.emsr &= ~(1 << 4);
+ }
+ break;
+
+ case 5:
+ if (strcmp (argv[3], "on") == 0) {
+ gpt->gpt5.emsr |= (1 << 4);
+ } else {
+ gpt->gpt5.emsr &= ~(1 << 4);
+ }
+ break;
+
+ case 6:
+ if (strcmp (argv[3], "on") == 0) {
+ gpt->gpt6.emsr |= (1 << 4);
+ } else {
+ gpt->gpt6.emsr &= ~(1 << 4);
+ }
+ break;
+
+ case 7:
+ if (strcmp (argv[3], "on") == 0) {
+ gpt->gpt7.emsr |= (1 << 4);
+ } else {
+ gpt->gpt7.emsr &= ~(1 << 4);
+ }
+ break;
+#ifndef CONFIG_TQM5200S
+ case 24:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+ (0x1 << 24);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+ ~(0x1 << 24);
+ }
+ break;
+
+ case 25:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+ (0x1 << 25);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+ ~(0x1 << 25);
+ }
+ break;
+
+ case 26:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+ (0x1 << 26);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+ ~(0x1 << 26);
+ }
+ break;
+
+ case 27:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+ (0x1 << 27);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+ ~(0x1 << 27);
+ }
+ break;
+
+ case 48:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+ (0x1 << 16);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+ ~(0x1 << 16);
+ }
+ break;
+
+ case 49:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+ (0x1 << 17);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+ ~(0x1 << 17);
+ }
+ break;
+
+ case 50:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+ (0x1 << 18);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+ ~(0x1 << 18);
+ }
+ break;
+
+ case 51:
+ if (strcmp (argv[3], "on") == 0) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+ (0x1 << 19);
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+ ~(0x1 << 19);
+ }
+ break;
+#endif /* !CONFIG_TQM5200S */
+ default:
+ printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]);
+ return 1;
+ }
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+/*
+ * return 1 on CAN initialization failure
+ * return 0 if no failure
+ */
+int can_init(void)
+{
+ static int init_done = 0;
+ int i;
+ struct mpc5xxx_mscan *can1 =
+ (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
+ struct mpc5xxx_mscan *can2 =
+ (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
+
+ /* GPIO configuration of the CAN pins is done in TQM5200.h */
+
+ if (!init_done) {
+ /* init CAN 1 */
+ can1->canctl1 |= 0x80; /* CAN enable */
+ udelay(100);
+
+ i = 0;
+ can1->canctl0 |= 0x02; /* sleep mode */
+ /* wait until sleep mode reached */
+ while (!(can1->canctl1 & 0x02)) {
+ udelay(10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 initialize error, "
+ "can not enter sleep mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ i = 0;
+ can1->canctl0 = 0x01; /* enter init mode */
+ /* wait until init mode reached */
+ while (!(can1->canctl1 & 0x01)) {
+ udelay(10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 initialize error, "
+ "can not enter init mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ can1->canctl1 = 0x80;
+ can1->canctl1 |= 0x40;
+ can1->canbtr0 = 0x0F;
+ can1->canbtr1 = 0x7F;
+ can1->canidac &= ~(0x30);
+ can1->canidar1 = 0x00;
+ can1->canidar3 = 0x00;
+ can1->canidar5 = 0x00;
+ can1->canidar7 = 0x00;
+ can1->canidmr0 = 0xFF;
+ can1->canidmr1 = 0xFF;
+ can1->canidmr2 = 0xFF;
+ can1->canidmr3 = 0xFF;
+ can1->canidmr4 = 0xFF;
+ can1->canidmr5 = 0xFF;
+ can1->canidmr6 = 0xFF;
+ can1->canidmr7 = 0xFF;
+
+ i = 0;
+ can1->canctl0 &= ~(0x01); /* leave init mode */
+ can1->canctl0 &= ~(0x02);
+ /* wait until init and sleep mode left */
+ while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
+ udelay(10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 initialize error, "
+ "can not leave init/sleep mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+
+ /* init CAN 2 */
+ can2->canctl1 |= 0x80; /* CAN enable */
+ udelay(100);
+
+ i = 0;
+ can2->canctl0 |= 0x02; /* sleep mode */
+ /* wait until sleep mode reached */
+ while (!(can2->canctl1 & 0x02)) {
+ udelay(10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 initialize error, "
+ "can not enter sleep mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ i = 0;
+ can2->canctl0 = 0x01; /* enter init mode */
+ /* wait until init mode reached */
+ while (!(can2->canctl1 & 0x01)) {
+ udelay(10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 initialize error, "
+ "can not enter init mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ can2->canctl1 = 0x80;
+ can2->canctl1 |= 0x40;
+ can2->canbtr0 = 0x0F;
+ can2->canbtr1 = 0x7F;
+ can2->canidac &= ~(0x30);
+ can2->canidar1 = 0x00;
+ can2->canidar3 = 0x00;
+ can2->canidar5 = 0x00;
+ can2->canidar7 = 0x00;
+ can2->canidmr0 = 0xFF;
+ can2->canidmr1 = 0xFF;
+ can2->canidmr2 = 0xFF;
+ can2->canidmr3 = 0xFF;
+ can2->canidmr4 = 0xFF;
+ can2->canidmr5 = 0xFF;
+ can2->canidmr6 = 0xFF;
+ can2->canidmr7 = 0xFF;
+ can2->canctl0 &= ~(0x01); /* leave init mode */
+ can2->canctl0 &= ~(0x02);
+
+ i = 0;
+ /* wait until init mode left */
+ while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
+ udelay(10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 initialize error, "
+ "can not leave init/sleep mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ }
+ init_done = 1;
+ }
+ return 0;
+}
+
+/*
+ * return 1 on CAN failure
+ * return 0 if no failure
+ */
+int do_can(char * const argv[])
+{
+ int i;
+ struct mpc5xxx_mscan *can1 =
+ (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
+ struct mpc5xxx_mscan *can2 =
+ (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
+
+ /* send a message on CAN1 */
+ can1->cantbsel = 0x01;
+ can1->cantxfg.idr[0] = 0x55;
+ can1->cantxfg.idr[1] = 0x00;
+ can1->cantxfg.idr[1] &= ~0x8;
+ can1->cantxfg.idr[1] &= ~0x10;
+ can1->cantxfg.dsr[0] = 0xCC;
+ can1->cantxfg.dlr = 1;
+ can1->cantxfg.tbpr = 0;
+ can1->cantflg = 0x01;
+
+ i = 0;
+ while ((can1->cantflg & 0x01) == 0) {
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 send timeout, "
+ "can not send message!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ udelay(1000);
+ }
+ udelay(1000);
+
+ i = 0;
+ while (!(can2->canrflg & 0x01)) {
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 receive timeout, "
+ "no message received!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ udelay(1000);
+ }
+
+ if (can2->canrxfg.dsr[0] != 0xCC) {
+ printf ("%s: CAN2 receive error, "
+ "data mismatch!\n",
+ __FUNCTION__);
+ return 1;
+ }
+
+ /* send a message on CAN2 */
+ can2->cantbsel = 0x01;
+ can2->cantxfg.idr[0] = 0x55;
+ can2->cantxfg.idr[1] = 0x00;
+ can2->cantxfg.idr[1] &= ~0x8;
+ can2->cantxfg.idr[1] &= ~0x10;
+ can2->cantxfg.dsr[0] = 0xCC;
+ can2->cantxfg.dlr = 1;
+ can2->cantxfg.tbpr = 0;
+ can2->cantflg = 0x01;
+
+ i = 0;
+ while ((can2->cantflg & 0x01) == 0) {
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN2 send error, "
+ "can not send message!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ udelay(1000);
+ }
+ udelay(1000);
+
+ i = 0;
+ while (!(can1->canrflg & 0x01)) {
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 receive timeout, "
+ "no message received!\n",
+ __FUNCTION__);
+ return 1;
+ }
+ udelay(1000);
+ }
+
+ if (can1->canrxfg.dsr[0] != 0xCC) {
+ printf ("%s: CAN1 receive error 0x%02x\n",
+ __FUNCTION__, (can1->canrxfg.dsr[0]));
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
+ * return 1 if rs232 port unknown
+ * return 2 on txd/rxd failure (only rs232 2)
+ * return 3 on rts/cts failure
+ * return 0 if no failure
+ */
+int do_rs232(char * const argv[])
+{
+ int error_status = 0;
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+ switch (simple_strtoul(argv[2], NULL, 10)) {
+
+ case 1:
+ /* check RTS <-> CTS loop */
+ /* set rts to 0 */
+ psc1->op1 |= 0x01;
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ /* check status at cts */
+ if ((psc1->ip & 0x01) != 0) {
+ error_status = 3;
+ printf ("%s: failure at rs232_1, cts status is %d "
+ "(should be 0)\n",
+ __FUNCTION__, (psc1->ip & 0x01));
+ }
+
+ /* set rts to 1 */
+ psc1->op0 |= 0x01;
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ /* check status at cts */
+ if ((psc1->ip & 0x01) != 1) {
+ error_status = 3;
+ printf ("%s: failure at rs232_1, cts status is %d "
+ "(should be 1)\n",
+ __FUNCTION__, (psc1->ip & 0x01));
+ }
+
+ break;
+
+ case 2:
+ /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
+ gpio->simple_ddr &= ~(0x00000F00);
+ gpio->simple_ddr |= 0x00000500;
+
+ /* check TXD <-> RXD loop */
+ /* set TXD to 1 */
+ gpio->simple_dvo |= (1 << 8);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
+ error_status = 2;
+ printf ("%s: failure at rs232_2, rxd status is %d "
+ "(should be 1)\n",
+ __FUNCTION__,
+ (gpio->simple_ival & 0x00000200) >> 9);
+ }
+
+ /* set TXD to 0 */
+ gpio->simple_dvo &= ~(1 << 8);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
+ error_status = 2;
+ printf ("%s: failure at rs232_2, rxd status is %d "
+ "(should be 0)\n",
+ __FUNCTION__,
+ (gpio->simple_ival & 0x00000200) >> 9);
+ }
+
+ /* check RTS <-> CTS loop */
+ /* set RTS to 1 */
+ gpio->simple_dvo |= (1 << 10);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
+ error_status = 3;
+ printf ("%s: failure at rs232_2, cts status is %d "
+ "(should be 1)\n",
+ __FUNCTION__,
+ (gpio->simple_ival & 0x00000800) >> 11);
+ }
+
+ /* set RTS to 0 */
+ gpio->simple_dvo &= ~(1 << 10);
+
+ /* wait some time before requesting status */
+ udelay(10);
+
+ if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
+ error_status = 3;
+ printf ("%s: failure at rs232_2, cts status is %d "
+ "(should be 0)\n",
+ __FUNCTION__,
+ (gpio->simple_ival & 0x00000800) >> 11);
+ }
+
+ /* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */
+ gpio->simple_ddr &= ~(0x00000F00);
+ gpio->simple_ddr |= 0x00000F00;
+ break;
+
+ default:
+ printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
+ error_status = 1;
+ break;
+ }
+
+ return error_status;
+}
+
+#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
+static void sm501_backlight (unsigned int state)
+{
+ if (state == BL_ON) {
+ *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
+ (1 << 26) | (1 << 27);
+ } else if (state == BL_OFF)
+ *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
+ ~((1 << 26) | (1 << 27));
+}
+#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
+
+int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int rcode;
+
+#ifdef CONFIG_STK52XX_REV100
+ printf ("Revision 100 of STK52XX not supported!\n");
+ return 1;
+#endif
+#if defined(CONFIG_STK52XX)
+ led_init();
+#endif
+ can_init();
+
+ switch (argc) {
+
+ case 0:
+ case 1:
+ break;
+
+ case 2:
+ if (strncmp (argv[1], "can", 3) == 0) {
+ rcode = do_can (argv);
+ if (rcode == 0)
+ printf ("OK\n");
+ else
+ printf ("Error\n");
+ return rcode;
+ }
+ break;
+
+ case 3:
+ if (strncmp (argv[1], "rs232", 3) == 0) {
+ rcode = do_rs232 (argv);
+ if (rcode == 0)
+ printf ("OK\n");
+ else
+ printf ("Error\n");
+ return rcode;
+#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
+ } else if (strncmp (argv[1], "backlight", 4) == 0) {
+ if (strncmp (argv[2], "on", 2) == 0) {
+ sm501_backlight (BL_ON);
+ return 0;
+ }
+ else if (strncmp (argv[2], "off", 3) == 0) {
+ sm501_backlight (BL_OFF);
+ return 0;
+ }
+#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
+ }
+ break;
+
+#if defined(CONFIG_STK52XX)
+ case 4:
+ if (strcmp (argv[1], "led") == 0) {
+ return (do_led (argv));
+ }
+ break;
+#endif
+
+ default:
+ break;
+ }
+
+ printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n");
+ return 1;
+}
+
+
+U_BOOT_CMD(
+ sound , 5, 1, cmd_sound,
+ "Sound sub-system",
+ "saw [duration] [freq] [channel]\n"
+ " - generate sawtooth for 'duration' ms with frequency 'freq'\n"
+ " on left \"l\" or right \"r\" channel\n"
+ "sound square [duration] [freq] [channel]\n"
+ " - generate squarewave for 'duration' ms with frequency 'freq'\n"
+ " on left \"l\" or right \"r\" channel\n"
+ "pcm1772 reg val"
+);
+
+U_BOOT_CMD(
+ wav , 3, 1, cmd_wav,
+ "play wav file",
+ "[addr] [bytes]\n"
+ " - play wav file at address 'addr' with length 'bytes'"
+);
+
+U_BOOT_CMD(
+ beep , 2, 1, cmd_beep,
+ "play short beep",
+ "[channel]\n"
+ " - play short beep on \"l\"eft or \"r\"ight channel"
+);
+#endif /* CONFIG_STK52XX || CONFIG_FO300 */
+
+#if defined(CONFIG_STK52XX)
+U_BOOT_CMD(
+ fkt , 4, 1, cmd_fkt,
+ "Function test routines",
+ "led number on/off\n"
+ " - 'number's like printed on STK52XX board\n"
+ "fkt can\n"
+ " - loopback plug for X83 required\n"
+ "fkt rs232 number\n"
+ " - loopback plug(s) for X2 required"
+#ifndef CONFIG_TQM5200S
+ "\n"
+ "fkt backlight on/off\n"
+ " - switch backlight on or off"
+#endif /* !CONFIG_TQM5200S */
+);
+#elif defined(CONFIG_FO300)
+U_BOOT_CMD(
+ fkt , 3, 1, cmd_fkt,
+ "Function test routines",
+ "fkt can\n"
+ " - loopback plug for X16/X29 required\n"
+ "fkt rs232 number\n"
+ " - loopback plug(s) for X21/X22 required"
+);
+#endif
+#endif
diff --git a/board/tqc/tqm5200/cmd_tb5200.c b/board/tqc/tqm5200/cmd_tb5200.c
new file mode 100644
index 0000000..876258d
--- /dev/null
+++ b/board/tqc/tqm5200/cmd_tb5200.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2005 - 2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * TB5200 specific functions
+ */
+/*#define DEBUG*/
+
+#include <common.h>
+#include <command.h>
+
+#if defined(CONFIG_CMD_BSP)
+#if defined (CONFIG_TB5200)
+
+#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL
+
+static void led_init(void)
+{
+ struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+ /* configure timer 4 for simple GPIO output */
+ gpt->gpt4.emsr |= 0x00000024;
+}
+
+int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+ led_init();
+
+ if (strcmp (argv[1], "on") == 0) {
+ debug ("switch status LED on\n");
+ gpt->gpt4.emsr |= (1 << 4);
+ } else if (strcmp (argv[1], "off") == 0) {
+ debug ("switch status LED off\n");
+ gpt->gpt4.emsr &= ~(1 << 4);
+ } else {
+ printf ("Usage:\nled on/off\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+static void sm501_backlight (unsigned int state)
+{
+ if (state == 1) {
+ *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
+ (1 << 26) | (1 << 27);
+ } else if (state == 0)
+ *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
+ ~((1 << 26) | (1 << 27));
+}
+
+int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (strcmp (argv[1], "on") == 0) {
+ debug ("switch backlight on\n");
+ sm501_backlight (1);
+ } else if (strcmp (argv[1], "off") == 0) {
+ debug ("switch backlight off\n");
+ sm501_backlight (0);
+ } else {
+ printf ("Usage:\nbacklight on/off\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ led , 2, 1, cmd_led,
+ "switch status LED on or off",
+ "on/off"
+);
+
+U_BOOT_CMD(
+ backlight , 2, 1, cmd_backlight,
+ "switch backlight on or off",
+ "on/off"
+ );
+
+#endif /* CONFIG_STK52XX */
+#endif
diff --git a/board/tqc/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h
new file mode 100644
index 0000000..3d99796
--- /dev/null
+++ b/board/tqc/tqm5200/mt48lc16m16a2-75.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define SDRAM_DDR 0 /* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x00CD0000
+/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */
+/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
+#define SDRAM_CONFIG2 0x8AD70000
+/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */
diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c
new file mode 100644
index 0000000..e9363ea
--- /dev/null
+++ b/board/tqc/tqm5200/tqm5200.c
@@ -0,0 +1,891 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004-2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <libfdt.h>
+#include <netdev.h>
+
+#ifdef CONFIG_VIDEO_SM501
+#include <sm501.h>
+#endif
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+#ifdef CONFIG_OF_LIBFDT
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_PS2MULT
+void ps2mult_early_init(void);
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \
+ defined(CONFIG_VIDEO)
+/*
+ * EDID block has been generated using Phoenix EDID Designer 1.3.
+ * This tool creates a text file containing:
+ *
+ * EDID BYTES:
+ *
+ * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
+ * ------------------------------------------------
+ * 00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
+ * 10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
+ * 20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
+ * 30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
+ * 40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
+ * 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
+ * 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
+ * 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
+ *
+ * Then this data has been manually converted to the char
+ * array below.
+ */
+static unsigned char edid_buf[128] = {
+ 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
+ 0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
+};
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
+ hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+ hi_addr_bit;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+#endif
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+ hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+ hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ * is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set tap delay */
+ *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+ __builtin_ffs(dramsize >> 20) - 1;
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ }
+
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
+
+ /* find RAM size using SDRAM CS1 only */
+ if (!dramsize)
+ sdram_start(0);
+ test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
+ if (!dramsize) {
+ sdram_start(1);
+ test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
+ }
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize2 = test1;
+ } else {
+ dramsize2 = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20)) {
+ dramsize2 = 0;
+ }
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+ | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13) {
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ } else {
+ dramsize = 0;
+ }
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ if (dramsize2 >= 0x13) {
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ } else {
+ dramsize2 = 0;
+ }
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+ }
+
+#if defined(CONFIG_TQM5200_B)
+ return dramsize + dramsize2;
+#else
+ return dramsize;
+#endif /* CONFIG_TQM5200_B */
+}
+
+int checkboard (void)
+{
+#if defined(CONFIG_AEVFIFO)
+ puts ("Board: AEVFIFO\n");
+ return 0;
+#endif
+
+#if defined(CONFIG_TQM5200S)
+# define MODULE_NAME "TQM5200S"
+#else
+# define MODULE_NAME "TQM5200"
+#endif
+
+#if defined(CONFIG_STK52XX)
+# define CARRIER_NAME "STK52xx"
+#elif defined(CONFIG_TB5200)
+# define CARRIER_NAME "TB5200"
+#elif defined(CONFIG_CAM5200)
+# define CARRIER_NAME "CAM5200"
+#elif defined(CONFIG_FO300)
+# define CARRIER_NAME "FO300"
+#elif defined(CONFIG_CHARON)
+# define CARRIER_NAME "CHARON"
+#else
+# error "UNKNOWN"
+#endif
+
+ puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
+ " on a " CARRIER_NAME " carrier board\n");
+
+ return 0;
+}
+
+#undef MODULE_NAME
+#undef CARRIER_NAME
+
+void flash_preinit(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write
+ * access for detection process.
+ * Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+
+#if defined (CONFIG_MINIFAP)
+#define SM501_POWER_MODE0_GATE 0x00000040UL
+#define SM501_POWER_MODE1_GATE 0x00000048UL
+#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
+#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
+#define SM501_GPIO_DATA_HIGH 0x00010004UL
+#define SM501_GPIO_51 0x00080000UL
+#endif /* CONFIG MINIFAP */
+
+void init_ide_reset (void)
+{
+ debug ("init_ide_reset\n");
+
+#if defined (CONFIG_MINIFAP)
+ /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
+
+ /* enable GPIO control (in both power modes) */
+ *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
+ POWER_MODE_GATE_GPIO_PWM_I2C;
+ *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
+ POWER_MODE_GATE_GPIO_PWM_I2C;
+ /* configure GPIO51 as output */
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
+ SM501_GPIO_51;
+#else
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+
+ /* by default the ATA reset is de-asserted */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+#endif
+}
+
+void ide_set_reset (int idereset)
+{
+ debug ("ide_reset(%d)\n", idereset);
+
+#if defined (CONFIG_MINIFAP)
+ if (idereset) {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+ ~SM501_GPIO_51;
+ } else {
+ *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+ SM501_GPIO_51;
+ }
+#else
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+ } else {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+ }
+#endif
+}
+#endif
+
+#ifdef CONFIG_POST
+/*
+ * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
+ * is left open, no keypress is detected.
+ */
+int post_hotkeys_pressed(void)
+{
+#ifdef CONFIG_STK52XX
+ struct mpc5xxx_gpio *gpio;
+
+ gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
+
+ /*
+ * Configure PSC6_0 through PSC6_3 as GPIO.
+ */
+ gpio->port_config &= ~(0x00700000);
+
+ /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
+ gpio->simple_gpioe |= 0x20000000;
+
+ /* Configure GPIO_IRDA_1 as input */
+ gpio->simple_ddr &= ~(0x20000000);
+
+ return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
+#else
+ return 0;
+#endif
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+
+ extern int usb_cpu_init(void);
+
+#ifdef CONFIG_PS2MULT
+ ps2mult_early_init();
+#endif /* CONFIG_PS2MULT */
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
+ /* Low level USB init, required for proper kernel operation */
+ usb_cpu_init();
+#endif
+
+ return (0);
+}
+#endif
+
+#ifdef CONFIG_FO300
+int silent_boot (void)
+{
+ vu_long timer3_status;
+
+ /* Configure GPT3 as GPIO input */
+ *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
+
+ /* Read in TIMER_3 pin status */
+ timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
+
+#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
+ /* Force silent console mode if S1 switch
+ * is in closed position (TIMER_3 pin status is LOW). */
+ if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
+ return 1;
+#else
+ /* Force silent console mode if S1 switch
+ * is in open position (TIMER_3 pin status is HIGH). */
+ if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
+ return 1;
+#endif
+
+ return 0;
+}
+
+int board_early_init_f (void)
+{
+ if (silent_boot())
+ gd->flags |= GD_FLG_SILENT;
+
+ return 0;
+}
+#endif /* CONFIG_FO300 */
+
+#if defined(CONFIG_CHARON)
+#include <i2c.h>
+#include <asm/io.h>
+
+/* The TFP410 registers */
+#define TFP410_REG_VEN_ID_L 0x00
+#define TFP410_REG_VEN_ID_H 0x01
+#define TFP410_REG_DEV_ID_L 0x02
+#define TFP410_REG_DEV_ID_H 0x03
+#define TFP410_REG_REV_ID 0x04
+
+#define TFP410_REG_CTL_1_MODE 0x08
+#define TFP410_REG_CTL_2_MODE 0x09
+#define TFP410_REG_CTL_3_MODE 0x0A
+
+#define TFP410_REG_CFG 0x0B
+
+#define TFP410_REG_DE_DLY 0x32
+#define TFP410_REG_DE_CTL 0x33
+#define TFP410_REG_DE_TOP 0x34
+#define TFP410_REG_DE_CNT_L 0x36
+#define TFP410_REG_DE_CNT_H 0x37
+#define TFP410_REG_DE_LIN_L 0x38
+#define TFP410_REG_DE_LIN_H 0x39
+
+#define TFP410_REG_H_RES_L 0x3A
+#define TFP410_REG_H_RES_H 0x3B
+#define TFP410_REG_V_RES_L 0x3C
+#define TFP410_REG_V_RES_H 0x3D
+
+static int tfp410_read_reg(int reg, uchar *buf)
+{
+ if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
+ puts ("Error reading the chip.\n");
+ return 1;
+ }
+ return 0;
+}
+
+static int tfp410_write_reg(int reg, uchar buf)
+{
+ if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
+ puts ("Error writing the chip.\n");
+ return 1;
+ }
+ return 0;
+}
+
+typedef struct _tfp410_config {
+ int reg;
+ uchar val;
+}TFP410_CONFIG;
+
+static TFP410_CONFIG tfp410_configtbl[] = {
+ {TFP410_REG_CTL_1_MODE, 0x37},
+ {TFP410_REG_CTL_2_MODE, 0x20},
+ {TFP410_REG_CTL_3_MODE, 0x80},
+ {TFP410_REG_DE_DLY, 0x90},
+ {TFP410_REG_DE_CTL, 0x00},
+ {TFP410_REG_DE_TOP, 0x23},
+ {TFP410_REG_DE_CNT_H, 0x02},
+ {TFP410_REG_DE_CNT_L, 0x80},
+ {TFP410_REG_DE_LIN_H, 0x01},
+ {TFP410_REG_DE_LIN_L, 0xe0},
+ {-1, 0},
+};
+
+static int charon_last_stage_init(void)
+{
+ volatile struct mpc5xxx_lpb *lpb =
+ (struct mpc5xxx_lpb *) MPC5XXX_LPB;
+ int oldbus = i2c_get_bus_num();
+ uchar buf;
+ int i = 0;
+
+ i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
+
+ /* check version */
+ if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
+ return -1;
+ if (!(buf & 0x04))
+ return -1;
+ if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
+ return -1;
+ if (!(buf & 0x10))
+ return -1;
+ /* OK, now init the chip */
+ while (tfp410_configtbl[i].reg != -1) {
+ int ret;
+
+ ret = tfp410_write_reg(tfp410_configtbl[i].reg,
+ tfp410_configtbl[i].val);
+ if (ret != 0)
+ return -1;
+ i++;
+ }
+ printf("TFP410 initialized.\n");
+ i2c_set_bus_num(oldbus);
+
+ /* set deadcycle for cs3 to 0 */
+ setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
+ return 0;
+}
+#endif
+
+int last_stage_init (void)
+{
+ /*
+ * auto scan for really existing devices and re-set chip select
+ * configuration.
+ */
+ u16 save, tmp;
+ int restore;
+
+ /*
+ * Check for SRAM and SRAM size
+ */
+
+ /* save original SRAM content */
+ save = *(volatile u16 *)CONFIG_SYS_CS2_START;
+ restore = 1;
+
+ /* write test pattern to SRAM */
+ *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
+ __asm__ volatile ("sync");
+ /*
+ * Put a different pattern on the data lines: otherwise they may float
+ * long enough to read back what we wrote.
+ */
+ tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
+ if (tmp == 0xA5A5)
+ puts ("!! possible error in SRAM detection\n");
+
+ if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
+ /* no SRAM at all, disable cs */
+ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
+ *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
+ *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
+ restore = 0;
+ __asm__ volatile ("sync");
+ } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
+ /* make sure that we access a mirrored address */
+ *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
+ __asm__ volatile ("sync");
+ if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
+ /* SRAM size = 512 kByte */
+ *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
+ 0x80000);
+ __asm__ volatile ("sync");
+ puts ("SRAM: 512 kB\n");
+ }
+ else
+ puts ("!! possible error in SRAM detection\n");
+ } else {
+ puts ("SRAM: 1 MB\n");
+ }
+ /* restore origianl SRAM content */
+ if (restore) {
+ *(volatile u16 *)CONFIG_SYS_CS2_START = save;
+ __asm__ volatile ("sync");
+ }
+
+#ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
+ /*
+ * Check for Grafic Controller
+ */
+
+ /* save origianl FB content */
+ save = *(volatile u16 *)CONFIG_SYS_CS1_START;
+ restore = 1;
+
+ /* write test pattern to FB memory */
+ *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
+ __asm__ volatile ("sync");
+ /*
+ * Put a different pattern on the data lines: otherwise they may float
+ * long enough to read back what we wrote.
+ */
+ tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
+ if (tmp == 0xA5A5)
+ puts ("!! possible error in grafic controller detection\n");
+
+ if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
+ /* no grafic controller at all, disable cs */
+ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
+ *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
+ *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
+ restore = 0;
+ __asm__ volatile ("sync");
+ } else {
+ puts ("VGA: SMI501 (Voyager) with 8 MB\n");
+ }
+ /* restore origianl FB content */
+ if (restore) {
+ *(volatile u16 *)CONFIG_SYS_CS1_START = save;
+ __asm__ volatile ("sync");
+ }
+
+#ifdef CONFIG_FO300
+ if (silent_boot()) {
+ setenv("bootdelay", "0");
+ disable_ctrlc(1);
+ }
+#endif
+#endif /* !CONFIG_TQM5200S */
+
+#if defined(CONFIG_CHARON)
+ charon_last_stage_init();
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_VIDEO_SM501
+
+#ifdef CONFIG_FO300
+#define DISPLAY_WIDTH 800
+#else
+#define DISPLAY_WIDTH 640
+#endif
+#define DISPLAY_HEIGHT 480
+
+#ifdef CONFIG_VIDEO_SM501_8BPP
+#error CONFIG_VIDEO_SM501_8BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_8BPP */
+
+#ifdef CONFIG_VIDEO_SM501_16BPP
+#error CONFIG_VIDEO_SM501_16BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_16BPP */
+#ifdef CONFIG_VIDEO_SM501_32BPP
+static const SMI_REGS init_regs [] =
+{
+#if 0 /* CRT only */
+ {0x00004, 0x0},
+ {0x00048, 0x00021807},
+ {0x0004C, 0x10090a01},
+ {0x00054, 0x1},
+ {0x00040, 0x00021807},
+ {0x00044, 0x10090a01},
+ {0x00054, 0x0},
+ {0x80200, 0x00010000},
+ {0x80204, 0x0},
+ {0x80208, 0x0A000A00},
+ {0x8020C, 0x02fa027f},
+ {0x80210, 0x004a028b},
+ {0x80214, 0x020c01df},
+ {0x80218, 0x000201e9},
+ {0x80200, 0x00013306},
+#else /* panel + CRT */
+#ifdef CONFIG_FO300
+ {0x00004, 0x0},
+ {0x00048, 0x00021807},
+ {0x0004C, 0x301a0a01},
+ {0x00054, 0x1},
+ {0x00040, 0x00021807},
+ {0x00044, 0x091a0a01},
+ {0x00054, 0x0},
+ {0x80000, 0x0f013106},
+ {0x80004, 0xc428bb17},
+ {0x8000C, 0x00000000},
+ {0x80010, 0x0C800C80},
+ {0x80014, 0x03200000},
+ {0x80018, 0x01e00000},
+ {0x8001C, 0x00000000},
+ {0x80020, 0x01e00320},
+ {0x80024, 0x042a031f},
+ {0x80028, 0x0086034a},
+ {0x8002C, 0x020c01df},
+ {0x80030, 0x000201ea},
+ {0x80200, 0x00010000},
+#else
+ {0x00004, 0x0},
+ {0x00048, 0x00021807},
+ {0x0004C, 0x091a0a01},
+ {0x00054, 0x1},
+ {0x00040, 0x00021807},
+ {0x00044, 0x091a0a01},
+ {0x00054, 0x0},
+ {0x80000, 0x0f013106},
+ {0x80004, 0xc428bb17},
+ {0x8000C, 0x00000000},
+ {0x80010, 0x0a000a00},
+ {0x80014, 0x02800000},
+ {0x80018, 0x01e00000},
+ {0x8001C, 0x00000000},
+ {0x80020, 0x01e00280},
+ {0x80024, 0x02fa027f},
+ {0x80028, 0x004a028b},
+ {0x8002C, 0x020c01df},
+ {0x80030, 0x000201e9},
+ {0x80200, 0x00010000},
+#endif /* #ifdef CONFIG_FO300 */
+#endif
+ {0, 0}
+};
+#endif /* CONFIG_VIDEO_SM501_32BPP */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+ if (line_number == 1) {
+ strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
+#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
+ defined(CONFIG_STK52XX) || defined(CONFIG_TB5200)
+ } else if (line_number == 2) {
+#if defined (CONFIG_CHARON)
+ strcpy (info, " on a CHARON carrier board");
+#endif
+#if defined (CONFIG_STK52XX)
+ strcpy (info, " on a STK52xx carrier board");
+#endif
+#if defined (CONFIG_TB5200)
+ strcpy (info, " on a TB5200 carrier board");
+#endif
+#if defined (CONFIG_FO300)
+ strcpy (info, " on a FO300 carrier board");
+#endif
+#endif
+ }
+ else {
+ info [0] = '\0';
+ }
+}
+#endif
+
+/*
+ * Returns SM501 register base address. First thing called in the
+ * driver. Checks if SM501 is physically present.
+ */
+unsigned int board_video_init (void)
+{
+ u16 save, tmp;
+ int restore, ret;
+
+ /*
+ * Check for Grafic Controller
+ */
+
+ /* save origianl FB content */
+ save = *(volatile u16 *)CONFIG_SYS_CS1_START;
+ restore = 1;
+
+ /* write test pattern to FB memory */
+ *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
+ __asm__ volatile ("sync");
+ /*
+ * Put a different pattern on the data lines: otherwise they may float
+ * long enough to read back what we wrote.
+ */
+ tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
+ if (tmp == 0xA5A5)
+ puts ("!! possible error in grafic controller detection\n");
+
+ if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
+ /* no grafic controller found */
+ restore = 0;
+ ret = 0;
+ } else {
+ ret = SM501_MMIO_BASE;
+ }
+
+ if (restore) {
+ *(volatile u16 *)CONFIG_SYS_CS1_START = save;
+ __asm__ volatile ("sync");
+ }
+ return ret;
+}
+
+/*
+ * Returns SM501 framebuffer address
+ */
+unsigned int board_video_get_fb (void)
+{
+ return SM501_FB_BASE;
+}
+
+/*
+ * Called after initializing the SM501 and before clearing the screen.
+ */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/*
+ * Return a pointer to the initialization sequence.
+ */
+const SMI_REGS *board_get_regs (void)
+{
+ return init_regs;
+}
+
+int board_get_width (void)
+{
+ return DISPLAY_WIDTH;
+}
+
+int board_get_height (void)
+{
+ return DISPLAY_HEIGHT;
+}
+
+#endif /* CONFIG_VIDEO_SM501 */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#if defined(CONFIG_VIDEO)
+ fdt_add_edid(blob, "smi,sm501", edid_buf);
+#endif
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_RESET_PHY_R)
+#include <miiphy.h>
+
+void reset_phy(void)
+{
+ /* init Micrel KSZ8993 PHY */
+ miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in FEC comes first */
+ return pci_eth_init(bis);
+}
diff --git a/board/tqc/tqm834x/Kconfig b/board/tqc/tqm834x/Kconfig
new file mode 100644
index 0000000..028b846
--- /dev/null
+++ b/board/tqc/tqm834x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_TQM834X
+
+config SYS_BOARD
+ default "tqm834x"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM834x"
+
+endif
diff --git a/board/tqc/tqm834x/MAINTAINERS b/board/tqc/tqm834x/MAINTAINERS
new file mode 100644
index 0000000..543ab1b
--- /dev/null
+++ b/board/tqc/tqm834x/MAINTAINERS
@@ -0,0 +1,6 @@
+TQM834X BOARD
+#M: -
+S: Maintained
+F: board/tqc/tqm834x/
+F: include/configs/TQM834x.h
+F: configs/TQM834x_defconfig
diff --git a/board/tqc/tqm834x/Makefile b/board/tqc/tqm834x/Makefile
new file mode 100644
index 0000000..12edc9a
--- /dev/null
+++ b/board/tqc/tqm834x/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += tqm834x.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c
new file mode 100644
index 0000000..1acec84
--- /dev/null
+++ b/board/tqc/tqm834x/pci.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pci_region pci1_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+};
+
+/*
+ * pci_init_board()
+ *
+ * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
+ * per TQM834x design physical connections to external devices (PCI sockets)
+ * are routed only to the PCI1 we do not account for the second one - this code
+ * supports PCI1 module only. Should support for the PCI2 be required in the
+ * future it needs a separate pci_controller structure (above) and handling -
+ * please refer to other boards' implementation for dual PCI host controllers,
+ * for example board/Marvell/db64360/pci.c, pci_init_board()
+ *
+ */
+void
+pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci1_regions };
+ u32 reg32;
+
+ /*
+ * Configure PCI controller and PCI_CLK_OUTPUT
+ *
+ * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
+ * line actually used for clocking all external PCI devices in TQM83xx.
+ * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
+ * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
+ * are known to hang the board; this issue is under investigation
+ * (13 oct 05)
+ */
+ reg32 = OCCR_PCICOE1;
+#if 0
+ /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
+ reg32 = 0xff000000;
+#endif
+ if (clk->spmr & SPMR_CKID) {
+ /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
+ * fields accordingly */
+ reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
+
+ reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
+ | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
+ | OCCR_PCICD6 | OCCR_PCICD7);
+ }
+
+ clk->occr = reg32;
+ udelay(2000);
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+ pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
+
+ udelay(2000);
+
+ mpc83xx_pci_init(1, reg);
+}
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
new file mode 100644
index 0000000..d891a38
--- /dev/null
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -0,0 +1,427 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/mmu.h>
+#include <pci.h>
+#include <flash.h>
+#include <mtd/cfi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IOSYNC asm("eieio")
+#define ISYNC asm("isync")
+#define SYNC asm("sync")
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define DDR_MAX_SIZE_PER_CS 0x20000000
+
+#if defined(DDR_CASLAT_20)
+#define TIMING_CASLAT TIMING_CFG1_CASLAT_20
+#define MODE_CASLAT DDR_MODE_CASLAT_20
+#else
+#define TIMING_CASLAT TIMING_CFG1_CASLAT_25
+#define MODE_CASLAT DDR_MODE_CASLAT_25
+#endif
+
+#define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
+ CSCONFIG_COL_BIT_9)
+
+/* External definitions */
+ulong flash_get_size (ulong base, int banknum);
+
+/* Local functions */
+static int detect_num_flash_banks(void);
+static long int get_ddr_bank_size(short cs, long *base);
+static void set_cs_bounds(short cs, long base, long size);
+static void set_cs_config(short cs, long config);
+static void set_ddr_config(void);
+
+/* Local variable */
+static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+/**************************************************************************
+ * Board initialzation after relocation to RAM. Used to detect the number
+ * of Flash banks on TQM834x.
+ */
+int board_early_init_r (void) {
+ /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return 0;
+
+ /* detect the number of Flash banks */
+ return detect_num_flash_banks();
+}
+
+/**************************************************************************
+ * DRAM initalization and size detection
+ */
+phys_size_t initdram (int board_type)
+{
+ long bank_size;
+ long size;
+ int cs;
+
+ /* during size detection, set up the max DDRLAW size */
+ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE;
+ im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
+
+ /* set CS bounds to maximum size */
+ for(cs = 0; cs < 4; ++cs) {
+ set_cs_bounds(cs,
+ CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
+ DDR_MAX_SIZE_PER_CS);
+
+ set_cs_config(cs, INITIAL_CS_CONFIG);
+ }
+
+ /* configure ddr controller */
+ set_ddr_config();
+
+ udelay(200);
+
+ /* enable DDR controller */
+ im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
+ SDRAM_CFG_SREN |
+ SDRAM_CFG_SDRAM_TYPE_DDR1);
+ SYNC;
+
+ /* size detection */
+ debug("\n");
+ size = 0;
+ for(cs = 0; cs < 4; ++cs) {
+ debug("\nDetecting Bank%d\n", cs);
+
+ bank_size = get_ddr_bank_size(cs,
+ (long *)(CONFIG_SYS_DDR_BASE + size));
+ size += bank_size;
+
+ debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20);
+
+ /* exit if less than one bank */
+ if(size < DDR_MAX_SIZE_PER_CS) break;
+ }
+
+ return size;
+}
+
+/**************************************************************************
+ * checkboard()
+ */
+int checkboard (void)
+{
+ puts("Board: TQM834x\n");
+
+#ifdef CONFIG_PCI
+ volatile immap_t * immr;
+ u32 w, f;
+
+ immr = (immap_t *)CONFIG_SYS_IMMR;
+ if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) {
+ printf("PCI: NOT in host mode..?!\n");
+ return 0;
+ }
+
+ /* get bus width */
+ w = 32;
+ if (immr->reset.rcwh & HRCWH_64_BIT_PCI)
+ w = 64;
+
+ /* get clock */
+ f = gd->pci_clk;
+
+ printf("PCI1: %d bit, %d MHz\n", w, f / 1000000);
+#else
+ printf("PCI: disabled\n");
+#endif
+ return 0;
+}
+
+
+/**************************************************************************
+ *
+ * Local functions
+ *
+ *************************************************************************/
+
+/**************************************************************************
+ * Detect the number of flash banks (1 or 2). Store it in
+ * a global variable tqm834x_num_flash_banks.
+ * Bank detection code based on the Monitor code.
+ */
+static int detect_num_flash_banks(void)
+{
+ typedef unsigned long FLASH_PORT_WIDTH;
+ typedef volatile unsigned long FLASH_PORT_WIDTHV;
+ FPWV *bank1_base;
+ FPWV *bank2_base;
+ FPW bank1_read;
+ FPW bank2_read;
+ ulong bank1_size;
+ ulong bank2_size;
+ ulong total_size;
+
+ cfi_flash_num_flash_banks = 2; /* assume two banks */
+
+ /* Get bank 1 and 2 information */
+ bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0);
+ debug("Bank1 size: %lu\n", bank1_size);
+ bank2_size = flash_get_size(CONFIG_SYS_FLASH_BASE + bank1_size, 1);
+ debug("Bank2 size: %lu\n", bank2_size);
+ total_size = bank1_size + bank2_size;
+
+ if (bank2_size > 0) {
+ /* Seems like we've got bank 2, but maybe it's mirrored 1 */
+
+ /* Set the base addresses */
+ bank1_base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
+ bank2_base = (FPWV *) (CONFIG_SYS_FLASH_BASE + bank1_size);
+
+ /* Put bank 2 into CFI command mode and read */
+ bank2_base[0x55] = 0x00980098;
+ IOSYNC;
+ ISYNC;
+ bank2_read = bank2_base[0x10];
+
+ /* Read from bank 1 (it's in read mode) */
+ bank1_read = bank1_base[0x10];
+
+ /* Reset Flash */
+ bank1_base[0] = 0x00F000F0;
+ bank2_base[0] = 0x00F000F0;
+
+ if (bank2_read == bank1_read) {
+ /*
+ * Looks like just one bank, but not sure yet. Let's
+ * read from bank 2 in autosoelect mode.
+ */
+ bank2_base[0x0555] = 0x00AA00AA;
+ bank2_base[0x02AA] = 0x00550055;
+ bank2_base[0x0555] = 0x00900090;
+ IOSYNC;
+ ISYNC;
+ bank2_read = bank2_base[0x10];
+
+ /* Read from bank 1 (it's in read mode) */
+ bank1_read = bank1_base[0x10];
+
+ /* Reset Flash */
+ bank1_base[0] = 0x00F000F0;
+ bank2_base[0] = 0x00F000F0;
+
+ if (bank2_read == bank1_read) {
+ /*
+ * In both CFI command and autoselect modes,
+ * we got the some data reading from Flash.
+ * There is only one mirrored bank.
+ */
+ cfi_flash_num_flash_banks = 1;
+ total_size = bank1_size;
+ }
+ }
+ }
+
+ debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks);
+
+ /* set OR0 and BR0 */
+ set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
+ (-(total_size) & OR_GPCM_AM));
+ set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
+ (BR_MS_GPCM | BR_PS_32 | BR_V));
+
+ return (0);
+}
+
+/*************************************************************************
+ * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
+ */
+static long int get_ddr_bank_size(short cs, long *base)
+{
+ /* This array lists all valid DDR SDRAM configurations, with
+ * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
+ * The last entry has to to have size equal 0 and is igonred during
+ * autodection. Bank sizes must be in increasing order of size
+ */
+ struct {
+ long row;
+ long col;
+ long size;
+ } conf[] = {
+ {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20},
+ {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20},
+ {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20},
+ {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20},
+ {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20},
+ {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20},
+ {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20},
+ {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20},
+ {0, 0, 0}
+ };
+
+ int i;
+ int detected;
+ long size;
+
+ detected = -1;
+ for(i = 0; conf[i].size != 0; ++i) {
+
+ /* set sdram bank configuration */
+ set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
+
+ debug("Getting RAM size...\n");
+ size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
+
+ if((size == conf[i].size) && (i == detected + 1))
+ detected = i;
+
+ debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
+ conf[i].row,
+ conf[i].col,
+ conf[i].size >> 20,
+ base,
+ size >> 20);
+ }
+
+ if(detected == -1){
+ /* disable empty cs */
+ debug("\nNo valid configurations for CS%d, disabling...\n", cs);
+ set_cs_config(cs, 0);
+ return 0;
+ }
+
+ debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
+ conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
+
+ /* configure cs ro detected params */
+ set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
+ conf[detected].col);
+
+ set_cs_bounds(cs, (long)base, conf[detected].size);
+
+ return(conf[detected].size);
+}
+
+/**************************************************************************
+ * Sets DDR bank CS bounds.
+ */
+static void set_cs_bounds(short cs, long base, long size)
+{
+ debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs);
+ if(size == 0){
+ im->ddr.csbnds[cs].csbnds = 0x00000000;
+ } else {
+ im->ddr.csbnds[cs].csbnds =
+ ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((base + size - 1) >> CSBNDS_EA_SHIFT) &
+ CSBNDS_EA);
+ }
+ SYNC;
+}
+
+/**************************************************************************
+ * Sets DDR banks CS configuration.
+ * config == 0x00000000 disables the CS.
+ */
+static void set_cs_config(short cs, long config)
+{
+ debug("Setting config %08lx for cs %d\n", config, cs);
+ im->ddr.cs_config[cs] = config;
+ SYNC;
+}
+
+/**************************************************************************
+ * Sets DDR clocks, timings and configuration.
+ */
+static void set_ddr_config(void) {
+ /* clock control */
+ im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
+ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
+ SYNC;
+
+ /* timing configuration */
+ im->ddr.timing_cfg_1 =
+ (4 << TIMING_CFG1_PRETOACT_SHIFT) |
+ (7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
+ (4 << TIMING_CFG1_ACTTORW_SHIFT) |
+ (5 << TIMING_CFG1_REFREC_SHIFT) |
+ (3 << TIMING_CFG1_WRREC_SHIFT) |
+ (3 << TIMING_CFG1_ACTTOACT_SHIFT) |
+ (1 << TIMING_CFG1_WRTORD_SHIFT) |
+ (TIMING_CFG1_CASLAT & TIMING_CASLAT);
+
+ im->ddr.timing_cfg_2 =
+ TIMING_CFG2_CPO_DEF |
+ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
+ SYNC;
+
+ /* don't enable DDR controller yet */
+ im->ddr.sdram_cfg =
+ SDRAM_CFG_SREN |
+ SDRAM_CFG_SDRAM_TYPE_DDR1;
+ SYNC;
+
+ /* Set SDRAM mode */
+ im->ddr.sdram_mode =
+ ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
+ SDRAM_MODE_ESD_SHIFT) |
+ ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
+ SDRAM_MODE_SD_SHIFT) |
+ ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
+ MODE_CASLAT);
+ SYNC;
+
+ /* Set fast SDRAM refresh rate */
+ im->ddr.sdram_interval =
+ (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
+ (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
+ SYNC;
+
+ /* Workaround for DDR6 Erratum
+ * see MPC8349E Device Errata Rev.8, 2/2006
+ * This workaround influences the MPC internal "input enables"
+ * dependent on CAS latency and MPC revision. According to errata
+ * sheet the internal reserved registers for this workaround are
+ * not available from revision 2.0 and up.
+ */
+
+ /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
+ * (0x200)
+ */
+ if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
+
+ /* There is a internal reserved register at IMMRBAR+0x2F00
+ * which has to be written with a certain value defined by
+ * errata sheet.
+ */
+ u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00);
+
+#if defined(DDR_CASLAT_20)
+ *reserved_p = 0x201c0000;
+#else
+ *reserved_p = 0x202c0000;
+#endif
+ }
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif /* CONFIG_PCI */
+
+ return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/tqc/tqm8xx/Kconfig b/board/tqc/tqm8xx/Kconfig
new file mode 100644
index 0000000..857fedb
--- /dev/null
+++ b/board/tqc/tqm8xx/Kconfig
@@ -0,0 +1,155 @@
+if TARGET_TQM823L
+
+config SYS_BOARD
+ default "tqm8xx"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM823L"
+
+endif
+
+if TARGET_TQM823M
+
+config SYS_BOARD
+ default "tqm8xx"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM823M"
+
+endif
+
+if TARGET_TQM850L
+
+config SYS_BOARD
+ default "tqm8xx"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM850L"
+
+endif
+
+if TARGET_TQM850M
+
+config SYS_BOARD
+ default "tqm8xx"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM850M"
+
+endif
+
+if TARGET_TQM855L
+
+config SYS_BOARD
+ default "tqm8xx"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM855L"
+
+endif
+
+if TARGET_TQM855M
+
+config SYS_BOARD
+ default "tqm8xx"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM855M"
+
+endif
+
+if TARGET_TQM860L
+
+config SYS_BOARD
+ default "tqm8xx"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM860L"
+
+endif
+
+if TARGET_TQM860M
+
+config SYS_BOARD
+ default "tqm8xx"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM860M"
+
+endif
+
+if TARGET_TQM862L
+
+config SYS_BOARD
+ default "tqm8xx"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM862L"
+
+endif
+
+if TARGET_TQM862M
+
+config SYS_BOARD
+ default "tqm8xx"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM862M"
+
+endif
+
+if TARGET_TQM866M
+
+config SYS_BOARD
+ default "tqm8xx"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM866M"
+
+endif
+
+if TARGET_TQM885D
+
+config SYS_BOARD
+ default "tqm8xx"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_CONFIG_NAME
+ default "TQM885D"
+
+endif
diff --git a/board/tqc/tqm8xx/MAINTAINERS b/board/tqc/tqm8xx/MAINTAINERS
new file mode 100644
index 0000000..f3ddc6a
--- /dev/null
+++ b/board/tqc/tqm8xx/MAINTAINERS
@@ -0,0 +1,31 @@
+TQM8XX BOARD
+M: Wolfgang Denk <wd@denx.de>
+S: Maintained
+F: board/tqc/tqm8xx/
+F: include/configs/TQM823L.h
+F: configs/TQM823L_defconfig
+F: configs/TQM823L_LCD_defconfig
+F: include/configs/TQM823M.h
+F: configs/TQM823M_defconfig
+F: include/configs/TQM850L.h
+F: configs/TQM850L_defconfig
+F: include/configs/TQM850M.h
+F: configs/TQM850M_defconfig
+F: include/configs/TQM855L.h
+F: configs/TQM855L_defconfig
+F: include/configs/TQM855M.h
+F: configs/TQM855M_defconfig
+F: include/configs/TQM860L.h
+F: configs/TQM860L_defconfig
+F: include/configs/TQM860M.h
+F: configs/TQM860M_defconfig
+F: include/configs/TQM862L.h
+F: configs/TQM862L_defconfig
+F: include/configs/TQM862M.h
+F: configs/TQM862M_defconfig
+F: include/configs/TQM866M.h
+F: configs/TQM866M_defconfig
+F: include/configs/TQM885D.h
+F: configs/TQM885D_defconfig
+F: configs/TTTech_defconfig
+F: configs/wtk_defconfig
diff --git a/board/tqc/tqm8xx/Makefile b/board/tqc/tqm8xx/Makefile
new file mode 100644
index 0000000..2651a2f
--- /dev/null
+++ b/board/tqc/tqm8xx/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = tqm8xx.o load_sernum_ethaddr.o
diff --git a/board/tqc/tqm8xx/load_sernum_ethaddr.c b/board/tqc/tqm8xx/load_sernum_ethaddr.c
new file mode 100644
index 0000000..0070da1
--- /dev/null
+++ b/board/tqc/tqm8xx/load_sernum_ethaddr.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*-----------------------------------------------------------------------
+ * Process Hardware Information Block:
+ *
+ * If we boot on a system fresh from factory, check if the Hardware
+ * Information Block exists and save the information it contains.
+ *
+ * The TQM8xxL / TQM82xx Hardware Information Block is defined as
+ * follows:
+ * - located in first flash bank
+ * - starts at offset 0x0003FFC0
+ * - size 0x00000040
+ *
+ * Internal structure:
+ * - sequence of ASCII character strings
+ * - fields separated by a single space character (0x20)
+ * - last field terminated by NUL character (0x00)
+ * - remaining space filled with NUL characters (0x00)
+ *
+ * Fields in Hardware Information Block:
+ * 1) Module Type
+ * 2) Serial Number
+ * 3) First MAC Address
+ * 4) Number of additional MAC addresses
+ */
+
+void load_sernum_ethaddr (void)
+{
+ unsigned char *hwi;
+ unsigned char serial [CONFIG_SYS_HWINFO_SIZE];
+ unsigned char ethaddr[CONFIG_SYS_HWINFO_SIZE];
+ unsigned short ih, is, ie, part;
+
+ hwi = (unsigned char *)(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET);
+ ih = is = ie = 0;
+
+ if (*((unsigned long *)hwi) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
+ return;
+ }
+
+ part = 1;
+
+ /* copy serial # / MAC address */
+ while ((hwi[ih] != '\0') && (ih < CONFIG_SYS_HWINFO_SIZE)) {
+ if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */
+ return;
+ }
+ switch (part) {
+ default: /* Copy serial # */
+ if (hwi[ih] == ' ') {
+ ++part;
+ }
+ serial[is++] = hwi[ih];
+ break;
+ case 3: /* Copy MAC address */
+ if (hwi[ih] == ' ') {
+ ++part;
+ break;
+ }
+ ethaddr[ie++] = hwi[ih];
+ if ((ie % 3) == 2)
+ ethaddr[ie++] = ':';
+ break;
+ }
+ ++ih;
+ }
+ serial[is] = '\0';
+ if (ie && ethaddr[ie-1] == ':')
+ --ie;
+ ethaddr[ie] = '\0';
+
+ /* set serial# and ethaddr if not yet defined */
+ if (getenv("serial#") == NULL) {
+ setenv ((char *)"serial#", (char *)serial);
+ }
+
+ if (getenv("ethaddr") == NULL) {
+ setenv ((char *)"ethaddr", (char *)ethaddr);
+ }
+}
diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c
new file mode 100644
index 0000000..6d17830
--- /dev/null
+++ b/board/tqc/tqm8xx/tqm8xx.c
@@ -0,0 +1,674 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <mpc8xx.h>
+#ifdef CONFIG_PS2MULT
+#include <ps2mult.h>
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
+extern flash_info_t flash_info[]; /* FLASH chips info */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static long int dram_size (long int, long int *, long int);
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
+const uint sdram_table[] =
+{
+ /*
+ * Single Read. (Offset 0 in UPMA RAM)
+ */
+ 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
+ 0x1FF5FC47, /* last */
+ /*
+ * SDRAM Initialization (offset 5 in UPMA RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
+ /*
+ * Burst Read. (Offset 8 in UPMA RAM)
+ */
+ 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
+ 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPMA RAM)
+ */
+ 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
+ 0x1FF5FC47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPMA RAM)
+ */
+ 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
+ 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPMA RAM)
+ */
+ 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC84, 0xFFFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPMA RAM)
+ */
+ 0xFFFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test TQ ID string (TQM8xx...)
+ * If present, check for "L" type (no second DRAM bank),
+ * otherwise "L" type is assumed as default.
+ *
+ * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
+ */
+
+int checkboard (void)
+{
+ char buf[64];
+ int i;
+ int l = getenv_f("serial#", buf, sizeof(buf));
+
+ puts ("Board: ");
+
+ if (l < 0 || strncmp(buf, "TQM8", 4)) {
+ puts ("### No HW ID - assuming TQM8xxL\n");
+ return (0);
+ }
+
+ if ((buf[6] == 'L')) { /* a TQM8xxL type */
+ gd->board_type = 'L';
+ }
+
+ if ((buf[6] == 'M')) { /* a TQM8xxM type */
+ gd->board_type = 'M';
+ }
+
+ if ((buf[6] == 'D')) { /* a TQM885D type */
+ gd->board_type = 'D';
+ }
+
+ for (i = 0; i < l; ++i) {
+ if (buf[i] == ' ')
+ break;
+ putc (buf[i]);
+ }
+
+ putc ('\n');
+
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size8, size9, size10;
+ long int size_b0 = 0;
+ long int size_b1 = 0;
+
+ upmconfig (UPMA, (uint *) sdram_table,
+ sizeof (sdram_table) / sizeof (uint));
+
+ /*
+ * Preliminary prescaler for refresh (depends on number of
+ * banks): This value is selected for four cycles every 62.4 us
+ * with two SDRAM banks or four cycles every 31.2 us with one
+ * bank. It will be adjusted after memory sizing.
+ */
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
+
+ /*
+ * The following value is used as an address (i.e. opcode) for
+ * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
+ * the port size is 32bit the SDRAM does NOT "see" the lower two
+ * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
+ * MICRON SDRAMs:
+ * -> 0 00 010 0 010
+ * | | | | +- Burst Length = 4
+ * | | | +----- Burst Type = Sequential
+ * | | +------- CAS Latency = 2
+ * | +----------- Operating Mode = Standard
+ * +-------------- Write Burst Mode = Programmed Burst Length
+ */
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+ * preliminary addresses - these have to be modified after the
+ * SDRAM size has been determined.
+ */
+ memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+ memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
+
+#ifndef CONFIG_CAN_DRIVER
+ if ((board_type != 'L') &&
+ (board_type != 'M') &&
+ (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
+ memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+ memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
+ }
+#endif /* CONFIG_CAN_DRIVER */
+
+ memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+
+ udelay (200);
+
+ /* perform SDRAM initializsation sequence */
+
+ memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
+ udelay (1);
+ memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
+ udelay (1);
+
+#ifndef CONFIG_CAN_DRIVER
+ if ((board_type != 'L') &&
+ (board_type != 'M') &&
+ (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
+ memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
+ udelay (1);
+ memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
+ udelay (1);
+ }
+#endif /* CONFIG_CAN_DRIVER */
+
+ memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+
+ udelay (1000);
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ * try 8 column mode
+ */
+ size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
+
+ udelay (1000);
+
+ /*
+ * try 9 column mode
+ */
+ size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
+
+ udelay(1000);
+
+#if defined(CONFIG_SYS_MAMR_10COL)
+ /*
+ * try 10 column mode
+ */
+ size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
+#else
+ size10 = 0;
+#endif /* CONFIG_SYS_MAMR_10COL */
+
+ if ((size8 < size10) && (size9 < size10)) {
+ size_b0 = size10;
+ } else if ((size8 < size9) && (size10 < size9)) {
+ size_b0 = size9;
+ memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
+ udelay (500);
+ } else {
+ size_b0 = size8;
+ memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
+ udelay (500);
+ }
+ debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
+
+#ifndef CONFIG_CAN_DRIVER
+ if ((board_type != 'L') &&
+ (board_type != 'M') &&
+ (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
+ /*
+ * Check Bank 1 Memory Size
+ * use current column settings
+ * [9 column SDRAM may also be used in 8 column mode,
+ * but then only half the real size will be used.]
+ */
+ size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
+ SDRAM_MAX_SIZE);
+ debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
+ } else {
+ size_b1 = 0;
+ }
+#endif /* CONFIG_CAN_DRIVER */
+
+ udelay (1000);
+
+ /*
+ * Adjust refresh rate depending on SDRAM type, both banks
+ * For types > 128 MBit leave it at the current (fast) rate
+ */
+ if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
+ /* reduce to 15.6 us (62.4 us / quad) */
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
+ udelay (1000);
+ }
+
+ /*
+ * Final mapping: map bigger bank first
+ */
+ if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
+
+ memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+ memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+ if (size_b0 > 0) {
+ /*
+ * Position Bank 0 immediately above Bank 1
+ */
+ memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+ memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ + size_b1;
+ } else {
+ unsigned long reg;
+
+ /*
+ * No bank 0
+ *
+ * invalidate bank
+ */
+ memctl->memc_br2 = 0;
+
+ /* adjust refresh rate depending on SDRAM type, one bank */
+ reg = memctl->memc_mptpr;
+ reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
+ memctl->memc_mptpr = reg;
+ }
+
+ } else { /* SDRAM Bank 0 is bigger - map first */
+
+ memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+ memctl->memc_br2 =
+ (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+ if (size_b1 > 0) {
+ /*
+ * Position Bank 1 immediately above Bank 0
+ */
+ memctl->memc_or3 =
+ ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+ memctl->memc_br3 =
+ ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ + size_b0;
+ } else {
+ unsigned long reg;
+
+#ifndef CONFIG_CAN_DRIVER
+ /*
+ * No bank 1
+ *
+ * invalidate bank
+ */
+ memctl->memc_br3 = 0;
+#endif /* CONFIG_CAN_DRIVER */
+
+ /* adjust refresh rate depending on SDRAM type, one bank */
+ reg = memctl->memc_mptpr;
+ reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
+ memctl->memc_mptpr = reg;
+ }
+ }
+
+ udelay (10000);
+
+#ifdef CONFIG_CAN_DRIVER
+ /* UPM initialization for CAN @ CLKOUT <= 66 MHz */
+
+ /* Initialize OR3 / BR3 */
+ memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
+ memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
+
+ /* Initialize MBMR */
+ memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
+
+ /* Initialize UPMB for CAN: single read */
+ memctl->memc_mdr = 0xFFFFCC04;
+ memctl->memc_mcr = 0x0100 | UPMB;
+
+ memctl->memc_mdr = 0x0FFFD004;
+ memctl->memc_mcr = 0x0101 | UPMB;
+
+ memctl->memc_mdr = 0x0FFFC000;
+ memctl->memc_mcr = 0x0102 | UPMB;
+
+ memctl->memc_mdr = 0x3FFFC004;
+ memctl->memc_mcr = 0x0103 | UPMB;
+
+ memctl->memc_mdr = 0xFFFFDC07;
+ memctl->memc_mcr = 0x0104 | UPMB;
+
+ /* Initialize UPMB for CAN: single write */
+ memctl->memc_mdr = 0xFFFCCC04;
+ memctl->memc_mcr = 0x0118 | UPMB;
+
+ memctl->memc_mdr = 0xCFFCDC04;
+ memctl->memc_mcr = 0x0119 | UPMB;
+
+ memctl->memc_mdr = 0x3FFCC000;
+ memctl->memc_mcr = 0x011A | UPMB;
+
+ memctl->memc_mdr = 0xFFFCC004;
+ memctl->memc_mcr = 0x011B | UPMB;
+
+ memctl->memc_mdr = 0xFFFDC405;
+ memctl->memc_mcr = 0x011C | UPMB;
+#endif /* CONFIG_CAN_DRIVER */
+
+#ifdef CONFIG_ISP1362_USB
+ /* Initialize OR5 / BR5 */
+ memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
+ memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
+#endif /* CONFIG_ISP1362_USB */
+ return (size_b0 + size_b1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ memctl->memc_mamr = mamr_value;
+
+ return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_MISC_INIT_R
+extern void load_sernum_ethaddr(void);
+int misc_init_r (void)
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+ load_sernum_ethaddr();
+
+#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
+ int scy, trlx, flash_or_timing, clk_diff;
+
+ scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
+ if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
+ trlx = OR_TRLX;
+ scy *= 2;
+ } else {
+ trlx = 0;
+ }
+
+ /*
+ * We assume that each 10MHz of bus clock require 1-clk SCY
+ * adjustment.
+ */
+ clk_diff = (gd->bus_clk / 1000000) - 50;
+
+ /*
+ * We need proper rounding here. This is what the "+5" and "-5"
+ * are here for.
+ */
+ if (clk_diff >= 0)
+ scy += (clk_diff + 5) / 10;
+ else
+ scy += (clk_diff - 5) / 10;
+
+ /*
+ * For bus frequencies above 50MHz, we want to use relaxed timing
+ * (OR_TRLX).
+ */
+ if (gd->bus_clk >= 50000000)
+ trlx = OR_TRLX;
+ else
+ trlx = 0;
+
+ if (trlx)
+ scy /= 2;
+
+ if (scy > 0xf)
+ scy = 0xf;
+ if (scy < 1)
+ scy = 1;
+
+ flash_or_timing = (scy << 4) | trlx |
+ (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
+
+ memctl->memc_or0 =
+ flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
+#else
+ memctl->memc_or0 =
+ CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
+#endif
+ memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+ debug ("## BR0: 0x%08x OR0: 0x%08x\n",
+ memctl->memc_br0, memctl->memc_or0);
+
+ if (flash_info[1].size) {
+#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
+ memctl->memc_or1 = flash_or_timing |
+ (-flash_info[1].size & 0xFFFF8000);
+#else
+ memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
+ (-flash_info[1].size & 0xFFFF8000);
+#endif
+ memctl->memc_br1 =
+ ((CONFIG_SYS_FLASH_BASE +
+ flash_info[0].
+ size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+ debug ("## BR1: 0x%08x OR1: 0x%08x\n",
+ memctl->memc_br1, memctl->memc_or1);
+ } else {
+ memctl->memc_br1 = 0; /* invalidate bank */
+
+ debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
+ memctl->memc_br1, memctl->memc_or1);
+ }
+
+# ifdef CONFIG_IDE_LED
+ /* Configure PA15 as output port */
+ immap->im_ioport.iop_padir |= 0x0001;
+ immap->im_ioport.iop_paodr |= 0x0001;
+ immap->im_ioport.iop_papar &= ~0x0001;
+ immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
+# endif
+
+ return (0);
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+
+# ifdef CONFIG_IDE_LED
+void ide_led (uchar led, uchar status)
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+ /* We have one led for both pcmcia slots */
+ if (status) { /* led on */
+ immap->im_ioport.iop_padat |= 0x0001;
+ } else {
+ immap->im_ioport.iop_padat &= ~0x0001;
+ }
+}
+# endif
+
+#ifdef CONFIG_LCD_INFO
+#include <lcd.h>
+#include <version.h>
+#include <timestamp.h>
+
+void lcd_show_board_info(void)
+{
+ char temp[32];
+
+ lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
+ lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
+ lcd_printf (" Wolfgang DENK, wd@denx.de\n");
+#ifdef CONFIG_LCD_INFO_BELOW_LOGO
+ lcd_printf ("MPC823 CPU at %s MHz\n",
+ strmhz(temp, gd->cpu_clk));
+ lcd_printf (" %ld MB RAM, %ld MB Flash\n",
+ gd->ram_size >> 20,
+ gd->bd->bi_flashsize >> 20 );
+#else
+ /* leave one blank line */
+ lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
+ strmhz(temp, gd->cpu_clk),
+ gd->ram_size >> 20,
+ gd->bd->bi_flashsize >> 20 );
+#endif /* CONFIG_LCD_INFO_BELOW_LOGO */
+}
+#endif /* CONFIG_LCD_INFO */
+
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+int fdt_set_node_and_value (void *blob,
+ char *nodename,
+ char *regname,
+ void *var,
+ int size)
+{
+ int ret = 0;
+ int nodeoffset = 0;
+
+ nodeoffset = fdt_path_offset (blob, nodename);
+ if (nodeoffset >= 0) {
+ ret = fdt_setprop (blob, nodeoffset, regname, var,
+ size);
+ if (ret < 0) {
+ printf("ft_blob_update(): "
+ "cannot set %s/%s property; err: %s\n",
+ nodename, regname, fdt_strerror (ret));
+ }
+ } else {
+ printf("ft_blob_update(): "
+ "cannot find %s node err:%s\n",
+ nodename, fdt_strerror (nodeoffset));
+ }
+ return ret;
+}
+
+int fdt_del_node_name (void *blob, char *nodename)
+{
+ int ret = 0;
+ int nodeoffset = 0;
+
+ nodeoffset = fdt_path_offset (blob, nodename);
+ if (nodeoffset >= 0) {
+ ret = fdt_del_node (blob, nodeoffset);
+ if (ret < 0) {
+ printf("%s: cannot delete %s; err: %s\n",
+ __func__, nodename, fdt_strerror (ret));
+ }
+ } else {
+ printf("%s: cannot find %s node err:%s\n",
+ __func__, nodename, fdt_strerror (nodeoffset));
+ }
+ return ret;
+}
+
+int fdt_del_prop_name (void *blob, char *nodename, char *propname)
+{
+ int ret = 0;
+ int nodeoffset = 0;
+
+ nodeoffset = fdt_path_offset (blob, nodename);
+ if (nodeoffset >= 0) {
+ ret = fdt_delprop (blob, nodeoffset, propname);
+ if (ret < 0) {
+ printf("%s: cannot delete %s %s; err: %s\n",
+ __func__, nodename, propname,
+ fdt_strerror (ret));
+ }
+ } else {
+ printf("%s: cannot find %s node err:%s\n",
+ __func__, nodename, fdt_strerror (nodeoffset));
+ }
+ return ret;
+}
+
+/*
+ * update "brg" property in the blob
+ */
+void ft_blob_update (void *blob, bd_t *bd)
+{
+ uchar enetaddr[6];
+ ulong brg_data = 0;
+
+ /* BRG */
+ brg_data = cpu_to_be32(bd->bi_busfreq);
+ fdt_set_node_and_value(blob,
+ "/soc/cpm", "brg-frequency",
+ &brg_data, sizeof(brg_data));
+
+ /* MAC addr */
+ if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ fdt_set_node_and_value(blob,
+ "ethernet0", "local-mac-address",
+ enetaddr, sizeof(u8) * 6);
+ }
+
+ if (hwconfig_arg_cmp("fec", "off")) {
+ /* no FEC on this plattform, delete DTS nodes */
+ fdt_del_node_name (blob, "ethernet1");
+ fdt_del_node_name (blob, "mdio1");
+ /* also the aliases entries */
+ fdt_del_prop_name (blob, "/aliases", "ethernet1");
+ fdt_del_prop_name (blob, "/aliases", "mdio1");
+ } else {
+ /* adjust local-mac-address for FEC ethernet */
+ if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
+ fdt_set_node_and_value(blob,
+ "ethernet1", "local-mac-address",
+ enetaddr, sizeof(u8) * 6);
+ }
+ }
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ ft_blob_update(blob, bd);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds
new file mode 100644
index 0000000..b77ae56
--- /dev/null
+++ b/board/tqc/tqm8xx/u-boot.lds
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000-2012
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ arch/powerpc/cpu/mpc8xx/start.o (.text*)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text*)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
+ board/tqc/tqm8xx/built-in.o (.text*)
+ disk/built-in.o (.text*)
+ drivers/net/built-in.o (.text*)
+ drivers/built-in.o (.text.pcmcia_on)
+ drivers/built-in.o (.text.pcmcia_hardware_enable)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.ppcenv*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig
new file mode 100644
index 0000000..f8b3d1f
--- /dev/null
+++ b/board/tqc/tqma6/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TQMA6
+
+config SYS_BOARD
+ default "tqma6"
+
+config SYS_VENDOR
+ default "tqc"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "tqma6"
+
+endif
diff --git a/board/tqc/tqma6/MAINTAINERS b/board/tqc/tqma6/MAINTAINERS
new file mode 100644
index 0000000..91cd244
--- /dev/null
+++ b/board/tqc/tqma6/MAINTAINERS
@@ -0,0 +1,6 @@
+TQ SYSTEMS TQMA6 BOARD
+M: Markus Niebel <Markus.Niebel@tq-group.com>
+S: Maintained
+F: board/tqc/tqma6/
+F: include/configs/tqma6.h
+F: configs/tqma6*_defconfig
diff --git a/board/tqc/tqma6/Makefile b/board/tqc/tqma6/Makefile
new file mode 100644
index 0000000..9ee6920
--- /dev/null
+++ b/board/tqc/tqma6/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2014, Markus Niebel <Markus.Niebel@tq-group.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := tqma6.o
+
+obj-$(CONFIG_MBA6) += tqma6_mba6.o
diff --git a/board/tqc/tqma6/README b/board/tqc/tqma6/README
new file mode 100644
index 0000000..2c012e7
--- /dev/null
+++ b/board/tqc/tqma6/README
@@ -0,0 +1,35 @@
+U-Boot for the TQ Systems TQMa6 modules
+
+This file contains information for the port of
+U-Boot to the TQ Systems TQMa6 modules.
+
+1. Boot source
+--------------
+
+The following boot source is supported:
+
+- SD/eMMC
+- SPI NOR
+
+2. Building
+------------
+
+To build U-Boot for the TQ Systems TQMa6 modules:
+
+ make tqma6<x>_<baseboard>_<boot>_config
+ make
+
+x is a placeholder for the CPU variant
+q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D)
+s - means i.MX6S: TQMa6S (i.MX6S)
+
+baseboard is a placeholder for the boot device
+mmc - means eMMC
+spi - mean SPI NOR
+
+This gives the following configurations:
+
+tqma6q_mba6_mmc_config
+tqma6q_mba6_spi_config
+tqma6s_mba6_mmc_config
+tqma6s_mba6_spi_config
diff --git a/board/tqc/tqma6/clocks.cfg b/board/tqc/tqma6/clocks.cfg
new file mode 100644
index 0000000..d9dd273
--- /dev/null
+++ b/board/tqc/tqma6/clocks.cfg
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c
new file mode 100644
index 0000000..c9e163e
--- /dev/null
+++ b/board/tqc/tqma6/tqma6.c
@@ -0,0 +1,279 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
+ * Author: Markus Niebel <markus.niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/spi.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <libfdt.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <power/pfuze100_pmic.h>
+#include <power/pmic.h>
+
+#include "tqma6_bb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+static const uint16_t tqma6_emmc_dsr = 0x0100;
+
+/* eMMC on USDHCI3 always present */
+static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
+ NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
+ /* eMMC reset */
+ NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
+};
+
+/*
+ * According to board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 eMMC (SD3) on TQMa6
+ * mmc1 .. n optional slots used on baseboard
+ */
+struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
+ .esdhc_base = USDHC3_BASE_ADDR,
+ .max_bus_width = 8,
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+ /* eMMC/uSDHC3 is always present */
+ ret = 1;
+ else
+ ret = tqma6_bb_board_mmc_getcd(mmc);
+
+ return ret;
+}
+
+int board_mmc_getwp(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+ /* eMMC/uSDHC3 is always present */
+ ret = 0;
+ else
+ ret = tqma6_bb_board_mmc_getwp(mmc);
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
+ ARRAY_SIZE(tqma6_usdhc3_pads));
+ tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
+ puts("Warning: failed to initialize eMMC dev\n");
+ } else {
+ struct mmc *mmc = find_mmc_device(0);
+ if (mmc)
+ mmc_set_dsr(mmc, tqma6_emmc_dsr);
+ }
+
+ tqma6_bb_board_mmc_init(bis);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
+ /* SS1 */
+ NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
+};
+
+#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
+
+static unsigned const tqma6_ecspi1_cs[] = {
+ TQMA6_SF_CS_GPIO,
+};
+
+static void tqma6_iomuxc_spi(void)
+{
+ unsigned i;
+
+ for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
+ gpio_direction_output(tqma6_ecspi1_cs[i], 1);
+ imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
+ ARRAY_SIZE(tqma6_ecspi1_pads));
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return ((bus == CONFIG_SF_DEFAULT_BUS) &&
+ (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
+}
+
+static struct i2c_pads_info tqma6_i2c3_pads = {
+ /* I2C3: on board LM75, M24C64, */
+ .scl = {
+ .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
+ I2C_PAD_CTRL),
+ .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
+ I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(1, 5)
+ },
+ .sda = {
+ .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
+ I2C_PAD_CTRL),
+ .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
+ I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+
+static void tqma6_setup_i2c(void)
+{
+ int ret;
+ /*
+ * use logical index for bus, e.g. I2C1 -> 0
+ * warn on error
+ */
+ ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
+ if (ret)
+ printf("setup I2C3 failed: %d\n", ret);
+}
+
+int board_early_init_f(void)
+{
+ return tqma6_bb_board_early_init_f();
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ tqma6_iomuxc_spi();
+ tqma6_setup_i2c();
+
+ tqma6_bb_board_init();
+
+ return 0;
+}
+
+static const char *tqma6_get_boardname(void)
+{
+ u32 cpurev = get_cpu_rev();
+
+ switch ((cpurev & 0xFF000) >> 12) {
+ case MXC_CPU_MX6SOLO:
+ return "TQMa6S";
+ break;
+ case MXC_CPU_MX6DL:
+ return "TQMa6DL";
+ break;
+ case MXC_CPU_MX6D:
+ return "TQMa6D";
+ break;
+ case MXC_CPU_MX6Q:
+ return "TQMa6Q";
+ break;
+ default:
+ return "??";
+ };
+}
+
+int board_late_init(void)
+{
+ struct pmic *p;
+ u32 reg;
+
+ setenv("board_name", tqma6_get_boardname());
+
+ /*
+ * configure PFUZE100 PMIC:
+ * TODO: should go to power_init_board if bus switching is
+ * fixed in generic power code
+ */
+ power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
+ p = pmic_get("PFUZE100");
+ if (p && !pmic_probe(p)) {
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+ }
+
+ tqma6_bb_board_late_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: %s on a %s\n", tqma6_get_boardname(),
+ tqma6_bb_get_boardname());
+ return 0;
+}
+
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* bring in eMMC dsr settings */
+ do_fixup_by_path_u32(blob,
+ "/soc/aips-bus@02100000/usdhc@02198000",
+ "dsr", tqma6_emmc_dsr, 2);
+ tqma6_bb_ft_board_setup(blob, bd);
+
+ return 0;
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/tqc/tqma6/tqma6_bb.h b/board/tqc/tqma6/tqma6_bb.h
new file mode 100644
index 0000000..fb7b462
--- /dev/null
+++ b/board/tqc/tqma6/tqma6_bb.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2013, 2014 TQ Systems
+ * Author: Markus Niebel <markus.niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TQMA6_BB__
+#define __TQMA6_BB__
+
+#include <common.h>
+
+int tqma6_bb_board_mmc_getwp(struct mmc *mmc);
+int tqma6_bb_board_mmc_getcd(struct mmc *mmc);
+int tqma6_bb_board_mmc_init(bd_t *bis);
+
+int tqma6_bb_board_early_init_f(void);
+int tqma6_bb_board_init(void);
+int tqma6_bb_board_late_init(void);
+int tqma6_bb_checkboard(void);
+
+const char *tqma6_bb_get_boardname(void);
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void tqma6_bb_ft_board_setup(void *blob, bd_t *bd);
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+
+#endif
diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c
new file mode 100644
index 0000000..6f4cffd
--- /dev/null
+++ b/board/tqc/tqma6/tqma6_mba6.c
@@ -0,0 +1,367 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
+ * Author: Markus Niebel <markus.niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <libfdt.h>
+#include <malloc.h>
+#include <i2c.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+
+#include "tqma6_bb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#if defined(CONFIG_MX6Q)
+
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
+#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac
+
+#elif defined(CONFIG_MX6S)
+
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768
+#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788
+
+#else
+
+#error "need to define target CPU"
+
+#endif
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_DSE_34ohm)
+#define ENET_TX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm)
+#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_34ohm)
+#define ENET_MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_60ohm)
+
+/* disable on die termination for RGMII */
+#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000
+/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000
+/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000
+
+#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25)
+
+static iomux_v3_cfg_t const mba6_enet_pads[] = {
+ NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_MDIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_MDIO_PAD_CTRL),
+
+ NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC, ENET_TX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0, ENET_TX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1, ENET_TX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2, ENET_TX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3, ENET_TX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL,
+ ENET_TX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_CLK_PAD_CTRL),
+ /*
+ * these pins are also used for config strapping by phy
+ */
+ NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0, ENET_RX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1, ENET_RX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2, ENET_RX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3, ENET_RX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC, ENET_RX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL,
+ ENET_RX_PAD_CTRL),
+ /* KSZ9031 PHY Reset */
+ NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25, GPIO_OUT_PAD_CTRL),
+};
+
+static void mba6_setup_iomuxc_enet(void)
+{
+ __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
+ (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
+ __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
+ (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
+
+ imx_iomux_v3_setup_multiple_pads(mba6_enet_pads,
+ ARRAY_SIZE(mba6_enet_pads));
+
+ /* Reset PHY */
+ gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
+ /* Need delay 10ms after power on according to KSZ9031 spec */
+ udelay(1000 * 10);
+ gpio_set_value(ENET_PHY_RESET_GPIO, 1);
+ /*
+ * KSZ9031 manual: 100 usec wait time after reset before communication
+ * over MDIO
+ * BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on
+ * reset before the phy sees a high level
+ */
+ udelay(200);
+}
+
+static iomux_v3_cfg_t const mba6_uart2_pads[] = {
+ NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
+};
+
+static void mba6_setup_iomuxc_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
+ ARRAY_SIZE(mba6_uart2_pads));
+}
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
+
+int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+
+ return ret;
+}
+
+int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+ ret = gpio_get_value(USDHC2_WP_GPIO);
+
+ return ret;
+}
+
+static struct fsl_esdhc_cfg mba6_usdhc_cfg = {
+ .esdhc_base = USDHC2_BASE_ADDR,
+ .max_bus_width = 4,
+};
+
+static iomux_v3_cfg_t const mba6_usdhc2_pads[] = {
+ NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC_CLK_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
+ /* CD */
+ NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, GPIO_IN_PAD_CTRL),
+ /* WP */
+ NEW_PAD_CTRL(MX6_PAD_GPIO_2__GPIO1_IO02, GPIO_IN_PAD_CTRL),
+};
+
+int tqma6_bb_board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(mba6_usdhc2_pads,
+ ARRAY_SIZE(mba6_usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ gpio_direction_input(USDHC2_WP_GPIO);
+
+ mba6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ if (fsl_esdhc_initialize(bis, &mba6_usdhc_cfg))
+ puts("Warning: failed to initialize SD\n");
+
+ return 0;
+}
+
+static struct i2c_pads_info mba6_i2c1_pads = {
+/* I2C1: MBa6x */
+ .scl = {
+ .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL,
+ I2C_PAD_CTRL),
+ .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27,
+ I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA,
+ I2C_PAD_CTRL),
+ .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26,
+ I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+static void mba6_setup_i2c(void)
+{
+ int ret;
+ /*
+ * use logical index for bus, e.g. I2C1 -> 0
+ * warn on error
+ */
+ ret = setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
+ if (ret)
+ printf("setup I2C1 failed: %d\n", ret);
+}
+
+
+static iomux_v3_cfg_t const mba6_ecspi1_pads[] = {
+ NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL),
+};
+
+static unsigned const mba6_ecspi1_cs[] = {
+ IMX_GPIO_NR(3, 24),
+ IMX_GPIO_NR(3, 25),
+};
+
+static void mba6_setup_iomuxc_spi(void)
+{
+ unsigned i;
+
+ for (i = 0; i < ARRAY_SIZE(mba6_ecspi1_cs); ++i)
+ gpio_direction_output(mba6_ecspi1_cs[i], 1);
+ imx_iomux_v3_setup_multiple_pads(mba6_ecspi1_pads,
+ ARRAY_SIZE(mba6_ecspi1_pads));
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+/*
+ * optimized pad skew values depends on CPU variant on the TQMa6x module:
+ * i.MX6Q/D or i.MX6DL/S
+ */
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)
+#define MBA6X_KSZ9031_CTRL_SKEW 0x0032
+#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
+#define MBA6X_KSZ9031_RX_SKEW 0x3333
+#define MBA6X_KSZ9031_TX_SKEW 0x2036
+#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#define MBA6X_KSZ9031_CTRL_SKEW 0x0030
+#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
+#define MBA6X_KSZ9031_RX_SKEW 0x3333
+#define MBA6X_KSZ9031_TX_SKEW 0x2052
+#else
+#error
+#endif
+ /* min rx/tx ctrl delay */
+ ksz9031_phy_extended_write(phydev, 2,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ MBA6X_KSZ9031_CTRL_SKEW);
+ /* min rx delay */
+ ksz9031_phy_extended_write(phydev, 2,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ MBA6X_KSZ9031_RX_SKEW);
+ /* max tx delay */
+ ksz9031_phy_extended_write(phydev, 2,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ MBA6X_KSZ9031_TX_SKEW);
+ /* rx/tx clk skew */
+ ksz9031_phy_extended_write(phydev, 2,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ MBA6X_KSZ9031_CLK_SKEW);
+
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ uint32_t base = IMX_FEC_BASE;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret;
+
+ bus = fec_get_miibus(base, -1);
+ if (!bus)
+ return 0;
+ /* scan phy */
+ phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
+ PHY_INTERFACE_MODE_RGMII);
+
+ if (!phydev) {
+ free(bus);
+ puts("No phy found\n");
+ return 0;
+ }
+ ret = fec_probe(bis, -1, base, bus, phydev);
+ if (ret) {
+ puts("FEC MXC: probe failed\n");
+ free(phydev);
+ free(bus);
+ }
+
+ return 0;
+}
+
+int tqma6_bb_board_early_init_f(void)
+{
+ mba6_setup_iomuxc_uart();
+
+ return 0;
+}
+
+int tqma6_bb_board_init(void)
+{
+ mba6_setup_i2c();
+ mba6_setup_iomuxc_spi();
+ /* do it here - to have reset completed */
+ mba6_setup_iomuxc_enet();
+
+ return 0;
+}
+
+int tqma6_bb_board_late_init(void)
+{
+ return 0;
+}
+
+const char *tqma6_bb_get_boardname(void)
+{
+ return "MBa6x";
+}
+
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
+{
+ /* TBD */
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/tqc/tqma6/tqma6q.cfg b/board/tqc/tqma6/tqma6q.cfg
new file mode 100644
index 0000000..f54dff7
--- /dev/null
+++ b/board/tqc/tqma6/tqma6q.cfg
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+#if defined(CONFIG_TQMA6X_MMC_BOOT)
+BOOT_FROM sd
+#elif defined(CONFIG_TQMA6X_SPI_BOOT)
+BOOT_FROM spi
+#endif
+
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* TQMa6Q/D DDR config Rev. 0100B */
+/* IOMUX configuration */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
+
+/* memory interface calibration values */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012001C
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43400350
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x023E032C
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43400348
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03300304
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323436
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38383242
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4236483E
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/* configure memory interface */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x545A79B4
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09308030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025536
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+#include "clocks.cfg"
diff --git a/board/tqc/tqma6/tqma6s.cfg b/board/tqc/tqma6/tqma6s.cfg
new file mode 100644
index 0000000..24d4e2f
--- /dev/null
+++ b/board/tqc/tqma6/tqma6s.cfg
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+#if defined(CONFIG_TQMA6X_MMC_BOOT)
+BOOT_FROM sd
+#elif defined(CONFIG_TQMA6X_SPI_BOOT)
+BOOT_FROM spi
+#endif
+
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* TQMa6S DDR config Rev. 0100B */
+/* IOMUX configuration */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008000
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
+
+/* memory interface calibration values */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380000
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0014000E
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00120014
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00000000
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00000000
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x0240023C
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0228022C
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x00000000
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x00000000
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4A4A4E4A
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x00000000
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36362A32
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x00000000
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x00000000
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000000
+
+/* configure memory interface */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+#include "clocks.cfg"
diff --git a/board/trizepsiv/Kconfig b/board/trizepsiv/Kconfig
new file mode 100644
index 0000000..56b2557
--- /dev/null
+++ b/board/trizepsiv/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_TRIZEPSIV
+
+config SYS_BOARD
+ default "trizepsiv"
+
+config SYS_CONFIG_NAME
+ default "trizepsiv"
+
+endif
diff --git a/board/trizepsiv/MAINTAINERS b/board/trizepsiv/MAINTAINERS
new file mode 100644
index 0000000..ba48c2e
--- /dev/null
+++ b/board/trizepsiv/MAINTAINERS
@@ -0,0 +1,7 @@
+TRIZEPSIV BOARD
+M: Stefano Babic <sbabic@denx.de>
+S: Maintained
+F: board/trizepsiv/
+F: include/configs/trizepsiv.h
+F: configs/polaris_defconfig
+F: configs/trizepsiv_defconfig
diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile
new file mode 100644
index 0000000..c49686f
--- /dev/null
+++ b/board/trizepsiv/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := conxs.o eeprom.o
diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
new file mode 100644
index 0000000..1ddf05d
--- /dev/null
+++ b/board/trizepsiv/conxs.c
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ *
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa.h>
+#include <asm/arch/regs-mmc.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define RH_A_PSM (1 << 8) /* power switching mode */
+#define RH_A_NPS (1 << 9) /* no power switching */
+
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
+#if CONFIG_MK_POLARIS
+#define BOOT_CONSOLE "serial_stuart"
+#else
+#define BOOT_CONSOLE "serial_ffuart"
+#endif
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
+
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
+
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+ /* Clear any OTG Pin Hold */
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+ writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
+ writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
+
+ /* Set port power control mask bits, only 3 ports. */
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+void usb_board_stop(void)
+{
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+ udelay(11);
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
+ udelay(10);
+
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+ return;
+}
+
+int board_init (void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* arch number of ConXS Board */
+ gd->bd->bi_arch_number = 776;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa000003c;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ char *console=getenv("boot_console");
+
+ if ((console == NULL) || (strcmp(console,"serial_btuart") &&
+ strcmp(console,"serial_stuart") &&
+ strcmp(console,"serial_ffuart"))) {
+ console = BOOT_CONSOLE;
+ }
+ setenv("stdout",console);
+ setenv("stdin", console);
+ setenv("stderr",console);
+ return 0;
+}
+
+int dram_init(void)
+{
+ pxa2xx_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c
new file mode 100644
index 0000000..1318edc
--- /dev/null
+++ b/board/trizepsiv/eeprom.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm9000.h>
+
+static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
+ unsigned int i;
+ u8 data[2];
+
+ for (i=0; i < 0x40; i++) {
+ if (!(i % 0x10))
+ printf("\n%08x:", i);
+ dm9000_read_srom_word(i, data);
+ printf(" %02x%02x", data[1], data[0]);
+ }
+ printf ("\n");
+ return (0);
+}
+
+static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
+ int offset,value;
+
+ if (argc < 4)
+ return cmd_usage(cmdtp);
+
+ offset=simple_strtoul(argv[2],NULL,16);
+ value=simple_strtoul(argv[3],NULL,16);
+ if (offset > 0x40) {
+ printf("Wrong offset : 0x%x\n",offset);
+ return cmd_usage(cmdtp);
+ }
+ dm9000_write_srom_word(offset, value);
+ return (0);
+}
+
+int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ if (strcmp (argv[1],"read") == 0)
+ return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv));
+ else if (strcmp (argv[1],"write") == 0)
+ return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
+ else
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(
+ dm9000ee,4,1,do_dm9000_eeprom,
+ "Read/Write eeprom connected to Ethernet Controller",
+ "\ndm9000ee write <word offset> <value> \n"
+ "\tdm9000ee read \n"
+ "\tword:\t\t00-02 : MAC Address\n"
+ "\t\t\t03-07 : DM9000 Configuration\n"
+ "\t\t\t08-63 : User data"
+);
diff --git a/board/ttcontrol/vision2/Kconfig b/board/ttcontrol/vision2/Kconfig
new file mode 100644
index 0000000..cacd2c5
--- /dev/null
+++ b/board/ttcontrol/vision2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_VISION2
+
+config SYS_BOARD
+ default "vision2"
+
+config SYS_VENDOR
+ default "ttcontrol"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "vision2"
+
+endif
diff --git a/board/ttcontrol/vision2/MAINTAINERS b/board/ttcontrol/vision2/MAINTAINERS
new file mode 100644
index 0000000..cfc9903
--- /dev/null
+++ b/board/ttcontrol/vision2/MAINTAINERS
@@ -0,0 +1,6 @@
+VISION2 BOARD
+M: Stefano Babic <sbabic@denx.de>
+S: Maintained
+F: board/ttcontrol/vision2/
+F: include/configs/vision2.h
+F: configs/vision2_defconfig
diff --git a/board/ttcontrol/vision2/Makefile b/board/ttcontrol/vision2/Makefile
new file mode 100644
index 0000000..c3e1e87
--- /dev/null
+++ b/board/ttcontrol/vision2/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := vision2.o
diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg
new file mode 100644
index 0000000..c74973e
--- /dev/null
+++ b/board/ttcontrol/vision2/imximage_hynix.cfg
@@ -0,0 +1,212 @@
+/*
+ * (C) Copyright 2009
+ * Stefano Babic DENX Software Engineering sbabic@denx.de.
+ *
+ * (C) Copyright 2010
+ * Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/*
+ * Boot Device : one of
+ * spi, nand, onenand, sd
+ */
+BOOT_FROM spi
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * #######################
+ * ### Disable WDOG ###
+ * #######################
+ */
+DATA 2 0x73f98000 0x30
+
+/*
+ * #######################
+ * ### SET DDR Clk ###
+ * #######################
+ */
+/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
+DATA 4 0x73FD4018 0x000024C0
+
+/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
+DATA 4 0x73FD4038 0x2010241
+
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
+DATA 4 0x73fa8600 0x00000107
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
+DATA 4 0x73fa8604 0x00000107
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
+DATA 4 0x73fa8608 0x00000187
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
+DATA 4 0x73fa860c 0x00000187
+/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
+DATA 4 0x73fa8614 0x00000107
+/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
+DATA 4 0x73fa86a8 0x00000187
+
+/*
+ * #######################
+ * ### Settings IOMUXC ###
+ * #######################
+ */
+/*
+ * DDR IOMUX configuration
+ * Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
+ * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
+ */
+DATA 4 0x73fa84b8 0x000000e7
+/* PVTC MAX (at GPC, PGR reg) */
+/* DATA 4 0x73FD8004 0x1fc00000 */
+
+/* DQM0 DS high slew rate slow */
+DATA 4 0x73fa84d4 0x000000e4
+/* DQM1 DS high slew rate slow */
+DATA 4 0x73fa84d8 0x000000e4
+/* DQM2 DS high slew rate slow */
+DATA 4 0x73fa84dc 0x000000e4
+/* DQM3 DS high slew rate slow */
+DATA 4 0x73fa84e0 0x000000e4
+
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
+DATA 4 0x73fa84bc 0x000000c4
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
+DATA 4 0x73fa84c0 0x000000c4
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
+DATA 4 0x73fa84c4 0x000000c4
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
+DATA 4 0x73fa84c8 0x000000c4
+
+/* DRAM_DATA B0 */
+DATA 4 0x73fa88a4 0x00000004
+/* DRAM_DATA B1 */
+DATA 4 0x73fa88ac 0x00000004
+/* DRAM_DATA B2 */
+DATA 4 0x73fa88b8 0x00000004
+/* DRAM_DATA B3 */
+DATA 4 0x73fa882c 0x00000004
+
+/* DRAM_DATA B0 slew rate */
+DATA 4 0x73fa8878 0x00000000
+/* DRAM_DATA B1 slew rate */
+DATA 4 0x73fa8880 0x00000000
+/* DRAM_DATA B2 slew rate */
+DATA 4 0x73fa888c 0x00000000
+/* DRAM_DATA B3 slew rate */
+DATA 4 0x73fa889c 0x00000000
+
+/*
+ * #######################
+ * ### Configure SDRAM ###
+ * #######################
+ */
+
+/* Configure CS0 */
+/* ####################### */
+
+/* ESDCTL0: Enable controller */
+DATA 4 0x83fd9000 0x83220000
+
+/* Init DRAM on CS0 */
+/* ESDSCR: Precharge command */
+DATA 4 0x83fd9014 0x04008008
+/* ESDSCR: Refresh command */
+DATA 4 0x83fd9014 0x00008010
+/* ESDSCR: Refresh command */
+DATA 4 0x83fd9014 0x00008010
+/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
+DATA 4 0x83fd9014 0x00338018
+/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
+DATA 4 0x83fd9014 0x0020801a
+/* ESDSCR */
+DATA 4 0x83fd9014 0x00008000
+
+/* ESDSCR: EMR with full Drive strength */
+/* DATA 4 0x83fd9014 0x0000801a */
+
+/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
+DATA 4 0x83fd9000 0xC3220000
+
+/*
+ * ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+ * DATA 4 0x83fd9004 0xC33574AA
+ */
+/*
+ * micron mDDR
+ * ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ * DATA 4 0x83FD9004 0x101564a8
+ */
+/*
+ * hynix mDDR
+ * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ */
+DATA 4 0x83FD9004 0x704564a8
+
+/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
+DATA 4 0x83fd9010 0x000a1700
+
+/* Configure CS1 */
+/* ####################### */
+
+/* ESDCTL1: Enable controller */
+DATA 4 0x83fd9008 0x83220000
+
+/* Init DRAM on CS1 */
+/* ESDSCR: Precharge command */
+DATA 4 0x83fd9014 0x0400800c
+/* ESDSCR: Refresh command */
+DATA 4 0x83fd9014 0x00008014
+/* ESDSCR: Refresh command */
+DATA 4 0x83fd9014 0x00008014
+/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
+DATA 4 0x83fd9014 0x0033801c
+/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
+DATA 4 0x83fd9014 0x0020801e
+/* ESDSCR */
+DATA 4 0x83fd9014 0x00008004
+
+/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
+DATA 4 0x83fd9008 0xC3220000
+/*
+ * ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+ * DATA 4 0x83fd900c 0xC33574AA
+ */
+/*
+ * micron mDDR
+ * ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ * DATA 4 0x83FD900C 0x101564a8
+ */
+/*
+ * hynix mDDR
+ * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
+ * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
+ */
+DATA 4 0x83FD900C 0x704564a8
+
+/* ESDSCR (mDRAM configuration finished) */
+DATA 4 0x83FD9014 0x00000004
+
+/* ESDSCR - clear "configuration request" bit */
+DATA 4 0x83fd9014 0x00000000
diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
new file mode 100644
index 0000000..247991d
--- /dev/null
+++ b/board/ttcontrol/vision2/vision2.c
@@ -0,0 +1,572 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx51.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/spi.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <power/pmic.h>
+#include <fsl_esdhc.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <linux/fb.h>
+
+#include <ipu_pixfmt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct fb_videomode const nec_nl6448bc26_09c = {
+ "NEC_NL6448BC26-09C",
+ 60, /* Refresh */
+ 640, /* xres */
+ 480, /* yres */
+ 37650, /* pixclock = 26.56Mhz */
+ 48, /* left margin */
+ 16, /* right margin */
+ 31, /* upper margin */
+ 12, /* lower margin */
+ 96, /* hsync-len */
+ 2, /* vsync-len */
+ 0, /* sync */
+ FB_VMODE_NONINTERLACED, /* vmode */
+ 0, /* flag */
+};
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+void hw_watchdog_reset(void)
+{
+ int val;
+
+ /* toggle watchdog trigger pin */
+ val = gpio_get_value(IMX_GPIO_NR(3, 2));
+ val = val ? 0 : 1;
+ gpio_set_value(IMX_GPIO_NR(3, 2), val);
+}
+#endif
+
+static void init_drive_strength(void)
+{
+ static const iomux_v3_cfg_t ddr_pads[] = {
+ NEW_PAD_CTRL(MX51_GRP_PKEDDR, 0),
+ NEW_PAD_CTRL(MX51_GRP_PKEADDR, PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX51_GRP_DDRAPKS, 0),
+ NEW_PAD_CTRL(MX51_GRP_DDRAPUS, PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX51_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_GRP_DDR_A0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX51_GRP_DDR_A1, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_RAS__DRAM_RAS,
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_CAS__DRAM_CAS,
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_GRP_PKEDDR, PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX51_GRP_DDRPKS, 0),
+ NEW_PAD_CTRL(MX51_GRP_HYSDDR0, 0),
+ NEW_PAD_CTRL(MX51_GRP_HYSDDR1, 0),
+ NEW_PAD_CTRL(MX51_GRP_HYSDDR2, 0),
+ NEW_PAD_CTRL(MX51_GRP_HYSDDR3, 0),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B0, PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B1, PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B2, PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_SR_B4, PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_GRP_DDRPUS, PAD_CTL_PUS_100K_UP),
+ NEW_PAD_CTRL(MX51_GRP_INMODE1, 0),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_B0, PAD_CTL_DSE_MED),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_B1, PAD_CTL_DSE_MED),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_B2, PAD_CTL_DSE_MED),
+ NEW_PAD_CTRL(MX51_GRP_DRAM_B4, PAD_CTL_DSE_MED),
+
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDWE__DRAM_SDWE, MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDCLK__DRAM_SDCLK,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS0__DRAM_SDQS0,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS1__DRAM_SDQS1,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS2__DRAM_SDQS2,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_SDQS3__DRAM_SDQS3,
+ MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_CS0__DRAM_CS0, MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_CS1__DRAM_CS1, MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_DQM0__DRAM_DQM0, MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_DQM1__DRAM_DQM1, MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_DQM2__DRAM_DQM2, MX51_GPIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX51_PAD_DRAM_DQM3__DRAM_DQM3, MX51_GPIO_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+static void setup_weim(void)
+{
+ struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
+
+ pweim->cs0gcr1 = 0x004100b9;
+ pweim->cs0gcr2 = 0x00000001;
+ pweim->cs0rcr1 = 0x0a018000;
+ pweim->cs0rcr2 = 0;
+ pweim->cs0wcr1 = 0x0704a240;
+}
+
+static void setup_uart(void)
+{
+ static const iomux_v3_cfg_t uart_pads[] = {
+ MX51_PAD_EIM_D25__UART3_RXD, /* console RX */
+ MX51_PAD_EIM_D26__UART3_TXD, /* console TX */
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == 0 && cs == 1) ? 121 : -1;
+}
+
+void spi_io_init(void)
+{
+ static const iomux_v3_cfg_t spi_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_SS0__ECSPI1_SS0, PAD_CTL_HYS |
+ PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1, PAD_CTL_HYS |
+ PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_DI1_PIN11__ECSPI1_SS2, PAD_CTL_HYS |
+ PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
+}
+
+static void reset_peripherals(int reset)
+{
+#ifdef CONFIG_VISION2_HW_1_0
+ static const iomux_v3_cfg_t fec_cfg_pads[] = {
+ /* RXD1 */
+ NEW_PAD_CTRL(MX51_PAD_EIM_EB3__GPIO2_23, NO_PAD_CTRL),
+ /* RXD2 */
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS2__GPIO2_27, NO_PAD_CTRL),
+ /* RXD3 */
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS3__GPIO2_28, NO_PAD_CTRL),
+ /* RXER */
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS4__GPIO2_29, NO_PAD_CTRL),
+ /* COL */
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__GPIO3_10, NO_PAD_CTRL),
+ /* RCLK */
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__GPIO3_11, NO_PAD_CTRL),
+ /* RXD0 */
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, NO_PAD_CTRL),
+ };
+
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
+ MX51_PAD_NANDF_D9__FEC_RDATA0,
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
+ MX51_PAD_EIM_CS4__FEC_RX_ER,
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
+ };
+#endif
+
+ if (reset) {
+
+ /* reset_n is on NANDF_D15 */
+ gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
+
+#ifdef CONFIG_VISION2_HW_1_0
+ /*
+ * set FEC Configuration lines
+ * set levels of FEC config lines
+ */
+ gpio_direction_output(IMX_GPIO_NR(3, 11), 0);
+ gpio_direction_output(IMX_GPIO_NR(3, 10), 1);
+ gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
+
+ /* set direction of FEC config lines */
+ gpio_direction_output(IMX_GPIO_NR(2, 27), 0);
+ gpio_direction_output(IMX_GPIO_NR(2, 28), 0);
+ gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
+ gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
+
+ imx_iomux_v3_setup_multiple_pads(fec_cfg_pads,
+ ARRAY_SIZE(fec_cfg_pads));
+#endif
+
+ /* activate reset_n pin */
+ imx_iomux_v3_setup_pad(
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D15__GPIO3_25,
+ PAD_CTL_DSE_MAX));
+ } else {
+ /* set FEC Control lines */
+ gpio_direction_input(IMX_GPIO_NR(3, 25));
+ udelay(500);
+
+#ifdef CONFIG_VISION2_HW_1_0
+ imx_iomux_v3_setup_multiple_pads(fec_pads,
+ ARRAY_SIZE(fec_pads));
+#endif
+ }
+}
+
+static void power_init_mx51(void)
+{
+ unsigned int val;
+ struct pmic *p;
+ int ret;
+
+ ret = pmic_init(I2C_PMIC);
+ if (ret)
+ return;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return;
+
+ /* Write needed to Power Gate 2 register */
+ pmic_reg_read(p, REG_POWER_MISC, &val);
+
+ /* enable VCAM with 2.775V to enable read from PMIC */
+ val = VCAMCONFIG | VCAMEN;
+ pmic_reg_write(p, REG_MODE_1, val);
+
+ /*
+ * Set switchers in Auto in NORMAL mode & STANDBY mode
+ * Setup the switcher mode for SW1 & SW2
+ */
+ pmic_reg_read(p, REG_SW_4, &val);
+ val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+ pmic_reg_write(p, REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ pmic_reg_read(p, REG_SW_5, &val);
+ val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
+ (SWMODE_MASK << SWMODE3_SHIFT));
+ val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
+ pmic_reg_write(p, REG_SW_5, val);
+
+
+ /* Set VGEN3 to 1.8V, VCAM to 3.0V */
+ pmic_reg_read(p, REG_SETTING_0, &val);
+ val &= ~(VCAM_MASK | VGEN3_MASK);
+ val |= VCAM_3_0;
+ pmic_reg_write(p, REG_SETTING_0, val);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
+ pmic_reg_read(p, REG_SETTING_1, &val);
+ val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+ val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
+ pmic_reg_write(p, REG_SETTING_1, val);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = VGEN3CONFIG | VCAMCONFIG;
+ pmic_reg_write(p, REG_MODE_1, val);
+ udelay(200);
+
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+ VVIDEOEN | VAUDIOEN | VSDEN;
+ pmic_reg_write(p, REG_MODE_1, val);
+
+ pmic_reg_read(p, REG_POWER_CTL2, &val);
+ val |= WDIRESET;
+ pmic_reg_write(p, REG_POWER_CTL2, val);
+
+ udelay(2500);
+
+}
+#endif
+
+static void setup_gpios(void)
+{
+ static const iomux_v3_cfg_t gpio_pads_1[] = {
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* CAM_SUP_DISn */
+ NEW_PAD_CTRL(MX51_PAD_DI1_PIN12__GPIO3_1, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* DAB Display EN */
+ NEW_PAD_CTRL(MX51_PAD_DI1_PIN13__GPIO3_2, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* WDOG_TRIGGER */
+ };
+
+ static const iomux_v3_cfg_t gpio_pads_2[] = {
+ NEW_PAD_CTRL(MX51_PAD_DI1_D0_CS__GPIO3_3, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* Display2 TxEN */
+ NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* DAB Light EN */
+ NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIN__GPIO3_5, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* AUDIO_MUTE */
+ NEW_PAD_CTRL(MX51_PAD_DISPB2_SER_DIO__GPIO3_6, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* SPARE_OUT */
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D14__GPIO3_26, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* BEEPER_EN */
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D13__GPIO3_27, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* POWER_OFF */
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D10__GPIO3_30, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* FRAM_WE */
+ NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__GPIO4_26, PAD_CTL_PKE |
+ PAD_CTL_DSE_MED), /* EXPANSION_EN */
+ MX51_PAD_GPIO1_2__PWM1_PWMO,
+ };
+
+ unsigned int i;
+
+ imx_iomux_v3_setup_multiple_pads(gpio_pads_1, ARRAY_SIZE(gpio_pads_1));
+
+ /* Now we need to trigger the watchdog */
+ WATCHDOG_RESET();
+
+ imx_iomux_v3_setup_multiple_pads(gpio_pads_2, ARRAY_SIZE(gpio_pads_2));
+
+ /*
+ * Set GPIO1_4 to high and output; it is used to reset
+ * the system on reboot
+ */
+ gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
+
+ gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
+ for (i = IMX_GPIO_NR(3, 1); i < IMX_GPIO_NR(3, 7); i++)
+ gpio_direction_output(i, 0);
+
+ gpio_direction_output(IMX_GPIO_NR(3, 30), 0);
+
+ /* Set POWER_OFF high */
+ gpio_direction_output(IMX_GPIO_NR(3, 27), 1);
+
+ gpio_direction_output(IMX_GPIO_NR(3, 26), 0);
+
+ gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
+
+ gpio_direction_output(IMX_GPIO_NR(4, 25), 1);
+
+ WATCHDOG_RESET();
+}
+
+static void setup_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
+ MX51_PAD_NANDF_CS3__FEC_MDC,
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
+ NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
+ MX51_PAD_NANDF_D9__FEC_RDATA0,
+ MX51_PAD_NANDF_CS6__FEC_TDATA3,
+ MX51_PAD_NANDF_CS5__FEC_TDATA2,
+ MX51_PAD_NANDF_CS4__FEC_TDATA1,
+ MX51_PAD_NANDF_D8__FEC_TDATA0,
+ MX51_PAD_NANDF_CS7__FEC_TX_EN,
+ MX51_PAD_NANDF_CS2__FEC_TX_ER,
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
+ NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
+ MX51_PAD_EIM_CS5__FEC_CRS,
+ MX51_PAD_EIM_CS4__FEC_RX_ER,
+ NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+ {MMC_SDHC1_BASE_ADDR},
+};
+
+int get_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+ *cd = gpio_get_value(IMX_GPIO_NR(1, 0));
+ else
+ *cd = 0;
+
+ return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
+ PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
+ NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+
+ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
+void lcd_enable(void)
+{
+ static const iomux_v3_cfg_t lcd_pads[] = {
+ MX51_PAD_DI1_PIN2__DI1_PIN2,
+ MX51_PAD_DI1_PIN3__DI1_PIN3,
+ };
+
+ int ret;
+
+ imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+ gpio_set_value(IMX_GPIO_NR(1, 2), 1);
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_2__GPIO1_2,
+ NO_PAD_CTRL));
+
+ ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
+ if (ret)
+ puts("LCD cannot be configured\n");
+}
+
+int board_early_init_f(void)
+{
+
+
+ init_drive_strength();
+
+ /* Setup debug led */
+ gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
+ imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
+ PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST));
+
+ /* wait a little while to give the pll time to settle */
+ sdelay(100000);
+
+ setup_weim();
+ setup_uart();
+ setup_fec();
+ setup_gpios();
+
+ spi_io_init();
+
+ return 0;
+}
+
+static void backlight(int on)
+{
+ if (on) {
+ gpio_set_value(IMX_GPIO_NR(3, 1), 1);
+ udelay(10000);
+ gpio_set_value(IMX_GPIO_NR(3, 4), 1);
+ } else {
+ gpio_set_value(IMX_GPIO_NR(3, 1), 0);
+ gpio_set_value(IMX_GPIO_NR(3, 4), 0);
+ }
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ lcd_enable();
+
+ backlight(1);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ power_init_mx51();
+
+ reset_peripherals(1);
+ udelay(2000);
+ reset_peripherals(0);
+ udelay(2000);
+
+ /* Early revisions require a second reset */
+#ifdef CONFIG_VISION2_HW_1_0
+ reset_peripherals(1);
+ udelay(2000);
+ reset_peripherals(0);
+ udelay(2000);
+#endif
+
+ return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int checkboard(void)
+{
+ puts("Board: TTControl Vision II CPU V\n");
+
+ return 0;
+}
+
+int do_vision_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int on;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ on = (strcmp(argv[1], "on") == 0);
+ backlight(on);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ lcdbl, CONFIG_SYS_MAXARGS, 1, do_vision_lcd,
+ "Vision2 Backlight",
+ "lcdbl [on|off]\n"
+);
diff --git a/board/udoo/1066mhz_4x256mx16.cfg b/board/udoo/1066mhz_4x256mx16.cfg
new file mode 100644
index 0000000..1ac0aec
--- /dev/null
+++ b/board/udoo/1066mhz_4x256mx16.cfg
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x54597955
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+
+DATA 4, MX6_MMDC_P0_MDOR, 0x00591023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
+
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43510360
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0342033F
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x033F033F
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03290266
+
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B3E4141
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x47413B4A
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x42404843
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4C3F4C45
+
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00350035
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00010001
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00010001
+
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
diff --git a/board/udoo/Kconfig b/board/udoo/Kconfig
new file mode 100644
index 0000000..970f39f
--- /dev/null
+++ b/board/udoo/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_UDOO
+
+config SYS_BOARD
+ default "udoo"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "udoo"
+
+endif
diff --git a/board/udoo/MAINTAINERS b/board/udoo/MAINTAINERS
new file mode 100644
index 0000000..ee8b61e
--- /dev/null
+++ b/board/udoo/MAINTAINERS
@@ -0,0 +1,6 @@
+UDOO BOARD
+M: Fabio Estevam <fabio.estevam@freescale.com>
+S: Maintained
+F: board/udoo/
+F: include/configs/udoo.h
+F: configs/udoo_quad_defconfig
diff --git a/board/udoo/Makefile b/board/udoo/Makefile
new file mode 100644
index 0000000..80efada
--- /dev/null
+++ b/board/udoo/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := udoo.o
diff --git a/board/udoo/clocks.cfg b/board/udoo/clocks.cfg
new file mode 100644
index 0000000..9cd1af1
--- /dev/null
+++ b/board/udoo/clocks.cfg
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000FF
+
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
diff --git a/board/udoo/ddr-setup.cfg b/board/udoo/ddr-setup.cfg
new file mode 100644
index 0000000..78cbe17
--- /dev/null
+++ b/board/udoo/ddr-setup.cfg
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6DL ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 64 bits x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ * memory bus width: 32 bits x16/x32
+ */
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
new file mode 100644
index 0000000..e9236d4
--- /dev/null
+++ b/board/udoo/udoo.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sata.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define WDT_EN IMX_GPIO_NR(5, 4)
+#define WDT_TRG IMX_GPIO_NR(3, 19)
+
+int dram_init(void)
+{
+ gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D19__GPIO3_IO19,
+};
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ /*
+ * Bug: Apparently uDoo does not works with Gigabit switches...
+ * Limiting speed to 10/100Mbps, and setting master mode, seems to
+ * be the only way to have a successfull PHY auto negotiation.
+ * How to fix: Understand why Linux kernel do not have this issue.
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
+
+ /* control data pad skew - devaddr = 0x02, register = 0x04 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* rx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* tx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+ return 0;
+}
+
+static iomux_v3_cfg_t const enet_pads1[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* RGMII reset */
+ MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* Ethernet power supply */
+ MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 32 - 1 - (MODE0) all */
+ MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 31 - 1 - (MODE1) all */
+ MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 28 - 1 - (MODE2) all */
+ MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 27 - 1 - (MODE3) all */
+ MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+ MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads2[] = {
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+ udelay(20);
+ gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
+
+ gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
+
+ gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+ gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+ udelay(1000);
+
+ gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
+
+ /* Need 100ms delay to exit from reset. */
+ udelay(1000 * 100);
+
+ gpio_free(IMX_GPIO_NR(6, 24));
+ gpio_free(IMX_GPIO_NR(6, 25));
+ gpio_free(IMX_GPIO_NR(6, 27));
+ gpio_free(IMX_GPIO_NR(6, 28));
+ gpio_free(IMX_GPIO_NR(6, 29));
+
+ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+}
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+static void setup_iomux_wdog(void)
+{
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+ gpio_direction_output(WDT_TRG, 0);
+ gpio_direction_output(WDT_EN, 1);
+ gpio_direction_input(WDT_TRG);
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1; /* Always present */
+}
+
+int board_eth_init(bd_t *bis)
+{
+ uint32_t base = IMX_FEC_BASE;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret;
+
+ setup_iomux_enet();
+
+#ifdef CONFIG_FEC_MXC
+ bus = fec_get_miibus(base, -1);
+ if (!bus)
+ return 0;
+ /* scan phy 4,5,6,7 */
+ phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
+
+ if (!phydev) {
+ free(bus);
+ return 0;
+ }
+ printf("using phy at %d\n", phydev->addr);
+ ret = fec_probe(bis, -1, base, bus, phydev);
+ if (ret) {
+ printf("FEC MXC: %s:failed\n", __func__);
+ free(phydev);
+ free(bus);
+ }
+#endif
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg.max_bus_width = 4;
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_wdog();
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Udoo\n");
+
+ return 0;
+}
diff --git a/board/udoo/udoo.cfg b/board/udoo/udoo.cfg
new file mode 100644
index 0000000..8d7ff25
--- /dev/null
+++ b/board/udoo/udoo.cfg
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "1066mhz_4x256mx16.cfg"
+#include "clocks.cfg"
diff --git a/board/v38b/Kconfig b/board/v38b/Kconfig
new file mode 100644
index 0000000..653bfc1
--- /dev/null
+++ b/board/v38b/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_V38B
+
+config SYS_BOARD
+ default "v38b"
+
+config SYS_CONFIG_NAME
+ default "v38b"
+
+endif
diff --git a/board/v38b/MAINTAINERS b/board/v38b/MAINTAINERS
new file mode 100644
index 0000000..d1a6ae6
--- /dev/null
+++ b/board/v38b/MAINTAINERS
@@ -0,0 +1,6 @@
+V38B BOARD
+#M: -
+S: Maintained
+F: board/v38b/
+F: include/configs/v38b.h
+F: configs/v38b_defconfig
diff --git a/board/v38b/Makefile b/board/v38b/Makefile
new file mode 100644
index 0000000..a20a5ef
--- /dev/null
+++ b/board/v38b/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := v38b.o ethaddr.o
diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c
new file mode 100644
index 0000000..982998f
--- /dev/null
+++ b/board/v38b/ethaddr.c
@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+/* For the V38B board the pin is GPIO_PSC_6 */
+#define GPIO_PIN GPIO_PSC6_0
+
+#define NO_ERROR 0
+#define ERR_NO_NUMBER 1
+#define ERR_BAD_NUMBER 2
+
+static int is_high(void);
+static int check_device(void);
+static void io_out(int value);
+static void io_input(void);
+static void io_output(void);
+static void init_gpio(void);
+static void read_byte(unsigned char *data);
+static void write_byte(unsigned char command);
+
+void read_2501_memory(unsigned char *psernum, unsigned char *perr);
+void board_get_enetaddr(uchar *enetaddr);
+
+
+static int is_high()
+{
+ return (*((vu_long *) MPC5XXX_WU_GPIO_DATA_I) & GPIO_PIN);
+}
+
+static void io_out(int value)
+{
+ if (value)
+ *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) |= GPIO_PIN;
+ else
+ *((vu_long *) MPC5XXX_WU_GPIO_DATA_O) &= ~GPIO_PIN;
+}
+
+static void io_input()
+{
+ *((vu_long *) MPC5XXX_WU_GPIO_DIR) &= ~GPIO_PIN;
+ udelay(3); /* allow input to settle */
+}
+
+static void io_output()
+{
+ *((vu_long *) MPC5XXX_WU_GPIO_DIR) |= GPIO_PIN;
+}
+
+static void init_gpio()
+{
+ *((vu_long *) MPC5XXX_WU_GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */
+}
+
+void read_2501_memory(unsigned char *psernum, unsigned char *perr)
+{
+#define NBYTES 28
+ unsigned char crcval, i;
+ unsigned char buf[NBYTES];
+
+ *perr = 0;
+ crcval = 0;
+
+ for (i = 0; i < NBYTES; i++)
+ buf[i] = 0;
+
+ if (!check_device())
+ *perr = ERR_NO_NUMBER;
+ else {
+ *perr = NO_ERROR;
+ write_byte(0xCC); /* skip ROM (0xCC) */
+ write_byte(0xF0); /* Read memory command 0xF0 */
+ write_byte(0x00); /* Address TA1=0, TA2=0 */
+ write_byte(0x00);
+ read_byte(&crcval); /* Read CRC of address and command */
+
+ for (i = 0; i < NBYTES; i++)
+ read_byte(&buf[i]);
+ }
+ if (strncmp((const char *) &buf[11], "MAREL IEEE 802.3", 16)) {
+ *perr = ERR_BAD_NUMBER;
+ psernum[0] = 0x00;
+ psernum[1] = 0xE0;
+ psernum[2] = 0xEE;
+ psernum[3] = 0xFF;
+ psernum[4] = 0xFF;
+ psernum[5] = 0xFF;
+ } else {
+ psernum[0] = 0x00;
+ psernum[1] = 0xE0;
+ psernum[2] = 0xEE;
+ psernum[3] = buf[7];
+ psernum[4] = buf[6];
+ psernum[5] = buf[5];
+ }
+}
+
+static int check_device()
+{
+ int found;
+
+ io_output();
+ io_out(0);
+ udelay(500); /* must be at least 480 us low pulse */
+
+ io_input();
+ udelay(60);
+
+ found = (is_high() == 0) ? 1 : 0;
+ udelay(500); /* must be at least 480 us low pulse */
+
+ return found;
+}
+
+static void write_byte(unsigned char command)
+{
+ char i;
+
+ for (i = 0; i < 8; i++) {
+ /* 1 us to 15 us low pulse starts bit slot */
+ /* Start with high pulse for 3 us */
+ io_input();
+ udelay(3);
+
+ io_out(0);
+ io_output();
+ udelay(3);
+
+ if (command & 0x01) {
+ /* 60 us high for 1-bit */
+ io_input();
+ udelay(60);
+ } else
+ /* 60 us low for 0-bit */
+ udelay(60);
+ /* Leave pin as input */
+ io_input();
+
+ command = command >> 1;
+ }
+}
+
+static void read_byte(unsigned char *data)
+{
+ unsigned char i, rdat = 0;
+
+ for (i = 0; i < 8; i++) {
+ /* read one bit from one-wire device */
+
+ /* 1 - 15 us low starts bit slot */
+ io_out(0);
+ io_output();
+ udelay(0);
+
+ /* allow line to be pulled high */
+ io_input();
+
+ /* delay 10 us */
+ udelay(10);
+
+ /* now sample input status */
+ if (is_high())
+ rdat = (rdat >> 1) | 0x80;
+ else
+ rdat = rdat >> 1;
+
+ udelay(60); /* at least 60 us */
+ }
+ /* copy the return value */
+ *data = rdat;
+}
+
+void board_get_enetaddr(uchar *enetaddr)
+{
+ unsigned char sn[6], err = NO_ERROR;
+
+ init_gpio();
+
+ read_2501_memory(sn, &err);
+
+ if (err == NO_ERROR) {
+ sprintf((char *)enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
+ sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]);
+ printf("MAC address: %s\n", enetaddr);
+ setenv("ethaddr", (char *)enetaddr);
+ } else {
+ sprintf((char *)enetaddr, "00:01:02:03:04:05");
+ printf("Error reading MAC address.\n");
+ printf("Setting default to %s\n", enetaddr);
+ setenv("ethaddr", (char *)enetaddr);
+ }
+}
diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c
new file mode 100644
index 0000000..a337729
--- /dev/null
+++ b/board/v38b/v38b.c
@@ -0,0 +1,260 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <net.h>
+#include <asm/processor.h>
+
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set mode register: extended mode */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+ __asm__ volatile ("sync");
+
+ /* set mode register: reset DLL */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+ __asm__ volatile ("sync");
+#endif /* SDRAM_DDR */
+
+ /* precharge all banks */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+ __asm__ volatile ("sync");
+}
+#endif /* !CONFIG_SYS_RAMBOOT */
+
+
+phys_size_t initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+#if SDRAM_DDR
+ /* set tap delay */
+ *(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+ __asm__ volatile ("sync");
+#endif /* SDRAM_DDR */
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else
+ dramsize = test2;
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0)
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ else
+ *(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+ /* find RAM size using SDRAM CS1 only */
+ if (!dramsize)
+ sdram_start(0);
+ test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ if (!dramsize) {
+ sdram_start(1);
+ test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+ }
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize2 = test1;
+ } else
+ dramsize2 = test2;
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20))
+ dramsize2 = 0;
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0)
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
+ | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+ else
+ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13)
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ else
+ dramsize = 0;
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ if (dramsize2 >= 0x13)
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ else
+ dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ *(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+ }
+
+ return dramsize + dramsize2;
+}
+
+
+int checkboard (void)
+{
+ puts("Board: MarelV38B\n");
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+ /*
+ * Enable and configure the direction (output) of PSC3_9 - watchdog
+ * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
+ * Manual.
+ */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
+#endif /* CONFIG_HW_WATCHDOG */
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write access for the
+ * detection process. Note that CS_BOOT cannot be cleared when
+ * executing in flash.
+ */
+ *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+
+ /*
+ * Enable GPIO_WKUP_7 to "read the status of the actual power
+ * situation". Default direction is input, so no need to set it
+ * explicitly.
+ */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
+ return 0;
+}
+
+extern void board_get_enetaddr(uchar *enetaddr);
+int misc_init_r(void)
+{
+ uchar enetaddr[6];
+
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ board_get_enetaddr(enetaddr);
+ eth_setenv_enetaddr("ethaddr", enetaddr);
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+void init_ide_reset(void)
+{
+ debug("init_ide_reset\n");
+
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+ /* Deassert reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+}
+
+
+void ide_set_reset(int idereset)
+{
+ debug("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+ /* Make a delay. MPC5200 spec says 25 usec min */
+ udelay(500000);
+ } else
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+}
+#endif
+
+
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ /*
+ * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
+ * we need a positive or negative transition on WDI i.e., our PSC3_9.
+ */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
+}
+#endif /* CONFIG_HW_WATCHDOG */
diff --git a/board/ve8313/Kconfig b/board/ve8313/Kconfig
new file mode 100644
index 0000000..a63744b
--- /dev/null
+++ b/board/ve8313/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_VE8313
+
+config SYS_BOARD
+ default "ve8313"
+
+config SYS_CONFIG_NAME
+ default "ve8313"
+
+endif
diff --git a/board/ve8313/MAINTAINERS b/board/ve8313/MAINTAINERS
new file mode 100644
index 0000000..e3ca332
--- /dev/null
+++ b/board/ve8313/MAINTAINERS
@@ -0,0 +1,6 @@
+VE8313 BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: board/ve8313/
+F: include/configs/ve8313.h
+F: configs/ve8313_defconfig
diff --git a/board/ve8313/Makefile b/board/ve8313/Makefile
new file mode 100644
index 0000000..41258f9
--- /dev/null
+++ b/board/ve8313/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ve8313.o
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
new file mode 100644
index 0000000..7f24a30
--- /dev/null
+++ b/board/ve8313/ve8313.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <ns16550.h>
+#include <nand.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void disable_addr_trans (void);
+extern void enable_addr_trans (void);
+
+int checkboard(void)
+{
+ puts("Board: ve8313\n");
+ return 0;
+}
+
+static long fixed_sdram(void)
+{
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+
+#ifndef CONFIG_SYS_RAMBOOT
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ u32 msize_log2 = __ilog2(msize);
+
+ out_be32(&im->sysconf.ddrlaw[0].bar,
+ (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+ out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
+ out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+ /*
+ * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+ * or the DDR2 controller may fail to initialize correctly.
+ */
+ __udelay(50000);
+
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+ out_be32(&im->ddr.csbnds[0].csbnds,
+ ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+ (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
+ CSBNDS_EA));
+ out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+ /* Currently we use only one CS, so disable the other bank. */
+ out_be32(&im->ddr.cs_config[1], 0);
+
+ out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+ out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+ out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
+
+ out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+ out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
+
+ out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+ sync();
+
+ /* enable DDR controller */
+ setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+
+ /* now check the real size */
+ disable_addr_trans ();
+ msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
+ enable_addr_trans ();
+#endif
+
+ return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile fsl_lbc_t *lbc = &im->im_lbc;
+ u32 msize;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+ return -1;
+
+ /* DDR SDRAM - Main SODIMM */
+ msize = fixed_sdram();
+
+ /* Local Bus setup lbcr and mrtpr */
+ out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+ out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+ sync();
+
+ /* return total bus SDRAM size(bytes) -- DDR */
+ return msize;
+}
+
+#define VE8313_WDT_EN 0x00020000
+#define VE8313_WDT_TRIG 0x00040000
+
+int board_early_init_f (void)
+{
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
+
+#if defined(CONFIG_HW_WATCHDOG)
+ /* enable WDT */
+ clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
+#else
+ /* disable WDT */
+ setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
+#endif
+ /* set WDT pins as output */
+ setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
+
+ return 0;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
+ unsigned long reg;
+
+ reg = in_be32(&gpio->dat);
+ if (reg & VE8313_WDT_TRIG)
+ clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
+ else
+ setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
+}
+#endif
+
+
+#if defined(CONFIG_PCI)
+static struct pci_region pci_regions[] = {
+ {
+ bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+ phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+ size: CONFIG_SYS_PCI1_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+ phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+ size: CONFIG_SYS_PCI1_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+ {
+ bus_start: CONFIG_SYS_PCI1_IO_BASE,
+ phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+ size: CONFIG_SYS_PCI1_IO_SIZE,
+ flags: PCI_REGION_IO
+ }
+};
+
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci_regions };
+
+ /* Enable all 3 PCI_CLK_OUTPUTs. */
+ setbits_be32(&clk->occr, 0xe0000000);
+
+ /*
+ * Configure PCI Local Access Windows
+ */
+ out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
+ out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+ out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
+ out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
+
+ mpc83xx_pci_init(1, reg);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+
+ return 0;
+}
+#endif
diff --git a/board/vpac270/Kconfig b/board/vpac270/Kconfig
new file mode 100644
index 0000000..1701b35
--- /dev/null
+++ b/board/vpac270/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_VPAC270
+
+config SYS_BOARD
+ default "vpac270"
+
+config SYS_CONFIG_NAME
+ default "vpac270"
+
+endif
diff --git a/board/vpac270/MAINTAINERS b/board/vpac270/MAINTAINERS
new file mode 100644
index 0000000..1c62765
--- /dev/null
+++ b/board/vpac270/MAINTAINERS
@@ -0,0 +1,8 @@
+VPAC270 BOARD
+M: Marek Vasut <marek.vasut@gmail.com>
+S: Maintained
+F: board/vpac270/
+F: include/configs/vpac270.h
+F: configs/vpac270_nor_128_defconfig
+F: configs/vpac270_nor_256_defconfig
+F: configs/vpac270_ond_256_defconfig
diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile
new file mode 100644
index 0000000..ad7f7d8
--- /dev/null
+++ b/board/vpac270/Makefile
@@ -0,0 +1,13 @@
+#
+# Voipac PXA270 Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y := vpac270.o
+else
+obj-y := onenand.o
+endif
diff --git a/board/vpac270/onenand.c b/board/vpac270/onenand.c
new file mode 100644
index 0000000..a749b31
--- /dev/null
+++ b/board/vpac270/onenand.c
@@ -0,0 +1,46 @@
+/*
+ * Voipac PXA270 OneNAND SPL
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <onenand_uboot.h>
+#include <asm/arch/pxa.h>
+
+void board_init_f(unsigned long unused)
+{
+ extern uint32_t _end;
+ uint32_t tmp;
+
+ asm volatile("mov %0, pc" : "=r"(tmp));
+ tmp >>= 24;
+
+ /* The code runs from OneNAND RAM, copy SPL to SRAM and execute it. */
+ if (tmp == 0) {
+ tmp = (uint32_t)&_end - CONFIG_SPL_TEXT_BASE;
+ onenand_spl_load_image(0, tmp, (void *)CONFIG_SPL_TEXT_BASE);
+ asm volatile("mov pc, %0" : : "r"(CONFIG_SPL_TEXT_BASE));
+ }
+
+ /* Hereby, the code runs from (S)RAM, copy U-Boot and execute it. */
+ arch_cpu_init();
+ pxa2xx_dram_init();
+ onenand_spl_load_image(CONFIG_SPL_ONENAND_LOAD_ADDR,
+ CONFIG_SPL_ONENAND_LOAD_SIZE,
+ (void *)CONFIG_SYS_TEXT_BASE);
+ asm volatile("mov pc, %0" : : "r"(CONFIG_SYS_TEXT_BASE));
+
+ for (;;)
+ ;
+}
+
+void __attribute__((noreturn)) hang(void)
+{
+ for (;;)
+ ;
+}
diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds
new file mode 100644
index 0000000..a10ea71
--- /dev/null
+++ b/board/vpac270/u-boot-spl.lds
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = CONFIG_SPL_TEXT_BASE;
+ .text.0 :
+ {
+ *(.vectors)
+ arch/arm/cpu/pxa/start.o (.text*)
+ arch/arm/lib/built-in.o (.text*)
+ board/vpac270/built-in.o (.text*)
+ drivers/mtd/onenand/built-in.o (.text*)
+ }
+
+
+ /* Start of the rest of the SPL */
+ . = CONFIG_SPL_TEXT_BASE + 0x800;
+
+ .text.1 :
+ {
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ __image_copy_end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ . = ALIGN(0x800);
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ _image_binary_end = .;
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ }
+
+ .dynsym _image_binary_end : { *(.dynsym) }
+ .dynbss : { *(.dynbss) }
+ .dynstr : { *(.dynstr*) }
+ .dynamic : { *(.dynamic*) }
+ .hash : { *(.hash*) }
+ .plt : { *(.plt*) }
+ .interp : { *(.interp*) }
+ .gnu : { *(.gnu*) }
+ .ARM.exidx : { *(.ARM.exidx*) }
+}
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
new file mode 100644
index 0000000..8d777df
--- /dev/null
+++ b/board/vpac270/vpac270.c
@@ -0,0 +1,126 @@
+/*
+ * Voipac PXA270 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/regs-mmc.h>
+#include <asm/arch/pxa.h>
+#include <netdev.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* Arch number of vpac270 */
+ gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+#ifndef CONFIG_ONENAND
+ pxa2xx_dram_init();
+#endif
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+#ifdef CONFIG_RAM_256M
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+int board_usb_init(int index, enum usb_init_type init)
+{
+ writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
+
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
+
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+ /* Clear any OTG Pin Hold */
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+ /* Set port power control mask bits, only 3 ports. */
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+ /* enable port 2 */
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+
+void usb_board_stop(void)
+{
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+ udelay(11);
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
+ udelay(10);
+
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+ return;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+int board_eth_init(bd_t *bis)
+{
+ return dm9000_initialize(bis);
+}
+#endif
diff --git a/board/w7o/Kconfig b/board/w7o/Kconfig
new file mode 100644
index 0000000..fd1b422
--- /dev/null
+++ b/board/w7o/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_W7OLMC
+
+config SYS_BOARD
+ default "w7o"
+
+config SYS_CONFIG_NAME
+ default "W7OLMC"
+
+endif
+
+if TARGET_W7OLMG
+
+config SYS_BOARD
+ default "w7o"
+
+config SYS_CONFIG_NAME
+ default "W7OLMG"
+
+endif
diff --git a/board/w7o/MAINTAINERS b/board/w7o/MAINTAINERS
new file mode 100644
index 0000000..bfedee5
--- /dev/null
+++ b/board/w7o/MAINTAINERS
@@ -0,0 +1,8 @@
+W7O BOARD
+M: Erik Theisen <etheisen@mindspring.com>
+S: Maintained
+F: board/w7o/
+F: include/configs/W7OLMC.h
+F: configs/W7OLMC_defconfig
+F: include/configs/W7OLMG.h
+F: configs/W7OLMG_defconfig
diff --git a/board/w7o/Makefile b/board/w7o/Makefile
new file mode 100644
index 0000000..955de50
--- /dev/null
+++ b/board/w7o/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2001
+# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = w7o.o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \
+ watchdog.o
+obj-y += init.o post1.o
diff --git a/board/w7o/cmd_vpd.c b/board/w7o/cmd_vpd.c
new file mode 100644
index 0000000..879cb61
--- /dev/null
+++ b/board/w7o/cmd_vpd.c
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+
+#if defined(CONFIG_CMD_BSP)
+
+#include "vpd.h"
+
+/* ======================================================================
+ * Interpreter command to retrieve board specific Vital Product Data, "VPD"
+ * ======================================================================
+ */
+int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ VPD vpd; /* Board specific data struct */
+ uchar dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
+
+ /* Validate usage */
+ if (argc > 2)
+ return cmd_usage(cmdtp);
+
+ /* Passed in EEPROM address */
+ if (argc == 2)
+ dev_addr = (uchar) simple_strtoul (argv[1], NULL, 16);
+
+ /* Read VPD and output it */
+ if (!vpd_get_data (dev_addr, &vpd)) {
+ vpd_print (&vpd);
+ return 0;
+ }
+
+ return 1;
+}
+
+U_BOOT_CMD(
+ vpd, 2, 1, do_vpd,
+ "Read Vital Product Data",
+ "[dev_addr]\n"
+ " - Read VPD Data from default address, or device address 'dev_addr'."
+);
+
+#endif
diff --git a/board/w7o/errors.h b/board/w7o/errors.h
new file mode 100644
index 0000000..05540fb
--- /dev/null
+++ b/board/w7o/errors.h
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ERRORS_H_
+#define _ERRORS_H_
+
+#define ERR_FF -1 /* led test value(2) */
+#define ERR_00 0x0000 /* led test value(2) */
+#define ERR_LED 0x01 /* led test failed (1)(3)(4) */
+#define ERR_RAMG 0x04 /* start SDRAM data bus test (2) */
+#define ERR_RAML 0x05 /* SDRAM data bus fault in LSW chip (5) */
+#define ERR_RAMH 0x06 /* SDRAM data bus fault in MSW chip (6) */
+#define ERR_RAMB 0x07 /* SDRAM data bus fault both chips (5)(6)(7) */
+#define ERR_ADDG 0x08 /* start Address ghosting test (13) */
+#define ERR_ADDF 0x09 /* fault during Address ghosting test (13) */
+#define ERR_POST1 0x0a /* post1 tests complete */
+#define ERR_TMP1 0x0b /* */
+#define ERR_R55G 0x0c /* start SDRAM fill 55 test (2) */
+#define ERR_R55L 0x0d /* SDRAM fill test 55 failed in LSW chip (8) */
+#define ERR_R55H 0x0e /* SDRAM fill test 55 failed in MSW chip (9) */
+#define ERR_R55B 0x0f /* SDRAM fill test 55 fail in both chips (10) */
+#define ERR_RAAG 0x10 /* start SDRAM fill aa test (2) */
+#define ERR_RAAL 0x11 /* SDRAM fill test aa failed in LSW chip (8) */
+#define ERR_RAAH 0x12 /* SDRAM fill test aa failed in MSW chip (9) */
+#define ERR_RAAB 0x13 /* SDRAM fill test aa fail in both chips (10) */
+#define ERR_R00G 0x14 /* start SDRAM fill 00 test (2) */
+#define ERR_R00L 0x15 /* SDRAM fill test 00 failed in LSW chip (8) */
+#define ERR_R00H 0x16 /* SDRAM fill test 00 failed in MSW chip (9) */
+#define ERR_R00B 0x17 /* SDRAM fill test 00 fail in both chips (10) */
+#define ERR_RTCG 0x18 /* start RTC test */
+#define ERR_RTCBAT 0x19 /* RTC battery failure */
+#define ERR_RTCTIM 0x1A /* RTC invalid time/date values */
+#define ERR_RTCVAL 0x1B /* RTC NVRAM not accessable */
+#define ERR_FPGAG 0x20 /* fault during FPGA programming */
+#define ERR_XRW1 0x21 /* Xilinx - can't read/write regs on FPGA 1 */
+#define ERR_XRW2 0x22 /* Xilinx - can't read/write regs on FPGA 2 */
+#define ERR_XRW3 0x23 /* Xilinx - can't read/write regs on FPGA 3 */
+#define ERR_XRW4 0x24 /* Xilinx - can't read/write regs on FPGA 4 */
+#define ERR_XRW5 0x25 /* Xilinx - can't read/write regs on FPGA 5 */
+#define ERR_XRW6 0x26 /* Xilinx - can't read/write regs on FPGA 6 */
+#define ERR_XINIT0 0x27 /* Xilinx - INIT line failed to go low */
+#define ERR_XINIT1 0x28 /* Xilinx - INIT line failed to go high */
+#define ERR_XDONE1 0x29 /* Xilinx - DONE line failed to go high */
+#define ERR_XIMAGE 0x2A /* Xilinx - Bad FPGA image in Flash */
+#define ERR_TempG 0x2b /* start temp sensor tests */
+#define ERR_Tinit0 0x2C /* temp sensor 0 failed to init */
+#define ERR_Tinit1 0x2D /* temp sensor 1 failed to init */
+#define ERR_Ttest0 0x2E /* temp sensor 0 failed test */
+#define ERR_Ttest1 0x2F /* temp sensor 1 failed test */
+#define ERR_lm75r 0x30 /* temp sensor read failure */
+#define ERR_lm75w 0x31 /* temp sensor write failure */
+
+
+#define ERR_POSTOK 0x55 /* PANIC: psych... OK */
+
+#if !defined(__ASSEMBLY__)
+extern void log_stat(int errcode);
+extern void log_warn(int errcode);
+extern void log_err(int errcode);
+#endif
+
+/*
+Debugging suggestions:
+(1) periferal data bus shorted or crossed
+(2) general processor halt, check reset, watch dog, power supply ripple, processor clock.
+(3) check p_we, p_r/w, p_oe, p_rdy lines.
+(4) check LED buffers
+(5) check SDRAM data bus bits 16-31, check LSW SDRAM chip.
+(6) check SDRAM data bus bits 0-15, check MSW SDRAM chip.
+(7) check SDRAM control lines and clocks
+(8) check decoupling caps, replace LSW SDRAM
+(9) check decoupling caps, replace MSW SDRAM
+(10)
+(11)
+(12)
+(13) SDRAM address shorted or unconnected, check sdram caps
+*/
+#endif /* _ERRORS_H_ */
diff --git a/board/w7o/flash.c b/board/w7o/flash.c
new file mode 100644
index 0000000..26bddc4
--- /dev/null
+++ b/board/w7o/flash.c
@@ -0,0 +1,927 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ * Based on code by:
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/ppc4xx.h>
+#include <asm/processor.h>
+
+#include <watchdog.h>
+
+/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+/*
+ * Functions
+ */
+static ulong flash_get_size(vu_long *addr, flash_info_t *info);
+static int write_word8(flash_info_t *info, ulong dest, ulong data);
+static int write_word32(flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+
+unsigned long flash_init(void)
+{
+ int i;
+ unsigned long size_b0, base_b0;
+ unsigned long size_b1;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+
+ /* Get Size of Boot and Main Flashes */
+ size_b0 = flash_get_size((vu_long *) FLASH_BASE0_PRELIM,
+ &flash_info[0]);
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 << 20);
+ return 0;
+ }
+ size_b1 =
+ flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
+ &flash_info[1]);
+ if (flash_info[1].flash_id == FLASH_UNKNOWN) {
+ printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+ size_b1, size_b1 << 20);
+ return 0;
+ }
+
+ /* Calculate base addresses */
+ base_b0 = -size_b0;
+
+ /* Setup offsets for Boot Flash */
+ flash_get_offsets(base_b0, &flash_info[0]);
+
+ /* Protect board level data */
+ (void) flash_protect(FLAG_PROTECT_SET,
+ base_b0,
+ flash_info[0].start[1] - 1, &flash_info[0]);
+
+ /* Monitor protection ON by default */
+ (void) flash_protect(FLAG_PROTECT_SET,
+ base_b0 + size_b0 - monitor_flash_len,
+ base_b0 + size_b0 - 1, &flash_info[0]);
+
+ /* Protect the FPGA image */
+ (void) flash_protect(FLAG_PROTECT_SET,
+ FLASH_BASE1_PRELIM,
+ FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN -
+ 1, &flash_info[1]);
+
+ /* Protect the default boot image */
+ (void) flash_protect(FLAG_PROTECT_SET,
+ FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN,
+ FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN +
+ 0x600000 - 1, &flash_info[1]);
+
+ /* Setup offsets for Main Flash */
+ flash_get_offsets(FLASH_BASE1_PRELIM, &flash_info[1]);
+
+ return size_b0 + size_b1;
+}
+
+static void flash_get_offsets(ulong base, flash_info_t *info)
+{
+ int i;
+
+ /* set up sector start address table - FOR BOOT ROM ONLY!!! */
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ }
+} /* end flash_get_offsets() */
+
+void flash_print_info(flash_info_t *info)
+{
+ int i;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("1 x AMD ");
+ break;
+ case FLASH_MAN_STM:
+ printf("1 x STM ");
+ break;
+ case FLASH_MAN_INTEL:
+ printf("2 x Intel ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+ printf("AM29LV040 (4096 Kbit, uniform sector size)\n");
+ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM)
+ printf("M29W040B (4096 Kbit, uniform block size)\n");
+ else
+ printf("UNKNOWN 29x040x (4096 Kbit, uniform sector size)\n");
+ break;
+ case FLASH_28F320J3A:
+ printf("28F320J3A (32 Mbit = 128K x 32)\n");
+ break;
+ case FLASH_28F640J3A:
+ printf("28F640J3A (64 Mbit = 128K x 64)\n");
+ break;
+ case FLASH_28F128J3A:
+ printf("28F128J3A (128 Mbit = 128K x 128)\n");
+ break;
+ default:
+ printf("Unknown Chip Type\n");
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) {
+ printf(" Size: %ld KB in %d Blocks\n",
+ info->size >> 10, info->sector_count);
+ } else {
+ printf(" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+ }
+
+ printf(" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count - 1))
+ size = info->start[i + 1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *) info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k = 0; k < size; k++) {
+ if (*flash++ != 0xffffffff) {
+ erased = 0;
+ break;
+ }
+ }
+
+ if ((i % 5) == 0)
+ printf("\n ");
+ printf(" %08lX%s%s",
+ info->start[i],
+ erased ? " E" : " ",
+ info->protect[i] ? "RO " : " ");
+ }
+ printf("\n");
+} /* end flash_print_info() */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size(vu_long *addr, flash_info_t *info)
+{
+ short i;
+ ulong base = (ulong) addr;
+
+ /* Setup default type */
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+
+ /* Test for Boot Flash */
+ if (base == FLASH_BASE0_PRELIM) {
+ unsigned char value;
+ volatile unsigned char *addr2 = (unsigned char *) addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ *(addr2 + 0x555) = 0xaa;
+ *(addr2 + 0x2aa) = 0x55;
+ *(addr2 + 0x555) = 0x90;
+
+ /* Manufacture ID */
+ value = *addr2;
+ switch (value) {
+ case (unsigned char) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (unsigned char) STM_MANUFACT:
+ info->flash_id = FLASH_MAN_STM;
+ break;
+ default:
+ *addr2 = 0xf0; /* no or unknown flash */
+ return 0;
+ }
+
+ /* Device ID */
+ value = *(addr2 + 1);
+ switch (value) {
+ case (unsigned char) AMD_ID_LV040B:
+ case (unsigned char) STM_ID_29W040B:
+ info->flash_id += FLASH_AM040;
+ info->sector_count = 8;
+ info->size = 0x00080000;
+ break; /* => 512Kb */
+ default:
+ *addr2 = 0xf0; /* => no or unknown flash */
+ return 0;
+ }
+ } else { /* MAIN Flash */
+ unsigned long value;
+ volatile unsigned long *addr2 = (unsigned long *) addr;
+
+ /* Write auto select command: read Manufacturer ID */
+ *addr2 = 0x90909090;
+
+ /* Manufacture ID */
+ value = *addr2;
+ switch (value) {
+ case (unsigned long) INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ *addr2 = 0xff; /* no or unknown flash */
+ return 0;
+ }
+
+ /* Device ID - This shit is interleaved... */
+ value = *(addr2 + 1);
+ switch (value) {
+ case (unsigned long) INTEL_ID_28F320J3A:
+ info->flash_id += FLASH_28F320J3A;
+ info->sector_count = 32;
+ info->size = 0x00400000 * 2;
+ break; /* => 2 X 4 MB */
+ case (unsigned long) INTEL_ID_28F640J3A:
+ info->flash_id += FLASH_28F640J3A;
+ info->sector_count = 64;
+ info->size = 0x00800000 * 2;
+ break; /* => 2 X 8 MB */
+ case (unsigned long) INTEL_ID_28F128J3A:
+ info->flash_id += FLASH_28F128J3A;
+ info->sector_count = 128;
+ info->size = 0x01000000 * 2;
+ break; /* => 2 X 16 MB */
+ default:
+ *addr2 = 0xff; /* => no or unknown flash */
+ }
+ }
+
+ /* Make sure we don't exceed CONFIG_SYS_MAX_FLASH_SECT */
+ if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+ printf("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ }
+
+ /* set up sector start address table */
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM040:
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * 0x00010000);
+ break;
+ case FLASH_28F320J3A:
+ case FLASH_28F640J3A:
+ case FLASH_28F128J3A:
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base +
+ (i * 0x00020000 * 2); /* 2 Banks */
+ break;
+ }
+
+ /* Test for Boot Flash */
+ if (base == FLASH_BASE0_PRELIM) {
+ volatile unsigned char *addr2;
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /*
+ * read sector protection at sector address,
+ * (AX .. A0) = 0x02
+ * D0 = 1 if protected
+ */
+ addr2 = (volatile unsigned char *) (info->start[i]);
+ info->protect[i] = *(addr2 + 2) & 1;
+ }
+
+ /* Restore read mode */
+ *(unsigned char *) base = 0xF0; /* Reset NORMAL Flash */
+ } else { /* Main Flash */
+ volatile unsigned long *addr2;
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /*
+ * read sector protection at sector address,
+ * (AX .. A0) = 0x02
+ * D0 = 1 if protected
+ */
+ addr2 = (volatile unsigned long *) (info->start[i]);
+ info->protect[i] = *(addr2 + 2) & 0x1;
+ }
+
+ /* Restore read mode */
+ *(unsigned long *) base = 0xFFFFFFFF; /* Reset Flash */
+ }
+
+ return info->size;
+} /* end flash_get_size() */
+
+static int wait_for_DQ7(ulong addr, uchar cmp_val, ulong tout)
+{
+ int i;
+
+ volatile uchar *vaddr = (uchar *) addr;
+
+ /* Loop X times */
+ for (i = 1; i <= (100 * tout); i++) { /* Wait up to tout ms */
+ udelay(10);
+ /* Pause 10 us */
+
+ /* Check for completion */
+ if ((vaddr[0] & 0x80) == (cmp_val & 0x80))
+ return 0;
+
+ /* KEEP THE LUSER HAPPY - Print a dot every 1.1 seconds */
+ if (!(i % 110000))
+ putc('.');
+
+ /* Kick the dog if needed */
+ WATCHDOG_RESET();
+ }
+
+ return 1;
+} /* wait_for_DQ7() */
+
+static int flash_erase8(flash_info_t *info, int s_first, int s_last)
+{
+ int tcode, rcode = 0;
+ volatile uchar *addr = (uchar *) (info->start[0]);
+ volatile uchar *sector_addr;
+ int flag, prot, sect;
+
+ /* Validate arguments */
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
+ return 1;
+ }
+
+ /* Check for KNOWN flash type */
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("Can't erase unknown flash type - aborted\n");
+ return 1;
+ }
+
+ /* Check for protected sectors */
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ sector_addr = (uchar *) (info->start[sect]);
+
+ if ((info->flash_id & FLASH_VENDMASK) ==
+ FLASH_MAN_STM)
+ printf("Erasing block %p\n", sector_addr);
+ else
+ printf("Erasing sector %p\n", sector_addr);
+
+ /* Disable interrupts which might cause timeout */
+ flag = disable_interrupts();
+
+ *(addr + 0x555) = (uchar) 0xAA;
+ *(addr + 0x2aa) = (uchar) 0x55;
+ *(addr + 0x555) = (uchar) 0x80;
+ *(addr + 0x555) = (uchar) 0xAA;
+ *(addr + 0x2aa) = (uchar) 0x55;
+ *sector_addr = (uchar) 0x30; /* sector erase */
+
+ /*
+ * Wait for each sector to complete, it's more
+ * reliable. According to AMD Spec, you must
+ * issue all erase commands within a specified
+ * timeout. This has been seen to fail, especially
+ * if printf()s are included (for debug)!!
+ * Takes up to 6 seconds.
+ */
+ tcode = wait_for_DQ7((ulong) sector_addr, 0x80, 6000);
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* Make sure we didn't timeout */
+ if (tcode) {
+ printf("Timeout\n");
+ rcode = 1;
+ }
+ }
+ }
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ /* reset to read mode */
+ addr = (uchar *) info->start[0];
+ *addr = (uchar) 0xF0; /* reset bank */
+
+ printf(" done\n");
+ return rcode;
+} /* end flash_erase8() */
+
+static int flash_erase32(flash_info_t *info, int s_first, int s_last)
+{
+ int flag, sect;
+ ulong start, now, last;
+ int prot = 0;
+
+ /* Validate arguments */
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN)
+ printf("- missing\n");
+ else
+ printf("- no sectors to erase\n");
+ return 1;
+ }
+
+ /* Check for KNOWN flash type */
+ if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+ printf("Can erase only Intel flash types - aborted\n");
+ return 1;
+ }
+
+ /* Check for protected sectors */
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect])
+ prot++;
+ }
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ start = get_timer(0);
+ last = start;
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ WATCHDOG_RESET();
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_long *addr = (vu_long *) (info->start[sect]);
+ unsigned long status;
+
+ /* Disable interrupts which might cause a timeout */
+ flag = disable_interrupts();
+
+ *addr = 0x00500050; /* clear status register */
+ *addr = 0x00200020; /* erase setup */
+ *addr = 0x00D000D0; /* erase confirm */
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* Wait at least 80us - let's wait 1 ms */
+ udelay(1000);
+
+ while (((status = *addr) & 0x00800080) != 0x00800080) {
+ now = get_timer(start);
+ if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+ /* suspend erase */
+ *addr = 0x00B000B0;
+ /* reset to read mode */
+ *addr = 0x00FF00FF;
+ return 1;
+ }
+
+ /*
+ * show that we're waiting
+ * every second (?)
+ */
+ if ((now - last) > 990) {
+ putc('.');
+ last = now;
+ }
+ }
+ *addr = 0x00FF00FF; /* reset to read mode */
+ }
+ }
+ printf(" done\n");
+ return 0;
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
+ return flash_erase8(info, s_first, s_last);
+ else
+ return flash_erase32(info, s_first, s_last);
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_buff8(flash_info_t *info, uchar *src, ulong addr,
+ ulong cnt)
+{
+ ulong cp, wp, data;
+ ulong start;
+ int i, l, rc;
+
+ start = get_timer(0);
+
+ wp = (addr & ~3); /* get lower word
+ aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ l = addr - wp;
+ if (l != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ for (; i < 4 && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+
+ for (; cnt == 0 && i < 4; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ rc = write_word8(info, wp, data);
+ if (rc != 0)
+ return rc;
+
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i = 0; i < 4; ++i)
+ data = (data << 8) | *src++;
+
+ rc = write_word8(info, wp, data);
+ if (rc != 0)
+ return rc;
+
+ wp += 4;
+ cnt -= 4;
+ if (get_timer(start) > 1000) { /* every second */
+ WATCHDOG_RESET();
+ putc('.');
+ start = get_timer(0);
+ }
+ }
+
+ if (cnt == 0)
+ return 0;
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+
+ for (; i < 4; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ return write_word8(info, wp, data);
+}
+
+#define FLASH_WIDTH 4 /* flash bus width in bytes */
+static int write_buff32(flash_info_t *info, uchar *src, ulong addr,
+ ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+ ulong start;
+
+ start = get_timer(0);
+
+ if (info->flash_id == FLASH_UNKNOWN)
+ return 4;
+
+ /* get lower FLASH_WIDTH aligned address */
+ wp = (addr & ~(FLASH_WIDTH - 1));
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ for (; i < FLASH_WIDTH && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+
+ for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ rc = write_word32(info, wp, data);
+ if (rc != 0)
+ return rc;
+
+ wp += FLASH_WIDTH;
+ }
+
+ /*
+ * handle FLASH_WIDTH aligned part
+ */
+ while (cnt >= FLASH_WIDTH) {
+ data = 0;
+ for (i = 0; i < FLASH_WIDTH; ++i)
+ data = (data << 8) | *src++;
+
+ rc = write_word32(info, wp, data);
+ if (rc != 0)
+ return rc;
+
+ wp += FLASH_WIDTH;
+ cnt -= FLASH_WIDTH;
+ if (get_timer(start) > 990) { /* every second */
+ putc('.');
+ start = get_timer(0);
+ }
+ }
+
+ if (cnt == 0)
+ return 0;
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+
+ for (; i < FLASH_WIDTH; ++i, ++cp)
+ data = (data << 8) | (*(uchar *) cp);
+
+ return write_word32(info, wp, data);
+}
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ int retval;
+
+ if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
+ retval = write_buff8(info, src, addr, cnt);
+ else
+ retval = write_buff32(info, src, addr, cnt);
+
+ return retval;
+}
+
+/*
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+static int write_word8(flash_info_t *info, ulong dest, ulong data)
+{
+ volatile uchar *addr2 = (uchar *) (info->start[0]);
+ volatile uchar *dest2 = (uchar *) dest;
+ volatile uchar *data2 = (uchar *) &data;
+ int flag;
+ int i, tcode, rcode = 0;
+
+ /* Check if Flash is (sufficently) erased */
+ if ((*((volatile uchar *)dest) & (uchar)data) != (uchar)data)
+ return 2;
+
+ for (i = 0; i < (4 / sizeof(uchar)); i++) {
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ *(addr2 + 0x555) = (uchar) 0xAA;
+ *(addr2 + 0x2aa) = (uchar) 0x55;
+ *(addr2 + 0x555) = (uchar) 0xA0;
+
+ dest2[i] = data2[i];
+
+ /* Wait for write to complete, up to 1ms */
+ tcode = wait_for_DQ7((ulong) &dest2[i], data2[i], 1);
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* Make sure we didn't timeout */
+ if (tcode)
+ rcode = 1;
+ }
+
+ return rcode;
+}
+
+static int write_word32(flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long *) dest;
+ ulong status;
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data)
+ return 2;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ *addr = 0x00400040; /* write setup */
+ *addr = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer(0);
+
+ while (((status = *addr) & 0x00800080) != 0x00800080) {
+ WATCHDOG_RESET();
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ *addr = 0x00FF00FF; /* restore read mode */
+ return 1;
+ }
+ }
+
+ *addr = 0x00FF00FF; /* restore read mode */
+
+ return 0;
+}
+
+static int _flash_protect(flash_info_t *info, long sector)
+{
+ int i;
+ int flag;
+ ulong status;
+ int rcode = 0;
+ volatile long *addr = (long *)sector;
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F320J3A:
+ case FLASH_28F640J3A:
+ case FLASH_28F128J3A:
+ /* Disable interrupts which might cause Flash to timeout */
+ flag = disable_interrupts();
+
+ /* Issue command */
+ *addr = 0x00500050L; /* Clear the status register */
+ *addr = 0x00600060L; /* Set lock bit setup */
+ *addr = 0x00010001L; /* Set lock bit confirm */
+
+ /* Wait for command completion */
+ for (i = 0; i < 10; i++) { /* 75us timeout, wait 100us */
+ udelay(10);
+ if ((*addr & 0x00800080L) == 0x00800080L)
+ break;
+ }
+
+ /* Not successful? */
+ status = *addr;
+ if (status != 0x00800080L) {
+ printf("Protect %x sector failed: %x\n",
+ (uint) sector, (uint) status);
+ rcode = 1;
+ }
+
+ /* Restore read mode */
+ *addr = 0x00ff00ffL;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ break;
+ case FLASH_AM040: /* No soft sector protection */
+ break;
+ }
+
+ /* Turn protection on for this sector */
+ for (i = 0; i < info->sector_count; i++) {
+ if (info->start[i] == sector) {
+ info->protect[i] = 1;
+ break;
+ }
+ }
+
+ return rcode;
+}
+
+static int _flash_unprotect(flash_info_t *info, long sector)
+{
+ int i;
+ int flag;
+ ulong status;
+ int rcode = 0;
+ volatile long *addr = (long *) sector;
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F320J3A:
+ case FLASH_28F640J3A:
+ case FLASH_28F128J3A:
+ /* Disable interrupts which might cause Flash to timeout */
+ flag = disable_interrupts();
+
+ *addr = 0x00500050L; /* Clear the status register */
+ *addr = 0x00600060L; /* Clear lock bit setup */
+ *addr = 0x00D000D0L; /* Clear lock bit confirm */
+
+ /* Wait for command completion */
+ for (i = 0; i < 80; i++) { /* 700ms timeout, wait 800 */
+ udelay(10000); /* Delay 10ms */
+ if ((*addr & 0x00800080L) == 0x00800080L)
+ break;
+ }
+
+ /* Not successful? */
+ status = *addr;
+ if (status != 0x00800080L) {
+ printf("Un-protect %x sector failed: %x\n",
+ (uint) sector, (uint) status);
+ *addr = 0x00ff00ffL;
+ rcode = 1;
+ }
+
+ /* restore read mode */
+ *addr = 0x00ff00ffL;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ break;
+ case FLASH_AM040: /* No soft sector protection */
+ break;
+ }
+
+ /*
+ * Fix Intel's little red wagon. Reprotect
+ * sectors that were protected before we undid
+ * protection on a specific sector.
+ */
+ for (i = 0; i < info->sector_count; i++) {
+ if (info->start[i] != sector) {
+ if (info->protect[i]) {
+ if (_flash_protect(info, info->start[i]))
+ rcode = 1;
+ }
+ } else /* Turn protection off for this sector */
+ info->protect[i] = 0;
+ }
+
+ return rcode;
+}
+
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+ int rcode;
+
+ if (prot)
+ rcode = _flash_protect(info, info->start[sector]);
+ else
+ rcode = _flash_unprotect(info, info->start[sector]);
+
+ return rcode;
+}
diff --git a/board/w7o/fpga.c b/board/w7o/fpga.c
new file mode 100644
index 0000000..a27e8ab
--- /dev/null
+++ b/board/w7o/fpga.c
@@ -0,0 +1,371 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ * and
+ * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <common.h>
+#include "w7o.h"
+#include <asm/processor.h>
+#include <linux/compiler.h>
+#include "errors.h"
+
+static void
+fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr)
+{
+ unsigned long i;
+ volatile unsigned long val;
+ volatile unsigned short *dest = daddr; /* volatile-bypass optimizer */
+
+ for (i = 0; i < len; i++, src++) {
+ val = *src;
+ *dest = (unsigned short) ((val & 0xff000000L) >> 16);
+ *dest = (unsigned short) ((val & 0x00ff0000L) >> 8);
+ *dest = (unsigned short) (val & 0x0000ff00L);
+ *dest = (unsigned short) ((val & 0x000000ffL) << 8);
+ }
+
+ /* Terminate programming with 4 C clocks */
+ dest = daddr;
+ val = *(unsigned short *) dest;
+ val = *(unsigned short *) dest;
+ val = *(unsigned short *) dest;
+ val = *(unsigned short *) dest;
+
+}
+
+
+int
+fpgaDownload(unsigned char *saddr, unsigned long size, unsigned short *daddr)
+{
+ int i; /* index, intr disable flag */
+ int start; /* timer */
+ unsigned long greg, grego; /* GPIO & output register */
+ unsigned long length; /* image size in words */
+ unsigned long *source; /* image source addr */
+ unsigned short *dest; /* destination FPGA addr */
+ volatile unsigned short *ndest; /* temp dest FPGA addr */
+ unsigned long cnfg = GPIO_XCV_CNFG; /* FPGA CNFG */
+ unsigned long eirq = GPIO_XCV_IRQ;
+ int retval = -1; /* Function return value */
+ __maybe_unused volatile unsigned short val; /* temp val */
+
+ /* Setup some basic values */
+ length = (size / 4) + 1; /* size in words, rounding UP
+ is OK */
+ source = (unsigned long *) saddr;
+ dest = (unsigned short *) daddr;
+
+ /* Get DCR output register */
+ grego = in32(PPC405GP_GPIO0_OR);
+
+ /* Reset FPGA */
+ grego &= ~GPIO_XCV_PROG; /* PROG line low */
+ out32(PPC405GP_GPIO0_OR, grego);
+
+ /* Setup timeout timer */
+ start = get_timer(0);
+
+ /* Wait for FPGA init line to go low */
+ while (in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) {
+ /* Check for timeout - 100us max, so use 3ms */
+ if (get_timer(start) > 3) {
+ printf(" failed to start init.\n");
+ log_warn(ERR_XINIT0); /* Don't halt */
+
+ /* Reset line stays low */
+ goto done; /* I like gotos... */
+ }
+ }
+
+ /* Unreset FPGA */
+ grego |= GPIO_XCV_PROG; /* PROG line high */
+ out32(PPC405GP_GPIO0_OR, grego);
+
+ /* Wait for FPGA end of init period = init line go hi */
+ while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) {
+
+ /* Check for timeout */
+ if (get_timer(start) > 3) {
+ printf(" failed to exit init.\n");
+ log_warn(ERR_XINIT1);
+
+ /* Reset FPGA */
+ grego &= ~GPIO_XCV_PROG; /* PROG line low */
+ out32(PPC405GP_GPIO0_OR, grego);
+
+ goto done;
+ }
+ }
+
+ /* Now program FPGA ... */
+ ndest = dest;
+ for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
+ /* Toggle IRQ/GPIO */
+ greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
+ greg |= eirq; /* toggle irq/gpio */
+ mtdcr(CPC0_CR0, greg); /* ... just do it */
+
+ /* turn on open drain for CNFG */
+ greg = in32(PPC405GP_GPIO0_ODR); /* get open drain register */
+ greg |= cnfg; /* CNFG open drain */
+ out32(PPC405GP_GPIO0_ODR, greg); /* .. just do it */
+
+ /* Turn output enable on for CNFG */
+ greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
+ greg |= cnfg; /* CNFG tristate inactive */
+ out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
+
+ /* Setup FPGA for programming */
+ grego &= ~cnfg; /* CONFIG line low */
+ out32(PPC405GP_GPIO0_OR, grego);
+
+ /*
+ * Program the FPGA
+ */
+ printf("\n destination: 0x%lx ", (unsigned long) ndest);
+
+ fpga_img_write(source, length, (unsigned short *) ndest);
+
+ /* Done programming */
+ grego |= cnfg; /* CONFIG line high */
+ out32(PPC405GP_GPIO0_OR, grego);
+
+ /* Turn output enable OFF for CNFG */
+ greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
+ greg &= ~cnfg; /* CNFG tristate inactive */
+ out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
+
+ /* Toggle IRQ/GPIO */
+ greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
+ greg &= ~eirq; /* toggle irq/gpio */
+ mtdcr(CPC0_CR0, greg); /* ... just do it */
+
+ /* XXX - Next FPGA addr */
+ ndest = (unsigned short *) ((char *) ndest + 0x00100000L);
+ cnfg >>= 1; /* XXX - Next */
+ eirq >>= 1;
+ }
+
+ /* Terminate programming with 4 C clocks */
+ ndest = dest;
+ for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
+ val = *ndest;
+ val = *ndest;
+ val = *ndest;
+ val = *ndest;
+ ndest = (unsigned short *) ((char *) ndest + 0x00100000L);
+ }
+
+ /* Setup timer */
+ start = get_timer(0);
+
+ /* Wait for FPGA end of programming period = Test DONE low */
+ while (!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) {
+
+ /* Check for timeout */
+ if (get_timer(start) > 3) {
+ printf(" done failed to come high.\n");
+ log_warn(ERR_XDONE1);
+
+ /* Reset FPGA */
+ grego &= ~GPIO_XCV_PROG; /* PROG line low */
+ out32(PPC405GP_GPIO0_OR, grego);
+
+ goto done;
+ }
+ }
+
+ printf("\n FPGA load succeeded\n");
+ retval = 0; /* Program OK */
+
+done:
+ return retval;
+}
+
+/* FPGA image is stored in flash */
+extern flash_info_t flash_info[];
+
+int init_fpga(void)
+{
+ unsigned int i, j, ptr; /* General purpose */
+ unsigned char bufchar; /* General purpose character */
+ unsigned char *buf; /* Start of image pointer */
+ unsigned long len; /* Length of image */
+ unsigned char *fn_buf; /* Start of filename string */
+ unsigned int fn_len; /* Length of filename string */
+ unsigned char *xcv_buf; /* Pointer to start of image */
+ unsigned long xcv_len; /* Length of image */
+ unsigned long crc; /* 30bit crc in image */
+ unsigned long calc_crc; /* Calc'd 30bit crc */
+ int retval = -1;
+
+ /* Tell the world what we are doing */
+ printf("FPGA: ");
+
+ /*
+ * Get address of first sector where the FPGA
+ * image is stored.
+ */
+ buf = (unsigned char *) flash_info[1].start[0];
+
+ /*
+ * Get the stored image's CRC & length.
+ */
+ crc = *(unsigned long *) (buf + 4); /* CRC is first long word */
+ len = *(unsigned long *) (buf + 8); /* Image len is next long */
+
+ /* Pedantic */
+ if ((len < 0x133A4) || (len > 0x80000))
+ goto bad_image;
+
+ /*
+ * Get the file name pointer and length.
+ * filename length is next short
+ */
+ fn_len = (*(unsigned short *) (buf + 12) & 0xff);
+ fn_buf = buf + 14;
+
+ /*
+ * Get the FPGA image pointer and length length.
+ */
+ xcv_buf = fn_buf + fn_len; /* pointer to fpga image */
+ xcv_len = len - 14 - fn_len; /* fpga image length */
+
+ /* Check for uninitialized FLASH */
+ if ((strncmp((char *) buf, "w7o", 3) != 0) || (len > 0x0007ffffL)
+ || (len == 0))
+ goto bad_image;
+
+ /*
+ * Calculate and Check the image's CRC.
+ */
+ calc_crc = crc32(0, xcv_buf, xcv_len);
+ if (crc != calc_crc) {
+ printf("\nfailed - bad CRC\n");
+ goto done;
+ }
+
+ /* Output the file name */
+ printf("file name : ");
+ for (i = 0; i < fn_len; i++) {
+ bufchar = fn_buf[+i];
+ if (bufchar < ' ' || bufchar > '~')
+ bufchar = '.';
+ putc(bufchar);
+ }
+
+ /*
+ * find rest of display data
+ */
+ ptr = 15; /* Offset to ncd filename
+ length in fpga image */
+ j = xcv_buf[ptr]; /* Get len of ncd filename */
+ if (j > 32)
+ goto bad_image;
+ ptr = ptr + j + 3; /* skip ncd filename string +
+ 3 bytes more bytes */
+
+ /*
+ * output target device string
+ */
+ j = xcv_buf[ptr++] - 1; /* len of targ str less term */
+ if (j > 32)
+ goto bad_image;
+ printf("\n target : ");
+ for (i = 0; i < j; i++) {
+ bufchar = (xcv_buf[ptr++]);
+ if (bufchar < ' ' || bufchar > '~')
+ bufchar = '.';
+ putc(bufchar);
+ }
+
+ /*
+ * output compilation date string and time string
+ */
+ ptr += 3; /* skip 2 bytes */
+ printf("\n synth time : ");
+ j = (xcv_buf[ptr++] - 1); /* len of date str less term */
+ if (j > 32)
+ goto bad_image;
+ for (i = 0; i < j; i++) {
+ bufchar = (xcv_buf[ptr++]);
+ if (bufchar < ' ' || bufchar > '~')
+ bufchar = '.';
+ putc(bufchar);
+ }
+
+ ptr += 3; /* Skip 2 bytes */
+ printf(" - ");
+ j = (xcv_buf[ptr++] - 1); /* slen = targ dev str len */
+ if (j > 32)
+ goto bad_image;
+ for (i = 0; i < j; i++) {
+ bufchar = (xcv_buf[ptr++]);
+ if (bufchar < ' ' || bufchar > '~')
+ bufchar = '.';
+ putc(bufchar);
+ }
+
+ /*
+ * output crc and length strings
+ */
+ printf("\n len & crc : 0x%lx 0x%lx", len, crc);
+
+ /*
+ * Program the FPGA.
+ */
+ retval = fpgaDownload((unsigned char *) xcv_buf, xcv_len,
+ (unsigned short *) 0xfd000000L);
+ return retval;
+
+bad_image:
+ printf("\n BAD FPGA image format @ %lx\n",
+ flash_info[1].start[0]);
+ log_warn(ERR_XIMAGE);
+done:
+ return retval;
+}
+
+void test_fpga(unsigned short *daddr)
+{
+ int i;
+ volatile unsigned short *ndest = daddr;
+
+ for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
+#if defined(CONFIG_W7OLMG)
+ ndest[0x7e] = 0x55aa;
+ if (ndest[0x7e] != 0x55aa)
+ log_warn(ERR_XRW1 + i);
+ ndest[0x7e] = 0xaa55;
+ if (ndest[0x7e] != 0xaa55)
+ log_warn(ERR_XRW1 + i);
+ ndest[0x7e] = 0xc318;
+ if (ndest[0x7e] != 0xc318)
+ log_warn(ERR_XRW1 + i);
+
+#elif defined(CONFIG_W7OLMC)
+ ndest[0x800] = 0x55aa;
+ ndest[0x801] = 0xaa55;
+ ndest[0x802] = 0xc318;
+ ndest[0x4800] = 0x55aa;
+ ndest[0x4801] = 0xaa55;
+ ndest[0x4802] = 0xc318;
+ if ((ndest[0x800] != 0x55aa) ||
+ (ndest[0x801] != 0xaa55) || (ndest[0x802] != 0xc318))
+ log_warn(ERR_XRW1 + (2 * i)); /* Auto gen error code */
+ if ((ndest[0x4800] != 0x55aa) ||
+ (ndest[0x4801] != 0xaa55) || (ndest[0x4802] != 0xc318))
+ log_warn(ERR_XRW2 + (2 * i)); /* Auto gen error code */
+
+#else
+#error "Unknown W7O board configuration"
+#endif
+ }
+
+ printf(" FPGA ready\n");
+ return;
+}
diff --git a/board/w7o/fsboot.c b/board/w7o/fsboot.c
new file mode 100644
index 0000000..8f4fe31
--- /dev/null
+++ b/board/w7o/fsboot.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2001
+ * Wave 7 Optics, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <elf.h>
+
+/*
+ * FIXME: Add code to test image and it's header.
+ */
+static int
+image_check(ulong addr)
+{
+ return valid_elf_image(addr);
+}
+
+void
+init_fsboot(void)
+{
+ char *envp;
+ ulong loadaddr;
+ ulong testaddr;
+ ulong alt_loadaddr;
+ char buf[9];
+
+ /*
+ * Get test image address
+ */
+ if ((envp = getenv("testaddr")) != NULL)
+ testaddr = simple_strtoul(envp, NULL, 16);
+ else
+ testaddr = -1;
+
+ /*
+ * Are we going to test boot and image?
+ */
+ if ((testaddr != -1) && image_check(testaddr)) {
+
+ /* Set alt_loadaddr */
+ alt_loadaddr = testaddr;
+ sprintf(buf, "%lX", alt_loadaddr);
+ setenv("alt_loadaddr", buf);
+
+ /* Clear test_addr */
+ setenv("testaddr", NULL);
+
+ /*
+ * Save current environment with alt_loadaddr,
+ * and cleared testaddr.
+ */
+ saveenv();
+
+ /*
+ * Setup temporary loadaddr to alt_loadaddr
+ * XXX - DO NOT SAVE ENVIRONMENT!
+ */
+ loadaddr = alt_loadaddr;
+ sprintf(buf, "%lX", loadaddr);
+ setenv("loadaddr", buf);
+
+ } else { /* Normal boot */
+ setenv("alt_loadaddr", NULL); /* Clear alt_loadaddr */
+ setenv("testaddr", NULL); /* Clear testaddr */
+ saveenv();
+ }
+
+ return;
+}
diff --git a/board/w7o/init.S b/board/w7o/init.S
new file mode 100644
index 0000000..dfde149
--- /dev/null
+++ b/board/w7o/init.S
@@ -0,0 +1,244 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0 IBM-pibs
+ */
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+/******************************************************************************
+ * Function: ext_bus_cntlr_init
+ *
+ * Description: Configures EBC Controller and a few basic chip selects.
+ *
+ * CS0 is setup to get the Boot Flash out of the addresss range
+ * so that we may setup a stack. CS7 is setup so that we can
+ * access and reset the hardware watchdog.
+ *
+ * IMPORTANT: For pass1 this code must run from
+ * cache since you can not reliably change a peripheral banks
+ * timing register (pbxap) while running code from that bank.
+ * For ex., since we are running from ROM on bank 0, we can NOT
+ * execute the code that modifies bank 0 timings from ROM, so
+ * we run it from cache.
+ *
+ * Notes: Does NOT use the stack.
+ *****************************************************************************/
+ .section ".text"
+ .align 2
+ .globl ext_bus_cntlr_init
+ .type ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+ mflr r0
+ /********************************************************************
+ * Prefetch entire ext_bus_cntrl_init function into the icache.
+ * This is necessary because we are going to change the same CS we
+ * are executing from. Otherwise a CPU lockup may occur.
+ *******************************************************************/
+ bl ..getAddr
+..getAddr:
+ mflr r3 /* get address of ..getAddr */
+
+ /* Calculate number of cache lines for this function */
+ addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
+ mtctr r4
+..ebcloop:
+ icbt r0, r3 /* prefetch cache line for addr in r3*/
+ addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
+ bdnz ..ebcloop /* continue for $CTR cache lines */
+
+ /********************************************************************
+ * Delay to ensure all accesses to ROM are complete before changing
+ * bank 0 timings. 200usec should be enough.
+ * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+ *******************************************************************/
+ addis r3, 0, 0x0
+ ori r3, r3, 0xA000 /* wait 200us from reset */
+ mtctr r3
+..spinlp:
+ bdnz ..spinlp /* spin loop */
+
+ /********************************************************************
+ * Setup External Bus Controller (EBC).
+ *******************************************************************/
+ addi r3, 0, EBC0_CFG
+ mtdcr EBC0_CFGADDR, r3
+ addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */
+ ori r4, r4, 0x0 /* Drive CS with external master */
+ mtdcr EBC0_CFGDATA, r4
+
+ /********************************************************************
+ * Change PCIINT signal to PerWE
+ *******************************************************************/
+ mfdcr r4, CPC0_CR1
+ ori r4, r4, 0x4000
+ mtdcr CPC0_CR1, r4
+
+ /********************************************************************
+ * Memory Bank 0 (Flash Bank 0) initialization
+ *******************************************************************/
+ addi r3, 0, PB1AP
+ mtdcr EBC0_CFGADDR, r3
+ addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
+ ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
+ mtdcr EBC0_CFGDATA, r4
+
+ addi r3, 0, PB0CR
+ mtdcr EBC0_CFGADDR, r3
+ addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
+ ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
+ mtdcr EBC0_CFGDATA, r4
+
+ /********************************************************************
+ * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
+ *******************************************************************/
+ addi r3, 0, PB7AP
+ mtdcr EBC0_CFGADDR, r3
+ addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
+ ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
+ mtdcr EBC0_CFGDATA, r4
+
+ addi r3, 0, PB7CR
+ mtdcr EBC0_CFGADDR, r3
+ addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
+ ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
+ mtdcr EBC0_CFGDATA, r4
+
+ /* We are all done */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function: sdram_init
+ *
+ * Description: Configures SDRAM memory banks.
+ *
+ * Serial Presence Detect, "SPD," reads the SDRAM EEPROM
+ * via the IIC bus and then configures the SDRAM memory
+ * banks appropriately. If Auto Memory Configuration is
+ * is not used, it is assumed that a 4MB 11x8x2, non-ECC,
+ * SDRAM is soldered down.
+ *
+ * Notes: Expects that the stack is already setup.
+ *****************************************************************************/
+ .section ".text"
+ .align 2
+ .globl sdram_init
+ .type sdram_init, @function
+sdram_init:
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -8(r1) /* Save back chain and move SP */
+ stw r0, +12(r1) /* Save link register */
+
+ /*
+ * First call spd_sdram to try to init SDRAM according to the
+ * contents of the SPD EEPROM. If the SPD EEPROM is blank or
+ * erronious, spd_sdram returns 0 in R3.
+ */
+ li r3,0
+ bl spd_sdram
+ addic. r3, r3, 0 /* Check for error, save dram size */
+ bne ..sdri_done /* If it worked, we're done... */
+
+ /********************************************************************
+ * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
+ * is the SMALLEST SDRAM size the 405 supports. We can do this
+ * because W7O boards have soldered on RAM, and there will always
+ * be some amount present. If we were using DIMMs, we should hang
+ * the board instead, since it doesn't have any RAM to continue
+ * running with.
+ *******************************************************************/
+
+ /*
+ * Disable memory controller to allow
+ * values to be changed.
+ */
+ addi r3, 0, SDRAM0_CFG
+ mtdcr SDRAM0_CFGADDR, r3
+ addis r4, 0, 0x0
+ ori r4, r4, 0x0
+ mtdcr SDRAM0_CFGDATA, r4
+
+ /*
+ * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
+ * All other banks are disabled.
+ */
+ addi r3, 0, SDRAM0_B0CR
+ mtdcr SDRAM0_CFGADDR, r3
+ addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
+ ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
+ mtdcr SDRAM0_CFGDATA, r4
+
+ /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
+ addi r4, 0, 0 /* Zero the data reg */
+
+ addi r3, r3, 4 /* Point to MB1CF reg */
+ mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
+ mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
+
+ addi r3, r3, 4 /* Point to MB2CF reg */
+ mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
+ mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
+
+ addi r3, r3, 4 /* Point to MB3CF reg */
+ mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
+ mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
+
+ /********************************************************************
+ * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
+ * To set the appropriate timings, we assume sdram is
+ * 100MHz (pc100 compliant).
+ *******************************************************************/
+
+ /*
+ * Set up SDTR1
+ */
+ addi r3, 0, SDRAM0_TR
+ mtdcr SDRAM0_CFGADDR, r3
+ addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
+ ori r4, r4, 0x400D
+ mtdcr SDRAM0_CFGDATA, r4
+
+ /*
+ * Set RTR
+ */
+ addi r3, 0, SDRAM0_RTR
+ mtdcr SDRAM0_CFGADDR, r3
+ addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */
+ mtdcr SDRAM0_CFGDATA, r4
+
+ /********************************************************************
+ * Delay to ensure 200usec have elapsed since reset. Assume worst
+ * case that the core is running 200Mhz:
+ * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+ *******************************************************************/
+ addis r3, 0, 0x0000
+ ori r3, r3, 0xA000 /* Wait 200us from reset */
+ mtctr r3
+..spinlp2:
+ bdnz ..spinlp2 /* spin loop */
+
+ /********************************************************************
+ * Set memory controller options reg, MCOPT1.
+ *******************************************************************/
+ addi r3, 0, SDRAM0_CFG
+ mtdcr SDRAM0_CFGADDR, r3
+ addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
+ ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
+ mtdcr SDRAM0_CFGDATA, r4 /* EMDULR=1 */
+
+..sdri_done:
+ /* restore and return */
+ lwz r0, +12(r1) /* Get saved link register */
+ addi r1, r1, +8 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+.Lfe1: .size sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */
diff --git a/board/w7o/post1.S b/board/w7o/post1.S
new file mode 100644
index 0000000..aae5387
--- /dev/null
+++ b/board/w7o/post1.S
@@ -0,0 +1,724 @@
+/*
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
+ * and
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/*
+ * Description:
+ * Routine to exercise memory for the bringing up of our boards.
+ */
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include <watchdog.h>
+
+#include "errors.h"
+
+#define _ASMLANGUAGE
+
+ .globl test_sdram
+ .globl test_led
+ .globl log_stat
+ .globl log_warn
+ .globl log_err
+ .globl temp_uart_init
+ .globl post_puts
+ .globl disp_hex
+
+/*****************************************************
+******* Text Strings for low level printing ******
+******* In section got2 *******
+*****************************************************/
+
+/*
+ * Define the text strings for errors and warnings.
+ * Switch to .data section.
+ */
+ .section ".data"
+err_str: .asciz "*** POST ERROR = "
+warn_str: .asciz "*** POST WARNING = "
+end_str: .asciz "\r\n"
+
+/*
+ * Enter the labels in Global Entry Table (GOT).
+ * Switch to .got2 section.
+ */
+ START_GOT
+ GOT_ENTRY(err_str)
+ GOT_ENTRY(warn_str)
+ GOT_ENTRY(end_str)
+ END_GOT
+
+/*
+ * Switch back to .text section.
+ */
+ .text
+
+/****************************************
+ ****************************************
+ ******** LED register test ********
+ ****************************************
+ ***************************************/
+test_led:
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -12(r1) /* Save back chain and move SP */
+ stw r0, +16(r1) /* Save link register */
+ stw r4, +8(r1) /* save R4 */
+
+ WATCHDOG_RESET /* Reset the watchdog */
+
+ addi r3, 0, ERR_FF /* first test value is ffff */
+ addi r4, r3, 0 /* save copy of pattern */
+ bl set_led /* store first test value */
+ bl get_led /* read it back */
+ xor. r4, r4, r3 /* compare to original */
+#if defined(CONFIG_W7OLMC)
+ andi. r4, r4, 0x00ff /* lmc has 8 bits */
+#else
+ andi. r4, r4, 0xffff /* lmg has 16 bits */
+#endif
+ beq LED2 /* next test */
+ addi r3, 0, ERR_LED /* error code = 1 */
+ bl log_err /* display error and halt */
+LED2: addi r3, 0, ERR_00 /* 2nd test value is 0000 */
+ addi r4, r3, 0 /* save copy of pattern */
+ bl set_led /* store first test value */
+ bl get_led /* read it back */
+ xor. r4, r4, r3 /* compare to original */
+#if defined(CONFIG_W7OLMC)
+ andi. r4, r4, 0x00ff /* lmc has 8 bits */
+#else
+ andi. r4, r4, 0xffff /* lmg has 16 bits */
+#endif
+ beq LED3 /* next test */
+ addi r3, 0, ERR_LED /* error code = 1 */
+ bl log_err /* display error and halt */
+
+LED3: /* restore stack and return */
+ lwz r0, +16(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ lwz r4, +8(r1) /* restore r4 */
+ addi r1, r1, +12 /* Remove frame from stack */
+ blr /* Return to calling function */
+
+/****************************************
+ ****************************************
+ ******** SDRAM TESTS ********
+ ****************************************
+ ***************************************/
+test_sdram:
+ /* called with mem size in r3 */
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -16(r1) /* Save back chain and move SP */
+ stw r0, +20(r1) /* Save link register */
+ stmw r30, +8(r1) /* save R30,R31 */
+ /* r30 is log2(mem size) */
+ /* r31 is mem size */
+
+ /* take log2 of total mem size */
+ addi r31, r3, 0 /* save total mem size */
+ addi r30, 0, 0 /* clear r30 */
+l2_loop:
+ srwi. r31, r31, 1 /* shift right 1 */
+ addi r30, r30, 1 /* count shifts */
+ bne l2_loop /* loop till done */
+ addi r30, r30, -1 /* correct for over count */
+ addi r31, r3, 0 /* save original size */
+
+ /* now kick the dog and test the mem */
+ WATCHDOG_RESET /* Reset the watchdog */
+ bl Data_Buster /* test crossed/shorted data lines */
+ addi r3, r30, 0 /* get log2(memsize) */
+ addi r4, r31, 0 /* get memsize */
+ bl Ghost_Buster /* test crossed/shorted addr lines */
+ addi r3, r31, 0 /* get mem size */
+ bl Bit_Buster /* check for bad internal bits */
+
+ /* restore stack and return */
+ lmw r30, +8(r1) /* Restore r30, r31 */
+ lwz r0, +20(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ addi r1, r1, +16 /* Remove frame from stack */
+ blr /* Return to calling function */
+
+
+/****************************************
+ ******** sdram data bus test ********
+ ***************************************/
+Data_Buster:
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -24(r1) /* Save back chain and move SP */
+ stw r0, +28(r1) /* Save link register */
+ stmw r28, 8(r1) /* save r28 - r31 on stack */
+ /* r31 i/o register */
+ /* r30 sdram base address */
+ /* r29 5555 syndrom */
+ /* r28 aaaa syndrom */
+
+ /* set up led register for this test */
+ addi r3, 0, ERR_RAMG /* set led code to 1 */
+ bl log_stat /* store test value */
+ /* now test the dram data bus */
+ xor r30, r30, r30 /* load r30 with base addr of sdram */
+ addis r31, 0, 0x5555 /* load r31 with test value */
+ ori r31, r31, 0x5555
+ stw r31,0(r30) /* sto the value */
+ lwz r29,0(r30) /* read it back */
+ xor r29,r31,r29 /* compare it to original */
+ addis r31, 0, 0xaaaa /* load r31 with test value */
+ ori r31, r31, 0xaaaa
+ stw r31,0(r30) /* sto the value */
+ lwz r28,0(r30) /* read it back */
+ xor r28,r31,r28 /* compare it to original */
+ or r3,r28,r29 /* or together both error terms */
+ /*
+ * Now that we have the error bits,
+ * we have to decide which part they are in.
+ */
+ bl get_idx /* r5 is now index to error */
+ addi r3, r3, ERR_RAMG
+ cmpwi r3, ERR_RAMG /* check for errors */
+ beq db_done /* skip if no errors */
+ bl log_err /* log the error */
+
+db_done:
+ lmw r28, 8(r1) /* restore r28 - r31 from stack */
+ lwz r0, +28(r1) /* Get saved link register */
+ addi r1, r1, +24 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+
+
+/****************************************************
+ ******** test for address ghosting in dram ********
+ ***************************************************/
+
+Ghost_Buster:
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -36(r1) /* Save back chain and move SP */
+ stw r0, +40(r1) /* Save link register */
+ stmw r25, 8(r1) /* save r25 - r31 on stack */
+ /* r31 = scratch register */
+ /* r30 is main referance loop counter,
+ 0 to 23 */
+ /* r29 is ghost loop count, 0 to 22 */
+ /* r28 is referance address */
+ /* r27 is ghost address */
+ /* r26 is log2 (mem size) =
+ number of byte addr bits */
+ /* r25 is mem size */
+
+ /* save the log2(mem size) and mem size */
+ addi r26, r3, 0 /* r26 is number of byte addr bits */
+ addi r25, r4, 0 /* r25 is mem size in bytes */
+
+ /* set the leds for address ghost test */
+ addi r3, 0, ERR_ADDG
+ bl set_led
+
+ /* first fill memory with zeros */
+ srwi r31, r25, 2 /* convert bytes to longs */
+ mtctr r31 /* setup byte counter */
+ addi r28, 0, 0 /* start at address at 0 */
+ addi r31, 0, 0 /* data value = 0 */
+clr_loop:
+ stw r31, 0(r28) /* Store zero value */
+ addi r28, r28, 4 /* Increment to next word */
+ andi. r27, r28, 0xffff /* check for 2^16 loops */
+ bne clr_skip /* if not there, then skip */
+ WATCHDOG_RESET /* kick the dog every now and then */
+clr_skip:
+ bdnz clr_loop /* Round and round... */
+
+ /* now do main test */
+ addi r30, 0, 0 /* start referance counter at 0 */
+outside:
+ /*
+ * Calculate the referance address
+ * the referance address is calculated by setting the (r30-1)
+ * bit of the base address
+ * when r30=0, the referance address is the base address.
+ * thus the sequence 0,1,2,4,8,..,2^(n-1)
+ * setting the bit is done with the following shift functions.
+ */
+ WATCHDOG_RESET /* Reset the watchdog */
+
+ addi r31, 0, 1 /* r31 = 1 */
+ slw r28, r31, r30 /* set bit coresponding to loop cnt */
+ srwi r28, r28, 1 /* then shift it right one so */
+ /* we start at location 0 */
+ /* fill referance address with Fs */
+ addi r31, 0, 0x00ff /* r31 = one byte of set bits */
+ stb r31,0(r28) /* save ff in referance address */
+
+ /* ghost (inner) loop, now check all posible ghosted addresses */
+ addi r29, 0, 0 /* start ghosted loop counter at 0 */
+inside:
+ /*
+ * Calculate the ghost address by flipping one
+ * bit of referance address. This gives the
+ * sequence 1,2,4,8,...,2^(n-1)
+ */
+ addi r31, 0, 1 /* r31 = 1 */
+ slw r27, r31, r29 /* set bit coresponding to loop cnt */
+ xor r27, r28, r27 /* ghost address = ref addr with
+ bit flipped*/
+
+ /* now check for ghosting */
+ lbz r31,0(r27) /* get content of ghost addr */
+ cmpwi r31, 0 /* compare read value to 0 */
+ bne Casper /* we found a ghost! */
+
+ /* now close ghost ( inner ) loop */
+ addi r29, r29, 1 /* increment inner loop counter */
+ cmpw r29, r26 /* check for last inner loop */
+ blt inside /* do more inner loops */
+
+ /* now close referance ( outer ) loop */
+ addi r31, 0, 0 /* r31 = zero */
+ stb r31, 0(28) /* zero out the altered address loc. */
+ /*
+ * Increment and check for end, count is zero based.
+ * With the ble, this gives us one more loops than
+ * address bits for sequence 0,1,2,4,8,...2^(n-1)
+ */
+ addi r30, r30, 1 /* increment outer loop counter */
+ cmpw r30, r26 /* check for last inner loop */
+ ble outside /* do more outer loops */
+
+ /* were done, lets go home */
+ b gb_done
+Casper: /* we found a ghost !! */
+ addi r3, 0, ERR_ADDF /* get indexed error message */
+ bl log_err /* log error led error code */
+gb_done: /* pack your bags, and go home */
+ lmw r25, 8(r1) /* restore r25 - r31 from stack */
+ lwz r0, +40(r1) /* Get saved link register */
+ addi r1, r1, +36 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+
+/****************************************************
+ ******** SDRAM data fill tests **********
+ ***************************************************/
+Bit_Buster:
+ /* called with mem size in r3 */
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -16(r1) /* Save back chain and move SP */
+ stw r0, +20(r1) /* Save link register */
+ stw r4, +8(r1) /* save R4 */
+ stw r5, +12(r1) /* save r5 */
+
+ addis r5, r3, 0 /* save mem size */
+
+ /* Test 55555555 */
+ addi r3, 0, ERR_R55G /* set up error code in case we fail */
+ bl log_stat /* store test value */
+ addis r4, 0, 0x5555
+ ori r4, r4, 0x5555
+ bl fill_test
+
+ /* Test aaaaaaaa */
+ addi r3, 0, ERR_RAAG /* set up error code in case we fail */
+ bl log_stat /* store test value */
+ addis r4, 0, 0xAAAA
+ ori r4, r4, 0xAAAA
+ bl fill_test
+
+ /* Test 00000000 */
+ addi r3, 0, ERR_R00G /* set up error code in case we fail */
+ bl log_stat /* store test value */
+ addis r4, 0, 0
+ ori r4, r4, 0
+ bl fill_test
+
+ /* restore stack and return */
+ lwz r5, +12(r1) /* restore r4 */
+ lwz r4, +8(r1) /* restore r4 */
+ lwz r0, +20(r1) /* Get saved link register */
+ addi r1, r1, +16 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+
+
+/****************************************************
+ ******** fill test ********
+ ***************************************************/
+/* tests memory by filling with value, and reading back */
+/* r5 = Size of memory in bytes */
+/* r4 = Value to write */
+/* r3 = Error code */
+fill_test:
+ mflr r0 /* Get link register */
+ stwu r1, -32(r1) /* Save back chain and move SP */
+ stw r0, +36(r1) /* Save link register */
+ stmw r27, 8(r1) /* save r27 - r31 on stack */
+ /* r31 - scratch register */
+ /* r30 - memory address */
+ mr r27, r3
+ mr r28, r4
+ mr r29, r5
+
+ WATCHDOG_RESET /* Reset the watchdog */
+
+ /* first fill memory with Value */
+ srawi r31, r29, 2 /* convert bytes to longs */
+ mtctr r31 /* setup counter */
+ addi r30, 0, 0 /* Make r30 = addr 0 */
+ft_0: stw r28, 0(r30) /* Store value */
+ addi r30, r30, 4 /* Increment to next word */
+ andi. r31, r30, 0xffff /* check for 2^16 loops */
+ bne ft_0a /* if not there, then skip */
+ WATCHDOG_RESET /* kick the dog every now and then */
+ft_0a: bdnz ft_0 /* Round and round... */
+
+ WATCHDOG_RESET /* Reset the watchdog */
+
+ /* Now confirm Value is in memory */
+ srawi r31, r29, 2 /* convert bytes to longs */
+ mtctr r31 /* setup counter */
+ addi r30, 0, 0 /* Make r30 = addr 0 */
+ft_1: lwz r31, 0(r30) /* get value from memory */
+ xor. r31, r31, r28 /* Writen = Read ? */
+ bne ft_err /* If bad, than halt */
+ addi r30, r30, 4 /* Increment to next word */
+ andi. r31, r30, 0xffff /* check for 2^16 loops*/
+ bne ft_1a /* if not there, then skip */
+ WATCHDOG_RESET /* kick the dog every now and then */
+ft_1a: bdnz ft_1 /* Round and round... */
+
+ WATCHDOG_RESET /* Reset the watchdog */
+
+ b fill_done /* restore and return */
+
+ft_err: addi r29, r27, 0 /* save current led code */
+ addi r27, r31, 0 /* get pattern in r27 */
+ bl get_idx /* get index from r27 */
+ add r27, r27, r29 /* add index to old led code */
+ bl log_err /* output led err code, halt CPU */
+
+fill_done:
+ lmw r27, 8(r1) /* restore r27 - r31 from stack */
+ lwz r0, +36(r1) /* Get saved link register */
+ addi r1, r1, +32 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+
+
+/****************************************************
+ ******* get error index from r3 pattern ********
+ ***************************************************/
+get_idx: /* r3 = (MSW(r3) !=0)*2 +
+ (LSW(r3) !=0) */
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -12(r1) /* Save back chain and move SP */
+ stw r0, +16(r1) /* Save link register */
+ stw r4, +8(r1) /* save R4 */
+
+ andi. r4, r3, 0xffff /* check for lower bits */
+ beq gi2 /* skip if no bits set */
+ andis. r4, r3, 0xffff /* check for upper bits */
+ beq gi3 /* skip if no bits set */
+ addi r3, 0, 3 /* both upper and lower bits set */
+ b gi_done
+gi2: andis. r4, r3, 0xffff /* check for upper bits*/
+ beq gi4 /* skip if no bits set */
+ addi r3, 0, 2 /* only upper bits set */
+ b gi_done
+gi3: addi r3, 0, 1 /* only lower bits set */
+ b gi_done
+gi4: addi r3, 0, 0 /* no bits set */
+gi_done:
+ /* restore stack and return */
+ lwz r0, +16(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ lwz r4, +8(r1) /* restore r4 */
+ addi r1, r1, +12 /* Remove frame from stack */
+ blr /* Return to calling function */
+
+/****************************************************
+ ******** set LED to R5 and hang ********
+ ***************************************************/
+log_stat: /* output a led code and continue */
+set_led:
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -12(r1) /* Save back chain and move SP */
+ stw r0, +16(r1) /* Save link register */
+ stw r4, +8(r1) /* save R4 */
+
+ addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */
+#if defined(CONFIG_W7OLMG) /* only on gateway, invert outputs */
+ xori r3,r3, 0xffff /* complement led code, active low */
+ sth r3, 0(r4) /* store first test value */
+ xori r3,r3, 0xffff /* complement led code, active low */
+#else /* if not gateway, then don't invert */
+ sth r3, 0(r4) /* store first test value */
+#endif
+
+ /* restore stack and return */
+ lwz r0, +16(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ lwz r4, +8(r1) /* restore r4 */
+ addi r1, r1, +12 /* Remove frame from stack */
+ blr /* Return to calling function */
+
+get_led:
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -12(r1) /* Save back chain and move SP */
+ stw r0, +16(r1) /* Save link register */
+ stw r4, +8(r1) /* save R4 */
+
+ addis r4, 0, 0xfe00 /* LED buffer is at 0xfe000000 */
+ lhz r3, 0(r4) /* store first test value */
+#if defined(CONFIG_W7OLMG) /* only on gateway, invert inputs */
+ xori r3,r3, 0xffff /* complement led code, active low */
+#endif
+
+ /* restore stack and return */
+ lwz r0, +16(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ lwz r4, +8(r1) /* restore r4 */
+ addi r1, r1, +12 /* Remove frame from stack */
+ blr /* Return to calling function */
+
+log_err: /* output the error and hang the board ( for now ) */
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -12(r1) /* Save back chain and move SP */
+ stw r0, +16(r1) /* Save link register */
+ stw r3, +8(r1) /* save a copy of error code */
+ bl set_led /* set the led pattern */
+ GET_GOT /* get GOT address in r14 */
+ lwz r3,GOT(err_str) /* get address of string */
+ bl post_puts /* output the warning string */
+ lwz r3, +8(r1) /* get error code */
+ addi r4, 0, 2 /* set disp length to 2 nibbles */
+ bl disp_hex /* output the error code */
+ lwz r3,GOT(end_str) /* get address of string */
+ bl post_puts /* output the warning string */
+halt:
+ b halt /* hang */
+
+ /* restore stack and return */
+ lwz r0, +16(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ addi r1, r1, +12 /* Remove frame from stack */
+ blr /* Return to calling function */
+
+log_warn: /* output a warning, then continue with operations */
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -16(r1) /* Save back chain and move SP */
+ stw r0, +20(r1) /* Save link register */
+ stw r3, +8(r1) /* save a copy of error code */
+ stw r14, +12(r1) /* save a copy of r14 (used by GOT) */
+
+ bl set_led /* set the led pattern */
+ GET_GOT /* get GOT address in r14 */
+ lwz r3,GOT(warn_str) /* get address of string */
+ bl post_puts /* output the warning string */
+ lwz r3, +8(r1) /* get error code */
+ addi r4, 0, 2 /* set disp length to 2 nibbles */
+ bl disp_hex /* output the error code */
+ lwz r3,GOT(end_str) /* get address of string */
+ bl post_puts /* output the warning string */
+
+ addis r3, 0, 64 /* has a long delay */
+ mtctr r3
+log_2:
+ WATCHDOG_RESET /* this keeps dog from barking, */
+ /* and takes time */
+ bdnz log_2 /* loop till time expires */
+
+ /* restore stack and return */
+ lwz r0, +20(r1) /* Get saved link register */
+ lwz r14, +12(r1) /* restore r14 */
+ mtlr r0 /* Restore link register */
+ addi r1, r1, +16 /* Remove frame from stack */
+ blr /* Return to calling function */
+
+/*******************************************************************
+ * temp_uart_init
+ * Temporary UART initialization routine
+ * Sets up UART0 to run at 9600N81 off of the internal clock.
+ * R3-R4 are used.
+ ******************************************************************/
+temp_uart_init:
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -8(r1) /* Save back chain and move SP */
+ stw r0, +12(r1) /* Save link register */
+
+ addis r3, 0, 0xef60
+ ori r3, r3, 0x0303 /* r3 = UART0_LCR */
+ addi r4, 0, 0x83 /* n81 format, divisor regs enabled */
+ stb r4, 0(r3)
+
+ /* set baud rate to use internal clock,
+ baud = (200e6/16)/31/42 = 9600 */
+
+ addis r3, 0, 0xef60 /* Address of baud divisor reg */
+ ori r3, r3, 0x0300 /* UART0_DLM */
+ addi r4, 0, +42 /* uart baud divisor LSB = 93 */
+ stb r4, 0(r3) /* baud = (200 /16)/14/93 */
+
+ addi r3, r3, 0x0001 /* uart baud divisor addr */
+ addi r4, 0, 0
+ stb r4, 0(r3) /* Divisor Latch MSB = 0 */
+
+ addis r3, 0, 0xef60
+ ori r3, r3, 0x0303 /* r3 = UART0_LCR */
+ addi r4, 0, 0x03 /* n81 format, tx/rx regs enabled */
+ stb r4, 0(r3)
+
+ /* output a few line feeds */
+ addi r3, 0, '\n' /* load line feed */
+ bl post_putc /* output the char */
+ addi r3, 0, '\n' /* load line feed */
+ bl post_putc /* output the char */
+
+ /* restore stack and return */
+ lwz r0, +12(r1) /* Get saved link register */
+ mtlr r0 /* Restore link register */
+ addi r1, r1, +8 /* Remove frame from stack */
+ blr /* Return to calling function */
+
+/**********************************************************************
+ ** post_putc
+ ** outputs charactor in R3
+ ** r3 returns the error code ( -1 if there is an error )
+ *********************************************************************/
+
+post_putc:
+
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -20(r1) /* Save back chain and move SP */
+ stw r0, +24(r1) /* Save link register */
+ stmw r29, 8(r1) /* save r29 - r31 on stack
+ r31 - uart base address
+ r30 - delay counter
+ r29 - scratch reg */
+
+ addis r31, 0, 0xef60 /* Point to uart base */
+ ori r31, r31, 0x0300
+ addis r30, 0, 152 /* Load about 10,000,000 ticks. */
+pputc_lp:
+ lbz r29, 5(r31) /* Read Line Status Register */
+ andi. r29, r29, 0x20 /* Check THRE status */
+ bne thre_set /* Branch if FIFO empty */
+ addic. r30, r30, -1 /* Decrement and check if empty. */
+ bne pputc_lp /* Try, try again */
+ addi r3, 0, -1 /* Load error code for timeout */
+ b pputc_done /* Bail out with error code set */
+thre_set:
+ stb r3, 0(r31) /* Store character to UART */
+ addi r3, 0, 0 /* clear error code */
+pputc_done:
+ lmw r29, 8(r1) /*restore r29 - r31 from stack */
+ lwz r0, +24(r1) /* Get saved link register */
+ addi r1, r1, +20 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+
+
+/****************************************************************
+ post_puts
+ Accepts a null-terminated string pointed to by R3
+ Outputs to the serial port until 0x00 is found.
+ r3 returns the error code ( -1 if there is an error )
+*****************************************************************/
+post_puts:
+
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -12(r1) /* Save back chain and move SP */
+ stw r0, +16(r1) /* Save link register */
+ stw r31, 8(r1) /* save r31 - char pointer */
+
+ addi r31, r3, 0 /* move pointer to R31 */
+pputs_nxt:
+ lbz r3, 0(r31) /* Get next character */
+ addic. r3, r3, 0 /* Check for zero */
+ beq pputs_term /* bail out if zero */
+ bl post_putc /* output the char */
+ addic. r3, r3, 0 /* check for error */
+ bne pputs_err
+ addi r31, r31, 1 /* point to next char */
+ b pputs_nxt /* loop till term */
+pputs_err:
+ addi r3, 0, -1 /* set error code */
+ b pputs_end /* were outa here */
+pputs_term:
+ addi r3, 0, 1 /* set success code */
+ /* restore stack and return */
+pputs_end:
+ lwz r31, 8(r1) /* restore r27 - r31 from stack */
+ lwz r0, +16(r1) /* Get saved link register */
+ addi r1, r1, +12 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
+
+
+/********************************************************************
+ ***** disp_hex
+ ***** Routine to display a hex value from a register.
+ ***** R3 is value to display
+ ***** R4 is number of nibbles to display ie 2 for byte 8 for (long)word
+ ***** Returns -1 in R3 if there is an error ( ie serial port hangs )
+ ***** Returns 0 in R3 if no error
+ *******************************************************************/
+disp_hex:
+ /* save the return info on stack */
+ mflr r0 /* Get link register */
+ stwu r1, -16(r1) /* Save back chain and move SP */
+ stw r0, +20(r1) /* Save link register */
+ stmw r30, 8(r1) /* save r30 - r31 on stack */
+ /* r31 output char */
+ /* r30 uart base address */
+ addi r30, 0, 8 /* Go through 8 nibbles. */
+ addi r31, r3, 0
+pputh_nxt:
+ rlwinm r31, r31, 4, 0, 31 /* Rotate next nibble into position */
+ andi. r3, r31, 0x0f /* Get nibble. */
+ addi r3, r3, 0x30 /* Add zero's ASCII code. */
+ cmpwi r3, 0x03a
+ blt pputh_out
+ addi r3, r3, 0x07 /* 0x27 for lower case. */
+pputh_out:
+ cmpw r30, r4
+ bgt pputh_skip
+ bl post_putc
+ addic. r3, r3, 0 /* check for error */
+ bne pputh_err
+pputh_skip:
+ addic. r30, r30, -1
+ bne pputh_nxt
+ xor r3, r3, r3 /* Clear error code */
+ b pputh_done
+pputh_err:
+ addi r3, 0, -1 /* set error code */
+pputh_done:
+ /* restore stack and return */
+ lmw r30, 8(r1) /* restore r30 - r31 from stack */
+ lwz r0, +20(r1) /* Get saved link register */
+ addi r1, r1, +16 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
diff --git a/board/w7o/post2.c b/board/w7o/post2.c
new file mode 100644
index 0000000..76b6597
--- /dev/null
+++ b/board/w7o/post2.c
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
+ * and
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <rtc.h>
+#include "errors.h"
+#include "dtt.h"
+
+/* for LM75 DTT POST test */
+#define DTT_READ_TEMP 0x0
+#define DTT_CONFIG 0x1
+#define DTT_TEMP_HYST 0x2
+#define DTT_TEMP_SET 0x3
+
+#if defined(CONFIG_RTC_M48T35A)
+void rtctest(void)
+{
+ volatile uchar *tchar = (uchar*)(CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 9);
+ struct rtc_time tmp;
+
+ /* set up led code for RTC tests */
+ log_stat(ERR_RTCG);
+
+ /*
+ * Do RTC battery test. The first write after power up
+ * fails if battery is low.
+ */
+ *tchar = 0xaa;
+ if ((*tchar ^ 0xaa) != 0x0) log_warn(ERR_RTCBAT);
+ *tchar = 0x55; /* Reset test address */
+
+ /*
+ * Now lets check the validity of the values in the RTC.
+ */
+ rtc_get(&tmp);
+ if ((tmp.tm_sec < 0) | (tmp.tm_sec > 59) |
+ (tmp.tm_min < 0) | (tmp.tm_min > 59) |
+ (tmp.tm_hour < 0) | (tmp.tm_hour > 23) |
+ (tmp.tm_mday < 1 ) | (tmp.tm_mday > 31) |
+ (tmp.tm_mon < 1 ) | (tmp.tm_mon > 12) |
+ (tmp.tm_year < 2000) | (tmp.tm_year > 2500) |
+ (tmp.tm_wday < 1 ) | (tmp.tm_wday > 7)) {
+ log_warn(ERR_RTCTIM);
+ rtc_reset();
+ }
+
+ /*
+ * Now lets do a check to see if the NV RAM is there.
+ */
+ *tchar = 0xaa;
+ if ((*tchar ^ 0xaa) != 0x0) log_err(ERR_RTCVAL);
+ *tchar = 0x55; /* Reset test address */
+
+} /* rtctest() */
+#endif /* CONFIG_RTC_M48T35A */
+
+
+#ifdef CONFIG_DTT_LM75
+int dtt_test(int sensor)
+{
+ short temp, trip, hyst;
+
+ /* get values */
+ temp = dtt_read(sensor, DTT_READ_TEMP) / 256;
+ trip = dtt_read(sensor, DTT_TEMP_SET) / 256;
+ hyst = dtt_read(sensor, DTT_TEMP_HYST) / 256;
+
+ /* check values */
+ if ((hyst != (CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS)) ||
+ (trip != CONFIG_SYS_DTT_MAX_TEMP) ||
+ (temp < CONFIG_SYS_DTT_LOW_TEMP) || (temp > CONFIG_SYS_DTT_MAX_TEMP))
+ return 1;
+
+ return 0;
+} /* dtt_test() */
+#endif /* CONFIG_DTT_LM75 */
+
+/*****************************************/
+
+void post2(void)
+{
+#if defined(CONFIG_RTC_M48T35A)
+ rtctest();
+#endif /* CONFIG_RTC_M48T35A */
+
+#ifdef CONFIG_DTT_LM75
+ log_stat(ERR_TempG);
+ if(dtt_test(2) != 0) log_warn(ERR_Ttest0);
+ if(dtt_test(4) != 0) log_warn(ERR_Ttest1);
+#endif /* CONFIG_DTT_LM75 */
+} /* post2() */
diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug
new file mode 100644
index 0000000..5740efb
--- /dev/null
+++ b/board/w7o/u-boot.lds.debug
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ lib/vsprintf.o (.text)
+ lib/crc32.o (.text)
+ arch/powerpc/lib/extable.o (.text)
+
+ common/env_embedded.o(.text)
+
+ *(.text)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/w7o/vpd.c b/board/w7o/vpd.c
new file mode 100644
index 0000000..fbcc394
--- /dev/null
+++ b/board/w7o/vpd.c
@@ -0,0 +1,412 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#if defined(VXWORKS)
+#include <stdio.h>
+#include <string.h>
+#define CONFIG_SYS_DEF_EEPROM_ADDR 0xa0
+extern char iicReadByte(char, char);
+extern ulong_t crc32(unsigned char *, unsigned long);
+#else
+#include <common.h>
+#endif
+
+#include "vpd.h"
+
+/*
+ * vpd_reader() - reads VPD data from I2C EEPROMS.
+ * returns pointer to buffer or NULL.
+ */
+static unsigned char *vpd_reader(unsigned char *buf, unsigned dev_addr,
+ unsigned off, unsigned count)
+{
+ unsigned offset = off; /* Calculated offset */
+
+ /*
+ * The main board EEPROM contains
+ * SDRAM SPD in the first 128 bytes,
+ * so skew the offset.
+ */
+ if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR)
+ offset += SDRAM_SPD_DATA_SIZE;
+
+ /* Try to read the I2C EEPROM */
+#if defined(VXWORKS)
+ {
+ int i;
+
+ for (i = 0; i < count; ++i)
+ buf[i] = iicReadByte(dev_addr, offset + i);
+ }
+#else
+ if (eeprom_read(dev_addr, offset, buf, count)) {
+ printf("Failed to read %d bytes from VPD EEPROM 0x%x @ 0x%x\n",
+ count, dev_addr, offset);
+ return NULL;
+ }
+#endif
+
+ return buf;
+}
+
+
+/*
+ * vpd_get_packet() - returns next VPD packet or NULL.
+ */
+static vpd_packet_t *vpd_get_packet(vpd_packet_t * vpd_packet)
+{
+ vpd_packet_t *packet = vpd_packet;
+
+ if (packet != NULL) {
+ if (packet->identifier == VPD_PID_TERM)
+ return NULL;
+ else
+ packet = (vpd_packet_t *) ((char *) packet +
+ packet->size + 2);
+ }
+
+ return packet;
+}
+
+
+/*
+ * vpd_find_packet() - Locates and returns the specified
+ * VPD packet or NULL on error.
+ */
+static vpd_packet_t *vpd_find_packet(vpd_t * vpd, unsigned char ident)
+{
+ vpd_packet_t *packet = (vpd_packet_t *) &vpd->packets;
+
+ /* Guaranteed illegal */
+ if (ident == VPD_PID_GI)
+ return NULL;
+
+ /* Scan tuples looking for a match */
+ while ((packet->identifier != ident) &&
+ (packet->identifier != VPD_PID_TERM))
+ packet = vpd_get_packet(packet);
+
+ /* Did we find it? */
+ if ((packet->identifier) && (packet->identifier != ident))
+ return NULL;
+ return packet;
+}
+
+
+/*
+ * vpd_is_valid() - Validates contents of VPD data
+ * in I2C EEPROM. Returns 1 for
+ * success or 0 for failure.
+ */
+static int vpd_is_valid(unsigned dev_addr, unsigned char *buf)
+{
+ unsigned num_bytes;
+ vpd_packet_t *packet;
+ vpd_t *vpd = (vpd_t *) buf;
+ unsigned short stored_crc16, calc_crc16 = 0xffff;
+
+ /* Check Eyecatcher */
+ if (strncmp
+ ((char *) (vpd->header.eyecatcher), VPD_EYECATCHER,
+ VPD_EYE_SIZE) != 0) {
+ unsigned offset = 0;
+
+ if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR)
+ offset += SDRAM_SPD_DATA_SIZE;
+ printf("Error: VPD EEPROM 0x%x corrupt @ 0x%x\n", dev_addr,
+ offset);
+
+ return 0;
+ }
+
+ /* Check Length */
+ if (vpd->header.size > VPD_MAX_EEPROM_SIZE) {
+ printf("Error: VPD EEPROM 0x%x contains bad size 0x%x\n",
+ dev_addr, vpd->header.size);
+ return 0;
+ }
+
+ /* Now find the termination packet */
+ packet = vpd_find_packet(vpd, VPD_PID_TERM);
+ if (packet == NULL) {
+ printf("Error: VPD EEPROM 0x%x missing termination packet\n",
+ dev_addr);
+ return 0;
+ }
+
+ /* Calculate data size */
+ num_bytes = (unsigned long) ((unsigned char *) packet -
+ (unsigned char *) vpd +
+ sizeof(vpd_packet_t));
+
+ /* Find stored CRC and clear it */
+ packet = vpd_find_packet(vpd, VPD_PID_CRC);
+ if (packet == NULL) {
+ printf("Error: VPD EEPROM 0x%x missing CRC\n", dev_addr);
+ return 0;
+ }
+ memcpy(&stored_crc16, packet->data, sizeof(ushort));
+ memset(packet->data, 0, sizeof(ushort));
+
+ /* OK, lets calculate the CRC and check it */
+#if defined(VXWORKS)
+ calc_crc16 = (0xffff & crc32(buf, num_bytes));
+#else
+ calc_crc16 = (0xffff & crc32(0, buf, num_bytes));
+#endif
+ /* Now restore the CRC */
+ memcpy(packet->data, &stored_crc16, sizeof(ushort));
+ if (stored_crc16 != calc_crc16) {
+ printf("Error: VPD EEPROM 0x%x has bad CRC 0x%x\n",
+ dev_addr, stored_crc16);
+ return 0;
+ }
+
+ return 1;
+}
+
+
+/*
+ * size_ok() - Check to see if packet size matches
+ * size of data we want. Returns 1 for
+ * good match or 0 for failure.
+ */
+static int size_ok(vpd_packet_t *packet, unsigned long size)
+{
+ if (packet->size != size) {
+ printf("VPD Packet 0x%x corrupt.\n", packet->identifier);
+ return 0;
+ }
+ return 1;
+}
+
+
+/*
+ * strlen_ok() - Check to see if packet size matches
+ * strlen of the string we want to populate.
+ * Returns 1 for valid length or 0 for failure.
+ */
+static int strlen_ok(vpd_packet_t *packet, unsigned long length)
+{
+ if (packet->size >= length) {
+ printf("VPD Packet 0x%x corrupt.\n", packet->identifier);
+ return 0;
+ }
+ return 1;
+}
+
+
+/*
+ * get_vpd_data() - populates the passed VPD structure 'vpdInfo'
+ * with data obtained from the specified
+ * I2C EEPROM 'dev_addr'. Returns 0 for
+ * success or 1 for failure.
+ */
+int vpd_get_data(unsigned char dev_addr, VPD *vpdInfo)
+{
+ unsigned char buf[VPD_EEPROM_SIZE];
+ vpd_t *vpd = (vpd_t *) buf;
+ vpd_packet_t *packet;
+
+ if (vpdInfo == NULL)
+ return 1;
+
+ /*
+ * Fill vpdInfo with 0s to blank out
+ * unused fields, fill vpdInfo->ethAddrs
+ * with all 0xffs so that other's code can
+ * determine how many real Ethernet addresses
+ * there are. OUIs starting with 0xff are
+ * broadcast addresses, and would never be
+ * permantely stored.
+ */
+ memset((void *) vpdInfo, 0, sizeof(VPD));
+ memset((void *) &vpdInfo->ethAddrs, 0xff, sizeof(vpdInfo->ethAddrs));
+ vpdInfo->_devAddr = dev_addr;
+
+ /* Read the minimum size first */
+ if (vpd_reader(buf, dev_addr, 0, VPD_EEPROM_SIZE) == NULL)
+ return 1;
+
+ /* Check validity of VPD data */
+ if (!vpd_is_valid(dev_addr, buf)) {
+ printf("VPD Data is INVALID!\n");
+ return 1;
+ }
+
+ /*
+ * Walk all the packets and populate
+ * the VPD info structure.
+ */
+ packet = (vpd_packet_t *) &vpd->packets;
+ do {
+ switch (packet->identifier) {
+ case VPD_PID_GI:
+ printf("Error: Illegal VPD value\n");
+ break;
+ case VPD_PID_PID:
+ if (strlen_ok(packet, MAX_PROD_ID)) {
+ strncpy(vpdInfo->productId,
+ (char *) (packet->data),
+ packet->size);
+ }
+ break;
+ case VPD_PID_REV:
+ if (size_ok(packet, sizeof(char)))
+ vpdInfo->revisionId = *packet->data;
+ break;
+ case VPD_PID_SN:
+ if (size_ok(packet, sizeof(unsigned long))) {
+ memcpy(&vpdInfo->serialNum,
+ packet->data,
+ sizeof(unsigned long));
+ }
+ break;
+ case VPD_PID_MANID:
+ if (size_ok(packet, sizeof(unsigned char)))
+ vpdInfo->manuID = *packet->data;
+ break;
+ case VPD_PID_PCO:
+ if (size_ok(packet, sizeof(unsigned long))) {
+ memcpy(&vpdInfo->configOpt,
+ packet->data,
+ sizeof(unsigned long));
+ }
+ break;
+ case VPD_PID_SYSCLK:
+ if (size_ok(packet, sizeof(unsigned long)))
+ memcpy(&vpdInfo->sysClk,
+ packet->data,
+ sizeof(unsigned long));
+ break;
+ case VPD_PID_SERCLK:
+ if (size_ok(packet, sizeof(unsigned long)))
+ memcpy(&vpdInfo->serClk,
+ packet->data,
+ sizeof(unsigned long));
+ break;
+ case VPD_PID_FLASH:
+ if (size_ok(packet, 9)) { /* XXX - hardcoded,
+ padding in struct */
+ memcpy(&vpdInfo->flashCfg, packet->data, 9);
+ }
+ break;
+ case VPD_PID_ETHADDR:
+ memcpy(vpdInfo->ethAddrs, packet->data, packet->size);
+ break;
+ case VPD_PID_POTS:
+ if (size_ok(packet, sizeof(char)))
+ vpdInfo->numPOTS = (unsigned) *packet->data;
+ break;
+ case VPD_PID_DS1:
+ if (size_ok(packet, sizeof(char)))
+ vpdInfo->numDS1 = (unsigned) *packet->data;
+ case VPD_PID_GAL:
+ case VPD_PID_CRC:
+ case VPD_PID_TERM:
+ break;
+ default:
+ printf("Warning: Found unknown VPD packet ID 0x%x\n",
+ packet->identifier);
+ break;
+ }
+ } while ((packet = vpd_get_packet(packet)));
+
+ return 0;
+}
+
+
+/*
+ * vpd_init() - Initialize default VPD environment
+ */
+int vpd_init(unsigned char dev_addr)
+{
+ return 0;
+}
+
+
+/*
+ * vpd_print() - Pretty print the VPD data.
+ */
+void vpd_print(VPD *vpdInfo)
+{
+ const char *const sp = "";
+ const char *const sfmt = "%4s%-20s: \"%s\"\n";
+ const char *const cfmt = "%4s%-20s: '%c'\n";
+ const char *const dfmt = "%4s%-20s: %ld\n";
+ const char *const hfmt = "%4s%-20s: %08lX\n";
+ const char *const dsfmt = "%4s%-20s: %d\n";
+ const char *const hsfmt = "%4s%-20s: %04X\n";
+ const char *const dhfmt = "%4s%-20s: %ld (%lX)\n";
+
+ printf("VPD read from I2C device: %02X\n", vpdInfo->_devAddr);
+
+ if (vpdInfo->productId[0])
+ printf(sfmt, sp, "Product ID", vpdInfo->productId);
+ else
+ printf(sfmt, sp, "Product ID", "UNKNOWN");
+
+ if (vpdInfo->revisionId)
+ printf(cfmt, sp, "Revision ID", vpdInfo->revisionId);
+
+ if (vpdInfo->serialNum)
+ printf(dfmt, sp, "Serial Number", vpdInfo->serialNum);
+
+ if (vpdInfo->manuID)
+ printf(dfmt, sp, "Manufacture ID", (long) vpdInfo->manuID);
+
+ if (vpdInfo->configOpt)
+ printf(hfmt, sp, "Configuration", vpdInfo->configOpt);
+
+ if (vpdInfo->sysClk)
+ printf(dhfmt, sp, "System Clock", vpdInfo->sysClk,
+ vpdInfo->sysClk);
+
+ if (vpdInfo->serClk)
+ printf(dhfmt, sp, "Serial Clock", vpdInfo->serClk,
+ vpdInfo->serClk);
+
+ if (vpdInfo->numPOTS)
+ printf(dfmt, sp, "Number of POTS lines", vpdInfo->numPOTS);
+
+ if (vpdInfo->numDS1)
+ printf(dfmt, sp, "Number of DS1s", vpdInfo->numDS1);
+
+ /* Print Ethernet Addresses */
+ if (vpdInfo->ethAddrs[0][0] != 0xff) {
+ int i, j;
+
+ printf("%4sEtherNet Address(es): ", sp);
+ for (i = 0; i < MAX_ETH_ADDRS; i++) {
+ if (vpdInfo->ethAddrs[i][0] != 0xff) {
+ for (j = 0; j < 6; j++) {
+ printf("%02X",
+ vpdInfo->ethAddrs[i][j]);
+ if (((j + 1) % 6) != 0)
+ printf(":");
+ else
+ printf(" ");
+ }
+ if (((i + 1) % 3) == 0)
+ printf("\n%24s: ", sp);
+ }
+ }
+ printf("\n");
+ }
+
+ if (vpdInfo->flashCfg.mfg && vpdInfo->flashCfg.dev) {
+ printf("Main Flash Configuration:\n");
+ printf(hsfmt, sp, "Manufacture ID", vpdInfo->flashCfg.mfg);
+ printf(hsfmt, sp, "Device ID", vpdInfo->flashCfg.dev);
+ printf(dsfmt, sp, "Device Width", vpdInfo->flashCfg.devWidth);
+ printf(dsfmt, sp, "Num. Devices", vpdInfo->flashCfg.numDevs);
+ printf(dsfmt, sp, "Num. Columns", vpdInfo->flashCfg.numCols);
+ printf(dsfmt, sp, "Column Width", vpdInfo->flashCfg.colWidth);
+ printf(dsfmt, sp, "WE Data Width",
+ vpdInfo->flashCfg.weDataWidth);
+ }
+}
diff --git a/board/w7o/vpd.h b/board/w7o/vpd.h
new file mode 100644
index 0000000..2395b18
--- /dev/null
+++ b/board/w7o/vpd.h
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _VPD_H_
+#define _VPD_H_
+
+/*
+ * Main Flash Configuration.
+ */
+typedef struct flashCfg_s {
+ unsigned short mfg; /* Manufacture ID */
+ unsigned short dev; /* Device ID */
+ unsigned char devWidth; /* Device Width */
+ unsigned char numDevs; /* Number of devices */
+ unsigned char numCols; /* Number of columns */
+ unsigned char colWidth; /* Width of a column */
+ unsigned char weDataWidth; /* Write/Erase Data Width */
+} flashCfg_t;
+
+/*
+ * Vital Product Data - VPD
+ */
+#define MAX_PROD_ID 15
+#define MAX_ETH_ADDRS 10
+typedef unsigned char EthAddr[6];
+typedef struct vpd {
+ unsigned char _devAddr; /* Device address during read */
+ char productId[MAX_PROD_ID]; /* Product ID */
+ char revisionId; /* Revision ID as a char */
+ unsigned long serialNum; /* Serial number */
+ unsigned char manuID; /* Manufact ID - byte int */
+ unsigned long configOpt; /* Config Option - bit field */
+ unsigned long sysClk; /* System clock in Hertz */
+ unsigned long serClk; /* Ext. clock in Hertz */
+ flashCfg_t flashCfg; /* Flash configuration */
+ unsigned long numPOTS; /* Number of POTS lines */
+ unsigned long numDS1; /* Number of DS1 circuits */
+ EthAddr ethAddrs[MAX_ETH_ADDRS]; /* Ethernet MAC, 1st = craft */
+} VPD;
+
+
+#define VPD_MAX_EEPROM_SIZE 512 /* Max size VPD EEPROM */
+#define SDRAM_SPD_DATA_SIZE 128 /* Size SPD in VPD EEPROM */
+
+/*
+ * PIDs - Packet Identifiers
+ */
+#define VPD_PID_GI 0x0 /* Guaranted Illegal */
+#define VPD_PID_PID 0x1 /* Product Identifier */
+#define VPD_PID_REV 0x2 /* Product Revision */
+#define VPD_PID_SN 0x3 /* Serial Number */
+#define VPD_PID_MANID 0x4 /* Manufacture ID */
+#define VPD_PID_PCO 0x5 /* Product configuration */
+#define VPD_PID_SYSCLK 0x6 /* System Clock */
+#define VPD_PID_SERCLK 0x7 /* Ser. Clk. Speed in Hertz */
+#define VPD_PID_CRC 0x8 /* VPD CRC */
+#define VPD_PID_FLASH 0x9 /* Flash Configuration */
+#define VPD_PID_ETHADDR 0xA /* Ethernet Address(es) */
+#define VPD_PID_GAL 0xB /* Galileo Switch Config */
+#define VPD_PID_POTS 0xC /* Number of POTS Lines */
+#define VPD_PID_DS1 0xD /* Number of DS1s */
+#define VPD_PID_TERM 0xFF /* Termination packet */
+
+/*
+ * VPD - Eyecatcher/Magic
+ */
+#define VPD_EYECATCHER "W7O"
+#define VPD_EYE_SIZE 3
+typedef struct vpd_header {
+ unsigned char eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "W7O" */
+ unsigned short size __attribute__((packed)); /* size of EEPROM */
+} vpd_header_t;
+
+
+#define VPD_DATA_SIZE (VPD_MAX_EEPROM_SIZE - SDRAM_SPD_DATA_SIZE - \
+ sizeof(vpd_header_t))
+typedef struct vpd_s {
+ vpd_header_t header;
+ unsigned char packets[VPD_DATA_SIZE];
+} vpd_t;
+
+typedef struct vpd_packet {
+ unsigned char identifier;
+ unsigned char size;
+ unsigned char data[1];
+} vpd_packet_t;
+
+/*
+ * VPD configOpt bit mask
+ */
+#define VPD_HAS_BBRAM 0x1 /* Battery backed SRAM */
+#define VPD_HAS_RTC 0x2 /* Battery backed RTC */
+#define VPD_HAS_EXT_SER_CLK 0x4 /* External serial clock */
+#define VPD_HAS_SER_TRANS_1 0x8 /* COM1 transceiver */
+#define VPD_HAS_SER_TRANS_2 0x10 /* COM2 transceiver */
+#define VPD_HAS_CRAFT_PHY 0x20 /* CRAFT Ethernet */
+#define VPD_HAS_DTT_1 0x40 /* I2C Digital therm. #1 */
+#define VPD_HAS_DTT_2 0x80 /* I2C Digital therm. #2 */
+#define VPD_HAS_1000_UP_LASER 0x100 /* GMM - 1000Mbit Uplink */
+#define VPD_HAS_70KM_UP_LASER 0x200 /* CMM - 70KM Uplink laser */
+#define VPD_HAS_2_UPLINKS 0x400 /* CMM - 2 uplink lasers */
+#define VPD_HAS_FPGA 0x800 /* Has 1 or more FPGAs */
+#define VPD_HAS_DFA 0x1000 /* CLM - Has 2 Fiber Inter. */
+#define VPD_HAS_GAL_SWITCH 0x2000 /* GMM - Has a Gal switch */
+#define VPD_HAS_POTS_LINES 0x4000 /* GMM - Has POTS lines */
+#define VPD_HAS_DS1_CHANNELS 0x8000 /* GMM - Has DS1 channels */
+#define VPD_HAS_CABLE_RETURN 0x10000 /* GBM/GBR - Cable ret. path */
+
+#define VPD_EEPROM_SIZE (256 - SDRAM_SPD_DATA_SIZE) /* Size EEPROM */
+
+extern int vpd_get_data(unsigned char dev_addr, VPD *vpd);
+extern void vpd_print(VPD *vpdInfo);
+
+#endif /* _VPD_H_ */
diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c
new file mode 100644
index 0000000..afbbaf5
--- /dev/null
+++ b/board/w7o/w7o.c
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include "w7o.h"
+#include <asm/processor.h>
+
+#include "vpd.h"
+#include "errors.h"
+#include <watchdog.h>
+
+unsigned long get_dram_size (void);
+void sdram_init(void);
+
+/* ------------------------------------------------------------------------- */
+
+int board_early_init_f (void)
+{
+#if defined(CONFIG_W7OLMG)
+ /*
+ * Setup GPIO pins - reset devices.
+ */
+ out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
+ out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
+ out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
+ */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
+ INT0 highest priority */
+
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+#elif defined(CONFIG_W7OLMC)
+ /*
+ * Setup GPIO pins
+ */
+ out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
+ out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
+ out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
+
+ /*
+ * IRQ 0-15 405GP internally generated; active high; level sensitive
+ * IRQ 16 405GP internally generated; active low; level sensitive
+ * IRQ 17-24 RESERVED
+ * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
+ * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
+ * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
+ * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
+ * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
+ * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
+ */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
+ mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,
+ INT0 highest priority */
+
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+
+#else /* Unknown */
+# error "Unknown W7O board configuration"
+#endif
+
+ WATCHDOG_RESET (); /* Reset the watchdog */
+ temp_uart_init (); /* init the uart for debug */
+ WATCHDOG_RESET (); /* Reset the watchdog */
+ test_led (); /* test the LEDs */
+ test_sdram (get_dram_size ()); /* test the dram */
+ log_stat (ERR_POST1); /* log status,post1 complete */
+ return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+ VPD vpd;
+
+ puts ("Board: ");
+
+ /* VPD data present in I2C EEPROM */
+ if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) {
+ /*
+ * Known board type.
+ */
+ if (vpd.productId[0] &&
+ ((strncmp (vpd.productId, "GMM", 3) == 0) ||
+ (strncmp (vpd.productId, "CMM", 3) == 0))) {
+
+ /* Output board information on startup */
+ printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
+ return (0);
+ }
+ }
+
+ puts ("### Unknown HW ID - assuming NOTHING\n");
+ return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+phys_size_t initdram (int board_type)
+{
+ /*
+ * ToDo: Move the asm init routine sdram_init() to this C file,
+ * or even better use some common ppc4xx code available
+ * in arch/powerpc/cpu/ppc4xx
+ */
+ sdram_init();
+
+ return get_dram_size ();
+}
+
+unsigned long get_dram_size (void)
+{
+ int tmp, i, regs[4];
+ int size = 0;
+
+ /* Get bank Size registers */
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */
+ regs[0] = mfdcr (SDRAM0_CFGDATA);
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */
+ regs[1] = mfdcr (SDRAM0_CFGDATA);
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */
+ regs[2] = mfdcr (SDRAM0_CFGDATA);
+
+ mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */
+ regs[3] = mfdcr (SDRAM0_CFGDATA);
+
+ /* compute the size, add each bank if enabled */
+ for (i = 0; i < 4; i++) {
+ if (regs[i] & 0x0001) { /* if enabled, */
+ tmp = ((regs[i] >> (31 - 14)) & 0x7); /* get size bits */
+ tmp = 0x400000 << tmp; /* Size bits X 4MB = size */
+ size += tmp;
+ }
+ }
+
+ return size;
+}
+
+int misc_init_f (void)
+{
+ return 0;
+}
+
+static void w7o_env_init (VPD * vpd)
+{
+ /*
+ * Read VPD
+ */
+ if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0)
+ return;
+
+ /*
+ * Known board type.
+ */
+ if (vpd->productId[0] &&
+ ((strncmp (vpd->productId, "GMM", 3) == 0) ||
+ (strncmp (vpd->productId, "CMM", 3) == 0))) {
+ char buf[30];
+ char *eth;
+ char *serial = getenv ("serial#");
+ char *ethaddr = getenv ("ethaddr");
+
+ /* Set 'serial#' envvar if serial# isn't set */
+ if (!serial) {
+ sprintf (buf, "%s-%ld", vpd->productId,
+ vpd->serialNum);
+ setenv ("serial#", buf);
+ }
+
+ /* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
+ eth = (char *)(vpd->ethAddrs[0]);
+ if (ethaddr
+ && (strcmp(ethaddr, __stringify(CONFIG_ETHADDR)) == 0)) {
+ /* Now setup ethaddr */
+ sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+ eth[0], eth[1], eth[2], eth[3], eth[4],
+ eth[5]);
+ setenv ("ethaddr", buf);
+ }
+ }
+} /* w7o_env_init() */
+
+
+int misc_init_r (void)
+{
+ VPD vpd; /* VPD information */
+
+#if defined(CONFIG_W7OLMG)
+ unsigned long greg; /* GPIO Register */
+
+ greg = in32 (PPC405GP_GPIO0_OR);
+
+ /*
+ * XXX - Unreset devices - this should be moved into VxWorks driver code
+ */
+ greg |= 0x41800000L; /* SAM, PHY, Galileo */
+
+ out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */
+#endif /* CONFIG_W7OLMG */
+
+ /*
+ * Initialize W7O environment variables
+ */
+ w7o_env_init (&vpd);
+
+ /*
+ * Initialize the FPGA(s).
+ */
+ if (init_fpga () == 0)
+ test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
+
+ /* More POST testing. */
+ post2 ();
+
+ /* Done with hardware initialization and POST. */
+ log_stat (ERR_POSTOK);
+
+ /* Call silly, fail safe boot init routine */
+ init_fsboot ();
+
+ return (0);
+}
diff --git a/board/w7o/w7o.h b/board/w7o/w7o.h
new file mode 100644
index 0000000..9ef682c
--- /dev/null
+++ b/board/w7o/w7o.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _W7O_H_
+#define _W7O_H_
+#include <config.h>
+
+/* AMCC 405GP PowerPC GPIO registers */
+#define PPC405GP_GPIO0_OR 0xef600700L /* GPIO Output */
+#define PPC405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */
+#define PPC405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */
+#define PPC405GP_GPIO0_IR 0xef60071cL /* GPIO Input */
+
+/* LMG FPGA <=> CPU GPIO signals */
+#define LMG_XCV_INIT 0x10000000L
+#define LMG_XCV_PROG 0x04000000L
+#define LMG_XCV_DONE 0x00400000L
+#define LMG_XCV_CNFG_0 0x08000000L
+#define LMG_XCV_IRQ_0 0x0L
+
+/* LMC FPGA <=> CPU GPIO signals */
+#define LMC_XCV_INIT 0x00800000L
+#define LMC_XCV_PROG 0x40000000L
+#define LMC_XCV_DONE 0x01000000L
+#define LMC_XCV_CNFG_0 0x00004000L /* Shared with IRQ 0 */
+#define LMC_XCV_CNFG_1 0x00002000L /* Shared with IRQ 1 */
+#define LMC_XCV_CNFG_2 0x00001000L /* Shared with IRQ 2 */
+#define LMC_XCV_IRQ_0 0x00080000L /* Shared with GPIO 17 */
+#define LMC_XCV_IRQ_1 0x00040000L /* Shared with GPIO 18 */
+#define LMC_XCV_IRQ_3 0x00020000L /* Shared tiwht GPIO 19 */
+
+
+/*
+ * Setup FPGA <=> GPIO mappings
+ */
+#if defined(CONFIG_W7OLMG)
+# define GPIO_XCV_INIT LMG_XCV_INIT
+# define GPIO_XCV_PROG LMG_XCV_PROG
+# define GPIO_XCV_DONE LMG_XCV_DONE
+# define GPIO_XCV_CNFG LMG_XCV_CNFG_0
+# define GPIO_XCV_IRQ LMG_XCV_IRQ_0
+# define GPIO_GPIO_1 0x40000000L
+# define GPIO_GPIO_6 0x02000000L
+# define GPIO_GPIO_7 0x01000000L
+# define GPIO_GPIO_8 0x00800000L
+#elif defined(CONFIG_W7OLMC)
+# define GPIO_XCV_INIT LMC_XCV_INIT
+# define GPIO_XCV_PROG LMC_XCV_PROG
+# define GPIO_XCV_DONE LMC_XCV_DONE
+# define GPIO_XCV_CNFG LMC_XCV_CNFG_0
+# define GPIO_XCV_IRQ LMC_XCV_IRQ_0
+#else
+# error "Unknown W7O board configuration"
+#endif
+
+/* Power On Self Tests */
+extern void post2(void);
+extern int test_led(void);
+extern int test_sdram(unsigned long size);
+extern void test_fpga(unsigned short *daddr);
+
+/* FGPA */
+extern int init_fpga(void);
+
+/* Misc */
+extern int temp_uart_init(void);
+extern void init_fsboot(void);
+
+#endif /* _W7O_H_ */
diff --git a/board/w7o/watchdog.c b/board/w7o/watchdog.c
new file mode 100644
index 0000000..ff1b212
--- /dev/null
+++ b/board/w7o/watchdog.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * W7O board level hardware watchdog.
+ */
+#include <common.h>
+#include <config.h>
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+
+void hw_watchdog_reset(void)
+{
+ volatile ushort *hwd = (ushort *)(CONFIG_SYS_W7O_EBC_PB7CR & 0xfff00000);
+
+ /*
+ * Read the LMG's hwd register and toggle the
+ * watchdog bit to reset it. On the LMC, just
+ * reading it is enough, but toggling the bit
+ * doen't hurt either.
+ */
+ *hwd = *hwd ^ 0x8000;
+
+} /* hw_watchdog_reset() */
+
+#endif /* CONFIG_HW_WATCHDOG */
diff --git a/board/wandboard/Kconfig b/board/wandboard/Kconfig
new file mode 100644
index 0000000..3928566
--- /dev/null
+++ b/board/wandboard/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_WANDBOARD
+
+config SYS_BOARD
+ default "wandboard"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "wandboard"
+
+endif
diff --git a/board/wandboard/MAINTAINERS b/board/wandboard/MAINTAINERS
new file mode 100644
index 0000000..b986980
--- /dev/null
+++ b/board/wandboard/MAINTAINERS
@@ -0,0 +1,8 @@
+WANDBOARD BOARD
+M: Fabio Estevam <fabio.estevam@freescale.com>
+S: Maintained
+F: board/wandboard/
+F: include/configs/wandboard.h
+F: configs/wandboard_dl_defconfig
+F: configs/wandboard_quad_defconfig
+F: configs/wandboard_solo_defconfig
diff --git a/board/wandboard/Makefile b/board/wandboard/Makefile
new file mode 100644
index 0000000..5b50eca
--- /dev/null
+++ b/board/wandboard/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := wandboard.o
diff --git a/board/wandboard/README b/board/wandboard/README
new file mode 100644
index 0000000..1f678e1
--- /dev/null
+++ b/board/wandboard/README
@@ -0,0 +1,45 @@
+U-Boot for Wandboard
+--------------------
+
+This file contains information for the port of U-Boot to the Wandboard.
+
+Wandboard is a development board that has three variants based on the following
+SoCs: mx6 quad, mx6 dual lite and mx6 solo.
+
+For more details about Wandboard, please refer to:
+http://www.wandboard.org/
+
+Building U-boot for Wandboard
+-----------------------------
+
+To build U-Boot for the Wandboard Dual Lite version:
+
+$ make wandboard_dl_config
+$ make
+
+To build U-Boot for the Wandboard Solo version:
+
+$ make wandboard_solo_config
+$ make
+
+To build U-Boot for the Wandboard Quad version:
+
+$ make wandboard_quad_config
+$ make
+
+Flashing U-boot into the SD card
+--------------------------------
+
+- After the 'make' command completes, the generated 'u-boot.imx' binary must be
+flashed into the SD card;
+
+$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=512 seek=2; sync
+
+(Note - the SD card node may vary, so adjust this as needed).
+
+- Insert the SD card into the slot located in the bottom of the board (same side
+as the mx6 processor)
+
+- Connect the serial cable to the host PC
+
+- Power up the board and U-boot messages will appear in the serial console.
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
new file mode 100644
index 0000000..1075c65
--- /dev/null
+++ b/board/wandboard/wandboard.c
@@ -0,0 +1,412 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014 O.S. Systems Software LTDA.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <phy.h>
+#include <input.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
+#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
+
+int dram_init(void)
+{
+ gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* Carrier MicroSD Card Detect */
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ /* SOM MicroSD Card Detect */
+ MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* AR8031 PHY Reset */
+ MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* Reset AR8031 PHY */
+ gpio_direction_output(ETH_PHY_RESET, 0);
+ udelay(500);
+ gpio_set_value(ETH_PHY_RESET, 1);
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC3_BASE_ADDR},
+ {USDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ int ret;
+ u32 index = 0;
+
+ /*
+ * Following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 SOM MicroSD
+ * mmc1 Carrier board MicroSD
+ */
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 4;
+ gpio_direction_input(USDHC3_CD_GPIO);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[1].max_bus_width = 4;
+ gpio_direction_input(USDHC1_CD_GPIO);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+struct i2c_pads_info i2c2_pad_info = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSync */
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSync */
+ MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04
+ | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm), /* Contrast */
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */
+
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
+
+ MX6_PAD_SD4_DAT2__GPIO2_IO10
+ | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_BKLEN */
+ MX6_PAD_SD4_DAT3__GPIO2_IO11
+ | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_VDDEN */
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+ return (0 == i2c_set_bus_num(dev->bus)) &&
+ (0 == i2c_probe(dev->addr));
+}
+
+static void enable_fwadapt_7wvga(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(
+ fwadapt_7wvga_pads,
+ ARRAY_SIZE(fwadapt_7wvga_pads));
+
+ gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
+ gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 1,
+ .addr = 0x10,
+ .pixfmt = IPU_PIX_FMT_RGB666,
+ .detect = detect_i2c,
+ .enable = enable_fwadapt_7wvga,
+ .mode = {
+ .name = "FWBADAPT-LCD-F07A-0102",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 33260,
+ .left_margin = 128,
+ .right_margin = 128,
+ .upper_margin = 22,
+ .lower_margin = 22,
+ .hsync_len = 1,
+ .vsync_len = 1,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ reg = readl(&mxc_ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &mxc_ccm->chsccdr);
+
+ /* Disable LCD backlight */
+ imx_iomux_v3_setup_pad(MX6_PAD_DI0_PIN4__GPIO4_IO20);
+ gpio_direction_input(IMX_GPIO_NR(4, 20));
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+
+ return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
+ return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c2_pad_info);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Wandboard\n");
+
+ return 0;
+}
diff --git a/board/woodburn/Kconfig b/board/woodburn/Kconfig
new file mode 100644
index 0000000..4699526
--- /dev/null
+++ b/board/woodburn/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_WOODBURN
+
+config SYS_BOARD
+ default "woodburn"
+
+config SYS_SOC
+ default "mx35"
+
+config SYS_CONFIG_NAME
+ default "woodburn"
+
+endif
+
+if TARGET_WOODBURN_SD
+
+config SYS_BOARD
+ default "woodburn"
+
+config SYS_SOC
+ default "mx35"
+
+config SYS_CONFIG_NAME
+ default "woodburn_sd"
+
+endif
diff --git a/board/woodburn/MAINTAINERS b/board/woodburn/MAINTAINERS
new file mode 100644
index 0000000..4fbf6bb
--- /dev/null
+++ b/board/woodburn/MAINTAINERS
@@ -0,0 +1,12 @@
+WOODBURN BOARD
+M: Stefano Babic <sbabic@denx.de>
+S: Maintained
+F: board/woodburn/
+F: include/configs/woodburn.h
+F: configs/woodburn_defconfig
+
+WOODBURN_SD BOARD
+#M: -
+S: Maintained
+F: include/configs/woodburn_sd.h
+F: configs/woodburn_sd_defconfig
diff --git a/board/woodburn/Makefile b/board/woodburn/Makefile
new file mode 100644
index 0000000..db2b2d5
--- /dev/null
+++ b/board/woodburn/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := woodburn.o
+obj-y += lowlevel_init.o
diff --git a/board/woodburn/imximage.cfg b/board/woodburn/imximage.cfg
new file mode 100644
index 0000000..ba42a5e
--- /dev/null
+++ b/board/woodburn/imximage.cfg
@@ -0,0 +1,4 @@
+BOOT_FROM sd
+
+/* DDR2 init */
+DATA 4 0xB8001010 0x00000304
diff --git a/board/woodburn/lowlevel_init.S b/board/woodburn/lowlevel_init.S
new file mode 100644
index 0000000..a9b7c1b
--- /dev/null
+++ b/board/woodburn/lowlevel_init.S
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ core_init
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ mov pc, lr
diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c
new file mode 100644
index 0000000..2744514
--- /dev/null
+++ b/board/woodburn/woodburn.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * Based on flea3.c and mx35pdk.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx35.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+#include <spl.h>
+
+#define CCM_CCMR_CONFIG 0x003F4208
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+
+/* For MMC */
+#define GPIO_MMC_CD 7
+#define GPIO_MMC_WP 8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+static void board_setup_sdram(void)
+{
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /* Initialize with default values both CSD0/1 */
+ writel(0x2000, &esdc->esdctl0);
+ writel(0x2000, &esdc->esdctl1);
+
+ mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+ 13, 10, 2, 0x8080);
+}
+
+static void setup_iomux_fec(void)
+{
+ static const iomux_v3_cfg_t fec_pads[] = {
+ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+ MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX35_PAD_FEC_COL__FEC_COL,
+ MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+ MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+ MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX35_PAD_FEC_MDC__FEC_MDC,
+ MX35_PAD_FEC_MDIO__FEC_MDIO,
+ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+ MX35_PAD_FEC_CRS__FEC_CRS,
+ MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+ MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+ MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+ MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+ MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+ MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+ };
+
+ /* setup pins for FEC */
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+int woodburn_init(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* initialize PLL and clock configuration */
+ writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+ /* Set-up RAM */
+ board_setup_sdram();
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDIO_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_I2C3_MASK,
+ &ccm->cgr1);
+
+ /* Set-up NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ /* Set pinmux for the required peripherals */
+ setup_iomux_fec();
+
+ /* setup GPIO1_4 FEC_ENABLE signal */
+ imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4);
+ gpio_direction_output(4, 1);
+ imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9);
+ gpio_direction_output(9, 1);
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+void board_init_f(ulong dummy)
+{
+ /* Set the stack pointer. */
+ asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+ /* Initialize MUX and SDRAM */
+ woodburn_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* Set global data pointer. */
+ gd = &gdata;
+
+ preloader_console_init();
+ timer_init();
+
+ board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+}
+
+#endif
+
+
+/* Booting from NOR in external mode */
+int board_early_init_f(void)
+{
+ return woodburn_init();
+}
+
+
+int board_init(void)
+{
+ struct pmic *p;
+ u32 val;
+ int ret;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ ret = pmic_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("FSL_PMIC");
+
+ /*
+ * Set switchers in Auto in NORMAL mode & STANDBY mode
+ * Setup the switcher mode for SW1 & SW2
+ */
+ pmic_reg_read(p, REG_SW_4, &val);
+ val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT)));
+ val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+ /* Set SWILIMB */
+ val |= (1 << 22);
+ pmic_reg_write(p, REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ pmic_reg_read(p, REG_SW_5, &val);
+ val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
+ (SWMODE_MASK << SWMODE3_SHIFT));
+ val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
+ (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
+ pmic_reg_write(p, REG_SW_5, val);
+
+ /* Set VGEN1 to 3.15V */
+ pmic_reg_read(p, REG_SETTING_0, &val);
+ val &= ~(VGEN1_MASK);
+ val |= VGEN1_3_15;
+ pmic_reg_write(p, REG_SETTING_0, val);
+
+ pmic_reg_read(p, REG_MODE_0, &val);
+ val |= VGEN1EN;
+ pmic_reg_write(p, REG_MODE_0, val);
+ udelay(2000);
+
+ return 0;
+}
+
+#if defined(CONFIG_FSL_ESDHC)
+struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
+
+int board_mmc_init(bd_t *bis)
+{
+ static const iomux_v3_cfg_t sdhc1_pads[] = {
+ MX35_PAD_SD1_CMD__ESDHC1_CMD,
+ MX35_PAD_SD1_CLK__ESDHC1_CLK,
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+ };
+
+ /* configure pins for SDHC1 only */
+ imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
+
+ /* MMC Card Detect on GPIO1_7 */
+ imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7);
+ gpio_direction_input(GPIO_MMC_CD);
+
+ /* MMC Write Protection on GPIO1_8 */
+ imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8);
+ gpio_direction_input(GPIO_MMC_WP);
+
+ esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+
+ return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return !gpio_get_value(GPIO_MMC_CD);
+}
+#endif
+
+u32 get_board_rev(void)
+{
+ int rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
diff --git a/board/xaeniax/Kconfig b/board/xaeniax/Kconfig
new file mode 100644
index 0000000..519e21f
--- /dev/null
+++ b/board/xaeniax/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_XAENIAX
+
+config SYS_BOARD
+ default "xaeniax"
+
+config SYS_CONFIG_NAME
+ default "xaeniax"
+
+endif
diff --git a/board/xaeniax/MAINTAINERS b/board/xaeniax/MAINTAINERS
new file mode 100644
index 0000000..44bb588
--- /dev/null
+++ b/board/xaeniax/MAINTAINERS
@@ -0,0 +1,6 @@
+XAENIAX BOARD
+#M: -
+S: Maintained
+F: board/xaeniax/
+F: include/configs/xaeniax.h
+F: configs/xaeniax_defconfig
diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile
new file mode 100644
index 0000000..e5f116d
--- /dev/null
+++ b/board/xaeniax/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := xaeniax.o flash.o
diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c
new file mode 100644
index 0000000..6ad6216
--- /dev/null
+++ b/board/xaeniax/flash.c
@@ -0,0 +1,412 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH ushort
+#define FLASH_PORT_WIDTHV vu_short
+#define SWAP(x) __swab16(x)
+#else
+#define FLASH_PORT_WIDTH ulong
+#define FLASH_PORT_WIDTHV vu_long
+#define SWAP(x) __swab32(x)
+#endif
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ int i;
+ ulong size = 0;
+
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+ switch (i) {
+ case 0:
+ flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+ flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+ break;
+ case 1:
+ flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+ flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+ break;
+ default:
+ panic ("configured too many flash banks!\n");
+ break;
+ }
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors
+ */
+ flash_protect ( FLAG_PROTECT_SET,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
+ &flash_info[0] );
+
+ flash_protect ( FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+ info->protect[i] = 0;
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ printf ("INTEL ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F128J3A:
+ printf ("28F128J3A\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+ return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+ volatile FPW value;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x5555] = (FPW) 0x00AA00AA;
+ addr[0x2AAA] = (FPW) 0x00550055;
+ addr[0x5555] = (FPW) 0x00900090;
+
+ mb ();
+ value = addr[0];
+
+ switch (value) {
+
+ case (FPW) INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ mb ();
+ value = addr[1]; /* device ID */
+
+ switch (value) {
+
+ case (FPW) INTEL_ID_28F128J3A:
+ info->flash_id += FLASH_28F128J3A;
+ info->sector_count = 128;
+ info->size = 0x02000000;
+ break; /* => 16 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ break;
+ }
+
+ if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ }
+
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int prot, sect;
+ ulong type, start;
+ int rcode = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ type = (info->flash_id & FLASH_VENDMASK);
+ if ((type != FLASH_MAN_INTEL)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ disable_interrupts();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ FPWV *addr = (FPWV *) (info->start[sect]);
+ FPW status;
+
+ printf ("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ *addr = (FPW) 0x00500050; /* clear status register */
+ *addr = (FPW) 0x00200020; /* erase setup */
+ *addr = (FPW) 0x00D000D0; /* erase confirm */
+
+ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = (FPW) 0x00B000B0; /* suspend erase */
+ *addr = (FPW) 0x00FF00FF; /* reset to read mode */
+ rcode = 1;
+ break;
+ }
+ }
+
+ *addr = 0x00500050; /* clear status register cmd. */
+ *addr = 0x00FF00FF; /* resest to read mode */
+
+ printf (" done\n");
+ }
+ }
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ FPW data;
+ int count, i, l, rc, port_width;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return 4;
+ }
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+ wp = (addr & ~1);
+ port_width = 2;
+#else
+ wp = (addr & ~3);
+ port_width = 4;
+#endif
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < port_width && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ count = 0;
+ while (cnt >= port_width) {
+ data = 0;
+ for (i = 0; i < port_width; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ cnt -= port_width;
+ if (count++ > 0x800) {
+ spin_wheel ();
+ count = 0;
+ }
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+ FPWV *addr = (FPWV *) dest;
+ ulong status;
+ ulong start;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ disable_interrupts();
+
+ *addr = (FPW) 0x00400040; /* write setup */
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ start = get_timer(0);
+
+ /* wait while polling the status register */
+ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+ *addr = (FPW) 0x00FF00FF; /* restore read mode */
+ return (1);
+ }
+ }
+
+ *addr = (FPW) 0x00FF00FF; /* restore read mode */
+
+ return (0);
+}
+
+void inline spin_wheel (void)
+{
+ static int p = 0;
+ static char w[] = "\\/-";
+
+ printf ("\010%c", w[p]);
+ (++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c
new file mode 100644
index 0000000..995c262
--- /dev/null
+++ b/board/xaeniax/xaeniax.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2004
+ * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/pxa.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* arch number of xaeniax */
+ gd->bd->bi_arch_number = 585;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ return 0;
+}
+
+int dram_init(void)
+{
+ pxa2xx_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
new file mode 100644
index 0000000..65d321a
--- /dev/null
+++ b/board/xes/common/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
+obj-$(CONFIG_MPC8572) += fsl_8xxx_clk.o
+obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
+obj-$(CONFIG_P2020) += fsl_8xxx_clk.o
+obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
+obj-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o
+obj-$(CONFIG_NAND_ACTL) += actl_nand.o
diff --git a/board/xes/common/actl_nand.c b/board/xes/common/actl_nand.c
new file mode 100644
index 0000000..bf896fe
--- /dev/null
+++ b/board/xes/common/actl_nand.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This driver support NAND devices which have address lines
+ * connected as ALE and CLE inputs.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+/*
+ * Hardware specific access to control-lines
+ */
+static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+ ulong IO_ADDR_W;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ IO_ADDR_W = (ulong)this->IO_ADDR_W;
+
+ IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
+ CONFIG_SYS_NAND_ACTL_ALE |
+ CONFIG_SYS_NAND_ACTL_NCE);
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
+ if (ctrl & NAND_NCE)
+ IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
+
+ this->IO_ADDR_W = (void *)IO_ADDR_W;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = nand_addr_hwcontrol;
+ nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
+
+ return 0;
+}
diff --git a/board/xes/common/board.c b/board/xes/common/board.c
new file mode 100644
index 0000000..4ed6f50
--- /dev/null
+++ b/board/xes/common/board.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "fsl_8xxx_misc.h"
+
+int checkboard(void)
+{
+ char name[] = CONFIG_SYS_BOARD_NAME;
+ char buf[64];
+ char *s;
+ int i;
+
+#ifdef CONFIG_SYS_FORM_CUSTOM
+ s = "Custom";
+#elif CONFIG_SYS_FORM_6U_CPCI
+ s = "6U CompactPCI";
+#elif CONFIG_SYS_FORM_ATCA_PMC
+ s = "ATCA w/PMC";
+#elif CONFIG_SYS_FORM_ATCA_AMC
+ s = "ATCA w/AMC";
+#elif CONFIG_SYS_FORM_VME
+ s = "VME";
+#elif CONFIG_SYS_FORM_6U_VPX
+ s = "6U VPX";
+#elif CONFIG_SYS_FORM_PMC
+ s = "PMC";
+#elif CONFIG_SYS_FORM_PCI
+ s = "PCI";
+#elif CONFIG_SYS_FORM_3U_CPCI
+ s = "3U CompactPCI";
+#elif CONFIG_SYS_FORM_AMC
+ s = "AdvancedMC";
+#elif CONFIG_SYS_FORM_XMC
+ s = "XMC";
+#elif CONFIG_SYS_FORM_PMC_XMC
+ s = "PMC/XMC";
+#elif CONFIG_SYS_FORM_PCI_EXPRESS
+ s = "PCI Express";
+#elif CONFIG_SYS_FORM_3U_VPX
+ s = "3U VPX";
+#else
+#error "Form factor not defined"
+#endif
+
+ name[strlen(name) - 1] += get_board_derivative();
+ printf("Board: X-ES %s %s SBC\n", name, s);
+
+ /* Display board specific information */
+ puts(" ");
+ i = getenv_f("board_rev", buf, sizeof(buf));
+ if (i > 0)
+ printf("Rev %s, ", buf);
+ i = getenv_f("serial#", buf, sizeof(buf));
+ if (i > 0)
+ printf("Serial# %s, ", buf);
+ i = getenv_f("board_cfg", buf, sizeof(buf));
+ if (i > 0)
+ printf("Cfg %s", buf);
+ puts("\n");
+
+ return 0;
+}
diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c
new file mode 100644
index 0000000..2a604d4
--- /dev/null
+++ b/board/xes/common/fsl_8xxx_clk.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+/*
+ * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
+ */
+unsigned long get_board_sys_clk(ulong dummy)
+{
+#if defined(CONFIG_MPC85xx)
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#elif defined(CONFIG_MPC86xx)
+ immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+#endif
+
+ if (in_be32(&gur->gpporcr) & 0x10000)
+ return 66666666;
+ else
+#ifdef CONFIG_P2020
+ return 100000000;
+#else
+ return 50000000;
+#endif
+}
+
+#ifdef CONFIG_MPC85xx
+/*
+ * Return DDR input clock - synchronous with SYSCLK or 66 MHz
+ * Note: 86xx doesn't support asynchronous DDR clk
+ */
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
+
+ if (ddr_ratio == 0x7)
+ return get_board_sys_clk(dummy);
+
+#ifdef CONFIG_P2020
+ if (in_be32(&gur->gpporcr) & 0x20000)
+ return 66666666;
+ else
+ return 100000000;
+#else
+ return 66666666;
+#endif
+}
+#endif
diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c
new file mode 100644
index 0000000..2899e11
--- /dev/null
+++ b/board/xes/common/fsl_8xxx_misc.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#ifdef CONFIG_PCA953X
+#include <pca953x.h>
+
+/*
+ * Determine if a board's flashes are write protected
+ */
+int board_flash_wp_on(void)
+{
+ if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ CONFIG_SYS_PCA953X_NVM_WP)
+ return 1;
+
+ return 0;
+}
+#endif
+
+/*
+ * Return a board's derivative model number. For example:
+ * return 2 for the XPedite5372 and return 1 for the XPedite5201.
+ */
+uint get_board_derivative(void)
+{
+#if defined(CONFIG_MPC85xx)
+ volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#elif defined(CONFIG_MPC86xx)
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+#endif
+
+ /*
+ * The top 4 lines of the local bus address are pulled low/high and
+ * can be read to determine the least significant digit of a board's
+ * model number.
+ */
+ return gur->gpporcr >> 28;
+}
diff --git a/board/xes/common/fsl_8xxx_misc.h b/board/xes/common/fsl_8xxx_misc.h
new file mode 100644
index 0000000..106bb23
--- /dev/null
+++ b/board/xes/common/fsl_8xxx_misc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_8XXX_MISC_H___
+#define __FSL_8XXX_MISC_H___
+
+uint get_board_derivative(void);
+
+#endif /* __FSL_8XXX_MISC_H__ */
diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
new file mode 100644
index 0000000..510f638
--- /dev/null
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
+
+void pci_init_board(void)
+{
+ int first_free_busno = 0;
+
+#ifdef CONFIG_PCI1
+ int pcie_ep;
+ struct fsl_pci_info pci_info;
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr = in_be32(&gur->devdisr);
+ uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
+ uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
+ uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
+ uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
+ uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info, 1);
+ set_next_law(pci_info.mem_phys,
+ law_size_bits(pci_info.mem_size), pci_info.law);
+ set_next_law(pci_info.io_phys,
+ law_size_bits(pci_info.io_size), pci_info.law);
+
+ pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
+ printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
+ pci_32 ? 32 : 64,
+ pcix ? "PCIX" : "PCI",
+ pci_spd_norm ? ">=" : "<=",
+ pcix ? freq * 2 : freq,
+ pcie_ep ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter");
+
+ first_free_busno = fsl_pci_init_port(&pci_info,
+ &pci1_hose, first_free_busno);
+ } else {
+ printf("PCI1: disabled\n");
+ }
+#elif defined CONFIG_MPC8548
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ /* PCI1 not present on MPC8572 */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
+#endif
+
+ fsl_pcie_init_board(first_free_busno);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_pci_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/xes/xpedite1000/Kconfig b/board/xes/xpedite1000/Kconfig
new file mode 100644
index 0000000..4d0ab2f
--- /dev/null
+++ b/board/xes/xpedite1000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_XPEDITE1000
+
+config SYS_BOARD
+ default "xpedite1000"
+
+config SYS_VENDOR
+ default "xes"
+
+config SYS_CONFIG_NAME
+ default "xpedite1000"
+
+endif
diff --git a/board/xes/xpedite1000/MAINTAINERS b/board/xes/xpedite1000/MAINTAINERS
new file mode 100644
index 0000000..055ce6a
--- /dev/null
+++ b/board/xes/xpedite1000/MAINTAINERS
@@ -0,0 +1,6 @@
+XPEDITE1000 BOARD
+M: Peter Tyser <ptyser@xes-inc.com>
+S: Maintained
+F: board/xes/xpedite1000/
+F: include/configs/xpedite1000.h
+F: configs/xpedite1000_defconfig
diff --git a/board/xes/xpedite1000/Makefile b/board/xes/xpedite1000/Makefile
new file mode 100644
index 0000000..308de91
--- /dev/null
+++ b/board/xes/xpedite1000/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = xpedite1000.o
+extra-y += init.o
diff --git a/board/xes/xpedite1000/README b/board/xes/xpedite1000/README
new file mode 100644
index 0000000..1da8b80
--- /dev/null
+++ b/board/xes/xpedite1000/README
@@ -0,0 +1,82 @@
+ XES XPedite1000 Board
+
+ Last Update: December 29, 2003
+=======================================================================
+
+This file contains some handy info regarding U-Boot and the XES
+XPedite1000 PPC440GX PrPMC board. See the README.ppc440 for additional
+information.
+
+
+SWITCH SETTINGS & JUMPERS
+==========================
+
+Jumpers selected for AMD29LV040B flash part as the boot flash.
+
+
+I2C Strap EEPROM & Environment Settings
+=======================================
+
+The XPedite1000 uses a single I2C eeprom for the 440 strappings and for
+the environment variables. The first page (256 bytes) contains the
+strappings and the 2 EMAC HW Ethernet addresses. Be careful not to
+change the 1st page of the EEPROM! Unpopulated jumper J560 can get you
+out of trouble as it disables the strapping read from EEPROM.
+
+I2C probe
+=====================
+
+The i2c utilities work and have been tested on Rev B. of the 440GX. See
+README.ebony for more information about i2c probing with the 440.
+
+
+GETTING OUT OF I2C TROUBLE
+===========================
+
+(Direct quote from README.ebony)
+If you're like me ... you may have screwed up your bootstrap serial
+eeprom ... or worse, your SPD eeprom when experimenting with the
+i2c commands. If so, here are some ideas on how to get out of
+trouble:
+
+Serial bootstrap eeprom corruption:
+-----------------------------------
+Power down the board and set the following straps:
+
+J560 - closed
+
+This will select the default sys0 and sys1 settings (the serial
+eeproms are not used). Then power up the board and fix the serial
+eeprom using the 'i2c mm' command. Here are the values I currently
+use:
+
+=> i2c md 50 0 10
+
+0000: 85 7d 42 06 07 80 11 00 00 00 00 00 00 00 00 00 .}B.............
+
+Once you have the eeproms set correctly change the
+J560 straps as you desire.
+
+
+PPC440GX Ethernet EMACs
+=======================
+
+The XES XPedite1000 uses emac 2 & 3 and ignores emac 0 & 1. PHYs are connected
+only to emac 2 & 3. The HW Ethernet addresses are read from the i2c eeprom and
+placed in the bd info structure for enet2addr and enet3addr. The ethernet driver
+senses that enetaddr and enet1addr are 0's and does not use them.
+
+As of this writing gigabit ethernet and the TCPIP acceleration hardware is not
+supported.
+
+
+Flash Support
+=============
+
+As of this writing, there is support for the 1/2mb boot flash only. User flash
+is not yet supported.
+
+
+Regards,
+--Travis
+<travis.sawyer@sandburst.com>
diff --git a/board/xes/xpedite1000/config.mk b/board/xes/xpedite1000/config.mk
new file mode 100644
index 0000000..ec7651e
--- /dev/null
+++ b/board/xes/xpedite1000/config.mk
@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2002-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+#
+# XES XPedite1000 PPC440GX
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/xes/xpedite1000/init.S b/board/xes/xpedite1000/init.S
new file mode 100644
index 0000000..9708ecc
--- /dev/null
+++ b/board/xes/xpedite1000/init.S
@@ -0,0 +1,33 @@
+/*
+* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
+#include <config.h>
+#include <asm/ppc4xx.h>
+
+/*
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ * Pointer to the table is returned in r1
+ */
+
+ .section .bootpg,"ax"
+ .globl tlbtab
+
+tlbtab:
+ tlbtab_start
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+ tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
+ tlbtab_end
diff --git a/board/xes/xpedite1000/u-boot.lds.debug b/board/xes/xpedite1000/u-boot.lds.debug
new file mode 100644
index 0000000..04089ae
--- /dev/null
+++ b/board/xes/xpedite1000/u-boot.lds.debug
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
+ board/xes/xpedite1000/init.o (.text)
+ arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
+ arch/powerpc/cpu/ppc4xx/traps.o (.text)
+ arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
+ arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/powerpc/cpu/ppc4xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib/crc32.o (.text)
+ arch/powerpc/lib/extable.o (.text)
+ lib/zlib.o (.text)
+
+/* common/env_embedded.o(.text) */
+
+ *(.text)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.eh_frame)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ }
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ __bss_end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c
new file mode 100644
index 0000000..daab578
--- /dev/null
+++ b/board/xes/xpedite1000/xpedite1000.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ unsigned long sdrreg;
+
+ /*
+ * Enable GPIO for pins 18 - 24
+ * 18 = SEEPROM_WP
+ * 19 = #M_RST
+ * 20 = #MONARCH
+ * 21 = #LED_ALARM
+ * 22 = #LED_ACT
+ * 23 = #LED_STATUS1
+ * 24 = #LED_STATUS2
+ */
+ mfsdr(SDR0_PFC0, sdrreg);
+ mtsdr(SDR0_PFC0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00);
+ out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
+ LED0_OFF();
+ LED1_OFF();
+ LED2_OFF();
+ LED3_OFF();
+
+ /* Setup the external bus controller/chip selects */
+ mtebc(PB0AP, 0x04055200); /* 16MB Strata FLASH */
+ mtebc(PB0CR, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */
+ mtebc(PB1AP, 0x04055200); /* 512KB Socketed AMD FLASH */
+ mtebc(PB1CR, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */
+ mtebc(PB6AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
+ mtebc(PB6CR, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */
+ mtebc(PB7AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
+ mtebc(PB7CR, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */
+
+ /*
+ * Setup the interrupt controller polarities, triggers, etc.
+ *
+ * Because of the interrupt handling rework to handle 440GX interrupts
+ * with the common code, we needed to change names of the UIC registers.
+ * Here the new relationship:
+ *
+ * U-Boot name 440GX name
+ * -----------------------
+ * UIC0 UICB0
+ * UIC1 UIC0
+ * UIC2 UIC1
+ * UIC3 UIC2
+ */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000003); /* SMI & UIC1 crit are critical */
+ mtdcr(UIC1PR, 0xfffffe00); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x01c00000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0xffffc0ff); /* per ref-board manual */
+ mtdcr(UIC2TR, 0x00ff8000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC3SR, 0xffffffff); /* clear all */
+ mtdcr(UIC3ER, 0x00000000); /* disable all */
+ mtdcr(UIC3CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC3TR, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr(UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(UIC3SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC0SR, 0xfc000000); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC0PR, 0xfc000000); /* */
+ mtdcr(UIC0TR, 0x00000000); /* */
+ mtdcr(UIC0VR, 0x00000001); /* */
+
+ LED0_ON();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char buf[64];
+ int i;
+
+ printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME);
+ printf(" ");
+ i = getenv_f("board_rev", buf, sizeof(buf));
+ if (i > 0)
+ printf("Rev %s, ", buf);
+ i = getenv_f("serial#", buf, sizeof(buf));
+ if (i > 0)
+ printf("Serial# %s, ", buf);
+ i = getenv_f("board_cfg", buf, sizeof(buf));
+ if (i > 0)
+ printf("Cfg %s", buf);
+ printf("\n");
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ return spd_sdram();
+}
+
+/*
+ * Override weak pci_pre_init()
+ *
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
+ *
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ */
+#if defined(CONFIG_PCI)
+int pci_pre_init(struct pci_controller * hose)
+{
+ unsigned long strap;
+
+ /* See if we're supposed to setup the pci */
+ mfsdr(SDR0_SDSTP1, strap);
+ if ((strap & 0x00010000) == 0)
+ return 0;
+
+#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
+ /* Setup System Device Register PCIL0_XCR */
+ mfsdr(SDR0_XCR, strap);
+ strap &= 0x0f000000;
+ mtsdr(SDR0_XCR, strap);
+#endif
+
+ return 1;
+}
+#endif /* defined(CONFIG_PCI) */
+
+#if defined(CONFIG_PCI)
+/*
+ * Override weak is_pci_host()
+ *
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
+ *
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
+ *
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
+int is_pci_host(struct pci_controller *hose)
+{
+ return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ return ctrlc();
+}
+#endif
diff --git a/board/xes/xpedite517x/Kconfig b/board/xes/xpedite517x/Kconfig
new file mode 100644
index 0000000..91bbd22
--- /dev/null
+++ b/board/xes/xpedite517x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_XPEDITE517X
+
+config SYS_BOARD
+ default "xpedite517x"
+
+config SYS_VENDOR
+ default "xes"
+
+config SYS_CONFIG_NAME
+ default "xpedite517x"
+
+endif
diff --git a/board/xes/xpedite517x/MAINTAINERS b/board/xes/xpedite517x/MAINTAINERS
new file mode 100644
index 0000000..26e0acc
--- /dev/null
+++ b/board/xes/xpedite517x/MAINTAINERS
@@ -0,0 +1,6 @@
+XPEDITE517X BOARD
+M: Peter Tyser <ptyser@xes-inc.com>
+S: Maintained
+F: board/xes/xpedite517x/
+F: include/configs/xpedite517x.h
+F: configs/xpedite517x_defconfig
diff --git a/board/xes/xpedite517x/Makefile b/board/xes/xpedite517x/Makefile
new file mode 100644
index 0000000..d88c3d4
--- /dev/null
+++ b/board/xes/xpedite517x/Makefile
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += xpedite517x.o
+obj-y += ddr.o
+obj-y += law.o
diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c
new file mode 100644
index 0000000..fd602ea
--- /dev/null
+++ b/board/xes/xpedite517x/ddr.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
+{
+ i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+ sizeof(ddr2_spd_eeprom_t));
+}
+
+/*
+ * There are four board-specific SDRAM timing parameters which must be
+ * calculated based on the particular PCB artwork. These are:
+ * 1.) CPO (Read Capture Delay)
+ * - TIMING_CFG_2 register
+ * Source: Calculation based on board trace lengths and
+ * chip-specific internal delays.
+ * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
+ * - TIMING_CFG_2 register
+ * Source: Calculation based on board trace lengths.
+ * Unless clock and DQ lanes are very different
+ * lengths (>2"), this should be set to the nominal value
+ * of 1/2 clock delay.
+ * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ * - DDR_SDRAM_CLK_CNTL register
+ * Source: Signal Integrity Simulations
+ * 4.) 2T Timing on Addr/Ctl
+ * - TIMING_CFG_2 register
+ * Source: Signal Integrity Simulations
+ * Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ * PCB routing on the XPedite5170 is nearly identical to the XPedite5370
+ * so we use the XPedite5370 settings as a basis for the XPedite5170.
+ */
+
+typedef struct board_memctl_options {
+ uint16_t datarate_mhz_low;
+ uint16_t datarate_mhz_high;
+ uint8_t clk_adjust;
+ uint8_t cpo_override;
+ uint8_t write_data_delay;
+} board_memctl_options_t;
+
+static struct board_memctl_options bopts_ctrl[][2] = {
+ {
+ /* Controller 0 */
+ {
+ /* DDR2 600/667 */
+ .datarate_mhz_low = 500,
+ .datarate_mhz_high = 750,
+ .clk_adjust = 5,
+ .cpo_override = 8,
+ .write_data_delay = 2,
+ },
+ {
+ /* DDR2 800 */
+ .datarate_mhz_low = 750,
+ .datarate_mhz_high = 850,
+ .clk_adjust = 5,
+ .cpo_override = 9,
+ .write_data_delay = 2,
+ },
+ },
+ {
+ /* Controller 1 */
+ {
+ /* DDR2 600/667 */
+ .datarate_mhz_low = 500,
+ .datarate_mhz_high = 750,
+ .clk_adjust = 5,
+ .cpo_override = 7,
+ .write_data_delay = 2,
+ },
+ {
+ /* DDR2 800 */
+ .datarate_mhz_low = 750,
+ .datarate_mhz_high = 850,
+ .clk_adjust = 5,
+ .cpo_override = 8,
+ .write_data_delay = 2,
+ },
+ },
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
+ sys_info_t sysinfo;
+ int i;
+ unsigned int datarate;
+
+ get_sys_info(&sysinfo);
+ datarate = get_ddr_freq(0) / 1000000;
+
+ for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
+ if ((bopts[i].datarate_mhz_low <= datarate) &&
+ (bopts[i].datarate_mhz_high >= datarate)) {
+ debug("controller %d:\n", ctrl_num);
+ debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
+ debug(" cpo = %d\n", bopts[i].cpo_override);
+ debug(" write_data_delay = %d\n",
+ bopts[i].write_data_delay);
+ popts->clk_adjust = bopts[i].clk_adjust;
+ popts->cpo_override = bopts[i].cpo_override;
+ popts->write_data_delay = bopts[i].write_data_delay;
+ }
+ }
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/xes/xpedite517x/law.c b/board/xes/xpedite517x/law.c
new file mode 100644
index 0000000..2aad5d2
--- /dev/null
+++ b/board/xes/xpedite517x/law.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ * CCSRBAR don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE
+ /* NAND LAW covers 2 NAND flashes */
+ SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c
new file mode 100644
index 0000000..0028870
--- /dev/null
+++ b/board/xes/xpedite517x/xpedite517x.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <fsl_ddr_sdram.h>
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+#include "../common/fsl_8xxx_misc.h"
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+#endif
+
+/*
+ * Print out which flash was booted from and if booting from the 2nd flash,
+ * swap flash chip selects to maintain consistent flash numbering/addresses.
+ */
+static void flash_cs_fixup(void)
+{
+ int flash_sel;
+
+ /*
+ * Print boot dev and swap flash flash chip selects if booted from 2nd
+ * flash. Swapping chip selects presents user with a common memory
+ * map regardless of which flash was booted from.
+ */
+ flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+ printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+ if (flash_sel) {
+ set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+ set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+ set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+ }
+}
+
+int board_early_init_r(void)
+{
+ /* Initialize PCA9557 devices */
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+ flash_cs_fixup();
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size = fsl_ddr_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /* Initialize and enable DDR ECC */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ return dram_size;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+ ft_board_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/xes/xpedite520x/Kconfig b/board/xes/xpedite520x/Kconfig
new file mode 100644
index 0000000..9c0c246
--- /dev/null
+++ b/board/xes/xpedite520x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_XPEDITE520X
+
+config SYS_BOARD
+ default "xpedite520x"
+
+config SYS_VENDOR
+ default "xes"
+
+config SYS_CONFIG_NAME
+ default "xpedite520x"
+
+endif
diff --git a/board/xes/xpedite520x/MAINTAINERS b/board/xes/xpedite520x/MAINTAINERS
new file mode 100644
index 0000000..f7bd437
--- /dev/null
+++ b/board/xes/xpedite520x/MAINTAINERS
@@ -0,0 +1,6 @@
+XPEDITE520X BOARD
+M: Peter Tyser <ptyser@xes-inc.com>
+S: Maintained
+F: board/xes/xpedite520x/
+F: include/configs/xpedite520x.h
+F: configs/xpedite520x_defconfig
diff --git a/board/xes/xpedite520x/Makefile b/board/xes/xpedite520x/Makefile
new file mode 100644
index 0000000..14841b9
--- /dev/null
+++ b/board/xes/xpedite520x/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += xpedite520x.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c
new file mode 100644
index 0000000..5c5eadc
--- /dev/null
+++ b/board/xes/xpedite520x/ddr.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+
+ /* We use soldered memory, but use an SPD EEPROM to describe it.
+ * The SPD has an unspecified dimm type, but the DDR2 initialization
+ * code requires a specific type to be specified. This sets the type
+ * as a standard unregistered SO-DIMM. */
+ if (spd->dimm_type == 0) {
+ spd->dimm_type = 0x4;
+ ((uchar *)spd)[63] += 0x4;
+ }
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 9;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/xes/xpedite520x/law.c b/board/xes/xpedite520x/law.c
new file mode 100644
index 0000000..0552407
--- /dev/null
+++ b/board/xes/xpedite520x/law.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite520x/tlb.c b/board/xes/xpedite520x/tlb.c
new file mode 100644
index 0000000..a8e1f48
--- /dev/null
+++ b/board/xes/xpedite520x/tlb.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* W**G* - NOR flashes */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* *I*G* - NAND flash */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if CONFIG_PCI1
+ /* *I*G* - PCI MEM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#if CONFIG_PCI2
+ /* *I*G* - PCI MEM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+ /* *I*G* - PCI IO */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite520x/xpedite520x.c b/board/xes/xpedite520x/xpedite520x.c
new file mode 100644
index 0000000..6a3df52
--- /dev/null
+++ b/board/xes/xpedite520x/xpedite520x.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+static void flash_cs_fixup(void)
+{
+ int flash_sel;
+
+ /*
+ * Print boot dev and swap flash flash chip selects if booted from 2nd
+ * flash. Swapping chip selects presents user with a common memory
+ * map regardless of which flash was booted from.
+ */
+ flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ CONFIG_SYS_PCA953X_FLASH_PASS_CS));
+ printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+ if (flash_sel) {
+ set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+ set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+ set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+ }
+}
+
+int board_early_init_r(void)
+{
+ /* Initialize PCA9557 devices */
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+
+ /*
+ * Remap NOR flash region to caching-inhibited
+ * so that flash can be erased/programmed properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* Invalidate existing TLB entry for NOR flash */
+ disable_tlb(0);
+ set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1);
+
+ flash_cs_fixup();
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+ ft_board_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/xes/xpedite537x/Kconfig b/board/xes/xpedite537x/Kconfig
new file mode 100644
index 0000000..35b3917
--- /dev/null
+++ b/board/xes/xpedite537x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_XPEDITE537X
+
+config SYS_BOARD
+ default "xpedite537x"
+
+config SYS_VENDOR
+ default "xes"
+
+config SYS_CONFIG_NAME
+ default "xpedite537x"
+
+endif
diff --git a/board/xes/xpedite537x/MAINTAINERS b/board/xes/xpedite537x/MAINTAINERS
new file mode 100644
index 0000000..b6123ac
--- /dev/null
+++ b/board/xes/xpedite537x/MAINTAINERS
@@ -0,0 +1,6 @@
+XPEDITE537X BOARD
+M: Peter Tyser <ptyser@xes-inc.com>
+S: Maintained
+F: board/xes/xpedite537x/
+F: include/configs/xpedite537x.h
+F: configs/xpedite537x_defconfig
diff --git a/board/xes/xpedite537x/Makefile b/board/xes/xpedite537x/Makefile
new file mode 100644
index 0000000..2dca0d7
--- /dev/null
+++ b/board/xes/xpedite537x/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += xpedite537x.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c
new file mode 100644
index 0000000..56b5a18
--- /dev/null
+++ b/board/xes/xpedite537x/ddr.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
+{
+ i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+ sizeof(ddr2_spd_eeprom_t));
+}
+
+/*
+ * There are four board-specific SDRAM timing parameters which must be
+ * calculated based on the particular PCB artwork. These are:
+ * 1.) CPO (Read Capture Delay)
+ * - TIMING_CFG_2 register
+ * Source: Calculation based on board trace lengths and
+ * chip-specific internal delays.
+ * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
+ * - TIMING_CFG_2 register
+ * Source: Calculation based on board trace lengths.
+ * Unless clock and DQ lanes are very different
+ * lengths (>2"), this should be set to the nominal value
+ * of 1/2 clock delay.
+ * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ * - DDR_SDRAM_CLK_CNTL register
+ * Source: Signal Integrity Simulations
+ * 4.) 2T Timing on Addr/Ctl
+ * - TIMING_CFG_2 register
+ * Source: Signal Integrity Simulations
+ * Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ * ====== XPedite5370 DDR2-600 read delay calculations ======
+ *
+ * See Freescale's App Note AN2583 as refrence. This document also
+ * contains the chip-specific delays for 8548E, 8572, etc.
+ *
+ * For MPC8572E
+ * Minimum chip delay (Ch 0): 1.372ns
+ * Maximum chip delay (Ch 0): 2.914ns
+ * Minimum chip delay (Ch 1): 1.220ns
+ * Maximum chip delay (Ch 1): 2.595ns
+ *
+ * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
+ *
+ * Minimum delay calc (Ch 0):
+ * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps
+ * = 3808ps
+ * = 3.808ns
+ *
+ * Maximum delay calc (Ch 0):
+ * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
+ * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps
+ * = 6240ps
+ * = 6.240ns
+ *
+ * Minimum delay calc (Ch 1):
+ * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps
+ * = 3288ps
+ * = 3.288ns
+ *
+ * Maximum delay calc (Ch 1):
+ * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
+ * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps
+ * = 5536ps
+ * = 5.536ns
+ *
+ * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
+ * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
+ * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
+ * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
+ *
+ *
+ * ====== XPedite5370 DDR2-800 read delay calculations ======
+ *
+ * See Freescale's App Note AN2583 as refrence. This document also
+ * contains the chip-specific delays for 8548E, 8572, etc.
+ *
+ * For MPC8572E
+ * Minimum chip delay (Ch 0): 1.372ns
+ * Maximum chip delay (Ch 0): 2.914ns
+ * Minimum chip delay (Ch 1): 1.220ns
+ * Maximum chip delay (Ch 1): 2.595ns
+ *
+ * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
+ *
+ * Minimum delay calc (Ch 0):
+ * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps
+ * = 3341ps
+ * = 3.341ns
+ *
+ * Maximum delay calc (Ch 0):
+ * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
+ * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps
+ * = 5673ps
+ * = 5.673ns
+ *
+ * Minimum delay calc (Ch 1):
+ * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps
+ * = 2822ps
+ * = 2.822ns
+ *
+ * Maximum delay calc (Ch 1):
+ * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
+ * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps
+ * = 4968ps
+ * = 4.968ns
+ *
+ * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
+ * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
+ * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
+ * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
+ *
+ * Write latency (WR_DATA_DELAY) is calculated by doing the following:
+ *
+ * The DDR SDRAM specification requires DQS be received no sooner than
+ * 75% of an SDRAM clock period—and no later than 125% of a clock
+ * period—from the capturing clock edge of the command/address at the
+ * SDRAM.
+ *
+ * Based on the above tracelengths, the following are calculated:
+ * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
+ * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
+ * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns
+ * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns
+ *
+ * Difference in arrival time CLK vs. DQS:
+ * Ch. 0 0.072ns
+ * Ch. 1 0.138ns
+ *
+ * Both of these values are much less than 25% of the clock
+ * period at DDR2-600 or DDR2-800, so no additional delay is needed over
+ * the 1/2 cycle which normally aligns the first DQS transition
+ * exactly WL (CAS latency minus one cycle) after the CAS strobe.
+ * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
+ * terminology corresponds to exactly one clock period delay after
+ * the CAS strobe. (due to the fact that the "delay" is referenced
+ * from the *falling* edge of the CLK, just after the rising edge
+ * which the CAS strobe is latched on.
+ */
+
+typedef struct board_memctl_options {
+ uint16_t datarate_mhz_low;
+ uint16_t datarate_mhz_high;
+ uint8_t clk_adjust;
+ uint8_t cpo_override;
+ uint8_t write_data_delay;
+} board_memctl_options_t;
+
+static struct board_memctl_options bopts_ctrl[][2] = {
+ {
+ /* Controller 0 */
+ {
+ /* DDR2 600/667 */
+ .datarate_mhz_low = 500,
+ .datarate_mhz_high = 750,
+ .clk_adjust = 5,
+ .cpo_override = 8,
+ .write_data_delay = 2,
+ },
+ {
+ /* DDR2 800 */
+ .datarate_mhz_low = 750,
+ .datarate_mhz_high = 850,
+ .clk_adjust = 5,
+ .cpo_override = 9,
+ .write_data_delay = 2,
+ },
+ },
+ {
+ /* Controller 1 */
+ {
+ /* DDR2 600/667 */
+ .datarate_mhz_low = 500,
+ .datarate_mhz_high = 750,
+ .clk_adjust = 5,
+ .cpo_override = 7,
+ .write_data_delay = 2,
+ },
+ {
+ /* DDR2 800 */
+ .datarate_mhz_low = 750,
+ .datarate_mhz_high = 850,
+ .clk_adjust = 5,
+ .cpo_override = 8,
+ .write_data_delay = 2,
+ },
+ },
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
+ sys_info_t sysinfo;
+ int i;
+ unsigned int datarate;
+
+ get_sys_info(&sysinfo);
+ datarate = sysinfo.freq_ddrbus / 1000 / 1000;
+
+ for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
+ if ((bopts[i].datarate_mhz_low <= datarate) &&
+ (bopts[i].datarate_mhz_high >= datarate)) {
+ debug("controller %d:\n", ctrl_num);
+ debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
+ debug(" cpo = %d\n", bopts[i].cpo_override);
+ debug(" write_data_delay = %d\n",
+ bopts[i].write_data_delay);
+ popts->clk_adjust = bopts[i].clk_adjust;
+ popts->cpo_override = bopts[i].cpo_override;
+ popts->write_data_delay = bopts[i].write_data_delay;
+ }
+ }
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/xes/xpedite537x/law.c b/board/xes/xpedite537x/law.c
new file mode 100644
index 0000000..092c9ac
--- /dev/null
+++ b/board/xes/xpedite537x/law.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite537x/tlb.c b/board/xes/xpedite537x/tlb.c
new file mode 100644
index 0000000..6d83f85
--- /dev/null
+++ b/board/xes/xpedite537x/tlb.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* W**G* - NOR flashes */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* *I*G* - NAND flash */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1M, 1),
+
+ /* **M** - Boot page for secondary processors */
+ SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+ 0, 3, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_PCIE1
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCIE2
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_PCIE3
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_64M, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite537x/xpedite537x.c b/board/xes/xpedite537x/xpedite537x.c
new file mode 100644
index 0000000..41419fe
--- /dev/null
+++ b/board/xes/xpedite537x/xpedite537x.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+static void flash_cs_fixup(void)
+{
+ int flash_sel;
+
+ /*
+ * Print boot dev and swap flash flash chip selects if booted from 2nd
+ * flash. Swapping chip selects presents user with a common memory
+ * map regardless of which flash was booted from.
+ */
+ flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+ printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+ if (flash_sel) {
+ set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+ set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+ set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+ }
+}
+
+int board_early_init_r(void)
+{
+ /* Initialize PCA9557 devices */
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+ /*
+ * Remap NOR flash region to caching-inhibited
+ * so that flash can be erased/programmed properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* Invalidate existing TLB entry for NOR flash */
+ disable_tlb(0);
+ set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1);
+
+ flash_cs_fixup();
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+ ft_board_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/xes/xpedite550x/Kconfig b/board/xes/xpedite550x/Kconfig
new file mode 100644
index 0000000..1b00137
--- /dev/null
+++ b/board/xes/xpedite550x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_XPEDITE550X
+
+config SYS_BOARD
+ default "xpedite550x"
+
+config SYS_VENDOR
+ default "xes"
+
+config SYS_CONFIG_NAME
+ default "xpedite550x"
+
+endif
diff --git a/board/xes/xpedite550x/MAINTAINERS b/board/xes/xpedite550x/MAINTAINERS
new file mode 100644
index 0000000..017f368
--- /dev/null
+++ b/board/xes/xpedite550x/MAINTAINERS
@@ -0,0 +1,6 @@
+XPEDITE550X BOARD
+M: Peter Tyser <ptyser@xes-inc.com>
+S: Maintained
+F: board/xes/xpedite550x/
+F: include/configs/xpedite550x.h
+F: configs/xpedite550x_defconfig
diff --git a/board/xes/xpedite550x/Makefile b/board/xes/xpedite550x/Makefile
new file mode 100644
index 0000000..1a3fe76
--- /dev/null
+++ b/board/xes/xpedite550x/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright 2007-2008 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += xpedite550x.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
new file mode 100644
index 0000000..0c0605e
--- /dev/null
+++ b/board/xes/xpedite550x/ddr.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
+{
+ i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+ sizeof(ddr3_spd_eeprom_t));
+}
+
+/*
+ * There are traditionally three board-specific SDRAM timing parameters
+ * which must be calculated based on the particular PCB artwork. These are:
+ * 1.) CPO (Read Capture Delay)
+ * - TIMING_CFG_2 register
+ * Source: Calculation based on board trace lengths and
+ * chip-specific internal delays.
+ * 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ * - DDR_SDRAM_CLK_CNTL register
+ * Source: Signal Integrity Simulations
+ * 3.) 2T Timing on Addr/Ctl
+ * - TIMING_CFG_2 register
+ * Source: Signal Integrity Simulations
+ * Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ * ====== XPedite550x DDR3-800 read delay calculations ======
+ *
+ * The P2020 processor provides an autoleveling option. Setting CPO to
+ * 0x1f enables this auto configuration.
+ */
+
+typedef struct {
+ unsigned short datarate_mhz_low;
+ unsigned short datarate_mhz_high;
+ unsigned char clk_adjust;
+ unsigned char cpo;
+} board_specific_parameters_t;
+
+const board_specific_parameters_t board_specific_parameters[][20] = {
+ {
+ /* Controller 0 */
+ {
+ /* DDR3-600/667 */
+ .datarate_mhz_low = 500,
+ .datarate_mhz_high = 750,
+ .clk_adjust = 5,
+ .cpo = 31,
+ },
+ {
+ /* DDR3-800 */
+ .datarate_mhz_low = 750,
+ .datarate_mhz_high = 850,
+ .clk_adjust = 5,
+ .cpo = 31,
+ },
+ },
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const board_specific_parameters_t *pbsp =
+ &(board_specific_parameters[ctrl_num][0]);
+ u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+ sizeof(board_specific_parameters[0][0]);
+ u32 i;
+ ulong ddr_freq;
+
+ /*
+ * Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+ * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+ * there are two dimms in the controller, set odt_rd_cfg to 3 and
+ * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+ */
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i&1) { /* odd CS */
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 0;
+ } else { /* even CS */
+ if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 4;
+ } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+ popts->cs_local_opts[i].odt_rd_cfg = 3;
+ popts->cs_local_opts[i].odt_wr_cfg = 3;
+ }
+ }
+ }
+
+ /*
+ * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+
+ for (i = 0; i < num_params; i++) {
+ if (ddr_freq >= pbsp->datarate_mhz_low &&
+ ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->twot_en = 0;
+ break;
+ }
+ pbsp++;
+ }
+
+ if (i == num_params) {
+ printf("Warning: board specific timing not found "
+ "for data rate %lu MT/s!\n", ddr_freq);
+ }
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+
+ /*
+ * Enable on-die termination.
+ * From the Micron Technical Node TN-41-04, RTT_Nom should typically
+ * be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR
+ * is handled in the Freescale DDR3 driver. Set RTT_Nom here.
+ */
+ popts->rtt_override = 1;
+ popts->rtt_override_value = 3;
+}
diff --git a/board/xes/xpedite550x/law.c b/board/xes/xpedite550x/law.c
new file mode 100644
index 0000000..1a3e91b
--- /dev/null
+++ b/board/xes/xpedite550x/law.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/xes/xpedite550x/tlb.c b/board/xes/xpedite550x/tlb.c
new file mode 100644
index 0000000..0bcb930
--- /dev/null
+++ b/board/xes/xpedite550x/tlb.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* W**G* - NOR flashes */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* *I*G* - NAND flash */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1M, 1),
+
+ /* **M** - Boot page for secondary processors */
+ SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+ 0, 3, BOOKE_PAGESZ_4K, 1),
+
+#ifdef CONFIG_PCIE1
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCIE2
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_PCIE3
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_64M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/xes/xpedite550x/xpedite550x.c b/board/xes/xpedite550x/xpedite550x.c
new file mode 100644
index 0000000..1f05150
--- /dev/null
+++ b/board/xes/xpedite550x/xpedite550x.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+static void flash_cs_fixup(void)
+{
+ int flash_sel;
+
+ /*
+ * Print boot dev and swap flash flash chip selects if booted from 2nd
+ * flash. Swapping chip selects presents user with a common memory
+ * map regardless of which flash was booted from.
+ */
+ flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+ printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
+
+ if (flash_sel) {
+ set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
+
+ set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
+ set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
+ }
+}
+
+int board_early_init_r(void)
+{
+ /* Initialize PCA9557 devices */
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
+
+ /*
+ * Remap NOR flash region to caching-inhibited
+ * so that flash can be erased/programmed properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* Invalidate existing TLB entry for NOR flash */
+ disable_tlb(0);
+ set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1);
+
+ flash_cs_fixup();
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+ ft_board_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig
new file mode 100644
index 0000000..461d7dc
--- /dev/null
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MICROBLAZE_GENERIC
+
+config SYS_BOARD
+ default "microblaze-generic"
+
+config SYS_VENDOR
+ default "xilinx"
+
+config SYS_CONFIG_NAME
+ default "microblaze-generic"
+
+endif
diff --git a/board/xilinx/microblaze-generic/MAINTAINERS b/board/xilinx/microblaze-generic/MAINTAINERS
new file mode 100644
index 0000000..6796d4d
--- /dev/null
+++ b/board/xilinx/microblaze-generic/MAINTAINERS
@@ -0,0 +1,6 @@
+MICROBLAZE-GENERIC BOARD
+M: Michal Simek <monstr@monstr.eu>
+S: Maintained
+F: board/xilinx/microblaze-generic/
+F: include/configs/microblaze-generic.h
+F: configs/microblaze-generic_defconfig
diff --git a/board/xilinx/microblaze-generic/Makefile b/board/xilinx/microblaze-generic/Makefile
new file mode 100644
index 0000000..22c8bef
--- /dev/null
+++ b/board/xilinx/microblaze-generic/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = microblaze-generic.o
diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
new file mode 100644
index 0000000..36bdd96
--- /dev/null
+++ b/board/xilinx/microblaze-generic/config.mk
@@ -0,0 +1,18 @@
+#
+# (C) Copyright 2007 Michal Simek
+#
+# Michal SIMEK <monstr@monstr.eu>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# CAUTION: This file is a faked configuration !!!
+# There is no real target for the microblaze-generic
+# configuration. You have to replace this file with
+# the generated file from your Xilinx design flow.
+#
+
+CONFIG_SYS_TEXT_BASE = 0x29000000
+
+PLATFORM_CPPFLAGS += -mno-xl-soft-mul
+PLATFORM_CPPFLAGS += -mno-xl-soft-div
+PLATFORM_CPPFLAGS += -mxl-barrel-shift
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
new file mode 100644
index 0000000..42a8d0c
--- /dev/null
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* This is a board specific file. It's OK to include board specific
+ * header files */
+
+#include <common.h>
+#include <config.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/microblaze_intc.h>
+#include <asm/asm.h>
+#include <asm/gpio.h>
+
+#ifdef CONFIG_XILINX_GPIO
+static int reset_pin = -1;
+#endif
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_XILINX_GPIO
+ if (reset_pin != -1)
+ gpio_direction_output(reset_pin, 1);
+#endif
+
+#ifdef CONFIG_XILINX_TB_WATCHDOG
+ hw_watchdog_disable();
+#endif
+
+ puts ("Reseting board\n");
+ __asm__ __volatile__ (" mts rmsr, r0;" \
+ "bra r0");
+
+ return 0;
+}
+
+int gpio_init (void)
+{
+#ifdef CONFIG_XILINX_GPIO
+ reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1);
+ if (reset_pin != -1)
+ gpio_request(reset_pin, "reset_pin");
+#endif
+ return 0;
+}
+
+void board_init(void)
+{
+ gpio_init();
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+#ifdef CONFIG_XILINX_AXIEMAC
+ ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
+ XILINX_AXIDMA_BASEADDR);
+#endif
+
+#ifdef CONFIG_XILINX_EMACLITE
+ u32 txpp = 0;
+ u32 rxpp = 0;
+# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+ txpp = 1;
+# endif
+# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+ rxpp = 1;
+# endif
+ ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
+ txpp, rxpp);
+#endif
+
+#ifdef CONFIG_XILINX_LL_TEMAC
+# ifdef XILINX_LLTEMAC_BASEADDR
+# ifdef XILINX_LLTEMAC_FIFO_BASEADDR
+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
+ XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR);
+# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
+# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
+ XILINX_LL_TEMAC_M_SDMA_DCR,
+ XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
+# else
+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
+ XILINX_LL_TEMAC_M_SDMA_PLB,
+ XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
+# endif
+# endif
+# endif
+# ifdef XILINX_LLTEMAC_BASEADDR1
+# ifdef XILINX_LLTEMAC_FIFO_BASEADDR1
+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
+ XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1);
+# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
+# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
+ XILINX_LL_TEMAC_M_SDMA_DCR,
+ XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
+# else
+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
+ XILINX_LL_TEMAC_M_SDMA_PLB,
+ XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
+# endif
+# endif
+# endif
+#endif
+
+ return ret;
+}
diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h
new file mode 100644
index 0000000..d6d0d67
--- /dev/null
+++ b/board/xilinx/microblaze-generic/xparameters.h
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * CAUTION: This file is a faked configuration !!!
+ * There is no real target for the microblaze-generic
+ * configuration. You have to replace this file with
+ * the generated file from your Xilinx design flow.
+ */
+
+#define XILINX_BOARD_NAME microblaze-generic
+
+/* System Clock Frequency */
+#define XILINX_CLOCK_FREQ 100000000
+
+/* Microblaze is microblaze_0 */
+#define XILINX_USE_MSR_INSTR 1
+#define XILINX_FSL_NUMBER 3
+
+/* Interrupt controller is opb_intc_0 */
+#define XILINX_INTC_BASEADDR 0x41200000
+#define XILINX_INTC_NUM_INTR_INPUTS 6
+
+/* Timer pheriphery is opb_timer_1 */
+#define XILINX_TIMER_BASEADDR 0x41c00000
+#define XILINX_TIMER_IRQ 0
+
+/* Uart pheriphery is RS232_Uart */
+#define XILINX_UARTLITE_BASEADDR 0x40600000
+#define XILINX_UARTLITE_BAUDRATE 115200
+
+/* IIC pheriphery is IIC_EEPROM */
+#define XILINX_IIC_0_BASEADDR 0x40800000
+#define XILINX_IIC_0_FREQ 100000
+#define XILINX_IIC_0_BIT 0
+
+/* GPIO is LEDs_4Bit*/
+#define XILINX_GPIO_BASEADDR 0x40000000
+
+/* Flash Memory is FLASH_2Mx32 */
+#define XILINX_FLASH_START 0x2c000000
+#define XILINX_FLASH_SIZE 0x00800000
+
+/* Main Memory is DDR_SDRAM_64Mx32 */
+#define XILINX_RAM_START 0x28000000
+#define XILINX_RAM_SIZE 0x04000000
+
+/* Sysace Controller is SysACE_CompactFlash */
+#define XILINX_SYSACE_BASEADDR 0x41800000
+#define XILINX_SYSACE_HIGHADDR 0x4180ffff
+#define XILINX_SYSACE_MEM_WIDTH 16
+
+/* Ethernet controller is Ethernet_MAC */
+#define XILINX_EMACLITE_BASEADDR 0x40C00000
+
+/* LL_TEMAC Ethernet controller */
+#define XILINX_LLTEMAC_BASEADDR 0x44000000
+#define XILINX_LLTEMAC_SDMA_CTRL_BASEADDR 0x42000180
+#define XILINX_LLTEMAC_BASEADDR1 0x44200000
+#define XILINX_LLTEMAC_FIFO_BASEADDR1 0x42100000
+
+/* Watchdog IP is wxi_timebase_wdt_0 */
+#define XILINX_WATCHDOG_BASEADDR 0x50000000
+#define XILINX_WATCHDOG_IRQ 1
diff --git a/board/xilinx/ml507/Kconfig b/board/xilinx/ml507/Kconfig
new file mode 100644
index 0000000..d580a7b
--- /dev/null
+++ b/board/xilinx/ml507/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ML507
+
+config SYS_BOARD
+ default "ml507"
+
+config SYS_VENDOR
+ default "xilinx"
+
+config SYS_CONFIG_NAME
+ default "ml507"
+
+endif
diff --git a/board/xilinx/ml507/MAINTAINERS b/board/xilinx/ml507/MAINTAINERS
new file mode 100644
index 0000000..8b40f44
--- /dev/null
+++ b/board/xilinx/ml507/MAINTAINERS
@@ -0,0 +1,7 @@
+ML507 BOARD
+M: Ricardo Ribalda <ricardo.ribalda@uam.es>
+S: Maintained
+F: board/xilinx/ml507/
+F: include/configs/ml507.h
+F: configs/ml507_defconfig
+F: configs/ml507_flash_defconfig
diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile
new file mode 100644
index 0000000..9a3809f
--- /dev/null
+++ b/board/xilinx/ml507/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2008
+# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
+# This work has been supported by: Qtechnology http://qtec.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ml507.o
+
+include $(srctree)/board/xilinx/ppc440-generic/Makefile
diff --git a/board/xilinx/ml507/ml507.c b/board/xilinx/ml507/ml507.c
new file mode 100644
index 0000000..83b764b
--- /dev/null
+++ b/board/xilinx/ml507/ml507.c
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+
+int checkboard(void)
+{
+ puts("Xilinx ML507 Board\n");
+ return 0;
+}
diff --git a/board/xilinx/ml507/xparameters.h b/board/xilinx/ml507/xparameters.h
new file mode 100644
index 0000000..e30e592
--- /dev/null
+++ b/board/xilinx/ml507/xparameters.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * based on xparameters-ml507.h by Xilinx
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
+#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
+#define XPAR_INTC_0_BASEADDR 0x81800000
+#define XPAR_UARTLITE_0_BASEADDR 0x84000000
+#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
+#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
+#define XPAR_UARTLITE_0_BAUDRATE 9600
+
+#endif
diff --git a/board/xilinx/ppc405-generic/Kconfig b/board/xilinx/ppc405-generic/Kconfig
new file mode 100644
index 0000000..dfbc07b
--- /dev/null
+++ b/board/xilinx/ppc405-generic/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_XILINX_PPC405_GENERIC
+
+config SYS_BOARD
+ default "ppc405-generic"
+
+config SYS_VENDOR
+ default "xilinx"
+
+config SYS_CONFIG_NAME
+ default "xilinx-ppc405-generic"
+
+endif
diff --git a/board/xilinx/ppc405-generic/MAINTAINERS b/board/xilinx/ppc405-generic/MAINTAINERS
new file mode 100644
index 0000000..2b0c98d
--- /dev/null
+++ b/board/xilinx/ppc405-generic/MAINTAINERS
@@ -0,0 +1,7 @@
+PPC405-GENERIC BOARD
+M: Ricardo Ribalda <ricardo.ribalda@uam.es>
+S: Maintained
+F: board/xilinx/ppc405-generic/
+F: include/configs/xilinx-ppc405-generic.h
+F: configs/xilinx-ppc405-generic_defconfig
+F: configs/xilinx-ppc405-generic_flash_defconfig
diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile
new file mode 100644
index 0000000..c9da870
--- /dev/null
+++ b/board/xilinx/ppc405-generic/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Work supported by Qtechnology http://www.qtec.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o
diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
new file mode 100644
index 0000000..e3dd468
--- /dev/null
+++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+ulong __get_PCI_freq(void)
+{
+ return 0;
+}
+
+ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq")));
+
+int __board_pre_init(void)
+{
+ return 0;
+}
+int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
+
+int __checkboard(void)
+{
+ puts("Xilinx PPC405 Generic Board\n");
+ return 0;
+}
+int checkboard(void) __attribute__((weak, alias("__checkboard")));
+
+phys_size_t __initdram(int board_type)
+{
+ return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
+ CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
+}
+phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
+
+void __get_sys_info(sys_info_t *sysInfo)
+{
+ sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+ sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+ sysInfo->freqPCI = 0;
+
+ return;
+}
+void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h
new file mode 100644
index 0000000..f0ff78f
--- /dev/null
+++ b/board/xilinx/ppc405-generic/xparameters.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * based on xparameters-ml507.h by Xilinx
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
+#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
+#define XPAR_INTC_0_BASEADDR 0x81800000
+#define XPAR_SPI_0_BASEADDR 0x83400000
+#define XPAR_UARTLITE_0_BASEADDR 0x84000000
+#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
+#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
+#define XPAR_UARTLITE_0_BAUDRATE 9600
+#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
+
+#endif
diff --git a/board/xilinx/ppc440-generic/Kconfig b/board/xilinx/ppc440-generic/Kconfig
new file mode 100644
index 0000000..d40783a
--- /dev/null
+++ b/board/xilinx/ppc440-generic/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_XILINX_PPC440_GENERIC
+
+config SYS_BOARD
+ default "ppc440-generic"
+
+config SYS_VENDOR
+ default "xilinx"
+
+config SYS_CONFIG_NAME
+ default "xilinx-ppc440-generic"
+
+endif
diff --git a/board/xilinx/ppc440-generic/MAINTAINERS b/board/xilinx/ppc440-generic/MAINTAINERS
new file mode 100644
index 0000000..2d0b11a
--- /dev/null
+++ b/board/xilinx/ppc440-generic/MAINTAINERS
@@ -0,0 +1,7 @@
+PPC440-GENERIC BOARD
+M: Ricardo Ribalda <ricardo.ribalda@uam.es>
+S: Maintained
+F: board/xilinx/ppc440-generic/
+F: include/configs/xilinx-ppc440-generic.h
+F: configs/xilinx-ppc440-generic_defconfig
+F: configs/xilinx-ppc440-generic_flash_defconfig
diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile
new file mode 100644
index 0000000..0acd95d
--- /dev/null
+++ b/board/xilinx/ppc440-generic/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Work supported by Qtechnology http://www.qtec.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o
+extra-y += ../../xilinx/ppc440-generic/init.o
diff --git a/board/xilinx/ppc440-generic/init.S b/board/xilinx/ppc440-generic/init.S
new file mode 100644
index 0000000..4598a37
--- /dev/null
+++ b/board/xilinx/ppc440-generic/init.S
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+
+.section .bootpg,"ax"
+.globl tlbtab
+
+tlbtab:
+tlbtab_start
+tlbentry(0x00000000, SZ_256M, 0x00000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x10000000, SZ_256M, 0x10000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x20000000, SZ_256M, 0x20000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x30000000, SZ_256M, 0x30000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x40000000, SZ_256M, 0x40000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x50000000, SZ_256M, 0x50000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x60000000, SZ_256M, 0x60000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x70000000, SZ_256M, 0x70000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x80000000, SZ_256M, 0x80000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0x90000000, SZ_256M, 0x90000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xa0000000, SZ_256M, 0xa0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xb0000000, SZ_256M, 0xb0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xc0000000, SZ_256M, 0xc0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xd0000000, SZ_256M, 0xd0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xe0000000, SZ_256M, 0xe0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbentry(0xf0000000, SZ_256M, 0xf0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
+tlbtab_end
diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
new file mode 100644
index 0000000..74df2f4
--- /dev/null
+++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+int __board_pre_init(void)
+{
+ return 0;
+}
+int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
+
+int __checkboard(void)
+{
+ puts("Xilinx PPC440 Generic Board\n");
+ return 0;
+}
+int checkboard(void) __attribute__((weak, alias("__checkboard")));
+
+phys_size_t __initdram(int board_type)
+{
+ return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
+ CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
+}
+phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
+
+void __get_sys_info(sys_info_t *sysInfo)
+{
+ sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+ sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+ sysInfo->freqPCI = 0;
+
+ return;
+}
+void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h
new file mode 100644
index 0000000..e30e592
--- /dev/null
+++ b/board/xilinx/ppc440-generic/xparameters.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * based on xparameters-ml507.h by Xilinx
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
+#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
+#define XPAR_INTC_0_BASEADDR 0x81800000
+#define XPAR_UARTLITE_0_BASEADDR 0x84000000
+#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
+#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
+#define XPAR_UARTLITE_0_BAUDRATE 9600
+
+#endif
diff --git a/board/xilinx/zynq/.gitignore b/board/xilinx/zynq/.gitignore
new file mode 100644
index 0000000..7c36bc9
--- /dev/null
+++ b/board/xilinx/zynq/.gitignore
@@ -0,0 +1,2 @@
+ps7_init.[ch]
+ps7_init_gpl.[ch]
diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS
new file mode 100644
index 0000000..382e921
--- /dev/null
+++ b/board/xilinx/zynq/MAINTAINERS
@@ -0,0 +1,7 @@
+ZYNQ BOARD
+M: Michal Simek <monstr@monstr.eu>
+M: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+S: Maintained
+F: board/xilinx/zynq/
+F: include/configs/zynq*.h
+F: configs/zynq_*_defconfig
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
new file mode 100644
index 0000000..3b1eb4f
--- /dev/null
+++ b/board/xilinx/zynq/Makefile
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
+
+# Please copy ps7_init_gpl.c/h from hw project to this directory
+obj-$(CONFIG_SPL_BUILD) += \
+ $(if $(wildcard $(srctree)/$(src)/ps7_init_gpl.c), ps7_init_gpl.o, \
+ $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o legacy.o))
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
+CFLAGS_REMOVE_ps7_init.o := -Wstrict-prototypes
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
new file mode 100644
index 0000000..258632e
--- /dev/null
+++ b/board/xilinx/zynq/board.c
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <fpga.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <zynqpl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static xilinx_desc fpga;
+
+/* It can be done differently */
+static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
+static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
+#endif
+
+int board_init(void)
+{
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+ u32 idcode;
+
+ idcode = zynq_slcr_get_idcode();
+
+ switch (idcode) {
+ case XILINX_ZYNQ_7010:
+ fpga = fpga010;
+ break;
+ case XILINX_ZYNQ_7015:
+ fpga = fpga015;
+ break;
+ case XILINX_ZYNQ_7020:
+ fpga = fpga020;
+ break;
+ case XILINX_ZYNQ_7030:
+ fpga = fpga030;
+ break;
+ case XILINX_ZYNQ_7045:
+ fpga = fpga045;
+ break;
+ case XILINX_ZYNQ_7100:
+ fpga = fpga100;
+ break;
+ }
+#endif
+
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+ fpga_init();
+ fpga_add(fpga_xilinx, &fpga);
+#endif
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+ case ZYNQ_BM_NOR:
+ setenv("modeboot", "norboot");
+ break;
+ case ZYNQ_BM_SD:
+ setenv("modeboot", "sdboot");
+ break;
+ case ZYNQ_BM_JTAG:
+ setenv("modeboot", "jtagboot");
+ break;
+ default:
+ setenv("modeboot", "");
+ break;
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ u32 ret = 0;
+
+#ifdef CONFIG_XILINX_AXIEMAC
+ ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
+ XILINX_AXIDMA_BASEADDR);
+#endif
+#ifdef CONFIG_XILINX_EMACLITE
+ u32 txpp = 0;
+ u32 rxpp = 0;
+# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+ txpp = 1;
+# endif
+# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+ rxpp = 1;
+# endif
+ ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
+ txpp, rxpp);
+#endif
+
+#if defined(CONFIG_ZYNQ_GEM)
+# if defined(CONFIG_ZYNQ_GEM0)
+ ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
+ CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
+# endif
+# if defined(CONFIG_ZYNQ_GEM1)
+ ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
+ CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
+# endif
+#endif
+ return ret;
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bd)
+{
+ int ret = 0;
+
+#if defined(CONFIG_ZYNQ_SDHCI)
+# if defined(CONFIG_ZYNQ_SDHCI0)
+ ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
+# endif
+# if defined(CONFIG_ZYNQ_SDHCI1)
+ ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
+# endif
+#endif
+ return ret;
+}
+#endif
+
+int dram_init(void)
+{
+#ifdef CONFIG_OF_CONTROL
+ int node;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ const void *blob = gd->fdt_blob;
+
+ node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
+ "memory", 7);
+ if (node == -FDT_ERR_NOTFOUND) {
+ debug("ZYNQ DRAM: Can't get memory node\n");
+ return -1;
+ }
+ addr = fdtdec_get_addr_size(blob, node, "reg", &size);
+ if (addr == FDT_ADDR_T_NONE || size == 0) {
+ debug("ZYNQ DRAM: Can't get base address or size\n");
+ return -1;
+ }
+ gd->ram_size = size;
+#else
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#endif
+ zynq_ddrc_init();
+
+ return 0;
+}
diff --git a/board/xilinx/zynq/legacy.c b/board/xilinx/zynq/legacy.c
new file mode 100644
index 0000000..4ae913e
--- /dev/null
+++ b/board/xilinx/zynq/legacy.c
@@ -0,0 +1,2 @@
+
+#warning usage of ps7_init files is deprecated please use ps7_init_gpl
diff --git a/board/xilinx/zynq/xil_io.h b/board/xilinx/zynq/xil_io.h
new file mode 100644
index 0000000..1eccf8d
--- /dev/null
+++ b/board/xilinx/zynq/xil_io.h
@@ -0,0 +1,13 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H
+
+/*
+ * This empty file is here because ps7_init_gpl.c exported by hw project
+ * has #include "xil_io.h" line.
+ */
+
+#endif /* XIL_IO_H */
diff --git a/board/zeus/Kconfig b/board/zeus/Kconfig
new file mode 100644
index 0000000..6779650
--- /dev/null
+++ b/board/zeus/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_ZEUS
+
+config SYS_BOARD
+ default "zeus"
+
+config SYS_CONFIG_NAME
+ default "zeus"
+
+endif
diff --git a/board/zeus/MAINTAINERS b/board/zeus/MAINTAINERS
new file mode 100644
index 0000000..3118710
--- /dev/null
+++ b/board/zeus/MAINTAINERS
@@ -0,0 +1,6 @@
+ZEUS BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/zeus/
+F: include/configs/zeus.h
+F: configs/zeus_defconfig
diff --git a/board/zeus/Makefile b/board/zeus/Makefile
new file mode 100644
index 0000000..aa3658a
--- /dev/null
+++ b/board/zeus/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y = zeus.o update.o
diff --git a/board/zeus/README b/board/zeus/README
new file mode 100644
index 0000000..1848d8c
--- /dev/null
+++ b/board/zeus/README
@@ -0,0 +1,73 @@
+
+Storage of the board specific values (ethaddr...)
+-------------------------------------------------
+
+The board specific environment variables that should be unique
+for each individual board, can be stored in the I2C EEPROM. This
+will be done from offset 0x80 with the length of 0x80 bytes. The
+following command can be used to store the values here:
+
+=> setdef de:20:6a:ed:e2:72 de:20:6a:ed:e2:73 AB0001
+
+ ethaddr eth1addr serial#
+
+Now those 3 values are stored into the I2C EEPROM. A CRC is added
+to make sure that the values get not corrupted.
+
+
+SW-Reset Pushbutton handling:
+-----------------------------
+
+The SW-reset push button is connected to a GPIO input too. This
+way U-Boot can "see" how long the SW-reset was pressed, and a
+specific action can be taken. Two different actions are supported:
+
+a) Release after more than 5 seconds and less then 10 seconds:
+ -> Run POST
+
+ Please note, that the POST test will take a while (approx. 1 min
+ on the 128MByte board). This is mainly due to the system memory
+ test.
+
+b) Release after more than 10 seconds:
+ -> Restore factory default settings
+
+ The factory default values are restored. The default environment
+ variables are restored (ipaddr, serverip...) and the board
+ specific values (ethaddr, eth1addr and serial#) are restored
+ to the environment from the I2C EEPROM. Also a bootline parameter
+ is added to the Linux bootline to signal the Linux kernel upon
+ the next startup, that the factory defaults should be restored.
+
+The command to check this sw-reset status and act accordingly is
+
+=> chkreset
+
+This command is added to the default "bootcmd", so that it is called
+automatically upon startup.
+
+Also, the 2 LED's are used to indicate the current status of this
+command (time passed since pushing the button). When the POST test
+will be run, the green LED will be switched off, and when the
+factory restore will be initiated, the reg LED will be switched off.
+
+
+Loggin of POST results:
+-----------------------
+
+The results of the POST tests are logged in a logbuffer located at the end
+of the onboard memory. It can be accessed with the U-Boot command "log":
+
+=> log show
+<4>POST memory PASSED
+<4>POST cache PASSED
+<4>POST cpu PASSED
+<4>POST uart PASSED
+<4>POST ethernet PASSED
+
+The DENX Linux kernel tree has support for this log buffer included. Exactly
+this buffer is used for logging of all kernel messages too. By enabling the
+compile time option "CONFIG_LOGBUFFER" this support is enabled. This way you
+can access the U-Boot log messages from Linux too.
+
+2007-08-10, Stefan Roese <sr@denx.de>
diff --git a/board/zeus/update.c b/board/zeus/update.c
new file mode 100644
index 0000000..ac738ef
--- /dev/null
+++ b/board/zeus/update.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <i2c.h>
+
+#if defined(CONFIG_ZEUS)
+
+u8 buf_zeus_ce[] = {
+/*00 01 02 03 04 05 06 07 */
+ 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*08 09 0a 0b 0c 0d 0e 0f */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*10 11 12 13 14 15 16 17 */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*18 19 1a 1b 1c 1d 1e 1f */
+ 0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 };
+
+u8 buf_zeus_pe[] = {
+
+/* CPU_CLOCK_DIV 1 = 00
+ CPU_PLB_FREQ_DIV 3 = 10
+ OPB_PLB_FREQ_DIV 2 = 01
+ EBC_PLB_FREQ_DIV 2 = 00
+ MAL_PLB_FREQ_DIV 1 = 00
+ PCI_PLB_FRQ_DIV 3 = 10
+ PLL_PLLOUTA = IS SET
+ PLL_OPERATING = IS NOT SET
+ PLL_FDB_MUL 10 = 1010
+ PLL_FWD_DIV_A 3 = 101
+ PLL_FWD_DIV_B 3 = 101
+ TUNE = 0x2be */
+/*00 01 02 03 04 05 06 07 */
+ 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*08 09 0a 0b 0c 0d 0e 0f */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*10 11 12 13 14 15 16 17 */
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*18 19 1a 1b 1c 1d 1e 1f */
+ 0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 };
+
+static int update_boot_eeprom(void)
+{
+ u32 len = 0x20;
+ u8 chip = CONFIG_SYS_I2C_EEPROM_ADDR;
+ u8 *pbuf;
+ u8 base;
+ int i;
+
+ if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE)) {
+ pbuf = buf_zeus_pe;
+ base = 0x40;
+ } else {
+ pbuf = buf_zeus_ce;
+ base = 0x00;
+ }
+
+ for (i = 0; i < len; i++, base++) {
+ if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) {
+ printf("i2c_write fail\n");
+ return 1;
+ }
+ udelay(11000);
+ }
+
+ return 0;
+}
+
+int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
+{
+ return update_boot_eeprom();
+}
+
+U_BOOT_CMD (
+ update_boot_eeprom, 1, 1, do_update_boot_eeprom,
+ "update boot eeprom content",
+ ""
+);
+
+#endif
diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c
new file mode 100644
index 0000000..e2b12f6
--- /dev/null
+++ b/board/zeus/zeus.c
@@ -0,0 +1,410 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <environment.h>
+#include <logbuff.h>
+#include <post.h>
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define REBOOT_MAGIC 0x07081967
+#define REBOOT_NOP 0x00000000
+#define REBOOT_DO_POST 0x00000001
+
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+ulong flash_get_size(ulong base, int banknum);
+void env_crc_update(void);
+
+static u32 start_time;
+
+int board_early_init_f(void)
+{
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000);
+ mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
+ mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+
+ /*
+ * Configure CPC0_PCI to enable PerWE as output
+ */
+ mtdcr(CPC0_PCI, CPC0_PCI_SPE);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u32 pbcr;
+ int size_val = 0;
+ u32 post_magic;
+ u32 post_val;
+
+ post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC);
+ post_val = in_be32((void *)CONFIG_SYS_POST_VAL);
+ if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) {
+ /*
+ * Set special bootline bootparameter to pass this POST boot
+ * mode to Linux to reset the username/password
+ */
+ setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes");
+
+ /*
+ * Normally don't run POST tests, only when enabled
+ * via the sw-reset button. So disable further tests
+ * upon next bootup here.
+ */
+ out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_NOP);
+ } else {
+ /*
+ * Only run POST when initiated via the sw-reset button mechanism
+ */
+ post_word_store(0);
+ }
+
+ /*
+ * Get current time
+ */
+ start_time = get_timer(0);
+
+ /*
+ * FLASH stuff...
+ */
+
+ /* Re-do sizing to get full correct info */
+
+ /* adjust flash start and offset */
+ mfebc(PB0CR, pbcr);
+ switch (gd->bd->bi_flashsize) {
+ case 1 << 20:
+ size_val = 0;
+ break;
+ case 2 << 20:
+ size_val = 1;
+ break;
+ case 4 << 20:
+ size_val = 2;
+ break;
+ case 8 << 20:
+ size_val = 3;
+ break;
+ case 16 << 20:
+ size_val = 4;
+ break;
+ case 32 << 20:
+ size_val = 5;
+ break;
+ case 64 << 20:
+ size_val = 6;
+ break;
+ case 128 << 20:
+ size_val = 7;
+ break;
+ }
+ pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+ mtebc(PB0CR, pbcr);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size(gd->bd->bi_flashstart, 0);
+
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CONFIG_SYS_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
+
+ /* Env protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
+
+ puts("Board: Zeus-");
+
+ if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE))
+ puts("PE");
+ else
+ puts("CE");
+
+ puts(" of BulletEndPoint");
+
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
+ }
+ putc('\n');
+
+ /* both LED's off */
+ gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0);
+ gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0);
+ udelay(10000);
+ /* and on again */
+ gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 1);
+ gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 1);
+
+ return (0);
+}
+
+static int default_env_var(char *buf, char *var)
+{
+ char *ptr;
+ char *val;
+
+ /*
+ * Find env variable
+ */
+ ptr = strstr(buf + 4, var);
+ if (ptr == NULL) {
+ printf("ERROR: %s not found!\n", var);
+ return -1;
+ }
+ ptr += strlen(var) + 1;
+
+ /*
+ * Now the ethaddr needs to be updated in the "normal"
+ * environment storage -> redundant flash.
+ */
+ val = ptr;
+ setenv(var, val);
+ printf("Updated %s from eeprom to %s!\n", var, val);
+
+ return 0;
+}
+
+static int restore_default(void)
+{
+ char *buf;
+ char *buf_save;
+ u32 crc;
+
+ set_default_env("");
+
+ gd->env_valid = 1;
+
+ /*
+ * Read board specific values from I2C EEPROM
+ * and set env variables accordingly
+ * -> ethaddr, eth1addr, serial#
+ */
+ buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
+ if (buf == NULL) {
+ printf("ERROR: malloc() failed\n");
+ return -1;
+ }
+ if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
+ (u8 *)buf, FACTORY_RESET_ENV_SIZE)) {
+ puts("\nError reading EEPROM!\n");
+ } else {
+ crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4);
+ if (crc != *(u32 *)buf) {
+ printf("ERROR: crc mismatch %08x %08x\n", crc, *(u32 *)buf);
+ return -1;
+ }
+
+ default_env_var(buf, "ethaddr");
+ buf += 8 + 18;
+ default_env_var(buf, "eth1addr");
+ buf += 9 + 18;
+ default_env_var(buf, "serial#");
+ }
+
+ /*
+ * Finally save updated env variables back to flash
+ */
+ saveenv();
+
+ free(buf_save);
+
+ return 0;
+}
+
+int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *buf;
+ char *buf_save;
+ char str[32];
+ u32 crc;
+ char var[32];
+
+ if (argc < 4) {
+ puts("ERROR!\n");
+ return -1;
+ }
+
+ buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
+ memset(buf, 0, FACTORY_RESET_ENV_SIZE);
+
+ strcpy(var, "ethaddr");
+ printf("Setting %s to %s\n", var, argv[1]);
+ sprintf(str, "%s=%s", var, argv[1]);
+ strcpy(buf + 4, str);
+ buf += strlen(str) + 1;
+
+ strcpy(var, "eth1addr");
+ printf("Setting %s to %s\n", var, argv[2]);
+ sprintf(str, "%s=%s", var, argv[2]);
+ strcpy(buf + 4, str);
+ buf += strlen(str) + 1;
+
+ strcpy(var, "serial#");
+ printf("Setting %s to %s\n", var, argv[3]);
+ sprintf(str, "%s=%s", var, argv[3]);
+ strcpy(buf + 4, str);
+
+ crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4);
+ *(u32 *)buf_save = crc;
+
+ if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
+ (u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) {
+ puts("\nError writing EEPROM!\n");
+ return -1;
+ }
+
+ free(buf_save);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ setdef, 4, 1, do_set_default,
+ "write board-specific values to EEPROM (ethaddr...)",
+ "ethaddr eth1addr serial#\n - write board-specific values to EEPROM"
+ );
+
+static inline int sw_reset_pressed(void)
+{
+ return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_SW_RESET));
+}
+
+int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
+{
+ int delta;
+ int count = 0;
+ int post = 0;
+ int factory_reset = 0;
+
+ if (!sw_reset_pressed()) {
+ printf("SW-Reset already high (Button released)\n");
+ printf("-> No action taken!\n");
+ return 0;
+ }
+
+ printf("Waiting for SW-Reset button to be released.");
+
+ while (1) {
+ delta = get_timer(start_time);
+ if (!sw_reset_pressed())
+ break;
+
+ if ((delta > CONFIG_SYS_TIME_POST) && !post) {
+ printf("\nWhen released now, POST tests will be started.");
+ gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0);
+ post = 1;
+ }
+
+ if ((delta > CONFIG_SYS_TIME_FACTORY_RESET) && !factory_reset) {
+ printf("\nWhen released now, factory default values"
+ " will be restored.");
+ gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0);
+ factory_reset = 1;
+ }
+
+ udelay(1000);
+ if (!(count++ % 1000))
+ printf(".");
+ }
+
+
+ printf("\nSW-Reset Button released after %d milli-seconds!\n", delta);
+
+ if (delta > CONFIG_SYS_TIME_FACTORY_RESET) {
+ printf("Starting factory reset value restoration...\n");
+
+ /*
+ * Restore default setting
+ */
+ restore_default();
+
+ /*
+ * Reset the board for default to become valid
+ */
+ do_reset(NULL, 0, 0, NULL);
+
+ return 0;
+ }
+
+ if (delta > CONFIG_SYS_TIME_POST) {
+ printf("Starting POST configuration...\n");
+
+ /*
+ * Enable POST upon next bootup
+ */
+ out_be32((void *)CONFIG_SYS_POST_MAGIC, REBOOT_MAGIC);
+ out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_DO_POST);
+ post_bootmode_init();
+
+ /*
+ * Reset the logbuffer for a clean start
+ */
+ logbuff_reset();
+
+ do_reset(NULL, 0, 0, NULL);
+
+ return 0;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD (
+ chkreset, 1, 1, do_chkreset,
+ "Check for status of SW-reset button and act accordingly",
+ ""
+);
+
+#if defined(CONFIG_POST)
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ u32 post_magic;
+ u32 post_val;
+
+ post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC);
+ post_val = in_be32((void *)CONFIG_SYS_POST_VAL);
+
+ if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST))
+ return 1;
+ else
+ return 0;
+}
+#endif /* CONFIG_POST */
diff --git a/board/zipitz2/Kconfig b/board/zipitz2/Kconfig
new file mode 100644
index 0000000..c663504
--- /dev/null
+++ b/board/zipitz2/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_ZIPITZ2
+
+config SYS_BOARD
+ default "zipitz2"
+
+config SYS_CONFIG_NAME
+ default "zipitz2"
+
+endif
diff --git a/board/zipitz2/MAINTAINERS b/board/zipitz2/MAINTAINERS
new file mode 100644
index 0000000..55b0f64
--- /dev/null
+++ b/board/zipitz2/MAINTAINERS
@@ -0,0 +1,6 @@
+ZIPITZ2 BOARD
+M: Marek Vasut <marek.vasut@gmail.com>
+S: Maintained
+F: board/zipitz2/
+F: include/configs/zipitz2.h
+F: configs/zipitz2_defconfig
diff --git a/board/zipitz2/Makefile b/board/zipitz2/Makefile
new file mode 100644
index 0000000..855f6bc
--- /dev/null
+++ b/board/zipitz2/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2009
+# Marek Vasut <marek.vasut@gmail.com>
+#
+# Heavily based on pxa255_idp platform
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := zipitz2.o
diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
new file mode 100644
index 0000000..90bba6a
--- /dev/null
+++ b/board/zipitz2/zipitz2.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2009
+ * Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Heavily based on pxa255_idp platform
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/pxa.h>
+#include <asm/arch/regs-mmc.h>
+#include <spi.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_SPI
+void lcd_start(void);
+#else
+inline void lcd_start(void) {};
+#endif
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* arch number of Z2 */
+ gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Enable LCD */
+ lcd_start();
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ pxa2xx_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_SPI
+
+struct {
+ unsigned char reg;
+ unsigned short data;
+ unsigned char mdelay;
+} lcd_data[] = {
+ { 0x07, 0x0000, 0 },
+ { 0x13, 0x0000, 10 },
+ { 0x11, 0x3004, 0 },
+ { 0x14, 0x200F, 0 },
+ { 0x10, 0x1a20, 0 },
+ { 0x13, 0x0040, 50 },
+ { 0x13, 0x0060, 0 },
+ { 0x13, 0x0070, 200 },
+ { 0x01, 0x0127, 0 },
+ { 0x02, 0x0700, 0 },
+ { 0x03, 0x1030, 0 },
+ { 0x08, 0x0208, 0 },
+ { 0x0B, 0x0620, 0 },
+ { 0x0C, 0x0110, 0 },
+ { 0x30, 0x0120, 0 },
+ { 0x31, 0x0127, 0 },
+ { 0x32, 0x0000, 0 },
+ { 0x33, 0x0503, 0 },
+ { 0x34, 0x0727, 0 },
+ { 0x35, 0x0124, 0 },
+ { 0x36, 0x0706, 0 },
+ { 0x37, 0x0701, 0 },
+ { 0x38, 0x0F00, 0 },
+ { 0x39, 0x0F00, 0 },
+ { 0x40, 0x0000, 0 },
+ { 0x41, 0x0000, 0 },
+ { 0x42, 0x013f, 0 },
+ { 0x43, 0x0000, 0 },
+ { 0x44, 0x013f, 0 },
+ { 0x45, 0x0000, 0 },
+ { 0x46, 0xef00, 0 },
+ { 0x47, 0x013f, 0 },
+ { 0x48, 0x0000, 0 },
+ { 0x07, 0x0015, 30 },
+ { 0x07, 0x0017, 0 },
+ { 0x20, 0x0000, 0 },
+ { 0x21, 0x0000, 0 },
+ { 0x22, 0x0000, 0 },
+};
+
+void zipitz2_spi_sda(int set)
+{
+ /* GPIO 13 */
+ if (set)
+ writel((1 << 13), GPSR0);
+ else
+ writel((1 << 13), GPCR0);
+}
+
+void zipitz2_spi_scl(int set)
+{
+ /* GPIO 22 */
+ if (set)
+ writel((1 << 22), GPCR0);
+ else
+ writel((1 << 22), GPSR0);
+}
+
+unsigned char zipitz2_spi_read(void)
+{
+ /* GPIO 40 */
+ return !!(readl(GPLR1) & (1 << 8));
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ /* Always valid */
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ /* GPIO 88 low */
+ writel((1 << 24), GPCR2);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ /* GPIO 88 high */
+ writel((1 << 24), GPSR2);
+
+}
+
+void lcd_start(void)
+{
+ int i;
+ unsigned char reg[3] = { 0x74, 0x00, 0 };
+ unsigned char data[3] = { 0x76, 0, 0 };
+ unsigned char dummy[3] = { 0, 0, 0 };
+
+ /* PWM2 AF */
+ writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
+ /* Enable clock to all PWM */
+ writel(readl(CKEN) | 0x3, CKEN);
+ /* Configure PWM2 */
+ writel(0x4f, PWM_CTRL2);
+ writel(0x2ff, PWM_PWDUTY2);
+ writel(792, PWM_PERVAL2);
+
+ /* Toggle the reset pin to reset the LCD */
+ writel((1 << 19), GPSR0);
+ udelay(100000);
+ writel((1 << 19), GPCR0);
+ udelay(20000);
+ writel((1 << 19), GPSR0);
+ udelay(20000);
+
+ /* Program the LCD init sequence */
+ for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
+ reg[0] = 0x74;
+ reg[1] = 0x0;
+ reg[2] = lcd_data[i].reg;
+ spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+
+ data[0] = 0x76;
+ data[1] = lcd_data[i].data >> 8;
+ data[2] = lcd_data[i].data & 0xff;
+ spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
+
+ if (lcd_data[i].mdelay)
+ udelay(lcd_data[i].mdelay * 1000);
+ }
+
+ writel((1 << 11), GPSR0);
+}
+#endif
